25 #define DEBUG_TYPE "mccodeemitter"
34 : MCII(mcii), Ctx(ctx) {
37 ~SystemZMCCodeEmitter()
override {}
46 uint64_t getBinaryCodeForInstr(
const MCInst &MI,
60 uint64_t getBDAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
63 uint64_t getBDAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
66 uint64_t getBDXAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
69 uint64_t getBDXAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
72 uint64_t getBDLAddr12Len8Encoding(
const MCInst &MI,
unsigned OpNum,
75 uint64_t getBDRAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
78 uint64_t getBDVAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
87 uint64_t getPCRelEncoding(
const MCInst &MI,
unsigned OpNum,
92 uint64_t getPC16DBLEncoding(
const MCInst &MI,
unsigned OpNum,
95 return getPCRelEncoding(MI, OpNum, Fixups,
98 uint64_t getPC32DBLEncoding(
const MCInst &MI,
unsigned OpNum,
101 return getPCRelEncoding(MI, OpNum, Fixups,
104 uint64_t getPC16DBLTLSEncoding(
const MCInst &MI,
unsigned OpNum,
107 return getPCRelEncoding(MI, OpNum, Fixups,
110 uint64_t getPC32DBLTLSEncoding(
const MCInst &MI,
unsigned OpNum,
113 return getPCRelEncoding(MI, OpNum, Fixups,
116 uint64_t getPC12DBLBPPEncoding(
const MCInst &MI,
unsigned OpNum,
119 return getPCRelEncoding(MI, OpNum, Fixups,
122 uint64_t getPC16DBLBPPEncoding(
const MCInst &MI,
unsigned OpNum,
125 return getPCRelEncoding(MI, OpNum, Fixups,
128 uint64_t getPC24DBLBPPEncoding(
const MCInst &MI,
unsigned OpNum,
131 return getPCRelEncoding(MI, OpNum, Fixups,
136 uint64_t computeAvailableFeatures(
const FeatureBitset &FB)
const;
137 void verifyInstructionPredicates(
const MCInst &MI,
138 uint64_t AvailableFeatures)
const;
145 return new SystemZMCCodeEmitter(MCII, Ctx);
148 void SystemZMCCodeEmitter::
152 verifyInstructionPredicates(MI,
155 uint64_t
Bits = getBinaryCodeForInstr(MI, Fixups, STI);
156 unsigned Size = MCII.get(MI.
getOpcode()).getSize();
158 unsigned ShiftValue = (Size * 8) - 8;
159 for (
unsigned I = 0;
I != Size; ++
I) {
160 OS << uint8_t(Bits >> ShiftValue);
165 uint64_t SystemZMCCodeEmitter::
170 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
172 return static_cast<uint64_t>(MO.
getImm());
176 uint64_t SystemZMCCodeEmitter::
177 getBDAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
181 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
182 assert(isUInt<4>(Base) && isUInt<12>(Disp));
183 return (Base << 12) | Disp;
186 uint64_t SystemZMCCodeEmitter::
187 getBDAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
191 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
192 assert(isUInt<4>(Base) && isInt<20>(Disp));
193 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
196 uint64_t SystemZMCCodeEmitter::
197 getBDXAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
201 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
202 uint64_t Index = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI);
203 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
204 return (Index << 16) | (Base << 12) | Disp;
207 uint64_t SystemZMCCodeEmitter::
208 getBDXAddr20Encoding(
const MCInst &MI,
unsigned OpNum,
212 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
213 uint64_t Index = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI);
214 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
215 return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
216 | ((Disp & 0xff000) >> 12);
219 uint64_t SystemZMCCodeEmitter::
220 getBDLAddr12Len8Encoding(
const MCInst &MI,
unsigned OpNum,
224 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
225 uint64_t Len = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI) - 1;
227 return (Len << 16) | (Base << 12) | Disp;
230 uint64_t SystemZMCCodeEmitter::
231 getBDRAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
235 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
236 uint64_t Len = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI);
237 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
238 return (Len << 16) | (Base << 12) | Disp;
241 uint64_t SystemZMCCodeEmitter::
242 getBDVAddr12Encoding(
const MCInst &MI,
unsigned OpNum,
246 uint64_t Disp = getMachineOpValue(MI, MI.
getOperand(OpNum + 1),
Fixups, STI);
247 uint64_t Index = getMachineOpValue(MI, MI.
getOperand(OpNum + 2),
Fixups, STI);
248 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
249 return (Index << 16) | (Base << 12) | Disp;
253 SystemZMCCodeEmitter::getPCRelEncoding(
const MCInst &MI,
unsigned OpNum,
256 bool AllowTLS)
const {
283 #define ENABLE_INSTR_PREDICATE_VERIFIER
284 #include "SystemZGenMCCodeEmitter.inc"
void push_back(const T &Elt)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
constexpr bool isUInt< 8 >(uint64_t x)
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getNumOperands() const
MCSubtargetInfo - Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const