LLVM  4.0.0
WebAssemblyLowerBrUnless.cpp
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1 //===-- WebAssemblyLowerBrUnless.cpp - Lower br_unless --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file lowers br_unless into br_if with an inverted condition.
12 ///
13 /// br_unless is not currently in the spec, but it's very convenient for LLVM
14 /// to use. This pass allows LLVM to use it, for now.
15 ///
16 //===----------------------------------------------------------------------===//
17 
18 #include "WebAssembly.h"
21 #include "WebAssemblySubtarget.h"
24 #include "llvm/Support/Debug.h"
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "wasm-lower-br_unless"
29 
30 namespace {
31 class WebAssemblyLowerBrUnless final : public MachineFunctionPass {
32  StringRef getPassName() const override {
33  return "WebAssembly Lower br_unless";
34  }
35 
36  void getAnalysisUsage(AnalysisUsage &AU) const override {
37  AU.setPreservesCFG();
39  }
40 
41  bool runOnMachineFunction(MachineFunction &MF) override;
42 
43 public:
44  static char ID; // Pass identification, replacement for typeid
45  WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
46 };
47 } // end anonymous namespace
48 
51  return new WebAssemblyLowerBrUnless();
52 }
53 
54 bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) {
55  DEBUG(dbgs() << "********** Lowering br_unless **********\n"
56  "********** Function: "
57  << MF.getName() << '\n');
58 
59  auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
60  const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
61  auto &MRI = MF.getRegInfo();
62 
63  for (auto &MBB : MF) {
64  for (auto MII = MBB.begin(); MII != MBB.end();) {
65  MachineInstr *MI = &*MII++;
66  if (MI->getOpcode() != WebAssembly::BR_UNLESS)
67  continue;
68 
69  unsigned Cond = MI->getOperand(1).getReg();
70  bool Inverted = false;
71 
72  // Attempt to invert the condition in place.
73  if (MFI.isVRegStackified(Cond)) {
74  assert(MRI.hasOneDef(Cond));
75  MachineInstr *Def = MRI.getVRegDef(Cond);
76  switch (Def->getOpcode()) {
77  using namespace WebAssembly;
78  case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
79  case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
80  case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
81  case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break;
82  case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break;
83  case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break;
84  case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break;
85  case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break;
86  case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break;
87  case LE_U_I32: Def->setDesc(TII.get(GT_U_I32)); Inverted = true; break;
88  case EQ_I64: Def->setDesc(TII.get(NE_I64)); Inverted = true; break;
89  case NE_I64: Def->setDesc(TII.get(EQ_I64)); Inverted = true; break;
90  case GT_S_I64: Def->setDesc(TII.get(LE_S_I64)); Inverted = true; break;
91  case GE_S_I64: Def->setDesc(TII.get(LT_S_I64)); Inverted = true; break;
92  case LT_S_I64: Def->setDesc(TII.get(GE_S_I64)); Inverted = true; break;
93  case LE_S_I64: Def->setDesc(TII.get(GT_S_I64)); Inverted = true; break;
94  case GT_U_I64: Def->setDesc(TII.get(LE_U_I64)); Inverted = true; break;
95  case GE_U_I64: Def->setDesc(TII.get(LT_U_I64)); Inverted = true; break;
96  case LT_U_I64: Def->setDesc(TII.get(GE_U_I64)); Inverted = true; break;
97  case LE_U_I64: Def->setDesc(TII.get(GT_U_I64)); Inverted = true; break;
98  case EQ_F32: Def->setDesc(TII.get(NE_F32)); Inverted = true; break;
99  case NE_F32: Def->setDesc(TII.get(EQ_F32)); Inverted = true; break;
100  case EQ_F64: Def->setDesc(TII.get(NE_F64)); Inverted = true; break;
101  case NE_F64: Def->setDesc(TII.get(EQ_F64)); Inverted = true; break;
102  default: break;
103  }
104  }
105 
106  // If we weren't able to invert the condition in place. Insert an
107  // instruction to invert it.
108  if (!Inverted) {
109  unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
110  BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
111  .addReg(Cond);
112  MFI.stackifyVReg(Tmp);
113  Cond = Tmp;
114  Inverted = true;
115  }
116 
117  // The br_unless condition has now been inverted. Insert a br_if and
118  // delete the br_unless.
119  assert(Inverted);
120  BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
121  .addOperand(MI->getOperand(0))
122  .addReg(Cond);
123  MBB.erase(MI);
124  }
125  }
126 
127  return true;
128 }
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end...
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
MachineBasicBlock * MBB
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
This file provides WebAssembly-specific target descriptions.
Represent the analysis usage information of a pass.
FunctionPass * createWebAssemblyLowerBrUnless()
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
This file declares the WebAssembly-specific subclass of TargetSubtarget.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
Representation of each machine instruction.
Definition: MachineInstr.h:52
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This file declares WebAssembly-specific per-machine-function information.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
StringRef getName() const
getName - Return the name of the corresponding LLVM function.