LLVM  4.0.0
ARMBaseRegisterInfo.cpp
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1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMBaseRegisterInfo.h"
15 #include "ARM.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
40 
41 #define DEBUG_TYPE "arm-register-info"
42 
43 #define GET_REGINFO_TARGET_DESC
44 #include "ARMGenRegisterInfo.inc"
45 
46 using namespace llvm;
47 
49  : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
50 
51 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
52  return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
53 }
54 
55 const MCPhysReg*
57  const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
58  bool UseSplitPush = STI.splitFramePushPop(*MF);
59  const MCPhysReg *RegList =
60  STI.isTargetDarwin()
61  ? CSR_iOS_SaveList
62  : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
63 
64  const Function *F = MF->getFunction();
65  if (F->getCallingConv() == CallingConv::GHC) {
66  // GHC set of callee saved regs is empty as all those regs are
67  // used for passing STG regs around
68  return CSR_NoRegs_SaveList;
69  } else if (F->hasFnAttribute("interrupt")) {
70  if (STI.isMClass()) {
71  // M-class CPUs have hardware which saves the registers needed to allow a
72  // function conforming to the AAPCS to function as a handler.
73  return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
74  } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
75  // Fast interrupt mode gives the handler a private copy of R8-R14, so less
76  // need to be saved to restore user-mode state.
77  return CSR_FIQ_SaveList;
78  } else {
79  // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
80  // exception handling.
81  return CSR_GenericInt_SaveList;
82  }
83  }
84 
85  if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
86  F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
87  return CSR_iOS_SwiftError_SaveList;
88 
90  return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
91  ? CSR_iOS_CXX_TLS_PE_SaveList
92  : CSR_iOS_CXX_TLS_SaveList;
93  return RegList;
94 }
95 
97  const MachineFunction *MF) const {
98  assert(MF && "Invalid MachineFunction pointer.");
100  MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
101  return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
102  return nullptr;
103 }
104 
105 const uint32_t *
107  CallingConv::ID CC) const {
108  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
109  if (CC == CallingConv::GHC)
110  // This is academic becase all GHC calls are (supposed to be) tail calls
111  return CSR_NoRegs_RegMask;
112 
113  if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
114  MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
115  return CSR_iOS_SwiftError_RegMask;
116 
117  if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
118  return CSR_iOS_CXX_TLS_RegMask;
119  return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
120 }
121 
122 const uint32_t*
124  return CSR_NoRegs_RegMask;
125 }
126 
127 const uint32_t *
130  "only know about special TLS call on Darwin");
131  return CSR_iOS_TLSCall_RegMask;
132 }
133 
134 const uint32_t *
136  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
137  if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
138  return CSR_NoRegs_RegMask;
139  else
140  return CSR_FPRegs_RegMask;
141 }
142 
143 
144 const uint32_t *
146  CallingConv::ID CC) const {
147  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
148  // This should return a register mask that is the same as that returned by
149  // getCallPreservedMask but that additionally preserves the register used for
150  // the first i32 argument (which must also be the register used to return a
151  // single i32 return value)
152  //
153  // In case that the calling convention does not use the same register for
154  // both or otherwise does not want to enable this optimization, the function
155  // should return NULL
156  if (CC == CallingConv::GHC)
157  // This is academic becase all GHC calls are (supposed to be) tail calls
158  return nullptr;
159  return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
160  : CSR_AAPCS_ThisReturn_RegMask;
161 }
162 
165  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
166  const ARMFrameLowering *TFI = getFrameLowering(MF);
167 
168  // FIXME: avoid re-calculating this every time.
169  BitVector Reserved(getNumRegs());
170  markSuperRegs(Reserved, ARM::SP);
171  markSuperRegs(Reserved, ARM::PC);
172  markSuperRegs(Reserved, ARM::FPSCR);
173  markSuperRegs(Reserved, ARM::APSR_NZCV);
174  if (TFI->hasFP(MF))
175  markSuperRegs(Reserved, getFramePointerReg(STI));
176  if (hasBasePointer(MF))
177  markSuperRegs(Reserved, BasePtr);
178  // Some targets reserve R9.
179  if (STI.isR9Reserved())
180  markSuperRegs(Reserved, ARM::R9);
181  // Reserve D16-D31 if the subtarget doesn't support them.
182  if (!STI.hasVFP3() || STI.hasD16()) {
183  static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
184  for (unsigned R = 0; R < 16; ++R)
185  markSuperRegs(Reserved, ARM::D16 + R);
186  }
187  const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
188  for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
189  for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
190  if (Reserved.test(*SI)) markSuperRegs(Reserved, *I);
191 
192  assert(checkAllSuperRegsMarked(Reserved));
193  return Reserved;
194 }
195 
196 const TargetRegisterClass *
198  const MachineFunction &) const {
199  const TargetRegisterClass *Super = RC;
201  do {
202  switch (Super->getID()) {
203  case ARM::GPRRegClassID:
204  case ARM::SPRRegClassID:
205  case ARM::DPRRegClassID:
206  case ARM::QPRRegClassID:
207  case ARM::QQPRRegClassID:
208  case ARM::QQQQPRRegClassID:
209  case ARM::GPRPairRegClassID:
210  return Super;
211  }
212  Super = *I++;
213  } while (Super);
214  return RC;
215 }
216 
217 const TargetRegisterClass *
219  const {
220  return &ARM::GPRRegClass;
221 }
222 
223 const TargetRegisterClass *
225  if (RC == &ARM::CCRRegClass)
226  return &ARM::rGPRRegClass; // Can't copy CCR registers.
227  return RC;
228 }
229 
230 unsigned
232  MachineFunction &MF) const {
233  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
234  const ARMFrameLowering *TFI = getFrameLowering(MF);
235 
236  switch (RC->getID()) {
237  default:
238  return 0;
239  case ARM::tGPRRegClassID:
240  return TFI->hasFP(MF) ? 4 : 5;
241  case ARM::GPRRegClassID: {
242  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
243  return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
244  }
245  case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
246  case ARM::DPRRegClassID:
247  return 32 - 10;
248  }
249 }
250 
251 // Get the other register in a GPRPair.
252 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
253  for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
254  if (ARM::GPRPairRegClass.contains(*Supers))
255  return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
256  return 0;
257 }
258 
259 // Resolve the RegPairEven / RegPairOdd register allocator hints.
260 void
262  ArrayRef<MCPhysReg> Order,
264  const MachineFunction &MF,
265  const VirtRegMap *VRM,
266  const LiveRegMatrix *Matrix) const {
267  const MachineRegisterInfo &MRI = MF.getRegInfo();
268  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
269 
270  unsigned Odd;
271  switch (Hint.first) {
272  case ARMRI::RegPairEven:
273  Odd = 0;
274  break;
275  case ARMRI::RegPairOdd:
276  Odd = 1;
277  break;
278  default:
279  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
280  return;
281  }
282 
283  // This register should preferably be even (Odd == 0) or odd (Odd == 1).
284  // Check if the other part of the pair has already been assigned, and provide
285  // the paired register as the first hint.
286  unsigned Paired = Hint.second;
287  if (Paired == 0)
288  return;
289 
290  unsigned PairedPhys = 0;
292  PairedPhys = Paired;
293  } else if (VRM && VRM->hasPhys(Paired)) {
294  PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
295  }
296 
297  // First prefer the paired physreg.
298  if (PairedPhys && is_contained(Order, PairedPhys))
299  Hints.push_back(PairedPhys);
300 
301  // Then prefer even or odd registers.
302  for (unsigned I = 0, E = Order.size(); I != E; ++I) {
303  unsigned Reg = Order[I];
304  if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
305  continue;
306  // Don't provide hints that are paired to a reserved register.
307  unsigned Paired = getPairedGPR(Reg, !Odd, this);
308  if (!Paired || MRI.isReserved(Paired))
309  continue;
310  Hints.push_back(Reg);
311  }
312 }
313 
314 void
316  MachineFunction &MF) const {
318  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
319  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
320  Hint.first == (unsigned)ARMRI::RegPairEven) &&
322  // If 'Reg' is one of the even / odd register pair and it's now changed
323  // (e.g. coalesced) into a different register. The other register of the
324  // pair allocation hint must be updated to reflect the relationship
325  // change.
326  unsigned OtherReg = Hint.second;
327  Hint = MRI->getRegAllocationHint(OtherReg);
328  // Make sure the pair has not already divorced.
329  if (Hint.second == Reg) {
330  MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
332  MRI->setRegAllocationHint(NewReg,
333  Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
334  : ARMRI::RegPairOdd, OtherReg);
335  }
336  }
337 }
338 
340  const MachineFrameInfo &MFI = MF.getFrameInfo();
341  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
342  const ARMFrameLowering *TFI = getFrameLowering(MF);
343 
344  // When outgoing call frames are so large that we adjust the stack pointer
345  // around the call, we can no longer use the stack pointer to reach the
346  // emergency spill slot.
347  if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
348  return true;
349 
350  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
351  // negative range for ldr/str (255), and thumb1 is positive offsets only.
352  // It's going to be better to use the SP or Base Pointer instead. When there
353  // are variable sized objects, we can't reference off of the SP, so we
354  // reserve a Base Pointer.
355  if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
356  // Conservatively estimate whether the negative offset from the frame
357  // pointer will be sufficient to reach. If a function has a smallish
358  // frame, it's less likely to have lots of spills and callee saved
359  // space, so it's all more likely to be within range of the frame pointer.
360  // If it's wrong, the scavenger will still enable access to work, it just
361  // won't be optimal.
362  if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
363  return false;
364  return true;
365  }
366 
367  return false;
368 }
369 
371  const MachineRegisterInfo *MRI = &MF.getRegInfo();
372  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
373  const ARMFrameLowering *TFI = getFrameLowering(MF);
374  // We can't realign the stack if:
375  // 1. Dynamic stack realignment is explicitly disabled,
376  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
377  // 3. There are VLAs in the function and the base pointer is disabled.
379  return false;
380  if (AFI->isThumb1OnlyFunction())
381  return false;
382  // Stack realignment requires a frame pointer. If we already started
383  // register allocation with frame pointer elimination, it is too late now.
385  return false;
386  // We may also need a base pointer if there are dynamic allocas or stack
387  // pointer adjustments around calls.
388  if (TFI->hasReservedCallFrame(MF))
389  return true;
390  // A base pointer is required and allowed. Check that it isn't too late to
391  // reserve it.
392  return MRI->canReserveReg(BasePtr);
393 }
394 
397  const MachineFrameInfo &MFI = MF.getFrameInfo();
399  return true;
400  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
401  || needsStackRealignment(MF);
402 }
403 
404 unsigned
406  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
407  const ARMFrameLowering *TFI = getFrameLowering(MF);
408 
409  if (TFI->hasFP(MF))
410  return getFramePointerReg(STI);
411  return ARM::SP;
412 }
413 
414 /// emitLoadConstPool - Emits a load from constpool to materialize the
415 /// specified immediate.
418  const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
419  ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
420  MachineFunction &MF = *MBB.getParent();
421  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
423  const Constant *C =
425  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
426 
427  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
428  .addReg(DestReg, getDefRegState(true), SubIdx)
429  .addConstantPoolIndex(Idx)
430  .addImm(0).addImm(Pred).addReg(PredReg)
431  .setMIFlags(MIFlags);
432 }
433 
436  return true;
437 }
438 
441  return true;
442 }
443 
446  return true;
447 }
448 
451  return true;
452 }
453 
454 int64_t ARMBaseRegisterInfo::
455 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
456  const MCInstrDesc &Desc = MI->getDesc();
457  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
458  int64_t InstrOffs = 0;
459  int Scale = 1;
460  unsigned ImmIdx = 0;
461  switch (AddrMode) {
464  case ARMII::AddrMode_i12:
465  InstrOffs = MI->getOperand(Idx+1).getImm();
466  Scale = 1;
467  break;
468  case ARMII::AddrMode5: {
469  // VFP address mode.
470  const MachineOperand &OffOp = MI->getOperand(Idx+1);
471  InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
472  if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
473  InstrOffs = -InstrOffs;
474  Scale = 4;
475  break;
476  }
477  case ARMII::AddrMode2: {
478  ImmIdx = Idx+2;
479  InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
480  if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
481  InstrOffs = -InstrOffs;
482  break;
483  }
484  case ARMII::AddrMode3: {
485  ImmIdx = Idx+2;
486  InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
487  if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
488  InstrOffs = -InstrOffs;
489  break;
490  }
491  case ARMII::AddrModeT1_s: {
492  ImmIdx = Idx+1;
493  InstrOffs = MI->getOperand(ImmIdx).getImm();
494  Scale = 4;
495  break;
496  }
497  default:
498  llvm_unreachable("Unsupported addressing mode!");
499  }
500 
501  return InstrOffs * Scale;
502 }
503 
504 /// needsFrameBaseReg - Returns true if the instruction's frame index
505 /// reference would be better served by a base register other than FP
506 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
507 /// references it should create new base registers for.
510  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
511  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
512  }
513 
514  // It's the load/store FI references that cause issues, as it can be difficult
515  // to materialize the offset if it won't fit in the literal field. Estimate
516  // based on the size of the local frame and some conservative assumptions
517  // about the rest of the stack frame (note, this is pre-regalloc, so
518  // we don't know everything for certain yet) whether this offset is likely
519  // to be out of range of the immediate. Return true if so.
520 
521  // We only generate virtual base registers for loads and stores, so
522  // return false for everything else.
523  unsigned Opc = MI->getOpcode();
524  switch (Opc) {
525  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
526  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
527  case ARM::t2LDRi12: case ARM::t2LDRi8:
528  case ARM::t2STRi12: case ARM::t2STRi8:
529  case ARM::VLDRS: case ARM::VLDRD:
530  case ARM::VSTRS: case ARM::VSTRD:
531  case ARM::tSTRspi: case ARM::tLDRspi:
532  break;
533  default:
534  return false;
535  }
536 
537  // Without a virtual base register, if the function has variable sized
538  // objects, all fixed-size local references will be via the frame pointer,
539  // Approximate the offset and see if it's legal for the instruction.
540  // Note that the incoming offset is based on the SP value at function entry,
541  // so it'll be negative.
542  MachineFunction &MF = *MI->getParent()->getParent();
543  const ARMFrameLowering *TFI = getFrameLowering(MF);
544  MachineFrameInfo &MFI = MF.getFrameInfo();
546 
547  // Estimate an offset from the frame pointer.
548  // Conservatively assume all callee-saved registers get pushed. R4-R6
549  // will be earlier than the FP, so we ignore those.
550  // R7, LR
551  int64_t FPOffset = Offset - 8;
552  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
553  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
554  FPOffset -= 80;
555  // Estimate an offset from the stack pointer.
556  // The incoming offset is relating to the SP at the start of the function,
557  // but when we access the local it'll be relative to the SP after local
558  // allocation, so adjust our SP-relative offset by that allocation size.
559  Offset += MFI.getLocalFrameSize();
560  // Assume that we'll have at least some spill slots allocated.
561  // FIXME: This is a total SWAG number. We should run some statistics
562  // and pick a real one.
563  Offset += 128; // 128 bytes of spill slots
564 
565  // If there's a frame pointer and the addressing mode allows it, try using it.
566  // The FP is only available if there is no dynamic realignment. We
567  // don't know for sure yet whether we'll need that, so we guess based
568  // on whether there are any local variables that would trigger it.
569  unsigned StackAlign = TFI->getStackAlignment();
570  if (TFI->hasFP(MF) &&
571  !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
572  if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
573  return false;
574  }
575  // If we can reference via the stack pointer, try that.
576  // FIXME: This (and the code that resolves the references) can be improved
577  // to only disallow SP relative references in the live range of
578  // the VLA(s). In practice, it's unclear how much difference that
579  // would make, but it may be worth doing.
580  if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
581  return false;
582 
583  // The offset likely isn't legal, we want to allocate a virtual base register.
584  return true;
585 }
586 
587 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
588 /// be a pointer to FrameIdx at the beginning of the basic block.
591  unsigned BaseReg, int FrameIdx,
592  int64_t Offset) const {
594  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
595  (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
596 
598  DebugLoc DL; // Defaults to "unknown"
599  if (Ins != MBB->end())
600  DL = Ins->getDebugLoc();
601 
602  const MachineFunction &MF = *MBB->getParent();
604  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
605  const MCInstrDesc &MCID = TII.get(ADDriOpc);
606  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
607 
608  MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
609  .addFrameIndex(FrameIdx).addImm(Offset);
610 
611  if (!AFI->isThumb1OnlyFunction())
613 }
614 
616  int64_t Offset) const {
618  MachineFunction &MF = *MBB.getParent();
619  const ARMBaseInstrInfo &TII =
620  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
622  int Off = Offset; // ARM doesn't need the general 64-bit offsets
623  unsigned i = 0;
624 
625  assert(!AFI->isThumb1OnlyFunction() &&
626  "This resolveFrameIndex does not support Thumb1!");
627 
628  while (!MI.getOperand(i).isFI()) {
629  ++i;
630  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
631  }
632  bool Done = false;
633  if (!AFI->isThumbFunction())
634  Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
635  else {
636  assert(AFI->isThumb2Function());
637  Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
638  }
639  assert (Done && "Unable to resolve frame index!");
640  (void)Done;
641 }
642 
644  int64_t Offset) const {
645  const MCInstrDesc &Desc = MI->getDesc();
646  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
647  unsigned i = 0;
648 
649  while (!MI->getOperand(i).isFI()) {
650  ++i;
651  assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
652  }
653 
654  // AddrMode4 and AddrMode6 cannot handle any offset.
655  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
656  return Offset == 0;
657 
658  unsigned NumBits = 0;
659  unsigned Scale = 1;
660  bool isSigned = true;
661  switch (AddrMode) {
664  // i8 supports only negative, and i12 supports only positive, so
665  // based on Offset sign, consider the appropriate instruction
666  Scale = 1;
667  if (Offset < 0) {
668  NumBits = 8;
669  Offset = -Offset;
670  } else {
671  NumBits = 12;
672  }
673  break;
674  case ARMII::AddrMode5:
675  // VFP address mode.
676  NumBits = 8;
677  Scale = 4;
678  break;
679  case ARMII::AddrMode_i12:
680  case ARMII::AddrMode2:
681  NumBits = 12;
682  break;
683  case ARMII::AddrMode3:
684  NumBits = 8;
685  break;
686  case ARMII::AddrModeT1_s:
687  NumBits = (BaseReg == ARM::SP ? 8 : 5);
688  Scale = 4;
689  isSigned = false;
690  break;
691  default:
692  llvm_unreachable("Unsupported addressing mode!");
693  }
694 
695  Offset += getFrameIndexInstrOffset(MI, i);
696  // Make sure the offset is encodable for instructions that scale the
697  // immediate.
698  if ((Offset & (Scale-1)) != 0)
699  return false;
700 
701  if (isSigned && Offset < 0)
702  Offset = -Offset;
703 
704  unsigned Mask = (1 << NumBits) - 1;
705  if ((unsigned)Offset <= Mask * Scale)
706  return true;
707 
708  return false;
709 }
710 
711 void
713  int SPAdj, unsigned FIOperandNum,
714  RegScavenger *RS) const {
715  MachineInstr &MI = *II;
717  MachineFunction &MF = *MBB.getParent();
718  const ARMBaseInstrInfo &TII =
719  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
720  const ARMFrameLowering *TFI = getFrameLowering(MF);
722  assert(!AFI->isThumb1OnlyFunction() &&
723  "This eliminateFrameIndex does not support Thumb1!");
724  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
725  unsigned FrameReg;
726 
727  int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
728 
729  // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
730  // call frame setup/destroy instructions have already been eliminated. That
731  // means the stack pointer cannot be used to access the emergency spill slot
732  // when !hasReservedCallFrame().
733 #ifndef NDEBUG
734  if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
735  assert(TFI->hasReservedCallFrame(MF) &&
736  "Cannot use SP to access the emergency spill slot in "
737  "functions without a reserved call frame");
739  "Cannot use SP to access the emergency spill slot in "
740  "functions with variable sized frame objects");
741  }
742 #endif // NDEBUG
743 
744  assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
745 
746  // Modify MI as necessary to handle as much of 'Offset' as possible
747  bool Done = false;
748  if (!AFI->isThumbFunction())
749  Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
750  else {
751  assert(AFI->isThumb2Function());
752  Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
753  }
754  if (Done)
755  return;
756 
757  // If we get here, the immediate doesn't fit into the instruction. We folded
758  // as much as possible above, handle the rest, providing a register that is
759  // SP+LargeImm.
760  assert((Offset ||
763  "This code isn't needed if offset already handled!");
764 
765  unsigned ScratchReg = 0;
766  int PIdx = MI.findFirstPredOperandIdx();
767  ARMCC::CondCodes Pred = (PIdx == -1)
769  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
770  if (Offset == 0)
771  // Must be addrmode4/6.
772  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
773  else {
774  ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
775  if (!AFI->isThumbFunction())
776  emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
777  Offset, Pred, PredReg, TII);
778  else {
779  assert(AFI->isThumb2Function());
780  emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
781  Offset, Pred, PredReg, TII);
782  }
783  // Update the original instruction to use the scratch register.
784  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
785  }
786 }
787 
789  const TargetRegisterClass *SrcRC,
790  unsigned SubReg,
791  const TargetRegisterClass *DstRC,
792  unsigned DstSubReg,
793  const TargetRegisterClass *NewRC) const {
794  auto MBB = MI->getParent();
795  auto MF = MBB->getParent();
796  const MachineRegisterInfo &MRI = MF->getRegInfo();
797  // If not copying into a sub-register this should be ok because we shouldn't
798  // need to split the reg.
799  if (!DstSubReg)
800  return true;
801  // Small registers don't frequently cause a problem, so we can coalesce them.
802  if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
803  return true;
804 
805  auto NewRCWeight =
807  auto SrcRCWeight =
809  auto DstRCWeight =
811  // If the source register class is more expensive than the destination, the
812  // coalescing is probably profitable.
813  if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
814  return true;
815  if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
816  return true;
817 
818  // If the register allocator isn't constrained, we can always allow coalescing
819  // unfortunately we don't know yet if we will be constrained.
820  // The goal of this heuristic is to restrict how many expensive registers
821  // we allow to coalesce in a given basic block.
822  auto AFI = MF->getInfo<ARMFunctionInfo>();
823  auto It = AFI->getCoalescedWeight(MBB);
824 
825  DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
826  << It->second << "\n");
827  DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
828  << NewRCWeight.RegWeight << "\n");
829 
830  // This number is the largest round number that which meets the criteria:
831  // (1) addresses PR18825
832  // (2) generates better code in some test cases (like vldm-shed-a9.ll)
833  // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
834  // In practice the SizeMultiplier will only factor in for straight line code
835  // that uses a lot of NEON vectors, which isn't terribly common.
836  unsigned SizeMultiplier = MBB->size()/100;
837  SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
838  if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
839  It->second += NewRCWeight.RegWeight;
840  return true;
841  }
842  return false;
843 }
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:92
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
Definition: SmallVector.h:211
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:226
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:588
static unsigned char getAM3Offset(unsigned AM3Opc)
size_t i
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:379
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
A debug info location.
Definition: DebugLoc.h:34
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:234
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isThumb1Only() const
Definition: ARMSubtarget.h:577
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
Live Register Matrix
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
const uint32_t * getNoPreservedMask() const override
bool isR9Reserved() const
Definition: ARMSubtarget.h:584
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
bool useSoftFloat() const
Definition: ARMSubtarget.h:575
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasVFP3() const
Definition: ARMSubtarget.h:446
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
bool isTargetDarwin() const
Definition: ARMSubtarget.h:508
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
unsigned SubReg
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
#define F(x, y, z)
Definition: MD5.cpp:51
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
MachineBasicBlock * MBB
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
int64_t getImm() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool isDebugValue() const
Definition: MachineInstr.h:777
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
unsigned const MachineRegisterInfo * MRI
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:42
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
static unsigned char getAM5Offset(unsigned AM5Opc)
bool isMClass() const
Definition: ARMSubtarget.h:580
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:595
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
uint32_t Offset
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const TargetRegisterClass *const * sc_iterator
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
static unsigned getFramePointerReg(const ARMSubtarget &STI)
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
static AddrOpc getAM2Op(unsigned AM2Opc)
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
#define R6(n)
static unsigned getAM2Offset(unsigned AM2Opc)
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool test(unsigned Idx) const
Definition: BitVector.h:323
bool hasVFP2() const
Definition: ARMSubtarget.h:445
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:558
const MachineInstrBuilder & addFrameIndex(int Idx) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
bool canRealignStack(const MachineFunction &MF) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:176
bool hasBasePointer(const MachineFunction &MF) const
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
static AddrOpc getAM3Op(unsigned AM3Opc)
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:169
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
#define I(x, y, z)
Definition: MD5.cpp:54
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static AddrOpc getAM5Op(unsigned AM5Opc)
const unsigned Kind
unsigned getReg() const
getReg - Returns the register number.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:178
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool cannotEliminateFrame(const MachineFunction &MF) const
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
#define DEBUG(X)
Definition: Debug.h:100
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
IRTranslator LLVM IR MI
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:98
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
bool hasD16() const
Definition: ARMSubtarget.h:503
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
char * PC
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:783