LLVM  4.0.0
LiveIntervalAnalysis.cpp
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1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and computes live intervals for
13 // each virtual and physical register.
14 //
15 //===----------------------------------------------------------------------===//
16 
18 #include "LiveRangeCalc.h"
19 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Value.h"
31 #include "llvm/Support/Debug.h"
37 #include <algorithm>
38 #include <cmath>
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "regalloc"
42 
43 char LiveIntervals::ID = 0;
45 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
46  "Live Interval Analysis", false, false)
51  "Live Interval Analysis", false, false)
52 
53 #ifndef NDEBUG
55  "precompute-phys-liveness", cl::Hidden,
56  cl::desc("Eagerly compute live intervals for all physreg units."));
57 #else
58 static bool EnablePrecomputePhysRegs = false;
59 #endif // NDEBUG
60 
61 namespace llvm {
63  "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
64  cl::desc(
65  "Use segment set for the computation of the live ranges of physregs."));
66 }
67 
69  AU.setPreservesCFG();
79 }
80 
82  DomTree(nullptr), LRCalc(nullptr) {
84 }
85 
87  delete LRCalc;
88 }
89 
91  // Free the live intervals themselves.
92  for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
93  delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
94  VirtRegIntervals.clear();
95  RegMaskSlots.clear();
96  RegMaskBits.clear();
97  RegMaskBlocks.clear();
98 
99  for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
100  delete RegUnitRanges[i];
101  RegUnitRanges.clear();
102 
103  // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
104  VNInfoAllocator.Reset();
105 }
106 
107 /// runOnMachineFunction - calculates LiveIntervals
108 ///
110  MF = &fn;
111  MRI = &MF->getRegInfo();
112  TRI = MF->getSubtarget().getRegisterInfo();
113  TII = MF->getSubtarget().getInstrInfo();
114  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
115  Indexes = &getAnalysis<SlotIndexes>();
116  DomTree = &getAnalysis<MachineDominatorTree>();
117 
118  if (!LRCalc)
119  LRCalc = new LiveRangeCalc();
120 
121  // Allocate space for all virtual registers.
122  VirtRegIntervals.resize(MRI->getNumVirtRegs());
123 
124  computeVirtRegs();
125  computeRegMasks();
126  computeLiveInRegUnits();
127 
129  // For stress testing, precompute live ranges of all physical register
130  // units, including reserved registers.
131  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
132  getRegUnit(i);
133  }
134  DEBUG(dump());
135  return true;
136 }
137 
138 /// print - Implement the dump method.
139 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
140  OS << "********** INTERVALS **********\n";
141 
142  // Dump the regunits.
143  for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
144  if (LiveRange *LR = RegUnitRanges[i])
145  OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
146 
147  // Dump the virtregs.
148  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
150  if (hasInterval(Reg))
151  OS << getInterval(Reg) << '\n';
152  }
153 
154  OS << "RegMasks:";
155  for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
156  OS << ' ' << RegMaskSlots[i];
157  OS << '\n';
158 
159  printInstrs(OS);
160 }
161 
162 void LiveIntervals::printInstrs(raw_ostream &OS) const {
163  OS << "********** MACHINEINSTRS **********\n";
164  MF->print(OS, Indexes);
165 }
166 
167 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
168 void LiveIntervals::dumpInstrs() const {
169  printInstrs(dbgs());
170 }
171 #endif
172 
173 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
174  float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
175  llvm::huge_valf : 0.0F;
176  return new LiveInterval(reg, Weight);
177 }
178 
179 
180 /// computeVirtRegInterval - Compute the live interval of a virtual register,
181 /// based on defs and uses.
182 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
183  assert(LRCalc && "LRCalc not initialized.");
184  assert(LI.empty() && "Should only compute empty intervals.");
185  LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
186  LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg));
187  computeDeadValues(LI, nullptr);
188 }
189 
190 void LiveIntervals::computeVirtRegs() {
191  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
193  if (MRI->reg_nodbg_empty(Reg))
194  continue;
196  }
197 }
198 
199 void LiveIntervals::computeRegMasks() {
200  RegMaskBlocks.resize(MF->getNumBlockIDs());
201 
202  // Find all instructions with regmask operands.
203  for (MachineBasicBlock &MBB : *MF) {
204  std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];
205  RMB.first = RegMaskSlots.size();
206 
207  // Some block starts, such as EH funclets, create masks.
208  if (const uint32_t *Mask = MBB.getBeginClobberMask(TRI)) {
209  RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));
210  RegMaskBits.push_back(Mask);
211  }
212 
213  for (MachineInstr &MI : MBB) {
214  for (const MachineOperand &MO : MI.operands()) {
215  if (!MO.isRegMask())
216  continue;
217  RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
218  RegMaskBits.push_back(MO.getRegMask());
219  }
220  }
221 
222  // Some block ends, such as funclet returns, create masks. Put the mask on
223  // the last instruction of the block, because MBB slot index intervals are
224  // half-open.
225  if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
226  assert(!MBB.empty() && "empty return block?");
227  RegMaskSlots.push_back(
228  Indexes->getInstructionIndex(MBB.back()).getRegSlot());
229  RegMaskBits.push_back(Mask);
230  }
231 
232  // Compute the number of register mask instructions in this block.
233  RMB.second = RegMaskSlots.size() - RMB.first;
234  }
235 }
236 
237 //===----------------------------------------------------------------------===//
238 // Register Unit Liveness
239 //===----------------------------------------------------------------------===//
240 //
241 // Fixed interference typically comes from ABI boundaries: Function arguments
242 // and return values are passed in fixed registers, and so are exception
243 // pointers entering landing pads. Certain instructions require values to be
244 // present in specific registers. That is also represented through fixed
245 // interference.
246 //
247 
248 /// computeRegUnitInterval - Compute the live range of a register unit, based
249 /// on the uses and defs of aliasing registers. The range should be empty,
250 /// or contain only dead phi-defs from ABI blocks.
251 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
252  assert(LRCalc && "LRCalc not initialized.");
253  LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
254 
255  // The physregs aliasing Unit are the roots and their super-registers.
256  // Create all values as dead defs before extending to uses. Note that roots
257  // may share super-registers. That's OK because createDeadDefs() is
258  // idempotent. It is very rare for a register unit to have multiple roots, so
259  // uniquing super-registers is probably not worthwhile.
260  for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
261  for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
262  Supers.isValid(); ++Supers) {
263  if (!MRI->reg_empty(*Supers))
264  LRCalc->createDeadDefs(LR, *Supers);
265  }
266  }
267 
268  // Now extend LR to reach all uses.
269  // Ignore uses of reserved registers. We only track defs of those.
270  for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
271  for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
272  Supers.isValid(); ++Supers) {
273  unsigned Reg = *Supers;
274  if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
275  LRCalc->extendToUses(LR, Reg);
276  }
277  }
278 
279  // Flush the segment set to the segment vector.
281  LR.flushSegmentSet();
282 }
283 
284 
285 /// computeLiveInRegUnits - Precompute the live ranges of any register units
286 /// that are live-in to an ABI block somewhere. Register values can appear
287 /// without a corresponding def when entering the entry block or a landing pad.
288 ///
289 void LiveIntervals::computeLiveInRegUnits() {
290  RegUnitRanges.resize(TRI->getNumRegUnits());
291  DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
292 
293  // Keep track of the live range sets allocated.
294  SmallVector<unsigned, 8> NewRanges;
295 
296  // Check all basic blocks for live-ins.
297  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
298  MFI != MFE; ++MFI) {
299  const MachineBasicBlock *MBB = &*MFI;
300 
301  // We only care about ABI blocks: Entry + landing pads.
302  if ((MFI != MF->begin() && !MBB->isEHPad()) || MBB->livein_empty())
303  continue;
304 
305  // Create phi-defs at Begin for all live-in registers.
306  SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
307  DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
308  for (const auto &LI : MBB->liveins()) {
309  for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
310  unsigned Unit = *Units;
311  LiveRange *LR = RegUnitRanges[Unit];
312  if (!LR) {
313  // Use segment set to speed-up initial computation of the live range.
314  LR = RegUnitRanges[Unit] = new LiveRange(UseSegmentSetForPhysRegs);
315  NewRanges.push_back(Unit);
316  }
317  VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
318  (void)VNI;
319  DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
320  }
321  }
322  DEBUG(dbgs() << '\n');
323  }
324  DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
325 
326  // Compute the 'normal' part of the ranges.
327  for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
328  unsigned Unit = NewRanges[i];
329  computeRegUnitRange(*RegUnitRanges[Unit], Unit);
330  }
331 }
332 
333 
336  for (auto VNI : VNIs) {
337  if (VNI->isUnused())
338  continue;
339  SlotIndex Def = VNI->def;
340  LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
341  }
342 }
343 
345 
346 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
347  ShrinkToUsesWorkList &WorkList,
348  const LiveRange &OldRange) {
349  // Keep track of the PHIs that are in use.
350  SmallPtrSet<VNInfo*, 8> UsedPHIs;
351  // Blocks that have already been added to WorkList as live-out.
353 
354  // Extend intervals to reach all uses in WorkList.
355  while (!WorkList.empty()) {
356  SlotIndex Idx = WorkList.back().first;
357  VNInfo *VNI = WorkList.back().second;
358  WorkList.pop_back();
359  const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
360  SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
361 
362  // Extend the live range for VNI to be live at Idx.
363  if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
364  assert(ExtVNI == VNI && "Unexpected existing value number");
365  (void)ExtVNI;
366  // Is this a PHIDef we haven't seen before?
367  if (!VNI->isPHIDef() || VNI->def != BlockStart ||
368  !UsedPHIs.insert(VNI).second)
369  continue;
370  // The PHI is live, make sure the predecessors are live-out.
371  for (auto &Pred : MBB->predecessors()) {
372  if (!LiveOut.insert(Pred).second)
373  continue;
374  SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
375  // A predecessor is not required to have a live-out value for a PHI.
376  if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
377  WorkList.push_back(std::make_pair(Stop, PVNI));
378  }
379  continue;
380  }
381 
382  // VNI is live-in to MBB.
383  DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
384  LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
385 
386  // Make sure VNI is live-out from the predecessors.
387  for (auto &Pred : MBB->predecessors()) {
388  if (!LiveOut.insert(Pred).second)
389  continue;
390  SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
391  assert(OldRange.getVNInfoBefore(Stop) == VNI &&
392  "Wrong value out of predecessor");
393  WorkList.push_back(std::make_pair(Stop, VNI));
394  }
395  }
396 }
397 
400  DEBUG(dbgs() << "Shrink: " << *li << '\n');
402  && "Can only shrink virtual registers");
403 
404  // Shrink subregister live ranges.
405  bool NeedsCleanup = false;
406  for (LiveInterval::SubRange &S : li->subranges()) {
407  shrinkToUses(S, li->reg);
408  if (S.empty())
409  NeedsCleanup = true;
410  }
411  if (NeedsCleanup)
412  li->removeEmptySubRanges();
413 
414  // Find all the values used, including PHI kills.
415  ShrinkToUsesWorkList WorkList;
416 
417  // Visit all instructions reading li->reg.
419  I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
420  I != E; ) {
421  MachineInstr *UseMI = &*(I++);
422  if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
423  continue;
424  SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
425  LiveQueryResult LRQ = li->Query(Idx);
426  VNInfo *VNI = LRQ.valueIn();
427  if (!VNI) {
428  // This shouldn't happen: readsVirtualRegister returns true, but there is
429  // no live value. It is likely caused by a target getting <undef> flags
430  // wrong.
431  DEBUG(dbgs() << Idx << '\t' << *UseMI
432  << "Warning: Instr claims to read non-existent value in "
433  << *li << '\n');
434  continue;
435  }
436  // Special case: An early-clobber tied operand reads and writes the
437  // register one slot early.
438  if (VNInfo *DefVNI = LRQ.valueDefined())
439  Idx = DefVNI->def;
440 
441  WorkList.push_back(std::make_pair(Idx, VNI));
442  }
443 
444  // Create new live ranges with only minimal live segments per def.
445  LiveRange NewLR;
446  createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
447  extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
448 
449  // Move the trimmed segments back.
450  li->segments.swap(NewLR.segments);
451 
452  // Handle dead values.
453  bool CanSeparate = computeDeadValues(*li, dead);
454  DEBUG(dbgs() << "Shrunk: " << *li << '\n');
455  return CanSeparate;
456 }
457 
458 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
460  bool MayHaveSplitComponents = false;
461  for (auto VNI : LI.valnos) {
462  if (VNI->isUnused())
463  continue;
464  SlotIndex Def = VNI->def;
466  assert(I != LI.end() && "Missing segment for VNI");
467 
468  // Is the register live before? Otherwise we may have to add a read-undef
469  // flag for subregister defs.
470  unsigned VReg = LI.reg;
471  if (MRI->shouldTrackSubRegLiveness(VReg)) {
472  if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
474  MI->setRegisterDefReadUndef(VReg);
475  }
476  }
477 
478  if (I->end != Def.getDeadSlot())
479  continue;
480  if (VNI->isPHIDef()) {
481  // This is a dead PHI. Remove it.
482  VNI->markUnused();
483  LI.removeSegment(I);
484  DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
485  MayHaveSplitComponents = true;
486  } else {
487  // This is a dead def. Make sure the instruction knows.
489  assert(MI && "No instruction defining live value");
490  MI->addRegisterDead(LI.reg, TRI);
491  if (dead && MI->allDefsAreDead()) {
492  DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
493  dead->push_back(MI);
494  }
495  }
496  }
497  return MayHaveSplitComponents;
498 }
499 
501  DEBUG(dbgs() << "Shrink: " << SR << '\n');
503  && "Can only shrink virtual registers");
504  // Find all the values used, including PHI kills.
505  ShrinkToUsesWorkList WorkList;
506 
507  // Visit all instructions reading Reg.
508  SlotIndex LastIdx;
509  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
510  // Skip "undef" uses.
511  if (!MO.readsReg())
512  continue;
513  // Maybe the operand is for a subregister we don't care about.
514  unsigned SubReg = MO.getSubReg();
515  if (SubReg != 0) {
516  LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
517  if ((LaneMask & SR.LaneMask).none())
518  continue;
519  }
520  // We only need to visit each instruction once.
521  MachineInstr *UseMI = MO.getParent();
522  SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
523  if (Idx == LastIdx)
524  continue;
525  LastIdx = Idx;
526 
527  LiveQueryResult LRQ = SR.Query(Idx);
528  VNInfo *VNI = LRQ.valueIn();
529  // For Subranges it is possible that only undef values are left in that
530  // part of the subregister, so there is no real liverange at the use
531  if (!VNI)
532  continue;
533 
534  // Special case: An early-clobber tied operand reads and writes the
535  // register one slot early.
536  if (VNInfo *DefVNI = LRQ.valueDefined())
537  Idx = DefVNI->def;
538 
539  WorkList.push_back(std::make_pair(Idx, VNI));
540  }
541 
542  // Create a new live ranges with only minimal live segments per def.
543  LiveRange NewLR;
545  extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
546 
547  // Move the trimmed ranges back.
548  SR.segments.swap(NewLR.segments);
549 
550  // Remove dead PHI value numbers
551  for (auto VNI : SR.valnos) {
552  if (VNI->isUnused())
553  continue;
554  const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
555  assert(Segment != nullptr && "Missing segment for VNI");
556  if (Segment->end != VNI->def.getDeadSlot())
557  continue;
558  if (VNI->isPHIDef()) {
559  // This is a dead PHI. Remove it.
560  DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
561  VNI->markUnused();
562  SR.removeSegment(*Segment);
563  }
564  }
565 
566  DEBUG(dbgs() << "Shrunk: " << SR << '\n');
567 }
568 
570  ArrayRef<SlotIndex> Indices,
571  ArrayRef<SlotIndex> Undefs) {
572  assert(LRCalc && "LRCalc not initialized.");
573  LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
574  for (unsigned i = 0, e = Indices.size(); i != e; ++i)
575  LRCalc->extend(LR, Indices[i], /*PhysReg=*/0, Undefs);
576 }
577 
579  SmallVectorImpl<SlotIndex> *EndPoints) {
580  LiveQueryResult LRQ = LR.Query(Kill);
581  VNInfo *VNI = LRQ.valueOutOrDead();
582  if (!VNI)
583  return;
584 
585  MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
586  SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
587 
588  // If VNI isn't live out from KillMBB, the value is trivially pruned.
589  if (LRQ.endPoint() < MBBEnd) {
590  LR.removeSegment(Kill, LRQ.endPoint());
591  if (EndPoints) EndPoints->push_back(LRQ.endPoint());
592  return;
593  }
594 
595  // VNI is live out of KillMBB.
596  LR.removeSegment(Kill, MBBEnd);
597  if (EndPoints) EndPoints->push_back(MBBEnd);
598 
599  // Find all blocks that are reachable from KillMBB without leaving VNI's live
600  // range. It is possible that KillMBB itself is reachable, so start a DFS
601  // from each successor.
603  VisitedTy Visited;
605  SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
606  SuccI != SuccE; ++SuccI) {
608  I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
609  I != E;) {
610  MachineBasicBlock *MBB = *I;
611 
612  // Check if VNI is live in to MBB.
613  SlotIndex MBBStart, MBBEnd;
614  std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
615  LiveQueryResult LRQ = LR.Query(MBBStart);
616  if (LRQ.valueIn() != VNI) {
617  // This block isn't part of the VNI segment. Prune the search.
618  I.skipChildren();
619  continue;
620  }
621 
622  // Prune the search if VNI is killed in MBB.
623  if (LRQ.endPoint() < MBBEnd) {
624  LR.removeSegment(MBBStart, LRQ.endPoint());
625  if (EndPoints) EndPoints->push_back(LRQ.endPoint());
626  I.skipChildren();
627  continue;
628  }
629 
630  // VNI is live through MBB.
631  LR.removeSegment(MBBStart, MBBEnd);
632  if (EndPoints) EndPoints->push_back(MBBEnd);
633  ++I;
634  }
635  }
636 }
637 
638 //===----------------------------------------------------------------------===//
639 // Register allocator hooks.
640 //
641 
643  // Keep track of regunit ranges.
645  // Keep track of subregister ranges.
646  SmallVector<std::pair<const LiveInterval::SubRange*,
648 
649  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
650  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
651  if (MRI->reg_nodbg_empty(Reg))
652  continue;
653  const LiveInterval &LI = getInterval(Reg);
654  if (LI.empty())
655  continue;
656 
657  // Find the regunit intervals for the assigned register. They may overlap
658  // the virtual register live range, cancelling any kills.
659  RU.clear();
660  for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
661  ++Units) {
662  const LiveRange &RURange = getRegUnit(*Units);
663  if (RURange.empty())
664  continue;
665  RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
666  }
667 
668  if (MRI->subRegLivenessEnabled()) {
669  SRs.clear();
670  for (const LiveInterval::SubRange &SR : LI.subranges()) {
671  SRs.push_back(std::make_pair(&SR, SR.find(LI.begin()->end)));
672  }
673  }
674 
675  // Every instruction that kills Reg corresponds to a segment range end
676  // point.
677  for (LiveInterval::const_iterator RI = LI.begin(), RE = LI.end(); RI != RE;
678  ++RI) {
679  // A block index indicates an MBB edge.
680  if (RI->end.isBlock())
681  continue;
682  MachineInstr *MI = getInstructionFromIndex(RI->end);
683  if (!MI)
684  continue;
685 
686  // Check if any of the regunits are live beyond the end of RI. That could
687  // happen when a physreg is defined as a copy of a virtreg:
688  //
689  // %EAX = COPY %vreg5
690  // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
691  // BAR %EAX<kill>
692  //
693  // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
694  for (auto &RUP : RU) {
695  const LiveRange &RURange = *RUP.first;
696  LiveRange::const_iterator &I = RUP.second;
697  if (I == RURange.end())
698  continue;
699  I = RURange.advanceTo(I, RI->end);
700  if (I == RURange.end() || I->start >= RI->end)
701  continue;
702  // I is overlapping RI.
703  goto CancelKill;
704  }
705 
706  if (MRI->subRegLivenessEnabled()) {
707  // When reading a partial undefined value we must not add a kill flag.
708  // The regalloc might have used the undef lane for something else.
709  // Example:
710  // %vreg1 = ... ; R32: %vreg1
711  // %vreg2:high16 = ... ; R64: %vreg2
712  // = read %vreg2<kill> ; R64: %vreg2
713  // = read %vreg1 ; R32: %vreg1
714  // The <kill> flag is correct for %vreg2, but the register allocator may
715  // assign R0L to %vreg1, and R0 to %vreg2 because the low 32bits of R0
716  // are actually never written by %vreg2. After assignment the <kill>
717  // flag at the read instruction is invalid.
718  LaneBitmask DefinedLanesMask;
719  if (!SRs.empty()) {
720  // Compute a mask of lanes that are defined.
721  DefinedLanesMask = LaneBitmask::getNone();
722  for (auto &SRP : SRs) {
723  const LiveInterval::SubRange &SR = *SRP.first;
724  LiveRange::const_iterator &I = SRP.second;
725  if (I == SR.end())
726  continue;
727  I = SR.advanceTo(I, RI->end);
728  if (I == SR.end() || I->start >= RI->end)
729  continue;
730  // I is overlapping RI
731  DefinedLanesMask |= SR.LaneMask;
732  }
733  } else
734  DefinedLanesMask = LaneBitmask::getAll();
735 
736  bool IsFullWrite = false;
737  for (const MachineOperand &MO : MI->operands()) {
738  if (!MO.isReg() || MO.getReg() != Reg)
739  continue;
740  if (MO.isUse()) {
741  // Reading any undefined lanes?
742  LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
743  if ((UseMask & ~DefinedLanesMask).any())
744  goto CancelKill;
745  } else if (MO.getSubReg() == 0) {
746  // Writing to the full register?
747  assert(MO.isDef());
748  IsFullWrite = true;
749  }
750  }
751 
752  // If an instruction writes to a subregister, a new segment starts in
753  // the LiveInterval. But as this is only overriding part of the register
754  // adding kill-flags is not correct here after registers have been
755  // assigned.
756  if (!IsFullWrite) {
757  // Next segment has to be adjacent in the subregister write case.
758  LiveRange::const_iterator N = std::next(RI);
759  if (N != LI.end() && N->start == RI->end)
760  goto CancelKill;
761  }
762  }
763 
764  MI->addRegisterKilled(Reg, nullptr);
765  continue;
766 CancelKill:
767  MI->clearRegisterKills(Reg, nullptr);
768  }
769  }
770 }
771 
774  // A local live range must be fully contained inside the block, meaning it is
775  // defined and killed at instructions, not at block boundaries. It is not
776  // live in or or out of any block.
777  //
778  // It is technically possible to have a PHI-defined live range identical to a
779  // single block, but we are going to return false in that case.
780 
781  SlotIndex Start = LI.beginIndex();
782  if (Start.isBlock())
783  return nullptr;
784 
785  SlotIndex Stop = LI.endIndex();
786  if (Stop.isBlock())
787  return nullptr;
788 
789  // getMBBFromIndex doesn't need to search the MBB table when both indexes
790  // belong to proper instructions.
791  MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
792  MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
793  return MBB1 == MBB2 ? MBB1 : nullptr;
794 }
795 
796 bool
797 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
798  for (const VNInfo *PHI : LI.valnos) {
799  if (PHI->isUnused() || !PHI->isPHIDef())
800  continue;
801  const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
802  // Conservatively return true instead of scanning huge predecessor lists.
803  if (PHIMBB->pred_size() > 100)
804  return true;
806  PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
807  if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
808  return true;
809  }
810  return false;
811 }
812 
813 float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
814  const MachineBlockFrequencyInfo *MBFI,
815  const MachineInstr &MI) {
816  BlockFrequency Freq = MBFI->getBlockFreq(MI.getParent());
817  const float Scale = 1.0f / MBFI->getEntryFreq();
818  return (isDef + isUse) * (Freq.getFrequency() * Scale);
819 }
820 
824  VNInfo *VN = Interval.getNextValue(
825  SlotIndex(getInstructionIndex(startInst).getRegSlot()),
827  LiveRange::Segment S(SlotIndex(getInstructionIndex(startInst).getRegSlot()),
828  getMBBEndIdx(startInst.getParent()), VN);
829  Interval.addSegment(S);
830 
831  return S;
832 }
833 
834 
835 //===----------------------------------------------------------------------===//
836 // Register mask functions
837 //===----------------------------------------------------------------------===//
838 
840  BitVector &UsableRegs) {
841  if (LI.empty())
842  return false;
843  LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
844 
845  // Use a smaller arrays for local live ranges.
846  ArrayRef<SlotIndex> Slots;
848  if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
849  Slots = getRegMaskSlotsInBlock(MBB->getNumber());
850  Bits = getRegMaskBitsInBlock(MBB->getNumber());
851  } else {
852  Slots = getRegMaskSlots();
853  Bits = getRegMaskBits();
854  }
855 
856  // We are going to enumerate all the register mask slots contained in LI.
857  // Start with a binary search of RegMaskSlots to find a starting point.
859  std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
860  ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
861 
862  // No slots in range, LI begins after the last call.
863  if (SlotI == SlotE)
864  return false;
865 
866  bool Found = false;
867  for (;;) {
868  assert(*SlotI >= LiveI->start);
869  // Loop over all slots overlapping this segment.
870  while (*SlotI < LiveI->end) {
871  // *SlotI overlaps LI. Collect mask bits.
872  if (!Found) {
873  // This is the first overlap. Initialize UsableRegs to all ones.
874  UsableRegs.clear();
875  UsableRegs.resize(TRI->getNumRegs(), true);
876  Found = true;
877  }
878  // Remove usable registers clobbered by this mask.
879  UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
880  if (++SlotI == SlotE)
881  return Found;
882  }
883  // *SlotI is beyond the current LI segment.
884  LiveI = LI.advanceTo(LiveI, *SlotI);
885  if (LiveI == LiveE)
886  return Found;
887  // Advance SlotI until it overlaps.
888  while (*SlotI < LiveI->start)
889  if (++SlotI == SlotE)
890  return Found;
891  }
892 }
893 
894 //===----------------------------------------------------------------------===//
895 // IntervalUpdate class.
896 //===----------------------------------------------------------------------===//
897 
898 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
900 private:
901  LiveIntervals& LIS;
902  const MachineRegisterInfo& MRI;
903  const TargetRegisterInfo& TRI;
904  SlotIndex OldIdx;
905  SlotIndex NewIdx;
907  bool UpdateFlags;
908 
909 public:
910  HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
911  const TargetRegisterInfo& TRI,
912  SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
913  : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
914  UpdateFlags(UpdateFlags) {}
915 
916  // FIXME: UpdateFlags is a workaround that creates live intervals for all
917  // physregs, even those that aren't needed for regalloc, in order to update
918  // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
919  // flags, and postRA passes will use a live register utility instead.
920  LiveRange *getRegUnitLI(unsigned Unit) {
921  if (UpdateFlags)
922  return &LIS.getRegUnit(Unit);
923  return LIS.getCachedRegUnit(Unit);
924  }
925 
926  /// Update all live ranges touched by MI, assuming a move from OldIdx to
927  /// NewIdx.
929  DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
930  bool hasRegMask = false;
931  for (MachineOperand &MO : MI->operands()) {
932  if (MO.isRegMask())
933  hasRegMask = true;
934  if (!MO.isReg())
935  continue;
936  if (MO.isUse()) {
937  if (!MO.readsReg())
938  continue;
939  // Aggressively clear all kill flags.
940  // They are reinserted by VirtRegRewriter.
941  MO.setIsKill(false);
942  }
943 
944  unsigned Reg = MO.getReg();
945  if (!Reg)
946  continue;
948  LiveInterval &LI = LIS.getInterval(Reg);
949  if (LI.hasSubRanges()) {
950  unsigned SubReg = MO.getSubReg();
951  LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg)
952  : MRI.getMaxLaneMaskForVReg(Reg);
953  for (LiveInterval::SubRange &S : LI.subranges()) {
954  if ((S.LaneMask & LaneMask).none())
955  continue;
956  updateRange(S, Reg, S.LaneMask);
957  }
958  }
959  updateRange(LI, Reg, LaneBitmask::getNone());
960  continue;
961  }
962 
963  // For physregs, only update the regunits that actually have a
964  // precomputed live range.
965  for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
966  if (LiveRange *LR = getRegUnitLI(*Units))
967  updateRange(*LR, *Units, LaneBitmask::getNone());
968  }
969  if (hasRegMask)
970  updateRegMaskSlots();
971  }
972 
973 private:
974  /// Update a single live range, assuming an instruction has been moved from
975  /// OldIdx to NewIdx.
976  void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
977  if (!Updated.insert(&LR).second)
978  return;
979  DEBUG({
980  dbgs() << " ";
982  dbgs() << PrintReg(Reg);
983  if (LaneMask.any())
984  dbgs() << " L" << PrintLaneMask(LaneMask);
985  } else {
986  dbgs() << PrintRegUnit(Reg, &TRI);
987  }
988  dbgs() << ":\t" << LR << '\n';
989  });
990  if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
991  handleMoveDown(LR);
992  else
993  handleMoveUp(LR, Reg, LaneMask);
994  DEBUG(dbgs() << " -->\t" << LR << '\n');
995  LR.verify();
996  }
997 
998  /// Update LR to reflect an instruction has been moved downwards from OldIdx
999  /// to NewIdx (OldIdx < NewIdx).
1000  void handleMoveDown(LiveRange &LR) {
1001  LiveRange::iterator E = LR.end();
1002  // Segment going into OldIdx.
1003  LiveRange::iterator OldIdxIn = LR.find(OldIdx.getBaseIndex());
1004 
1005  // No value live before or after OldIdx? Nothing to do.
1006  if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1007  return;
1008 
1009  LiveRange::iterator OldIdxOut;
1010  // Do we have a value live-in to OldIdx?
1011  if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1012  // If the live-in value already extends to NewIdx, there is nothing to do.
1013  if (SlotIndex::isEarlierEqualInstr(NewIdx, OldIdxIn->end))
1014  return;
1015  // Aggressively remove all kill flags from the old kill point.
1016  // Kill flags shouldn't be used while live intervals exist, they will be
1017  // reinserted by VirtRegRewriter.
1018  if (MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end))
1019  for (MIBundleOperands MO(*KillMI); MO.isValid(); ++MO)
1020  if (MO->isReg() && MO->isUse())
1021  MO->setIsKill(false);
1022 
1023  // Is there a def before NewIdx which is not OldIdx?
1024  LiveRange::iterator Next = std::next(OldIdxIn);
1025  if (Next != E && !SlotIndex::isSameInstr(OldIdx, Next->start) &&
1026  SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1027  // If we are here then OldIdx was just a use but not a def. We only have
1028  // to ensure liveness extends to NewIdx.
1029  LiveRange::iterator NewIdxIn =
1030  LR.advanceTo(Next, NewIdx.getBaseIndex());
1031  // Extend the segment before NewIdx if necessary.
1032  if (NewIdxIn == E ||
1033  !SlotIndex::isEarlierInstr(NewIdxIn->start, NewIdx)) {
1034  LiveRange::iterator Prev = std::prev(NewIdxIn);
1035  Prev->end = NewIdx.getRegSlot();
1036  }
1037  // Extend OldIdxIn.
1038  OldIdxIn->end = Next->start;
1039  return;
1040  }
1041 
1042  // Adjust OldIdxIn->end to reach NewIdx. This may temporarily make LR
1043  // invalid by overlapping ranges.
1044  bool isKill = SlotIndex::isSameInstr(OldIdx, OldIdxIn->end);
1045  OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());
1046  // If this was not a kill, then there was no def and we're done.
1047  if (!isKill)
1048  return;
1049 
1050  // Did we have a Def at OldIdx?
1051  OldIdxOut = Next;
1052  if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1053  return;
1054  } else {
1055  OldIdxOut = OldIdxIn;
1056  }
1057 
1058  // If we are here then there is a Definition at OldIdx. OldIdxOut points
1059  // to the segment starting there.
1060  assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1061  "No def?");
1062  VNInfo *OldIdxVNI = OldIdxOut->valno;
1063  assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1064 
1065  // If the defined value extends beyond NewIdx, just move the beginning
1066  // of the segment to NewIdx.
1067  SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1068  if (SlotIndex::isEarlierInstr(NewIdxDef, OldIdxOut->end)) {
1069  OldIdxVNI->def = NewIdxDef;
1070  OldIdxOut->start = OldIdxVNI->def;
1071  return;
1072  }
1073 
1074  // If we are here then we have a Definition at OldIdx which ends before
1075  // NewIdx.
1076 
1077  // Is there an existing Def at NewIdx?
1078  LiveRange::iterator AfterNewIdx
1079  = LR.advanceTo(OldIdxOut, NewIdx.getRegSlot());
1080  bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1081  if (!OldIdxDefIsDead &&
1082  SlotIndex::isEarlierInstr(OldIdxOut->end, NewIdxDef)) {
1083  // OldIdx is not a dead def, and NewIdxDef is inside a new interval.
1084  VNInfo *DefVNI;
1085  if (OldIdxOut != LR.begin() &&
1086  !SlotIndex::isEarlierInstr(std::prev(OldIdxOut)->end,
1087  OldIdxOut->start)) {
1088  // There is no gap between OldIdxOut and its predecessor anymore,
1089  // merge them.
1090  LiveRange::iterator IPrev = std::prev(OldIdxOut);
1091  DefVNI = OldIdxVNI;
1092  IPrev->end = OldIdxOut->end;
1093  } else {
1094  // The value is live in to OldIdx
1095  LiveRange::iterator INext = std::next(OldIdxOut);
1096  assert(INext != E && "Must have following segment");
1097  // We merge OldIdxOut and its successor. As we're dealing with subreg
1098  // reordering, there is always a successor to OldIdxOut in the same BB
1099  // We don't need INext->valno anymore and will reuse for the new segment
1100  // we create later.
1101  DefVNI = OldIdxVNI;
1102  INext->start = OldIdxOut->end;
1103  INext->valno->def = INext->start;
1104  }
1105  // If NewIdx is behind the last segment, extend that and append a new one.
1106  if (AfterNewIdx == E) {
1107  // OldIdxOut is undef at this point, Slide (OldIdxOut;AfterNewIdx] up
1108  // one position.
1109  // |- ?/OldIdxOut -| |- X0 -| ... |- Xn -| end
1110  // => |- X0/OldIdxOut -| ... |- Xn -| |- undef/NewS -| end
1111  std::copy(std::next(OldIdxOut), E, OldIdxOut);
1112  // The last segment is undefined now, reuse it for a dead def.
1113  LiveRange::iterator NewSegment = std::prev(E);
1114  *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),
1115  DefVNI);
1116  DefVNI->def = NewIdxDef;
1117 
1118  LiveRange::iterator Prev = std::prev(NewSegment);
1119  Prev->end = NewIdxDef;
1120  } else {
1121  // OldIdxOut is undef at this point, Slide (OldIdxOut;AfterNewIdx] up
1122  // one position.
1123  // |- ?/OldIdxOut -| |- X0 -| ... |- Xn/AfterNewIdx -| |- Next -|
1124  // => |- X0/OldIdxOut -| ... |- Xn -| |- Xn/AfterNewIdx -| |- Next -|
1125  std::copy(std::next(OldIdxOut), std::next(AfterNewIdx), OldIdxOut);
1126  LiveRange::iterator Prev = std::prev(AfterNewIdx);
1127  // We have two cases:
1128  if (SlotIndex::isEarlierInstr(Prev->start, NewIdxDef)) {
1129  // Case 1: NewIdx is inside a liverange. Split this liverange at
1130  // NewIdxDef into the segment "Prev" followed by "NewSegment".
1131  LiveRange::iterator NewSegment = AfterNewIdx;
1132  *NewSegment = LiveRange::Segment(NewIdxDef, Prev->end, Prev->valno);
1133  Prev->valno->def = NewIdxDef;
1134 
1135  *Prev = LiveRange::Segment(Prev->start, NewIdxDef, DefVNI);
1136  DefVNI->def = Prev->start;
1137  } else {
1138  // Case 2: NewIdx is in a lifetime hole. Keep AfterNewIdx as is and
1139  // turn Prev into a segment from NewIdx to AfterNewIdx->start.
1140  *Prev = LiveRange::Segment(NewIdxDef, AfterNewIdx->start, DefVNI);
1141  DefVNI->def = NewIdxDef;
1142  assert(DefVNI != AfterNewIdx->valno);
1143  }
1144  }
1145  return;
1146  }
1147 
1148  if (AfterNewIdx != E &&
1149  SlotIndex::isSameInstr(AfterNewIdx->start, NewIdxDef)) {
1150  // There is an existing def at NewIdx. The def at OldIdx is coalesced into
1151  // that value.
1152  assert(AfterNewIdx->valno != OldIdxVNI && "Multiple defs of value?");
1153  LR.removeValNo(OldIdxVNI);
1154  } else {
1155  // There was no existing def at NewIdx. We need to create a dead def
1156  // at NewIdx. Shift segments over the old OldIdxOut segment, this frees
1157  // a new segment at the place where we want to construct the dead def.
1158  // |- OldIdxOut -| |- X0 -| ... |- Xn -| |- AfterNewIdx -|
1159  // => |- X0/OldIdxOut -| ... |- Xn -| |- undef/NewS. -| |- AfterNewIdx -|
1160  assert(AfterNewIdx != OldIdxOut && "Inconsistent iterators");
1161  std::copy(std::next(OldIdxOut), AfterNewIdx, OldIdxOut);
1162  // We can reuse OldIdxVNI now.
1163  LiveRange::iterator NewSegment = std::prev(AfterNewIdx);
1164  VNInfo *NewSegmentVNI = OldIdxVNI;
1165  NewSegmentVNI->def = NewIdxDef;
1166  *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),
1167  NewSegmentVNI);
1168  }
1169  }
1170 
1171  /// Update LR to reflect an instruction has been moved upwards from OldIdx
1172  /// to NewIdx (NewIdx < OldIdx).
1173  void handleMoveUp(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
1174  LiveRange::iterator E = LR.end();
1175  // Segment going into OldIdx.
1176  LiveRange::iterator OldIdxIn = LR.find(OldIdx.getBaseIndex());
1177 
1178  // No value live before or after OldIdx? Nothing to do.
1179  if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1180  return;
1181 
1182  LiveRange::iterator OldIdxOut;
1183  // Do we have a value live-in to OldIdx?
1184  if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1185  // If the live-in value isn't killed here, then we have no Def at
1186  // OldIdx, moreover the value must be live at NewIdx so there is nothing
1187  // to do.
1188  bool isKill = SlotIndex::isSameInstr(OldIdx, OldIdxIn->end);
1189  if (!isKill)
1190  return;
1191 
1192  // At this point we have to move OldIdxIn->end back to the nearest
1193  // previous use or (dead-)def but no further than NewIdx.
1194  SlotIndex DefBeforeOldIdx
1195  = std::max(OldIdxIn->start.getDeadSlot(),
1196  NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));
1197  OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, Reg, LaneMask);
1198 
1199  // Did we have a Def at OldIdx? If not we are done now.
1200  OldIdxOut = std::next(OldIdxIn);
1201  if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1202  return;
1203  } else {
1204  OldIdxOut = OldIdxIn;
1205  OldIdxIn = OldIdxOut != LR.begin() ? std::prev(OldIdxOut) : E;
1206  }
1207 
1208  // If we are here then there is a Definition at OldIdx. OldIdxOut points
1209  // to the segment starting there.
1210  assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1211  "No def?");
1212  VNInfo *OldIdxVNI = OldIdxOut->valno;
1213  assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1214  bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1215 
1216  // Is there an existing def at NewIdx?
1217  SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1218  LiveRange::iterator NewIdxOut = LR.find(NewIdx.getRegSlot());
1219  if (SlotIndex::isSameInstr(NewIdxOut->start, NewIdx)) {
1220  assert(NewIdxOut->valno != OldIdxVNI &&
1221  "Same value defined more than once?");
1222  // If OldIdx was a dead def remove it.
1223  if (!OldIdxDefIsDead) {
1224  // Remove segment starting at NewIdx and move begin of OldIdxOut to
1225  // NewIdx so it can take its place.
1226  OldIdxVNI->def = NewIdxDef;
1227  OldIdxOut->start = NewIdxDef;
1228  LR.removeValNo(NewIdxOut->valno);
1229  } else {
1230  // Simply remove the dead def at OldIdx.
1231  LR.removeValNo(OldIdxVNI);
1232  }
1233  } else {
1234  // Previously nothing was live after NewIdx, so all we have to do now is
1235  // move the begin of OldIdxOut to NewIdx.
1236  if (!OldIdxDefIsDead) {
1237  // Do we have any intermediate Defs between OldIdx and NewIdx?
1238  if (OldIdxIn != E &&
1239  SlotIndex::isEarlierInstr(NewIdxDef, OldIdxIn->start)) {
1240  // OldIdx is not a dead def and NewIdx is before predecessor start.
1241  LiveRange::iterator NewIdxIn = NewIdxOut;
1242  assert(NewIdxIn == LR.find(NewIdx.getBaseIndex()));
1243  const SlotIndex SplitPos = NewIdxDef;
1244 
1245  // Merge the OldIdxIn and OldIdxOut segments into OldIdxOut.
1246  *OldIdxOut = LiveRange::Segment(OldIdxIn->start, OldIdxOut->end,
1247  OldIdxIn->valno);
1248  // OldIdxIn and OldIdxVNI are now undef and can be overridden.
1249  // We Slide [NewIdxIn, OldIdxIn) down one position.
1250  // |- X0/NewIdxIn -| ... |- Xn-1 -||- Xn/OldIdxIn -||- OldIdxOut -|
1251  // => |- undef/NexIdxIn -| |- X0 -| ... |- Xn-1 -| |- Xn/OldIdxOut -|
1252  std::copy_backward(NewIdxIn, OldIdxIn, OldIdxOut);
1253  // NewIdxIn is now considered undef so we can reuse it for the moved
1254  // value.
1255  LiveRange::iterator NewSegment = NewIdxIn;
1256  LiveRange::iterator Next = std::next(NewSegment);
1257  if (SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1258  // There is no gap between NewSegment and its predecessor.
1259  *NewSegment = LiveRange::Segment(Next->start, SplitPos,
1260  Next->valno);
1261  *Next = LiveRange::Segment(SplitPos, Next->end, OldIdxVNI);
1262  Next->valno->def = SplitPos;
1263  } else {
1264  // There is a gap between NewSegment and its predecessor
1265  // Value becomes live in.
1266  *NewSegment = LiveRange::Segment(SplitPos, Next->start, OldIdxVNI);
1267  NewSegment->valno->def = SplitPos;
1268  }
1269  } else {
1270  // Leave the end point of a live def.
1271  OldIdxOut->start = NewIdxDef;
1272  OldIdxVNI->def = NewIdxDef;
1273  if (OldIdxIn != E && SlotIndex::isEarlierInstr(NewIdx, OldIdxIn->end))
1274  OldIdxIn->end = NewIdx.getRegSlot();
1275  }
1276  } else {
1277  // OldIdxVNI is a dead def. It may have been moved across other values
1278  // in LR, so move OldIdxOut up to NewIdxOut. Slide [NewIdxOut;OldIdxOut)
1279  // down one position.
1280  // |- X0/NewIdxOut -| ... |- Xn-1 -| |- Xn/OldIdxOut -| |- next - |
1281  // => |- undef/NewIdxOut -| |- X0 -| ... |- Xn-1 -| |- next -|
1282  std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));
1283  // OldIdxVNI can be reused now to build a new dead def segment.
1284  LiveRange::iterator NewSegment = NewIdxOut;
1285  VNInfo *NewSegmentVNI = OldIdxVNI;
1286  *NewSegment = LiveRange::Segment(NewIdxDef, NewIdxDef.getDeadSlot(),
1287  NewSegmentVNI);
1288  NewSegmentVNI->def = NewIdxDef;
1289  }
1290  }
1291  }
1292 
1293  void updateRegMaskSlots() {
1295  std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1296  OldIdx);
1297  assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1298  "No RegMask at OldIdx.");
1299  *RI = NewIdx.getRegSlot();
1300  assert((RI == LIS.RegMaskSlots.begin() ||
1301  SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1302  "Cannot move regmask instruction above another call");
1303  assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1304  SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1305  "Cannot move regmask instruction below another call");
1306  }
1307 
1308  // Return the last use of reg between NewIdx and OldIdx.
1309  SlotIndex findLastUseBefore(SlotIndex Before, unsigned Reg,
1310  LaneBitmask LaneMask) {
1312  SlotIndex LastUse = Before;
1313  for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1314  if (MO.isUndef())
1315  continue;
1316  unsigned SubReg = MO.getSubReg();
1317  if (SubReg != 0 && LaneMask.any()
1318  && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())
1319  continue;
1320 
1321  const MachineInstr &MI = *MO.getParent();
1322  SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1323  if (InstSlot > LastUse && InstSlot < OldIdx)
1324  LastUse = InstSlot.getRegSlot();
1325  }
1326  return LastUse;
1327  }
1328 
1329  // This is a regunit interval, so scanning the use list could be very
1330  // expensive. Scan upwards from OldIdx instead.
1331  assert(Before < OldIdx && "Expected upwards move");
1332  SlotIndexes *Indexes = LIS.getSlotIndexes();
1333  MachineBasicBlock *MBB = Indexes->getMBBFromIndex(Before);
1334 
1335  // OldIdx may not correspond to an instruction any longer, so set MII to
1336  // point to the next instruction after OldIdx, or MBB->end().
1337  MachineBasicBlock::iterator MII = MBB->end();
1338  if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1339  Indexes->getNextNonNullIndex(OldIdx)))
1340  if (MI->getParent() == MBB)
1341  MII = MI;
1342 
1343  MachineBasicBlock::iterator Begin = MBB->begin();
1344  while (MII != Begin) {
1345  if ((--MII)->isDebugValue())
1346  continue;
1347  SlotIndex Idx = Indexes->getInstructionIndex(*MII);
1348 
1349  // Stop searching when Before is reached.
1350  if (!SlotIndex::isEarlierInstr(Before, Idx))
1351  return Before;
1352 
1353  // Check if MII uses Reg.
1354  for (MIBundleOperands MO(*MII); MO.isValid(); ++MO)
1355  if (MO->isReg() && !MO->isUndef() &&
1357  TRI.hasRegUnit(MO->getReg(), Reg))
1358  return Idx.getRegSlot();
1359  }
1360  // Didn't reach Before. It must be the first instruction in the block.
1361  return Before;
1362  }
1363 };
1364 
1365 void LiveIntervals::handleMove(MachineInstr &MI, bool UpdateFlags) {
1366  assert(!MI.isBundled() && "Can't handle bundled instructions yet.");
1367  SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1368  Indexes->removeMachineInstrFromMaps(MI);
1369  SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1370  assert(getMBBStartIdx(MI.getParent()) <= OldIndex &&
1371  OldIndex < getMBBEndIdx(MI.getParent()) &&
1372  "Cannot handle moves across basic block boundaries.");
1373 
1374  HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1375  HME.updateAllRanges(&MI);
1376 }
1377 
1379  MachineInstr &BundleStart,
1380  bool UpdateFlags) {
1381  SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1382  SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1383  HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1384  HME.updateAllRanges(&MI);
1385 }
1386 
1387 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1389  const SlotIndex endIdx,
1390  LiveRange &LR, const unsigned Reg,
1391  LaneBitmask LaneMask) {
1392  LiveInterval::iterator LII = LR.find(endIdx);
1393  SlotIndex lastUseIdx;
1394  if (LII == LR.begin()) {
1395  // This happens when the function is called for a subregister that only
1396  // occurs _after_ the range that is to be repaired.
1397  return;
1398  }
1399  if (LII != LR.end() && LII->start < endIdx)
1400  lastUseIdx = LII->end;
1401  else
1402  --LII;
1403 
1404  for (MachineBasicBlock::iterator I = End; I != Begin;) {
1405  --I;
1406  MachineInstr &MI = *I;
1407  if (MI.isDebugValue())
1408  continue;
1409 
1410  SlotIndex instrIdx = getInstructionIndex(MI);
1411  bool isStartValid = getInstructionFromIndex(LII->start);
1412  bool isEndValid = getInstructionFromIndex(LII->end);
1413 
1414  // FIXME: This doesn't currently handle early-clobber or multiple removed
1415  // defs inside of the region to repair.
1417  OE = MI.operands_end();
1418  OI != OE; ++OI) {
1419  const MachineOperand &MO = *OI;
1420  if (!MO.isReg() || MO.getReg() != Reg)
1421  continue;
1422 
1423  unsigned SubReg = MO.getSubReg();
1424  LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
1425  if ((Mask & LaneMask).none())
1426  continue;
1427 
1428  if (MO.isDef()) {
1429  if (!isStartValid) {
1430  if (LII->end.isDead()) {
1431  SlotIndex prevStart;
1432  if (LII != LR.begin())
1433  prevStart = std::prev(LII)->start;
1434 
1435  // FIXME: This could be more efficient if there was a
1436  // removeSegment method that returned an iterator.
1437  LR.removeSegment(*LII, true);
1438  if (prevStart.isValid())
1439  LII = LR.find(prevStart);
1440  else
1441  LII = LR.begin();
1442  } else {
1443  LII->start = instrIdx.getRegSlot();
1444  LII->valno->def = instrIdx.getRegSlot();
1445  if (MO.getSubReg() && !MO.isUndef())
1446  lastUseIdx = instrIdx.getRegSlot();
1447  else
1448  lastUseIdx = SlotIndex();
1449  continue;
1450  }
1451  }
1452 
1453  if (!lastUseIdx.isValid()) {
1454  VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1455  LiveRange::Segment S(instrIdx.getRegSlot(),
1456  instrIdx.getDeadSlot(), VNI);
1457  LII = LR.addSegment(S);
1458  } else if (LII->start != instrIdx.getRegSlot()) {
1459  VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1460  LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1461  LII = LR.addSegment(S);
1462  }
1463 
1464  if (MO.getSubReg() && !MO.isUndef())
1465  lastUseIdx = instrIdx.getRegSlot();
1466  else
1467  lastUseIdx = SlotIndex();
1468  } else if (MO.isUse()) {
1469  // FIXME: This should probably be handled outside of this branch,
1470  // either as part of the def case (for defs inside of the region) or
1471  // after the loop over the region.
1472  if (!isEndValid && !LII->end.isBlock())
1473  LII->end = instrIdx.getRegSlot();
1474  if (!lastUseIdx.isValid())
1475  lastUseIdx = instrIdx.getRegSlot();
1476  }
1477  }
1478  }
1479 }
1480 
1481 void
1485  ArrayRef<unsigned> OrigRegs) {
1486  // Find anchor points, which are at the beginning/end of blocks or at
1487  // instructions that already have indexes.
1488  while (Begin != MBB->begin() && !Indexes->hasIndex(*Begin))
1489  --Begin;
1490  while (End != MBB->end() && !Indexes->hasIndex(*End))
1491  ++End;
1492 
1493  SlotIndex endIdx;
1494  if (End == MBB->end())
1495  endIdx = getMBBEndIdx(MBB).getPrevSlot();
1496  else
1497  endIdx = getInstructionIndex(*End);
1498 
1499  Indexes->repairIndexesInRange(MBB, Begin, End);
1500 
1501  for (MachineBasicBlock::iterator I = End; I != Begin;) {
1502  --I;
1503  MachineInstr &MI = *I;
1504  if (MI.isDebugValue())
1505  continue;
1507  MOE = MI.operands_end();
1508  MOI != MOE; ++MOI) {
1509  if (MOI->isReg() &&
1510  TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1511  !hasInterval(MOI->getReg())) {
1512  createAndComputeVirtRegInterval(MOI->getReg());
1513  }
1514  }
1515  }
1516 
1517  for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1518  unsigned Reg = OrigRegs[i];
1520  continue;
1521 
1522  LiveInterval &LI = getInterval(Reg);
1523  // FIXME: Should we support undefs that gain defs?
1524  if (!LI.hasAtLeastOneValue())
1525  continue;
1526 
1527  for (LiveInterval::SubRange &S : LI.subranges()) {
1528  repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1529  }
1530  repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1531  }
1532 }
1533 
1535  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1536  if (LiveRange *LR = getCachedRegUnit(*Units))
1537  if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1538  LR->removeValNo(VNI);
1539  }
1540 }
1541 
1543  // LI may not have the main range computed yet, but its subranges may
1544  // be present.
1545  VNInfo *VNI = LI.getVNInfoAt(Pos);
1546  if (VNI != nullptr) {
1547  assert(VNI->def.getBaseIndex() == Pos.getBaseIndex());
1548  LI.removeValNo(VNI);
1549  }
1550 
1551  // Also remove the value defined in subranges.
1552  for (LiveInterval::SubRange &S : LI.subranges()) {
1553  if (VNInfo *SVNI = S.getVNInfoAt(Pos))
1554  if (SVNI->def.getBaseIndex() == Pos.getBaseIndex())
1555  S.removeValNo(SVNI);
1556  }
1557  LI.removeEmptySubRanges();
1558 }
1559 
1561  SmallVectorImpl<LiveInterval*> &SplitLIs) {
1562  ConnectedVNInfoEqClasses ConEQ(*this);
1563  unsigned NumComp = ConEQ.Classify(LI);
1564  if (NumComp <= 1)
1565  return;
1566  DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
1567  unsigned Reg = LI.reg;
1568  const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
1569  for (unsigned I = 1; I < NumComp; ++I) {
1570  unsigned NewVReg = MRI->createVirtualRegister(RegClass);
1571  LiveInterval &NewLI = createEmptyInterval(NewVReg);
1572  SplitLIs.push_back(&NewLI);
1573  }
1574  ConEQ.Distribute(LI, SplitLIs.data(), *MRI);
1575 }
1576 
1578  assert(LRCalc && "LRCalc not initialized.");
1579  LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
1580  LRCalc->constructMainRangeFromSubranges(LI);
1581 }
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:193
void push_back(const T &Elt)
Definition: SmallVector.h:211
bool isEHPad() const
Returns true if the block is a landing pad.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:241
mop_iterator operands_end()
Definition: MachineInstr.h:296
bool isValid() const
Check if the iterator is at the end of the list.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
Definition: LiveInterval.h:383
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef< SlotIndex > getRegMaskSlots() const
getRegMaskSlots - Returns a sorted array of slot indices of all instructions with register mask opera...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:406
const unsigned reg
Definition: LiveInterval.h:656
iterator_range< livein_iterator > liveins() const
cl::opt< bool > UseSegmentSetForPhysRegs
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
void createDeadDefs(LiveRange &LR, unsigned Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
void updateAllRanges(MachineInstr *MI)
Update all live ranges touched by MI, assuming a move from OldIdx to NewIdx.
size_t i
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
Definition: SlotIndexes.h:234
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool runOnMachineFunction(MachineFunction &) override
runOnMachineFunction - pass entry point
Interval Class - An Interval is a set of nodes defined such that every node in the interval has all o...
Definition: Interval.h:37
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static LaneBitmask getAll()
Definition: LaneBitmask.h:75
vni_iterator vni_begin()
Definition: LiveInterval.h:213
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
MIBundleOperands - Iterate over all operands in a bundle of machine instructions. ...
iterator end() const
Definition: ArrayRef.h:130
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void removeMachineInstrFromMaps(MachineInstr &MI)
Remove the given machine instruction from the mapping.
Definition: SlotIndexes.h:606
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
Definition: LiveInterval.h:246
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:873
INITIALIZE_PASS_BEGIN(LiveIntervals,"liveintervals","Live Interval Analysis", false, false) INITIALIZE_PASS_END(LiveIntervals
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
A live range for subregisters.
Definition: LiveInterval.h:632
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
I SRs[*I]
Live Interval false
SlotIndex endPoint() const
Return the end point of the last live range segment to interact with the instruction, if any.
Definition: LiveInterval.h:143
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
void markUnused()
Mark this value as unused.
Definition: LiveInterval.h:80
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
void print(raw_ostream &O, const Module *=nullptr) const override
print - Implement the dump method.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
void dump() const
Definition: Pass.cpp:122
void flushSegmentSet()
Flush segment set into the regular segment vector.
bool empty() const
Definition: LiveInterval.h:357
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:396
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void Distribute(LiveInterval &LI, LiveInterval *LIV[], MachineRegisterInfo &MRI)
Distribute values in LI into a separate LiveIntervals for each connected component.
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB...
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
Definition: SlotIndexes.h:196
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill...
void clear()
clear - Clear all bits.
Definition: BitVector.h:188
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
intervalIsInOneMBB - If LI is confined to a single basic block, return a pointer to that block...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all instructions with register mas...
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it...
Definition: Allocator.h:192
ArrayRef< const uint32_t * > getRegMaskBits() const
getRegMaskBits() - Returns an array of register mask pointers corresponding to getRegMaskSlots().
iterator end()
Definition: LiveInterval.h:206
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:401
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:710
unsigned SubReg
Result of a LiveRange query.
Definition: LiveInterval.h:86
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SmallVector< std::pair< SlotIndex, VNInfo * >, 16 > ShrinkToUsesWorkList
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:219
Live Interval Analysis
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:252
constexpr bool any() const
Definition: LaneBitmask.h:51
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:77
static reg_instr_iterator reg_instr_end()
SlotIndex getNextNonNullIndex(SlotIndex Index)
Returns the next non-null index, if one exists.
Definition: SlotIndexes.h:422
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
SlotIndexes pass.
Definition: SlotIndexes.h:323
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MCRegUnitRootIterator enumerates the root registers of a register unit.
Segments segments
Definition: LiveInterval.h:195
MachineBasicBlock * MBB
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:223
VNInfo * valueOutOrDead() const
Returns the value alive at the end of the instruction, if any.
Definition: LiveInterval.h:125
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses...
static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes, ShrinkToUsesWorkList &WorkList, const LiveRange &OldRange)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
AnalysisUsage & addPreservedID(const void *ID)
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
const float huge_valf
Use this rather than HUGE_VALF; the latter causes warnings on MSVC.
Definition: MathExtras.cpp:29
const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the start of this basic block.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
LiveRange * getCachedRegUnit(unsigned Unit)
getCachedRegUnit - Return the live range for Unit if it has already been computed, or NULL if it hasn't been computed yet.
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:282
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
bool isDebugValue() const
Definition: MachineInstr.h:777
void reset(const MachineFunction *MF, SlotIndexes *, MachineDominatorTree *, VNInfo::Allocator *)
reset - Prepare caches for a new set of non-overlapping live ranges.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:565
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
bool hasAtLeastOneValue() const
Definition: LiveInterval.h:284
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
Definition: BitVector.h:501
SlotIndexes * getSlotIndexes() const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:516
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:144
unsigned const MachineRegisterInfo * MRI
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void swap(SmallVectorImpl &RHS)
Definition: SmallVector.h:675
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Use)
Attempt to extend a value defined after StartIdx to include Use.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
MachineInstrBuilder & UseMI
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
Live Interval static false cl::opt< bool > EnablePrecomputePhysRegs("precompute-phys-liveness", cl::Hidden, cl::desc("Eagerly compute live intervals for all physreg units."))
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
void initializeLiveIntervalsPass(PassRegistry &)
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
iterator begin() const
Definition: ArrayRef.h:129
VNInfo * valueDefined() const
Return the value defined by this instruction, if any.
Definition: LiveInterval.h:131
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
HMEditor(LiveIntervals &LIS, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
iterator_range< pred_iterator > predecessors()
void verify() const
Walk the range and assert if any invariants fail to hold.
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< unsigned > OrigRegs)
repairIntervalsInRange - Update live intervals for instructions in a range of iterators.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:74
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:416
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
unsigned id
The ID number of this value.
Definition: LiveInterval.h:50
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
getRegMaskBitsInBlock - Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBB...
Iterator for intrusive lists based on ilist_node.
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:190
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:892
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:521
static LaneBitmask getNone()
Definition: LaneBitmask.h:74
LiveRange * getRegUnitLI(unsigned Unit)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
LiveInterval & getInterval(unsigned Reg)
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &Instr)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:489
A range adaptor for a pair of iterators.
void repairIndexesInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End)
Repair indexes after adding and removing instructions.
LiveInterval & createEmptyInterval(unsigned Reg)
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
VNInfoList valnos
Definition: LiveInterval.h:196
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Definition: LiveInterval.h:360
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B)
Return true if A refers to the same instruction as B or an earlier one.
Definition: SlotIndexes.h:202
pointer data()
Return a pointer to the vector's buffer, even if empty().
Definition: SmallVector.h:142
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void addKillFlags(const VirtRegMap *)
addKillFlags - Add kill flags to any instruction that kills a virtual register.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:367
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
AnalysisUsage & addRequiredTransitiveID(char &ID)
Definition: Pass.cpp:299
AnalysisUsage & addRequiredTransitive()
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:479
bool hasInterval(unsigned Reg) const
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:247
std::vector< uint8_t > Unit
Definition: FuzzerDefs.h:71
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
mop_iterator operands_begin()
Definition: MachineInstr.h:295
static LLVM_ATTRIBUTE_UNUSED Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:82
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart, bool UpdateFlags=false)
moveIntoBundle - Update intervals for operands of MI so that they begin/end on the SlotIndex for Bund...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:100
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:98
iterator FindSegmentContaining(SlotIndex Idx)
Return an iterator to the segment that contains the specified index, or end() if there is none...
Definition: LiveInterval.h:411
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:101
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:738
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
vni_iterator vni_end()
Definition: LiveInterval.h:214
unsigned pred_size() const
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
Definition: LiveInterval.h:404
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
handleMove - call this method to notify LiveIntervals that instruction 'mi' has been moved within a b...
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)
static void createSegmentsForValues(LiveRange &LR, iterator_range< LiveInterval::vni_iterator > VNIs)
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...
void resize(size_type N)
Definition: SmallVector.h:352
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.
Definition: SlotIndexes.h:468