28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "AMDGPUGenDFAPacketizer.inc"
40 const DebugLoc &DL,
unsigned DestReg,
41 unsigned SrcReg,
bool KillSrc)
const {
42 unsigned VectorComponents = 0;
43 if ((AMDGPU::R600_Reg128RegClass.
contains(DestReg) ||
44 AMDGPU::R600_Reg128VerticalRegClass.
contains(DestReg)) &&
45 (AMDGPU::R600_Reg128RegClass.
contains(SrcReg) ||
46 AMDGPU::R600_Reg128VerticalRegClass.
contains(SrcReg))) {
48 }
else if((AMDGPU::R600_Reg64RegClass.
contains(DestReg) ||
49 AMDGPU::R600_Reg64VerticalRegClass.
contains(DestReg)) &&
50 (AMDGPU::R600_Reg64RegClass.
contains(SrcReg) ||
51 AMDGPU::R600_Reg64VerticalRegClass.
contains(SrcReg))) {
55 if (VectorComponents > 0) {
56 for (
unsigned I = 0;
I < VectorComponents;
I++) {
59 RI.getSubReg(DestReg, SubRegIndex),
60 RI.getSubReg(SrcReg, SubRegIndex))
76 E = MBBI->operands_end();
I !=
E; ++
I) {
89 case AMDGPU::MOV_IMM_F32:
90 case AMDGPU::MOV_IMM_I32:
101 default:
return false;
102 case AMDGPU::CUBE_r600_pseudo:
103 case AMDGPU::CUBE_r600_real:
104 case AMDGPU::CUBE_eg_pseudo:
105 case AMDGPU::CUBE_eg_real:
143 case AMDGPU::INTERP_PAIR_XY:
144 case AMDGPU::INTERP_PAIR_ZW:
145 case AMDGPU::INTERP_VEC_LOAD:
157 return (
get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
165 return (
get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
200 case AMDGPU::GROUP_BARRIER:
222 if (!
I->isReg() || !
I->isUse() ||
226 if (AMDGPU::R600_LDS_SRC_REGRegClass.
contains(
I->getReg()))
233 static const unsigned SrcSelTable[][2] = {
234 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
235 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
236 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
237 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
238 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
239 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
240 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
241 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
242 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
243 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
244 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}
247 for (
const auto &Row : SrcSelTable) {
260 static const unsigned OpTable[8][2] = {
261 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X},
262 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y},
263 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z},
264 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W},
265 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X},
266 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y},
267 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z},
268 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W},
271 for (
unsigned j = 0; j < 8; j++) {
275 if (Reg == AMDGPU::ALU_CONST) {
286 static const unsigned OpTable[3][2] = {
287 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
288 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel},
289 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel},
292 for (
unsigned j = 0; j < 3; j++) {
298 if (Reg == AMDGPU::ALU_CONST) {
304 if (Reg == AMDGPU::ALU_LITERAL_X) {
307 if (Operand.
isImm()) {
313 Result.
push_back(std::make_pair(&MO, 0));
318 std::vector<std::pair<int, unsigned>>
321 unsigned &ConstCount)
const {
323 const std::pair<int, unsigned> DummyPair(-1, 0);
324 std::vector<std::pair<int, unsigned> > Result;
326 for (
const auto &Src :
getSrcs(MI)) {
328 unsigned Reg = Src.first->getReg();
329 int Index = RI.getEncodingValue(Reg) & 0xff;
330 if (Reg == AMDGPU::OQAP) {
331 Result.push_back(std::make_pair(Index, 0U));
333 if (PV.
find(Reg) != PV.
end()) {
335 Result.push_back(std::make_pair(255, 0U));
340 Result.push_back(DummyPair);
344 Result.push_back(std::make_pair(Index, Chan));
347 Result.push_back(DummyPair);
351 static std::vector<std::pair<int, unsigned> >
352 Swizzle(std::vector<std::pair<int, unsigned> > Src,
354 if (Src[0] == Src[1])
383 unsigned Cycles[3] = { 2, 1, 0};
387 unsigned Cycles[3] = { 1, 2, 2};
391 unsigned Cycles[3] = { 2, 1, 2};
395 unsigned Cycles[3] = { 2, 2, 1};
407 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
408 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
409 const std::vector<std::pair<int, unsigned> > &TransSrcs,
412 memset(Vector, -1,
sizeof(Vector));
413 for (
unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
414 const std::vector<std::pair<int, unsigned> > &Srcs =
416 for (
unsigned j = 0; j < 3; j++) {
417 const std::pair<int, unsigned> &Src = Srcs[j];
418 if (Src.first < 0 || Src.first == 255)
420 if (Src.first ==
GET_REG_INDEX(RI.getEncodingValue(AMDGPU::OQAP))) {
430 if (Vector[Src.second][j] < 0)
431 Vector[Src.second][j] = Src.first;
432 if (Vector[Src.second][j] != Src.first)
437 for (
unsigned i = 0, e = TransSrcs.size(); i < e; ++
i) {
438 const std::pair<int, unsigned> &Src = TransSrcs[
i];
442 if (Src.first == 255)
444 if (Vector[Src.second][Cycle] < 0)
445 Vector[Src.second][Cycle] = Src.first;
446 if (Vector[Src.second][Cycle] != Src.first)
447 return IGSrcs.size() - 1;
449 return IGSrcs.size();
457 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
459 assert(Idx < SwzCandidate.size());
463 for (
unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
468 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
476 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
477 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
478 const std::vector<std::pair<int, unsigned> > &TransSrcs,
480 unsigned ValidUpTo = 0;
482 ValidUpTo =
isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
483 if (ValidUpTo == IGSrcs.size())
493 const std::vector<std::pair<int, unsigned> > &TransOps,
494 unsigned ConstCount) {
498 for (
unsigned i = 0, e = TransOps.size(); i < e; ++
i) {
499 const std::pair<int, unsigned> &Src = TransOps[
i];
503 if (ConstCount > 0 && Cycle == 0)
505 if (ConstCount > 1 && Cycle == 1)
514 std::vector<BankSwizzle> &ValidSwizzle,
519 std::vector<std::vector<std::pair<int, unsigned> > > IGSrcs;
520 ValidSwizzle.clear();
523 for (
unsigned i = 0, e = IG.size(); i < e; ++
i) {
524 IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount));
526 AMDGPU::OpName::bank_swizzle);
528 IG[i]->getOperand(Op).getImm());
530 std::vector<std::pair<int, unsigned> > TransOps;
534 TransOps = std::move(IGSrcs.back());
536 ValidSwizzle.pop_back();
544 for (
unsigned i = 0; i < 4; i++) {
545 TransBS = TransSwz[
i];
551 ValidSwizzle.push_back(TransBS);
563 assert (Consts.size() <= 12 &&
"Too many operands in instructions group");
564 unsigned Pair1 = 0, Pair2 = 0;
565 for (
unsigned i = 0, n = Consts.size(); i < n; ++
i) {
566 unsigned ReadConstHalf = Consts[
i] & 2;
567 unsigned ReadConstIndex = Consts[
i] & (~3);
568 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
570 Pair1 = ReadHalfConst;
573 if (Pair1 == ReadHalfConst)
576 Pair2 = ReadHalfConst;
579 if (Pair2 != ReadHalfConst)
588 std::vector<unsigned> Consts;
590 for (
unsigned i = 0, n = MIs.size(); i < n; i++) {
595 for (
const auto &Src :
getSrcs(MI)) {
596 if (Src.first->getReg() == AMDGPU::ALU_LITERAL_X)
597 Literals.
insert(Src.second);
598 if (Literals.
size() > 4)
600 if (Src.first->getReg() == AMDGPU::ALU_CONST)
601 Consts.push_back(Src.second);
602 if (AMDGPU::R600_KC0RegClass.
contains(Src.first->getReg()) ||
603 AMDGPU::R600_KC1RegClass.
contains(Src.first->getReg())) {
604 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
606 Consts.push_back((Index << 2) | Chan);
616 return static_cast<const R600Subtarget &
>(STI).createDFAPacketizer(II);
632 while (I != MBB.
begin()) {
644 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
648 return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 ||
649 Opcode == AMDGPU::BRANCH_COND_f32;
656 bool AllowModify)
const {
668 if (!
isJump(I->getOpcode())) {
673 while (I != MBB.
begin() && std::prev(I)->getOpcode() == AMDGPU::JUMP) {
676 I->removeFromParent();
683 if (I == MBB.
begin() || !
isJump((--I)->getOpcode())) {
684 if (LastOpc == AMDGPU::JUMP) {
687 }
else if (LastOpc == AMDGPU::JUMP_COND) {
703 unsigned SecondLastOpc = SecondLastInst.
getOpcode();
706 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
727 if (It->getOpcode() == AMDGPU::CF_ALU ||
728 It->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
739 int *BytesAdded)
const {
740 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
741 assert(!BytesAdded &&
"code size not handled");
749 assert(PredSet &&
"No previous predicate !");
753 BuildMI(&MBB, DL,
get(AMDGPU::JUMP_COND))
757 if (CfAlu == MBB.
end())
759 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
760 CfAlu->setDesc(
get(AMDGPU::CF_ALU_PUSH_BEFORE));
765 assert(PredSet &&
"No previous predicate !");
768 BuildMI(&MBB, DL,
get(AMDGPU::JUMP_COND))
773 if (CfAlu == MBB.
end())
775 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU);
776 CfAlu->setDesc(
get(AMDGPU::CF_ALU_PUSH_BEFORE));
782 int *BytesRemoved)
const {
783 assert(!BytesRemoved &&
"code size not handled");
790 if (I == MBB.
begin()) {
794 switch (I->getOpcode()) {
797 case AMDGPU::JUMP_COND: {
800 I->eraseFromParent();
802 if (CfAlu == MBB.
end())
804 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
805 CfAlu->setDesc(
get(AMDGPU::CF_ALU));
809 I->eraseFromParent();
814 if (I == MBB.
begin()) {
818 switch (I->getOpcode()) {
822 case AMDGPU::JUMP_COND: {
825 I->eraseFromParent();
827 if (CfAlu == MBB.
end())
829 assert (CfAlu->getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE);
830 CfAlu->setDesc(
get(AMDGPU::CF_ALU));
834 I->eraseFromParent();
847 default:
return false;
848 case AMDGPU::PRED_SEL_ONE:
849 case AMDGPU::PRED_SEL_ZERO:
850 case AMDGPU::PREDICATE_BIT:
863 }
else if (MI.
getOpcode() == AMDGPU::CF_ALU) {
873 return AMDGPUInstrInfo::isPredicable(MI);
881 unsigned ExtraPredCycles,
889 unsigned ExtraTCycles,
892 unsigned ExtraFCycles,
916 case AMDGPU::PRED_SETE_INT:
917 MO.
setImm(AMDGPU::PRED_SETNE_INT);
919 case AMDGPU::PRED_SETNE_INT:
920 MO.
setImm(AMDGPU::PRED_SETE_INT);
922 case AMDGPU::PRED_SETE:
923 MO.
setImm(AMDGPU::PRED_SETNE);
925 case AMDGPU::PRED_SETNE:
926 MO.
setImm(AMDGPU::PRED_SETE);
934 case AMDGPU::PRED_SEL_ZERO:
935 MO2.
setReg(AMDGPU::PRED_SEL_ONE);
937 case AMDGPU::PRED_SEL_ONE:
938 MO2.
setReg(AMDGPU::PRED_SEL_ZERO);
947 std::vector<MachineOperand> &Pred)
const {
992 unsigned *PredCost)
const {
999 unsigned Channel)
const {
1012 int RegOpIdx = OffsetOpIdx + 1;
1022 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1036 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
1051 case AMDGPU::R600_EXTRACT_ELT_V2:
1052 case AMDGPU::R600_EXTRACT_ELT_V4:
1058 case AMDGPU::R600_INSERT_ELT_V2:
1059 case AMDGPU::R600_INSERT_ELT_V4:
1082 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
1083 Reserved.
set(SuperReg);
1084 for (
unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1085 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1092 return &AMDGPU::R600_TReg32_XRegClass;
1097 unsigned ValueReg,
unsigned Address,
1098 unsigned OffsetReg)
const {
1099 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1104 unsigned ValueReg,
unsigned Address,
1106 unsigned AddrChan)
const {
1110 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
break;
1111 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address);
break;
1112 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address);
break;
1113 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address);
break;
1116 AMDGPU::AR_X, OffsetReg);
1129 unsigned ValueReg,
unsigned Address,
1130 unsigned OffsetReg)
const {
1131 return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1136 unsigned ValueReg,
unsigned Address,
1138 unsigned AddrChan)
const {
1142 case 0: AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
break;
1143 case 1: AddrReg = AMDGPU::R600_Addr_YRegClass.getRegister(Address);
break;
1144 case 2: AddrReg = AMDGPU::R600_Addr_ZRegClass.getRegister(Address);
break;
1145 case 3: AddrReg = AMDGPU::R600_Addr_WRegClass.getRegister(Address);
break;
1178 unsigned Reg = LI->first;
1185 for (RegIndex = 0, RegEnd = IndirectRC->
getNumRegs(); RegIndex != RegEnd;
1190 Offset = std::max(Offset, (
int)RegIndex);
1212 unsigned IgnoredFrameReg;
1227 unsigned Src1Reg)
const {
1256 .
addReg(AMDGPU::PRED_SEL_OFF)
1263 #define OPERAND_CASE(Label) \
1265 static const unsigned Ops[] = \
1307 Opcode = AMDGPU::DOT4_r600;
1309 Opcode = AMDGPU::DOT4_eg;
1317 static const unsigned Operands[14] = {
1318 AMDGPU::OpName::update_exec_mask,
1319 AMDGPU::OpName::update_pred,
1321 AMDGPU::OpName::omod,
1322 AMDGPU::OpName::dst_rel,
1323 AMDGPU::OpName::clamp,
1324 AMDGPU::OpName::src0_neg,
1325 AMDGPU::OpName::src0_rel,
1326 AMDGPU::OpName::src0_abs,
1327 AMDGPU::OpName::src0_sel,
1328 AMDGPU::OpName::src1_neg,
1329 AMDGPU::OpName::src1_rel,
1330 AMDGPU::OpName::src1_abs,
1331 AMDGPU::OpName::src1_sel,
1339 for (
unsigned i = 0; i < 14; i++) {
1352 uint64_t Imm)
const {
1354 AMDGPU::ALU_LITERAL_X);
1361 unsigned DstReg,
unsigned SrcReg)
const {
1374 int64_t Imm)
const {
1376 assert(Idx != -1 &&
"Operand not supported for this instruction.");
1386 unsigned Flag)
const {
1421 assert(!IsOP3 &&
"Cannot set absolute value modifier for OP3 "
1438 assert(FlagIndex != -1 &&
"Flag not supported for this instruction");
1442 "Instruction flags not supported for this instruction");
1451 unsigned Flag)
const {
1472 unsigned Flag)
const {
1479 unsigned InstFlags = FlagOp.
getImm();
1481 FlagOp.
setImm(InstFlags);
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
int getIndirectIndexEnd(const MachineFunction &MF) const
bool hasCaymanISA() const
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
mop_iterator operands_end()
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
unsigned int getPredicationCost(const MachineInstr &) const override
bool isLDSInstr(unsigned Opcode) const
AMDGPU specific subclass of TargetSubtarget.
bool hasVertexCache() const
unsigned getRegister(unsigned i) const
Return the specified register in the class.
livein_iterator livein_end() const
Interface definition for R600InstrInfo.
MachineBasicBlock * getMBB() const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getNumObjects() const
Return the number of objects.
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isPredicated(const MachineInstr &MI) const override
static unsigned getSlotedOps(unsigned Op, unsigned Slot)
static bool isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, const std::vector< std::pair< int, unsigned > > &TransOps, unsigned ConstCount)
Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr ...
MachineInstrBundleIterator< MachineInstr > iterator
bool expandPostRAPseudo(MachineInstr &MI) const override
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Interface definition for R600RegisterInfo.
bool isVectorOnly(unsigned Opcode) const
return AArch64::GPR64RegClass contains(Reg)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool isCubeOp(unsigned opcode) const
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
static MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op)
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
R600InstrInfo(const R600Subtarget &)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, BranchProbability Probability) const override
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
#define HAS_NATIVE_OPERANDS(Flags)
bool hasInstrModifiers(unsigned Opcode) const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
static bool isJump(unsigned Opcode)
bool usesVertexCache(unsigned Opcode) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
bool usesTextureCache(unsigned Opcode) const
Generation getGeneration() const
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
bool isExport(unsigned Opcode) const
const R600FrameLowering * getFrameLowering() const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
unsigned const MachineRegisterInfo * MRI
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubRegFromChannel(unsigned Channel) const
bool isCompute(CallingConv::ID cc)
const TargetRegisterClass * getIndirectAddrRegClass() const
static const unsigned End
void setImm(int64_t immVal)
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
static MachineInstr * findFirstPredicateSetterFrom(MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
bool empty() const
empty - Check if the array is empty.
The AMDGPU TargetMachine interface definition for hw codgen targets.
static void write(bool isBE, void *P, T V)
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
unsigned getHWRegIndex(unsigned Reg) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setIsKill(bool Val=true)
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
bool readsLDSSrcReg(const MachineInstr &MI) const
static bool NextPossibleSolution(std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, unsigned Idx)
Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swiz...
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
#define OPERAND_CASE(Label)
livein_iterator livein_begin() const
unsigned getStackWidth(const MachineFunction &MF) const
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
bool canBeConsideredALU(const MachineInstr &MI) const
bool mustBeLastInClause(unsigned Opcode) const
static bool isPredicateSetter(unsigned Opcode)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
unsigned getNumRegs() const
Return the number of registers in this class.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const
Reserve the registers that may be accesed using indirect addressing.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool definesAddressRegister(MachineInstr &MI) const
#define GET_FLAG_OPERAND_IDX(Flags)
Helper for getting the operand index for the instruction flags operand.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isPredicable(MachineInstr &MI) const override
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
iterator find(const KeyT &Val)
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool isRegisterLoad(const MachineInstr &MI) const
bool usesAddressRegister(MachineInstr &MI) const
unsigned getMaxAlusPerClause() const
bool isReductionOp(unsigned opcode) const
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
unsigned getReg() const
getReg - Returns the register number.
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
mop_iterator operands_begin()
bool livein_empty() const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
#define GET_REG_INDEX(reg)
bool isMov(unsigned Opcode) const
int getIndirectIndexBegin(const MachineFunction &MF) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, BranchProbability Probability) const override
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
bool isRegisterStore(const MachineInstr &MI) const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
bool isLDSRetInstr(unsigned Opcode) const
bool isALUInstr(unsigned Opcode) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isTransOnly(unsigned Opcode) const
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.