LLVM  4.0.0
HexagonFrameLowering.h
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1 //=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
12 
13 #include "Hexagon.h"
14 #include "HexagonBlockRanges.h"
15 #include "llvm/ADT/STLExtras.h"
19 #include <vector>
20 
21 namespace llvm {
22 
23 class HexagonInstrInfo;
24 class HexagonRegisterInfo;
25 
27 public:
30 
31  // All of the prolog/epilog functionality, including saving and restoring
32  // callee-saved registers is handled in emitPrologue. This is to have the
33  // logic for shrink-wrapping in one place.
35  override;
37  override {}
38 
40  MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
41  const TargetRegisterInfo *TRI) const override {
42  return true;
43  }
44 
46  MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
47  const TargetRegisterInfo *TRI) const override {
48  return true;
49  }
50 
53  MachineBasicBlock::iterator I) const override;
55  RegScavenger *RS = nullptr) const override;
56  void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
57  RegScavenger *RS) const override;
58 
59  bool targetHandlesStackFrameRounding() const override {
60  return true;
61  }
62 
63  int getFrameIndexReference(const MachineFunction &MF, int FI,
64  unsigned &FrameReg) const override;
65  bool hasFP(const MachineFunction &MF) const override;
66 
67  const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
68  const override {
69  static const SpillSlot Offsets[] = {
70  { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
71  { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
72  { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
73  { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
74  { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
75  { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
76  };
77  NumEntries = array_lengthof(Offsets);
78  return Offsets;
79  }
80 
82  const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
83  const override;
84 
85  bool needsAligna(const MachineFunction &MF) const;
86  const MachineInstr *getAlignaInstr(const MachineFunction &MF) const;
87 
88  void insertCFIInstructions(MachineFunction &MF) const;
89 
90 private:
91  typedef std::vector<CalleeSavedInfo> CSIVect;
92 
93  void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
94  unsigned SP, unsigned CF) const;
95  void insertPrologueInBlock(MachineBasicBlock &MBB, bool PrologueStubs) const;
96  void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
97  bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
98  const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
99  bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
100  const HexagonRegisterInfo &HRI) const;
101  void updateEntryPaths(MachineFunction &MF, MachineBasicBlock &SaveB) const;
102  bool updateExitPaths(MachineBasicBlock &MBB, MachineBasicBlock &RestoreB,
103  BitVector &DoneT, BitVector &DoneF, BitVector &Path) const;
104  void insertCFIInstructionsAt(MachineBasicBlock &MBB,
105  MachineBasicBlock::iterator At) const;
106 
107  void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
108 
109  bool expandCopy(MachineBasicBlock &B, MachineBasicBlock::iterator It,
111  SmallVectorImpl<unsigned> &NewRegs) const;
112  bool expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
114  SmallVectorImpl<unsigned> &NewRegs) const;
115  bool expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It,
117  SmallVectorImpl<unsigned> &NewRegs) const;
118  bool expandStoreVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
120  SmallVectorImpl<unsigned> &NewRegs) const;
121  bool expandLoadVecPred(MachineBasicBlock &B, MachineBasicBlock::iterator It,
123  SmallVectorImpl<unsigned> &NewRegs) const;
124  bool expandStoreVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
126  SmallVectorImpl<unsigned> &NewRegs) const;
127  bool expandLoadVec2(MachineBasicBlock &B, MachineBasicBlock::iterator It,
129  SmallVectorImpl<unsigned> &NewRegs) const;
130  bool expandStoreVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
132  SmallVectorImpl<unsigned> &NewRegs) const;
133  bool expandLoadVec(MachineBasicBlock &B, MachineBasicBlock::iterator It,
135  SmallVectorImpl<unsigned> &NewRegs) const;
136  bool expandSpillMacros(MachineFunction &MF,
137  SmallVectorImpl<unsigned> &NewRegs) const;
138 
139  unsigned findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
142  const TargetRegisterClass *RC) const;
143  void optimizeSpillSlots(MachineFunction &MF,
145 
146  void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
147  MachineBasicBlock *&EpilogB) const;
148 
149  void addCalleeSaveRegistersAsImpOperand(MachineInstr *MI, const CSIVect &CSI,
150  bool IsDef, bool IsKill) const;
151  bool shouldInlineCSR(MachineFunction &MF, const CSIVect &CSI) const;
152  bool useSpillFunction(MachineFunction &MF, const CSIVect &CSI) const;
153  bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const;
154  bool mayOverflowFrameOffset(MachineFunction &MF) const;
155 };
156 
157 } // end namespace llvm
158 
159 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:777
static const MCPhysReg VRegs[32]
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
const HexagonInstrInfo * TII
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
MachineBasicBlock * MBB
bool needsAligna(const MachineFunction &MF) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Perform most of the PEI work here:
unsigned const MachineRegisterInfo * MRI
void insertCFIInstructions(MachineFunction &MF) const
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
Information about stack frame layout on the target.
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
Basic Alias true
std::map< RegisterRef, RangeList > RegToRangeMap
#define I(x, y, z)
Definition: MD5.cpp:54
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool targetHandlesStackFrameRounding() const override
targetHandlesStackFrameRounding - Returns true if the target is responsible for rounding up the stack...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
IRTranslator LLVM IR MI
const MachineInstr * getAlignaInstr(const MachineFunction &MF) const