LLVM  4.0.0
AArch64TargetMachine.cpp
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1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64.h"
14 #include "AArch64CallLowering.h"
16 #include "AArch64LegalizerInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/Triple.h"
32 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
37 #include "llvm/Pass.h"
38 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Transforms/Scalar.h"
44 #include <memory>
45 #include <string>
46 
47 using namespace llvm;
48 
49 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
50  cl::desc("Enable the CCMP formation pass"),
51  cl::init(true), cl::Hidden);
52 
53 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
54  cl::desc("Enable the machine combiner pass"),
55  cl::init(true), cl::Hidden);
56 
57 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
58  cl::desc("Suppress STP for AArch64"),
59  cl::init(true), cl::Hidden);
60 
62  "aarch64-enable-simd-scalar",
63  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
64  cl::init(false), cl::Hidden);
65 
66 static cl::opt<bool>
67  EnablePromoteConstant("aarch64-enable-promote-const",
68  cl::desc("Enable the promote constant pass"),
69  cl::init(true), cl::Hidden);
70 
72  "aarch64-enable-collect-loh",
73  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
74  cl::init(true), cl::Hidden);
75 
76 static cl::opt<bool>
77  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
78  cl::desc("Enable the pass that removes dead"
79  " definitons and replaces stores to"
80  " them with stores to the zero"
81  " register"),
82  cl::init(true));
83 
85  "aarch64-enable-copyelim",
86  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
87  cl::Hidden);
88 
89 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
90  cl::desc("Enable the load/store pair"
91  " optimization pass"),
92  cl::init(true), cl::Hidden);
93 
95  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
96  cl::desc("Run SimplifyCFG after expanding atomic operations"
97  " to make use of cmpxchg flow-based information"),
98  cl::init(true));
99 
100 static cl::opt<bool>
101 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
102  cl::desc("Run early if-conversion"),
103  cl::init(true));
104 
105 static cl::opt<bool>
106  EnableCondOpt("aarch64-enable-condopt",
107  cl::desc("Enable the condition optimizer pass"),
108  cl::init(true), cl::Hidden);
109 
110 static cl::opt<bool>
111 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
112  cl::desc("Work around Cortex-A53 erratum 835769"),
113  cl::init(false));
114 
115 static cl::opt<bool>
116  EnableAddressTypePromotion("aarch64-enable-type-promotion", cl::Hidden,
117  cl::desc("Enable the type promotion pass"),
118  cl::init(true));
119 
120 static cl::opt<bool>
121  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
122  cl::desc("Enable optimizations on complex GEPs"),
123  cl::init(false));
124 
125 static cl::opt<bool>
126  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
127  cl::desc("Relax out of range conditional branches"));
128 
129 // FIXME: Unify control over GlobalMerge.
131  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
132  cl::desc("Enable the global merge pass"));
133 
134 static cl::opt<bool>
135  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
136  cl::desc("Enable the loop data prefetch pass"),
137  cl::init(true));
138 
139 extern "C" void LLVMInitializeAArch64Target() {
140  // Register the target.
144  auto PR = PassRegistry::getPassRegistry();
161 }
162 
163 //===----------------------------------------------------------------------===//
164 // AArch64 Lowering public interface.
165 //===----------------------------------------------------------------------===//
166 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
167  if (TT.isOSBinFormatMachO())
168  return llvm::make_unique<AArch64_MachoTargetObjectFile>();
169 
170  return llvm::make_unique<AArch64_ELFTargetObjectFile>();
171 }
172 
173 // Helper function to build a DataLayout string
174 static std::string computeDataLayout(const Triple &TT,
175  const MCTargetOptions &Options,
176  bool LittleEndian) {
177  if (Options.getABIName() == "ilp32")
178  return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
179  if (TT.isOSBinFormatMachO())
180  return "e-m:o-i64:64-i128:128-n32:64-S128";
181  if (LittleEndian)
182  return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
183  return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
184 }
185 
188  // AArch64 Darwin is always PIC.
189  if (TT.isOSDarwin())
190  return Reloc::PIC_;
191  // On ELF platforms the default static relocation model has a smart enough
192  // linker to cope with referencing external symbols defined in a shared
193  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
194  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
195  return Reloc::Static;
196  return *RM;
197 }
198 
199 /// Create an AArch64 architecture model.
200 ///
202  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
203  const TargetOptions &Options, Optional<Reloc::Model> RM,
204  CodeModel::Model CM, CodeGenOpt::Level OL, bool LittleEndian)
205  // This nested ternary is horrible, but DL needs to be properly
206  // initialized before TLInfo is constructed.
207  : LLVMTargetMachine(T, computeDataLayout(TT, Options.MCOptions,
208  LittleEndian),
209  TT, CPU, FS, Options,
210  getEffectiveRelocModel(TT, RM), CM, OL),
211  TLOF(createTLOF(getTargetTriple())),
212  isLittle(LittleEndian) {
213  initAsmInfo();
214 }
215 
217 
218 #ifdef LLVM_BUILD_GLOBAL_ISEL
219 namespace {
220 
221 struct AArch64GISelActualAccessor : public GISelAccessor {
222  std::unique_ptr<CallLowering> CallLoweringInfo;
223  std::unique_ptr<InstructionSelector> InstSelector;
224  std::unique_ptr<LegalizerInfo> Legalizer;
225  std::unique_ptr<RegisterBankInfo> RegBankInfo;
226 
227  const CallLowering *getCallLowering() const override {
228  return CallLoweringInfo.get();
229  }
230 
231  const InstructionSelector *getInstructionSelector() const override {
232  return InstSelector.get();
233  }
234 
235  const LegalizerInfo *getLegalizerInfo() const override {
236  return Legalizer.get();
237  }
238 
239  const RegisterBankInfo *getRegBankInfo() const override {
240  return RegBankInfo.get();
241  }
242 };
243 
244 } // end anonymous namespace
245 #endif
246 
247 const AArch64Subtarget *
249  Attribute CPUAttr = F.getFnAttribute("target-cpu");
250  Attribute FSAttr = F.getFnAttribute("target-features");
251 
252  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
253  ? CPUAttr.getValueAsString().str()
254  : TargetCPU;
255  std::string FS = !FSAttr.hasAttribute(Attribute::None)
256  ? FSAttr.getValueAsString().str()
257  : TargetFS;
258 
259  auto &I = SubtargetMap[CPU + FS];
260  if (!I) {
261  // This needs to be done before we create a new subtarget since any
262  // creation will depend on the TM and the code generation flags on the
263  // function that reside in TargetOptions.
265  I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
266  isLittle);
267 #ifndef LLVM_BUILD_GLOBAL_ISEL
268  GISelAccessor *GISel = new GISelAccessor();
269 #else
270  AArch64GISelActualAccessor *GISel =
271  new AArch64GISelActualAccessor();
272  GISel->CallLoweringInfo.reset(
273  new AArch64CallLowering(*I->getTargetLowering()));
274  GISel->Legalizer.reset(new AArch64LegalizerInfo());
275 
276  auto *RBI = new AArch64RegisterBankInfo(*I->getRegisterInfo());
277 
278  // FIXME: At this point, we can't rely on Subtarget having RBI.
279  // It's awkward to mix passing RBI and the Subtarget; should we pass
280  // TII/TRI as well?
281  GISel->InstSelector.reset(new AArch64InstructionSelector(*this, *I, *RBI));
282 
283  GISel->RegBankInfo.reset(RBI);
284 #endif
285  I->setGISelAccessor(*GISel);
286  }
287  return I.get();
288 }
289 
290 void AArch64leTargetMachine::anchor() { }
291 
293  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
294  const TargetOptions &Options, Optional<Reloc::Model> RM,
296  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
297 
298 void AArch64beTargetMachine::anchor() { }
299 
301  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
302  const TargetOptions &Options, Optional<Reloc::Model> RM,
304  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
305 
306 namespace {
307 
308 /// AArch64 Code Generator Pass Configuration Options.
309 class AArch64PassConfig : public TargetPassConfig {
310 public:
311  AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
312  : TargetPassConfig(TM, PM) {
313  if (TM->getOptLevel() != CodeGenOpt::None)
314  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
315  }
316 
317  AArch64TargetMachine &getAArch64TargetMachine() const {
318  return getTM<AArch64TargetMachine>();
319  }
320 
322  createMachineScheduler(MachineSchedContext *C) const override {
327  return DAG;
328  }
329 
330  void addIRPasses() override;
331  bool addPreISel() override;
332  bool addInstSelector() override;
333 #ifdef LLVM_BUILD_GLOBAL_ISEL
334  bool addIRTranslator() override;
335  bool addLegalizeMachineIR() override;
336  bool addRegBankSelect() override;
337  bool addGlobalInstructionSelect() override;
338 #endif
339  bool addILPOpts() override;
340  void addPreRegAlloc() override;
341  void addPostRegAlloc() override;
342  void addPreSched2() override;
343  void addPreEmitPass() override;
344 };
345 
346 } // end anonymous namespace
347 
349  return TargetIRAnalysis([this](const Function &F) {
350  return TargetTransformInfo(AArch64TTIImpl(this, F));
351  });
352 }
353 
355  return new AArch64PassConfig(this, PM);
356 }
357 
358 void AArch64PassConfig::addIRPasses() {
359  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
360  // ourselves.
361  addPass(createAtomicExpandPass(TM));
362 
363  // Cmpxchg instructions are often used with a subsequent comparison to
364  // determine whether it succeeded. We can exploit existing control-flow in
365  // ldrex/strex loops to simplify this, but it needs tidying up.
367  addPass(createCFGSimplificationPass());
368 
369  // Run LoopDataPrefetch
370  //
371  // Run this before LSR to remove the multiplies involved in computing the
372  // pointer values N iterations ahead.
374  addPass(createLoopDataPrefetchPass());
375 
377 
378  // Match interleaved memory accesses to ldN/stN intrinsics.
379  if (TM->getOptLevel() != CodeGenOpt::None)
380  addPass(createInterleavedAccessPass(TM));
381 
383  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
384  // and lower a GEP with multiple indices to either arithmetic operations or
385  // multiple GEPs with single index.
386  addPass(createSeparateConstOffsetFromGEPPass(TM, true));
387  // Call EarlyCSE pass to find and remove subexpressions in the lowered
388  // result.
389  addPass(createEarlyCSEPass());
390  // Do loop invariant code motion in case part of the lowered result is
391  // invariant.
392  addPass(createLICMPass());
393  }
394 }
395 
396 // Pass Pipeline Configuration
397 bool AArch64PassConfig::addPreISel() {
398  // Run promote constant before global merge, so that the promoted constants
399  // get a chance to be merged
402  // FIXME: On AArch64, this depends on the type.
403  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
404  // and the offset has to be a multiple of the related size in bytes.
405  if ((TM->getOptLevel() != CodeGenOpt::None &&
407  EnableGlobalMerge == cl::BOU_TRUE) {
408  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
409  (EnableGlobalMerge == cl::BOU_UNSET);
410  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
411  }
412 
415 
416  return false;
417 }
418 
419 bool AArch64PassConfig::addInstSelector() {
420  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
421 
422  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
423  // references to _TLS_MODULE_BASE_ as possible.
424  if (TM->getTargetTriple().isOSBinFormatELF() &&
425  getOptLevel() != CodeGenOpt::None)
427 
428  return false;
429 }
430 
431 #ifdef LLVM_BUILD_GLOBAL_ISEL
432 bool AArch64PassConfig::addIRTranslator() {
433  addPass(new IRTranslator());
434  return false;
435 }
436 
437 bool AArch64PassConfig::addLegalizeMachineIR() {
438  addPass(new Legalizer());
439  return false;
440 }
441 
442 bool AArch64PassConfig::addRegBankSelect() {
443  addPass(new RegBankSelect());
444  return false;
445 }
446 
447 bool AArch64PassConfig::addGlobalInstructionSelect() {
448  addPass(new InstructionSelect());
449  return false;
450 }
451 #endif
452 
453 bool AArch64PassConfig::addILPOpts() {
454  if (EnableCondOpt)
456  if (EnableCCMP)
458  if (EnableMCR)
459  addPass(&MachineCombinerID);
461  addPass(&EarlyIfConverterID);
465  return true;
466 }
467 
468 void AArch64PassConfig::addPreRegAlloc() {
469  // Change dead register definitions to refer to the zero register.
472 
473  // Use AdvSIMD scalar instructions whenever profitable.
475  addPass(createAArch64AdvSIMDScalar());
476  // The AdvSIMD pass may produce copies that can be rewritten to
477  // be register coaleascer friendly.
478  addPass(&PeepholeOptimizerID);
479  }
480 }
481 
482 void AArch64PassConfig::addPostRegAlloc() {
483  // Remove redundant copy instructions.
486 
487  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
488  // Improve performance for some FP/SIMD code for A57.
490 }
491 
492 void AArch64PassConfig::addPreSched2() {
493  // Expand some pseudo instructions to allow proper scheduling.
495  // Use load/store pair instructions when possible.
498 }
499 
500 void AArch64PassConfig::addPreEmitPass() {
501  if (EnableA53Fix835769)
502  addPass(createAArch64A53Fix835769());
503  // Relax conditional branch instructions if they're otherwise out of
504  // range of their destination.
505  if (BranchRelaxation)
506  addPass(&BranchRelaxationPassID);
507 
510  addPass(createAArch64CollectLOHPass());
511 }
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
Definition: GISelAccessor.h:29
Target & getTheAArch64beTarget()
static cl::opt< bool > EnableAddressTypePromotion("aarch64-enable-type-promotion", cl::Hidden, cl::desc("Enable the type promotion pass"), cl::init(true))
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:575
void initializeAArch64A53Fix835769Pass(PassRegistry &)
bool hasValue() const
Definition: Optional.h:125
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
const AArch64Subtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
void initializeAArch64LoadStoreOptPass(PassRegistry &)
Target & getTheAArch64leTarget()
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
Analysis pass providing the TargetTransformInfo.
This class provides the information for the target register banks.
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:234
FunctionPass * createAArch64ConditionalCompares()
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool IsLittleEndian)
Create an AArch64 architecture model.
ModulePass * createAArch64PromoteConstantPass()
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:185
FunctionPass * createAArch64AddressTypePromotionPass()
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createLoopDataPrefetchPass()
const Triple & getTargetTriple() const
This file declares the targeting of the RegisterBankInfo class for AArch64.
FunctionPass * createAArch64CollectLOHPass()
Holds all the information related to register banks.
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
FunctionPass * createAArch64VectorByElementOptPass()
createAArch64VectorByElementOptPass - returns an instance of the vector by element optimization pass...
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
void initializeGlobalISel(PassRegistry &Registry)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:21
void initializeLDTLSCleanupPass(PassRegistry &)
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:69
FunctionPass * createAArch64RedundantCopyEliminationPass()
Target & getTheARM64Target()
void initializeAArch64CollectLOHPass(PassRegistry &)
Target-Independent Code Generator Pass Configuration Options.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
#define F(x, y, z)
Definition: MD5.cpp:51
FunctionPass * createAArch64A57FPLoadBalancing()
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
This file declares the targeting of the Machinelegalizer class for AArch64.
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
Function Alias Analysis false
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead"" definitons and replaces stores to"" them with stores to the zero"" register"), cl::init(true))
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(const TargetInstrInfo *TII)
FunctionPass * createInterleavedAccessPass(const TargetMachine *TM)
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
void initializeAArch64PromoteConstantPass(PassRegistry &)
FunctionPass * createSeparateConstOffsetFromGEPPass(const TargetMachine *TM=nullptr, bool LowerGEP=false)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:83
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
void LLVMInitializeAArch64Target()
void initializeAArch64VectorByElementOptPass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(int Threshold=-1, std::function< bool(const Function &)> Ftor=nullptr)
Pass * createLICMPass()
Definition: LICM.cpp:217
FunctionPass * createAArch64AdvSIMDScalar()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:225
This file declares the targeting of the InstructionSelector class for AArch64.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:455
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden, cl::desc("Work around Cortex-A53 erratum 835769"), cl::init(false))
void initializeAArch64AddressTypePromotionPass(PassRegistry &)
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
FunctionPass * createAArch64A53Fix835769()
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
This pass is responsible for selecting generic machine instructions to target-specific instructions...
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Target - Wrapper for Target specific information.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
FunctionPass * createAArch64ConditionOptimizerPass()
TargetIRAnalysis getTargetIRAnalysis() override
Get the TargetIRAnalysis for this target.
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG...
Provides the logic to select generic machine instructions.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
Basic Alias true
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations"" to make use of cmpxchg flow-based information"), cl::init(true))
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
This class provides the information for the target register banks.
const TargetRegisterInfo * TRI
Definition: ScheduleDAG.h:580
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
FunctionPass * createAArch64StorePairSuppressPass()
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:54
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
This file describes how to lower LLVM calls to machine code calls.
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
const TargetInstrInfo * TII
Definition: ScheduleDAG.h:579
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair"" optimization pass"), cl::init(true), cl::Hidden)
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:178
This file declares the IRTranslator pass.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1050
FunctionPass * createAArch64DeadRegisterDefinitions()
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
This pass exposes codegen information to IR-level passes.
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
void initializeAArch64StorePairSuppressPass(PassRegistry &)