LLVM  4.0.0
AArch64TargetTransformInfo.cpp
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1 //===-- AArch64TargetTransformInfo.cpp - AArch64 specific TTI -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
13 #include "llvm/Analysis/LoopInfo.h"
15 #include "llvm/Support/Debug.h"
16 #include "llvm/Target/CostTable.h"
18 #include <algorithm>
19 using namespace llvm;
20 
21 #define DEBUG_TYPE "aarch64tti"
22 
23 /// \brief Calculate the cost of materializing a 64-bit value. This helper
24 /// method might only calculate a fraction of a larger immediate. Therefore it
25 /// is valid to return a cost of ZERO.
27  // Check if the immediate can be encoded within an instruction.
28  if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, 64))
29  return 0;
30 
31  if (Val < 0)
32  Val = ~Val;
33 
34  // Calculate how many moves we will need to materialize this constant.
35  unsigned LZ = countLeadingZeros((uint64_t)Val);
36  return (64 - LZ + 15) / 16;
37 }
38 
39 /// \brief Calculate the cost of materializing the given constant.
41  assert(Ty->isIntegerTy());
42 
43  unsigned BitSize = Ty->getPrimitiveSizeInBits();
44  if (BitSize == 0)
45  return ~0U;
46 
47  // Sign-extend all constants to a multiple of 64-bit.
48  APInt ImmVal = Imm;
49  if (BitSize & 0x3f)
50  ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
51 
52  // Split the constant into 64-bit chunks and calculate the cost for each
53  // chunk.
54  int Cost = 0;
55  for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
56  APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
57  int64_t Val = Tmp.getSExtValue();
58  Cost += getIntImmCost(Val);
59  }
60  // We need at least one instruction to materialze the constant.
61  return std::max(1, Cost);
62 }
63 
64 int AArch64TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx,
65  const APInt &Imm, Type *Ty) {
66  assert(Ty->isIntegerTy());
67 
68  unsigned BitSize = Ty->getPrimitiveSizeInBits();
69  // There is no cost model for constants with a bit size of 0. Return TCC_Free
70  // here, so that constant hoisting will ignore this constant.
71  if (BitSize == 0)
72  return TTI::TCC_Free;
73 
74  unsigned ImmIdx = ~0U;
75  switch (Opcode) {
76  default:
77  return TTI::TCC_Free;
78  case Instruction::GetElementPtr:
79  // Always hoist the base address of a GetElementPtr.
80  if (Idx == 0)
81  return 2 * TTI::TCC_Basic;
82  return TTI::TCC_Free;
83  case Instruction::Store:
84  ImmIdx = 0;
85  break;
86  case Instruction::Add:
87  case Instruction::Sub:
88  case Instruction::Mul:
89  case Instruction::UDiv:
90  case Instruction::SDiv:
91  case Instruction::URem:
92  case Instruction::SRem:
93  case Instruction::And:
94  case Instruction::Or:
95  case Instruction::Xor:
96  case Instruction::ICmp:
97  ImmIdx = 1;
98  break;
99  // Always return TCC_Free for the shift value of a shift instruction.
100  case Instruction::Shl:
101  case Instruction::LShr:
102  case Instruction::AShr:
103  if (Idx == 1)
104  return TTI::TCC_Free;
105  break;
106  case Instruction::Trunc:
107  case Instruction::ZExt:
108  case Instruction::SExt:
109  case Instruction::IntToPtr:
110  case Instruction::PtrToInt:
111  case Instruction::BitCast:
112  case Instruction::PHI:
113  case Instruction::Call:
114  case Instruction::Select:
115  case Instruction::Ret:
116  case Instruction::Load:
117  break;
118  }
119 
120  if (Idx == ImmIdx) {
121  int NumConstants = (BitSize + 63) / 64;
122  int Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
123  return (Cost <= NumConstants * TTI::TCC_Basic)
124  ? static_cast<int>(TTI::TCC_Free)
125  : Cost;
126  }
127  return AArch64TTIImpl::getIntImmCost(Imm, Ty);
128 }
129 
131  const APInt &Imm, Type *Ty) {
132  assert(Ty->isIntegerTy());
133 
134  unsigned BitSize = Ty->getPrimitiveSizeInBits();
135  // There is no cost model for constants with a bit size of 0. Return TCC_Free
136  // here, so that constant hoisting will ignore this constant.
137  if (BitSize == 0)
138  return TTI::TCC_Free;
139 
140  switch (IID) {
141  default:
142  return TTI::TCC_Free;
143  case Intrinsic::sadd_with_overflow:
144  case Intrinsic::uadd_with_overflow:
145  case Intrinsic::ssub_with_overflow:
146  case Intrinsic::usub_with_overflow:
147  case Intrinsic::smul_with_overflow:
148  case Intrinsic::umul_with_overflow:
149  if (Idx == 1) {
150  int NumConstants = (BitSize + 63) / 64;
151  int Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
152  return (Cost <= NumConstants * TTI::TCC_Basic)
153  ? static_cast<int>(TTI::TCC_Free)
154  : Cost;
155  }
156  break;
157  case Intrinsic::experimental_stackmap:
158  if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
159  return TTI::TCC_Free;
160  break;
161  case Intrinsic::experimental_patchpoint_void:
162  case Intrinsic::experimental_patchpoint_i64:
163  if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
164  return TTI::TCC_Free;
165  break;
166  }
167  return AArch64TTIImpl::getIntImmCost(Imm, Ty);
168 }
169 
172  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
173  if (TyWidth == 32 || TyWidth == 64)
174  return TTI::PSK_FastHardware;
175  // TODO: AArch64TargetLowering::LowerCTPOP() supports 128bit popcount.
176  return TTI::PSK_Software;
177 }
178 
179 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
180  int ISD = TLI->InstructionOpcodeToISD(Opcode);
181  assert(ISD && "Invalid opcode");
182 
183  EVT SrcTy = TLI->getValueType(DL, Src);
184  EVT DstTy = TLI->getValueType(DL, Dst);
185 
186  if (!SrcTy.isSimple() || !DstTy.isSimple())
187  return BaseT::getCastInstrCost(Opcode, Dst, Src);
188 
189  static const TypeConversionCostTblEntry
190  ConversionTbl[] = {
195 
196  // The number of shll instructions for the extension.
213 
214  // LowerVectorINT_TO_FP:
221 
222  // Complex: to v2f32
229 
230  // Complex: to v4f32
235 
236  // Complex: to v8f32
241 
242  // Complex: to v16f32
245 
246  // Complex: to v2f64
253 
254 
255  // LowerVectorFP_TO_INT
262 
263  // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
270 
271  // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
276 
277  // Complex, from v2f64: legal type is v2i32, 1 narrowing => ~2.
284  };
285 
286  if (const auto *Entry = ConvertCostTableLookup(ConversionTbl, ISD,
287  DstTy.getSimpleVT(),
288  SrcTy.getSimpleVT()))
289  return Entry->Cost;
290 
291  return BaseT::getCastInstrCost(Opcode, Dst, Src);
292 }
293 
295  VectorType *VecTy,
296  unsigned Index) {
297 
298  // Make sure we were given a valid extend opcode.
299  assert((Opcode == Instruction::SExt || Opcode == Instruction::ZExt) &&
300  "Invalid opcode");
301 
302  // We are extending an element we extract from a vector, so the source type
303  // of the extend is the element type of the vector.
304  auto *Src = VecTy->getElementType();
305 
306  // Sign- and zero-extends are for integer types only.
307  assert(isa<IntegerType>(Dst) && isa<IntegerType>(Src) && "Invalid type");
308 
309  // Get the cost for the extract. We compute the cost (if any) for the extend
310  // below.
311  auto Cost = getVectorInstrCost(Instruction::ExtractElement, VecTy, Index);
312 
313  // Legalize the types.
314  auto VecLT = TLI->getTypeLegalizationCost(DL, VecTy);
315  auto DstVT = TLI->getValueType(DL, Dst);
316  auto SrcVT = TLI->getValueType(DL, Src);
317 
318  // If the resulting type is still a vector and the destination type is legal,
319  // we may get the extension for free. If not, get the default cost for the
320  // extend.
321  if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT))
322  return Cost + getCastInstrCost(Opcode, Dst, Src);
323 
324  // The destination type should be larger than the element type. If not, get
325  // the default cost for the extend.
326  if (DstVT.getSizeInBits() < SrcVT.getSizeInBits())
327  return Cost + getCastInstrCost(Opcode, Dst, Src);
328 
329  switch (Opcode) {
330  default:
331  llvm_unreachable("Opcode should be either SExt or ZExt");
332 
333  // For sign-extends, we only need a smov, which performs the extension
334  // automatically.
335  case Instruction::SExt:
336  return Cost;
337 
338  // For zero-extends, the extend is performed automatically by a umov unless
339  // the destination type is i64 and the element type is i8 or i16.
340  case Instruction::ZExt:
341  if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u)
342  return Cost;
343  }
344 
345  // If we are unable to perform the extend for free, get the default cost.
346  return Cost + getCastInstrCost(Opcode, Dst, Src);
347 }
348 
349 int AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
350  unsigned Index) {
351  assert(Val->isVectorTy() && "This must be a vector type");
352 
353  if (Index != -1U) {
354  // Legalize the type.
355  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Val);
356 
357  // This type is legalized to a scalar type.
358  if (!LT.second.isVector())
359  return 0;
360 
361  // The type may be split. Normalize the index to the new type.
362  unsigned Width = LT.second.getVectorNumElements();
363  Index = Index % Width;
364 
365  // The element at index zero is already inside the vector.
366  if (Index == 0)
367  return 0;
368  }
369 
370  // All other insert/extracts cost this much.
371  return ST->getVectorInsertExtractBaseCost();
372 }
373 
375  unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
376  TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
378  // Legalize the type.
379  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
380 
381  int ISD = TLI->InstructionOpcodeToISD(Opcode);
382 
383  if (ISD == ISD::SDIV &&
385  Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
386  // On AArch64, scalar signed division by constants power-of-two are
387  // normally expanded to the sequence ADD + CMP + SELECT + SRA.
388  // The OperandValue properties many not be same as that of previous
389  // operation; conservatively assume OP_None.
390  int Cost = getArithmeticInstrCost(Instruction::Add, Ty, Opd1Info, Opd2Info,
393  Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Opd1Info, Opd2Info,
396  Cost += getArithmeticInstrCost(Instruction::Select, Ty, Opd1Info, Opd2Info,
399  Cost += getArithmeticInstrCost(Instruction::AShr, Ty, Opd1Info, Opd2Info,
402  return Cost;
403  }
404 
405  switch (ISD) {
406  default:
407  return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
408  Opd1PropInfo, Opd2PropInfo);
409  case ISD::ADD:
410  case ISD::MUL:
411  case ISD::XOR:
412  case ISD::OR:
413  case ISD::AND:
414  // These nodes are marked as 'custom' for combining purposes only.
415  // We know that they are legal. See LowerAdd in ISelLowering.
416  return 1 * LT.first;
417  }
418 }
419 
421  const SCEV *Ptr) {
422  // Address computations in vectorized code with non-consecutive addresses will
423  // likely result in more instructions compared to scalar code where the
424  // computation can more often be merged into the index mode. The resulting
425  // extra micro-ops can significantly decrease throughput.
426  unsigned NumVectorInstToHideOverhead = 10;
427  int MaxMergeDistance = 64;
428 
429  if (Ty->isVectorTy() && SE &&
430  !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1))
431  return NumVectorInstToHideOverhead;
432 
433  // In many cases the address computation is not merged into the instruction
434  // addressing mode.
435  return 1;
436 }
437 
438 int AArch64TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
439  Type *CondTy) {
440 
441  int ISD = TLI->InstructionOpcodeToISD(Opcode);
442  // We don't lower some vector selects well that are wider than the register
443  // width.
444  if (ValTy->isVectorTy() && ISD == ISD::SELECT) {
445  // We would need this many instructions to hide the scalarization happening.
446  const int AmortizationCost = 20;
447  static const TypeConversionCostTblEntry
448  VectorSelectTbl[] = {
452  { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
453  { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
454  { ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
455  };
456 
457  EVT SelCondTy = TLI->getValueType(DL, CondTy);
458  EVT SelValTy = TLI->getValueType(DL, ValTy);
459  if (SelCondTy.isSimple() && SelValTy.isSimple()) {
460  if (const auto *Entry = ConvertCostTableLookup(VectorSelectTbl, ISD,
461  SelCondTy.getSimpleVT(),
462  SelValTy.getSimpleVT()))
463  return Entry->Cost;
464  }
465  }
466  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
467 }
468 
469 int AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Ty,
470  unsigned Alignment, unsigned AddressSpace) {
471  auto LT = TLI->getTypeLegalizationCost(DL, Ty);
472 
473  if (ST->isMisaligned128StoreSlow() && Opcode == Instruction::Store &&
474  LT.second.is128BitVector() && Alignment < 16) {
475  // Unaligned stores are extremely inefficient. We don't split all
476  // unaligned 128-bit stores because the negative impact that has shown in
477  // practice on inlined block copy code.
478  // We make such stores expensive so that we will only vectorize if there
479  // are 6 other instructions getting vectorized.
480  const int AmortizationCost = 6;
481 
482  return LT.first * 2 * AmortizationCost;
483  }
484 
485  if (Ty->isVectorTy() && Ty->getVectorElementType()->isIntegerTy(8) &&
486  Ty->getVectorNumElements() < 8) {
487  // We scalarize the loads/stores because there is not v.4b register and we
488  // have to promote the elements to v.4h.
489  unsigned NumVecElts = Ty->getVectorNumElements();
490  unsigned NumVectorizableInstsToAmortize = NumVecElts * 2;
491  // We generate 2 instructions per vector element.
492  return NumVectorizableInstsToAmortize * NumVecElts * 2;
493  }
494 
495  return LT.first;
496 }
497 
499  unsigned Factor,
500  ArrayRef<unsigned> Indices,
501  unsigned Alignment,
502  unsigned AddressSpace) {
503  assert(Factor >= 2 && "Invalid interleave factor");
504  assert(isa<VectorType>(VecTy) && "Expect a vector type");
505 
506  if (Factor <= TLI->getMaxSupportedInterleaveFactor()) {
507  unsigned NumElts = VecTy->getVectorNumElements();
508  Type *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
509  unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy);
510 
511  // ldN/stN only support legal vector types of size 64 or 128 in bits.
512  if (NumElts % Factor == 0 && (SubVecSize == 64 || SubVecSize == 128))
513  return Factor;
514  }
515 
516  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
517  Alignment, AddressSpace);
518 }
519 
521  int Cost = 0;
522  for (auto *I : Tys) {
523  if (!I->isVectorTy())
524  continue;
525  if (I->getScalarSizeInBits() * I->getVectorNumElements() == 128)
526  Cost += getMemoryOpCost(Instruction::Store, I, 128, 0) +
528  }
529  return Cost;
530 }
531 
533  return ST->getMaxInterleaveFactor();
534 }
535 
538  // Enable partial unrolling and runtime unrolling.
540 
541  // For inner loop, it is more likely to be a hot one, and the runtime check
542  // can be promoted out from LICM pass, so the overhead is less, let's try
543  // a larger threshold to unroll more loops.
544  if (L->getLoopDepth() > 1)
545  UP.PartialThreshold *= 2;
546 
547  // Disable partial & runtime unrolling on -Os.
549 }
550 
552  Type *ExpectedType) {
553  switch (Inst->getIntrinsicID()) {
554  default:
555  return nullptr;
556  case Intrinsic::aarch64_neon_st2:
557  case Intrinsic::aarch64_neon_st3:
558  case Intrinsic::aarch64_neon_st4: {
559  // Create a struct type
560  StructType *ST = dyn_cast<StructType>(ExpectedType);
561  if (!ST)
562  return nullptr;
563  unsigned NumElts = Inst->getNumArgOperands() - 1;
564  if (ST->getNumElements() != NumElts)
565  return nullptr;
566  for (unsigned i = 0, e = NumElts; i != e; ++i) {
567  if (Inst->getArgOperand(i)->getType() != ST->getElementType(i))
568  return nullptr;
569  }
570  Value *Res = UndefValue::get(ExpectedType);
571  IRBuilder<> Builder(Inst);
572  for (unsigned i = 0, e = NumElts; i != e; ++i) {
573  Value *L = Inst->getArgOperand(i);
574  Res = Builder.CreateInsertValue(Res, L, i);
575  }
576  return Res;
577  }
578  case Intrinsic::aarch64_neon_ld2:
579  case Intrinsic::aarch64_neon_ld3:
580  case Intrinsic::aarch64_neon_ld4:
581  if (Inst->getType() == ExpectedType)
582  return Inst;
583  return nullptr;
584  }
585 }
586 
588  MemIntrinsicInfo &Info) {
589  switch (Inst->getIntrinsicID()) {
590  default:
591  break;
592  case Intrinsic::aarch64_neon_ld2:
593  case Intrinsic::aarch64_neon_ld3:
594  case Intrinsic::aarch64_neon_ld4:
595  Info.ReadMem = true;
596  Info.WriteMem = false;
597  Info.IsSimple = true;
598  Info.NumMemRefs = 1;
599  Info.PtrVal = Inst->getArgOperand(0);
600  break;
601  case Intrinsic::aarch64_neon_st2:
602  case Intrinsic::aarch64_neon_st3:
603  case Intrinsic::aarch64_neon_st4:
604  Info.ReadMem = false;
605  Info.WriteMem = true;
606  Info.IsSimple = true;
607  Info.NumMemRefs = 1;
608  Info.PtrVal = Inst->getArgOperand(Inst->getNumArgOperands() - 1);
609  break;
610  }
611 
612  switch (Inst->getIntrinsicID()) {
613  default:
614  return false;
615  case Intrinsic::aarch64_neon_ld2:
616  case Intrinsic::aarch64_neon_st2:
617  Info.MatchingId = VECTOR_LDST_TWO_ELEMENTS;
618  break;
619  case Intrinsic::aarch64_neon_ld3:
620  case Intrinsic::aarch64_neon_st3:
621  Info.MatchingId = VECTOR_LDST_THREE_ELEMENTS;
622  break;
623  case Intrinsic::aarch64_neon_ld4:
624  case Intrinsic::aarch64_neon_st4:
625  Info.MatchingId = VECTOR_LDST_FOUR_ELEMENTS;
626  break;
627  }
628  return true;
629 }
630 
632  return ST->getCacheLineSize();
633 }
634 
636  return ST->getPrefetchDistance();
637 }
638 
640  return ST->getMinPrefetchStride();
641 }
642 
644  return ST->getMaxPrefetchIterationsAhead();
645 }
MachineLoop * L
APInt ashr(unsigned shiftAmt) const
Arithmetic right-shift function.
Definition: APInt.cpp:1035
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance)
unsigned getVectorInsertExtractBaseCost() const
size_t i
Cost tables and simple lookup functions.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:51
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
The main scalar evolution driver.
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold, but used for partial/runtime unrolling (set to UINT_MAX to disable).
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
unsigned PartialThreshold
The cost threshold for the unrolled loop, like Threshold, but used for partial/runtime unrolling (set...
bool IsSimple
True only if this memory operation is non-volatile, non-atomic, and unordered.
Type Conversion Cost Table.
Definition: CostTable.h:45
unsigned getMaxInterleaveFactor(unsigned VF)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:180
int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
Definition: BasicTTIImpl.h:363
Class to represent struct types.
Definition: DerivedTypes.h:199
unsigned getNumArgOperands() const
Return the number of call arguments.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:588
static bool isLogicalImmediate(uint64_t imm, unsigned regSize)
isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the...
const TypeConversionCostTblEntry * ConvertCostTableLookup(ArrayRef< TypeConversionCostTblEntry > Tbl, int ISD, MVT Dst, MVT Src)
Find in type conversion cost table, TypeTy must be comparable to CompareTy by ==. ...
Definition: CostTable.h:55
Type * getVectorElementType() const
Definition: Type.h:353
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
Definition: BasicTTIImpl.h:567
unsigned getMinPrefetchStride() const
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:410
PopcntSupportKind
Flags indicating the kind of support for population count.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getPrefetchDistance() const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Type * getScalarType() const LLVM_READONLY
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.cpp:44
Type * getElementType() const
Definition: DerivedTypes.h:336
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:453
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
Definition: BasicTTIImpl.h:490
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)
int getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:399
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:219
Type * getElementType(unsigned N) const
Definition: DerivedTypes.h:290
unsigned getMaxPrefetchIterationsAhead() const
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1321
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1947
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1952
Expected to fold away in lowering.
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:939
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1255
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
bool isMisaligned128StoreSlow() const
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine...
EVT - Extended Value Type.
Definition: ValueTypes.h:31
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
Definition: Constants.cpp:1337
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
OperandValueProperties
Additional properties of an operand's values.
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
Definition: BasicTTIImpl.h:306
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:230
AddressSpace
Definition: NVPTXBaseInfo.h:22
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
unsigned getMaxInterleaveFactor() const
unsigned getCacheLineSize() const
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
Class to represent vector types.
Definition: DerivedTypes.h:369
Class for arbitrary precision integers.
Definition: APInt.h:77
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:354
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:195
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:400
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:438
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1942
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:333
This class represents an analyzed expression in the program.
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
int getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:368
Parameters that control the generic loop unrolling transformation.
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
The cost of a typical 'add' instruction.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:107
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:108
LLVM Value Representation.
Definition: Value.h:71
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1007
static VectorType * get(Type *ElementType, unsigned NumElements)
This static method is the primary way to construct an VectorType.
Definition: Type.cpp:631
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:533
Value * PtrVal
This is the pointer that the intrinsic is loading from or storing to.
OperandValueKind
Additional information about an operand's possible values.
This pass exposes codegen information to IR-level passes.
Conversion operators.
Definition: ISDOpcodes.h:397
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
Definition: BasicTTIImpl.h:231
int * Ptr
Value * CreateInsertValue(Value *Agg, Value *Val, ArrayRef< unsigned > Idxs, const Twine &Name="")
Definition: IRBuilder.h:1679
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:406
unsigned getNumElements() const
Random access to the elements.
Definition: DerivedTypes.h:289
unsigned getLoopDepth() const
Return the nesting level of this loop.
Definition: LoopInfo.h:95
Information about a load/store intrinsic defined by the target.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:226
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
This file describes how to lower LLVM code to machine code.