LLVM  4.0.0
ARMTargetTransformInfo.cpp
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1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "ARMTargetTransformInfo.h"
11 #include "llvm/Support/Debug.h"
12 #include "llvm/Target/CostTable.h"
14 using namespace llvm;
15 
16 #define DEBUG_TYPE "armtti"
17 
18 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
19  assert(Ty->isIntegerTy());
20 
21  unsigned Bits = Ty->getPrimitiveSizeInBits();
22  if (Bits == 0 || Imm.getActiveBits() >= 64)
23  return 4;
24 
25  int64_t SImmVal = Imm.getSExtValue();
26  uint64_t ZImmVal = Imm.getZExtValue();
27  if (!ST->isThumb()) {
28  if ((SImmVal >= 0 && SImmVal < 65536) ||
29  (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
30  (ARM_AM::getSOImmVal(~ZImmVal) != -1))
31  return 1;
32  return ST->hasV6T2Ops() ? 2 : 3;
33  }
34  if (ST->isThumb2()) {
35  if ((SImmVal >= 0 && SImmVal < 65536) ||
36  (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
37  (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
38  return 1;
39  return ST->hasV6T2Ops() ? 2 : 3;
40  }
41  // Thumb1.
42  if (SImmVal >= 0 && SImmVal < 256)
43  return 1;
44  if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
45  return 2;
46  // Load from constantpool.
47  return 3;
48 }
49 
50 
51 // Constants smaller than 256 fit in the immediate field of
52 // Thumb1 instructions so we return a zero cost and 1 otherwise.
53 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
54  const APInt &Imm, Type *Ty) {
55  if (Imm.isNonNegative() && Imm.getLimitedValue() < 256)
56  return 0;
57 
58  return 1;
59 }
60 
61 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
62  Type *Ty) {
63  // Division by a constant can be turned into multiplication, but only if we
64  // know it's constant. So it's not so much that the immediate is cheap (it's
65  // not), but that the alternative is worse.
66  // FIXME: this is probably unneeded with GlobalISel.
67  if ((Opcode == Instruction::SDiv || Opcode == Instruction::UDiv ||
68  Opcode == Instruction::SRem || Opcode == Instruction::URem) &&
69  Idx == 1)
70  return 0;
71 
72  if (Opcode == Instruction::And)
73  // Conversion to BIC is free, and means we can use ~Imm instead.
74  return std::min(getIntImmCost(Imm, Ty), getIntImmCost(~Imm, Ty));
75 
76  if (Opcode == Instruction::Add)
77  // Conversion to SUB is free, and means we can use -Imm instead.
78  return std::min(getIntImmCost(Imm, Ty), getIntImmCost(-Imm, Ty));
79 
80  if (Opcode == Instruction::ICmp && Imm.isNegative() &&
81  Ty->getIntegerBitWidth() == 32) {
82  int64_t NegImm = -Imm.getSExtValue();
83  if (ST->isThumb2() && NegImm < 1<<12)
84  // icmp X, #-C -> cmn X, #C
85  return 0;
86  if (ST->isThumb() && NegImm < 1<<8)
87  // icmp X, #-C -> adds X, #C
88  return 0;
89  }
90 
91  return getIntImmCost(Imm, Ty);
92 }
93 
94 
95 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
96  int ISD = TLI->InstructionOpcodeToISD(Opcode);
97  assert(ISD && "Invalid opcode");
98 
99  // Single to/from double precision conversions.
100  static const CostTblEntry NEONFltDblTbl[] = {
101  // Vector fptrunc/fpext conversions.
102  { ISD::FP_ROUND, MVT::v2f64, 2 },
103  { ISD::FP_EXTEND, MVT::v2f32, 2 },
104  { ISD::FP_EXTEND, MVT::v4f32, 4 }
105  };
106 
107  if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
108  ISD == ISD::FP_EXTEND)) {
109  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
110  if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second))
111  return LT.first * Entry->Cost;
112  }
113 
114  EVT SrcTy = TLI->getValueType(DL, Src);
115  EVT DstTy = TLI->getValueType(DL, Dst);
116 
117  if (!SrcTy.isSimple() || !DstTy.isSimple())
118  return BaseT::getCastInstrCost(Opcode, Dst, Src);
119 
120  // Some arithmetic, load and store operations have specific instructions
121  // to cast up/down their types automatically at no extra cost.
122  // TODO: Get these tables to know at least what the related operations are.
123  static const TypeConversionCostTblEntry NEONVectorConversionTbl[] = {
130 
131  // The number of vmovl instructions for the extension.
142 
143  // Operations that we legalize using splitting.
146 
147  // Vector float <-> i32 conversions.
150 
171 
178 
179  // Vector double <-> i32 conversions.
182 
189 
196  };
197 
198  if (SrcTy.isVector() && ST->hasNEON()) {
199  if (const auto *Entry = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
200  DstTy.getSimpleVT(),
201  SrcTy.getSimpleVT()))
202  return Entry->Cost;
203  }
204 
205  // Scalar float to integer conversions.
206  static const TypeConversionCostTblEntry NEONFloatConversionTbl[] = {
227  };
228  if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
229  if (const auto *Entry = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
230  DstTy.getSimpleVT(),
231  SrcTy.getSimpleVT()))
232  return Entry->Cost;
233  }
234 
235  // Scalar integer to float conversions.
236  static const TypeConversionCostTblEntry NEONIntegerConversionTbl[] = {
257  };
258 
259  if (SrcTy.isInteger() && ST->hasNEON()) {
260  if (const auto *Entry = ConvertCostTableLookup(NEONIntegerConversionTbl,
261  ISD, DstTy.getSimpleVT(),
262  SrcTy.getSimpleVT()))
263  return Entry->Cost;
264  }
265 
266  // Scalar integer conversion costs.
267  static const TypeConversionCostTblEntry ARMIntegerConversionTbl[] = {
268  // i16 -> i64 requires two dependent operations.
270 
271  // Truncates on i64 are assumed to be free.
274  { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
276  };
277 
278  if (SrcTy.isInteger()) {
279  if (const auto *Entry = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
280  DstTy.getSimpleVT(),
281  SrcTy.getSimpleVT()))
282  return Entry->Cost;
283  }
284 
285  return BaseT::getCastInstrCost(Opcode, Dst, Src);
286 }
287 
288 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
289  unsigned Index) {
290  // Penalize inserting into an D-subregister. We end up with a three times
291  // lower estimated throughput on swift.
292  if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement &&
293  ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32)
294  return 3;
295 
296  if ((Opcode == Instruction::InsertElement ||
297  Opcode == Instruction::ExtractElement)) {
298  // Cross-class copies are expensive on many microarchitectures,
299  // so assume they are expensive by default.
300  if (ValTy->getVectorElementType()->isIntegerTy())
301  return 3;
302 
303  // Even if it's not a cross class copy, this likely leads to mixing
304  // of NEON and VFP code and should be therefore penalized.
305  if (ValTy->isVectorTy() &&
306  ValTy->getScalarSizeInBits() <= 32)
307  return std::max(BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U);
308  }
309 
310  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
311 }
312 
313 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) {
314 
315  int ISD = TLI->InstructionOpcodeToISD(Opcode);
316  // On NEON a a vector select gets lowered to vbsl.
317  if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
318  // Lowering of some vector selects is currently far from perfect.
319  static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = {
320  { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
321  { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
323  };
324 
325  EVT SelCondTy = TLI->getValueType(DL, CondTy);
326  EVT SelValTy = TLI->getValueType(DL, ValTy);
327  if (SelCondTy.isSimple() && SelValTy.isSimple()) {
328  if (const auto *Entry = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
329  SelCondTy.getSimpleVT(),
330  SelValTy.getSimpleVT()))
331  return Entry->Cost;
332  }
333 
334  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
335  return LT.first;
336  }
337 
338  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
339 }
340 
342  const SCEV *Ptr) {
343  // Address computations in vectorized code with non-consecutive addresses will
344  // likely result in more instructions compared to scalar code where the
345  // computation can more often be merged into the index mode. The resulting
346  // extra micro-ops can significantly decrease throughput.
347  unsigned NumVectorInstToHideOverhead = 10;
348  int MaxMergeDistance = 64;
349 
350  if (Ty->isVectorTy() && SE &&
351  !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1))
352  return NumVectorInstToHideOverhead;
353 
354  // In many cases the address computation is not merged into the instruction
355  // addressing mode.
356  return 1;
357 }
358 
360  // Use similar logic that's in ARMISelLowering:
361  // Any ARM CPU with VFP2 has floating point, but Thumb1 didn't have access
362  // to VFP.
363 
364  if (ST->hasVFP2() && !ST->isThumb1Only()) {
365  if (Ty->isFloatTy()) {
367  }
368 
369  if (Ty->isDoubleTy()) {
372  }
373  }
374 
376 }
377 
379  Type *SubTp) {
380  // We only handle costs of reverse and alternate shuffles for now.
381  if (Kind != TTI::SK_Reverse && Kind != TTI::SK_Alternate)
382  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
383 
384  if (Kind == TTI::SK_Reverse) {
385  static const CostTblEntry NEONShuffleTbl[] = {
386  // Reverse shuffle cost one instruction if we are shuffling within a
387  // double word (vrev) or two if we shuffle a quad word (vrev, vext).
392 
397 
398  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
399 
400  if (const auto *Entry = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE,
401  LT.second))
402  return LT.first * Entry->Cost;
403 
404  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
405  }
406  if (Kind == TTI::SK_Alternate) {
407  static const CostTblEntry NEONAltShuffleTbl[] = {
408  // Alt shuffle cost table for ARM. Cost is the number of instructions
409  // required to create the shuffled vector.
410 
415 
419 
421 
423 
424  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
425  if (const auto *Entry = CostTableLookup(NEONAltShuffleTbl,
426  ISD::VECTOR_SHUFFLE, LT.second))
427  return LT.first * Entry->Cost;
428  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
429  }
430  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
431 }
432 
434  unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
436  TTI::OperandValueProperties Opd2PropInfo,
438 
439  int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
440  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
441 
442  const unsigned FunctionCallDivCost = 20;
443  const unsigned ReciprocalDivCost = 10;
444  static const CostTblEntry CostTbl[] = {
445  // Division.
446  // These costs are somewhat random. Choose a cost of 20 to indicate that
447  // vectorizing devision (added function call) is going to be very expensive.
448  // Double registers types.
449  { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
450  { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
451  { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
452  { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
453  { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
454  { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
455  { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
456  { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
457  { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
458  { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
459  { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
460  { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
461  { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
462  { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
463  { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
464  { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
465  // Quad register types.
466  { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
467  { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
468  { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
469  { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
470  { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
471  { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
472  { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
473  { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
474  { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
475  { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
476  { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
477  { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
478  { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
479  { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
480  { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
481  { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
482  // Multiplication.
483  };
484 
485  if (ST->hasNEON())
486  if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second))
487  return LT.first * Entry->Cost;
488 
489  int Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
490  Opd1PropInfo, Opd2PropInfo);
491 
492  // This is somewhat of a hack. The problem that we are facing is that SROA
493  // creates a sequence of shift, and, or instructions to construct values.
494  // These sequences are recognized by the ISel and have zero-cost. Not so for
495  // the vectorized code. Because we have support for v2i64 but not i64 those
496  // sequences look particularly beneficial to vectorize.
497  // To work around this we increase the cost of v2i64 operations to make them
498  // seem less beneficial.
499  if (LT.second == MVT::v2i64 &&
501  Cost += 4;
502 
503  return Cost;
504 }
505 
506 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
507  unsigned AddressSpace) {
508  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
509 
510  if (Src->isVectorTy() && Alignment != 16 &&
511  Src->getVectorElementType()->isDoubleTy()) {
512  // Unaligned loads/stores are extremely inefficient.
513  // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.
514  return LT.first * 4;
515  }
516  return LT.first;
517 }
518 
519 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
520  unsigned Factor,
521  ArrayRef<unsigned> Indices,
522  unsigned Alignment,
523  unsigned AddressSpace) {
524  assert(Factor >= 2 && "Invalid interleave factor");
525  assert(isa<VectorType>(VecTy) && "Expect a vector type");
526 
527  // vldN/vstN doesn't support vector types of i64/f64 element.
528  bool EltIs64Bits = DL.getTypeSizeInBits(VecTy->getScalarType()) == 64;
529 
530  if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits) {
531  unsigned NumElts = VecTy->getVectorNumElements();
532  Type *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
533  unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy);
534 
535  // vldN/vstN only support legal vector types of size 64 or 128 in bits.
536  if (NumElts % Factor == 0 && (SubVecSize == 64 || SubVecSize == 128))
537  return Factor;
538  }
539 
540  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
541  Alignment, AddressSpace);
542 }
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:467
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance)
bool isFPOnlySP() const
Definition: ARMSubtarget.h:471
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1309
Cost tables and simple lookup functions.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:313
The main scalar evolution driver.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
Definition: APInt.h:329
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:148
uint64_t getLimitedValue(uint64_t Limit=~0ULL) const
If this value is smaller than the specified limit, return it, otherwise return the limit value...
Definition: APInt.h:409
Type Conversion Cost Table.
Definition: CostTable.h:45
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:420
bool isThumb1Only() const
Definition: ARMSubtarget.h:577
Cost Table Entry.
Definition: CostTable.h:25
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:324
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:133
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
Definition: BasicTTIImpl.h:363
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
const TypeConversionCostTblEntry * ConvertCostTableLookup(ArrayRef< TypeConversionCostTblEntry > Tbl, int ISD, MVT Dst, MVT Src)
Find in type conversion cost table, TypeTy must be comparable to CompareTy by ==. ...
Definition: CostTable.h:55
Type * getVectorElementType() const
Definition: Type.h:353
bool isThumb() const
Definition: ARMSubtarget.h:576
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:123
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
Definition: BasicTTIImpl.h:567
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
Choose alternate elements from vector.
int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:410
static int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
unsigned getActiveBits() const
Compute the number of active bits in the value.
Definition: APInt.h:1279
bool hasNEON() const
Definition: ARMSubtarget.h:449
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Reverse the order of the vector.
Type * getScalarType() const LLVM_READONLY
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.cpp:44
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:453
static bool isThumbImmShiftedVal(unsigned V)
isThumbImmShiftedVal - Return true if the specified value can be obtained by left shifting a 8-bit im...
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
Definition: BasicTTIImpl.h:490
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:219
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1321
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:145
unsigned getIntegerBitWidth() const
Definition: DerivedTypes.h:96
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:485
EVT - Extended Value Type.
Definition: ValueTypes.h:31
OperandValueProperties
Additional properties of an operand's values.
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
Definition: BasicTTIImpl.h:354
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:485
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
Definition: BasicTTIImpl.h:306
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type...
Definition: Type.cpp:123
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
AddressSpace
Definition: NVPTXBaseInfo.h:22
int getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
bool hasVFP2() const
Definition: ARMSubtarget.h:445
Class for arbitrary precision integers.
Definition: APInt.h:77
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:354
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:195
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:400
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:438
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1942
const CostTblEntry * CostTableLookup(ArrayRef< CostTblEntry > Tbl, int ISD, MVT Ty)
Find in cost table, TypeTy must be comparable to CompareTy by ==.
Definition: CostTable.h:32
This class represents an analyzed expression in the program.
bool isThumb2() const
Definition: ARMSubtarget.h:578
int getIntImmCost(const APInt &Imm, Type *Ty)
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:529
const unsigned Kind
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info=TTI::OK_AnyValue, TTI::OperandValueKind Op2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:118
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
The cost of a typical 'add' instruction.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:107
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:108
static VectorType * get(Type *ElementType, unsigned NumElements)
This static method is the primary way to construct an VectorType.
Definition: Type.cpp:631
int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:533
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
OperandValueKind
Additional information about an operand's possible values.
Conversion operators.
Definition: ISDOpcodes.h:397
int * Ptr
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:406
The cost of a 'div' instruction on x86.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:226
This file describes how to lower LLVM code to machine code.
ShuffleKind
The various kinds of shuffle patterns for vector queries.