LLVM  4.0.0
Public Member Functions | Protected Types | Protected Attributes | List of all members
llvm::X86Subtarget Class Referencefinal

#include <X86Subtarget.h>

Inheritance diagram for llvm::X86Subtarget:
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Collaboration diagram for llvm::X86Subtarget:
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Public Member Functions

 X86Subtarget (const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, unsigned StackAlignOverride)
 This constructor initializes the data members to match that of the specified triple. More...
 
void setGISelAccessor (GISelAccessor &GISel)
 This object will take onwership of GISelAccessor. More...
 
const X86TargetLoweringgetTargetLowering () const override
 
const X86InstrInfogetInstrInfo () const override
 
const X86FrameLoweringgetFrameLowering () const override
 
const X86SelectionDAGInfogetSelectionDAGInfo () const override
 
const X86RegisterInfogetRegisterInfo () const override
 
unsigned getStackAlignment () const
 Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget. More...
 
unsigned getMaxInlineSizeThreshold () const
 Returns the maximum memset / memcpy size that still makes it profitable to inline the call. More...
 
void ParseSubtargetFeatures (StringRef CPU, StringRef FS)
 ParseSubtargetFeatures - Parses features string setting specified subtarget options. More...
 
const CallLoweringgetCallLowering () const override
 Methods used by Global ISel. More...
 
const InstructionSelectorgetInstructionSelector () const override
 
const LegalizerInfogetLegalizerInfo () const override
 
const RegisterBankInfogetRegBankInfo () const override
 
bool is64Bit () const
 Is this x86_64? (disregarding specific ABI / programming model) More...
 
bool is32Bit () const
 
bool is16Bit () const
 
bool isTarget64BitILP32 () const
 Is this x86_64 with the ILP32 programming model (x32 ABI)? More...
 
bool isTarget64BitLP64 () const
 Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? More...
 
PICStyles::Style getPICStyle () const
 
void setPICStyle (PICStyles::Style Style)
 
bool hasX87 () const
 
bool hasCMov () const
 
bool hasSSE1 () const
 
bool hasSSE2 () const
 
bool hasSSE3 () const
 
bool hasSSSE3 () const
 
bool hasSSE41 () const
 
bool hasSSE42 () const
 
bool hasAVX () const
 
bool hasAVX2 () const
 
bool hasAVX512 () const
 
bool hasFp256 () const
 
bool hasInt256 () const
 
bool hasSSE4A () const
 
bool hasMMX () const
 
bool has3DNow () const
 
bool has3DNowA () const
 
bool hasPOPCNT () const
 
bool hasAES () const
 
bool hasFXSR () const
 
bool hasXSAVE () const
 
bool hasXSAVEOPT () const
 
bool hasXSAVEC () const
 
bool hasXSAVES () const
 
bool hasPCLMUL () const
 
bool hasFMA () const
 
bool hasFMA4 () const
 
bool hasAnyFMA () const
 
bool hasXOP () const
 
bool hasTBM () const
 
bool hasMOVBE () const
 
bool hasRDRAND () const
 
bool hasF16C () const
 
bool hasFSGSBase () const
 
bool hasLZCNT () const
 
bool hasBMI () const
 
bool hasBMI2 () const
 
bool hasVBMI () const
 
bool hasIFMA () const
 
bool hasRTM () const
 
bool hasHLE () const
 
bool hasADX () const
 
bool hasSHA () const
 
bool hasPRFCHW () const
 
bool hasRDSEED () const
 
bool hasLAHFSAHF () const
 
bool hasMWAITX () const
 
bool isBTMemSlow () const
 
bool isSHLDSlow () const
 
bool isPMULLDSlow () const
 
bool isUnalignedMem16Slow () const
 
bool isUnalignedMem32Slow () const
 
bool hasSSEUnalignedMem () const
 
bool hasCmpxchg16b () const
 
bool useLeaForSP () const
 
bool hasFastPartialYMMWrite () const
 
bool hasFastScalarFSQRT () const
 
bool hasFastVectorFSQRT () const
 
bool hasFastLZCNT () const
 
bool hasSlowDivide32 () const
 
bool hasSlowDivide64 () const
 
bool padShortFunctions () const
 
bool callRegIndirect () const
 
bool LEAusesAG () const
 
bool slowLEA () const
 
bool slowIncDec () const
 
bool hasCDI () const
 
bool hasPFI () const
 
bool hasERI () const
 
bool hasDQI () const
 
bool hasBWI () const
 
bool hasVLX () const
 
bool hasPKU () const
 
bool hasMPX () const
 
virtual bool isXRaySupported () const override
 
bool isAtom () const
 
bool isSLM () const
 
bool useSoftFloat () const
 
bool hasMFence () const
 Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2). More...
 
const TriplegetTargetTriple () const
 
bool isTargetDarwin () const
 
bool isTargetFreeBSD () const
 
bool isTargetDragonFly () const
 
bool isTargetSolaris () const
 
bool isTargetPS4 () const
 
bool isTargetELF () const
 
bool isTargetCOFF () const
 
bool isTargetMachO () const
 
bool isTargetLinux () const
 
bool isTargetKFreeBSD () const
 
bool isTargetGlibc () const
 
bool isTargetAndroid () const
 
bool isTargetNaCl () const
 
bool isTargetNaCl32 () const
 
bool isTargetNaCl64 () const
 
bool isTargetMCU () const
 
bool isTargetWindowsMSVC () const
 
bool isTargetKnownWindowsMSVC () const
 
bool isTargetWindowsCoreCLR () const
 
bool isTargetWindowsCygwin () const
 
bool isTargetWindowsGNU () const
 
bool isTargetWindowsItanium () const
 
bool isTargetCygMing () const
 
bool isOSWindows () const
 
bool isTargetWin64 () const
 
bool isTargetWin32 () const
 
bool isPICStyleGOT () const
 
bool isPICStyleRIPRel () const
 
bool isPICStyleStubPIC () const
 
bool isPositionIndependent () const
 
bool isCallingConvWin64 (CallingConv::ID CC) const
 
unsigned char classifyLocalReference (const GlobalValue *GV) const
 Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
unsigned char classifyGlobalReference (const GlobalValue *GV, const Module &M) const
 
unsigned char classifyGlobalReference (const GlobalValue *GV) const
 Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
unsigned char classifyGlobalFunctionReference (const GlobalValue *GV, const Module &M) const
 Classify a global function reference for the current subtarget. More...
 
unsigned char classifyGlobalFunctionReference (const GlobalValue *GV) const
 
unsigned char classifyBlockAddressReference () const
 Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context. More...
 
bool isLegalToCallImmediateAddr () const
 Return true if the subtarget allows calls to immediate address. More...
 
const char * getBZeroEntry () const
 This function returns the name of a function which has an interface like the non-standard bzero function, if such a function exists on the current subtarget and it is considered prefereable over memset with zero passed as the second argument. More...
 
bool hasSinCos () const
 This function returns true if the target has sincos() routine in its compiler runtime or math libraries. More...
 
bool enableMachineScheduler () const override
 Enable the MachineScheduler pass for all X86 subtargets. More...
 
bool enableEarlyIfConversion () const override
 
const InstrItineraryDatagetInstrItineraryData () const override
 Return the instruction itineraries based on the subtarget selection. More...
 
AntiDepBreakMode getAntiDepBreakMode () const override
 

Protected Types

enum  X86SSEEnum {
  NoSSE, SSE1, SSE2, SSE3,
  SSSE3, SSE41, SSE42, AVX,
  AVX2, AVX512F
}
 
enum  X863DNowEnum { NoThreeDNow, MMX, ThreeDNow, ThreeDNowA }
 
enum  X86ProcFamilyEnum { Others, IntelAtom, IntelSLM }
 

Protected Attributes

X86ProcFamilyEnum X86ProcFamily
 X86 processor family: Intel Atom, and others. More...
 
PICStyles::Style PICStyle
 Which PIC style to use. More...
 
const TargetMachineTM
 
X86SSEEnum X86SSELevel
 SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. More...
 
X863DNowEnum X863DNowLevel
 MMX, 3DNow, 3DNow Athlon, or none supported. More...
 
bool HasX87
 True if the processor supports X87 instructions. More...
 
bool HasCMov
 True if this processor has conditional move instructions (generally pentium pro+). More...
 
bool HasX86_64
 True if the processor supports X86-64 instructions. More...
 
bool HasPOPCNT
 True if the processor supports POPCNT. More...
 
bool HasSSE4A
 True if the processor supports SSE4A instructions. More...
 
bool HasAES
 Target has AES instructions. More...
 
bool HasFXSR
 Target has FXSAVE/FXRESTOR instructions. More...
 
bool HasXSAVE
 Target has XSAVE instructions. More...
 
bool HasXSAVEOPT
 Target has XSAVEOPT instructions. More...
 
bool HasXSAVEC
 Target has XSAVEC instructions. More...
 
bool HasXSAVES
 Target has XSAVES instructions. More...
 
bool HasPCLMUL
 Target has carry-less multiplication. More...
 
bool HasFMA
 Target has 3-operand fused multiply-add. More...
 
bool HasFMA4
 Target has 4-operand fused multiply-add. More...
 
bool HasXOP
 Target has XOP instructions. More...
 
bool HasTBM
 Target has TBM instructions. More...
 
bool HasMOVBE
 True if the processor has the MOVBE instruction. More...
 
bool HasRDRAND
 True if the processor has the RDRAND instruction. More...
 
bool HasF16C
 Processor has 16-bit floating point conversion instructions. More...
 
bool HasFSGSBase
 Processor has FS/GS base insturctions. More...
 
bool HasLZCNT
 Processor has LZCNT instruction. More...
 
bool HasBMI
 Processor has BMI1 instructions. More...
 
bool HasBMI2
 Processor has BMI2 instructions. More...
 
bool HasVBMI
 Processor has VBMI instructions. More...
 
bool HasIFMA
 Processor has Integer Fused Multiply Add. More...
 
bool HasRTM
 Processor has RTM instructions. More...
 
bool HasHLE
 Processor has HLE. More...
 
bool HasADX
 Processor has ADX instructions. More...
 
bool HasSHA
 Processor has SHA instructions. More...
 
bool HasPRFCHW
 Processor has PRFCHW instructions. More...
 
bool HasRDSEED
 Processor has RDSEED instructions. More...
 
bool HasLAHFSAHF
 Processor has LAHF/SAHF instructions. More...
 
bool HasMWAITX
 Processor has MONITORX/MWAITX instructions. More...
 
bool HasPFPREFETCHWT1
 Processor has Prefetch with intent to Write instruction. More...
 
bool IsBTMemSlow
 True if BT (bit test) of memory instructions are slow. More...
 
bool IsSHLDSlow
 True if SHLD instructions are slow. More...
 
bool IsPMULLDSlow
 True if the PMULLD instruction is slow compared to PMULLW/PMULHW and. More...
 
bool IsUAMem16Slow
 True if unaligned memory accesses of 16-bytes are slow. More...
 
bool IsUAMem32Slow
 True if unaligned memory accesses of 32-bytes are slow. More...
 
bool HasSSEUnalignedMem
 True if SSE operations can have unaligned memory operands. More...
 
bool HasCmpxchg16b
 True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips. More...
 
bool UseLeaForSP
 True if the LEA instruction should be used for adjusting the stack pointer. More...
 
bool HasFastPartialYMMWrite
 True if there is no performance penalty to writing only the lower parts of a YMM register without clearing the upper part. More...
 
bool HasFastScalarFSQRT
 True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration. More...
 
bool HasFastVectorFSQRT
 True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. More...
 
bool HasSlowDivide32
 True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible. More...
 
bool HasSlowDivide64
 True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible. More...
 
bool HasFastLZCNT
 True if LZCNT instruction is fast. More...
 
bool PadShortFunctions
 True if the short functions should be padded to prevent a stall when returning too early. More...
 
bool CallRegIndirect
 True if the Calls with memory reference should be converted to a register-based indirect call. More...
 
bool LEAUsesAG
 True if the LEA instruction inputs have to be ready at address generation (AG) time. More...
 
bool SlowLEA
 True if the LEA instruction with certain arguments is slow. More...
 
bool SlowIncDec
 True if INC and DEC instructions are slow when writing to flags. More...
 
bool HasPFI
 Processor has AVX-512 PreFetch Instructions. More...
 
bool HasERI
 Processor has AVX-512 Exponential and Reciprocal Instructions. More...
 
bool HasCDI
 Processor has AVX-512 Conflict Detection Instructions. More...
 
bool HasDQI
 Processor has AVX-512 Doubleword and Quadword instructions. More...
 
bool HasBWI
 Processor has AVX-512 Byte and Word instructions. More...
 
bool HasVLX
 Processor has AVX-512 Vector Length eXtenstions. More...
 
bool HasPKU
 Processor has PKU extenstions. More...
 
bool HasMPX
 Processor supports MPX - Memory Protection Extensions. More...
 
bool HasInvPCId
 Processor supports Invalidate Process-Context Identifier. More...
 
bool HasVMFUNC
 Processor has VM Functions. More...
 
bool HasSMAP
 Processor has Supervisor Mode Access Protection. More...
 
bool HasSGX
 Processor has Software Guard Extensions. More...
 
bool HasCLFLUSHOPT
 Processor supports Flush Cache Line instruction. More...
 
bool HasPCOMMIT
 Processor has Persistent Commit feature. More...
 
bool HasCLWB
 Processor supports Cache Line Write Back instruction. More...
 
bool UseSoftFloat
 Use software floating point for code generation. More...
 
unsigned stackAlignment
 The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More...
 
unsigned MaxInlineSizeThreshold
 Max. More...
 
Triple TargetTriple
 What processor and OS we're targeting. More...
 
InstrItineraryData InstrItins
 Instruction itineraries for scheduling. More...
 
std::unique_ptr< GISelAccessorGISel
 Gather the accessor points to GlobalISel-related APIs. More...
 

Detailed Description

Definition at line 46 of file X86Subtarget.h.

Member Enumeration Documentation

Enumerator
NoThreeDNow 
MMX 
ThreeDNow 
ThreeDNowA 

Definition at line 53 of file X86Subtarget.h.

Enumerator
Others 
IntelAtom 
IntelSLM 

Definition at line 57 of file X86Subtarget.h.

Enumerator
NoSSE 
SSE1 
SSE2 
SSE3 
SSSE3 
SSE41 
SSE42 
AVX 
AVX2 
AVX512F 

Definition at line 49 of file X86Subtarget.h.

Constructor & Destructor Documentation

X86Subtarget::X86Subtarget ( const Triple TT,
StringRef  CPU,
StringRef  FS,
const X86TargetMachine TM,
unsigned  StackAlignOverride 
)

This constructor initializes the data members to match that of the specified triple.

Definition at line 313 of file X86Subtarget.cpp.

References llvm::PICStyles::GOT, is64Bit(), isPositionIndependent(), isTargetCOFF(), isTargetDarwin(), isTargetELF(), llvm::PICStyles::None, llvm::PICStyles::RIPRel, setPICStyle(), and llvm::PICStyles::StubPIC.

Member Function Documentation

bool llvm::X86Subtarget::callRegIndirect ( ) const
inline

Definition at line 472 of file X86Subtarget.h.

References CallRegIndirect.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

unsigned char X86Subtarget::classifyBlockAddressReference ( ) const

Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context.

Definition at line 49 of file X86Subtarget.cpp.

References classifyLocalReference().

unsigned char X86Subtarget::classifyGlobalFunctionReference ( const GlobalValue GV,
const Module M 
) const

Classify a global function reference for the current subtarget.

Definition at line 123 of file X86Subtarget.cpp.

References assert(), F, is64Bit(), isTargetCOFF(), isTargetELF(), llvm::X86II::MO_GOTPCREL, llvm::X86II::MO_NO_FLAG, llvm::X86II::MO_PLT, llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.

Referenced by classifyGlobalFunctionReference().

unsigned char X86Subtarget::classifyGlobalFunctionReference ( const GlobalValue GV) const
unsigned char X86Subtarget::classifyGlobalReference ( const GlobalValue GV,
const Module M 
) const
unsigned char X86Subtarget::classifyGlobalReference ( const GlobalValue GV) const

Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context.

Definition at line 56 of file X86Subtarget.cpp.

References classifyGlobalReference(), and llvm::GlobalValue::getParent().

unsigned char X86Subtarget::classifyLocalReference ( const GlobalValue GV) const
bool X86Subtarget::enableEarlyIfConversion ( ) const
override

Definition at line 359 of file X86Subtarget.cpp.

References hasCMov(), and X86EarlyIfConv.

bool llvm::X86Subtarget::enableMachineScheduler ( ) const
inlineoverride

Enable the MachineScheduler pass for all X86 subtargets.

Definition at line 617 of file X86Subtarget.h.

AntiDepBreakMode llvm::X86Subtarget::getAntiDepBreakMode ( ) const
inlineoverride

Definition at line 626 of file X86Subtarget.h.

References llvm::TargetSubtargetInfo::ANTIDEP_CRITICAL.

const char * X86Subtarget::getBZeroEntry ( ) const

This function returns the name of a function which has an interface like the non-standard bzero function, if such a function exists on the current subtarget and it is considered prefereable over memset with zero passed as the second argument.

This function returns the name of a function which has an interface like the non-standard bzero function, if such a function exists on the current subtarget and it is considered preferable over memset with zero passed as the second argument.

Otherwise it returns null.

Definition at line 150 of file X86Subtarget.cpp.

References getTargetTriple().

const CallLowering * X86Subtarget::getCallLowering ( ) const
override

Methods used by Global ISel.

Definition at line 339 of file X86Subtarget.cpp.

References assert(), and GISel.

const X86FrameLowering* llvm::X86Subtarget::getFrameLowering ( ) const
inlineoverride
const X86InstrInfo* llvm::X86Subtarget::getInstrInfo ( ) const
inlineoverride
const InstrItineraryData* llvm::X86Subtarget::getInstrItineraryData ( ) const
inlineoverride

Return the instruction itineraries based on the subtarget selection.

Definition at line 622 of file X86Subtarget.h.

References InstrItins.

const InstructionSelector * X86Subtarget::getInstructionSelector ( ) const
override

Definition at line 344 of file X86Subtarget.cpp.

References assert(), and GISel.

const LegalizerInfo * X86Subtarget::getLegalizerInfo ( ) const
override

Definition at line 349 of file X86Subtarget.cpp.

References assert(), and GISel.

unsigned llvm::X86Subtarget::getMaxInlineSizeThreshold ( ) const
inline

Returns the maximum memset / memcpy size that still makes it profitable to inline the call.

Definition at line 362 of file X86Subtarget.h.

References MaxInlineSizeThreshold.

PICStyles::Style llvm::X86Subtarget::getPICStyle ( ) const
inline

Definition at line 405 of file X86Subtarget.h.

References PICStyle.

const RegisterBankInfo * X86Subtarget::getRegBankInfo ( ) const
override

Definition at line 354 of file X86Subtarget.cpp.

References assert(), and GISel.

const X86RegisterInfo* llvm::X86Subtarget::getRegisterInfo ( ) const
inlineoverride
const X86SelectionDAGInfo* llvm::X86Subtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 348 of file X86Subtarget.h.

unsigned llvm::X86Subtarget::getStackAlignment ( ) const
inline

Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 358 of file X86Subtarget.h.

References stackAlignment.

const X86TargetLowering* llvm::X86Subtarget::getTargetLowering ( ) const
inlineoverride
const Triple& llvm::X86Subtarget::getTargetTriple ( ) const
inline
bool llvm::X86Subtarget::has3DNow ( ) const
inline

Definition at line 423 of file X86Subtarget.h.

References ThreeDNow, and X863DNowLevel.

bool llvm::X86Subtarget::has3DNowA ( ) const
inline

Definition at line 424 of file X86Subtarget.h.

References ThreeDNowA, and X863DNowLevel.

bool llvm::X86Subtarget::hasADX ( ) const
inline

Definition at line 451 of file X86Subtarget.h.

References HasADX.

bool llvm::X86Subtarget::hasAES ( ) const
inline

Definition at line 426 of file X86Subtarget.h.

References HasAES.

bool llvm::X86Subtarget::hasAnyFMA ( ) const
inline
bool llvm::X86Subtarget::hasAVX ( ) const
inline
bool llvm::X86Subtarget::hasAVX2 ( ) const
inline
bool llvm::X86Subtarget::hasAVX512 ( ) const
inline

Definition at line 418 of file X86Subtarget.h.

References AVX512F, and X86SSELevel.

Referenced by combineCompareEqual(), combineMaskedLoad(), combineSelect(), combineToExtendVectorInReg(), combineVectorSignBitsTruncation(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), CopyToFromAsymmetricReg(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86RegisterInfo::getReservedRegs(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), hasAnyFMA(), isAddSub(), llvm::X86TTIImpl::isLegalMaskedGather(), lower1BitVectorShuffle(), lower512BitVectorShuffle(), LowerEXTEND_VECTOR_INREG(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerScalarImmediateShift(), lowerUINT_TO_FP_v2i32(), LowerVectorCTLZ(), LowerVSETCC(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86InstrInfo::setExecutionDomain(), truncateVectorCompareWithPACKSS(), and llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasBMI ( ) const
inline
bool llvm::X86Subtarget::hasBMI2 ( ) const
inline

Definition at line 446 of file X86Subtarget.h.

References HasBMI2.

bool llvm::X86Subtarget::hasBWI ( ) const
inline
bool llvm::X86Subtarget::hasCDI ( ) const
inline

Definition at line 476 of file X86Subtarget.h.

References HasCDI.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasCMov ( ) const
inline

Definition at line 409 of file X86Subtarget.h.

References HasCMov.

Referenced by llvm::X86InstrInfo::canInsertSelect(), combineXor(), and enableEarlyIfConversion().

bool llvm::X86Subtarget::hasCmpxchg16b ( ) const
inline

Definition at line 463 of file X86Subtarget.h.

References HasCmpxchg16b.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasDQI ( ) const
inline
bool llvm::X86Subtarget::hasERI ( ) const
inline

Definition at line 478 of file X86Subtarget.h.

References HasERI.

bool llvm::X86Subtarget::hasF16C ( ) const
inline

Definition at line 442 of file X86Subtarget.h.

References HasF16C.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasFastLZCNT ( ) const
inline

Definition at line 468 of file X86Subtarget.h.

References HasFastLZCNT.

Referenced by llvm::X86TargetLowering::isCtlzFast().

bool llvm::X86Subtarget::hasFastPartialYMMWrite ( ) const
inline

Definition at line 465 of file X86Subtarget.h.

References HasFastPartialYMMWrite.

bool llvm::X86Subtarget::hasFastScalarFSQRT ( ) const
inline

Definition at line 466 of file X86Subtarget.h.

References HasFastScalarFSQRT.

bool llvm::X86Subtarget::hasFastVectorFSQRT ( ) const
inline

Definition at line 467 of file X86Subtarget.h.

References HasFastVectorFSQRT.

bool llvm::X86Subtarget::hasFMA ( ) const
inline

Definition at line 435 of file X86Subtarget.h.

References HasFMA, and HasFMA4.

Referenced by hasAnyFMA().

bool llvm::X86Subtarget::hasFMA4 ( ) const
inline

Definition at line 436 of file X86Subtarget.h.

References HasFMA4.

Referenced by hasAnyFMA().

bool llvm::X86Subtarget::hasFp256 ( ) const
inline
bool llvm::X86Subtarget::hasFSGSBase ( ) const
inline

Definition at line 443 of file X86Subtarget.h.

References HasFSGSBase.

bool llvm::X86Subtarget::hasFXSR ( ) const
inline

Definition at line 427 of file X86Subtarget.h.

References HasFXSR.

bool llvm::X86Subtarget::hasHLE ( ) const
inline

Definition at line 450 of file X86Subtarget.h.

References HasHLE.

bool llvm::X86Subtarget::hasIFMA ( ) const
inline

Definition at line 448 of file X86Subtarget.h.

References HasIFMA.

bool llvm::X86Subtarget::hasInt256 ( ) const
inline
bool llvm::X86Subtarget::hasLAHFSAHF ( ) const
inline

Definition at line 455 of file X86Subtarget.h.

References HasLAHFSAHF.

Referenced by llvm::X86InstrInfo::copyPhysReg().

bool llvm::X86Subtarget::hasLZCNT ( ) const
inline
bool llvm::X86Subtarget::hasMFence ( ) const
inline

Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).

There isn't any reason to disable it if the target processor supports it.

Definition at line 494 of file X86Subtarget.h.

References hasSSE2(), and is64Bit().

Referenced by LowerATOMIC_FENCE().

bool llvm::X86Subtarget::hasMMX ( ) const
inline
bool llvm::X86Subtarget::hasMOVBE ( ) const
inline

Definition at line 440 of file X86Subtarget.h.

References HasMOVBE.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasMPX ( ) const
inline

Definition at line 483 of file X86Subtarget.h.

References HasMPX.

bool llvm::X86Subtarget::hasMWAITX ( ) const
inline

Definition at line 456 of file X86Subtarget.h.

References HasMWAITX.

bool llvm::X86Subtarget::hasPCLMUL ( ) const
inline

Definition at line 432 of file X86Subtarget.h.

References HasPCLMUL.

bool llvm::X86Subtarget::hasPFI ( ) const
inline

Definition at line 477 of file X86Subtarget.h.

References HasPFI.

bool llvm::X86Subtarget::hasPKU ( ) const
inline

Definition at line 482 of file X86Subtarget.h.

References HasPKU.

bool llvm::X86Subtarget::hasPOPCNT ( ) const
inline
bool llvm::X86Subtarget::hasPRFCHW ( ) const
inline

Definition at line 453 of file X86Subtarget.h.

References HasPRFCHW.

bool llvm::X86Subtarget::hasRDRAND ( ) const
inline

Definition at line 441 of file X86Subtarget.h.

References HasRDRAND.

bool llvm::X86Subtarget::hasRDSEED ( ) const
inline

Definition at line 454 of file X86Subtarget.h.

References HasRDSEED.

bool llvm::X86Subtarget::hasRTM ( ) const
inline

Definition at line 449 of file X86Subtarget.h.

References HasRTM.

bool llvm::X86Subtarget::hasSHA ( ) const
inline

Definition at line 452 of file X86Subtarget.h.

References HasSHA.

bool X86Subtarget::hasSinCos ( ) const

This function returns true if the target has sincos() routine in its compiler runtime or math libraries.

Definition at line 159 of file X86Subtarget.cpp.

References getTargetTriple(), is64Bit(), llvm::Triple::isMacOSX(), and llvm::Triple::isMacOSXVersionLT().

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasSlowDivide32 ( ) const
inline

Definition at line 469 of file X86Subtarget.h.

References HasSlowDivide32.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasSlowDivide64 ( ) const
inline

Definition at line 470 of file X86Subtarget.h.

References HasSlowDivide64.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasSSE1 ( ) const
inline
bool llvm::X86Subtarget::hasSSE2 ( ) const
inline
bool llvm::X86Subtarget::hasSSE3 ( ) const
inline
bool llvm::X86Subtarget::hasSSE41 ( ) const
inline
bool llvm::X86Subtarget::hasSSE42 ( ) const
inline
bool llvm::X86Subtarget::hasSSE4A ( ) const
inline
bool llvm::X86Subtarget::hasSSEUnalignedMem ( ) const
inline

Definition at line 462 of file X86Subtarget.h.

References HasSSEUnalignedMem.

bool llvm::X86Subtarget::hasSSSE3 ( ) const
inline
bool llvm::X86Subtarget::hasTBM ( ) const
inline

Definition at line 439 of file X86Subtarget.h.

References HasTBM.

Referenced by combineAnd().

bool llvm::X86Subtarget::hasVBMI ( ) const
inline
bool llvm::X86Subtarget::hasVLX ( ) const
inline
bool llvm::X86Subtarget::hasX87 ( ) const
inline

Definition at line 408 of file X86Subtarget.h.

References HasX87.

Referenced by llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::hasXOP ( ) const
inline
bool llvm::X86Subtarget::hasXSAVE ( ) const
inline

Definition at line 428 of file X86Subtarget.h.

References HasXSAVE.

bool llvm::X86Subtarget::hasXSAVEC ( ) const
inline

Definition at line 430 of file X86Subtarget.h.

References HasXSAVEC.

bool llvm::X86Subtarget::hasXSAVEOPT ( ) const
inline

Definition at line 429 of file X86Subtarget.h.

References HasXSAVEOPT.

bool llvm::X86Subtarget::hasXSAVES ( ) const
inline

Definition at line 431 of file X86Subtarget.h.

References HasXSAVES.

bool llvm::X86Subtarget::is16Bit ( ) const
inline

Definition at line 389 of file X86Subtarget.h.

bool llvm::X86Subtarget::is32Bit ( ) const
inline
bool llvm::X86Subtarget::is64Bit ( ) const
inline

Is this x86_64? (disregarding specific ABI / programming model)

Definition at line 381 of file X86Subtarget.h.

Referenced by classifyGlobalFunctionReference(), classifyGlobalReference(), classifyLocalReference(), combineCompareEqual(), combineSIntToFP(), combineStore(), computeBytesPoppedByCalleeForSRet(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::copyPhysReg(), llvm::X86FrameLowering::emitEpilogue(), emitMonitor(), ExpandMOVImmSExti8(), llvm::X86TargetLowering::findRepresentativeClass(), llvm::X86InstrInfo::foldMemoryOperandImpl(), get64BitArgumentGPRs(), get64BitArgumentXMMs(), llvm::X86TargetLowering::getByValTypeAlignment(), getExtendedControlRegister(), llvm::X86InstrInfo::getGlobalBaseReg(), llvm::X86TargetLowering::getIRStackGuard(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), getRetOpcode(), llvm::X86TargetLowering::getSafeStackPointerLocation(), hasMFence(), hasSinCos(), llvm::X86InstrInfo::isCoalescableExtInstr(), llvm::X86TargetLowering::isLegalAddressingMode(), isTargetNaCl32(), isTargetNaCl64(), isXRaySupported(), llvm::X86TargetLowering::isZExtFree(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerBITCAST(), LowerCMP_SWAP(), LowerFSINCOS(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerVACOPY(), printAsmMRegister(), llvm::X86FrameLowering::processFunctionBeforeFrameFinalized(), recoverFramePointer(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), SimplifyShortMoveForm(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), llvm::X86TargetLowering::supportSwiftError(), llvm::X86TargetLowering::useLoadStackGuardNode(), llvm::X86FrameLowering::X86FrameLowering(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().

bool llvm::X86Subtarget::isAtom ( ) const
inline
bool llvm::X86Subtarget::isBTMemSlow ( ) const
inline

Definition at line 457 of file X86Subtarget.h.

References IsBTMemSlow.

bool llvm::X86Subtarget::isCallingConvWin64 ( CallingConv::ID  CC) const
inline
bool X86Subtarget::isLegalToCallImmediateAddr ( ) const

Return true if the subtarget allows calls to immediate address.

Definition at line 166 of file X86Subtarget.cpp.

References llvm::TargetMachine::getRelocationModel(), isTargetELF(), isTargetWin32(), llvm::Reloc::Static, and TM.

bool llvm::X86Subtarget::isOSWindows ( ) const
inline
bool llvm::X86Subtarget::isPICStyleGOT ( ) const
inline
bool llvm::X86Subtarget::isPICStyleRIPRel ( ) const
inline
bool llvm::X86Subtarget::isPICStyleStubPIC ( ) const
inline
bool llvm::X86Subtarget::isPMULLDSlow ( ) const
inline

Definition at line 459 of file X86Subtarget.h.

References IsPMULLDSlow.

Referenced by reduceVMULWidth().

bool llvm::X86Subtarget::isPositionIndependent ( ) const
inline
bool llvm::X86Subtarget::isSHLDSlow ( ) const
inline

Definition at line 458 of file X86Subtarget.h.

References IsSHLDSlow.

Referenced by combineOr().

bool llvm::X86Subtarget::isSLM ( ) const
inline
bool llvm::X86Subtarget::isTarget64BitILP32 ( ) const
inline
bool llvm::X86Subtarget::isTarget64BitLP64 ( ) const
inline
bool llvm::X86Subtarget::isTargetAndroid ( ) const
inline
bool llvm::X86Subtarget::isTargetCOFF ( ) const
inline
bool llvm::X86Subtarget::isTargetCygMing ( ) const
inline
bool llvm::X86Subtarget::isTargetDarwin ( ) const
inline
bool llvm::X86Subtarget::isTargetDragonFly ( ) const
inline
bool llvm::X86Subtarget::isTargetELF ( ) const
inline
bool llvm::X86Subtarget::isTargetFreeBSD ( ) const
inline
bool llvm::X86Subtarget::isTargetGlibc ( ) const
inline
bool llvm::X86Subtarget::isTargetKFreeBSD ( ) const
inline

Definition at line 509 of file X86Subtarget.h.

References llvm::Triple::isOSKFreeBSD(), and TargetTriple.

bool llvm::X86Subtarget::isTargetKnownWindowsMSVC ( ) const
inline
bool llvm::X86Subtarget::isTargetLinux ( ) const
inline
bool llvm::X86Subtarget::isTargetMachO ( ) const
inline
bool llvm::X86Subtarget::isTargetMCU ( ) const
inline

Definition at line 515 of file X86Subtarget.h.

References llvm::Triple::isOSIAMCU(), and TargetTriple.

Referenced by computeBytesPoppedByCalleeForSRet().

bool llvm::X86Subtarget::isTargetNaCl ( ) const
inline

Definition at line 512 of file X86Subtarget.h.

References llvm::Triple::isOSNaCl(), and TargetTriple.

Referenced by isTargetNaCl32(), and isTargetNaCl64().

bool llvm::X86Subtarget::isTargetNaCl32 ( ) const
inline

Definition at line 513 of file X86Subtarget.h.

References is64Bit(), and isTargetNaCl().

bool llvm::X86Subtarget::isTargetNaCl64 ( ) const
inline

Definition at line 514 of file X86Subtarget.h.

References is64Bit(), and isTargetNaCl().

Referenced by llvm::X86FrameLowering::X86FrameLowering().

bool llvm::X86Subtarget::isTargetPS4 ( ) const
inline

Definition at line 502 of file X86Subtarget.h.

References llvm::Triple::isPS4CPU(), and TargetTriple.

bool llvm::X86Subtarget::isTargetSolaris ( ) const
inline

Definition at line 501 of file X86Subtarget.h.

References llvm::Triple::isOSSolaris(), and TargetTriple.

bool llvm::X86Subtarget::isTargetWin32 ( ) const
inline
bool llvm::X86Subtarget::isTargetWin64 ( ) const
inline
bool llvm::X86Subtarget::isTargetWindowsCoreCLR ( ) const
inline
bool llvm::X86Subtarget::isTargetWindowsCygwin ( ) const
inline

Definition at line 529 of file X86Subtarget.h.

References llvm::Triple::isWindowsCygwinEnvironment(), and TargetTriple.

bool llvm::X86Subtarget::isTargetWindowsGNU ( ) const
inline
bool llvm::X86Subtarget::isTargetWindowsItanium ( ) const
inline
bool llvm::X86Subtarget::isTargetWindowsMSVC ( ) const
inline
bool llvm::X86Subtarget::isUnalignedMem16Slow ( ) const
inline
bool llvm::X86Subtarget::isUnalignedMem32Slow ( ) const
inline
virtual bool llvm::X86Subtarget::isXRaySupported ( ) const
inlineoverridevirtual

Definition at line 485 of file X86Subtarget.h.

References is64Bit().

bool llvm::X86Subtarget::LEAusesAG ( ) const
inline

Definition at line 473 of file X86Subtarget.h.

References LEAUsesAG.

bool llvm::X86Subtarget::padShortFunctions ( ) const
inline

Definition at line 471 of file X86Subtarget.h.

References PadShortFunctions.

void llvm::X86Subtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  FS 
)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

void llvm::X86Subtarget::setGISelAccessor ( GISelAccessor GISel)
inline

This object will take onwership of GISelAccessor.

Definition at line 339 of file X86Subtarget.h.

void llvm::X86Subtarget::setPICStyle ( PICStyles::Style  Style)
inline

Definition at line 406 of file X86Subtarget.h.

References PICStyle.

Referenced by X86Subtarget().

bool llvm::X86Subtarget::slowIncDec ( ) const
inline

Definition at line 475 of file X86Subtarget.h.

References SlowIncDec.

bool llvm::X86Subtarget::slowLEA ( ) const
inline

Definition at line 474 of file X86Subtarget.h.

References SlowLEA.

bool llvm::X86Subtarget::useLeaForSP ( ) const
inline

Definition at line 464 of file X86Subtarget.h.

References UseLeaForSP.

bool llvm::X86Subtarget::useSoftFloat ( ) const
inline

Member Data Documentation

bool llvm::X86Subtarget::CallRegIndirect
protected

True if the Calls with memory reference should be converted to a register-based indirect call.

Definition at line 232 of file X86Subtarget.h.

Referenced by callRegIndirect().

std::unique_ptr<GISelAccessor> llvm::X86Subtarget::GISel
protected

Gather the accessor points to GlobalISel-related APIs.

This is used to avoid ifndefs spreading around while GISel is an optional library.

Definition at line 309 of file X86Subtarget.h.

Referenced by getCallLowering(), getInstructionSelector(), getLegalizerInfo(), and getRegBankInfo().

bool llvm::X86Subtarget::HasADX
protected

Processor has ADX instructions.

Definition at line 155 of file X86Subtarget.h.

Referenced by hasADX().

bool llvm::X86Subtarget::HasAES
protected

Target has AES instructions.

Definition at line 92 of file X86Subtarget.h.

Referenced by hasAES().

bool llvm::X86Subtarget::HasBMI
protected

Processor has BMI1 instructions.

Definition at line 137 of file X86Subtarget.h.

Referenced by hasBMI().

bool llvm::X86Subtarget::HasBMI2
protected

Processor has BMI2 instructions.

Definition at line 140 of file X86Subtarget.h.

Referenced by hasBMI2().

bool llvm::X86Subtarget::HasBWI
protected

Processor has AVX-512 Byte and Word instructions.

Definition at line 257 of file X86Subtarget.h.

Referenced by hasBWI().

bool llvm::X86Subtarget::HasCDI
protected

Processor has AVX-512 Conflict Detection Instructions.

Definition at line 251 of file X86Subtarget.h.

Referenced by hasCDI().

bool llvm::X86Subtarget::HasCLFLUSHOPT
protected

Processor supports Flush Cache Line instruction.

Definition at line 281 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasCLWB
protected

Processor supports Cache Line Write Back instruction.

Definition at line 287 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasCMov
protected

True if this processor has conditional move instructions (generally pentium pro+).

Definition at line 80 of file X86Subtarget.h.

Referenced by hasCMov().

bool llvm::X86Subtarget::HasCmpxchg16b
protected

True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips.

Definition at line 197 of file X86Subtarget.h.

Referenced by hasCmpxchg16b().

bool llvm::X86Subtarget::HasDQI
protected

Processor has AVX-512 Doubleword and Quadword instructions.

Definition at line 254 of file X86Subtarget.h.

Referenced by hasDQI().

bool llvm::X86Subtarget::HasERI
protected

Processor has AVX-512 Exponential and Reciprocal Instructions.

Definition at line 248 of file X86Subtarget.h.

Referenced by hasERI().

bool llvm::X86Subtarget::HasF16C
protected

Processor has 16-bit floating point conversion instructions.

Definition at line 128 of file X86Subtarget.h.

Referenced by hasF16C().

bool llvm::X86Subtarget::HasFastLZCNT
protected

True if LZCNT instruction is fast.

Definition at line 224 of file X86Subtarget.h.

Referenced by hasFastLZCNT().

bool llvm::X86Subtarget::HasFastPartialYMMWrite
protected

True if there is no performance penalty to writing only the lower parts of a YMM register without clearing the upper part.

Definition at line 205 of file X86Subtarget.h.

Referenced by hasFastPartialYMMWrite().

bool llvm::X86Subtarget::HasFastScalarFSQRT
protected

True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration.

Definition at line 209 of file X86Subtarget.h.

Referenced by hasFastScalarFSQRT().

bool llvm::X86Subtarget::HasFastVectorFSQRT
protected

True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.

Definition at line 213 of file X86Subtarget.h.

Referenced by hasFastVectorFSQRT().

bool llvm::X86Subtarget::HasFMA
protected

Target has 3-operand fused multiply-add.

Definition at line 110 of file X86Subtarget.h.

Referenced by hasFMA().

bool llvm::X86Subtarget::HasFMA4
protected

Target has 4-operand fused multiply-add.

Definition at line 113 of file X86Subtarget.h.

Referenced by hasFMA(), and hasFMA4().

bool llvm::X86Subtarget::HasFSGSBase
protected

Processor has FS/GS base insturctions.

Definition at line 131 of file X86Subtarget.h.

Referenced by hasFSGSBase().

bool llvm::X86Subtarget::HasFXSR
protected

Target has FXSAVE/FXRESTOR instructions.

Definition at line 95 of file X86Subtarget.h.

Referenced by hasFXSR().

bool llvm::X86Subtarget::HasHLE
protected

Processor has HLE.

Definition at line 152 of file X86Subtarget.h.

Referenced by hasHLE().

bool llvm::X86Subtarget::HasIFMA
protected

Processor has Integer Fused Multiply Add.

Definition at line 146 of file X86Subtarget.h.

Referenced by hasIFMA().

bool llvm::X86Subtarget::HasInvPCId
protected

Processor supports Invalidate Process-Context Identifier.

Definition at line 269 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasLAHFSAHF
protected

Processor has LAHF/SAHF instructions.

Definition at line 167 of file X86Subtarget.h.

Referenced by hasLAHFSAHF().

bool llvm::X86Subtarget::HasLZCNT
protected

Processor has LZCNT instruction.

Definition at line 134 of file X86Subtarget.h.

Referenced by hasLZCNT().

bool llvm::X86Subtarget::HasMOVBE
protected

True if the processor has the MOVBE instruction.

Definition at line 122 of file X86Subtarget.h.

Referenced by hasMOVBE().

bool llvm::X86Subtarget::HasMPX
protected

Processor supports MPX - Memory Protection Extensions.

Definition at line 266 of file X86Subtarget.h.

Referenced by hasMPX().

bool llvm::X86Subtarget::HasMWAITX
protected

Processor has MONITORX/MWAITX instructions.

Definition at line 170 of file X86Subtarget.h.

Referenced by hasMWAITX().

bool llvm::X86Subtarget::HasPCLMUL
protected

Target has carry-less multiplication.

Definition at line 107 of file X86Subtarget.h.

Referenced by hasPCLMUL().

bool llvm::X86Subtarget::HasPCOMMIT
protected

Processor has Persistent Commit feature.

Definition at line 284 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasPFI
protected

Processor has AVX-512 PreFetch Instructions.

Definition at line 245 of file X86Subtarget.h.

Referenced by hasPFI().

bool llvm::X86Subtarget::HasPFPREFETCHWT1
protected

Processor has Prefetch with intent to Write instruction.

Definition at line 173 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasPKU
protected

Processor has PKU extenstions.

Definition at line 263 of file X86Subtarget.h.

Referenced by hasPKU().

bool llvm::X86Subtarget::HasPOPCNT
protected

True if the processor supports POPCNT.

Definition at line 86 of file X86Subtarget.h.

Referenced by hasPOPCNT().

bool llvm::X86Subtarget::HasPRFCHW
protected

Processor has PRFCHW instructions.

Definition at line 161 of file X86Subtarget.h.

Referenced by hasPRFCHW().

bool llvm::X86Subtarget::HasRDRAND
protected

True if the processor has the RDRAND instruction.

Definition at line 125 of file X86Subtarget.h.

Referenced by hasRDRAND().

bool llvm::X86Subtarget::HasRDSEED
protected

Processor has RDSEED instructions.

Definition at line 164 of file X86Subtarget.h.

Referenced by hasRDSEED().

bool llvm::X86Subtarget::HasRTM
protected

Processor has RTM instructions.

Definition at line 149 of file X86Subtarget.h.

Referenced by hasRTM().

bool llvm::X86Subtarget::HasSGX
protected

Processor has Software Guard Extensions.

Definition at line 278 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasSHA
protected

Processor has SHA instructions.

Definition at line 158 of file X86Subtarget.h.

Referenced by hasSHA().

bool llvm::X86Subtarget::HasSlowDivide32
protected

True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible.

Definition at line 217 of file X86Subtarget.h.

Referenced by hasSlowDivide32().

bool llvm::X86Subtarget::HasSlowDivide64
protected

True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible.

Definition at line 221 of file X86Subtarget.h.

Referenced by hasSlowDivide64().

bool llvm::X86Subtarget::HasSMAP
protected

Processor has Supervisor Mode Access Protection.

Definition at line 275 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasSSE4A
protected

True if the processor supports SSE4A instructions.

Definition at line 89 of file X86Subtarget.h.

Referenced by hasSSE4A().

bool llvm::X86Subtarget::HasSSEUnalignedMem
protected

True if SSE operations can have unaligned memory operands.

This may require setting a configuration bit in the processor.

Definition at line 193 of file X86Subtarget.h.

Referenced by hasSSEUnalignedMem().

bool llvm::X86Subtarget::HasTBM
protected

Target has TBM instructions.

Definition at line 119 of file X86Subtarget.h.

Referenced by hasTBM().

bool llvm::X86Subtarget::HasVBMI
protected

Processor has VBMI instructions.

Definition at line 143 of file X86Subtarget.h.

Referenced by hasVBMI().

bool llvm::X86Subtarget::HasVLX
protected

Processor has AVX-512 Vector Length eXtenstions.

Definition at line 260 of file X86Subtarget.h.

Referenced by hasVLX().

bool llvm::X86Subtarget::HasVMFUNC
protected

Processor has VM Functions.

Definition at line 272 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasX86_64
protected

True if the processor supports X86-64 instructions.

Definition at line 83 of file X86Subtarget.h.

bool llvm::X86Subtarget::HasX87
protected

True if the processor supports X87 instructions.

Definition at line 76 of file X86Subtarget.h.

Referenced by hasX87().

bool llvm::X86Subtarget::HasXOP
protected

Target has XOP instructions.

Definition at line 116 of file X86Subtarget.h.

Referenced by hasXOP().

bool llvm::X86Subtarget::HasXSAVE
protected

Target has XSAVE instructions.

Definition at line 98 of file X86Subtarget.h.

Referenced by hasXSAVE().

bool llvm::X86Subtarget::HasXSAVEC
protected

Target has XSAVEC instructions.

Definition at line 102 of file X86Subtarget.h.

Referenced by hasXSAVEC().

bool llvm::X86Subtarget::HasXSAVEOPT
protected

Target has XSAVEOPT instructions.

Definition at line 100 of file X86Subtarget.h.

Referenced by hasXSAVEOPT().

bool llvm::X86Subtarget::HasXSAVES
protected

Target has XSAVES instructions.

Definition at line 104 of file X86Subtarget.h.

Referenced by hasXSAVES().

InstrItineraryData llvm::X86Subtarget::InstrItins
protected

Instruction itineraries for scheduling.

Definition at line 304 of file X86Subtarget.h.

Referenced by getInstrItineraryData().

bool llvm::X86Subtarget::IsBTMemSlow
protected

True if BT (bit test) of memory instructions are slow.

Definition at line 176 of file X86Subtarget.h.

Referenced by isBTMemSlow().

bool llvm::X86Subtarget::IsPMULLDSlow
protected

True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.

Definition at line 183 of file X86Subtarget.h.

Referenced by isPMULLDSlow().

bool llvm::X86Subtarget::IsSHLDSlow
protected

True if SHLD instructions are slow.

Definition at line 179 of file X86Subtarget.h.

Referenced by isSHLDSlow().

bool llvm::X86Subtarget::IsUAMem16Slow
protected

True if unaligned memory accesses of 16-bytes are slow.

Definition at line 186 of file X86Subtarget.h.

Referenced by isUnalignedMem16Slow().

bool llvm::X86Subtarget::IsUAMem32Slow
protected

True if unaligned memory accesses of 32-bytes are slow.

Definition at line 189 of file X86Subtarget.h.

Referenced by isUnalignedMem32Slow().

bool llvm::X86Subtarget::LEAUsesAG
protected

True if the LEA instruction inputs have to be ready at address generation (AG) time.

Definition at line 236 of file X86Subtarget.h.

Referenced by LEAusesAG().

unsigned llvm::X86Subtarget::MaxInlineSizeThreshold
protected

Max.

memset / memcpy size that is turned into rep/movs, rep/stos ops.

Definition at line 298 of file X86Subtarget.h.

Referenced by getMaxInlineSizeThreshold().

bool llvm::X86Subtarget::PadShortFunctions
protected

True if the short functions should be padded to prevent a stall when returning too early.

Definition at line 228 of file X86Subtarget.h.

Referenced by padShortFunctions().

PICStyles::Style llvm::X86Subtarget::PICStyle
protected

Which PIC style to use.

Definition at line 65 of file X86Subtarget.h.

Referenced by getPICStyle(), isPICStyleGOT(), isPICStyleRIPRel(), isPICStyleStubPIC(), and setPICStyle().

bool llvm::X86Subtarget::SlowIncDec
protected

True if INC and DEC instructions are slow when writing to flags.

Definition at line 242 of file X86Subtarget.h.

Referenced by slowIncDec().

bool llvm::X86Subtarget::SlowLEA
protected

True if the LEA instruction with certain arguments is slow.

Definition at line 239 of file X86Subtarget.h.

Referenced by slowLEA().

unsigned llvm::X86Subtarget::stackAlignment
protected

The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 294 of file X86Subtarget.h.

Referenced by getStackAlignment().

Triple llvm::X86Subtarget::TargetTriple
protected
const TargetMachine& llvm::X86Subtarget::TM
protected
bool llvm::X86Subtarget::UseLeaForSP
protected

True if the LEA instruction should be used for adjusting the stack pointer.

This is an optimization for Intel Atom processors.

Definition at line 201 of file X86Subtarget.h.

Referenced by useLeaForSP().

bool llvm::X86Subtarget::UseSoftFloat
protected

Use software floating point for code generation.

Definition at line 290 of file X86Subtarget.h.

Referenced by useSoftFloat().

X863DNowEnum llvm::X86Subtarget::X863DNowLevel
protected

MMX, 3DNow, 3DNow Athlon, or none supported.

Definition at line 73 of file X86Subtarget.h.

Referenced by has3DNow(), has3DNowA(), and hasMMX().

X86ProcFamilyEnum llvm::X86Subtarget::X86ProcFamily
protected

X86 processor family: Intel Atom, and others.

Definition at line 62 of file X86Subtarget.h.

Referenced by isAtom(), and isSLM().

X86SSEEnum llvm::X86Subtarget::X86SSELevel
protected

SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.

Definition at line 70 of file X86Subtarget.h.

Referenced by hasAVX(), hasAVX2(), hasAVX512(), hasSSE1(), hasSSE2(), hasSSE3(), hasSSE41(), hasSSE42(), and hasSSSE3().


The documentation for this class was generated from the following files: