38 #define DEBUG_TYPE "mips-isel"
53 processFunctionAfterISel(MF);
69 bool MipsDAGToDAGISel::selectAddrRegImm(
SDValue Addr,
SDValue &Base,
75 bool MipsDAGToDAGISel::selectAddrDefault(
SDValue Addr,
SDValue &Base,
87 bool MipsDAGToDAGISel::selectIntAddr11MM(
SDValue Addr,
SDValue &Base,
93 bool MipsDAGToDAGISel::selectIntAddr12MM(
SDValue Addr,
SDValue &Base,
99 bool MipsDAGToDAGISel::selectIntAddr16MM(
SDValue Addr,
SDValue &Base,
105 bool MipsDAGToDAGISel::selectIntAddrLSL2MM(
SDValue Addr,
SDValue &Base,
111 bool MipsDAGToDAGISel::selectIntAddrSImm10(
SDValue Addr,
SDValue &Base,
117 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(
SDValue Addr,
SDValue &Base,
123 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(
SDValue Addr,
SDValue &Base,
129 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(
SDValue Addr,
SDValue &Base,
141 bool MipsDAGToDAGISel::selectAddr16SP(
SDValue Addr,
SDValue &Base,
147 bool MipsDAGToDAGISel::selectVSplat(
SDNode *
N,
APInt &Imm,
148 unsigned MinSizeInBits)
const {
153 bool MipsDAGToDAGISel::selectVSplatUimm1(
SDValue N,
SDValue &Imm)
const {
158 bool MipsDAGToDAGISel::selectVSplatUimm2(
SDValue N,
SDValue &Imm)
const {
163 bool MipsDAGToDAGISel::selectVSplatUimm3(
SDValue N,
SDValue &Imm)
const {
168 bool MipsDAGToDAGISel::selectVSplatUimm4(
SDValue N,
SDValue &Imm)
const {
173 bool MipsDAGToDAGISel::selectVSplatUimm5(
SDValue N,
SDValue &Imm)
const {
178 bool MipsDAGToDAGISel::selectVSplatUimm6(
SDValue N,
SDValue &Imm)
const {
183 bool MipsDAGToDAGISel::selectVSplatUimm8(
SDValue N,
SDValue &Imm)
const {
188 bool MipsDAGToDAGISel::selectVSplatSimm5(
SDValue N,
SDValue &Imm)
const {
193 bool MipsDAGToDAGISel::selectVSplatUimmPow2(
SDValue N,
SDValue &Imm)
const {
198 bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(
SDValue N,
SDValue &Imm)
const {
203 bool MipsDAGToDAGISel::selectVSplatMaskL(
SDValue N,
SDValue &Imm)
const {
208 bool MipsDAGToDAGISel::selectVSplatMaskR(
SDValue N,
SDValue &Imm)
const {
215 void MipsDAGToDAGISel::Select(
SDNode *Node) {
244 cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
246 "Unexpected unaligned loads/stores.");
255 bool MipsDAGToDAGISel::
256 SelectInlineAsmMemoryOperand(
const SDValue &
Op,
unsigned ConstraintID,
257 std::vector<SDValue> &OutOps) {
259 switch(ConstraintID) {
266 OutOps.push_back(Op);
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
void setNodeId(int Id)
Set unique node id.
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
const TargetLowering * getTargetLowering() const
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
static unsigned getAlignment(GlobalVariable *GV)
const DataLayout & getDataLayout() const
SDNode * getNode() const
get the SDNode which holds the desired result
const MipsSubtarget * Subtarget
Keep a pointer to the MipsSubtarget around so that we can make the right decision when generating cod...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void dump() const
Dump this node, for debugging.
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
SDNode * getGlobalBaseReg()
getGlobalBaseReg - Output the instructions required to put the GOT address into a register...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getRegister(unsigned Reg, EVT VT)
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...