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LLVM
4.0.0
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#include <TargetRegisterInfo.h>
Public Types | |
| typedef const MCPhysReg * | iterator |
| typedef const MCPhysReg * | const_iterator |
| typedef const MVT::SimpleValueType * | vt_iterator |
| typedef const TargetRegisterClass *const * | sc_iterator |
Public Member Functions | |
| unsigned | getID () const |
| Return the register class ID number. More... | |
| iterator | begin () const |
| begin/end - Return all of the registers in this class. More... | |
| iterator | end () const |
| unsigned | getNumRegs () const |
| Return the number of registers in this class. More... | |
| iterator_range < SmallVectorImpl< MCPhysReg > ::const_iterator > | getRegisters () const |
| unsigned | getRegister (unsigned i) const |
| Return the specified register in the class. More... | |
| bool | contains (unsigned Reg) const |
| Return true if the specified register is included in this register class. More... | |
| bool | contains (unsigned Reg1, unsigned Reg2) const |
| Return true if both registers are in this class. More... | |
| unsigned | getSize () const |
| Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a spilled copy of this register. More... | |
| unsigned | getAlignment () const |
| Return the minimum required alignment for a register of this class. More... | |
| int | getCopyCost () const |
| Return the cost of copying a value between two registers in this class. More... | |
| bool | isAllocatable () const |
| Return true if this register class may be used to create virtual registers. More... | |
| bool | hasType (MVT vt) const |
| Return true if this TargetRegisterClass has the ValueType vt. More... | |
| vt_iterator | vt_begin () const |
| vt_begin / vt_end - Loop over all of the value types that can be represented by values in this register class. More... | |
| vt_iterator | vt_end () const |
| bool | hasSubClass (const TargetRegisterClass *RC) const |
| Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass. More... | |
| bool | hasSubClassEq (const TargetRegisterClass *RC) const |
| Returns true if RC is a sub-class of or equal to this class. More... | |
| bool | hasSuperClass (const TargetRegisterClass *RC) const |
| Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass. More... | |
| bool | hasSuperClassEq (const TargetRegisterClass *RC) const |
| Returns true if RC is a super-class of or equal to this class. More... | |
| const uint32_t * | getSubClassMask () const |
| Returns a bit vector of subclasses, including this one. More... | |
| const uint16_t * | getSuperRegIndices () const |
| Returns a 0-terminated list of sub-register indices that project some super-register class into this register class. More... | |
| sc_iterator | getSuperClasses () const |
| Returns a NULL-terminated list of super-classes. More... | |
| bool | isASubClass () const |
| Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass. More... | |
| ArrayRef< MCPhysReg > | getRawAllocationOrder (const MachineFunction &MF) const |
| Returns the preferred order for allocating registers from this register class in MF. More... | |
| LaneBitmask | getLaneMask () const |
| Returns the combination of all lane masks of register in this class. More... | |
Public Attributes | |
| const MCRegisterClass * | MC |
| const vt_iterator | VTs |
| const uint32_t * | SubClassMask |
| const uint16_t * | SuperRegIndices |
| const LaneBitmask | LaneMask |
| const uint8_t | AllocationPriority |
| Classes with a higher priority value are assigned first by register allocators using a greedy heuristic. More... | |
| const bool | HasDisjunctSubRegs |
| Whether the class supports two (or more) disjunct subregister indices. More... | |
| const bool | CoveredBySubRegs |
| Whether a combination of subregisters can cover every register in the class. More... | |
| const sc_iterator | SuperClasses |
| ArrayRef< MCPhysReg >(* | OrderFunc )(const MachineFunction &) |
Definition at line 39 of file TargetRegisterInfo.h.
Definition at line 42 of file TargetRegisterInfo.h.
Definition at line 41 of file TargetRegisterInfo.h.
Definition at line 44 of file TargetRegisterInfo.h.
Definition at line 43 of file TargetRegisterInfo.h.
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begin/end - Return all of the registers in this class.
Definition at line 68 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::begin(), and MC.
Referenced by llvm::PPCInstrInfo::DefinesPredicate(), getRawAllocationOrder(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
Return true if the specified register is included in this register class.
This does not include virtual registers.
Definition at line 86 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::contains(), and MC.
Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), llvm::SystemZInstrInfo::convertToThreeAddress(), copyHint(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::PPCInstrInfo::insertSelect(), llvm::CoalescerPair::setRegisters(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().
Return true if both registers are in this class.
Definition at line 91 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::contains(), and MC.
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Definition at line 69 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::end(), and MC.
Referenced by llvm::PPCInstrInfo::DefinesPredicate(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::TargetLowering::getRegForInlineAsmConstraint(), GetRegistersForValue(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
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Return the minimum required alignment for a register of this class.
Definition at line 100 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getAlignment(), and MC.
Referenced by llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), and llvm::RegScavenger::scavengeRegister().
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Return the cost of copying a value between two registers in this class.
A negative number means the register class is very expensive to copy e.g. status flag register classes.
Definition at line 105 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getCopyCost(), and MC.
Referenced by CheckForPhysRegDependency().
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Return the register class ID number.
Definition at line 64 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getID(), and MC.
Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::RegisterBank::covers(), llvm::HexagonRegisterInfo::getCallerSavedRegs(), GetCostForDef(), llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::ARMRegisterBankInfo::getRegBankFromRegClass(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::X86RegisterInfo::getRegPressureLimit(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), hasSubClassEq(), INITIALIZE_PASS(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::regPressureDelta(), and llvm::ResourcePriorityQueue::scheduledNode().
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Returns the combination of all lane masks of register in this class.
The lane masks of the registers are the combination of all lane masks of their subregisters. Returns 1 if there are no subregisters.
Definition at line 220 of file TargetRegisterInfo.h.
References LaneMask.
Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::getMaxLaneMaskForVReg().
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Return the number of registers in this class.
Definition at line 72 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getNumRegs(), and MC.
Referenced by llvm::RegisterClassInfo::computePSetLimit(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::R600InstrInfo::getIndirectIndexBegin(), and getRawAllocationOrder().
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Returns the preferred order for allocating registers from this register class in MF.
The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.
The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.
By default, this method returns all registers in the class.
Definition at line 213 of file TargetRegisterInfo.h.
References begin(), getNumRegs(), llvm::makeArrayRef(), and OrderFunc.
Referenced by getAllocatableSetForRC().
Return the specified register in the class.
Definition at line 80 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getRegister(), and MC.
Referenced by llvm::R600InstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), and llvm::tryFoldSPUpdateIntoPushPop().
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Definition at line 75 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::begin(), llvm::MCRegisterClass::end(), llvm::make_range(), and MC.
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Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a spilled copy of this register.
Definition at line 97 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::getSize(), and MC.
Referenced by llvm::DwarfExpression::AddMachineReg(), llvm::PPCFrameLowering::addScavengingSpillSlot(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), assignCalleeSavedSpillSlots(), computeIndirectRegAndOffset(), llvm::NVPTXInstrInfo::copyPhysReg(), llvm::SIInstrInfo::copyPhysReg(), llvm::MipsFunctionInfo::createEhDataRegsFI(), llvm::XCoreFunctionInfo::createEHSpillSlot(), llvm::XCoreFunctionInfo::createFPSpillSlot(), llvm::MipsFunctionInfo::createISRRegFI(), llvm::XCoreFunctionInfo::createLRSpillSlot(), llvm::MipsSEFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::MipsFrameLowering::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::TargetRegisterInfo::getCommonSuperRegClass(), llvm::SIRegisterInfo::getEquivalentSGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::MipsFunctionInfo::getMoveF64ViaSpillFI(), llvm::SIInstrInfo::getMovOpcode(), getMOVRELDPseudo(), llvm::SIInstrInfo::getOpSize(), llvm::BitTracker::MachineEvaluator::getRegBitWidth(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::SIRegisterInfo::hasVGPRs(), llvm::X86InstrInfo::insertSelect(), llvm::X86InstrInfo::loadRegFromAddr(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::AArch64InstrInfo::loadRegFromStackSlot(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::loadRegFromStackSlot(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::XCoreFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::SIRegisterInfo::restoreSGPR(), llvm::RegScavenger::scavengeRegister(), llvm::SIInstrInfo::shouldClusterMemOps(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::SIRegisterInfo::spillSGPR(), llvm::X86InstrInfo::storeRegToAddr(), llvm::SIInstrInfo::storeRegToStackSlot(), llvm::AArch64InstrInfo::storeRegToStackSlot(), llvm::ARMBaseInstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::storeRegToStackSlot(), llvm::X86InstrInfo::unfoldMemoryOperand(), and llvm::RegisterBank::verify().
Returns a bit vector of subclasses, including this one.
The vector is indexed by class IDs.
To use it, consider the returned array as a chunk of memory that contains an array of bits of size NumRegClasses. Each 32-bit chunk contains a bitset of the ID of the subclasses in big-endian style. I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumRegClasses - 1 ... ] Where the number represents the class ID and XXX bits that should be ignored.
See the implementation of hasSubClassEq for an example of how it can be used.
Definition at line 170 of file TargetRegisterInfo.h.
References SubClassMask.
Referenced by llvm::TargetRegisterInfo::getAllocatableClass(), llvm::TargetRegisterInfo::getCommonSubClass(), and llvm::TargetRegisterInfo::getMatchingSuperRegClass().
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Returns a NULL-terminated list of super-classes.
The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.
Definition at line 189 of file TargetRegisterInfo.h.
References SuperClasses.
Referenced by llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), and llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass().
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Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.
The list has an entry for each Idx such that:
There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)
Definition at line 182 of file TargetRegisterInfo.h.
References SuperRegIndices.
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Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition at line 133 of file TargetRegisterInfo.h.
References hasSubClassEq().
Referenced by llvm::TargetRegisterInfo::getMinimalPhysRegClass(), and hasSuperClass().
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Returns true if RC is a sub-class of or equal to this class.
Definition at line 138 of file TargetRegisterInfo.h.
References getID(), and SubClassMask.
Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), hasSubClass(), hasSuperClassEq(), UpdateOperandRegClass(), and llvm::RegisterBank::verify().
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Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition at line 145 of file TargetRegisterInfo.h.
References hasSubClass().
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Returns true if RC is a super-class of or equal to this class.
Definition at line 150 of file TargetRegisterInfo.h.
References hasSubClassEq().
Referenced by llvm::PPCInstrInfo::getOperandLatency(), isFPR64(), isFRClass(), and isGRClass().
Return true if this TargetRegisterClass has the ValueType vt.
Definition at line 112 of file TargetRegisterInfo.h.
References i, llvm::MVT::Other, and VTs.
Referenced by llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), firstCommonClass(), llvm::AVRRegisterInfo::getLargestLegalSuperClass(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MipsSEInstrInfo::loadRegFromStack(), llvm::AVRInstrInfo::loadRegFromStackSlot(), llvm::MipsSEInstrInfo::storeRegToStack(), and llvm::AVRInstrInfo::storeRegToStackSlot().
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Return true if this register class may be used to create virtual registers.
Definition at line 109 of file TargetRegisterInfo.h.
References llvm::MCRegisterClass::isAllocatable(), and MC.
Referenced by llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetRegisterInfo::getAllocatableClass(), getAllocatableSetForRC(), and llvm::MachineRegisterInfo::setRegClass().
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Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition at line 195 of file TargetRegisterInfo.h.
References SuperClasses.
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vt_begin / vt_end - Loop over all of the value types that can be represented by values in this register class.
Definition at line 121 of file TargetRegisterInfo.h.
References VTs.
Referenced by GetRegistersForValue(), getRegTy(), llvm::TargetLoweringBase::isLegalRC(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 125 of file TargetRegisterInfo.h.
References I, llvm::MVT::Other, and VTs.
Referenced by getRegTy(), and llvm::TargetLoweringBase::isLegalRC().
| const uint8_t llvm::TargetRegisterClass::AllocationPriority |
Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.
The value is in the range [0,63].
Definition at line 54 of file TargetRegisterInfo.h.
Whether a combination of subregisters can cover every register in the class.
See also the CoveredBySubRegs description in Target.td.
Definition at line 59 of file TargetRegisterInfo.h.
Whether the class supports two (or more) disjunct subregister indices.
Definition at line 56 of file TargetRegisterInfo.h.
Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::shouldTrackSubRegLiveness().
| const LaneBitmask llvm::TargetRegisterClass::LaneMask |
Definition at line 51 of file TargetRegisterInfo.h.
Referenced by llvm::rdf::DataFlowGraph::alias(), getLaneMask(), llvm::rdf::RegisterAggr::normalize(), llvm::rdf::DataFlowGraph::normalizeRef(), and llvm::rdf::CopyPropagation::run().
| const MCRegisterClass* llvm::TargetRegisterClass::MC |
Definition at line 47 of file TargetRegisterInfo.h.
Referenced by begin(), contains(), end(), getAlignment(), getCopyCost(), getID(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getNumRegs(), llvm::TargetRegisterInfo::getRegClassName(), getRegister(), getRegisters(), llvm::SIRegisterInfo::getRegSplitParts(), getSize(), and isAllocatable().
| ArrayRef<MCPhysReg>(* llvm::TargetRegisterClass::OrderFunc)(const MachineFunction &) |
Definition at line 61 of file TargetRegisterInfo.h.
Referenced by getRawAllocationOrder().
Definition at line 49 of file TargetRegisterInfo.h.
Referenced by getSubClassMask(), and hasSubClassEq().
| const sc_iterator llvm::TargetRegisterClass::SuperClasses |
Definition at line 60 of file TargetRegisterInfo.h.
Referenced by getSuperClasses(), and isASubClass().
| const uint16_t* llvm::TargetRegisterClass::SuperRegIndices |
Definition at line 50 of file TargetRegisterInfo.h.
Referenced by getSuperRegIndices().
| const vt_iterator llvm::TargetRegisterClass::VTs |
Definition at line 48 of file TargetRegisterInfo.h.
Referenced by hasType(), vt_begin(), and vt_end().
1.8.6