LLVM  4.0.0
llvm::SISubtarget Member List

This is the complete list of members for llvm::SISubtarget, including all inherited members.

AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, const TargetMachine &TM)llvm::AMDGPUSubtarget
CaymanISAllvm::AMDGPUSubtargetprotected
CFALUBugllvm::AMDGPUSubtargetprotected
CIInstsllvm::AMDGPUSubtargetprotected
debuggerEmitPrologue() const llvm::SISubtargetinline
DebuggerEmitProloguellvm::AMDGPUSubtargetprotected
debuggerInsertNops() const llvm::SISubtargetinline
DebuggerInsertNopsllvm::AMDGPUSubtargetprotected
debuggerReserveRegs() const llvm::SISubtargetinline
DebuggerReserveRegsllvm::AMDGPUSubtargetprotected
debuggerSupported() const llvm::SISubtargetinline
DumpCodellvm::AMDGPUSubtargetprotected
dumpCode() const llvm::AMDGPUSubtargetinline
enableIEEEBit(const MachineFunction &MF) const llvm::AMDGPUSubtargetinline
EnableLoadStoreOptllvm::AMDGPUSubtargetprotected
enableMachineScheduler() const overridellvm::AMDGPUSubtargetinline
EnablePromoteAllocallvm::AMDGPUSubtargetprotected
enableSIScheduler() const llvm::SISubtargetinline
EnableSISchedulerllvm::AMDGPUSubtargetprotected
enableSubRegLiveness() const overridellvm::AMDGPUSubtargetinline
EnableUnsafeDSOffsetFoldingllvm::AMDGPUSubtargetprotected
EnableVGPRSpillingllvm::AMDGPUSubtargetprotected
EnableXNACKllvm::AMDGPUSubtargetprotected
EVERGREEN enum valuellvm::AMDGPUSubtarget
FastFMAF32llvm::AMDGPUSubtargetprotected
FeatureDisablellvm::AMDGPUSubtargetprotected
FIXED_SGPR_COUNT_FOR_INIT_BUG enum valuellvm::SISubtarget
FlatAddressSpacellvm::AMDGPUSubtargetprotected
FlatForGloballlvm::AMDGPUSubtargetprotected
FP16Denormalsllvm::AMDGPUSubtargetprotected
FP32Denormalsllvm::AMDGPUSubtargetprotected
FP64llvm::AMDGPUSubtargetprotected
FP64Denormalsllvm::AMDGPUSubtargetprotected
FPExceptionsllvm::AMDGPUSubtargetprotected
GCN1Encodingllvm::AMDGPUSubtargetprotected
GCN3Encodingllvm::AMDGPUSubtargetprotected
Genllvm::AMDGPUSubtargetprotected
Generation enum namellvm::AMDGPUSubtarget
getAlignmentForImplicitArgPtr() const llvm::AMDGPUSubtargetinline
getCallLowering() const overridellvm::SISubtargetinline
getEUsPerCU() const llvm::AMDGPUSubtargetinline
getExplicitKernelArgOffset(const MachineFunction &MF) const llvm::AMDGPUSubtargetinline
getFlatWorkGroupSizes(const Function &F) const llvm::AMDGPUSubtarget
getFrameLowering() const overridellvm::SISubtargetinlinevirtual
getGeneration() const llvm::AMDGPUSubtargetinline
getImplicitArgNumBytes(const MachineFunction &MF) const llvm::AMDGPUSubtargetinline
getInstrInfo() const overridellvm::SISubtargetinlinevirtual
getInstrItineraryData() const overridellvm::AMDGPUSubtargetinline
getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const llvm::SISubtarget
getLDSBankCount() const llvm::AMDGPUSubtargetinline
getLocalMemorySize() const llvm::AMDGPUSubtargetinline
getMaxFlatWorkGroupSize() const llvm::AMDGPUSubtargetinline
getMaxLocalMemSizeWithWaveCount(unsigned WaveCount) const llvm::AMDGPUSubtarget
getMaxNumSGPRs() const llvm::SISubtarget
getMaxNumUserSGPRs() const llvm::SISubtargetinline
getMaxPrivateElementSize() const llvm::AMDGPUSubtargetinline
getMaxWavesPerCU() const llvm::AMDGPUSubtargetinline
getMaxWavesPerCU(unsigned FlatWorkGroupSize) const llvm::AMDGPUSubtargetinline
getMaxWavesPerEU() const llvm::AMDGPUSubtargetinline
getMaxWavesPerEU(unsigned FlatWorkGroupSize) const llvm::AMDGPUSubtargetinline
getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const llvm::AMDGPUSubtargetinline
getMinFlatWorkGroupSize() const llvm::AMDGPUSubtargetinline
getMinWavesPerEU() const llvm::AMDGPUSubtargetinline
getOccupancyWithLocalMemSize(uint32_t Bytes) const llvm::AMDGPUSubtarget
getOccupancyWithNumSGPRs(unsigned SGPRs) const llvm::SISubtarget
getOccupancyWithNumVGPRs(unsigned VGPRs) const llvm::SISubtarget
getRegisterInfo() const overridellvm::SISubtargetinlinevirtual
getScalarizeGlobalBehavior() const llvm::AMDGPUSubtargetinline
getSelectionDAGInfo() const overridellvm::AMDGPUSubtargetinline
getStackAlignment() const llvm::AMDGPUSubtargetinline
getTargetLowering() const overridellvm::SISubtargetinlinevirtual
getWavefrontSize() const llvm::AMDGPUSubtargetinline
getWavesPerEU(const Function &F) const llvm::AMDGPUSubtarget
getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const llvm::AMDGPUSubtargetinline
HalfRate64Opsllvm::AMDGPUSubtargetprotected
has12DWordStoreHazard() const llvm::SISubtargetinline
Has16BitInstsllvm::AMDGPUSubtargetprotected
has16BitInsts() const llvm::AMDGPUSubtargetinline
hasAddr64() const llvm::AMDGPUSubtargetinline
hasBCNT(unsigned Size) const llvm::AMDGPUSubtargetinline
hasBFE() const llvm::AMDGPUSubtargetinline
hasBFI() const llvm::AMDGPUSubtargetinline
hasBFM() const llvm::AMDGPUSubtargetinline
hasBORROW() const llvm::AMDGPUSubtargetinline
hasCARRY() const llvm::AMDGPUSubtargetinline
hasCaymanISA() const llvm::AMDGPUSubtargetinline
hasFastFMAF32() const llvm::AMDGPUSubtargetinline
hasFFBH() const llvm::AMDGPUSubtargetinline
hasFFBL() const llvm::AMDGPUSubtargetinline
hasFlatAddressSpace() const llvm::SISubtargetinline
hasFP16Denormals() const llvm::AMDGPUSubtargetinline
hasFP32Denormals() const llvm::AMDGPUSubtargetinline
hasFP64Denormals() const llvm::AMDGPUSubtargetinline
hasFPExceptions() const llvm::AMDGPUSubtargetinline
hasHalfRate64Ops() const llvm::AMDGPUSubtargetinline
hasHWFP64() const llvm::AMDGPUSubtargetinline
hasInv2PiInlineImm() const llvm::SISubtargetinline
HasInv2PiInlineImmllvm::AMDGPUSubtargetprotected
HasMovrelllvm::AMDGPUSubtargetprotected
hasMovrel() const llvm::SISubtargetinline
hasMulI24() const llvm::AMDGPUSubtargetinline
hasMulU24() const llvm::AMDGPUSubtargetinline
hasScalarCompareEq64() const llvm::SISubtargetinline
hasScalarStores() const llvm::SISubtargetinline
HasScalarStoresllvm::AMDGPUSubtargetprotected
hasSGPRInitBug() const llvm::SISubtargetinline
hasSMemRealTime() const llvm::SISubtargetinline
HasSMemRealTimellvm::AMDGPUSubtargetprotected
hasUnalignedBufferAccess() const llvm::AMDGPUSubtargetinline
hasUnalignedScratchAccess() const llvm::AMDGPUSubtargetinline
HasVertexCachellvm::AMDGPUSubtargetprotected
HasVGPRIndexModellvm::AMDGPUSubtargetprotected
hasVGPRIndexMode() const llvm::SISubtargetinline
initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)llvm::AMDGPUSubtarget
InstrItinsllvm::AMDGPUSubtargetprotected
isAmdCodeObjectV2(const MachineFunction &MF) const llvm::AMDGPUSubtargetinline
isAmdHsaOS() const llvm::AMDGPUSubtargetinline
IsaVersionllvm::AMDGPUSubtargetprotected
ISAVersion0_0_0 enum valuellvm::AMDGPUSubtarget
ISAVersion7_0_0 enum valuellvm::AMDGPUSubtarget
ISAVersion7_0_1 enum valuellvm::AMDGPUSubtarget
ISAVersion7_0_2 enum valuellvm::AMDGPUSubtarget
ISAVersion8_0_0 enum valuellvm::AMDGPUSubtarget
ISAVersion8_0_1 enum valuellvm::AMDGPUSubtarget
ISAVersion8_0_2 enum valuellvm::AMDGPUSubtarget
ISAVersion8_0_3 enum valuellvm::AMDGPUSubtarget
ISAVersion8_0_4 enum valuellvm::AMDGPUSubtarget
ISAVersion8_1_0 enum valuellvm::AMDGPUSubtarget
IsGCNllvm::AMDGPUSubtargetprotected
isMesa3DOS() const llvm::AMDGPUSubtargetinline
isMesaGfxShader(const MachineFunction &MF) const llvm::AMDGPUSubtargetinline
isMesaKernel(const MachineFunction &MF) const llvm::AMDGPUSubtargetinline
isOpenCLEnv() const llvm::AMDGPUSubtargetinline
isPromoteAllocaEnabled() const llvm::AMDGPUSubtargetinline
isVGPRSpillingEnabled(const Function &F) const llvm::SISubtarget
isXNACKEnabled() const llvm::AMDGPUSubtargetinline
LDSBankCountllvm::AMDGPUSubtargetprotected
loadStoreOptEnabled() const llvm::SISubtargetinline
LocalMemorySizellvm::AMDGPUSubtargetprotected
MaxPrivateElementSizellvm::AMDGPUSubtargetprotected
needWaitcntBeforeBarrier() const llvm::SISubtargetinline
NORTHERN_ISLANDS enum valuellvm::AMDGPUSubtarget
overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const overridellvm::SISubtarget
ParseSubtargetFeatures(StringRef CPU, StringRef FS)llvm::AMDGPUSubtarget
R600 enum valuellvm::AMDGPUSubtarget
R600ALUInstllvm::AMDGPUSubtargetprotected
R700 enum valuellvm::AMDGPUSubtarget
ScalarizeGloballlvm::AMDGPUSubtargetprotected
SEA_ISLANDS enum valuellvm::AMDGPUSubtarget
setGISelAccessor(GISelAccessor &GISel)llvm::SISubtargetinline
setScalarizeGlobalBehavior(bool b)llvm::AMDGPUSubtargetinline
SGPRInitBugllvm::AMDGPUSubtargetprotected
SISubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)llvm::SISubtarget
SOUTHERN_ISLANDS enum valuellvm::AMDGPUSubtarget
TargetTriplellvm::AMDGPUSubtargetprotected
TexVTXClauseSizellvm::AMDGPUSubtargetprotected
TSInfollvm::AMDGPUSubtargetprotected
UnalignedBufferAccessllvm::AMDGPUSubtargetprotected
UnalignedScratchAccessllvm::AMDGPUSubtargetprotected
unsafeDSOffsetFoldingEnabled() const llvm::AMDGPUSubtargetinline
useFlatForGlobal() const llvm::AMDGPUSubtargetinline
VOLCANIC_ISLANDS enum valuellvm::AMDGPUSubtarget
WavefrontSizellvm::AMDGPUSubtargetprotected
~AMDGPUSubtarget() overridellvm::AMDGPUSubtarget