LLVM  4.0.0
GCNHazardRecognizer.h
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1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines hazard recognizers for scheduling on GCN processors.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
15 #define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
16 
17 #include "llvm/ADT/STLExtras.h"
19 #include <list>
20 
21 namespace llvm {
22 
23 class MachineFunction;
24 class MachineInstr;
25 class ScheduleDAG;
26 class SIInstrInfo;
27 class SISubtarget;
28 
30  // This variable stores the instruction that has been emitted this cycle. It
31  // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
32  // called.
33  MachineInstr *CurrCycleInstr;
34  std::list<MachineInstr*> EmittedInstrs;
35  const MachineFunction &MF;
36  const SISubtarget &ST;
37 
38  int getWaitStatesSince(function_ref<bool(MachineInstr *)> IsHazard);
39  int getWaitStatesSinceDef(unsigned Reg,
40  function_ref<bool(MachineInstr *)> IsHazardDef =
41  [](MachineInstr *) { return true; });
42  int getWaitStatesSinceSetReg(function_ref<bool(MachineInstr *)> IsHazard);
43 
44  int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
45  int checkSMRDHazards(MachineInstr *SMRD);
46  int checkVMEMHazards(MachineInstr* VMEM);
47  int checkDPPHazards(MachineInstr *DPP);
48  int checkDivFMasHazards(MachineInstr *DivFMas);
49  int checkGetRegHazards(MachineInstr *GetRegInstr);
50  int checkSetRegHazards(MachineInstr *SetRegInstr);
51  int createsVALUHazard(const MachineInstr &MI);
52  int checkVALUHazards(MachineInstr *VALU);
53  int checkRWLaneHazards(MachineInstr *RWLane);
54  int checkRFEHazards(MachineInstr *RFE);
55 public:
57  // We can only issue one instruction per cycle.
58  bool atIssueLimit() const override { return true; }
59  void EmitInstruction(SUnit *SU) override;
60  void EmitInstruction(MachineInstr *MI) override;
61  HazardType getHazardType(SUnit *SU, int Stalls) override;
62  void EmitNoop() override;
63  unsigned PreEmitNoops(SUnit *SU) override;
64  unsigned PreEmitNoops(MachineInstr *) override;
65  void AdvanceCycle() override;
66  void RecedeCycle() override;
67 };
68 
69 } // end namespace llvm
70 
71 #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
An efficient, type-erasing, non-owning reference to a callable.
Definition: STLExtras.h:83
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned PreEmitNoops(SUnit *SU) override
PreEmitNoops - This callback is invoked prior to emitting an instruction.
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
GCNHazardRecognizer(const MachineFunction &MF)
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool atIssueLimit() const override
atIssueLimit - Return true if no more instructions may be issued in this cycle.
IRTranslator LLVM IR MI
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:244