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LLVM
4.0.0
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This class provides the information for the target register banks. More...
#include <AArch64RegisterBankInfo.h>
Public Member Functions | |
| AArch64RegisterBankInfo (const TargetRegisterInfo &TRI) | |
| unsigned | copyCost (const RegisterBank &A, const RegisterBank &B, unsigned Size) const override |
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B. More... | |
| const RegisterBank & | getRegBankFromRegClass (const TargetRegisterClass &RC) const override |
Get a register bank that covers RC. More... | |
| InstructionMappings | getInstrAlternativeMappings (const MachineInstr &MI) const override |
Get the alternative mappings for MI. More... | |
| InstructionMapping | getInstrMapping (const MachineInstr &MI) const override |
Get the mapping of the different operands of MI on the register bank. More... | |
Public Member Functions inherited from llvm::RegisterBankInfo | |
| virtual | ~RegisterBankInfo () |
| const RegisterBank & | getRegBank (unsigned ID) const |
Get the register bank identified by ID. More... | |
| const RegisterBank * | getRegBank (unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const |
Get the register bank of Reg. More... | |
| unsigned | getNumRegBanks () const |
| Get the total number of register banks. More... | |
Additional Inherited Members | |
Public Types inherited from llvm::RegisterBankInfo | |
| typedef SmallVector < InstructionMapping, 4 > | InstructionMappings |
| Convenient type to represent the alternatives for mapping an instruction. More... | |
Static Public Member Functions inherited from llvm::RegisterBankInfo | |
| static const TargetRegisterClass * | constrainGenericRegister (unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) |
Constrain the (possibly generic) virtual register Reg to RC. More... | |
Public Attributes inherited from llvm::RegisterBankInfo | |
| struct llvm::RegisterBankInfo::PartialMapping | ScalarAddx2 |
| VectorAdd | |
Get the possible mapping for MI. More... | |
Static Public Attributes inherited from llvm::RegisterBankInfo | |
| static const unsigned | DefaultMappingID = UINT_MAX |
| Identifier used when the related instruction mapping instance is generated by target independent code. More... | |
| static const unsigned | InvalidMappingID = UINT_MAX - 1 |
| Identifier used when the related instruction mapping instance is generated by the default constructor. More... | |
Protected Member Functions inherited from llvm::RegisterBankInfo | |
| RegisterBankInfo (RegisterBank **RegBanks, unsigned NumRegBanks) | |
Create a RegisterBankInfo that can accomodate up to NumRegBanks RegisterBank instances. More... | |
| RegisterBankInfo () | |
| This constructor is meaningless. More... | |
| RegisterBank & | getRegBank (unsigned ID) |
Get the register bank identified by ID. More... | |
| InstructionMapping | getInstrMappingImpl (const MachineInstr &MI) const |
Try to get the mapping of MI. More... | |
| const PartialMapping & | getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
| Get the uniquely generated PartialMapping for the given arguments. More... | |
| const RegisterBank * | getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const |
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any. More... | |
| const ValueMapping & | getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
| Methods to get a uniquely generated ValueMapping. More... | |
| const ValueMapping & | getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const |
| Get the ValueMapping for the given arguments. More... | |
| template<typename Iterator > | |
| const ValueMapping * | getOperandsMapping (Iterator Begin, Iterator End) const |
| Methods to get a uniquely generated array of ValueMapping. More... | |
| const ValueMapping * | getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const |
Get the uniquely generated array of ValueMapping for the elements of OpdsMapping. More... | |
| const ValueMapping * | getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const |
| Get the uniquely generated array of ValueMapping for the given arguments. More... | |
Static Protected Member Functions inherited from llvm::RegisterBankInfo | |
| static void | applyDefaultMapping (const OperandsMapper &OpdMapper) |
| Helper method to apply something that is like the default mapping. More... | |
Protected Attributes inherited from llvm::RegisterBankInfo | |
| RegisterBank ** | RegBanks |
| Hold the set of supported register banks. More... | |
| unsigned | NumRegBanks |
| Total number of register banks. More... | |
| DenseMap< unsigned, const PartialMapping * > | MapOfPartialMappings |
| Keep dynamically allocated PartialMapping in a separate map. More... | |
| DenseMap< unsigned, const ValueMapping * > | MapOfValueMappings |
| Keep dynamically allocated ValueMapping in a separate map. More... | |
| DenseMap< unsigned, ValueMapping * > | MapOfOperandsMappings |
| Keep dynamically allocated array of ValueMapping in a separate map. More... | |
This class provides the information for the target register banks.
Definition at line 37 of file AArch64RegisterBankInfo.h.
| AArch64RegisterBankInfo::AArch64RegisterBankInfo | ( | const TargetRegisterInfo & | TRI | ) |
Definition at line 33 of file AArch64RegisterBankInfo.cpp.
References assert(), llvm::AArch64::CCRRegBank, llvm::AArch64::CCRRegBankID, CHECK_PARTIALMAP, CHECK_VALUEMAP, CHECK_VALUEMAP_3OPS, CHECK_VALUEMAP_CROSSREGCPY, llvm::RegisterBank::covers(), FPR, llvm::AArch64::FPRRegBank, llvm::AArch64::FPRRegBankID, llvm::RegisterBankInfo::getRegBank(), llvm::TargetRegisterInfo::getRegClass(), llvm::RegisterBank::getSize(), llvm::GPR, llvm::AArch64::GPRRegBank, llvm::AArch64::GPRRegBankID, and llvm::verify().
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overridevirtual |
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Since register banks may cover different size, Size specifies what will be the size in bits that will be copied around.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 203 of file AArch64RegisterBankInfo.cpp.
References llvm::RegisterBankInfo::copyCost(), llvm::AArch64::FPRRegBank, and llvm::AArch64::GPRRegBank.
Referenced by getInstrAlternativeMappings(), and getInstrMapping().
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overridevirtual |
Get the alternative mappings for MI.
Alternative in the sense different from getInstrMapping.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 262 of file AArch64RegisterBankInfo.cpp.
References copyCost(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::AArch64::FPRRegBank, llvm::RegisterBankInfo::getInstrAlternativeMappings(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::getSizeInBits(), llvm::MachineFunction::getSubtarget(), getValueMapping(), llvm::AArch64::GPRRegBank, and MRI.
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overridevirtual |
Get the mapping of the different operands of MI on the register bank.
This mapping should be the direct translation of MI. In other words, when MI is mapped with the returned mapping, only the register banks of the operands of MI need to be updated. In particular, neither the opcode nor the type of MI needs to be updated for this direct mapping.
The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.
For instance, if MI is a vector add, the mapping should not be a scalarization of the add.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 442 of file AArch64RegisterBankInfo.cpp.
References copyCost(), llvm::RegisterBankInfo::DefaultMappingID, llvm::AArch64::FPRRegBank, llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), getValueMapping(), llvm::AArch64::GPRRegBank, isPreISelGenericFloatingPointOpcode(), llvm::isPreISelGenericOpcode(), llvm::MachineOperand::isReg(), llvm::RegisterBankInfo::InstructionMapping::isValid(), llvm::LLT::isVector(), and llvm::RegisterBankInfo::InstructionMapping::setOperandsMapping().
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overridevirtual |
Get a register bank that covers RC.
RC is a user-defined register class (as opposed as one generated by TableGen).Reimplemented from llvm::RegisterBankInfo.
Definition at line 224 of file AArch64RegisterBankInfo.cpp.
References llvm::AArch64::CCRRegBankID, llvm::AArch64::FPRRegBankID, llvm::TargetRegisterClass::getID(), llvm::RegisterBankInfo::getRegBank(), llvm::AArch64::GPRRegBankID, and llvm_unreachable.
1.8.6