35 #define GET_REGINFO_MC_DESC
36 #include "X86GenRegisterInfo.inc"
38 #define GET_INSTRINFO_MC_DESC
39 #include "X86GenInstrInfo.inc"
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "X86GenSubtargetInfo.inc"
47 FS =
"+64bit-mode,-32bit-mode,-16bit-mode";
49 FS =
"-64bit-mode,+32bit-mode,-16bit-mode";
51 FS =
"-64bit-mode,-32bit-mode,+16bit-mode";
70 for (
unsigned Reg = X86::NoRegister + 1;
Reg < X86::NUM_TARGET_REGS; ++
Reg) {
77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH,
78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX,
79 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX,
80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI,
82 unsigned CVLowRegStart = 1;
89 unsigned FP0Start = 128;
90 for (
unsigned I = 0; I < 8; ++
I)
94 unsigned CVXMM0Start = 154;
95 for (
unsigned I = 0; I < 8; ++
I)
99 unsigned CVXMM8Start = 252;
100 for (
unsigned I = 0; I < 8; ++
I)
106 unsigned CVX64RegStart = 324;
108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX,
109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP,
110 X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13,
111 X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B,
112 X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W,
113 X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W,
114 X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D,
115 X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3,
116 X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9,
117 X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
128 ArchFS = (
Twine(ArchFS) +
"," + FS).str();
133 std::string CPUName = CPU;
137 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
142 InitX86MCInstrInfo(X);
159 const Triple &TheTriple) {
184 int stackGrowth = is64Bit ? -8 : -4;
187 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
193 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
214 unsigned SyntaxVariant,
218 if (SyntaxVariant == 0)
220 if (SyntaxVariant == 1)
285 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
287 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
289 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
291 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
293 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
295 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
297 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
299 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
305 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
307 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
309 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
311 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
313 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
315 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
317 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
319 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
321 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
323 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
325 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
327 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
329 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
331 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
333 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
335 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
342 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
344 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
346 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
348 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
350 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
352 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
354 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
356 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
358 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
360 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
362 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
364 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
366 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
368 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
370 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
372 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
378 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
380 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
382 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
384 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
386 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
388 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
390 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
392 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
394 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
396 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
398 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
400 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
402 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
404 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
406 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
408 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
414 case X86::AH:
case X86::AL:
case X86::AX:
case X86::EAX:
case X86::RAX:
416 case X86::DH:
case X86::DL:
case X86::DX:
case X86::EDX:
case X86::RDX:
418 case X86::CH:
case X86::CL:
case X86::CX:
case X86::ECX:
case X86::RCX:
420 case X86::BH:
case X86::BL:
case X86::BX:
case X86::EBX:
case X86::RBX:
422 case X86::SIL:
case X86::SI:
case X86::ESI:
case X86::RSI:
424 case X86::DIL:
case X86::DI:
case X86::EDI:
case X86::RDI:
426 case X86::BPL:
case X86::BP:
case X86::EBP:
case X86::RBP:
428 case X86::SPL:
case X86::SP:
case X86::ESP:
case X86::RSP:
430 case X86::R8B:
case X86::R8W:
case X86::R8D:
case X86::R8:
432 case X86::R9B:
case X86::R9W:
case X86::R9D:
case X86::R9:
434 case X86::R10B:
case X86::R10W:
case X86::R10D:
case X86::R10:
436 case X86::R11B:
case X86::R11W:
case X86::R11D:
case X86::R11:
438 case X86::R12B:
case X86::R12W:
case X86::R12D:
case X86::R12:
440 case X86::R13B:
case X86::R13W:
case X86::R13D:
case X86::R13:
442 case X86::R14B:
case X86::R14W:
case X86::R14D:
case X86::R14:
444 case X86::R15B:
case X86::R15W:
case X86::R15D:
case X86::R15:
452 assert(Res != 0 &&
"Unexpected register or VT");
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
MCStreamer * createX86WinCOFFStreamer(MCContext &C, MCAsmBackend &AB, raw_pwrite_stream &OS, MCCodeEmitter *CE, bool RelaxAll, bool IncrementalLinkerCompatible)
Construct an X86 Windows COFF machine code streamer which will generate PE/COFF format object files...
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static MCRegisterInfo * createX86MCRegisterInfo(const Triple &TT)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
std::string ParseX86Triple(const Triple &TT)
static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, CodeModel::Model &CM)
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Reg
All possible values of the reg field in the ModR/M byte.
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Context object for machine code objects.
static MCRelocationInfo * createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx)
void addInitialFrameState(const MCCFIInstruction &Inst)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
void LLVMInitializeX86TargetMC()
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
static bool is64Bit(const char *name)
Interface to description of machine instruction set.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Create MCExprs from relocations found in an object file.
bool isWindowsCoreCLREnvironment() const
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
Triple - Helper class for working with autoconf configuration names.
MCSubtargetInfo * createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a X86 MCSubtargetInfo instance.
unsigned getX86SubSuperRegisterOrZero(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
static MCAsmInfo * createX86MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static MCInstrInfo * createX86MCInstrInfo()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
MCSubtargetInfo - Generic base class for all target subtargets.
Target & getTheX86_32Target()
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
bool isWindowsItaniumEnvironment() const
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target...
StringRef - Represent a constant reference to a string, i.e.
static MCInstrAnalysis * createX86MCInstrAnalysis(const MCInstrInfo *Info)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
static MCInstPrinter * createX86MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Target & getTheX86_64Target()
void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg)
mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register number mapping.