16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
126 if (
const auto *BO = dyn_cast<BinaryWithFlagsSDNode>(Op))
127 return BO->Flags.hasNoSignedZeros();
150 EVT ExtVT)
const override;
156 unsigned AS)
const override;
179 SDValue CC, DAGCombinerInfo &DCI) const;
187 int &RefinementSteps,
bool &UseOneConstNR,
188 bool Reciprocal)
const override;
190 int &RefinementSteps)
const override;
202 unsigned Depth = 0)
const override;
205 unsigned Depth = 0)
const override;
213 unsigned Reg,
EVT VT)
const;
227 namespace AMDGPUISD {
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
const TargetMachine & getTargetMachine() const
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const
Function Alias Analysis Results
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
Pointer to the start of the shader's constant data.
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const AMDGPUSubtarget * Subtarget
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
MVT - Machine Value Type.
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool shouldCombineMemoryType(EVT VT) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isLoadBitCastBeneficial(EVT, EVT) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On archi...
SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
CCState - This class holds information needed while lowering arguments and return values...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
An SDNode that represents everything that will be needed to construct a MachineInstr.
SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
Class for arbitrary precision integers.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
void AnalyzeReturn(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
bool mayIgnoreSignedZero(SDValue Op) const
This file describes how to lower LLVM code to machine code.
bool isSelectSupported(SelectSupportKind) const override
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const