LLVM  4.0.0
CalcSpillWeights.cpp
Go to the documentation of this file.
1 //===------------------------ CalcSpillWeights.cpp ------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
17 #include "llvm/Support/Debug.h"
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "calcspillweights"
25 
27  MachineFunction &MF,
28  VirtRegMap *VRM,
29  const MachineLoopInfo &MLI,
30  const MachineBlockFrequencyInfo &MBFI,
32  DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
33  << "********** Function: " << MF.getName() << '\n');
34 
36  VirtRegAuxInfo VRAI(MF, LIS, VRM, MLI, MBFI, norm);
37  for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
39  if (MRI.reg_nodbg_empty(Reg))
40  continue;
42  }
43 }
44 
45 // Return the preferred allocation register for reg, given a COPY instruction.
46 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
47  const TargetRegisterInfo &tri,
48  const MachineRegisterInfo &mri) {
49  unsigned sub, hreg, hsub;
50  if (mi->getOperand(0).getReg() == reg) {
51  sub = mi->getOperand(0).getSubReg();
52  hreg = mi->getOperand(1).getReg();
53  hsub = mi->getOperand(1).getSubReg();
54  } else {
55  sub = mi->getOperand(1).getSubReg();
56  hreg = mi->getOperand(0).getReg();
57  hsub = mi->getOperand(0).getSubReg();
58  }
59 
60  if (!hreg)
61  return 0;
62 
64  return sub == hsub ? hreg : 0;
65 
66  const TargetRegisterClass *rc = mri.getRegClass(reg);
67 
68  // Only allow physreg hints in rc.
69  if (sub == 0)
70  return rc->contains(hreg) ? hreg : 0;
71 
72  // reg:sub should match the physreg hreg.
73  return tri.getMatchingSuperReg(hreg, sub, rc);
74 }
75 
76 // Check if all values in LI are rematerializable
77 static bool isRematerializable(const LiveInterval &LI,
78  const LiveIntervals &LIS,
79  VirtRegMap *VRM,
80  const TargetInstrInfo &TII) {
81  unsigned Reg = LI.reg;
82  unsigned Original = VRM ? VRM->getOriginal(Reg) : 0;
84  I != E; ++I) {
85  const VNInfo *VNI = *I;
86  if (VNI->isUnused())
87  continue;
88  if (VNI->isPHIDef())
89  return false;
90 
92  assert(MI && "Dead valno in interval");
93 
94  // Trace copies introduced by live range splitting. The inline
95  // spiller can rematerialize through these copies, so the spill
96  // weight must reflect this.
97  if (VRM) {
98  while (MI->isFullCopy()) {
99  // The copy destination must match the interval register.
100  if (MI->getOperand(0).getReg() != Reg)
101  return false;
102 
103  // Get the source register.
104  Reg = MI->getOperand(1).getReg();
105 
106  // If the original (pre-splitting) registers match this
107  // copy came from a split.
109  VRM->getOriginal(Reg) != Original)
110  return false;
111 
112  // Follow the copy live-in value.
113  const LiveInterval &SrcLI = LIS.getInterval(Reg);
114  LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
115  VNI = SrcQ.valueIn();
116  assert(VNI && "Copy from non-existing value");
117  if (VNI->isPHIDef())
118  return false;
119  MI = LIS.getInstructionFromIndex(VNI->def);
120  assert(MI && "Dead valno in interval");
121  }
122  }
123 
124  if (!TII.isTriviallyReMaterializable(*MI, LIS.getAliasAnalysis()))
125  return false;
126  }
127  return true;
128 }
129 
130 void
132  MachineRegisterInfo &mri = MF.getRegInfo();
133  const TargetRegisterInfo &tri = *MF.getSubtarget().getRegisterInfo();
134  MachineBasicBlock *mbb = nullptr;
135  MachineLoop *loop = nullptr;
136  bool isExiting = false;
137  float totalWeight = 0;
138  unsigned numInstr = 0; // Number of instructions using li
140 
141  // Find the best physreg hint and the best virtreg hint.
142  float bestPhys = 0, bestVirt = 0;
143  unsigned hintPhys = 0, hintVirt = 0;
144 
145  // Don't recompute a target specific hint.
146  bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
147 
148  // Don't recompute spill weight for an unspillable register.
149  bool Spillable = li.isSpillable();
150 
152  I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
153  I != E; ) {
154  MachineInstr *mi = &*(I++);
155  numInstr++;
156  if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
157  continue;
158  if (!visited.insert(mi).second)
159  continue;
160 
161  float weight = 1.0f;
162  if (Spillable) {
163  // Get loop info for mi.
164  if (mi->getParent() != mbb) {
165  mbb = mi->getParent();
166  loop = Loops.getLoopFor(mbb);
167  isExiting = loop ? loop->isLoopExiting(mbb) : false;
168  }
169 
170  // Calculate instr weight.
171  bool reads, writes;
172  std::tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
173  weight = LiveIntervals::getSpillWeight(writes, reads, &MBFI, *mi);
174 
175  // Give extra weight to what looks like a loop induction variable update.
176  if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
177  weight *= 3;
178 
179  totalWeight += weight;
180  }
181 
182  // Get allocation hints from copies.
183  if (noHint || !mi->isCopy())
184  continue;
185  unsigned hint = copyHint(mi, li.reg, tri, mri);
186  if (!hint)
187  continue;
188  // Force hweight onto the stack so that x86 doesn't add hidden precision,
189  // making the comparison incorrectly pass (i.e., 1 > 1 == true??).
190  //
191  // FIXME: we probably shouldn't use floats at all.
192  volatile float hweight = Hint[hint] += weight;
194  if (hweight > bestPhys && mri.isAllocatable(hint)) {
195  bestPhys = hweight;
196  hintPhys = hint;
197  }
198  } else {
199  if (hweight > bestVirt) {
200  bestVirt = hweight;
201  hintVirt = hint;
202  }
203  }
204  }
205 
206  Hint.clear();
207 
208  // Always prefer the physreg hint.
209  if (unsigned hint = hintPhys ? hintPhys : hintVirt) {
210  mri.setRegAllocationHint(li.reg, 0, hint);
211  // Weakly boost the spill weight of hinted registers.
212  totalWeight *= 1.01F;
213  }
214 
215  // If the live interval was already unspillable, leave it that way.
216  if (!Spillable)
217  return;
218 
219  // Mark li as unspillable if all live ranges are tiny and the interval
220  // is not live at any reg mask. If the interval is live at a reg mask
221  // spilling may be required.
222  if (li.isZeroLength(LIS.getSlotIndexes()) &&
223  !li.isLiveAtIndexes(LIS.getRegMaskSlots())) {
224  li.markNotSpillable();
225  return;
226  }
227 
228  // If all of the definitions of the interval are re-materializable,
229  // it is a preferred candidate for spilling.
230  // FIXME: this gets much more complicated once we support non-trivial
231  // re-materialization.
232  if (isRematerializable(li, LIS, VRM, *MF.getSubtarget().getInstrInfo()))
233  totalWeight *= 0.5F;
234 
235  li.weight = normalize(totalWeight, li.getSize(), numInstr);
236 }
bool isFullCopy() const
Definition: MachineInstr.h:810
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
ArrayRef< SlotIndex > getRegMaskSlots() const
getRegMaskSlots - Returns a sorted array of slot indices of all instructions with register mask opera...
const unsigned reg
Definition: LiveInterval.h:656
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
size_t i
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
vni_iterator vni_begin()
Definition: LiveInterval.h:213
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:754
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
bool isLiveAtIndexes(ArrayRef< SlotIndex > Slots) const
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
bool isLoopExiting(const BlockT *BB) const
True if terminator in the block can branch to another block that is outside of the current loop...
Definition: LoopInfo.h:160
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
float(* NormalizingFn)(float, unsigned, unsigned)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
Result of a LiveRange query.
Definition: LiveInterval.h:86
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getSize() const
getSize - Returns the sum of sizes of all the LiveRange's.
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:77
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, VirtRegMap *VRM, const TargetInstrInfo &TII)
static bool sub(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
Subtracts the integer array y from the integer array x.
Definition: APInt.cpp:274
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:216
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
static unsigned copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:777
bool isImplicitDef() const
Definition: MachineInstr.h:788
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
#define rc(i)
SlotIndexes * getSlotIndexes() const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:516
unsigned const MachineRegisterInfo * MRI
unsigned getOriginal(unsigned VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting...
Definition: VirtRegMap.h:151
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
bool isCopy() const
Definition: MachineInstr.h:807
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:74
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, VirtRegMap *VRM, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:824
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:759
LiveInterval & getInterval(unsigned Reg)
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &Instr)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isZeroLength(SlotIndexes *Indexes) const
Returns true if the live range is zero length, i.e.
Definition: LiveInterval.h:561
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
AliasAnalysis * getAliasAnalysis() const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:101
vni_iterator vni_end()
Definition: LiveInterval.h:214
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.