LLVM  4.0.0
Macros | Enumerations | Functions | Variables
AArch64InstrInfo.cpp File Reference
#include "AArch64InstrInfo.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include "AArch64GenInstrInfo.inc"
Include dependency graph for AArch64InstrInfo.cpp:

Go to the source code of this file.

Macros

#define GET_INSTRINFO_CTOR_DTOR
 

Enumerations

enum  AccessKind { AK_Write = 0x01, AK_Read = 0x10, AK_All = 0x11 }
 
enum  FMAInstKind { FMAInstKind::Default, FMAInstKind::Indexed, FMAInstKind::Accumulator }
 

Functions

static void parseCondBranch (MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
 
static unsigned getBranchDisplacementBits (unsigned Opc)
 
static unsigned removeCopies (const MachineRegisterInfo &MRI, unsigned VReg)
 
static unsigned canFoldIntoCSel (const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewVReg=nullptr)
 
static bool canBeExpandedToORR (const MachineInstr &MI, unsigned BitSize)
 Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx. More...
 
static bool UpdateOperandRegClass (MachineInstr &Instr)
 
static unsigned convertFlagSettingOpcode (const MachineInstr &MI)
 Return the opcode that does not set flags when possible - otherwise return the original opcode. More...
 
static bool areCFlagsAccessedBetweenInstrs (MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI, const AccessKind AccessToCheck=AK_All)
 True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To. More...
 
static unsigned sForm (MachineInstr &Instr)
 Get opcode of S version of Instr. More...
 
static bool areCFlagsAliveInSuccessors (MachineBasicBlock *MBB)
 Check if AArch64::NZCV should be alive in successors of MBB. More...
 
static AArch64CC::CondCode findCondCodeUsedByInstr (const MachineInstr &Instr)
 Find a condition code used by the instruction. More...
 
static UsedNZCV getUsedNZCV (AArch64CC::CondCode CC)
 
static bool isADDSRegImm (unsigned Opcode)
 
static bool isSUBSRegImm (unsigned Opcode)
 
static bool canInstrSubstituteCmpInstr (MachineInstr *MI, MachineInstr *CmpInstr, const TargetRegisterInfo *TRI)
 Check if CmpInstr can be substituted by MI. More...
 
static bool scaleOffset (unsigned Opc, int64_t &Offset)
 
static bool canPairLdStOpc (unsigned FirstOpc, unsigned SecondOpc)
 
static const MachineInstrBuilderAddSubReg (const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
 
static bool forwardCopyWillClobberTuple (unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
 
static bool isCombineInstrSettingFlag (unsigned Opc)
 
static bool isCombineInstrCandidate32 (unsigned Opc)
 
static bool isCombineInstrCandidate64 (unsigned Opc)
 
static bool isCombineInstrCandidateFP (const MachineInstr &Inst)
 
static bool isCombineInstrCandidate (unsigned Opc)
 
static bool canCombine (MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc, unsigned ZeroReg=0, bool CheckZeroReg=false)
 
static bool canCombineWithMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
 
static bool canCombineWithFMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc)
 
static bool getMaddPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
 Find instructions that can be turned into madd. More...
 
static bool getFMAPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
 Floating-Point Support. More...
 
static MachineInstrgenFusedMultiply (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind=FMAInstKind::Default)
 genFusedMultiply - Generate fused multiply instructions. More...
 
static MachineInstrgenMaddR (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr * > &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
 genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V More...
 

Variables

static const
MachineMemOperand::Flags 
MOSuppressPair
 
static cl::opt< unsignedTBZDisplacementBits ("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
 
static cl::opt< unsignedCBZDisplacementBits ("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
 
static cl::opt< unsignedBCCDisplacementBits ("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))
 

Macro Definition Documentation

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 51 of file AArch64InstrInfo.cpp.

Enumeration Type Documentation

enum AccessKind
Enumerator
AK_Write 
AK_Read 
AK_All 

Definition at line 961 of file AArch64InstrInfo.cpp.

enum FMAInstKind
strong
Enumerator
Default 
Indexed 
Accumulator 

Definition at line 3561 of file AArch64InstrInfo.cpp.

Function Documentation

static const MachineInstrBuilder& AddSubReg ( const MachineInstrBuilder MIB,
unsigned  Reg,
unsigned  SubIdx,
unsigned  State,
const TargetRegisterInfo TRI 
)
static
static bool areCFlagsAccessedBetweenInstrs ( MachineBasicBlock::iterator  From,
MachineBasicBlock::iterator  To,
const TargetRegisterInfo TRI,
const AccessKind  AccessToCheck = AK_All 
)
static

True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.

Note: If From and To are from different blocks it's assumed CC are accessed on the path.

Definition at line 972 of file AArch64InstrInfo.cpp.

References AK_Read, AK_Write, assert(), llvm::find_if(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), MI, llvm::MachineInstr::modifiesRegister(), and llvm::MachineInstr::readsRegister().

Referenced by canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().

static bool areCFlagsAliveInSuccessors ( MachineBasicBlock MBB)
static

Check if AArch64::NZCV should be alive in successors of MBB.

Definition at line 1088 of file AArch64InstrInfo.cpp.

References llvm::MachineBasicBlock::successors().

Referenced by canInstrSubstituteCmpInstr().

static bool canBeExpandedToORR ( const MachineInstr MI,
unsigned  BitSize 
)
static

Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.

Definition at line 666 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::processLogicalImmediate().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

static bool canCombine ( MachineBasicBlock MBB,
MachineOperand MO,
unsigned  CombineOpc,
unsigned  ZeroReg = 0,
bool  CheckZeroReg = false 
)
static
static bool canCombineWithFMUL ( MachineBasicBlock MBB,
MachineOperand MO,
unsigned  MulOpc 
)
static

Definition at line 3181 of file AArch64InstrInfo.cpp.

References canCombine().

Referenced by getFMAPatterns().

static bool canCombineWithMUL ( MachineBasicBlock MBB,
MachineOperand MO,
unsigned  MulOpc,
unsigned  ZeroReg 
)
static

Definition at line 3174 of file AArch64InstrInfo.cpp.

References canCombine().

Referenced by getMaddPatterns().

static unsigned canFoldIntoCSel ( const MachineRegisterInfo MRI,
unsigned  VReg,
unsigned NewVReg = nullptr 
)
static
static bool canInstrSubstituteCmpInstr ( MachineInstr MI,
MachineInstr CmpInstr,
const TargetRegisterInfo TRI 
)
static

Check if CmpInstr can be substituted by MI.

CmpInstr can be substituted:

  • CmpInstr is either 'ADDS vreg, 0' or 'SUBS vreg, 0'
  • and, MI and CmpInstr are from the same MachineBB
  • and, condition flags are not alive in successors of the CmpInstr parent
  • and, if MI opcode is the S form there must be no defs of flags between MI and CmpInstr or if MI opcode is not the S form there must be neither defs of flags nor uses of flags between MI and CmpInstr.
  • and C/V flags are not used after CmpInstr

Definition at line 1208 of file AArch64InstrInfo.cpp.

References AK_All, AK_Write, areCFlagsAccessedBetweenInstrs(), areCFlagsAliveInSuccessors(), assert(), E, findCondCodeUsedByInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), getUsedNZCV(), I, llvm::MachineBasicBlock::instr_end(), llvm::AArch64CC::Invalid, isADDSRegImm(), isSUBSRegImm(), llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), and sForm().

static bool canPairLdStOpc ( unsigned  FirstOpc,
unsigned  SecondOpc 
)
static

Definition at line 1845 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

static unsigned convertFlagSettingOpcode ( const MachineInstr MI)
static

Return the opcode that does not set flags when possible - otherwise return the original opcode.

The caller is responsible to do the actual substitution and legality checking.

Definition at line 916 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::definesRegister(), and llvm::MachineInstr::getOpcode().

Referenced by getMaddPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

static AArch64CC::CondCode findCondCodeUsedByInstr ( const MachineInstr Instr)
static

Find a condition code used by the instruction.

Returns AArch64CC::Invalid if either the instruction does not use condition codes or we don't optimize CmpInstr in the presence of such instructions.

Definition at line 1119 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64CC::Invalid.

Referenced by canInstrSubstituteCmpInstr().

static bool forwardCopyWillClobberTuple ( unsigned  DestReg,
unsigned  SrcReg,
unsigned  NumRegs 
)
static

Definition at line 2012 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple().

static MachineInstr* genFusedMultiply ( MachineFunction MF,
MachineRegisterInfo MRI,
const TargetInstrInfo TII,
MachineInstr Root,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
unsigned  IdxMulOpd,
unsigned  MaddOpc,
const TargetRegisterClass RC,
FMAInstKind  kind = FMAInstKind::Default 
)
static

genFusedMultiply - Generate fused multiply instructions.

This function supports both integer and floating point instructions. A typical example: F|MUL I=A,B,0 F|ADD R,I,C ==> F|MADD R,A,B,C

Parameters
Rootis the F|ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the F|MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the f|madd instruction

Definition at line 3575 of file AArch64InstrInfo.cpp.

References Accumulator, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), Default, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), Indexed, llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

static MachineInstr* genMaddR ( MachineFunction MF,
MachineRegisterInfo MRI,
const TargetInstrInfo TII,
MachineInstr Root,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
unsigned  IdxMulOpd,
unsigned  MaddOpc,
unsigned  VR,
const TargetRegisterClass RC 
)
static

genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V

Parameters
Rootis the ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the madd instruction
VRis a virtual register that holds the value of an ADD operand (V in the example above).

Definition at line 3640 of file AArch64InstrInfo.cpp.

References assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

static unsigned getBranchDisplacementBits ( unsigned  Opc)
static
static bool getFMAPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns 
)
static
static bool getMaddPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns 
)
static
static UsedNZCV getUsedNZCV ( AArch64CC::CondCode  CC)
static
static bool isADDSRegImm ( unsigned  Opcode)
static

Definition at line 1189 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr().

static bool isCombineInstrCandidate ( unsigned  Opc)
static

Definition at line 3138 of file AArch64InstrInfo.cpp.

References isCombineInstrCandidate32(), and isCombineInstrCandidate64().

Referenced by getMaddPatterns().

static bool isCombineInstrCandidate32 ( unsigned  Opc)
static

Definition at line 3078 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

static bool isCombineInstrCandidate64 ( unsigned  Opc)
static

Definition at line 3097 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

static bool isCombineInstrCandidateFP ( const MachineInstr Inst)
static
static bool isCombineInstrSettingFlag ( unsigned  Opc)
static

Definition at line 3059 of file AArch64InstrInfo.cpp.

Referenced by getMaddPatterns().

static bool isSUBSRegImm ( unsigned  Opcode)
static

Definition at line 1193 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr().

static void parseCondBranch ( MachineInstr LastInst,
MachineBasicBlock *&  Target,
SmallVectorImpl< MachineOperand > &  Cond 
)
static
static unsigned removeCopies ( const MachineRegisterInfo MRI,
unsigned  VReg 
)
static
static bool scaleOffset ( unsigned  Opc,
int64_t &  Offset 
)
static

Definition at line 1811 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

static unsigned sForm ( MachineInstr Instr)
static

Get opcode of S version of Instr.

If Instr is S version its opcode is returned. AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version or we are not interested in it.

Definition at line 1055 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by canInstrSubstituteCmpInstr().

static bool UpdateOperandRegClass ( MachineInstr Instr)
static

Variable Documentation

cl::opt<unsigned> BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))
static
cl::opt<unsigned> CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
static
const MachineMemOperand::Flags MOSuppressPair
static
Initial value:
=
MachineMemOperand::MOTargetFlag1

Definition at line 54 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::isLdStPairSuppressed(), and llvm::AArch64InstrInfo::suppressLdStPair().

cl::opt<unsigned> TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
static