29 #define DEBUG_TYPE "mccodeemitter"
33 X86MCCodeEmitter(
const X86MCCodeEmitter &) =
delete;
34 void operator=(
const X86MCCodeEmitter &) =
delete;
39 : MCII(mcii), Ctx(ctx) {
42 ~X86MCCodeEmitter()
override {}
58 bool Is16BitMemOperand(
const MCInst &
MI,
unsigned Op,
64 if (is16BitMode(STI) && BaseReg.
getReg() == 0 &&
67 if ((BaseReg.
getReg() != 0 &&
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.
getReg())) ||
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.
getReg())))
75 unsigned GetX86RegNum(
const MCOperand &MO)
const {
76 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg()) & 0x7;
79 unsigned getX86RegEncoding(
const MCInst &MI,
unsigned OpNum)
const {
80 return Ctx.getRegisterInfo()->getEncodingValue(
85 bool isREXExtendedReg(
const MCInst &MI,
unsigned OpNum)
const {
86 return (getX86RegEncoding(MI, OpNum) >> 3) & 1;
89 void EmitByte(uint8_t
C,
unsigned &CurByte,
raw_ostream &OS)
const {
94 void EmitConstant(uint64_t Val,
unsigned Size,
unsigned &CurByte,
97 for (
unsigned i = 0;
i != Size; ++
i) {
98 EmitByte(Val & 255, CurByte, OS);
107 int ImmOffset = 0)
const;
109 inline static uint8_t ModRMByte(
unsigned Mod,
unsigned RegOpcode,
111 assert(Mod < 4 && RegOpcode < 8 && RM < 8 &&
"ModRM Fields out of range!");
112 return RM | (RegOpcode << 3) | (Mod << 6);
115 void EmitRegModRMByte(
const MCOperand &ModRMReg,
unsigned RegOpcodeFld,
117 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
120 void EmitSIBByte(
unsigned SS,
unsigned Index,
unsigned Base,
123 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
126 void emitMemModRMByte(
const MCInst &MI,
unsigned Op,
unsigned RegOpcodeField,
127 uint64_t TSFlags,
bool Rex,
unsigned &CurByte,
135 void EmitVEXOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
int MemOperand,
139 void EmitSegmentOverridePrefix(
unsigned &CurByte,
unsigned SegOperand,
142 bool emitOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
int MemOperand,
146 uint8_t DetermineREXPrefix(
const MCInst &MI, uint64_t TSFlags,
155 return new X86MCCodeEmitter(MCII, Ctx);
161 return Value == (int8_t)Value;
168 "Compressed 8-bit displacement is only valid for EVEX inst.");
172 if (CD8_Scale == 0) {
177 unsigned Mask = CD8_Scale - 1;
178 assert((CD8_Scale & Mask) == 0 &&
"Invalid memory object size.");
181 Value /= (int)CD8_Scale;
182 bool Ret = (Value == (int8_t)Value);
210 if ((BaseReg.
getReg() != 0 &&
211 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.
getReg())) ||
212 (IndexReg.
getReg() != 0 &&
213 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.
getReg())))
215 if (BaseReg.
getReg() == X86::EIP) {
216 assert(IndexReg.
getReg() == 0 &&
"Invalid eip-based address.");
229 if ((BaseReg.
getReg() != 0 &&
230 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.
getReg())) ||
231 (IndexReg.
getReg() != 0 &&
232 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.
getReg())))
251 const MCExpr *RHS =
nullptr;
263 if (S.
getName() !=
"_GLOBAL_OFFSET_TABLE_")
278 void X86MCCodeEmitter::
282 const MCExpr *Expr =
nullptr;
283 if (DispOp.
isImm()) {
289 EmitConstant(DispOp.
getImm()+ImmOffset, Size, CurByte, OS);
346 EmitConstant(0, Size, CurByte, OS);
349 void X86MCCodeEmitter::emitMemModRMByte(
const MCInst &
MI,
unsigned Op,
350 unsigned RegOpcodeField,
351 uint64_t TSFlags,
bool Rex,
359 unsigned BaseReg = Base.
getReg();
363 if (BaseReg == X86::RIP ||
364 BaseReg == X86::EIP) {
365 assert(is64BitMode(STI) &&
"Rip-relative addressing requires 64-bit mode");
366 assert(IndexReg.
getReg() == 0 &&
"Invalid rip-relative address");
367 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
373 unsigned FixupKind = [=]() {
404 CurByte, OS,
Fixups, -ImmSize);
408 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
412 if (Is16BitMemOperand(MI, Op, STI)) {
425 static const unsigned R16Table[] = { 0, 0, 0, 7, 0, 6, 4, 5 };
426 unsigned RMfield = R16Table[BaseRegNo];
428 assert(RMfield &&
"invalid 16-bit base register");
431 unsigned IndexReg16 = R16Table[GetX86RegNum(IndexReg)];
433 assert(IndexReg16 &&
"invalid 16-bit index register");
435 assert(((IndexReg16 ^ RMfield) & 2) &&
436 "invalid 16-bit base/index register combination");
438 "invalid scale for 16-bit memory reference");
442 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
444 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
450 EmitByte(ModRMByte(0, RegOpcodeField, RMfield), CurByte, OS);
454 EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS);
459 EmitByte(ModRMByte(2, RegOpcodeField, RMfield), CurByte, OS);
462 EmitByte(ModRMByte(0, RegOpcodeField, 6), CurByte, OS);
483 (!is64BitMode(STI) || BaseReg != 0)) {
486 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
496 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
503 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
511 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
519 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
530 IndexReg.
getReg() != X86::RSP &&
"Cannot use ESP as index reg!");
532 bool ForceDisp32 =
false;
533 bool ForceDisp8 =
false;
539 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
541 }
else if (!Disp.
isImm()) {
543 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
545 }
else if (Disp.
getImm() == 0 &&
550 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
553 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
557 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
559 ImmOffset = CDisp8 - Disp.
getImm();
562 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
566 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 };
567 unsigned SS = SSTable[Scale.
getImm()];
574 IndexRegNo = GetX86RegNum(IndexReg);
577 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
581 IndexRegNo = GetX86RegNum(IndexReg);
584 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
590 else if (ForceDisp32 || Disp.
getImm() != 0)
597 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
598 int MemOperand,
const MCInst &MI,
615 uint8_t EVEX_R2 = 0x1;
659 uint8_t EVEX_V2 = 0x1;
692 uint8_t EVEX_z = (HasEVEX_K && (TSFlags &
X86II::EVEX_Z)) ? 1 : 0;
701 uint8_t EVEX_aaa = 0;
703 bool EncodeRC =
false;
720 VEX_B = ~(BaseRegEnc >> 3) & 1;
722 VEX_X = ~(IndexRegEnc >> 3) & 1;
724 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
729 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
732 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
733 VEX_4V = ~VRegEnc & 0xf;
734 EVEX_V2 = ~(VRegEnc >> 4) & 1;
737 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
738 VEX_R = ~(RegEnc >> 3) & 1;
739 EVEX_R2 = ~(RegEnc >> 4) & 1;
751 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
752 VEX_R = ~(RegEnc >> 3) & 1;
753 EVEX_R2 = ~(RegEnc >> 4) & 1;
756 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
759 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
760 VEX_4V = ~VRegEnc & 0xf;
761 EVEX_V2 = ~(VRegEnc >> 4) & 1;
765 VEX_B = ~(BaseRegEnc >> 3) & 1;
767 VEX_X = ~(IndexRegEnc >> 3) & 1;
769 EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
776 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
777 VEX_R = ~(RegEnc >> 3) & 1;
780 VEX_B = ~(BaseRegEnc >> 3) & 1;
782 VEX_X = ~(IndexRegEnc >> 3) & 1;
789 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
790 VEX_R = ~(RegEnc >> 3) & 1;
792 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
793 VEX_4V = ~VRegEnc & 0xf;
796 VEX_B = ~(BaseRegEnc >> 3) & 1;
798 VEX_X = ~(IndexRegEnc >> 3) & 1;
809 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
810 VEX_4V = ~VRegEnc & 0xf;
811 EVEX_V2 = ~(VRegEnc >> 4) & 1;
815 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
818 VEX_B = ~(BaseRegEnc >> 3) & 1;
820 VEX_X = ~(IndexRegEnc >> 3) & 1;
831 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
832 VEX_R = ~(RegEnc >> 3) & 1;
833 EVEX_R2 = ~(RegEnc >> 4) & 1;
836 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
839 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
840 VEX_4V = ~VRegEnc & 0xf;
841 EVEX_V2 = ~(VRegEnc >> 4) & 1;
844 RegEnc = getX86RegEncoding(MI, CurOp++);
845 VEX_B = ~(RegEnc >> 3) & 1;
846 VEX_X = ~(RegEnc >> 4) & 1;
850 unsigned RcOperand = NumOps-1;
851 assert(RcOperand >= CurOp);
861 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
862 VEX_R = ~(RegEnc >> 3) & 1;
864 RegEnc = getX86RegEncoding(MI, CurOp++);
865 VEX_B = ~(RegEnc >> 3) & 1;
867 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf;
872 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
873 VEX_R = ~(RegEnc >> 3) & 1;
875 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
876 VEX_4V = ~VRegEnc & 0xf;
881 RegEnc = getX86RegEncoding(MI, CurOp++);
882 VEX_B = ~(RegEnc >> 3) & 1;
883 VEX_X = ~(RegEnc >> 4) & 1;
891 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
892 VEX_B = ~(RegEnc >> 3) & 1;
893 VEX_X = ~(RegEnc >> 4) & 1;
896 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
899 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
900 VEX_4V = ~VRegEnc & 0xf;
901 EVEX_V2 = ~(VRegEnc >> 4) & 1;
904 RegEnc = getX86RegEncoding(MI, CurOp++);
905 VEX_R = ~(RegEnc >> 3) & 1;
906 EVEX_R2 = ~(RegEnc >> 4) & 1;
918 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++);
919 VEX_4V = ~VRegEnc & 0xf;
920 EVEX_V2 = ~(VRegEnc >> 4) & 1;
923 EVEX_aaa = getX86RegEncoding(MI, CurOp++);
925 unsigned RegEnc = getX86RegEncoding(MI, CurOp++);
926 VEX_B = ~(RegEnc >> 3) & 1;
927 VEX_X = ~(RegEnc >> 4) & 1;
948 uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
951 if (Encoding ==
X86II::VEX && VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) {
952 EmitByte(0xC5, CurByte, OS);
953 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
958 EmitByte(Encoding ==
X86II::XOP ? 0x8F : 0xC4, CurByte, OS);
959 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
960 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
968 assert((VEX_5M & 0x3) == VEX_5M
969 &&
"More than 2 significant bits in VEX.m-mmmm fields for EVEX!");
971 EmitByte(0x62, CurByte, OS);
972 EmitByte((VEX_R << 7) |
976 VEX_5M, CurByte, OS);
977 EmitByte((VEX_W << 7) |
980 VEX_PP, CurByte, OS);
982 EmitByte((EVEX_z << 7) |
986 EVEX_aaa, CurByte, OS);
988 EmitByte((EVEX_z << 7) |
993 EVEX_aaa, CurByte, OS);
1000 uint8_t X86MCCodeEmitter::DetermineREXPrefix(
const MCInst &MI, uint64_t TSFlags,
1004 bool UsesHighByteReg =
false;
1015 for (
unsigned i = CurOp;
i != NumOps; ++
i) {
1017 if (!MO.
isReg())
continue;
1019 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1020 UsesHighByteReg =
true;
1027 switch (TSFlags & X86II::FormMask) {
1029 REX |= isREXExtendedReg(MI, CurOp++) << 0;
1032 REX |= isREXExtendedReg(MI, CurOp++) << 2;
1033 REX |= isREXExtendedReg(MI, CurOp++) << 0;
1036 REX |= isREXExtendedReg(MI, CurOp++) << 2;
1043 REX |= isREXExtendedReg(MI, CurOp++) << 0;
1044 REX |= isREXExtendedReg(MI, CurOp++) << 2;
1050 REX |= isREXExtendedReg(MI, CurOp++) << 2;
1065 REX |= isREXExtendedReg(MI, CurOp++) << 0;
1068 if (REX && UsesHighByteReg)
1075 void X86MCCodeEmitter::EmitSegmentOverridePrefix(
unsigned &CurByte,
1076 unsigned SegOperand,
1083 case X86::CS: EmitByte(0x2E, CurByte, OS);
break;
1084 case X86::SS: EmitByte(0x36, CurByte, OS);
break;
1085 case X86::DS: EmitByte(0x3E, CurByte, OS);
break;
1086 case X86::ES: EmitByte(0x26, CurByte, OS);
break;
1087 case X86::FS: EmitByte(0x64, CurByte, OS);
break;
1088 case X86::GS: EmitByte(0x65, CurByte, OS);
break;
1098 bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags,
unsigned &CurByte,
1099 int MemOperand,
const MCInst &MI,
1107 EmitByte(0x66, CurByte, OS);
1111 EmitByte(0xF0, CurByte, OS);
1113 switch (TSFlags & X86II::OpPrefixMask) {
1115 EmitByte(0x66, CurByte, OS);
1118 EmitByte(0xF3, CurByte, OS);
1121 EmitByte(0xF2, CurByte, OS);
1127 if (is64BitMode(STI)) {
1128 if (uint8_t REX = DetermineREXPrefix(MI, TSFlags, MemOperand, Desc)) {
1129 EmitByte(0x40 | REX, CurByte, OS);
1135 switch (TSFlags & X86II::OpMapMask) {
1139 EmitByte(0x0F, CurByte, OS);
1143 switch (TSFlags & X86II::OpMapMask) {
1145 EmitByte(0x38, CurByte, OS);
1148 EmitByte(0x3A, CurByte, OS);
1154 void X86MCCodeEmitter::
1160 uint64_t TSFlags = Desc.
TSFlags;
1170 unsigned CurByte = 0;
1184 unsigned I8RegNum = 0;
1188 if (MemoryOperand != -1) MemoryOperand += CurOp;
1191 if (MemoryOperand >= 0)
1197 EmitByte(0xF3, CurByte, OS);
1200 bool need_address_override;
1205 need_address_override =
true;
1206 }
else if (MemoryOperand < 0) {
1207 need_address_override =
false;
1208 }
else if (is64BitMode(STI)) {
1209 assert(!Is16BitMemOperand(MI, MemoryOperand, STI));
1211 }
else if (is32BitMode(STI)) {
1213 need_address_override = Is16BitMemOperand(MI, MemoryOperand, STI);
1215 assert(is16BitMode(STI));
1217 need_address_override = !Is16BitMemOperand(MI, MemoryOperand, STI);
1220 if (need_address_override)
1221 EmitByte(0x67, CurByte, OS);
1225 Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
1227 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
1236 default:
errs() <<
"FORM: " << Form <<
"\n";
1245 "SI and DI register sizes do not match");
1248 EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
1250 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1251 (is32BitMode(STI) && siReg == X86::SI))
1252 EmitByte(0x67, CurByte, OS);
1254 EmitByte(BaseOpcode, CurByte, OS);
1261 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1263 if ((!is32BitMode(STI) && siReg == X86::ESI) ||
1264 (is32BitMode(STI) && siReg == X86::SI))
1265 EmitByte(0x67, CurByte, OS);
1267 EmitByte(BaseOpcode, CurByte, OS);
1273 if ((!is32BitMode(STI) && siReg == X86::EDI) ||
1274 (is32BitMode(STI) && siReg == X86::DI))
1275 EmitByte(0x67, CurByte, OS);
1277 EmitByte(BaseOpcode, CurByte, OS);
1281 EmitByte(BaseOpcode, CurByte, OS);
1285 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1286 EmitByte(BaseOpcode, CurByte, OS);
1293 EmitByte(BaseOpcode, CurByte, OS);
1301 EmitByte(BaseOpcode, CurByte, OS);
1310 EmitByte(BaseOpcode + GetX86RegNum(MI.
getOperand(CurOp++)), CurByte, OS);
1314 EmitByte(BaseOpcode, CurByte, OS);
1315 unsigned SrcRegNum = CurOp + 1;
1324 GetX86RegNum(MI.
getOperand(SrcRegNum)), CurByte, OS);
1325 CurOp = SrcRegNum + 1;
1329 EmitByte(BaseOpcode, CurByte, OS);
1338 emitMemModRMByte(MI, CurOp, GetX86RegNum(MI.
getOperand(SrcRegNum)), TSFlags,
1339 Rex, CurByte, OS, Fixups, STI);
1340 CurOp = SrcRegNum + 1;
1344 EmitByte(BaseOpcode, CurByte, OS);
1345 unsigned SrcRegNum = CurOp + 1;
1354 GetX86RegNum(MI.
getOperand(CurOp)), CurByte, OS);
1355 CurOp = SrcRegNum + 1;
1357 I8RegNum = getX86RegEncoding(MI, CurOp++);
1364 EmitByte(BaseOpcode, CurByte, OS);
1365 unsigned SrcRegNum = CurOp + 1;
1368 GetX86RegNum(MI.
getOperand(CurOp)), CurByte, OS);
1369 CurOp = SrcRegNum + 1;
1374 EmitByte(BaseOpcode, CurByte, OS);
1375 unsigned SrcRegNum = CurOp + 1;
1381 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1382 I8RegNum = getX86RegEncoding(MI, SrcRegNum++);
1385 GetX86RegNum(MI.
getOperand(CurOp)), CurByte, OS);
1386 CurOp = SrcRegNum + 1;
1390 unsigned FirstMemOp = CurOp+1;
1398 EmitByte(BaseOpcode, CurByte, OS);
1400 emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.
getOperand(CurOp)),
1401 TSFlags, Rex, CurByte, OS, Fixups, STI);
1404 I8RegNum = getX86RegEncoding(MI, CurOp++);
1408 unsigned FirstMemOp = CurOp+1;
1410 EmitByte(BaseOpcode, CurByte, OS);
1412 emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.
getOperand(CurOp)),
1413 TSFlags, Rex, CurByte, OS, Fixups, STI);
1419 unsigned FirstMemOp = CurOp+1;
1424 assert(HasVEX_I8Reg &&
"MRMSrcRegOp4 should imply VEX_I8Reg");
1425 I8RegNum = getX86RegEncoding(MI, FirstMemOp++);
1427 EmitByte(BaseOpcode, CurByte, OS);
1429 emitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.
getOperand(CurOp)),
1430 TSFlags, Rex, CurByte, OS, Fixups, STI);
1444 EmitByte(BaseOpcode, CurByte, OS);
1460 EmitByte(BaseOpcode, CurByte, OS);
1461 emitMemModRMByte(MI, CurOp,
1463 Rex, CurByte, OS, Fixups, STI);
1489 EmitByte(BaseOpcode, CurByte, OS);
1497 assert(I8RegNum < 16 &&
"Register encoding out of range");
1499 if (CurOp != NumOps) {
1501 assert(Val < 16 &&
"Immediate operand value out of range");
1510 while (CurOp != NumOps && NumOps - CurOp <= 2) {
1517 if (TSFlags & X86II::Has3DNow0F0FOpcode)
1522 if ( CurOp != NumOps) {
1523 errs() <<
"Cannot encode all operands of: ";
static bool HasSecRelSymbolRef(const MCExpr *Expr)
void push_back(const T &Elt)
static bool Is64BitMemOperand(const MCInst &MI, unsigned Op)
Is64BitMemOperand - Return true if the specified instruction has a 64-bit memory operand.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
bool isX86_64NonExtLowByteReg(unsigned reg)
const MCSymbol & getSymbol() const
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static bool isDisp8(int Value)
isDisp8 - Return true if this signed displacement fits in a 8-bit sign-extended field.
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
static GlobalOffsetTableExprKind StartsWithGlobalOffsetTable(const MCExpr *Expr)
static MCFixupKind getKindForSize(unsigned Size, bool isPCRel)
Return the generic fixup kind for a value with the given size.
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
XOP - Opcode prefix used by XOP instructions.
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction's TSFlags indicates that it is...
AddrSegmentReg - The operand # of the segment in the memory operand.
A one-byte pc relative fixup.
MCCodeEmitter * createX86MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
A four-byte section relative fixup.
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MRM_XX - A mod/rm byte of exactly 0xXX.
bool hasImm(uint64_t TSFlags)
static bool isCDisp8(uint64_t TSFlags, int Value, int &CValue)
isCDisp8 - Return true if this signed displacement fits in a 8-bit compressed dispacement field...
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
static MCFixupKind getImmFixupKind(uint64_t TSFlags)
getImmFixupKind - Return the appropriate fixup kind to use for an immediate in an instruction with th...
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
AddrNumOperands - Total number of operands in a memory reference.
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Lanai::Fixups FixupKind(const MCExpr *Expr)
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction's TSFlags indicates that it i...
Binary assembler expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool Is32BitMemOperand(const MCInst &MI, unsigned Op)
Is32BitMemOperand - Return true if the specified instruction has a 32-bit memory operand.
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
A two-byte pc relative fixup.
A four-byte pc relative fixup.
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
unsigned char getBaseOpcodeFor(uint64_t TSFlags)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned getOpcode() const
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
StringRef getName() const
getName - Get the symbol name.
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
unsigned getNumOperands() const
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
VariantKind getKind() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/ESI...
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/ERI with a possib...
LLVM Value Representation.
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This class implements an extremely fast bulk output stream that can only output to a stream...
GlobalOffsetTableExprKind
StartsWithGlobalOffsetTable - Check if this expression starts with GLOBAL_OFFSET_TABLE and if it is o...
Represents a location in source code.
Instances of this class represent operands of the MCInst class.
static MCOperand createImm(int64_t Val)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
const MCOperand & getOperand(unsigned i) const
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...