54 raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterRef> &
P) {
55 auto &TRI =
P.G.getTRI();
56 if (
P.Obj.Reg > 0 &&
P.Obj.Reg < TRI.getNumRegs())
57 OS << TRI.getName(
P.Obj.Reg);
59 OS <<
'#' <<
P.Obj.Reg;
65 raw_ostream &operator<< (raw_ostream &OS, const Print<NodeId> &
P) {
67 uint16_t Attrs = NA.Addr->
getAttrs();
77 default: OS <<
"c?";
break;
93 default: OS <<
"r?";
break;
108 OS << Print<NodeId>(RA.
Id,
G) <<
'<'
115 raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<DefNode*>> &
P) {
118 if (
NodeId N =
P.Obj.Addr->getReachingDef())
121 if (
NodeId N =
P.Obj.Addr->getReachedDef())
124 if (
NodeId N =
P.Obj.Addr->getReachedUse())
127 if (
NodeId N =
P.Obj.Addr->getSibling())
133 raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<UseNode*>> &
P) {
136 if (
NodeId N =
P.Obj.Addr->getReachingDef())
139 if (
NodeId N =
P.Obj.Addr->getSibling())
149 if (
NodeId N =
P.Obj.Addr->getReachingDef())
152 if (
NodeId N =
P.Obj.Addr->getPredecessor())
155 if (
NodeId N =
P.Obj.Addr->getSibling())
161 raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<RefNode*>> &
P) {
162 switch (
P.Obj.Addr->getKind()) {
164 OS << PrintNode<DefNode*>(
P.Obj,
P.G);
170 OS << PrintNode<UseNode*>(
P.Obj,
P.G);
178 unsigned N =
P.Obj.size();
179 for (
auto I :
P.Obj) {
180 OS << Print<NodeId>(
I.Id,
P.G);
189 unsigned N =
P.Obj.size();
190 for (
auto I :
P.Obj) {
191 OS << Print<NodeId>(
I,
P.G);
200 template <
typename T>
209 template <
typename T>
210 raw_ostream &operator<< (raw_ostream &OS, const PrintListV<T> &
P) {
211 unsigned N =
P.List.size();
213 OS << PrintNode<T>(
A,
P.G);
223 raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<PhiNode*>> &
P) {
224 OS << Print<NodeId>(
P.Obj.Id,
P.G) <<
": phi ["
225 << PrintListV<RefNode*>(
P.Obj.Addr->members(
P.G),
P.G) <<
']';
234 OS << Print<NodeId>(
P.Obj.Id,
P.G) <<
": " <<
P.G.getTII().getName(Opc);
240 return Op.isMBB() ||
Op.isGlobal() ||
Op.isSymbol();
252 OS <<
" [" << PrintListV<RefNode*>(
P.Obj.Addr->members(
P.G),
P.G) <<
']';
259 switch (
P.Obj.Addr->getKind()) {
261 OS << PrintNode<PhiNode*>(
P.Obj,
P.G);
264 OS << PrintNode<StmtNode*>(
P.Obj,
P.G);
279 auto PrintBBs = [&OS,&
P] (std::vector<int> Ns) ->
void {
280 unsigned N = Ns.size();
288 OS << Print<NodeId>(
P.Obj.Id,
P.G) <<
": --- BB#" << BB->
getNumber()
289 <<
" --- preds(" << NP <<
"): ";
291 Ns.push_back(
B->getNumber());
295 OS <<
" succs(" << NS <<
"): ";
298 Ns.push_back(
B->getNumber());
302 for (
auto I :
P.Obj.Addr->members(
P.G))
311 <<
P.Obj.Addr->getCode()->getName() <<
'\n';
312 for (
auto I :
P.Obj.Addr->members(
P.G))
319 raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterSet> &
P) {
322 OS << ' ' << Print<RegisterRef>(
I,
P.G);
328 raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterAggr> &
P) {
337 OS << Print<NodeId>(
I->Id, P.
G)
358 void NodeAllocator::startNewBlock() {
360 char *
P =
static_cast<char*
>(
T);
365 assert((Blocks.size() < ((size_t)1 << (8*
sizeof(
NodeId)-BitsPerIndex))) &&
366 "Out of bits for block index");
370 bool NodeAllocator::needNewBlock() {
374 char *ActiveBegin = Blocks.back();
375 uint32_t Index = (ActiveEnd-ActiveBegin)/NodeMemSize;
376 return Index >= NodesPerBlock;
384 uint32_t Index = (ActiveEnd - Blocks[ActiveB])/NodeMemSize;
386 makeId(ActiveB, Index) };
392 uintptr_t
A =
reinterpret_cast<uintptr_t
>(
P);
393 for (
unsigned i = 0, n = Blocks.size();
i != n; ++
i) {
394 uintptr_t
B =
reinterpret_cast<uintptr_t
>(Blocks[
i]);
395 if (A < B || A >= B + NodesPerBlock*NodeMemSize)
398 return makeId(
i, Idx);
451 while (NA.
Addr !=
this) {
514 if (MA.
Id == NA.
Id) {
525 while (MA.
Addr !=
this) {
550 while (NA.
Addr !=
this) {
634 if (O.isGlobal() || O.isSymbol())
675 auto F = Masks.find(NR.
Reg);
676 if (
F != Masks.end()) {
677 if ((
F->second & NR.
Mask).any())
682 if (ExpAliasUnits.
test(*U))
693 auto F = Masks.find(NR.
Reg);
694 if (
F == Masks.end())
701 auto F = Masks.find(NR.
Reg);
702 if (
F == Masks.end())
703 Masks.insert({NR.
Reg, NR.
Mask});
705 F->second |= NR.Mask;
714 ExpAliasUnits.set(*U);
721 for (std::pair<RegisterId,LaneBitmask> P : RG.Masks)
728 auto F = Masks.find(NR.
Reg);
729 if (
F == Masks.end())
740 for (std::pair<RegisterId,LaneBitmask> P : RG.Masks)
767 : MF(mf),
TII(tii), TRI(tri), MDT(mdt), MDF(mdf), TOI(toi) {
784 Pos = DS.Stack.size();
785 while (Pos > 0 && DS.isDelimiter(DS.Stack[Pos-1]))
802 unsigned P = nextDown(Stack.size());
817 unsigned P = Stack.size();
819 bool Found = isDelimiter(Stack[P-1], N);
829 unsigned DataFlowGraph::DefStack::nextUp(
unsigned P)
const {
832 unsigned SS = Stack.size();
837 IsDelim = isDelimiter(Stack[P-1]);
838 }
while (P < SS && IsDelim);
844 unsigned DataFlowGraph::DefStack::nextDown(
unsigned P)
const {
847 assert(P > 0 && P <= Stack.size());
848 bool IsDelim = isDelimiter(Stack[P-1]);
852 IsDelim = isDelimiter(Stack[P-1]);
853 }
while (P > 0 && IsDelim);
871 RegisterSet DataFlowGraph::getLandingPadLiveIns()
const {
998 BlockNodes.insert(std::make_pair(&B, BA));
1000 if (
I.isDebugValue())
1007 NodeList Blocks = Func.Addr->members(*
this);
1011 buildBlockRefs(EA, RefM);
1029 if (!EHRegs.empty()) {
1060 recordDefsForDF(PhiM, RefM, BA);
1062 buildPhis(PhiM, RefM, BA);
1066 linkBlockRefs(DM, EA);
1117 for (
auto I = DefM.begin(),
E = DefM.end();
I !=
E; ++
I)
1118 I->second.start_block(B);
1126 for (
auto I = DefM.begin(),
E = DefM.end();
I !=
E; ++
I)
1127 I->second.clear_block(B);
1130 for (
auto I = DefM.begin(),
E = DefM.end(), NextI =
I;
I !=
E;
I = NextI) {
1131 NextI = std::next(
I);
1133 if (
I->second.empty())
1160 if (Visited.count(DA.
Id))
1169 if (!Defined.insert(RR).second) {
1171 dbgs() <<
"Multiple definitions of register: "
1179 DefM[RR.
Reg].push(DA);
1183 DefM[
A.Reg].push(DA);
1187 Visited.insert(T.Id);
1202 }
while (RA.
Id != 0 && RA.
Id != Start);
1215 std::pair<uint32_t,LaneBitmask> PA = *UMA;
1216 std::pair<uint32_t,LaneBitmask> PB = *UMB;
1217 if (PA.first == PB.first) {
1222 if (PA.second.none() || PB.second.none())
1232 if (LA.
any() && LB.
any()) {
1243 if ((MaskA & MaskB & RC.
LaneMask).any())
1251 if (PA.first < PB.first)
1253 else if (PB.first < PA.first)
1260 void DataFlowGraph::reset() {
1284 return Related(
TA) &&
1309 template <
typename Predicate>
1319 if (NA.
Id == 0 || NA.
Id == Start)
1326 if (NA.
Id != 0 && NA.
Id != Start)
1327 return std::make_pair(RA, NA);
1339 return TA.Addr->getFlags() ==
Flags;
1341 auto Loc = locateNextRef(IA, RA, IsShadow);
1342 if (Loc.second.Id != 0 || !Create)
1359 return TA.Addr->getFlags() ==
Flags;
1361 return locateNextRef(IA, RA, IsShadow).second;
1384 if (!UseOp.isReg() || !UseOp.isUse() || UseOp.isUndef())
1398 while (uint16_t R = *ImpD++)
1401 while (uint16_t R = *ImpU++)
1404 bool IsCall = isCall(In);
1415 for (
unsigned OpN = 0; OpN < NumOps; ++OpN) {
1424 if (isDefUndef(In, RR))
1431 if (IsCall && Op.
isDead())
1435 DoneDefs.insert(RR);
1440 for (
unsigned OpN = 0; OpN < NumOps; ++OpN) {
1445 if (!NeedsImplicit && !ImpDefs.count(RR))
1447 if (DoneDefs.count(RR))
1453 if (isDefUndef(In, RR))
1460 if (IsCall && Op.
isDead())
1464 DoneDefs.insert(RR);
1467 for (
unsigned OpN = 0; OpN < NumOps; ++OpN) {
1476 bool TakeImplicit = NeedsImplicit || IsPredicated;
1477 if (Implicit && !TakeImplicit && !ImpUses.count(RR))
1492 BlockRefsMap &RefM) {
1499 buildBlockRefs(SBA, RefM);
1501 Refs.insert(RefsS.begin(), RefsS.end());
1511 void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM, BlockRefsMap &RefM,
1518 auto DFLoc = MDF.
find(BB);
1519 if (DFLoc == MDF.
end() || DFLoc->second.empty())
1535 for (
unsigned i = 0;
i < IDF.size(); ++
i) {
1536 auto F = MDF.
find(IDF[
i]);
1538 IDF.insert(F->second.
begin(), F->second.
end());
1543 for (
auto DB : IDF) {
1546 Refs.insert(RefsD.begin(), RefsD.end());
1551 for (
auto DB : IDF) {
1553 PhiM[DBA.
Id].insert(Defs.begin(), Defs.end());
1559 void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, BlockRefsMap &RefM,
1563 auto HasDF = PhiM.find(BA.
Id);
1564 if (HasDF == PhiM.end() || HasDF->second.empty())
1580 MaxDF.insert(MaxCoverIn(I, HasDF->second));
1582 std::vector<RegisterRef> MaxRefs;
1585 MaxRefs.push_back(MaxCoverIn(I, RefB));
1592 std::sort(MaxRefs.begin(), MaxRefs.end());
1594 auto NewEnd = std::unique(MaxRefs.begin(), MaxRefs.end());
1595 MaxRefs.erase(NewEnd, MaxRefs.end());
1598 std::vector<unsigned> &Closure) ->
bool {
1599 for (
unsigned I : Closure)
1600 if (
alias(RR, MaxRefs[I]))
1611 while (!MaxRefs.empty()) {
1616 std::vector<unsigned> ClosureIdx = { 0 };
1617 for (
unsigned i = 1; i != MaxRefs.size(); ++
i)
1618 if (Aliased(MaxRefs[i], ClosureIdx))
1619 ClosureIdx.push_back(i);
1622 unsigned CS = ClosureIdx.size();
1626 for (
unsigned X = 0;
X != CS; ++
X) {
1634 for (
unsigned X = 0;
X != CS; ++
X) {
1642 auto Begin = MaxRefs.begin();
1643 for (
unsigned i = ClosureIdx.size(); i != 0; --
i)
1644 MaxRefs.erase(Begin + ClosureIdx[i-1]);
1649 void DataFlowGraph::removeUnusedPhis() {
1662 static auto HasUsedDef = [](
NodeList &Ms) ->
bool {
1676 while (!PhiQ.
empty()) {
1677 auto PA = addr<PhiNode*>(PhiQ[0]);
1680 if (HasUsedDef(Refs))
1684 auto RDA = addr<DefNode*>(RD);
1702 template <
typename T>
1713 for (
auto I = DS.top(),
E = DS.bottom(); I !=
E; I.down()) {
1718 bool Alias = Defs.hasAliasOf(QR);
1719 bool Cover = Defs.insert(QR).hasCoverOf(RR);
1739 TAP.
Addr->linkToDef(TAP.
Id, RDA);
1763 auto F = DefM.find(RR.
Reg);
1764 if (F == DefM.
end())
1766 DefStack &DS = F->second;
1768 linkRefUp<UseNode*>(SA, RA, DS);
1770 linkRefUp<DefNode*>(SA, RA, DS);
1782 assert(BA.
Addr &&
"block node address is needed to create a data-flow link");
1790 linkStmtRefs(DefM, IA);
1801 linkBlockRefs(DefM, SBA);
1810 return PUA.
Addr->getPredecessor() == BA.
Id;
1832 linkRefUp<UseNode*>(IA, PUA, DefM[RR.
Reg]);
1851 auto RDA = addr<DefNode*>(RD);
1853 if (TA.Id == UA.
Id) {
1858 while (TA.Id != 0) {
1859 NodeId S = TA.Addr->getSibling();
1864 TA = addr<UseNode*>(S);
1897 auto RA = addr<RefNode*>(
N);
1909 I.Addr->setSibling(0);
1911 I.Addr->setSibling(0);
1914 I.Addr->setReachingDef(RD);
1916 I.Addr->setReachingDef(RD);
1925 auto RDA = addr<DefNode*>(RD);
1927 if (TA.Id == DA.
Id) {
1934 while (TA.Id != 0) {
1935 NodeId S = TA.Addr->getSibling();
1937 TA.Addr->setSibling(Sib);
1940 TA = addr<DefNode*>(S);
1945 if (!ReachedDefs.empty()) {
1951 if (!ReachedUses.empty()) {
NodeList members(const DataFlowGraph &G) const
raw_ostream & operator<<(raw_ostream &OS, const PrintLaneMaskOpt &P)
void pushDefs(NodeAddr< InstrNode * > IA, DefStackMap &DM)
unsigned succ_size() const
void setReachingDef(NodeId RD)
bool isEHPad() const
Returns true if the block is a landing pad.
mop_iterator operands_end()
A common definition of LaneBitmask for use in TableGen and CodeGen.
RegisterRef restrictRef(RegisterRef AR, RegisterRef BR) const
const GlobalValue * getGlobal() const
static uint16_t kind(uint16_t T)
bool alias(RegisterRef RA, RegisterRef RB) const
bool isValid() const
Returns true if this iterator is not yet at the end.
NodeAddr< RefNode * > getNextRelated(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
NodeAddr< NodeBase * > New()
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
NodeId getReachedDef() const
livein_iterator livein_end() const
uint16_t getFlags() const
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
static uint16_t type(uint16_t T)
NodeBase * ptr(NodeId N) const
This class provides various memory handling functions that manipulate MemoryBlock instances...
Describe properties that are true of each instruction in the target description file.
virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
uint16_t getAttrs() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const char * getSymbolName() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
iterator_range< mop_iterator > operands()
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const TargetRegisterInfo &TRI)
unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
void unlinkUse(NodeAddr< UseNode * > UA, bool RemoveFromOwner)
iterator_range< succ_iterator > successors()
StringRef getName() const
Return a constant reference to the value's name.
void releaseBlock(NodeId B, DefStackMap &DefM)
const TargetInstrInfo & TII
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
MCSuperRegIterator enumerates all super-registers of Reg.
struct fuzzer::@269 Flags
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it...
const HexagonInstrInfo * TII
DominanceFrontierBase< MachineBasicBlock >::DomSetType DomSetType
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
NodeId getReachedUse() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< NodeBase * > getFirstMember(const DataFlowGraph &G) const
std::vector< NodeAddr< NodeBase * > > NodeList
bool remove(const value_type &X)
Remove an item from the set vector.
constexpr bool any() const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void append(NodeAddr< NodeBase * > NA)
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
const MachineBasicBlock & front() const
bool insert(const value_type &X)
Insert a new element into the SetVector.
static bool IsDef(const NodeAddr< NodeBase * > BA)
MCRegUnitRootIterator enumerates the root registers of a register unit.
MachineFunction * getCode() const
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
bool empty() const
Determine if the SetVector is empty or not.
Base class for the actual dominator tree node.
virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
void clear_block(NodeId N)
NodeAddr< BlockNode * > findBlock(const MachineBasicBlock *BB, const DataFlowGraph &G) const
void addMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
NodeList members_if(Predicate P, const DataFlowGraph &G) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
RegisterAggr & clear(RegisterRef RR)
void setFlags(uint16_t F)
INITIALIZE_PASS(HexagonEarlyIfConversion,"hexagon-eif","Hexagon early if conversion", false, false) bool HexagonEarlyIfConversion MachineBasicBlock * SB
void setReachedDef(NodeId D)
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
bool isReturn(QueryType Type=AnyInBundle) const
Control flow instructions. These all have token chains.
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
unsigned const MachineRegisterInfo * MRI
bool hasCoverOf(RegisterRef RR) const
constexpr bool none() const
NodeAddr< BlockNode * > getEntryBlock(const DataFlowGraph &G)
This is an important base class in LLVM.
const MachineOperand & getOperand(unsigned i) const
LLVM_ATTRIBUTE_RETURNS_NONNULL LLVM_ATTRIBUTE_RETURNS_NOALIAS void * Allocate(size_t Size, size_t Alignment)
Allocate space at the specified alignment.
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
bool hasPersonalityFn() const
Check whether this function has a personality function.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
static uint16_t flags(uint16_t T)
iterator_range< pred_iterator > predecessors()
static bool IsPhi(const NodeAddr< NodeBase * > BA)
unsigned getSubReg() const
virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
NodeId getPredecessor() const
iterator find(MachineBasicBlock *B)
NodeAddr< NodeBase * > getLastMember(const DataFlowGraph &G) const
void setPredecessor(NodeId B)
RegisterAggr & insert(RegisterRef RR)
void markBlock(NodeId B, DefStackMap &DefM)
MachineOperand class - Representation of each machine instruction operand.
NodeId getSibling() const
bool test(unsigned Idx) const
virtual const TargetLowering * getTargetLowering() const
NodeId id(const NodeBase *P) const
livein_iterator livein_begin() const
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
void setAttrs(uint16_t A)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void addPhi(NodeAddr< PhiNode * > PA, const DataFlowGraph &G)
std::unordered_map< RegisterId, DefStack > DefStackMap
std::set< NodeId > NodeSet
RegisterRef getRegRef(const DataFlowGraph &G) const
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
static void clear(coro::Shape &Shape)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
RegisterRef unpack(PackedRegisterRef PR) const
Representation of each machine instruction.
static void printRefHeader(raw_ostream &OS, const NodeAddr< RefNode * > RA, const DataFlowGraph &G)
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void setRegRef(RegisterRef RR, DataFlowGraph &G)
PackedRegisterRef pack(RegisterRef RR)
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
void addMemberAfter(NodeAddr< NodeBase * > MA, NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
void push_back(MachineInstr *MI)
bool isCall(QueryType Type=AnyInBundle) const
void build(unsigned Options=BuildOptions::None)
constexpr bool all() const
const LaneBitmask LaneMask
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
MachineBasicBlock * getCode() const
RegisterRef normalizeRef(RegisterRef RR) const
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void removeMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
NodeId id(const NodeBase *P) const
void unlinkDef(NodeAddr< DefNode * > DA, bool RemoveFromOwner)
A vector that has set insertion semantics.
static LLVM_ATTRIBUTE_UNUSED Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
NodeAddr< T > addr(NodeId N) const
NodeId getReachingDef() const
RegisterRef normalize(RegisterRef RR) const
This class implements an extremely fast bulk output stream that can only output to a stream...
bool hasAliasOf(RegisterRef RR) const
std::set< RegisterRef > RegisterSet
auto find_if(R &&Range, UnaryPredicate P) -> decltype(std::begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
NodeAddr< RefNode * > getNextRef(RegisterRef RR, Predicate P, bool NextOnly, const DataFlowGraph &G)
void start_block(NodeId N)
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
unsigned pred_size() const
NodeAddr< RefNode * > getNextShadow(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA, bool Create)
This file describes how to lower LLVM code to machine code.
void setReachedUse(NodeId U)
void setSibling(NodeId Sib)