14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
44 const unsigned *OperandCycles;
45 const unsigned *ForwardingPaths;
60 const unsigned *
OC,
const unsigned *FP);
79 FeatureBits = FeatureBits_;
129 unsigned DefIdx)
const {
130 assert(DefIdx < SC->NumWriteLatencyEntries &&
131 "MachineModel does not specify a WriteResource for DefIdx");
137 unsigned WriteResID)
const {
143 if (
I->UseIdx < UseIdx)
145 if (
I->UseIdx > UseIdx)
148 if (!
I->WriteResourceID ||
I->WriteResourceID == WriteResID) {
164 auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
165 return Found != ProcDesc.end() &&
StringRef(Found->Key) == CPU;
unsigned NumWriteProcResEntries
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
void setFeatureBits(const FeatureBitset &FeatureBits_)
setFeatureBits - Set the feature bits.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
getSchedModelForCPU - Get the machine model of a CPU.
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
StringRef getCPU() const
getCPU - Return the CPU string.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
void InitMCProcessorInfo(StringRef CPU, StringRef FS)
Initialize the scheduling model and feature bits.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
unsigned NumReadAdvanceEntries
FeatureBitset ToggleFeature(uint64_t FB)
ToggleFeature - Toggle a feature and returns the re-computed feature bits.
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Summarize the scheduling resources required for an instruction of a particular scheduling class...
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Triple - Helper class for working with autoconf configuration names.
Specify the latency in cpu cycles for a particular scheduling class and def index.
CHAIN = SC CHAIN, Imm128 - System call.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
These values represent a non-pipelined step in the execution of an instruction.
MCSubtargetInfo - Generic base class for all target subtargets.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef - Represent a constant reference to a string, i.e.
Machine model for scheduling, bundling, and heuristics.
void setDefaultFeatures(StringRef CPU, StringRef FS)
Set the features to the default for the given CPU with an appended feature string.