24 "amdgpu-spill-sgpr-to-vgpr",
25 cl::desc(
"Enable spilling VGPRs to SGPRs"),
31 TIDReg(AMDGPU::NoRegister),
32 ScratchRSrcReg(AMDGPU::NoRegister),
33 ScratchWaveOffsetReg(AMDGPU::NoRegister),
34 PrivateSegmentBufferUserSGPR(AMDGPU::NoRegister),
35 DispatchPtrUserSGPR(AMDGPU::NoRegister),
36 QueuePtrUserSGPR(AMDGPU::NoRegister),
37 KernargSegmentPtrUserSGPR(AMDGPU::NoRegister),
38 DispatchIDUserSGPR(AMDGPU::NoRegister),
39 FlatScratchInitUserSGPR(AMDGPU::NoRegister),
40 PrivateSegmentSizeUserSGPR(AMDGPU::NoRegister),
41 GridWorkGroupCountXUserSGPR(AMDGPU::NoRegister),
42 GridWorkGroupCountYUserSGPR(AMDGPU::NoRegister),
43 GridWorkGroupCountZUserSGPR(AMDGPU::NoRegister),
44 WorkGroupIDXSystemSGPR(AMDGPU::NoRegister),
45 WorkGroupIDYSystemSGPR(AMDGPU::NoRegister),
46 WorkGroupIDZSystemSGPR(AMDGPU::NoRegister),
47 WorkGroupInfoSystemSGPR(AMDGPU::NoRegister),
48 PrivateSegmentWaveByteOffsetSystemSGPR(AMDGPU::NoRegister),
51 FlatWorkGroupSizes(0, 0),
53 DebuggerWorkGroupIDStackObjectIndices({{0, 0, 0}}),
115 if (HasStackObjects || MaySpill)
119 if (HasStackObjects || MaySpill)
122 if (F->hasFnAttribute(
"amdgpu-dispatch-ptr"))
125 if (F->hasFnAttribute(
"amdgpu-queue-ptr"))
128 if (F->hasFnAttribute(
"amdgpu-dispatch-id"))
131 if (HasStackObjects || MaySpill)
148 PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg(
149 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
151 return PrivateSegmentBufferUserSGPR;
155 DispatchPtrUserSGPR = TRI.getMatchingSuperReg(
156 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
158 return DispatchPtrUserSGPR;
162 QueuePtrUserSGPR = TRI.getMatchingSuperReg(
163 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
165 return QueuePtrUserSGPR;
169 KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg(
170 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
172 return KernargSegmentPtrUserSGPR;
176 DispatchIDUserSGPR = TRI.getMatchingSuperReg(
177 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
179 return DispatchIDUserSGPR;
183 FlatScratchInitUserSGPR = TRI.getMatchingSuperReg(
184 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
186 return FlatScratchInitUserSGPR;
190 PrivateMemoryPtrUserSGPR = TRI.getMatchingSuperReg(
191 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass);
193 return PrivateMemoryPtrUserSGPR;
209 Offset += SubIdx * 4;
211 unsigned LaneVGPRIdx = Offset / (64 * 4);
212 unsigned Lane = (Offset / 4) % 64;
218 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass,
221 if (LaneVGPR == AMDGPU::NoRegister)
231 BI->addLiveIn(LaneVGPR);
PrivateMemoryInputPtr(false)
AMDGPU specific subclass of TargetSubtarget.
bool isVGPRSpillingEnabled(const Function &F) const
HasNonSpillStackObjects(false)
unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI)
GridWorkgroupCountZ(false)
unsigned addPrivateMemoryPtr(const SIRegisterInfo &TRI)
PrivateSegmentWaveByteOffset(false)
SIMachineFunctionInfo(const MachineFunction &MF)
bool isAmdCodeObjectV2(const MachineFunction &MF) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned addDispatchID(const SIRegisterInfo &TRI)
std::pair< unsigned, unsigned > getWavesPerEU(const Function &F) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isMesaGfxShader(const MachineFunction &MF) const
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Generation getGeneration() const
GridWorkgroupCountY(false)
GridWorkgroupCountX(false)
initializer< Ty > init(const Ty &Val)
DebuggerWorkItemIDStackObjectIndices({{0, 0, 0}})
unsigned const MachineRegisterInfo * MRI
bool isShader(CallingConv::ID cc)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned addQueuePtr(const SIRegisterInfo &TRI)
unsigned addDispatchPtr(const SIRegisterInfo &TRI)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Iterator for intrusive lists based on ilist_node.
const SIRegisterInfo * getRegisterInfo() const override
SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex, unsigned SubIdx)
std::map< unsigned, unsigned > LaneVGPRs
unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
unsigned addFlatScratchInit(const SIRegisterInfo &TRI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
unsigned getInitialPSInputAddr(const Function &F)
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
std::pair< unsigned, unsigned > getFlatWorkGroupSizes(const Function &F) const
PrivateSegmentBuffer(false)
bool debuggerEmitPrologue() const