15 #define DEBUG_TYPE "hexagon-shuffle"
29 cl::desc(
"Disable Hexagon instruction shuffling"));
31 void HexagonMCShuffler::init(
MCInst &MCB) {
33 MCInst const *Extender =
nullptr;
51 void HexagonMCShuffler::init(
MCInst &MCB,
MCInst const *AddMI,
52 bool bInsertAtFront) {
54 if (bInsertAtFront && AddMI)
57 MCInst const *Extender =
nullptr;
69 if (!bInsertAtFront && AddMI)
83 MCInst const *MI =
I->getDesc();
84 MCInst const *Extender =
I->getExtender();
116 DEBUG(
dbgs() <<
"Skipping empty bundle");
119 DEBUG(
dbgs() <<
"Skipping stand-alone insn");
126 unsigned shuffleError = MCS.
getError();
127 switch (shuffleError) {
165 DEBUG(
dbgs() <<
"Skipping empty bundle");
168 DEBUG(
dbgs() <<
"Skipping stand-alone insn");
172 bool doneShuffling =
false;
173 unsigned shuffleError;
174 while (possibleDuplexes.
size() > 0 && (!doneShuffling)) {
180 if (MCS.
size() == 1) {
193 if (doneShuffling ==
false) {
214 if (fixupCount >= 2) {
226 unsigned shuffleError = MCS.
getError();
227 switch (shuffleError) {
unsigned getError() const
bool isBundle(MCInst const &MCI)
No free slots for store insns.
bool isImmext(MCInst const &MCI)
bool reshuffleTo(MCInst &MCB)
#define HEXAGON_PACKET_SIZE
void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate)
Context object for machine code objects.
No free slots for branch insns.
Instances of this class represent a single low-level machine instruction.
No free slots for load insns.
initializer< Ty > init(const Ty &Val)
MCSubtargetInfo const & STI
Interface to description of machine instruction set.
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
No free slots for other insns.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void append(MCInst const *ID, MCInst const *Extender, unsigned S, bool X=false)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &)
LLVM_NODISCARD T pop_back_val()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static MCOperand createInst(const MCInst *Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
MCSubtargetInfo - Generic base class for all target subtargets.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
static cl::opt< bool > DisableShuffle("disable-hexagon-shuffle", cl::Hidden, cl::init(false), cl::desc("Disable Hexagon instruction shuffling"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
void addOperand(const MCOperand &Op)
static MCOperand createImm(int64_t Val)
const MCOperand & getOperand(unsigned i) const