LLVM  4.0.0
SelectionDAGBuilder.h
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1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
15 #define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H
16 
17 #include "StatepointLowering.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/IR/CallSite.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Statepoint.h"
28 #include <utility>
29 #include <vector>
30 
31 namespace llvm {
32 
33 class AddrSpaceCastInst;
34 class AllocaInst;
35 class BasicBlock;
36 class BitCastInst;
37 class BranchInst;
38 class CallInst;
39 class DbgValueInst;
40 class ExtractElementInst;
41 class ExtractValueInst;
42 class FCmpInst;
43 class FPExtInst;
44 class FPToSIInst;
45 class FPToUIInst;
46 class FPTruncInst;
47 class Function;
48 class FunctionLoweringInfo;
49 class GetElementPtrInst;
50 class GCFunctionInfo;
51 class ICmpInst;
52 class IntToPtrInst;
53 class IndirectBrInst;
54 class InvokeInst;
55 class InsertElementInst;
56 class InsertValueInst;
57 class Instruction;
58 class LoadInst;
59 class MachineBasicBlock;
60 class MachineInstr;
61 class MachineRegisterInfo;
62 class MDNode;
63 class MVT;
64 class PHINode;
65 class PtrToIntInst;
66 class ReturnInst;
67 class SDDbgValue;
68 class SExtInst;
69 class SelectInst;
70 class ShuffleVectorInst;
71 class SIToFPInst;
72 class StoreInst;
73 class SwitchInst;
74 class DataLayout;
75 class TargetLibraryInfo;
76 class TargetLowering;
77 class TruncInst;
78 class UIToFPInst;
79 class UnreachableInst;
80 class VAArgInst;
81 class ZExtInst;
82 
83 //===----------------------------------------------------------------------===//
84 /// SelectionDAGBuilder - This is the common target-independent lowering
85 /// implementation that is parameterized by a TargetLowering object.
86 ///
88  /// CurInst - The current instruction being visited
89  const Instruction *CurInst;
90 
92 
93  /// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
94  /// to preserve debug information for incoming arguments.
95  DenseMap<const Value*, SDValue> UnusedArgNodeMap;
96 
97  /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
98  class DanglingDebugInfo {
99  const DbgValueInst* DI;
100  DebugLoc dl;
101  unsigned SDNodeOrder;
102  public:
103  DanglingDebugInfo() : DI(nullptr), dl(DebugLoc()), SDNodeOrder(0) { }
104  DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO)
105  : DI(di), dl(std::move(DL)), SDNodeOrder(SDNO) {}
106  const DbgValueInst* getDI() { return DI; }
107  DebugLoc getdl() { return dl; }
108  unsigned getSDNodeOrder() { return SDNodeOrder; }
109  };
110 
111  /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
112  /// yet seen the referent. We defer handling these until we do see it.
113  DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
114 
115 public:
116  /// PendingLoads - Loads are not emitted to the program immediately. We bunch
117  /// them up and then emit token factor nodes when possible. This allows us to
118  /// get simple disambiguation between loads without worrying about alias
119  /// analysis.
121 
122  /// State used while lowering a statepoint sequence (gc_statepoint,
123  /// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.
125 private:
126 
127  /// PendingExports - CopyToReg nodes that copy values to virtual registers
128  /// for export to other blocks need to be emitted before any terminator
129  /// instruction, but they have no other ordering requirements. We bunch them
130  /// up and the emit a single tokenfactor for them just before terminator
131  /// instructions.
132  SmallVector<SDValue, 8> PendingExports;
133 
134  /// SDNodeOrder - A unique monotonically increasing number used to order the
135  /// SDNodes we create.
136  unsigned SDNodeOrder;
137 
138  enum CaseClusterKind {
139  /// A cluster of adjacent case labels with the same destination, or just one
140  /// case.
141  CC_Range,
142  /// A cluster of cases suitable for jump table lowering.
143  CC_JumpTable,
144  /// A cluster of cases suitable for bit test lowering.
145  CC_BitTests
146  };
147 
148  /// A cluster of case labels.
149  struct CaseCluster {
150  CaseClusterKind Kind;
151  const ConstantInt *Low, *High;
152  union {
154  unsigned JTCasesIndex;
155  unsigned BTCasesIndex;
156  };
157  BranchProbability Prob;
158 
159  static CaseCluster range(const ConstantInt *Low, const ConstantInt *High,
160  MachineBasicBlock *MBB, BranchProbability Prob) {
161  CaseCluster C;
162  C.Kind = CC_Range;
163  C.Low = Low;
164  C.High = High;
165  C.MBB = MBB;
166  C.Prob = Prob;
167  return C;
168  }
169 
170  static CaseCluster jumpTable(const ConstantInt *Low,
171  const ConstantInt *High, unsigned JTCasesIndex,
172  BranchProbability Prob) {
173  CaseCluster C;
174  C.Kind = CC_JumpTable;
175  C.Low = Low;
176  C.High = High;
177  C.JTCasesIndex = JTCasesIndex;
178  C.Prob = Prob;
179  return C;
180  }
181 
182  static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High,
183  unsigned BTCasesIndex, BranchProbability Prob) {
184  CaseCluster C;
185  C.Kind = CC_BitTests;
186  C.Low = Low;
187  C.High = High;
188  C.BTCasesIndex = BTCasesIndex;
189  C.Prob = Prob;
190  return C;
191  }
192  };
193 
194  typedef std::vector<CaseCluster> CaseClusterVector;
195  typedef CaseClusterVector::iterator CaseClusterIt;
196 
197  struct CaseBits {
198  uint64_t Mask;
199  MachineBasicBlock* BB;
200  unsigned Bits;
201  BranchProbability ExtraProb;
202 
203  CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
204  BranchProbability Prob):
205  Mask(mask), BB(bb), Bits(bits), ExtraProb(Prob) { }
206 
207  CaseBits() : Mask(0), BB(nullptr), Bits(0) {}
208  };
209 
210  typedef std::vector<CaseBits> CaseBitsVector;
211 
212  /// Sort Clusters and merge adjacent cases.
213  void sortAndRangeify(CaseClusterVector &Clusters);
214 
215  /// CaseBlock - This structure is used to communicate between
216  /// SelectionDAGBuilder and SDISel for the code generation of additional basic
217  /// blocks needed by multi-case switch statements.
218  struct CaseBlock {
219  CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
220  const Value *cmpmiddle, MachineBasicBlock *truebb,
221  MachineBasicBlock *falsebb, MachineBasicBlock *me,
222  BranchProbability trueprob = BranchProbability::getUnknown(),
223  BranchProbability falseprob = BranchProbability::getUnknown())
224  : CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
225  TrueBB(truebb), FalseBB(falsebb), ThisBB(me), TrueProb(trueprob),
226  FalseProb(falseprob) {}
227 
228  // CC - the condition code to use for the case block's setcc node
229  ISD::CondCode CC;
230 
231  // CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
232  // Emit by default LHS op RHS. MHS is used for range comparisons:
233  // If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
234  const Value *CmpLHS, *CmpMHS, *CmpRHS;
235 
236  // TrueBB/FalseBB - the block to branch to if the setcc is true/false.
237  MachineBasicBlock *TrueBB, *FalseBB;
238 
239  // ThisBB - the block into which to emit the code for the setcc and branches
240  MachineBasicBlock *ThisBB;
241 
242  // TrueProb/FalseProb - branch weights.
243  BranchProbability TrueProb, FalseProb;
244  };
245 
246  struct JumpTable {
247  JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
248  MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
249 
250  /// Reg - the virtual register containing the index of the jump table entry
251  //. to jump to.
252  unsigned Reg;
253  /// JTI - the JumpTableIndex for this jump table in the function.
254  unsigned JTI;
255  /// MBB - the MBB into which to emit the code for the indirect jump.
256  MachineBasicBlock *MBB;
257  /// Default - the MBB of the default bb, which is a successor of the range
258  /// check MBB. This is when updating PHI nodes in successors.
259  MachineBasicBlock *Default;
260  };
261  struct JumpTableHeader {
262  JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
263  bool E = false)
264  : First(std::move(F)), Last(std::move(L)), SValue(SV), HeaderBB(H),
265  Emitted(E) {}
266  APInt First;
267  APInt Last;
268  const Value *SValue;
269  MachineBasicBlock *HeaderBB;
270  bool Emitted;
271  };
272  typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
273 
274  struct BitTestCase {
275  BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr,
276  BranchProbability Prob):
277  Mask(M), ThisBB(T), TargetBB(Tr), ExtraProb(Prob) { }
278  uint64_t Mask;
279  MachineBasicBlock *ThisBB;
280  MachineBasicBlock *TargetBB;
281  BranchProbability ExtraProb;
282  };
283 
284  typedef SmallVector<BitTestCase, 3> BitTestInfo;
285 
286  struct BitTestBlock {
287  BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT,
288  bool E, bool CR, MachineBasicBlock *P, MachineBasicBlock *D,
289  BitTestInfo C, BranchProbability Pr)
290  : First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg),
291  RegVT(RgVT), Emitted(E), ContiguousRange(CR), Parent(P), Default(D),
292  Cases(std::move(C)), Prob(Pr) {}
293  APInt First;
294  APInt Range;
295  const Value *SValue;
296  unsigned Reg;
297  MVT RegVT;
298  bool Emitted;
299  bool ContiguousRange;
300  MachineBasicBlock *Parent;
301  MachineBasicBlock *Default;
302  BitTestInfo Cases;
303  BranchProbability Prob;
304  BranchProbability DefaultProb;
305  };
306 
307  /// Check whether a range of clusters is dense enough for a jump table.
308  bool isDense(const CaseClusterVector &Clusters,
309  const SmallVectorImpl<unsigned> &TotalCases,
310  unsigned First, unsigned Last, unsigned MinDensity) const;
311 
312  /// Build a jump table cluster from Clusters[First..Last]. Returns false if it
313  /// decides it's not a good idea.
314  bool buildJumpTable(const CaseClusterVector &Clusters, unsigned First,
315  unsigned Last, const SwitchInst *SI,
316  MachineBasicBlock *DefaultMBB, CaseCluster &JTCluster);
317 
318  /// Find clusters of cases suitable for jump table lowering.
319  void findJumpTables(CaseClusterVector &Clusters, const SwitchInst *SI,
320  MachineBasicBlock *DefaultMBB);
321 
322  /// Check whether the range [Low,High] fits in a machine word.
323  bool rangeFitsInWord(const APInt &Low, const APInt &High);
324 
325  /// Check whether these clusters are suitable for lowering with bit tests based
326  /// on the number of destinations, comparison metric, and range.
327  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
328  const APInt &Low, const APInt &High);
329 
330  /// Build a bit test cluster from Clusters[First..Last]. Returns false if it
331  /// decides it's not a good idea.
332  bool buildBitTests(CaseClusterVector &Clusters, unsigned First, unsigned Last,
333  const SwitchInst *SI, CaseCluster &BTCluster);
334 
335  /// Find clusters of cases suitable for bit test lowering.
336  void findBitTestClusters(CaseClusterVector &Clusters, const SwitchInst *SI);
337 
338  struct SwitchWorkListItem {
339  MachineBasicBlock *MBB;
340  CaseClusterIt FirstCluster;
341  CaseClusterIt LastCluster;
342  const ConstantInt *GE;
343  const ConstantInt *LT;
344  BranchProbability DefaultProb;
345  };
346  typedef SmallVector<SwitchWorkListItem, 4> SwitchWorkList;
347 
348  /// Determine the rank by weight of CC in [First,Last]. If CC has more weight
349  /// than each cluster in the range, its rank is 0.
350  static unsigned caseClusterRank(const CaseCluster &CC, CaseClusterIt First,
351  CaseClusterIt Last);
352 
353  /// Emit comparison and split W into two subtrees.
354  void splitWorkItem(SwitchWorkList &WorkList, const SwitchWorkListItem &W,
355  Value *Cond, MachineBasicBlock *SwitchMBB);
356 
357  /// Lower W.
358  void lowerWorkItem(SwitchWorkListItem W, Value *Cond,
359  MachineBasicBlock *SwitchMBB,
360  MachineBasicBlock *DefaultMBB);
361 
362 
363  /// A class which encapsulates all of the information needed to generate a
364  /// stack protector check and signals to isel via its state being initialized
365  /// that a stack protector needs to be generated.
366  ///
367  /// *NOTE* The following is a high level documentation of SelectionDAG Stack
368  /// Protector Generation. The reason that it is placed here is for a lack of
369  /// other good places to stick it.
370  ///
371  /// High Level Overview of SelectionDAG Stack Protector Generation:
372  ///
373  /// Previously, generation of stack protectors was done exclusively in the
374  /// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
375  /// splitting basic blocks at the IR level to create the success/failure basic
376  /// blocks in the tail of the basic block in question. As a result of this,
377  /// calls that would have qualified for the sibling call optimization were no
378  /// longer eligible for optimization since said calls were no longer right in
379  /// the "tail position" (i.e. the immediate predecessor of a ReturnInst
380  /// instruction).
381  ///
382  /// Then it was noticed that since the sibling call optimization causes the
383  /// callee to reuse the caller's stack, if we could delay the generation of
384  /// the stack protector check until later in CodeGen after the sibling call
385  /// decision was made, we get both the tail call optimization and the stack
386  /// protector check!
387  ///
388  /// A few goals in solving this problem were:
389  ///
390  /// 1. Preserve the architecture independence of stack protector generation.
391  ///
392  /// 2. Preserve the normal IR level stack protector check for platforms like
393  /// OpenBSD for which we support platform-specific stack protector
394  /// generation.
395  ///
396  /// The main problem that guided the present solution is that one can not
397  /// solve this problem in an architecture independent manner at the IR level
398  /// only. This is because:
399  ///
400  /// 1. The decision on whether or not to perform a sibling call on certain
401  /// platforms (for instance i386) requires lower level information
402  /// related to available registers that can not be known at the IR level.
403  ///
404  /// 2. Even if the previous point were not true, the decision on whether to
405  /// perform a tail call is done in LowerCallTo in SelectionDAG which
406  /// occurs after the Stack Protector Pass. As a result, one would need to
407  /// put the relevant callinst into the stack protector check success
408  /// basic block (where the return inst is placed) and then move it back
409  /// later at SelectionDAG/MI time before the stack protector check if the
410  /// tail call optimization failed. The MI level option was nixed
411  /// immediately since it would require platform-specific pattern
412  /// matching. The SelectionDAG level option was nixed because
413  /// SelectionDAG only processes one IR level basic block at a time
414  /// implying one could not create a DAG Combine to move the callinst.
415  ///
416  /// To get around this problem a few things were realized:
417  ///
418  /// 1. While one can not handle multiple IR level basic blocks at the
419  /// SelectionDAG Level, one can generate multiple machine basic blocks
420  /// for one IR level basic block. This is how we handle bit tests and
421  /// switches.
422  ///
423  /// 2. At the MI level, tail calls are represented via a special return
424  /// MIInst called "tcreturn". Thus if we know the basic block in which we
425  /// wish to insert the stack protector check, we get the correct behavior
426  /// by always inserting the stack protector check right before the return
427  /// statement. This is a "magical transformation" since no matter where
428  /// the stack protector check intrinsic is, we always insert the stack
429  /// protector check code at the end of the BB.
430  ///
431  /// Given the aforementioned constraints, the following solution was devised:
432  ///
433  /// 1. On platforms that do not support SelectionDAG stack protector check
434  /// generation, allow for the normal IR level stack protector check
435  /// generation to continue.
436  ///
437  /// 2. On platforms that do support SelectionDAG stack protector check
438  /// generation:
439  ///
440  /// a. Use the IR level stack protector pass to decide if a stack
441  /// protector is required/which BB we insert the stack protector check
442  /// in by reusing the logic already therein. If we wish to generate a
443  /// stack protector check in a basic block, we place a special IR
444  /// intrinsic called llvm.stackprotectorcheck right before the BB's
445  /// returninst or if there is a callinst that could potentially be
446  /// sibling call optimized, before the call inst.
447  ///
448  /// b. Then when a BB with said intrinsic is processed, we codegen the BB
449  /// normally via SelectBasicBlock. In said process, when we visit the
450  /// stack protector check, we do not actually emit anything into the
451  /// BB. Instead, we just initialize the stack protector descriptor
452  /// class (which involves stashing information/creating the success
453  /// mbbb and the failure mbb if we have not created one for this
454  /// function yet) and export the guard variable that we are going to
455  /// compare.
456  ///
457  /// c. After we finish selecting the basic block, in FinishBasicBlock if
458  /// the StackProtectorDescriptor attached to the SelectionDAGBuilder is
459  /// initialized, we produce the validation code with one of these
460  /// techniques:
461  /// 1) with a call to a guard check function
462  /// 2) with inlined instrumentation
463  ///
464  /// 1) We insert a call to the check function before the terminator.
465  ///
466  /// 2) We first find a splice point in the parent basic block
467  /// before the terminator and then splice the terminator of said basic
468  /// block into the success basic block. Then we code-gen a new tail for
469  /// the parent basic block consisting of the two loads, the comparison,
470  /// and finally two branches to the success/failure basic blocks. We
471  /// conclude by code-gening the failure basic block if we have not
472  /// code-gened it already (all stack protector checks we generate in
473  /// the same function, use the same failure basic block).
474  class StackProtectorDescriptor {
475  public:
476  StackProtectorDescriptor()
477  : ParentMBB(nullptr), SuccessMBB(nullptr), FailureMBB(nullptr) {}
478 
479  /// Returns true if all fields of the stack protector descriptor are
480  /// initialized implying that we should/are ready to emit a stack protector.
481  bool shouldEmitStackProtector() const {
482  return ParentMBB && SuccessMBB && FailureMBB;
483  }
484 
485  bool shouldEmitFunctionBasedCheckStackProtector() const {
486  return ParentMBB && !SuccessMBB && !FailureMBB;
487  }
488 
489  /// Initialize the stack protector descriptor structure for a new basic
490  /// block.
491  void initialize(const BasicBlock *BB, MachineBasicBlock *MBB,
492  bool FunctionBasedInstrumentation) {
493  // Make sure we are not initialized yet.
494  assert(!shouldEmitStackProtector() && "Stack Protector Descriptor is "
495  "already initialized!");
496  ParentMBB = MBB;
497  if (!FunctionBasedInstrumentation) {
498  SuccessMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ true);
499  FailureMBB = AddSuccessorMBB(BB, MBB, /* IsLikely */ false, FailureMBB);
500  }
501  }
502 
503  /// Reset state that changes when we handle different basic blocks.
504  ///
505  /// This currently includes:
506  ///
507  /// 1. The specific basic block we are generating a
508  /// stack protector for (ParentMBB).
509  ///
510  /// 2. The successor machine basic block that will contain the tail of
511  /// parent mbb after we create the stack protector check (SuccessMBB). This
512  /// BB is visited only on stack protector check success.
513  void resetPerBBState() {
514  ParentMBB = nullptr;
515  SuccessMBB = nullptr;
516  }
517 
518  /// Reset state that only changes when we switch functions.
519  ///
520  /// This currently includes:
521  ///
522  /// 1. FailureMBB since we reuse the failure code path for all stack
523  /// protector checks created in an individual function.
524  ///
525  /// 2.The guard variable since the guard variable we are checking against is
526  /// always the same.
527  void resetPerFunctionState() {
528  FailureMBB = nullptr;
529  }
530 
531  MachineBasicBlock *getParentMBB() { return ParentMBB; }
532  MachineBasicBlock *getSuccessMBB() { return SuccessMBB; }
533  MachineBasicBlock *getFailureMBB() { return FailureMBB; }
534 
535  private:
536  /// The basic block for which we are generating the stack protector.
537  ///
538  /// As a result of stack protector generation, we will splice the
539  /// terminators of this basic block into the successor mbb SuccessMBB and
540  /// replace it with a compare/branch to the successor mbbs
541  /// SuccessMBB/FailureMBB depending on whether or not the stack protector
542  /// was violated.
543  MachineBasicBlock *ParentMBB;
544 
545  /// A basic block visited on stack protector check success that contains the
546  /// terminators of ParentMBB.
547  MachineBasicBlock *SuccessMBB;
548 
549  /// This basic block visited on stack protector check failure that will
550  /// contain a call to __stack_chk_fail().
551  MachineBasicBlock *FailureMBB;
552 
553  /// Add a successor machine basic block to ParentMBB. If the successor mbb
554  /// has not been created yet (i.e. if SuccMBB = 0), then the machine basic
555  /// block will be created. Assign a large weight if IsLikely is true.
556  MachineBasicBlock *AddSuccessorMBB(const BasicBlock *BB,
557  MachineBasicBlock *ParentMBB,
558  bool IsLikely,
559  MachineBasicBlock *SuccMBB = nullptr);
560  };
561 
562 private:
563  const TargetMachine &TM;
564 public:
565  /// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling
566  /// nodes without a corresponding SDNode.
567  static const unsigned LowestSDNodeOrder = 1;
568 
570  const DataLayout *DL;
573 
574  /// SwitchCases - Vector of CaseBlock structures used to communicate
575  /// SwitchInst code generation information.
576  std::vector<CaseBlock> SwitchCases;
577  /// JTCases - Vector of JumpTable structures used to communicate
578  /// SwitchInst code generation information.
579  std::vector<JumpTableBlock> JTCases;
580  /// BitTestCases - Vector of BitTestBlock structures used to communicate
581  /// SwitchInst code generation information.
582  std::vector<BitTestBlock> BitTestCases;
583  /// A StackProtectorDescriptor structure used to communicate stack protector
584  /// information in between SelectBasicBlock and FinishBasicBlock.
585  StackProtectorDescriptor SPDescriptor;
586 
587  // Emit PHI-node-operand constants only once even if used by multiple
588  // PHI nodes.
590 
591  /// FuncInfo - Information about the function as a whole.
592  ///
594 
595  /// GFI - Garbage collection metadata for the function.
597 
598  /// LPadToCallSiteMap - Map a landing pad to the call site indexes.
600 
601  /// HasTailCall - This is set to true if a call in the current
602  /// block has been translated as a tail call. In this case,
603  /// no subsequent DAG nodes should be created.
604  ///
606 
608 
611  : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
612  DAG(dag), FuncInfo(funcinfo),
613  HasTailCall(false) {
614  }
615 
616  void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
617  const TargetLibraryInfo *li);
618 
619  /// clear - Clear out the current SelectionDAG and the associated
620  /// state and prepare this SelectionDAGBuilder object to be used
621  /// for a new block. This doesn't clear out information about
622  /// additional blocks that are needed to complete switch lowering
623  /// or PHI node updating; that information is cleared out as it is
624  /// consumed.
625  void clear();
626 
627  /// clearDanglingDebugInfo - Clear the dangling debug information
628  /// map. This function is separated from the clear so that debug
629  /// information that is dangling in a basic block can be properly
630  /// resolved in a different basic block. This allows the
631  /// SelectionDAG to resolve dangling debug information attached
632  /// to PHI nodes.
633  void clearDanglingDebugInfo();
634 
635  /// getRoot - Return the current virtual root of the Selection DAG,
636  /// flushing any PendingLoad items. This must be done before emitting
637  /// a store or any other node that may need to be ordered after any
638  /// prior load instructions.
639  ///
640  SDValue getRoot();
641 
642  /// getControlRoot - Similar to getRoot, but instead of flushing all the
643  /// PendingLoad items, flush all the PendingExports items. It is necessary
644  /// to do this before emitting a terminator instruction.
645  ///
647 
648  SDLoc getCurSDLoc() const {
649  return SDLoc(CurInst, SDNodeOrder);
650  }
651 
653  return CurInst ? CurInst->getDebugLoc() : DebugLoc();
654  }
655 
656  void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
657 
658  void visit(const Instruction &I);
659 
660  void visit(unsigned Opcode, const User &I);
661 
662  /// getCopyFromRegs - If there was virtual register allocated for the value V
663  /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
664  SDValue getCopyFromRegs(const Value *V, Type *Ty);
665 
666  // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
667  // generate the debug data structures now that we've seen its definition.
668  void resolveDanglingDebugInfo(const Value *V, SDValue Val);
669  SDValue getValue(const Value *V);
670  bool findValue(const Value *V) const;
671 
673  SDValue getValueImpl(const Value *V);
674 
675  void setValue(const Value *V, SDValue NewN) {
676  SDValue &N = NodeMap[V];
677  assert(!N.getNode() && "Already set a value for this node!");
678  N = NewN;
679  }
680 
681  void setUnusedArgValue(const Value *V, SDValue NewN) {
682  SDValue &N = UnusedArgNodeMap[V];
683  assert(!N.getNode() && "Already set a value for this node!");
684  N = NewN;
685  }
686 
687  void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
689  MachineBasicBlock *SwitchBB,
691  BranchProbability FW);
693  MachineBasicBlock *FBB,
694  MachineBasicBlock *CurBB,
695  MachineBasicBlock *SwitchBB,
697  bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
698  bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
699  void CopyToExportRegsIfNeeded(const Value *V);
700  void ExportFromCurrentBlock(const Value *V);
701  void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
702  const BasicBlock *EHPadBB = nullptr);
703 
704  // Lower range metadata from 0 to N to assert zext to an integer of nearest
705  // floor power of two.
707  SDValue Op);
708 
710  ImmutableCallSite CS, unsigned ArgIdx,
711  unsigned NumArgs, SDValue Callee,
712  Type *ReturnTy, bool IsPatchPoint);
713 
714  std::pair<SDValue, SDValue>
716  const BasicBlock *EHPadBB = nullptr);
717 
718  /// UpdateSplitBlock - When an MBB was split during scheduling, update the
719  /// references that need to refer to the last resulting block.
721 
722  /// Describes a gc.statepoint or a gc.statepoint like thing for the purposes
723  /// of lowering into a STATEPOINT node.
725  /// Bases[i] is the base pointer for Ptrs[i]. Together they denote the set
726  /// of gc pointers this STATEPOINT has to relocate.
729 
730  /// The set of gc.relocate calls associated with this gc.statepoint.
732 
733  /// The full list of gc arguments to the gc.statepoint being lowered.
735 
736  /// The gc.statepoint instruction.
737  const Instruction *StatepointInstr = nullptr;
738 
739  /// The list of gc transition arguments present in the gc.statepoint being
740  /// lowered.
742 
743  /// The ID that the resulting STATEPOINT instruction has to report.
744  unsigned ID = -1;
745 
746  /// Information regarding the underlying call instruction.
748 
749  /// The deoptimization state associated with this gc.statepoint call, if
750  /// any.
752 
753  /// Flags associated with the meta arguments being lowered.
754  uint64_t StatepointFlags = -1;
755 
756  /// The number of patchable bytes the call needs to get lowered into.
757  unsigned NumPatchBytes = -1;
758 
759  /// The exception handling unwind destination, in case this represents an
760  /// invoke of gc.statepoint.
761  const BasicBlock *EHPadBB = nullptr;
762 
764  };
765 
766  /// Lower \p SLI into a STATEPOINT instruction.
767  SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SLI);
768 
769  // This function is responsible for the whole statepoint lowering process.
770  // It uniformly handles invoke and call statepoints.
772  const BasicBlock *EHPadBB = nullptr);
773 
775  const BasicBlock *EHPadBB);
776 
777  void LowerDeoptimizeCall(const CallInst *CI);
779 
781  const BasicBlock *EHPadBB,
782  bool VarArgDisallowed,
783  bool ForceVoidReturnTy);
784 
785 private:
786  // Terminator instructions.
787  void visitRet(const ReturnInst &I);
788  void visitBr(const BranchInst &I);
789  void visitSwitch(const SwitchInst &I);
790  void visitIndirectBr(const IndirectBrInst &I);
791  void visitUnreachable(const UnreachableInst &I);
792  void visitCleanupRet(const CleanupReturnInst &I);
793  void visitCatchSwitch(const CatchSwitchInst &I);
794  void visitCatchRet(const CatchReturnInst &I);
795  void visitCatchPad(const CatchPadInst &I);
796  void visitCleanupPad(const CleanupPadInst &CPI);
797 
798  BranchProbability getEdgeProbability(const MachineBasicBlock *Src,
799  const MachineBasicBlock *Dst) const;
800  void addSuccessorWithProb(
803 
804 public:
805  void visitSwitchCase(CaseBlock &CB,
806  MachineBasicBlock *SwitchBB);
807  void visitSPDescriptorParent(StackProtectorDescriptor &SPD,
808  MachineBasicBlock *ParentBB);
809  void visitSPDescriptorFailure(StackProtectorDescriptor &SPD);
810  void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
811  void visitBitTestCase(BitTestBlock &BB,
812  MachineBasicBlock* NextMBB,
813  BranchProbability BranchProbToNext,
814  unsigned Reg,
815  BitTestCase &B,
816  MachineBasicBlock *SwitchBB);
817  void visitJumpTable(JumpTable &JT);
818  void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
819  MachineBasicBlock *SwitchBB);
820 
821 private:
822  // These all get lowered before this pass.
823  void visitInvoke(const InvokeInst &I);
824  void visitResume(const ResumeInst &I);
825 
826  void visitBinary(const User &I, unsigned OpCode);
827  void visitShift(const User &I, unsigned Opcode);
828  void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
829  void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
830  void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
831  void visitFSub(const User &I);
832  void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
833  void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
834  void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
835  void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
836  void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
837  void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
838  void visitSDiv(const User &I);
839  void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
840  void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
841  void visitOr (const User &I) { visitBinary(I, ISD::OR); }
842  void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
843  void visitShl (const User &I) { visitShift(I, ISD::SHL); }
844  void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
845  void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
846  void visitICmp(const User &I);
847  void visitFCmp(const User &I);
848  // Visit the conversion instructions
849  void visitTrunc(const User &I);
850  void visitZExt(const User &I);
851  void visitSExt(const User &I);
852  void visitFPTrunc(const User &I);
853  void visitFPExt(const User &I);
854  void visitFPToUI(const User &I);
855  void visitFPToSI(const User &I);
856  void visitUIToFP(const User &I);
857  void visitSIToFP(const User &I);
858  void visitPtrToInt(const User &I);
859  void visitIntToPtr(const User &I);
860  void visitBitCast(const User &I);
861  void visitAddrSpaceCast(const User &I);
862 
863  void visitExtractElement(const User &I);
864  void visitInsertElement(const User &I);
865  void visitShuffleVector(const User &I);
866 
867  void visitExtractValue(const ExtractValueInst &I);
868  void visitInsertValue(const InsertValueInst &I);
869  void visitLandingPad(const LandingPadInst &I);
870 
871  void visitGetElementPtr(const User &I);
872  void visitSelect(const User &I);
873 
874  void visitAlloca(const AllocaInst &I);
875  void visitLoad(const LoadInst &I);
876  void visitStore(const StoreInst &I);
877  void visitMaskedLoad(const CallInst &I, bool IsExpanding = false);
878  void visitMaskedStore(const CallInst &I, bool IsCompressing = false);
879  void visitMaskedGather(const CallInst &I);
880  void visitMaskedScatter(const CallInst &I);
881  void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
882  void visitAtomicRMW(const AtomicRMWInst &I);
883  void visitFence(const FenceInst &I);
884  void visitPHI(const PHINode &I);
885  void visitCall(const CallInst &I);
886  bool visitMemCmpCall(const CallInst &I);
887  bool visitMemPCpyCall(const CallInst &I);
888  bool visitMemChrCall(const CallInst &I);
889  bool visitStrCpyCall(const CallInst &I, bool isStpcpy);
890  bool visitStrCmpCall(const CallInst &I);
891  bool visitStrLenCall(const CallInst &I);
892  bool visitStrNLenCall(const CallInst &I);
893  bool visitUnaryFloatCall(const CallInst &I, unsigned Opcode);
894  bool visitBinaryFloatCall(const CallInst &I, unsigned Opcode);
895  void visitAtomicLoad(const LoadInst &I);
896  void visitAtomicStore(const StoreInst &I);
897  void visitLoadFromSwiftError(const LoadInst &I);
898  void visitStoreToSwiftError(const StoreInst &I);
899 
900  void visitInlineAsm(ImmutableCallSite CS);
901  const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
902  void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
903 
904  void visitVAStart(const CallInst &I);
905  void visitVAArg(const VAArgInst &I);
906  void visitVAEnd(const CallInst &I);
907  void visitVACopy(const CallInst &I);
908  void visitStackmap(const CallInst &I);
909  void visitPatchpoint(ImmutableCallSite CS,
910  const BasicBlock *EHPadBB = nullptr);
911 
912  // These two are implemented in StatepointLowering.cpp
913  void visitGCRelocate(const GCRelocateInst &I);
914  void visitGCResult(const GCResultInst &I);
915 
916  void visitUserOp1(const Instruction &I) {
917  llvm_unreachable("UserOp1 should not exist at instruction selection time!");
918  }
919  void visitUserOp2(const Instruction &I) {
920  llvm_unreachable("UserOp2 should not exist at instruction selection time!");
921  }
922 
923  void processIntegerCallValue(const Instruction &I,
924  SDValue Value, bool IsSigned);
925 
926  void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
927 
928  void emitInlineAsmError(ImmutableCallSite CS, const Twine &Message);
929 
930  /// EmitFuncArgumentDbgValue - If V is an function argument then create
931  /// corresponding DBG_VALUE machine instruction for it now. At the end of
932  /// instruction selection, they will be inserted to the entry BB.
933  bool EmitFuncArgumentDbgValue(const Value *V, DILocalVariable *Variable,
934  DIExpression *Expr, DILocation *DL,
935  int64_t Offset, bool IsIndirect,
936  const SDValue &N);
937 
938  /// Return the next block after MBB, or nullptr if there is none.
939  MachineBasicBlock *NextBlock(MachineBasicBlock *MBB);
940 
941  /// Update the DAG and DAG builder with the relevant information after
942  /// a new root node has been created which could be a tail call.
943  void updateDAGForMaybeTailCall(SDValue MaybeTC);
944 
945  /// Return the appropriate SDDbgValue based on N.
946  SDDbgValue *getDbgValue(SDValue N, DILocalVariable *Variable,
947  DIExpression *Expr, int64_t Offset, DebugLoc dl,
948  unsigned DbgSDNodeOrder);
949 };
950 
951 /// RegsForValue - This struct represents the registers (physical or virtual)
952 /// that a particular set of values is assigned, and the type information about
953 /// the value. The most common situation is to represent one value at a time,
954 /// but struct or array values are handled element-wise as multiple values. The
955 /// splitting of aggregates is performed recursively, so that we never have
956 /// aggregate-typed registers. The values at this point do not necessarily have
957 /// legal types, so each value may require one or more registers of some legal
958 /// type.
959 ///
960 struct RegsForValue {
961  /// ValueVTs - The value types of the values, which may not be legal, and
962  /// may need be promoted or synthesized from one or more registers.
963  ///
965 
966  /// RegVTs - The value types of the registers. This is the same size as
967  /// ValueVTs and it records, for each value, what the type of the assigned
968  /// register or registers are. (Individual values are never synthesized
969  /// from more than one type of register.)
970  ///
971  /// With virtual registers, the contents of RegVTs is redundant with TLI's
972  /// getRegisterType member function, however when with physical registers
973  /// it is necessary to have a separate record of the types.
974  ///
976 
977  /// Regs - This list holds the registers assigned to the values.
978  /// Each legal or promoted value requires one register, and each
979  /// expanded value requires multiple registers.
980  ///
982 
983  RegsForValue();
984 
985  RegsForValue(const SmallVector<unsigned, 4> &regs, MVT regvt, EVT valuevt);
986 
988  const DataLayout &DL, unsigned Reg, Type *Ty);
989 
990  /// append - Add the specified values to this one.
991  void append(const RegsForValue &RHS) {
992  ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
993  RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
994  Regs.append(RHS.Regs.begin(), RHS.Regs.end());
995  }
996 
997  /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
998  /// this value and returns the result as a ValueVTs value. This uses
999  /// Chain/Flag as the input and updates them for the output Chain/Flag.
1000  /// If the Flag pointer is NULL, no flag is used.
1002  const SDLoc &dl, SDValue &Chain, SDValue *Flag,
1003  const Value *V = nullptr) const;
1004 
1005  /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified
1006  /// value into the registers specified by this object. This uses Chain/Flag
1007  /// as the input and updates them for the output Chain/Flag. If the Flag
1008  /// pointer is nullptr, no flag is used. If V is not nullptr, then it is used
1009  /// in printing better diagnostic messages on error.
1010  void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl,
1011  SDValue &Chain, SDValue *Flag, const Value *V = nullptr,
1012  ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
1013 
1014  /// AddInlineAsmOperands - Add this value to the specified inlineasm node
1015  /// operand list. This adds the code marker, matching input operand index
1016  /// (if applicable), and includes the number of values added into it.
1017  void AddInlineAsmOperands(unsigned Kind, bool HasMatching,
1018  unsigned MatchingIdx, const SDLoc &dl,
1019  SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
1020 };
1021 
1022 } // end namespace llvm
1023 
1024 #endif
MachineLoop * L
Return a value (possibly void), from a function.
std::vector< BitTestBlock > BitTestCases
BitTestCases - Vector of BitTestBlock structures used to communicate SwitchInst code generation infor...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
bool findValue(const Value *V) const
LLVMContext & Context
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block...
const TargetLibraryInfo * LibInfo
StatepointFlags
The statepoint intrinsic accepts a set of flags as its third argument.
Definition: Statepoint.h:40
Various leaf nodes.
Definition: ISDOpcodes.h:60
void LowerDeoptimizeCall(const CallInst *CI)
TargetLowering::CallLoweringInfo CLI
Information regarding the underlying call instruction.
void CopyValueToVirtualRegister(const Value *V, unsigned Reg)
SmallVector< const GCRelocateInst *, 16 > GCRelocates
The set of gc.relocate calls associated with this gc.statepoint.
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
A specialization of it's base class for read only access to a gc.statepoint.
Definition: Statepoint.h:300
void LowerStatepoint(ImmutableStatepoint Statepoint, const BasicBlock *EHPadBB=nullptr)
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, CodeGenOpt::Level ol)
This class represents a function call, abstracting a target machine's calling convention.
void setValue(const Value *V, SDValue NewN)
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
demanded bits
A debug info location.
Definition: DebugLoc.h:34
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
DebugLoc getCurDebugLoc() const
uint64_t High
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
unsigned ID
The ID that the resulting STATEPOINT instruction has to report.
StackProtectorDescriptor SPDescriptor
A StackProtectorDescriptor structure used to communicate stack protector information in between Selec...
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
SDValue getRoot()
getRoot - Return the current virtual root of the Selection DAG, flushing any PendingLoad items...
void AddInlineAsmOperands(unsigned Kind, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector< SDValue > &Ops) const
AddInlineAsmOperands - Add this value to the specified inlineasm node operand list.
void visitSwitchCase(CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
Shift and rotation operations.
Definition: ISDOpcodes.h:344
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, BranchProbability TW, BranchProbability FW)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
void visitJumpTable(JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
ArrayRef< const Use > GCTransitionArgs
The list of gc transition arguments present in the gc.statepoint being lowered.
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
SmallVector< EVT, 4 > ValueVTs
ValueVTs - The value types of the values, which may not be legal, and may need be promoted or synthes...
Reg
All possible values of the reg field in the ModR/M byte.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void LowerCallSiteWithDeoptBundle(ImmutableCallSite CS, SDValue Callee, const BasicBlock *EHPadBB)
This file implements a class to represent arbitrary precision integral constant values and operations...
#define F(x, y, z)
Definition: MD5.cpp:51
MachineBasicBlock * MBB
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don't look in FuncInfo.ValueMap for a virtual register.
Function Alias Analysis false
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool ShouldEmitAsBranches(const std::vector< CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op)
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
uint64_t * Cases
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, bool IsPatchPoint)
Populate a CallLowerinInfo (into CLI) based on the properties of the call being lowered.
void append(const RegsForValue &RHS)
append - Add the specified values to this one.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
SDNode * getNode() const
get the SDNode which holds the desired result
#define P(N)
std::pair< SDValue, SDValue > lowerInvokable(TargetLowering::CallLoweringInfo &CLI, const BasicBlock *EHPadBB=nullptr)
const Instruction * StatepointInstr
The gc.statepoint instruction.
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, const SDLoc &dl, SDValue &Chain, SDValue *Flag, const Value *V=nullptr) const
getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from this value and returns the resu...
bool HasTailCall
HasTailCall - This is set to true if a call in the current block has been translated as a tail call...
ArrayRef< const Use > DeoptState
The deoptimization state associated with this gc.statepoint call, if any.
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
Simple binary floating point operators.
Definition: ISDOpcodes.h:246
Conditional or Unconditional Branch instruction.
This function has undefined behavior.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
Resume the propagation of an exception.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Indirect Branch Instruction.
#define H(x, y, z)
Definition: MD5.cpp:53
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:259
uint32_t Offset
This class tracks both per-statepoint and per-selectiondag information.
A specialization of it's base class for read-write access to a gc.statepoint.
Definition: Statepoint.h:313
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:392
EVT - Extended Value Type.
Definition: ValueTypes.h:31
This structure contains all information that is necessary for lowering calls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it, emit nodes to copy the value into the virtual registers.
static BranchProbability getUnknown()
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
This is the shared class of boolean and integer constants.
Definition: Constants.h:88
SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SLI)
Lower SLI into a STATEPOINT instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
RegsForValue - This struct represents the registers (physical or virtual) that a particular set of va...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
Provides information about what library functions are available for the current target.
void clear()
clear - Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuil...
void visit(const Instruction &I)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
UpdateSplitBlock - When an MBB was split during scheduling, update the references that need to refer ...
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
GCFunctionInfo * GFI
GFI - Garbage collection metadata for the function.
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringRef > StandardNames)
initialize - Initialize the set of available library functions based on the specified target triple...
void visitBitTestCase(BitTestBlock &BB, MachineBasicBlock *NextMBB, BranchProbability BranchProbToNext, unsigned Reg, BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
std::vector< JumpTableBlock > JTCases
JTCases - Vector of JumpTable structures used to communicate SwitchInst code generation information...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:403
SmallVector< SDValue, 8 > PendingLoads
PendingLoads - Loads are not emitted to the program immediately.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:333
This represents the llvm.dbg.value instruction.
ImmutableCallSite - establish a view to a call site for examination.
Definition: CallSite.h:665
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
SmallVector< const Value *, 16 > Bases
Bases[i] is the base pointer for Ptrs[i].
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
SDValue getCopyFromRegs(const Value *V, Type *Ty)
getCopyFromRegs - If there was virtual register allocated for the value V emit CopyFromReg of the spe...
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall, const BasicBlock *EHPadBB=nullptr)
const unsigned Kind
unsigned NumPatchBytes
The number of patchable bytes the call needs to get lowered into.
Multiway switch.
void LowerCallSiteWithDeoptBundleImpl(ImmutableCallSite CS, SDValue Callee, const BasicBlock *EHPadBB, bool VarArgDisallowed, bool ForceVoidReturnTy)
FunctionLoweringInfo & FuncInfo
FuncInfo - Information about the function as a whole.
SmallVector< MVT, 4 > RegVTs
RegVTs - The value types of the registers.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const BasicBlock * EHPadBB
The exception handling unwind destination, in case this represents an invoke of gc.statepoint.
void setUnusedArgValue(const Value *V, SDValue NewN)
LLVM Value Representation.
Definition: Value.h:71
void init(GCFunctionInfo *gfi, AliasAnalysis &aa, const TargetLibraryInfo *li)
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, Instruction::BinaryOps Opc, BranchProbability TW, BranchProbability FW)
FindMergedConditions - If Cond is an expression like.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
ArrayRef< const Use > GCArgs
The full list of gc arguments to the gc.statepoint being lowered.
Invoke instruction.
std::vector< CaseBlock > SwitchCases
SwitchCases - Vector of CaseBlock structures used to communicate SwitchInst code generation informati...
SDValue getControlRoot()
getControlRoot - Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports items.
Garbage collection metadata for a single function.
Definition: GCMetadata.h:74
void clearDanglingDebugInfo()
clearDanglingDebugInfo - Clear the dangling debug information map.
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
LPadToCallSiteMap - Map a landing pad to the call site indexes.
DenseMap< const Constant *, unsigned > ConstantsOut
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
SmallVector< unsigned, 4 > Regs
Regs - This list holds the registers assigned to the values.
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests" ...
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, SDValue *Flag, const Value *V=nullptr, ISD::NodeType PreferredExtendType=ISD::ANY_EXTEND) const
getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified value into the registers s...
Describes a gc.statepoint or a gc.statepoint like thing for the purposes of lowering into a STATEPOIN...
This file describes how to lower LLVM code to machine code.