LLVM  4.0.0
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::SIInstrInfo Class Referencefinal

#include <SIInstrInfo.h>

Inheritance diagram for llvm::SIInstrInfo:
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Collaboration diagram for llvm::SIInstrInfo:
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Public Types

enum  TargetOperandFlags {
  MO_NONE = 0, MO_GOTPCREL = 1, MO_GOTPCREL32 = 2, MO_GOTPCREL32_LO = 2,
  MO_GOTPCREL32_HI = 3, MO_REL32 = 4, MO_REL32_LO = 4, MO_REL32_HI = 5
}
 

Public Member Functions

 SIInstrInfo (const SISubtarget &)
 
const SIRegisterInfogetRegisterInfo () const
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 
bool getMemOpBaseRegImmOfs (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const final
 
bool shouldClusterMemOps (MachineInstr &FirstLdSt, MachineInstr &SecondLdSt, unsigned NumLoads) const final
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
unsigned calculateLDSSpillAddress (MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
unsigned getMovOpcode (const TargetRegisterClass *DstRC) const
 
LLVM_READONLY int commuteOpcode (unsigned Opc) const
 
LLVM_READONLY int commuteOpcode (const MachineInstr &MI) const
 
bool findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
MachineBasicBlockgetBranchDestBlock (const MachineInstr &MI) const override
 
unsigned insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
 
bool analyzeBranchImpl (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool areMemAccessesTriviallyDisjoint (MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
 
unsigned getMachineCSELookAheadLimit () const override
 
MachineInstrconvertToThreeAddress (MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool isSALU (uint16_t Opcode) const
 
bool isVALU (uint16_t Opcode) const
 
bool isVMEM (uint16_t Opcode) const
 
bool isSOP1 (uint16_t Opcode) const
 
bool isSOP2 (uint16_t Opcode) const
 
bool isSOPC (uint16_t Opcode) const
 
bool isSOPK (uint16_t Opcode) const
 
bool isSOPP (uint16_t Opcode) const
 
bool isVOP1 (uint16_t Opcode) const
 
bool isVOP2 (uint16_t Opcode) const
 
bool isVOP3 (uint16_t Opcode) const
 
bool isVOPC (uint16_t Opcode) const
 
bool isMUBUF (uint16_t Opcode) const
 
bool isMTBUF (uint16_t Opcode) const
 
bool isSMRD (uint16_t Opcode) const
 
bool isDS (uint16_t Opcode) const
 
bool isMIMG (uint16_t Opcode) const
 
bool isGather4 (uint16_t Opcode) const
 
bool isFLAT (uint16_t Opcode) const
 
bool isEXP (uint16_t Opcode) const
 
bool isWQM (uint16_t Opcode) const
 
bool isDisableWQM (uint16_t Opcode) const
 
bool isVGPRSpill (uint16_t Opcode) const
 
bool isSGPRSpill (uint16_t Opcode) const
 
bool isDPP (uint16_t Opcode) const
 
bool sopkIsZext (uint16_t Opcode) const
 
bool isScalarStore (uint16_t Opcode) const
 
bool isFixedSize (uint16_t Opcode) const
 
bool isVGPRCopy (const MachineInstr &MI) const
 
bool isInlineConstant (const APInt &Imm) const
 
bool isInlineConstant (const MachineOperand &MO, uint8_t OperandType) const
 
bool isInlineConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isInlineConstant (const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
 returns true if UseMO is substituted with DefMO in MI it would be an inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx) const
 returns true if the operand OpIdx in MI is a valid inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
 
bool isInlineConstant (const MachineOperand &MO) const
 
bool isLiteralConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isLiteralConstant (const MachineInstr &MI, int OpIdx) const
 
bool isLiteralConstantLike (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isImmOperandLegal (const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
 
bool hasVALU32BitEncoding (unsigned Opcode) const
 Return true if this 64-bit VALU instruction has a 32-bit encoding. More...
 
bool usesConstantBus (const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 Returns true if this operand uses the constant bus. More...
 
bool hasModifiers (unsigned Opcode) const
 Return true if this instruction has any modifiers. More...
 
bool hasModifiersSet (const MachineInstr &MI, unsigned OpName) const
 
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
 
bool isSALUOpSupportedOnVALU (const MachineInstr &MI) const
 
const TargetRegisterClassgetOpRegClass (const MachineInstr &MI, unsigned OpNo) const
 Return the correct register class for OpNo. More...
 
unsigned getOpSize (uint16_t Opcode, unsigned OpNo) const
 Return the size in bytes of the operand OpNo on the given. More...
 
unsigned getOpSize (const MachineInstr &MI, unsigned OpNo) const
 This form should usually be preferred since it handles operands with unknown register classes. More...
 
bool canReadVGPR (const MachineInstr &MI, unsigned OpNo) const
 
void legalizeOpWithMove (MachineInstr &MI, unsigned OpIdx) const
 Legalize the OpIndex operand of this instruction by inserting a MOV. More...
 
bool isOperandLegal (const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
 Check if MO is a legal operand if it was the OpIdx Operand for MI. More...
 
bool isLegalVSrcOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO would be a valid operand for the given operand definition OpInfo. More...
 
bool isLegalRegOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO (a register operand) is a legal register for the given operand description. More...
 
void legalizeOperandsVOP2 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Legalize operands in MI by either commuting it or inserting a copy of src1. More...
 
void legalizeOperandsVOP3 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Fix operands in MI to satisfy constant bus requirements. More...
 
unsigned readlaneVGPRToSGPR (unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
 Copy a value from a VGPR (SrcReg) to SGPR. More...
 
void legalizeOperandsSMRD (MachineRegisterInfo &MRI, MachineInstr &MI) const
 
void legalizeGenericOperand (MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
 
void legalizeOperands (MachineInstr &MI) const
 Legalize all operands in this instruction. More...
 
void moveToVALU (MachineInstr &MI) const
 Replace this instruction's opcode with the equivalent VALU opcode. More...
 
void insertWaitStates (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
unsigned getNumWaitStates (const MachineInstr &MI) const
 Return the number of wait states that result from executing this instruction. More...
 
LLVM_READONLY MachineOperandgetNamedOperand (MachineInstr &MI, unsigned OperandName) const
 Returns the operand named Op. More...
 
LLVM_READONLY const
MachineOperand
getNamedOperand (const MachineInstr &MI, unsigned OpName) const
 
int64_t getNamedImmOperand (const MachineInstr &MI, unsigned OpName) const
 Get required immediate operand. More...
 
uint64_t getDefaultRsrcDataFormat () const
 
uint64_t getScratchRsrcWords23 () const
 
bool isLowLatencyInstruction (const MachineInstr &MI) const
 
bool isHighLatencyInstruction (const MachineInstr &MI) const
 
const MCInstrDescgetMCOpcodeFromPseudo (unsigned Opcode) const
 Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...
 
unsigned isStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isSGPRStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 
bool mayAccessFlatAddressSpace (const MachineInstr &MI) const
 
ArrayRef< std::pair< int,
const char * > > 
getSerializableTargetIndices () const override
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 This is used by the post-RA scheduler (SchedulePostRAList.cpp). More...
 
ScheduleHazardRecognizerCreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const override
 This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass. More...
 
- Public Member Functions inherited from llvm::AMDGPUInstrInfo
 AMDGPUInstrInfo (const AMDGPUSubtarget &st)
 
bool shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 
int getMaskedMIMGOp (uint16_t Opcode, unsigned Channels) const
 Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels. More...
 

Static Public Member Functions

static bool isSALU (const MachineInstr &MI)
 
static bool isVALU (const MachineInstr &MI)
 
static bool isVMEM (const MachineInstr &MI)
 
static bool isSOP1 (const MachineInstr &MI)
 
static bool isSOP2 (const MachineInstr &MI)
 
static bool isSOPC (const MachineInstr &MI)
 
static bool isSOPK (const MachineInstr &MI)
 
static bool isSOPP (const MachineInstr &MI)
 
static bool isVOP1 (const MachineInstr &MI)
 
static bool isVOP2 (const MachineInstr &MI)
 
static bool isVOP3 (const MachineInstr &MI)
 
static bool isVOPC (const MachineInstr &MI)
 
static bool isMUBUF (const MachineInstr &MI)
 
static bool isMTBUF (const MachineInstr &MI)
 
static bool isSMRD (const MachineInstr &MI)
 
static bool isDS (const MachineInstr &MI)
 
static bool isMIMG (const MachineInstr &MI)
 
static bool isGather4 (const MachineInstr &MI)
 
static bool isFLAT (const MachineInstr &MI)
 
static bool isEXP (const MachineInstr &MI)
 
static bool isWQM (const MachineInstr &MI)
 
static bool isDisableWQM (const MachineInstr &MI)
 
static bool isVGPRSpill (const MachineInstr &MI)
 
static bool isSGPRSpill (const MachineInstr &MI)
 
static bool isDPP (const MachineInstr &MI)
 
static bool isScalarUnit (const MachineInstr &MI)
 
static bool usesVM_CNT (const MachineInstr &MI)
 
static bool sopkIsZext (const MachineInstr &MI)
 
static bool isScalarStore (const MachineInstr &MI)
 
static bool isFixedSize (const MachineInstr &MI)
 
static int operandBitWidth (uint8_t OperandType)
 
static unsigned getVALUOp (const MachineInstr &MI)
 

Protected Member Functions

bool swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
 
MachineInstrcommuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
 

Detailed Description

Definition at line 25 of file SIInstrInfo.h.

Member Enumeration Documentation

Enumerator
MO_NONE 
MO_GOTPCREL 
MO_GOTPCREL32 
MO_GOTPCREL32_LO 
MO_GOTPCREL32_HI 
MO_REL32 
MO_REL32_LO 
MO_REL32_HI 

Definition at line 99 of file SIInstrInfo.h.

Constructor & Destructor Documentation

SIInstrInfo::SIInstrInfo ( const SISubtarget ST)
explicit

Definition at line 38 of file SIInstrInfo.cpp.

Member Function Documentation

bool SIInstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
override
bool SIInstrInfo::analyzeBranchImpl ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const
bool SIInstrInfo::areLoadsFromSameBasePtr ( SDNode Load1,
SDNode Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override
bool SIInstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr MIa,
MachineInstr MIb,
AliasAnalysis AA = nullptr 
) const
override
unsigned SIInstrInfo::calculateLDSSpillAddress ( MachineBasicBlock MBB,
MachineInstr MI,
RegScavenger RS,
unsigned  TmpReg,
unsigned  FrameOffset,
unsigned  Size 
) const
bool SIInstrInfo::canReadVGPR ( const MachineInstr MI,
unsigned  OpNo 
) const
Returns
true if it is legal for the operand at index OpNo to read a VGPR.

Definition at line 2208 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), getOpRegClass(), and llvm::SIRegisterInfo::hasVGPRs().

MachineInstr * SIInstrInfo::commuteInstructionImpl ( MachineInstr MI,
bool  NewMI,
unsigned  OpIdx0,
unsigned  OpIdx1 
) const
overrideprotected
int SIInstrInfo::commuteOpcode ( unsigned  Opc) const
LLVM_READONLY int llvm::SIInstrInfo::commuteOpcode ( const MachineInstr MI) const
inline

Definition at line 165 of file SIInstrInfo.h.

References commuteOpcode(), and llvm::MachineInstr::getOpcode().

MachineInstr * SIInstrInfo::convertToThreeAddress ( MachineFunction::iterator MBB,
MachineInstr MI,
LiveVariables LV 
) const
override
void SIInstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override
ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData II,
const ScheduleDAG DAG 
) const
override

This is used by the post-RA scheduler (SchedulePostRAList.cpp).

The post-RA version of misched uses CreateTargetMIHazardRecognizer.

Definition at line 3632 of file SIInstrInfo.cpp.

References llvm::ScheduleDAG::MF.

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const MachineFunction MF) const
override

This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.

Definition at line 3640 of file SIInstrInfo.cpp.

bool SIInstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override
bool SIInstrInfo::findCommutedOpIndices ( MachineInstr MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2 
) const
override
bool SIInstrInfo::FoldImmediate ( MachineInstr UseMI,
MachineInstr DefMI,
unsigned  Reg,
MachineRegisterInfo MRI 
) const
final
MachineBasicBlock * SIInstrInfo::getBranchDestBlock ( const MachineInstr MI) const
override
uint64_t SIInstrInfo::getDefaultRsrcDataFormat ( ) const
unsigned SIInstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override
unsigned llvm::SIInstrInfo::getMachineCSELookAheadLimit ( ) const
inlineoverride

Definition at line 213 of file SIInstrInfo.h.

const MCInstrDesc& llvm::SIInstrInfo::getMCOpcodeFromPseudo ( unsigned  Opcode) const
inline

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.

Definition at line 709 of file SIInstrInfo.h.

References llvm::AMDGPUInstrInfo::pseudoToMCOpcode().

Referenced by getInstSizeInBytes().

bool SIInstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
const TargetRegisterInfo TRI 
) const
final
unsigned SIInstrInfo::getMovOpcode ( const TargetRegisterClass DstRC) const
int64_t llvm::SIInstrInfo::getNamedImmOperand ( const MachineInstr MI,
unsigned  OpName 
) const
inline
MachineOperand * SIInstrInfo::getNamedOperand ( MachineInstr MI,
unsigned  OperandName 
) const
LLVM_READONLY const MachineOperand* llvm::SIInstrInfo::getNamedOperand ( const MachineInstr MI,
unsigned  OpName 
) const
inline

Definition at line 690 of file SIInstrInfo.h.

References getNamedOperand().

unsigned SIInstrInfo::getNumWaitStates ( const MachineInstr MI) const

Return the number of wait states that result from executing this instruction.

Definition at line 799 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by llvm::GCNHazardRecognizer::AdvanceCycle().

const TargetRegisterClass * SIInstrInfo::getOpRegClass ( const MachineInstr MI,
unsigned  OpNo 
) const

Return the correct register class for OpNo.

For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.

Definition at line 2191 of file SIInstrInfo.cpp.

References Desc, llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), MRI, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by canReadVGPR(), getMemOpBaseRegImmOfs(), getOpSize(), and legalizeOperands().

unsigned llvm::SIInstrInfo::getOpSize ( uint16_t  Opcode,
unsigned  OpNo 
) const
inline

Return the size in bytes of the operand OpNo on the given.

Definition at line 592 of file SIInstrInfo.h.

References assert(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.

Referenced by isInlineConstant().

unsigned llvm::SIInstrInfo::getOpSize ( const MachineInstr MI,
unsigned  OpNo 
) const
inline

This form should usually be preferred since it handles operands with unknown register classes.

Definition at line 606 of file SIInstrInfo.h.

References getOpRegClass(), and llvm::TargetRegisterClass::getSize().

const SIRegisterInfo& llvm::SIInstrInfo::getRegisterInfo ( ) const
inline
uint64_t SIInstrInfo::getScratchRsrcWords23 ( ) const
ArrayRef< std::pair< int, const char * > > SIInstrInfo::getSerializableTargetIndices ( ) const
override
unsigned SIInstrInfo::getVALUOp ( const MachineInstr MI)
static
bool SIInstrInfo::hasModifiers ( unsigned  Opcode) const

Return true if this instruction has any modifiers.

e.g. src[012]_mod, omod, clamp.

Definition at line 1790 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

bool SIInstrInfo::hasModifiersSet ( const MachineInstr MI,
unsigned  OpName 
) const

Definition at line 1798 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), and getNamedOperand().

Referenced by canShrink(), and FoldImmediate().

bool SIInstrInfo::hasVALU32BitEncoding ( unsigned  Opcode) const

Return true if this 64-bit VALU instruction has a 32-bit encoding.

This function will return false if you pass it a 32-bit instruction.

Definition at line 1782 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getVOPe32(), and llvm::AMDGPUInstrInfo::pseudoToMCOpcode().

unsigned SIInstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override
unsigned SIInstrInfo::insertIndirectBranch ( MachineBasicBlock MBB,
MachineBasicBlock NewDestBB,
const DebugLoc DL,
int64_t  BrOffset,
RegScavenger RS = nullptr 
) const
override
void SIInstrInfo::insertNoop ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI 
) const
override

Definition at line 794 of file SIInstrInfo.cpp.

References insertWaitStates().

void SIInstrInfo::insertWaitStates ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
int  Count 
) const
bool SIInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override

Definition at line 1033 of file SIInstrInfo.cpp.

References assert(), BranchOffsetBits, and llvm::isIntN().

static bool llvm::SIInstrInfo::isDisableWQM ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isDisableWQM ( uint16_t  Opcode) const
inline

Definition at line 395 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM.

static bool llvm::SIInstrInfo::isDPP ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isDPP ( uint16_t  Opcode) const
inline

Definition at line 419 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP.

static bool llvm::SIInstrInfo::isDS ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isDS ( uint16_t  Opcode) const
inline

Definition at line 347 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS.

static bool llvm::SIInstrInfo::isEXP ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isEXP ( uint16_t  Opcode) const
inline

Definition at line 379 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP.

static bool llvm::SIInstrInfo::isFixedSize ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isFixedSize ( uint16_t  Opcode) const
inline

Definition at line 453 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE.

static bool llvm::SIInstrInfo::isFLAT ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isFLAT ( uint16_t  Opcode) const
inline

Definition at line 371 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT.

static bool llvm::SIInstrInfo::isGather4 ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isGather4 ( uint16_t  Opcode) const
inline

Definition at line 363 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4.

bool SIInstrInfo::isHighLatencyInstruction ( const MachineInstr MI) const
bool SIInstrInfo::isImmOperandLegal ( const MachineInstr MI,
unsigned  OpNo,
const MachineOperand MO 
) const
bool SIInstrInfo::isInlineConstant ( const APInt Imm) const
bool SIInstrInfo::isInlineConstant ( const MachineOperand MO,
uint8_t  OperandType 
) const
bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
inline

Definition at line 491 of file SIInstrInfo.h.

References isInlineConstant(), and llvm::MCOperandInfo::OperandType.

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
const MachineOperand UseMO,
const MachineOperand DefMO 
) const
inline

returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.

Definition at line 498 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), isInlineConstant(), MI, llvm::MCInstrDesc::NumOperands, and llvm::MCInstrDesc::OpInfo.

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
unsigned  OpIdx 
) const
inline

returns true if the operand OpIdx in MI is a valid inline immediate.

Definition at line 512 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), isInlineConstant(), llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr MI,
unsigned  OpIdx,
const MachineOperand MO 
) const
inline
bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand MO) const
inline
bool SIInstrInfo::isLegalRegOperand ( const MachineRegisterInfo MRI,
const MCOperandInfo OpInfo,
const MachineOperand MO 
) const
bool SIInstrInfo::isLegalVSrcOperand ( const MachineRegisterInfo MRI,
const MCOperandInfo OpInfo,
const MachineOperand MO 
) const

Check if MO would be a valid operand for the given operand definition OpInfo.

Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).

Definition at line 2334 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTargetIndex().

bool llvm::SIInstrInfo::isLiteralConstant ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
inline
bool llvm::SIInstrInfo::isLiteralConstant ( const MachineInstr MI,
int  OpIdx 
) const
inline
bool SIInstrInfo::isLiteralConstantLike ( const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
unsigned SIInstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override
bool SIInstrInfo::isLowLatencyInstruction ( const MachineInstr MI) const

Definition at line 3480 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isSMRD().

Referenced by llvm::SIScheduleDAGMI::schedule().

static bool llvm::SIInstrInfo::isMIMG ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isMIMG ( uint16_t  Opcode) const
inline

Definition at line 355 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MIMG.

static bool llvm::SIInstrInfo::isMTBUF ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isMTBUF ( uint16_t  Opcode) const
inline

Definition at line 331 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MTBUF.

static bool llvm::SIInstrInfo::isMUBUF ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isMUBUF ( uint16_t  Opcode) const
inline

Definition at line 323 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MUBUF.

bool SIInstrInfo::isOperandLegal ( const MachineInstr MI,
unsigned  OpIdx,
const MachineOperand MO = nullptr 
) const
bool SIInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr MI,
AliasAnalysis AA 
) const
override

Definition at line 85 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

static bool llvm::SIInstrInfo::isSALU ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSALU ( uint16_t  Opcode) const
inline

Definition at line 227 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SALU.

bool SIInstrInfo::isSALUOpSupportedOnVALU ( const MachineInstr MI) const

Definition at line 2187 of file SIInstrInfo.cpp.

References getVALUOp().

static bool llvm::SIInstrInfo::isScalarStore ( const MachineInstr MI)
inlinestatic
Returns
true if this is an s_store_dword* instruction. This is more specific than than isSMEM && mayStore.

Definition at line 441 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SCALAR_STORE, and llvm::MCInstrDesc::TSFlags.

bool llvm::SIInstrInfo::isScalarStore ( uint16_t  Opcode) const
inline

Definition at line 445 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SCALAR_STORE.

static bool llvm::SIInstrInfo::isScalarUnit ( const MachineInstr MI)
inlinestatic
bool SIInstrInfo::isSchedulingBoundary ( const MachineInstr MI,
const MachineBasicBlock MBB,
const MachineFunction MF 
) const
override
static bool llvm::SIInstrInfo::isSGPRSpill ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 411 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SGPRSpill.

unsigned SIInstrInfo::isSGPRStackAccess ( const MachineInstr MI,
int &  FrameIndex 
) const
static bool llvm::SIInstrInfo::isSMRD ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSMRD ( uint16_t  Opcode) const
inline

Definition at line 339 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SMRD.

static bool llvm::SIInstrInfo::isSOP1 ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSOP1 ( uint16_t  Opcode) const
inline

Definition at line 251 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP1.

static bool llvm::SIInstrInfo::isSOP2 ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSOP2 ( uint16_t  Opcode) const
inline

Definition at line 259 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP2.

static bool llvm::SIInstrInfo::isSOPC ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSOPC ( uint16_t  Opcode) const
inline

Definition at line 267 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPC.

static bool llvm::SIInstrInfo::isSOPK ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSOPK ( uint16_t  Opcode) const
inline

Definition at line 275 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK.

static bool llvm::SIInstrInfo::isSOPP ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isSOPP ( uint16_t  Opcode) const
inline

Definition at line 283 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPP.

unsigned SIInstrInfo::isStackAccess ( const MachineInstr MI,
int &  FrameIndex 
) const
unsigned SIInstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override
static bool llvm::SIInstrInfo::isVALU ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isVALU ( uint16_t  Opcode) const
inline

Definition at line 235 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VALU.

bool llvm::SIInstrInfo::isVGPRCopy ( const MachineInstr MI) const
inline
static bool llvm::SIInstrInfo::isVGPRSpill ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isVGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 403 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VGPRSpill.

static bool llvm::SIInstrInfo::isVMEM ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isVMEM ( uint16_t  Opcode) const
inline

Definition at line 243 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

static bool llvm::SIInstrInfo::isVOP1 ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isVOP1 ( uint16_t  Opcode) const
inline

Definition at line 291 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP1.

static bool llvm::SIInstrInfo::isVOP2 ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isVOP2 ( uint16_t  Opcode) const
inline

Definition at line 299 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP2.

static bool llvm::SIInstrInfo::isVOP3 ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isVOP3 ( uint16_t  Opcode) const
inline

Definition at line 307 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP3.

static bool llvm::SIInstrInfo::isVOPC ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isVOPC ( uint16_t  Opcode) const
inline

Definition at line 315 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOPC.

static bool llvm::SIInstrInfo::isWQM ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::isWQM ( uint16_t  Opcode) const
inline

Definition at line 387 of file SIInstrInfo.h.

References llvm::SIInstrFlags::WQM.

void SIInstrInfo::legalizeGenericOperand ( MachineBasicBlock InsertMBB,
MachineBasicBlock::iterator  I,
const TargetRegisterClass DstRC,
MachineOperand Op,
MachineRegisterInfo MRI,
const DebugLoc DL 
) const
void SIInstrInfo::legalizeOperands ( MachineInstr MI) const

Legalize all operands in this instruction.

This function may create new instruction and insert them before MI.

Definition at line 2582 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), E, llvm::AMDGPU::getAddr64Inst(), llvm::Function::getCallingConv(), llvm::MachineInstr::getDebugLoc(), getDefaultRsrcDataFormat(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getMBB(), getNamedImmOperand(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::SIRegisterInfo::hasVGPRs(), I, i, isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::AMDGPU::isShader(), isSMRD(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP2(), isVOP3(), isVOPC(), legalizeGenericOperand(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), MI, MRI, Offset, readlaneVGPRToSGPR(), llvm::MachineInstr::removeFromParent(), llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMemRefs(), llvm::MachineOperand::setReg(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by moveToVALU().

void SIInstrInfo::legalizeOperandsSMRD ( MachineRegisterInfo MRI,
MachineInstr MI 
) const
void SIInstrInfo::legalizeOperandsVOP2 ( MachineRegisterInfo MRI,
MachineInstr MI 
) const
void SIInstrInfo::legalizeOperandsVOP3 ( MachineRegisterInfo MRI,
MachineInstr MI 
) const
void SIInstrInfo::legalizeOpWithMove ( MachineInstr MI,
unsigned  OpIdx 
) const
void SIInstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool SIInstrInfo::mayAccessFlatAddressSpace ( const MachineInstr MI) const
void SIInstrInfo::moveToVALU ( MachineInstr MI) const
static int llvm::SIInstrInfo::operandBitWidth ( uint8_t  OperandType)
inlinestatic
unsigned SIInstrInfo::readlaneVGPRToSGPR ( unsigned  SrcReg,
MachineInstr UseMI,
MachineRegisterInfo MRI 
) const
unsigned SIInstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override
bool SIInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 1347 of file SIInstrInfo.cpp.

References assert(), and llvm::SmallVectorTemplateCommon< T >::size().

bool SIInstrInfo::shouldClusterMemOps ( MachineInstr FirstLdSt,
MachineInstr SecondLdSt,
unsigned  NumLoads 
) const
final
static bool llvm::SIInstrInfo::sopkIsZext ( const MachineInstr MI)
inlinestatic
bool llvm::SIInstrInfo::sopkIsZext ( uint16_t  Opcode) const
inline

Definition at line 435 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK_ZEXT.

void SIInstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool SIInstrInfo::swapSourceModifiers ( MachineInstr MI,
MachineOperand Src0,
unsigned  Src0OpName,
MachineOperand Src1,
unsigned  Src1OpName 
) const
protected
bool SIInstrInfo::usesConstantBus ( const MachineRegisterInfo MRI,
const MachineOperand MO,
const MCOperandInfo OpInfo 
) const
static bool llvm::SIInstrInfo::usesVM_CNT ( const MachineInstr MI)
inlinestatic
bool SIInstrInfo::verifyInstruction ( const MachineInstr MI,
StringRef ErrInfo 
) const
override

Definition at line 1890 of file SIInstrInfo.cpp.

References compareMachineOp(), llvm::TargetRegisterClass::contains(), Desc, E, findImplicitSGPRRead(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), I, i, llvm::MachineOperand::isFI(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isInlineAsm(), isInlineConstant(), llvm::isInt< 16 >(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegTiedToUseOperand(), isSMRD(), isSOPK(), isSubRegOf(), llvm::isUInt< 16 >(), llvm::MachineOperand::isUse(), llvm::MCInstrDesc::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP1(), isVOP2(), isVOP3(), isVOPC(), LLVM_FALLTHROUGH, llvm::MachineInstr::mayStore(), llvm::InlineAsm::MIOp_FirstOperand, MRI, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOI::OPERAND_REGISTER, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, shouldReadExec(), sopkIsZext(), and usesConstantBus().


The documentation for this class was generated from the following files: