LLVM  4.0.0
Classes | Namespaces | Typedefs
MachineRegisterInfo.h File Reference
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/PointerUnion.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/LowLevelType.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <vector>
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Classes

class  llvm::MachineRegisterInfo
 MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc. More...
 
class  llvm::MachineRegisterInfo::Delegate
 
class  llvm::MachineRegisterInfo::defusechain_iterator< Uses, Defs, SkipDebug, ByOperand, ByInstr, ByBundle >
 reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register within the MachineFunction that corresponds to this MachineRegisterInfo object. More...
 
class  llvm::MachineRegisterInfo::defusechain_instr_iterator< Uses, Defs, SkipDebug, ByOperand, ByInstr, ByBundle >
 defusechain_iterator - This class provides iterator support for machine operands in the function that use or define a specific register. More...
 
class  llvm::MachineRegisterInfo::defusechain_iterator< Uses, Defs, SkipDebug, ByOperand, ByInstr, ByBundle >
 reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register within the MachineFunction that corresponds to this MachineRegisterInfo object. More...
 
class  llvm::MachineRegisterInfo::defusechain_instr_iterator< Uses, Defs, SkipDebug, ByOperand, ByInstr, ByBundle >
 defusechain_iterator - This class provides iterator support for machine operands in the function that use or define a specific register. More...
 
class  llvm::PSetIterator
 Iterate over the pressure sets affected by the given physical or virtual register. More...
 

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Typedefs

typedef PointerUnion< const
TargetRegisterClass *, const
RegisterBank * > 
llvm::RegClassOrRegBank
 Convenient type to represent either a register class or a register bank. More...