15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
423 unsigned ShuffleKind, SelectionDAG &DAG);
428 unsigned ShuffleKind, SelectionDAG &DAG);
433 unsigned ShuffleKind, SelectionDAG &DAG);
453 unsigned &InsertAtByte,
bool &Swap,
bool IsLE);
463 SDValue
get_VSPLTI_elt(SDNode *N,
unsigned ByteSize, SelectionDAG &DAG);
531 EVT VT)
const override;
582 std::vector<SDNode *> *Created)
const override;
591 unsigned Depth = 0)
const override;
600 bool IsStore,
bool IsLoad)
const override;
602 bool IsStore,
bool IsLoad)
const override;
611 unsigned CmpOpcode = 0,
612 unsigned CmpPred = 0)
const;
617 unsigned CmpOpcode = 0,
618 unsigned CmpPred = 0)
const;
631 AsmOperandInfo &
info,
const char *constraint)
const override;
633 std::pair<unsigned, const TargetRegisterClass *>
646 std::string &Constraint,
647 std::vector<SDValue> &Ops,
652 if (ConstraintCode ==
"es")
654 else if (ConstraintCode ==
"o")
656 else if (ConstraintCode ==
"Q")
658 else if (ConstraintCode ==
"Z")
660 else if (ConstraintCode ==
"Zy")
668 Type *Ty,
unsigned AS)
const override;
695 Type *Ty)
const override;
701 unsigned Intrinsic)
const override;
716 bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
724 bool *
Fast =
nullptr)
const override;
737 unsigned DefinedValues)
const override;
783 struct ReuseLoadInfo {
788 bool IsDereferenceable;
795 : IsDereferenceable(
false), IsInvariant(
false), Alignment(0),
800 if (IsDereferenceable)
808 bool canReuseLoadAddress(SDValue
Op, EVT MemVT, ReuseLoadInfo &RLI,
811 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
812 SelectionDAG &DAG)
const;
814 void LowerFP_TO_INTForReuse(SDValue
Op, ReuseLoadInfo &RLI,
815 SelectionDAG &DAG,
const SDLoc &dl)
const;
816 SDValue LowerFP_TO_INTDirectMove(SDValue
Op, SelectionDAG &DAG,
817 const SDLoc &dl)
const;
819 bool directMoveIsProfitable(
const SDValue &
Op)
const;
820 SDValue LowerINT_TO_FPDirectMove(SDValue
Op, SelectionDAG &DAG,
821 const SDLoc &dl)
const;
823 SDValue getFramePointerFrameIndex(SelectionDAG & DAG)
const;
824 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG)
const;
827 IsEligibleForTailCallOptimization(SDValue Callee,
830 const SmallVectorImpl<ISD::InputArg> &
Ins,
831 SelectionDAG& DAG)
const;
834 IsEligibleForTailCallOptimization_64SVR4(
837 ImmutableCallSite *CS,
839 const SmallVectorImpl<ISD::OutputArg> &Outs,
840 const SmallVectorImpl<ISD::InputArg> &
Ins,
841 SelectionDAG& DAG)
const;
843 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG,
int SPDiff,
844 SDValue Chain, SDValue &LROpOut,
846 const SDLoc &dl)
const;
848 SDValue LowerRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
849 SDValue LowerFRAMEADDR(SDValue
Op, SelectionDAG &DAG)
const;
850 SDValue LowerConstantPool(SDValue
Op, SelectionDAG &DAG)
const;
851 SDValue LowerBlockAddress(SDValue
Op, SelectionDAG &DAG)
const;
852 SDValue LowerGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
853 SDValue LowerGlobalAddress(SDValue
Op, SelectionDAG &DAG)
const;
854 SDValue LowerJumpTable(SDValue
Op, SelectionDAG &DAG)
const;
855 SDValue LowerSETCC(SDValue
Op, SelectionDAG &DAG)
const;
856 SDValue LowerINIT_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
857 SDValue LowerADJUST_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
858 SDValue LowerVASTART(SDValue
Op, SelectionDAG &DAG)
const;
859 SDValue LowerVAARG(SDValue
Op, SelectionDAG &DAG)
const;
860 SDValue LowerVACOPY(SDValue
Op, SelectionDAG &DAG)
const;
861 SDValue LowerSTACKRESTORE(SDValue
Op, SelectionDAG &DAG)
const;
862 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue
Op, SelectionDAG &DAG)
const;
863 SDValue LowerDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
864 SDValue LowerEH_DWARF_CFA(SDValue
Op, SelectionDAG &DAG)
const;
865 SDValue LowerLOAD(SDValue
Op, SelectionDAG &DAG)
const;
866 SDValue LowerSTORE(SDValue
Op, SelectionDAG &DAG)
const;
867 SDValue LowerTRUNCATE(SDValue
Op, SelectionDAG &DAG)
const;
868 SDValue LowerSELECT_CC(SDValue
Op, SelectionDAG &DAG)
const;
869 SDValue LowerFP_TO_INT(SDValue
Op, SelectionDAG &DAG,
870 const SDLoc &dl)
const;
871 SDValue LowerINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
872 SDValue LowerFLT_ROUNDS_(SDValue
Op, SelectionDAG &DAG)
const;
873 SDValue LowerSHL_PARTS(SDValue
Op, SelectionDAG &DAG)
const;
874 SDValue LowerSRL_PARTS(SDValue
Op, SelectionDAG &DAG)
const;
875 SDValue LowerSRA_PARTS(SDValue
Op, SelectionDAG &DAG)
const;
876 SDValue LowerBUILD_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
877 SDValue LowerVECTOR_SHUFFLE(SDValue
Op, SelectionDAG &DAG)
const;
878 SDValue LowerINSERT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
879 SDValue LowerEXTRACT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
880 SDValue LowerINTRINSIC_WO_CHAIN(SDValue
Op, SelectionDAG &DAG)
const;
881 SDValue LowerSCALAR_TO_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
882 SDValue LowerSIGN_EXTEND_INREG(SDValue
Op, SelectionDAG &DAG)
const;
883 SDValue LowerMUL(SDValue
Op, SelectionDAG &DAG)
const;
885 SDValue LowerVectorLoad(SDValue
Op, SelectionDAG &DAG)
const;
886 SDValue LowerVectorStore(SDValue
Op, SelectionDAG &DAG)
const;
888 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
890 const SmallVectorImpl<ISD::InputArg> &
Ins,
891 const SDLoc &dl, SelectionDAG &DAG,
892 SmallVectorImpl<SDValue> &InVals)
const;
894 bool isTailCall,
bool isVarArg,
bool isPatchPoint,
895 bool hasNest, SelectionDAG &DAG,
896 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
897 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
898 SDValue &Callee,
int SPDiff,
unsigned NumBytes,
899 const SmallVectorImpl<ISD::InputArg> &
Ins,
900 SmallVectorImpl<SDValue> &InVals,
901 ImmutableCallSite *CS)
const;
904 LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
905 const SmallVectorImpl<ISD::InputArg> &
Ins,
906 const SDLoc &dl, SelectionDAG &DAG,
907 SmallVectorImpl<SDValue> &InVals)
const override;
910 LowerCall(TargetLowering::CallLoweringInfo &CLI,
911 SmallVectorImpl<SDValue> &InVals)
const override;
916 const SmallVectorImpl<ISD::OutputArg> &Outs,
917 LLVMContext &
Context)
const override;
919 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
920 const SmallVectorImpl<ISD::OutputArg> &Outs,
921 const SmallVectorImpl<SDValue> &OutVals,
922 const SDLoc &dl, SelectionDAG &DAG)
const override;
924 SDValue extendArgForPPC64(ISD::ArgFlagsTy
Flags, EVT ObjectVT,
925 SelectionDAG &DAG, SDValue ArgVal,
926 const SDLoc &dl)
const;
928 SDValue LowerFormalArguments_Darwin(
930 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
931 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const;
932 SDValue LowerFormalArguments_64SVR4(
934 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
935 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const;
936 SDValue LowerFormalArguments_32SVR4(
938 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl,
939 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals)
const;
941 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
942 SDValue CallSeqStart,
943 ISD::ArgFlagsTy
Flags, SelectionDAG &DAG,
944 const SDLoc &dl)
const;
946 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
948 bool isTailCall,
bool isPatchPoint,
949 const SmallVectorImpl<ISD::OutputArg> &Outs,
950 const SmallVectorImpl<SDValue> &OutVals,
951 const SmallVectorImpl<ISD::InputArg> &
Ins,
952 const SDLoc &dl, SelectionDAG &DAG,
953 SmallVectorImpl<SDValue> &InVals,
954 ImmutableCallSite *CS)
const;
955 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
957 bool isTailCall,
bool isPatchPoint,
958 const SmallVectorImpl<ISD::OutputArg> &Outs,
959 const SmallVectorImpl<SDValue> &OutVals,
960 const SmallVectorImpl<ISD::InputArg> &
Ins,
961 const SDLoc &dl, SelectionDAG &DAG,
962 SmallVectorImpl<SDValue> &InVals,
963 ImmutableCallSite *CS)
const;
964 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
966 bool isTailCall,
bool isPatchPoint,
967 const SmallVectorImpl<ISD::OutputArg> &Outs,
968 const SmallVectorImpl<SDValue> &OutVals,
969 const SmallVectorImpl<ISD::InputArg> &
Ins,
970 const SDLoc &dl, SelectionDAG &DAG,
971 SmallVectorImpl<SDValue> &InVals,
972 ImmutableCallSite *CS)
const;
974 SDValue lowerEH_SJLJ_SETJMP(SDValue
Op, SelectionDAG &DAG)
const;
975 SDValue lowerEH_SJLJ_LONGJMP(SDValue
Op, SelectionDAG &DAG)
const;
977 SDValue DAGCombineExtBoolTrunc(SDNode *
N, DAGCombinerInfo &DCI)
const;
978 SDValue DAGCombineBuildVector(SDNode *
N, DAGCombinerInfo &DCI)
const;
979 SDValue DAGCombineTruncBoolExt(SDNode *
N, DAGCombinerInfo &DCI)
const;
980 SDValue combineFPToIntToFP(SDNode *
N, DAGCombinerInfo &DCI)
const;
985 SDValue ConvertSETCCToSubtract(SDNode *
N, DAGCombinerInfo &DCI)
const;
987 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
988 int &RefinementSteps,
bool &UseOneConstNR,
989 bool Reciprocal)
const override;
990 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
991 int &RefinementSteps)
const override;
992 unsigned combineRepeatedFPDivisors()
const override;
997 combineElementTruncationToVectorTruncation(SDNode *
N,
998 DAGCombinerInfo &DCI)
const;
1003 const TargetLibraryInfo *LibInfo);
1008 ISD::ArgFlagsTy &ArgFlags,
1014 ISD::ArgFlagsTy &ArgFlags,
1021 ISD::ArgFlagsTy &ArgFlags,
1027 ISD::ArgFlagsTy &ArgFlags,
1031 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Return with a flag operand, matched by 'blr'.
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
QVFPERM = This corresponds to the QPX qvfperm instruction.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
GPRC = address of GLOBAL_OFFSET_TABLE.
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
A Module instance is used to store all the information related to an LLVM module. ...
bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
This class represents a function call, abstracting a target machine's calling convention.
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
QBRC, CHAIN = QVLFSb CHAIN, Ptr The 4xf32 load used for v4i1 constants.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) !=...
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
CALL - A direct function call.
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align=1, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation...
bool isFPExtFree(EVT VT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
struct fuzzer::@269 Flags
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
The memory access is dereferenceable (i.e., doesn't trap).
Direct move from a GPR to a VSX register (algebraic)
X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
QVALIGNI = This corresponds to the QPX qvaligni instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
AtomicOrdering
Atomic ordering for LLVM's memory model.
unsigned getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Context object for machine code objects.
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
G8RC = ADDIS_TLSGD_HA X2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
Function Alias Analysis false
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a res...
bool isArrayTy() const
True if this is an instance of ArrayType.
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
XXINSERT - The PPC VSX insert instruction.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
unsigned getScalarSizeInBits() const
Instruction * emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
FSEL - Traditional three-operand fsel node.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
This is an important base class in LLVM.
G8RC = ADDIS_DTPREL_HA X3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
Direct move from a VSX register to a GPR.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask...
STFIWX - The STFIWX instruction.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target...
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
G8RC = ADDIS_TLSLD_HA X2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
QVESPLATI = This corresponds to the QPX qvesplati instruction.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Common code between 32-bit and 64-bit PowerPC targets.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
EVT - Extended Value Type.
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class contains a discriminated union of information about pointers in memory operands...
Instruction * emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
Extract a subvector from unsigned integer vector and convert to FP.
QBFLT = Access the underlying QPX floating-point boolean representation.
X3 = GET_TLSLD_ADDR X3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators...
bool isJumpTableRelative() const override
XXSPLT - The PPC VSX splat instructions.
bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
VECSHL - The PPC VSX shift left instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
Provides information about what library functions are available for the current target.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
CHAIN = SC CHAIN, Imm128 - System call.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node. ...
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
X3 = GET_TLS_ADDR X3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
VPERM - The PPC VPERM Instruction.
STXSIX - The STXSI[bh]X instruction.
i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after execu...
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
G8RC = ADDIS_GOT_TPREL_HA X2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
Class for arbitrary precision integers.
QVGPCI = This corresponds to the QPX qvgpci instruction.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
AddrMode
ARM Addressing Modes.
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be represented as an inde...
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2...
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
Flags
Flags values. These may be or'd together.
GPRC = address of GLOBAL_OFFSET_TABLE.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Representation of each machine instruction.
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry...
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Reciprocal estimate instructions (unary FP ops).
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
Direct move from a GPR to a VSX register (zero)
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
The CMPB instruction (takes two operands of i32 or i64).
The memory access always returns the same value (or traps).
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction. ...
TC_RETURN - A tail call return.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, bool Aligned) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2...
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
These nodes represent the 32-bit PPC shifts that operate on 6-bit shift amounts.
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
Extract a subvector from signed integer vector and convert to FP.
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the altivec VCMP*o instructions.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
int isQVALIGNIShuffleMask(SDNode *N)
If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. ...
bool useSoftFloat() const override