LLVM  4.0.0
MipsInstrInfo.cpp
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1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsInstrInfo.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
23 
24 using namespace llvm;
25 
26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "MipsGenInstrInfo.inc"
28 
29 // Pin the vtable to this file.
30 void MipsInstrInfo::anchor() {}
31 
32 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
33  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
34  Subtarget(STI), UncondBrOpc(UncondBr) {}
35 
37  if (STI.inMips16Mode())
38  return llvm::createMips16InstrInfo(STI);
39 
40  return llvm::createMipsSEInstrInfo(STI);
41 }
42 
44  return op.isImm() && op.getImm() == 0;
45 }
46 
47 /// insertNoop - If data hazard condition is found insert the target nop
48 /// instruction.
49 // FIXME: This appears to be dead code.
50 void MipsInstrInfo::
52 {
53  DebugLoc DL;
54  BuildMI(MBB, MI, DL, get(Mips::NOP));
55 }
56 
60  MachineFunction &MF = *MBB.getParent();
61  MachineFrameInfo &MFI = MF.getFrameInfo();
62  unsigned Align = MFI.getObjectAlignment(FI);
63 
65  Flags, MFI.getObjectSize(FI), Align);
66 }
67 
68 //===----------------------------------------------------------------------===//
69 // Branch Analysis
70 //===----------------------------------------------------------------------===//
71 
72 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
73  MachineBasicBlock *&BB,
74  SmallVectorImpl<MachineOperand> &Cond) const {
75  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
76  int NumOp = Inst->getNumExplicitOperands();
77 
78  // for both int and fp branches, the last explicit operand is the
79  // MBB.
80  BB = Inst->getOperand(NumOp-1).getMBB();
82 
83  for (int i=0; i<NumOp-1; i++)
84  Cond.push_back(Inst->getOperand(i));
85 }
86 
88  MachineBasicBlock *&TBB,
89  MachineBasicBlock *&FBB,
91  bool AllowModify) const {
92  SmallVector<MachineInstr*, 2> BranchInstrs;
93  BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
94 
95  return (BT == BT_None) || (BT == BT_Indirect);
96 }
97 
98 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
99  const DebugLoc &DL,
100  ArrayRef<MachineOperand> Cond) const {
101  unsigned Opc = Cond[0].getImm();
102  const MCInstrDesc &MCID = get(Opc);
103  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
104 
105  for (unsigned i = 1; i < Cond.size(); ++i) {
106  if (Cond[i].isReg())
107  MIB.addReg(Cond[i].getReg());
108  else if (Cond[i].isImm())
109  MIB.addImm(Cond[i].getImm());
110  else
111  assert(false && "Cannot copy operand");
112  }
113  MIB.addMBB(TBB);
114 }
115 
117  MachineBasicBlock *TBB,
118  MachineBasicBlock *FBB,
120  const DebugLoc &DL,
121  int *BytesAdded) const {
122  // Shouldn't be a fall through.
123  assert(TBB && "insertBranch must not be told to insert a fallthrough");
124  assert(!BytesAdded && "code size not handled");
125 
126  // # of condition operands:
127  // Unconditional branches: 0
128  // Floating point branches: 1 (opc)
129  // Int BranchZero: 2 (opc, reg)
130  // Int Branch: 3 (opc, reg0, reg1)
131  assert((Cond.size() <= 3) &&
132  "# of Mips branch conditions must be <= 3!");
133 
134  // Two-way Conditional branch.
135  if (FBB) {
136  BuildCondBr(MBB, TBB, DL, Cond);
137  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
138  return 2;
139  }
140 
141  // One way branch.
142  // Unconditional branch.
143  if (Cond.empty())
144  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
145  else // Conditional branch.
146  BuildCondBr(MBB, TBB, DL, Cond);
147  return 1;
148 }
149 
151  int *BytesRemoved) const {
152  assert(!BytesRemoved && "code size not handled");
153 
154  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
155  unsigned removed;
156 
157  // Skip all the debug instructions.
158  while (I != REnd && I->isDebugValue())
159  ++I;
160 
161  if (I == REnd)
162  return 0;
163 
164  MachineBasicBlock::iterator FirstBr = ++I.getReverse();
165 
166  // Up to 2 branches are removed.
167  // Note that indirect branches are not removed.
168  for (removed = 0; I != REnd && removed < 2; ++I, ++removed)
169  if (!getAnalyzableBrOpc(I->getOpcode()))
170  break;
171 
172  MBB.erase((--I).getReverse(), FirstBr);
173 
174  return removed;
175 }
176 
177 /// reverseBranchCondition - Return the inverse opcode of the
178 /// specified Branch instruction.
180  SmallVectorImpl<MachineOperand> &Cond) const {
181  assert( (Cond.size() && Cond.size() <= 3) &&
182  "Invalid Mips branch condition!");
183  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
184  return false;
185 }
186 
189  SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
190  SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
191 
192  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
193 
194  // Skip all the debug instructions.
195  while (I != REnd && I->isDebugValue())
196  ++I;
197 
198  if (I == REnd || !isUnpredicatedTerminator(*I)) {
199  // This block ends with no branches (it just falls through to its succ).
200  // Leave TBB/FBB null.
201  TBB = FBB = nullptr;
202  return BT_NoBranch;
203  }
204 
205  MachineInstr *LastInst = &*I;
206  unsigned LastOpc = LastInst->getOpcode();
207  BranchInstrs.push_back(LastInst);
208 
209  // Not an analyzable branch (e.g., indirect jump).
210  if (!getAnalyzableBrOpc(LastOpc))
211  return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
212 
213  // Get the second to last instruction in the block.
214  unsigned SecondLastOpc = 0;
215  MachineInstr *SecondLastInst = nullptr;
216 
217  if (++I != REnd) {
218  SecondLastInst = &*I;
219  SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
220 
221  // Not an analyzable branch (must be an indirect jump).
222  if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
223  return BT_None;
224  }
225 
226  // If there is only one terminator instruction, process it.
227  if (!SecondLastOpc) {
228  // Unconditional branch.
229  if (LastInst->isUnconditionalBranch()) {
230  TBB = LastInst->getOperand(0).getMBB();
231  return BT_Uncond;
232  }
233 
234  // Conditional branch
235  AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
236  return BT_Cond;
237  }
238 
239  // If we reached here, there are two branches.
240  // If there are three terminators, we don't know what sort of block this is.
241  if (++I != REnd && isUnpredicatedTerminator(*I))
242  return BT_None;
243 
244  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
245 
246  // If second to last instruction is an unconditional branch,
247  // analyze it and remove the last instruction.
248  if (SecondLastInst->isUnconditionalBranch()) {
249  // Return if the last instruction cannot be removed.
250  if (!AllowModify)
251  return BT_None;
252 
253  TBB = SecondLastInst->getOperand(0).getMBB();
254  LastInst->eraseFromParent();
255  BranchInstrs.pop_back();
256  return BT_Uncond;
257  }
258 
259  // Conditional branch followed by an unconditional branch.
260  // The last one must be unconditional.
261  if (!LastInst->isUnconditionalBranch())
262  return BT_None;
263 
264  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
265  FBB = LastInst->getOperand(0).getMBB();
266 
267  return BT_CondUncond;
268 }
269 
270 /// Return the corresponding compact (no delay slot) form of a branch.
272  const MachineBasicBlock::iterator I) const {
273  unsigned Opcode = I->getOpcode();
274  bool canUseShortMicroMipsCTI = false;
275 
276  if (Subtarget.inMicroMipsMode()) {
277  switch (Opcode) {
278  case Mips::BNE:
279  case Mips::BNE_MM:
280  case Mips::BEQ:
281  case Mips::BEQ_MM:
282  // microMIPS has NE,EQ branches that do not have delay slots provided one
283  // of the operands is zero.
284  if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
285  canUseShortMicroMipsCTI = true;
286  break;
287  // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
288  // expanded to JR_MM, so they can be replaced with JRC16_MM.
289  case Mips::JR:
290  case Mips::PseudoReturn:
291  case Mips::PseudoIndirectBranch:
292  case Mips::TAILCALLREG:
293  canUseShortMicroMipsCTI = true;
294  break;
295  }
296  }
297 
298  // MIPSR6 forbids both operands being the zero register.
299  if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
300  (I->getOperand(0).isReg() &&
301  (I->getOperand(0).getReg() == Mips::ZERO ||
302  I->getOperand(0).getReg() == Mips::ZERO_64)) &&
303  (I->getOperand(1).isReg() &&
304  (I->getOperand(1).getReg() == Mips::ZERO ||
305  I->getOperand(1).getReg() == Mips::ZERO_64)))
306  return 0;
307 
308  if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
309  switch (Opcode) {
310  case Mips::B:
311  return Mips::BC;
312  case Mips::BAL:
313  return Mips::BALC;
314  case Mips::BEQ:
315  case Mips::BEQ_MM:
316  if (canUseShortMicroMipsCTI)
317  return Mips::BEQZC_MM;
318  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
319  return 0;
320  return Mips::BEQC;
321  case Mips::BNE:
322  case Mips::BNE_MM:
323  if (canUseShortMicroMipsCTI)
324  return Mips::BNEZC_MM;
325  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
326  return 0;
327  return Mips::BNEC;
328  case Mips::BGE:
329  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
330  return 0;
331  return Mips::BGEC;
332  case Mips::BGEU:
333  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
334  return 0;
335  return Mips::BGEUC;
336  case Mips::BGEZ:
337  return Mips::BGEZC;
338  case Mips::BGTZ:
339  return Mips::BGTZC;
340  case Mips::BLEZ:
341  return Mips::BLEZC;
342  case Mips::BLT:
343  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
344  return 0;
345  return Mips::BLTC;
346  case Mips::BLTU:
347  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
348  return 0;
349  return Mips::BLTUC;
350  case Mips::BLTZ:
351  return Mips::BLTZC;
352  case Mips::BEQ64:
353  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
354  return 0;
355  return Mips::BEQC64;
356  case Mips::BNE64:
357  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
358  return 0;
359  return Mips::BNEC64;
360  case Mips::BGTZ64:
361  return Mips::BGTZC64;
362  case Mips::BGEZ64:
363  return Mips::BGEZC64;
364  case Mips::BLTZ64:
365  return Mips::BLTZC64;
366  case Mips::BLEZ64:
367  return Mips::BLEZC64;
368  // For MIPSR6, the instruction 'jic' can be used for these cases. Some
369  // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
370  case Mips::JR:
371  case Mips::PseudoReturn:
372  case Mips::PseudoIndirectBranch:
373  case Mips::TAILCALLREG:
374  if (canUseShortMicroMipsCTI)
375  return Mips::JRC16_MM;
376  return Mips::JIC;
377  case Mips::JALRPseudo:
378  return Mips::JIALC;
379  case Mips::JR64:
380  case Mips::PseudoReturn64:
381  case Mips::PseudoIndirectBranch64:
382  case Mips::TAILCALLREG64:
383  return Mips::JIC64;
384  case Mips::JALR64Pseudo:
385  return Mips::JIALC64;
386  default:
387  return 0;
388  }
389  }
390 
391  return 0;
392 }
393 
394 /// Predicate for distingushing between control transfer instructions and all
395 /// other instructions for handling forbidden slots. Consider inline assembly
396 /// as unsafe as well.
398  if (MI.isInlineAsm())
399  return false;
400 
401  return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
402 
403 }
404 
405 /// Predicate for distingushing instructions that have forbidden slots.
407  return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
408 }
409 
410 /// Return the number of bytes of code the specified instruction may be.
412  switch (MI.getOpcode()) {
413  default:
414  return MI.getDesc().getSize();
415  case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
416  const MachineFunction *MF = MI.getParent()->getParent();
417  const char *AsmStr = MI.getOperand(0).getSymbolName();
418  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
419  }
420  case Mips::CONSTPOOL_ENTRY:
421  // If this machine instr is a constant pool entry, its size is recorded as
422  // operand #2.
423  return MI.getOperand(2).getImm();
424  }
425 }
426 
431 
432  // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
433  // Pick the zero form of the branch for readable assembly and for greater
434  // branch distance in non-microMIPS mode.
435  // Additional MIPSR6 does not permit the use of register $zero for compact
436  // branches.
437  // FIXME: Certain atomic sequences on mips64 generate 32bit references to
438  // Mips::ZERO, which is incorrect. This test should be updated to use
439  // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
440  // are fixed.
441  int ZeroOperandPosition = -1;
442  bool BranchWithZeroOperand = false;
443  if (I->isBranch() && !I->isPseudo()) {
444  auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
445  ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
446  BranchWithZeroOperand = ZeroOperandPosition != -1;
447  }
448 
449  if (BranchWithZeroOperand) {
450  switch (NewOpc) {
451  case Mips::BEQC:
452  NewOpc = Mips::BEQZC;
453  break;
454  case Mips::BNEC:
455  NewOpc = Mips::BNEZC;
456  break;
457  case Mips::BGEC:
458  NewOpc = Mips::BGEZC;
459  break;
460  case Mips::BLTC:
461  NewOpc = Mips::BLTZC;
462  break;
463  case Mips::BEQC64:
464  NewOpc = Mips::BEQZC64;
465  break;
466  case Mips::BNEC64:
467  NewOpc = Mips::BNEZC64;
468  break;
469  }
470  }
471 
472  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
473 
474  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
475  // immediate 0 as an operand and requires the removal of it's %RA<imp-def>
476  // implicit operand as copying the implicit operations of the instructio we're
477  // looking at will give us the correct flags.
478  if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
479  NewOpc == Mips::JIALC64) {
480 
481  if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
482  MIB->RemoveOperand(0);
483 
484  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
485  MIB.addOperand(I->getOperand(J));
486  }
487 
488  MIB.addImm(0);
489 
490  } else {
491  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
492  if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
493  continue;
494 
495  MIB.addOperand(I->getOperand(J));
496  }
497  }
498 
499  MIB.copyImplicitOps(*I);
500 
501  MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
502  return MIB;
503 }
static bool isReg(const MCInst &MI, unsigned OpNo)
bool isZeroImm(const MachineOperand &op) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const MipsABIInfo & getABI() const
size_t i
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
MachineBasicBlock * getMBB() const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
const char * getSymbolName() const
A debug info location.
Definition: DebugLoc.h:34
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
#define op(i)
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
struct fuzzer::@269 Flags
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:35
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
MachineBasicBlock * MBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
int64_t getImm() const
reverse_iterator rend()
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
HasForbiddenSlot - Instruction has a forbidden slot.
Definition: MipsBaseInfo.h:123
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:560
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:454
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:136
bool inMicroMipsMode() const
bool inMips16Mode() const
bool hasMips32r6() const
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isInlineAsm() const
Definition: MachineInstr.h:789
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:464
Flags
Flags values. These may be or'd together.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned GetZeroReg() const
Definition: MipsABIInfo.cpp:85
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IsCTI - Instruction is a Control Transfer Instruction.
Definition: MipsBaseInfo.h:121
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
IRTranslator LLVM IR MI
static const MipsInstrInfo * create(MipsSubtarget &STI)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:470