LLVM  4.0.0
InstructionSelector.h
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1 //==-- llvm/CodeGen/GlobalISel/InstructionSelector.h -------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file declares the API for the instruction selector.
11 /// This class is responsible for selecting machine instructions.
12 /// It's implemented by the target. It's used by the InstructionSelect pass.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
17 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
18 
19 namespace llvm {
20 class MachineInstr;
21 class RegisterBankInfo;
22 class TargetInstrInfo;
23 class TargetRegisterInfo;
24 
25 /// Provides the logic to select generic machine instructions.
27 public:
28  virtual ~InstructionSelector() {}
29 
30  /// Select the (possibly generic) instruction \p I to only use target-specific
31  /// opcodes. It is OK to insert multiple instructions, but they cannot be
32  /// generic pre-isel instructions.
33  ///
34  /// \returns whether selection succeeded.
35  /// \pre I.getParent() && I.getParent()->getParent()
36  /// \post
37  /// if returns true:
38  /// for I in all mutated/inserted instructions:
39  /// !isPreISelGenericOpcode(I.getOpcode())
40  ///
41  virtual bool select(MachineInstr &I) const = 0;
42 
43 protected:
45 
46  /// Mutate the newly-selected instruction \p I to constrain its (possibly
47  /// generic) virtual register operands to the instruction's register class.
48  /// This could involve inserting COPYs before (for uses) or after (for defs).
49  /// This requires the number of operands to match the instruction description.
50  /// \returns whether operand regclass constraining succeeded.
51  ///
52  // FIXME: Not all instructions have the same number of operands. We should
53  // probably expose a constrain helper per operand and let the target selector
54  // constrain individual registers, like fast-isel.
56  const TargetInstrInfo &TII,
57  const TargetRegisterInfo &TRI,
58  const RegisterBankInfo &RBI) const;
59 };
60 
61 } // End namespace llvm.
62 
63 #endif
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Holds all the information related to register banks.
const HexagonInstrInfo * TII
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool select(MachineInstr &I) const =0
Select the (possibly generic) instruction I to only use target-specific opcodes.
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accomodate up to NumRegBanks RegisterBank instances.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:52
#define I(x, y, z)
Definition: MD5.cpp:54