LLVM  4.0.0
InstrEmitter.cpp
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1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
12 // selection.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/StackMaps.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/Support/Debug.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "instr-emitter"
35 
36 /// MinRCSize - Smallest register class we allow when constraining virtual
37 /// registers. If satisfying all register class constraints would require
38 /// using a smaller register class, emit a COPY to a new virtual register
39 /// instead.
40 const unsigned MinRCSize = 4;
41 
42 /// CountResults - The results of target nodes have register or immediate
43 /// operands first, then an optional chain, and optional glue operands (which do
44 /// not go into the resulting MachineInstr).
46  unsigned N = Node->getNumValues();
47  while (N && Node->getValueType(N - 1) == MVT::Glue)
48  --N;
49  if (N && Node->getValueType(N - 1) == MVT::Other)
50  --N; // Skip over chain result.
51  return N;
52 }
53 
54 /// countOperands - The inputs to target nodes have any actual inputs first,
55 /// followed by an optional chain operand, then an optional glue operand.
56 /// Compute the number of actual operands that will go into the resulting
57 /// MachineInstr.
58 ///
59 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
60 /// the chain and glue. These operands may be implicit on the machine instr.
61 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
62  unsigned &NumImpUses) {
63  unsigned N = Node->getNumOperands();
64  while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
65  --N;
66  if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
67  --N; // Ignore chain if it exists.
68 
69  // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
70  NumImpUses = N - NumExpUses;
71  for (unsigned I = N; I > NumExpUses; --I) {
72  if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
73  continue;
74  if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
76  continue;
77  NumImpUses = N - I;
78  break;
79  }
80 
81  return N;
82 }
83 
84 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
85 /// implicit physical register output.
86 void InstrEmitter::
87 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
88  unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89  unsigned VRBase = 0;
91  // Just use the input register directly!
92  SDValue Op(Node, ResNo);
93  if (IsClone)
94  VRBaseMap.erase(Op);
95  bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
96  (void)isNew; // Silence compiler warning.
97  assert(isNew && "Node emitted out of order - early");
98  return;
99  }
100 
101  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
102  // the CopyToReg'd destination register instead of creating a new vreg.
103  bool MatchReg = true;
104  const TargetRegisterClass *UseRC = nullptr;
105  MVT VT = Node->getSimpleValueType(ResNo);
106 
107  // Stick to the preferred register classes for legal types.
108  if (TLI->isTypeLegal(VT))
109  UseRC = TLI->getRegClassFor(VT);
110 
111  if (!IsClone && !IsCloned)
112  for (SDNode *User : Node->uses()) {
113  bool Match = true;
114  if (User->getOpcode() == ISD::CopyToReg &&
115  User->getOperand(2).getNode() == Node &&
116  User->getOperand(2).getResNo() == ResNo) {
117  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119  VRBase = DestReg;
120  Match = false;
121  } else if (DestReg != SrcReg)
122  Match = false;
123  } else {
124  for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
125  SDValue Op = User->getOperand(i);
126  if (Op.getNode() != Node || Op.getResNo() != ResNo)
127  continue;
128  MVT VT = Node->getSimpleValueType(Op.getResNo());
129  if (VT == MVT::Other || VT == MVT::Glue)
130  continue;
131  Match = false;
132  if (User->isMachineOpcode()) {
133  const MCInstrDesc &II = TII->get(User->getMachineOpcode());
134  const TargetRegisterClass *RC = nullptr;
135  if (i+II.getNumDefs() < II.getNumOperands()) {
136  RC = TRI->getAllocatableClass(
137  TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
138  }
139  if (!UseRC)
140  UseRC = RC;
141  else if (RC) {
142  const TargetRegisterClass *ComRC =
143  TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
144  // If multiple uses expect disjoint register classes, we emit
145  // copies in AddRegisterOperand.
146  if (ComRC)
147  UseRC = ComRC;
148  }
149  }
150  }
151  }
152  MatchReg &= Match;
153  if (VRBase)
154  break;
155  }
156 
157  const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
158  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
159 
160  // Figure out the register class to create for the destreg.
161  if (VRBase) {
162  DstRC = MRI->getRegClass(VRBase);
163  } else if (UseRC) {
164  assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
165  DstRC = UseRC;
166  } else {
167  DstRC = TLI->getRegClassFor(VT);
168  }
169 
170  // If all uses are reading from the src physical register and copying the
171  // register is either impossible or very expensive, then don't create a copy.
172  if (MatchReg && SrcRC->getCopyCost() < 0) {
173  VRBase = SrcReg;
174  } else {
175  // Create the reg, emit the copy.
176  VRBase = MRI->createVirtualRegister(DstRC);
177  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178  VRBase).addReg(SrcReg);
179  }
180 
181  SDValue Op(Node, ResNo);
182  if (IsClone)
183  VRBaseMap.erase(Op);
184  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185  (void)isNew; // Silence compiler warning.
186  assert(isNew && "Node emitted out of order - early");
187 }
188 
189 /// getDstOfCopyToRegUse - If the only use of the specified result number of
190 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
191 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
192  unsigned ResNo) const {
193  if (!Node->hasOneUse())
194  return 0;
195 
196  SDNode *User = *Node->use_begin();
197  if (User->getOpcode() == ISD::CopyToReg &&
198  User->getOperand(2).getNode() == Node &&
199  User->getOperand(2).getResNo() == ResNo) {
200  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
202  return Reg;
203  }
204  return 0;
205 }
206 
207 void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
208  MachineInstrBuilder &MIB,
209  const MCInstrDesc &II,
210  bool IsClone, bool IsCloned,
211  DenseMap<SDValue, unsigned> &VRBaseMap) {
212  assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
213  "IMPLICIT_DEF should have been handled as a special case elsewhere!");
214 
215  unsigned NumResults = CountResults(Node);
216  for (unsigned i = 0; i < II.getNumDefs(); ++i) {
217  // If the specific node value is only used by a CopyToReg and the dest reg
218  // is a vreg in the same register class, use the CopyToReg'd destination
219  // register instead of creating a new vreg.
220  unsigned VRBase = 0;
221  const TargetRegisterClass *RC =
222  TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
223  // Always let the value type influence the used register class. The
224  // constraints on the instruction may be too lax to represent the value
225  // type correctly. For example, a 64-bit float (X86::FR64) can't live in
226  // the 32-bit float super-class (X86::FR32).
227  if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
228  const TargetRegisterClass *VTRC =
229  TLI->getRegClassFor(Node->getSimpleValueType(i));
230  if (RC)
231  VTRC = TRI->getCommonSubClass(RC, VTRC);
232  if (VTRC)
233  RC = VTRC;
234  }
235 
236  if (II.OpInfo[i].isOptionalDef()) {
237  // Optional def must be a physical register.
238  unsigned NumResults = CountResults(Node);
239  VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
241  MIB.addReg(VRBase, RegState::Define);
242  }
243 
244  if (!VRBase && !IsClone && !IsCloned)
245  for (SDNode *User : Node->uses()) {
246  if (User->getOpcode() == ISD::CopyToReg &&
247  User->getOperand(2).getNode() == Node &&
248  User->getOperand(2).getResNo() == i) {
249  unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
251  const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
252  if (RegRC == RC) {
253  VRBase = Reg;
254  MIB.addReg(VRBase, RegState::Define);
255  break;
256  }
257  }
258  }
259  }
260 
261  // Create the result registers for this node and add the result regs to
262  // the machine instruction.
263  if (VRBase == 0) {
264  assert(RC && "Isn't a register operand!");
265  VRBase = MRI->createVirtualRegister(RC);
266  MIB.addReg(VRBase, RegState::Define);
267  }
268 
269  // If this def corresponds to a result of the SDNode insert the VRBase into
270  // the lookup map.
271  if (i < NumResults) {
272  SDValue Op(Node, i);
273  if (IsClone)
274  VRBaseMap.erase(Op);
275  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
276  (void)isNew; // Silence compiler warning.
277  assert(isNew && "Node emitted out of order - early");
278  }
279  }
280 }
281 
282 /// getVR - Return the virtual register corresponding to the specified result
283 /// of the specified node.
284 unsigned InstrEmitter::getVR(SDValue Op,
285  DenseMap<SDValue, unsigned> &VRBaseMap) {
286  if (Op.isMachineOpcode() &&
287  Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
288  // Add an IMPLICIT_DEF instruction before every use.
289  unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
290  // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
291  // does not include operand register class info.
292  if (!VReg) {
293  const TargetRegisterClass *RC =
295  VReg = MRI->createVirtualRegister(RC);
296  }
297  BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
298  TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
299  return VReg;
300  }
301 
303  assert(I != VRBaseMap.end() && "Node emitted out of order - late");
304  return I->second;
305 }
306 
307 
308 /// AddRegisterOperand - Add the specified register as an operand to the
309 /// specified machine instr. Insert register copies if the register is
310 /// not in the required register class.
311 void
312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
313  SDValue Op,
314  unsigned IIOpNum,
315  const MCInstrDesc *II,
316  DenseMap<SDValue, unsigned> &VRBaseMap,
317  bool IsDebug, bool IsClone, bool IsCloned) {
318  assert(Op.getValueType() != MVT::Other &&
319  Op.getValueType() != MVT::Glue &&
320  "Chain and glue operands should occur at end of operand list!");
321  // Get/emit the operand.
322  unsigned VReg = getVR(Op, VRBaseMap);
323 
324  const MCInstrDesc &MCID = MIB->getDesc();
325  bool isOptDef = IIOpNum < MCID.getNumOperands() &&
326  MCID.OpInfo[IIOpNum].isOptionalDef();
327 
328  // If the instruction requires a register in a different class, create
329  // a new virtual register and copy the value into it, but first attempt to
330  // shrink VReg's register class within reason. For example, if VReg == GR32
331  // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
332  if (II) {
333  const TargetRegisterClass *OpRC = nullptr;
334  if (IIOpNum < II->getNumOperands())
335  OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
336 
337  if (OpRC) {
338  const TargetRegisterClass *ConstrainedRC
339  = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
340  if (!ConstrainedRC) {
341  OpRC = TRI->getAllocatableClass(OpRC);
342  assert(OpRC && "Constraints cannot be fulfilled for allocation");
343  unsigned NewVReg = MRI->createVirtualRegister(OpRC);
344  BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
345  TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
346  VReg = NewVReg;
347  } else {
348  assert(ConstrainedRC->isAllocatable() &&
349  "Constraining an allocatable VReg produced an unallocatable class?");
350  }
351  }
352  }
353 
354  // If this value has only one use, that use is a kill. This is a
355  // conservative approximation. InstrEmitter does trivial coalescing
356  // with CopyFromReg nodes, so don't emit kill flags for them.
357  // Avoid kill flags on Schedule cloned nodes, since there will be
358  // multiple uses.
359  // Tied operands are never killed, so we need to check that. And that
360  // means we need to determine the index of the operand.
361  bool isKill = Op.hasOneUse() &&
362  Op.getNode()->getOpcode() != ISD::CopyFromReg &&
363  !IsDebug &&
364  !(IsClone || IsCloned);
365  if (isKill) {
366  unsigned Idx = MIB->getNumOperands();
367  while (Idx > 0 &&
368  MIB->getOperand(Idx-1).isReg() &&
369  MIB->getOperand(Idx-1).isImplicit())
370  --Idx;
371  bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
372  if (isTied)
373  isKill = false;
374  }
375 
376  MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
377  getDebugRegState(IsDebug));
378 }
379 
380 /// AddOperand - Add the specified operand to the specified machine instr. II
381 /// specifies the instruction information for the node, and IIOpNum is the
382 /// operand number (in the II) that we are adding.
383 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
384  SDValue Op,
385  unsigned IIOpNum,
386  const MCInstrDesc *II,
387  DenseMap<SDValue, unsigned> &VRBaseMap,
388  bool IsDebug, bool IsClone, bool IsCloned) {
389  if (Op.isMachineOpcode()) {
390  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
391  IsDebug, IsClone, IsCloned);
392  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
393  MIB.addImm(C->getSExtValue());
394  } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
395  MIB.addFPImm(F->getConstantFPValue());
396  } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
397  // Turn additional physreg operands into implicit uses on non-variadic
398  // instructions. This is used by call and return instructions passing
399  // arguments in registers.
400  bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
401  MIB.addReg(R->getReg(), getImplRegState(Imp));
402  } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
403  MIB.addRegMask(RM->getRegMask());
404  } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
405  MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
406  TGA->getTargetFlags());
407  } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
408  MIB.addMBB(BBNode->getBasicBlock());
409  } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
410  MIB.addFrameIndex(FI->getIndex());
411  } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
412  MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
413  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
414  int Offset = CP->getOffset();
415  unsigned Align = CP->getAlignment();
416  Type *Type = CP->getType();
417  // MachineConstantPool wants an explicit alignment.
418  if (Align == 0) {
419  Align = MF->getDataLayout().getPrefTypeAlignment(Type);
420  if (Align == 0) {
421  // Alignment of vector types. FIXME!
422  Align = MF->getDataLayout().getTypeAllocSize(Type);
423  }
424  }
425 
426  unsigned Idx;
428  if (CP->isMachineConstantPoolEntry())
429  Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
430  else
431  Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
432  MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
433  } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
434  MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
435  } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
436  MIB.addSym(SymNode->getMCSymbol());
437  } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
438  MIB.addBlockAddress(BA->getBlockAddress(),
439  BA->getOffset(),
440  BA->getTargetFlags());
441  } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
442  MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
443  } else {
444  assert(Op.getValueType() != MVT::Other &&
445  Op.getValueType() != MVT::Glue &&
446  "Chain and glue operands should occur at end of operand list!");
447  AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
448  IsDebug, IsClone, IsCloned);
449  }
450 }
451 
452 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
453  MVT VT, const DebugLoc &DL) {
454  const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
455  const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
456 
457  // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
458  // within reason.
459  if (RC && RC != VRC)
460  RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
461 
462  // VReg has been adjusted. It can be used with SubIdx operands now.
463  if (RC)
464  return VReg;
465 
466  // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
467  // register instead.
468  RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
469  assert(RC && "No legal register class for VT supports that SubIdx");
470  unsigned NewReg = MRI->createVirtualRegister(RC);
471  BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
472  .addReg(VReg);
473  return NewReg;
474 }
475 
476 /// EmitSubregNode - Generate machine code for subreg nodes.
477 ///
478 void InstrEmitter::EmitSubregNode(SDNode *Node,
479  DenseMap<SDValue, unsigned> &VRBaseMap,
480  bool IsClone, bool IsCloned) {
481  unsigned VRBase = 0;
482  unsigned Opc = Node->getMachineOpcode();
483 
484  // If the node is only used by a CopyToReg and the dest reg is a vreg, use
485  // the CopyToReg'd destination register instead of creating a new vreg.
486  for (SDNode *User : Node->uses()) {
487  if (User->getOpcode() == ISD::CopyToReg &&
488  User->getOperand(2).getNode() == Node) {
489  unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
491  VRBase = DestReg;
492  break;
493  }
494  }
495  }
496 
497  if (Opc == TargetOpcode::EXTRACT_SUBREG) {
498  // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
499  // constraints on the %dst register, COPY can target all legal register
500  // classes.
501  unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
502  const TargetRegisterClass *TRC =
503  TLI->getRegClassFor(Node->getSimpleValueType(0));
504 
505  unsigned Reg;
506  MachineInstr *DefMI;
509  Reg = R->getReg();
510  DefMI = nullptr;
511  } else {
512  Reg = getVR(Node->getOperand(0), VRBaseMap);
513  DefMI = MRI->getVRegDef(Reg);
514  }
515 
516  unsigned SrcReg, DstReg, DefSubIdx;
517  if (DefMI &&
518  TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
519  SubIdx == DefSubIdx &&
520  TRC == MRI->getRegClass(SrcReg)) {
521  // Optimize these:
522  // r1025 = s/zext r1024, 4
523  // r1026 = extract_subreg r1025, 4
524  // to a copy
525  // r1026 = copy r1024
526  VRBase = MRI->createVirtualRegister(TRC);
527  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
528  TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
529  MRI->clearKillFlags(SrcReg);
530  } else {
531  // Reg may not support a SubIdx sub-register, and we may need to
532  // constrain its register class or issue a COPY to a compatible register
533  // class.
535  Reg = ConstrainForSubReg(Reg, SubIdx,
536  Node->getOperand(0).getSimpleValueType(),
537  Node->getDebugLoc());
538 
539  // Create the destreg if it is missing.
540  if (VRBase == 0)
541  VRBase = MRI->createVirtualRegister(TRC);
542 
543  // Create the extract_subreg machine instruction.
544  MachineInstrBuilder CopyMI =
545  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
546  TII->get(TargetOpcode::COPY), VRBase);
548  CopyMI.addReg(Reg, 0, SubIdx);
549  else
550  CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
551  }
552  } else if (Opc == TargetOpcode::INSERT_SUBREG ||
553  Opc == TargetOpcode::SUBREG_TO_REG) {
554  SDValue N0 = Node->getOperand(0);
555  SDValue N1 = Node->getOperand(1);
556  SDValue N2 = Node->getOperand(2);
557  unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
558 
559  // Figure out the register class to create for the destreg. It should be
560  // the largest legal register class supporting SubIdx sub-registers.
561  // RegisterCoalescer will constrain it further if it decides to eliminate
562  // the INSERT_SUBREG instruction.
563  //
564  // %dst = INSERT_SUBREG %src, %sub, SubIdx
565  //
566  // is lowered by TwoAddressInstructionPass to:
567  //
568  // %dst = COPY %src
569  // %dst:SubIdx = COPY %sub
570  //
571  // There is no constraint on the %src register class.
572  //
573  const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0));
574  SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
575  assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
576 
577  if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
578  VRBase = MRI->createVirtualRegister(SRC);
579 
580  // Create the insert_subreg or subreg_to_reg machine instruction.
581  MachineInstrBuilder MIB =
582  BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
583 
584  // If creating a subreg_to_reg, then the first input operand
585  // is an implicit value immediate, otherwise it's a register
586  if (Opc == TargetOpcode::SUBREG_TO_REG) {
587  const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
588  MIB.addImm(SD->getZExtValue());
589  } else
590  AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
591  IsClone, IsCloned);
592  // Add the subregster being inserted
593  AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
594  IsClone, IsCloned);
595  MIB.addImm(SubIdx);
596  MBB->insert(InsertPos, MIB);
597  } else
598  llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
599 
600  SDValue Op(Node, 0);
601  bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
602  (void)isNew; // Silence compiler warning.
603  assert(isNew && "Node emitted out of order - early");
604 }
605 
606 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
607 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
608 /// register is constrained to be in a particular register class.
609 ///
610 void
611 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
612  DenseMap<SDValue, unsigned> &VRBaseMap) {
613  unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
614 
615  // Create the new VReg in the destination class and emit a copy.
616  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
617  const TargetRegisterClass *DstRC =
618  TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
619  unsigned NewVReg = MRI->createVirtualRegister(DstRC);
620  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
621  NewVReg).addReg(VReg);
622 
623  SDValue Op(Node, 0);
624  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
625  (void)isNew; // Silence compiler warning.
626  assert(isNew && "Node emitted out of order - early");
627 }
628 
629 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
630 ///
631 void InstrEmitter::EmitRegSequence(SDNode *Node,
632  DenseMap<SDValue, unsigned> &VRBaseMap,
633  bool IsClone, bool IsCloned) {
634  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
635  const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
636  unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
637  const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
638  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
639  unsigned NumOps = Node->getNumOperands();
640  assert((NumOps & 1) == 1 &&
641  "REG_SEQUENCE must have an odd number of operands!");
642  for (unsigned i = 1; i != NumOps; ++i) {
643  SDValue Op = Node->getOperand(i);
644  if ((i & 1) == 0) {
646  // Skip physical registers as they don't have a vreg to get and we'll
647  // insert copies for them in TwoAddressInstructionPass anyway.
649  unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
650  unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
651  const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
652  const TargetRegisterClass *SRC =
653  TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
654  if (SRC && SRC != RC) {
655  MRI->setRegClass(NewVReg, SRC);
656  RC = SRC;
657  }
658  }
659  }
660  AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
661  IsClone, IsCloned);
662  }
663 
664  MBB->insert(InsertPos, MIB);
665  SDValue Op(Node, 0);
666  bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
667  (void)isNew; // Silence compiler warning.
668  assert(isNew && "Node emitted out of order - early");
669 }
670 
671 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
672 ///
673 MachineInstr *
675  DenseMap<SDValue, unsigned> &VRBaseMap) {
676  uint64_t Offset = SD->getOffset();
677  MDNode *Var = SD->getVariable();
678  MDNode *Expr = SD->getExpression();
679  DebugLoc DL = SD->getDebugLoc();
680  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
681  "Expected inlined-at fields to agree");
682 
683  if (SD->getKind() == SDDbgValue::FRAMEIX) {
684  // Stack address; this needs to be lowered in target-dependent fashion.
685  // EmitTargetCodeForFrameDebugValue is responsible for allocation.
686  return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
687  .addFrameIndex(SD->getFrameIx())
688  .addImm(Offset)
689  .addMetadata(Var)
690  .addMetadata(Expr);
691  }
692  // Otherwise, we're going to create an instruction here.
693  const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
694  MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
695  if (SD->getKind() == SDDbgValue::SDNODE) {
696  SDNode *Node = SD->getSDNode();
697  SDValue Op = SDValue(Node, SD->getResNo());
698  // It's possible we replaced this SDNode with other(s) and therefore
699  // didn't generate code for it. It's better to catch these cases where
700  // they happen and transfer the debug info, but trying to guarantee that
701  // in all cases would be very fragile; this is a safeguard for any
702  // that were missed.
704  if (I==VRBaseMap.end())
705  MIB.addReg(0U); // undef
706  else
707  AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
708  /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
709  } else if (SD->getKind() == SDDbgValue::CONST) {
710  const Value *V = SD->getConst();
711  if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
712  if (CI->getBitWidth() > 64)
713  MIB.addCImm(CI);
714  else
715  MIB.addImm(CI->getSExtValue());
716  } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
717  MIB.addFPImm(CF);
718  } else {
719  // Could be an Undef. In any case insert an Undef so we can see what we
720  // dropped.
721  MIB.addReg(0U);
722  }
723  } else {
724  // Insert an Undef so we can see what we dropped.
725  MIB.addReg(0U);
726  }
727 
728  // Indirect addressing is indicated by an Imm as the second parameter.
729  if (SD->isIndirect())
730  MIB.addImm(Offset);
731  else {
732  assert(Offset == 0 && "direct value cannot have an offset");
733  MIB.addReg(0U, RegState::Debug);
734  }
735 
736  MIB.addMetadata(Var);
737  MIB.addMetadata(Expr);
738 
739  return &*MIB;
740 }
741 
742 /// EmitMachineNode - Generate machine code for a target-specific node and
743 /// needed dependencies.
744 ///
745 void InstrEmitter::
746 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
747  DenseMap<SDValue, unsigned> &VRBaseMap) {
748  unsigned Opc = Node->getMachineOpcode();
749 
750  // Handle subreg insert/extract specially
751  if (Opc == TargetOpcode::EXTRACT_SUBREG ||
752  Opc == TargetOpcode::INSERT_SUBREG ||
753  Opc == TargetOpcode::SUBREG_TO_REG) {
754  EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
755  return;
756  }
757 
758  // Handle COPY_TO_REGCLASS specially.
759  if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
760  EmitCopyToRegClassNode(Node, VRBaseMap);
761  return;
762  }
763 
764  // Handle REG_SEQUENCE specially.
765  if (Opc == TargetOpcode::REG_SEQUENCE) {
766  EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
767  return;
768  }
769 
770  if (Opc == TargetOpcode::IMPLICIT_DEF)
771  // We want a unique VR for each IMPLICIT_DEF use.
772  return;
773 
774  const MCInstrDesc &II = TII->get(Opc);
775  unsigned NumResults = CountResults(Node);
776  unsigned NumDefs = II.getNumDefs();
777  const MCPhysReg *ScratchRegs = nullptr;
778 
779  // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
780  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
781  // Stackmaps do not have arguments and do not preserve their calling
782  // convention. However, to simplify runtime support, they clobber the same
783  // scratch registers as AnyRegCC.
784  unsigned CC = CallingConv::AnyReg;
785  if (Opc == TargetOpcode::PATCHPOINT) {
787  NumDefs = NumResults;
788  }
789  ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
790  }
791 
792  unsigned NumImpUses = 0;
793  unsigned NodeOperands =
794  countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
795  bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
796 #ifndef NDEBUG
797  unsigned NumMIOperands = NodeOperands + NumResults;
798  if (II.isVariadic())
799  assert(NumMIOperands >= II.getNumOperands() &&
800  "Too few operands for a variadic node!");
801  else
802  assert(NumMIOperands >= II.getNumOperands() &&
803  NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
804  NumImpUses &&
805  "#operands for dag node doesn't match .td file!");
806 #endif
807 
808  // Create the new machine instruction.
809  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
810 
811  // Add result register values for things that are defined by this
812  // instruction.
813  if (NumResults)
814  CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
815 
816  // Emit all of the actual operands of this instruction, adding them to the
817  // instruction as appropriate.
818  bool HasOptPRefs = NumDefs > NumResults;
819  assert((!HasOptPRefs || !HasPhysRegOuts) &&
820  "Unable to cope with optional defs and phys regs defs!");
821  unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
822  for (unsigned i = NumSkip; i != NodeOperands; ++i)
823  AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
824  VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
825 
826  // Add scratch registers as implicit def and early clobber
827  if (ScratchRegs)
828  for (unsigned i = 0; ScratchRegs[i]; ++i)
829  MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
831 
832  // Transfer all of the memory reference descriptions of this instruction.
833  MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
834  cast<MachineSDNode>(Node)->memoperands_end());
835 
836  // Insert the instruction into position in the block. This needs to
837  // happen before any custom inserter hook is called so that the
838  // hook knows where in the block to insert the replacement code.
839  MBB->insert(InsertPos, MIB);
840 
841  // The MachineInstr may also define physregs instead of virtregs. These
842  // physreg values can reach other instructions in different ways:
843  //
844  // 1. When there is a use of a Node value beyond the explicitly defined
845  // virtual registers, we emit a CopyFromReg for one of the implicitly
846  // defined physregs. This only happens when HasPhysRegOuts is true.
847  //
848  // 2. A CopyFromReg reading a physreg may be glued to this instruction.
849  //
850  // 3. A glued instruction may implicitly use a physreg.
851  //
852  // 4. A glued instruction may use a RegisterSDNode operand.
853  //
854  // Collect all the used physreg defs, and make sure that any unused physreg
855  // defs are marked as dead.
856  SmallVector<unsigned, 8> UsedRegs;
857 
858  // Additional results must be physical register defs.
859  if (HasPhysRegOuts) {
860  for (unsigned i = NumDefs; i < NumResults; ++i) {
861  unsigned Reg = II.getImplicitDefs()[i - NumDefs];
862  if (!Node->hasAnyUseOfValue(i))
863  continue;
864  // This implicitly defined physreg has a use.
865  UsedRegs.push_back(Reg);
866  EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
867  }
868  }
869 
870  // Scan the glue chain for any used physregs.
871  if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
872  for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
873  if (F->getOpcode() == ISD::CopyFromReg) {
874  UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
875  continue;
876  } else if (F->getOpcode() == ISD::CopyToReg) {
877  // Skip CopyToReg nodes that are internal to the glue chain.
878  continue;
879  }
880  // Collect declared implicit uses.
881  const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
882  UsedRegs.append(MCID.getImplicitUses(),
883  MCID.getImplicitUses() + MCID.getNumImplicitUses());
884  // In addition to declared implicit uses, we must also check for
885  // direct RegisterSDNode operands.
886  for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
887  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
888  unsigned Reg = R->getReg();
890  UsedRegs.push_back(Reg);
891  }
892  }
893  }
894 
895  // Finally mark unused registers as dead.
896  if (!UsedRegs.empty() || II.getImplicitDefs())
897  MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
898 
899  // Run post-isel target hook to adjust this instruction if needed.
900  if (II.hasPostISelHook())
901  TLI->AdjustInstrPostInstrSelection(*MIB, Node);
902 }
903 
904 /// EmitSpecialNode - Generate machine code for a target-independent node and
905 /// needed dependencies.
906 void InstrEmitter::
907 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
908  DenseMap<SDValue, unsigned> &VRBaseMap) {
909  switch (Node->getOpcode()) {
910  default:
911 #ifndef NDEBUG
912  Node->dump();
913 #endif
914  llvm_unreachable("This target-independent node should have been selected!");
915  case ISD::EntryToken:
916  llvm_unreachable("EntryToken should have been excluded from the schedule!");
917  case ISD::MERGE_VALUES:
918  case ISD::TokenFactor: // fall thru
919  break;
920  case ISD::CopyToReg: {
921  unsigned SrcReg;
922  SDValue SrcVal = Node->getOperand(2);
923  if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
924  SrcReg = R->getReg();
925  else
926  SrcReg = getVR(SrcVal, VRBaseMap);
927 
928  unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
929  if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
930  break;
931 
932  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
933  DestReg).addReg(SrcReg);
934  break;
935  }
936  case ISD::CopyFromReg: {
937  unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
938  EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
939  break;
940  }
941  case ISD::EH_LABEL: {
942  MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
943  BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
944  TII->get(TargetOpcode::EH_LABEL)).addSym(S);
945  break;
946  }
947 
948  case ISD::LIFETIME_START:
949  case ISD::LIFETIME_END: {
950  unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
952 
954  BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
955  .addFrameIndex(FI->getIndex());
956  break;
957  }
958 
959  case ISD::INLINEASM: {
960  unsigned NumOps = Node->getNumOperands();
961  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
962  --NumOps; // Ignore the glue operand.
963 
964  // Create the inline asm machine instruction.
965  MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(),
967 
968  // Add the asm string as an external symbol operand.
969  SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
970  const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
971  MIB.addExternalSymbol(AsmStr);
972 
973  // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
974  // bits.
975  int64_t ExtraInfo =
976  cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
977  getZExtValue();
978  MIB.addImm(ExtraInfo);
979 
980  // Remember to operand index of the group flags.
981  SmallVector<unsigned, 8> GroupIdx;
982 
983  // Remember registers that are part of early-clobber defs.
985 
986  // Add all of the operand registers to the instruction.
987  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
988  unsigned Flags =
989  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
990  const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
991 
992  GroupIdx.push_back(MIB->getNumOperands());
993  MIB.addImm(Flags);
994  ++i; // Skip the ID value.
995 
996  switch (InlineAsm::getKind(Flags)) {
997  default: llvm_unreachable("Bad flags!");
999  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1000  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1001  // FIXME: Add dead flags for physical and virtual registers defined.
1002  // For now, mark physical register defs as implicit to help fast
1003  // regalloc. This makes inline asm look a lot like calls.
1004  MIB.addReg(Reg, RegState::Define |
1006  }
1007  break;
1010  for (unsigned j = 0; j != NumVals; ++j, ++i) {
1011  unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1014  ECRegs.push_back(Reg);
1015  }
1016  break;
1017  case InlineAsm::Kind_RegUse: // Use of register.
1018  case InlineAsm::Kind_Imm: // Immediate.
1019  case InlineAsm::Kind_Mem: // Addressing mode.
1020  // The addressing mode has been selected, just add all of the
1021  // operands to the machine instruction.
1022  for (unsigned j = 0; j != NumVals; ++j, ++i)
1023  AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1024  /*IsDebug=*/false, IsClone, IsCloned);
1025 
1026  // Manually set isTied bits.
1028  unsigned DefGroup = 0;
1029  if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1030  unsigned DefIdx = GroupIdx[DefGroup] + 1;
1031  unsigned UseIdx = GroupIdx.back() + 1;
1032  for (unsigned j = 0; j != NumVals; ++j)
1033  MIB->tieOperands(DefIdx + j, UseIdx + j);
1034  }
1035  }
1036  break;
1037  }
1038  }
1039 
1040  // GCC inline assembly allows input operands to also be early-clobber
1041  // output operands (so long as the operand is written only after it's
1042  // used), but this does not match the semantics of our early-clobber flag.
1043  // If an early-clobber operand register is also an input operand register,
1044  // then remove the early-clobber flag.
1045  for (unsigned Reg : ECRegs) {
1046  if (MIB->readsRegister(Reg, TRI)) {
1047  MachineOperand *MO = MIB->findRegisterDefOperand(Reg, false, TRI);
1048  assert(MO && "No def operand for clobbered register?");
1049  MO->setIsEarlyClobber(false);
1050  }
1051  }
1052 
1053  // Get the mdnode from the asm if it exists and add it to the instruction.
1055  const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1056  if (MD)
1057  MIB.addMetadata(MD);
1058 
1059  MBB->insert(InsertPos, MIB);
1060  break;
1061  }
1062  }
1063 }
1064 
1065 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1066 /// at the given position in the given block.
1068  MachineBasicBlock::iterator insertpos)
1069  : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1070  TII(MF->getSubtarget().getInstrInfo()),
1071  TRI(MF->getSubtarget().getRegisterInfo()),
1072  TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1073  InsertPos(insertpos) {}
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
bool isImplicit() const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void push_back(const T &Elt)
Definition: SmallVector.h:211
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
Definition: MCInstrDesc.h:506
const DebugLoc & getDebugLoc() const
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
size_t i
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:952
bool hasOneUse() const
Return true if there is exactly one use of this node.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:528
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getReg() const
unsigned getNumOperands() const
Definition: User.h:167
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Definition: DataLayout.cpp:699
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Completely target-dependent object reference.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
unsigned getNumOperands() const
Return the number of values used by this operation.
unsigned getNumOperands() const
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:830
const SDValue & getOperand(unsigned Num) const
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:225
EntryToken - This is the marker used to indicate the start of a region.
Definition: ISDOpcodes.h:45
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
unsigned getResNo() const
get the index which selects a specific result in the SDNode
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers. ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:172
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
CopyToReg - This node has three operands: a chain, a register number to set to this value...
Definition: ISDOpcodes.h:170
unsigned SubReg
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
unsigned getMachineOpcode() const
MDNode * getExpression() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
void setIsEarlyClobber(bool Val=true)
#define F(x, y, z)
Definition: MD5.cpp:51
bool isIndirect() const
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MachineBasicBlock * MBB
DbgValueKind getKind() const
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:525
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag...
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: Object/ELF.h:236
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getDebugRegState(bool B)
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:743
unsigned getDefRegState(bool B)
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
unsigned const MachineRegisterInfo * MRI
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:269
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned char TargetFlags=0) const
uint32_t Offset
unsigned getFrameIx() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
Value * getOperand(unsigned i) const
Definition: User.h:145
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:392
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:594
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:865
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
This is the shared class of boolean and integer constants.
Definition: Constants.h:88
void dump() const
Dump this node, for debugging.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:408
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
MachineOperand class - Representation of each machine instruction operand.
SDNode * getSDNode() const
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
bool isMachineOpcode() const
Represents one node in the SelectionDAG.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
iterator_range< use_iterator > uses()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
unsigned getImplRegState(bool B)
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:503
DebugLoc getDebugLoc() const
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:175
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const DebugLoc & getDebugLoc() const
Return the source location info.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const Value * getConst() const
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
uint64_t getOffset() const
LLVM Value Representation.
Definition: Value.h:71
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
static const Function * getParent(const Value *V)
unsigned getResNo() const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
MDNode * getVariable() const
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
SDDbgValue - Holds the information from a dbg_value node through SDISel.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
This file describes how to lower LLVM code to machine code.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
uint64_t getZExtValue() const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.