10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
18 #define GET_INSTRINFO_OPERAND_ENUM
19 #include "AMDGPUGenInstrInfo.inc"
20 #undef GET_INSTRINFO_OPERAND_ENUM
29 class MCRegisterClass;
32 class MCSubtargetInfo;
83 std::pair<int, int> Default,
84 bool OnlyFirstRequired =
false);
116 unsigned &Vmcnt,
unsigned &Expcnt,
unsigned &Lgkmcnt);
138 unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt);
unsigned getExpcntBitMask(IsaVersion Version)
Instances of this class represent a uniqued identifier for a section in the current translation unit...
unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt)
unsigned getVmcntBitMask(IsaVersion Version)
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
MCSection * getHSATextSection(MCContext &Ctx)
MCSection * getHSARodataReadonlyAgentSection(MCContext &Ctx)
unsigned getWaitcntBitMask(IsaVersion Version)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned encodeWaitcnt(IsaVersion Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt)
Context object for machine code objects.
uint8_t OperandType
Information about the type of the operand.
bool isGroupSegment(const GlobalValue *GV)
bool isReadOnlySegment(const GlobalValue *GV)
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
MCSection * getHSADataGlobalAgentSection(MCContext &Ctx)
MCSection * getHSADataGlobalProgramSection(MCContext &Ctx)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool isSI(const MCSubtargetInfo &STI)
unsigned const MachineRegisterInfo * MRI
IsaVersion getIsaVersion(const FeatureBitset &Features)
bool isShader(CallingConv::ID cc)
bool isCompute(CallingConv::ID cc)
unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const FeatureBitset &Features)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Operands with register or inline constant.
Triple - Helper class for working with autoconf configuration names.
unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt)
unsigned getLgkmcntBitMask(IsaVersion Version)
void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt)
bool isCI(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
bool isVI(const MCSubtargetInfo &STI)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
MCSubtargetInfo - Generic base class for all target subtargets.
bool shouldEmitConstantsToTextSection(const Triple &TT)
Operands with register or 32-bit immediate.
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const FeatureBitset Features
const MCOperandInfo * OpInfo
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
StringRef - Represent a constant reference to a string, i.e.
This holds information about one operand of a machine instruction, indicating the register class for ...