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LLVM
4.0.0
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This pass merges inputs of swizzeable instructions into vector sharing common data and/or have enough undef subreg using swizzle abilities. More...
#include "AMDGPU.h"#include "AMDGPUSubtarget.h"#include "R600Defines.h"#include "R600InstrInfo.h"#include "llvm/ADT/DenseMap.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/StringRef.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineDominators.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineLoopInfo.h"#include "llvm/CodeGen/MachineOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/IR/DebugLoc.h"#include "llvm/PassAnalysisSupport.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/raw_ostream.h"#include <cassert>#include <utility>#include <vector>Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "vec-merger" |
Functions | |
| static bool | isImplicitlyDef (MachineRegisterInfo &MRI, unsigned Reg) |
| static unsigned | getReassignedChan (const std::vector< std::pair< unsigned, unsigned >> &RemapChan, unsigned Chan) |
This pass merges inputs of swizzeable instructions into vector sharing common data and/or have enough undef subreg using swizzle abilities.
For instance let's consider the following pseudo code : vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 ... vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3 (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3
is turned into : vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3 ... vreg7<def> = INSERT_SUBREG vreg4, sub3 (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3
This allow regalloc to reduce register pressure for vector registers and to reduce MOV count.
Definition in file R600OptimizeVectorRegisters.cpp.
| #define DEBUG_TYPE "vec-merger" |
Definition at line 57 of file R600OptimizeVectorRegisters.cpp.
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Definition at line 186 of file R600OptimizeVectorRegisters.cpp.
References llvm_unreachable.
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Definition at line 60 of file R600OptimizeVectorRegisters.cpp.
References llvm::MachineRegisterInfo::def_instr_begin(), llvm::MachineRegisterInfo::def_instr_end(), E, llvm::MachineRegisterInfo::isReserved(), and llvm_unreachable.
1.8.6