15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
25 class X86TargetMachine;
670 bool hasSymbolicDisplacement =
true);
675 bool is64Bit,
bool IsVarArg,
bool GuaranteeTCO);
703 unsigned JTI,
MCContext &Ctx)
const override;
724 bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
738 bool *
Fast)
const override;
813 EVT VT)
const override;
821 unsigned Depth = 0)
const override;
826 unsigned Depth)
const override;
829 int64_t &
Offset)
const override;
841 const char *constraint)
const override;
849 std::string &Constraint,
850 std::vector<SDValue> &Ops,
855 if (ConstraintCode ==
"i")
857 else if (ConstraintCode ==
"o")
859 else if (ConstraintCode ==
"v")
861 else if (ConstraintCode ==
"X")
870 std::pair<unsigned, const TargetRegisterClass *>
877 Type *Ty,
unsigned AS)
const override;
897 unsigned AS)
const override;
940 unsigned Intrinsic)
const override;
952 EVT VT)
const override;
958 EVT VT)
const override;
967 return !X86ScalarSSEf64 || VT ==
MVT::f80;
973 EVT NewVT)
const override;
978 return (VT ==
MVT::f64 && X86ScalarSSEf64) ||
979 (VT ==
MVT::f32 && X86ScalarSSEf32);
985 Type *Ty)
const override;
1049 unsigned Factor)
const override;
1051 std::pair<const TargetRegisterClass *, uint8_t>
1053 MVT VT)
const override;
1063 bool X86ScalarSSEf32;
1064 bool X86ScalarSSEf64;
1067 std::vector<APFloat> LegalFPImmediates;
1071 void addLegalFPImmediate(
const APFloat& Imm) {
1072 LegalFPImmediates.push_back(Imm);
1075 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1077 const SmallVectorImpl<ISD::InputArg> &
Ins,
1078 const SDLoc &dl, SelectionDAG &DAG,
1079 SmallVectorImpl<SDValue> &InVals)
const;
1081 const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1082 const SDLoc &dl, SelectionDAG &DAG,
1083 const CCValAssign &VA, MachineFrameInfo &MFI,
1085 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
1086 const SDLoc &dl, SelectionDAG &DAG,
1087 const CCValAssign &VA,
1088 ISD::ArgFlagsTy
Flags)
const;
1094 bool IsEligibleForTailCallOptimization(SDValue Callee,
1097 bool isCalleeStructRet,
1098 bool isCallerStructRet,
1100 const SmallVectorImpl<ISD::OutputArg> &Outs,
1101 const SmallVectorImpl<SDValue> &OutVals,
1102 const SmallVectorImpl<ISD::InputArg> &
Ins,
1103 SelectionDAG& DAG)
const;
1104 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1105 SDValue Chain,
bool IsTailCall,
1106 bool Is64Bit,
int FPDiff,
1107 const SDLoc &dl)
const;
1109 unsigned GetAlignedArgumentStackSize(
unsigned StackSize,
1110 SelectionDAG &DAG)
const;
1112 unsigned getAddressSpace(
void)
const;
1114 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue
Op, SelectionDAG &DAG,
1116 bool isReplace)
const;
1118 SDValue LowerBUILD_VECTOR(SDValue
Op, SelectionDAG &DAG)
const;
1119 SDValue LowerBUILD_VECTORvXi1(SDValue
Op, SelectionDAG &DAG)
const;
1120 SDValue LowerVSELECT(SDValue
Op, SelectionDAG &DAG)
const;
1121 SDValue LowerEXTRACT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1122 SDValue ExtractBitFromMaskVector(SDValue
Op, SelectionDAG &DAG)
const;
1123 SDValue InsertBitToMaskVector(SDValue
Op, SelectionDAG &DAG)
const;
1124 SDValue LowerINSERT_VECTOR_ELT(SDValue
Op, SelectionDAG &DAG)
const;
1126 unsigned getGlobalWrapperKind(
const GlobalValue *GV =
nullptr)
const;
1127 SDValue LowerConstantPool(SDValue
Op, SelectionDAG &DAG)
const;
1128 SDValue LowerBlockAddress(SDValue
Op, SelectionDAG &DAG)
const;
1129 SDValue LowerGlobalAddress(
const GlobalValue *GV,
const SDLoc &dl,
1130 int64_t
Offset, SelectionDAG &DAG)
const;
1131 SDValue LowerGlobalAddress(SDValue
Op, SelectionDAG &DAG)
const;
1132 SDValue LowerGlobalTLSAddress(SDValue
Op, SelectionDAG &DAG)
const;
1133 SDValue LowerExternalSymbol(SDValue
Op, SelectionDAG &DAG)
const;
1135 SDValue LowerSINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1136 SDValue LowerUINT_TO_FP(SDValue
Op, SelectionDAG &DAG)
const;
1137 SDValue LowerUINT_TO_FP_i64(SDValue
Op, SelectionDAG &DAG)
const;
1138 SDValue LowerUINT_TO_FP_i32(SDValue
Op, SelectionDAG &DAG)
const;
1139 SDValue lowerUINT_TO_FP_vec(SDValue
Op, SelectionDAG &DAG)
const;
1140 SDValue LowerTRUNCATE(SDValue
Op, SelectionDAG &DAG)
const;
1141 SDValue LowerFP_TO_INT(SDValue
Op,
const X86Subtarget &Subtarget,
1142 SelectionDAG &DAG)
const;
1144 SelectionDAG &DAG)
const;
1145 SDValue LowerSETCC(SDValue
Op, SelectionDAG &DAG)
const;
1146 SDValue LowerSETCCE(SDValue
Op, SelectionDAG &DAG)
const;
1147 SDValue LowerSELECT(SDValue
Op, SelectionDAG &DAG)
const;
1148 SDValue LowerBRCOND(SDValue
Op, SelectionDAG &DAG)
const;
1149 SDValue LowerJumpTable(SDValue
Op, SelectionDAG &DAG)
const;
1150 SDValue LowerDYNAMIC_STACKALLOC(SDValue
Op, SelectionDAG &DAG)
const;
1151 SDValue LowerVASTART(SDValue
Op, SelectionDAG &DAG)
const;
1152 SDValue LowerVAARG(SDValue
Op, SelectionDAG &DAG)
const;
1153 SDValue LowerRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1154 SDValue LowerADDROFRETURNADDR(SDValue
Op, SelectionDAG &DAG)
const;
1155 SDValue LowerFRAMEADDR(SDValue
Op, SelectionDAG &DAG)
const;
1156 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue
Op, SelectionDAG &DAG)
const;
1157 SDValue LowerEH_RETURN(SDValue
Op, SelectionDAG &DAG)
const;
1158 SDValue lowerEH_SJLJ_SETJMP(SDValue
Op, SelectionDAG &DAG)
const;
1159 SDValue lowerEH_SJLJ_LONGJMP(SDValue
Op, SelectionDAG &DAG)
const;
1160 SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue
Op, SelectionDAG &DAG)
const;
1161 SDValue LowerINIT_TRAMPOLINE(SDValue
Op, SelectionDAG &DAG)
const;
1162 SDValue LowerFLT_ROUNDS_(SDValue
Op, SelectionDAG &DAG)
const;
1163 SDValue LowerWin64_i128OP(SDValue
Op, SelectionDAG &DAG)
const;
1164 SDValue LowerGC_TRANSITION_START(SDValue
Op, SelectionDAG &DAG)
const;
1165 SDValue LowerGC_TRANSITION_END(SDValue
Op, SelectionDAG &DAG)
const;
1168 LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1169 const SmallVectorImpl<ISD::InputArg> &
Ins,
1170 const SDLoc &dl, SelectionDAG &DAG,
1171 SmallVectorImpl<SDValue> &InVals)
const override;
1172 SDValue LowerCall(CallLoweringInfo &CLI,
1173 SmallVectorImpl<SDValue> &InVals)
const override;
1175 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
1176 const SmallVectorImpl<ISD::OutputArg> &Outs,
1177 const SmallVectorImpl<SDValue> &OutVals,
1178 const SDLoc &dl, SelectionDAG &DAG)
const override;
1180 bool supportSplitCSR(MachineFunction *MF)
const override {
1182 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
1184 void initializeSplitCSR(MachineBasicBlock *Entry)
const override;
1185 void insertCopiesSplitCSR(
1186 MachineBasicBlock *Entry,
1187 const SmallVectorImpl<MachineBasicBlock *> &Exits)
const override;
1189 bool isUsedByReturnOnly(SDNode *
N, SDValue &Chain)
const override;
1191 bool mayBeEmittedAsTailCall(CallInst *CI)
const override;
1193 EVT getTypeForExtReturn(LLVMContext &
Context, EVT VT,
1198 const SmallVectorImpl<ISD::OutputArg> &Outs,
1199 LLVMContext &
Context)
const override;
1204 shouldExpandAtomicLoadInIR(LoadInst *SI)
const override;
1205 bool shouldExpandAtomicStoreInIR(StoreInst *SI)
const override;
1207 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI)
const override;
1210 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI)
const override;
1212 bool needsCmpXchgNb(
Type *MemType)
const;
1214 void SetupEntryBlockForSjLj(MachineInstr &
MI, MachineBasicBlock *
MBB,
1215 MachineBasicBlock *DispatchBB,
int FI)
const;
1219 EmitVAARG64WithCustomInserter(MachineInstr &
MI,
1220 MachineBasicBlock *
MBB)
const;
1224 EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr,
1225 MachineBasicBlock *BB)
const;
1227 MachineBasicBlock *EmitLoweredSelect(MachineInstr &
I,
1228 MachineBasicBlock *BB)
const;
1230 MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &
I,
1231 MachineBasicBlock *BB)
const;
1233 MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &
MI,
1234 MachineBasicBlock *BB)
const;
1236 MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &
MI,
1237 MachineBasicBlock *BB)
const;
1239 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &
MI,
1240 MachineBasicBlock *BB)
const;
1242 MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &
MI,
1243 MachineBasicBlock *BB)
const;
1245 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &
MI,
1246 MachineBasicBlock *BB)
const;
1248 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &
MI,
1249 MachineBasicBlock *
MBB)
const;
1251 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &
MI,
1252 MachineBasicBlock *
MBB)
const;
1254 MachineBasicBlock *emitFMA3Instr(MachineInstr &
MI,
1255 MachineBasicBlock *
MBB)
const;
1257 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &
MI,
1258 MachineBasicBlock *
MBB)
const;
1262 SDValue EmitTest(SDValue Op0,
unsigned X86CC,
const SDLoc &dl,
1263 SelectionDAG &DAG)
const;
1267 SDValue EmitCmp(SDValue Op0, SDValue Op1,
unsigned X86CC,
const SDLoc &dl,
1268 SelectionDAG &DAG)
const;
1271 SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG)
const;
1274 bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG)
const override;
1277 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
1278 int &RefinementSteps,
bool &UseOneConstNR,
1279 bool Reciprocal)
const override;
1282 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
int Enabled,
1283 int &RefinementSteps)
const override;
1286 unsigned combineRepeatedFPDivisors()
const override;
1291 const TargetLibraryInfo *libInfo);
1300 :
MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1318 :
MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1382 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) !=...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isVINSERT128Index(SDNode *N)
Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable f...
Double shift instructions.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
Vector comparison generating mask bits for fp and integer signed and unsigned data types...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
Repeat move, corresponds to X86::REP_MOVSx.
static bool classof(const SDNode *N)
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
Return with a flag operand.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
bool isVectorClearMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Compute Double Block Packed Sum-Absolute-Differences.
bool isVEXTRACT128Index(SDNode *N)
Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable fo...
A Module instance is used to store all the information related to an LLVM module. ...
static bool classof(const SDNode *N)
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
const SDValue & getValue() const
This class represents a function call, abstracting a target machine's calling convention.
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
unsigned getInsertVINSERT128Immediate(SDNode *N)
Return the appropriate immediate to insert at the specified INSERT_SUBVECTOR index with VINSERTF128...
const SDValue & getOperand(unsigned Num) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
static bool classof(const SDNode *N)
SSE4A Extraction and Insertion.
static bool classof(const SDNode *N)
An instruction for reading from memory.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Bitwise logical ANDNOT of floating point values.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
This operation implements the lowering for readcyclecounter.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
X86 compare and logical compare instructions.
MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isVector() const
isVector - Return true if this is a vector value type.
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
A description of a memory reference used in the backend.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
struct fuzzer::@269 Flags
Bitwise Logical AND NOT of Packed FP values.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type...
bool isVINSERT256Index(SDNode *N)
Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable f...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result...
unsigned getExtractVEXTRACT128Immediate(SDNode *N)
Return the appropriate immediate to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Integer horizontal add/sub.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
Context object for machine code objects.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const SDValue & getBasePtr() const
Copies a 32-bit value from the low word of a MMX vector to a GPR.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
X86 FP SETCC, similar to above, but with output as an i1 mask and with optional rounding mode...
bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const override
Return true if the MachineFunction contains a COPY which would imply HasOpaqueSPAdjustment.
Return from interrupt. Operand 0 is the number of bytes to pop.
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
static bool classof(const SDNode *N)
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
Floating point horizontal add/sub.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Bitwise logical XOR of floating point values.
static bool classof(const SDNode *N)
const SDValue & getBasePtr() const
const SDValue & getMask() const
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
This instruction implements an extending load to FP stack slots.
This is an important class for using LLVM in a threaded context.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
This is an important base class in LLVM.
Repeat fill, corresponds to X86::REP_STOSx.
static bool is64Bit(const char *name)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
X86 conditional branches.
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Commutative FMIN and FMAX.
On Darwin, this node represents the result of the popl at function entry, used for PIC code...
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
Windows x64, Windows Itanium (IA-64)
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
MachineMemOperand * MMO
Memory reference information.
bool isVEXTRACT256Index(SDNode *N)
Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable fo...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
These operations represent an abstract X86 call instruction, which includes a bunch of information...
Floating point max and min.
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word. ...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Provides information about what library functions are available for the current target.
X86 Read Time-Stamp Counter and Processor ID.
bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const override
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
This is an abstract virtual class for memory operations.
unsigned getExtractVEXTRACT256Immediate(SDNode *N)
Return the appropriate immediate to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64X4...
Floating point reciprocal-sqrt and reciprocal approximation.
bool useSoftFloat() const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
X86 bit-test instructions.
virtual bool needsFixedCatchObjects() const override
const SDValue & getValue() const
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
MaskedTruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Class for arbitrary precision integers.
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
AddrMode
ARM Addressing Modes.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source...
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Places new result values for the node in Results (their number and types must exactly match those of ...
Representation of each machine instruction.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code...
Value * getIRStackGuard(IRBuilder<> &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress.
Bitwise logical AND of floating point values.
Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Customize the preferred legalization strategy for certain types.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Value * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
LOCK-prefixed arithmetic read-modify-write instructions.
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getInsertVINSERT256Immediate(SDNode *N)
Return the appropriate immediate to insert at the specified INSERT_SUBVECTOR index with VINSERTF64x4...
Blend where the selector is an immediate.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
This instruction implements a truncating store to FP stack slots.
Combined add and sub on an FP vector.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This instruction grabs the address of the next argument from a va_list.
LLVM Value Representation.
Bitwise logical OR of floating point values.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
Blend where the condition has been shrunk.
X86 Read Performance Monitoring Counters.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
StringRef - Represent a constant reference to a string, i.e.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Returns true of the given offset can be fit into displacement field of the instruction.
bool isVectorShiftByScalarCheap(Type *Ty) const override
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Compute Sum of Absolute Differences.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
bool isIntDivCheap(EVT VT, AttributeSet Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
Shuffle 16 8-bit values within a vector.
This file describes how to lower LLVM code to machine code.
Special wrapper used under X86-64 PIC mode for RIP relative displacements.