63 #define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
64 #define FIXUPBW_NAME "x86-fixup-bw-insts"
66 #define DEBUG_TYPE FIXUPBW_NAME
71 cl::desc(
"Change byte and word instructions to larger sizes"),
84 unsigned &SuperDestReg)
const;
101 bool &WasCandidate)
const;
156 MLI = &getAnalysis<MachineLoopInfo>();
159 DEBUG(
dbgs() <<
"Start X86FixupBWInsts\n";);
163 processBasicBlock(MF,
MBB);
165 DEBUG(
dbgs() <<
"End X86FixupBWInsts\n";);
179 bool FixupBWInstPass::getSuperRegDestIfDead(
MachineInstr *OrigMI,
180 unsigned &SuperDestReg)
const {
186 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
192 if (SubRegIdx == X86::sub_8bit_hi)
195 if (LiveRegs.contains(SuperDestReg))
198 if (SubRegIdx == X86::sub_8bit) {
202 unsigned UpperByteReg =
205 if (LiveRegs.contains(UpperByteReg))
212 MachineInstr *FixupBWInstPass::tryReplaceLoad(
unsigned New32BitOpcode,
220 if (!getSuperRegDestIfDead(MI, NewDestReg))
228 for (
unsigned i = 1;
i < NumArgs; ++
i)
242 if (!getSuperRegDestIfDead(MI, NewDestReg))
250 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
251 TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
266 if (
Op.getReg() != (
Op.isDef() ? NewDestReg : NewSrcReg))
274 bool &WasCandidate)
const {
276 WasCandidate =
false;
286 if (ML->begin() == ML->end() && !OptForSize) {
287 NewMI = tryReplaceLoad(X86::MOVZX32rm8, MI);
298 NewMI = tryReplaceLoad(X86::MOVZX32rm16, MI);
308 NewMI = tryReplaceCopy(MI);
339 LiveRegs.addLiveOuts(MBB);
341 bool WasCandidate =
false;
346 MachineInstr *NewMI = tryReplaceInstr(MI, MBB, WasCandidate);
351 MIReplacements.
push_back(std::make_pair(MI, NewMI));
355 LiveRegs.stepBackward(*MI);
358 while (!MIReplacements.
empty()) {
void push_back(const T &Elt)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeFixupBWInstPassPass(PassRegistry &)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
AnalysisUsage & addRequired()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
mmo_iterator memoperands_end() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
FunctionPass class - This class is used to implement most global optimizations.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static cl::opt< bool > FixupBWInsts("fixup-byte-word-insts", cl::desc("Change byte and word instructions to larger sizes"), cl::init(true), cl::Hidden)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
iterator_range< mop_iterator > implicit_operands()
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
A set of live physical registers with functions to track liveness when walking backward/forward throu...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
StringRef - Represent a constant reference to a string, i.e.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
Properties which a MachineFunction may have at a given point in time.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.