25 const InstrStage *IS,
const unsigned *
OC,
const unsigned *FP)
26 :
MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
TargetSubtargetInfo()=delete
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
virtual ~TargetSubtargetInfo()
Triple - Helper class for working with autoconf configuration names.
Specify the latency in cpu cycles for a particular scheduling class and def index.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
These values represent a non-pipelined step in the execution of an instruction.
MCSubtargetInfo - Generic base class for all target subtargets.
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
StringRef - Represent a constant reference to a string, i.e.
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).