|
LLVM
4.0.0
|
#include <R600InstrInfo.h>
Public Types | |
| enum | BankSwizzle { ALU_VEC_012_SCL_210 = 0, ALU_VEC_021_SCL_122, ALU_VEC_120_SCL_212, ALU_VEC_102_SCL_221, ALU_VEC_201, ALU_VEC_210 } |
Definition at line 37 of file R600InstrInfo.h.
| Enumerator | |
|---|---|
| ALU_VEC_012_SCL_210 | |
| ALU_VEC_021_SCL_122 | |
| ALU_VEC_120_SCL_212 | |
| ALU_VEC_102_SCL_221 | |
| ALU_VEC_201 | |
| ALU_VEC_210 | |
Definition at line 58 of file R600InstrInfo.h.
|
explicit |
Definition at line 31 of file R600InstrInfo.cpp.
| void R600InstrInfo::addFlag | ( | MachineInstr & | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Add one of the MO_FLAG* flags to the specified Operand.
Definition at line 1450 of file R600InstrInfo.cpp.
References clearFlag(), getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NOT_LAST, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter(), and insertBranch().
|
override |
Definition at line 652 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::CreateReg(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, isBranch(), isJump(), isPredicateSetter(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
| MachineInstrBuilder R600InstrInfo::buildDefaultInstruction | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | Opcode, | ||
| unsigned | DstReg, | ||
| unsigned | Src0Reg, | ||
| unsigned | Src1Reg = 0 |
||
| ) | const |
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.
You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.
Definition at line 1222 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().
Referenced by buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), copyPhysReg(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| MachineInstrBuilder R600InstrInfo::buildIndirectRead | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | ValueReg, | ||
| unsigned | Address, | ||
| unsigned | OffsetReg | ||
| ) | const |
Build instruction(s) for an indirect register read.
Definition at line 1127 of file R600InstrInfo.cpp.
| MachineInstrBuilder R600InstrInfo::buildIndirectWrite | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | ValueReg, | ||
| unsigned | Address, | ||
| unsigned | OffsetReg | ||
| ) | const |
Build instruction(s) for an indirect register write.
Definition at line 1095 of file R600InstrInfo.cpp.
| MachineInstr * R600InstrInfo::buildMovImm | ( | MachineBasicBlock & | BB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | DstReg, | ||
| uint64_t | Imm | ||
| ) | const |
Definition at line 1349 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), and setImmOperand().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| MachineInstr * R600InstrInfo::buildMovInstr | ( | MachineBasicBlock * | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | DstReg, | ||
| unsigned | SrcReg | ||
| ) | const |
Definition at line 1359 of file R600InstrInfo.cpp.
References buildDefaultInstruction().
Referenced by expandPostRAPseudo().
| MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction | ( | MachineBasicBlock & | MBB, |
| MachineInstr * | MI, | ||
| unsigned | Slot, | ||
| unsigned | DstReg | ||
| ) | const |
Definition at line 1301 of file R600InstrInfo.cpp.
References assert(), buildDefaultInstruction(), llvm::AMDGPUSubtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), getSlotedOps(), llvm::MachineOperand::isImm(), MI, llvm::AMDGPUSubtarget::R700, llvm::MachineOperand::setImm(), setImmOperand(), llvm::MachineOperand::setReg(), and write().
Calculate the "Indirect Address" for the given RegIndex and Channel.
We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.
Definition at line 998 of file R600InstrInfo.cpp.
References assert().
Referenced by expandPostRAPseudo().
| bool R600InstrInfo::canBeConsideredALU | ( | const MachineInstr & | MI | ) | const |
Opcode represents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass. Definition at line 136 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), isALUInstr(), isCubeOp(), and isVector().
| void R600InstrInfo::clearFlag | ( | MachineInstr & | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Clear the specified flag on the instruction.
Definition at line 1471 of file R600InstrInfo.cpp.
References getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by addFlag(), and removeBranch().
|
override |
Definition at line 38 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), contains(), llvm::RegState::Define, llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), I, llvm::RegState::Implicit, and llvm::MachineOperand::setIsKill().
|
override |
Definition at line 614 of file R600InstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData().
| bool R600InstrInfo::definesAddressRegister | ( | MachineInstr & | MI | ) | const |
Definition at line 211 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findRegisterDefOperandIdx().
|
override |
Definition at line 946 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isPredicateSetter().
|
override |
Definition at line 1004 of file R600InstrInfo.cpp.
References llvm::dwarf::syntax::Address, buildMovInstr(), calculateIndirectAddress(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::eraseFromParent(), llvm::R600RegisterInfo::getHWRegChan(), llvm::R600RegisterInfo::getHWRegIndex(), llvm::MachineOperand::getImm(), getIndirectAddrRegClass(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::TargetRegisterClass::getRegister(), isRegisterLoad(), isRegisterStore(), MBB, and MI.
| bool R600InstrInfo::FindSwizzleForVectorSlot | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
| std::vector< R600InstrInfo::BankSwizzle > & | SwzCandidate, | ||
| const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
| R600InstrInfo::BankSwizzle | TransSwz | ||
| ) | const |
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
Definition at line 475 of file R600InstrInfo.cpp.
References isLegalUpTo(), and NextPossibleSolution().
Referenced by fitsReadPortLimitations().
| bool R600InstrInfo::fitsConstReadLimitations | ( | const std::vector< MachineInstr * > & | MIs | ) | const |
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
This function check if MI set in input meet this limitations
Definition at line 586 of file R600InstrInfo.cpp.
References contains(), llvm::R600RegisterInfo::getHWRegChan(), llvm::MachineInstr::getOpcode(), getSrcs(), i, llvm::SmallSet< T, N, C >::insert(), isALUInstr(), and llvm::SmallSet< T, N, C >::size().
Same but using const index set instead of MI set.
Definition at line 561 of file R600InstrInfo.cpp.
| bool R600InstrInfo::fitsReadPortLimitations | ( | const std::vector< MachineInstr * > & | MIs, |
| const DenseMap< unsigned, unsigned > & | PV, | ||
| std::vector< BankSwizzle > & | BS, | ||
| bool | isLastAluTrans | ||
| ) | const |
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.
Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.
Definition at line 512 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, FindSwizzleForVectorSlot(), getOperandIdx(), i, and isConstCompatible().
| MachineOperand & R600InstrInfo::getFlagOp | ( | MachineInstr & | MI, |
| unsigned | SrcIdx = 0, |
||
| unsigned | Flag = 0 |
||
| ) | const |
| SrcIdx | The register source to set the flag on (e.g src0, src1, src2) |
| Flag | The flag being set. |
Definition at line 1385 of file R600InstrInfo.cpp.
References assert(), GET_FLAG_OPERAND_IDX, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and write().
Referenced by addFlag(), and clearFlag().
| const TargetRegisterClass * R600InstrInfo::getIndirectAddrRegClass | ( | ) | const |
Definition at line 1091 of file R600InstrInfo.cpp.
Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().
| int R600InstrInfo::getIndirectIndexBegin | ( | const MachineFunction & | MF | ) | const |
Definition at line 1161 of file R600InstrInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::MachineFunction::getFrameInfo(), getIndirectAddrRegClass(), llvm::MachineFrameInfo::getNumObjects(), llvm::TargetRegisterClass::getNumRegs(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getRegister(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::AArch64CC::LE, llvm::MachineRegisterInfo::livein_begin(), llvm::MachineRegisterInfo::livein_empty(), llvm::MachineRegisterInfo::livein_end(), MRI, and Offset.
Referenced by getIndirectIndexEnd(), and reserveIndirectRegisters().
| int R600InstrInfo::getIndirectIndexEnd | ( | const MachineFunction & | MF | ) | const |
Definition at line 1196 of file R600InstrInfo.cpp.
References llvm::AMDGPUFrameLowering::getFrameIndexReference(), llvm::MachineFunction::getFrameInfo(), llvm::R600Subtarget::getFrameLowering(), getIndirectIndexBegin(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFunction::getSubtarget(), llvm::MachineFrameInfo::hasVarSizedObjects(), and Offset.
Referenced by reserveIndirectRegisters().
|
override |
Definition at line 990 of file R600InstrInfo.cpp.
| unsigned R600InstrInfo::getMaxAlusPerClause | ( | ) | const |
Definition at line 1218 of file R600InstrInfo.cpp.
| int R600InstrInfo::getOperandIdx | ( | const MachineInstr & | MI, |
| unsigned | Op | ||
| ) | const |
Get the index of Op in the MachineInstr.
Op. Definition at line 1365 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by buildSlotOfVectorInstruction(), copyPhysReg(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), fitsReadPortLimitations(), getFlagOp(), getSelIdx(), getSrcs(), isLDSRetInstr(), PredicateInstruction(), and setImmOperand().
Get the index of Op for the given Opcode.
Op. Definition at line 1369 of file R600InstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx().
|
override |
Definition at line 986 of file R600InstrInfo.cpp.
|
inline |
Definition at line 69 of file R600InstrInfo.h.
Referenced by llvm::R600Subtarget::getRegisterInfo().
Definition at line 232 of file R600InstrInfo.cpp.
References getOperandIdx().
| SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs | ( | MachineInstr & | MI | ) | const |
Definition at line 256 of file R600InstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by fitsConstReadLimitations().
Definition at line 116 of file R600InstrInfo.cpp.
References R600_InstFlag::OP1, R600_InstFlag::OP2, and R600_InstFlag::OP3.
|
override |
Definition at line 734 of file R600InstrInfo.cpp.
References addFlag(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), llvm::MachineInstr::getOperand(), llvm::RegState::Kill, MO_FLAG_PUSH, and llvm::MachineOperand::setImm().
Opcode represents an ALU instruction. Definition at line 110 of file R600InstrInfo.cpp.
References R600_InstFlag::ALU_INST.
Referenced by canBeConsideredALU(), fitsConstReadLimitations(), and readsLDSSrcReg().
Definition at line 99 of file R600InstrInfo.cpp.
Referenced by canBeConsideredALU().
Definition at line 172 of file R600InstrInfo.cpp.
References R600_InstFlag::IS_EXPORT.
| bool llvm::R600InstrInfo::isFlagSet | ( | const MachineInstr & | MI, |
| unsigned | Operand, | ||
| unsigned | Flag | ||
| ) | const |
Determine if the specified Flag is set on this Operand.
Definition at line 124 of file R600InstrInfo.cpp.
References R600_InstFlag::LDS_1A, R600_InstFlag::LDS_1A1D, and R600_InstFlag::LDS_1A2D.
Referenced by isLDSRetInstr().
Definition at line 132 of file R600InstrInfo.cpp.
References getOperandIdx(), and isLDSInstr().
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
|
override |
MBBI can be moved into a new basic. Definition at line 73 of file R600InstrInfo.cpp.
References E, I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and llvm::TargetRegisterInfo::isVirtualRegister().
| unsigned R600InstrInfo::isLegalUpTo | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
| const std::vector< R600InstrInfo::BankSwizzle > & | Swz, | ||
| const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
| R600InstrInfo::BankSwizzle | TransSwz | ||
| ) | const |
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.
Definition at line 406 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, GET_REG_INDEX, getTransSwizzle(), i, and Swizzle().
Referenced by FindSwizzleForVectorSlot().
Definition at line 84 of file R600InstrInfo.cpp.
|
override |
Definition at line 855 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), and isVector().
|
override |
Definition at line 840 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
|
override |
Definition at line 898 of file R600InstrInfo.cpp.
|
override |
Definition at line 879 of file R600InstrInfo.cpp.
|
override |
Definition at line 887 of file R600InstrInfo.cpp.
|
override |
Definition at line 906 of file R600InstrInfo.cpp.
Definition at line 95 of file R600InstrInfo.cpp.
|
inline |
Definition at line 318 of file R600InstrInfo.h.
References llvm::MachineInstr::getOpcode(), and llvm::R600InstrFlags::REGISTER_LOAD.
Referenced by expandPostRAPseudo().
|
inline |
Definition at line 314 of file R600InstrInfo.h.
References llvm::MachineInstr::getOpcode(), and llvm::R600InstrFlags::REGISTER_STORE.
Referenced by expandPostRAPseudo().
Definition at line 154 of file R600InstrInfo.cpp.
References llvm::AMDGPUSubtarget::hasCaymanISA().
Referenced by isTransOnly().
| bool R600InstrInfo::isTransOnly | ( | const MachineInstr & | MI | ) | const |
Definition at line 160 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isTransOnly().
| bool R600InstrInfo::isVector | ( | const MachineInstr & | MI | ) | const |
Vector instructions are instructions that must fill all instruction slots within an instruction group.
Definition at line 34 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and R600_InstFlag::VECTOR.
Referenced by canBeConsideredALU(), and isPredicable().
Definition at line 164 of file R600InstrInfo.cpp.
Referenced by isVectorOnly().
| bool R600InstrInfo::isVectorOnly | ( | const MachineInstr & | MI | ) | const |
Definition at line 168 of file R600InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isVectorOnly().
Definition at line 197 of file R600InstrInfo.cpp.
|
override |
Definition at line 952 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::RegState::Implicit, MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
| bool R600InstrInfo::readsLDSSrcReg | ( | const MachineInstr & | MI | ) | const |
Definition at line 215 of file R600InstrInfo.cpp.
References contains(), E, llvm::MachineInstr::getOpcode(), I, isALUInstr(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::operands_begin(), and llvm::MachineInstr::operands_end().
|
override |
Definition at line 781 of file R600InstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), clearFlag(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), I, and MO_FLAG_PUSH.
| void R600InstrInfo::reserveIndirectRegisters | ( | BitVector & | Reserved, |
| const MachineFunction & | MF | ||
| ) | const |
Reserve the registers that may be accesed using indirect addressing.
Definition at line 1070 of file R600InstrInfo.cpp.
References llvm::WebAssembly::End, llvm::R600Subtarget::getFrameLowering(), getIndirectIndexBegin(), getIndirectIndexEnd(), llvm::AMDGPUFrameLowering::getStackWidth(), llvm::MachineFunction::getSubtarget(), and llvm::BitVector::set().
|
override |
Definition at line 913 of file R600InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
| void R600InstrInfo::setImmOperand | ( | MachineInstr & | MI, |
| unsigned | Op, | ||
| int64_t | Imm | ||
| ) | const |
Helper function for setting instruction flag values.
Definition at line 1373 of file R600InstrInfo.cpp.
References assert(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::setImm().
Referenced by buildMovImm(), buildSlotOfVectorInstruction(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| bool R600InstrInfo::usesAddressRegister | ( | MachineInstr & | MI | ) | const |
Definition at line 207 of file R600InstrInfo.cpp.
References llvm::MachineInstr::findRegisterUseOperandIdx().
Definition at line 186 of file R600InstrInfo.cpp.
References llvm::R600Subtarget::hasVertexCache(), IS_TEX, and IS_VTX.
Referenced by usesTextureCache().
| bool R600InstrInfo::usesTextureCache | ( | const MachineInstr & | MI | ) | const |
Definition at line 190 of file R600InstrInfo.cpp.
References llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::isCompute(), usesTextureCache(), and usesVertexCache().
Definition at line 176 of file R600InstrInfo.cpp.
References llvm::R600Subtarget::hasVertexCache(), and IS_VTX.
Referenced by usesTextureCache(), and usesVertexCache().
| bool R600InstrInfo::usesVertexCache | ( | const MachineInstr & | MI | ) | const |
Definition at line 180 of file R600InstrInfo.cpp.
References llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::isCompute(), and usesVertexCache().
1.8.6