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LLVM
4.0.0
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ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. More...
#include <ScheduleDAGInstrs.h>
Classes | |
| class | Value2SUsMap |
Public Types | |
| typedef std::list< SUnit * > | SUList |
| A list of SUnits, used in Value2SUsMap, during DAG construction. More... | |
Public Member Functions | |
| ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false) | |
| ~ScheduleDAGInstrs () override | |
| const TargetSchedModel * | getSchedModel () const |
| Get the machine model for instruction scheduling. More... | |
| const MCSchedClassDesc * | getSchedClass (SUnit *SU) const |
| Resolve and cache a resolved scheduling class for an SUnit. More... | |
| MachineBasicBlock::iterator | begin () const |
| begin - Return an iterator to the top of the current scheduling region. More... | |
| MachineBasicBlock::iterator | end () const |
| end - Return an iterator to the bottom of the current scheduling region. More... | |
| SUnit * | newSUnit (MachineInstr *MI) |
| newSUnit - Creates a new SUnit and return a ptr to it. More... | |
| SUnit * | getSUnit (MachineInstr *MI) const |
| getSUnit - Return an existing SUnit for this MI, or NULL. More... | |
| virtual void | startBlock (MachineBasicBlock *BB) |
| startBlock - Prepare to perform scheduling in the given block. More... | |
| virtual void | finishBlock () |
| finishBlock - Clean up after scheduling in the given block. More... | |
| virtual void | enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) |
| Initialize the scheduler state for the next scheduling region. More... | |
| virtual void | exitRegion () |
| Notify that the scheduler has finished scheduling the current region. More... | |
| void | buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false) |
| buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input. More... | |
| void | addSchedBarrierDeps () |
| addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More... | |
| virtual void | schedule ()=0 |
| schedule - Order nodes according to selected style, filling in the Sequence member. More... | |
| virtual void | finalizeSchedule () |
| finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More... | |
| void | dumpNode (const SUnit *SU) const override |
| std::string | getGraphNodeLabel (const SUnit *SU) const override |
| Return a label for a DAG node that points to an instruction. More... | |
| std::string | getDAGName () const override |
| Return a label for the region of code covered by the DAG. More... | |
| void | fixupKills (MachineBasicBlock *MBB) |
| Fix register kill flags that scheduling has made invalid. More... | |
Public Member Functions inherited from llvm::ScheduleDAG | |
| ScheduleDAG (MachineFunction &mf) | |
| virtual | ~ScheduleDAG () |
| void | clearDAG () |
| clearDAG - clear the DAG state (between regions). More... | |
| const MCInstrDesc * | getInstrDesc (const SUnit *SU) const |
| getInstrDesc - Return the MCInstrDesc of this SUnit. More... | |
| virtual void | viewGraph (const Twine &Name, const Twine &Title) |
| viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'. More... | |
| virtual void | viewGraph () |
| Out-of-line implementation with no arguments is handy for gdb. More... | |
| virtual void | addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const |
| addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG. More... | |
| unsigned | VerifyScheduledDAG (bool isBottomUp) |
| VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent. More... | |
Protected Types | |
| typedef std::vector< std::pair < MachineInstr *, MachineInstr * > > | DbgValueVector |
| DbgValues - Remember instruction that precedes DBG_VALUE. More... | |
Protected Member Functions | |
| void | reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N) |
| Remove in FIFO order some SUs from huge maps. More... | |
| void | addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0) |
| Add a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency. More... | |
| void | addChainDependencies (SUnit *SU, SUList &sus, unsigned Latency) |
| Add dependencies as needed from all SUs in list to SU. More... | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap) |
| Add dependencies as needed from all SUs in map, to SU. More... | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) |
| Add dependencies as needed to SU, from all SUs mapped to V. More... | |
| void | addBarrierChain (Value2SUsMap &map) |
| Add barrier chain edges from all SUs in map, and then clear the map. More... | |
| void | insertBarrierChain (Value2SUsMap &map) |
| Insert a barrier chain in a huge region, far below current SU. More... | |
| void | initSUnits () |
| Create an SUnit for each real instruction, numbered in top-down topological order. More... | |
| void | addPhysRegDataDeps (SUnit *SU, unsigned OperIdx) |
| MO is an operand of SU's instruction that defines a physical register. More... | |
| void | addPhysRegDeps (SUnit *SU, unsigned OperIdx) |
| addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More... | |
| void | addVRegDefDeps (SUnit *SU, unsigned OperIdx) |
| addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More... | |
| void | addVRegUseDeps (SUnit *SU, unsigned OperIdx) |
| addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More... | |
| void | startBlockForKills (MachineBasicBlock *BB) |
| PostRA helper for rewriting kill flags. More... | |
| bool | toggleKillFlag (MachineInstr *MI, MachineOperand &MO) |
| Toggle a register operand kill flag. More... | |
| LaneBitmask | getLaneMaskForMO (const MachineOperand &MO) const |
| Returns a mask for which lanes get read/written by the given (register) machine operand. More... | |
Protected Attributes | |
| const MachineLoopInfo * | MLI |
| const MachineFrameInfo & | MFI |
| TargetSchedModel | SchedModel |
| TargetSchedModel provides an interface to the machine model. More... | |
| bool | RemoveKillFlags |
| True if the DAG builder should remove kill flags (in preparation for rescheduling). More... | |
| bool | CanHandleTerminators |
| The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More... | |
| bool | TrackLaneMasks |
| Whether lane masks should get tracked. More... | |
| MachineBasicBlock * | BB |
| State specific to the current scheduling region. More... | |
| MachineBasicBlock::iterator | RegionBegin |
| The beginning of the range to be scheduled. More... | |
| MachineBasicBlock::iterator | RegionEnd |
| The end of the range to be scheduled. More... | |
| unsigned | NumRegionInstrs |
| Instructions in this region (distance(RegionBegin, RegionEnd)). More... | |
| DenseMap< MachineInstr *, SUnit * > | MISUnitMap |
| After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More... | |
| Reg2SUnitsMap | Defs |
| State internal to DAG building. More... | |
| Reg2SUnitsMap | Uses |
| VReg2SUnitMultiMap | CurrentVRegDefs |
| Tracks the last instruction(s) in this region defining each virtual register. More... | |
| VReg2SUnitOperIdxMultiMap | CurrentVRegUses |
| Tracks the last instructions in this region using each virtual register. More... | |
| AliasAnalysis * | AAForDep |
| SUnit * | BarrierChain |
| Remember a generic side-effecting instruction as we proceed. More... | |
| UndefValue * | UnknownValue |
| For an unanalyzable memory access, this Value is used in maps. More... | |
| DbgValueVector | DbgValues |
| MachineInstr * | FirstDbgValue |
| BitVector | LiveRegs |
| Set of live physical registers for updating kill flags. More... | |
Additional Inherited Members | |
Public Attributes inherited from llvm::ScheduleDAG | |
| const TargetMachine & | TM |
| const TargetInstrInfo * | TII |
| const TargetRegisterInfo * | TRI |
| MachineFunction & | MF |
| MachineRegisterInfo & | MRI |
| std::vector< SUnit > | SUnits |
| SUnit | EntrySU |
| SUnit | ExitSU |
| bool | StressSched |
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs.
Definition at line 100 of file ScheduleDAGInstrs.h.
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DbgValues - Remember instruction that precedes DBG_VALUE.
These are generated by buildSchedGraph but persist so they can be referenced when emitting the final schedule.
Definition at line 223 of file ScheduleDAGInstrs.h.
| typedef std::list<SUnit *> llvm::ScheduleDAGInstrs::SUList |
A list of SUnits, used in Value2SUsMap, during DAG construction.
Note: to gain speed it might be worth investigating an optimized implementation of this data structure, such as a singly linked list with a memory pool (SmallVector was tried but slow and SparseSet is not applicable).
Definition at line 172 of file ScheduleDAGInstrs.h.
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Definition at line 89 of file ScheduleDAGInstrs.cpp.
References DbgValues, llvm::MCSubtargetInfo::getSchedModel(), llvm::MachineFunction::getSubtarget(), llvm::TargetSchedModel::init(), SchedModel, llvm::ARM_MB::ST, and llvm::ScheduleDAG::TII.
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Definition at line 235 of file ScheduleDAGInstrs.h.
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Add barrier chain edges from all SUs in map, and then clear the map.
This is equivalent to insertBarrierChain(), but optimized for the common case where the new BarrierChain (a global memory object) has a higher NodeNum than all SUs in map. It is assumed BarrierChain has been set before calling this.
Definition at line 756 of file ScheduleDAGInstrs.cpp.
References assert(), BarrierChain, and I.
Referenced by buildSchedGraph().
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Add dependencies as needed from all SUs in list to SU.
Definition at line 189 of file ScheduleDAGInstrs.h.
References addChainDependency().
Referenced by addChainDependencies(), and buildSchedGraph().
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Add dependencies as needed from all SUs in map, to SU.
Definition at line 740 of file ScheduleDAGInstrs.cpp.
References addChainDependencies(), and I.
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Add dependencies as needed to SU, from all SUs mapped to V.
Definition at line 747 of file ScheduleDAGInstrs.cpp.
References addChainDependencies(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::end(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::find(), and llvm::ScheduleDAGInstrs::Value2SUsMap::getTrueMemOrderLatency().
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Add a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency.
Check whether two objects need a chain edge and add it if needed.
Definition at line 617 of file ScheduleDAGInstrs.cpp.
References AAForDep, llvm::SUnit::addPred(), llvm::MachineFunction::getDataLayout(), llvm::SUnit::getInstr(), llvm::SDep::MayAliasMem, llvm::ScheduleDAG::MF, MFI, MIsNeedChainEdge(), and llvm::SDep::setLatency().
Referenced by addChainDependencies().
MO is an operand of SU's instruction that defines a physical register.
Add data dependencies from SU to any uses of the physical register.
Definition at line 276 of file ScheduleDAGInstrs.cpp.
References llvm::SUnit::addPred(), llvm::SDep::Artificial, assert(), llvm::TargetSchedModel::computeOperandLatency(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), llvm::SDep::Data, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::SUnit::hasPhysRegDefs, I, llvm::MachineOperand::isDef(), llvm::MCRegAliasIterator::isValid(), llvm::ScheduleDAG::MF, SchedModel, llvm::SDep::setLatency(), llvm::ARM_MB::ST, llvm::ScheduleDAG::TRI, and Uses.
Referenced by addPhysRegDeps().
addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx.
Definition at line 319 of file ScheduleDAGInstrs.cpp.
References addPhysRegDataDeps(), llvm::SUnit::addPred(), llvm::SDep::Anti, B, llvm::TargetSchedModel::computeOutputLatency(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), Defs, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::equal_range(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::erase(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::eraseAll(), llvm::ScheduleDAG::ExitSU, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SUnit::hasPhysRegUses, I, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::SUnit::isCall, llvm::MachineRegisterInfo::isConstantPhysReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isUse(), llvm::MCRegAliasIterator::isValid(), Kind, MI, llvm::ScheduleDAG::MRI, llvm::SDep::Output, P, llvm::MachineInstr::registerDefIsDead(), RemoveKillFlags, SchedModel, llvm::MachineOperand::setIsKill(), llvm::SDep::setLatency(), llvm::ScheduleDAG::TRI, and Uses.
Referenced by buildSchedGraph().
| void ScheduleDAGInstrs::addSchedBarrierDeps | ( | ) |
addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier.
addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier by adding the exit SU to the register defs and use list.
We want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.
This is because we want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.
Definition at line 247 of file ScheduleDAGInstrs.cpp.
References addVRegUseDeps(), BB, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAG::ExitSU, llvm::MachineInstr::getOperandNo(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isCall(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineInstr::operands(), RegionEnd, llvm::SUnit::setInstr(), llvm::MachineBasicBlock::successors(), and Uses.
Referenced by buildSchedGraph().
addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx.
TODO: Hoist loop induction variable increments. This has to be reevaluated. Generally, IV scheduling should be done before coalescing.
Definition at line 415 of file ScheduleDAGInstrs.cpp.
References llvm::SUnit::addPred(), llvm::TargetSubtargetInfo::adjustSchedDependency(), llvm::LaneBitmask::any(), assert(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetSchedModel::computeOutputLatency(), CurrentVRegDefs, CurrentVRegUses, llvm::SDep::Data, E, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::erase(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::LaneBitmask::getAll(), llvm::SUnit::getInstr(), getLaneMaskForMO(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::hasOneDef(), I, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isUndef(), llvm::make_range(), llvm::ScheduleDAG::MF, MI, llvm::ScheduleDAG::MRI, llvm::SDep::Output, SchedModel, llvm::MachineOperand::setIsUndef(), llvm::SDep::setLatency(), llvm::ARM_MB::ST, and TrackLaneMasks.
Referenced by buildSchedGraph().
addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit.
Add a register antidependency from this SUnit to instructions that occur later in the same scheduling region if they write the virtual register.
TODO: Handle ExitSU "uses" properly.
Definition at line 524 of file ScheduleDAGInstrs.cpp.
References llvm::SDep::Anti, CurrentVRegDefs, CurrentVRegUses, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::LaneBitmask::getAll(), llvm::SUnit::getInstr(), getLaneMaskForMO(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::make_range(), MI, and TrackLaneMasks.
Referenced by addSchedBarrierDeps(), and buildSchedGraph().
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begin - Return an iterator to the top of the current scheduling region.
Definition at line 248 of file ScheduleDAGInstrs.h.
References RegionBegin.
Referenced by llvm::ScheduleDAGMI::dumpSchedule(), enterRegion(), llvm::VLIWMachineScheduler::schedule(), llvm::ScheduleDAGMI::schedule(), llvm::SIScheduleDAGMI::schedule(), and llvm::ScheduleDAGMILive::schedule().
| void ScheduleDAGInstrs::buildSchedGraph | ( | AliasAnalysis * | AA, |
| RegPressureTracker * | RPTracker = nullptr, |
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| PressureDiffs * | PDiffs = nullptr, |
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| LiveIntervals * | LIS = nullptr, |
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| bool | TrackLaneMasks = false |
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| ) |
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
If RegPressure is non-null, compute register pressure as a side effect.
The DAG builder is an efficient place to do it because it already visits operands.
Definition at line 803 of file ScheduleDAGInstrs.cpp.
References AAForDep, addBarrierChain(), addChainDependencies(), llvm::PressureDiffs::addInstruction(), addPhysRegDeps(), llvm::SUnit::addPred(), llvm::SUnit::addPredBarrier(), addSchedBarrierDeps(), addVRegDefDeps(), addVRegUseDeps(), llvm::RegisterOperands::adjustLaneLiveness(), llvm::SDep::Artificial, assert(), BarrierChain, CanHandleTerminators, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::clear(), llvm::ScheduleDAG::clearDAG(), llvm::RegisterOperands::collect(), CurrentVRegDefs, CurrentVRegUses, llvm::dbgs(), DbgValues, DEBUG, Defs, llvm::SmallVectorBase::empty(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::empty(), EnableAASchedMI, llvm::ScheduleDAG::ExitSU, FirstDbgValue, llvm::MachineFunction::getDataLayout(), llvm::LiveIntervals::getInstructionIndex(), llvm::MachineInstr::getNumOperands(), llvm::MCRegisterInfo::getNumRegs(), llvm::MachineRegisterInfo::getNumVirtRegs(), llvm::MachineInstr::getOperand(), llvm::RegPressureTracker::getPos(), getReductionSize(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), getUnderlyingObjectsForInstr(), HugeRegion, llvm::PressureDiffs::init(), initSUnits(), llvm::ScheduleDAGInstrs::Value2SUsMap::insert(), llvm::MachineInstr::isDebugValue(), llvm::MachineOperand::isDef(), llvm::MachineInstr::isDereferenceableInvariantLoad(), isGlobalMemoryObject(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineInstr::isPosition(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isTerminator(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::SUnit::Latency, llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), llvm::ScheduleDAG::MF, MFI, MI, MISUnitMap, llvm::ScheduleDAG::MRI, llvm::SUnit::NodeNum, llvm::SUnit::NumSuccs, llvm::MachineOperand::readsReg(), llvm::RegPressureTracker::recede(), llvm::RegPressureTracker::recedeSkipDebugValues(), reduceHugeMemNodeMaps(), RegionBegin, RegionEnd, llvm::SDep::setLatency(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::setUniverse(), llvm::ScheduleDAGInstrs::Value2SUsMap::size(), llvm::ARM_MB::ST, llvm::ScheduleDAG::SUnits, TrackLaneMasks, llvm::ScheduleDAG::TRI, UnknownValue, llvm::TargetSubtargetInfo::useAA(), and Uses.
Referenced by llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), llvm::DefaultVLIWScheduler::schedule(), and llvm::ScheduleDAGMI::schedule().
Implements llvm::ScheduleDAG.
Definition at line 1321 of file ScheduleDAGInstrs.cpp.
References llvm::MachineInstr::dump(), and llvm::SUnit::getInstr().
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end - Return an iterator to the bottom of the current scheduling region.
Definition at line 251 of file ScheduleDAGInstrs.h.
References RegionEnd.
Referenced by llvm::ScheduleDAGMI::dumpSchedule(), and enterRegion().
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Initialize the scheduler state for the next scheduling region.
Initialize the DAG and common scheduler state for the current scheduling region.
This does not actually create the DAG, only clears it. The scheduling driver may call BuildSchedGraph multiple times per scheduling region.
Reimplemented in llvm::ScheduleDAGMILive, and llvm::ScheduleDAGMI.
Definition at line 223 of file ScheduleDAGInstrs.cpp.
References assert(), BB, begin(), end(), NumRegionInstrs, RegionBegin, and RegionEnd.
Referenced by llvm::ScheduleDAGMI::enterRegion(), and llvm::VLIWPacketizerList::PacketizeMIs().
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Notify that the scheduler has finished scheduling the current region.
Close the current scheduling region.
Don't clear any state in case the driver wants to refer to the previous scheduling region.
Definition at line 235 of file ScheduleDAGInstrs.cpp.
Referenced by llvm::VLIWPacketizerList::PacketizeMIs().
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finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
By default does nothing.
Definition at line 300 of file ScheduleDAGInstrs.h.
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finishBlock - Clean up after scheduling in the given block.
Definition at line 214 of file ScheduleDAGInstrs.cpp.
References BB.
Referenced by llvm::VLIWPacketizerList::PacketizeMIs().
| void ScheduleDAGInstrs::fixupKills | ( | MachineBasicBlock * | MBB | ) |
Fix register kill flags that scheduling has made invalid.
Definition at line 1222 of file ScheduleDAGInstrs.cpp.
References llvm::MachineBasicBlock::begin(), llvm::dbgs(), DEBUG, llvm::MachineInstr::dump(), E, llvm::WebAssembly::End, llvm::MachineBasicBlock::end(), llvm::getBundleEnd(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getNumber(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getRegMask(), I, i, llvm::MachineInstr::isDebugValue(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineInstr::isRegTiedToUseOperand(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::MCRegisterInfo::DiffListIterator::isValid(), MI, MRI, llvm::MachineInstr::operands(), and llvm::MachineBasicBlock::size().
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Return a label for the region of code covered by the DAG.
Return the basic block label.
It is not necessarilly unique because a block contains multiple scheduling regions. But it is fine for visualization.
Implements llvm::ScheduleDAG.
Definition at line 1341 of file ScheduleDAGInstrs.cpp.
Return a label for a DAG node that points to an instruction.
Implements llvm::ScheduleDAG.
Definition at line 1327 of file ScheduleDAGInstrs.cpp.
References llvm::SUnit::getInstr(), llvm::MachineInstr::print(), and llvm::raw_string_ostream::str().
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Returns a mask for which lanes get read/written by the given (register) machine operand.
Definition at line 395 of file ScheduleDAGInstrs.cpp.
References llvm::LaneBitmask::getAll(), llvm::TargetRegisterClass::getLaneMask(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::TargetRegisterInfo::getSubRegIndexLaneMask(), llvm::TargetRegisterClass::HasDisjunctSubRegs, llvm::ScheduleDAG::MRI, SubReg, and llvm::ScheduleDAG::TRI.
Referenced by addVRegDefDeps(), and addVRegUseDeps().
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Resolve and cache a resolved scheduling class for an SUnit.
Definition at line 241 of file ScheduleDAGInstrs.h.
References llvm::SUnit::getInstr(), llvm::TargetSchedModel::hasInstrSchedModel(), llvm::TargetSchedModel::resolveSchedClass(), llvm::SUnit::SchedClass, and SchedModel.
Referenced by llvm::SchedBoundary::bumpNode(), llvm::SchedBoundary::checkHazard(), llvm::SystemZHazardRecognizer::dumpSU(), llvm::SystemZHazardRecognizer::EmitInstruction(), llvm::SystemZHazardRecognizer::groupingCost(), llvm::SchedRemainder::init(), llvm::GenericSchedulerBase::SchedCandidate::initResourceDelta(), initSUnits(), llvm::SystemZPostRASchedStrategy::releaseTopNode(), and llvm::SystemZHazardRecognizer::resourcesCost().
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Get the machine model for instruction scheduling.
Definition at line 238 of file ScheduleDAGInstrs.h.
References SchedModel.
Referenced by llvm::ConvergingVLIWScheduler::initialize(), llvm::PostGenericScheduler::initialize(), and llvm::SystemZHazardRecognizer::setDAG().
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getSUnit - Return an existing SUnit for this MI, or NULL.
Definition at line 345 of file ScheduleDAGInstrs.h.
References I, and MISUnitMap.
Referenced by llvm::ScheduleDAGMILive::computeCyclicCriticalPath(), and llvm::ScheduleDAGMI::dumpSchedule().
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Create an SUnit for each real instruction, numbered in top-down topological order.
The instruction order A < B, implies that no edge exists from B to A.
Map each real instruction to its SUnit.
After initSUnits, the SUnits vector cannot be resized and the scheduler may hang onto SUnit pointers. We may relax this in the future by using SUnit IDs instead of pointers.
MachineScheduler relies on initSUnits numbering the nodes by their order in the original instruction list.
Definition at line 638 of file ScheduleDAGInstrs.cpp.
References llvm::MCProcResourceDesc::BufferSize, llvm::SUnit::getInstr(), llvm::TargetSchedModel::getProcResource(), getSchedClass(), llvm::TargetSchedModel::getWriteProcResBegin(), llvm::TargetSchedModel::getWriteProcResEnd(), llvm::TargetSchedModel::hasInstrSchedModel(), llvm::SUnit::hasReservedResource, llvm::SUnit::isCall, llvm::SUnit::isCommutable, llvm::SUnit::isUnbuffered, llvm::SUnit::Latency, llvm::make_range(), MI, MISUnitMap, newSUnit(), NumRegionInstrs, RegionBegin, RegionEnd, llvm::PPCISD::SC, SchedModel, and llvm::ScheduleDAG::SUnits.
Referenced by buildSchedGraph().
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Insert a barrier chain in a huge region, far below current SU.
Add barrier chain edges from all SUs in map with higher NodeNums than this new BarrierChain, and remove them from map. It is assumed BarrierChain has been set before calling this.
Definition at line 767 of file ScheduleDAGInstrs.cpp.
References assert(), BarrierChain, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::begin(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::end(), I, llvm::SUnit::NodeNum, llvm::ScheduleDAGInstrs::Value2SUsMap::reComputeSize(), and llvm::MapVector< KeyT, ValueT, MapType, VectorType >::remove_if().
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newSUnit - Creates a new SUnit and return a ptr to it.
Definition at line 334 of file ScheduleDAGInstrs.h.
References assert(), and llvm::ScheduleDAG::SUnits.
Referenced by initSUnits().
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Remove in FIFO order some SUs from huge maps.
Reduce maps in FIFO order, by N SUs.
This is better than turning every Nth memory SU into BarrierChain in buildSchedGraph(), since it avoids unnecessary edges between seen SUs above the new BarrierChain, and those below it.
Definition at line 1095 of file ScheduleDAGInstrs.cpp.
References llvm::SUnit::addPredBarrier(), assert(), llvm::dbgs(), DEBUG, llvm::ScheduleDAGInstrs::Value2SUsMap::dump(), I, N, and llvm::ScheduleDAGInstrs::Value2SUsMap::size().
Referenced by buildSchedGraph().
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schedule - Order nodes according to selected style, filling in the Sequence member.
Typically, a scheduling algorithm will implement schedule() without overriding enterRegion() or exitRegion().
Implemented in llvm::ScheduleDAGMILive, llvm::SIScheduleDAGMI, llvm::ScheduleDAGMI, llvm::DefaultVLIWScheduler, and llvm::VLIWMachineScheduler.
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startBlock - Prepare to perform scheduling in the given block.
Definition at line 210 of file ScheduleDAGInstrs.cpp.
References BB.
Referenced by llvm::VLIWPacketizerList::PacketizeMIs().
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PostRA helper for rewriting kill flags.
Initialize register live-range state for updating kills.
Definition at line 1146 of file ScheduleDAGInstrs.cpp.
References llvm::MCRegisterInfo::DiffListIterator::isValid(), and llvm::MachineBasicBlock::successors().
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Toggle a register operand kill flag.
Other adjustments may be made to the instruction if necessary. Return true if the operand has been deleted, false if not.
Definition at line 1185 of file ScheduleDAGInstrs.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineOperand::getReg(), llvm::RegState::ImplicitDefine, llvm::MachineOperand::isKill(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::MachineOperand::setIsKill(), and toggleBundleKillFlag().
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Definition at line 158 of file ScheduleDAGInstrs.h.
Referenced by addChainDependency(), and buildSchedGraph().
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Remember a generic side-effecting instruction as we proceed.
No other SU ever gets scheduled around it (except in the special case of a huge region that gets reduced).
Definition at line 163 of file ScheduleDAGInstrs.h.
Referenced by addBarrierChain(), buildSchedGraph(), and insertBarrierChain().
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State specific to the current scheduling region.
The block in which to insert instructions
Definition at line 126 of file ScheduleDAGInstrs.h.
Referenced by addSchedBarrierDeps(), llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), llvm::ScheduleDAGMILive::computeCyclicCriticalPath(), enterRegion(), finishBlock(), llvm::SIScheduleDAGMI::getBB(), llvm::ScheduleDAGMILive::initRegPressure(), llvm::SIScheduleDAGMI::initRPTracker(), llvm::ScheduleDAGMI::moveInstruction(), llvm::ScheduleDAGMI::placeDebugValues(), llvm::VLIWMachineScheduler::schedule(), startBlock(), and llvm::ScheduleDAGMILive::updatePressureDiffs().
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The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering.
A specialized scheduler can override TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate it has taken responsibility for scheduling the terminator correctly.
Definition at line 117 of file ScheduleDAGInstrs.h.
Referenced by buildSchedGraph(), and llvm::DefaultVLIWScheduler::DefaultVLIWScheduler().
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Tracks the last instruction(s) in this region defining each virtual register.
There may be multiple current definitions for a register with disjunct lanemasks.
Definition at line 154 of file ScheduleDAGInstrs.h.
Referenced by addVRegDefDeps(), addVRegUseDeps(), and buildSchedGraph().
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Tracks the last instructions in this region using each virtual register.
Definition at line 156 of file ScheduleDAGInstrs.h.
Referenced by addVRegDefDeps(), addVRegUseDeps(), and buildSchedGraph().
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Definition at line 224 of file ScheduleDAGInstrs.h.
Referenced by buildSchedGraph(), llvm::ScheduleDAGMI::placeDebugValues(), and ScheduleDAGInstrs().
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State internal to DAG building.
Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. This is allocated here instead of inside BuildSchedGraph to avoid the need for it to be initialized and destructed for each block.
Definition at line 148 of file ScheduleDAGInstrs.h.
Referenced by addPhysRegDeps(), and buildSchedGraph().
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Definition at line 225 of file ScheduleDAGInstrs.h.
Referenced by buildSchedGraph(), and llvm::ScheduleDAGMI::placeDebugValues().
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Set of live physical registers for updating kill flags.
Definition at line 228 of file ScheduleDAGInstrs.h.
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Definition at line 103 of file ScheduleDAGInstrs.h.
Referenced by addChainDependency(), and buildSchedGraph().
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After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.
Definition at line 139 of file ScheduleDAGInstrs.h.
Referenced by buildSchedGraph(), getSUnit(), and initSUnits().
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Definition at line 102 of file ScheduleDAGInstrs.h.
Referenced by llvm::VLIWMachineScheduler::schedule().
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Instructions in this region (distance(RegionBegin, RegionEnd)).
Definition at line 135 of file ScheduleDAGInstrs.h.
Referenced by enterRegion(), and initSUnits().
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The beginning of the range to be scheduled.
Definition at line 129 of file ScheduleDAGInstrs.h.
Referenced by begin(), buildSchedGraph(), enterRegion(), llvm::ScheduleDAGMI::initQueues(), llvm::ScheduleDAGMILive::initQueues(), llvm::ScheduleDAGMILive::initRegPressure(), llvm::SIScheduleDAGMI::initRPTracker(), initSUnits(), llvm::ScheduleDAGMI::moveInstruction(), llvm::ScheduleDAGMI::placeDebugValues(), and llvm::SIScheduleDAGMI::schedule().
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The end of the range to be scheduled.
Definition at line 132 of file ScheduleDAGInstrs.h.
Referenced by addSchedBarrierDeps(), llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), buildSchedGraph(), end(), enterRegion(), llvm::ScheduleDAGMILive::enterRegion(), llvm::ScheduleDAGMI::initQueues(), llvm::ScheduleDAGMILive::initRegPressure(), initSUnits(), and llvm::ScheduleDAGMI::placeDebugValues().
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True if the DAG builder should remove kill flags (in preparation for rescheduling).
Definition at line 110 of file ScheduleDAGInstrs.h.
Referenced by addPhysRegDeps().
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TargetSchedModel provides an interface to the machine model.
Definition at line 106 of file ScheduleDAGInstrs.h.
Referenced by addPhysRegDataDeps(), addPhysRegDeps(), addVRegDefDeps(), getSchedClass(), getSchedModel(), initSUnits(), and ScheduleDAGInstrs().
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Whether lane masks should get tracked.
Definition at line 120 of file ScheduleDAGInstrs.h.
Referenced by addVRegDefDeps(), addVRegUseDeps(), buildSchedGraph(), and llvm::ScheduleDAGMILive::collectVRegUses().
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For an unanalyzable memory access, this Value is used in maps.
Definition at line 217 of file ScheduleDAGInstrs.h.
Referenced by buildSchedGraph().
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Definition at line 149 of file ScheduleDAGInstrs.h.
Referenced by addPhysRegDataDeps(), addPhysRegDeps(), addSchedBarrierDeps(), and buildSchedGraph().
1.8.6