14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
31 class InstructionSelector;
36 class SelectionDAGTargetInfo;
38 class TargetFrameLowering;
39 class TargetInstrInfo;
41 class TargetRegisterClass;
42 class TargetRegisterInfo;
43 class TargetSchedModel;
44 struct MachineSchedPolicy;
61 const unsigned *
OC,
const unsigned *FP);
171 unsigned NumRegionInstrs)
const {}
185 return CriticalPathRCs.
clear();
191 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
const {
197 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
const {
214 virtual bool useAA()
const;
234 #endif // LLVM_TARGET_TARGETSUBTARGETINFO_H
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
ScheduleDAGSDNodes *(* FunctionPassCtor)(SelectionDAGISel *, CodeGenOpt::Level)
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
TargetSubtargetInfo()=delete
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
virtual const CallLowering * getCallLowering() const
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
virtual AntiDepBreakMode getAntiDepBreakMode() const
Holds all the information related to register banks.
Provide an instruction scheduling machine model to CodeGen passes.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
Itinerary data supplied by a subtarget to be used by a target.
virtual bool isXRaySupported() const
virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual const InstructionSelector * getInstructionSelector() const
TargetInstrInfo - Interface to description of machine instruction set.
SDep - Scheduling dependency.
void operator=(const TargetSubtargetInfo &)=delete
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
virtual ~TargetSubtargetInfo()
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
Triple - Helper class for working with autoconf configuration names.
virtual const TargetFrameLowering * getFrameLowering() const
Specify the latency in cpu cycles for a particular scheduling class and def index.
virtual const TargetLowering * getTargetLowering() const
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
Information about stack frame layout on the target.
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accomodate up to NumRegBanks RegisterBank instances.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
TargetSubtargetInfo - Generic base class for all target subtargets.
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
These values represent a non-pipelined step in the execution of an instruction.
MCSubtargetInfo - Generic base class for all target subtargets.
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
virtual const TargetInstrInfo * getInstrInfo() const
virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual const LegalizerInfo * getLegalizerInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level) const
Target can subclass this hook to select a different DAG scheduler.
SmallVectorImpl< const TargetRegisterClass * > RegClassVector
SUnit - Scheduling unit. This is a node in the scheduling DAG.
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).