LLVM  4.0.0
MachineRegisterInfo.h
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1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the MachineRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
16 
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/PointerUnion.h"
21 // PointerUnion needs to have access to the full RegisterBank type.
28 #include <vector>
29 
30 namespace llvm {
32 
33 /// Convenient type to represent either a register class or a register bank.
36 
37 /// MachineRegisterInfo - Keep track of information for virtual and physical
38 /// registers, including vreg register classes, use/def chains for registers,
39 /// etc.
41 public:
42  class Delegate {
43  virtual void anchor();
44  public:
45  virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
46 
47  virtual ~Delegate() {}
48  };
49 
50 private:
51  MachineFunction *MF;
52  Delegate *TheDelegate;
53 
54  /// True if subregister liveness is tracked.
55  const bool TracksSubRegLiveness;
56 
57  /// VRegInfo - Information we keep for each virtual register.
58  ///
59  /// Each element in this list contains the register class of the vreg and the
60  /// start of the use/def list for the register.
63  VRegInfo;
64 
65  /// RegAllocHints - This vector records register allocation hints for virtual
66  /// registers. For each virtual register, it keeps a register and hint type
67  /// pair making up the allocation hint. Hint type is target specific except
68  /// for the value 0 which means the second value of the pair is the preferred
69  /// register for allocation. For example, if the hint is <0, 1024>, it means
70  /// the allocator should prefer the physical register allocated to the virtual
71  /// register of the hint.
73 
74  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
75  /// physical registers.
76  std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
77 
78  /// getRegUseDefListHead - Return the head pointer for the register use/def
79  /// list for the specified virtual or physical register.
80  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
82  return VRegInfo[RegNo].second;
83  return PhysRegUseDefLists[RegNo];
84  }
85 
86  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
88  return VRegInfo[RegNo].second;
89  return PhysRegUseDefLists[RegNo];
90  }
91 
92  /// Get the next element in the use-def chain.
93  static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
94  assert(MO && MO->isReg() && "This is not a register operand!");
95  return MO->Contents.Reg.Next;
96  }
97 
98  /// UsedPhysRegMask - Additional used physregs including aliases.
99  /// This bit vector represents all the registers clobbered by function calls.
100  BitVector UsedPhysRegMask;
101 
102  /// ReservedRegs - This is a bit vector of reserved registers. The target
103  /// may change its mind about which registers should be reserved. This
104  /// vector is the frozen set of reserved registers when register allocation
105  /// started.
106  BitVector ReservedRegs;
107 
108  typedef DenseMap<unsigned, LLT> VRegToTypeMap;
109  /// Map generic virtual registers to their actual size.
110  mutable std::unique_ptr<VRegToTypeMap> VRegToType;
111 
112  /// Keep track of the physical registers that are live in to the function.
113  /// Live in values are typically arguments in registers. LiveIn values are
114  /// allowed to have virtual registers associated with them, stored in the
115  /// second element.
116  std::vector<std::pair<unsigned, unsigned> > LiveIns;
117 
118  MachineRegisterInfo(const MachineRegisterInfo&) = delete;
119  void operator=(const MachineRegisterInfo&) = delete;
120 public:
121  explicit MachineRegisterInfo(MachineFunction *MF);
122 
124  return MF->getSubtarget().getRegisterInfo();
125  }
126 
127  void resetDelegate(Delegate *delegate) {
128  // Ensure another delegate does not take over unless the current
129  // delegate first unattaches itself. If we ever need to multicast
130  // notifications, we will need to change to using a list.
131  assert(TheDelegate == delegate &&
132  "Only the current delegate can perform reset!");
133  TheDelegate = nullptr;
134  }
135 
136  void setDelegate(Delegate *delegate) {
137  assert(delegate && !TheDelegate &&
138  "Attempted to set delegate to null, or to change it without "
139  "first resetting it!");
140 
141  TheDelegate = delegate;
142  }
143 
144  //===--------------------------------------------------------------------===//
145  // Function State
146  //===--------------------------------------------------------------------===//
147 
148  // isSSA - Returns true when the machine function is in SSA form. Early
149  // passes require the machine function to be in SSA form where every virtual
150  // register has a single defining instruction.
151  //
152  // The TwoAddressInstructionPass and PHIElimination passes take the machine
153  // function out of SSA form when they introduce multiple defs per virtual
154  // register.
155  bool isSSA() const {
156  return MF->getProperties().hasProperty(
158  }
159 
160  // leaveSSA - Indicates that the machine function is no longer in SSA form.
161  void leaveSSA() {
163  }
164 
165  /// tracksLiveness - Returns true when tracking register liveness accurately.
166  /// (see MachineFUnctionProperties::Property description for details)
167  bool tracksLiveness() const {
168  return MF->getProperties().hasProperty(
170  }
171 
172  /// invalidateLiveness - Indicates that register liveness is no longer being
173  /// tracked accurately.
174  ///
175  /// This should be called by late passes that invalidate the liveness
176  /// information.
178  MF->getProperties().reset(
180  }
181 
182  /// Returns true if liveness for register class @p RC should be tracked at
183  /// the subregister level.
186  }
187  bool shouldTrackSubRegLiveness(unsigned VReg) const {
188  assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
189  return shouldTrackSubRegLiveness(*getRegClass(VReg));
190  }
191  bool subRegLivenessEnabled() const {
192  return TracksSubRegLiveness;
193  }
194 
195  //===--------------------------------------------------------------------===//
196  // Register Info
197  //===--------------------------------------------------------------------===//
198 
199  // Strictly for use by MachineInstr.cpp.
201 
202  // Strictly for use by MachineInstr.cpp.
204 
205  // Strictly for use by MachineInstr.cpp.
206  void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
207 
208  /// Verify the sanity of the use list for Reg.
209  void verifyUseList(unsigned Reg) const;
210 
211  /// Verify the use list of all registers.
212  void verifyUseLists() const;
213 
214  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
215  /// and uses of a register within the MachineFunction that corresponds to this
216  /// MachineRegisterInfo object.
217  template<bool Uses, bool Defs, bool SkipDebug,
218  bool ByOperand, bool ByInstr, bool ByBundle>
220  template<bool Uses, bool Defs, bool SkipDebug,
221  bool ByOperand, bool ByInstr, bool ByBundle>
223 
224  // Make it a friend so it can access getNextOperandForReg().
225  template<bool, bool, bool, bool, bool, bool>
226  friend class defusechain_iterator;
227  template<bool, bool, bool, bool, bool, bool>
229 
230 
231 
232  /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
233  /// register.
236  reg_iterator reg_begin(unsigned RegNo) const {
237  return reg_iterator(getRegUseDefListHead(RegNo));
238  }
239  static reg_iterator reg_end() { return reg_iterator(nullptr); }
240 
242  return make_range(reg_begin(Reg), reg_end());
243  }
244 
245  /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
246  /// of the specified register, stepping by MachineInstr.
247  typedef defusechain_instr_iterator<true,true,false,false,true,false>
249  reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
250  return reg_instr_iterator(getRegUseDefListHead(RegNo));
251  }
253  return reg_instr_iterator(nullptr);
254  }
255 
257  reg_instructions(unsigned Reg) const {
258  return make_range(reg_instr_begin(Reg), reg_instr_end());
259  }
260 
261  /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
262  /// of the specified register, stepping by bundle.
263  typedef defusechain_instr_iterator<true,true,false,false,false,true>
265  reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
266  return reg_bundle_iterator(getRegUseDefListHead(RegNo));
267  }
269  return reg_bundle_iterator(nullptr);
270  }
271 
274  }
275 
276  /// reg_empty - Return true if there are no instructions using or defining the
277  /// specified register (it may be live-in).
278  bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
279 
280  /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
281  /// of the specified register, skipping those marked as Debug.
282  typedef defusechain_iterator<true,true,true,true,false,false>
284  reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
285  return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
286  }
288  return reg_nodbg_iterator(nullptr);
289  }
290 
292  reg_nodbg_operands(unsigned Reg) const {
293  return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
294  }
295 
296  /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
297  /// all defs and uses of the specified register, stepping by MachineInstr,
298  /// skipping those marked as Debug.
299  typedef defusechain_instr_iterator<true,true,true,false,true,false>
302  return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
303  }
305  return reg_instr_nodbg_iterator(nullptr);
306  }
307 
309  reg_nodbg_instructions(unsigned Reg) const {
311  }
312 
313  /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
314  /// all defs and uses of the specified register, stepping by bundle,
315  /// skipping those marked as Debug.
316  typedef defusechain_instr_iterator<true,true,true,false,false,true>
319  return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
320  }
322  return reg_bundle_nodbg_iterator(nullptr);
323  }
324 
326  reg_nodbg_bundles(unsigned Reg) const {
328  }
329 
330  /// reg_nodbg_empty - Return true if the only instructions using or defining
331  /// Reg are Debug instructions.
332  bool reg_nodbg_empty(unsigned RegNo) const {
333  return reg_nodbg_begin(RegNo) == reg_nodbg_end();
334  }
335 
336  /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
337  typedef defusechain_iterator<false,true,false,true,false,false>
339  def_iterator def_begin(unsigned RegNo) const {
340  return def_iterator(getRegUseDefListHead(RegNo));
341  }
342  static def_iterator def_end() { return def_iterator(nullptr); }
343 
345  return make_range(def_begin(Reg), def_end());
346  }
347 
348  /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
349  /// specified register, stepping by MachineInst.
350  typedef defusechain_instr_iterator<false,true,false,false,true,false>
352  def_instr_iterator def_instr_begin(unsigned RegNo) const {
353  return def_instr_iterator(getRegUseDefListHead(RegNo));
354  }
356  return def_instr_iterator(nullptr);
357  }
358 
360  def_instructions(unsigned Reg) const {
361  return make_range(def_instr_begin(Reg), def_instr_end());
362  }
363 
364  /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
365  /// specified register, stepping by bundle.
366  typedef defusechain_instr_iterator<false,true,false,false,false,true>
368  def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
369  return def_bundle_iterator(getRegUseDefListHead(RegNo));
370  }
372  return def_bundle_iterator(nullptr);
373  }
374 
377  }
378 
379  /// def_empty - Return true if there are no instructions defining the
380  /// specified register (it may be live-in).
381  bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
382 
383  /// Return true if there is exactly one operand defining the specified
384  /// register.
385  bool hasOneDef(unsigned RegNo) const {
386  def_iterator DI = def_begin(RegNo);
387  if (DI == def_end())
388  return false;
389  return ++DI == def_end();
390  }
391 
392  /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
393  typedef defusechain_iterator<true,false,false,true,false,false>
395  use_iterator use_begin(unsigned RegNo) const {
396  return use_iterator(getRegUseDefListHead(RegNo));
397  }
398  static use_iterator use_end() { return use_iterator(nullptr); }
399 
401  return make_range(use_begin(Reg), use_end());
402  }
403 
404  /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
405  /// specified register, stepping by MachineInstr.
406  typedef defusechain_instr_iterator<true,false,false,false,true,false>
408  use_instr_iterator use_instr_begin(unsigned RegNo) const {
409  return use_instr_iterator(getRegUseDefListHead(RegNo));
410  }
412  return use_instr_iterator(nullptr);
413  }
414 
416  use_instructions(unsigned Reg) const {
417  return make_range(use_instr_begin(Reg), use_instr_end());
418  }
419 
420  /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
421  /// specified register, stepping by bundle.
422  typedef defusechain_instr_iterator<true,false,false,false,false,true>
424  use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
425  return use_bundle_iterator(getRegUseDefListHead(RegNo));
426  }
428  return use_bundle_iterator(nullptr);
429  }
430 
433  }
434 
435  /// use_empty - Return true if there are no instructions using the specified
436  /// register.
437  bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
438 
439  /// hasOneUse - Return true if there is exactly one instruction using the
440  /// specified register.
441  bool hasOneUse(unsigned RegNo) const {
442  use_iterator UI = use_begin(RegNo);
443  if (UI == use_end())
444  return false;
445  return ++UI == use_end();
446  }
447 
448  /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
449  /// specified register, skipping those marked as Debug.
450  typedef defusechain_iterator<true,false,true,true,false,false>
452  use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
453  return use_nodbg_iterator(getRegUseDefListHead(RegNo));
454  }
456  return use_nodbg_iterator(nullptr);
457  }
458 
460  use_nodbg_operands(unsigned Reg) const {
461  return make_range(use_nodbg_begin(Reg), use_nodbg_end());
462  }
463 
464  /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
465  /// all uses of the specified register, stepping by MachineInstr, skipping
466  /// those marked as Debug.
467  typedef defusechain_instr_iterator<true,false,true,false,true,false>
470  return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
471  }
473  return use_instr_nodbg_iterator(nullptr);
474  }
475 
477  use_nodbg_instructions(unsigned Reg) const {
479  }
480 
481  /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
482  /// all uses of the specified register, stepping by bundle, skipping
483  /// those marked as Debug.
484  typedef defusechain_instr_iterator<true,false,true,false,false,true>
487  return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
488  }
490  return use_bundle_nodbg_iterator(nullptr);
491  }
492 
494  use_nodbg_bundles(unsigned Reg) const {
496  }
497 
498  /// use_nodbg_empty - Return true if there are no non-Debug instructions
499  /// using the specified register.
500  bool use_nodbg_empty(unsigned RegNo) const {
501  return use_nodbg_begin(RegNo) == use_nodbg_end();
502  }
503 
504  /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
505  /// instruction using the specified register.
506  bool hasOneNonDBGUse(unsigned RegNo) const;
507 
508  /// replaceRegWith - Replace all instances of FromReg with ToReg in the
509  /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
510  /// except that it also changes any definitions of the register as well.
511  ///
512  /// Note that it is usually necessary to first constrain ToReg's register
513  /// class to match the FromReg constraints using:
514  ///
515  /// constrainRegClass(ToReg, getRegClass(FromReg))
516  ///
517  /// That function will return NULL if the virtual registers have incompatible
518  /// constraints.
519  ///
520  /// Note that if ToReg is a physical register the function will replace and
521  /// apply sub registers to ToReg in order to obtain a final/proper physical
522  /// register.
523  void replaceRegWith(unsigned FromReg, unsigned ToReg);
524 
525  /// getVRegDef - Return the machine instr that defines the specified virtual
526  /// register or null if none is found. This assumes that the code is in SSA
527  /// form, so there should only be one definition.
528  MachineInstr *getVRegDef(unsigned Reg) const;
529 
530  /// getUniqueVRegDef - Return the unique machine instr that defines the
531  /// specified virtual register or null if none is found. If there are
532  /// multiple definitions or no definition, return null.
533  MachineInstr *getUniqueVRegDef(unsigned Reg) const;
534 
535  /// clearKillFlags - Iterate over all the uses of the given register and
536  /// clear the kill flag from the MachineOperand. This function is used by
537  /// optimization passes which extend register lifetimes and need only
538  /// preserve conservative kill flag information.
539  void clearKillFlags(unsigned Reg) const;
540 
541 #ifndef NDEBUG
542  void dumpUses(unsigned RegNo) const;
543 #endif
544 
545  /// Returns true if PhysReg is unallocatable and constant throughout the
546  /// function. Writing to a constant register has no effect.
547  bool isConstantPhysReg(unsigned PhysReg) const;
548 
549  /// Get an iterator over the pressure sets affected by the given physical or
550  /// virtual register. If RegUnit is physical, it must be a register unit (from
551  /// MCRegUnitIterator).
552  PSetIterator getPressureSets(unsigned RegUnit) const;
553 
554  //===--------------------------------------------------------------------===//
555  // Virtual Register Info
556  //===--------------------------------------------------------------------===//
557 
558  /// Return the register class of the specified virtual register.
559  /// This shouldn't be used directly unless \p Reg has a register class.
560  /// \see getRegClassOrNull when this might happen.
561  ///
562  const TargetRegisterClass *getRegClass(unsigned Reg) const {
563  assert(VRegInfo[Reg].first.is<const TargetRegisterClass *>() &&
564  "Register class not set, wrong accessor");
565  return VRegInfo[Reg].first.get<const TargetRegisterClass *>();
566  }
567 
568  /// Return the register class of \p Reg, or null if Reg has not been assigned
569  /// a register class yet.
570  ///
571  /// \note A null register class can only happen when these two
572  /// conditions are met:
573  /// 1. Generic virtual registers are created.
574  /// 2. The machine function has not completely been through the
575  /// instruction selection process.
576  /// None of this condition is possible without GlobalISel for now.
577  /// In other words, if GlobalISel is not used or if the query happens after
578  /// the select pass, using getRegClass is safe.
579  const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
580  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
581  return Val.dyn_cast<const TargetRegisterClass *>();
582  }
583 
584  /// Return the register bank of \p Reg, or null if Reg has not been assigned
585  /// a register bank or has been assigned a register class.
586  /// \note It is possible to get the register bank from the register class via
587  /// RegisterBankInfo::getRegBankFromRegClass.
588  ///
589  const RegisterBank *getRegBankOrNull(unsigned Reg) const {
590  const RegClassOrRegBank &Val = VRegInfo[Reg].first;
591  return Val.dyn_cast<const RegisterBank *>();
592  }
593 
594  /// Return the register bank or register class of \p Reg.
595  /// \note Before the register bank gets assigned (i.e., before the
596  /// RegBankSelect pass) \p Reg may not have either.
597  ///
598  const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
599  return VRegInfo[Reg].first;
600  }
601 
602  /// setRegClass - Set the register class of the specified virtual register.
603  ///
604  void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
605 
606  /// Set the register bank to \p RegBank for \p Reg.
607  ///
608  void setRegBank(unsigned Reg, const RegisterBank &RegBank);
609 
610  /// constrainRegClass - Constrain the register class of the specified virtual
611  /// register to be a common subclass of RC and the current register class,
612  /// but only if the new class has at least MinNumRegs registers. Return the
613  /// new register class, or NULL if no such class exists.
614  /// This should only be used when the constraint is known to be trivial, like
615  /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
616  ///
617  const TargetRegisterClass *constrainRegClass(unsigned Reg,
618  const TargetRegisterClass *RC,
619  unsigned MinNumRegs = 0);
620 
621  /// recomputeRegClass - Try to find a legal super-class of Reg's register
622  /// class that still satisfies the constraints from the instructions using
623  /// Reg. Returns true if Reg was upgraded.
624  ///
625  /// This method can be used after constraints have been removed from a
626  /// virtual register, for example after removing instructions or splitting
627  /// the live range.
628  ///
629  bool recomputeRegClass(unsigned Reg);
630 
631  /// createVirtualRegister - Create and return a new virtual register in the
632  /// function with the specified register class.
633  ///
634  unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
635 
636  /// Accessor for VRegToType. This accessor should only be used
637  /// by global-isel related work.
639  if (!VRegToType)
640  VRegToType.reset(new VRegToTypeMap);
641  return *VRegToType.get();
642  }
643 
644  /// Get the low-level type of \p VReg or LLT{} if VReg is not a generic
645  /// (target independent) virtual register.
646  LLT getType(unsigned VReg) const;
647 
648  /// Set the low-level type of \p VReg to \p Ty.
649  void setType(unsigned VReg, LLT Ty);
650 
651  /// Create and return a new generic virtual register with low-level
652  /// type \p Ty.
653  unsigned createGenericVirtualRegister(LLT Ty);
654 
655  /// Remove all types associated to virtual registers (after instruction
656  /// selection and constraining of all generic virtual registers).
657  void clearVirtRegTypes();
658 
659  /// Creates a new virtual register that has no register class, register bank
660  /// or size assigned yet. This is only allowed to be used
661  /// temporarily while constructing machine instructions. Most operations are
662  /// undefined on an incomplete register until one of setRegClass(),
663  /// setRegBank() or setSize() has been called on it.
665 
666  /// getNumVirtRegs - Return the number of virtual registers created.
667  ///
668  unsigned getNumVirtRegs() const { return VRegInfo.size(); }
669 
670  /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
671  void clearVirtRegs();
672 
673  /// setRegAllocationHint - Specify a register allocation hint for the
674  /// specified virtual register.
675  void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
677  RegAllocHints[VReg].first = Type;
678  RegAllocHints[VReg].second = PrefReg;
679  }
680 
681  /// Specify the preferred register allocation hint for the specified virtual
682  /// register.
683  void setSimpleHint(unsigned VReg, unsigned PrefReg) {
684  setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
685  }
686 
687  /// getRegAllocationHint - Return the register allocation hint for the
688  /// specified virtual register.
689  std::pair<unsigned, unsigned>
690  getRegAllocationHint(unsigned VReg) const {
692  return RegAllocHints[VReg];
693  }
694 
695  /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
696  /// standard simple hint (Type == 0) is not set.
697  unsigned getSimpleHint(unsigned VReg) const {
699  std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
700  return Hint.first ? 0 : Hint.second;
701  }
702 
703  /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
704  /// specified register as undefined which causes the DBG_VALUE to be
705  /// deleted during LiveDebugVariables analysis.
706  void markUsesInDebugValueAsUndef(unsigned Reg) const;
707 
708  /// Return true if the specified register is modified in this function.
709  /// This checks that no defining machine operands exist for the register or
710  /// any of its aliases. Definitions found on functions marked noreturn are
711  /// ignored, to consider them pass 'true' for optional parameter
712  /// SkipNoReturnDef. The register is also considered modified when it is set
713  /// in the UsedPhysRegMask.
714  bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
715 
716  /// Return true if the specified register is modified or read in this
717  /// function. This checks that no machine operands exist for the register or
718  /// any of its aliases. The register is also considered used when it is set
719  /// in the UsedPhysRegMask.
720  bool isPhysRegUsed(unsigned PhysReg) const;
721 
722  /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
723  /// This corresponds to the bit mask attached to register mask operands.
724  void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
725  UsedPhysRegMask.setBitsNotInMask(RegMask);
726  }
727 
728  const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
729 
730  void setUsedPhysRegMask(BitVector &Mask) { UsedPhysRegMask = Mask; }
731 
732  //===--------------------------------------------------------------------===//
733  // Reserved Register Info
734  //===--------------------------------------------------------------------===//
735  //
736  // The set of reserved registers must be invariant during register
737  // allocation. For example, the target cannot suddenly decide it needs a
738  // frame pointer when the register allocator has already used the frame
739  // pointer register for something else.
740  //
741  // These methods can be used by target hooks like hasFP() to avoid changing
742  // the reserved register set during register allocation.
743 
744  /// freezeReservedRegs - Called by the register allocator to freeze the set
745  /// of reserved registers before allocation begins.
746  void freezeReservedRegs(const MachineFunction&);
747 
748  /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
749  /// to ensure the set of reserved registers stays constant.
750  bool reservedRegsFrozen() const {
751  return !ReservedRegs.empty();
752  }
753 
754  /// canReserveReg - Returns true if PhysReg can be used as a reserved
755  /// register. Any register can be reserved before freezeReservedRegs() is
756  /// called.
757  bool canReserveReg(unsigned PhysReg) const {
758  return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
759  }
760 
761  /// getReservedRegs - Returns a reference to the frozen set of reserved
762  /// registers. This method should always be preferred to calling
763  /// TRI::getReservedRegs() when possible.
764  const BitVector &getReservedRegs() const {
766  "Reserved registers haven't been frozen yet. "
767  "Use TRI::getReservedRegs().");
768  return ReservedRegs;
769  }
770 
771  /// isReserved - Returns true when PhysReg is a reserved register.
772  ///
773  /// Reserved registers may belong to an allocatable register class, but the
774  /// target has explicitly requested that they are not used.
775  ///
776  bool isReserved(unsigned PhysReg) const {
777  return getReservedRegs().test(PhysReg);
778  }
779 
780  /// isAllocatable - Returns true when PhysReg belongs to an allocatable
781  /// register class and it hasn't been reserved.
782  ///
783  /// Allocatable registers may show up in the allocation order of some virtual
784  /// register, so a register allocator needs to track its liveness and
785  /// availability.
786  bool isAllocatable(unsigned PhysReg) const {
787  return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
788  !isReserved(PhysReg);
789  }
790 
791  //===--------------------------------------------------------------------===//
792  // LiveIn Management
793  //===--------------------------------------------------------------------===//
794 
795  /// addLiveIn - Add the specified register as a live-in. Note that it
796  /// is an error to add the same register to the same set more than once.
797  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
798  LiveIns.push_back(std::make_pair(Reg, vreg));
799  }
800 
801  // Iteration support for the live-ins set. It's kept in sorted order
802  // by register number.
803  typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
805  livein_iterator livein_begin() const { return LiveIns.begin(); }
806  livein_iterator livein_end() const { return LiveIns.end(); }
807  bool livein_empty() const { return LiveIns.empty(); }
808 
809  bool isLiveIn(unsigned Reg) const;
810 
811  /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
812  /// corresponding live-in physical register.
813  unsigned getLiveInPhysReg(unsigned VReg) const;
814 
815  /// getLiveInVirtReg - If PReg is a live-in physical register, return the
816  /// corresponding live-in physical register.
817  unsigned getLiveInVirtReg(unsigned PReg) const;
818 
819  /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
820  /// into the given entry block.
821  void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
822  const TargetRegisterInfo &TRI,
823  const TargetInstrInfo &TII);
824 
825  /// Returns a mask covering all bits that can appear in lane masks of
826  /// subregisters of the virtual register @p Reg.
827  LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
828 
829  /// defusechain_iterator - This class provides iterator support for machine
830  /// operands in the function that use or define a specific register. If
831  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
832  /// returns defs. If neither are true then you are silly and it always
833  /// returns end(). If SkipDebug is true it skips uses marked Debug
834  /// when incrementing.
835  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
836  bool ByOperand, bool ByInstr, bool ByBundle>
838  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
839  MachineOperand *Op;
840  explicit defusechain_iterator(MachineOperand *op) : Op(op) {
841  // If the first node isn't one we're interested in, advance to one that
842  // we are interested in.
843  if (op) {
844  if ((!ReturnUses && op->isUse()) ||
845  (!ReturnDefs && op->isDef()) ||
846  (SkipDebug && op->isDebug()))
847  advance();
848  }
849  }
850  friend class MachineRegisterInfo;
851 
852  void advance() {
853  assert(Op && "Cannot increment end iterator!");
854  Op = getNextOperandForReg(Op);
855 
856  // All defs come before the uses, so stop def_iterator early.
857  if (!ReturnUses) {
858  if (Op) {
859  if (Op->isUse())
860  Op = nullptr;
861  else
862  assert(!Op->isDebug() && "Can't have debug defs");
863  }
864  } else {
865  // If this is an operand we don't care about, skip it.
866  while (Op && ((!ReturnDefs && Op->isDef()) ||
867  (SkipDebug && Op->isDebug())))
868  Op = getNextOperandForReg(Op);
869  }
870  }
871  public:
872  typedef std::iterator<std::forward_iterator_tag,
874  typedef std::iterator<std::forward_iterator_tag,
876 
877  defusechain_iterator() : Op(nullptr) {}
878 
879  bool operator==(const defusechain_iterator &x) const {
880  return Op == x.Op;
881  }
882  bool operator!=(const defusechain_iterator &x) const {
883  return !operator==(x);
884  }
885 
886  /// atEnd - return true if this iterator is equal to reg_end() on the value.
887  bool atEnd() const { return Op == nullptr; }
888 
889  // Iterator traversal: forward iteration only
890  defusechain_iterator &operator++() { // Preincrement
891  assert(Op && "Cannot increment end iterator!");
892  if (ByOperand)
893  advance();
894  else if (ByInstr) {
895  MachineInstr *P = Op->getParent();
896  do {
897  advance();
898  } while (Op && Op->getParent() == P);
899  } else if (ByBundle) {
901  getBundleStart(Op->getParent()->getIterator());
902  do {
903  advance();
904  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
905  }
906 
907  return *this;
908  }
909  defusechain_iterator operator++(int) { // Postincrement
910  defusechain_iterator tmp = *this; ++*this; return tmp;
911  }
912 
913  /// getOperandNo - Return the operand # of this MachineOperand in its
914  /// MachineInstr.
915  unsigned getOperandNo() const {
916  assert(Op && "Cannot dereference end iterator!");
917  return Op - &Op->getParent()->getOperand(0);
918  }
919 
920  // Retrieve a reference to the current operand.
922  assert(Op && "Cannot dereference end iterator!");
923  return *Op;
924  }
925 
927  assert(Op && "Cannot dereference end iterator!");
928  return Op;
929  }
930  };
931 
932  /// defusechain_iterator - This class provides iterator support for machine
933  /// operands in the function that use or define a specific register. If
934  /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
935  /// returns defs. If neither are true then you are silly and it always
936  /// returns end(). If SkipDebug is true it skips uses marked Debug
937  /// when incrementing.
938  template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
939  bool ByOperand, bool ByInstr, bool ByBundle>
941  : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
942  MachineOperand *Op;
943  explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
944  // If the first node isn't one we're interested in, advance to one that
945  // we are interested in.
946  if (op) {
947  if ((!ReturnUses && op->isUse()) ||
948  (!ReturnDefs && op->isDef()) ||
949  (SkipDebug && op->isDebug()))
950  advance();
951  }
952  }
953  friend class MachineRegisterInfo;
954 
955  void advance() {
956  assert(Op && "Cannot increment end iterator!");
957  Op = getNextOperandForReg(Op);
958 
959  // All defs come before the uses, so stop def_iterator early.
960  if (!ReturnUses) {
961  if (Op) {
962  if (Op->isUse())
963  Op = nullptr;
964  else
965  assert(!Op->isDebug() && "Can't have debug defs");
966  }
967  } else {
968  // If this is an operand we don't care about, skip it.
969  while (Op && ((!ReturnDefs && Op->isDef()) ||
970  (SkipDebug && Op->isDebug())))
971  Op = getNextOperandForReg(Op);
972  }
973  }
974  public:
975  typedef std::iterator<std::forward_iterator_tag,
977  typedef std::iterator<std::forward_iterator_tag,
979 
981 
982  bool operator==(const defusechain_instr_iterator &x) const {
983  return Op == x.Op;
984  }
985  bool operator!=(const defusechain_instr_iterator &x) const {
986  return !operator==(x);
987  }
988 
989  /// atEnd - return true if this iterator is equal to reg_end() on the value.
990  bool atEnd() const { return Op == nullptr; }
991 
992  // Iterator traversal: forward iteration only
994  assert(Op && "Cannot increment end iterator!");
995  if (ByOperand)
996  advance();
997  else if (ByInstr) {
998  MachineInstr *P = Op->getParent();
999  do {
1000  advance();
1001  } while (Op && Op->getParent() == P);
1002  } else if (ByBundle) {
1004  getBundleStart(Op->getParent()->getIterator());
1005  do {
1006  advance();
1007  } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);
1008  }
1009 
1010  return *this;
1011  }
1012  defusechain_instr_iterator operator++(int) { // Postincrement
1013  defusechain_instr_iterator tmp = *this; ++*this; return tmp;
1014  }
1015 
1016  // Retrieve a reference to the current operand.
1018  assert(Op && "Cannot dereference end iterator!");
1019  if (ByBundle)
1020  return *getBundleStart(Op->getParent()->getIterator());
1021  return *Op->getParent();
1022  }
1023 
1024  MachineInstr *operator->() const { return &operator*(); }
1025  };
1026 };
1027 
1028 /// Iterate over the pressure sets affected by the given physical or virtual
1029 /// register. If Reg is physical, it must be a register unit (from
1030 /// MCRegUnitIterator).
1032  const int *PSet;
1033  unsigned Weight;
1034 public:
1035  PSetIterator(): PSet(nullptr), Weight(0) {}
1036  PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
1037  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1039  const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
1040  PSet = TRI->getRegClassPressureSets(RC);
1041  Weight = TRI->getRegClassWeight(RC).RegWeight;
1042  }
1043  else {
1044  PSet = TRI->getRegUnitPressureSets(RegUnit);
1045  Weight = TRI->getRegUnitWeight(RegUnit);
1046  }
1047  if (*PSet == -1)
1048  PSet = nullptr;
1049  }
1050  bool isValid() const { return PSet; }
1051 
1052  unsigned getWeight() const { return Weight; }
1053 
1054  unsigned operator*() const { return *PSet; }
1055 
1056  void operator++() {
1057  assert(isValid() && "Invalid PSetIterator.");
1058  ++PSet;
1059  if (*PSet == -1)
1060  PSet = nullptr;
1061  }
1062 };
1063 
1064 inline PSetIterator MachineRegisterInfo::
1065 getPressureSets(unsigned RegUnit) const {
1066  return PSetIterator(RegUnit, this);
1067 }
1068 
1069 } // End llvm namespace
1070 
1071 #endif
iterator_range< reg_bundle_iterator > reg_bundles(unsigned Reg) const
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register...
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
MachineFunctionProperties & reset(Property P)
livein_iterator livein_end() const
bool hasProperty(Property P) const
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
iterator_range< use_iterator > use_operands(unsigned Reg) const
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
Definition: PointerUnion.h:142
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const BitVector & getUsedPhysRegsMask() const
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(unsigned Reg) const
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
Definition: BitVector.h:495
bool shouldTrackSubRegLiveness(unsigned VReg) const
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
#define op(i)
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
static use_nodbg_iterator use_nodbg_end()
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static use_iterator use_end()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
use_instr_iterator use_instr_begin(unsigned RegNo) const
iterator_range< use_bundle_iterator > use_bundles(unsigned Reg) const
static void advance(T &it, size_t Val)
void setUsedPhysRegMask(BitVector &Mask)
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MachineFunctionProperties & getProperties() const
Get the function properties.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
def_bundle_iterator def_bundle_begin(unsigned RegNo) const
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
bool isLiveIn(unsigned Reg) const
static def_instr_iterator def_instr_end()
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register...
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI)
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register...
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register...
TargetInstrInfo - Interface to description of machine instruction set.
iterator_range< def_iterator > def_operands(unsigned Reg) const
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
#define P(N)
iterator_range< reg_instr_iterator > reg_instructions(unsigned Reg) const
unsigned const MachineRegisterInfo * MRI
bool operator!=(const defusechain_iterator &x) const
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
use_bundle_iterator use_bundle_begin(unsigned RegNo) const
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:116
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(unsigned Reg) const
iterator_range< def_bundle_iterator > def_bundles(unsigned Reg) const
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
unsigned createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet...
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register...
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
Iterator for intrusive lists based on ilist_node.
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool test(unsigned Idx) const
Definition: BitVector.h:323
static reg_bundle_iterator reg_bundle_end()
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
unsigned getWeight() const
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
livein_iterator livein_begin() const
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
This class implements the register bank concept.
Definition: RegisterBank.h:29
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
void resetDelegate(Delegate *delegate)
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
A range adaptor for a pair of iterators.
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
unsigned operator*() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
def_iterator def_begin(unsigned RegNo) const
bool operator==(const defusechain_instr_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool hasOneDef(unsigned RegNo) const
Return true if there is exactly one operand defining the specified register.
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register...
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
static use_bundle_iterator use_bundle_end()
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
def_instr_iterator def_instr_begin(unsigned RegNo) const
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
Iterate over the pressure sets affected by the given physical or virtual register.
use_iterator use_begin(unsigned RegNo) const
bool operator==(const defusechain_iterator &x) const
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void setSimpleHint(unsigned VReg, unsigned PrefReg)
Specify the preferred register allocation hint for the specified virtual register.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
static reg_nodbg_iterator reg_nodbg_end()
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
static use_instr_nodbg_iterator use_instr_nodbg_end()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void dumpUses(unsigned RegNo) const
static def_iterator def_end()
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
bool isDebug() const
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
void setDelegate(Delegate *delegate)
reg_iterator reg_begin(unsigned RegNo) const
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
void verifyUseLists() const
Verify the use list of all registers.
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const
static reg_iterator reg_end()
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool operator!=(const defusechain_instr_iterator &x) const
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
static def_bundle_iterator def_bundle_end()
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
Definition: PointerUnion.h:87
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.