LLVM  4.0.0
Thumb1FrameLowering.cpp
Go to the documentation of this file.
1 //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb1 implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Thumb1FrameLowering.h"
15 #include "ARMMachineFunctionInfo.h"
22 
23 using namespace llvm;
24 
26  : ARMFrameLowering(sti) {}
27 
29  const MachineFrameInfo &MFI = MF.getFrameInfo();
30  unsigned CFSize = MFI.getMaxCallFrameSize();
31  // It's not always a good idea to include the call frame as part of the
32  // stack frame. ARM (especially Thumb) has small immediate offset to
33  // address the stack frame. So a large call frame can cause poor codegen
34  // and may even makes it impossible to scavenge a register.
35  if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
36  return false;
37 
38  return !MFI.hasVarSizedObjects();
39 }
40 
43  const TargetInstrInfo &TII, const DebugLoc &dl,
44  const ThumbRegisterInfo &MRI, int NumBytes,
45  unsigned MIFlags = MachineInstr::NoFlags) {
46  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
47  MRI, MIFlags);
48 }
49 
50 
54  const Thumb1InstrInfo &TII =
55  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
56  const ThumbRegisterInfo *RegInfo =
57  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
58  if (!hasReservedCallFrame(MF)) {
59  // If we have alloca, convert as follows:
60  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
61  // ADJCALLSTACKUP -> add, sp, sp, amount
62  MachineInstr &Old = *I;
63  DebugLoc dl = Old.getDebugLoc();
64  unsigned Amount = Old.getOperand(0).getImm();
65  if (Amount != 0) {
66  // We need to keep the stack aligned properly. To do this, we round the
67  // amount of space needed for the outgoing arguments up to the next
68  // alignment boundary.
69  unsigned Align = getStackAlignment();
70  Amount = (Amount+Align-1)/Align*Align;
71 
72  // Replace the pseudo instruction with a new instruction...
73  unsigned Opc = Old.getOpcode();
74  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
75  emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
76  } else {
77  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
78  emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
79  }
80  }
81  }
82  return MBB.erase(I);
83 }
84 
86  MachineBasicBlock &MBB) const {
88  MachineFrameInfo &MFI = MF.getFrameInfo();
90  MachineModuleInfo &MMI = MF.getMMI();
91  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
92  const ThumbRegisterInfo *RegInfo =
93  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
94  const Thumb1InstrInfo &TII =
95  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
96 
97  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
98  unsigned NumBytes = MFI.getStackSize();
99  assert(NumBytes >= ArgRegsSaveSize &&
100  "ArgRegsSaveSize is included in NumBytes");
101  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
102 
103  // Debug location must be unknown since the first debug location is used
104  // to determine the end of the prologue.
105  DebugLoc dl;
106 
107  unsigned FramePtr = RegInfo->getFrameRegister(MF);
108  unsigned BasePtr = RegInfo->getBaseRegister();
109  int CFAOffset = 0;
110 
111  // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
112  NumBytes = (NumBytes + 3) & ~3;
113  MFI.setStackSize(NumBytes);
114 
115  // Determine the sizes of each callee-save spill areas and record which frame
116  // belongs to which callee-save spill areas.
117  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
118  int FramePtrSpillFI = 0;
119 
120  if (ArgRegsSaveSize) {
121  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
123  CFAOffset -= ArgRegsSaveSize;
124  unsigned CFIIndex = MF.addFrameInst(
125  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
126  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
127  .addCFIIndex(CFIIndex)
129  }
130 
131  if (!AFI->hasStackFrame()) {
132  if (NumBytes - ArgRegsSaveSize != 0) {
133  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
135  CFAOffset -= NumBytes - ArgRegsSaveSize;
136  unsigned CFIIndex = MF.addFrameInst(
137  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
138  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
139  .addCFIIndex(CFIIndex)
141  }
142  return;
143  }
144 
145  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
146  unsigned Reg = CSI[i].getReg();
147  int FI = CSI[i].getFrameIdx();
148  switch (Reg) {
149  case ARM::R8:
150  case ARM::R9:
151  case ARM::R10:
152  case ARM::R11:
153  if (STI.splitFramePushPop(MF)) {
154  GPRCS2Size += 4;
155  break;
156  }
158  case ARM::R4:
159  case ARM::R5:
160  case ARM::R6:
161  case ARM::R7:
162  case ARM::LR:
163  if (Reg == FramePtr)
164  FramePtrSpillFI = FI;
165  GPRCS1Size += 4;
166  break;
167  default:
168  DPRCSSize += 8;
169  }
170  }
171 
172  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
173  ++MBBI;
174  }
175 
176  // Determine starting offsets of spill areas.
177  unsigned DPRCSOffset = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
178  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
179  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
180  bool HasFP = hasFP(MF);
181  if (HasFP)
182  AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
183  NumBytes);
184  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
185  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
186  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
187  NumBytes = DPRCSOffset;
188 
189  int FramePtrOffsetInBlock = 0;
190  unsigned adjustedGPRCS1Size = GPRCS1Size;
191  if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
192  tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
193  FramePtrOffsetInBlock = NumBytes;
194  adjustedGPRCS1Size += NumBytes;
195  NumBytes = 0;
196  }
197 
198  if (adjustedGPRCS1Size) {
199  CFAOffset -= adjustedGPRCS1Size;
200  unsigned CFIIndex = MF.addFrameInst(
201  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
202  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
203  .addCFIIndex(CFIIndex)
205  }
206  for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
207  E = CSI.end(); I != E; ++I) {
208  unsigned Reg = I->getReg();
209  int FI = I->getFrameIdx();
210  switch (Reg) {
211  case ARM::R8:
212  case ARM::R9:
213  case ARM::R10:
214  case ARM::R11:
215  case ARM::R12:
216  if (STI.splitFramePushPop(MF))
217  break;
218  // fallthough
219  case ARM::R0:
220  case ARM::R1:
221  case ARM::R2:
222  case ARM::R3:
223  case ARM::R4:
224  case ARM::R5:
225  case ARM::R6:
226  case ARM::R7:
227  case ARM::LR:
228  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
229  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
230  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
231  .addCFIIndex(CFIIndex)
233  break;
234  }
235  }
236 
237  // Adjust FP so it point to the stack slot that contains the previous FP.
238  if (HasFP) {
239  FramePtrOffsetInBlock +=
240  MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
241  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
242  .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
244  if(FramePtrOffsetInBlock) {
245  CFAOffset += FramePtrOffsetInBlock;
246  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
247  nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
248  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
249  .addCFIIndex(CFIIndex)
251  } else {
252  unsigned CFIIndex =
254  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
255  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
256  .addCFIIndex(CFIIndex)
258  }
259  if (NumBytes > 508)
260  // If offset is > 508 then sp cannot be adjusted in a single instruction,
261  // try restoring from fp instead.
262  AFI->setShouldRestoreSPFromFP(true);
263  }
264 
265  // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
266  // and tMOVr instructions. We don't need to add any call frame information
267  // in-between these instructions, because they do not modify the high
268  // registers.
269  while (true) {
270  MachineBasicBlock::iterator OldMBBI = MBBI;
271  // Skip a run of tMOVr instructions
272  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
273  MBBI++;
274  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
275  MBBI++;
276  } else {
277  // We have reached an instruction which is not a push, so the previous
278  // run of tMOVr instructions (which may have been empty) was not part of
279  // the prologue. Reset MBBI back to the last PUSH of the prologue.
280  MBBI = OldMBBI;
281  break;
282  }
283  }
284 
285  // Emit call frame information for the callee-saved high registers.
286  for (auto &I : CSI) {
287  unsigned Reg = I.getReg();
288  int FI = I.getFrameIdx();
289  switch (Reg) {
290  case ARM::R8:
291  case ARM::R9:
292  case ARM::R10:
293  case ARM::R11:
294  case ARM::R12: {
295  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
296  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
297  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
298  .addCFIIndex(CFIIndex)
300  break;
301  }
302  default:
303  break;
304  }
305  }
306 
307  if (NumBytes) {
308  // Insert it after all the callee-save spills.
309  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
311  if (!HasFP) {
312  CFAOffset -= NumBytes;
313  unsigned CFIIndex = MF.addFrameInst(
314  MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
315  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
316  .addCFIIndex(CFIIndex)
318  }
319  }
320 
321  if (STI.isTargetELF() && HasFP)
323  AFI->getFramePtrSpillOffset());
324 
325  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
326  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
327  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
328 
329  // Thumb1 does not currently support dynamic stack realignment. Report a
330  // fatal error rather then silently generate bad code.
331  if (RegInfo->needsStackRealignment(MF))
332  report_fatal_error("Dynamic stack realignment not supported for thumb1.");
333 
334  // If we need a base pointer, set it up here. It's whatever the value
335  // of the stack pointer is at this point. Any variable size objects
336  // will be allocated after this, so we can still use the base pointer
337  // to reference locals.
338  if (RegInfo->hasBasePointer(MF))
339  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
340  .addReg(ARM::SP));
341 
342  // If the frame has variable sized objects then the epilogue must restore
343  // the sp from fp. We can assume there's an FP here since hasFP already
344  // checks for hasVarSizedObjects.
345  if (MFI.hasVarSizedObjects())
346  AFI->setShouldRestoreSPFromFP(true);
347 }
348 
349 static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
350  if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
351  isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
352  return true;
353  else if (MI.getOpcode() == ARM::tPOP) {
354  return true;
355  } else if (MI.getOpcode() == ARM::tMOVr) {
356  unsigned Dst = MI.getOperand(0).getReg();
357  unsigned Src = MI.getOperand(1).getReg();
358  return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
359  ARM::hGPRRegClass.contains(Dst));
360  }
361  return false;
362 }
363 
365  MachineBasicBlock &MBB) const {
367  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
368  MachineFrameInfo &MFI = MF.getFrameInfo();
370  const ThumbRegisterInfo *RegInfo =
371  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
372  const Thumb1InstrInfo &TII =
373  *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
374 
375  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
376  int NumBytes = (int)MFI.getStackSize();
377  assert((unsigned)NumBytes >= ArgRegsSaveSize &&
378  "ArgRegsSaveSize is included in NumBytes");
379  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
380  unsigned FramePtr = RegInfo->getFrameRegister(MF);
381 
382  if (!AFI->hasStackFrame()) {
383  if (NumBytes - ArgRegsSaveSize != 0)
384  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
385  } else {
386  // Unwind MBBI to point to first LDR / VLDRD.
387  if (MBBI != MBB.begin()) {
388  do
389  --MBBI;
390  while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
391  if (!isCSRestore(*MBBI, CSRegs))
392  ++MBBI;
393  }
394 
395  // Move SP to start of FP callee save spill area.
396  NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
399  ArgRegsSaveSize);
400 
401  if (AFI->shouldRestoreSPFromFP()) {
402  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
403  // Reset SP based on frame pointer only if the stack frame extends beyond
404  // frame pointer stack slot, the target is ELF and the function has FP, or
405  // the target uses var sized objects.
406  if (NumBytes) {
407  assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
408  "No scratch register to restore SP from FP!");
409  emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
410  TII, *RegInfo);
411  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
412  ARM::SP)
413  .addReg(ARM::R4));
414  } else
415  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
416  ARM::SP)
417  .addReg(FramePtr));
418  } else {
419  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
420  &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
421  MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
422  if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
423  emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
424  } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
425  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
426  }
427  }
428 
429  if (needPopSpecialFixUp(MF)) {
430  bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
431  (void)Done;
432  assert(Done && "Emission of the special fixup failed!?");
433  }
434 }
435 
437  if (!needPopSpecialFixUp(*MBB.getParent()))
438  return true;
439 
440  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
441  return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
442 }
443 
444 bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
445  ARMFunctionInfo *AFI =
446  const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
447  if (AFI->getArgRegsSaveSize())
448  return true;
449 
450  // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
451  for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
452  if (CSI.getReg() == ARM::LR)
453  return true;
454 
455  return false;
456 }
457 
458 bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
459  bool DoIt) const {
460  MachineFunction &MF = *MBB.getParent();
462  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
463  const TargetInstrInfo &TII = *STI.getInstrInfo();
464  const ThumbRegisterInfo *RegInfo =
465  static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
466 
467  // If MBBI is a return instruction, or is a tPOP followed by a return
468  // instruction in the successor BB, we may be able to directly restore
469  // LR in the PC.
470  // This is only possible with v5T ops (v4T can't change the Thumb bit via
471  // a POP PC instruction), and only if we do not need to emit any SP update.
472  // Otherwise, we need a temporary register to pop the value
473  // and copy that value into LR.
474  auto MBBI = MBB.getFirstTerminator();
475  bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
476  if (CanRestoreDirectly) {
477  if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
478  CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
479  MBBI->getOpcode() == ARM::tPOP_RET);
480  else {
481  auto MBBI_prev = MBBI;
482  MBBI_prev--;
483  assert(MBBI_prev->getOpcode() == ARM::tPOP);
484  assert(MBB.succ_size() == 1);
485  if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
486  MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
487  else
488  CanRestoreDirectly = false;
489  }
490  }
491 
492  if (CanRestoreDirectly) {
493  if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
494  return true;
495  MachineInstrBuilder MIB =
497  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET)));
498  // Copy implicit ops and popped registers, if any.
499  for (auto MO: MBBI->operands())
500  if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
501  MIB.addOperand(MO);
503  // Erase the old instruction (tBX_RET or tPOP).
504  MBB.erase(MBBI);
505  return true;
506  }
507 
508  // Look for a temporary register to use.
509  // First, compute the liveness information.
510  LivePhysRegs UsedRegs(STI.getRegisterInfo());
511  UsedRegs.addLiveOuts(MBB);
512  // The semantic of pristines changed recently and now,
513  // the callee-saved registers that are touched in the function
514  // are not part of the pristines set anymore.
515  // Add those callee-saved now.
516  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
517  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
518  for (unsigned i = 0; CSRegs[i]; ++i)
519  UsedRegs.addReg(CSRegs[i]);
520 
521  DebugLoc dl = DebugLoc();
522  if (MBBI != MBB.end()) {
523  dl = MBBI->getDebugLoc();
524  auto InstUpToMBBI = MBB.end();
525  while (InstUpToMBBI != MBBI)
526  // The pre-decrement is on purpose here.
527  // We want to have the liveness right before MBBI.
528  UsedRegs.stepBackward(*--InstUpToMBBI);
529  }
530 
531  // Look for a register that can be directly use in the POP.
532  unsigned PopReg = 0;
533  // And some temporary register, just in case.
534  unsigned TemporaryReg = 0;
535  BitVector PopFriendly =
536  TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID));
537  assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
538  // Rebuild the GPRs from the high registers because they are removed
539  // form the GPR reg class for thumb1.
540  BitVector GPRsNoLRSP =
541  TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID));
542  GPRsNoLRSP |= PopFriendly;
543  GPRsNoLRSP.reset(ARM::LR);
544  GPRsNoLRSP.reset(ARM::SP);
545  GPRsNoLRSP.reset(ARM::PC);
546  for (int Register = GPRsNoLRSP.find_first(); Register != -1;
547  Register = GPRsNoLRSP.find_next(Register)) {
548  if (!UsedRegs.contains(Register)) {
549  // Remember the first pop-friendly register and exit.
550  if (PopFriendly.test(Register)) {
551  PopReg = Register;
552  TemporaryReg = 0;
553  break;
554  }
555  // Otherwise, remember that the register will be available to
556  // save a pop-friendly register.
557  TemporaryReg = Register;
558  }
559  }
560 
561  if (!DoIt && !PopReg && !TemporaryReg)
562  return false;
563 
564  assert((PopReg || TemporaryReg) && "Cannot get LR");
565 
566  if (TemporaryReg) {
567  assert(!PopReg && "Unnecessary MOV is about to be inserted");
568  PopReg = PopFriendly.find_first();
569  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
570  .addReg(TemporaryReg, RegState::Define)
571  .addReg(PopReg, RegState::Kill));
572  }
573 
574  if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
575  // We couldn't use the direct restoration above, so
576  // perform the opposite conversion: tPOP_RET to tPOP.
577  MachineInstrBuilder MIB =
579  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP)));
580  bool Popped = false;
581  for (auto MO: MBBI->operands())
582  if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
583  MO.getReg() != ARM::PC) {
584  MIB.addOperand(MO);
585  if (!MO.isImplicit())
586  Popped = true;
587  }
588  // Is there anything left to pop?
589  if (!Popped)
590  MBB.erase(MIB.getInstr());
591  // Erase the old instruction.
592  MBB.erase(MBBI);
593  MBBI = AddDefaultPred(BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET)));
594  }
595 
596  assert(PopReg && "Do not know how to get LR");
597  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
598  .addReg(PopReg, RegState::Define);
599 
600  emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
601 
602  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
603  .addReg(ARM::LR, RegState::Define)
604  .addReg(PopReg, RegState::Kill));
605 
606  if (TemporaryReg)
607  AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
608  .addReg(PopReg, RegState::Define)
609  .addReg(TemporaryReg, RegState::Kill));
610 
611  return true;
612 }
613 
614 // Return the first iteraror after CurrentReg which is present in EnabledRegs,
615 // or OrderEnd if no further registers are in that set. This does not advance
616 // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
617 template <unsigned SetSize>
618 static const unsigned *
619 findNextOrderedReg(const unsigned *CurrentReg,
620  SmallSet<unsigned, SetSize> &EnabledRegs,
621  const unsigned *OrderEnd) {
622  while (CurrentReg != OrderEnd && !EnabledRegs.count(*CurrentReg))
623  ++CurrentReg;
624  return CurrentReg;
625 }
626 
630  const std::vector<CalleeSavedInfo> &CSI,
631  const TargetRegisterInfo *TRI) const {
632  if (CSI.empty())
633  return false;
634 
635  DebugLoc DL;
636  const TargetInstrInfo &TII = *STI.getInstrInfo();
637  MachineFunction &MF = *MBB.getParent();
638  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
640 
641  SmallSet<unsigned, 9> LoRegsToSave; // r0-r7, lr
642  SmallSet<unsigned, 4> HiRegsToSave; // r8-r11
643  SmallSet<unsigned, 9> CopyRegs; // Registers which can be used after pushing
644  // LoRegs for saving HiRegs.
645 
646  for (unsigned i = CSI.size(); i != 0; --i) {
647  unsigned Reg = CSI[i-1].getReg();
648 
649  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
650  LoRegsToSave.insert(Reg);
651  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
652  HiRegsToSave.insert(Reg);
653  } else {
654  llvm_unreachable("callee-saved register of unexpected class");
655  }
656 
657  if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
658  !MF.getRegInfo().isLiveIn(Reg) &&
659  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
660  CopyRegs.insert(Reg);
661  }
662 
663  // Unused argument registers can be used for the high register saving.
664  for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
665  if (!MF.getRegInfo().isLiveIn(ArgReg))
666  CopyRegs.insert(ArgReg);
667 
668  // Push the low registers and lr
669  if (!LoRegsToSave.empty()) {
670  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
671  AddDefaultPred(MIB);
672  for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
673  if (LoRegsToSave.count(Reg)) {
674  bool isKill = !MF.getRegInfo().isLiveIn(Reg);
675  if (isKill)
676  MBB.addLiveIn(Reg);
677 
678  MIB.addReg(Reg, getKillRegState(isKill));
679  }
680  }
682  }
683 
684  // Push the high registers. There are no store instructions that can access
685  // these registers directly, so we have to move them to low registers, and
686  // push them. This might take multiple pushes, as it is possible for there to
687  // be fewer low registers available than high registers which need saving.
688 
689  // These are in reverse order so that in the case where we need to use
690  // multiple PUSH instructions, the order of the registers on the stack still
691  // matches the unwind info. They need to be swicthed back to ascending order
692  // before adding to the PUSH instruction.
693  static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
694  ARM::R5, ARM::R4, ARM::R3,
695  ARM::R2, ARM::R1, ARM::R0};
696  static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
697 
698  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
699  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
700 
701  // Find the first register to save.
702  const unsigned *HiRegToSave = findNextOrderedReg(
703  std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
704 
705  while (HiRegToSave != AllHighRegsEnd) {
706  // Find the first low register to use.
707  const unsigned *CopyReg =
708  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
709 
710  // Create the PUSH, but don't insert it yet (the MOVs need to come first).
711  MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH));
712  AddDefaultPred(PushMIB);
713 
714  SmallVector<unsigned, 4> RegsToPush;
715  while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
716  if (HiRegsToSave.count(*HiRegToSave)) {
717  bool isKill = !MF.getRegInfo().isLiveIn(*HiRegToSave);
718  if (isKill)
719  MBB.addLiveIn(*HiRegToSave);
720 
721  // Emit a MOV from the high reg to the low reg.
722  MachineInstrBuilder MIB =
723  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr));
724  MIB.addReg(*CopyReg, RegState::Define);
725  MIB.addReg(*HiRegToSave, getKillRegState(isKill));
726  AddDefaultPred(MIB);
727 
728  // Record the register that must be added to the PUSH.
729  RegsToPush.push_back(*CopyReg);
730 
731  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
732  HiRegToSave =
733  findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
734  }
735  }
736 
737  // Add the low registers to the PUSH, in ascending order.
738  for (unsigned Reg : reverse(RegsToPush))
739  PushMIB.addReg(Reg, RegState::Kill);
740 
741  // Insert the PUSH instruction after the MOVs.
742  MBB.insert(MI, PushMIB);
743  }
744 
745  return true;
746 }
747 
751  const std::vector<CalleeSavedInfo> &CSI,
752  const TargetRegisterInfo *TRI) const {
753  if (CSI.empty())
754  return false;
755 
756  MachineFunction &MF = *MBB.getParent();
758  const TargetInstrInfo &TII = *STI.getInstrInfo();
759  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
761 
762  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
763  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
764 
765  SmallSet<unsigned, 9> LoRegsToRestore;
766  SmallSet<unsigned, 4> HiRegsToRestore;
767  // Low registers (r0-r7) which can be used to restore the high registers.
768  SmallSet<unsigned, 9> CopyRegs;
769 
770  for (CalleeSavedInfo I : CSI) {
771  unsigned Reg = I.getReg();
772 
773  if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
774  LoRegsToRestore.insert(Reg);
775  } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
776  HiRegsToRestore.insert(Reg);
777  } else {
778  llvm_unreachable("callee-saved register of unexpected class");
779  }
780 
781  // If this is a low register not used as the frame pointer, we may want to
782  // use it for restoring the high registers.
783  if ((ARM::tGPRRegClass.contains(Reg)) &&
784  !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
785  CopyRegs.insert(Reg);
786  }
787 
788  // If this is a return block, we may be able to use some unused return value
789  // registers for restoring the high regs.
790  auto Terminator = MBB.getFirstTerminator();
791  if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
792  CopyRegs.insert(ARM::R0);
793  CopyRegs.insert(ARM::R1);
794  CopyRegs.insert(ARM::R2);
795  CopyRegs.insert(ARM::R3);
796  for (auto Op : Terminator->implicit_operands()) {
797  if (Op.isReg())
798  CopyRegs.erase(Op.getReg());
799  }
800  }
801 
802  static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
803  ARM::R4, ARM::R5, ARM::R6, ARM::R7};
804  static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
805 
806  const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
807  const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
808 
809  // Find the first register to restore.
810  auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
811  HiRegsToRestore, AllHighRegsEnd);
812 
813  while (HiRegToRestore != AllHighRegsEnd) {
814  assert(!CopyRegs.empty());
815  // Find the first low register to use.
816  auto CopyReg =
817  findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
818 
819  // Create the POP instruction.
820  MachineInstrBuilder PopMIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPOP));
821  AddDefaultPred(PopMIB);
822 
823  while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
824  // Add the low register to the POP.
825  PopMIB.addReg(*CopyReg, RegState::Define);
826 
827  // Create the MOV from low to high register.
828  MachineInstrBuilder MIB =
829  BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr));
830  MIB.addReg(*HiRegToRestore, RegState::Define);
831  MIB.addReg(*CopyReg, RegState::Kill);
832  AddDefaultPred(MIB);
833 
834  CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
835  HiRegToRestore =
836  findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
837  }
838  }
839 
840 
841 
842 
843  MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
844  AddDefaultPred(MIB);
845 
846  bool NeedsPop = false;
847  for (unsigned i = CSI.size(); i != 0; --i) {
848  unsigned Reg = CSI[i-1].getReg();
849 
850  // High registers (excluding lr) have already been dealt with
851  if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
852  continue;
853 
854  if (Reg == ARM::LR) {
855  if (MBB.succ_empty()) {
856  // Special epilogue for vararg functions. See emitEpilogue
857  if (isVarArg)
858  continue;
859  // ARMv4T requires BX, see emitEpilogue
860  if (!STI.hasV5TOps())
861  continue;
862  Reg = ARM::PC;
863  (*MIB).setDesc(TII.get(ARM::tPOP_RET));
864  if (MI != MBB.end())
865  MIB.copyImplicitOps(*MI);
866  MI = MBB.erase(MI);
867  } else
868  // LR may only be popped into PC, as part of return sequence.
869  // If this isn't the return sequence, we'll need emitPopSpecialFixUp
870  // to restore LR the hard way.
871  continue;
872  }
873  MIB.addReg(Reg, getDefRegState(true));
874  NeedsPop = true;
875  }
876 
877  // It's illegal to emit pop instruction without operands.
878  if (NeedsPop)
879  MBB.insert(MI, &*MIB);
880  else
881  MF.DeleteMachineInstr(MIB);
882 
883  return true;
884 }
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
unsigned succ_size() const
void push_back(const T &Elt)
Definition: SmallVector.h:211
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:241
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:157
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
#define R4(n)
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
size_t i
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned getBaseRegister() const
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:396
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:233
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:130
A debug info location.
Definition: DebugLoc.h:34
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
#define R2(n)
void setGPRCalleeSavedArea2Offset(unsigned o)
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:383
bool erase(const T &V)
Definition: SmallSet.h:107
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
return AArch64::GPR64RegClass contains(Reg)
unsigned getDPRCalleeSavedAreaSize() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:376
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
LLVM_NODISCARD bool empty() const
Definition: SmallSet.h:55
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, const DebugLoc &dl, const ThumbRegisterInfo &MRI, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags)
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
const HexagonInstrInfo * TII
bool isTargetELF() const
Definition: ARMSubtarget.h:518
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Thumb1FrameLowering(const ARMSubtarget &sti)
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned getArgRegsSaveSize() const
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setDPRCalleeSavedAreaOffset(unsigned o)
static const unsigned * findNextOrderedReg(const unsigned *CurrentReg, SmallSet< unsigned, SetSize > &EnabledRegs, const unsigned *OrderEnd)
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void setFramePtrSpillOffset(unsigned o)
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:241
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool isLiveIn(unsigned Reg) const
int getOffsetAdjustment() const
Return the correction for frame offsets.
MachineBasicBlock * MBB
int64_t getImm() const
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:369
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:376
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void setStackSize(uint64_t Size)
Set the size of the stack.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:595
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
unsigned getFramePtrSpillOffset() const
BitVector & reset()
Definition: BitVector.h:260
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setGPRCalleeSavedArea2Size(unsigned s)
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:80
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:64
#define R6(n)
void setGPRCalleeSavedArea1Size(unsigned s)
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool test(unsigned Idx) const
Definition: BitVector.h:323
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs)
Promote Memory to Register
Definition: Mem2Reg.cpp:100
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
bool hasBasePointer(const MachineFunction &MF) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
Representation of each machine instruction.
Definition: MachineInstr.h:52
void setGPRCalleeSavedArea1Offset(unsigned o)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of live physical registers with functions to track liveness when walking backward/forward throu...
Definition: LivePhysRegs.h:45
bool hasV5TOps() const
Definition: ARMSubtarget.h:415
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
#define I(x, y, z)
Definition: MD5.cpp:54
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:385
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
void setDPRCalleeSavedAreaSize(unsigned s)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getGPRCalleeSavedArea1Size() const
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static const unsigned FramePtr
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineModuleInfo & getMMI() const
const ARMSubtarget & STI
unsigned getGPRCalleeSavedArea2Size() const
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
This class contains meta information specific to a module.
char * PC
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...