LLVM  4.0.0
RegisterClassInfo.cpp
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1 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee-saved vs. caller-saved and
12 // reserved registers depend on calling conventions and other dynamic
13 // information, so some things cannot be determined statically.
14 //
15 //===----------------------------------------------------------------------===//
16 
21 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 static cl::opt<unsigned>
29 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
30  cl::desc("Limit all regclasses to N registers"));
31 
33  : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
34 
36  bool Update = false;
37  MF = &mf;
38 
39  // Allocate new array the first time we see a new target.
40  if (MF->getSubtarget().getRegisterInfo() != TRI) {
41  TRI = MF->getSubtarget().getRegisterInfo();
42  RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
43  unsigned NumPSets = TRI->getNumRegPressureSets();
44  PSetLimits.reset(new unsigned[NumPSets]);
45  std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
46  Update = true;
47  }
48 
49  // Does this MF have different CSRs?
50  assert(TRI && "no register info set");
51  const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
52  if (Update || CSR != CalleeSaved) {
53  // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
54  // overlapping CSR.
55  CSRNum.clear();
56  CSRNum.resize(TRI->getNumRegs(), 0);
57  for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
58  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
59  CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
60  Update = true;
61  }
62  CalleeSaved = CSR;
63 
64  // Different reserved registers?
65  const BitVector &RR = MF->getRegInfo().getReservedRegs();
66  if (Reserved.size() != RR.size() || RR != Reserved) {
67  Update = true;
68  Reserved = RR;
69  }
70 
71  // Invalidate cached information from previous function.
72  if (Update)
73  ++Tag;
74 }
75 
76 /// compute - Compute the preferred allocation order for RC with reserved
77 /// registers filtered out. Volatile registers come first followed by CSR
78 /// aliases ordered according to the CSR order specified by the target.
79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80  assert(RC && "no register class given");
81  RCInfo &RCI = RegClass[RC->getID()];
82 
83  // Raw register count, including all reserved regs.
84  unsigned NumRegs = RC->getNumRegs();
85 
86  if (!RCI.Order)
87  RCI.Order.reset(new MCPhysReg[NumRegs]);
88 
89  unsigned N = 0;
91  unsigned MinCost = 0xff;
92  unsigned LastCost = ~0u;
93  unsigned LastCostChange = 0;
94 
95  // FIXME: Once targets reserve registers instead of removing them from the
96  // allocation order, we can simply use begin/end here.
97  ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
98  for (unsigned i = 0; i != RawOrder.size(); ++i) {
99  unsigned PhysReg = RawOrder[i];
100  // Remove reserved registers from the allocation order.
101  if (Reserved.test(PhysReg))
102  continue;
103  unsigned Cost = TRI->getCostPerUse(PhysReg);
104  MinCost = std::min(MinCost, Cost);
105 
106  if (CSRNum[PhysReg])
107  // PhysReg aliases a CSR, save it for later.
108  CSRAlias.push_back(PhysReg);
109  else {
110  if (Cost != LastCost)
111  LastCostChange = N;
112  RCI.Order[N++] = PhysReg;
113  LastCost = Cost;
114  }
115  }
116  RCI.NumRegs = N + CSRAlias.size();
117  assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
118 
119  // CSR aliases go after the volatile registers, preserve the target's order.
120  for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
121  unsigned PhysReg = CSRAlias[i];
122  unsigned Cost = TRI->getCostPerUse(PhysReg);
123  if (Cost != LastCost)
124  LastCostChange = N;
125  RCI.Order[N++] = PhysReg;
126  LastCost = Cost;
127  }
128 
129  // Register allocator stress test. Clip register class to N registers.
130  if (StressRA && RCI.NumRegs > StressRA)
131  RCI.NumRegs = StressRA;
132 
133  // Check if RC is a proper sub-class.
134  if (const TargetRegisterClass *Super =
135  TRI->getLargestLegalSuperClass(RC, *MF))
136  if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
137  RCI.ProperSubClass = true;
138 
139  RCI.MinCost = uint8_t(MinCost);
140  RCI.LastCostChange = LastCostChange;
141 
142  DEBUG({
143  dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
144  for (unsigned I = 0; I != RCI.NumRegs; ++I)
145  dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
146  dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
147  });
148 
149  // RCI is now up-to-date.
150  RCI.Tag = Tag;
151 }
152 
153 /// This is not accurate because two overlapping register sets may have some
154 /// nonoverlapping reserved registers. However, computing the allocation order
155 /// for all register classes would be too expensive.
156 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
157  const TargetRegisterClass *RC = nullptr;
158  unsigned NumRCUnits = 0;
160  RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) {
161  const int *PSetID = TRI->getRegClassPressureSets(*RI);
162  for (; *PSetID != -1; ++PSetID) {
163  if ((unsigned)*PSetID == Idx)
164  break;
165  }
166  if (*PSetID == -1)
167  continue;
168 
169  // Found a register class that counts against this pressure set.
170  // For efficiency, only compute the set order for the largest set.
171  unsigned NUnits = TRI->getRegClassWeight(*RI).WeightLimit;
172  if (!RC || NUnits > NumRCUnits) {
173  RC = *RI;
174  NumRCUnits = NUnits;
175  }
176  }
177  compute(RC);
178  unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
179  return TRI->getRegPressureSetLimit(*MF, Idx) -
180  TRI->getRegClassWeight(RC).RegWeight * NReserved;
181 }
void push_back(const T &Elt)
Definition: SmallVector.h:211
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:119
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
size_t i
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
regclass_iterator regclass_end() const
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned getNumRegClasses() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
regclass_iterator regclass_begin() const
Register class iterators.
unsigned getCostPerUse(unsigned RegNo) const
Return the additional cost of using this register instead of other registers in its class...
MCRegAliasIterator enumerates all registers aliasing Reg.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
bool test(unsigned Idx) const
Definition: BitVector.h:323
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getNumRegs() const
Return the number of registers in this class.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
static cl::opt< unsigned > StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), cl::desc("Limit all regclasses to N registers"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:100
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const TargetRegisterClass *const * regclass_iterator
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
void resize(size_type N)
Definition: SmallVector.h:352