LLVM  4.0.0
MipsLongBranch.cpp
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1 //===-- MipsLongBranch.cpp - Emit long branches ---------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass expands a branch or jump instruction into a long branch if its
11 // offset is too large to fit into its immediate field.
12 //
13 // FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
14 //===----------------------------------------------------------------------===//
15 
16 #include "Mips.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
24 #include "llvm/IR/Function.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "mips-long-branch"
34 
35 STATISTIC(LongBranches, "Number of long branches.");
36 
38  "skip-mips-long-branch",
39  cl::init(false),
40  cl::desc("MIPS: Skip long branch pass."),
41  cl::Hidden);
42 
44  "force-mips-long-branch",
45  cl::init(false),
46  cl::desc("MIPS: Expand all branches to long format."),
47  cl::Hidden);
48 
49 namespace {
50  typedef MachineBasicBlock::iterator Iter;
51  typedef MachineBasicBlock::reverse_iterator ReverseIter;
52 
53  struct MBBInfo {
54  uint64_t Size, Address;
55  bool HasLongBranch;
56  MachineInstr *Br;
57 
58  MBBInfo() : Size(0), HasLongBranch(false), Br(nullptr) {}
59  };
60 
61  class MipsLongBranch : public MachineFunctionPass {
62 
63  public:
64  static char ID;
65  MipsLongBranch(TargetMachine &tm)
66  : MachineFunctionPass(ID), TM(tm), IsPIC(TM.isPositionIndependent()),
67  ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
68 
69  StringRef getPassName() const override { return "Mips Long Branch"; }
70 
71  bool runOnMachineFunction(MachineFunction &F) override;
72 
73  MachineFunctionProperties getRequiredProperties() const override {
76  }
77 
78  private:
79  void splitMBB(MachineBasicBlock *MBB);
80  void initMBBInfo();
81  int64_t computeOffset(const MachineInstr *Br);
82  void replaceBranch(MachineBasicBlock &MBB, Iter Br, const DebugLoc &DL,
83  MachineBasicBlock *MBBOpnd);
84  void expandToLongBranch(MBBInfo &Info);
85 
86  const TargetMachine &TM;
87  MachineFunction *MF;
88  SmallVector<MBBInfo, 16> MBBInfos;
89  bool IsPIC;
90  MipsABIInfo ABI;
91  unsigned LongBranchSeqSize;
92  };
93 
94  char MipsLongBranch::ID = 0;
95 } // end of anonymous namespace
96 
97 /// createMipsLongBranchPass - Returns a pass that converts branches to long
98 /// branches.
100  return new MipsLongBranch(tm);
101 }
102 
103 /// Iterate over list of Br's operands and search for a MachineBasicBlock
104 /// operand.
106  for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
107  const MachineOperand &MO = Br.getOperand(I);
108 
109  if (MO.isMBB())
110  return MO.getMBB();
111  }
112 
113  llvm_unreachable("This instruction does not have an MBB operand.");
114 }
115 
116 // Traverse the list of instructions backwards until a non-debug instruction is
117 // found or it reaches E.
118 static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) {
119  for (; B != E; ++B)
120  if (!B->isDebugValue())
121  return B;
122 
123  return E;
124 }
125 
126 // Split MBB if it has two direct jumps/branches.
127 void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
128  ReverseIter End = MBB->rend();
129  ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
130 
131  // Return if MBB has no branch instructions.
132  if ((LastBr == End) ||
133  (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
134  return;
135 
136  ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End);
137 
138  // MBB has only one branch instruction if FirstBr is not a branch
139  // instruction.
140  if ((FirstBr == End) ||
141  (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
142  return;
143 
144  assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
145 
146  // Create a new MBB. Move instructions in MBB to the newly created MBB.
147  MachineBasicBlock *NewMBB =
148  MF->CreateMachineBasicBlock(MBB->getBasicBlock());
149 
150  // Insert NewMBB and fix control flow.
151  MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
152  NewMBB->transferSuccessors(MBB);
153  NewMBB->removeSuccessor(Tgt, true);
154  MBB->addSuccessor(NewMBB);
155  MBB->addSuccessor(Tgt);
156  MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
157 
158  NewMBB->splice(NewMBB->end(), MBB, LastBr.getReverse(), MBB->end());
159 }
160 
161 // Fill MBBInfos.
162 void MipsLongBranch::initMBBInfo() {
163  // Split the MBBs if they have two branches. Each basic block should have at
164  // most one branch after this loop is executed.
165  for (auto &MBB : *MF)
166  splitMBB(&MBB);
167 
168  MF->RenumberBlocks();
169  MBBInfos.clear();
170  MBBInfos.resize(MF->size());
171 
172  const MipsInstrInfo *TII =
173  static_cast<const MipsInstrInfo *>(MF->getSubtarget().getInstrInfo());
174  for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
175  MachineBasicBlock *MBB = MF->getBlockNumbered(I);
176 
177  // Compute size of MBB.
179  MI != MBB->instr_end(); ++MI)
180  MBBInfos[I].Size += TII->getInstSizeInBytes(*MI);
181 
182  // Search for MBB's branch instruction.
183  ReverseIter End = MBB->rend();
184  ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
185 
186  if ((Br != End) && !Br->isIndirectBranch() &&
187  (Br->isConditionalBranch() || (Br->isUnconditionalBranch() && IsPIC)))
188  MBBInfos[I].Br = &*Br;
189  }
190 }
191 
192 // Compute offset of branch in number of bytes.
193 int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
194  int64_t Offset = 0;
195  int ThisMBB = Br->getParent()->getNumber();
196  int TargetMBB = getTargetMBB(*Br)->getNumber();
197 
198  // Compute offset of a forward branch.
199  if (ThisMBB < TargetMBB) {
200  for (int N = ThisMBB + 1; N < TargetMBB; ++N)
201  Offset += MBBInfos[N].Size;
202 
203  return Offset + 4;
204  }
205 
206  // Compute offset of a backward branch.
207  for (int N = ThisMBB; N >= TargetMBB; --N)
208  Offset += MBBInfos[N].Size;
209 
210  return -Offset + 4;
211 }
212 
213 // Replace Br with a branch which has the opposite condition code and a
214 // MachineBasicBlock operand MBBOpnd.
215 void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
216  const DebugLoc &DL,
217  MachineBasicBlock *MBBOpnd) {
218  const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
219  MBB.getParent()->getSubtarget().getInstrInfo());
220  unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
221  const MCInstrDesc &NewDesc = TII->get(NewOpc);
222 
223  MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
224 
225  for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
226  MachineOperand &MO = Br->getOperand(I);
227 
228  if (!MO.isReg()) {
229  assert(MO.isMBB() && "MBB operand expected.");
230  break;
231  }
232 
233  MIB.addReg(MO.getReg());
234  }
235 
236  MIB.addMBB(MBBOpnd);
237 
238  if (Br->hasDelaySlot()) {
239  // Bundle the instruction in the delay slot to the newly created branch
240  // and erase the original branch.
241  assert(Br->isBundledWithSucc());
242  MachineBasicBlock::instr_iterator II = Br.getInstrIterator();
243  MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
244  }
245  Br->eraseFromParent();
246 }
247 
248 // Expand branch instructions to long branches.
249 // TODO: This function has to be fixed for beqz16 and bnez16, because it
250 // currently assumes that all branches have 16-bit offsets, and will produce
251 // wrong code if branches whose allowed offsets are [-128, -126, ..., 126]
252 // are present.
253 void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
255  MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
256  DebugLoc DL = I.Br->getDebugLoc();
257  const BasicBlock *BB = MBB->getBasicBlock();
259  MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
260  const MipsSubtarget &Subtarget =
261  static_cast<const MipsSubtarget &>(MF->getSubtarget());
262  const MipsInstrInfo *TII =
263  static_cast<const MipsInstrInfo *>(Subtarget.getInstrInfo());
264 
265  MF->insert(FallThroughMBB, LongBrMBB);
266  MBB->replaceSuccessor(TgtMBB, LongBrMBB);
267 
268  if (IsPIC) {
269  MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
270  MF->insert(FallThroughMBB, BalTgtMBB);
271  LongBrMBB->addSuccessor(BalTgtMBB);
272  BalTgtMBB->addSuccessor(TgtMBB);
273 
274  // We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal
275  // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
276  // pseudo-instruction wrapping BGEZAL).
277  unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
278 
279  if (!ABI.IsN64()) {
280  // $longbr:
281  // addiu $sp, $sp, -8
282  // sw $ra, 0($sp)
283  // lui $at, %hi($tgt - $baltgt)
284  // bal $baltgt
285  // addiu $at, $at, %lo($tgt - $baltgt)
286  // $baltgt:
287  // addu $at, $ra, $at
288  // lw $ra, 0($sp)
289  // jr $at
290  // addiu $sp, $sp, 8
291  // $fallthrough:
292  //
293 
294  Pos = LongBrMBB->begin();
295 
296  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
297  .addReg(Mips::SP).addImm(-8);
298  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
299  .addReg(Mips::SP).addImm(0);
300 
301  // LUi and ADDiu instructions create 32-bit offset of the target basic
302  // block from the target of BAL instruction. We cannot use immediate
303  // value for this offset because it cannot be determined accurately when
304  // the program has inline assembly statements. We therefore use the
305  // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
306  // are resolved during the fixup, so the values will always be correct.
307  //
308  // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
309  // expressions at this point (it is possible only at the MC layer),
310  // we replace LUi and ADDiu with pseudo instructions
311  // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
312  // blocks as operands to these instructions. When lowering these pseudo
313  // instructions to LUi and ADDiu in the MC layer, we will create
314  // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
315  // operands to lowered instructions.
316 
317  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
318  .addMBB(TgtMBB).addMBB(BalTgtMBB);
319  MIBundleBuilder(*LongBrMBB, Pos)
320  .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
321  .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
322  .addReg(Mips::AT)
323  .addMBB(TgtMBB)
324  .addMBB(BalTgtMBB));
325 
326  Pos = BalTgtMBB->begin();
327 
328  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
329  .addReg(Mips::RA).addReg(Mips::AT);
330  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
331  .addReg(Mips::SP).addImm(0);
332 
333  // In NaCl, modifying the sp is not allowed in branch delay slot.
334  if (Subtarget.isTargetNaCl())
335  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
336  .addReg(Mips::SP).addImm(8);
337 
338  if (Subtarget.hasMips32r6())
339  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR))
340  .addReg(Mips::ZERO).addReg(Mips::AT);
341  else
342  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
343 
344  if (Subtarget.isTargetNaCl()) {
345  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
346  // Bundle-align the target of indirect branch JR.
347  TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
348  } else
349  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
350  .addReg(Mips::SP).addImm(8);
351 
352  BalTgtMBB->rbegin()->bundleWithPred();
353  } else {
354  // $longbr:
355  // daddiu $sp, $sp, -16
356  // sd $ra, 0($sp)
357  // daddiu $at, $zero, %hi($tgt - $baltgt)
358  // dsll $at, $at, 16
359  // bal $baltgt
360  // daddiu $at, $at, %lo($tgt - $baltgt)
361  // $baltgt:
362  // daddu $at, $ra, $at
363  // ld $ra, 0($sp)
364  // jr64 $at
365  // daddiu $sp, $sp, 16
366  // $fallthrough:
367  //
368 
369  // We assume the branch is within-function, and that offset is within
370  // +/- 2GB. High 32 bits will therefore always be zero.
371 
372  // Note that this will work even if the offset is negative, because
373  // of the +1 modification that's added in that case. For example, if the
374  // offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is
375  //
376  // 0xFFFFFFFFFFF00000 + 0x80008000 = 0x000000007FF08000
377  //
378  // and the bits [47:32] are zero. For %highest
379  //
380  // 0xFFFFFFFFFFF00000 + 0x800080008000 = 0x000080007FF08000
381  //
382  // and the bits [63:48] are zero.
383 
384  Pos = LongBrMBB->begin();
385 
386  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
387  .addReg(Mips::SP_64).addImm(-16);
388  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
389  .addReg(Mips::SP_64).addImm(0);
390  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
391  Mips::AT_64).addReg(Mips::ZERO_64)
392  .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB);
393  BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
394  .addReg(Mips::AT_64).addImm(16);
395 
396  MIBundleBuilder(*LongBrMBB, Pos)
397  .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
398  .append(
399  BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
400  .addReg(Mips::AT_64)
401  .addMBB(TgtMBB, MipsII::MO_ABS_LO)
402  .addMBB(BalTgtMBB));
403 
404  Pos = BalTgtMBB->begin();
405 
406  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
407  .addReg(Mips::RA_64).addReg(Mips::AT_64);
408  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
409  .addReg(Mips::SP_64).addImm(0);
410 
411  if (Subtarget.hasMips64r6())
412  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR64))
413  .addReg(Mips::ZERO_64).addReg(Mips::AT_64);
414  else
415  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64);
416 
417  BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
418  .addReg(Mips::SP_64).addImm(16);
419  BalTgtMBB->rbegin()->bundleWithPred();
420  }
421 
422  assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
423  } else {
424  // $longbr:
425  // j $tgt
426  // nop
427  // $fallthrough:
428  //
429  Pos = LongBrMBB->begin();
430  LongBrMBB->addSuccessor(TgtMBB);
431  MIBundleBuilder(*LongBrMBB, Pos)
432  .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
433  .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
434 
435  assert(LongBrMBB->size() == LongBranchSeqSize);
436  }
437 
438  if (I.Br->isUnconditionalBranch()) {
439  // Change branch destination.
440  assert(I.Br->getDesc().getNumOperands() == 1);
441  I.Br->RemoveOperand(0);
442  I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
443  } else
444  // Change branch destination and reverse condition.
445  replaceBranch(*MBB, I.Br, DL, &*FallThroughMBB);
446 }
447 
448 static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
449  MachineBasicBlock &MBB = F.front();
451  DebugLoc DL = MBB.findDebugLoc(MBB.begin());
452  BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
453  .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
454  BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
455  .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
456  MBB.removeLiveIn(Mips::V0);
457 }
458 
459 bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
460  const MipsSubtarget &STI =
461  static_cast<const MipsSubtarget &>(F.getSubtarget());
462  const MipsInstrInfo *TII =
463  static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
464  LongBranchSeqSize =
465  !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
466 
467  if (STI.inMips16Mode() || !STI.enableLongBranchPass())
468  return false;
469  if (IsPIC && static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
470  F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
471  emitGPDisp(F, TII);
472 
473  if (SkipLongBranch)
474  return true;
475 
476  MF = &F;
477  initMBBInfo();
478 
479  SmallVectorImpl<MBBInfo>::iterator I, E = MBBInfos.end();
480  bool EverMadeChange = false, MadeChange = true;
481 
482  while (MadeChange) {
483  MadeChange = false;
484 
485  for (I = MBBInfos.begin(); I != E; ++I) {
486  // Skip if this MBB doesn't have a branch or the branch has already been
487  // converted to a long branch.
488  if (!I->Br || I->HasLongBranch)
489  continue;
490 
491  int ShVal = STI.inMicroMipsMode() ? 2 : 4;
492  int64_t Offset = computeOffset(I->Br) / ShVal;
493 
494  if (STI.isTargetNaCl()) {
495  // The offset calculation does not include sandboxing instructions
496  // that will be added later in the MC layer. Since at this point we
497  // don't know the exact amount of code that "sandboxing" will add, we
498  // conservatively estimate that code will not grow more than 100%.
499  Offset *= 2;
500  }
501 
502  // Check if offset fits into 16-bit immediate field of branches.
503  if (!ForceLongBranch && isInt<16>(Offset))
504  continue;
505 
506  I->HasLongBranch = true;
507  I->Size += LongBranchSeqSize * 4;
508  ++LongBranches;
509  EverMadeChange = MadeChange = true;
510  }
511  }
512 
513  if (!EverMadeChange)
514  return true;
515 
516  // Compute basic block addresses.
517  if (IsPIC) {
518  uint64_t Address = 0;
519 
520  for (I = MBBInfos.begin(); I != E; Address += I->Size, ++I)
521  I->Address = Address;
522  }
523 
524  // Do the expansion.
525  for (I = MBBInfos.begin(); I != E; ++I)
526  if (I->HasLongBranch)
527  expandToLongBranch(*I);
528 
529  MF->RenumberBlocks();
530 
531  return true;
532 }
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator instr_begin()
instr_iterator instr_end()
STATISTIC(NumFunctions,"Total number of functions")
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
const MipsInstrInfo * getInstrInfo() const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
A debug info location.
Definition: DebugLoc.h:34
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII)
void append(SmallVectorImpl< char > &path, const Twine &a, const Twine &b="", const Twine &c="", const Twine &d="")
Append to path.
Definition: Path.cpp:448
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
const MachineBasicBlock & front() const
#define F(x, y, z)
Definition: MD5.cpp:51
MachineBasicBlock * MBB
Function Alias Analysis false
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
reverse_iterator rend()
reverse_iterator rbegin()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
FunctionPass * createMipsLongBranchPass(MipsTargetMachine &TM)
createMipsLongBranchPass - Returns a pass that converts branches to long branches.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
static cl::opt< bool > SkipLongBranch("skip-mips-long-branch", cl::init(false), cl::desc("MIPS: Skip long branch pass."), cl::Hidden)
uint32_t Offset
static const unsigned End
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
bool inMicroMipsMode() const
bool inMips16Mode() const
bool hasMips32r6() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
Iterator for intrusive lists based on ilist_node.
bool isTargetNaCl() const
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool hasMips64r6() const
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
MachineFunctionProperties & set(Property P)
static const unsigned MIPS_NACL_BUNDLE_ALIGN
Definition: MipsMCNaCl.h:18
Representation of each machine instruction.
Definition: MachineInstr.h:52
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
static cl::opt< bool > ForceLongBranch("force-mips-long-branch", cl::init(false), cl::desc("MIPS: Expand all branches to long format."), cl::Hidden)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool enableLongBranchPass() const
unsigned getReg() const
getReg - Returns the register number.
MIBundleBuilder & append(MachineInstr *MI)
Insert MI into MBB by appending it to the instructions in the bundle.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
virtual const TargetInstrInfo * getInstrInfo() const
static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
BasicBlockListType::iterator iterator
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static MachineBasicBlock * getTargetMBB(const MachineInstr &Br)
Iterate over list of Br's operands and search for a MachineBasicBlock operand.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Properties which a MachineFunction may have at a given point in time.
Helper class for constructing bundles of MachineInstrs.