32 #define DEBUG_TYPE "mccodeemitter"
34 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
38 PPCMCCodeEmitter(
const PPCMCCodeEmitter &) =
delete;
39 void operator=(
const PPCMCCodeEmitter &) =
delete;
47 : MCII(mcii), CTX(ctx),
50 ~PPCMCCodeEmitter()
override {}
52 unsigned getDirectBrEncoding(
const MCInst &
MI,
unsigned OpNo,
55 unsigned getCondBrEncoding(
const MCInst &
MI,
unsigned OpNo,
58 unsigned getAbsDirectBrEncoding(
const MCInst &
MI,
unsigned OpNo,
61 unsigned getAbsCondBrEncoding(
const MCInst &
MI,
unsigned OpNo,
64 unsigned getImm16Encoding(
const MCInst &
MI,
unsigned OpNo,
67 unsigned getMemRIEncoding(
const MCInst &
MI,
unsigned OpNo,
70 unsigned getMemRIXEncoding(
const MCInst &
MI,
unsigned OpNo,
73 unsigned getMemRIX16Encoding(
const MCInst &
MI,
unsigned OpNo,
76 unsigned getSPE8DisEncoding(
const MCInst &
MI,
unsigned OpNo,
79 unsigned getSPE4DisEncoding(
const MCInst &
MI,
unsigned OpNo,
82 unsigned getSPE2DisEncoding(
const MCInst &
MI,
unsigned OpNo,
85 unsigned getTLSRegEncoding(
const MCInst &
MI,
unsigned OpNo,
88 unsigned getTLSCallEncoding(
const MCInst &
MI,
unsigned OpNo,
91 unsigned get_crbitm_encoding(
const MCInst &
MI,
unsigned OpNo,
103 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
109 verifyInstructionPredicates(MI,
115 uint64_t
Bits = getBinaryCodeForInstr(MI, Fixups, STI);
118 unsigned Size = Desc.
getSize();
123 if (IsLittleEndian) {
132 if (IsLittleEndian) {
133 uint64_t Swapped = (Bits << 32) | (Bits >> 32);
147 uint64_t computeAvailableFeatures(
const FeatureBitset &FB)
const;
148 void verifyInstructionPredicates(
const MCInst &MI,
149 uint64_t AvailableFeatures)
const;
157 return new PPCMCCodeEmitter(MCII, Ctx);
160 unsigned PPCMCCodeEmitter::
161 getDirectBrEncoding(
const MCInst &MI,
unsigned OpNo,
165 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
173 unsigned PPCMCCodeEmitter::getCondBrEncoding(
const MCInst &MI,
unsigned OpNo,
177 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
185 unsigned PPCMCCodeEmitter::
186 getAbsDirectBrEncoding(
const MCInst &MI,
unsigned OpNo,
190 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
198 unsigned PPCMCCodeEmitter::
199 getAbsCondBrEncoding(
const MCInst &MI,
unsigned OpNo,
203 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
211 unsigned PPCMCCodeEmitter::getImm16Encoding(
const MCInst &MI,
unsigned OpNo,
215 if (MO.
isReg() || MO.
isImm())
return getMachineOpValue(MI, MO, Fixups, STI);
223 unsigned PPCMCCodeEmitter::getMemRIEncoding(
const MCInst &MI,
unsigned OpNo,
229 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 16;
233 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits;
242 unsigned PPCMCCodeEmitter::getMemRIXEncoding(
const MCInst &MI,
unsigned OpNo,
248 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 14;
252 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits;
260 unsigned PPCMCCodeEmitter::getMemRIX16Encoding(
const MCInst &MI,
unsigned OpNo,
266 unsigned RegBits = getMachineOpValue(MI, MI.
getOperand(OpNo+1),
Fixups, STI) << 12;
271 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
274 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(
const MCInst &MI,
unsigned OpNo,
285 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
290 unsigned PPCMCCodeEmitter::getSPE4DisEncoding(
const MCInst &MI,
unsigned OpNo,
301 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2;
306 unsigned PPCMCCodeEmitter::getSPE2DisEncoding(
const MCInst &MI,
unsigned OpNo,
317 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1;
322 unsigned PPCMCCodeEmitter::getTLSRegEncoding(
const MCInst &MI,
unsigned OpNo,
326 if (MO.
isReg())
return getMachineOpValue(MI, MO, Fixups, STI);
335 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 :
PPC::R2);
338 unsigned PPCMCCodeEmitter::getTLSCallEncoding(
const MCInst &MI,
unsigned OpNo,
347 return getDirectBrEncoding(MI, OpNo, Fixups, STI);
350 unsigned PPCMCCodeEmitter::
351 get_crbitm_encoding(
const MCInst &MI,
unsigned OpNo,
358 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
361 unsigned PPCMCCodeEmitter::
372 unsigned Encode = CTX.getRegisterInfo()->getEncodingValue(Reg);
382 "Relocation required in an instruction that we cannot encode!");
388 #define ENABLE_INSTR_PREDICATE_VERIFIER
389 #include "PPCGenMCCodeEmitter.inc"
void push_back(const T &Elt)
STATISTIC(NumFunctions,"Total number of functions")
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
fixup_ppc_brcond14abs - 14-bit absolute relocation for conditional branches.
static bool isVRRegister(unsigned Reg)
fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or '...
fixup_ppc_br24abs - 24-bit absolute relocation for direct branches like 'ba' and 'bla'.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
fixup_ppc_nofixup - Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS gener...
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
MCCodeEmitter - Generic instruction encoding interface.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
fixup_ppc_half16ds - A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs l...
MCSubtargetInfo - Generic base class for all target subtargets.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
fixup_ppc_brcond14 - 14-bit PC relative relocation for conditional branches.
T reverseBits(T Val)
Reverse the bits in Val.
Instances of this class represent operands of the MCInst class.
MCCodeEmitter * createPPCMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const