LLVM  4.0.0
PPCISelLowering.h
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1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
17 
18 #include "PPC.h"
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
24 
25 namespace llvm {
26  namespace PPCISD {
27  enum NodeType : unsigned {
28  // Start the numbering where the builtin ops and target ops leave off.
30 
31  /// FSEL - Traditional three-operand fsel node.
32  ///
34 
35  /// FCFID - The FCFID instruction, taking an f64 operand and producing
36  /// and f64 value containing the FP representation of the integer that
37  /// was temporarily in the f64 operand.
39 
40  /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41  /// unsigned integers and single-precision outputs.
43 
44  /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45  /// operand, producing an f64 value containing the integer representation
46  /// of that FP value.
48 
49  /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50  /// unsigned integers with round toward zero.
52 
53  /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
54  /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
56 
57  /// Reciprocal estimate instructions (unary FP ops).
59 
60  // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
61  // three v4f32 operands and producing a v4f32 result.
63 
64  /// VPERM - The PPC VPERM Instruction.
65  ///
67 
68  /// XXSPLT - The PPC VSX splat instructions
69  ///
71 
72  /// XXINSERT - The PPC VSX insert instruction
73  ///
75 
76  /// VECSHL - The PPC VSX shift left instruction
77  ///
79 
80  /// The CMPB instruction (takes two operands of i32 or i64).
82 
83  /// Hi/Lo - These represent the high and low 16-bit parts of a global
84  /// address respectively. These nodes have two operands, the first of
85  /// which must be a TargetGlobalAddress, and the second of which must be a
86  /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
87  /// though these are usually folded into other nodes.
88  Hi, Lo,
89 
90  /// The following two target-specific nodes are used for calls through
91  /// function pointers in the 64-bit SVR4 ABI.
92 
93  /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
94  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
95  /// compute an allocation on the stack.
97 
98  /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
99  /// compute an offset from native SP to the address of the most recent
100  /// dynamic alloca.
102 
103  /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
104  /// at function entry, used for PIC code.
106 
107  /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
108  /// shift amounts. These nodes are generated by the multi-precision shift
109  /// code.
111 
112  /// The combination of sra[wd]i and addze used to implemented signed
113  /// integer division by a power of 2. The first operand is the dividend,
114  /// and the second is the constant shift amount (representing the
115  /// divisor).
117 
118  /// CALL - A direct function call.
119  /// CALL_NOP is a call with the special NOP which follows 64-bit
120  /// SVR4 calls.
122 
123  /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
124  /// MTCTR instruction.
126 
127  /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
128  /// BCTRL instruction.
130 
131  /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
132  /// instruction and the TOC reload required on SVR4 PPC64.
134 
135  /// Return with a flag operand, matched by 'blr'
137 
138  /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
139  /// This copies the bits corresponding to the specified CRREG into the
140  /// resultant GPR. Bits corresponding to other CR regs are undefined.
142 
143  /// Direct move from a VSX register to a GPR
145 
146  /// Direct move from a GPR to a VSX register (algebraic)
148 
149  /// Direct move from a GPR to a VSX register (zero)
151 
152  /// Extract a subvector from signed integer vector and convert to FP.
153  /// It is primarily used to convert a (widened) illegal integer vector
154  /// type to a legal floating point vector type.
155  /// For example v2i32 -> widened to v4i32 -> v2f64
157 
158  /// Extract a subvector from unsigned integer vector and convert to FP.
159  /// As with SINT_VEC_TO_FP, used for converting illegal types.
161 
162  // FIXME: Remove these once the ANDI glue bug is fixed:
163  /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
164  /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
165  /// implement truncation of i32 or i64 to i1.
167 
168  // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
169  // target (returns (Lo, Hi)). It takes a chain operand.
171 
172  // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
174 
175  // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
177 
178  /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
179  /// instructions. For lack of better number, we use the opcode number
180  /// encoding for the OPC field to identify the compare. For example, 838
181  /// is VCMPGTSH.
183 
184  /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
185  /// altivec VCMP*o instructions. For lack of better number, we use the
186  /// opcode number encoding for the OPC field to identify the compare. For
187  /// example, 838 is VCMPGTSH.
189 
190  /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
191  /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
192  /// condition register to branch on, OPC is the branch opcode to use (e.g.
193  /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
194  /// an optional input flag argument.
196 
197  /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
198  /// loops.
200 
201  /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
202  /// towards zero. Used only as part of the long double-to-int
203  /// conversion sequence.
205 
206  /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
208 
209  /// TC_RETURN - A tail call return.
210  /// operand #0 chain
211  /// operand #1 callee (register or absolute)
212  /// operand #2 stack adjustment
213  /// operand #3 optional in flag
215 
216  /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
219 
220  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
221  /// on PPC32.
223 
224  /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
225  /// local dynamic TLS on PPC32.
227 
228  /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
229  /// TLS model, produces an ADDIS8 instruction that adds the GOT
230  /// base to sym\@got\@tprel\@ha.
232 
233  /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
234  /// TLS model, produces a LD instruction with base register G8RReg
235  /// and offset sym\@got\@tprel\@l. This completes the addition that
236  /// finds the offset of "sym" relative to the thread pointer.
238 
239  /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
240  /// model, produces an ADD instruction that adds the contents of
241  /// G8RReg to the thread pointer. Symbol contains a relocation
242  /// sym\@tls which is to be replaced by the thread pointer and
243  /// identifies to the linker that the instruction is part of a
244  /// TLS sequence.
246 
247  /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
248  /// model, produces an ADDIS8 instruction that adds the GOT base
249  /// register to sym\@got\@tlsgd\@ha.
251 
252  /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
253  /// model, produces an ADDI8 instruction that adds G8RReg to
254  /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
255  /// ADDIS_TLSGD_L_ADDR until after register assignment.
257 
258  /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
259  /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
260  /// ADDIS_TLSGD_L_ADDR until after register assignment.
262 
263  /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
264  /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
265  /// register assignment.
267 
268  /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
269  /// model, produces an ADDIS8 instruction that adds the GOT base
270  /// register to sym\@got\@tlsld\@ha.
272 
273  /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
274  /// model, produces an ADDI8 instruction that adds G8RReg to
275  /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
276  /// ADDIS_TLSLD_L_ADDR until after register assignment.
278 
279  /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
280  /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
281  /// ADDIS_TLSLD_L_ADDR until after register assignment.
283 
284  /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
285  /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
286  /// following register assignment.
288 
289  /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
290  /// model, produces an ADDIS8 instruction that adds X3 to
291  /// sym\@dtprel\@ha.
293 
294  /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
295  /// model, produces an ADDI8 instruction that adds G8RReg to
296  /// sym\@got\@dtprel\@l.
298 
299  /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
300  /// during instruction selection to optimize a BUILD_VECTOR into
301  /// operations on splats. This is necessary to avoid losing these
302  /// optimizations due to constant folding.
304 
305  /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
306  /// operand identifies the operating system entry point.
307  SC,
308 
309  /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
311 
312  /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
313  /// history rolling buffer entry.
315 
316  /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
318 
319  /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
320  /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
321  /// or stxvd2x instruction. The chain is necessary because the
322  /// sequence replaces a load and needs to provide the same number
323  /// of outputs.
325 
326  /// An SDNode for swaps that are not associated with any loads/stores
327  /// and thereby have no chain.
329 
330  /// QVFPERM = This corresponds to the QPX qvfperm instruction.
332 
333  /// QVGPCI = This corresponds to the QPX qvgpci instruction.
335 
336  /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
338 
339  /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
341 
342  /// QBFLT = Access the underlying QPX floating-point boolean
343  /// representation.
345 
346  /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
347  /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
348  /// the GPRC input, then stores it through Ptr. Type can be either i16 or
349  /// i32.
351 
352  /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
353  /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
354  /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
355  /// or i32.
357 
358  /// STFIWX - The STFIWX instruction. The first operand is an input token
359  /// chain, then an f64 value to store, then an address to store it to.
361 
362  /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
363  /// load which sign-extends from a 32-bit integer value into the
364  /// destination 64-bit register.
366 
367  /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
368  /// load which zero-extends from a 32-bit integer value into the
369  /// destination 64-bit register.
371 
372  /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
373  /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
374  /// This can be used for converting loaded integers to floating point.
376 
377  /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
378  /// chain, then an f64 value to store, then an address to store it to,
379  /// followed by a byte-width for the store.
381 
382  /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
383  /// Maps directly to an lxvd2x instruction that will be followed by
384  /// an xxswapd.
386 
387  /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
388  /// Maps directly to an stxvd2x instruction that will be preceded by
389  /// an xxswapd.
391 
392  /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
393  /// The 4xf32 load used for v4i1 constants.
395 
396  /// GPRC = TOC_ENTRY GA, TOC
397  /// Loads the entry for GA from the TOC, where the TOC base is given by
398  /// the last operand.
400  };
401  }
402 
403  /// Define some predicates that are used for node matching.
404  namespace PPC {
405  /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
406  /// VPKUHUM instruction.
407  bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
408  SelectionDAG &DAG);
409 
410  /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
411  /// VPKUWUM instruction.
412  bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
413  SelectionDAG &DAG);
414 
415  /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
416  /// VPKUDUM instruction.
417  bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
418  SelectionDAG &DAG);
419 
420  /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
421  /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
422  bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
423  unsigned ShuffleKind, SelectionDAG &DAG);
424 
425  /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
426  /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
427  bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
428  unsigned ShuffleKind, SelectionDAG &DAG);
429 
430  /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
431  /// a VMRGEW or VMRGOW instruction
432  bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
433  unsigned ShuffleKind, SelectionDAG &DAG);
434 
435  /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
436  /// shift amount, otherwise return -1.
437  int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
438  SelectionDAG &DAG);
439 
440  /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
441  /// specifies a splat of a single element that is suitable for input to
442  /// VSPLTB/VSPLTH/VSPLTW.
443  bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
444 
445  /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
446  /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
447  /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
448  /// vector into the other. This function will also set a couple of
449  /// output parameters for how much the source vector needs to be shifted and
450  /// what byte number needs to be specified for the instruction to put the
451  /// element in the desired location of the target vector.
452  bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
453  unsigned &InsertAtByte, bool &Swap, bool IsLE);
454 
455  /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
456  /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
457  unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
458 
459  /// get_VSPLTI_elt - If this is a build_vector of constants which can be
460  /// formed by using a vspltis[bhw] instruction of the specified element
461  /// size, return the constant being splatted. The ByteSize field indicates
462  /// the number of bytes of each element [124] -> [bhw].
463  SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
464 
465  /// If this is a qvaligni shuffle mask, return the shift
466  /// amount, otherwise return -1.
467  int isQVALIGNIShuffleMask(SDNode *N);
468  }
469 
471  const PPCSubtarget &Subtarget;
472 
473  public:
474  explicit PPCTargetLowering(const PPCTargetMachine &TM,
475  const PPCSubtarget &STI);
476 
477  /// getTargetNodeName() - This method returns the name of a target specific
478  /// DAG node.
479  const char *getTargetNodeName(unsigned Opcode) const override;
480 
481  /// getPreferredVectorAction - The code we generate when vector types are
482  /// legalized by promoting the integer element type is often much worse
483  /// than code we generate if we widen the type for applicable vector types.
484  /// The issue with promoting is that the vector is scalaraized, individual
485  /// elements promoted and then the vector is rebuilt. So say we load a pair
486  /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
487  /// loads, moves back into VSR's (or memory ops if we don't have moves) and
488  /// then the VPERM for the shuffle. All in all a very slow sequence.
490  const override {
491  if (VT.getScalarSizeInBits() % 8 == 0)
492  return TypeWidenVector;
494  }
495  bool useSoftFloat() const override;
496 
497  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
498  return MVT::i32;
499  }
500 
501  bool isCheapToSpeculateCttz() const override {
502  return true;
503  }
504 
505  bool isCheapToSpeculateCtlz() const override {
506  return true;
507  }
508 
509  bool isCtlzFast() const override {
510  return true;
511  }
512 
513  bool hasAndNotCompare(SDValue) const override {
514  return true;
515  }
516 
517  bool supportSplitCSR(MachineFunction *MF) const override {
518  return
520  MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
521  }
522 
523  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
524 
526  MachineBasicBlock *Entry,
527  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
528 
529  /// getSetCCResultType - Return the ISD::SETCC ValueType
531  EVT VT) const override;
532 
533  /// Return true if target always beneficiates from combining into FMA for a
534  /// given value type. This must typically return false on targets where FMA
535  /// takes more cycles to execute than FADD.
536  bool enableAggressiveFMAFusion(EVT VT) const override;
537 
538  /// getPreIndexedAddressParts - returns true by value, base pointer and
539  /// offset pointer and addressing mode by reference if the node's address
540  /// can be legally represented as pre-indexed load / store address.
542  SDValue &Offset,
544  SelectionDAG &DAG) const override;
545 
546  /// SelectAddressRegReg - Given the specified addressed, check to see if it
547  /// can be represented as an indexed [r+r] operation. Returns false if it
548  /// can be more efficiently represented with [r+imm].
549  bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
550  SelectionDAG &DAG) const;
551 
552  /// SelectAddressRegImm - Returns true if the address N can be represented
553  /// by a base register plus a signed 16-bit displacement [r+imm], and if it
554  /// is not better represented as reg+reg. If Aligned is true, only accept
555  /// displacements suitable for STD and friends, i.e. multiples of 4.
556  bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
557  SelectionDAG &DAG, bool Aligned) const;
558 
559  /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
560  /// represented as an indexed [r+r] operation.
561  bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
562  SelectionDAG &DAG) const;
563 
565 
566  /// LowerOperation - Provide custom lowering hooks for some operations.
567  ///
568  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
569 
570  /// ReplaceNodeResults - Replace the results of node with an illegal result
571  /// type with new values built out of custom code.
572  ///
574  SelectionDAG &DAG) const override;
575 
576  SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
577  SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
578 
579  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
580 
581  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
582  std::vector<SDNode *> *Created) const override;
583 
584  unsigned getRegisterByName(const char* RegName, EVT VT,
585  SelectionDAG &DAG) const override;
586 
588  APInt &KnownZero,
589  APInt &KnownOne,
590  const SelectionDAG &DAG,
591  unsigned Depth = 0) const override;
592 
593  unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
594 
595  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
596  return true;
597  }
598 
600  bool IsStore, bool IsLoad) const override;
602  bool IsStore, bool IsLoad) const override;
603 
606  MachineBasicBlock *MBB) const override;
609  unsigned AtomicSize,
610  unsigned BinOpcode,
611  unsigned CmpOpcode = 0,
612  unsigned CmpPred = 0) const;
615  bool is8bit,
616  unsigned Opcode,
617  unsigned CmpOpcode = 0,
618  unsigned CmpPred = 0) const;
619 
621  MachineBasicBlock *MBB) const;
622 
624  MachineBasicBlock *MBB) const;
625 
626  ConstraintType getConstraintType(StringRef Constraint) const override;
627 
628  /// Examine constraint string and operand type and determine a weight value.
629  /// The operand object must already have been set up with the operand type.
631  AsmOperandInfo &info, const char *constraint) const override;
632 
633  std::pair<unsigned, const TargetRegisterClass *>
635  StringRef Constraint, MVT VT) const override;
636 
637  /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
638  /// function arguments in the caller parameter area. This is the actual
639  /// alignment, not its logarithm.
640  unsigned getByValTypeAlignment(Type *Ty,
641  const DataLayout &DL) const override;
642 
643  /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
644  /// vector. If it is invalid, don't add anything to Ops.
646  std::string &Constraint,
647  std::vector<SDValue> &Ops,
648  SelectionDAG &DAG) const override;
649 
650  unsigned
651  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
652  if (ConstraintCode == "es")
654  else if (ConstraintCode == "o")
656  else if (ConstraintCode == "Q")
658  else if (ConstraintCode == "Z")
660  else if (ConstraintCode == "Zy")
662  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
663  }
664 
665  /// isLegalAddressingMode - Return true if the addressing mode represented
666  /// by AM is legal for this target, for a load/store of the specified type.
667  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
668  Type *Ty, unsigned AS) const override;
669 
670  /// isLegalICmpImmediate - Return true if the specified immediate is legal
671  /// icmp immediate, that is the target has icmp instructions which can
672  /// compare a register against the immediate without having to materialize
673  /// the immediate into a register.
674  bool isLegalICmpImmediate(int64_t Imm) const override;
675 
676  /// isLegalAddImmediate - Return true if the specified immediate is legal
677  /// add immediate, that is the target has add instructions which can
678  /// add a register and the immediate without having to materialize
679  /// the immediate into a register.
680  bool isLegalAddImmediate(int64_t Imm) const override;
681 
682  /// isTruncateFree - Return true if it's free to truncate a value of
683  /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
684  /// register X1 to i32 by referencing its sub-register R1.
685  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
686  bool isTruncateFree(EVT VT1, EVT VT2) const override;
687 
688  bool isZExtFree(SDValue Val, EVT VT2) const override;
689 
690  bool isFPExtFree(EVT VT) const override;
691 
692  /// \brief Returns true if it is beneficial to convert a load of a constant
693  /// to just the constant itself.
695  Type *Ty) const override;
696 
697  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
698 
699  bool getTgtMemIntrinsic(IntrinsicInfo &Info,
700  const CallInst &I,
701  unsigned Intrinsic) const override;
702 
703  /// getOptimalMemOpType - Returns the target specific optimal type for load
704  /// and store operations as a result of memset, memcpy, and memmove
705  /// lowering. If DstAlign is zero that means it's safe to destination
706  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
707  /// means there isn't a need to check it against alignment requirement,
708  /// probably because the source does not need to be loaded. If 'IsMemset' is
709  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
710  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
711  /// source is constant so it does not need to be loaded.
712  /// It returns EVT::Other if the type should be determined using generic
713  /// target-independent logic.
714  EVT
715  getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
716  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
717  MachineFunction &MF) const override;
718 
719  /// Is unaligned memory access allowed for the given type, and is it fast
720  /// relative to software emulation.
722  unsigned AddrSpace,
723  unsigned Align = 1,
724  bool *Fast = nullptr) const override;
725 
726  /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
727  /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
728  /// expanded to FMAs when this method returns true, otherwise fmuladd is
729  /// expanded to fmul + fadd.
730  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
731 
732  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
733 
734  // Should we expand the build vector with shuffles?
735  bool
737  unsigned DefinedValues) const override;
738 
739  /// createFastISel - This method returns a target-specific FastISel object,
740  /// or null if the target does not support "fast" instruction selection.
742  const TargetLibraryInfo *LibInfo) const override;
743 
744  /// \brief Returns true if an argument of type Ty needs to be passed in a
745  /// contiguous block of registers in calling convention CallConv.
747  Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
748  // We support any array type as "consecutive" block in the parameter
749  // save area. The element type defines the alignment requirement and
750  // whether the argument should go in GPRs, FPRs, or VRs if available.
751  //
752  // Note that clang uses this capability both to implement the ELFv2
753  // homogeneous float/vector aggregate ABI, and to avoid having to use
754  // "byval" when passing aggregates that might fully fit in registers.
755  return Ty->isArrayTy();
756  }
757 
758  /// If a physical register, this returns the register that receives the
759  /// exception address on entry to an EH pad.
760  unsigned
761  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
762 
763  /// If a physical register, this returns the register that receives the
764  /// exception typeid on entry to a landing pad.
765  unsigned
766  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
767 
768  /// Override to support customized stack guard loading.
769  bool useLoadStackGuardNode() const override;
770  void insertSSPDeclarations(Module &M) const override;
771 
772  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
773 
774  unsigned getJumpTableEncoding() const override;
775  bool isJumpTableRelative() const override;
777  SelectionDAG &DAG) const override;
779  unsigned JTI,
780  MCContext &Ctx) const override;
781 
782  private:
783  struct ReuseLoadInfo {
784  SDValue Ptr;
785  SDValue Chain;
786  SDValue ResChain;
787  MachinePointerInfo MPI;
788  bool IsDereferenceable;
789  bool IsInvariant;
790  unsigned Alignment;
791  AAMDNodes AAInfo;
792  const MDNode *Ranges;
793 
794  ReuseLoadInfo()
795  : IsDereferenceable(false), IsInvariant(false), Alignment(0),
796  Ranges(nullptr) {}
797 
798  MachineMemOperand::Flags MMOFlags() const {
800  if (IsDereferenceable)
802  if (IsInvariant)
804  return F;
805  }
806  };
807 
808  bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
809  SelectionDAG &DAG,
811  void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
812  SelectionDAG &DAG) const;
813 
814  void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
815  SelectionDAG &DAG, const SDLoc &dl) const;
816  SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
817  const SDLoc &dl) const;
818 
819  bool directMoveIsProfitable(const SDValue &Op) const;
820  SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
821  const SDLoc &dl) const;
822 
823  SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
824  SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
825 
826  bool
827  IsEligibleForTailCallOptimization(SDValue Callee,
828  CallingConv::ID CalleeCC,
829  bool isVarArg,
830  const SmallVectorImpl<ISD::InputArg> &Ins,
831  SelectionDAG& DAG) const;
832 
833  bool
834  IsEligibleForTailCallOptimization_64SVR4(
835  SDValue Callee,
836  CallingConv::ID CalleeCC,
837  ImmutableCallSite *CS,
838  bool isVarArg,
839  const SmallVectorImpl<ISD::OutputArg> &Outs,
840  const SmallVectorImpl<ISD::InputArg> &Ins,
841  SelectionDAG& DAG) const;
842 
843  SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
844  SDValue Chain, SDValue &LROpOut,
845  SDValue &FPOpOut,
846  const SDLoc &dl) const;
847 
848  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
849  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
850  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
851  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
852  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
853  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
854  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
855  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
856  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
857  SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
858  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
859  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
860  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
861  SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
862  SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
863  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
864  SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
865  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
866  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
867  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
868  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
869  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
870  const SDLoc &dl) const;
871  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
872  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
873  SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
874  SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
875  SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
876  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
877  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
878  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
879  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
880  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
881  SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
882  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
883  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
884 
885  SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
886  SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
887 
888  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
889  CallingConv::ID CallConv, bool isVarArg,
890  const SmallVectorImpl<ISD::InputArg> &Ins,
891  const SDLoc &dl, SelectionDAG &DAG,
892  SmallVectorImpl<SDValue> &InVals) const;
893  SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
894  bool isTailCall, bool isVarArg, bool isPatchPoint,
895  bool hasNest, SelectionDAG &DAG,
896  SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
897  SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
898  SDValue &Callee, int SPDiff, unsigned NumBytes,
899  const SmallVectorImpl<ISD::InputArg> &Ins,
900  SmallVectorImpl<SDValue> &InVals,
901  ImmutableCallSite *CS) const;
902 
903  SDValue
904  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
905  const SmallVectorImpl<ISD::InputArg> &Ins,
906  const SDLoc &dl, SelectionDAG &DAG,
907  SmallVectorImpl<SDValue> &InVals) const override;
908 
909  SDValue
910  LowerCall(TargetLowering::CallLoweringInfo &CLI,
911  SmallVectorImpl<SDValue> &InVals) const override;
912 
913  bool
914  CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
915  bool isVarArg,
916  const SmallVectorImpl<ISD::OutputArg> &Outs,
917  LLVMContext &Context) const override;
918 
919  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
920  const SmallVectorImpl<ISD::OutputArg> &Outs,
921  const SmallVectorImpl<SDValue> &OutVals,
922  const SDLoc &dl, SelectionDAG &DAG) const override;
923 
924  SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
925  SelectionDAG &DAG, SDValue ArgVal,
926  const SDLoc &dl) const;
927 
928  SDValue LowerFormalArguments_Darwin(
929  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
930  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
931  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
932  SDValue LowerFormalArguments_64SVR4(
933  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
934  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
935  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
936  SDValue LowerFormalArguments_32SVR4(
937  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
938  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
939  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
940 
941  SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
942  SDValue CallSeqStart,
943  ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
944  const SDLoc &dl) const;
945 
946  SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
947  CallingConv::ID CallConv, bool isVarArg,
948  bool isTailCall, bool isPatchPoint,
949  const SmallVectorImpl<ISD::OutputArg> &Outs,
950  const SmallVectorImpl<SDValue> &OutVals,
951  const SmallVectorImpl<ISD::InputArg> &Ins,
952  const SDLoc &dl, SelectionDAG &DAG,
953  SmallVectorImpl<SDValue> &InVals,
954  ImmutableCallSite *CS) const;
955  SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
956  CallingConv::ID CallConv, bool isVarArg,
957  bool isTailCall, bool isPatchPoint,
958  const SmallVectorImpl<ISD::OutputArg> &Outs,
959  const SmallVectorImpl<SDValue> &OutVals,
960  const SmallVectorImpl<ISD::InputArg> &Ins,
961  const SDLoc &dl, SelectionDAG &DAG,
962  SmallVectorImpl<SDValue> &InVals,
963  ImmutableCallSite *CS) const;
964  SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
965  CallingConv::ID CallConv, bool isVarArg,
966  bool isTailCall, bool isPatchPoint,
967  const SmallVectorImpl<ISD::OutputArg> &Outs,
968  const SmallVectorImpl<SDValue> &OutVals,
969  const SmallVectorImpl<ISD::InputArg> &Ins,
970  const SDLoc &dl, SelectionDAG &DAG,
971  SmallVectorImpl<SDValue> &InVals,
972  ImmutableCallSite *CS) const;
973 
974  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
975  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
976 
977  SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
978  SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
979  SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
980  SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
981 
982  /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
983  /// SETCC with integer subtraction when (1) there is a legal way of doing it
984  /// (2) keeping the result of comparison in GPR has performance benefit.
985  SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
986 
987  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
988  int &RefinementSteps, bool &UseOneConstNR,
989  bool Reciprocal) const override;
990  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
991  int &RefinementSteps) const override;
992  unsigned combineRepeatedFPDivisors() const override;
993 
994  CCAssignFn *useFastISelCCs(unsigned Flag) const;
995 
996  SDValue
997  combineElementTruncationToVectorTruncation(SDNode *N,
998  DAGCombinerInfo &DCI) const;
999  };
1000 
1001  namespace PPC {
1002  FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1003  const TargetLibraryInfo *LibInfo);
1004  }
1005 
1006  bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1007  CCValAssign::LocInfo &LocInfo,
1008  ISD::ArgFlagsTy &ArgFlags,
1009  CCState &State);
1010 
1011  bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1012  MVT &LocVT,
1013  CCValAssign::LocInfo &LocInfo,
1014  ISD::ArgFlagsTy &ArgFlags,
1015  CCState &State);
1016 
1017  bool
1018  CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
1019  MVT &LocVT,
1020  CCValAssign::LocInfo &LocInfo,
1021  ISD::ArgFlagsTy &ArgFlags,
1022  CCState &State);
1023 
1024  bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1025  MVT &LocVT,
1026  CCValAssign::LocInfo &LocInfo,
1027  ISD::ArgFlagsTy &ArgFlags,
1028  CCState &State);
1029 }
1030 
1031 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
Return with a flag operand, matched by 'blr'.
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
LLVMContext & Context
QVFPERM = This corresponds to the QPX qvfperm instruction.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
GPRC = address of GLOBAL_OFFSET_TABLE.
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
This class represents a function call, abstracting a target machine's calling convention.
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
QBRC, CHAIN = QVLFSb CHAIN, Ptr The 4xf32 load used for v4i1 constants.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) !=...
Metadata node.
Definition: Metadata.h:830
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
CALL - A direct function call.
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align=1, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation...
bool isFPExtFree(EVT VT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
lazy value info
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
struct fuzzer::@269 Flags
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:588
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
The memory access is dereferenceable (i.e., doesn't trap).
Direct move from a GPR to a VSX register (algebraic)
X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
QVALIGNI = This corresponds to the QPX qvaligni instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
AtomicOrdering
Atomic ordering for LLVM's memory model.
unsigned getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Context object for machine code objects.
Definition: MCContext.h:51
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:31
#define F(x, y, z)
Definition: MD5.cpp:51
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
MachineBasicBlock * MBB
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
G8RC = ADDIS_TLSGD_HA X2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
Function Alias Analysis false
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a res...
bool isArrayTy() const
True if this is an instance of ArrayType.
Definition: Type.h:210
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
XXINSERT - The PPC VSX insert instruction.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:262
Instruction * emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
FSEL - Traditional three-operand fsel node.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
This is an important base class in LLVM.
Definition: Constant.h:42
G8RC = ADDIS_DTPREL_HA X3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
Direct move from a VSX register to a GPR.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:818
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask...
STFIWX - The STFIWX instruction.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target...
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
uint32_t Offset
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
G8RC = ADDIS_TLSLD_HA X2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
QVESPLATI = This corresponds to the QPX qvesplati instruction.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Common code between 32-bit and 64-bit PowerPC targets.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1...
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
EVT - Extended Value Type.
Definition: ValueTypes.h:31
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class contains a discriminated union of information about pointers in memory operands...
Instruction * emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
Extract a subvector from unsigned integer vector and convert to FP.
QBFLT = Access the underlying QPX floating-point boolean representation.
X3 = GET_TLSLD_ADDR X3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators...
bool isJumpTableRelative() const override
XXSPLT - The PPC VSX splat instructions.
bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
VECSHL - The PPC VSX shift left instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
Provides information about what library functions are available for the current target.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:625
CHAIN = SC CHAIN, Imm128 - System call.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node. ...
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
X3 = GET_TLS_ADDR X3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:769
Represents one node in the SelectionDAG.
VPERM - The PPC VPERM Instruction.
STXSIX - The STXSI[bh]X instruction.
i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after execu...
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
G8RC = ADDIS_GOT_TPREL_HA X2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
Class for arbitrary precision integers.
Definition: APInt.h:77
QVGPCI = This corresponds to the QPX qvgpci instruction.
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be represented as an inde...
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2...
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
Flags
Flags values. These may be or'd together.
GPRC = address of GLOBAL_OFFSET_TABLE.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Representation of each machine instruction.
Definition: MachineInstr.h:52
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry...
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
Reciprocal estimate instructions (unary FP ops).
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
Direct move from a GPR to a VSX register (zero)
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
The CMPB instruction (takes two operands of i32 or i64).
The memory access always returns the same value (or traps).
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction. ...
TC_RETURN - A tail call return.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, bool Aligned) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2...
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
These nodes represent the 32-bit PPC shifts that operate on 6-bit shift amounts.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
Extract a subvector from signed integer vector and convert to FP.
int * Ptr
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the altivec VCMP*o instructions.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:799
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
int isQVALIGNIShuffleMask(SDNode *N)
If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. ...
bool useSoftFloat() const override