LLVM  4.0.0
RegisterBankInfo.h
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1 //==-- llvm/CodeGen/GlobalISel/RegisterBankInfo.h ----------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file declares the API for the register bank info.
11 /// This API is responsible for handling the register banks.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
16 #define LLVM_CODEGEN_GLOBALISEL_REGBANKINFO_H
17 
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/ADT/Hashing.h"
21 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/MachineValueType.h" // For SimpleValueType.
25 
26 #include <cassert>
27 #include <memory> // For unique_ptr.
28 
29 namespace llvm {
30 class MachineInstr;
31 class MachineRegisterInfo;
32 class TargetInstrInfo;
33 class TargetRegisterInfo;
34 class raw_ostream;
35 
36 /// Holds all the information related to register banks.
38 public:
39  /// Helper struct that represents how a value is partially mapped
40  /// into a register.
41  /// The StartIdx and Length represent what region of the orginal
42  /// value this partial mapping covers.
43  /// This can be represented as a Mask of contiguous bit starting
44  /// at StartIdx bit and spanning Length bits.
45  /// StartIdx is the number of bits from the less significant bits.
46  struct PartialMapping {
47  /// Number of bits at which this partial mapping starts in the
48  /// original value. The bits are counted from less significant
49  /// bits to most significant bits.
50  unsigned StartIdx;
51  /// Length of this mapping in bits. This is how many bits this
52  /// partial mapping covers in the original value:
53  /// from StartIdx to StartIdx + Length -1.
54  unsigned Length;
55  /// Register bank where the partial value lives.
57 
58  PartialMapping() = default;
59 
60  /// Provide a shortcut for quickly building PartialMapping.
61  PartialMapping(unsigned StartIdx, unsigned Length,
62  const RegisterBank &RegBank)
63  : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
64 
65  /// \return the index of in the original value of the most
66  /// significant bit that this partial mapping covers.
67  unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
68 
69  /// Print this partial mapping on dbgs() stream.
70  void dump() const;
71 
72  /// Print this partial mapping on \p OS;
73  void print(raw_ostream &OS) const;
74 
75  /// Check that the Mask is compatible with the RegBank.
76  /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
77  /// there is no way this mapping is valid.
78  ///
79  /// \note This method does not check anything when assertions are disabled.
80  ///
81  /// \return True is the check was successful.
82  bool verify() const;
83  };
84 
85  /// Helper struct that represents how a value is mapped through
86  /// different register banks.
87  ///
88  /// \note: So far we do not have any users of the complex mappings
89  /// (mappings with more than one partial mapping), but when we do,
90  /// we would have needed to duplicate partial mappings.
91  /// The alternative could be to use an array of pointers of partial
92  /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
93  /// pointers instead.
94  ///
95  /// E.g.,
96  /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
97  /// can expand the
98  /// <2 x 32-bit> add into 2 x 32-bit add.
99  ///
100  /// Currently the TableGen-like file would look like:
101  /// \code
102  /// PartialMapping[] = {
103  /// /*32-bit add*/ {0, 32, GPR},
104  /// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
105  /// /*<2x32-bit> vadd {0, 64, VPR}
106  /// }; // PartialMapping duplicated.
107  ///
108  /// ValueMapping[] {
109  /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
110  /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
111  /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
112  /// };
113  /// \endcode
114  ///
115  /// With the array of pointer, we would have:
116  /// \code
117  /// PartialMapping[] = {
118  /// /*32-bit add*/ {0, 32, GPR},
119  /// /*<2x32-bit> vadd {0, 64, VPR}
120  /// }; // No more duplication.
121  ///
122  /// BreakDowns[] = {
123  /// /*AddBreakDown*/ &PartialMapping[0],
124  /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[0],
125  /// /*VAddBreakDown*/ &PartialMapping[1]
126  /// }; // Addresses of PartialMapping duplicated (smaller).
127  ///
128  /// ValueMapping[] {
129  /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
130  /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
131  /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
132  /// };
133  /// \endcode
134  ///
135  /// Given that a PartialMapping is actually small, the code size
136  /// impact is actually a degradation. Moreover the compile time will
137  /// be hit by the additional indirection.
138  /// If PartialMapping gets bigger we may reconsider.
139  struct ValueMapping {
140  /// How the value is broken down between the different register banks.
142 
143  /// Number of partial mapping to break down this value.
144  unsigned NumBreakDowns;
145 
146  /// The default constructor creates an invalid (isValid() == false)
147  /// instance.
148  ValueMapping() : ValueMapping(nullptr, 0) {}
149 
150  /// Initialize a ValueMapping with the given parameter.
151  /// \p BreakDown needs to have a life time at least as long
152  /// as this instance.
154  : BreakDown(BreakDown), NumBreakDowns(NumBreakDowns) {}
155 
156  /// Iterators through the PartialMappings.
157  const PartialMapping *begin() const { return BreakDown; }
158  const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
159 
160  /// Check if this ValueMapping is valid.
161  bool isValid() const { return BreakDown && NumBreakDowns; }
162 
163  /// Verify that this mapping makes sense for a value of
164  /// \p MeaningfulBitWidth.
165  /// \note This method does not check anything when assertions are disabled.
166  ///
167  /// \return True is the check was successful.
168  bool verify(unsigned MeaningfulBitWidth) const;
169 
170  /// Print this on dbgs() stream.
171  void dump() const;
172 
173  /// Print this on \p OS;
174  void print(raw_ostream &OS) const;
175  };
176 
177  /// Helper class that represents how the value of an instruction may be
178  /// mapped and what is the related cost of such mapping.
180  /// Identifier of the mapping.
181  /// This is used to communicate between the target and the optimizers
182  /// which mapping should be realized.
183  unsigned ID;
184  /// Cost of this mapping.
185  unsigned Cost;
186  /// Mapping of all the operands.
187  const ValueMapping *OperandsMapping;
188  /// Number of operands.
189  unsigned NumOperands;
190 
191  const ValueMapping &getOperandMapping(unsigned i) {
192  assert(i < getNumOperands() && "Out of bound operand");
193  return OperandsMapping[i];
194  }
195 
196  public:
197  /// Constructor for the mapping of an instruction.
198  /// \p NumOperands must be equal to number of all the operands of
199  /// the related instruction.
200  /// The rationale is that it is more efficient for the optimizers
201  /// to be able to assume that the mapping of the ith operand is
202  /// at the index i.
203  ///
204  /// \pre ID != InvalidMappingID
205  InstructionMapping(unsigned ID, unsigned Cost,
206  const ValueMapping *OperandsMapping,
207  unsigned NumOperands)
208  : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
209  NumOperands(NumOperands) {
211  "Use the default constructor for invalid mapping");
212  }
213 
214  /// Default constructor.
215  /// Use this constructor to express that the mapping is invalid.
216  InstructionMapping() : ID(InvalidMappingID), Cost(0), NumOperands(0) {}
217 
218  /// Get the cost.
219  unsigned getCost() const { return Cost; }
220 
221  /// Get the ID.
222  unsigned getID() const { return ID; }
223 
224  /// Get the number of operands.
225  unsigned getNumOperands() const { return NumOperands; }
226 
227  /// Get the value mapping of the ith operand.
228  /// \pre The mapping for the ith operand has been set.
229  /// \pre The ith operand is a register.
230  const ValueMapping &getOperandMapping(unsigned i) const {
231  const ValueMapping &ValMapping =
232  const_cast<InstructionMapping *>(this)->getOperandMapping(i);
233  return ValMapping;
234  }
235 
236  /// Set the mapping for all the operands.
237  /// In other words, OpdsMapping should hold at least getNumOperands
238  /// ValueMapping.
239  void setOperandsMapping(const ValueMapping *OpdsMapping) {
240  OperandsMapping = OpdsMapping;
241  }
242 
243  /// Check whether this object is valid.
244  /// This is a lightweight check for obvious wrong instance.
245  bool isValid() const {
246  return getID() != InvalidMappingID && OperandsMapping;
247  }
248 
249  /// Verifiy that this mapping makes sense for \p MI.
250  /// \pre \p MI must be connected to a MachineFunction.
251  ///
252  /// \note This method does not check anything when assertions are disabled.
253  ///
254  /// \return True is the check was successful.
255  bool verify(const MachineInstr &MI) const;
256 
257  /// Print this on dbgs() stream.
258  void dump() const;
259 
260  /// Print this on \p OS;
261  void print(raw_ostream &OS) const;
262  };
263 
264  /// Convenient type to represent the alternatives for mapping an
265  /// instruction.
266  /// \todo When we move to TableGen this should be an array ref.
268 
269  /// Helper class used to get/create the virtual registers that will be used
270  /// to replace the MachineOperand when applying a mapping.
272  /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
273  /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
274  /// Note: We use a SmallVector to avoid heap allocation for most cases.
275  SmallVector<int, 8> OpToNewVRegIdx;
276  /// Hold the registers that will be used to map MI with InstrMapping.
277  SmallVector<unsigned, 8> NewVRegs;
278  /// Current MachineRegisterInfo, used to create new virtual registers.
279  MachineRegisterInfo &MRI;
280  /// Instruction being remapped.
281  MachineInstr &MI;
282  /// New mapping of the instruction.
283  const InstructionMapping &InstrMapping;
284 
285  /// Constant value identifying that the index in OpToNewVRegIdx
286  /// for an operand has not been set yet.
287  static const int DontKnowIdx;
288 
289  /// Get the range in NewVRegs to store all the partial
290  /// values for the \p OpIdx-th operand.
291  ///
292  /// \return The iterator range for the space created.
293  //
294  /// \pre getMI().getOperand(OpIdx).isReg()
296  getVRegsMem(unsigned OpIdx);
297 
298  /// Get the end iterator for a range starting at \p StartIdx and
299  /// spannig \p NumVal in NewVRegs.
300  /// \pre StartIdx + NumVal <= NewVRegs.size()
302  getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
303  SmallVectorImpl<unsigned>::iterator getNewVRegsEnd(unsigned StartIdx,
304  unsigned NumVal);
305 
306  public:
307  /// Create an OperandsMapper that will hold the information to apply \p
308  /// InstrMapping to \p MI.
309  /// \pre InstrMapping.verify(MI)
310  OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
311  MachineRegisterInfo &MRI);
312 
313  /// Getters.
314  /// @{
315  /// The MachineInstr being remapped.
316  MachineInstr &getMI() const { return MI; }
317 
318  /// The final mapping of the instruction.
319  const InstructionMapping &getInstrMapping() const { return InstrMapping; }
320  /// @}
321 
322  /// Create as many new virtual registers as needed for the mapping of the \p
323  /// OpIdx-th operand.
324  /// The number of registers is determined by the number of breakdown for the
325  /// related operand in the instruction mapping.
326  ///
327  /// \pre getMI().getOperand(OpIdx).isReg()
328  ///
329  /// \post All the partial mapping of the \p OpIdx-th operand have been
330  /// assigned a new virtual register.
331  void createVRegs(unsigned OpIdx);
332 
333  /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
334  /// the OpIdx-th operand to \p NewVReg.
335  ///
336  /// \pre getMI().getOperand(OpIdx).isReg()
337  /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
338  /// PartialMapIdx
339  /// \pre NewReg != 0
340  ///
341  /// \post the \p PartialMapIdx-th register of the value mapping of the \p
342  /// OpIdx-th operand has been set.
343  void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
344 
345  /// Get all the virtual registers required to map the \p OpIdx-th operand of
346  /// the instruction.
347  ///
348  /// This return an empty range when createVRegs or setVRegs has not been
349  /// called.
350  /// The iterator may be invalidated by a call to setVRegs or createVRegs.
351  ///
352  /// When \p ForDebug is true, we will not check that the list of new virtual
353  /// registers does not contain uninitialized values.
354  ///
355  /// \pre getMI().getOperand(OpIdx).isReg()
356  /// \pre ForDebug || All partial mappings have been set a register
358  getVRegs(unsigned OpIdx, bool ForDebug = false) const;
359 
360  /// Print this operands mapper on dbgs() stream.
361  void dump() const;
362 
363  /// Print this operands mapper on \p OS stream.
364  void print(raw_ostream &OS, bool ForDebug = false) const;
365  };
366 
367 protected:
368  /// Hold the set of supported register banks.
370  /// Total number of register banks.
371  unsigned NumRegBanks;
372 
373  /// Keep dynamically allocated PartialMapping in a separate map.
374  /// This shouldn't be needed when everything gets TableGen'ed.
376 
377  /// Keep dynamically allocated ValueMapping in a separate map.
378  /// This shouldn't be needed when everything gets TableGen'ed.
380 
381  /// Keep dynamically allocated array of ValueMapping in a separate map.
382  /// This shouldn't be needed when everything gets TableGen'ed.
384 
385  /// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks
386  /// RegisterBank instances.
388 
389  /// This constructor is meaningless.
390  /// It just provides a default constructor that can be used at link time
391  /// when GlobalISel is not built.
392  /// That way, targets can still inherit from this class without doing
393  /// crazy gymnastic to avoid link time failures.
394  /// \note That works because the constructor is inlined.
396  llvm_unreachable("This constructor should not be executed");
397  }
398 
399  /// Get the register bank identified by \p ID.
401  assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
402  return *RegBanks[ID];
403  }
404 
405  /// Try to get the mapping of \p MI.
406  /// See getInstrMapping for more details on what a mapping represents.
407  ///
408  /// Unlike getInstrMapping the returned InstructionMapping may be invalid
409  /// (isValid() == false).
410  /// This means that the target independent code is not smart enough
411  /// to get the mapping of \p MI and thus, the target has to provide the
412  /// information for \p MI.
413  ///
414  /// This implementation is able to get the mapping of:
415  /// - Target specific instructions by looking at the encoding constraints.
416  /// - Any instruction if all the register operands have already been assigned
417  /// a register, a register class, or a register bank.
418  /// - Copies and phis if at least one of the operands has been assigned a
419  /// register, a register class, or a register bank.
420  /// In other words, this method will likely fail to find a mapping for
421  /// any generic opcode that has not been lowered by target specific code.
423 
424  /// Get the uniquely generated PartialMapping for the
425  /// given arguments.
426  const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
427  const RegisterBank &RegBank) const;
428 
429  /// Methods to get a uniquely generated ValueMapping.
430  /// @{
431 
432  /// The most common ValueMapping consists of a single PartialMapping.
433  /// Feature a method for that.
434  const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
435  const RegisterBank &RegBank) const;
436 
437  /// Get the ValueMapping for the given arguments.
438  const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
439  unsigned NumBreakDowns) const;
440  /// @}
441 
442  /// Methods to get a uniquely generated array of ValueMapping.
443  /// @{
444 
445  /// Get the uniquely generated array of ValueMapping for the
446  /// elements of between \p Begin and \p End.
447  ///
448  /// Elements that are nullptr will be replaced by
449  /// invalid ValueMapping (ValueMapping::isValid == false).
450  ///
451  /// \pre The pointers on ValueMapping between \p Begin and \p End
452  /// must uniquely identify a ValueMapping. Otherwise, there is no
453  /// guarantee that the return instance will be unique, i.e., another
454  /// OperandsMapping could have the same content.
455  template <typename Iterator>
456  const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
457 
458  /// Get the uniquely generated array of ValueMapping for the
459  /// elements of \p OpdsMapping.
460  ///
461  /// Elements of \p OpdsMapping that are nullptr will be replaced by
462  /// invalid ValueMapping (ValueMapping::isValid == false).
464  const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
465 
466  /// Get the uniquely generated array of ValueMapping for the
467  /// given arguments.
468  ///
469  /// Arguments that are nullptr will be replaced by invalid
470  /// ValueMapping (ValueMapping::isValid == false).
472  std::initializer_list<const ValueMapping *> OpdsMapping) const;
473  /// @}
474 
475  /// Get the register bank for the \p OpIdx-th operand of \p MI form
476  /// the encoding constraints, if any.
477  ///
478  /// \return A register bank that covers the register class of the
479  /// related encoding constraints or nullptr if \p MI did not provide
480  /// enough information to deduce it.
481  const RegisterBank *
482  getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
483  const TargetInstrInfo &TII,
484  const TargetRegisterInfo &TRI) const;
485 
486  /// Helper method to apply something that is like the default mapping.
487  /// Basically, that means that \p OpdMapper.getMI() is left untouched
488  /// aside from the reassignment of the register operand that have been
489  /// remapped.
490  /// If the mapping of one of the operand spans several registers, this
491  /// method will abort as this is not like a default mapping anymore.
492  ///
493  /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
494  /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
495  static void applyDefaultMapping(const OperandsMapper &OpdMapper);
496 
497  /// See ::applyMapping.
498  virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const {
499  llvm_unreachable("The target has to implement that part");
500  }
501 
502 public:
503  virtual ~RegisterBankInfo();
504 
505  /// Get the register bank identified by \p ID.
506  const RegisterBank &getRegBank(unsigned ID) const {
507  return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
508  }
509 
510  /// Get the register bank of \p Reg.
511  /// If Reg has not been assigned a register, a register class,
512  /// or a register bank, then this returns nullptr.
513  ///
514  /// \pre Reg != 0 (NoRegister)
515  const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
516  const TargetRegisterInfo &TRI) const;
517 
518  /// Get the total number of register banks.
519  unsigned getNumRegBanks() const { return NumRegBanks; }
520 
521  /// Get a register bank that covers \p RC.
522  ///
523  /// \pre \p RC is a user-defined register class (as opposed as one
524  /// generated by TableGen).
525  ///
526  /// \note The mapping RC -> RegBank could be built while adding the
527  /// coverage for the register banks. However, we do not do it, because,
528  /// at least for now, we only need this information for register classes
529  /// that are used in the description of instruction. In other words,
530  /// there are just a handful of them and we do not want to waste space.
531  ///
532  /// \todo This should be TableGen'ed.
533  virtual const RegisterBank &
535  llvm_unreachable("The target must override this method");
536  }
537 
538  /// Get the cost of a copy from \p B to \p A, or put differently,
539  /// get the cost of A = COPY B. Since register banks may cover
540  /// different size, \p Size specifies what will be the size in bits
541  /// that will be copied around.
542  ///
543  /// \note Since this is a copy, both registers have the same size.
544  virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
545  unsigned Size) const {
546  // Optimistically assume that copies are coalesced. I.e., when
547  // they are on the same bank, they are free.
548  // Otherwise assume a non-zero cost of 1. The targets are supposed
549  // to override that properly anyway if they care.
550  return &A != &B;
551  }
552 
553  /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
554  ///
555  /// \pre \p Reg is a virtual register that either has a bank or a class.
556  /// \returns The constrained register class, or nullptr if there is none.
557  /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
558  static const TargetRegisterClass *
561 
562  /// Identifier used when the related instruction mapping instance
563  /// is generated by target independent code.
564  /// Make sure not to use that identifier to avoid possible collision.
565  static const unsigned DefaultMappingID;
566 
567  /// Identifier used when the related instruction mapping instance
568  /// is generated by the default constructor.
569  /// Make sure not to use that identifier.
570  static const unsigned InvalidMappingID;
571 
572  /// Get the mapping of the different operands of \p MI
573  /// on the register bank.
574  /// This mapping should be the direct translation of \p MI.
575  /// In other words, when \p MI is mapped with the returned mapping,
576  /// only the register banks of the operands of \p MI need to be updated.
577  /// In particular, neither the opcode nor the type of \p MI needs to be
578  /// updated for this direct mapping.
579  ///
580  /// The target independent implementation gives a mapping based on
581  /// the register classes for the target specific opcode.
582  /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
583  /// Make sure you do not use that ID for the alternative mapping
584  /// for MI. See getInstrAlternativeMappings for the alternative
585  /// mappings.
586  ///
587  /// For instance, if \p MI is a vector add, the mapping should
588  /// not be a scalarization of the add.
589  ///
590  /// \post returnedVal.verify(MI).
591  ///
592  /// \note If returnedVal does not verify MI, this would probably mean
593  /// that the target does not support that instruction.
594  virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const;
595 
596  /// Get the alternative mappings for \p MI.
597  /// Alternative in the sense different from getInstrMapping.
598  virtual InstructionMappings
600 
601  /// Get the possible mapping for \p MI.
602  /// A mapping defines where the different operands may live and at what cost.
603  /// For instance, let us consider:
604  /// v0(16) = G_ADD <2 x i8> v1, v2
605  /// The possible mapping could be:
606  ///
607  /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
608  /// /*v2*/{(0xFFFF, VPR)}}
609  /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
610  /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
611  /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
612  ///
613  /// \note The first alternative of the returned mapping should be the
614  /// direct translation of \p MI current form.
615  ///
616  /// \post !returnedVal.empty().
617  InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;
618 
619  /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
620  /// After this call \p OpdMapper.getMI() may not be valid anymore.
621  /// \p OpdMapper.getInstrMapping().getID() carries the information of
622  /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
623  /// by the various getInstrXXXMapping method.
624  ///
625  /// Therefore, getting the mapping and applying it should be kept in
626  /// sync.
627  void applyMapping(const OperandsMapper &OpdMapper) const {
628  // The only mapping we know how to handle is the default mapping.
629  if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
630  return applyDefaultMapping(OpdMapper);
631  // For other mapping, the target needs to do the right thing.
632  // If that means calling applyDefaultMapping, fine, but this
633  // must be explicitly stated.
634  applyMappingImpl(OpdMapper);
635  }
636 
637  /// Get the size in bits of \p Reg.
638  /// Utility method to get the size of any registers. Unlike
639  /// MachineRegisterInfo::getSize, the register does not need to be a
640  /// virtual register.
641  ///
642  /// \pre \p Reg != 0 (NoRegister).
643  static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
644  const TargetRegisterInfo &TRI);
645 
646  /// Check that information hold by this instance make sense for the
647  /// given \p TRI.
648  ///
649  /// \note This method does not check anything when assertions are disabled.
650  ///
651  /// \return True is the check was successful.
652  bool verify(const TargetRegisterInfo &TRI) const;
653 };
654 
655 inline raw_ostream &
656 operator<<(raw_ostream &OS,
657  const RegisterBankInfo::PartialMapping &PartMapping) {
658  PartMapping.print(OS);
659  return OS;
660 }
661 
662 inline raw_ostream &
663 operator<<(raw_ostream &OS, const RegisterBankInfo::ValueMapping &ValMapping) {
664  ValMapping.print(OS);
665  return OS;
666 }
667 
668 inline raw_ostream &
669 operator<<(raw_ostream &OS,
670  const RegisterBankInfo::InstructionMapping &InstrMapping) {
671  InstrMapping.print(OS);
672  return OS;
673 }
674 
675 inline raw_ostream &
676 operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
677  OpdMapper.print(OS, /*ForDebug*/ false);
678  return OS;
679 }
680 
681 /// Hashing function for PartialMapping.
682 /// It is required for the hashing of ValueMapping.
683 hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
684 } // End namespace llvm.
685 
686 #endif
void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
void dump() const
Print this on dbgs() stream.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
DenseMap< unsigned, ValueMapping * > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.
bool isValid() const
Check if this ValueMapping is valid.
DenseMap< unsigned, const PartialMapping * > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
size_t i
Helper class that represents how the value of an instruction may be mapped and what is the related co...
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Methods to get a uniquely generated ValueMapping.
iterator_range< SmallVectorImpl< unsigned >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Helper struct that represents how a value is partially mapped into a register.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
Holds all the information related to register banks.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Reg
All possible values of the reg field in the ModR/M byte.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank)
Provide a shortcut for quickly building PartialMapping.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
This file implements a class to represent arbitrary precision integral constant values and operations...
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
bool verify() const
Check that the Mask is compatible with the RegBank.
InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4132
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Methods to get a uniquely generated array of ValueMapping.
const RegisterBank * RegBank
Register bank where the partial value lives.
TargetInstrInfo - Interface to description of machine instruction set.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg...
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
Initialize a ValueMapping with the given parameter.
unsigned const MachineRegisterInfo * MRI
SmallVector< InstructionMapping, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Get the size in bits of Reg.
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
unsigned NumRegBanks
Total number of register banks.
static const unsigned End
ValueMapping()
The default constructor creates an invalid (isValid() == false) instance.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
MachineInstr & getMI() const
Getters.
const PartialMapping * begin() const
Iterators through the PartialMappings.
void dump() const
Print this partial mapping on dbgs() stream.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const RegisterBank & getRegBank(unsigned ID) const
Get the register bank identified by ID.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
const ValueMapping & getOperandMapping(unsigned i) const
Get the value mapping of the ith operand.
This class implements the register bank concept.
Definition: RegisterBank.h:29
DenseMap< unsigned, const ValueMapping * > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
Helper struct that represents how a value is mapped through different register banks.
unsigned getCost() const
Get the cost.
A range adaptor for a pair of iterators.
void dump() const
Print this operands mapper on dbgs() stream.
void print(raw_ostream &OS) const
Print this on OS;.
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
bool isValid() const
Check whether this object is valid.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
void print(raw_ostream &OS) const
Print this on OS;.
InstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands)
Constructor for the mapping of an instruction.
unsigned getNumRegBanks() const
Get the total number of register banks.
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
unsigned getNumOperands() const
Get the number of operands.
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See applyMapping.
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1726
Helper struct that represents how a value is mapped through different register banks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void dump() const
Print this on dbgs() stream.
unsigned NumBreakDowns
Number of partial mapping to break down this value.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
const PartialMapping * end() const
class llvm::RegisterBankInfo *void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
RegisterBankInfo()
This constructor is meaningless.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
RegisterBank ** RegBanks
Hold the set of supported register banks.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.