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LLVM
4.0.0
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#include <AArch64InstrInfo.h>
Static Public Member Functions | |
| static bool | isPairableLdStInst (const MachineInstr &MI) |
Definition at line 30 of file AArch64InstrInfo.h.
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Definition at line 69 of file AArch64InstrInfo.cpp.
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Definition at line 199 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isUncondBranchOpcode(), and parseCondBranch().
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 820 of file AArch64InstrInfo.cpp.
References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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Definition at line 785 of file AArch64InstrInfo.cpp.
References assert(), getMemOpBaseRegImmOfsWidth(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), and llvm::MachineInstr::mayLoadOrStore().
Referenced by mayAlias().
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Definition at line 490 of file AArch64InstrInfo.cpp.
References canFoldIntoCSel(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), MRI, and llvm::ArrayRef< T >::size().
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Definition at line 2045 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyPhysRegTuple(), llvm::RegState::Define, llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::AArch64_AM::getShifterImm(), llvm::AArch64Subtarget::hasNEON(), llvm::AArch64Subtarget::hasZeroCycleRegMove(), llvm::AArch64Subtarget::hasZeroCycleZeroing(), llvm::RegState::Implicit, llvm_unreachable, llvm::AArch64_AM::LSL, and llvm::RegState::Undef.
| void AArch64InstrInfo::copyPhysRegTuple | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| const DebugLoc & | DL, | ||
| unsigned | DestReg, | ||
| unsigned | SrcReg, | ||
| bool | KillSrc, | ||
| unsigned | Opcode, | ||
| llvm::ArrayRef< unsigned > | Indices | ||
| ) | const |
Definition at line 2019 of file AArch64InstrInfo.cpp.
References AddSubReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, llvm::WebAssembly::End, forwardCopyWillClobberTuple(), llvm::getKillRegState(), getRegisterInfo(), llvm::AArch64Subtarget::hasNEON(), llvm::ArrayRef< T >::size(), and SubReg.
Referenced by copyPhysReg().
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Definition at line 4259 of file AArch64InstrInfo.cpp.
References llvm::BitmaskEnumDetail::Mask(), and llvm::AArch64II::MO_FRAGMENT.
| MachineInstr * AArch64InstrInfo::emitFrameIndexDebugValue | ( | MachineFunction & | MF, |
| int | FrameIx, | ||
| uint64_t | Offset, | ||
| const MDNode * | Var, | ||
| const MDNode * | Expr, | ||
| const DebugLoc & | DL | ||
| ) | const |
Definition at line 1988 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMetadata(), and llvm::BuildMI().
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Definition at line 1280 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AArch64ISD::ADRP, llvm::BuildMI(), llvm::AArch64Subtarget::ClassifyGlobalReference(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getTarget(), llvm::RegState::Kill, llvm::CodeModel::Large, llvm::AArch64ISD::LOADgot, llvm::MachineInstr::memoperands_begin(), llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, and llvm::SystemZISD::TM.
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Definition at line 2594 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::constrainRegClass(), contains(), llvm::ISD::FrameIndex, llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::TargetRegisterInfo::getMinimalPhysRegClass(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineInstr::isCopy(), llvm::MachineInstr::isFullCopy(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), loadRegFromStackSlot(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setSubReg(), llvm::ArrayRef< T >::size(), and storeRegToStackSlot().
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When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.
Definition at line 3676 of file AArch64InstrInfo.cpp.
References Accumulator, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), Indexed, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isImm(), llvm::ISD::MUL, llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, llvm::AArch64_AM::processLogicalImmediate(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SignExtend64(), and TII.
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Definition at line 177 of file AArch64InstrInfo.cpp.
References B, llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm_unreachable.
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GetInstSize - Return the number of bytes of code the specified instruction may be.
This returns the maximum number of bytes.
Definition at line 75 of file AArch64InstrInfo.cpp.
References assert(), Desc, llvm::ISD::EH_LABEL, llvm::MachineInstr::getDesc(), llvm::TargetMachine::getMCAsmInfo(), llvm::StackMapOpers::getNumPatchBytes(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::AMDGPUISD::KILL, MBB, and llvm::AArch64ISD::TLSDESC_CALLSEQ.
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Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
All potential patterns are listed in the <Patterns> array.
All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
Definition at line 3548 of file AArch64InstrInfo.cpp.
References getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), and getMaddPatterns().
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Definition at line 1670 of file AArch64InstrInfo.cpp.
References getMemOpBaseRegImmOfsWidth().
| bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth | ( | MachineInstr & | LdSt, |
| unsigned & | BaseReg, | ||
| int64_t & | Offset, | ||
| unsigned & | Width, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Definition at line 1677 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), and llvm::MachineInstr::mayLoadOrStore().
Referenced by areMemAccessesTriviallyDisjoint(), and getMemOpBaseRegImmOfs().
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Definition at line 3047 of file AArch64InstrInfo.cpp.
References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), and llvm::MCInst::setOpcode().
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getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 40 of file AArch64InstrInfo.h.
Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), copyPhysRegTuple(), llvm::AArch64Subtarget::getRegisterInfo(), isCandidateToMergeOrPair(), and optimizeCondBranch().
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Definition at line 4280 of file AArch64InstrInfo.cpp.
References llvm::makeArrayRef(), llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, and llvm::AArch64II::MO_TLS.
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Definition at line 4265 of file AArch64InstrInfo.cpp.
References llvm::makeArrayRef(), llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_HI12, llvm::AArch64II::MO_PAGE, and llvm::AArch64II::MO_PAGEOFF.
| bool AArch64InstrInfo::hasExtendedReg | ( | const MachineInstr & | MI | ) | const |
Returns true if there is an extendable register and that the extending value is non-zero.
Return true if this is this instruction has a non-zero immediate.
Definition at line 1378 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().
| bool AArch64InstrInfo::hasShiftedReg | ( | const MachineInstr & | MI | ) | const |
Returns true if there is a shiftable register and that the shift value is non-zero.
Return true if this is this instruction has a non-zero immediate.
Definition at line 1332 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().
Referenced by shouldScheduleAdjacent().
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Definition at line 379 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), assert(), B, llvm::BuildMI(), and llvm::ArrayRef< T >::empty().
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Definition at line 531 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), canFoldIntoCSel(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::AArch64_AM::encodeLogicalImmediate(), llvm::AArch64CC::EQ, llvm::AArch64CC::getInvertedCondCode(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MRI, llvm::AArch64CC::NE, and llvm::ArrayRef< T >::size().
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Definition at line 675 of file AArch64InstrInfo.cpp.
References canBeExpandedToORR(), llvm::AArch64Subtarget::ExynosM1, llvm::AArch64_AM::getArithShiftValue(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::AArch64Subtarget::getProcFamily(), llvm::MachineOperand::getReg(), llvm::AArch64_AM::getShiftType(), llvm::AArch64_AM::getShiftValue(), llvm::AArch64Subtarget::hasCustomCheapAsMoveHandling(), llvm::AArch64Subtarget::hasZeroCycleZeroing(), llvm::MachineInstr::isAsCheapAsAMove(), llvm_unreachable, and llvm::AArch64_AM::LSL.
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Return true when Inst is associative and commutative so that it can be reassociated.
Definition at line 3190 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
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BranchOpc bytes is capable of jumping to a position BrOffset bytes away. Definition at line 169 of file AArch64InstrInfo.cpp.
References assert(), llvm::tgtok::Bits, getBranchDisplacementBits(), and llvm::isIntN().
| bool AArch64InstrInfo::isCandidateToMergeOrPair | ( | MachineInstr & | MI | ) | const |
Return true if this is a load/store that can be potentially paired/merged.
Definition at line 1632 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineOperand::isImm(), isLdStPairSuppressed(), llvm::AArch64Subtarget::isPaired128Slow(), llvm::MachineOperand::isReg(), and llvm::MachineInstr::modifiesRegister().
Referenced by shouldClusterMemOps().
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Definition at line 765 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
| bool AArch64InstrInfo::isFPRCopy | ( | const MachineInstr & | MI | ) | const |
Does this instruction rename an FPR without modifying bits?
Definition at line 1460 of file AArch64InstrInfo.cpp.
References assert(), contains(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isReg().
| bool AArch64InstrInfo::isGPRCopy | ( | const MachineInstr & | MI | ) | const |
Does this instruction rename a GPR without modifying bits?
Definition at line 1430 of file AArch64InstrInfo.cpp.
References assert(), contains(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
| bool AArch64InstrInfo::isGPRZero | ( | const MachineInstr & | MI | ) | const |
Does this instruction set its full destination register to zero?
Definition at line 1406 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().
| bool AArch64InstrInfo::isLdStPairSuppressed | ( | const MachineInstr & | MI | ) | const |
Return true if pairing the given load or store is hinted to be unprofitable.
Check all MachineMemOperands for a hint to suppress pairing.
Definition at line 1588 of file AArch64InstrInfo.cpp.
References llvm::any_of(), llvm::MachineInstr::memoperands(), and MOSuppressPair.
Referenced by areCandidatesToMergeOrPair(), and isCandidateToMergeOrPair().
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Definition at line 1481 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
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Definition at line 90 of file AArch64InstrInfo.h.
References llvm::MachineInstr::getOpcode().
Referenced by shouldClusterMemOps().
| bool AArch64InstrInfo::isScaledAddr | ( | const MachineInstr & | MI | ) | const |
Return true if this is load/store scales or extends its register offset.
This refers to scaling a dynamic index as opposed to scaled immediates. MI should be a memory op that allows scaled addressing.
Definition at line 1529 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::AArch64_AM::getMemDoShift(), llvm::AArch64_AM::getMemExtendType(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::UXTX.
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Definition at line 1504 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
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Definition at line 167 of file AArch64InstrInfo.h.
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Return true when a code sequence can improve throughput.
It should be called only for instructions in loops.
| Pattern | - combiner pattern |
Definition at line 3503 of file AArch64InstrInfo.cpp.
References llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, and llvm::FMULSUBS_OP2.
Return true if this is an unscaled load/store.
Definition at line 1601 of file AArch64InstrInfo.cpp.
Referenced by areCandidatesToMergeOrPair(), isLdOffsetInRangeOfSt(), isUnscaledLdSt(), and shouldClusterMemOps().
| bool AArch64InstrInfo::isUnscaledLdSt | ( | MachineInstr & | MI | ) | const |
Return true if this is an unscaled load/store.
Definition at line 1626 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isUnscaledLdSt().
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Definition at line 2430 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineBasicBlock::end(), llvm::getDefRegState(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::AArch64Subtarget::hasNEON(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineMemOperand::MOLoad, and Offset.
Referenced by foldMemoryOperandImpl().
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optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.
Try to optimize a compare instruction.
A compare instruction is an instruction which produces AArch64::NZCV. It can be truly compare instruction when there are no uses of its destination register.
The following steps are tried in order:
Definition at line 1010 of file AArch64InstrInfo.cpp.
References assert(), convertFlagSettingOpcode(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), UpdateOperandRegClass(), and llvm::MachineRegisterInfo::use_nodbg_empty().
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Replace csincr-branch sequence by simple conditional branch.
Examples: 1. csinc w9, wzr, wzr, <condition code>=""> tbnz w9, #0, 0x44 to b.<inverted condition="" code>="">
2. csinc w9, wzr, wzr, <condition code>=""> tbz w9, #0, 0x44 to b.<condition code>="">
Replace compare and branch sequence by TBZ/TBNZ instruction when the compare's constant operand is power of 2.
Examples: and w8, w8, #0x400 cbnz w8, L1 to tbnz w8, #10, L1
| MI | Conditional Branch |
Definition at line 4121 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::BuildMI(), llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineRegisterInfo::def_empty(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineInstr::isCopy(), llvm::isPowerOf2_64(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), MBB, llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setSubReg().
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Definition at line 327 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), and llvm::isUncondBranchOpcode().
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Definition at line 286 of file AArch64InstrInfo.cpp.
References llvm::AArch64CC::getInvertedCondCode(), and llvm_unreachable.
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Detect opportunities for ldp/stp formation.
Only called for LdSt for which getMemOpBaseRegImmOfs returns true.
Definition at line 1866 of file AArch64InstrInfo.cpp.
References assert(), canPairLdStOpc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isCandidateToMergeOrPair(), isPairableLdStInst(), isUnscaledLdSt(), and scaleOffset().
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Definition at line 1906 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::AArch64Subtarget::hasArithmeticBccFusion(), llvm::AArch64Subtarget::hasArithmeticCbzFusion(), and hasShiftedReg().
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Definition at line 2326 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), llvm::AArch64Subtarget::hasNEON(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineMemOperand::MOStore, and Offset.
Referenced by foldMemoryOperandImpl().
| void AArch64InstrInfo::suppressLdStPair | ( | MachineInstr & | MI | ) | const |
Hint that pairing the given load or store is unprofitable.
Set a flag on the first MachineMemOperand to suppress pairing.
Definition at line 1595 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), and MOSuppressPair.
|
override |
AArch64 supports MachineCombiner.
Definition at line 3053 of file AArch64InstrInfo.cpp.
1.8.6