LLVM  4.0.0
HexagonISelLowering.cpp
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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
22 #include "llvm/ADT/APInt.h"
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/IR/BasicBlock.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/DataLayout.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalValue.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/Module.h"
43 #include "llvm/IR/Type.h"
44 #include "llvm/IR/Value.h"
45 #include "llvm/MC/MCRegisterInfo.h"
46 #include "llvm/Support/Casting.h"
47 #include "llvm/Support/CodeGen.h"
49 #include "llvm/Support/Debug.h"
55 #include <algorithm>
56 #include <cassert>
57 #include <cstddef>
58 #include <cstdint>
59 #include <limits>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "hexagon-lowering"
65 
66 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
67  cl::init(true), cl::Hidden,
68  cl::desc("Control jump table emission on Hexagon target"));
69 
70 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
72  cl::desc("Enable Hexagon SDNode scheduling"));
73 
74 static cl::opt<bool> EnableFastMath("ffast-math",
76  cl::desc("Enable Fast Math processing"));
77 
78 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
80  cl::desc("Set minimum jump tables"));
81 
82 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
84  cl::desc("Max #stores to inline memcpy"));
85 
86 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
88  cl::desc("Max #stores to inline memcpy"));
89 
90 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
92  cl::desc("Max #stores to inline memmove"));
93 
94 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
96  cl::desc("Max #stores to inline memmove"));
97 
98 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
100  cl::desc("Max #stores to inline memset"));
101 
102 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
104  cl::desc("Max #stores to inline memset"));
105 
106 
107 namespace {
108 
109  class HexagonCCState : public CCState {
110  unsigned NumNamedVarArgParams;
111 
112  public:
113  HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
115  int NumNamedVarArgParams)
116  : CCState(CC, isVarArg, MF, locs, C),
117  NumNamedVarArgParams(NumNamedVarArgParams) {}
118 
119  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
120  };
121 
123  Even = 0,
124  Odd,
125  NoPattern
126  };
127 
128 } // end anonymous namespace
129 
130 // Implement calling convention for Hexagon.
131 
132 static bool isHvxVectorType(MVT ty);
133 
134 static bool
135 CC_Hexagon(unsigned ValNo, MVT ValVT,
136  MVT LocVT, CCValAssign::LocInfo LocInfo,
137  ISD::ArgFlagsTy ArgFlags, CCState &State);
138 
139 static bool
140 CC_Hexagon32(unsigned ValNo, MVT ValVT,
141  MVT LocVT, CCValAssign::LocInfo LocInfo,
142  ISD::ArgFlagsTy ArgFlags, CCState &State);
143 
144 static bool
145 CC_Hexagon64(unsigned ValNo, MVT ValVT,
146  MVT LocVT, CCValAssign::LocInfo LocInfo,
147  ISD::ArgFlagsTy ArgFlags, CCState &State);
148 
149 static bool
150 CC_HexagonVector(unsigned ValNo, MVT ValVT,
151  MVT LocVT, CCValAssign::LocInfo LocInfo,
152  ISD::ArgFlagsTy ArgFlags, CCState &State);
153 
154 static bool
155 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
156  MVT LocVT, CCValAssign::LocInfo LocInfo,
157  ISD::ArgFlagsTy ArgFlags, CCState &State);
158 
159 static bool
160 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
161  MVT LocVT, CCValAssign::LocInfo LocInfo,
162  ISD::ArgFlagsTy ArgFlags, CCState &State);
163 
164 static bool
165 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
166  MVT LocVT, CCValAssign::LocInfo LocInfo,
167  ISD::ArgFlagsTy ArgFlags, CCState &State);
168 
169 static bool
170 RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
171  MVT LocVT, CCValAssign::LocInfo LocInfo,
172  ISD::ArgFlagsTy ArgFlags, CCState &State);
173 
174 static bool
175 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
176  MVT LocVT, CCValAssign::LocInfo LocInfo,
177  ISD::ArgFlagsTy ArgFlags, CCState &State) {
178  HexagonCCState &HState = static_cast<HexagonCCState &>(State);
179 
180  if (ValNo < HState.getNumNamedVarArgParams()) {
181  // Deal with named arguments.
182  return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
183  }
184 
185  // Deal with un-named arguments.
186  unsigned Offset;
187  if (ArgFlags.isByVal()) {
188  // If pass-by-value, the size allocated on stack is decided
189  // by ArgFlags.getByValSize(), not by the size of LocVT.
190  Offset = State.AllocateStack(ArgFlags.getByValSize(),
191  ArgFlags.getByValAlign());
192  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
193  return false;
194  }
195  if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
196  LocVT = MVT::i32;
197  ValVT = MVT::i32;
198  if (ArgFlags.isSExt())
199  LocInfo = CCValAssign::SExt;
200  else if (ArgFlags.isZExt())
201  LocInfo = CCValAssign::ZExt;
202  else
203  LocInfo = CCValAssign::AExt;
204  }
205  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
206  Offset = State.AllocateStack(4, 4);
207  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
208  return false;
209  }
210  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
211  Offset = State.AllocateStack(8, 8);
212  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
213  return false;
214  }
215  if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
216  LocVT == MVT::v16i8) {
217  Offset = State.AllocateStack(16, 16);
218  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
219  return false;
220  }
221  if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
222  LocVT == MVT::v32i8) {
223  Offset = State.AllocateStack(32, 32);
224  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
225  return false;
226  }
227  if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
228  LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
229  Offset = State.AllocateStack(64, 64);
230  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
231  return false;
232  }
233  if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
234  LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
235  Offset = State.AllocateStack(128, 128);
236  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
237  return false;
238  }
239  if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
240  LocVT == MVT::v256i8) {
241  Offset = State.AllocateStack(256, 256);
242  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
243  return false;
244  }
245 
246  llvm_unreachable(nullptr);
247 }
248 
249 static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
250  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
251  if (ArgFlags.isByVal()) {
252  // Passed on stack.
253  unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
254  ArgFlags.getByValAlign());
255  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
256  return false;
257  }
258 
259  if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
260  LocVT = MVT::i32;
261  ValVT = MVT::i32;
262  if (ArgFlags.isSExt())
263  LocInfo = CCValAssign::SExt;
264  else if (ArgFlags.isZExt())
265  LocInfo = CCValAssign::ZExt;
266  else
267  LocInfo = CCValAssign::AExt;
268  } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
269  LocVT = MVT::i32;
270  LocInfo = CCValAssign::BCvt;
271  } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
272  LocVT = MVT::i64;
273  LocInfo = CCValAssign::BCvt;
274  }
275 
276  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
277  if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
278  return false;
279  }
280 
281  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
282  if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
283  return false;
284  }
285 
286  if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
287  unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 32);
288  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
289  return false;
290  }
291 
292  if (isHvxVectorType(LocVT)) {
293  if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
294  return false;
295  }
296 
297  return true; // CC didn't match.
298 }
299 
300 
301 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
302  MVT LocVT, CCValAssign::LocInfo LocInfo,
303  ISD::ArgFlagsTy ArgFlags, CCState &State) {
304  static const MCPhysReg RegList[] = {
305  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
306  Hexagon::R5
307  };
308  if (unsigned Reg = State.AllocateReg(RegList)) {
309  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
310  return false;
311  }
312 
313  unsigned Offset = State.AllocateStack(4, 4);
314  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
315  return false;
316 }
317 
318 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
319  MVT LocVT, CCValAssign::LocInfo LocInfo,
320  ISD::ArgFlagsTy ArgFlags, CCState &State) {
321  if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
322  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
323  return false;
324  }
325 
326  static const MCPhysReg RegList1[] = {
327  Hexagon::D1, Hexagon::D2
328  };
329  static const MCPhysReg RegList2[] = {
330  Hexagon::R1, Hexagon::R3
331  };
332  if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
333  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
334  return false;
335  }
336 
337  unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
338  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
339  return false;
340 }
341 
342 static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
343  MVT LocVT, CCValAssign::LocInfo LocInfo,
344  ISD::ArgFlagsTy ArgFlags, CCState &State) {
345  static const MCPhysReg VecLstS[] = {
346  Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
347  Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
348  Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
349  Hexagon::V15
350  };
351  static const MCPhysReg VecLstD[] = {
352  Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
353  Hexagon::W5, Hexagon::W6, Hexagon::W7
354  };
355  auto &MF = State.getMachineFunction();
356  auto &HST = MF.getSubtarget<HexagonSubtarget>();
357  bool UseHVX = HST.useHVXOps();
358  bool UseHVXDbl = HST.useHVXDblOps();
359 
360  if ((UseHVX && !UseHVXDbl) &&
361  (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
362  LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
363  if (unsigned Reg = State.AllocateReg(VecLstS)) {
364  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
365  return false;
366  }
367  unsigned Offset = State.AllocateStack(64, 64);
368  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
369  return false;
370  }
371  if ((UseHVX && !UseHVXDbl) &&
372  (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
373  LocVT == MVT::v128i8)) {
374  if (unsigned Reg = State.AllocateReg(VecLstD)) {
375  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
376  return false;
377  }
378  unsigned Offset = State.AllocateStack(128, 128);
379  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
380  return false;
381  }
382  // 128B Mode
383  if ((UseHVX && UseHVXDbl) &&
384  (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
385  LocVT == MVT::v256i8)) {
386  if (unsigned Reg = State.AllocateReg(VecLstD)) {
387  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
388  return false;
389  }
390  unsigned Offset = State.AllocateStack(256, 256);
391  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
392  return false;
393  }
394  if ((UseHVX && UseHVXDbl) &&
395  (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
396  LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
397  if (unsigned Reg = State.AllocateReg(VecLstS)) {
398  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
399  return false;
400  }
401  unsigned Offset = State.AllocateStack(128, 128);
402  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
403  return false;
404  }
405  return true;
406 }
407 
408 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
409  MVT LocVT, CCValAssign::LocInfo LocInfo,
410  ISD::ArgFlagsTy ArgFlags, CCState &State) {
411  auto &MF = State.getMachineFunction();
412  auto &HST = MF.getSubtarget<HexagonSubtarget>();
413  bool UseHVX = HST.useHVXOps();
414  bool UseHVXDbl = HST.useHVXDblOps();
415 
416  if (LocVT == MVT::i1) {
417  // Return values of type MVT::i1 still need to be assigned to R0, but
418  // the value type needs to remain i1. LowerCallResult will deal with it,
419  // but it needs to recognize i1 as the value type.
420  LocVT = MVT::i32;
421  } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
422  LocVT = MVT::i32;
423  ValVT = MVT::i32;
424  if (ArgFlags.isSExt())
425  LocInfo = CCValAssign::SExt;
426  else if (ArgFlags.isZExt())
427  LocInfo = CCValAssign::ZExt;
428  else
429  LocInfo = CCValAssign::AExt;
430  } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
431  LocVT = MVT::i32;
432  LocInfo = CCValAssign::BCvt;
433  } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
434  LocVT = MVT::i64;
435  LocInfo = CCValAssign::BCvt;
436  } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
437  LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
438  LocVT == MVT::v512i1) {
439  LocVT = MVT::v16i32;
440  ValVT = MVT::v16i32;
441  LocInfo = CCValAssign::Full;
442  } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
443  LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
444  (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) {
445  LocVT = MVT::v32i32;
446  ValVT = MVT::v32i32;
447  LocInfo = CCValAssign::Full;
448  } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
449  LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
450  LocVT = MVT::v64i32;
451  ValVT = MVT::v64i32;
452  LocInfo = CCValAssign::Full;
453  }
454  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
455  if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
456  return false;
457  }
458 
459  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
460  if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
461  return false;
462  }
463  if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
464  if (!RetCC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
465  return false;
466  }
467  return true; // CC didn't match.
468 }
469 
470 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
471  MVT LocVT, CCValAssign::LocInfo LocInfo,
472  ISD::ArgFlagsTy ArgFlags, CCState &State) {
473  if (LocVT == MVT::i32 || LocVT == MVT::f32) {
474  // Note that use of registers beyond R1 is not ABI compliant. However there
475  // are (experimental) IR passes which generate internal functions that
476  // return structs using these additional registers.
477  static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
478  Hexagon::R2, Hexagon::R3,
479  Hexagon::R4, Hexagon::R5 };
480  if (unsigned Reg = State.AllocateReg(RegList)) {
481  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
482  return false;
483  }
484  }
485 
486  unsigned Offset = State.AllocateStack(4, 4);
487  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
488  return false;
489 }
490 
491 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
492  MVT LocVT, CCValAssign::LocInfo LocInfo,
493  ISD::ArgFlagsTy ArgFlags, CCState &State) {
494  if (LocVT == MVT::i64 || LocVT == MVT::f64) {
495  if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
496  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
497  return false;
498  }
499  }
500 
501  unsigned Offset = State.AllocateStack(8, 8);
502  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
503  return false;
504 }
505 
506 static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
507  MVT LocVT, CCValAssign::LocInfo LocInfo,
508  ISD::ArgFlagsTy ArgFlags, CCState &State) {
509  auto &MF = State.getMachineFunction();
510  auto &HST = MF.getSubtarget<HexagonSubtarget>();
511  bool UseHVX = HST.useHVXOps();
512  bool UseHVXDbl = HST.useHVXDblOps();
513 
514  unsigned OffSiz = 64;
515  if (LocVT == MVT::v16i32) {
516  if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
517  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
518  return false;
519  }
520  } else if (LocVT == MVT::v32i32) {
521  unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
522  if (unsigned Reg = State.AllocateReg(Req)) {
523  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
524  return false;
525  }
526  OffSiz = 128;
527  } else if (LocVT == MVT::v64i32) {
528  if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
529  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
530  return false;
531  }
532  OffSiz = 256;
533  }
534 
535  unsigned Offset = State.AllocateStack(OffSiz, OffSiz);
536  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
537  return false;
538 }
539 
540 void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
541  if (VT != PromotedLdStVT) {
543  AddPromotedToType(ISD::LOAD, VT, PromotedLdStVT);
544 
546  AddPromotedToType(ISD::STORE, VT, PromotedLdStVT);
547  }
548 }
549 
550 SDValue
552  const {
553  return SDValue();
554 }
555 
556 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
557 /// by "Src" to address "Dst" of size "Size". Alignment information is
558 /// specified by the specific parameter attribute. The copy will be passed as
559 /// a byval function parameter. Sometimes what we are copying is the end of a
560 /// larger object, the part that does not fit in registers.
563  SelectionDAG &DAG, const SDLoc &dl) {
564  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
565  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
566  /*isVolatile=*/false, /*AlwaysInline=*/false,
567  /*isTailCall=*/false,
569 }
570 
571 static bool isHvxVectorType(MVT Ty) {
572  switch (Ty.SimpleTy) {
573  case MVT::v8i64:
574  case MVT::v16i32:
575  case MVT::v32i16:
576  case MVT::v64i8:
577  case MVT::v16i64:
578  case MVT::v32i32:
579  case MVT::v64i16:
580  case MVT::v128i8:
581  case MVT::v32i64:
582  case MVT::v64i32:
583  case MVT::v128i16:
584  case MVT::v256i8:
585  case MVT::v512i1:
586  case MVT::v1024i1:
587  return true;
588  default:
589  return false;
590  }
591 }
592 
593 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
594 // passed by value, the function prototype is modified to return void and
595 // the value is stored in memory pointed by a pointer passed by caller.
596 SDValue
598  bool isVarArg,
600  const SmallVectorImpl<SDValue> &OutVals,
601  const SDLoc &dl, SelectionDAG &DAG) const {
602  // CCValAssign - represent the assignment of the return value to locations.
604 
605  // CCState - Info about the registers and stack slot.
606  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
607  *DAG.getContext());
608 
609  // Analyze return values of ISD::RET
610  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
611 
612  SDValue Flag;
613  SmallVector<SDValue, 4> RetOps(1, Chain);
614 
615  // Copy the result values into the output registers.
616  for (unsigned i = 0; i != RVLocs.size(); ++i) {
617  CCValAssign &VA = RVLocs[i];
618 
619  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
620 
621  // Guarantee that all emitted copies are stuck together with flags.
622  Flag = Chain.getValue(1);
623  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
624  }
625 
626  RetOps[0] = Chain; // Update chain.
627 
628  // Add the flag if we have it.
629  if (Flag.getNode())
630  RetOps.push_back(Flag);
631 
632  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
633 }
634 
636  // If either no tail call or told not to tail call at all, don't.
637  auto Attr =
638  CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
639  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
640  return false;
641 
642  return true;
643 }
644 
645 /// LowerCallResult - Lower the result values of an ISD::CALL into the
646 /// appropriate copies out of appropriate physical registers. This assumes that
647 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
648 /// being lowered. Returns a SDNode with the same number of values as the
649 /// ISD::CALL.
651  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
652  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
654  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
655  // Assign locations to each value returned by this call.
657 
658  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
659  *DAG.getContext());
660 
661  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
662 
663  // Copy all of the result registers out of their specified physreg.
664  for (unsigned i = 0; i != RVLocs.size(); ++i) {
665  SDValue RetVal;
666  if (RVLocs[i].getValVT() == MVT::i1) {
667  // Return values of type MVT::i1 require special handling. The reason
668  // is that MVT::i1 is associated with the PredRegs register class, but
669  // values of that type are still returned in R0. Generate an explicit
670  // copy into a predicate register from R0, and treat the value of the
671  // predicate register as the call result.
672  auto &MRI = DAG.getMachineFunction().getRegInfo();
673  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
674  MVT::i32, InFlag);
675  // FR0 = (Value, Chain, Glue)
676  unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
677  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
678  FR0.getValue(0), FR0.getValue(2));
679  // TPR = (Chain, Glue)
680  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1,
681  TPR.getValue(1));
682  } else {
683  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
684  RVLocs[i].getValVT(), InFlag);
685  }
686  InVals.push_back(RetVal.getValue(0));
687  Chain = RetVal.getValue(1);
688  InFlag = RetVal.getValue(2);
689  }
690 
691  return Chain;
692 }
693 
694 /// LowerCall - Functions arguments are copied from virtual regs to
695 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
696 SDValue
698  SmallVectorImpl<SDValue> &InVals) const {
699  SelectionDAG &DAG = CLI.DAG;
700  SDLoc &dl = CLI.DL;
702  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
704  SDValue Chain = CLI.Chain;
705  SDValue Callee = CLI.Callee;
706  bool &IsTailCall = CLI.IsTailCall;
707  CallingConv::ID CallConv = CLI.CallConv;
708  bool IsVarArg = CLI.IsVarArg;
709  bool DoesNotReturn = CLI.DoesNotReturn;
710 
711  bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
713  auto PtrVT = getPointerTy(MF.getDataLayout());
714 
715  // Check for varargs.
716  unsigned NumNamedVarArgParams = -1U;
717  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
718  const GlobalValue *GV = GAN->getGlobal();
719  Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
720  if (const Function* F = dyn_cast<Function>(GV)) {
721  // If a function has zero args and is a vararg function, that's
722  // disallowed so it must be an undeclared function. Do not assume
723  // varargs if the callee is undefined.
724  if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
725  NumNamedVarArgParams = F->getFunctionType()->getNumParams();
726  }
727  }
728 
729  // Analyze operands of the call, assigning locations to each operand.
731  HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
732  *DAG.getContext(), NumNamedVarArgParams);
733 
734  if (IsVarArg)
735  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
736  else
737  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
738 
739  auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
740  if (Attr.getValueAsString() == "true")
741  IsTailCall = false;
742 
743  if (IsTailCall) {
744  bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
745  IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
746  IsVarArg, IsStructRet,
747  StructAttrFlag,
748  Outs, OutVals, Ins, DAG);
749  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
750  CCValAssign &VA = ArgLocs[i];
751  if (VA.isMemLoc()) {
752  IsTailCall = false;
753  break;
754  }
755  }
756  DEBUG(dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
757  : "Argument must be passed on stack. "
758  "Not eligible for Tail Call\n"));
759  }
760  // Get a count of how many bytes are to be pushed on the stack.
761  unsigned NumBytes = CCInfo.getNextStackOffset();
763  SmallVector<SDValue, 8> MemOpChains;
764 
765  auto &HRI = *Subtarget.getRegisterInfo();
766  SDValue StackPtr =
767  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
768 
769  bool NeedsArgAlign = false;
770  unsigned LargestAlignSeen = 0;
771  // Walk the register/memloc assignments, inserting copies/loads.
772  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
773  CCValAssign &VA = ArgLocs[i];
774  SDValue Arg = OutVals[i];
775  ISD::ArgFlagsTy Flags = Outs[i].Flags;
776  // Record if we need > 8 byte alignment on an argument.
777  bool ArgAlign = isHvxVectorType(VA.getValVT());
778  NeedsArgAlign |= ArgAlign;
779 
780  // Promote the value if needed.
781  switch (VA.getLocInfo()) {
782  default:
783  // Loc info must be one of Full, SExt, ZExt, or AExt.
784  llvm_unreachable("Unknown loc info!");
785  case CCValAssign::BCvt:
786  case CCValAssign::Full:
787  break;
788  case CCValAssign::SExt:
789  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
790  break;
791  case CCValAssign::ZExt:
792  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
793  break;
794  case CCValAssign::AExt:
795  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
796  break;
797  }
798 
799  if (VA.isMemLoc()) {
800  unsigned LocMemOffset = VA.getLocMemOffset();
801  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
802  StackPtr.getValueType());
803  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
804  if (ArgAlign)
805  LargestAlignSeen = std::max(LargestAlignSeen,
806  VA.getLocVT().getStoreSizeInBits() >> 3);
807  if (Flags.isByVal()) {
808  // The argument is a struct passed by value. According to LLVM, "Arg"
809  // is is pointer.
810  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
811  Flags, DAG, dl));
812  } else {
814  DAG.getMachineFunction(), LocMemOffset);
815  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
816  MemOpChains.push_back(S);
817  }
818  continue;
819  }
820 
821  // Arguments that can be passed on register must be kept at RegsToPass
822  // vector.
823  if (VA.isRegLoc())
824  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
825  }
826 
827  if (NeedsArgAlign && Subtarget.hasV60TOps()) {
828  DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
830  // V6 vectors passed by value have 64 or 128 byte alignment depending
831  // on whether we are 64 byte vector mode or 128 byte.
832  bool UseHVXDbl = Subtarget.useHVXDblOps();
833  assert(Subtarget.useHVXOps());
834  const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
835  LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
836  MFI.ensureMaxAlignment(LargestAlignSeen);
837  }
838  // Transform all store nodes into one single node because all store
839  // nodes are independent of each other.
840  if (!MemOpChains.empty())
841  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
842 
843  if (!IsTailCall) {
844  SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
845  Chain = DAG.getCALLSEQ_START(Chain, C, dl);
846  }
847 
848  // Build a sequence of copy-to-reg nodes chained together with token
849  // chain and flag operands which copy the outgoing args into registers.
850  // The Glue is necessary since all emitted instructions must be
851  // stuck together.
852  SDValue Glue;
853  if (!IsTailCall) {
854  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
855  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
856  RegsToPass[i].second, Glue);
857  Glue = Chain.getValue(1);
858  }
859  } else {
860  // For tail calls lower the arguments to the 'real' stack slot.
861  //
862  // Force all the incoming stack arguments to be loaded from the stack
863  // before any new outgoing arguments are stored to the stack, because the
864  // outgoing stack slots may alias the incoming argument stack slots, and
865  // the alias isn't otherwise explicit. This is slightly more conservative
866  // than necessary, because it means that each store effectively depends
867  // on every argument instead of just those arguments it would clobber.
868  //
869  // Do not flag preceding copytoreg stuff together with the following stuff.
870  Glue = SDValue();
871  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
872  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
873  RegsToPass[i].second, Glue);
874  Glue = Chain.getValue(1);
875  }
876  Glue = SDValue();
877  }
878 
879  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
880  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
881 
882  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
883  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
884  // node so that legalize doesn't hack it.
885  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
886  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
887  } else if (ExternalSymbolSDNode *S =
888  dyn_cast<ExternalSymbolSDNode>(Callee)) {
889  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
890  }
891 
892  // Returns a chain & a flag for retval copy to use.
893  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
895  Ops.push_back(Chain);
896  Ops.push_back(Callee);
897 
898  // Add argument registers to the end of the list so that they are
899  // known live into the call.
900  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
901  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
902  RegsToPass[i].second.getValueType()));
903  }
904 
905  if (Glue.getNode())
906  Ops.push_back(Glue);
907 
908  if (IsTailCall) {
910  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
911  }
912 
913  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
914  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
915  Glue = Chain.getValue(1);
916 
917  // Create the CALLSEQ_END node.
918  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
919  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
920  Glue = Chain.getValue(1);
921 
922  // Handle result values, copying them out of physregs into vregs that we
923  // return.
924  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
925  InVals, OutVals, Callee);
926 }
927 
929  SDValue &Base, SDValue &Offset,
930  bool &IsInc, SelectionDAG &DAG) {
931  if (Ptr->getOpcode() != ISD::ADD)
932  return false;
933 
934  auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
935  bool UseHVX = HST.useHVXOps();
936  bool UseHVXDbl = HST.useHVXDblOps();
937 
938  bool ValidHVXDblType =
939  (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
940  VT == MVT::v64i16 || VT == MVT::v128i8);
941  bool ValidHVXType =
942  UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
943  VT == MVT::v32i16 || VT == MVT::v64i8);
944 
945  if (ValidHVXDblType || ValidHVXType ||
946  VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
947  IsInc = (Ptr->getOpcode() == ISD::ADD);
948  Base = Ptr->getOperand(0);
949  Offset = Ptr->getOperand(1);
950  // Ensure that Offset is a constant.
951  return isa<ConstantSDNode>(Offset);
952  }
953 
954  return false;
955 }
956 
957 /// getPostIndexedAddressParts - returns true by value, base pointer and
958 /// offset pointer and addressing mode by reference if this node can be
959 /// combined with a load / store to form a post-indexed load / store.
961  SDValue &Base,
962  SDValue &Offset,
964  SelectionDAG &DAG) const
965 {
966  EVT VT;
967  SDValue Ptr;
968 
969  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
970  VT = LD->getMemoryVT();
971  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
972  VT = ST->getMemoryVT();
973  if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore())
974  return false;
975  } else {
976  return false;
977  }
978 
979  bool IsInc = false;
980  bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
981  if (isLegal) {
982  auto &HII = *Subtarget.getInstrInfo();
983  int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
984  if (HII.isValidAutoIncImm(VT, OffsetVal)) {
985  AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
986  return true;
987  }
988  }
989 
990  return false;
991 }
992 
993 SDValue
995  SDNode *Node = Op.getNode();
997  auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
998  switch (Node->getOpcode()) {
999  case ISD::INLINEASM: {
1000  unsigned NumOps = Node->getNumOperands();
1001  if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1002  --NumOps; // Ignore the flag operand.
1003 
1004  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1005  if (FuncInfo.hasClobberLR())
1006  break;
1007  unsigned Flags =
1008  cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1009  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1010  ++i; // Skip the ID value.
1011 
1012  switch (InlineAsm::getKind(Flags)) {
1013  default: llvm_unreachable("Bad flags!");
1016  case InlineAsm::Kind_Imm:
1018  case InlineAsm::Kind_Mem: {
1019  for (; NumVals; --NumVals, ++i) {}
1020  break;
1021  }
1023  for (; NumVals; --NumVals, ++i) {
1024  unsigned Reg =
1025  cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1026 
1027  // Check it to be lr
1028  const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
1029  if (Reg == QRI->getRARegister()) {
1030  FuncInfo.setHasClobberLR(true);
1031  break;
1032  }
1033  }
1034  break;
1035  }
1036  }
1037  }
1038  }
1039  } // Node->getOpcode
1040  return Op;
1041 }
1042 
1043 // Need to transform ISD::PREFETCH into something that doesn't inherit
1044 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
1045 // SDNPMayStore.
1047  SelectionDAG &DAG) const {
1048  SDValue Chain = Op.getOperand(0);
1049  SDValue Addr = Op.getOperand(1);
1050  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
1051  // if the "reg" is fed by an "add".
1052  SDLoc DL(Op);
1053  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1054  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1055 }
1056 
1058  SelectionDAG &DAG) const {
1059  SDValue Chain = Op.getOperand(0);
1060  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1061  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
1062  if (IntNo == Intrinsic::hexagon_prefetch) {
1063  SDValue Addr = Op.getOperand(2);
1064  SDLoc DL(Op);
1065  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1066  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1067  }
1068  return SDValue();
1069 }
1070 
1071 SDValue
1073  SelectionDAG &DAG) const {
1074  SDValue Chain = Op.getOperand(0);
1075  SDValue Size = Op.getOperand(1);
1076  SDValue Align = Op.getOperand(2);
1077  SDLoc dl(Op);
1078 
1079  ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
1080  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
1081 
1082  unsigned A = AlignConst->getSExtValue();
1083  auto &HFI = *Subtarget.getFrameLowering();
1084  // "Zero" means natural stack alignment.
1085  if (A == 0)
1086  A = HFI.getStackAlignment();
1087 
1088  DEBUG({
1089  dbgs () << __func__ << " Align: " << A << " Size: ";
1090  Size.getNode()->dump(&DAG);
1091  dbgs() << "\n";
1092  });
1093 
1094  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
1095  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1096  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
1097 
1098  DAG.ReplaceAllUsesOfValueWith(Op, AA);
1099  return AA;
1100 }
1101 
1103  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1104  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1105  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1106  MachineFunction &MF = DAG.getMachineFunction();
1107  MachineFrameInfo &MFI = MF.getFrameInfo();
1108  MachineRegisterInfo &RegInfo = MF.getRegInfo();
1109  auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1110 
1111  // Assign locations to all of the incoming arguments.
1113  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1114  *DAG.getContext());
1115 
1116  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
1117 
1118  // For LLVM, in the case when returning a struct by value (>8byte),
1119  // the first argument is a pointer that points to the location on caller's
1120  // stack where the return value will be stored. For Hexagon, the location on
1121  // caller's stack is passed only when the struct size is smaller than (and
1122  // equal to) 8 bytes. If not, no address will be passed into callee and
1123  // callee return the result direclty through R0/R1.
1124 
1125  SmallVector<SDValue, 8> MemOps;
1126  bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
1127 
1128  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1129  CCValAssign &VA = ArgLocs[i];
1130  ISD::ArgFlagsTy Flags = Ins[i].Flags;
1131  unsigned ObjSize;
1132  unsigned StackLocation;
1133  int FI;
1134 
1135  if ( (VA.isRegLoc() && !Flags.isByVal())
1136  || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
1137  // Arguments passed in registers
1138  // 1. int, long long, ptr args that get allocated in register.
1139  // 2. Large struct that gets an register to put its address in.
1140  EVT RegVT = VA.getLocVT();
1141  if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1142  RegVT == MVT::i32 || RegVT == MVT::f32) {
1143  unsigned VReg =
1144  RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1145  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1146  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1147  } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1148  unsigned VReg =
1149  RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1150  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1151  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1152 
1153  // Single Vector
1154  } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
1155  RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
1156  unsigned VReg =
1157  RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass);
1158  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1159  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1160  } else if (UseHVX && UseHVXDbl &&
1161  ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1162  RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
1163  unsigned VReg =
1164  RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass);
1165  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1166  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1167 
1168  // Double Vector
1169  } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1170  RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
1171  unsigned VReg =
1172  RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass);
1173  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1174  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1175  } else if (UseHVX && UseHVXDbl &&
1176  ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
1177  RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
1178  unsigned VReg =
1179  RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass);
1180  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1181  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1182  } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
1183  assert(0 && "need to support VecPred regs");
1184  unsigned VReg =
1185  RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass);
1186  RegInfo.addLiveIn(VA.getLocReg(), VReg);
1187  InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1188  } else {
1189  assert (0);
1190  }
1191  } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
1192  assert (0 && "ByValSize must be bigger than 8 bytes");
1193  } else {
1194  // Sanity check.
1195  assert(VA.isMemLoc());
1196 
1197  if (Flags.isByVal()) {
1198  // If it's a byval parameter, then we need to compute the
1199  // "real" size, not the size of the pointer.
1200  ObjSize = Flags.getByValSize();
1201  } else {
1202  ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
1203  }
1204 
1205  StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
1206  // Create the frame index object for this incoming parameter...
1207  FI = MFI.CreateFixedObject(ObjSize, StackLocation, true);
1208 
1209  // Create the SelectionDAG nodes cordl, responding to a load
1210  // from this parameter.
1211  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1212 
1213  if (Flags.isByVal()) {
1214  // If it's a pass-by-value aggregate, then do not dereference the stack
1215  // location. Instead, we should generate a reference to the stack
1216  // location.
1217  InVals.push_back(FIN);
1218  } else {
1219  InVals.push_back(
1220  DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo()));
1221  }
1222  }
1223  }
1224 
1225  if (!MemOps.empty())
1226  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1227 
1228  if (isVarArg) {
1229  // This will point to the next argument passed via stack.
1232  CCInfo.getNextStackOffset(),
1233  true);
1234  FuncInfo.setVarArgsFrameIndex(FrameIndex);
1235  }
1236 
1237  return Chain;
1238 }
1239 
1240 SDValue
1242  // VASTART stores the address of the VarArgsFrameIndex slot into the
1243  // memory location argument.
1244  MachineFunction &MF = DAG.getMachineFunction();
1246  SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
1247  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1248  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
1249  MachinePointerInfo(SV));
1250 }
1251 
1252 // Creates a SPLAT instruction for a constant value VAL.
1253 static SDValue createSplat(SelectionDAG &DAG, const SDLoc &dl, EVT VT,
1254  SDValue Val) {
1255  if (VT.getSimpleVT() == MVT::v4i8)
1256  return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
1257 
1258  if (VT.getSimpleVT() == MVT::v4i16)
1259  return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
1260 
1261  return SDValue();
1262 }
1263 
1264 static bool isSExtFree(SDValue N) {
1265  // A sign-extend of a truncate of a sign-extend is free.
1266  if (N.getOpcode() == ISD::TRUNCATE &&
1268  return true;
1269  // We have sign-extended loads.
1270  if (N.getOpcode() == ISD::LOAD)
1271  return true;
1272  return false;
1273 }
1274 
1276  SDLoc dl(Op);
1277  SDValue InpVal = Op.getOperand(0);
1278  if (isa<ConstantSDNode>(InpVal)) {
1279  uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
1280  return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
1281  }
1282  SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
1283  return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
1284 }
1285 
1287  SDLoc dl(Op);
1288 
1289  SDValue LHS = Op.getOperand(0);
1290  SDValue RHS = Op.getOperand(1);
1291  SDValue Cmp = Op.getOperand(2);
1292  ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1293 
1294  EVT VT = Op.getValueType();
1295  EVT LHSVT = LHS.getValueType();
1296  EVT RHSVT = RHS.getValueType();
1297 
1298  if (LHSVT == MVT::v2i16) {
1300  unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1301  : ISD::ZERO_EXTEND;
1302  SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1303  SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1304  SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1305  return SC;
1306  }
1307 
1308  // Treat all other vector types as legal.
1309  if (VT.isVector())
1310  return Op;
1311 
1312  // Equals and not equals should use sign-extend, not zero-extend, since
1313  // we can represent small negative values in the compare instructions.
1314  // The LLVM default is to use zero-extend arbitrarily in these cases.
1315  if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1316  (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1317  (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1319  if (C && C->getAPIntValue().isNegative()) {
1320  LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1321  RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1322  return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1323  LHS, RHS, Op.getOperand(2));
1324  }
1325  if (isSExtFree(LHS) || isSExtFree(RHS)) {
1326  LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1327  RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1328  return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1329  LHS, RHS, Op.getOperand(2));
1330  }
1331  }
1332  return SDValue();
1333 }
1334 
1335 SDValue
1337  SDValue PredOp = Op.getOperand(0);
1338  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1339  EVT OpVT = Op1.getValueType();
1340  SDLoc DL(Op);
1341 
1342  if (OpVT == MVT::v2i16) {
1343  SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1344  SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1345  SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1346  SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1347  return TR;
1348  }
1349 
1350  return SDValue();
1351 }
1352 
1353 // Handle only specific vector loads.
1355  EVT VT = Op.getValueType();
1356  SDLoc DL(Op);
1357  LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1358  SDValue Chain = LoadNode->getChain();
1359  SDValue Ptr = Op.getOperand(1);
1360  SDValue LoweredLoad;
1361  SDValue Result;
1362  SDValue Base = LoadNode->getBasePtr();
1363  ISD::LoadExtType Ext = LoadNode->getExtensionType();
1364  unsigned Alignment = LoadNode->getAlignment();
1365  SDValue LoadChain;
1366 
1367  if(Ext == ISD::NON_EXTLOAD)
1368  Ext = ISD::ZEXTLOAD;
1369 
1370  if (VT == MVT::v4i16) {
1371  if (Alignment == 2) {
1372  SDValue Loads[4];
1373  // Base load.
1374  Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1375  LoadNode->getPointerInfo(), MVT::i16, Alignment,
1376  LoadNode->getMemOperand()->getFlags());
1377  // Base+2 load.
1378  SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
1379  Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1380  Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1381  LoadNode->getPointerInfo(), MVT::i16, Alignment,
1382  LoadNode->getMemOperand()->getFlags());
1383  // SHL 16, then OR base and base+2.
1384  SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
1385  SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1386  SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1387  // Base + 4.
1388  Increment = DAG.getConstant(4, DL, MVT::i32);
1389  Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1390  Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1391  LoadNode->getPointerInfo(), MVT::i16, Alignment,
1392  LoadNode->getMemOperand()->getFlags());
1393  // Base + 6.
1394  Increment = DAG.getConstant(6, DL, MVT::i32);
1395  Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1396  Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1397  LoadNode->getPointerInfo(), MVT::i16, Alignment,
1398  LoadNode->getMemOperand()->getFlags());
1399  // SHL 16, then OR base+4 and base+6.
1400  Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1401  SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1402  // Combine to i64. This could be optimised out later if we can
1403  // affect reg allocation of this code.
1404  Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1405  LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1406  Loads[0].getValue(1), Loads[1].getValue(1),
1407  Loads[2].getValue(1), Loads[3].getValue(1));
1408  } else {
1409  // Perform default type expansion.
1410  Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1411  LoadNode->getAlignment(),
1412  LoadNode->getMemOperand()->getFlags());
1413  LoadChain = Result.getValue(1);
1414  }
1415  } else
1416  llvm_unreachable("Custom lowering unsupported load");
1417 
1418  Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1419  // Since we pretend to lower a load, we need the original chain
1420  // info attached to the result.
1421  SDValue Ops[] = { Result, LoadChain };
1422 
1423  return DAG.getMergeValues(Ops, DL);
1424 }
1425 
1426 SDValue
1428  EVT ValTy = Op.getValueType();
1429  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1430  unsigned Align = CPN->getAlignment();
1431  bool IsPositionIndependent = isPositionIndependent();
1432  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1433 
1434  unsigned Offset = 0;
1435  SDValue T;
1436  if (CPN->isMachineConstantPoolEntry())
1437  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
1438  TF);
1439  else
1440  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset,
1441  TF);
1442 
1443  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1444  "Inconsistent target flag encountered");
1445 
1446  if (IsPositionIndependent)
1447  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1448  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1449 }
1450 
1451 SDValue
1453  EVT VT = Op.getValueType();
1454  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1455  if (isPositionIndependent()) {
1457  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1458  }
1459 
1460  SDValue T = DAG.getTargetJumpTable(Idx, VT);
1461  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1462 }
1463 
1464 SDValue
1466  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1467  MachineFunction &MF = DAG.getMachineFunction();
1468  MachineFrameInfo &MFI = MF.getFrameInfo();
1469  MFI.setReturnAddressIsTaken(true);
1470 
1472  return SDValue();
1473 
1474  EVT VT = Op.getValueType();
1475  SDLoc dl(Op);
1476  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1477  if (Depth) {
1478  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1479  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1480  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1481  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1482  MachinePointerInfo());
1483  }
1484 
1485  // Return LR, which contains the return address. Mark it an implicit live-in.
1486  unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1487  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1488 }
1489 
1490 SDValue
1492  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1494  MFI.setFrameAddressIsTaken(true);
1495 
1496  EVT VT = Op.getValueType();
1497  SDLoc dl(Op);
1498  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1499  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1500  HRI.getFrameRegister(), VT);
1501  while (Depth--)
1502  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1503  MachinePointerInfo());
1504  return FrameAddr;
1505 }
1506 
1507 SDValue
1509  SDLoc dl(Op);
1510  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1511 }
1512 
1513 SDValue
1515  SDLoc dl(Op);
1516  auto *GAN = cast<GlobalAddressSDNode>(Op);
1517  auto PtrVT = getPointerTy(DAG.getDataLayout());
1518  auto *GV = GAN->getGlobal();
1519  int64_t Offset = GAN->getOffset();
1520 
1521  auto &HLOF = *HTM.getObjFileLowering();
1523 
1524  if (RM == Reloc::Static) {
1525  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1526  const GlobalObject *GO = GV->getBaseObject();
1527  if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
1528  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1529  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1530  }
1531 
1532  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1533  if (UsePCRel) {
1534  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1536  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1537  }
1538 
1539  // Use GOT index.
1540  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1541  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1542  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1543  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1544 }
1545 
1546 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1547 SDValue
1549  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1550  SDLoc dl(Op);
1551  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1552 
1554  if (RM == Reloc::Static) {
1555  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1556  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1557  }
1558 
1559  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1560  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1561 }
1562 
1563 SDValue
1565  const {
1566  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1569  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1570 }
1571 
1572 SDValue
1574  GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, unsigned ReturnReg,
1575  unsigned char OperandFlags) const {
1577  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1578  SDLoc dl(GA);
1579  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1580  GA->getValueType(0),
1581  GA->getOffset(),
1582  OperandFlags);
1583  // Create Operands for the call.The Operands should have the following:
1584  // 1. Chain SDValue
1585  // 2. Callee which in this case is the Global address value.
1586  // 3. Registers live into the call.In this case its R0, as we
1587  // have just one argument to be passed.
1588  // 4. InFlag if there is any.
1589  // Note: The order is important.
1590 
1591  if (InFlag) {
1592  SDValue Ops[] = { Chain, TGA,
1593  DAG.getRegister(Hexagon::R0, PtrVT), *InFlag };
1594  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1595  } else {
1596  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT)};
1597  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1598  }
1599 
1600  // Inform MFI that function has calls.
1601  MFI.setAdjustsStack(true);
1602 
1603  SDValue Flag = Chain.getValue(1);
1604  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
1605 }
1606 
1607 //
1608 // Lower using the intial executable model for TLS addresses
1609 //
1610 SDValue
1612  SelectionDAG &DAG) const {
1613  SDLoc dl(GA);
1614  int64_t Offset = GA->getOffset();
1615  auto PtrVT = getPointerTy(DAG.getDataLayout());
1616 
1617  // Get the thread pointer.
1618  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1619 
1620  bool IsPositionIndependent = isPositionIndependent();
1621  unsigned char TF =
1622  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1623 
1624  // First generate the TLS symbol address
1625  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1626  Offset, TF);
1627 
1628  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1629 
1630  if (IsPositionIndependent) {
1631  // Generate the GOT pointer in case of position independent code
1632  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1633 
1634  // Add the TLS Symbol address to GOT pointer.This gives
1635  // GOT relative relocation for the symbol.
1636  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1637  }
1638 
1639  // Load the offset value for TLS symbol.This offset is relative to
1640  // thread pointer.
1641  SDValue LoadOffset =
1642  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1643 
1644  // Address of the thread local variable is the add of thread
1645  // pointer and the offset of the variable.
1646  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1647 }
1648 
1649 //
1650 // Lower using the local executable model for TLS addresses
1651 //
1652 SDValue
1654  SelectionDAG &DAG) const {
1655  SDLoc dl(GA);
1656  int64_t Offset = GA->getOffset();
1657  auto PtrVT = getPointerTy(DAG.getDataLayout());
1658 
1659  // Get the thread pointer.
1660  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1661  // Generate the TLS symbol address
1662  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1664  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1665 
1666  // Address of the thread local variable is the add of thread
1667  // pointer and the offset of the variable.
1668  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1669 }
1670 
1671 //
1672 // Lower using the general dynamic model for TLS addresses
1673 //
1674 SDValue
1676  SelectionDAG &DAG) const {
1677  SDLoc dl(GA);
1678  int64_t Offset = GA->getOffset();
1679  auto PtrVT = getPointerTy(DAG.getDataLayout());
1680 
1681  // First generate the TLS symbol address
1682  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1684 
1685  // Then, generate the GOT pointer
1686  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1687 
1688  // Add the TLS symbol and the GOT pointer
1689  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1690  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1691 
1692  // Copy over the argument to R0
1693  SDValue InFlag;
1694  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1695  InFlag = Chain.getValue(1);
1696 
1697  return GetDynamicTLSAddr(DAG, Chain, GA, &InFlag, PtrVT,
1698  Hexagon::R0, HexagonII::MO_GDPLT);
1699 }
1700 
1701 //
1702 // Lower TLS addresses.
1703 //
1704 // For now for dynamic models, we only support the general dynamic model.
1705 //
1706 SDValue
1708  SelectionDAG &DAG) const {
1709  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1710 
1711  switch (HTM.getTLSModel(GA->getGlobal())) {
1714  return LowerToTLSGeneralDynamicModel(GA, DAG);
1715  case TLSModel::InitialExec:
1716  return LowerToTLSInitialExecModel(GA, DAG);
1717  case TLSModel::LocalExec:
1718  return LowerToTLSLocalExecModel(GA, DAG);
1719  }
1720  llvm_unreachable("Bogus TLS model");
1721 }
1722 
1723 //===----------------------------------------------------------------------===//
1724 // TargetLowering Implementation
1725 //===----------------------------------------------------------------------===//
1726 
1728  const HexagonSubtarget &ST)
1729  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1730  Subtarget(ST) {
1731  bool IsV4 = !Subtarget.hasV5TOps();
1732  auto &HRI = *Subtarget.getRegisterInfo();
1733  bool UseHVX = Subtarget.useHVXOps();
1734  bool UseHVXSgl = Subtarget.useHVXSglOps();
1735  bool UseHVXDbl = Subtarget.useHVXDblOps();
1736 
1740  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1741 
1744 
1747  else
1749 
1750  // Limits for inline expansion of memcpy/memmove
1757 
1758  //
1759  // Set up register classes.
1760  //
1761 
1762  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1763  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1764  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1765  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1766  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1767  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1768  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1769  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1770  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1771  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1772  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1773 
1774  if (Subtarget.hasV5TOps()) {
1775  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1776  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1777  }
1778 
1779  if (Subtarget.hasV60TOps()) {
1780  if (Subtarget.useHVXSglOps()) {
1781  addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass);
1782  addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass);
1783  addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass);
1784  addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass);
1785  addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);
1786  addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass);
1787  addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);
1788  addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass);
1789  addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass);
1790  } else if (Subtarget.useHVXDblOps()) {
1791  addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass);
1792  addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass);
1793  addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass);
1794  addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass);
1795  addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass);
1796  addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass);
1797  addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass);
1798  addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass);
1799  addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
1800  }
1801  }
1802 
1803  //
1804  // Handling of scalar operations.
1805  //
1806  // All operations default to "legal", except:
1807  // - indexed loads and stores (pre-/post-incremented),
1808  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1809  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1810  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1811  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1812  // which default to "expand" for at least one type.
1813 
1814  // Misc operations.
1815  setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1816  setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1817 
1829 
1830  // Custom legalize GlobalAddress nodes into CONST32.
1834 
1835  // Hexagon needs to optimize cases with negative constants.
1838 
1839  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1843 
1847 
1848  if (EmitJumpTables)
1850  else
1851  setMinimumJumpTableEntries(std::numeric_limits<int>::max());
1853 
1854  // Hexagon has instructions for add/sub with carry. The problem with
1855  // modeling these instructions is that they produce 2 results: Rdd and Px.
1856  // To model the update of Px, we will have to use Defs[p0..p3] which will
1857  // cause any predicate live range to spill. So, we pretend we dont't have
1858  // these instructions.
1875 
1876  // Only add and sub that detect overflow are the saturating ones.
1877  for (MVT VT : MVT::integer_valuetypes()) {
1882  }
1883 
1888 
1889  // In V5, popcount can count # of 1s in i64 but returns i32.
1890  // On V4 it will be expanded (set later).
1895 
1896  // We custom lower i64 to i64 mul, so that it is not considered as a legal
1897  // operation. There is a pattern that will match i64 mul and transform it
1898  // to a series of instructions.
1900 
1901  for (unsigned IntExpOp :
1906  setOperationAction(IntExpOp, MVT::i32, Expand);
1907  setOperationAction(IntExpOp, MVT::i64, Expand);
1908  }
1909 
1910  for (unsigned FPExpOp :
1913  setOperationAction(FPExpOp, MVT::f32, Expand);
1914  setOperationAction(FPExpOp, MVT::f64, Expand);
1915  }
1916 
1917  // No extending loads from i32.
1918  for (MVT VT : MVT::integer_valuetypes()) {
1922  }
1923  // Turn FP truncstore into trunc + store.
1925  // Turn FP extload into load/fpextend.
1926  for (MVT VT : MVT::fp_valuetypes())
1928 
1929  // Expand BR_CC and SELECT_CC for all integer and fp types.
1930  for (MVT VT : MVT::integer_valuetypes()) {
1933  }
1934  for (MVT VT : MVT::fp_valuetypes()) {
1937  }
1939 
1940  //
1941  // Handling of vector operations.
1942  //
1943 
1944  // Custom lower v4i16 load only. Let v4i16 store to be
1945  // promoted for now.
1946  promoteLdStType(MVT::v4i8, MVT::i32);
1947  promoteLdStType(MVT::v2i16, MVT::i32);
1948  promoteLdStType(MVT::v8i8, MVT::i64);
1949  promoteLdStType(MVT::v2i32, MVT::i64);
1950 
1955 
1956  // Set the action for vector operations to "expand", then override it with
1957  // either "custom" or "legal" for specific cases.
1958  static const unsigned VectExpOps[] = {
1959  // Integer arithmetic:
1964  // Logical/bit:
1967  // Floating point arithmetic/math functions:
1974  // Misc:
1976  // Vector:
1981  };
1982 
1983  for (MVT VT : MVT::vector_valuetypes()) {
1984  for (unsigned VectExpOp : VectExpOps)
1985  setOperationAction(VectExpOp, VT, Expand);
1986 
1987  // Expand all extending loads and truncating stores:
1988  for (MVT TargetVT : MVT::vector_valuetypes()) {
1989  if (TargetVT == VT)
1990  continue;
1991  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1992  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1993  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1994  setTruncStoreAction(VT, TargetVT, Expand);
1995  }
1996 
1997  // Normalize all inputs to SELECT to be vectors of i32.
1998  if (VT.getVectorElementType() != MVT::i32) {
1999  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
2001  AddPromotedToType(ISD::SELECT, VT, VT32);
2002  }
2006  }
2007 
2008  // Types natively supported:
2009  for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
2011  MVT::v2i32, MVT::v1i64}) {
2018 
2019  setOperationAction(ISD::ADD, NativeVT, Legal);
2020  setOperationAction(ISD::SUB, NativeVT, Legal);
2021  setOperationAction(ISD::MUL, NativeVT, Legal);
2022  setOperationAction(ISD::AND, NativeVT, Legal);
2023  setOperationAction(ISD::OR, NativeVT, Legal);
2024  setOperationAction(ISD::XOR, NativeVT, Legal);
2025  }
2026 
2031 
2032  if (UseHVX) {
2033  if (UseHVXSgl) {
2038  // We try to generate the vpack{e/o} instructions. If we fail
2039  // we fall back upon ExpandOp.
2045  } else if (UseHVXDbl) {
2050  // We try to generate the vpack{e/o} instructions. If we fail
2051  // we fall back upon ExpandOp.
2058  } else {
2059  llvm_unreachable("Unrecognized HVX mode");
2060  }
2061  }
2062  // Subtarget-specific operation actions.
2063  //
2064  if (Subtarget.hasV5TOps()) {
2069 
2072 
2085  } else { // V4
2095 
2100 
2101  // Expand these operations for both f32 and f64:
2102  for (unsigned FPExpOpV4 :
2104  setOperationAction(FPExpOpV4, MVT::f32, Expand);
2105  setOperationAction(FPExpOpV4, MVT::f64, Expand);
2106  }
2107 
2108  for (ISD::CondCode FPExpCCV4 :
2110  ISD::SETUO, ISD::SETO}) {
2111  setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
2112  setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
2113  }
2114  }
2115 
2116  // Handling of indexed loads/stores: default is "expand".
2117  //
2118  for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
2121  }
2122 
2123  if (UseHVXSgl) {
2128  }
2129  } else if (UseHVXDbl) {
2134  }
2135  }
2136 
2138 
2139  //
2140  // Library calls for unsupported operations
2141  //
2142  bool FastMath = EnableFastMath;
2143 
2144  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
2145  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
2146  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
2147  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
2148  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
2149  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
2150  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
2151  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
2152 
2153  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
2154  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
2155  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
2156  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
2157  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
2158  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
2159 
2160  if (IsV4) {
2161  // Handle single-precision floating point operations on V4.
2162  if (FastMath) {
2163  setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
2164  setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
2165  setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
2166  setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
2167  setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
2168  // Double-precision compares.
2169  setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
2170  setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
2171  } else {
2172  setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
2173  setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
2174  setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
2175  setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
2176  setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
2177  // Double-precision compares.
2178  setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
2179  setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
2180  }
2181  }
2182 
2183  // This is the only fast library function for sqrtd.
2184  if (FastMath)
2185  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
2186 
2187  // Prefix is: nothing for "slow-math",
2188  // "fast2_" for V4 fast-math and V5+ fast-math double-precision
2189  // (actually, keep fast-math and fast-math2 separate for now)
2190  if (FastMath) {
2191  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
2192  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
2193  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
2194  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
2195  // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
2196  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
2197  } else {
2198  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
2199  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
2200  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
2201  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
2202  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
2203  }
2204 
2205  if (Subtarget.hasV5TOps()) {
2206  if (FastMath)
2207  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
2208  else
2209  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
2210  } else {
2211  // V4
2212  setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
2213  setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
2214  setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
2215  setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
2216  setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
2217  setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
2218  setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
2219  setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
2220  setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
2221  setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
2222  setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
2223  setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
2224  setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
2225  setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
2226  setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
2227  setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
2228  setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
2229  setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
2230  setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
2231  setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
2232  setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
2233  setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
2234  setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
2235  setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
2236  setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
2237  setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
2238  setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
2239  setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
2240  setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
2241  setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
2242  }
2243 
2244  // These cause problems when the shift amount is non-constant.
2245  setLibcallName(RTLIB::SHL_I128, nullptr);
2246  setLibcallName(RTLIB::SRL_I128, nullptr);
2247  setLibcallName(RTLIB::SRA_I128, nullptr);
2248 }
2249 
2250 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
2251  switch ((HexagonISD::NodeType)Opcode) {
2252  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
2253  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
2254  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
2255  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
2256  case HexagonISD::CALL: return "HexagonISD::CALL";
2257  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
2258  case HexagonISD::CALLR: return "HexagonISD::CALLR";
2259  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
2260  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
2261  case HexagonISD::CONST32: return "HexagonISD::CONST32";
2262  case HexagonISD::CP: return "HexagonISD::CP";
2263  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
2264  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
2265  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
2266  case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
2267  case HexagonISD::INSERT: return "HexagonISD::INSERT";
2268  case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
2269  case HexagonISD::JT: return "HexagonISD::JT";
2270  case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
2271  case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT";
2272  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
2273  case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
2274  case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
2275  case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
2276  case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
2277  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
2278  case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
2279  case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
2280  case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
2281  case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
2282  case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
2283  case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
2284  case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
2285  case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
2286  case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
2287  case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
2288  case HexagonISD::VPACK: return "HexagonISD::VPACK";
2289  case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
2290  case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
2291  case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
2292  case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
2293  case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
2294  case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
2295  case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
2296  case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
2297  case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
2298  case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
2299  case HexagonISD::OP_END: break;
2300  }
2301  return nullptr;
2302 }
2303 
2305  EVT MTy1 = EVT::getEVT(Ty1);
2306  EVT MTy2 = EVT::getEVT(Ty2);
2307  if (!MTy1.isSimple() || !MTy2.isSimple())
2308  return false;
2309  return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
2310 }
2311 
2313  if (!VT1.isSimple() || !VT2.isSimple())
2314  return false;
2315  return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
2316 }
2317 
2319  return isOperationLegalOrCustom(ISD::FMA, VT);
2320 }
2321 
2322 // Should we expand the build vector with shuffles?
2324  unsigned DefinedValues) const {
2325  // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2326  EVT EltVT = VT.getVectorElementType();
2327  int EltBits = EltVT.getSizeInBits();
2328  if ((EltBits != 8) && (EltBits != 16))
2329  return false;
2330 
2331  return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
2332 }
2333 
2335  int even_start = -2;
2336  int odd_start = -1;
2337  size_t mask_len = Mask.size();
2338  for (auto idx : Mask) {
2339  if ((idx - even_start) == 2)
2340  even_start = idx;
2341  else
2342  break;
2343  }
2344  if (even_start == (int)(mask_len * 2) - 2)
2345  return StridedLoadKind::Even;
2346  for (auto idx : Mask) {
2347  if ((idx - odd_start) == 2)
2348  odd_start = idx;
2349  else
2350  break;
2351  }
2352  if (odd_start == (int)(mask_len * 2) - 1)
2353  return StridedLoadKind::Odd;
2354 
2355  return StridedLoadKind::NoPattern;
2356 }
2357 
2359  EVT VT) const {
2360  if (Subtarget.useHVXOps())
2361  return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
2362  return true;
2363 }
2364 
2365 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2366 // to select data from, V3 is the permutation.
2367 SDValue
2369  const {
2370  const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2371  SDValue V1 = Op.getOperand(0);
2372  SDValue V2 = Op.getOperand(1);
2373  SDLoc dl(Op);
2374  EVT VT = Op.getValueType();
2375  bool UseHVX = Subtarget.useHVXOps();
2376 
2377  if (V2.isUndef())
2378  V2 = V1;
2379 
2380  if (SVN->isSplat()) {
2381  int Lane = SVN->getSplatIndex();
2382  if (Lane == -1) Lane = 0;
2383 
2384  // Test if V1 is a SCALAR_TO_VECTOR.
2385  if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2386  return createSplat(DAG, dl, VT, V1.getOperand(0));
2387 
2388  // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
2389  // (and probably will turn into a SCALAR_TO_VECTOR once legalization
2390  // reaches it).
2391  if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2392  !isa<ConstantSDNode>(V1.getOperand(0))) {
2393  bool IsScalarToVector = true;
2394  for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
2395  if (!V1.getOperand(i).isUndef()) {
2396  IsScalarToVector = false;
2397  break;
2398  }
2399  }
2400  if (IsScalarToVector)
2401  return createSplat(DAG, dl, VT, V1.getOperand(0));
2402  }
2403  return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
2404  }
2405 
2406  if (UseHVX) {
2407  ArrayRef<int> Mask = SVN->getMask();
2408  size_t MaskLen = Mask.size();
2409  int ElemSizeInBits = VT.getScalarSizeInBits();
2410  if ((Subtarget.useHVXSglOps() && (ElemSizeInBits * MaskLen) == 64 * 8) ||
2411  (Subtarget.useHVXDblOps() && (ElemSizeInBits * MaskLen) == 128 * 8)) {
2412  // Return 1 for odd and 2 of even
2413  StridedLoadKind Pattern = isStridedLoad(Mask);
2414 
2415  if (Pattern == StridedLoadKind::NoPattern)
2416  return SDValue();
2417 
2418  SDValue Vec0 = Op.getOperand(0);
2419  SDValue Vec1 = Op.getOperand(1);
2420  SDValue StridePattern = DAG.getConstant(Pattern, dl, MVT::i32);
2421  SDValue Ops[] = { Vec1, Vec0, StridePattern };
2422  return DAG.getNode(HexagonISD::VPACK, dl, VT, Ops);
2423  }
2424  // We used to assert in the "else" part here, but that is bad for Halide
2425  // Halide creates intermediate double registers by interleaving two
2426  // concatenated vector registers. The interleaving requires vector_shuffle
2427  // nodes and we shouldn't barf on a double register result of a
2428  // vector_shuffle because it is most likely an intermediate result.
2429  }
2430  // FIXME: We need to support more general vector shuffles. See
2431  // below the comment from the ARM backend that deals in the general
2432  // case with the vector shuffles. For now, let expand handle these.
2433  return SDValue();
2434 
2435  // If the shuffle is not directly supported and it has 4 elements, use
2436  // the PerfectShuffle-generated table to synthesize it from other shuffles.
2437 }
2438 
2439 // If BUILD_VECTOR has same base element repeated several times,
2440 // report true.
2442  unsigned NElts = BVN->getNumOperands();
2443  SDValue V0 = BVN->getOperand(0);
2444 
2445  for (unsigned i = 1, e = NElts; i != e; ++i) {
2446  if (BVN->getOperand(i) != V0)
2447  return false;
2448  }
2449  return true;
2450 }
2451 
2452 // Lower a vector shift. Try to convert
2453 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2454 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
2455 SDValue
2457  BuildVectorSDNode *BVN = nullptr;
2458  SDValue V1 = Op.getOperand(0);
2459  SDValue V2 = Op.getOperand(1);
2460  SDValue V3;
2461  SDLoc dl(Op);
2462  EVT VT = Op.getValueType();
2463 
2464  if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
2465  isCommonSplatElement(BVN))
2466  V3 = V2;
2467  else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
2468  isCommonSplatElement(BVN))
2469  V3 = V1;
2470  else
2471  return SDValue();
2472 
2473  SDValue CommonSplat = BVN->getOperand(0);
2474  SDValue Result;
2475 
2476  if (VT.getSimpleVT() == MVT::v4i16) {
2477  switch (Op.getOpcode()) {
2478  case ISD::SRA:
2479  Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
2480  break;
2481  case ISD::SHL:
2482  Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
2483  break;
2484  case ISD::SRL:
2485  Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
2486  break;
2487  default:
2488  return SDValue();
2489  }
2490  } else if (VT.getSimpleVT() == MVT::v2i32) {
2491  switch (Op.getOpcode()) {
2492  case ISD::SRA:
2493  Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
2494  break;
2495  case ISD::SHL:
2496  Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
2497  break;
2498  case ISD::SRL:
2499  Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
2500  break;
2501  default:
2502  return SDValue();
2503  }
2504  } else {
2505  return SDValue();
2506  }
2507 
2508  return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2509 }
2510 
2511 SDValue
2513  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2514  SDLoc dl(Op);
2515  EVT VT = Op.getValueType();
2516 
2517  unsigned Size = VT.getSizeInBits();
2518 
2519  // Only handle vectors of 64 bits or shorter.
2520  if (Size > 64)
2521  return SDValue();
2522 
2523  APInt APSplatBits, APSplatUndef;
2524  unsigned SplatBitSize;
2525  bool HasAnyUndefs;
2526  unsigned NElts = BVN->getNumOperands();
2527 
2528  // Try to generate a SPLAT instruction.
2529  if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
2530  (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2531  HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
2532  unsigned SplatBits = APSplatBits.getZExtValue();
2533  int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
2534  (32 - SplatBitSize));
2535  return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
2536  }
2537 
2538  // Try to generate COMBINE to build v2i32 vectors.
2539  if (VT.getSimpleVT() == MVT::v2i32) {
2540  SDValue V0 = BVN->getOperand(0);
2541  SDValue V1 = BVN->getOperand(1);
2542 
2543  if (V0.isUndef())
2544  V0 = DAG.getConstant(0, dl, MVT::i32);
2545  if (V1.isUndef())
2546  V1 = DAG.getConstant(0, dl, MVT::i32);
2547 
2550  // If the element isn't a constant, it is in a register:
2551  // generate a COMBINE Register Register instruction.
2552  if (!C0 || !C1)
2553  return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2554 
2555  // If one of the operands is an 8 bit integer constant, generate
2556  // a COMBINE Immediate Immediate instruction.
2557  if (isInt<8>(C0->getSExtValue()) ||
2558  isInt<8>(C1->getSExtValue()))
2559  return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2560  }
2561 
2562  // Try to generate a S2_packhl to build v2i16 vectors.
2563  if (VT.getSimpleVT() == MVT::v2i16) {
2564  for (unsigned i = 0, e = NElts; i != e; ++i) {
2565  if (BVN->getOperand(i).isUndef())
2566  continue;
2568  // If the element isn't a constant, it is in a register:
2569  // generate a S2_packhl instruction.
2570  if (!Cst) {
2571  SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2572  BVN->getOperand(1), BVN->getOperand(0));
2573 
2574  return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
2575  pack);
2576  }
2577  }
2578  }
2579 
2580  // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2581  // and insert_vector_elt for all the other cases.
2582  uint64_t Res = 0;
2583  unsigned EltSize = Size / NElts;
2584  SDValue ConstVal;
2585  uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2586  bool HasNonConstantElements = false;
2587 
2588  for (unsigned i = 0, e = NElts; i != e; ++i) {
2589  // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2590  // combine, const64, etc. are Big Endian.
2591  unsigned OpIdx = NElts - i - 1;
2592  SDValue Operand = BVN->getOperand(OpIdx);
2593  if (Operand.isUndef())
2594  continue;
2595 
2596  int64_t Val = 0;
2597  if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2598  Val = Cst->getSExtValue();
2599  else
2600  HasNonConstantElements = true;
2601 
2602  Val &= Mask;
2603  Res = (Res << EltSize) | Val;
2604  }
2605 
2606  if (Size > 64)
2607  return SDValue();
2608 
2609  if (Size == 64)
2610  ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2611  else
2612  ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2613 
2614  // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2615  // ConstVal, the constant part of the vector.
2616  if (HasNonConstantElements) {
2617  EVT EltVT = VT.getVectorElementType();
2618  SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2619  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2620  DAG.getConstant(32, dl, MVT::i64));
2621 
2622  for (unsigned i = 0, e = NElts; i != e; ++i) {
2623  // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2624  // is Big Endian.
2625  unsigned OpIdx = NElts - i - 1;
2626  SDValue Operand = BVN->getOperand(OpIdx);
2627  if (isa<ConstantSDNode>(Operand))
2628  // This operand is already in ConstVal.
2629  continue;
2630 
2631  if (VT.getSizeInBits() == 64 &&
2632  Operand.getValueSizeInBits() == 32) {
2633  SDValue C = DAG.getConstant(0, dl, MVT::i32);
2634  Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2635  }
2636 
2637  SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2638  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2639  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2640  const SDValue Ops[] = {ConstVal, Operand, Combined};
2641 
2642  if (VT.getSizeInBits() == 32)
2643  ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2644  else
2645  ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2646  }
2647  }
2648 
2649  return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2650 }
2651 
2652 SDValue
2654  SelectionDAG &DAG) const {
2655  SDLoc dl(Op);
2656  bool UseHVX = Subtarget.useHVXOps();
2657  EVT VT = Op.getValueType();
2658  unsigned NElts = Op.getNumOperands();
2659  SDValue Vec0 = Op.getOperand(0);
2660  EVT VecVT = Vec0.getValueType();
2661  unsigned Width = VecVT.getSizeInBits();
2662 
2663  if (NElts == 2) {
2664  MVT ST = VecVT.getSimpleVT();
2665  // We are trying to concat two v2i16 to a single v4i16, or two v4i8
2666  // into a single v8i8.
2667  if (ST == MVT::v2i16 || ST == MVT::v4i8)
2668  return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
2669 
2670  if (UseHVX) {
2671  assert((Width == 64*8 && Subtarget.useHVXSglOps()) ||
2672  (Width == 128*8 && Subtarget.useHVXDblOps()));
2673  SDValue Vec1 = Op.getOperand(1);
2674  MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;
2675  MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;
2676  SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2677  SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2678  SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
2679  return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2680  }
2681  }
2682 
2683  if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
2684  return SDValue();
2685 
2686  SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
2687  SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
2688  SDValue W = DAG.getConstant(Width, dl, MVT::i64);
2689  // Create the "width" part of the argument to insert_rp/insertp_rp.
2690  SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2691  SDValue V = C0;
2692 
2693  for (unsigned i = 0, e = NElts; i != e; ++i) {
2694  unsigned N = NElts-i-1;
2695  SDValue OpN = Op.getOperand(N);
2696 
2697  if (VT.getSizeInBits() == 64 && OpN.getValueSizeInBits() == 32) {
2698  SDValue C = DAG.getConstant(0, dl, MVT::i32);
2699  OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
2700  }
2701  SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
2702  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2703  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2704  if (VT.getSizeInBits() == 32)
2705  V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
2706  else if (VT.getSizeInBits() == 64)
2707  V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
2708  else
2709  return SDValue();
2710  }
2711 
2712  return DAG.getNode(ISD::BITCAST, dl, VT, V);
2713 }
2714 
2715 SDValue
2716 HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
2717  SelectionDAG &DAG) const {
2718  EVT VT = Op.getOperand(0).getValueType();
2719  SDLoc dl(Op);
2720  bool UseHVX = Subtarget.useHVXOps();
2721  bool UseHVXSgl = Subtarget.useHVXSglOps();
2722  // Just in case...
2723 
2724  if (!VT.isVector() || !UseHVX)
2725  return SDValue();
2726 
2727  EVT ResVT = Op.getValueType();
2728  unsigned ResSize = ResVT.getSizeInBits();
2729  unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);
2730  unsigned OpSize = VT.getSizeInBits();
2731 
2732  // We deal only with cases where the result is the vector size
2733  // and the vector operand is a double register.
2734  if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
2735  !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
2736  return SDValue();
2737 
2739  if (!Cst)
2740  return SDValue();
2741  unsigned Val = Cst->getZExtValue();
2742 
2743  // These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
2744  if (Val == 0) {
2745  SDValue Vec = Op.getOperand(0);
2746  return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
2747  }
2748 
2749  if (ResVT.getVectorNumElements() == Val) {
2750  SDValue Vec = Op.getOperand(0);
2751  return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
2752  }
2753 
2754  return SDValue();
2755 }
2756 
2757 SDValue
2759  SelectionDAG &DAG) const {
2760  // If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
2761  // be able to simplify it to an EXTRACT_SUBREG.
2762  if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
2764  return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
2765 
2766  EVT VT = Op.getValueType();
2767  int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2768  SDLoc dl(Op);
2769  SDValue Idx = Op.getOperand(1);
2770  SDValue Vec = Op.getOperand(0);
2771  EVT VecVT = Vec.getValueType();
2772  EVT EltVT = VecVT.getVectorElementType();
2773  int EltSize = EltVT.getSizeInBits();
2775  EltSize : VTN * EltSize, dl, MVT::i64);
2776 
2777  // Constant element number.
2778  if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2779  uint64_t X = CI->getZExtValue();
2780  SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2781  const SDValue Ops[] = {Vec, Width, Offset};
2782 
2783  ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2784  assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
2785 
2786  SDValue N;
2787  MVT SVT = VecVT.getSimpleVT();
2788  uint64_t W = CW->getZExtValue();
2789 
2790  if (W == 32) {
2791  // Translate this node into EXTRACT_SUBREG.
2792  unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
2793 
2794  if (X == 0)
2795  Subreg = Hexagon::isub_lo;
2796  else if (SVT == MVT::v2i32 && X == 1)
2797  Subreg = Hexagon::isub_hi;
2798  else if (SVT == MVT::v4i16 && X == 2)
2799  Subreg = Hexagon::isub_hi;
2800  else if (SVT == MVT::v8i8 && X == 4)
2801  Subreg = Hexagon::isub_hi;
2802  else
2803  llvm_unreachable("Bad offset");
2804  N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2805 
2806  } else if (SVT.getSizeInBits() == 32) {
2807  N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2808  } else if (SVT.getSizeInBits() == 64) {
2809  N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2810  if (VT.getSizeInBits() == 32)
2811  N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2812  } else
2813  return SDValue();
2814 
2815  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2816  }
2817 
2818  // Variable element number.
2819  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2820  DAG.getConstant(EltSize, dl, MVT::i32));
2821  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2822  DAG.getConstant(32, dl, MVT::i64));
2823  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2824 
2825  const SDValue Ops[] = {Vec, Combined};
2826 
2827  SDValue N;
2828  if (VecVT.getSizeInBits() == 32) {
2829  N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2830  } else {
2831  N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2832  if (VT.getSizeInBits() == 32)
2833  N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2834  }
2835  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2836 }
2837 
2838 SDValue
2840  SelectionDAG &DAG) const {
2841  EVT VT = Op.getValueType();
2842  int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2843  SDLoc dl(Op);
2844  SDValue Vec = Op.getOperand(0);
2845  SDValue Val = Op.getOperand(1);
2846  SDValue Idx = Op.getOperand(2);
2847  EVT VecVT = Vec.getValueType();
2848  EVT EltVT = VecVT.getVectorElementType();
2849  int EltSize = EltVT.getSizeInBits();
2850  SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2851  EltSize : VTN * EltSize, dl, MVT::i64);
2852 
2853  if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2854  SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2855  const SDValue Ops[] = {Vec, Val, Width, Offset};
2856 
2857  SDValue N;
2858  if (VT.getSizeInBits() == 32)
2859  N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2860  else if (VT.getSizeInBits() == 64)
2861  N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2862  else
2863  return SDValue();
2864 
2865  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2866  }
2867 
2868  // Variable element number.
2869  SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2870  DAG.getConstant(EltSize, dl, MVT::i32));
2871  SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2872  DAG.getConstant(32, dl, MVT::i64));
2873  SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2874 
2875  if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
2876  SDValue C = DAG.getConstant(0, dl, MVT::i32);
2877  Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2878  }
2879 
2880  const SDValue Ops[] = {Vec, Val, Combined};
2881 
2882  SDValue N;
2883  if (VT.getSizeInBits() == 32)
2884  N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2885  else if (VT.getSizeInBits() == 64)
2886  N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2887  else
2888  return SDValue();
2889 
2890  return DAG.getNode(ISD::BITCAST, dl, VT, N);
2891 }
2892 
2893 bool
2895  // Assuming the caller does not have either a signext or zeroext modifier, and
2896  // only one value is accepted, any reasonable truncation is allowed.
2897  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2898  return false;
2899 
2900  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2901  // fragile at the moment: any support for multiple value returns would be
2902  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2903  return Ty1->getPrimitiveSizeInBits() <= 32;
2904 }
2905 
2906 SDValue
2908  SDValue Chain = Op.getOperand(0);
2909  SDValue Offset = Op.getOperand(1);
2910  SDValue Handler = Op.getOperand(2);
2911  SDLoc dl(Op);
2912  auto PtrVT = getPointerTy(DAG.getDataLayout());
2913 
2914  // Mark function as containing a call to EH_RETURN.
2915  HexagonMachineFunctionInfo *FuncInfo =
2917  FuncInfo->setHasEHReturn();
2918 
2919  unsigned OffsetReg = Hexagon::R28;
2920 
2921  SDValue StoreAddr =
2922  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2923  DAG.getIntPtrConstant(4, dl));
2924  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2925  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2926 
2927  // Not needed we already use it as explict input to EH_RETURN.
2928  // MF.getRegInfo().addLiveOut(OffsetReg);
2929 
2930  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2931 }
2932 
2933 SDValue
2935  unsigned Opc = Op.getOpcode();
2936  switch (Opc) {
2937  default:
2938 #ifndef NDEBUG
2939  Op.getNode()->dumpr(&DAG);
2940  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2941  errs() << "Check for a non-legal type in this operation\n";
2942 #endif
2943  llvm_unreachable("Should not custom lower this!");
2944  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2945  case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2946  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2947  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2948  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2949  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2950  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2951  case ISD::SRA:
2952  case ISD::SHL:
2953  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2954  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2955  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2956  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2957  // Frame & Return address. Currently unimplemented.
2958  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2959  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2960  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2961  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2962  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2963  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2964  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2965  case ISD::VASTART: return LowerVASTART(Op, DAG);
2966  // Custom lower some vector loads.
2967  case ISD::LOAD: return LowerLOAD(Op, DAG);
2968  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2969  case ISD::SETCC: return LowerSETCC(Op, DAG);
2970  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2971  case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2972  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2973  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2974  case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2975  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2976  }
2977 }
2978 
2979 /// Returns relocation base for the given PIC jumptable.
2980 SDValue
2982  SelectionDAG &DAG) const {
2983  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2984  EVT VT = Table.getValueType();
2986  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2987 }
2988 
2989 //===----------------------------------------------------------------------===//
2990 // Inline Assembly Support
2991 //===----------------------------------------------------------------------===//
2992 
2995  if (Constraint.size() == 1) {
2996  switch (Constraint[0]) {
2997  case 'q':
2998  case 'v':
2999  if (Subtarget.useHVXOps())
3000  return C_Register;
3001  break;
3002  }
3003  }
3004  return TargetLowering::getConstraintType(Constraint);
3005 }
3006 
3007 std::pair<unsigned, const TargetRegisterClass*>
3009  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3010  bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
3011 
3012  if (Constraint.size() == 1) {
3013  switch (Constraint[0]) {
3014  case 'r': // R0-R31
3015  switch (VT.SimpleTy) {
3016  default:
3017  llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
3018  case MVT::i1:
3019  case MVT::i8:
3020  case MVT::i16:
3021  case MVT::i32:
3022  case MVT::f32:
3023  return std::make_pair(0U, &Hexagon::IntRegsRegClass);
3024  case MVT::i64:
3025  case MVT::f64:
3026  return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
3027  }
3028  case 'q': // q0-q3
3029  switch (VT.SimpleTy) {
3030  default:
3031  llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
3032  case MVT::v1024i1:
3033  case MVT::v512i1:
3034  case MVT::v32i16:
3035  case MVT::v16i32:
3036  case MVT::v64i8:
3037  case MVT::v8i64:
3038  return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
3039  }
3040  case 'v': // V0-V31
3041  switch (VT.SimpleTy) {
3042  default:
3043  llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
3044  case MVT::v16i32:
3045  case MVT::v32i16:
3046  case MVT::v64i8:
3047  case MVT::v8i64:
3048  return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
3049  case MVT::v32i32:
3050  case MVT::v64i16:
3051  case MVT::v16i64:
3052  case MVT::v128i8:
3053  if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
3054  return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
3055  return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
3056  case MVT::v256i8:
3057  case MVT::v128i16:
3058  case MVT::v64i32:
3059  case MVT::v32i64:
3060  return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
3061  }
3062 
3063  default:
3064  llvm_unreachable("Unknown asm register class");
3065  }
3066  }
3067 
3068  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3069 }
3070 
3071 /// isFPImmLegal - Returns true if the target can instruction select the
3072 /// specified FP immediate natively. If false, the legalizer will
3073 /// materialize the FP immediate as a load from a constant pool.
3075  return Subtarget.hasV5TOps();
3076 }
3077 
3078 /// isLegalAddressingMode - Return true if the addressing mode represented by
3079 /// AM is legal for this target, for a load/store of the specified type.
3081  const AddrMode &AM, Type *Ty,
3082  unsigned AS) const {
3083  if (Ty->isSized()) {
3084  // When LSR detects uses of the same base address to access different
3085  // types (e.g. unions), it will assume a conservative type for these
3086  // uses:
3087  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3088  // The type Ty passed here would then be "void". Skip the alignment
3089  // checks, but do not return false right away, since that confuses
3090  // LSR into crashing.
3091  unsigned A = DL.getABITypeAlignment(Ty);
3092  // The base offset must be a multiple of the alignment.
3093  if ((AM.BaseOffs % A) != 0)
3094  return false;
3095  // The shifted offset must fit in 11 bits.
3096  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3097  return false;
3098  }
3099 
3100  // No global is ever allowed as a base.
3101  if (AM.BaseGV)
3102  return false;
3103 
3104  int Scale = AM.Scale;
3105  if (Scale < 0)
3106  Scale = -Scale;
3107  switch (Scale) {
3108  case 0: // No scale reg, "r+i", "r", or just "i".
3109  break;
3110  default: // No scaled addressing mode.
3111  return false;
3112  }
3113  return true;
3114 }
3115 
3116 /// Return true if folding a constant offset with the given GlobalAddress is
3117 /// legal. It is frequently not legal in PIC relocation models.
3119  const {
3120  return HTM.getRelocationModel() == Reloc::Static;
3121 }
3122 
3123 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3124 /// icmp immediate, that is the target has icmp instructions which can compare
3125 /// a register against the immediate without having to materialize the
3126 /// immediate into a register.
3128  return Imm >= -512 && Imm <= 511;
3129 }
3130 
3131 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3132 /// for tail call optimization. Targets which want to do tail call
3133 /// optimization should implement this function.
3135  SDValue Callee,
3136  CallingConv::ID CalleeCC,
3137  bool isVarArg,
3138  bool isCalleeStructRet,
3139  bool isCallerStructRet,
3140  const SmallVectorImpl<ISD::OutputArg> &Outs,
3141  const SmallVectorImpl<SDValue> &OutVals,
3143  SelectionDAG& DAG) const {
3144  const Function *CallerF = DAG.getMachineFunction().getFunction();
3145  CallingConv::ID CallerCC = CallerF->getCallingConv();
3146  bool CCMatch = CallerCC == CalleeCC;
3147 
3148  // ***************************************************************************
3149  // Look for obvious safe cases to perform tail call optimization that do not
3150  // require ABI changes.
3151  // ***************************************************************************
3152 
3153  // If this is a tail call via a function pointer, then don't do it!
3154  if (!isa<GlobalAddressSDNode>(Callee) &&
3155  !isa<ExternalSymbolSDNode>(Callee)) {
3156  return false;
3157  }
3158 
3159  // Do not optimize if the calling conventions do not match and the conventions
3160  // used are not C or Fast.
3161  if (!CCMatch) {
3162  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3163  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3164  // If R & E, then ok.
3165  if (!R || !E)
3166  return false;
3167  }
3168 
3169  // Do not tail call optimize vararg calls.
3170  if (isVarArg)
3171  return false;
3172 
3173  // Also avoid tail call optimization if either caller or callee uses struct
3174  // return semantics.
3175  if (isCalleeStructRet || isCallerStructRet)
3176  return false;
3177 
3178  // In addition to the cases above, we also disable Tail Call Optimization if
3179  // the calling convention code that at least one outgoing argument needs to
3180  // go on the stack. We cannot check that here because at this point that
3181  // information is not available.
3182  return true;
3183 }
3184 
3185 /// Returns the target specific optimal type for load and store operations as
3186 /// a result of memset, memcpy, and memmove lowering.
3187 ///
3188 /// If DstAlign is zero that means it's safe to destination alignment can
3189 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3190 /// a need to check it against alignment requirement, probably because the
3191 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3192 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3193 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3194 /// does not need to be loaded. It returns EVT::Other if the type should be
3195 /// determined using generic target-independent logic.
3197  unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3198  bool MemcpyStrSrc, MachineFunction &MF) const {
3199 
3200  auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3201  return (GivenA % MinA) == 0;
3202  };
3203 
3204  if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3205  return MVT::i64;
3206  if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3207  return MVT::i32;
3208  if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3209  return MVT::i16;
3210 
3211  return MVT::Other;
3212 }
3213 
3215  unsigned AS, unsigned Align, bool *Fast) const {
3216  if (Fast)
3217  *Fast = false;
3218 
3219  switch (VT.getSimpleVT().SimpleTy) {
3220  default:
3221  return false;
3222  case MVT::v64i8:
3223  case MVT::v128i8:
3224  case MVT::v256i8:
3225  case MVT::v32i16:
3226  case MVT::v64i16:
3227  case MVT::v128i16:
3228  case MVT::v16i32:
3229  case MVT::v32i32:
3230  case MVT::v64i32:
3231  case MVT::v8i64:
3232  case MVT::v16i64:
3233  case MVT::v32i64:
3234  return true;
3235  }
3236  return false;
3237 }
3238 
3239 std::pair<const TargetRegisterClass*, uint8_t>
3241  MVT VT) const {
3242  const TargetRegisterClass *RRC = nullptr;
3243 
3244  uint8_t Cost = 1;
3245  switch (VT.SimpleTy) {
3246  default:
3248  case MVT::v64i8:
3249  case MVT::v32i16:
3250  case MVT::v16i32:
3251  case MVT::v8i64:
3252  RRC = &Hexagon::VectorRegsRegClass;
3253  break;
3254  case MVT::v128i8:
3255  case MVT::v64i16:
3256  case MVT::v32i32:
3257  case MVT::v16i64:
3258  if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
3259  Subtarget.useHVXDblOps())
3260  RRC = &Hexagon::VectorRegs128BRegClass;
3261  else
3262  RRC = &Hexagon::VecDblRegsRegClass;
3263  break;
3264  case MVT::v256i8:
3265  case MVT::v128i16:
3266  case MVT::v64i32:
3267  case MVT::v32i64:
3268  RRC = &Hexagon::VecDblRegs128BRegClass;
3269  break;
3270  }
3271  return std::make_pair(RRC, Cost);
3272 }
3273 
3275  AtomicOrdering Ord) const {
3276  BasicBlock *BB = Builder.GetInsertBlock();
3277  Module *M = BB->getParent()->getParent();
3278  Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
3279  unsigned SZ = Ty->getPrimitiveSizeInBits();
3280  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3281  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3282  : Intrinsic::hexagon_L4_loadd_locked;
3283  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3284  return Builder.CreateCall(Fn, Addr, "larx");
3285 }
3286 
3287 /// Perform a store-conditional operation to Addr. Return the status of the
3288 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3290  Value *Val, Value *Addr, AtomicOrdering Ord) const {
3291  BasicBlock *BB = Builder.GetInsertBlock();
3292  Module *M = BB->getParent()->getParent();
3293  Type *Ty = Val->getType();
3294  unsigned SZ = Ty->getPrimitiveSizeInBits();
3295  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3296  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3297  : Intrinsic::hexagon_S4_stored_locked;
3298  Value *Fn = Intrinsic::getDeclaration(M, IntID);
3299  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3300  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3301  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3302  return Ext;
3303 }
3304 
3307  // Do not expand loads and stores that don't exceed 64 bits.
3308  return LI->getType()->getPrimitiveSizeInBits() > 64
3311 }
3312 
3314  // Do not expand loads and stores that don't exceed 64 bits.
3315  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3316 }
3317 
3319  AtomicCmpXchgInst *AI) const {
3320  const DataLayout &DL = AI->getModule()->getDataLayout();
3321  unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3322  return Size >= 4 && Size <= 8;
3323 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:500
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:467
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
Value * getValueOperand()
Definition: Instructions.h:391
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:524
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
MVT getValVT() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
#define R4(n)
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Flags getFlags() const
Return the raw flags of the source value,.
LLVMContext * getContext() const
Definition: SelectionDAG.h:333
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1309
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:724
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:304
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:572
size_t i
LocInfo getLocInfo() const
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:313
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
const TargetMachine & getTargetMachine() const
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:504
HexagonTargetObjectFile * getObjFileLowering() const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:219
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Y = RRC X, rotate right via carry.
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:330
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:615
This class represents a function call, abstracting a target machine's calling convention.
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
const GlobalValue * getGlobal() const
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:237
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:268
unsigned getSizeInBits() const
unsigned getByValSize() const
static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Hexagon target-specific information for each MachineFunction.
unsigned getNumOperands() const
Return the number of values used by this operation.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:100
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned Num) const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:234
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
An instruction for reading from memory.
Definition: Instructions.h:164
const HexagonFrameLowering * getFrameLowering() const override
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
#define R2(n)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Same for subtraction.
Definition: ISDOpcodes.h:240
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
const SDValue & getBasePtr() const
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:299
The address of the GOT.
Definition: ISDOpcodes.h:66
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:690
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:369
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
Definition: ISDOpcodes.h:881
bool isRegLoc() const
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void dumpr() const
Dump (recursively) this node and its use-def subgraph.
SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:324
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:388
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:133
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:822
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
struct fuzzer::@269 Flags
Shift and rotation operations.
Definition: ISDOpcodes.h:344
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:327
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
void addLoc(const CCValAssign &V)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:588
Reg
All possible values of the reg field in the ModR/M byte.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
SimpleValueType SimpleTy
#define Hexagon_PointerSize
Definition: Hexagon.h:20
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool isPositionIndependent() const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM's memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:611
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
Definition: ValueTypes.h:239
MachineFunction & getMachineFunction() const
static SDValue createSplat(SelectionDAG &DAG, const SDLoc &dl, EVT VT, SDValue Val)
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
unsigned getLocReg() const
#define F(x, y, z)
Definition: MD5.cpp:51
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:410
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:421
#define T
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition: ISDOpcodes.h:363
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:949
MachineConstantPoolValue * getMachineCPVal() const
An instruction for storing to memory.
Definition: Instructions.h:300
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
const APInt & getAPIntValue() const
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:1301
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:487
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:875
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:151
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:328
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset)
Stack pointer relative access.
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
This class is used to represent ISD::STORE nodes.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:453
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
Definition: ISDOpcodes.h:274
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:254
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:262
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:166
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
unsigned const MachineRegisterInfo * MRI
bool isMachineConstantPoolEntry() const
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Simple binary floating point operators.
Definition: ISDOpcodes.h:246
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, SDValue &Base, SDValue &Offset, bool &IsInc, SelectionDAG &DAG)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
MVT getLocVT() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:637
static bool CC_Hexagon(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:818
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:279
const Constant * getConstVal() const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:228
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1947
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
uint32_t Offset
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
static mvt_range vector_valuetypes()
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:1466
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:628
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:485
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
This structure contains all information that is necessary for lowering calls.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
static bool isSExtFree(SDValue N)
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
const MachinePointerInfo & getPointerInfo() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
unsigned getByValAlign() const
bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
ArrayRef< int > getMask() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:546
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:540
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:689
#define HEXAGON_LRFP_SIZE
Definition: Hexagon.h:27
CCState - This class holds information needed while lowering arguments and return values...
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:494
void dump() const
Dump this node, for debugging.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:285
#define HEXAGON_GOT_SYM_NAME
Definition: Hexagon.h:43
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:58
static bool isHvxVectorType(MVT ty)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:230
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
const DataFlowGraph & G
Definition: RDFGraph.cpp:206
const SDValue & getChain() const
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:347
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
CHAIN = SC CHAIN, Imm128 - System call.
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
Definition: IRBuilder.h:307
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:121
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:584
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:513
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:715
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Class for arbitrary precision integers.
Definition: APInt.h:77
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:354
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:195
static StridedLoadKind isStridedLoad(const ArrayRef< int > &Mask)
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
void setPrefLoopAlignment(unsigned Align)
Set the target's preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:400
const GlobalObject * getBaseObject() const
Definition: GlobalValue.h:517
bool isMemLoc() const
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:403
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:259
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:560
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:384
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:578
SmallVector< SDValue, 32 > OutVals
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:333
MO_GOT - Indicates a GOT-relative relocation.
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const
bool isUndef() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:610
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:169
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
unsigned getStoreSizeInBits() const
getStoreSizeInBits - Return the number of bits overwritten by a store of the specified value type...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:418
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:536
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:256
#define N
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memcpy"))
CallInst * CreateCall(Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:1579
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
bool isTailCall() const
static bool CC_Hexagon_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static volatile int Zero
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:530
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:391
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
getEVT - Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:309
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
Definition: ISDOpcodes.h:102
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition: SelectionDAG.h:742
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:183
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:291
static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:107
unsigned getAlignment() const
static cl::opt< int > MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::ZeroOrMore, cl::init(6), cl::desc("Max #stores to inline memcpy"))
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
aarch64 promote const
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:108
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:537
LLVM Value Representation.
Definition: Value.h:71
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:249
SDValue getRegister(unsigned Reg, EVT VT)
const HexagonInstrInfo * getInstrInfo() const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:685
static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
#define DEBUG(X)
Definition: Debug.h:100
Primary interface to the complete machine description for the target machine.
static bool isCommonSplatElement(BuildVectorSDNode *BVN)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame)...
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:377
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
unsigned getLocMemOffset() const
MVT getVectorElementType() const
Conversion operators.
Definition: ISDOpcodes.h:397
SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const
int * Ptr
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:381
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:406
unsigned getAlignment() const
static cl::opt< int > MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::ZeroOrMore, cl::init(6), cl::desc("Max #stores to inline memmove"))
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
static cl::opt< int > MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memset"))
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
Definition: ISDOpcodes.h:516
static cl::opt< bool > EnableFastMath("ffast-math", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Fast Math processing"))
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
const BasicBlock * getParent() const
Definition: Instruction.h:62
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
Definition: ISDOpcodes.h:321
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:226
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:222
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:529
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
uint64_t getZExtValue() const
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:799
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:248
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:545