LLVM  4.0.0
ARMBaseRegisterInfo.h
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1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
16 
19 
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
22 
23 namespace llvm {
24 /// Register allocation hints.
25 namespace ARMRI {
26  enum {
29  };
30 }
31 
32 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
33 /// or a stack/pc register that we should push/pop.
34 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
35  using namespace ARM;
36  switch (Reg) {
37  case R0: case R1: case R2: case R3:
38  case R4: case R5: case R6: case R7:
39  case LR: case SP: case PC:
40  return true;
41  case R8: case R9: case R10: case R11: case R12:
42  // For iOS we want r7 and lr to be next to each other.
43  return !isIOS;
44  default:
45  return false;
46  }
47 }
48 
49 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
50  using namespace ARM;
51  switch (Reg) {
52  case R8: case R9: case R10: case R11: case R12:
53  // iOS has this second area.
54  return isIOS;
55  default:
56  return false;
57  }
58 }
59 
60 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
61  using namespace ARM;
62  switch (Reg) {
63  case D15: case D14: case D13: case D12:
64  case D11: case D10: case D9: case D8:
65  case D7: case D6: case D5: case D4:
66  case D3: case D2: case D1: case D0:
67  case D31: case D30: case D29: case D28:
68  case D27: case D26: case D25: case D24:
69  case D23: case D22: case D21: case D20:
70  case D19: case D18: case D17: case D16:
71  return true;
72  default:
73  return false;
74  }
75 }
76 
77 static inline bool isCalleeSavedRegister(unsigned Reg,
78  const MCPhysReg *CSRegs) {
79  for (unsigned i = 0; CSRegs[i]; ++i)
80  if (Reg == CSRegs[i])
81  return true;
82  return false;
83 }
84 
86 protected:
87  /// BasePtr - ARM physical register used as a base ptr in complex stack
88  /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
89  /// variable size stack objects.
90  unsigned BasePtr;
91 
92  // Can be only subclassed.
93  explicit ARMBaseRegisterInfo();
94 
95  // Return the opcode that implements 'Op', or 0 if no opcode
96  unsigned getOpcode(int Op) const;
97 
98 public:
99  /// Code Generation virtual methods...
100  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
101  const MCPhysReg *
104  CallingConv::ID) const override;
105  const uint32_t *getNoPreservedMask() const override;
106  const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
107  const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
108 
109  /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
110  /// case that 'returned' is on an i32 first argument if the calling convention
111  /// is one that can (partially) model this attribute with a preserved mask
112  /// (i.e. it is a calling convention that uses the same register for the first
113  /// i32 argument and an i32 return value)
114  ///
115  /// Should return NULL in the case that the calling convention does not have
116  /// this property
118  CallingConv::ID) const;
119 
120  BitVector getReservedRegs(const MachineFunction &MF) const override;
121 
122  const TargetRegisterClass *
124  unsigned Kind = 0) const override;
125  const TargetRegisterClass *
126  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
127 
128  const TargetRegisterClass *
130  const MachineFunction &MF) const override;
131 
132  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
133  MachineFunction &MF) const override;
134 
135  void getRegAllocationHints(unsigned VirtReg,
136  ArrayRef<MCPhysReg> Order,
138  const MachineFunction &MF,
139  const VirtRegMap *VRM,
140  const LiveRegMatrix *Matrix) const override;
141 
142  void updateRegAllocHint(unsigned Reg, unsigned NewReg,
143  MachineFunction &MF) const override;
144 
145  bool hasBasePointer(const MachineFunction &MF) const;
146 
147  bool canRealignStack(const MachineFunction &MF) const override;
149  int Idx) const override;
150  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
152  unsigned BaseReg, int FrameIdx,
153  int64_t Offset) const override;
154  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
155  int64_t Offset) const override;
156  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
157  int64_t Offset) const override;
158 
159  bool cannotEliminateFrame(const MachineFunction &MF) const;
160 
161  // Debug information queries.
162  unsigned getFrameRegister(const MachineFunction &MF) const override;
163  unsigned getBaseRegister() const { return BasePtr; }
164 
165  bool isLowRegister(unsigned Reg) const;
166 
167 
168  /// emitLoadConstPool - Emits a load from constpool to materialize the
169  /// specified immediate.
170  virtual void
172  const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
173  int Val, ARMCC::CondCodes Pred = ARMCC::AL,
174  unsigned PredReg = 0,
175  unsigned MIFlags = MachineInstr::NoFlags) const;
176 
177  /// Code Generation virtual methods...
178  bool requiresRegisterScavenging(const MachineFunction &MF) const override;
179 
180  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
181 
182  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
183 
184  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
185 
187  int SPAdj, unsigned FIOperandNum,
188  RegScavenger *RS = nullptr) const override;
189 
190  /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
192  const TargetRegisterClass *SrcRC,
193  unsigned SubReg,
194  const TargetRegisterClass *DstRC,
195  unsigned DstSubReg,
196  const TargetRegisterClass *NewRC) const override;
197 };
198 
199 } // end namespace llvm
200 
201 #endif
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
#define R4(n)
size_t i
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
unsigned getBaseRegister() const
void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
A debug info location.
Definition: DebugLoc.h:34
#define R2(n)
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
Live Register Matrix
const uint32_t * getNoPreservedMask() const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
MachineBasicBlock * MBB
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
static bool isARMArea1Register(unsigned Reg, bool isIOS)
isARMArea1Register - Returns true if the register is a low register (r0-r7) or a stack/pc register th...
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
bool isLowRegister(unsigned Reg) const
uint32_t Offset
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
#define R6(n)
static bool isARMArea2Register(unsigned Reg, bool isIOS)
bool canRealignStack(const MachineFunction &MF) const override
bool hasBasePointer(const MachineFunction &MF) const
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned getOpcode(int Op) const
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
static bool isARMArea3Register(unsigned Reg, bool isIOS)
const unsigned Kind
bool cannotEliminateFrame(const MachineFunction &MF) const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
IRTranslator LLVM IR MI
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
char * PC