27 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
34 for (
auto Reg : RegList) {
39 const size_t RequiredGprsUponSplit = 2;
40 if (AvailableRegs.
size() < RequiredGprsUponSplit)
44 for (
unsigned I = 0;
I < RequiredGprsUponSplit;
I++) {
51 assert(Reg &&
"Expecting a register will be available");
63 static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,
64 X86::ZMM3, X86::ZMM4, X86::ZMM5};
69 static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,
70 X86::YMM3, X86::YMM4, X86::YMM5};
74 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,
75 X86::XMM3, X86::XMM4, X86::XMM5};
80 static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};
95 for (
auto Reg : RegList) {
99 assert(AssigedReg ==
Reg &&
"Expecting a valid register allocation");
112 "an available register.");
121 if (ArgFlags.
isHva())
153 if (
Reg == X86::XMM4 ||
Reg == X86::XMM5)
156 if (!ArgFlags.
isHva()) {
165 return ArgFlags.
isHva();
173 if (ArgFlags.
isHva())
187 if (ArgFlags.
isHva())
void push_back(const T &Elt)
const_iterator end(StringRef path)
Get end iterator over path.
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
bool is512BitVector() const
is512BitVector - Return true if this is a 512-bit vector type.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
const_iterator begin(StringRef path)
Get begin iterator over path.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
bool isSecArgPass() const
static ArrayRef< MCPhysReg > CC_X86_64_VectorCallGetGPRs()
MachineFunction & getMachineFunction() const
bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Vectorcall calling convention has special handling for vector types or HVA for 32 bit arch...
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
bool IsShadowAllocatedReg(unsigned Reg) const
A shadow allocated register is a register that was allocated but wasn't added to the location list (L...
MVT - Machine Value Type.
bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Vectorcall calling convention has special handling for vector types or HVA for 64 bit arch...
bool isVector() const
isVector - Return true if this is a vector value type.
static bool is64Bit(const char *name)
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CCState - This class holds information needed while lowering arguments and return values...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
bool isAllocated(unsigned Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static ArrayRef< MCPhysReg > CC_X86_VectorCallGetSSEs(const MVT &ValVT)
bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
When regcall calling convention compiled to 32 bit arch, special treatment is required for 64 bit mas...
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.