LLVM  4.0.0
X86EvexToVex.cpp
Go to the documentation of this file.
1 //===----------------------- X86EvexToVex.cpp ----------------------------===//
2 // Compress EVEX instructions to VEX encoding when possible to reduce code size
3 //
4 // The LLVM Compiler Infrastructure
5 //
6 // This file is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
8 //
9 //===---------------------------------------------------------------------===//
10 /// \file
11 /// This file defines the pass that goes over all AVX-512 instructions which
12 /// are encoded using the EVEX prefix and if possible replaces them by their
13 /// corresponding VEX encoding which is usually shorter by 2 bytes.
14 /// EVEX instructions may be encoded via the VEX prefix when the AVX-512
15 /// instruction has a corresponding AVX/AVX2 opcode and when it does not
16 /// use the xmm or the mask registers or xmm/ymm registers wuith indexes
17 /// higher than 15.
18 /// The pass applies code reduction on the generated code for AVX-512 instrs.
19 ///
20 //===---------------------------------------------------------------------===//
21 
23 #include "X86.h"
24 #include "X86InstrBuilder.h"
25 #include "X86InstrInfo.h"
26 #include "X86InstrTablesInfo.h"
27 #include "X86MachineFunctionInfo.h"
28 #include "X86Subtarget.h"
29 #include "X86TargetMachine.h"
30 
31 using namespace llvm;
32 
33 #define EVEX2VEX_DESC "Compressing EVEX instrs to VEX encoding when possible"
34 #define EVEX2VEX_NAME "x86-evex-to-vex-compress"
35 
36 #define DEBUG_TYPE EVEX2VEX_NAME
37 
38 namespace {
39 
40 class EvexToVexInstPass : public MachineFunctionPass {
41 
42  /// X86EvexToVexCompressTable - Evex to Vex encoding opcode map.
43  typedef DenseMap<unsigned, uint16_t> EvexToVexTableType;
44  EvexToVexTableType EvexToVex128Table;
45  EvexToVexTableType EvexToVex256Table;
46 
47  /// For EVEX instructions that can be encoded using VEX encoding, replace
48  /// them by the VEX encoding in order to reduce size.
49  bool CompressEvexToVexImpl(MachineInstr &MI) const;
50 
51  /// For initializing the hash map tables of all AVX-512 EVEX
52  /// corresponding to AVX/AVX2 opcodes.
53  void AddTableEntry(EvexToVexTableType &EvexToVexTable, uint16_t EvexOp,
54  uint16_t VexOp);
55 
56 public:
57  static char ID;
58 
59  StringRef getPassName() const override { return EVEX2VEX_DESC; }
60 
61  EvexToVexInstPass() : MachineFunctionPass(ID) {
63 
64  // Initialize the EVEX to VEX 128 table map.
66  AddTableEntry(EvexToVex128Table, Entry.EvexOpcode, Entry.VexOpcode);
67  }
68 
69  // Initialize the EVEX to VEX 256 table map.
71  AddTableEntry(EvexToVex256Table, Entry.EvexOpcode, Entry.VexOpcode);
72  }
73  }
74 
75  /// Loop over all of the basic blocks, replacing EVEX instructions
76  /// by equivalent VEX instructions when possible for reducing code size.
77  bool runOnMachineFunction(MachineFunction &MF) override;
78 
79  // This pass runs after regalloc and doesn't support VReg operands.
80  MachineFunctionProperties getRequiredProperties() const override {
83  }
84 
85 private:
86  /// Machine instruction info used throughout the class.
87  const X86InstrInfo *TII;
88 };
89 
90 char EvexToVexInstPass::ID = 0;
91 }
92 
93 INITIALIZE_PASS(EvexToVexInstPass, EVEX2VEX_NAME, EVEX2VEX_DESC, false, false)
94 
96  return new EvexToVexInstPass();
97 }
98 
99 bool EvexToVexInstPass::runOnMachineFunction(MachineFunction &MF) {
100  TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
101 
102  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
103  if (!ST.hasAVX512())
104  return false;
105 
106  bool Changed = false;
107 
108  /// Go over all basic blocks in function and replace
109  /// EVEX encoded instrs by VEX encoding when possible.
110  for (MachineBasicBlock &MBB : MF) {
111 
112  // Traverse the basic block.
113  for (MachineInstr &MI : MBB)
114  Changed |= CompressEvexToVexImpl(MI);
115  }
116 
117  return Changed;
118 }
119 
120 void EvexToVexInstPass::AddTableEntry(EvexToVexTableType &EvexToVexTable,
121  uint16_t EvexOp, uint16_t VexOp) {
122  EvexToVexTable[EvexOp] = VexOp;
123 }
124 
125 // For EVEX instructions that can be encoded using VEX encoding
126 // replace them by the VEX encoding in order to reduce size.
127 bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
128 
129  // VEX format.
130  // # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1
131  // [Prefixes] [VEX] OPCODE ModR/M [SIB] [DISP] [IMM]
132  //
133  // EVEX format.
134  // # of bytes: 4 1 1 1 4 / 1 1
135  // [Prefixes] EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate]
136 
137  const MCInstrDesc &Desc = MI.getDesc();
138 
139  // Check for EVEX instructions only.
140  if ((Desc.TSFlags & X86II::EncodingMask) != X86II::EVEX)
141  return false;
142 
143  // Check for EVEX instructions with mask or broadcast as in these cases
144  // the EVEX prefix is needed in order to carry this information
145  // thus preventing the transformation to VEX encoding.
146  if (Desc.TSFlags & (X86II::EVEX_K | X86II::EVEX_B))
147  return false;
148 
149  // Check for non EVEX_V512 instrs only.
150  // EVEX_V512 instr: bit EVEX_L2 = 1; bit VEX_L = 0.
151  if ((Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L))
152  return false;
153 
154  // EVEX_V128 instr: bit EVEX_L2 = 0, bit VEX_L = 0.
155  bool IsEVEX_V128 =
156  (!(Desc.TSFlags & X86II::EVEX_L2) && !(Desc.TSFlags & X86II::VEX_L));
157 
158  // EVEX_V256 instr: bit EVEX_L2 = 0, bit VEX_L = 1.
159  bool IsEVEX_V256 =
160  (!(Desc.TSFlags & X86II::EVEX_L2) && (Desc.TSFlags & X86II::VEX_L));
161 
162  unsigned NewOpc = 0;
163 
164  // Check for EVEX_V256 instructions.
165  if (IsEVEX_V256) {
166  // Search for opcode in the EvexToVex256 table.
167  auto It = EvexToVex256Table.find(MI.getOpcode());
168  if (It != EvexToVex256Table.end())
169  NewOpc = It->second;
170  }
171 
172  // Check for EVEX_V128 or Scalar instructions.
173  else if (IsEVEX_V128) {
174  // Search for opcode in the EvexToVex128 table.
175  auto It = EvexToVex128Table.find(MI.getOpcode());
176  if (It != EvexToVex128Table.end())
177  NewOpc = It->second;
178  }
179 
180  if (!NewOpc)
181  return false;
182 
183  auto isHiRegIdx = [](unsigned Reg) {
184  // Check for XMM register with indexes between 16 - 31.
185  if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
186  return true;
187 
188  // Check for YMM register with indexes between 16 - 31.
189  if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
190  return true;
191 
192  return false;
193  };
194 
195  // Check that operands are not ZMM regs or
196  // XMM/YMM regs with hi indexes between 16 - 31.
197  for (const MachineOperand &MO : MI.explicit_operands()) {
198  if (!MO.isReg())
199  continue;
200 
201  unsigned Reg = MO.getReg();
202 
203  assert (!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31));
204 
205  if (isHiRegIdx(Reg))
206  return false;
207  }
208 
209  const MCInstrDesc &MCID = TII->get(NewOpc);
210  MI.setDesc(MCID);
212  return true;
213 }
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:307
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX ecnoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
MachineBasicBlock * MBB
void initializeEvexToVexInstPassPass(PassRegistry &)
static const X86EvexToVexCompressTableEntry X86EvexToVex128CompressTable[]
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static const X86EvexToVexCompressTableEntry X86EvexToVex256CompressTable[]
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:36
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
#define EVEX2VEX_DESC
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:52
#define EVEX2VEX_NAME
bool hasAVX512() const
Definition: X86Subtarget.h:418
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:146
Properties which a MachineFunction may have at a given point in time.