LLVM  4.0.0
InstructionSelect.cpp
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the InstructionSelect class.
11 //===----------------------------------------------------------------------===//
12 
15 #include "llvm/ADT/Twine.h"
20 #include "llvm/IR/Function.h"
22 #include "llvm/Support/Debug.h"
24 
25 #define DEBUG_TYPE "instruction-select"
26 
27 using namespace llvm;
28 
29 char InstructionSelect::ID = 0;
31  "Select target instructions out of generic instructions",
32  false, false)
35  "Select target instructions out of generic instructions",
36  false, false)
37 
38 InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) {
40 }
41 
45 }
46 
47 static void reportSelectionError(const MachineInstr *MI, const Twine &Message) {
48  const MachineFunction &MF = *MI->getParent()->getParent();
49  std::string ErrStorage;
50  raw_string_ostream Err(ErrStorage);
51  Err << Message << ":\nIn function: " << MF.getName() << '\n';
52  if (MI)
53  Err << *MI << '\n';
54  report_fatal_error(Err.str());
55 }
56 
58  // If the ISel pipeline failed, do not bother running that pass.
59  if (MF.getProperties().hasProperty(
61  return false;
62 
63  DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
64 
65  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
67  assert(ISel && "Cannot work without InstructionSelector");
68 
69  // FIXME: freezeReservedRegs is now done in IRTranslator, but there are many
70  // other MF/MFI fields we need to initialize.
71 
72  const MachineRegisterInfo &MRI = MF.getRegInfo();
73 
74 #ifndef NDEBUG
75  // Check that our input is fully legal: we require the function to have the
76  // Legalized property, so it should be.
77  // FIXME: This should be in the MachineVerifier, but it can't use the
78  // LegalizerInfo as it's currently in the separate GlobalISel library.
79  // The RegBankSelected property is already checked in the verifier. Note
80  // that it has the same layering problem, but we only use inline methods so
81  // end up not needing to link against the GlobalISel library.
82  if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo())
83  for (const MachineBasicBlock &MBB : MF)
84  for (const MachineInstr &MI : MBB)
85  if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI))
86  reportSelectionError(&MI, "Instruction is not legal");
87 
88 #endif
89  // FIXME: We could introduce new blocks and will need to fix the outer loop.
90  // Until then, keep track of the number of blocks to assert that we don't.
91  const size_t NumBlocks = MF.size();
92 
93  bool Failed = false;
94  for (MachineBasicBlock *MBB : post_order(&MF)) {
95  if (MBB->empty())
96  continue;
97 
98  // Select instructions in reverse block order. We permit erasing so have
99  // to resort to manually iterating and recognizing the begin (rend) case.
100  bool ReachedBegin = false;
101  for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
102  !ReachedBegin;) {
103 #ifndef NDEBUG
104  // Keep track of the insertion range for debug printing.
105  const auto AfterIt = std::next(MII);
106 #endif
107  // Select this instruction.
108  MachineInstr &MI = *MII;
109 
110  // And have our iterator point to the next instruction, if there is one.
111  if (MII == Begin)
112  ReachedBegin = true;
113  else
114  --MII;
115 
116  DEBUG(dbgs() << "Selecting: \n " << MI);
117 
118  if (!ISel->select(MI)) {
119  if (TPC.isGlobalISelAbortEnabled())
120  // FIXME: It would be nice to dump all inserted instructions. It's
121  // not
122  // obvious how, esp. considering select() can insert after MI.
123  reportSelectionError(&MI, "Cannot select");
124  Failed = true;
125  break;
126  }
127 
128  // Dump the range of instructions that MI expanded into.
129  DEBUG({
130  auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
131  dbgs() << "Into:\n";
132  for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
133  dbgs() << " " << InsertedMI;
134  dbgs() << '\n';
135  });
136  }
137  }
138 
139  // Now that selection is complete, there are no more generic vregs. Verify
140  // that the size of the now-constrained vreg is unchanged and that it has a
141  // register class.
142  for (auto &VRegToType : MRI.getVRegToType()) {
143  unsigned VReg = VRegToType.first;
144  auto *RC = MRI.getRegClassOrNull(VReg);
145  auto *MI = MRI.def_instr_begin(VReg) == MRI.def_instr_end()
146  ? nullptr
147  : &*MRI.def_instr_begin(VReg);
148  if (!RC) {
149  if (TPC.isGlobalISelAbortEnabled())
150  reportSelectionError(MI, "VReg as no regclass after selection");
151  Failed = true;
152  break;
153  }
154 
155  if (VRegToType.second.isValid() &&
156  VRegToType.second.getSizeInBits() > (RC->getSize() * 8)) {
157  if (TPC.isGlobalISelAbortEnabled())
159  MI, "VReg has explicit size different from class size");
160  Failed = true;
161  break;
162  }
163  }
164 
165  MRI.getVRegToType().clear();
166 
167  if (!TPC.isGlobalISelAbortEnabled() && (Failed || MF.size() != NumBlocks)) {
168  MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
169  return false;
170  }
171  assert(MF.size() == NumBlocks && "Inserting blocks is not supported yet");
172 
173  // FIXME: Should we accurately track changes?
174  return true;
175 }
static void reportSelectionError(const MachineInstr *MI, const Twine &Message)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasProperty(Property P) const
void initializeInstructionSelectPass(PassRegistry &)
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const MachineFunctionProperties & getProperties() const
Get the function properties.
Target-Independent Code Generator Pass Configuration Options.
MachineBasicBlock * MBB
static def_instr_iterator def_instr_end()
virtual const InstructionSelector * getInstructionSelector() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TracePC TPC
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
iterator_range< po_iterator< T > > post_order(const T &G)
#define DEBUG_TYPE
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:479
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
This pass is responsible for selecting generic machine instructions to target-specific instructions...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:52
def_instr_iterator def_instr_begin(unsigned RegNo) const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,"Select target instructions out of generic instructions", false, false) INITIALIZE_PASS_END(InstructionSelect
Select target instructions out of generic false
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
virtual const LegalizerInfo * getLegalizerInfo() const
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
inst_range instructions(Function *F)
Definition: InstIterator.h:132
StringRef getName() const
getName - Return the name of the corresponding LLVM function.