LLVM  4.0.0
MipsSubtarget.h
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1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
16 
18 #include "MipsFrameLowering.h"
19 #include "MipsISelLowering.h"
20 #include "MipsInstrInfo.h"
22 #include "llvm/IR/DataLayout.h"
26 #include <string>
27 
28 #define GET_SUBTARGETINFO_HEADER
29 #include "MipsGenSubtargetInfo.inc"
30 
31 namespace llvm {
32 class StringRef;
33 
34 class MipsTargetMachine;
35 
37  virtual void anchor();
38 
39  enum MipsArchEnum {
40  MipsDefault,
41  Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
42  Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
43  };
44 
45  enum class CPU { P5600 };
46 
47  // Mips architecture version
48  MipsArchEnum MipsArchVersion;
49 
50  // Processor implementation (unused but required to exist by
51  // tablegen-erated code).
52  CPU ProcImpl;
53 
54  // IsLittle - The target is Little Endian
55  bool IsLittle;
56 
57  // IsSoftFloat - The target does not support any floating point instructions.
58  bool IsSoftFloat;
59 
60  // IsSingleFloat - The target only supports single precision float
61  // point operations. This enable the target to use all 32 32-bit
62  // floating point registers instead of only using even ones.
63  bool IsSingleFloat;
64 
65  // IsFPXX - MIPS O32 modeless ABI.
66  bool IsFPXX;
67 
68  // NoABICalls - Disable SVR4-style position-independent code.
69  bool NoABICalls;
70 
71  // IsFP64bit - The target processor has 64-bit floating point registers.
72  bool IsFP64bit;
73 
74  /// Are odd single-precision registers permitted?
75  /// This corresponds to -modd-spreg and -mno-odd-spreg
76  bool UseOddSPReg;
77 
78  // IsNan2008 - IEEE 754-2008 NaN encoding.
79  bool IsNaN2008bit;
80 
81  // IsFP64bit - General-purpose registers are 64 bits wide
82  bool IsGP64bit;
83 
84  // IsPTR64bit - Pointers are 64 bit wide
85  bool IsPTR64bit;
86 
87  // HasVFPU - Processor has a vector floating point unit.
88  bool HasVFPU;
89 
90  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
91  bool HasCnMips;
92 
93  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
94  bool IsLinux;
95 
96  // UseSmallSection - Small section is used.
97  bool UseSmallSection;
98 
99  /// Features related to the presence of specific instructions.
100 
101  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
102  bool HasMips3_32;
103 
104  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
105  bool HasMips3_32r2;
106 
107  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
108  bool HasMips4_32;
109 
110  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
111  bool HasMips4_32r2;
112 
113  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
114  bool HasMips5_32r2;
115 
116  // InMips16 -- can process Mips16 instructions
117  bool InMips16Mode;
118 
119  // Mips16 hard float
120  bool InMips16HardFloat;
121 
122  // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
123  bool PreviousInMips16Mode;
124 
125  // InMicroMips -- can process MicroMips instructions
126  bool InMicroMipsMode;
127 
128  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
129  bool HasDSP, HasDSPR2, HasDSPR3;
130 
131  // Allow mixed Mips16 and Mips32 in one source file
132  bool AllowMixed16_32;
133 
134  // Optimize for space by compiling all functions as Mips 16 unless
135  // it needs floating point. Functions needing floating point are
136  // compiled as Mips32
137  bool Os16;
138 
139  // HasMSA -- supports MSA ASE.
140  bool HasMSA;
141 
142  // UseTCCInDIV -- Enables the use of trapping in the assembler.
143  bool UseTCCInDIV;
144 
145  // HasEVA -- supports EVA ASE.
146  bool HasEVA;
147 
148  InstrItineraryData InstrItins;
149 
150  // We can override the determination of whether we are in mips16 mode
151  // as from the command line
152  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
153 
154  const MipsTargetMachine &TM;
155 
156  Triple TargetTriple;
157 
158  const SelectionDAGTargetInfo TSInfo;
159  std::unique_ptr<const MipsInstrInfo> InstrInfo;
160  std::unique_ptr<const MipsFrameLowering> FrameLowering;
161  std::unique_ptr<const MipsTargetLowering> TLInfo;
162 
163 public:
164  bool isPositionIndependent() const;
165  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
166  bool enablePostRAScheduler() const override;
167  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
169 
170  bool isABI_N64() const;
171  bool isABI_N32() const;
172  bool isABI_O32() const;
173  const MipsABIInfo &getABI() const;
174  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
175 
176  /// This constructor initializes the data members to match that
177  /// of the specified triple.
178  MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
179  bool little, const MipsTargetMachine &TM);
180 
181  /// ParseSubtargetFeatures - Parses features string setting specified
182  /// subtarget options. Definition of function is auto generated by tblgen.
184 
185  bool hasMips1() const { return MipsArchVersion >= Mips1; }
186  bool hasMips2() const { return MipsArchVersion >= Mips2; }
187  bool hasMips3() const { return MipsArchVersion >= Mips3; }
188  bool hasMips4() const { return MipsArchVersion >= Mips4; }
189  bool hasMips5() const { return MipsArchVersion >= Mips5; }
190  bool hasMips4_32() const { return HasMips4_32; }
191  bool hasMips4_32r2() const { return HasMips4_32r2; }
192  bool hasMips32() const {
193  return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
194  hasMips64();
195  }
196  bool hasMips32r2() const {
197  return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
198  hasMips64r2();
199  }
200  bool hasMips32r3() const {
201  return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
202  hasMips64r2();
203  }
204  bool hasMips32r5() const {
205  return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
206  hasMips64r5();
207  }
208  bool hasMips32r6() const {
209  return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
210  hasMips64r6();
211  }
212  bool hasMips64() const { return MipsArchVersion >= Mips64; }
213  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
214  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
215  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
216  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
217 
218  bool hasCnMips() const { return HasCnMips; }
219 
220  bool isLittle() const { return IsLittle; }
221  bool isABICalls() const { return !NoABICalls; }
222  bool isFPXX() const { return IsFPXX; }
223  bool isFP64bit() const { return IsFP64bit; }
224  bool useOddSPReg() const { return UseOddSPReg; }
225  bool noOddSPReg() const { return !UseOddSPReg; }
226  bool isNaN2008() const { return IsNaN2008bit; }
227  bool isGP64bit() const { return IsGP64bit; }
228  bool isGP32bit() const { return !IsGP64bit; }
229  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
230  bool isPTR64bit() const { return IsPTR64bit; }
231  bool isPTR32bit() const { return !IsPTR64bit; }
232  bool isSingleFloat() const { return IsSingleFloat; }
233  bool hasVFPU() const { return HasVFPU; }
234  bool inMips16Mode() const { return InMips16Mode; }
235  bool inMips16ModeDefault() const {
236  return InMips16Mode;
237  }
238  // Hard float for mips16 means essentially to compile as soft float
239  // but to use a runtime library for soft float that is written with
240  // native mips32 floating point instructions (those runtime routines
241  // run in mips32 hard float mode).
242  bool inMips16HardFloat() const {
243  return inMips16Mode() && InMips16HardFloat;
244  }
245  bool inMicroMipsMode() const { return InMicroMipsMode; }
246  bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
247  bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
248  bool hasDSP() const { return HasDSP; }
249  bool hasDSPR2() const { return HasDSPR2; }
250  bool hasDSPR3() const { return HasDSPR3; }
251  bool hasMSA() const { return HasMSA; }
252  bool hasEVA() const { return HasEVA; }
253  bool useSmallSection() const { return UseSmallSection; }
254 
255  bool hasStandardEncoding() const { return !inMips16Mode(); }
256 
257  bool useSoftFloat() const { return IsSoftFloat; }
258 
259  bool enableLongBranchPass() const {
260  return hasStandardEncoding() || allowMixed16_32();
261  }
262 
263  /// Features related to the presence of specific instructions.
264  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
265  bool hasMTHC1() const { return hasMips32r2(); }
266 
267  bool allowMixed16_32() const { return inMips16ModeDefault() |
268  AllowMixed16_32; }
269 
270  bool os16() const { return Os16; }
271 
272  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
273 
274  // for now constant islands are on for the whole compilation unit but we only
275  // really use them if in addition we are in mips16 mode
276  static bool useConstantIslands();
277 
278  unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
279 
280  // Grab relocation model
282 
284  const TargetMachine &TM);
285 
286  /// Does the system support unaligned memory access.
287  ///
288  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
289  /// specify which component of the system provides it. Hardware, software, and
290  /// hybrid implementations are all valid.
291  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
292 
293  // Set helper classes
294  void setHelperClassesMips16();
295  void setHelperClassesMipsSE();
296 
297  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
298  return &TSInfo;
299  }
300  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
301  const TargetFrameLowering *getFrameLowering() const override {
302  return FrameLowering.get();
303  }
304  const MipsRegisterInfo *getRegisterInfo() const override {
305  return &InstrInfo->getRegisterInfo();
306  }
307  const MipsTargetLowering *getTargetLowering() const override {
308  return TLInfo.get();
309  }
310  const InstrItineraryData *getInstrItineraryData() const override {
311  return &InstrItins;
312  }
313 };
314 } // End llvm namespace
315 
316 #endif
bool hasMips64r5() const
const MipsABIInfo & getABI() const
bool noOddSPReg() const
void setHelperClassesMips16()
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
const MipsInstrInfo * getInstrInfo() const override
const InstrItineraryData * getInstrItineraryData() const override
bool hasMips64r3() const
bool isPositionIndependent() const
bool isFPXX() const
bool isGP32bit() const
bool hasMips32() const
unsigned getGPRSizeInBytes() const
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool isNaN2008() const
bool isPTR64bit() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool hasMSA() const
bool inMips16HardFloat() const
bool hasMips64() const
bool os16() const
bool hasVFPU() const
unsigned stackAlignment() const
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:545
Itinerary data supplied by a subtarget to be used by a target.
const TargetFrameLowering * getFrameLowering() const override
bool inMicroMips32r6Mode() const
bool inMips16ModeDefault() const
bool useOddSPReg() const
bool hasMTHC1() const
bool hasMips64r2() const
bool hasMips1() const
bool isFP64bit() const
bool hasMips4_32() const
bool useSoftFloat() const
bool inMicroMipsMode() const
bool inMips16Mode() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
bool hasMips32r6() const
bool hasMips32r3() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
static bool useConstantIslands()
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool isTargetNaCl() const
bool isABICalls() const
bool isABI_N64() const
const MipsRegisterInfo * getRegisterInfo() const override
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void setHelperClassesMipsSE()
Information about stack frame layout on the target.
bool isLittle() const
bool hasStandardEncoding() const
bool isABI_N32() const
bool hasMips64r6() const
bool hasMips2() const
bool hasMips4_32r2() const
bool isPTR32bit() const
const MipsTargetLowering * getTargetLowering() const override
bool hasEVA() const
bool isGP64bit() const
bool hasDSPR3() const
MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, bool little, const MipsTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
Reloc::Model getRelocationModel() const
bool hasMips5() const
bool hasDSPR2() const
bool isSingleFloat() const
bool hasMips4() const
bool hasMips32r2() const
bool allowMixed16_32() const
bool inMicroMips64r6Mode() const
bool hasMips3() const
bool enableLongBranchPass() const
bool isABI_O32() const
bool hasDSP() const
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool hasCnMips() const
bool useSmallSection() const
bool isABI_FPXX() const
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool hasMips32r5() const