LLVM  4.0.0
MCSubtargetInfo.h
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1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subtarget options of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_MC_MCSUBTARGETINFO_H
15 #define LLVM_MC_MCSUBTARGETINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
20 #include <string>
21 
22 namespace llvm {
23 
24 class StringRef;
25 
26 //===----------------------------------------------------------------------===//
27 ///
28 /// MCSubtargetInfo - Generic base class for all target subtargets.
29 ///
31  Triple TargetTriple; // Target triple
32  std::string CPU; // CPU being targeted.
33  ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
34  ArrayRef<SubtargetFeatureKV> ProcDesc; // Processor descriptions
35 
36  // Scheduler machine model
37  const SubtargetInfoKV *ProcSchedModels;
38  const MCWriteProcResEntry *WriteProcResTable;
39  const MCWriteLatencyEntry *WriteLatencyTable;
40  const MCReadAdvanceEntry *ReadAdvanceTable;
41  const MCSchedModel *CPUSchedModel;
42 
43  const InstrStage *Stages; // Instruction itinerary stages
44  const unsigned *OperandCycles; // Itinerary operand cycles
45  const unsigned *ForwardingPaths; // Forwarding paths
46  FeatureBitset FeatureBits; // Feature bits for current CPU + FS
47 
48  MCSubtargetInfo() = delete;
49  MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
50  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
51 
52 public:
53  MCSubtargetInfo(const MCSubtargetInfo &) = default;
54  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
57  const SubtargetInfoKV *ProcSched,
58  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
59  const MCReadAdvanceEntry *RA, const InstrStage *IS,
60  const unsigned *OC, const unsigned *FP);
61 
62  /// getTargetTriple - Return the target triple string.
63  const Triple &getTargetTriple() const { return TargetTriple; }
64 
65  /// getCPU - Return the CPU string.
66  StringRef getCPU() const {
67  return CPU;
68  }
69 
70  /// getFeatureBits - Return the feature bits.
71  ///
72  const FeatureBitset& getFeatureBits() const {
73  return FeatureBits;
74  }
75 
76  /// setFeatureBits - Set the feature bits.
77  ///
78  void setFeatureBits(const FeatureBitset &FeatureBits_) {
79  FeatureBits = FeatureBits_;
80  }
81 
82 protected:
83  /// Initialize the scheduling model and feature bits.
84  ///
85  /// FIXME: Find a way to stick this in the constructor, since it should only
86  /// be called during initialization.
88 
89 public:
90  /// Set the features to the default for the given CPU with an appended feature
91  /// string.
93 
94  /// ToggleFeature - Toggle a feature and returns the re-computed feature
95  /// bits. This version does not change the implied bits.
96  FeatureBitset ToggleFeature(uint64_t FB);
97 
98  /// ToggleFeature - Toggle a feature and returns the re-computed feature
99  /// bits. This version does not change the implied bits.
101 
102  /// ToggleFeature - Toggle a set of features and returns the re-computed
103  /// feature bits. This version will also change all implied bits.
105 
106  /// Apply a feature flag and return the re-computed feature bits, including
107  /// all feature bits implied by the flag.
109 
110  /// getSchedModelForCPU - Get the machine model of a CPU.
111  ///
112  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
113 
114  /// Get the machine model for this subtarget's CPU.
115  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
116 
117  /// Return an iterator at the first process resource consumed by the given
118  /// scheduling class.
120  const MCSchedClassDesc *SC) const {
121  return &WriteProcResTable[SC->WriteProcResIdx];
122  }
124  const MCSchedClassDesc *SC) const {
126  }
127 
129  unsigned DefIdx) const {
130  assert(DefIdx < SC->NumWriteLatencyEntries &&
131  "MachineModel does not specify a WriteResource for DefIdx");
132 
133  return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
134  }
135 
136  int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
137  unsigned WriteResID) const {
138  // TODO: The number of read advance entries in a class can be significant
139  // (~50). Consider compressing the WriteID into a dense ID of those that are
140  // used by ReadAdvance and representing them as a bitset.
141  for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
142  *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
143  if (I->UseIdx < UseIdx)
144  continue;
145  if (I->UseIdx > UseIdx)
146  break;
147  // Find the first WriteResIdx match, which has the highest cycle count.
148  if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
149  return I->Cycles;
150  }
151  }
152  return 0;
153  }
154 
155  /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
156  ///
158 
159  /// Initialize an InstrItineraryData instance.
160  void initInstrItins(InstrItineraryData &InstrItins) const;
161 
162  /// Check whether the CPU string is valid.
163  bool isCPUStringValid(StringRef CPU) const {
164  auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
165  return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
166  }
167 };
168 
169 } // End llvm namespace
170 
171 #endif
unsigned NumWriteProcResEntries
Definition: MCSchedule.h:112
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
void setFeatureBits(const FeatureBitset &FeatureBits_)
setFeatureBits - Set the feature bits.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
getSchedModelForCPU - Get the machine model of a CPU.
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
StringRef getCPU() const
getCPU - Return the CPU string.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
void InitMCProcessorInfo(StringRef CPU, StringRef FS)
Initialize the scheduling model and feature bits.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
unsigned NumReadAdvanceEntries
Definition: MCSchedule.h:116
FeatureBitset ToggleFeature(uint64_t FB)
ToggleFeature - Toggle a feature and returns the re-computed feature bits.
bool isCPUStringValid(StringRef CPU) const
Check whether the CPU string is valid.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:55
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
CHAIN = SC CHAIN, Imm128 - System call.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:86
These values represent a non-pipelined step in the execution of an instruction.
#define I(x, y, z)
Definition: MD5.cpp:54
MCSubtargetInfo - Generic base class for all target subtargets.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
void setDefaultFeatures(StringRef CPU, StringRef FS)
Set the features to the default for the given CPU with an appended feature string.