LLVM  4.0.0
MipsAsmBackend.cpp
Go to the documentation of this file.
1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MipsAsmBackend class.
11 //
12 //===----------------------------------------------------------------------===//
13 //
14 
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDirectives.h"
25 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCValue.h"
29 #include "llvm/Support/Format.h"
32 
33 using namespace llvm;
34 
35 // Prepare value for the target space for it
36 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
37  MCContext *Ctx = nullptr) {
38 
39  unsigned Kind = Fixup.getKind();
40 
41  // Add/subtract and shift
42  switch (Kind) {
43  default:
44  return 0;
45  case FK_Data_2:
60  Value &= 0xffff;
61  break;
62  case FK_DTPRel_4:
63  case FK_DTPRel_8:
64  case FK_TPRel_4:
65  case FK_TPRel_8:
66  case FK_GPRel_4:
67  case FK_Data_4:
68  case FK_Data_8:
71  break;
73  // The displacement is then divided by 4 to give us an 18 bit
74  // address range. Forcing a signed division because Value can be negative.
75  Value = (int64_t)Value / 4;
76  // We now check if Value can be encoded as a 16-bit signed immediate.
77  if (!isInt<16>(Value) && Ctx) {
78  Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup");
79  return 0;
80  }
81  break;
84  // Forcing a signed division because Value can be negative.
85  Value = (int64_t)Value / 4;
86  // We now check if Value can be encoded as a 19-bit signed immediate.
87  if (!isInt<19>(Value) && Ctx) {
88  Ctx->reportError(Fixup.getLoc(), "out of range PC19 fixup");
89  return 0;
90  }
91  break;
93  // So far we are only using this type for jumps.
94  // The displacement is then divided by 4 to give us an 28 bit
95  // address range.
96  Value >>= 2;
97  break;
105  // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
106  Value = ((Value + 0x8000) >> 16) & 0xffff;
107  break;
109  // Get the 3rd 16-bits.
110  Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
111  break;
113  // Get the 4th 16-bits.
114  Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
115  break;
117  Value >>= 1;
118  break;
120  Value -= 4;
121  // Forcing a signed division because Value can be negative.
122  Value = (int64_t) Value / 2;
123  // We now check if Value can be encoded as a 7-bit signed immediate.
124  if (!isInt<7>(Value) && Ctx) {
125  Ctx->reportError(Fixup.getLoc(), "out of range PC7 fixup");
126  return 0;
127  }
128  break;
130  Value -= 2;
131  // Forcing a signed division because Value can be negative.
132  Value = (int64_t) Value / 2;
133  // We now check if Value can be encoded as a 10-bit signed immediate.
134  if (!isInt<10>(Value) && Ctx) {
135  Ctx->reportError(Fixup.getLoc(), "out of range PC10 fixup");
136  return 0;
137  }
138  break;
140  Value -= 4;
141  // Forcing a signed division because Value can be negative.
142  Value = (int64_t)Value / 2;
143  // We now check if Value can be encoded as a 16-bit signed immediate.
144  if (!isInt<16>(Value) && Ctx) {
145  Ctx->reportError(Fixup.getLoc(), "out of range PC16 fixup");
146  return 0;
147  }
148  break;
150  // Forcing a signed division because Value can be negative.
151  Value = (int64_t)Value / 8;
152  // We now check if Value can be encoded as a 18-bit signed immediate.
153  if (!isInt<18>(Value) && Ctx) {
154  Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
155  return 0;
156  }
157  break;
159  // Check alignment.
160  if ((Value & 7) && Ctx) {
161  Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
162  }
163  // Forcing a signed division because Value can be negative.
164  Value = (int64_t)Value / 8;
165  // We now check if Value can be encoded as a 18-bit signed immediate.
166  if (!isInt<18>(Value) && Ctx) {
167  Ctx->reportError(Fixup.getLoc(), "out of range PC18 fixup");
168  return 0;
169  }
170  break;
172  // Forcing a signed division because Value can be negative.
173  Value = (int64_t) Value / 4;
174  // We now check if Value can be encoded as a 21-bit signed immediate.
175  if (!isInt<21>(Value) && Ctx) {
176  Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
177  return 0;
178  }
179  break;
181  // Forcing a signed division because Value can be negative.
182  Value = (int64_t) Value / 4;
183  // We now check if Value can be encoded as a 26-bit signed immediate.
184  if (!isInt<26>(Value) && Ctx) {
185  Ctx->reportError(Fixup.getLoc(), "out of range PC26 fixup");
186  return 0;
187  }
188  break;
190  // Forcing a signed division because Value can be negative.
191  Value = (int64_t)Value / 2;
192  // We now check if Value can be encoded as a 26-bit signed immediate.
193  if (!isInt<26>(Value) && Ctx) {
194  Ctx->reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
195  return 0;
196  }
197  break;
199  // Forcing a signed division because Value can be negative.
200  Value = (int64_t)Value / 2;
201  // We now check if Value can be encoded as a 21-bit signed immediate.
202  if (!isInt<21>(Value) && Ctx) {
203  Ctx->reportError(Fixup.getLoc(), "out of range PC21 fixup");
204  return 0;
205  }
206  break;
207  }
208 
209  return Value;
210 }
211 
214  return createMipsELFObjectWriter(OS,
215  MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
216 }
217 
218 // Little-endian fixup data byte ordering:
219 // mips32r2: a | b | x | x
220 // microMIPS: x | x | a | b
221 
222 static bool needsMMLEByteOrder(unsigned Kind) {
223  return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
224  Kind >= Mips::fixup_MICROMIPS_26_S1 &&
226 }
227 
228 // Calculate index for microMIPS specific little endian byte order
229 static unsigned calculateMMLEIndex(unsigned i) {
230  assert(i <= 3 && "Index out of range!");
231 
232  return (1 - i / 2) * 2 + i % 2;
233 }
234 
235 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
236 /// data fragment, at the offset specified by the fixup and following the
237 /// fixup kind as appropriate.
238 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
239  unsigned DataSize, uint64_t Value,
240  bool IsPCRel) const {
241  MCFixupKind Kind = Fixup.getKind();
242  Value = adjustFixupValue(Fixup, Value);
243 
244  if (!Value)
245  return; // Doesn't change encoding.
246 
247  // Where do we start in the object
248  unsigned Offset = Fixup.getOffset();
249  // Number of bytes we need to fixup
250  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
251  // Used to point to big endian bytes
252  unsigned FullSize;
253 
254  switch ((unsigned)Kind) {
255  case FK_Data_2:
256  case Mips::fixup_Mips_16:
258  FullSize = 2;
259  break;
260  case FK_Data_8:
261  case Mips::fixup_Mips_64:
262  FullSize = 8;
263  break;
264  case FK_Data_4:
265  default:
266  FullSize = 4;
267  break;
268  }
269 
270  // Grab current value, if any, from bits.
271  uint64_t CurVal = 0;
272 
273  bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
274 
275  for (unsigned i = 0; i != NumBytes; ++i) {
276  unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
277  : i)
278  : (FullSize - 1 - i);
279  CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
280  }
281 
282  uint64_t Mask = ((uint64_t)(-1) >>
283  (64 - getFixupKindInfo(Kind).TargetSize));
284  CurVal |= Value & Mask;
285 
286  // Write out the fixed up bytes back to the code/data bits.
287  for (unsigned i = 0; i != NumBytes; ++i) {
288  unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
289  : i)
290  : (FullSize - 1 - i);
291  Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
292  }
293 }
294 
297  .Case("R_MIPS_NONE", (MCFixupKind)Mips::fixup_Mips_NONE)
298  .Case("R_MIPS_32", FK_Data_4)
300 }
301 
304  const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
305  // This table *must* be in same the order of fixup_* kinds in
306  // MipsFixupKinds.h.
307  //
308  // name offset bits flags
309  { "fixup_Mips_NONE", 0, 0, 0 },
310  { "fixup_Mips_16", 0, 16, 0 },
311  { "fixup_Mips_32", 0, 32, 0 },
312  { "fixup_Mips_REL32", 0, 32, 0 },
313  { "fixup_Mips_26", 0, 26, 0 },
314  { "fixup_Mips_HI16", 0, 16, 0 },
315  { "fixup_Mips_LO16", 0, 16, 0 },
316  { "fixup_Mips_GPREL16", 0, 16, 0 },
317  { "fixup_Mips_LITERAL", 0, 16, 0 },
318  { "fixup_Mips_GOT", 0, 16, 0 },
319  { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
320  { "fixup_Mips_CALL16", 0, 16, 0 },
321  { "fixup_Mips_GPREL32", 0, 32, 0 },
322  { "fixup_Mips_SHIFT5", 6, 5, 0 },
323  { "fixup_Mips_SHIFT6", 6, 5, 0 },
324  { "fixup_Mips_64", 0, 64, 0 },
325  { "fixup_Mips_TLSGD", 0, 16, 0 },
326  { "fixup_Mips_GOTTPREL", 0, 16, 0 },
327  { "fixup_Mips_TPREL_HI", 0, 16, 0 },
328  { "fixup_Mips_TPREL_LO", 0, 16, 0 },
329  { "fixup_Mips_TLSLDM", 0, 16, 0 },
330  { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
331  { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
332  { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
333  { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
334  { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
335  { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
336  { "fixup_Mips_GOT_OFST", 0, 16, 0 },
337  { "fixup_Mips_GOT_DISP", 0, 16, 0 },
338  { "fixup_Mips_HIGHER", 0, 16, 0 },
339  { "fixup_Mips_HIGHEST", 0, 16, 0 },
340  { "fixup_Mips_GOT_HI16", 0, 16, 0 },
341  { "fixup_Mips_GOT_LO16", 0, 16, 0 },
342  { "fixup_Mips_CALL_HI16", 0, 16, 0 },
343  { "fixup_Mips_CALL_LO16", 0, 16, 0 },
344  { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
345  { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
346  { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
347  { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
348  { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
349  { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
350  { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
351  { "fixup_MICROMIPS_HI16", 0, 16, 0 },
352  { "fixup_MICROMIPS_LO16", 0, 16, 0 },
353  { "fixup_MICROMIPS_GOT16", 0, 16, 0 },
354  { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel },
355  { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
356  { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
357  { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
358  { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
359  { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
360  { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
361  { "fixup_MICROMIPS_CALL16", 0, 16, 0 },
362  { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
363  { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
364  { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
365  { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
366  { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
367  { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
368  { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
369  { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
370  { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 },
371  { "fixup_Mips_SUB", 0, 64, 0 },
372  { "fixup_MICROMIPS_SUB", 0, 64, 0 }
373  };
374 
375  const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
376  // This table *must* be in same the order of fixup_* kinds in
377  // MipsFixupKinds.h.
378  //
379  // name offset bits flags
380  { "fixup_Mips_NONE", 0, 0, 0 },
381  { "fixup_Mips_16", 16, 16, 0 },
382  { "fixup_Mips_32", 0, 32, 0 },
383  { "fixup_Mips_REL32", 0, 32, 0 },
384  { "fixup_Mips_26", 6, 26, 0 },
385  { "fixup_Mips_HI16", 16, 16, 0 },
386  { "fixup_Mips_LO16", 16, 16, 0 },
387  { "fixup_Mips_GPREL16", 16, 16, 0 },
388  { "fixup_Mips_LITERAL", 16, 16, 0 },
389  { "fixup_Mips_GOT", 16, 16, 0 },
390  { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
391  { "fixup_Mips_CALL16", 16, 16, 0 },
392  { "fixup_Mips_GPREL32", 0, 32, 0 },
393  { "fixup_Mips_SHIFT5", 21, 5, 0 },
394  { "fixup_Mips_SHIFT6", 21, 5, 0 },
395  { "fixup_Mips_64", 0, 64, 0 },
396  { "fixup_Mips_TLSGD", 16, 16, 0 },
397  { "fixup_Mips_GOTTPREL", 16, 16, 0 },
398  { "fixup_Mips_TPREL_HI", 16, 16, 0 },
399  { "fixup_Mips_TPREL_LO", 16, 16, 0 },
400  { "fixup_Mips_TLSLDM", 16, 16, 0 },
401  { "fixup_Mips_DTPREL_HI", 16, 16, 0 },
402  { "fixup_Mips_DTPREL_LO", 16, 16, 0 },
403  { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
404  { "fixup_Mips_GPOFF_HI", 16, 16, 0 },
405  { "fixup_Mips_GPOFF_LO", 16, 16, 0 },
406  { "fixup_Mips_GOT_PAGE", 16, 16, 0 },
407  { "fixup_Mips_GOT_OFST", 16, 16, 0 },
408  { "fixup_Mips_GOT_DISP", 16, 16, 0 },
409  { "fixup_Mips_HIGHER", 16, 16, 0 },
410  { "fixup_Mips_HIGHEST", 16, 16, 0 },
411  { "fixup_Mips_GOT_HI16", 16, 16, 0 },
412  { "fixup_Mips_GOT_LO16", 16, 16, 0 },
413  { "fixup_Mips_CALL_HI16", 16, 16, 0 },
414  { "fixup_Mips_CALL_LO16", 16, 16, 0 },
415  { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
416  { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
417  { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
418  { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
419  { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
420  { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
421  { "fixup_MICROMIPS_26_S1", 6, 26, 0 },
422  { "fixup_MICROMIPS_HI16", 16, 16, 0 },
423  { "fixup_MICROMIPS_LO16", 16, 16, 0 },
424  { "fixup_MICROMIPS_GOT16", 16, 16, 0 },
425  { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel },
426  { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel },
427  { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
428  { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
429  { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel },
430  { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel },
431  { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel },
432  { "fixup_MICROMIPS_CALL16", 16, 16, 0 },
433  { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
434  { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
435  { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
436  { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
437  { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
438  { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
439  { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
440  { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
441  { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 },
442  { "fixup_Mips_SUB", 0, 64, 0 },
443  { "fixup_MICROMIPS_SUB", 0, 64, 0 }
444  };
445 
446  if (Kind < FirstTargetFixupKind)
447  return MCAsmBackend::getFixupKindInfo(Kind);
448 
449  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
450  "Invalid kind!");
451 
452  if (IsLittle)
453  return LittleEndianInfos[Kind - FirstTargetFixupKind];
454  return BigEndianInfos[Kind - FirstTargetFixupKind];
455 }
456 
457 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
458 /// to the given output. If the target cannot generate such a sequence,
459 /// it should return an error.
460 ///
461 /// \return - True on success.
462 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
463  // Check for a less than instruction size number of bytes
464  // FIXME: 16 bit instructions are not handled yet here.
465  // We shouldn't be using a hard coded number for instruction size.
466 
467  // If the count is not 4-byte aligned, we must be writing data into the text
468  // section (otherwise we have unaligned instructions, and thus have far
469  // bigger problems), so just write zeros instead.
470  OW->WriteZeros(Count);
471  return true;
472 }
473 
474 /// processFixupValue - Target hook to process the literal value of a fixup
475 /// if necessary.
477  const MCAsmLayout &Layout,
478  const MCFixup &Fixup,
479  const MCFragment *DF,
480  const MCValue &Target,
481  uint64_t &Value,
482  bool &IsResolved) {
483  // At this point we'll ignore the value returned by adjustFixupValue as
484  // we are only checking if the fixup can be applied correctly. We have
485  // access to MCContext from here which allows us to report a fatal error
486  // with *possibly* a source code location.
487  // The caller will also ignore any changes we make to Value
488  // (recordRelocation() overwrites it with it's own calculation).
489  (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
490 }
491 
492 // MCAsmBackend
494  const MCRegisterInfo &MRI,
495  const Triple &TT, StringRef CPU,
496  const MCTargetOptions &Options) {
497  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
498  /*Is64Bit*/ false);
499 }
500 
502  const MCRegisterInfo &MRI,
503  const Triple &TT, StringRef CPU,
504  const MCTargetOptions &Options) {
505  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
506  /*Is64Bit*/ false);
507 }
508 
510  const MCRegisterInfo &MRI,
511  const Triple &TT, StringRef CPU,
512  const MCTargetOptions &Options) {
513  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
514 }
515 
517  const MCRegisterInfo &MRI,
518  const Triple &TT, StringRef CPU,
519  const MCTargetOptions &Options) {
520  return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
521  /*Is64Bit*/ true);
522 }
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:279
static bool needsMMLEByteOrder(unsigned Kind)
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value, bool IsPCRel) const override
ApplyFixup - Apply the Value for given Fixup into the provided data fragment, at the offset specified...
void WriteZeros(unsigned N)
A eight-byte dtp relative fixup.
Definition: MCFixup.h:37
SMLoc getLoc() const
Definition: MCFixup.h:112
size_t i
This represents an "assembler immediate".
Definition: MCValue.h:40
static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx=nullptr)
MCAsmBackend * createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
MCContext & getContext() const
Definition: MCAssembler.h:258
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:66
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
MCAsmBackend * createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &IsResolved) override
processFixupValue - Target hook to process the literal value of a fixup if necessary.
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
A four-byte tp relative fixup.
Definition: MCFixup.h:38
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
A four-byte fixup.
Definition: MCFixup.h:26
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Context object for machine code objects.
Definition: MCContext.h:51
A four-byte gp relative fixup.
Definition: MCFixup.h:34
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override
WriteNopData - Write an (optimal) nop sequence of Count bytes to the given output.
uint32_t getOffset() const
Definition: MCFixup.h:95
MCAsmBackend * createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
A four-byte dtp relative fixup.
Definition: MCFixup.h:36
unsigned const MachineRegisterInfo * MRI
MCObjectWriter * createObjectWriter(raw_pwrite_stream &OS) const override
Create a new MCObjectWriter instance for use by the assembler backend to emit the final object file...
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
virtual Optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
uint32_t Offset
A eight-byte tp relative fixup.
Definition: MCFixup.h:39
MCFixupKind getKind() const
Definition: MCFixup.h:93
MCObjectWriter * createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool Is64Bit)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned TargetSize
The number of bits written by this fixup.
Target - Wrapper for Target specific information.
A eight-byte fixup.
Definition: MCFixup.h:27
Optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
MCAsmBackend * createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:333
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static unsigned calculateMMLEIndex(unsigned i)
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
A two-byte fixup.
Definition: MCFixup.h:25