LLVM  4.0.0
ARMBaseInstrInfo.h
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
16 
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/Support/CodeGen.h"
23 
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
26 
27 namespace llvm {
28  class ARMSubtarget;
29  class ARMBaseRegisterInfo;
30 
32  const ARMSubtarget &Subtarget;
33 
34 protected:
35  // Can be only subclassed.
36  explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
37 
39  unsigned LoadImmOpc, unsigned LoadOpc) const;
40 
41  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
42  /// and \p DefIdx.
43  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
44  /// the list is modeled as <Reg:SubReg, SubIdx>.
45  /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
46  /// two elements:
47  /// - vreg1:sub1, sub0
48  /// - vreg2<:0>, sub1
49  ///
50  /// \returns true if it is possible to build such an input sequence
51  /// with the pair \p MI, \p DefIdx. False otherwise.
52  ///
53  /// \pre MI.isRegSequenceLike().
55  const MachineInstr &MI, unsigned DefIdx,
56  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
57 
58  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
59  /// and \p DefIdx.
60  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
61  /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
62  /// - vreg1:sub1, sub0
63  ///
64  /// \returns true if it is possible to build such an input sequence
65  /// with the pair \p MI, \p DefIdx. False otherwise.
66  ///
67  /// \pre MI.isExtractSubregLike().
68  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
69  RegSubRegPairAndIdx &InputReg) const override;
70 
71  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
72  /// and \p DefIdx.
73  /// \p [out] BaseReg and \p [out] InsertedReg contain
74  /// the equivalent inputs of INSERT_SUBREG.
75  /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
76  /// - BaseReg: vreg0:sub0
77  /// - InsertedReg: vreg1:sub1, sub3
78  ///
79  /// \returns true if it is possible to build such an input sequence
80  /// with the pair \p MI, \p DefIdx. False otherwise.
81  ///
82  /// \pre MI.isInsertSubregLike().
83  bool
84  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85  RegSubRegPair &BaseReg,
86  RegSubRegPairAndIdx &InsertedReg) const override;
87 
88  /// Commutes the operands in the given instruction.
89  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
90  ///
91  /// Do not call this method for a non-commutable instruction or for
92  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
93  /// Even though the instruction is commutable, the method may still
94  /// fail to commute the operands, null pointer is returned in such cases.
96  unsigned OpIdx1,
97  unsigned OpIdx2) const override;
98 
99 public:
100  // Return whether the target has an explicit NOP encoding.
101  bool hasNOP() const;
102 
103  virtual void getNoopForElfTarget(MCInst &NopInst) const {
104  getNoopForMachoTarget(NopInst);
105  }
106 
107  // Return the non-pre/post incrementing version of 'Opc'. Return 0
108  // if there is not such an opcode.
109  virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
110 
112  MachineInstr &MI,
113  LiveVariables *LV) const override;
114 
115  virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
116  const ARMSubtarget &getSubtarget() const { return Subtarget; }
117 
120  const ScheduleDAG *DAG) const override;
121 
124  const ScheduleDAG *DAG) const override;
125 
126  // Branch analysis.
128  MachineBasicBlock *&FBB,
130  bool AllowModify = false) const override;
132  int *BytesRemoved = nullptr) const override;
135  const DebugLoc &DL,
136  int *BytesAdded = nullptr) const override;
137 
138  bool
140 
141  // Predication support.
142  bool isPredicated(const MachineInstr &MI) const override;
143 
145  int PIdx = MI.findFirstPredOperandIdx();
146  return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
147  : ARMCC::AL;
148  }
149 
151  ArrayRef<MachineOperand> Pred) const override;
152 
154  ArrayRef<MachineOperand> Pred2) const override;
155 
157  std::vector<MachineOperand> &Pred) const override;
158 
159  bool isPredicable(MachineInstr &MI) const override;
160 
161  /// GetInstSize - Returns the size of the specified MachineInstr.
162  ///
163  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
164 
165  unsigned isLoadFromStackSlot(const MachineInstr &MI,
166  int &FrameIndex) const override;
167  unsigned isStoreToStackSlot(const MachineInstr &MI,
168  int &FrameIndex) const override;
169  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
170  int &FrameIndex) const override;
171  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
172  int &FrameIndex) const override;
173 
175  unsigned SrcReg, bool KillSrc,
176  const ARMSubtarget &Subtarget) const;
178  unsigned DestReg, bool KillSrc,
179  const ARMSubtarget &Subtarget) const;
180 
182  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
183  bool KillSrc) const override;
184 
187  unsigned SrcReg, bool isKill, int FrameIndex,
188  const TargetRegisterClass *RC,
189  const TargetRegisterInfo *TRI) const override;
190 
193  unsigned DestReg, int FrameIndex,
194  const TargetRegisterClass *RC,
195  const TargetRegisterInfo *TRI) const override;
196 
197  bool expandPostRAPseudo(MachineInstr &MI) const override;
198 
200  unsigned DestReg, unsigned SubIdx,
201  const MachineInstr &Orig,
202  const TargetRegisterInfo &TRI) const override;
203 
205  MachineFunction &MF) const override;
206 
207  const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
208  unsigned SubIdx, unsigned State,
209  const TargetRegisterInfo *TRI) const;
210 
211  bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
212  const MachineRegisterInfo *MRI) const override;
213 
214  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
215  /// determine if two loads are loading from the same base address. It should
216  /// only return true if the base pointers are the same and the only
217  /// differences between the two addresses is the offset. It also returns the
218  /// offsets by reference.
219  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
220  int64_t &Offset2) const override;
221 
222  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
223  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
224  /// should be scheduled togther. On some targets if two loads are loading from
225  /// addresses in the same cache line, it's better if they are scheduled
226  /// together. This function takes two integers that represent the load offsets
227  /// from the common base address. It returns true if it decides it's desirable
228  /// to schedule the two loads together. "NumLoads" is the number of loads that
229  /// have already been scheduled after Load1.
230  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
231  int64_t Offset1, int64_t Offset2,
232  unsigned NumLoads) const override;
233 
234  bool isSchedulingBoundary(const MachineInstr &MI,
235  const MachineBasicBlock *MBB,
236  const MachineFunction &MF) const override;
237 
239  unsigned NumCycles, unsigned ExtraPredCycles,
240  BranchProbability Probability) const override;
241 
242  bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
243  unsigned ExtraT, MachineBasicBlock &FMBB,
244  unsigned NumF, unsigned ExtraF,
245  BranchProbability Probability) const override;
246 
248  BranchProbability Probability) const override {
249  return NumCycles == 1;
250  }
251 
253  MachineBasicBlock &FMBB) const override;
254 
255  /// analyzeCompare - For a comparison instruction, return the source registers
256  /// in SrcReg and SrcReg2 if having two register operands, and the value it
257  /// compares against in CmpValue. Return true if the comparison instruction
258  /// can be analyzed.
259  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
260  unsigned &SrcReg2, int &CmpMask,
261  int &CmpValue) const override;
262 
263  /// optimizeCompareInstr - Convert the instruction to set the zero flag so
264  /// that we can remove a "comparison with zero"; Remove a redundant CMP
265  /// instruction if the flags can be updated in the same way by an earlier
266  /// instruction such as SUB.
267  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
268  unsigned SrcReg2, int CmpMask, int CmpValue,
269  const MachineRegisterInfo *MRI) const override;
270 
271  bool analyzeSelect(const MachineInstr &MI,
272  SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
273  unsigned &FalseOp, bool &Optimizable) const override;
274 
277  bool) const override;
278 
279  /// FoldImmediate - 'Reg' is known to be defined by a move immediate
280  /// instruction, try to fold the immediate into the use instruction.
281  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
282  MachineRegisterInfo *MRI) const override;
283 
284  unsigned getNumMicroOps(const InstrItineraryData *ItinData,
285  const MachineInstr &MI) const override;
286 
287  int getOperandLatency(const InstrItineraryData *ItinData,
288  const MachineInstr &DefMI, unsigned DefIdx,
289  const MachineInstr &UseMI,
290  unsigned UseIdx) const override;
291  int getOperandLatency(const InstrItineraryData *ItinData,
292  SDNode *DefNode, unsigned DefIdx,
293  SDNode *UseNode, unsigned UseIdx) const override;
294 
295  /// VFP/NEON execution domains.
296  std::pair<uint16_t, uint16_t>
297  getExecutionDomain(const MachineInstr &MI) const override;
298  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
299 
300  unsigned
301  getPartialRegUpdateClearance(const MachineInstr &, unsigned,
302  const TargetRegisterInfo *) const override;
303  void breakPartialRegDependency(MachineInstr &, unsigned,
304  const TargetRegisterInfo *TRI) const override;
305 
306  /// Get the number of addresses by LDM or VLDM or zero for unknown.
307  unsigned getNumLDMAddresses(const MachineInstr &MI) const;
308 
309 private:
310  unsigned getInstBundleLength(const MachineInstr &MI) const;
311 
312  int getVLDMDefCycle(const InstrItineraryData *ItinData,
313  const MCInstrDesc &DefMCID,
314  unsigned DefClass,
315  unsigned DefIdx, unsigned DefAlign) const;
316  int getLDMDefCycle(const InstrItineraryData *ItinData,
317  const MCInstrDesc &DefMCID,
318  unsigned DefClass,
319  unsigned DefIdx, unsigned DefAlign) const;
320  int getVSTMUseCycle(const InstrItineraryData *ItinData,
321  const MCInstrDesc &UseMCID,
322  unsigned UseClass,
323  unsigned UseIdx, unsigned UseAlign) const;
324  int getSTMUseCycle(const InstrItineraryData *ItinData,
325  const MCInstrDesc &UseMCID,
326  unsigned UseClass,
327  unsigned UseIdx, unsigned UseAlign) const;
328  int getOperandLatency(const InstrItineraryData *ItinData,
329  const MCInstrDesc &DefMCID,
330  unsigned DefIdx, unsigned DefAlign,
331  const MCInstrDesc &UseMCID,
332  unsigned UseIdx, unsigned UseAlign) const;
333 
334  int getOperandLatencyImpl(const InstrItineraryData *ItinData,
335  const MachineInstr &DefMI, unsigned DefIdx,
336  const MCInstrDesc &DefMCID, unsigned DefAdj,
337  const MachineOperand &DefMO, unsigned Reg,
338  const MachineInstr &UseMI, unsigned UseIdx,
339  const MCInstrDesc &UseMCID, unsigned UseAdj) const;
340 
341  unsigned getPredicationCost(const MachineInstr &MI) const override;
342 
343  unsigned getInstrLatency(const InstrItineraryData *ItinData,
344  const MachineInstr &MI,
345  unsigned *PredCost = nullptr) const override;
346 
347  int getInstrLatency(const InstrItineraryData *ItinData,
348  SDNode *Node) const override;
349 
350  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
351  const MachineRegisterInfo *MRI,
352  const MachineInstr &DefMI, unsigned DefIdx,
353  const MachineInstr &UseMI,
354  unsigned UseIdx) const override;
355  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
356  const MachineInstr &DefMI,
357  unsigned DefIdx) const override;
358 
359  /// verifyInstruction - Perform target specific instruction verification.
360  bool verifyInstruction(const MachineInstr &MI,
361  StringRef &ErrInfo) const override;
362 
363  virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
364 
365  void expandMEMCPY(MachineBasicBlock::iterator) const;
366 
367 private:
368  /// Modeling special VFP / NEON fp MLA / MLS hazards.
369 
370  /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
371  /// MLx table.
372  DenseMap<unsigned, unsigned> MLxEntryMap;
373 
374  /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
375  /// stalls when scheduled together with fp MLA / MLS opcodes.
376  SmallSet<unsigned, 16> MLxHazardOpcodes;
377 
378 public:
379  /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
380  /// instruction.
381  bool isFpMLxInstruction(unsigned Opcode) const {
382  return MLxEntryMap.count(Opcode);
383  }
384 
385  /// isFpMLxInstruction - This version also returns the multiply opcode and the
386  /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
387  /// the MLX instructions with an extra lane operand.
388  bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
389  unsigned &AddSubOpc, bool &NegAcc,
390  bool &HasLane) const;
391 
392  /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
393  /// will cause stalls when scheduled after (within 4-cycle window) a fp
394  /// MLA / MLS instruction.
395  bool canCauseFpMLxStall(unsigned Opcode) const {
396  return MLxHazardOpcodes.count(Opcode);
397  }
398 
399  /// Returns true if the instruction has a shift by immediate that can be
400  /// executed in one cycle less.
401  bool isSwiftFastImmShift(const MachineInstr *MI) const;
402 };
403 
404 static inline
406  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
407 }
408 
409 static inline
411  return MIB.addReg(0);
412 }
413 
414 static inline
416  bool isDead = false) {
417  return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
418 }
419 
420 static inline
422  return MIB.addReg(0);
423 }
424 
425 static inline
426 bool isUncondBranchOpcode(int Opc) {
427  return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
428 }
429 
430 static inline
431 bool isCondBranchOpcode(int Opc) {
432  return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
433 }
434 
435 static inline
436 bool isJumpTableBranchOpcode(int Opc) {
437  return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
438  Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
439 }
440 
441 static inline
442 bool isIndirectBranchOpcode(int Opc) {
443  return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
444 }
445 
446 static inline bool isPopOpcode(int Opc) {
447  return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
448  Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
449  Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
450 }
451 
452 static inline bool isPushOpcode(int Opc) {
453  return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
454  Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
455 }
456 
457 /// getInstrPredicate - If instruction is predicated, returns its predicate
458 /// condition, otherwise returns AL. It also returns the condition code
459 /// register by reference.
460 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
461 
462 unsigned getMatchingCondBranchOpcode(unsigned Opc);
463 
464 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
465 /// opcode of the SSA instruction representing the conditional MI.
466 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
467  MachineInstr *&MI,
468  const MachineRegisterInfo &MRI);
469 
470 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
471 /// the instruction is encoded with an 'S' bit is determined by the optional
472 /// CPSR def operand.
473 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
474 
475 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
476 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
477 /// code.
478 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
480  const DebugLoc &dl, unsigned DestReg,
481  unsigned BaseReg, int NumBytes,
482  ARMCC::CondCodes Pred, unsigned PredReg,
483  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
484 
485 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
487  const DebugLoc &dl, unsigned DestReg,
488  unsigned BaseReg, int NumBytes,
489  ARMCC::CondCodes Pred, unsigned PredReg,
490  const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
491 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
493  const DebugLoc &dl, unsigned DestReg,
494  unsigned BaseReg, int NumBytes,
495  const TargetInstrInfo &TII,
496  const ARMBaseRegisterInfo &MRI,
497  unsigned MIFlags = 0);
498 
499 /// Tries to add registers to the reglist of a given base-updating
500 /// push/pop instruction to adjust the stack by an additional
501 /// NumBytes. This can save a few bytes per function in code-size, but
502 /// obviously generates more memory traffic. As such, it only takes
503 /// effect in functions being optimised for size.
504 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
505  MachineFunction &MF, MachineInstr *MI,
506  unsigned NumBytes);
507 
508 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
509 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
510 /// offset could not be handled directly in MI, and return the left-over
511 /// portion by reference.
512 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
513  unsigned FrameReg, int &Offset,
514  const ARMBaseInstrInfo &TII);
515 
516 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
517  unsigned FrameReg, int &Offset,
518  const ARMBaseInstrInfo &TII);
519 
520 } // End llvm namespace
521 
522 #endif
bool isPredicable(MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
virtual void getNoopForElfTarget(MCInst &NopInst) const
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isPredicated(const MachineInstr &MI) const override
MachineInstrBundleIterator< MachineInstr > iterator
A debug info location.
Definition: DebugLoc.h:34
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:345
static const MachineInstrBuilder & AddNoT1CC(const MachineInstrBuilder &MIB)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
Reg
All possible values of the reg field in the ModR/M byte.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
MachineBasicBlock * MBB
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
unsigned getMatchingCondBranchOpcode(unsigned Opc)
int64_t getImm() const
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static bool isCondBranchOpcode(int Opc)
unsigned getDeadRegState(bool B)
unsigned getDefRegState(bool B)
unsigned const MachineRegisterInfo * MRI
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
MachineInstrBuilder & UseMI
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
static bool isJumpTableBranchOpcode(int Opc)
uint32_t Offset
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
MachineInstr * duplicate(MachineInstr &Orig, MachineFunction &MF) const override
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:64
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static bool isIndirectBranchOpcode(int Opc)
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Iterator for intrusive lists based on ilist_node.
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
MachineOperand class - Representation of each machine instruction operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:122
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
unsigned canFoldARMInstrIntoMOVCC(unsigned Reg, MachineInstr *&MI, const MachineRegisterInfo &MRI)
Determine if MI can be folded into an ARM MOVCC instruction, and return the opcode of the SSA instruc...
ARMBaseInstrInfo(const ARMSubtarget &STI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
static bool isPopOpcode(int Opc)
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
#define I(x, y, z)
Definition: MD5.cpp:54
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
const ARMSubtarget & getSubtarget() const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override