LLVM  4.0.0
X86BaseInfo.h
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1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the X86 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
19 
20 #include "X86MCTargetDesc.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/DataTypes.h"
24 
25 namespace llvm {
26 
27 namespace X86 {
28  // Enums for memory operand decoding. Each memory operand is represented with
29  // a 5 operand sequence in the form:
30  // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
31  // These enums help decode this.
32  enum {
36  AddrDisp = 3,
37 
38  /// AddrSegmentReg - The operand # of the segment in the memory operand.
40 
41  /// AddrNumOperands - Total number of operands in a memory reference.
43  };
44 
45  /// AVX512 static rounding constants. These need to match the values in
46  /// avx512fintrin.h.
51  TO_ZERO = 3,
53  };
54 } // end namespace X86;
55 
56 /// X86II - This namespace holds all of the target specific flags that
57 /// instruction info tracks.
58 ///
59 namespace X86II {
60  /// Target Operand Flag enum.
61  enum TOF {
62  //===------------------------------------------------------------------===//
63  // X86 Specific MachineOperand flags.
64 
66 
67  /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
68  /// relocation of:
69  /// SYMBOL_LABEL + [. - PICBASELABEL]
71 
72  /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
73  /// immediate should get the value of the symbol minus the PIC base label:
74  /// SYMBOL_LABEL - PICBASELABEL
76 
77  /// MO_GOT - On a symbol operand this indicates that the immediate is the
78  /// offset to the GOT entry for the symbol name from the base of the GOT.
79  ///
80  /// See the X86-64 ELF ABI supplement for more details.
81  /// SYMBOL_LABEL @GOT
83 
84  /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
85  /// the offset to the location of the symbol name from the base of the GOT.
86  ///
87  /// See the X86-64 ELF ABI supplement for more details.
88  /// SYMBOL_LABEL @GOTOFF
90 
91  /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
92  /// offset to the GOT entry for the symbol name from the current code
93  /// location.
94  ///
95  /// See the X86-64 ELF ABI supplement for more details.
96  /// SYMBOL_LABEL @GOTPCREL
98 
99  /// MO_PLT - On a symbol operand this indicates that the immediate is
100  /// offset to the PLT entry of symbol name from the current code location.
101  ///
102  /// See the X86-64 ELF ABI supplement for more details.
103  /// SYMBOL_LABEL @PLT
105 
106  /// MO_TLSGD - On a symbol operand this indicates that the immediate is
107  /// the offset of the GOT entry with the TLS index structure that contains
108  /// the module number and variable offset for the symbol. Used in the
109  /// general dynamic TLS access model.
110  ///
111  /// See 'ELF Handling for Thread-Local Storage' for more details.
112  /// SYMBOL_LABEL @TLSGD
114 
115  /// MO_TLSLD - On a symbol operand this indicates that the immediate is
116  /// the offset of the GOT entry with the TLS index for the module that
117  /// contains the symbol. When this index is passed to a call to
118  /// __tls_get_addr, the function will return the base address of the TLS
119  /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
120  ///
121  /// See 'ELF Handling for Thread-Local Storage' for more details.
122  /// SYMBOL_LABEL @TLSLD
124 
125  /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
126  /// the offset of the GOT entry with the TLS index for the module that
127  /// contains the symbol. When this index is passed to a call to
128  /// ___tls_get_addr, the function will return the base address of the TLS
129  /// block for the symbol. Used in the IA32 local dynamic TLS access model.
130  ///
131  /// See 'ELF Handling for Thread-Local Storage' for more details.
132  /// SYMBOL_LABEL @TLSLDM
134 
135  /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
136  /// the offset of the GOT entry with the thread-pointer offset for the
137  /// symbol. Used in the x86-64 initial exec TLS access model.
138  ///
139  /// See 'ELF Handling for Thread-Local Storage' for more details.
140  /// SYMBOL_LABEL @GOTTPOFF
142 
143  /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
144  /// the absolute address of the GOT entry with the negative thread-pointer
145  /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
146  /// model.
147  ///
148  /// See 'ELF Handling for Thread-Local Storage' for more details.
149  /// SYMBOL_LABEL @INDNTPOFF
151 
152  /// MO_TPOFF - On a symbol operand this indicates that the immediate is
153  /// the thread-pointer offset for the symbol. Used in the x86-64 local
154  /// exec TLS access model.
155  ///
156  /// See 'ELF Handling for Thread-Local Storage' for more details.
157  /// SYMBOL_LABEL @TPOFF
159 
160  /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
161  /// the offset of the GOT entry with the TLS offset of the symbol. Used
162  /// in the local dynamic TLS access model.
163  ///
164  /// See 'ELF Handling for Thread-Local Storage' for more details.
165  /// SYMBOL_LABEL @DTPOFF
167 
168  /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
169  /// the negative thread-pointer offset for the symbol. Used in the IA32
170  /// local exec TLS access model.
171  ///
172  /// See 'ELF Handling for Thread-Local Storage' for more details.
173  /// SYMBOL_LABEL @NTPOFF
175 
176  /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
177  /// the offset of the GOT entry with the negative thread-pointer offset for
178  /// the symbol. Used in the PIC IA32 initial exec TLS access model.
179  ///
180  /// See 'ELF Handling for Thread-Local Storage' for more details.
181  /// SYMBOL_LABEL @GOTNTPOFF
183 
184  /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
185  /// reference is actually to the "__imp_FOO" symbol. This is used for
186  /// dllimport linkage on windows.
188 
189  /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
190  /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
191  /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
193 
194  /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
195  /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
196  /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
198 
199  /// MO_TLVP - On a symbol operand this indicates that the immediate is
200  /// some TLS offset.
201  ///
202  /// This is the TLS offset for the Darwin TLS mechanism.
204 
205  /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
206  /// is some TLS offset from the picbase.
207  ///
208  /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
210 
211  /// MO_SECREL - On a symbol operand this indicates that the immediate is
212  /// the offset from beginning of section.
213  ///
214  /// This is the TLS offset for the COFF/Windows TLS mechanism.
216  };
217 
218  enum : uint64_t {
219  //===------------------------------------------------------------------===//
220  // Instruction encodings. These are the standard/most common forms for X86
221  // instructions.
222  //
223 
224  // PseudoFrm - This represents an instruction that is a pseudo instruction
225  // or one that has not been implemented yet. It is illegal to code generate
226  // it, but tolerated for intermediate implementation stages.
227  Pseudo = 0,
228 
229  /// Raw - This form is for instructions that don't have any operands, so
230  /// they are just a fixed opcode value, like 'leave'.
231  RawFrm = 1,
232 
233  /// AddRegFrm - This form is used for instructions like 'push r32' that have
234  /// their one register operand added to their opcode.
236 
237  /// RawFrmMemOffs - This form is for instructions that store an absolute
238  /// memory offset as an immediate with a possible segment override.
240 
241  /// RawFrmSrc - This form is for instructions that use the source index
242  /// register SI/ESI/RSI with a possible segment override.
244 
245  /// RawFrmDst - This form is for instructions that use the destination index
246  /// register DI/EDI/ESI.
248 
249  /// RawFrmSrc - This form is for instructions that use the source index
250  /// register SI/ESI/ERI with a possible segment override, and also the
251  /// destination index register DI/ESI/RDI.
253 
254  /// RawFrmImm8 - This is used for the ENTER instruction, which has two
255  /// immediates, the first of which is a 16-bit immediate (specified by
256  /// the imm encoding) and the second is a 8-bit fixed value.
258 
259  /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
260  /// immediates, the first of which is a 16 or 32-bit immediate (specified by
261  /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
262  /// manual, this operand is described as pntr16:32 and pntr16:16
264 
265  /// MRM[0-7][rm] - These forms are used to represent instructions that use
266  /// a Mod/RM byte, and use the middle field to hold extended opcode
267  /// information. In the intel manual these are represented as /0, /1, ...
268  ///
269 
270  /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
271  /// to specify a destination, which in this case is memory.
272  ///
274 
275  /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
276  /// to specify a source, which in this case is memory.
277  ///
278  MRMSrcMem = 33,
279 
280  /// MRMSrcMem4VOp3 - This form is used for instructions that encode
281  /// operand 3 with VEX.VVVV and load from memory.
282  ///
284 
285  /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
286  /// byte to specify the fourth source, which in this case is memory.
287  ///
289 
290  /// MRMXm - This form is used for instructions that use the Mod/RM byte
291  /// to specify a memory source, but doesn't use the middle field.
292  ///
293  MRMXm = 39, // Instruction that uses Mod/RM but not the middle field.
294 
295  // Next, instructions that operate on a memory r/m operand...
296  MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3
297  MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7
298 
299  /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
300  /// to specify a destination, which in this case is a register.
301  ///
303 
304  /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
305  /// to specify a source, which in this case is a register.
306  ///
307  MRMSrcReg = 49,
308 
309  /// MRMSrcReg4VOp3 - This form is used for instructions that encode
310  /// operand 3 with VEX.VVVV and do not load from memory.
311  ///
313 
314  /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
315  /// byte to specify the fourth source, which in this case is a register.
316  ///
318 
319  /// MRMXr - This form is used for instructions that use the Mod/RM byte
320  /// to specify a register source, but doesn't use the middle field.
321  ///
322  MRMXr = 55, // Instruction that uses Mod/RM but not the middle field.
323 
324  // Instructions that operate on a register r/m operand...
325  MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3
326  MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7
327 
328  /// MRM_XX - A mod/rm byte of exactly 0xXX.
329  MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67,
330  MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71,
331  MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75,
332  MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79,
333  MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83,
334  MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87,
335  MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91,
336  MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95,
337  MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99,
338  MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103,
339  MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107,
340  MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111,
341  MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115,
342  MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119,
343  MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123,
344  MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127,
345 
346  FormMask = 127,
347 
348  //===------------------------------------------------------------------===//
349  // Actual flags...
350 
351  // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
352  // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
353  // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
354  // prefix in 16-bit mode.
357 
361 
362  // AsSize - AdSizeX implies this instruction determines its need of 0x67
363  // prefix from a normal ModRM memory operand. The other types indicate that
364  // an operand is encoded with a specific width and a prefix is needed if
365  // it differs from the current mode.
368 
373 
374  //===------------------------------------------------------------------===//
375  // OpPrefix - There are several prefix bytes that are used as opcode
376  // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
377  // no prefix.
378  //
381 
382  // PS, PD - Prefix code for packed single and double precision vector
383  // floating point operations performed in the SSE registers.
385 
386  // XS, XD - These prefix codes are for single and double precision scalar
387  // floating point operations performed in the SSE registers.
389 
390  //===------------------------------------------------------------------===//
391  // OpMap - This field determines which opcode map this instruction
392  // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
393  //
396 
397  // OB - OneByte - Set if this instruction has a one byte opcode.
398  OB = 0 << OpMapShift,
399 
400  // TB - TwoByte - Set if this instruction has a two byte opcode, which
401  // starts with a 0x0F byte before the real opcode.
402  TB = 1 << OpMapShift,
403 
404  // T8, TA - Prefix after the 0x0F prefix.
405  T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
406 
407  // XOP8 - Prefix to include use of imm byte.
408  XOP8 = 4 << OpMapShift,
409 
410  // XOP9 - Prefix to exclude use of imm byte.
411  XOP9 = 5 << OpMapShift,
412 
413  // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
414  XOPA = 6 << OpMapShift,
415 
416  //===------------------------------------------------------------------===//
417  // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
418  // They are used to specify GPRs and SSE registers, 64-bit operand size,
419  // etc. We only cares about REX.W and REX.R bits and only the former is
420  // statically determined.
421  //
423  REX_W = 1 << REXShift,
424 
425  //===------------------------------------------------------------------===//
426  // This three-bit field describes the size of an immediate operand. Zero is
427  // unused so that we can tell if we forgot to set a value.
429  ImmMask = 15 << ImmShift,
430  Imm8 = 1 << ImmShift,
433  Imm16 = 4 << ImmShift,
435  Imm32 = 6 << ImmShift,
437  Imm32S = 8 << ImmShift,
438  Imm64 = 9 << ImmShift,
439 
440  //===------------------------------------------------------------------===//
441  // FP Instruction Classification... Zero is non-fp instruction.
442 
443  // FPTypeMask - Mask for all of the FP types...
446 
447  // NotFP - The default, set for instructions that do not use FP registers.
449 
450  // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
452 
453  // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
455 
456  // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
457  // result back to ST(0). For example, fcos, fsqrt, etc.
458  //
460 
461  // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
462  // explicit argument, storing the result to either ST(0) or the implicit
463  // argument. For example: fadd, fsub, fmul, etc...
465 
466  // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
467  // explicit argument, but have no destination. Example: fucom, fucomi, ...
469 
470  // CondMovFP - "2 operand" floating point conditional move instructions.
472 
473  // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
475 
476  // Lock prefix
478  LOCK = 1 << LOCKShift,
479 
480  // REP prefix
482  REP = 1 << REPShift,
483 
484  // Execution domain for SSE instructions.
485  // 0 means normal, non-SSE instruction.
487 
488  // Encoding
491 
492  // VEX - encoding using 0xC4/0xC5
494 
495  /// XOP - Opcode prefix used by XOP instructions.
497 
498  // VEX_EVEX - Specifies that this instruction use EVEX form which provides
499  // syntax support up to 32 512-bit register operands and up to 7 16-bit
500  // mask operands as well as source operand data swizzling/memory operand
501  // conversion, eviction hint, and rounding mode.
503 
504  // Opcode
506 
507  /// VEX_W - Has a opcode specific functionality, but is used in the same
508  /// way as REX_W is for regular SSE instructions.
510  VEX_W = 1ULL << VEX_WShift,
511 
512  /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
513  /// address instructions in SSE are represented as 3 address ones in AVX
514  /// and the additional register is encoded in VEX_VVVV prefix.
515  VEX_4VShift = VEX_WShift + 1,
516  VEX_4V = 1ULL << VEX_4VShift,
517 
518  /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
519  /// instruction uses 256-bit wide registers. This is usually auto detected
520  /// if a VR256 register is used, but some AVX instructions also have this
521  /// field marked when using a f256 memory references.
522  VEX_LShift = VEX_4VShift + 1,
523  VEX_L = 1ULL << VEX_LShift,
524 
525  // EVEX_K - Set if this instruction requires masking
526  EVEX_KShift = VEX_LShift + 1,
527  EVEX_K = 1ULL << EVEX_KShift,
528 
529  // EVEX_Z - Set if this instruction has EVEX.Z field set.
530  EVEX_ZShift = EVEX_KShift + 1,
531  EVEX_Z = 1ULL << EVEX_ZShift,
532 
533  // EVEX_L2 - Set if this instruction has EVEX.L' field set.
534  EVEX_L2Shift = EVEX_ZShift + 1,
536 
537  // EVEX_B - Set if this instruction has EVEX.B field set.
538  EVEX_BShift = EVEX_L2Shift + 1,
539  EVEX_B = 1ULL << EVEX_BShift,
540 
541  // The scaling factor for the AVX512's 8-bit compressed displacement.
542  CD8_Scale_Shift = EVEX_BShift + 1,
544 
545  /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
546  /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
547  /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
548  /// storing a classifier in the imm8 field. To simplify our implementation,
549  /// we handle this by storeing the classifier in the opcode field and using
550  /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
551  Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7,
553 
554  /// Explicitly specified rounding control
555  EVEX_RCShift = Has3DNow0F0FOpcodeShift + 1,
557  };
558 
559  // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
560  // specified machine instruction.
561  //
562  inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
563  return TSFlags >> X86II::OpcodeShift;
564  }
565 
566  inline bool hasImm(uint64_t TSFlags) {
567  return (TSFlags & X86II::ImmMask) != 0;
568  }
569 
570  /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
571  /// of the specified instruction.
572  inline unsigned getSizeOfImm(uint64_t TSFlags) {
573  switch (TSFlags & X86II::ImmMask) {
574  default: llvm_unreachable("Unknown immediate size");
575  case X86II::Imm8:
576  case X86II::Imm8PCRel:
577  case X86II::Imm8Reg: return 1;
578  case X86II::Imm16:
579  case X86II::Imm16PCRel: return 2;
580  case X86II::Imm32:
581  case X86II::Imm32S:
582  case X86II::Imm32PCRel: return 4;
583  case X86II::Imm64: return 8;
584  }
585  }
586 
587  /// isImmPCRel - Return true if the immediate of the specified instruction's
588  /// TSFlags indicates that it is pc relative.
589  inline unsigned isImmPCRel(uint64_t TSFlags) {
590  switch (TSFlags & X86II::ImmMask) {
591  default: llvm_unreachable("Unknown immediate size");
592  case X86II::Imm8PCRel:
593  case X86II::Imm16PCRel:
594  case X86II::Imm32PCRel:
595  return true;
596  case X86II::Imm8:
597  case X86II::Imm8Reg:
598  case X86II::Imm16:
599  case X86II::Imm32:
600  case X86II::Imm32S:
601  case X86II::Imm64:
602  return false;
603  }
604  }
605 
606  /// isImmSigned - Return true if the immediate of the specified instruction's
607  /// TSFlags indicates that it is signed.
608  inline unsigned isImmSigned(uint64_t TSFlags) {
609  switch (TSFlags & X86II::ImmMask) {
610  default: llvm_unreachable("Unknown immediate signedness");
611  case X86II::Imm32S:
612  return true;
613  case X86II::Imm8:
614  case X86II::Imm8PCRel:
615  case X86II::Imm8Reg:
616  case X86II::Imm16:
617  case X86II::Imm16PCRel:
618  case X86II::Imm32:
619  case X86II::Imm32PCRel:
620  case X86II::Imm64:
621  return false;
622  }
623  }
624 
625  /// getOperandBias - compute any additional adjustment needed to
626  /// the offset to the start of the memory operand
627  /// in this instruction.
628  /// If this is a two-address instruction,skip one of the register operands.
629  /// FIXME: This should be handled during MCInst lowering.
630  inline unsigned getOperandBias(const MCInstrDesc& Desc)
631  {
632  unsigned NumOps = Desc.getNumOperands();
633  if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
634  return 1;
635  if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
636  Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
637  // Special case for AVX-512 GATHER with 2 TIED_TO operands
638  // Skip the first 2 operands: dst, mask_wb
639  return 2;
640  if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
641  Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
642  // Special case for GATHER with 2 TIED_TO operands
643  // Skip the first 2 operands: dst, mask_wb
644  return 2;
645  if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
646  // SCATTER
647  return 1;
648  return 0;
649  }
650 
651  /// getMemoryOperandNo - The function returns the MCInst operand # for the
652  /// first field of the memory operand. If the instruction doesn't have a
653  /// memory operand, this returns -1.
654  ///
655  /// Note that this ignores tied operands. If there is a tied register which
656  /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
657  /// counted as one operand.
658  ///
659  inline int getMemoryOperandNo(uint64_t TSFlags) {
660  bool HasVEX_4V = TSFlags & X86II::VEX_4V;
661  bool HasEVEX_K = TSFlags & X86II::EVEX_K;
662 
663  switch (TSFlags & X86II::FormMask) {
664  default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
665  case X86II::Pseudo:
666  case X86II::RawFrm:
667  case X86II::AddRegFrm:
668  case X86II::RawFrmImm8:
669  case X86II::RawFrmImm16:
671  case X86II::RawFrmSrc:
672  case X86II::RawFrmDst:
673  case X86II::RawFrmDstSrc:
674  return -1;
675  case X86II::MRMDestMem:
676  return 0;
677  case X86II::MRMSrcMem:
678  // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
679  // mask register.
680  return 1 + HasVEX_4V + HasEVEX_K;
682  // Skip registers encoded in reg.
683  return 1 + HasEVEX_K;
684  case X86II::MRMSrcMemOp4:
685  // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
686  return 3;
687  case X86II::MRMDestReg:
688  case X86II::MRMSrcReg:
690  case X86II::MRMSrcRegOp4:
691  case X86II::MRMXr:
692  case X86II::MRM0r: case X86II::MRM1r:
693  case X86II::MRM2r: case X86II::MRM3r:
694  case X86II::MRM4r: case X86II::MRM5r:
695  case X86II::MRM6r: case X86II::MRM7r:
696  return -1;
697  case X86II::MRMXm:
698  case X86II::MRM0m: case X86II::MRM1m:
699  case X86II::MRM2m: case X86II::MRM3m:
700  case X86II::MRM4m: case X86II::MRM5m:
701  case X86II::MRM6m: case X86II::MRM7m:
702  // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
703  return 0 + HasVEX_4V + HasEVEX_K;
704  case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
705  case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
706  case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
707  case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
708  case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
709  case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
710  case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
711  case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
712  case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
713  case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
714  case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
715  case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
716  case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
717  case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
718  case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
719  case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
720  case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
721  case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
722  case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
723  case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
724  case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
725  case X86II::MRM_FF:
726  return -1;
727  }
728  }
729 
730  /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
731  /// higher) register? e.g. r8, xmm8, xmm13, etc.
732  inline bool isX86_64ExtendedReg(unsigned RegNo) {
733  if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
734  (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) ||
735  (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
736  return true;
737 
738  switch (RegNo) {
739  default: break;
740  case X86::R8: case X86::R9: case X86::R10: case X86::R11:
741  case X86::R12: case X86::R13: case X86::R14: case X86::R15:
742  case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
743  case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
744  case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
745  case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
746  case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
747  case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
748  case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
749  case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
750  case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11:
751  case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15:
752  return true;
753  }
754  return false;
755  }
756 
757  /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
758  /// registers? e.g. zmm21, etc.
759  static inline bool is32ExtendedReg(unsigned RegNo) {
760  return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
761  (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
762  (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
763  }
764 
765 
766  inline bool isX86_64NonExtLowByteReg(unsigned reg) {
767  return (reg == X86::SPL || reg == X86::BPL ||
768  reg == X86::SIL || reg == X86::DIL);
769  }
770 
771  /// isKMasked - Is this a masked instruction.
772  inline bool isKMasked(uint64_t TSFlags) {
773  return (TSFlags & X86II::EVEX_K) != 0;
774  }
775 
776  /// isKMergedMasked - Is this a merge masked instruction.
777  inline bool isKMergeMasked(uint64_t TSFlags) {
778  return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
779  }
780 }
781 
782 } // end namespace llvm;
783 
784 #endif
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:215
bool isX86_64NonExtLowByteReg(unsigned reg)
Definition: X86BaseInfo.h:766
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:123
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:209
AddRegFrm - This form is used for instructions like 'push r32' that have their one register operand a...
Definition: X86BaseInfo.h:235
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
RawFrmImm8 - This is used for the ENTER instruction, which has two immediates, the first of which is ...
Definition: X86BaseInfo.h:257
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:97
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:166
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:307
XOP - Opcode prefix used by XOP instructions.
Definition: X86BaseInfo.h:496
unsigned isImmPCRel(uint64_t TSFlags)
isImmPCRel - Return true if the immediate of the specified instruction's TSFlags indicates that it is...
Definition: X86BaseInfo.h:589
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:197
MRMSrcMem4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and load from memory.
Definition: X86BaseInfo.h:283
MRMXm - This form is used for instructions that use the Mod/RM byte to specify a memory source...
Definition: X86BaseInfo.h:293
MRMSrcMem - This form is used for instructions that use the Mod/RM byte to specify a source...
Definition: X86BaseInfo.h:278
VEX_L - Stands for a bit in the VEX opcode prefix meaning the current instruction uses 256-bit wide r...
Definition: X86BaseInfo.h:522
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:82
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:141
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
Definition: X86BaseInfo.h:239
MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:288
MRM_XX - A mod/rm byte of exactly 0xXX.
Definition: X86BaseInfo.h:329
bool hasImm(uint64_t TSFlags)
Definition: X86BaseInfo.h:566
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:192
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:732
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:70
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:182
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:203
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:133
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:174
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
Definition: X86BaseInfo.h:630
unsigned isImmSigned(uint64_t TSFlags)
isImmSigned - Return true if the immediate of the specified instruction's TSFlags indicates that it i...
Definition: X86BaseInfo.h:608
VEX_4V - Used to specify an additional AVX/SSE register.
Definition: X86BaseInfo.h:515
RawFrmImm16 - This is used for CALL FAR instructions, which have two immediates, the first of which i...
Definition: X86BaseInfo.h:263
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
Windows x64, Windows Itanium (IA-64)
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:113
MRM[0-7][rm] - These forms are used to represent instructions that use a Mod/RM byte, and use the middle field to hold extended opcode information.
Definition: X86BaseInfo.h:273
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:158
static bool is32ExtendedReg(unsigned RegNo)
is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher) registers? e...
Definition: X86BaseInfo.h:759
MRMXr - This form is used for instructions that use the Mod/RM byte to specify a register source...
Definition: X86BaseInfo.h:322
MRMSrcReg4VOp3 - This form is used for instructions that encode operand 3 with VEX.VVVV and do not load from memory.
Definition: X86BaseInfo.h:312
VEX_W - Has a opcode specific functionality, but is used in the same way as REX_W is for regular SSE ...
Definition: X86BaseInfo.h:509
unsigned char getBaseOpcodeFor(uint64_t TSFlags)
Definition: X86BaseInfo.h:562
bool isKMergeMasked(uint64_t TSFlags)
isKMergedMasked - Is this a merge masked instruction.
Definition: X86BaseInfo.h:777
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:89
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:150
unsigned getSizeOfImm(uint64_t TSFlags)
getSizeOfImm - Decode the "size of immediate" field from the TSFlags field of the specified instructi...
Definition: X86BaseInfo.h:572
TOF
Target Operand Flag enum.
Definition: X86BaseInfo.h:61
STATIC_ROUNDING
AVX512 static rounding constants.
Definition: X86BaseInfo.h:47
bool isKMasked(uint64_t TSFlags)
isKMasked - Is this a masked instruction.
Definition: X86BaseInfo.h:772
Has3DNow0F0FOpcode - This flag indicates that the instruction uses the wacky 0x0F 0x0F prefix for 3DN...
Definition: X86BaseInfo.h:551
Explicitly specified rounding control.
Definition: X86BaseInfo.h:555
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:104
RawFrmDst - This form is for instructions that use the destination index register DI/EDI/ESI...
Definition: X86BaseInfo.h:247
MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM byte to specify the fourth sour...
Definition: X86BaseInfo.h:317
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/ERI with a possib...
Definition: X86BaseInfo.h:252
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
Definition: X86BaseInfo.h:243
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:75
Raw - This form is for instructions that don't have any operands, so they are just a fixed opcode val...
Definition: X86BaseInfo.h:231
MRMDestReg - This form is used for instructions that use the Mod/RM byte to specify a destination...
Definition: X86BaseInfo.h:302
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:187
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:659