47 const char *
Features,
void *DisInfo,
int TagType,
84 std::unique_ptr<MCRelocationInfo> RelInfo(
90 TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo)));
96 Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
102 TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
144 while (!Comments.
empty()) {
149 size_t Position = Comments.
find(
'\n');
150 FormattedOS << CommentBegin <<
' ' << Comments.
substr(0, Position);
152 Comments = Comments.
substr(Position+1);
166 const int NoInformationAvailable = -1;
170 return NoInformationAvailable;
180 for (
unsigned OpIdx = 0, OpIdxEnd = Inst.
getNumOperands(); OpIdx != OpIdxEnd;
194 const int NoInformationAvailable = -1;
209 return NoInformationAvailable;
214 DefIdx != DefEnd; ++DefIdx) {
218 Latency = std::max(Latency, WLEntry->
Cycles);
249 uint64_t BytesSize, uint64_t
PC,
char *OutString,
250 size_t OutStringSize){
263 nulls(), Annotations);
283 assert(OutStringSize != 0 &&
"Output buffer cannot be zero size");
284 size_t OutputSize =
std::min(OutStringSize-1, InsnStr.
size());
285 std::memcpy(OutString, InsnStr.
data(), OutputSize);
286 OutString[OutputSize] =
'\0';
303 DC->
addOptions(LLVMDisassembler_Option_UseMarkup);
304 Options &= ~LLVMDisassembler_Option_UseMarkup;
310 DC->
addOptions(LLVMDisassembler_Option_PrintImmHex);
311 Options &= ~LLVMDisassembler_Option_PrintImmHex;
320 AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
325 DC->
addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
326 Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
333 DC->
addOptions(LLVMDisassembler_Option_SetInstrComments);
334 Options &= ~LLVMDisassembler_Option_SetInstrComments;
338 DC->
addOptions(LLVMDisassembler_Option_PrintLatency);
339 Options &= ~LLVMDisassembler_Option_PrintLatency;
341 return (Options == 0);
MCDisassembler * createMCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) const
void setIP(MCInstPrinter *NewIP)
unsigned getAssemblerDialect() const
#define LLVMDisassembler_Option_SetInstrComments
const MCAsmInfo * getAsmInfo() const
const MCRegisterInfo * getRegisterInfo() const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI)=0
Print the specified MCInst to the specified raw_ostream.
LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName.
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
MCRegisterInfo * createMCRegInfo(StringRef TT) const
createMCRegInfo - Create a MCRegisterInfo implementation.
static void emitComments(LLVMDisasmContext *DC, formatted_raw_ostream &FormattedOS)
Emits the comments that are stored in DC comment stream.
void setPrintImmHex(bool Value)
A raw_ostream that writes to an SmallVector or SmallString.
const std::string & getTripleName() const
uint64_t getOptions() const
void setSymbolizer(std::unique_ptr< MCSymbolizer > Symzer)
Set Symzer as the current symbolizer.
#define LLVMDisassembler_Option_UseMarkup
static const Target * lookupTarget(const std::string &Triple, std::string &Error)
lookupTarget - Lookup a target based on a target triple.
LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName and a specific CPU.
StringRef getCommentString() const
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
const MCDisassembler * getDisAsm() const
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
const MCSubtargetInfo * getSubtargetInfo() const
unsigned getCommentColumn() const
This indicates the column (zero-based) at which asm comments should be printed.
static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Emits latency information in DC->CommentStream for Inst, based on the information available in DC...
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Context object for machine code objects.
raw_svector_ostream CommentStream
void * LLVMDisasmContextRef
An opaque reference to a disassembler context.
Itinerary data supplied by a subtarget to be used by a target.
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
MCAsmInfo * createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple) const
createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple.
unsigned const MachineRegisterInfo * MRI
unsigned NumWriteLatencyEntries
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Summarize the scheduling resources required for an instruction of a particular scheduling class...
void setCommentStream(raw_ostream &OS)
Specify a stream to emit comments to.
#define LLVMDisassembler_Option_PrintImmHex
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Interface to description of machine instruction set.
MCRelocationInfo * createMCRelocationInfo(StringRef TT, MCContext &Ctx) const
createMCRelocationInfo - Create a target specific MCRelocationInfo.
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
MCInstPrinter * createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) const
static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst from the itinerary scheduling model, based on DC information...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Triple - Helper class for working with autoconf configuration names.
Specify the latency in cpu cycles for a particular scheduling class and def index.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
StringRef str()
Return a StringRef for the vector contents.
MCSymbolizer * createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) const
createMCSymbolizer - Create a target specific MCSymbolizer.
const MCInstrInfo * getInstrInfo() const
LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName, a specific CPU and specific feature string.
unsigned getOpcode() const
Target - Wrapper for Target specific information.
StringRef str() const
Explicit conversion to StringRef.
void setUseMarkup(bool Value)
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize)
Disassemble a single instruction using the disassembler context specified in the parameter DC...
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options)
Set the disassembler's options.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
#define LLVMDisassembler_Option_AsmPrinterVariant
unsigned getSchedClass() const
Return the scheduling class for this instruction.
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
pointer data()
Return a pointer to the vector's buffer, even if empty().
unsigned getNumOperands() const
void LLVMDisasmDispose(LLVMDisasmContextRef DCR)
Dispose of a disassembler context.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
MCSubtargetInfo - Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
const FeatureBitset Features
void addOptions(uint64_t Options)
void setCPU(const char *CPU)
StringRef - Represent a constant reference to a string, i.e.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
SmallString< 128 > CommentsToEmit
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Machine model for scheduling, bundling, and heuristics.
const Target * getTarget() const
const MCSchedClassDesc * SCDesc
#define LLVMDisassembler_Option_PrintLatency