36 #define DEBUG_TYPE "mips-fastisel"
42 class MipsFastISel final :
public FastISel {
47 typedef enum { RegBase, FrameIndexBase } BaseKind;
63 void setKind(BaseKind K) {
Kind = K; }
64 BaseKind getKind()
const {
return Kind; }
65 bool isRegBase()
const {
return Kind == RegBase; }
66 bool isFIBase()
const {
return Kind == FrameIndexBase; }
67 void setReg(
unsigned Reg) {
68 assert(isRegBase() &&
"Invalid base register access!");
72 assert(isRegBase() &&
"Invalid base register access!");
75 void setFI(
unsigned FI) {
76 assert(isFIBase() &&
"Invalid base frame index access!");
79 unsigned getFI()
const {
80 assert(isFIBase() &&
"Invalid base frame index access!");
84 void setOffset(int64_t Offset_) {
Offset = Offset_; }
101 bool fastLowerArguments()
override;
102 bool fastLowerCall(CallLoweringInfo &CLI)
override;
103 bool fastLowerIntrinsicCall(
const IntrinsicInst *II)
override;
105 bool UnsupportedFPMode;
119 bool selectFPToInt(
const Instruction *I,
bool IsSigned);
124 bool selectDivRem(
const Instruction *I,
unsigned ISDOpcode);
127 bool isTypeLegal(
Type *Ty,
MVT &VT);
128 bool isTypeSupported(
Type *Ty,
MVT &VT);
129 bool isLoadTypeLegal(
Type *Ty,
MVT &VT);
132 void simplifyAddress(
Address &Addr);
136 bool emitLoad(
MVT VT,
unsigned &ResultReg,
Address &Addr,
137 unsigned Alignment = 0);
138 bool emitStore(
MVT VT,
unsigned SrcReg,
Address Addr,
140 bool emitStore(
MVT VT,
unsigned SrcReg,
Address &Addr,
141 unsigned Alignment = 0);
142 unsigned emitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
bool isZExt);
143 bool emitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
unsigned DestReg,
146 bool emitIntZExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
unsigned DestReg);
148 bool emitIntSExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
unsigned DestReg);
149 bool emitIntSExt32r1(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
151 bool emitIntSExt32r2(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
154 unsigned getRegEnsuringSimpleIntegerWidening(
const Value *,
bool IsUnsigned);
156 unsigned emitLogicalOp(
unsigned ISDOpc,
MVT RetVT,
const Value *LHS,
163 unsigned materializeExternalCallSym(
MCSymbol *Syn);
166 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc));
169 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc),
173 unsigned MemReg, int64_t MemOffset) {
177 unsigned MemReg, int64_t MemOffset) {
178 return emitInst(Opc, DstReg).
addReg(MemReg).
addImm(MemOffset);
181 unsigned fastEmitInst_rr(
unsigned MachineInstOpcode,
183 unsigned Op0,
bool Op0IsKill,
184 unsigned Op1,
bool Op1IsKill);
190 unsigned Op0,
bool Op0IsKill, uint64_t imm1,
191 uint64_t imm2,
unsigned Op3,
bool Op3IsKill) {
200 bool finishCall(CallLoweringInfo &CLI,
MVT RetVT,
unsigned NumBytes);
211 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
214 UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
217 unsigned fastMaterializeAlloca(
const AllocaInst *AI)
override;
218 unsigned fastMaterializeConstant(
const Constant *C)
override;
219 bool fastSelectInstruction(
const Instruction *I)
override;
221 #include "MipsGenFastISel.inc"
241 #include "MipsGenCallingConv.inc"
247 unsigned MipsFastISel::emitLogicalOp(
unsigned ISDOpc,
MVT RetVT,
250 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
268 unsigned LHSReg = getRegForValue(LHS);
273 if (
const auto *
C = dyn_cast<ConstantInt>(RHS))
276 RHSReg = getRegForValue(RHS);
280 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
284 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
288 unsigned MipsFastISel::fastMaterializeAlloca(
const AllocaInst *AI) {
290 "Alloca should always return a pointer.");
293 FuncInfo.StaticAllocaMap.find(AI);
295 if (SI != FuncInfo.StaticAllocaMap.
end()) {
296 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
297 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Mips::LEA_ADDiu),
299 .addFrameIndex(SI->second)
307 unsigned MipsFastISel::materializeInt(
const Constant *
C,
MVT VT) {
315 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
317 unsigned ResultReg = createResultReg(RC);
320 unsigned Opc = Mips::ADDiu;
321 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
324 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
327 unsigned Lo = Imm & 0xFFFF;
328 unsigned Hi = (Imm >> 16) & 0xFFFF;
331 unsigned TmpReg = createResultReg(RC);
332 emitInst(Mips::LUi, TmpReg).addImm(Hi);
333 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
335 emitInst(Mips::LUi, ResultReg).addImm(Hi);
340 unsigned MipsFastISel::materializeFP(
const ConstantFP *CFP,
MVT VT) {
341 if (UnsupportedFPMode)
346 unsigned DestReg = createResultReg(RC);
347 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
348 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
352 unsigned DestReg = createResultReg(RC);
353 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
355 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
362 unsigned MipsFastISel::materializeGV(
const GlobalValue *GV,
MVT VT) {
367 unsigned DestReg = createResultReg(RC);
373 emitInst(Mips::LW, DestReg)
374 .addReg(MFI->getGlobalBaseReg())
378 unsigned TempReg = createResultReg(RC);
379 emitInst(Mips::ADDiu, TempReg)
387 unsigned MipsFastISel::materializeExternalCallSym(
MCSymbol *Sym) {
389 unsigned DestReg = createResultReg(RC);
390 emitInst(Mips::LW, DestReg)
391 .addReg(MFI->getGlobalBaseReg())
398 unsigned MipsFastISel::fastMaterializeConstant(
const Constant *C) {
399 EVT CEVT = TLI.getValueType(DL, C->
getType(),
true);
406 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
407 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
408 else if (
const GlobalValue *GV = dyn_cast<GlobalValue>(C))
409 return materializeGV(GV, VT);
410 else if (isa<ConstantInt>(C))
411 return materializeInt(C, VT);
416 bool MipsFastISel::computeAddress(
const Value *Obj,
Address &Addr) {
418 const User *U =
nullptr;
419 unsigned Opcode = Instruction::UserOp1;
420 if (
const Instruction *
I = dyn_cast<Instruction>(Obj)) {
423 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
424 FuncInfo.MBBMap[
I->getParent()] == FuncInfo.MBB) {
425 Opcode =
I->getOpcode();
428 }
else if (
const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
429 Opcode = C->getOpcode();
435 case Instruction::BitCast: {
437 return computeAddress(U->
getOperand(0), Addr);
439 case Instruction::GetElementPtr: {
441 int64_t TmpOffset = Addr.getOffset();
450 unsigned Idx = cast<ConstantInt>(
Op)->getZExtValue();
455 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
460 if (canFoldAddIntoGEP(U, Op)) {
463 cast<ConstantInt>(cast<AddOperator>(
Op)->getOperand(1));
466 Op = cast<AddOperator>(
Op)->getOperand(0);
470 goto unsupported_gep;
475 Addr.setOffset(TmpOffset);
483 case Instruction::Alloca: {
486 FuncInfo.StaticAllocaMap.
find(AI);
487 if (SI != FuncInfo.StaticAllocaMap.end()) {
488 Addr.setKind(Address::FrameIndexBase);
489 Addr.setFI(SI->second);
495 Addr.setReg(getRegForValue(Obj));
496 return Addr.getReg() != 0;
499 bool MipsFastISel::computeCallAddress(
const Value *V,
Address &Addr) {
500 const User *U =
nullptr;
501 unsigned Opcode = Instruction::UserOp1;
503 if (
const auto *
I = dyn_cast<Instruction>(V)) {
506 if (
I->getParent() == FuncInfo.MBB->getBasicBlock()) {
507 Opcode =
I->getOpcode();
510 }
else if (
const auto *C = dyn_cast<ConstantExpr>(V)) {
511 Opcode = C->getOpcode();
518 case Instruction::BitCast:
520 return computeCallAddress(U->
getOperand(0), Addr);
522 case Instruction::IntToPtr:
525 TLI.getPointerTy(DL))
526 return computeCallAddress(U->
getOperand(0), Addr);
528 case Instruction::PtrToInt:
530 if (TLI.getValueType(DL, U->
getType()) == TLI.getPointerTy(DL))
531 return computeCallAddress(U->
getOperand(0), Addr);
535 if (
const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
536 Addr.setGlobalValue(GV);
541 if (!Addr.getGlobalValue()) {
542 Addr.setReg(getRegForValue(V));
543 return Addr.getReg() != 0;
549 bool MipsFastISel::isTypeLegal(
Type *Ty,
MVT &VT) {
550 EVT evt = TLI.getValueType(DL, Ty,
true);
558 return TLI.isTypeLegal(VT);
561 bool MipsFastISel::isTypeSupported(
Type *Ty,
MVT &VT) {
565 if (isTypeLegal(Ty, VT))
576 bool MipsFastISel::isLoadTypeLegal(
Type *Ty,
MVT &VT) {
577 if (isTypeLegal(Ty, VT))
593 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
596 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
605 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
606 emitInst(
Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
607 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
611 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
612 emitInst(
Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
613 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
617 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
621 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
625 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
626 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
627 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
631 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
632 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
633 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
637 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
641 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
645 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
646 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
647 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
651 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
652 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
653 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
662 if (UnsupportedFPMode)
666 if (!IsFloat && !IsDouble)
668 unsigned Opc, CondMovOpc;
671 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
672 CondMovOpc = Mips::MOVT_I;
675 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
676 CondMovOpc = Mips::MOVF_I;
679 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
680 CondMovOpc = Mips::MOVT_I;
683 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
684 CondMovOpc = Mips::MOVT_I;
687 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
688 CondMovOpc = Mips::MOVF_I;
691 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
692 CondMovOpc = Mips::MOVF_I;
697 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
698 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
699 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
700 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
703 emitInst(CondMovOpc, ResultReg)
706 .addReg(RegWithZero);
712 bool MipsFastISel::emitLoad(
MVT VT,
unsigned &ResultReg,
Address &Addr,
713 unsigned Alignment) {
720 ResultReg = createResultReg(&Mips::GPR32RegClass);
725 ResultReg = createResultReg(&Mips::GPR32RegClass);
730 ResultReg = createResultReg(&Mips::GPR32RegClass);
735 if (UnsupportedFPMode)
737 ResultReg = createResultReg(&Mips::FGR32RegClass);
742 if (UnsupportedFPMode)
744 ResultReg = createResultReg(&Mips::AFGR64RegClass);
751 if (Addr.isRegBase()) {
752 simplifyAddress(Addr);
753 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
756 if (Addr.isFIBase()) {
757 unsigned FI = Addr.getFI();
759 int64_t
Offset = Addr.getOffset();
764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
773 bool MipsFastISel::emitStore(
MVT VT,
unsigned SrcReg,
Address &Addr,
774 unsigned Alignment) {
790 if (UnsupportedFPMode)
795 if (UnsupportedFPMode)
802 if (Addr.isRegBase()) {
803 simplifyAddress(Addr);
804 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
807 if (Addr.isFIBase()) {
808 unsigned FI = Addr.getFI();
810 int64_t Offset = Addr.getOffset();
815 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc))
825 bool MipsFastISel::selectLogicalOp(
const Instruction *
I) {
827 if (!isTypeSupported(I->
getType(), VT))
848 updateValueMap(I, ResultReg);
852 bool MipsFastISel::selectLoad(
const Instruction *I) {
859 if (!isLoadTypeLegal(I->
getType(), VT))
868 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
870 updateValueMap(I, ResultReg);
874 bool MipsFastISel::selectStore(
const Instruction *I) {
888 SrcReg = getRegForValue(Op0);
897 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
906 bool MipsFastISel::selectBranch(
const Instruction *I) {
921 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
924 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Mips::BGTZ))
927 finishCondBranch(BI->
getParent(), TBB, FBB);
933 bool MipsFastISel::selectCmp(
const Instruction *I) {
934 const CmpInst *CI = cast<CmpInst>(
I);
935 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
938 updateValueMap(I, ResultReg);
943 bool MipsFastISel::selectFPExt(
const Instruction *I) {
944 if (UnsupportedFPMode)
947 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
948 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
959 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
960 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
961 updateValueMap(I, DestReg);
965 bool MipsFastISel::selectSelect(
const Instruction *I) {
966 assert(isa<SelectInst>(I) &&
"Expected a select instruction.");
971 if (!isTypeSupported(I->
getType(), VT) || UnsupportedFPMode) {
972 DEBUG(
dbgs() <<
".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
980 CondMovOpc = Mips::MOVN_I_I;
981 RC = &Mips::GPR32RegClass;
983 CondMovOpc = Mips::MOVN_I_S;
984 RC = &Mips::FGR32RegClass;
986 CondMovOpc = Mips::MOVN_I_D32;
987 RC = &Mips::AFGR64RegClass;
995 unsigned CondReg = getRegForValue(Cond);
997 if (!Src1Reg || !Src2Reg || !CondReg)
1000 unsigned ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1007 unsigned ResultReg = createResultReg(RC);
1008 unsigned TempReg = createResultReg(RC);
1010 if (!ResultReg || !TempReg)
1013 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1014 emitInst(CondMovOpc, ResultReg)
1015 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1016 updateValueMap(I, ResultReg);
1021 bool MipsFastISel::selectFPTrunc(
const Instruction *I) {
1022 if (UnsupportedFPMode)
1025 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
1026 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
1031 unsigned SrcReg = getRegForValue(Src);
1035 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1039 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1040 updateValueMap(I, DestReg);
1045 bool MipsFastISel::selectFPToInt(
const Instruction *I,
bool IsSigned) {
1046 if (UnsupportedFPMode)
1053 if (!isTypeLegal(DstTy, DstVT))
1061 if (!isTypeLegal(SrcTy, SrcVT))
1067 unsigned SrcReg = getRegForValue(Src);
1073 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1074 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1075 unsigned Opc = (SrcVT ==
MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1078 emitInst(Opc, TempReg).addReg(SrcReg);
1079 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1081 updateValueMap(I, DestReg);
1085 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1087 unsigned &NumBytes) {
1091 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1093 NumBytes = CCInfo.getNextStackOffset();
1098 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1101 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
1113 }
else if (
i == 1) {
1142 unsigned ArgReg = getRegForValue(ArgVal);
1154 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT,
false);
1162 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT,
true);
1173 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1174 TII.get(TargetOpcode::COPY), VA.
getLocReg()).addReg(ArgReg);
1187 if (isa<UndefValue>(ArgVal))
1197 unsigned BEAlign = 0;
1198 if (ArgSize < 8 && !Subtarget->isLittle())
1199 BEAlign = 8 - ArgSize;
1202 Addr.setKind(Address::RegBase);
1203 Addr.setReg(Mips::SP);
1206 unsigned Alignment =
DL.getABITypeAlignment(ArgVal->
getType());
1219 bool MipsFastISel::finishCall(CallLoweringInfo &CLI,
MVT RetVT,
1220 unsigned NumBytes) {
1222 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1226 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1229 if (RVLocs.
size() != 1)
1232 MVT CopyVT = RVLocs[0].getValVT();
1237 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1240 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1241 TII.get(TargetOpcode::COPY),
1242 ResultReg).addReg(RVLocs[0].getLocReg());
1243 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1245 CLI.ResultReg = ResultReg;
1246 CLI.NumResultRegs = 1;
1251 bool MipsFastISel::fastLowerArguments() {
1252 DEBUG(
dbgs() <<
"fastLowerArguments\n");
1254 if (!FuncInfo.CanLowerReturn) {
1255 DEBUG(
dbgs() <<
".. gave up (!CanLowerReturn)\n");
1261 DEBUG(
dbgs() <<
".. gave up (varargs)\n");
1267 DEBUG(
dbgs() <<
".. gave up (calling convention is not C)\n");
1279 struct AllocatedReg {
1283 : RC(RC), Reg(Reg) {}
1290 for (
const auto &FormalArg : F->
args()) {
1294 DEBUG(
dbgs() <<
".. gave up (inreg, structret, byval)\n");
1298 Type *ArgTy = FormalArg.getType();
1300 DEBUG(
dbgs() <<
".. gave up (struct, array, or vector)\n");
1304 EVT ArgVT = TLI.getValueType(DL, ArgTy);
1307 DEBUG(
dbgs() <<
".. .. gave up (not a simple type)\n");
1319 DEBUG(
dbgs() <<
".. .. gave up (i8/i16 arg is not extended)\n");
1323 if (NextGPR32 == GPR32ArgRegs.
end()) {
1324 DEBUG(
dbgs() <<
".. .. gave up (ran out of GPR32 arguments)\n");
1328 DEBUG(
dbgs() <<
".. .. GPR32(" << *NextGPR32 <<
")\n");
1329 Allocation.
emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1332 NextFGR32 = FGR32ArgRegs.
end();
1333 NextAFGR64 = AFGR64ArgRegs.
end();
1339 DEBUG(
dbgs() <<
".. .. gave up (i32 arg is zero extended)\n");
1343 if (NextGPR32 == GPR32ArgRegs.
end()) {
1344 DEBUG(
dbgs() <<
".. .. gave up (ran out of GPR32 arguments)\n");
1348 DEBUG(
dbgs() <<
".. .. GPR32(" << *NextGPR32 <<
")\n");
1349 Allocation.
emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1352 NextFGR32 = FGR32ArgRegs.
end();
1353 NextAFGR64 = AFGR64ArgRegs.
end();
1357 if (UnsupportedFPMode) {
1358 DEBUG(
dbgs() <<
".. .. gave up (UnsupportedFPMode)\n");
1361 if (NextFGR32 == FGR32ArgRegs.
end()) {
1362 DEBUG(
dbgs() <<
".. .. gave up (ran out of FGR32 arguments)\n");
1365 DEBUG(
dbgs() <<
".. .. FGR32(" << *NextFGR32 <<
")\n");
1366 Allocation.
emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1369 if (NextGPR32 != GPR32ArgRegs.
end())
1371 if (NextAFGR64 != AFGR64ArgRegs.
end())
1376 if (UnsupportedFPMode) {
1377 DEBUG(
dbgs() <<
".. .. gave up (UnsupportedFPMode)\n");
1380 if (NextAFGR64 == AFGR64ArgRegs.
end()) {
1381 DEBUG(
dbgs() <<
".. .. gave up (ran out of AFGR64 arguments)\n");
1384 DEBUG(
dbgs() <<
".. .. AFGR64(" << *NextAFGR64 <<
")\n");
1385 Allocation.
emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1388 if (NextGPR32 != GPR32ArgRegs.
end())
1390 if (NextGPR32 != GPR32ArgRegs.
end())
1392 if (NextFGR32 != FGR32ArgRegs.
end())
1397 DEBUG(
dbgs() <<
".. .. gave up (unknown type)\n");
1405 for (
const auto &FormalArg : F->
args()) {
1406 unsigned SrcReg = Allocation[Idx].Reg;
1407 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[Idx].RC);
1411 unsigned ResultReg = createResultReg(Allocation[Idx].RC);
1412 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1413 TII.get(TargetOpcode::COPY), ResultReg)
1415 updateValueMap(&FormalArg, ResultReg);
1421 unsigned IncomingArgSizeInBytes = 0;
1426 IncomingArgSizeInBytes =
std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC),
1427 IncomingArgSizeInBytes);
1435 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1437 bool IsTailCall = CLI.IsTailCall;
1438 bool IsVarArg = CLI.IsVarArg;
1439 const Value *Callee = CLI.Callee;
1456 if (CLI.RetTy->isVoidTy())
1458 else if (!isTypeSupported(CLI.RetTy, RetVT))
1461 for (
auto Flag : CLI.OutFlags)
1467 OutVTs.
reserve(CLI.OutVals.size());
1469 for (
auto *Val : CLI.OutVals) {
1471 if (!isTypeLegal(Val->getType(), VT) &&
1483 if (!computeCallAddress(Callee, Addr))
1488 if (!processCallArgs(CLI, OutVTs, NumBytes))
1491 if (!Addr.getGlobalValue())
1495 unsigned DestAddress;
1497 DestAddress = materializeExternalCallSym(Symbol);
1499 DestAddress = materializeGV(Addr.getGlobalValue(),
MVT::i32);
1500 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Mips::JALR),
1503 Mips::RA).addReg(Mips::T9);
1506 for (
auto Reg : CLI.OutRegs)
1511 MIB.
addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1516 return finishCall(CLI, RetVT, NumBytes);
1519 bool MipsFastISel::fastLowerIntrinsicCall(
const IntrinsicInst *II) {
1523 case Intrinsic::bswap: {
1527 if (!isTypeSupported(RetTy, VT))
1530 unsigned SrcReg = getRegForValue(II->
getOperand(0));
1533 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1537 if (Subtarget->hasMips32r2()) {
1538 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1539 updateValueMap(II, DestReg);
1542 unsigned TempReg[3];
1543 for (
int i = 0;
i < 3;
i++) {
1544 TempReg[
i] = createResultReg(&Mips::GPR32RegClass);
1545 if (TempReg[
i] == 0)
1548 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1549 emitInst(
Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1550 emitInst(
Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1551 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1552 updateValueMap(II, DestReg);
1556 if (Subtarget->hasMips32r2()) {
1557 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1558 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1559 emitInst(
Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1560 updateValueMap(II, DestReg);
1563 unsigned TempReg[8];
1564 for (
int i = 0;
i < 8;
i++) {
1565 TempReg[
i] = createResultReg(&Mips::GPR32RegClass);
1566 if (TempReg[
i] == 0)
1570 emitInst(
Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1571 emitInst(
Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1572 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1573 emitInst(
Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1575 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1576 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1578 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1579 emitInst(
Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1580 emitInst(
Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1581 updateValueMap(II, DestReg);
1587 case Intrinsic::memcpy:
1588 case Intrinsic::memmove: {
1589 const auto *MTI = cast<MemTransferInst>(II);
1591 if (MTI->isVolatile())
1593 if (!MTI->getLength()->getType()->isIntegerTy(32))
1595 const char *IntrMemName = isa<MemCpyInst>(II) ?
"memcpy" :
"memmove";
1598 case Intrinsic::memset: {
1599 const MemSetInst *MSI = cast<MemSetInst>(II);
1611 bool MipsFastISel::selectRet(
const Instruction *I) {
1617 if (!FuncInfo.CanLowerReturn)
1638 CCInfo.AnalyzeReturn(Outs, RetCC);
1641 if (ValLocs.size() != 1)
1656 unsigned Reg = getRegForValue(RV);
1660 unsigned SrcReg = Reg + VA.
getValNo();
1663 if (!
MRI.getRegClass(SrcReg)->contains(DestReg))
1666 EVT RVEVT = TLI.getValueType(DL, RV->
getType());
1678 if (RVVT ==
MVT::f64 && UnsupportedFPMode) {
1679 DEBUG(
dbgs() <<
".. .. gave up (UnsupportedFPMode\n");
1685 if (RVVT != DestVT) {
1689 if (Outs[0].
Flags.isZExt() || Outs[0].Flags.isSExt()) {
1690 bool IsZExt = Outs[0].Flags.isZExt();
1691 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1698 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1699 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1705 for (
unsigned i = 0, e = RetRegs.
size();
i != e; ++
i)
1710 bool MipsFastISel::selectTrunc(
const Instruction *I) {
1716 SrcVT = TLI.getValueType(DL, Op->
getType(),
true);
1717 DestVT = TLI.getValueType(DL, I->
getType(),
true);
1724 unsigned SrcReg = getRegForValue(Op);
1730 updateValueMap(I, SrcReg);
1733 bool MipsFastISel::selectIntExt(
const Instruction *I) {
1738 bool isZExt = isa<ZExtInst>(
I);
1739 unsigned SrcReg = getRegForValue(Src);
1743 EVT SrcEVT, DestEVT;
1744 SrcEVT = TLI.getValueType(DL, SrcTy,
true);
1745 DestEVT = TLI.getValueType(DL, DestTy,
true);
1753 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1755 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1757 updateValueMap(I, ResultReg);
1760 bool MipsFastISel::emitIntSExt32r1(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1773 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1774 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1775 emitInst(
Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1779 bool MipsFastISel::emitIntSExt32r2(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1785 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1788 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1794 bool MipsFastISel::emitIntSExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1798 if (Subtarget->hasMips32r2())
1799 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1800 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1803 bool MipsFastISel::emitIntZExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1821 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1825 bool MipsFastISel::emitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1826 unsigned DestReg,
bool IsZExt) {
1835 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1836 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1839 unsigned MipsFastISel::emitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1841 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1842 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1843 return Success ? DestReg : 0;
1846 bool MipsFastISel::selectDivRem(
const Instruction *I,
unsigned ISDOpcode) {
1847 EVT DestEVT = TLI.getValueType(DL, I->
getType(),
true);
1856 switch (ISDOpcode) {
1869 unsigned Src0Reg = getRegForValue(I->
getOperand(0));
1870 unsigned Src1Reg = getRegForValue(I->
getOperand(1));
1871 if (!Src0Reg || !Src1Reg)
1874 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1875 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1877 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1884 emitInst(MFOpc, ResultReg);
1886 updateValueMap(I, ResultReg);
1890 bool MipsFastISel::selectShift(
const Instruction *I) {
1893 if (!isTypeSupported(I->
getType(), RetVT))
1896 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1902 unsigned Op0Reg = getRegForValue(Op0);
1907 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1908 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1912 MVT Op0MVT = TLI.getValueType(DL, Op0->
getType(),
true).getSimpleVT();
1913 bool IsZExt = Opcode == Instruction::LShr;
1914 if (!emitIntExt(Op0MVT, Op0Reg,
MVT::i32, TempReg, IsZExt))
1920 if (
const auto *C = dyn_cast<ConstantInt>(I->
getOperand(1))) {
1921 uint64_t ShiftVal = C->getZExtValue();
1926 case Instruction::Shl:
1929 case Instruction::AShr:
1932 case Instruction::LShr:
1937 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1938 updateValueMap(I, ResultReg);
1942 unsigned Op1Reg = getRegForValue(I->
getOperand(1));
1949 case Instruction::Shl:
1950 Opcode = Mips::SLLV;
1952 case Instruction::AShr:
1953 Opcode = Mips::SRAV;
1955 case Instruction::LShr:
1956 Opcode = Mips::SRLV;
1960 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1961 updateValueMap(I, ResultReg);
1965 bool MipsFastISel::fastSelectInstruction(
const Instruction *I) {
1970 return selectLoad(I);
1972 return selectStore(I);
1973 case Instruction::SDiv:
1977 case Instruction::UDiv:
1981 case Instruction::SRem:
1985 case Instruction::URem:
1989 case Instruction::Shl:
1990 case Instruction::LShr:
1991 case Instruction::AShr:
1992 return selectShift(I);
1996 return selectLogicalOp(I);
1997 case Instruction::Br:
1998 return selectBranch(I);
2000 return selectRet(I);
2001 case Instruction::Trunc:
2002 return selectTrunc(I);
2003 case Instruction::ZExt:
2004 case Instruction::SExt:
2005 return selectIntExt(I);
2006 case Instruction::FPTrunc:
2007 return selectFPTrunc(I);
2008 case Instruction::FPExt:
2009 return selectFPExt(I);
2010 case Instruction::FPToSI:
2011 return selectFPToInt(I,
true);
2012 case Instruction::FPToUI:
2013 return selectFPToInt(I,
false);
2014 case Instruction::ICmp:
2015 case Instruction::FCmp:
2016 return selectCmp(I);
2018 return selectSelect(I);
2023 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(
const Value *V,
2025 unsigned VReg = getRegForValue(V);
2028 MVT VMVT = TLI.getValueType(DL, V->
getType(),
true).getSimpleVT();
2030 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
2031 if (!emitIntExt(VMVT, VReg,
MVT::i32, TempReg, IsUnsigned))
2038 void MipsFastISel::simplifyAddress(
Address &Addr) {
2041 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2042 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
2043 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2044 Addr.setReg(DestReg);
2049 unsigned MipsFastISel::fastEmitInst_rr(
unsigned MachineInstOpcode,
2051 unsigned Op0,
bool Op0IsKill,
2052 unsigned Op1,
bool Op1IsKill) {
2060 unsigned ResultReg = createResultReg(RC);
2064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2079 return new MipsFastISel(funcInfo, libInfo);
Return a value (possibly void), from a function.
void push_back(const T &Elt)
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Type * getIndexedType() const
This class is the base class for the comparison instructions.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
uint64_t getZExtValue() const
Get zero extended value.
LocInfo getLocInfo() const
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned getNumOperands() const
Describe properties that are true of each instruction in the target description file.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
0 1 0 0 True if ordered and less than
unsigned getSizeInBits() const
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
1 1 1 0 True if unordered or not equal
This class wraps the llvm.memset intrinsic.
Type * getReturnType() const
Returns the type of the ret val.
const Function * getParent() const
Return the enclosing method, or null if none.
constexpr bool isInt< 16 >(int64_t x)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
void reserve(size_type N)
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
unsigned getValNo() const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool isVector() const
isVector - Return true if this is a vector value type.
StructType * getStructTypeOrNull() const
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
A description of a memory reference used in the backend.
std::string getEVTString() const
getEVTString - This function returns value type as a string, e.g.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This class represents the LLVM 'select' instruction.
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
Class to represent struct types.
A Use represents the edge between a Value definition and its users.
bool hasInternalLinkage() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned getNumArgOperands() const
Return the number of call arguments.
Reg
All possible values of the reg field in the ModR/M byte.
0 1 0 1 True if ordered and less than or equal
APInt bitcastToAPInt() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
A constant value that is initialized with an expression using other constant values.
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
BasicBlock * getSuccessor(unsigned i) const
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
bool isArrayTy() const
True if this is an instance of ArrayType.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset)
Stack pointer relative access.
unsigned getKillRegState(bool B)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
uint64_t getElementOffset(unsigned Idx) const
Local Stack Slot Allocation
INITIALIZE_PASS(HexagonEarlyIfConversion,"hexagon-eif","Hexagon early if conversion", false, false) bool HexagonEarlyIfConversion MachineBasicBlock * SB
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_ADD)...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
unsigned const MachineRegisterInfo * MRI
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
Conditional or Unconditional Branch instruction.
C - The default llvm calling convention, compatible with C.
bool isVectorTy() const
True if this is an instance of VectorType.
This is an important base class in LLVM.
PointerType * getType() const
Overload to return most specific pointer type.
bool isVector() const
isVector - Return true if this is a vector value type.
const Value * getCondition() const
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
static ManagedStatic< OptionRegistry > OR
ConstantFP - Floating Point Values [float, double].
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
#define LLVM_ATTRIBUTE_UNUSED
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Value * getOperand(unsigned i) const
Predicate getPredicate() const
Return the predicate for this instruction.
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
EVT - Extended Value Type.
LLVMContext & getContext() const
All values hold a context through their type.
static bool isAtomic(Instruction *I)
const Value * getTrueValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
The memory access writes data.
0 0 1 0 True if ordered and greater than
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
CCValAssign - Represent assignment of one arg/retval to a location.
Value * getLength() const
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
Function * getCalledFunction() const
Return the function called, or null if this is an indirect function invocation.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
AttributeSet getAttributes() const
Return the attribute list for this Function.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool isIntegerTy() const
True if this is an instance of IntegerType.
This file defines the FastISel class.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
bool isStructTy() const
True if this is an instance of StructType.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Value * getCondition() const
void emplace_back(ArgTypes &&...Args)
Bitwise operators - logical and, logical or, logical xor.
unsigned greater or equal
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
iterator find(const KeyT &Val)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
constexpr bool isUInt< 16 >(uint64_t x)
bool hasLocalLinkage() const
const APFloat & getValueAPF() const
bool isUnsigned() const
Determine if this instruction is using an unsigned comparison.
static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
0 0 0 1 True if ordered and equal
LLVM Value Representation.
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
Primary interface to the complete machine description for the target machine.
const Value * getFalseValue() const
unsigned getLocMemOffset() const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
0 0 1 1 True if ordered and greater than or equal
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const BasicBlock * getParent() const
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void convertToReg(unsigned RegNo)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
iterator_range< arg_iterator > args()
A wrapper class for inspecting calls to intrinsic functions.
an instruction to allocate memory on the stack
gep_type_iterator gep_type_begin(const User *GEP)