15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
55 class SIScheduleDAGMI;
56 class SIScheduleBlockCreator;
62 std::vector<SUnit*> SUnits;
63 std::map<unsigned, unsigned> NodeNum2Index;
64 std::vector<SUnit*> TopReadySUs;
65 std::vector<SUnit*> ScheduledSUnits;
75 std::vector<unsigned> InternalAdditionnalPressure;
77 std::vector<unsigned> LiveInPressure;
78 std::vector<unsigned> LiveOutPressure;
84 std::set<unsigned> LiveInRegs;
85 std::set<unsigned> LiveOutRegs;
88 bool HighLatencyBlock;
90 std::vector<unsigned> HasLowLatencyNonWaitedParent;
95 std::vector<SIScheduleBlock*> Preds;
96 std::vector<SIScheduleBlock*> Succs;
97 unsigned NumHighLatencySuccessors;
102 DAG(DAG), BC(BC), TopRPTracker(TopPressure), Scheduled(
false),
103 HighLatencyBlock(
false), ID(ID), NumHighLatencySuccessors(0) {}
107 unsigned getID()
const {
return ID; }
119 const std::vector<SIScheduleBlock*>&
getPreds()
const {
return Preds; }
120 const std::vector<SIScheduleBlock*>&
getSuccs()
const {
return Succs; }
126 return NumHighLatencySuccessors;
156 return InternalAdditionnalPressure;
172 unsigned LowLatencyOffset;
173 bool HasLowLatencyNonWaitedParent;
175 SISchedCandidate() =
default;
177 bool isValid()
const {
return SU; }
180 void setBest(SISchedCandidate &Best) {
181 assert(Best.Reason !=
NoCand &&
"uninitialized Sched candidate");
183 Reason = Best.Reason;
184 SGPRUsage = Best.SGPRUsage;
185 VGPRUsage = Best.VGPRUsage;
186 IsLowLatency = Best.IsLowLatency;
187 LowLatencyOffset = Best.LowLatencyOffset;
188 HasLowLatencyNonWaitedParent = Best.HasLowLatencyNonWaitedParent;
194 void undoReleaseSucc(SUnit *SU, SDep *SuccEdge);
195 void releaseSucc(SUnit *SU, SDep *SuccEdge);
198 void releaseSuccessors(SUnit *SU,
bool InOrOutBlock);
200 void nodeScheduled(SUnit *SU);
201 void tryCandidateTopDown(SISchedCandidate &Cand, SISchedCandidate &TryCand);
202 void tryCandidateBottomUp(SISchedCandidate &Cand, SISchedCandidate &TryCand);
204 void traceCandidate(
const SISchedCandidate &Cand);
224 std::vector<std::unique_ptr<SIScheduleBlock>> BlockPtrs;
227 std::vector<SIScheduleBlock*> CurrentBlocks;
228 std::vector<int> Node2CurrentBlock;
232 std::vector<int> TopDownIndex2Block;
233 std::vector<int> TopDownBlock2Index;
234 std::vector<int> BottomUpIndex2Block;
240 int NextNonReservedID;
241 std::vector<int> CurrentColoring;
242 std::vector<int> CurrentTopDownReservedDependencyColoring;
243 std::vector<int> CurrentBottomUpReservedDependencyColoring;
256 void colorHighLatenciesAlone();
259 void colorHighLatenciesGroups();
263 void colorComputeReservedDependencies();
266 void colorAccordingToReservedDependencies();
271 void colorEndsAccordingToDependencies();
274 void colorForceConsecutiveOrderInGroup();
278 void colorMergeConstantLoadsNextGroup();
281 void colorMergeIfPossibleNextGroup();
285 void colorMergeIfPossibleNextGroupOnlyForReserved();
289 void colorMergeIfPossibleSmallGroupsToNextGroup();
294 void cutHugeBlocks();
298 void regroupNoUserInstructions();
302 void topologicalSort();
304 void scheduleInsideBlocks();
318 std::vector<SIScheduleBlock*> Blocks;
320 std::vector<std::map<unsigned, unsigned>> LiveOutRegsNumUsages;
321 std::set<unsigned> LiveRegs;
323 std::map<unsigned, unsigned> LiveRegsConsumers;
325 std::vector<unsigned> LastPosHighLatencyParentScheduled;
326 int LastPosWaitedHighLatency;
328 std::vector<SIScheduleBlock*> BlocksScheduled;
329 unsigned NumBlockScheduled;
330 std::vector<SIScheduleBlock*> ReadyBlocks;
332 unsigned VregCurrentUsage;
333 unsigned SregCurrentUsage;
336 unsigned maxVregUsage;
337 unsigned maxSregUsage;
339 std::vector<unsigned> BlockNumPredsLeft;
340 std::vector<unsigned> BlockNumSuccsLeft;
348 std::vector<SIScheduleBlock*>
getBlocks() {
return BlocksScheduled; }
360 unsigned NumSuccessors;
361 unsigned NumHighLatencySuccessors;
362 unsigned LastPosHighLatParentScheduled;
365 SIBlockSchedCandidate() =
default;
367 bool isValid()
const {
return Block; }
370 void setBest(SIBlockSchedCandidate &Best) {
371 assert(Best.Reason !=
NoCand &&
"uninitialized Sched candidate");
373 Reason = Best.Reason;
374 IsHighLatency = Best.IsHighLatency;
375 VGPRUsageDiff = Best.VGPRUsageDiff;
376 NumSuccessors = Best.NumSuccessors;
377 NumHighLatencySuccessors = Best.NumHighLatencySuccessors;
378 LastPosHighLatParentScheduled = Best.LastPosHighLatParentScheduled;
379 Height = Best.Height;
383 bool tryCandidateLatency(SIBlockSchedCandidate &Cand,
384 SIBlockSchedCandidate &TryCand);
385 bool tryCandidateRegUsage(SIBlockSchedCandidate &Cand,
386 SIBlockSchedCandidate &TryCand);
387 SIScheduleBlock *pickBlock();
389 void addLiveRegs(std::set<unsigned> &
Regs);
390 void decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &
Regs);
391 void releaseBlockSuccs(SIScheduleBlock *Parent);
392 void blockScheduled(SIScheduleBlock *Block);
396 std::vector<int> checkRegUsageImpact(std::set<unsigned> &InRegs,
397 std::set<unsigned> &OutRegs);
403 std::vector<unsigned>
SUs;
426 std::vector<SUnit> SUnitsLinksBackup;
429 std::vector<unsigned> ScheduledSUnits;
430 std::vector<unsigned> ScheduledSUnitsInv;
462 unsigned &SgprUsage);
465 std::set<unsigned> InRegs;
467 InRegs.insert(RegMaskPair.RegUnit);
476 void topologicalSort();
478 void moveLowLatencies();
493 #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H
std::vector< SIScheduleBlock * > Blocks
SIScheduleDAGMI(MachineSchedContext *C)
unsigned getNumHighLatencySuccessors() const
MachineBasicBlock::iterator CurrentTop
The top of the unscheduled zone.
SIScheduleCandReason Reason
std::vector< unsigned > & getInternalAdditionnalRegUsage()
std::vector< unsigned > IsLowLatencySU
void addUnit(SUnit *SU)
Functions for Block construction.
std::vector< SIScheduleBlock * > getBlocks()
MachineInstrBundleIterator< MachineInstr > iterator
~SIScheduleBlockScheduler()=default
RegisterClassInfo * RegClassInfo
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
std::vector< unsigned > LowLatencyOffset
~SIScheduleBlock()=default
std::set< unsigned > getInRegs()
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
Function Alias Analysis false
SmallVector< RegisterMaskPair, 8 > LiveInRegs
List of live in virtual registers or physical register units.
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
bool isRepeat(SIScheduleCandReason R)
unsigned getSGPRSetID() const
std::vector< int > TopDownIndex2Block
struct SIScheduleBlockResult scheduleVariant(SISchedulerBlockCreatorVariant BlockVariant, SISchedulerBlockSchedulerVariant ScheduleVariant)
void printDebug(bool Full)
~SIScheduleDAGMI() override
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx...
bool isSUInBlock(SUnit *SU, unsigned ID)
std::vector< int > TopDownIndex2SU
std::vector< SUnit * > getScheduledUnits()
SIScheduleBlockScheduler(SIScheduleDAGMI *DAG, SISchedulerBlockSchedulerVariant Variant, SIScheduleBlocks BlocksStruct)
MachineRegisterInfo * getMRI()
MachineBasicBlock * getBB()
static const unsigned End
Track the current register pressure at some position in the instruction stream, and remember the high...
const TargetRegisterInfo * getTRI()
SIScheduleBlocks getBlocks(SISchedulerBlockCreatorVariant BlockVariant)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineBasicBlock::iterator getCurrentBottom()
void schedule(MachineBasicBlock::iterator BeginBlock, MachineBasicBlock::iterator EndBlock)
std::set< unsigned > & getOutRegs()
SIScheduleBlock(SIScheduleDAGMI *DAG, SIScheduleBlockCreator *BC, unsigned ID)
void addSucc(SIScheduleBlock *Succ)
std::vector< unsigned > IsHighLatencySU
std::vector< unsigned > SUs
SISchedulerBlockCreatorVariant
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
SIScheduleBlockCreator(SIScheduleDAGMI *DAG)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
MachineBasicBlock::iterator getCurrentTop()
void fillVgprSgprCost(_Iterator First, _Iterator End, unsigned &VgprUsage, unsigned &SgprUsage)
bool isHighLatencyBlock()
const std::vector< SIScheduleBlock * > & getSuccs() const
unsigned getVGPRSetID() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Interface definition for SIInstrInfo.
void addPred(SIScheduleBlock *Pred)
const TargetRegisterInfo * TRI
std::vector< int > BottomUpIndex2SU
SIScheduler(SIScheduleDAGMI *DAG)
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
void restoreSULinksLeft()
void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)
Setup the RegPressureTracker.
void initRPTracker(RegPressureTracker &RPTracker)
MachineBasicBlock::iterator CurrentBottom
The bottom of the unscheduled zone.
std::set< unsigned > & getInRegs()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< int > TopDownBlock2Index
void setRepeat(SIScheduleCandReason R)
const std::vector< SIScheduleBlock * > & getPreds() const
~SIScheduleBlockCreator()
MachineBasicBlock * BB
State specific to the current scheduling region.
RegisterPressure & getPressure()
Get the resulting register pressure over the traversed region.
MachineRegisterInfo & MRI
RegPressureTracker RPTracker
SISchedulerBlockSchedulerVariant
SUnit - Scheduling unit. This is a node in the scheduling DAG.