43 static int NotFoundIndex = -10;
53 for (
int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) {
83 bool Modified =
false;
84 for (
auto MFI = MF.
begin(),
E = MF.
end(); MFI !=
E; ++MFI) {
86 for (
auto MBBI = MBB.
begin(),
E = MBB.
end(); MBBI !=
E; ++MBBI) {
89 if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) {
124 bool Modified =
false;
125 for (
auto MFI = MF.
begin(),
E = MF.
end(); MFI !=
E; ++MFI) {
127 for (
auto MBBI = MBB.
begin(),
E = MBB.
end(); MBBI !=
E; ++MBBI) {
132 const int UNASSIGNED_INDEX = -1;
133 int Reg1Index = UNASSIGNED_INDEX;
134 int Reg2Index = UNASSIGNED_INDEX;
135 int Reg3Index = UNASSIGNED_INDEX;
144 if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
145 Reg3Index != UNASSIGNED_INDEX) {
155 if (ScratchReg1Index == UNASSIGNED_INDEX ||
156 ScratchReg2Index == UNASSIGNED_INDEX) {
157 errs() <<
"Cannot allocate free scratch registers for the FixFSMULD "
163 .addReg(ScratchReg1Index)
168 .addReg(ScratchReg2Index)
175 .
addReg(ScratchReg2Index);
214 bool Modified =
false;
215 for (
auto MFI = MF.
begin(),
E = MF.
end(); MFI !=
E; ++MFI) {
217 for (
auto MBBI = MBB.
begin(),
E = MBB.
end(); MBBI !=
E; ++MBBI) {
221 const int UNASSIGNED_INDEX = -1;
222 int Reg1Index = UNASSIGNED_INDEX;
223 int Reg2Index = UNASSIGNED_INDEX;
224 int Reg3Index = UNASSIGNED_INDEX;
233 if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
234 Reg3Index != UNASSIGNED_INDEX) {
244 if (ScratchReg1Index == UNASSIGNED_INDEX ||
245 ScratchReg2Index == UNASSIGNED_INDEX) {
246 errs() <<
"Cannot allocate free scratch registers for the "
252 .addReg(ScratchReg1Index)
257 .addReg(ScratchReg2Index)
264 .
addReg(ScratchReg2Index);
296 bool Modified =
false;
297 for (
auto MFI = MF.
begin(),
E = MF.
end(); MFI !=
E; ++MFI) {
299 for (
auto MBBI = MBB.
begin(),
E = MBB.
end(); MBBI !=
E; ++MBBI) {
308 errs() <<
"Error: You are using the detectroundchange "
309 "option to detect rounding changes that will "
310 "cause LEON errata. The only way to fix this "
311 "is to remove the call to fesetround from "
312 "the source code.\n";
349 bool Modified =
false;
350 for (
auto MFI = MF.
begin(),
E = MF.
end(); MFI !=
E; ++MFI) {
352 for (
auto MBBI = MBB.
begin(),
E = MBB.
end(); MBBI !=
E; ++MBBI) {
360 if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
361 for (
int InsertedCount = 0; InsertedCount < 5; InsertedCount++)
365 for (
int InsertedCount = 0; InsertedCount < 28; InsertedCount++)
LLVM_NODISCARD int compare_lower(StringRef RHS) const
compare_lower - Compare two strings, ignoring case.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
const GlobalValue * getGlobal() const
ReplaceFMULS(TargetMachine &tm)
FixAllFDIVSQRT(TargetMachine &tm)
InsertNOPLoad(TargetMachine &tm)
const SparcInstrInfo * getInstrInfo() const override
DetectRoundChange(TargetMachine &tm)
StringRef getName() const
Return a constant reference to the value's name.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
LEONMachineFunctionPass(TargetMachine &tm, char &ID)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
void clearUsedRegisterList()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
TargetInstrInfo - Interface to description of machine instruction set.
const SparcSubtarget * Subtarget
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int GetRegIndexForOperand(MachineInstr &MI, int OperandIndex)
unsigned const MachineRegisterInfo * MRI
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const MachineOperand & getOperand(unsigned i) const
int getUnusedFPRegister(MachineRegisterInfo &MRI)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void markRegisterUsed(int registerIndex)
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
FixFSMULD(TargetMachine &tm)
std::vector< int > UsedRegisters
unsigned getReg() const
getReg - Returns the register number.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.