41 #define DEBUG_TYPE "arm-register-info"
43 #define GET_REGINFO_TARGET_DESC
44 #include "ARMGenRegisterInfo.inc"
62 : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
68 return CSR_NoRegs_SaveList;
73 return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
77 return CSR_FIQ_SaveList;
81 return CSR_GenericInt_SaveList;
87 return CSR_iOS_SwiftError_SaveList;
91 ? CSR_iOS_CXX_TLS_PE_SaveList
92 : CSR_iOS_CXX_TLS_SaveList;
98 assert(MF &&
"Invalid MachineFunction pointer.");
101 return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
111 return CSR_NoRegs_RegMask;
115 return CSR_iOS_SwiftError_RegMask;
118 return CSR_iOS_CXX_TLS_RegMask;
119 return STI.
isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
124 return CSR_NoRegs_RegMask;
130 "only know about special TLS call on Darwin");
131 return CSR_iOS_TLSCall_RegMask;
138 return CSR_NoRegs_RegMask;
140 return CSR_FPRegs_RegMask;
160 : CSR_AAPCS_ThisReturn_RegMask;
170 markSuperRegs(Reserved, ARM::SP);
171 markSuperRegs(Reserved,
ARM::PC);
172 markSuperRegs(Reserved, ARM::FPSCR);
173 markSuperRegs(Reserved, ARM::APSR_NZCV);
177 markSuperRegs(Reserved,
BasePtr);
180 markSuperRegs(Reserved, ARM::R9);
183 static_assert(ARM::D31 == ARM::D16 + 15,
"Register list not consecutive!");
184 for (
unsigned R = 0; R < 16; ++R)
185 markSuperRegs(Reserved, ARM::D16 + R);
190 if (Reserved.
test(*
SI)) markSuperRegs(Reserved, *
I);
192 assert(checkAllSuperRegsMarked(Reserved));
202 switch (Super->
getID()) {
203 case ARM::GPRRegClassID:
204 case ARM::SPRRegClassID:
205 case ARM::DPRRegClassID:
206 case ARM::QPRRegClassID:
207 case ARM::QQPRRegClassID:
208 case ARM::QQQQPRRegClassID:
209 case ARM::GPRPairRegClassID:
220 return &ARM::GPRRegClass;
225 if (RC == &ARM::CCRRegClass)
226 return &ARM::rGPRRegClass;
236 switch (RC->
getID()) {
239 case ARM::tGPRRegClassID:
240 return TFI->hasFP(MF) ? 4 : 5;
241 case ARM::GPRRegClassID: {
242 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
245 case ARM::SPRRegClassID:
246 case ARM::DPRRegClassID:
254 if (ARM::GPRPairRegClass.
contains(*Supers))
255 return RI->
getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
271 switch (Hint.first) {
286 unsigned Paired = Hint.second;
290 unsigned PairedPhys = 0;
293 }
else if (VRM && VRM->
hasPhys(Paired)) {
302 for (
unsigned I = 0,
E = Order.
size();
I !=
E; ++
I) {
303 unsigned Reg = Order[
I];
304 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
326 unsigned OtherReg = Hint.second;
329 if (Hint.second == Reg) {
347 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
388 if (TFI->hasReservedCallFrame(MF))
401 || needsStackRealignment(MF);
418 const DebugLoc &dl,
unsigned DestReg,
unsigned SubIdx,
int Val,
429 .addConstantPoolIndex(Idx)
458 int64_t InstrOffs = 0;
473 InstrOffs = -InstrOffs;
481 InstrOffs = -InstrOffs;
488 InstrOffs = -InstrOffs;
501 return InstrOffs * Scale;
511 assert(i < MI->getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
525 case ARM::LDRi12:
case ARM::LDRH:
case ARM::LDRBi12:
526 case ARM::STRi12:
case ARM::STRH:
case ARM::STRBi12:
527 case ARM::t2LDRi12:
case ARM::t2LDRi8:
528 case ARM::t2STRi12:
case ARM::t2STRi8:
529 case ARM::VLDRS:
case ARM::VLDRD:
530 case ARM::VSTRS:
case ARM::VSTRD:
531 case ARM::tSTRspi:
case ARM::tLDRspi:
551 int64_t FPOffset = Offset - 8;
570 if (TFI->
hasFP(MF) &&
591 unsigned BaseReg,
int FrameIdx,
599 if (Ins != MBB->
end())
600 DL = Ins->getDebugLoc();
626 "This resolveFrameIndex does not support Thumb1!");
639 assert (Done &&
"Unable to resolve frame index!");
651 assert(i < MI->getNumOperands() &&
"Instr doesn't have FrameIndex operand!");
658 unsigned NumBits = 0;
660 bool isSigned =
true;
687 NumBits = (BaseReg == ARM::SP ? 8 : 5);
698 if ((Offset & (Scale-1)) != 0)
701 if (isSigned && Offset < 0)
704 unsigned Mask = (1 << NumBits) - 1;
705 if ((
unsigned)Offset <= Mask * Scale)
713 int SPAdj,
unsigned FIOperandNum,
723 "This eliminateFrameIndex does not support Thumb1!");
736 "Cannot use SP to access the emergency spill slot in "
737 "functions without a reserved call frame");
739 "Cannot use SP to access the emergency spill slot in "
740 "functions with variable sized frame objects");
744 assert(!MI.
isDebugValue() &&
"DBG_VALUEs should be handled in target-independent code");
763 "This code isn't needed if offset already handled!");
765 unsigned ScratchReg = 0;
813 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
815 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
825 DEBUG(
dbgs() <<
"\tARM::shouldCoalesce - Coalesced Weight: "
826 << It->second <<
"\n");
827 DEBUG(
dbgs() <<
"\tARM::shouldCoalesce - Reg Weight: "
828 << NewRCWeight.RegWeight <<
"\n");
836 unsigned SizeMultiplier =
MBB->
size()/100;
837 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
838 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
839 It->second += NewRCWeight.RegWeight;
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
bool useR7AsFramePointer() const
static unsigned char getAM3Offset(unsigned AM3Opc)
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
const ARMTargetLowering * getTargetLowering() const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isThumbFunction() const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isThumb1Only() const
const MCPhysReg * iterator
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const uint32_t * getNoPreservedMask() const override
bool isR9Reserved() const
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
bool useSoftFloat() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
bool isTargetDarwin() const
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
unsigned getLocalFrameMaxAlign() const
Return the required alignment of the local object blob.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool isThumb1OnlyFunction() const
const uint32_t * getSjLjDispatchPreservedMask(const MachineFunction &MF) const
size_t size() const
size - Get the array size.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool isDebugValue() const
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
unsigned const MachineRegisterInfo * MRI
bool requiresRegisterScavenging(const MachineFunction &MF) const override
Code Generation virtual methods...
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
static unsigned char getAM5Offset(unsigned AM5Opc)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
const TargetRegisterClass *const * sc_iterator
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
static unsigned getFramePointerReg(const ARMSubtarget &STI)
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
static AddrOpc getAM2Op(unsigned AM2Opc)
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static unsigned getAM2Offset(unsigned AM2Opc)
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool test(unsigned Idx) const
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
bool canRealignStack(const MachineFunction &MF) const override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
AttributeSet getAttributes() const
Return the attribute list for this Function.
bool hasBasePointer(const MachineFunction &MF) const
AddrMode
ARM Addressing Modes.
static AddrOpc getAM3Op(unsigned AM3Opc)
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const override
SrcRC and DstRC will be morphed into NewRC if this returns true.
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static AddrOpc getAM5Op(unsigned AM5Opc)
unsigned getReg() const
getReg - Returns the register number.
StringRef getValueAsString() const
Return the attribute's value as a string.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool cannotEliminateFrame(const MachineFunction &MF) const
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool isThumb2Function() const
DenseMap< const MachineBasicBlock *, unsigned >::iterator getCoalescedWeight(MachineBasicBlock *MBB)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
const uint32_t * getTLSCallPreservedMask(const MachineFunction &MF) const
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.