|
LLVM
4.0.0
|
#include <X86Subtarget.h>
Protected Types | |
| enum | X86SSEEnum { NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F } |
| enum | X863DNowEnum { NoThreeDNow, MMX, ThreeDNow, ThreeDNowA } |
| enum | X86ProcFamilyEnum { Others, IntelAtom, IntelSLM } |
Protected Attributes | |
| X86ProcFamilyEnum | X86ProcFamily |
| X86 processor family: Intel Atom, and others. More... | |
| PICStyles::Style | PICStyle |
| Which PIC style to use. More... | |
| const TargetMachine & | TM |
| X86SSEEnum | X86SSELevel |
| SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. More... | |
| X863DNowEnum | X863DNowLevel |
| MMX, 3DNow, 3DNow Athlon, or none supported. More... | |
| bool | HasX87 |
| True if the processor supports X87 instructions. More... | |
| bool | HasCMov |
| True if this processor has conditional move instructions (generally pentium pro+). More... | |
| bool | HasX86_64 |
| True if the processor supports X86-64 instructions. More... | |
| bool | HasPOPCNT |
| True if the processor supports POPCNT. More... | |
| bool | HasSSE4A |
| True if the processor supports SSE4A instructions. More... | |
| bool | HasAES |
| Target has AES instructions. More... | |
| bool | HasFXSR |
| Target has FXSAVE/FXRESTOR instructions. More... | |
| bool | HasXSAVE |
| Target has XSAVE instructions. More... | |
| bool | HasXSAVEOPT |
| Target has XSAVEOPT instructions. More... | |
| bool | HasXSAVEC |
| Target has XSAVEC instructions. More... | |
| bool | HasXSAVES |
| Target has XSAVES instructions. More... | |
| bool | HasPCLMUL |
| Target has carry-less multiplication. More... | |
| bool | HasFMA |
| Target has 3-operand fused multiply-add. More... | |
| bool | HasFMA4 |
| Target has 4-operand fused multiply-add. More... | |
| bool | HasXOP |
| Target has XOP instructions. More... | |
| bool | HasTBM |
| Target has TBM instructions. More... | |
| bool | HasMOVBE |
| True if the processor has the MOVBE instruction. More... | |
| bool | HasRDRAND |
| True if the processor has the RDRAND instruction. More... | |
| bool | HasF16C |
| Processor has 16-bit floating point conversion instructions. More... | |
| bool | HasFSGSBase |
| Processor has FS/GS base insturctions. More... | |
| bool | HasLZCNT |
| Processor has LZCNT instruction. More... | |
| bool | HasBMI |
| Processor has BMI1 instructions. More... | |
| bool | HasBMI2 |
| Processor has BMI2 instructions. More... | |
| bool | HasVBMI |
| Processor has VBMI instructions. More... | |
| bool | HasIFMA |
| Processor has Integer Fused Multiply Add. More... | |
| bool | HasRTM |
| Processor has RTM instructions. More... | |
| bool | HasHLE |
| Processor has HLE. More... | |
| bool | HasADX |
| Processor has ADX instructions. More... | |
| bool | HasSHA |
| Processor has SHA instructions. More... | |
| bool | HasPRFCHW |
| Processor has PRFCHW instructions. More... | |
| bool | HasRDSEED |
| Processor has RDSEED instructions. More... | |
| bool | HasLAHFSAHF |
| Processor has LAHF/SAHF instructions. More... | |
| bool | HasMWAITX |
| Processor has MONITORX/MWAITX instructions. More... | |
| bool | HasPFPREFETCHWT1 |
| Processor has Prefetch with intent to Write instruction. More... | |
| bool | IsBTMemSlow |
| True if BT (bit test) of memory instructions are slow. More... | |
| bool | IsSHLDSlow |
| True if SHLD instructions are slow. More... | |
| bool | IsPMULLDSlow |
| True if the PMULLD instruction is slow compared to PMULLW/PMULHW and. More... | |
| bool | IsUAMem16Slow |
| True if unaligned memory accesses of 16-bytes are slow. More... | |
| bool | IsUAMem32Slow |
| True if unaligned memory accesses of 32-bytes are slow. More... | |
| bool | HasSSEUnalignedMem |
| True if SSE operations can have unaligned memory operands. More... | |
| bool | HasCmpxchg16b |
| True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips. More... | |
| bool | UseLeaForSP |
| True if the LEA instruction should be used for adjusting the stack pointer. More... | |
| bool | HasFastPartialYMMWrite |
| True if there is no performance penalty to writing only the lower parts of a YMM register without clearing the upper part. More... | |
| bool | HasFastScalarFSQRT |
| True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration. More... | |
| bool | HasFastVectorFSQRT |
| True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. More... | |
| bool | HasSlowDivide32 |
| True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible. More... | |
| bool | HasSlowDivide64 |
| True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible. More... | |
| bool | HasFastLZCNT |
| True if LZCNT instruction is fast. More... | |
| bool | PadShortFunctions |
| True if the short functions should be padded to prevent a stall when returning too early. More... | |
| bool | CallRegIndirect |
| True if the Calls with memory reference should be converted to a register-based indirect call. More... | |
| bool | LEAUsesAG |
| True if the LEA instruction inputs have to be ready at address generation (AG) time. More... | |
| bool | SlowLEA |
| True if the LEA instruction with certain arguments is slow. More... | |
| bool | SlowIncDec |
| True if INC and DEC instructions are slow when writing to flags. More... | |
| bool | HasPFI |
| Processor has AVX-512 PreFetch Instructions. More... | |
| bool | HasERI |
| Processor has AVX-512 Exponential and Reciprocal Instructions. More... | |
| bool | HasCDI |
| Processor has AVX-512 Conflict Detection Instructions. More... | |
| bool | HasDQI |
| Processor has AVX-512 Doubleword and Quadword instructions. More... | |
| bool | HasBWI |
| Processor has AVX-512 Byte and Word instructions. More... | |
| bool | HasVLX |
| Processor has AVX-512 Vector Length eXtenstions. More... | |
| bool | HasPKU |
| Processor has PKU extenstions. More... | |
| bool | HasMPX |
| Processor supports MPX - Memory Protection Extensions. More... | |
| bool | HasInvPCId |
| Processor supports Invalidate Process-Context Identifier. More... | |
| bool | HasVMFUNC |
| Processor has VM Functions. More... | |
| bool | HasSMAP |
| Processor has Supervisor Mode Access Protection. More... | |
| bool | HasSGX |
| Processor has Software Guard Extensions. More... | |
| bool | HasCLFLUSHOPT |
| Processor supports Flush Cache Line instruction. More... | |
| bool | HasPCOMMIT |
| Processor has Persistent Commit feature. More... | |
| bool | HasCLWB |
| Processor supports Cache Line Write Back instruction. More... | |
| bool | UseSoftFloat |
| Use software floating point for code generation. More... | |
| unsigned | stackAlignment |
| The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More... | |
| unsigned | MaxInlineSizeThreshold |
| Max. More... | |
| Triple | TargetTriple |
| What processor and OS we're targeting. More... | |
| InstrItineraryData | InstrItins |
| Instruction itineraries for scheduling. More... | |
| std::unique_ptr< GISelAccessor > | GISel |
| Gather the accessor points to GlobalISel-related APIs. More... | |
Definition at line 46 of file X86Subtarget.h.
|
protected |
| Enumerator | |
|---|---|
| NoThreeDNow | |
| MMX | |
| ThreeDNow | |
| ThreeDNowA | |
Definition at line 53 of file X86Subtarget.h.
|
protected |
| Enumerator | |
|---|---|
| Others | |
| IntelAtom | |
| IntelSLM | |
Definition at line 57 of file X86Subtarget.h.
|
protected |
| Enumerator | |
|---|---|
| NoSSE | |
| SSE1 | |
| SSE2 | |
| SSE3 | |
| SSSE3 | |
| SSE41 | |
| SSE42 | |
| AVX | |
| AVX2 | |
| AVX512F | |
Definition at line 49 of file X86Subtarget.h.
| X86Subtarget::X86Subtarget | ( | const Triple & | TT, |
| StringRef | CPU, | ||
| StringRef | FS, | ||
| const X86TargetMachine & | TM, | ||
| unsigned | StackAlignOverride | ||
| ) |
This constructor initializes the data members to match that of the specified triple.
Definition at line 313 of file X86Subtarget.cpp.
References llvm::PICStyles::GOT, is64Bit(), isPositionIndependent(), isTargetCOFF(), isTargetDarwin(), isTargetELF(), llvm::PICStyles::None, llvm::PICStyles::RIPRel, setPICStyle(), and llvm::PICStyles::StubPIC.
|
inline |
Definition at line 472 of file X86Subtarget.h.
References CallRegIndirect.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
| unsigned char X86Subtarget::classifyBlockAddressReference | ( | ) | const |
Classify a blockaddress reference for the current subtarget according to how we should reference it in a non-pcrel context.
Definition at line 49 of file X86Subtarget.cpp.
References classifyLocalReference().
| unsigned char X86Subtarget::classifyGlobalFunctionReference | ( | const GlobalValue * | GV, |
| const Module & | M | ||
| ) | const |
Classify a global function reference for the current subtarget.
Definition at line 123 of file X86Subtarget.cpp.
References assert(), F, is64Bit(), isTargetCOFF(), isTargetELF(), llvm::X86II::MO_GOTPCREL, llvm::X86II::MO_NO_FLAG, llvm::X86II::MO_PLT, llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.
Referenced by classifyGlobalFunctionReference().
| unsigned char X86Subtarget::classifyGlobalFunctionReference | ( | const GlobalValue * | GV | ) | const |
Definition at line 118 of file X86Subtarget.cpp.
References classifyGlobalFunctionReference(), and llvm::GlobalValue::getParent().
| unsigned char X86Subtarget::classifyGlobalReference | ( | const GlobalValue * | GV, |
| const Module & | M | ||
| ) | const |
Definition at line 89 of file X86Subtarget.cpp.
References classifyLocalReference(), llvm::TargetMachine::getCodeModel(), is64Bit(), llvm::GlobalValue::isAbsoluteSymbolRef(), isPositionIndependent(), isTargetCOFF(), isTargetDarwin(), llvm::CodeModel::Large, llvm::X86II::MO_DARWIN_NONLAZY, llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE, llvm::X86II::MO_DLLIMPORT, llvm::X86II::MO_GOT, llvm::X86II::MO_GOTPCREL, llvm::X86II::MO_NO_FLAG, llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.
Referenced by classifyGlobalReference(), llvm::X86TargetLowering::isLegalAddressingMode(), and llvm::X86TargetLowering::LowerAsmOperandForConstraint().
| unsigned char X86Subtarget::classifyGlobalReference | ( | const GlobalValue * | GV | ) | const |
Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context.
Definition at line 56 of file X86Subtarget.cpp.
References classifyGlobalReference(), and llvm::GlobalValue::getParent().
| unsigned char X86Subtarget::classifyLocalReference | ( | const GlobalValue * | GV | ) | const |
Classify a global variable reference for the current subtarget according to how we should reference it in a non-pcrel context.
Definition at line 61 of file X86Subtarget.cpp.
References llvm::GlobalValue::hasCommonLinkage(), is64Bit(), llvm::GlobalValue::isDeclarationForLinker(), isPositionIndependent(), isTargetCOFF(), isTargetDarwin(), llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE, llvm::X86II::MO_GOTOFF, llvm::X86II::MO_NO_FLAG, and llvm::X86II::MO_PIC_BASE_OFFSET.
Referenced by classifyBlockAddressReference(), and classifyGlobalReference().
|
override |
Definition at line 359 of file X86Subtarget.cpp.
References hasCMov(), and X86EarlyIfConv.
|
inlineoverride |
Enable the MachineScheduler pass for all X86 subtargets.
Definition at line 617 of file X86Subtarget.h.
|
inlineoverride |
Definition at line 626 of file X86Subtarget.h.
References llvm::TargetSubtargetInfo::ANTIDEP_CRITICAL.
| const char * X86Subtarget::getBZeroEntry | ( | ) | const |
This function returns the name of a function which has an interface like the non-standard bzero function, if such a function exists on the current subtarget and it is considered prefereable over memset with zero passed as the second argument.
This function returns the name of a function which has an interface like the non-standard bzero function, if such a function exists on the current subtarget and it is considered preferable over memset with zero passed as the second argument.
Otherwise it returns null.
Definition at line 150 of file X86Subtarget.cpp.
References getTargetTriple().
|
override |
Methods used by Global ISel.
Definition at line 339 of file X86Subtarget.cpp.
|
inlineoverride |
Definition at line 345 of file X86Subtarget.h.
Referenced by ExpandMOVImmSExti8(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::X86TargetLowering::getRegisterByName(), llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::storeRegToStackSlot().
|
inlineoverride |
Definition at line 344 of file X86Subtarget.h.
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter(), emitMonitor(), emitRDPKRU(), emitWRPKRU(), and getRegisterInfo().
|
inlineoverride |
Return the instruction itineraries based on the subtarget selection.
Definition at line 622 of file X86Subtarget.h.
References InstrItins.
|
override |
Definition at line 344 of file X86Subtarget.cpp.
|
override |
Definition at line 349 of file X86Subtarget.cpp.
|
inline |
Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition at line 362 of file X86Subtarget.h.
References MaxInlineSizeThreshold.
|
inline |
Definition at line 405 of file X86Subtarget.h.
References PICStyle.
|
override |
Definition at line 354 of file X86Subtarget.cpp.
|
inlineoverride |
Definition at line 351 of file X86Subtarget.h.
References getInstrInfo(), and llvm::X86InstrInfo::getRegisterInfo().
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::getRegisterByName(), llvm::X86TargetLowering::getReturnAddressFrameIndex(), LowerINTRINSIC_W_CHAIN(), LowerINTRINSIC_WO_CHAIN(), llvm::X86TargetLowering::ReplaceNodeResults(), and llvm::X86TargetLowering::X86TargetLowering().
|
inlineoverride |
Definition at line 348 of file X86Subtarget.h.
|
inline |
Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Definition at line 358 of file X86Subtarget.h.
References stackAlignment.
|
inlineoverride |
Definition at line 341 of file X86Subtarget.h.
Referenced by combineOrCmpEqZeroToCtlzSrl(), combineSIntToFP(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), and LowerINSERT_SUBVECTOR().
Definition at line 496 of file X86Subtarget.h.
References TargetTriple.
Referenced by computeBytesPoppedByCalleeForSRet(), getBZeroEntry(), llvm::X86TargetLowering::getSafeStackPointerLocation(), llvm::X86TargetLowering::getSDagStackGuard(), llvm::X86TargetLowering::getSSPStackGuardCheck(), hasSinCos(), and llvm::X86TargetLowering::insertSSPDeclarations().
|
inline |
Definition at line 423 of file X86Subtarget.h.
References ThreeDNow, and X863DNowLevel.
|
inline |
Definition at line 424 of file X86Subtarget.h.
References ThreeDNowA, and X863DNowLevel.
|
inline |
Definition at line 451 of file X86Subtarget.h.
References HasADX.
|
inline |
Definition at line 426 of file X86Subtarget.h.
References HasAES.
|
inline |
Definition at line 437 of file X86Subtarget.h.
References hasAVX512(), hasFMA(), and hasFMA4().
Referenced by combineFMA(), combineFneg(), isFMAddSub(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 416 of file X86Subtarget.h.
References AVX, and X86SSELevel.
Referenced by llvm::X86InstrInfo::breakPartialRegDependency(), combineFMinNumFMaxNum(), combineSext(), combineX86ShuffleChain(), llvm::X86InstrInfo::copyPhysReg(), CopyToFromAsymmetricReg(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaxInterleaveFactor(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TTIImpl::getReductionCost(), llvm::X86TTIImpl::getRegisterBitWidth(), hasFp256(), isAddSub(), llvm::X86TTIImpl::isLegalMaskedLoad(), LowerEXTRACT_SUBVECTOR(), LowerINSERT_SUBVECTOR(), LowerToHorizontalOp(), lowerV2F64VectorShuffle(), lowerV4F32VectorShuffle(), LowerVectorBroadcast(), lowerVectorShuffleAsBroadcast(), LowerVSETCC(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), llvm::X86InstrInfo::shouldScheduleAdjacent(), and X86ChooseCmpOpcode().
|
inline |
Definition at line 417 of file X86Subtarget.h.
References AVX2, and X86SSELevel.
Referenced by combineBasicSADPattern(), combineLoopSADPattern(), combineSelect(), combineShuffleOfConcatUndef(), combineVectorTruncation(), combineX86ShuffleChain(), detectAVGPattern(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86InstrInfo::getExecutionDomain(), llvm::X86TTIImpl::getIntrinsicInstrCost(), hasInt256(), insert128BitVector(), lower256BitVectorShuffle(), lowerShuffleAsRepeatedMaskAndLanePermute(), LowerToHorizontalOp(), lowerV16I16VectorShuffle(), lowerV2X128VectorShuffle(), lowerV32I8VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8I32VectorShuffle(), LowerVectorBroadcast(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleWithPSHUFB(), lowerVectorShuffleWithUndefHalf(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), llvm::X86TargetLowering::ReplaceNodeResults(), and llvm::X86InstrInfo::setExecutionDomain().
|
inline |
Definition at line 418 of file X86Subtarget.h.
References AVX512F, and X86SSELevel.
Referenced by combineCompareEqual(), combineMaskedLoad(), combineSelect(), combineToExtendVectorInReg(), combineVectorSignBitsTruncation(), combineVSelectWithAllOnesOrZeros(), combineX86ShuffleChain(), CopyToFromAsymmetricReg(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86RegisterInfo::getReservedRegs(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), hasAnyFMA(), isAddSub(), llvm::X86TTIImpl::isLegalMaskedGather(), lower1BitVectorShuffle(), lower512BitVectorShuffle(), LowerEXTEND_VECTOR_INREG(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerScalarImmediateShift(), lowerUINT_TO_FP_v2i32(), LowerVectorCTLZ(), LowerVSETCC(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86InstrInfo::setExecutionDomain(), truncateVectorCompareWithPACKSS(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 445 of file X86Subtarget.h.
References HasBMI.
Referenced by combineAnd(), llvm::X86TargetLowering::hasAndNotCompare(), llvm::X86TargetLowering::isCheapToSpeculateCttz(), Passv64i1ArgInRegs(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 446 of file X86Subtarget.h.
References HasBMI2.
|
inline |
Definition at line 480 of file X86Subtarget.h.
References HasBWI.
Referenced by combineBasicSADPattern(), combineLoopSADPattern(), combineSelect(), combineX86ShuffleChain(), llvm::X86InstrInfo::copyPhysReg(), CopyToFromAsymmetricReg(), detectAVGPattern(), EmitKTEST(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), getMaskNode(), llvm::X86TargetLowering::getSetCCResultType(), getv64i1Argument(), getZeroVector(), llvm::X86TTIImpl::isLegalMaskedLoad(), lower1BitVectorShuffle(), LowerExtended1BitVectorLoad(), LowerMLOAD(), LowerMSTORE(), LowerMUL(), LowerSIGN_EXTEND_AVX512(), LowerTruncateVecI1(), LowerTruncatingStore(), lowerV16I16VectorShuffle(), lowerV16I32VectorShuffle(), lowerV32I16VectorShuffle(), lowerV64I8VectorShuffle(), LowerVectorCTPOP(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleWithPSHUFB(), LowerVSETCC(), LowerZERO_EXTEND_AVX512(), matchVectorShuffleAsShift(), Passv64i1ArgInRegs(), llvm::X86TargetLowering::ReplaceNodeResults(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 476 of file X86Subtarget.h.
References HasCDI.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 409 of file X86Subtarget.h.
References HasCMov.
Referenced by llvm::X86InstrInfo::canInsertSelect(), combineXor(), and enableEarlyIfConversion().
|
inline |
Definition at line 463 of file X86Subtarget.h.
References HasCmpxchg16b.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 479 of file X86Subtarget.h.
References HasDQI.
Referenced by combineSIntToFP(), CopyToFromAsymmetricReg(), EmitKTEST(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86InstrInfo::getExecutionDomain(), insert1BitVector(), lower1BitVectorShuffle(), LowerExtended1BitVectorLoad(), LowerSIGN_EXTEND_AVX512(), LowerTruncatingStore(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86InstrInfo::setExecutionDomain(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 478 of file X86Subtarget.h.
References HasERI.
|
inline |
Definition at line 442 of file X86Subtarget.h.
References HasF16C.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 468 of file X86Subtarget.h.
References HasFastLZCNT.
Referenced by llvm::X86TargetLowering::isCtlzFast().
|
inline |
Definition at line 465 of file X86Subtarget.h.
References HasFastPartialYMMWrite.
|
inline |
Definition at line 466 of file X86Subtarget.h.
References HasFastScalarFSQRT.
|
inline |
Definition at line 467 of file X86Subtarget.h.
References HasFastVectorFSQRT.
|
inline |
Definition at line 435 of file X86Subtarget.h.
References HasFMA, and HasFMA4.
Referenced by hasAnyFMA().
|
inline |
|
inline |
Definition at line 419 of file X86Subtarget.h.
References hasAVX().
Referenced by combineFaddFsub(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), LowerANY_EXTEND(), LowerZERO_EXTEND(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 443 of file X86Subtarget.h.
References HasFSGSBase.
|
inline |
Definition at line 427 of file X86Subtarget.h.
References HasFXSR.
|
inline |
Definition at line 450 of file X86Subtarget.h.
References HasHLE.
|
inline |
Definition at line 448 of file X86Subtarget.h.
References HasIFMA.
|
inline |
Definition at line 420 of file X86Subtarget.h.
References hasAVX2().
Referenced by combineAdd(), combineLogicBlendIntoPBLENDV(), combineSignExtendInReg(), combineSub(), combineToExtendVectorInReg(), getOnesVector(), llvm::X86TargetLowering::isVectorShiftByScalarCheap(), LowerAVXExtend(), LowerBITREVERSE(), LowerEXTEND_VECTOR_INREG(), LowerExtendedLoad(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), LowerScalarImmediateShift(), LowerShift(), LowerSIGN_EXTEND(), LowerVectorBroadcast(), LowerVectorCTLZ(), LowerVectorCTPOP(), LowerVSETCC(), materializeVectorConstant(), performShiftToAllZeros(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), truncateVectorCompareWithPACKSS(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 455 of file X86Subtarget.h.
References HasLAHFSAHF.
Referenced by llvm::X86InstrInfo::copyPhysReg().
|
inline |
Definition at line 444 of file X86Subtarget.h.
References HasLZCNT.
Referenced by llvm::X86TargetLowering::isCheapToSpeculateCtlz(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).
There isn't any reason to disable it if the target processor supports it.
Definition at line 494 of file X86Subtarget.h.
References hasSSE2(), and is64Bit().
Referenced by LowerATOMIC_FENCE().
|
inline |
Definition at line 422 of file X86Subtarget.h.
References MMX, and X863DNowLevel.
Referenced by llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), LowerBITCAST(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 440 of file X86Subtarget.h.
References HasMOVBE.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 483 of file X86Subtarget.h.
References HasMPX.
|
inline |
Definition at line 456 of file X86Subtarget.h.
References HasMWAITX.
|
inline |
Definition at line 432 of file X86Subtarget.h.
References HasPCLMUL.
|
inline |
Definition at line 477 of file X86Subtarget.h.
References HasPFI.
|
inline |
Definition at line 482 of file X86Subtarget.h.
References HasPKU.
|
inline |
Definition at line 425 of file X86Subtarget.h.
References HasPOPCNT.
Referenced by llvm::X86TTIImpl::getPopcntSupport(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 453 of file X86Subtarget.h.
References HasPRFCHW.
|
inline |
Definition at line 441 of file X86Subtarget.h.
References HasRDRAND.
|
inline |
Definition at line 454 of file X86Subtarget.h.
References HasRDSEED.
|
inline |
Definition at line 449 of file X86Subtarget.h.
References HasRTM.
|
inline |
Definition at line 452 of file X86Subtarget.h.
References HasSHA.
| bool X86Subtarget::hasSinCos | ( | ) | const |
This function returns true if the target has sincos() routine in its compiler runtime or math libraries.
Definition at line 159 of file X86Subtarget.cpp.
References getTargetTriple(), is64Bit(), llvm::Triple::isMacOSX(), and llvm::Triple::isMacOSXVersionLT().
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 469 of file X86Subtarget.h.
References HasSlowDivide32.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 470 of file X86Subtarget.h.
References HasSlowDivide64.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 410 of file X86Subtarget.h.
References SSE1, and X86SSELevel.
Referenced by combineBitcast(), combineFAndFNotToFAndn(), combineFMinNumFMaxNum(), combineSelect(), combineSetCC(), convertIntLogicToFPLogic(), get64BitArgumentXMMs(), llvm::X86TargetLowering::getByValTypeAlignment(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), llvm::X86TargetLowering::getSingleConstraintMatchWeight(), llvm::X86TargetLowering::LowerXConstraint(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), X86ChooseCmpOpcode(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 411 of file X86Subtarget.h.
References SSE2, and X86SSELevel.
Referenced by combineBasicSADPattern(), combineBitcast(), combineCompareEqual(), combineFAndFNotToFAndn(), combineFMinNumFMaxNum(), combineLogicBlendIntoPBLENDV(), combineSelect(), combineSetCC(), combineStore(), combineToExtendVectorInReg(), combineVectorSignBitsTruncation(), combineVectorTruncation(), llvm::X86InstrInfo::commuteInstructionImpl(), convertIntLogicToFPLogic(), detectAVGPattern(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getZeroVector(), hasMFence(), LowerBITCAST(), LowerEXTEND_VECTOR_INREG(), LowerExtendedLoad(), LowerMUL(), LowerMUL_LOHI(), LowerShift(), LowerVSETCC(), lowerX86FPLogicOp(), llvm::X86TargetLowering::LowerXConstraint(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryPermuteVectorShuffle(), matchUnaryVectorShuffle(), materializeVectorConstant(), reduceVMULWidth(), llvm::X86TargetLowering::ReplaceNodeResults(), truncateVectorCompareWithPACKSS(), X86ChooseCmpOpcode(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 412 of file X86Subtarget.h.
References SSE3, and X86SSELevel.
Referenced by llvm::X86TargetLowering::BuildFILD(), combineFaddFsub(), isAddSub(), LowerToHorizontalOp(), lowerV4F32VectorShuffle(), lowerVectorShuffleAsBroadcast(), matchUnaryVectorShuffle(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 414 of file X86Subtarget.h.
References SSE41, and X86SSELevel.
Referenced by combineLogicBlendIntoPBLENDV(), combineSelect(), combineToExtendVectorInReg(), combineVectorTruncation(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::X86TTIImpl::getArithmeticInstrCost(), llvm::X86TTIImpl::getCastInstrCost(), getTargetVShiftNode(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerEXTEND_VECTOR_INREG(), LowerExtendedLoad(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), lowerUINT_TO_FP_vXi32(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4I32VectorShuffle(), lowerV8I16VectorShuffle(), LowerVectorAllZeroTest(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), LowerVSETCC(), matchBinaryPermuteVectorShuffle(), matchBinaryVectorShuffle(), matchUnaryVectorShuffle(), reduceVMULWidth(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 415 of file X86Subtarget.h.
References SSE42, and X86SSELevel.
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter(), foldVectorXorShiftIntoCmp(), llvm::X86TTIImpl::getCmpSelInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getReductionCost(), and LowerVSETCC().
|
inline |
Definition at line 421 of file X86Subtarget.h.
References HasSSE4A.
Referenced by lowerV16I8VectorShuffle(), lowerV8I16VectorShuffle(), and lowerVectorShuffleAsSpecificZeroOrAnyExtend().
|
inline |
Definition at line 462 of file X86Subtarget.h.
References HasSSEUnalignedMem.
|
inline |
Definition at line 413 of file X86Subtarget.h.
References SSSE3, and X86SSELevel.
Referenced by combineAdd(), combineSub(), combineVectorTruncation(), combineX86ShuffleChain(), llvm::X86TTIImpl::getIntrinsicInstrCost(), LowerBITREVERSE(), LowerToHorizontalOp(), lowerV16I8VectorShuffle(), lowerV2I64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV8I16VectorShuffle(), LowerVectorCTLZ(), LowerVectorCTPOP(), lowerVectorShuffleAsByteRotate(), lowerVectorShuffleAsSpecificZeroOrAnyExtend(), lowerVectorShuffleWithPSHUFB(), matchBinaryPermuteVectorShuffle(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
|
inline |
Definition at line 447 of file X86Subtarget.h.
References HasVBMI.
Referenced by combineX86ShuffleChain(), llvm::X86TTIImpl::getShuffleCost(), and lowerV64I8VectorShuffle().
|
inline |
Definition at line 481 of file X86Subtarget.h.
References HasVLX.
Referenced by combineSelect(), combineX86ShuffleChain(), llvm::X86InstrInfo::copyPhysReg(), llvm::X86TTIImpl::getGatherScatterOpCost(), llvm::X86RegisterInfo::getLargestLegalSuperClass(), getLoadStoreRegOpcode(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getSetCCResultType(), getZeroVector(), LowerExtended1BitVectorLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerSIGN_EXTEND_AVX512(), LowerTruncatingStore(), lowerV16I16VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8I32VectorShuffle(), LowerVectorBroadcast(), lowerVectorShuffleAsRotate(), LowerVSETCC(), LowerZERO_EXTEND_AVX512(), llvm::X86TargetLowering::ReplaceNodeResults(), SupportedVectorShiftWithImm(), SupportedVectorVarShift(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 408 of file X86Subtarget.h.
References HasX87.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 438 of file X86Subtarget.h.
References HasXOP.
Referenced by combineX86ShuffleChain(), llvm::X86TTIImpl::getIntrinsicInstrCost(), LowerBITREVERSE(), LowerRotate(), LowerScalarImmediateShift(), LowerShift(), LowerVSETCC(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 428 of file X86Subtarget.h.
References HasXSAVE.
|
inline |
Definition at line 430 of file X86Subtarget.h.
References HasXSAVEC.
|
inline |
Definition at line 429 of file X86Subtarget.h.
References HasXSAVEOPT.
|
inline |
Definition at line 431 of file X86Subtarget.h.
References HasXSAVES.
|
inline |
Definition at line 389 of file X86Subtarget.h.
|
inline |
Definition at line 385 of file X86Subtarget.h.
Referenced by llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::X86FrameLowering::emitPrologue(), getMaskNode(), getv64i1Argument(), LowerVectorBroadcast(), Passv64i1ArgInRegs(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::restoreWin32EHStackPointers(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Is this x86_64? (disregarding specific ABI / programming model)
Definition at line 381 of file X86Subtarget.h.
Referenced by classifyGlobalFunctionReference(), classifyGlobalReference(), classifyLocalReference(), combineCompareEqual(), combineSIntToFP(), combineStore(), computeBytesPoppedByCalleeForSRet(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::copyPhysReg(), llvm::X86FrameLowering::emitEpilogue(), emitMonitor(), ExpandMOVImmSExti8(), llvm::X86TargetLowering::findRepresentativeClass(), llvm::X86InstrInfo::foldMemoryOperandImpl(), get64BitArgumentGPRs(), get64BitArgumentXMMs(), llvm::X86TargetLowering::getByValTypeAlignment(), getExtendedControlRegister(), llvm::X86InstrInfo::getGlobalBaseReg(), llvm::X86TargetLowering::getIRStackGuard(), getLoadStoreRegOpcode(), llvm::X86TTIImpl::getNumberOfRegisters(), llvm::X86TargetLowering::getOptimalMemOpType(), llvm::X86TargetLowering::getPICJumpTableRelocBase(), getReadPerformanceCounter(), getReadTimeStampCounter(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getRegisterBitWidth(), getRetOpcode(), llvm::X86TargetLowering::getSafeStackPointerLocation(), hasMFence(), hasSinCos(), llvm::X86InstrInfo::isCoalescableExtInstr(), llvm::X86TargetLowering::isLegalAddressingMode(), isTargetNaCl32(), isTargetNaCl64(), isXRaySupported(), llvm::X86TargetLowering::isZExtFree(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), LowerBITCAST(), LowerCMP_SWAP(), LowerFSINCOS(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerVACOPY(), printAsmMRegister(), llvm::X86FrameLowering::processFunctionBeforeFrameFinalized(), recoverFramePointer(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), SimplifyShortMoveForm(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), llvm::X86TargetLowering::supportSwiftError(), llvm::X86TargetLowering::useLoadStackGuardNode(), llvm::X86FrameLowering::X86FrameLowering(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 487 of file X86Subtarget.h.
References IntelAtom, and X86ProcFamily.
Referenced by llvm::X86TTIImpl::enableInterleavedAccessVectorization(), llvm::X86TTIImpl::getMaxInterleaveFactor(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 457 of file X86Subtarget.h.
References IsBTMemSlow.
|
inline |
Definition at line 562 of file X86Subtarget.h.
References llvm::CallingConv::C, llvm::CallingConv::Fast, llvm::CallingConv::Intel_OCL_BI, isTargetWin64(), llvm::CallingConv::X86_64_SysV, llvm::CallingConv::X86_64_Win64, llvm::CallingConv::X86_FastCall, llvm::CallingConv::X86_StdCall, llvm::CallingConv::X86_ThisCall, and llvm::CallingConv::X86_VectorCall.
Referenced by llvm::X86FrameLowering::emitPrologue(), get64BitArgumentGPRs(), get64BitArgumentXMMs(), and LowerVACOPY().
| bool X86Subtarget::isLegalToCallImmediateAddr | ( | ) | const |
Return true if the subtarget allows calls to immediate address.
Definition at line 166 of file X86Subtarget.cpp.
References llvm::TargetMachine::getRelocationModel(), isTargetELF(), isTargetWin32(), llvm::Reloc::Static, and TM.
|
inline |
Definition at line 543 of file X86Subtarget.h.
References llvm::Triple::isOSWindows(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitPrologue(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), and llvm::X86FrameLowering::spillCalleeSavedRegisters().
|
inline |
Definition at line 553 of file X86Subtarget.h.
References llvm::PICStyles::GOT, and PICStyle.
Referenced by llvm::X86TargetLowering::getJumpTableEncoding(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), and llvm::X86TargetLowering::LowerCustomJumpTableEntry().
|
inline |
Definition at line 554 of file X86Subtarget.h.
References PICStyle, and llvm::PICStyles::RIPRel.
Referenced by llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::X86AsmPrinter::PrintAsmOperand().
|
inline |
Definition at line 556 of file X86Subtarget.h.
References PICStyle, and llvm::PICStyles::StubPIC.
Referenced by llvm::X86TargetLowering::LowerAsmOperandForConstraint().
|
inline |
Definition at line 459 of file X86Subtarget.h.
References IsPMULLDSlow.
Referenced by reduceVMULWidth().
|
inline |
Definition at line 560 of file X86Subtarget.h.
References llvm::TargetMachine::isPositionIndependent(), and TM.
Referenced by classifyGlobalReference(), classifyLocalReference(), and X86Subtarget().
|
inline |
|
inline |
Definition at line 488 of file X86Subtarget.h.
References IntelSLM, and X86ProcFamily.
Referenced by llvm::X86TTIImpl::enableInterleavedAccessVectorization(), and llvm::X86TTIImpl::getArithmeticInstrCost().
|
inline |
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition at line 394 of file X86Subtarget.h.
References llvm::Triple::getEnvironment(), llvm::Triple::GNUX32, llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitEpilogue(), llvm::X86FrameLowering::emitPrologue(), and llvm::X86RegisterInfo::getPtrSizedFrameRegister().
|
inline |
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition at line 400 of file X86Subtarget.h.
References llvm::Triple::getEnvironment(), llvm::Triple::GNUX32, llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by llvm::X86TargetLowering::getExceptionPointerRegister(), llvm::X86TargetLowering::getExceptionSelectorRegister(), llvm::X86RegisterInfo::getPointerRegClass(), and llvm::X86FrameLowering::X86FrameLowering().
|
inline |
Definition at line 511 of file X86Subtarget.h.
References llvm::Triple::isAndroid(), and TargetTriple.
Referenced by llvm::X86TargetLowering::getSafeStackPointerLocation().
|
inline |
Definition at line 505 of file X86Subtarget.h.
References llvm::Triple::isOSBinFormatCOFF(), and TargetTriple.
Referenced by classifyGlobalFunctionReference(), classifyGlobalReference(), classifyLocalReference(), llvm::X86AsmPrinter::runOnMachineFunction(), and X86Subtarget().
|
inline |
Definition at line 541 of file X86Subtarget.h.
References llvm::Triple::isOSCygMing(), and TargetTriple.
Referenced by isTargetWin32(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 498 of file X86Subtarget.h.
References llvm::Triple::isOSDarwin(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks(), classifyGlobalReference(), classifyLocalReference(), LowerFSINCOS(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 500 of file X86Subtarget.h.
References llvm::Triple::isOSDragonFly(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks().
|
inline |
Definition at line 504 of file X86Subtarget.h.
References llvm::Triple::isOSBinFormatELF(), and TargetTriple.
Referenced by classifyGlobalFunctionReference(), isLegalToCallImmediateAddr(), X86Subtarget(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 499 of file X86Subtarget.h.
References llvm::Triple::isOSFreeBSD(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks().
|
inline |
Definition at line 510 of file X86Subtarget.h.
References llvm::Triple::isOSGlibc(), and TargetTriple.
Referenced by llvm::X86TargetLowering::getIRStackGuard(), and llvm::X86TargetLowering::insertSSPDeclarations().
|
inline |
Definition at line 509 of file X86Subtarget.h.
References llvm::Triple::isOSKFreeBSD(), and TargetTriple.
|
inline |
Definition at line 521 of file X86Subtarget.h.
References llvm::Triple::isKnownWindowsMSVCEnvironment(), and TargetTriple.
Referenced by llvm::X86AsmPrinter::GetCPISymbol(), isTargetWin32(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 508 of file X86Subtarget.h.
References llvm::Triple::isOSLinux(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForHiPEPrologue(), and llvm::X86FrameLowering::adjustForSegmentedStacks().
|
inline |
Definition at line 506 of file X86Subtarget.h.
References llvm::Triple::isOSBinFormatMachO(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitPrologue(), and llvm::X86TargetLowering::useLoadStackGuardNode().
|
inline |
Definition at line 515 of file X86Subtarget.h.
References llvm::Triple::isOSIAMCU(), and TargetTriple.
Referenced by computeBytesPoppedByCalleeForSRet().
|
inline |
Definition at line 512 of file X86Subtarget.h.
References llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by isTargetNaCl32(), and isTargetNaCl64().
|
inline |
Definition at line 513 of file X86Subtarget.h.
References is64Bit(), and isTargetNaCl().
|
inline |
Definition at line 514 of file X86Subtarget.h.
References is64Bit(), and isTargetNaCl().
Referenced by llvm::X86FrameLowering::X86FrameLowering().
|
inline |
Definition at line 502 of file X86Subtarget.h.
References llvm::Triple::isPS4CPU(), and TargetTriple.
|
inline |
Definition at line 501 of file X86Subtarget.h.
References llvm::Triple::isOSSolaris(), and TargetTriple.
|
inline |
Definition at line 549 of file X86Subtarget.h.
References isTargetCygMing(), and isTargetKnownWindowsMSVC().
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks(), isLegalToCallImmediateAddr(), and llvm::X86FrameLowering::restoreWin32EHStackPointers().
|
inline |
Definition at line 545 of file X86Subtarget.h.
References llvm::Triple::isOSWindows(), and TargetTriple.
Referenced by llvm::X86FrameLowering::adjustForSegmentedStacks(), llvm::X86FrameLowering::canUseAsEpilogue(), llvm::X86FrameLowering::getFrameIndexReferencePreferSP(), isCallingConvWin64(), llvm::X86TargetLowering::needsFixedCatchObjects(), and llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 525 of file X86Subtarget.h.
References llvm::Triple::isWindowsCoreCLREnvironment(), and TargetTriple.
Referenced by llvm::X86FrameLowering::emitStackProbe().
|
inline |
Definition at line 529 of file X86Subtarget.h.
References llvm::Triple::isWindowsCygwinEnvironment(), and TargetTriple.
|
inline |
Definition at line 533 of file X86Subtarget.h.
References llvm::Triple::isWindowsGNUEnvironment(), and TargetTriple.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 537 of file X86Subtarget.h.
References llvm::Triple::isWindowsItaniumEnvironment(), and TargetTriple.
Referenced by llvm::X86TargetLowering::X86TargetLowering().
|
inline |
Definition at line 517 of file X86Subtarget.h.
References llvm::Triple::isWindowsMSVCEnvironment(), and TargetTriple.
Referenced by llvm::X86FrameLowering::restoreWin32EHStackPointers().
|
inline |
Definition at line 460 of file X86Subtarget.h.
References IsUAMem16Slow.
Referenced by llvm::X86TargetLowering::allowsMisalignedMemoryAccesses(), llvm::X86TargetLowering::getOptimalMemOpType(), and llvm::X86InstrInfo::unfoldMemoryOperand().
|
inline |
Definition at line 461 of file X86Subtarget.h.
References IsUAMem32Slow.
Referenced by llvm::X86TargetLowering::allowsMisalignedMemoryAccesses(), and llvm::X86TTIImpl::getMemoryOpCost().
|
inlineoverridevirtual |
Definition at line 485 of file X86Subtarget.h.
References is64Bit().
|
inline |
Definition at line 473 of file X86Subtarget.h.
References LEAUsesAG.
|
inline |
Definition at line 471 of file X86Subtarget.h.
References PadShortFunctions.
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Definition of function is auto generated by tblgen.
|
inline |
This object will take onwership of GISelAccessor.
Definition at line 339 of file X86Subtarget.h.
|
inline |
|
inline |
Definition at line 475 of file X86Subtarget.h.
References SlowIncDec.
|
inline |
Definition at line 474 of file X86Subtarget.h.
References SlowLEA.
|
inline |
Definition at line 464 of file X86Subtarget.h.
References UseLeaForSP.
|
inline |
Definition at line 489 of file X86Subtarget.h.
References UseSoftFloat.
Referenced by combineFMinNumFMaxNum(), combineSIntToFP(), combineStore(), get64BitArgumentXMMs(), llvm::X86TargetLowering::useSoftFloat(), and llvm::X86TargetLowering::X86TargetLowering().
|
protected |
True if the Calls with memory reference should be converted to a register-based indirect call.
Definition at line 232 of file X86Subtarget.h.
Referenced by callRegIndirect().
|
protected |
Gather the accessor points to GlobalISel-related APIs.
This is used to avoid ifndefs spreading around while GISel is an optional library.
Definition at line 309 of file X86Subtarget.h.
Referenced by getCallLowering(), getInstructionSelector(), getLegalizerInfo(), and getRegBankInfo().
|
protected |
Processor has ADX instructions.
Definition at line 155 of file X86Subtarget.h.
Referenced by hasADX().
|
protected |
|
protected |
Processor has BMI1 instructions.
Definition at line 137 of file X86Subtarget.h.
Referenced by hasBMI().
|
protected |
Processor has BMI2 instructions.
Definition at line 140 of file X86Subtarget.h.
Referenced by hasBMI2().
|
protected |
Processor has AVX-512 Byte and Word instructions.
Definition at line 257 of file X86Subtarget.h.
Referenced by hasBWI().
|
protected |
Processor has AVX-512 Conflict Detection Instructions.
Definition at line 251 of file X86Subtarget.h.
Referenced by hasCDI().
|
protected |
Processor supports Flush Cache Line instruction.
Definition at line 281 of file X86Subtarget.h.
|
protected |
Processor supports Cache Line Write Back instruction.
Definition at line 287 of file X86Subtarget.h.
|
protected |
True if this processor has conditional move instructions (generally pentium pro+).
Definition at line 80 of file X86Subtarget.h.
Referenced by hasCMov().
|
protected |
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips, but not the first AMD chips.
Definition at line 197 of file X86Subtarget.h.
Referenced by hasCmpxchg16b().
|
protected |
Processor has AVX-512 Doubleword and Quadword instructions.
Definition at line 254 of file X86Subtarget.h.
Referenced by hasDQI().
|
protected |
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition at line 248 of file X86Subtarget.h.
Referenced by hasERI().
|
protected |
Processor has 16-bit floating point conversion instructions.
Definition at line 128 of file X86Subtarget.h.
Referenced by hasF16C().
|
protected |
True if LZCNT instruction is fast.
Definition at line 224 of file X86Subtarget.h.
Referenced by hasFastLZCNT().
|
protected |
True if there is no performance penalty to writing only the lower parts of a YMM register without clearing the upper part.
Definition at line 205 of file X86Subtarget.h.
Referenced by hasFastPartialYMMWrite().
|
protected |
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Raphson iteration.
Definition at line 209 of file X86Subtarget.h.
Referenced by hasFastScalarFSQRT().
|
protected |
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
Definition at line 213 of file X86Subtarget.h.
Referenced by hasFastVectorFSQRT().
|
protected |
Target has 3-operand fused multiply-add.
Definition at line 110 of file X86Subtarget.h.
Referenced by hasFMA().
|
protected |
Target has 4-operand fused multiply-add.
Definition at line 113 of file X86Subtarget.h.
|
protected |
Processor has FS/GS base insturctions.
Definition at line 131 of file X86Subtarget.h.
Referenced by hasFSGSBase().
|
protected |
Target has FXSAVE/FXRESTOR instructions.
Definition at line 95 of file X86Subtarget.h.
Referenced by hasFXSR().
|
protected |
|
protected |
Processor has Integer Fused Multiply Add.
Definition at line 146 of file X86Subtarget.h.
Referenced by hasIFMA().
|
protected |
Processor supports Invalidate Process-Context Identifier.
Definition at line 269 of file X86Subtarget.h.
|
protected |
Processor has LAHF/SAHF instructions.
Definition at line 167 of file X86Subtarget.h.
Referenced by hasLAHFSAHF().
|
protected |
Processor has LZCNT instruction.
Definition at line 134 of file X86Subtarget.h.
Referenced by hasLZCNT().
|
protected |
True if the processor has the MOVBE instruction.
Definition at line 122 of file X86Subtarget.h.
Referenced by hasMOVBE().
|
protected |
Processor supports MPX - Memory Protection Extensions.
Definition at line 266 of file X86Subtarget.h.
Referenced by hasMPX().
|
protected |
Processor has MONITORX/MWAITX instructions.
Definition at line 170 of file X86Subtarget.h.
Referenced by hasMWAITX().
|
protected |
Target has carry-less multiplication.
Definition at line 107 of file X86Subtarget.h.
Referenced by hasPCLMUL().
|
protected |
Processor has Persistent Commit feature.
Definition at line 284 of file X86Subtarget.h.
|
protected |
Processor has AVX-512 PreFetch Instructions.
Definition at line 245 of file X86Subtarget.h.
Referenced by hasPFI().
|
protected |
Processor has Prefetch with intent to Write instruction.
Definition at line 173 of file X86Subtarget.h.
|
protected |
Processor has PKU extenstions.
Definition at line 263 of file X86Subtarget.h.
Referenced by hasPKU().
|
protected |
True if the processor supports POPCNT.
Definition at line 86 of file X86Subtarget.h.
Referenced by hasPOPCNT().
|
protected |
Processor has PRFCHW instructions.
Definition at line 161 of file X86Subtarget.h.
Referenced by hasPRFCHW().
|
protected |
True if the processor has the RDRAND instruction.
Definition at line 125 of file X86Subtarget.h.
Referenced by hasRDRAND().
|
protected |
Processor has RDSEED instructions.
Definition at line 164 of file X86Subtarget.h.
Referenced by hasRDSEED().
|
protected |
Processor has RTM instructions.
Definition at line 149 of file X86Subtarget.h.
Referenced by hasRTM().
|
protected |
Processor has Software Guard Extensions.
Definition at line 278 of file X86Subtarget.h.
|
protected |
Processor has SHA instructions.
Definition at line 158 of file X86Subtarget.h.
Referenced by hasSHA().
|
protected |
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possible.
Definition at line 217 of file X86Subtarget.h.
Referenced by hasSlowDivide32().
|
protected |
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possible.
Definition at line 221 of file X86Subtarget.h.
Referenced by hasSlowDivide64().
|
protected |
Processor has Supervisor Mode Access Protection.
Definition at line 275 of file X86Subtarget.h.
|
protected |
True if the processor supports SSE4A instructions.
Definition at line 89 of file X86Subtarget.h.
Referenced by hasSSE4A().
|
protected |
True if SSE operations can have unaligned memory operands.
This may require setting a configuration bit in the processor.
Definition at line 193 of file X86Subtarget.h.
Referenced by hasSSEUnalignedMem().
|
protected |
|
protected |
Processor has VBMI instructions.
Definition at line 143 of file X86Subtarget.h.
Referenced by hasVBMI().
|
protected |
Processor has AVX-512 Vector Length eXtenstions.
Definition at line 260 of file X86Subtarget.h.
Referenced by hasVLX().
|
protected |
Processor has VM Functions.
Definition at line 272 of file X86Subtarget.h.
|
protected |
True if the processor supports X86-64 instructions.
Definition at line 83 of file X86Subtarget.h.
|
protected |
True if the processor supports X87 instructions.
Definition at line 76 of file X86Subtarget.h.
Referenced by hasX87().
|
protected |
|
protected |
Target has XSAVE instructions.
Definition at line 98 of file X86Subtarget.h.
Referenced by hasXSAVE().
|
protected |
Target has XSAVEC instructions.
Definition at line 102 of file X86Subtarget.h.
Referenced by hasXSAVEC().
|
protected |
Target has XSAVEOPT instructions.
Definition at line 100 of file X86Subtarget.h.
Referenced by hasXSAVEOPT().
|
protected |
Target has XSAVES instructions.
Definition at line 104 of file X86Subtarget.h.
Referenced by hasXSAVES().
|
protected |
Instruction itineraries for scheduling.
Definition at line 304 of file X86Subtarget.h.
Referenced by getInstrItineraryData().
|
protected |
True if BT (bit test) of memory instructions are slow.
Definition at line 176 of file X86Subtarget.h.
Referenced by isBTMemSlow().
|
protected |
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition at line 183 of file X86Subtarget.h.
Referenced by isPMULLDSlow().
|
protected |
True if SHLD instructions are slow.
Definition at line 179 of file X86Subtarget.h.
Referenced by isSHLDSlow().
|
protected |
True if unaligned memory accesses of 16-bytes are slow.
Definition at line 186 of file X86Subtarget.h.
Referenced by isUnalignedMem16Slow().
|
protected |
True if unaligned memory accesses of 32-bytes are slow.
Definition at line 189 of file X86Subtarget.h.
Referenced by isUnalignedMem32Slow().
|
protected |
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition at line 236 of file X86Subtarget.h.
Referenced by LEAusesAG().
|
protected |
Max.
memset / memcpy size that is turned into rep/movs, rep/stos ops.
Definition at line 298 of file X86Subtarget.h.
Referenced by getMaxInlineSizeThreshold().
|
protected |
True if the short functions should be padded to prevent a stall when returning too early.
Definition at line 228 of file X86Subtarget.h.
Referenced by padShortFunctions().
|
protected |
Which PIC style to use.
Definition at line 65 of file X86Subtarget.h.
Referenced by getPICStyle(), isPICStyleGOT(), isPICStyleRIPRel(), isPICStyleStubPIC(), and setPICStyle().
|
protected |
True if INC and DEC instructions are slow when writing to flags.
Definition at line 242 of file X86Subtarget.h.
Referenced by slowIncDec().
|
protected |
True if the LEA instruction with certain arguments is slow.
Definition at line 239 of file X86Subtarget.h.
Referenced by slowLEA().
|
protected |
The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
Definition at line 294 of file X86Subtarget.h.
Referenced by getStackAlignment().
|
protected |
What processor and OS we're targeting.
Definition at line 301 of file X86Subtarget.h.
Referenced by getTargetTriple(), isOSWindows(), isTarget64BitILP32(), isTarget64BitLP64(), isTargetAndroid(), isTargetCOFF(), isTargetCygMing(), isTargetDarwin(), isTargetDragonFly(), isTargetELF(), isTargetFreeBSD(), isTargetGlibc(), isTargetKFreeBSD(), isTargetKnownWindowsMSVC(), isTargetLinux(), isTargetMachO(), isTargetMCU(), isTargetNaCl(), isTargetPS4(), isTargetSolaris(), isTargetWin64(), isTargetWindowsCoreCLR(), isTargetWindowsCygwin(), isTargetWindowsGNU(), isTargetWindowsItanium(), and isTargetWindowsMSVC().
|
protected |
Definition at line 67 of file X86Subtarget.h.
Referenced by classifyGlobalFunctionReference(), classifyGlobalReference(), isLegalToCallImmediateAddr(), and isPositionIndependent().
|
protected |
True if the LEA instruction should be used for adjusting the stack pointer.
This is an optimization for Intel Atom processors.
Definition at line 201 of file X86Subtarget.h.
Referenced by useLeaForSP().
|
protected |
Use software floating point for code generation.
Definition at line 290 of file X86Subtarget.h.
Referenced by useSoftFloat().
|
protected |
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition at line 73 of file X86Subtarget.h.
Referenced by has3DNow(), has3DNowA(), and hasMMX().
|
protected |
X86 processor family: Intel Atom, and others.
Definition at line 62 of file X86Subtarget.h.
|
protected |
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition at line 70 of file X86Subtarget.h.
Referenced by hasAVX(), hasAVX2(), hasAVX512(), hasSSE1(), hasSSE2(), hasSSE3(), hasSSE41(), hasSSE42(), and hasSSSE3().
1.8.6