LLVM  4.0.0
TargetSchedule.cpp
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1 //===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements a wrapper around MCSchedModel that allows the interface
11 // to benefit from information currently only available in TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
21 
22 using namespace llvm;
23 
24 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
25  cl::desc("Use TargetSchedModel for latency lookup"));
26 
27 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
28  cl::desc("Use InstrItineraryData for latency lookup"));
29 
31  return EnableSchedModel && SchedModel.hasInstrSchedModel();
32 }
33 
35  return EnableSchedItins && !InstrItins.isEmpty();
36 }
37 
38 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
39  // Dividend and Divisor will be naturally swapped as needed.
40  while(Divisor) {
41  unsigned Rem = Dividend % Divisor;
42  Dividend = Divisor;
43  Divisor = Rem;
44  };
45  return Dividend;
46 }
47 static unsigned lcm(unsigned A, unsigned B) {
48  unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
49  assert((LCM >= A && LCM >= B) && "LCM overflow");
50  return LCM;
51 }
52 
54  const TargetSubtargetInfo *sti,
55  const TargetInstrInfo *tii) {
56  SchedModel = sm;
57  STI = sti;
58  TII = tii;
59  STI->initInstrItins(InstrItins);
60 
61  unsigned NumRes = SchedModel.getNumProcResourceKinds();
62  ResourceFactors.resize(NumRes);
63  ResourceLCM = SchedModel.IssueWidth;
64  for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
65  unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
66  if (NumUnits > 0)
67  ResourceLCM = lcm(ResourceLCM, NumUnits);
68  }
69  MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
70  for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
71  unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
72  ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
73  }
74 }
75 
77  const MCSchedClassDesc *SC) const {
78  if (hasInstrItineraries()) {
79  int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
80  return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
81  }
82  if (hasInstrSchedModel()) {
83  if (!SC)
84  SC = resolveSchedClass(MI);
85  if (SC->isValid())
86  return SC->NumMicroOps;
87  }
88  return MI->isTransient() ? 0 : 1;
89 }
90 
91 // The machine model may explicitly specify an invalid latency, which
92 // effectively means infinite latency. Since users of the TargetSchedule API
93 // don't know how to handle this, we convert it to a very large latency that is
94 // easy to distinguish when debugging the DAG but won't induce overflow.
95 static unsigned capLatency(int Cycles) {
96  return Cycles >= 0 ? Cycles : 1000;
97 }
98 
99 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
100 /// evaluation of predicates that depend on instruction operands or flags.
103 
104  // Get the definition's scheduling class descriptor from this machine model.
105  unsigned SchedClass = MI->getDesc().getSchedClass();
106  const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
107  if (!SCDesc->isValid())
108  return SCDesc;
109 
110 #ifndef NDEBUG
111  unsigned NIter = 0;
112 #endif
113  while (SCDesc->isVariant()) {
114  assert(++NIter < 6 && "Variants are nested deeper than the magic number");
115 
116  SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
117  SCDesc = SchedModel.getSchedClassDesc(SchedClass);
118  }
119  return SCDesc;
120 }
121 
122 /// Find the def index of this operand. This index maps to the machine model and
123 /// is independent of use operands. Def operands may be reordered with uses or
124 /// merged with uses without affecting the def index (e.g. before/after
125 /// regalloc). However, an instruction's def operands must never be reordered
126 /// with respect to each other.
127 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
128  unsigned DefIdx = 0;
129  for (unsigned i = 0; i != DefOperIdx; ++i) {
130  const MachineOperand &MO = MI->getOperand(i);
131  if (MO.isReg() && MO.isDef())
132  ++DefIdx;
133  }
134  return DefIdx;
135 }
136 
137 /// Find the use index of this operand. This is independent of the instruction's
138 /// def operands.
139 ///
140 /// Note that uses are not determined by the operand's isUse property, which
141 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
142 /// a "use". The machine model allows an operand to be both a Def and Use.
143 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
144  unsigned UseIdx = 0;
145  for (unsigned i = 0; i != UseOperIdx; ++i) {
146  const MachineOperand &MO = MI->getOperand(i);
147  if (MO.isReg() && MO.readsReg() && !MO.isDef())
148  ++UseIdx;
149  }
150  return UseIdx;
151 }
152 
153 // Top-level API for clients that know the operand indices.
155  const MachineInstr *DefMI, unsigned DefOperIdx,
156  const MachineInstr *UseMI, unsigned UseOperIdx) const {
157 
159  return TII->defaultDefLatency(SchedModel, *DefMI);
160 
161  if (hasInstrItineraries()) {
162  int OperLatency = 0;
163  if (UseMI) {
164  OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
165  *UseMI, UseOperIdx);
166  }
167  else {
168  unsigned DefClass = DefMI->getDesc().getSchedClass();
169  OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
170  }
171  if (OperLatency >= 0)
172  return OperLatency;
173 
174  // No operand latency was found.
175  unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
176 
177  // Expected latency is the max of the stage latency and itinerary props.
178  // Rather than directly querying InstrItins stage latency, we call a TII
179  // hook to allow subtargets to specialize latency. This hook is only
180  // applicable to the InstrItins model. InstrSchedModel should model all
181  // special cases without TII hooks.
182  InstrLatency =
183  std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
184  return InstrLatency;
185  }
186  // hasInstrSchedModel()
187  const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
188  unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
189  if (DefIdx < SCDesc->NumWriteLatencyEntries) {
190  // Lookup the definition's write latency in SubtargetInfo.
191  const MCWriteLatencyEntry *WLEntry =
192  STI->getWriteLatencyEntry(SCDesc, DefIdx);
193  unsigned WriteID = WLEntry->WriteResourceID;
194  unsigned Latency = capLatency(WLEntry->Cycles);
195  if (!UseMI)
196  return Latency;
197 
198  // Lookup the use's latency adjustment in SubtargetInfo.
199  const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
200  if (UseDesc->NumReadAdvanceEntries == 0)
201  return Latency;
202  unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
203  int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
204  if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
205  return 0;
206  return Latency - Advance;
207  }
208  // If DefIdx does not exist in the model (e.g. implicit defs), then return
209  // unit latency (defaultDefLatency may be too conservative).
210 #ifndef NDEBUG
211  if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
212  && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
213  && SchedModel.isComplete()) {
214  errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
215  << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
216  llvm_unreachable("incomplete machine model");
217  }
218 #endif
219  // FIXME: Automatically giving all implicit defs defaultDefLatency is
220  // undesirable. We should only do it for defs that are known to the MC
221  // desc like flags. Truly implicit defs should get 1 cycle latency.
222  return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
223 }
224 
225 unsigned
226 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
227  unsigned Latency = 0;
228  for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
229  DefIdx != DefEnd; ++DefIdx) {
230  // Lookup the definition's write latency in SubtargetInfo.
231  const MCWriteLatencyEntry *WLEntry =
232  STI->getWriteLatencyEntry(&SCDesc, DefIdx);
233  Latency = std::max(Latency, capLatency(WLEntry->Cycles));
234  }
235  return Latency;
236 }
237 
238 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
239  assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
240 
241  unsigned SCIdx = TII->get(Opcode).getSchedClass();
242  const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx);
243 
244  if (SCDesc->isValid() && !SCDesc->isVariant())
245  return computeInstrLatency(*SCDesc);
246 
247  llvm_unreachable("No MI sched latency");
248 }
249 
250 unsigned
251 TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
252  bool UseDefaultDefLatency) const {
253  // For the itinerary model, fall back to the old subtarget hook.
254  // Allow subtargets to compute Bundle latencies outside the machine model.
255  if (hasInstrItineraries() || MI->isBundle() ||
256  (!hasInstrSchedModel() && !UseDefaultDefLatency))
257  return TII->getInstrLatency(&InstrItins, *MI);
258 
259  if (hasInstrSchedModel()) {
260  const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
261  if (SCDesc->isValid())
262  return computeInstrLatency(*SCDesc);
263  }
264  return TII->defaultDefLatency(SchedModel, *MI);
265 }
266 
267 unsigned TargetSchedModel::
268 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
269  const MachineInstr *DepMI) const {
270  if (!SchedModel.isOutOfOrder())
271  return 1;
272 
273  // Out-of-order processor can dispatch WAW dependencies in the same cycle.
274 
275  // Treat predication as a data dependency for out-of-order cpus. In-order
276  // cpus do not need to treat predicated writes specially.
277  //
278  // TODO: The following hack exists because predication passes do not
279  // correctly append imp-use operands, and readsReg() strangely returns false
280  // for predicated defs.
281  unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
282  const MachineFunction &MF = *DefMI->getParent()->getParent();
283  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
284  if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
285  return computeInstrLatency(DefMI);
286 
287  // If we have a per operand scheduling model, check if this def is writing
288  // an unbuffered resource. If so, it treated like an in-order cpu.
289  if (hasInstrSchedModel()) {
290  const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
291  if (SCDesc->isValid()) {
292  for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
293  *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
294  if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
295  return 1;
296  }
297  }
298  }
299  return 0;
300 }
bool isImplicit() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
size_t i
static unsigned lcm(unsigned A, unsigned B)
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
unsigned IssueWidth
Definition: MCSchedule.h:139
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
unsigned short NumMicroOps
Definition: MCSchedule.h:108
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti, const TargetInstrInfo *tii)
Initialize the machine model for instruction scheduling.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:212
static unsigned gcd(unsigned Dividend, unsigned Divisor)
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
static cl::opt< bool > EnableSchedItins("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup"))
bool isReg() const
isReg - Tests if this is a MO_Register operand.
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
Reg
All possible values of the reg field in the ModR/M byte.
INITIALIZE_PASS(AArch64VectorByElementOpt,"aarch64-vectorbyelement-opt", AARCH64_VECTOR_BY_ELEMENT_OPT_NAME, false, false) bool AArch64VectorByElementOpt unsigned SCIdx
Based only on latency of instructions, determine if it is cost efficient to replace the instruction I...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
bool isValid() const
Definition: MCSchedule.h:118
unsigned NumReadAdvanceEntries
Definition: MCSchedule.h:116
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isBundle() const
Definition: MachineInstr.h:804
unsigned getNumProcResourceKinds() const
Definition: MCSchedule.h:208
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
unsigned NumWriteLatencyEntries
Definition: MCSchedule.h:114
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:55
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:199
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:219
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool isVariant() const
Definition: MCSchedule.h:121
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:865
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
MachineOperand class - Representation of each machine instruction operand.
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
CHAIN = SC CHAIN, Imm128 - System call.
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:833
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx)
Find the use index of this operand.
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return the number of issue slots required for this MI.
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:556
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
static cl::opt< bool > EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup"))
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
Definition: MCSchedule.h:203
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:206
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx)
Find the def index of this operand.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
bool isEmpty() const
Returns true if there are no itineraries.
static unsigned capLatency(int Cycles)
const MCSchedClassDesc * SCDesc
void resize(size_type N)
Definition: SmallVector.h:352