LLVM  4.0.0
SIDefines.h
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1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #include "llvm/MC/MCInstrDesc.h"
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
14 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
15 
16 namespace llvm {
17 
18 namespace SIInstrFlags {
19 // This needs to be kept in sync with the field bits in InstSI.
20 enum : uint64_t {
21  // Low bits - basic encoding information.
22  SALU = 1 << 0,
23  VALU = 1 << 1,
24 
25  // SALU instruction formats.
26  SOP1 = 1 << 2,
27  SOP2 = 1 << 3,
28  SOPC = 1 << 4,
29  SOPK = 1 << 5,
30  SOPP = 1 << 6,
31 
32  // VALU instruction formats.
33  VOP1 = 1 << 7,
34  VOP2 = 1 << 8,
35  VOPC = 1 << 9,
36 
37  // TODO: Should this be spilt into VOP3 a and b?
38  VOP3 = 1 << 10,
39 
40  VINTRP = 1 << 13,
41  SDWA = 1 << 14,
42  DPP = 1 << 15,
43 
44  // Memory instruction formats.
45  MUBUF = 1 << 16,
46  MTBUF = 1 << 17,
47  SMRD = 1 << 18,
48  MIMG = 1 << 19,
49  EXP = 1 << 20,
50  FLAT = 1 << 21,
51  DS = 1 << 22,
52 
53  // Pseudo instruction formats.
54  VGPRSpill = 1 << 23,
55  SGPRSpill = 1 << 24,
56 
57  // High bits - other information.
58  VM_CNT = UINT64_C(1) << 32,
59  EXP_CNT = UINT64_C(1) << 33,
60  LGKM_CNT = UINT64_C(1) << 34,
61 
62  WQM = UINT64_C(1) << 35,
63  DisableWQM = UINT64_C(1) << 36,
64  Gather4 = UINT64_C(1) << 37,
65  SOPK_ZEXT = UINT64_C(1) << 38,
66  SCALAR_STORE = UINT64_C(1) << 39,
67  FIXED_SIZE = UINT64_C(1) << 40,
68  VOPAsmPrefer32Bit = UINT64_C(1) << 41
69 
70 };
71 
72 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
73 // The result is true if any of these tests are true.
74 enum ClassFlags {
75  S_NAN = 1 << 0, // Signaling NaN
76  Q_NAN = 1 << 1, // Quiet NaN
77  N_INFINITY = 1 << 2, // Negative infinity
78  N_NORMAL = 1 << 3, // Negative normal
79  N_SUBNORMAL = 1 << 4, // Negative subnormal
80  N_ZERO = 1 << 5, // Negative zero
81  P_ZERO = 1 << 6, // Positive zero
82  P_SUBNORMAL = 1 << 7, // Positive subnormal
83  P_NORMAL = 1 << 8, // Positive normal
84  P_INFINITY = 1 << 9 // Positive infinity
85 };
86 }
87 
88 namespace AMDGPU {
89  enum OperandType {
90  /// Operands with register or 32-bit immediate
97 
98  /// Operands with register or inline constant
105 
108 
111 
114 
115  // Operand for source modifiers for VOP instructions
117 
118  /// Operand with 32-bit immediate that uses the constant bus.
121  };
122 }
123 
124 // Input operand modifiers bit-masks
125 // NEG and SEXT share same bit-mask because they can't be set simultaneously.
126 namespace SISrcMods {
127  enum {
128  NEG = 1 << 0, // Floating-point negate modifier
129  ABS = 1 << 1, // Floating-point absolute modifier
130  SEXT = 1 << 0 // Integer sign-extend modifier
131  };
132 }
133 
134 namespace SIOutMods {
135  enum {
136  NONE = 0,
137  MUL2 = 1,
138  MUL4 = 2,
139  DIV2 = 3
140  };
141 }
142 
143 namespace VGPRIndexMode {
144  enum {
145  SRC0_ENABLE = 1 << 0,
146  SRC1_ENABLE = 1 << 1,
147  SRC2_ENABLE = 1 << 2,
148  DST_ENABLE = 1 << 3
149  };
150 }
151 
152 namespace AMDGPUAsmVariants {
153  enum {
154  DEFAULT = 0,
155  VOP3 = 1,
156  SDWA = 2,
157  DPP = 3
158  };
159 }
160 
161 namespace AMDGPU {
162 namespace EncValues { // Encoding values of enum9/8/7 operands
163 
164 enum {
165  SGPR_MIN = 0,
166  SGPR_MAX = 101,
167  TTMP_MIN = 112,
168  TTMP_MAX = 123,
175  VGPR_MIN = 256,
176  VGPR_MAX = 511
177 };
178 
179 } // namespace EncValues
180 } // namespace AMDGPU
181 
182 namespace AMDGPU {
183 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
184 
185 enum Id { // Message ID, width(4) [3:0].
190  ID_SYSMSG = 15,
191  ID_GAPS_LAST_, // Indicate that sequence has gaps.
195  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
196 };
197 
198 enum Op { // Both GS and SYS operation IDs.
201  // width(2) [5:4]
209  OP_GS_MASK_ = (((1 << OP_GS_WIDTH_) - 1) << OP_SHIFT_),
210  // width(3) [6:4]
219 };
220 
221 enum StreamId { // Stream ID, (2) [9:8].
228 };
229 
230 } // namespace SendMsg
231 
232 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
233 
234 enum Id { // HwRegCode, (6) [5:0]
236  ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined.
237  ID_MODE = 1,
240  ID_HW_ID = 4,
247  ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
248 };
249 
250 enum Offset { // Offset, (5) [10:6]
255 };
256 
257 enum WidthMinusOne { // WidthMinusOne, (5) [15:11]
262 };
263 
264 } // namespace Hwreg
265 
266 namespace SDWA {
267 
268 enum SdwaSel {
269  BYTE_0 = 0,
270  BYTE_1 = 1,
271  BYTE_2 = 2,
272  BYTE_3 = 3,
273  WORD_0 = 4,
274  WORD_1 = 5,
275  DWORD = 6,
276 };
277 
278 enum DstUnused {
282 };
283 
284 } // namespace SDWA
285 } // namespace AMDGPU
286 
287 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
288 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
289 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
290 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
291 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
292 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
293 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
294 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
295 
296 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
297 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
298 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
299 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE
300 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
301 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
302 #define C_00B84C_USER_SGPR 0xFFFFFFC1
303 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
304 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
305 #define C_00B84C_TGID_X_EN 0xFFFFFF7F
306 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
307 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
308 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF
309 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
310 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
311 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF
312 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
313 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
314 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
315 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
316 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
317 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
318 /* CIK */
319 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
320 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
321 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
322 /* */
323 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
324 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
325 #define C_00B84C_LDS_SIZE 0xFF007FFF
326 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
327 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
328 #define C_00B84C_EXCP_EN
329 
330 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
331 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
332 
333 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
334 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
335 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
336 #define C_00B848_VGPRS 0xFFFFFFC0
337 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
338 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
339 #define C_00B848_SGPRS 0xFFFFFC3F
340 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
341 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
342 #define C_00B848_PRIORITY 0xFFFFF3FF
343 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
344 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
345 #define C_00B848_FLOAT_MODE 0xFFF00FFF
346 #define S_00B848_PRIV(x) (((x) & 0x1) << 20)
347 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
348 #define C_00B848_PRIV 0xFFEFFFFF
349 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
350 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
351 #define C_00B848_DX10_CLAMP 0xFFDFFFFF
352 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
353 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
354 #define C_00B848_DEBUG_MODE 0xFFBFFFFF
355 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
356 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
357 #define C_00B848_IEEE_MODE 0xFF7FFFFF
358 
359 
360 // Helpers for setting FLOAT_MODE
361 #define FP_ROUND_ROUND_TO_NEAREST 0
362 #define FP_ROUND_ROUND_TO_INF 1
363 #define FP_ROUND_ROUND_TO_NEGINF 2
364 #define FP_ROUND_ROUND_TO_ZERO 3
365 
366 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
367 // precision.
368 #define FP_ROUND_MODE_SP(x) ((x) & 0x3)
369 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
370 
371 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
372 #define FP_DENORM_FLUSH_OUT 1
373 #define FP_DENORM_FLUSH_IN 2
374 #define FP_DENORM_FLUSH_NONE 3
375 
376 
377 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
378 // precision.
379 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
380 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
381 
382 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
383 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
384 
385 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
386 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
387 
388 #define R_SPILLED_SGPRS 0x4
389 #define R_SPILLED_VGPRS 0x8
390 
391 } // End namespace llvm
392 
393 #endif
Operands with register or inline constant.
Definition: SIDefines.h:99
Operands with register or 32-bit immediate.
Definition: SIDefines.h:91
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:119