LLVM  4.0.0
ARMRegisterBankInfo.cpp
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1 //===- ARMRegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the RegisterBankInfo class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMRegisterBankInfo.h"
15 #include "ARMInstrInfo.h" // For the register classes
20 
21 using namespace llvm;
22 
23 #ifndef LLVM_BUILD_GLOBAL_ISEL
24 #error "You shouldn't build this"
25 #endif
26 
27 // FIXME: TableGen this.
28 // If it grows too much and TableGen still isn't ready to do the job, extract it
29 // into an ARMGenRegisterBankInfo.def (similar to AArch64).
30 namespace llvm {
31 namespace ARM {
33  // Classes 0-31
34  (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) |
35  (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) |
36  (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) |
37  (1u << ARM::GPRnopc_and_hGPRRegClassID) |
38  (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) |
39  (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) |
40  (1u << ARM::hGPR_and_tcGPRRegClassID),
41  // Classes 32-63
42  0,
43  // Classes 64-96
44  0,
45  // FIXME: Some of the entries below this point can be safely removed once
46  // this is tablegenerated. It's only needed because of the hardcoded
47  // register class limit.
48  // Classes 97-128
49  0,
50  // Classes 129-160
51  0,
52  // Classes 161-192
53  0,
54  // Classes 193-224
55  0,
56 };
57 
60 
62 
65 } // end namespace arm
66 } // end namespace llvm
67 
70  static bool AlreadyInit = false;
71  // We have only one set of register banks, whatever the subtarget
72  // is. Therefore, the initialization of the RegBanks table should be
73  // done only once. Indeed the table of all register banks
74  // (ARM::RegBanks) is unique in the compiler. At some point, it
75  // will get tablegen'ed and the whole constructor becomes empty.
76  if (AlreadyInit)
77  return;
78  AlreadyInit = true;
79 
81  (void)RBGPR;
82  assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
83 
84  // Initialize the GPR bank.
85  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
86  "Subclass not added?");
87  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
88  "Subclass not added?");
89  assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
90  "Subclass not added?");
91  assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
92  "Subclass not added?");
93  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
94  "Subclass not added?");
95  assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
96  "Subclass not added?");
97  assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
98  "Subclass not added?");
99  assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");
100 }
101 
103  const TargetRegisterClass &RC) const {
104  using namespace ARM;
105 
106  switch (RC.getID()) {
107  case GPRRegClassID:
108  case tGPR_and_tcGPRRegClassID:
110  default:
111  llvm_unreachable("Unsupported register kind");
112  }
113 
114  llvm_unreachable("Switch should handle all register classes");
115 }
116 
119  auto Opc = MI.getOpcode();
120 
121  // Try the default logic for non-generic instructions that are either copies
122  // or already have some operands assigned to banks.
123  if (!isPreISelGenericOpcode(Opc)) {
125  if (Mapping.isValid())
126  return Mapping;
127  }
128 
129  using namespace TargetOpcode;
130 
131  unsigned NumOperands = MI.getNumOperands();
132  const ValueMapping *OperandsMapping = &ARM::ValueMappings[0];
133 
134  switch (Opc) {
135  case G_ADD:
136  case G_LOAD:
137  // FIXME: We're abusing the fact that everything lives in a GPR for now; in
138  // the real world we would use different mappings.
139  OperandsMapping = &ARM::ValueMappings[0];
140  break;
141  case G_FRAME_INDEX:
142  OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr});
143  break;
144  default:
145  return InstructionMapping{};
146  }
147 
148  return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
149  NumOperands};
150 }
RegisterBank ** RegBanks
Hold the set of supported register banks.
RegisterBankInfo::PartialMapping GPRPartialMapping
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getID() const
Return the register class ID number.
setjmp/longjmp based exceptions
const uint32_t GPRCoverageData[]
Holds all the information related to register banks.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Methods to get a uniquely generated array of ValueMapping.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
This file declares the targeting of the RegisterBankInfo class for ARM.
RegisterBankInfo::ValueMapping ValueMappings[]
Helper struct that represents how a value is partially mapped into a register.
Conditional register: NZCV.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
RegisterBank GPRRegBank(ARM::GPRRegBankID,"GPRB", 32, ARM::GPRCoverageData)
This class implements the register bank concept.
Definition: RegisterBank.h:29
Helper struct that represents how a value is mapped through different register banks.
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
bool isValid() const
Check whether this object is valid.
Representation of each machine instruction.
Definition: MachineInstr.h:52
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const override
Get a register bank that covers RC.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:55
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
InstructionMapping getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
RegisterBank * RegBanks[]
IRTranslator LLVM IR MI