LLVM  4.0.0
SparcDisassembler.cpp
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1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Sparc Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Sparc.h"
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCAsmInfo.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "sparc-disassembler"
27 
29 
30 namespace {
31 
32 /// A disassembler class for Sparc.
33 class SparcDisassembler : public MCDisassembler {
34 public:
35  SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
36  : MCDisassembler(STI, Ctx) {}
37  virtual ~SparcDisassembler() {}
38 
39  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
40  ArrayRef<uint8_t> Bytes, uint64_t Address,
41  raw_ostream &VStream,
42  raw_ostream &CStream) const override;
43 };
44 }
45 
46 namespace llvm {
50 }
51 
53  const MCSubtargetInfo &STI,
54  MCContext &Ctx) {
55  return new SparcDisassembler(STI, Ctx);
56 }
57 
58 
60  // Register the disassembler.
67 }
68 
69 static const unsigned IntRegDecoderTable[] = {
70  SP::G0, SP::G1, SP::G2, SP::G3,
71  SP::G4, SP::G5, SP::G6, SP::G7,
72  SP::O0, SP::O1, SP::O2, SP::O3,
73  SP::O4, SP::O5, SP::O6, SP::O7,
74  SP::L0, SP::L1, SP::L2, SP::L3,
75  SP::L4, SP::L5, SP::L6, SP::L7,
76  SP::I0, SP::I1, SP::I2, SP::I3,
77  SP::I4, SP::I5, SP::I6, SP::I7 };
78 
79 static const unsigned FPRegDecoderTable[] = {
80  SP::F0, SP::F1, SP::F2, SP::F3,
81  SP::F4, SP::F5, SP::F6, SP::F7,
82  SP::F8, SP::F9, SP::F10, SP::F11,
83  SP::F12, SP::F13, SP::F14, SP::F15,
84  SP::F16, SP::F17, SP::F18, SP::F19,
85  SP::F20, SP::F21, SP::F22, SP::F23,
86  SP::F24, SP::F25, SP::F26, SP::F27,
87  SP::F28, SP::F29, SP::F30, SP::F31 };
88 
89 static const unsigned DFPRegDecoderTable[] = {
90  SP::D0, SP::D16, SP::D1, SP::D17,
91  SP::D2, SP::D18, SP::D3, SP::D19,
92  SP::D4, SP::D20, SP::D5, SP::D21,
93  SP::D6, SP::D22, SP::D7, SP::D23,
94  SP::D8, SP::D24, SP::D9, SP::D25,
95  SP::D10, SP::D26, SP::D11, SP::D27,
96  SP::D12, SP::D28, SP::D13, SP::D29,
97  SP::D14, SP::D30, SP::D15, SP::D31 };
98 
99 static const unsigned QFPRegDecoderTable[] = {
100  SP::Q0, SP::Q8, ~0U, ~0U,
101  SP::Q1, SP::Q9, ~0U, ~0U,
102  SP::Q2, SP::Q10, ~0U, ~0U,
103  SP::Q3, SP::Q11, ~0U, ~0U,
104  SP::Q4, SP::Q12, ~0U, ~0U,
105  SP::Q5, SP::Q13, ~0U, ~0U,
106  SP::Q6, SP::Q14, ~0U, ~0U,
107  SP::Q7, SP::Q15, ~0U, ~0U } ;
108 
109 static const unsigned FCCRegDecoderTable[] = {
110  SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
111 
112 static const unsigned ASRRegDecoderTable[] = {
113  SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
114  SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
115  SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
116  SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
117  SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
118  SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
119  SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
120  SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
121 
122 static const unsigned PRRegDecoderTable[] = {
123  SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
124  SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
125  SP::OTHERWIN, SP::WSTATE
126 };
127 
128 static const uint16_t IntPairDecoderTable[] = {
129  SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
130  SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
131  SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
132  SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
133 };
134 
135 static const unsigned CPRegDecoderTable[] = {
136  SP::C0, SP::C1, SP::C2, SP::C3,
137  SP::C4, SP::C5, SP::C6, SP::C7,
138  SP::C8, SP::C9, SP::C10, SP::C11,
139  SP::C12, SP::C13, SP::C14, SP::C15,
140  SP::C16, SP::C17, SP::C18, SP::C19,
141  SP::C20, SP::C21, SP::C22, SP::C23,
142  SP::C24, SP::C25, SP::C26, SP::C27,
143  SP::C28, SP::C29, SP::C30, SP::C31
144 };
145 
146 
147 static const uint16_t CPPairDecoderTable[] = {
148  SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
149  SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
150  SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
151  SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
152 };
153 
155  unsigned RegNo,
156  uint64_t Address,
157  const void *Decoder) {
158  if (RegNo > 31)
159  return MCDisassembler::Fail;
160  unsigned Reg = IntRegDecoderTable[RegNo];
161  Inst.addOperand(MCOperand::createReg(Reg));
163 }
164 
166  unsigned RegNo,
167  uint64_t Address,
168  const void *Decoder) {
169  if (RegNo > 31)
170  return MCDisassembler::Fail;
171  unsigned Reg = IntRegDecoderTable[RegNo];
172  Inst.addOperand(MCOperand::createReg(Reg));
174 }
175 
176 
178  unsigned RegNo,
179  uint64_t Address,
180  const void *Decoder) {
181  if (RegNo > 31)
182  return MCDisassembler::Fail;
183  unsigned Reg = FPRegDecoderTable[RegNo];
184  Inst.addOperand(MCOperand::createReg(Reg));
186 }
187 
188 
190  unsigned RegNo,
191  uint64_t Address,
192  const void *Decoder) {
193  if (RegNo > 31)
194  return MCDisassembler::Fail;
195  unsigned Reg = DFPRegDecoderTable[RegNo];
196  Inst.addOperand(MCOperand::createReg(Reg));
198 }
199 
200 
202  unsigned RegNo,
203  uint64_t Address,
204  const void *Decoder) {
205  if (RegNo > 31)
206  return MCDisassembler::Fail;
207 
208  unsigned Reg = QFPRegDecoderTable[RegNo];
209  if (Reg == ~0U)
210  return MCDisassembler::Fail;
211  Inst.addOperand(MCOperand::createReg(Reg));
213 }
214 
216  unsigned RegNo,
217  uint64_t Address,
218  const void *Decoder) {
219  if (RegNo > 31)
220  return MCDisassembler::Fail;
221  unsigned Reg = CPRegDecoderTable[RegNo];
222  Inst.addOperand(MCOperand::createReg(Reg));
224 }
225 
226 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
227  uint64_t Address,
228  const void *Decoder) {
229  if (RegNo > 3)
230  return MCDisassembler::Fail;
233 }
234 
235 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
236  uint64_t Address,
237  const void *Decoder) {
238  if (RegNo > 31)
239  return MCDisassembler::Fail;
242 }
243 
244 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
245  uint64_t Address,
246  const void *Decoder) {
247  if (RegNo >= array_lengthof(PRRegDecoderTable))
248  return MCDisassembler::Fail;
251 }
252 
253 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
254  uint64_t Address, const void *Decoder) {
256 
257  if (RegNo > 31)
258  return MCDisassembler::Fail;
259 
260  if ((RegNo & 1))
262 
263  unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
264  Inst.addOperand(MCOperand::createReg(RegisterPair));
265  return S;
266 }
267 
268 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
269  uint64_t Address, const void *Decoder) {
270  if (RegNo > 31)
271  return MCDisassembler::Fail;
272 
273  unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
274  Inst.addOperand(MCOperand::createReg(RegisterPair));
276 }
277 
278 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
279  const void *Decoder);
280 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
281  const void *Decoder);
282 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
283  const void *Decoder);
284 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
285  const void *Decoder);
286 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
287  const void *Decoder);
288 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
289  const void *Decoder);
290 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
291  const void *Decoder);
292 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
293  uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
295  uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
297  uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
299  uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
301  uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
303  uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
305  uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
307  uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
309  uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
311  const void *Decoder);
312 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
313  const void *Decoder);
314 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
315  const void *Decoder);
316 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
317  const void *Decoder);
318 
319 #include "SparcGenDisassemblerTables.inc"
320 
321 /// Read four bytes from the ArrayRef and return 32 bit word.
323  uint64_t &Size, uint32_t &Insn,
324  bool IsLittleEndian) {
325  // We want to read exactly 4 Bytes of data.
326  if (Bytes.size() < 4) {
327  Size = 0;
328  return MCDisassembler::Fail;
329  }
330 
331  Insn = IsLittleEndian
332  ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
333  (Bytes[3] << 24)
334  : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
335  (Bytes[0] << 24);
336 
338 }
339 
340 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
341  ArrayRef<uint8_t> Bytes,
342  uint64_t Address,
343  raw_ostream &VStream,
344  raw_ostream &CStream) const {
345  uint32_t Insn;
346  bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
347  DecodeStatus Result =
348  readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
349  if (Result == MCDisassembler::Fail)
350  return MCDisassembler::Fail;
351 
352  // Calling the auto-generated decoder function.
353 
354  if (STI.getFeatureBits()[Sparc::FeatureV9])
355  {
356  Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
357  }
358  else
359  {
360  Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
361  }
362  if (Result != MCDisassembler::Fail)
363  return Result;
364 
365  Result =
366  decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
367 
368  if (Result != MCDisassembler::Fail) {
369  Size = 4;
370  return Result;
371  }
372 
373  return MCDisassembler::Fail;
374 }
375 
376 
377 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
378  const void *Decoder);
379 
380 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
381  const void *Decoder,
382  bool isLoad, DecodeFunc DecodeRD) {
383  unsigned rd = fieldFromInstruction(insn, 25, 5);
384  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
385  bool isImm = fieldFromInstruction(insn, 13, 1);
386  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
387  unsigned asi = fieldFromInstruction(insn, 5, 8);
388  unsigned rs2 = 0;
389  unsigned simm13 = 0;
390  if (isImm)
391  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
392  else
393  rs2 = fieldFromInstruction(insn, 0, 5);
394 
396  if (isLoad) {
397  status = DecodeRD(MI, rd, Address, Decoder);
398  if (status != MCDisassembler::Success)
399  return status;
400  }
401 
402  // Decode rs1.
403  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
404  if (status != MCDisassembler::Success)
405  return status;
406 
407  // Decode imm|rs2.
408  if (isImm)
409  MI.addOperand(MCOperand::createImm(simm13));
410  else {
411  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
412  if (status != MCDisassembler::Success)
413  return status;
414  }
415 
416  if (hasAsi)
418 
419  if (!isLoad) {
420  status = DecodeRD(MI, rd, Address, Decoder);
421  if (status != MCDisassembler::Success)
422  return status;
423  }
425 }
426 
427 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
428  const void *Decoder) {
429  return DecodeMem(Inst, insn, Address, Decoder, true,
431 }
432 
433 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
434  const void *Decoder) {
435  return DecodeMem(Inst, insn, Address, Decoder, true,
437 }
438 
439 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
440  const void *Decoder) {
441  return DecodeMem(Inst, insn, Address, Decoder, true,
443 }
444 
445 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
446  const void *Decoder) {
447  return DecodeMem(Inst, insn, Address, Decoder, true,
449 }
450 
451 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
452  const void *Decoder) {
453  return DecodeMem(Inst, insn, Address, Decoder, true,
455 }
456 
457 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
458  const void *Decoder) {
459  return DecodeMem(Inst, insn, Address, Decoder, true,
461 }
462 
463 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
464  const void *Decoder) {
465  return DecodeMem(Inst, insn, Address, Decoder, true,
467 }
468 
469 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
470  uint64_t Address, const void *Decoder) {
471  return DecodeMem(Inst, insn, Address, Decoder, false,
473 }
474 
475 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
476  uint64_t Address, const void *Decoder) {
477  return DecodeMem(Inst, insn, Address, Decoder, false,
479 }
480 
481 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
482  const void *Decoder) {
483  return DecodeMem(Inst, insn, Address, Decoder, false,
485 }
486 
487 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
488  uint64_t Address, const void *Decoder) {
489  return DecodeMem(Inst, insn, Address, Decoder, false,
491 }
492 
493 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
494  uint64_t Address, const void *Decoder) {
495  return DecodeMem(Inst, insn, Address, Decoder, false,
497 }
498 
499 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
500  uint64_t Address, const void *Decoder) {
501  return DecodeMem(Inst, insn, Address, Decoder, false,
503 }
504 
505 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
506  uint64_t Address, const void *Decoder) {
507  return DecodeMem(Inst, insn, Address, Decoder, false,
509 }
510 
511 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
512  uint64_t Address, uint64_t Offset,
513  uint64_t Width, MCInst &MI,
514  const void *Decoder) {
515  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
516  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
517  Offset, Width);
518 }
519 
520 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
521  uint64_t Address, const void *Decoder) {
522  unsigned tgt = fieldFromInstruction(insn, 0, 30);
523  tgt <<= 2;
524  if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
525  0, 30, MI, Decoder))
528 }
529 
530 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
531  uint64_t Address, const void *Decoder) {
532  unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
535 }
536 
537 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
538  const void *Decoder) {
539 
540  unsigned rd = fieldFromInstruction(insn, 25, 5);
541  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
542  unsigned isImm = fieldFromInstruction(insn, 13, 1);
543  unsigned rs2 = 0;
544  unsigned simm13 = 0;
545  if (isImm)
546  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
547  else
548  rs2 = fieldFromInstruction(insn, 0, 5);
549 
550  // Decode RD.
551  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
552  if (status != MCDisassembler::Success)
553  return status;
554 
555  // Decode RS1.
556  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
557  if (status != MCDisassembler::Success)
558  return status;
559 
560  // Decode RS1 | SIMM13.
561  if (isImm)
562  MI.addOperand(MCOperand::createImm(simm13));
563  else {
564  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
565  if (status != MCDisassembler::Success)
566  return status;
567  }
569 }
570 
571 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
572  const void *Decoder) {
573 
574  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
575  unsigned isImm = fieldFromInstruction(insn, 13, 1);
576  unsigned rs2 = 0;
577  unsigned simm13 = 0;
578  if (isImm)
579  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
580  else
581  rs2 = fieldFromInstruction(insn, 0, 5);
582 
583  // Decode RS1.
584  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
585  if (status != MCDisassembler::Success)
586  return status;
587 
588  // Decode RS2 | SIMM13.
589  if (isImm)
590  MI.addOperand(MCOperand::createImm(simm13));
591  else {
592  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
593  if (status != MCDisassembler::Success)
594  return status;
595  }
597 }
598 
599 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
600  const void *Decoder) {
601 
602  unsigned rd = fieldFromInstruction(insn, 25, 5);
603  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
604  unsigned isImm = fieldFromInstruction(insn, 13, 1);
605  bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
606  unsigned asi = fieldFromInstruction(insn, 5, 8);
607  unsigned rs2 = 0;
608  unsigned simm13 = 0;
609  if (isImm)
610  simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
611  else
612  rs2 = fieldFromInstruction(insn, 0, 5);
613 
614  // Decode RD.
615  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
616  if (status != MCDisassembler::Success)
617  return status;
618 
619  // Decode RS1.
620  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
621  if (status != MCDisassembler::Success)
622  return status;
623 
624  // Decode RS1 | SIMM13.
625  if (isImm)
626  MI.addOperand(MCOperand::createImm(simm13));
627  else {
628  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
629  if (status != MCDisassembler::Success)
630  return status;
631  }
632 
633  if (hasAsi)
635 
637 }
638 
639 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
640  const void *Decoder) {
641 
642  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
643  unsigned isImm = fieldFromInstruction(insn, 13, 1);
644  unsigned cc =fieldFromInstruction(insn, 25, 4);
645  unsigned rs2 = 0;
646  unsigned imm7 = 0;
647  if (isImm)
648  imm7 = fieldFromInstruction(insn, 0, 7);
649  else
650  rs2 = fieldFromInstruction(insn, 0, 5);
651 
652  // Decode RS1.
653  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
654  if (status != MCDisassembler::Success)
655  return status;
656 
657  // Decode RS1 | IMM7.
658  if (isImm)
660  else {
661  status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
662  if (status != MCDisassembler::Success)
663  return status;
664  }
665 
666  // Decode CC
668 
670 }
static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder, bool isLoad, DecodeFunc DecodeRD)
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static const uint16_t IntPairDecoderTable[]
static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
DecodeStatus(* DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static const uint16_t CPPairDecoderTable[]
Reg
All possible values of the reg field in the ModR/M byte.
static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
Context object for machine code objects.
Definition: MCContext.h:51
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
void LLVMInitializeSparcDisassembler()
Target & getTheSparcTarget()
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsLittleEndian)
Read four bytes from the ArrayRef and return 32 bit word.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
TracePC TPC
static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheSparcelTarget()
static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
uint32_t Offset
static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static const unsigned FCCRegDecoderTable[]
static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder)
static const unsigned IntRegDecoderTable[]
static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static const unsigned FPRegDecoderTable[]
static const unsigned CPRegDecoderTable[]
static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned ASRRegDecoderTable[]
static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static const unsigned DFPRegDecoderTable[]
Target - Wrapper for Target specific information.
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheSparcV9Target()
static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder)
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder)
static const unsigned QFPRegDecoderTable[]
MCSubtargetInfo - Generic base class for all target subtargets.
static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const unsigned PRRegDecoderTable[]
static bool isBranch(unsigned Opcode)
LLVM Value Representation.
Definition: Value.h:71
static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createSparcDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
isLittleEndian(LE)
std::error_code status(const Twine &path, file_status &result)
Get file status as if by POSIX stat().
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117