29 cl::desc(
"Use old-style Thumb2 if-conversion heuristics"),
74 while (Count && MBBI != E) {
75 if (MBBI->isDebugValue()) {
79 if (MBBI->getOpcode() == ARM::t2IT) {
80 unsigned Mask = MBBI->getOperand(1).getImm();
82 MBBI->eraseFromParent();
84 unsigned MaskOn = 1 << Count;
85 unsigned MaskOff = ~(MaskOn - 1);
86 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
102 while (MBBI->isDebugValue()) {
104 if (MBBI == MBB.
end())
108 unsigned PredReg = 0;
114 const DebugLoc &DL,
unsigned DestReg,
115 unsigned SrcReg,
bool KillSrc)
const {
117 if (!ARM::GPRRegClass.
contains(DestReg, SrcReg))
126 unsigned SrcReg,
bool isKill,
int FI,
130 if (I != MBB.
end()) DL = I->getDebugLoc();
138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
140 RC == &ARM::GPRnopcRegClass) {
143 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
158 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
169 unsigned DestReg,
int FI,
178 if (I != MBB.
end()) DL = I->getDebugLoc();
180 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
181 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
182 RC == &ARM::GPRnopcRegClass) {
184 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
188 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
195 &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
212 void Thumb2InstrInfo::expandLoadStackGuard(
223 const DebugLoc &dl,
unsigned DestReg,
224 unsigned BaseReg,
int NumBytes,
228 if (NumBytes == 0 && DestReg != BaseReg) {
229 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
235 bool isSub = NumBytes < 0;
236 if (isSub) NumBytes = -NumBytes;
240 if (DestReg != ARM::SP && DestReg != BaseReg &&
244 if (NumBytes < 65536) {
246 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
250 }
else if ((NumBytes & 0xffff) == 0) {
252 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
261 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
272 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
283 unsigned ThisVal = NumBytes;
285 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
293 bool HasCCOut =
true;
294 if (BaseReg == ARM::SP) {
296 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
297 assert((ThisVal & 3) == 0 &&
"Stack update is not multiple of 4?");
298 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
306 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
313 NumBytes &= ~ThisVal;
315 "Bit extraction didn't work?");
318 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
319 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
322 }
else if (ThisVal < 4096) {
323 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
330 NumBytes &= ~ThisVal;
332 "Bit extraction didn't work?");
340 .
addImm(ThisVal)).setMIFlags(MIFlags);
352 case ARM::t2LDRi12:
return ARM::t2LDRi8;
353 case ARM::t2LDRHi12:
return ARM::t2LDRHi8;
354 case ARM::t2LDRBi12:
return ARM::t2LDRBi8;
355 case ARM::t2LDRSHi12:
return ARM::t2LDRSHi8;
356 case ARM::t2LDRSBi12:
return ARM::t2LDRSBi8;
357 case ARM::t2STRi12:
return ARM::t2STRi8;
358 case ARM::t2STRBi12:
return ARM::t2STRBi8;
359 case ARM::t2STRHi12:
return ARM::t2STRHi8;
360 case ARM::t2PLDi12:
return ARM::t2PLDi8;
384 case ARM::t2LDRi8:
return ARM::t2LDRi12;
385 case ARM::t2LDRHi8:
return ARM::t2LDRHi12;
386 case ARM::t2LDRBi8:
return ARM::t2LDRBi12;
387 case ARM::t2LDRSHi8:
return ARM::t2LDRSHi12;
388 case ARM::t2LDRSBi8:
return ARM::t2LDRSBi12;
389 case ARM::t2STRi8:
return ARM::t2STRi12;
390 case ARM::t2STRBi8:
return ARM::t2STRBi12;
391 case ARM::t2STRHi8:
return ARM::t2STRHi12;
392 case ARM::t2PLDi8:
return ARM::t2PLDi12;
397 case ARM::t2LDRSHi12:
398 case ARM::t2LDRSBi12:
416 case ARM::t2LDRs:
return ARM::t2LDRi12;
417 case ARM::t2LDRHs:
return ARM::t2LDRHi12;
418 case ARM::t2LDRBs:
return ARM::t2LDRBi12;
419 case ARM::t2LDRSHs:
return ARM::t2LDRSHi12;
420 case ARM::t2LDRSBs:
return ARM::t2LDRSBi12;
421 case ARM::t2STRs:
return ARM::t2STRi12;
422 case ARM::t2STRBs:
return ARM::t2STRBi12;
423 case ARM::t2STRHs:
return ARM::t2STRHi12;
424 case ARM::t2PLDs:
return ARM::t2PLDi12;
429 case ARM::t2LDRSHi12:
430 case ARM::t2LDRSBi12:
454 unsigned FrameReg,
int &
Offset,
465 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
471 MI.
setDesc(TII.get(ARM::tMOVr));
481 bool HasCCOut = Opcode != ARM::t2ADDri12;
486 MI.
setDesc(TII.get(ARM::t2SUBri));
488 MI.
setDesc(TII.get(ARM::t2ADDri));
504 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
517 unsigned RotAmt = countLeadingZeros<unsigned>(
Offset);
518 unsigned ThisImmVal = Offset &
ARM_AM::rotr32(0xff000000U, RotAmt);
521 Offset &= ~ThisImmVal;
524 "Bit extraction didn't work?");
538 unsigned NewOpc = Opcode;
541 if (OffsetReg != 0) {
552 unsigned NumBits = 0;
576 Offset += InstrOffs * 4;
577 assert((Offset & (Scale-1)) == 0 &&
"Can't encode this offset!");
587 assert((Offset & 3) == 0 &&
"Can't encode this offset!");
592 if (NewOpc != Opcode)
599 int ImmedOffset = Offset / Scale;
600 unsigned Mask = (1 << NumBits) - 1;
601 if ((
unsigned)Offset <= Mask * Scale) {
607 ImmedOffset |= 1 << NumBits;
609 ImmedOffset = -ImmedOffset;
617 ImmedOffset = ImmedOffset &
Mask;
621 ImmedOffset |= 1 << NumBits;
623 ImmedOffset = -ImmedOffset;
624 if (ImmedOffset == 0)
630 Offset &= ~(Mask*Scale);
633 Offset = (isSub) ? -Offset : Offset;
640 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static unsigned negativeOffsetOpcode(unsigned opcode)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
return AArch64::GPR64RegClass contains(Reg)
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
static unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
static cl::opt< bool > OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, cl::desc("Use old-style Thumb2 if-conversion heuristics"), cl::init(false))
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
A description of a memory reference used in the backend.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
static MCOperand createReg(unsigned Reg)
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
static int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Instances of this class represent a single low-level machine instruction.
unsigned getKillRegState(bool B)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getUnindexedOpcode(unsigned Opc) const override
initializer< Ty > init(const Ty &Val)
unsigned const MachineRegisterInfo * MRI
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static unsigned char getAM5Offset(unsigned AM5Opc)
const MachineOperand & getOperand(unsigned i) const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
bool isPositionIndependent() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Thumb2InstrInfo(const ARMSubtarget &STI)
static unsigned immediateOffsetOpcode(unsigned opcode)
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
The memory access writes data.
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
void setOpcode(unsigned Op)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
AddrMode
ARM Addressing Modes.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static unsigned positiveOffsetOpcode(unsigned opcode)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static AddrOpc getAM5Op(unsigned AM5Opc)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void addOperand(const MCOperand &Op)
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static MCOperand createImm(int64_t Val)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const