LLVM  4.0.0
LiveIntervalAnalysis.h
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1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
17 //
18 //===----------------------------------------------------------------------===//
19 
20 #ifndef LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVALANALYSIS_H
22 
23 #include "llvm/ADT/IndexedMap.h"
24 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/Support/Allocator.h"
33 #include <cmath>
34 
35 namespace llvm {
36 
37 extern cl::opt<bool> UseSegmentSetForPhysRegs;
38 
39  class BitVector;
40  class BlockFrequency;
41  class LiveRangeCalc;
42  class LiveVariables;
43  class MachineDominatorTree;
44  class MachineLoopInfo;
45  class TargetRegisterInfo;
46  class MachineRegisterInfo;
47  class TargetInstrInfo;
48  class TargetRegisterClass;
49  class VirtRegMap;
50  class MachineBlockFrequencyInfo;
51 
53  MachineFunction* MF;
55  const TargetRegisterInfo* TRI;
56  const TargetInstrInfo* TII;
57  AliasAnalysis *AA;
58  SlotIndexes* Indexes;
59  MachineDominatorTree *DomTree;
60  LiveRangeCalc *LRCalc;
61 
62  /// Special pool allocator for VNInfo's (LiveInterval val#).
63  ///
64  VNInfo::Allocator VNInfoAllocator;
65 
66  /// Live interval pointers for all the virtual registers.
68 
69  /// RegMaskSlots - Sorted list of instructions with register mask operands.
70  /// Always use the 'r' slot, RegMasks are normal clobbers, not early
71  /// clobbers.
72  SmallVector<SlotIndex, 8> RegMaskSlots;
73 
74  /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
75  /// pointer to the corresponding register mask. This pointer can be
76  /// recomputed as:
77  ///
78  /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
79  /// unsigned OpNum = findRegMaskOperand(MI);
80  /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
81  ///
82  /// This is kept in a separate vector partly because some standard
83  /// libraries don't support lower_bound() with mixed objects, partly to
84  /// improve locality when searching in RegMaskSlots.
85  /// Also see the comment in LiveInterval::find().
87 
88  /// For each basic block number, keep (begin, size) pairs indexing into the
89  /// RegMaskSlots and RegMaskBits arrays.
90  /// Note that basic block numbers may not be layout contiguous, that's why
91  /// we can't just keep track of the first register mask in each basic
92  /// block.
94 
95  /// Keeps a live range set for each register unit to track fixed physreg
96  /// interference.
97  SmallVector<LiveRange*, 0> RegUnitRanges;
98 
99  public:
100  static char ID; // Pass identification, replacement for typeid
101  LiveIntervals();
102  ~LiveIntervals() override;
103 
104  // Calculate the spill weight to assign to a single instruction.
105  static float getSpillWeight(bool isDef, bool isUse,
106  const MachineBlockFrequencyInfo *MBFI,
107  const MachineInstr &Instr);
108 
110  if (hasInterval(Reg))
111  return *VirtRegIntervals[Reg];
112  else
114  }
115 
116  const LiveInterval &getInterval(unsigned Reg) const {
117  return const_cast<LiveIntervals*>(this)->getInterval(Reg);
118  }
119 
120  bool hasInterval(unsigned Reg) const {
121  return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
122  }
123 
124  // Interval creation.
126  assert(!hasInterval(Reg) && "Interval already exists!");
127  VirtRegIntervals.grow(Reg);
128  VirtRegIntervals[Reg] = createInterval(Reg);
129  return *VirtRegIntervals[Reg];
130  }
131 
134  computeVirtRegInterval(LI);
135  return LI;
136  }
137 
138  // Interval removal.
139  void removeInterval(unsigned Reg) {
140  delete VirtRegIntervals[Reg];
141  VirtRegIntervals[Reg] = nullptr;
142  }
143 
144  /// Given a register and an instruction, adds a live segment from that
145  /// instruction to the end of its MBB.
147  MachineInstr &startInst);
148 
149  /// After removing some uses of a register, shrink its live range to just
150  /// the remaining uses. This method does not compute reaching defs for new
151  /// uses, and it doesn't remove dead defs.
152  /// Dead PHIDef values are marked as unused. New dead machine instructions
153  /// are added to the dead vector. Returns true if the interval may have been
154  /// separated into multiple connected components.
155  bool shrinkToUses(LiveInterval *li,
156  SmallVectorImpl<MachineInstr*> *dead = nullptr);
157 
158  /// Specialized version of
159  /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
160  /// that works on a subregister live range and only looks at uses matching
161  /// the lane mask of the subregister range.
162  /// This may leave the subrange empty which needs to be cleaned up with
163  /// LiveInterval::removeEmptySubranges() afterwards.
164  void shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg);
165 
166  /// Extend the live range @p LR to reach all points in @p Indices. The
167  /// points in the @p Indices array must be jointly dominated by the union
168  /// of the existing defs in @p LR and points in @p Undefs.
169  ///
170  /// PHI-defs are added as needed to maintain SSA form.
171  ///
172  /// If a SlotIndex in @p Indices is the end index of a basic block, @p LR
173  /// will be extended to be live out of the basic block.
174  /// If a SlotIndex in @p Indices is jointy dominated only by points in
175  /// @p Undefs, the live range will not be extended to that point.
176  ///
177  /// See also LiveRangeCalc::extend().
179  ArrayRef<SlotIndex> Undefs);
180 
182  extendToIndices(LR, Indices, /*Undefs=*/{});
183  }
184 
185  /// If @p LR has a live value at @p Kill, prune its live range by removing
186  /// any liveness reachable from Kill. Add live range end points to
187  /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
188  /// value's live range.
189  ///
190  /// Calling pruneValue() and extendToIndices() can be used to reconstruct
191  /// SSA form after adding defs to a virtual register.
193  SmallVectorImpl<SlotIndex> *EndPoints);
194 
196  return Indexes;
197  }
198 
200  return AA;
201  }
202 
203  /// isNotInMIMap - returns true if the specified machine instr has been
204  /// removed or was never entered in the map.
205  bool isNotInMIMap(const MachineInstr &Instr) const {
206  return !Indexes->hasIndex(Instr);
207  }
208 
209  /// Returns the base index of the given instruction.
211  return Indexes->getInstructionIndex(Instr);
212  }
213 
214  /// Returns the instruction associated with the given index.
216  return Indexes->getInstructionFromIndex(index);
217  }
218 
219  /// Return the first index in the given basic block.
221  return Indexes->getMBBStartIdx(mbb);
222  }
223 
224  /// Return the last index in the given basic block.
226  return Indexes->getMBBEndIdx(mbb);
227  }
228 
229  bool isLiveInToMBB(const LiveRange &LR,
230  const MachineBasicBlock *mbb) const {
231  return LR.liveAt(getMBBStartIdx(mbb));
232  }
233 
234  bool isLiveOutOfMBB(const LiveRange &LR,
235  const MachineBasicBlock *mbb) const {
236  return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
237  }
238 
240  return Indexes->getMBBFromIndex(index);
241  }
242 
244  Indexes->insertMBBInMaps(MBB);
245  assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
246  "Blocks must be added in order.");
247  RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
248  }
249 
251  return Indexes->insertMachineInstrInMaps(MI);
252  }
253 
256  for (MachineBasicBlock::iterator I = B; I != E; ++I)
257  Indexes->insertMachineInstrInMaps(*I);
258  }
259 
261  Indexes->removeMachineInstrFromMaps(MI);
262  }
263 
265  return Indexes->replaceMachineInstrInMaps(MI, NewMI);
266  }
267 
268  VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
269 
270  void getAnalysisUsage(AnalysisUsage &AU) const override;
271  void releaseMemory() override;
272 
273  /// runOnMachineFunction - pass entry point
274  bool runOnMachineFunction(MachineFunction&) override;
275 
276  /// print - Implement the dump method.
277  void print(raw_ostream &O, const Module* = nullptr) const override;
278 
279  /// intervalIsInOneMBB - If LI is confined to a single basic block, return
280  /// a pointer to that block. If LI is live in to or out of any block,
281  /// return NULL.
283 
284  /// Returns true if VNI is killed by any PHI-def values in LI.
285  /// This may conservatively return true to avoid expensive computations.
286  bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
287 
288  /// addKillFlags - Add kill flags to any instruction that kills a virtual
289  /// register.
290  void addKillFlags(const VirtRegMap*);
291 
292  /// handleMove - call this method to notify LiveIntervals that
293  /// instruction 'mi' has been moved within a basic block. This will update
294  /// the live intervals for all operands of mi. Moves between basic blocks
295  /// are not supported.
296  ///
297  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
298  void handleMove(MachineInstr &MI, bool UpdateFlags = false);
299 
300  /// moveIntoBundle - Update intervals for operands of MI so that they
301  /// begin/end on the SlotIndex for BundleStart.
302  ///
303  /// \param UpdateFlags Update live intervals for nonallocatable physregs.
304  ///
305  /// Requires MI and BundleStart to have SlotIndexes, and assumes
306  /// existing liveness is accurate. BundleStart should be the first
307  /// instruction in the Bundle.
308  void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
309  bool UpdateFlags = false);
310 
311  /// repairIntervalsInRange - Update live intervals for instructions in a
312  /// range of iterators. It is intended for use after target hooks that may
313  /// insert or remove instructions, and is only efficient for a small number
314  /// of instructions.
315  ///
316  /// OrigRegs is a vector of registers that were originally used by the
317  /// instructions in the range between the two iterators.
318  ///
319  /// Currently, the only only changes that are supported are simple removal
320  /// and addition of uses.
324  ArrayRef<unsigned> OrigRegs);
325 
326  // Register mask functions.
327  //
328  // Machine instructions may use a register mask operand to indicate that a
329  // large number of registers are clobbered by the instruction. This is
330  // typically used for calls.
331  //
332  // For compile time performance reasons, these clobbers are not recorded in
333  // the live intervals for individual physical registers. Instead,
334  // LiveIntervalAnalysis maintains a sorted list of instructions with
335  // register mask operands.
336 
337  /// getRegMaskSlots - Returns a sorted array of slot indices of all
338  /// instructions with register mask operands.
339  ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
340 
341  /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
342  /// instructions with register mask operands in the basic block numbered
343  /// MBBNum.
345  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
346  return getRegMaskSlots().slice(P.first, P.second);
347  }
348 
349  /// getRegMaskBits() - Returns an array of register mask pointers
350  /// corresponding to getRegMaskSlots().
351  ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
352 
353  /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
354  /// to getRegMaskSlotsInBlock(MBBNum).
356  std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
357  return getRegMaskBits().slice(P.first, P.second);
358  }
359 
360  /// checkRegMaskInterference - Test if LI is live across any register mask
361  /// instructions, and compute a bit mask of physical registers that are not
362  /// clobbered by any of them.
363  ///
364  /// Returns false if LI doesn't cross any register mask instructions. In
365  /// that case, the bit vector is not filled in.
367  BitVector &UsableRegs);
368 
369  // Register unit functions.
370  //
371  // Fixed interference occurs when MachineInstrs use physregs directly
372  // instead of virtual registers. This typically happens when passing
373  // arguments to a function call, or when instructions require operands in
374  // fixed registers.
375  //
376  // Each physreg has one or more register units, see MCRegisterInfo. We
377  // track liveness per register unit to handle aliasing registers more
378  // efficiently.
379 
380  /// getRegUnit - Return the live range for Unit.
381  /// It will be computed if it doesn't exist.
382  LiveRange &getRegUnit(unsigned Unit) {
383  LiveRange *LR = RegUnitRanges[Unit];
384  if (!LR) {
385  // Compute missing ranges on demand.
386  // Use segment set to speed-up initial computation of the live range.
387  RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
388  computeRegUnitRange(*LR, Unit);
389  }
390  return *LR;
391  }
392 
393  /// getCachedRegUnit - Return the live range for Unit if it has already
394  /// been computed, or NULL if it hasn't been computed yet.
396  return RegUnitRanges[Unit];
397  }
398 
399  const LiveRange *getCachedRegUnit(unsigned Unit) const {
400  return RegUnitRanges[Unit];
401  }
402 
403  /// removeRegUnit - Remove computed live range for Unit. Subsequent uses
404  /// should rely on on-demand recomputation.
405  void removeRegUnit(unsigned Unit) {
406  delete RegUnitRanges[Unit];
407  RegUnitRanges[Unit] = nullptr;
408  }
409 
410  /// Remove value numbers and related live segments starting at position
411  /// @p Pos that are part of any liverange of physical register @p Reg or one
412  /// of its subregisters.
413  void removePhysRegDefAt(unsigned Reg, SlotIndex Pos);
414 
415  /// Remove value number and related live segments of @p LI and its subranges
416  /// that start at position @p Pos.
417  void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
418 
419  /// Split separate components in LiveInterval \p LI into separate intervals.
422 
423  /// For live interval \p LI with correct SubRanges construct matching
424  /// information for the main live range. Expects the main live range to not
425  /// have any segments or value numbers.
427 
428  private:
429  /// Compute live intervals for all virtual registers.
430  void computeVirtRegs();
431 
432  /// Compute RegMaskSlots and RegMaskBits.
433  void computeRegMasks();
434 
435  /// Walk the values in @p LI and check for dead values:
436  /// - Dead PHIDef values are marked as unused.
437  /// - Dead operands are marked as such.
438  /// - Completely dead machine instructions are added to the @p dead vector
439  /// if it is not nullptr.
440  /// Returns true if any PHI value numbers have been removed which may
441  /// have separated the interval into multiple connected components.
442  bool computeDeadValues(LiveInterval &LI,
444 
445  static LiveInterval* createInterval(unsigned Reg);
446 
447  void printInstrs(raw_ostream &O) const;
448  void dumpInstrs() const;
449 
450  void computeLiveInRegUnits();
451  void computeRegUnitRange(LiveRange&, unsigned Unit);
452  void computeVirtRegInterval(LiveInterval&);
453 
454 
455  /// Helper function for repairIntervalsInRange(), walks backwards and
456  /// creates/modifies live segments in @p LR to match the operands found.
457  /// Only full operands or operands with subregisters matching @p LaneMask
458  /// are considered.
459  void repairOldRegInRange(MachineBasicBlock::iterator Begin,
461  const SlotIndex endIdx, LiveRange &LR,
462  unsigned Reg,
463  LaneBitmask LaneMask = LaneBitmask::getAll());
464 
465  class HMEditor;
466  };
467 } // End llvm namespace
468 
469 #endif
void push_back(const T &Elt)
Definition: SmallVector.h:211
ArrayRef< SlotIndex > getRegMaskSlots() const
getRegMaskSlots - Returns a sorted array of slot indices of all instructions with register mask opera...
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices)
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:406
cl::opt< bool > UseSegmentSetForPhysRegs
void RemoveMachineInstrFromMaps(MachineInstr &MI)
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
bool runOnMachineFunction(MachineFunction &) override
runOnMachineFunction - pass entry point
static LaneBitmask getAll()
Definition: LaneBitmask.h:75
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
void removeMachineInstrFromMaps(MachineInstr &MI)
Remove the given machine instruction from the mapping.
Definition: SlotIndexes.h:606
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
A live range for subregisters.
Definition: LiveInterval.h:632
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
void print(raw_ostream &O, const Module *=nullptr) const override
print - Implement the dump method.
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
This file defines the MallocAllocator and BumpPtrAllocator interfaces.
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB...
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill...
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
intervalIsInOneMBB - If LI is confined to a single basic block, return a pointer to that block...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all instructions with register mas...
ArrayRef< const uint32_t * > getRegMaskBits() const
getRegMaskBits() - Returns an array of register mask pointers corresponding to getRegMaskSlots().
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:401
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Reg
All possible values of the reg field in the ModR/M byte.
void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B, MachineBasicBlock::iterator E)
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
void insertMBBInMaps(MachineBasicBlock *MBB)
SlotIndexes pass.
Definition: SlotIndexes.h:323
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
MachineBasicBlock * MBB
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
LiveRange * getCachedRegUnit(unsigned Unit)
getCachedRegUnit - Return the live range for Unit if it has already been computed, or NULL if it hasn't been computed yet.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
TargetInstrInfo - Interface to description of machine instruction set.
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:565
#define P(N)
SlotIndexes * getSlotIndexes() const
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
Definition: SlotIndexes.h:637
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:138
void removeInterval(unsigned Reg)
const LiveRange * getCachedRegUnit(unsigned Unit) const
Represent the analysis usage information of a pass.
static const unsigned End
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< unsigned > OrigRegs)
repairIntervalsInRange - Update live intervals for instructions in a range of iterators.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:376
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:416
void removeRegUnit(unsigned Unit)
removeRegUnit - Remove computed live range for Unit.
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
getRegMaskBitsInBlock - Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBB...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:521
LiveInterval & getInterval(unsigned Reg)
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &Instr)
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:489
LiveInterval & createEmptyInterval(unsigned Reg)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
void addKillFlags(const VirtRegMap *)
addKillFlags - Add kill flags to any instruction that kills a virtual register.
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:479
bool hasInterval(unsigned Reg) const
std::vector< uint8_t > Unit
Definition: FuzzerDefs.h:71
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
AliasAnalysis * getAliasAnalysis() const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
bool isNotInMIMap(const MachineInstr &Instr) const
isNotInMIMap - returns true if the specified machine instr has been removed or was never entered in t...
void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart, bool UpdateFlags=false)
moveIntoBundle - Update intervals for operands of MI so that they begin/end on the SlotIndex for Bund...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
const LiveInterval & getInterval(unsigned Reg) const
IRTranslator LLVM IR MI
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
handleMove - call this method to notify LiveIntervals that instruction 'mi' has been moved within a b...
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...
SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in maps used by register allocat...
Definition: SlotIndexes.h:622