76 for (
unsigned I = 0,
E = ArgLocs.
size();
I !=
E; ++
I) {
116 std::pair<SDValue, SDValue>
119 const SDLoc &dl,
bool doesNotReturn,
120 bool isReturnValueUsed)
const {
122 Args.reserve(Ops.
size());
130 Args.push_back(Entry);
153 const SDLoc &dl)
const {
155 &&
"Unsupported setcc type!");
159 bool ShouldInvertCC =
false;
226 ShouldInvertCC =
true;
254 SDValue Ops[2] = {NewLHS, NewRHS};
341 const APInt &Demanded) {
351 if (!C)
return false;
361 DAG.getConstant(Demanded &
364 return CombineTo(Op, New);
379 const APInt &Demanded,
382 "ShrinkDemandedOp only supports binary operators!");
384 "ShrinkDemandedOp only supports nodes with one result!");
399 unsigned SmallVTBits = DemandedSize;
402 for (; SmallVTBits < BitWidth; SmallVTBits =
NextPowerOf2(SmallVTBits)) {
412 bool NeedZext = DemandedSize > SmallVTBits;
415 return CombineTo(Op, Z);
424 const APInt &Demanded,
428 APInt KnownZero, KnownOne;
443 if (Old.hasOneUse()) {
463 DAG.UpdateNodeOperands(User, NewOps);
481 const APInt &DemandedMask,
486 bool AssumeSingleUse)
const {
489 "Mask size mismatches value type size!");
490 APInt NewMask = DemandedMask;
495 KnownZero = KnownOne =
APInt(BitWidth, 0);
508 }
else if (DemandedMask == 0) {
513 }
else if (Depth == 6) {
517 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
521 KnownOne = cast<ConstantSDNode>(
Op)->getAPIntValue();
522 KnownZero = ~KnownOne;
528 if (!isa<ConstantSDNode>(SrcOp)) {
530 KnownZero = KnownOne =
APInt(BitWidth, 0);
533 KnownOne2 = cast<ConstantSDNode>(SrcOp)->getAPIntValue();
534 KnownZero2 = ~KnownOne2;
540 "Expected BUILD_VECTOR implicit truncation");
541 KnownOne2 = KnownOne2.
trunc(BitWidth);
542 KnownZero2 = KnownZero2.
trunc(BitWidth);
547 KnownOne &= KnownOne2;
548 KnownZero &= KnownZero2;
558 APInt LHSZero, LHSOne;
562 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
576 LHSOne == ~RHSC->getAPIntValue()) {
584 KnownOne, TLO, Depth+1))
586 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
588 KnownZero2, KnownOne2, TLO, Depth+1))
590 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
594 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
596 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
599 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
600 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.
getValueType()));
602 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
605 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
609 KnownOne &= KnownOne2;
611 KnownZero |= KnownZero2;
615 KnownOne, TLO, Depth+1))
617 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
619 KnownZero2, KnownOne2, TLO, Depth+1))
621 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
625 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
627 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
631 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
633 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
636 if (TLO.ShrinkDemandedConstant(Op, NewMask))
639 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
643 KnownZero &= KnownZero2;
645 KnownOne |= KnownOne2;
649 KnownOne, TLO, Depth+1))
651 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
653 KnownOne2, TLO, Depth+1))
655 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
659 if ((KnownZero & NewMask) == NewMask)
661 if ((KnownZero2 & NewMask) == NewMask)
664 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
670 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
676 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
678 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
685 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
686 if (KnownOne == KnownOne2) {
688 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
698 APInt Expanded =
C->getAPIntValue() | (~NewMask);
701 if (Expanded !=
C->getAPIntValue()) {
704 TLO.DAG.getConstant(Expanded, dl, VT));
705 return TLO.CombineTo(Op, New);
709 }
else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
714 KnownZero = KnownZeroOut;
715 KnownOne = KnownOneOut;
719 KnownOne, TLO, Depth+1))
722 KnownOne2, TLO, Depth+1))
724 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
725 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
728 if (TLO.ShrinkDemandedConstant(Op, NewMask))
732 KnownOne &= KnownOne2;
733 KnownZero &= KnownZero2;
737 KnownOne, TLO, Depth+1))
740 KnownOne2, TLO, Depth+1))
742 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
743 assert((KnownZero2 & KnownOne2) == 0 &&
"Bits known to be one AND zero?");
746 if (TLO.ShrinkDemandedConstant(Op, NewMask))
750 KnownOne &= KnownOne2;
751 KnownZero &= KnownZero2;
755 unsigned ShAmt = SA->getZExtValue();
759 if (ShAmt >= BitWidth)
768 unsigned C1= cast<ConstantSDNode>(InOp.
getOperand(1))->getZExtValue();
779 return TLO.CombineTo(Op, TLO.DAG.
getNode(Opc, dl, VT,
785 KnownZero, KnownOne, TLO, Depth+1))
794 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
801 TLO.DAG.getConstant(ShAmt, dl, ShTy));
816 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.
getOperand(1))
818 if (InnerShAmt < ShAmt &&
819 InnerShAmt < InnerBits &&
820 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
821 NewMask.trunc(ShAmt) == 0) {
823 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
834 KnownZero <<= SA->getZExtValue();
835 KnownOne <<= SA->getZExtValue();
843 unsigned ShAmt = SA->getZExtValue();
848 if (ShAmt >= BitWidth)
851 APInt InDemandedMask = (NewMask << ShAmt);
855 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
864 unsigned C1= cast<ConstantSDNode>(InOp.
getOperand(1))->getZExtValue();
874 return TLO.CombineTo(Op, TLO.DAG.
getNode(Opc, dl, VT,
881 KnownZero, KnownOne, TLO, Depth+1))
883 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
884 KnownZero = KnownZero.lshr(ShAmt);
885 KnownOne = KnownOne.lshr(ShAmt);
888 KnownZero |= HighBits;
897 return TLO.CombineTo(Op,
903 unsigned ShAmt = SA->getZExtValue();
906 if (ShAmt >= BitWidth)
909 APInt InDemandedMask = (NewMask << ShAmt);
913 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
923 KnownZero, KnownOne, TLO, Depth+1))
925 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
926 KnownZero = KnownZero.lshr(ShAmt);
927 KnownOne = KnownOne.lshr(ShAmt);
934 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
937 return TLO.CombineTo(Op,
942 int Log2 = NewMask.exactLogBase2();
946 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
952 if (KnownOne.intersects(SignBit))
954 KnownOne |= HighBits;
962 if (MsbMask == NewMask) {
966 bool AlreadySignExtended =
967 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
970 if (!AlreadySignExtended) {
974 if (TLO.LegalTypes() && !ShiftAmtTy.
isVector())
977 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
992 if ((NewBits & NewMask) == 0)
997 APInt InputDemandedBits =
1004 InputDemandedBits |= InSignBit;
1007 KnownZero, KnownOne, TLO, Depth+1))
1009 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
1015 if (KnownZero.intersects(InSignBit))
1016 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(
1019 if (KnownOne.intersects(InSignBit)) {
1020 KnownOne |= NewBits;
1021 KnownZero &= ~NewBits;
1023 KnownZero &= ~NewBits;
1024 KnownOne &= ~NewBits;
1035 APInt KnownZeroLo, KnownOneLo;
1036 APInt KnownZeroHi, KnownOneHi;
1039 KnownOneLo, TLO, Depth + 1))
1043 KnownOneHi, TLO, Depth + 1))
1046 KnownZero = KnownZeroLo.
zext(BitWidth) |
1047 KnownZeroHi.
zext(BitWidth).
shl(HalfBitWidth);
1049 KnownOne = KnownOneLo.
zext(BitWidth) |
1050 KnownOneHi.
zext(BitWidth).
shl(HalfBitWidth);
1055 APInt InMask = NewMask.
trunc(OperandBitWidth);
1066 KnownZero, KnownOne, TLO, Depth+1))
1068 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
1069 KnownZero = KnownZero.zext(BitWidth);
1070 KnownOne = KnownOne.zext(BitWidth);
1071 KnownZero |= NewBits;
1079 APInt NewBits = ~InMask & NewMask;
1089 APInt InDemandedBits = InMask & NewMask;
1090 InDemandedBits |= InSignBit;
1091 InDemandedBits = InDemandedBits.
trunc(InBits);
1094 KnownOne, TLO, Depth+1))
1096 KnownZero = KnownZero.
zext(BitWidth);
1097 KnownOne = KnownOne.
zext(BitWidth);
1100 if (KnownZero.intersects(InSignBit))
1106 if (KnownOne.intersects(InSignBit)) {
1107 KnownOne |= NewBits;
1108 assert((KnownZero & NewBits) == 0);
1110 assert((KnownOne & NewBits) == 0);
1111 assert((KnownZero & NewBits) == 0);
1117 APInt InMask = NewMask.
trunc(OperandBitWidth);
1119 KnownZero, KnownOne, TLO, Depth+1))
1121 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
1122 KnownZero = KnownZero.zext(BitWidth);
1123 KnownOne = KnownOne.zext(BitWidth);
1130 APInt TruncMask = NewMask.
zext(OperandBitWidth);
1132 KnownZero, KnownOne, TLO, Depth+1))
1134 KnownZero = KnownZero.
trunc(BitWidth);
1135 KnownOne = KnownOne.
trunc(BitWidth);
1146 if (TLO.LegalTypes() &&
1155 if (TLO.LegalTypes()) {
1157 Shift = TLO.DAG.getConstant(ShVal, dl,
1162 OperandBitWidth - BitWidth);
1165 if (ShAmt->
getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1180 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
1190 KnownZero, KnownOne, TLO, Depth+1))
1192 assert((KnownZero & KnownOne) == 0 &&
"Bits known to be one AND zero?");
1194 KnownZero |= ~InMask & NewMask;
1200 if (!TLO.LegalOperations() &&
1215 if (!OpVTLegal && OpVTSizeInBits > 32)
1231 BitWidth - NewMask.countLeadingZeros());
1233 KnownOne2, TLO, Depth+1) ||
1235 KnownOne2, TLO, Depth+1) ||
1237 TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) {
1248 return TLO.CombineTo(Op, NewOp);
1256 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1262 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1285 unsigned Depth)
const {
1290 "Should use MaskedValueIsZero if you don't know whether Op"
1291 " is a target node!");
1299 unsigned Depth)
const {
1304 "Should use ComputeNumSignBits if you don't know whether Op"
1305 " is a target node!");
1340 const SDLoc &DL)
const {
1344 ?
APInt(ElementWidth, 1)
1395 DAGCombinerInfo &DCI,
1396 const SDLoc &DL)
const {
1427 if (DCI.isBeforeLegalizeOps() ||
1429 return DAG.
getSetCC(DL, VT, N0, Zero, Cond);
1440 if (YConst && YConst->isNullValue())
1446 return DAG.
getSetCC(DL, VT, NewAnd, Zero, Cond);
1457 const SDLoc &dl)
const {
1478 if (isa<ConstantSDNode>(N0.
getNode()) &&
1481 return DAG.
getSetCC(dl, VT, N1, N0, SwappedCC);
1483 if (
auto *N1C = dyn_cast<ConstantSDNode>(N1.
getNode())) {
1484 const APInt &C1 = N1C->getAPIntValue();
1493 = cast<ConstantSDNode>(N0.
getOperand(1))->getAPIntValue();
1544 MinBits = N0->getOperand(0).getValueSizeInBits();
1546 }
else if (N0->getOpcode() ==
ISD::AND) {
1548 if (
auto *
C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1549 if ((
C->getAPIntValue()+1).isPowerOf2()) {
1550 MinBits =
C->getAPIntValue().countTrailingOnes();
1555 MinBits = N0->getOperand(0).getValueSizeInBits();
1558 }
else if (
auto *LN0 = dyn_cast<LoadSDNode>(N0)) {
1561 MinBits = LN0->getMemoryVT().getSizeInBits();
1565 MinBits = LN0->getMemoryVT().getSizeInBits();
1571 unsigned ReqdBits = Signed ?
1572 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1577 MinBits < C1.getBitWidth() &&
1578 MinBits >= ReqdBits) {
1583 if (MinBits == 1 && C1 == 1)
1588 return DAG.
getSetCC(dl, VT, Trunc, C, Cond);
1615 cast<CondCodeSDNode>(TopSetCC.
getOperand(2))->
get(),
1630 N0.getOpcode() ==
ISD::AND && C1 == 0 &&
1631 N0.getNode()->hasOneUse() &&
1632 isa<LoadSDNode>(N0.getOperand(0)) &&
1633 N0.getOperand(0).getNode()->hasOneUse() &&
1634 isa<ConstantSDNode>(N0.getOperand(1))) {
1635 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1637 unsigned bestWidth = 0, bestOffset = 0;
1639 unsigned origWidth = N0.getValueSizeInBits();
1640 unsigned maskWidth = origWidth;
1646 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1647 for (
unsigned width = origWidth / 2; width>=8; width /= 2) {
1649 for (
unsigned offset=0; offset<origWidth/width; offset++) {
1650 if ((newMask & Mask) == Mask) {
1652 bestOffset = (origWidth/width - offset - 1) * (width/8);
1654 bestOffset = (uint64_t)offset * (width/8);
1655 bestMask = Mask.lshr(offset * (width/8) * 8);
1659 newMask = newMask << width;
1668 if (bestOffset != 0)
1691 C1.getBitWidth() - InSize))) {
1706 return DAG.
getConstant(C1.isNonNegative(), dl, VT);
1720 EVT newVT = N0.getOperand(0).getValueType();
1739 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1741 EVT ExtDstTy = N0.getValueType();
1746 if (C1.getMinSignedBits() > ExtSrcTyBits)
1750 EVT Op0Ty = N0.getOperand(0).getValueType();
1751 if (Op0Ty == ExtSrcTy) {
1761 return DAG.
getSetCC(dl, VT, ZextOp,
1767 }
else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1772 bool TrueWhenTrue = (Cond ==
ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1776 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->
get();
1778 N0.getOperand(0).getValueType().isInteger());
1781 return DAG.
getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1786 N0.getOperand(0).getOpcode() ==
ISD::XOR &&
1787 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1788 isa<ConstantSDNode>(N0.getOperand(1)) &&
1789 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1802 N0.getOperand(0).getOpcode() ==
ISD::XOR);
1805 N0.getOperand(0).getOperand(0),
1809 return DAG.
getSetCC(dl, VT, Val, N1,
1812 }
else if (N1C->getAPIntValue() == 1 &&
1830 cast<ConstantSDNode>(Op0.
getOperand(1))->getAPIntValue() == 1) {
1853 APInt MinVal, MaxVal;
1854 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1865 if (C1 == MinVal)
return DAG.
getConstant(1, dl, VT);
1871 (!N1C->isOpaque() || (N1C->isOpaque() && C.
getBitWidth() <= 64 &&
1880 if (C1 == MaxVal)
return DAG.
getConstant(1, dl, VT);
1886 (!N1C->isOpaque() || (N1C->isOpaque() && C.
getBitWidth() <= 64 &&
1942 (VT == N0.getValueType() ||
1946 if (
auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1952 if (AndRHS->getAPIntValue().isPowerOf2()) {
1955 DAG.
getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1958 }
else if (Cond ==
ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1961 if (C1.isPowerOf2()) {
1971 if (C1.getMinSignedBits() <= 64 &&
1975 N0.getOpcode() ==
ISD::AND && N0.hasOneUse()) {
1976 if (
auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1977 const APInt &AndRHSC = AndRHS->getAPIntValue();
1978 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1984 EVT CmpTy = N0.getValueType();
1989 return DAG.
getSetCC(dl, VT, Shift, CmpRHS, Cond);
2003 ShiftBits = C1.countTrailingOnes();
2007 ShiftBits = C1.countTrailingZeros();
2009 NewC = NewC.
lshr(ShiftBits);
2016 EVT CmpTy = N0.getValueType();
2020 return DAG.
getSetCC(dl, VT, Shift, CmpRHS, NewCond);
2026 if (isa<ConstantFPSDNode>(N0.
getNode())) {
2030 }
else if (
auto *CFP = dyn_cast<ConstantFPSDNode>(N1.
getNode())) {
2033 if (CFP->getValueAPF().isNaN()) {
2051 return DAG.
getSetCC(dl, VT, N0, N0, Cond);
2059 if (CFP->getValueAPF().isInfinity()) {
2060 if (CFP->getValueAPF().isNegative()) {
2119 return DAG.
getSetCC(dl, VT, N0, N1, NewCond);
2145 bool LegalRHSImm =
false;
2147 if (
auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2148 if (
auto *LHSR = dyn_cast<ConstantSDNode>(N0.
getOperand(1))) {
2153 LHSR->getAPIntValue(),
2165 RHSC->getAPIntValue(),
2176 RHSC->getAPIntValue(),
2183 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2240 if (
SDValue V = simplifySetCCWithAnd(VT, N0, N1, Cond, DCI, dl))
2302 if (
auto *GASD = dyn_cast<GlobalAddressSDNode>(N)) {
2303 GA = GASD->getGlobal();
2304 Offset += GASD->getOffset();
2312 if (
auto *V = dyn_cast<ConstantSDNode>(N2)) {
2313 Offset += V->getSExtValue();
2317 if (
auto *V = dyn_cast<ConstantSDNode>(N1)) {
2318 Offset += V->getSExtValue();
2339 unsigned S = Constraint.
size();
2342 switch (Constraint[0]) {
2370 if (S > 1 && Constraint[0] ==
'{' && Constraint[S-1] ==
'}') {
2371 if (S == 8 && Constraint.
substr(1, 6) ==
"memory")
2392 std::string &Constraint,
2393 std::vector<SDValue> &Ops,
2396 if (Constraint.length() > 1)
return;
2398 char ConstraintLetter = Constraint[0];
2399 switch (ConstraintLetter) {
2433 if (ConstraintLetter !=
'n') {
2434 int64_t Offs = GA->getOffset();
2437 C ?
SDLoc(C) : SDLoc(),
2444 if (ConstraintLetter !=
's') {
2458 std::pair<unsigned, const TargetRegisterClass *>
2462 if (Constraint.
empty() || Constraint[0] !=
'{')
2463 return std::make_pair(0u, static_cast<TargetRegisterClass*>(
nullptr));
2464 assert(*(Constraint.
end()-1) ==
'}' &&
"Not a brace enclosed constraint?");
2469 std::pair<unsigned, const TargetRegisterClass*> R =
2470 std::make_pair(0u, static_cast<const TargetRegisterClass*>(
nullptr));
2485 std::pair<unsigned, const TargetRegisterClass*> S =
2486 std::make_pair(*
I, RC);
2508 assert(!ConstraintCode.empty() &&
"No known constraint!");
2509 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2515 assert(!ConstraintCode.empty() &&
"No known constraint!");
2516 return atoi(ConstraintCode.c_str());
2531 unsigned maCount = 0;
2539 ConstraintOperands.emplace_back(std::move(CI));
2549 switch (OpInfo.
Type) {
2565 assert(ResNo == 0 &&
"Asm only has one result!");
2588 if (
StructType *STy = dyn_cast<StructType>(OpTy))
2589 if (STy->getNumElements() == 1)
2590 OpTy = STy->getElementType(0);
2608 }
else if (
PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2618 if (!ConstraintOperands.empty()) {
2620 unsigned bestMAIndex = 0;
2621 int bestWeight = -1;
2627 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2629 for (
unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2630 cIndex != eIndex; ++cIndex) {
2656 weightSum += weight;
2659 if (weightSum > bestWeight) {
2660 bestWeight = weightSum;
2661 bestMAIndex = maIndex;
2666 for (
unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2667 cIndex != eIndex; ++cIndex) {
2677 for (
unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2678 cIndex != eIndex; ++cIndex) {
2689 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2692 std::pair<unsigned, const TargetRegisterClass *> InputRC =
2697 (MatchRC.second != InputRC.second)) {
2699 " with a matching output constraint of"
2700 " incompatible type!");
2706 return ConstraintOperands;
2733 rCodes = &info.
Codes;
2739 for (
unsigned i = 0, e = rCodes->size();
i != e; ++
i) {
2742 if (weight > BestWeight)
2743 BestWeight = weight;
2759 if (!CallOperandVal)
2762 switch (*constraint) {
2765 if (isa<ConstantInt>(CallOperandVal))
2769 if (isa<GlobalValue>(CallOperandVal))
2774 if (isa<ConstantFP>(CallOperandVal))
2821 assert(OpInfo.
Codes.size() > 1 &&
"Doesn't have multiple constraint options");
2822 unsigned BestIdx = 0;
2824 int BestGenerality = -1;
2827 for (
unsigned i = 0, e = OpInfo.
Codes.size();
i != e; ++
i) {
2837 "Unhandled multi-letter 'other' constraint");
2838 std::vector<SDValue> ResultOps;
2841 if (!ResultOps.empty()) {
2855 if (Generality > BestGenerality) {
2858 BestGenerality = Generality;
2871 assert(!OpInfo.
Codes.empty() &&
"Must have at least one constraint");
2874 if (OpInfo.
Codes.size() == 1) {
2887 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2905 std::vector<SDNode *> &Created) {
2906 assert(d != 0 &&
"Division by zero!");
2918 Created.push_back(Op1.
getNode());
2924 while ((t = d*xn) != 1)
2929 Created.push_back(Mul.
getNode());
2935 std::vector<SDNode *> *Created)
const {
2949 std::vector<SDNode *> *Created)
const {
2950 assert(Created &&
"No vector to hold sdiv ops.");
2961 if (cast<BinaryWithFlagsSDNode>(N)->
Flags.hasExact())
2972 DAG.getConstant(magics.
m, dl, VT));
2977 DAG.getConstant(magics.
m, dl, VT)).getNode(), 1);
2983 Created->push_back(Q.
getNode());
2988 Created->push_back(Q.
getNode());
2990 auto &DL = DAG.getDataLayout();
2996 Created->push_back(Q.
getNode());
3003 Created->push_back(T.
getNode());
3004 return DAG.getNode(
ISD::ADD, dl, VT, Q, T);
3013 std::vector<SDNode *> *Created)
const {
3014 assert(Created &&
"No vector to hold udiv ops.");
3033 if (magics.
a != 0 && !Divisor[0]) {
3038 Created->push_back(Q.
getNode());
3042 assert(magics.
a == 0 &&
"Should use cheap fixup now");
3057 Created->push_back(Q.
getNode());
3059 if (magics.
a == 0) {
3061 "We shouldn't generate an undefined shift!");
3067 Created->push_back(NPQ.
getNode());
3071 Created->push_back(NPQ.
getNode());
3073 Created->push_back(NPQ.
getNode());
3083 if (!isa<ConstantSDNode>(Op.
getOperand(0))) {
3085 "be a constant integer");
3114 if (!HasMULHU && !HasMULHS && !HasUMUL_LOHI && !HasSMUL_LOHI)
3129 if ((
Signed && HasSMUL_LOHI) || (!
Signed && HasUMUL_LOHI)) {
3131 Hi =
SDValue(Lo.getNode(), 1);
3157 if (MakeMUL_LOHI(LL, RL, Lo, Hi,
false)) {
3170 RHSSB > InnerBitSize) {
3173 if (MakeMUL_LOHI(LL, RL, Lo, Hi,
true)) {
3180 unsigned ShiftAmount = OuterBitSize - InnerBitSize;
3202 if (!MakeMUL_LOHI(LL, RL, Lo, Hi,
false))
3225 if (!MakeMUL_LOHI(LL, RH, Lo, Hi,
false))
3232 if (!MakeMUL_LOHI(LH, RL, Lo, Hi,
false))
3273 DAG,
Kind, LL, LH, RL, RH);
3325 dl, Exponent, ExponentLoBit,
3366 for (
unsigned Idx = 0; Idx < NumElem; ++Idx) {
3368 DAG.
getExtLoad(ExtType, SL, DstEltVT, Chain, BasePTR,
3415 for (
unsigned Idx = 0; Idx < NumElem; ++Idx) {
3434 std::pair<SDValue, SDValue>
3437 "unaligned indexed loads not implemented!");
3461 return std::make_pair(Result, newLoad.
getValue(1));
3469 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
3485 for (
unsigned i = 1;
i < NumRegs;
i++) {
3503 8 * (LoadedBytes -
Offset));
3523 return std::make_pair(Load, TF);
3527 "Unaligned load of unsupported type.");
3537 unsigned IncrementSize = NumBits / 8;
3552 Hi = DAG.
getExtLoad(HiExtType, dl, VT, Chain, Ptr,
3554 NewLoadedVT,
MinAlign(Alignment, IncrementSize),
3564 NewLoadedVT,
MinAlign(Alignment, IncrementSize),
3578 return std::make_pair(Result, TF);
3584 "unaligned indexed stores not implemented!");
3620 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
3637 for (
unsigned i = 1;
i < NumRegs;
i++) {
3649 StackPtr, StackPtrIncrement);
3657 8 * (StoredBytes -
Offset));
3675 "Unaligned store of unknown type.");
3679 int IncrementSize = NumBits / 8;
3695 EVT PtrVT = Ptr.getValueType();
3698 Alignment =
MinAlign(Alignment, IncrementSize);
3713 bool IsCompressedMemory)
const {
3718 "Incompatible types of Data and Mask");
3719 if (IsCompressedMemory) {
3745 if (isa<ConstantSDNode>(Idx))
3773 "Converting bits to bytes lost precision");
3777 EVT IdxVT = Index.getValueType();
3798 std::string NameString = (
"__emutls_v." + GA->
getGlobal()->
getName()).str();
3802 assert(EmuTlsVar &&
"Cannot find EmuTlsVar ");
3804 Entry.
Ty = VoidPtrType;
3805 Args.push_back(Entry);
3812 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
3821 "Emulated TLS must have zero offset in GlobalAddressSDNode");
3822 return CallResult.first;
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
bool hasNoUnsignedWrap() const
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned char TargetFlags=0)
APInt ashr(unsigned shiftAmt) const
Arithmetic right-shift function.
static MVT getIntegerVT(unsigned BitWidth)
void push_back(const T &Elt)
unsigned Log2_32_Ceil(uint32_t Value)
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is z...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
mu magicu(unsigned LeadingZeros=0) const
Calculate the magic numbers required to implement an unsigned integer division by a constant as a seq...
SDValue getValue(unsigned R) const
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Flags getFlags() const
Return the raw flags of the source value,.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
LLVMContext * getContext() const
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
virtual StringRef getRegAsmName(unsigned Reg) const
Return the assembly name for Reg.
bool hasOneUse() const
Return true if there is exactly one use of this node.
virtual bool hasAndNotCompare(SDValue Y) const
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) !=...
A Module instance is used to store all the information related to an LLVM module. ...
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
const TargetMachine & getTargetMachine() const
bool isCalledByLegalizer() const
SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const
Carry-setting nodes for multiple precision addition and subtraction.
bool isConstTrueVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the true value from getBooleanContents().
bool isKnownToBeAPowerOfTwo(SDValue Val) const
Test if the given value is known to have exactly one bit set.
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
const GlobalValue * getGlobal() const
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d, const SDLoc &dl, SelectionDAG &DAG, std::vector< SDNode * > &Created)
Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the con...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
regclass_iterator regclass_end() const
virtual bool isLegalICmpImmediate(int64_t) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isBitwiseNot(SDValue V)
Returns true if V is a bitwise not operation.
unsigned getNumOperands() const
Return the number of values used by this operation.
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned Num) const
The two locations do not alias at all.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
ms magic() const
Calculate the magic numbers required to implement a signed integer division by a constant as a sequen...
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const
Expand float(f32) to SINT(i64) conversion.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
static bool isCommutativeBinOp(unsigned Opcode)
Returns true if the opcode is a commutative binary operation.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
Type * getElementType() const
SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Turn load of vector type into a load of the individual elements.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
const MCPhysReg * iterator
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal...
const SDValue & getBasePtr() const
CallLoweringInfo & setDiscardResult(bool Value=true)
SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will ...
Magic data for optimising unsigned division by a constant.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
SDValue getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const
Return a constant of type VT that contains a true value that respects getBooleanContents() ...
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
bool isAllOnesValue() const
SDValue getExternalSymbol(const char *Sym, EVT VT)
ConstraintCodeVector Codes
Code - The constraint code, either the register name (in braces) or the constraint letter/number...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
StringRef getName() const
Return a constant reference to the value's name.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
bool isSingleValueType() const
Return true if the type is a valid type for a register in codegen.
bool isNegative() const
Determine sign of this APInt.
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors...
bool isVector() const
isVector - Return true if this is a vector value type.
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
void setNoSignedWrap(bool b)
void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes...
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
This method will be invoked for all target nodes and for any target-independent nodes that the target...
static SDValue clampDynamicVectorIndex(SelectionDAG &DAG, SDValue Idx, EVT VecVT, const SDLoc &dl)
struct fuzzer::@269 Flags
int64_t getOffset() const
Shift and rotation operations.
Class to represent struct types.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
ValTy * getCalledValue() const
getCalledValue - Return the pointer to function that is being called.
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
virtual void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
MachinePointerInfo getWithOffset(int64_t O) const
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const
Increments memory address Addr according to the type of the value DataVT that should be stored...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
bool isPositionIndependent() const
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
Constant fold a setcc to true or false.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
Context object for machine code objects.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
APInt shl(unsigned shiftAmt) const
Left-shift function.
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
unsigned getLocReg() const
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Return true if result of the specified node is used by a return node only.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
static SDNodeIterator begin(const SDNode *N)
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
EK_LabelDifference32 - Each entry is the address of the block minus the address of the jump table...
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
Try to simplify a setcc built with the specified operands and cc.
bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const
Return if N is a True value when extended to VT.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
EK_BlockAddress - Each entry is a plain address of block, e.g.
CallLoweringInfo & setZExtResult(bool Value=true)
bool isLittleEndian() const
Layout endianness...
signed char MatchingInput
MatchingInput - If this is not -1, this is an output constraint where an input constraint is required...
const SDValue & getBasePtr() const
EVT getHalfSizedIntegerVT(LLVMContext &Context) const
getHalfSizedIntegerVT - Finds the smallest simple value type that is greater than or equal to half th...
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
unsigned getMinSignedBits() const
Get the minimum bit size for this signed APInt.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
size_t size() const
size - Get the array size.
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Idx) const
Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base a...
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
bool isLegalRC(const TargetRegisterClass *RC) const
Return true if the value types that can be represented by the specified register class are all legal...
Class to represent pointers.
This class is used to represent ISD::STORE nodes.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
Soften the operands of a comparison.
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
SDNode * getNode() const
get the SDNode which holds the desired result
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators...
unsigned getScalarSizeInBits() const
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isMatchingInputConstraint() const
Return true of this is an input operand that is a matching constraint like "4".
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
unsigned const MachineRegisterInfo * MRI
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
regclass_iterator regclass_begin() const
Register class iterators.
APInt trunc(unsigned width) const
Truncate to new width.
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
C - The default llvm calling convention, compatible with C.
bool isIndirect
isIndirect - True if this operand is an indirect operand.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
int64_t getSExtValue() const
Get sign extended value.
unsigned getMatchedOperand() const
If this is an input matching constraint, this method returns the output operand it matches...
bool isBeforeLegalizeOps() const
Carry-using nodes for multiple precision addition and subtraction.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG)
If there are multiple different constraints that we could pick for this operand (e.g.
unsigned getScalarValueSizeInBits() const
void AddToWorklist(SDNode *N)
SubConstraintInfoVector multipleAlternatives
multipleAlternatives - If there are multiple alternative constraints, this array will contain them...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
uint16_t getParamAlignment(uint16_t i) const
Extract the alignment for a call or parameter (0=unknown).
bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result.
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
bool isPositionIndependent() const
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool CombineTo(SDValue O, SDValue N)
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
unsigned getOpcode() const
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded, DAGCombinerInfo &DCI)
Helper for SimplifyDemandedBits that can simplify an operation with multiple uses.
const SDValue & getValue() const
bool isConstFalseVal(const SDNode *N) const
Return if the N is a constant or constant vector equal to the false value from getBooleanContents().
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
Look at Op.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will ...
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
EVT - Extended Value Type.
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
Type * getType() const
getType - Return the type of the instruction that generated this call site
uint64_t NextPowerOf2(uint64_t A)
NextPowerOf2 - Returns the next power of two (in 64-bits) that is strictly greater than A...
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::string ConstraintCode
This contains the actual string for the code, like "m".
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
const MachinePointerInfo & getPointerInfo() const
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Get the CondCode that's to be used to test the result of the comparison libcall against zero...
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type...
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
std::vector< AsmOperandInfo > AsmOperandInfoVector
TokenFactor - This node takes multiple tokens as input and produces a single token result...
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
std::vector< std::string > ConstraintCodeVector
static void Merge(const std::string &Input, const std::vector< std::string > Result, size_t NumNewFeatures)
void setNoUnsignedWrap(bool b)
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
double Log2(double Value)
Log2 - This function returns the log base 2 of the specified value.
ValTy * getArgument(unsigned ArgNo) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
CCValAssign - Represent assignment of one arg/retval to a location.
GlobalVariable * getNamedGlobal(StringRef Name)
Return the global variable in the module with the specified name, of arbitrary type.
const SDValue & getChain() const
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
bool hasMatchingInput() const
hasMatchingInput - Return true if this is an output constraint that has a matching input constraint...
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static APInt getMinValue(unsigned numBits)
Gets minimum unsigned value of APInt for a specific bit width.
CallLoweringInfo & setSExtResult(bool Value=true)
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset...
bool hasNoSignedWrap() const
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
void setAdjustsStack(bool V)
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
Check whether a given call node is in tail position within its function.
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
AttributeSet getAttributes() const
Return the attribute list for this Function.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
bool isIntegerTy() const
True if this is an instance of IntegerType.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
ANY_EXTEND - Used for integer types. The high bits are undefined.
MulExpansionKind
Enum that specifies when a multiplication should be expanded.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
bool isAllOnesValue() const
Determine if all bits are set.
These are IR-level optimization flags that may be propagated to SDNodes.
Magic data for optimising signed division by a constant.
Bitwise operators - logical and, logical or, logical xor.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
ArrayRef< SDUse > ops() const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
bool paramHasAttr(unsigned i, Attribute::AttrKind Kind) const
Return true if the call or the callee has the given attribute.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT)
Return an integer indicating how general CT is.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getCondCode(ISD::CondCode Cond)
bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, const SDLoc &dl)
Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
TargetLowering(const TargetLowering &)=delete
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
static SDNodeIterator end(const SDNode *N)
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
Examine constraint type and operand type and determine a weight value.
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
const TargetLowering & getTargetLoweringInfo() const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
unsigned countLeadingZeros() const
The APInt version of the countLeadingZeros functions in MathExtras.h.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
APInt zext(unsigned width) const
Zero extend to a new width.
SetCC operator - This evaluates to a true value iff the condition is true.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
EK_GPRel32BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
MVT ConstraintVT
The ValueType for the operand value.
BooleanContent
Enum that describes how the target represents true/false values.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
TRUNCATE - Completely drop the high bits.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
const TargetRegisterClass *const * regclass_iterator
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
const SDNodeFlags * getFlags() const
This could be defined as a virtual function and implemented more simply and directly, but it is not to avoid creating a vtable for this class.
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
ParseConstraints - Split up the constraint string into the specific constraints and their prefixes...
This file describes how to lower LLVM code to machine code.
void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO)
bool isVoidTy() const
Return true if this is 'void'.
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
void selectAlternative(unsigned index)
selectAlternative - Point this constraint to the alternative constraint indicated by the index...
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.