25 cl::desc(
"Use TargetSchedModel for latency lookup"));
28 cl::desc(
"Use InstrItineraryData for latency lookup"));
38 static unsigned gcd(
unsigned Dividend,
unsigned Divisor) {
41 unsigned Rem = Dividend % Divisor;
47 static unsigned lcm(
unsigned A,
unsigned B) {
48 unsigned LCM = (uint64_t(A) *
B) /
gcd(A, B);
49 assert((LCM >= A && LCM >= B) &&
"LCM overflow");
62 ResourceFactors.
resize(NumRes);
64 for (
unsigned Idx = 0; Idx < NumRes; ++Idx) {
67 ResourceLCM =
lcm(ResourceLCM, NumUnits);
69 MicroOpFactor = ResourceLCM / SchedModel.
IssueWidth;
70 for (
unsigned Idx = 0; Idx < NumRes; ++Idx) {
72 ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
96 return Cycles >= 0 ? Cycles : 1000;
114 assert(++NIter < 6 &&
"Variants are nested deeper than the magic number");
129 for (
unsigned i = 0;
i != DefOperIdx; ++
i) {
145 for (
unsigned i = 0;
i != UseOperIdx; ++
i) {
171 if (OperLatency >= 0)
188 unsigned DefIdx =
findDefIdx(DefMI, DefOperIdx);
189 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
202 unsigned UseIdx =
findUseIdx(UseMI, UseOperIdx);
204 if (Advance > 0 && (
unsigned)Advance > Latency)
206 return Latency - Advance;
214 errs() <<
"DefIdx " << DefIdx <<
" exceeds machine model writes for "
215 << *DefMI <<
" (Try with MCSchedModel.CompleteModel set to false)";
229 DefIdx != DefEnd; ++DefIdx) {
238 unsigned TargetSchedModel::computeInstrLatency(
unsigned Opcode)
const {
245 return computeInstrLatency(*SCDesc);
252 bool UseDefaultDefLatency)
const {
262 return computeInstrLatency(*SCDesc);
285 return computeInstrLatency(DefMI);
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
static unsigned lcm(unsigned A, unsigned B)
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class...
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
unsigned short NumMicroOps
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti, const TargetInstrInfo *tii)
Initialize the machine model for instruction scheduling.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
static unsigned gcd(unsigned Dividend, unsigned Divisor)
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
static cl::opt< bool > EnableSchedItins("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup"))
bool isReg() const
isReg - Tests if this is a MO_Register operand.
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
Reg
All possible values of the reg field in the ModR/M byte.
INITIALIZE_PASS(AArch64VectorByElementOpt,"aarch64-vectorbyelement-opt", AARCH64_VECTOR_BY_ELEMENT_OPT_NAME, false, false) bool AArch64VectorByElementOpt unsigned SCIdx
Based only on latency of instructions, determine if it is cost efficient to replace the instruction I...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
unsigned NumReadAdvanceEntries
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getNumProcResourceKinds() const
initializer< Ty > init(const Ty &Val)
unsigned NumWriteLatencyEntries
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
bool isOptionalDef() const
Set if this operand is a optional def.
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
Summarize the scheduling resources required for an instruction of a particular scheduling class...
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Specify the latency in cpu cycles for a particular scheduling class and def index.
MachineOperand class - Representation of each machine instruction operand.
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
CHAIN = SC CHAIN, Imm128 - System call.
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx)
Find the use index of this operand.
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return the number of issue slots required for this MI.
Representation of each machine instruction.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
static cl::opt< bool > EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup"))
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isOutOfOrder() const
Return true if machine supports out of order execution.
const MCOperandInfo * OpInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx)
Find the def index of this operand.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
Machine model for scheduling, bundling, and heuristics.
bool isEmpty() const
Returns true if there are no itineraries.
static unsigned capLatency(int Cycles)
const MCSchedClassDesc * SCDesc