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LLVM
4.0.0
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#include <HexagonRegisterInfo.h>
Definition at line 31 of file HexagonRegisterInfo.h.
| HexagonRegisterInfo::HexagonRegisterInfo | ( | ) |
Definition at line 41 of file HexagonRegisterInfo.cpp.
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Definition at line 159 of file HexagonRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::HexagonSubtarget::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), MI, MRI, Offset, llvm::MachineInstr::RemoveOperand(), and llvm::MachineInstr::setDesc().
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Code Generation virtual methods...
Definition at line 105 of file HexagonRegisterInfo.cpp.
References llvm::HexagonSubtarget::getHexagonArchVersion(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getSubtarget(), llvm_unreachable, R2, llvm::HexagonSubtarget::V4, llvm::HexagonSubtarget::V5, llvm::HexagonSubtarget::V55, and llvm::HexagonSubtarget::V60.
| const MCPhysReg * HexagonRegisterInfo::getCallerSavedRegs | ( | const MachineFunction * | MF, |
| const TargetRegisterClass * | RC | ||
| ) | const |
Definition at line 56 of file HexagonRegisterInfo.cpp.
References llvm::dbgs(), llvm::Empty, llvm::TargetRegisterClass::getID(), llvm_unreachable, R2, R4, R6, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::NVPTX::PTXLdStInstCode::V4.
Referenced by needToReserveScavengingSpillSlots().
| unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg | ( | ) | const |
Definition at line 266 of file HexagonRegisterInfo.cpp.
References R6.
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Definition at line 219 of file HexagonRegisterInfo.cpp.
References getFrameRegister(), getStackRegister(), and llvm::HexagonFrameLowering::hasFP().
Referenced by llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::HexagonPacketizerList::isCallDependent(), and llvm::HexagonTargetLowering::LowerFRAMEADDR().
| unsigned HexagonRegisterInfo::getFrameRegister | ( | ) | const |
Definition at line 228 of file HexagonRegisterInfo.cpp.
Referenced by getFrameRegister().
| unsigned HexagonRegisterInfo::getHexagonSubRegIndex | ( | const TargetRegisterClass * | RC, |
| unsigned | GenIdx | ||
| ) | const |
Definition at line 238 of file HexagonRegisterInfo.cpp.
References assert(), llvm::TargetRegisterClass::getID(), llvm::TargetRegisterClass::getSuperClasses(), llvm_unreachable, llvm::Hexagon::ps_sub_hi, and llvm::Hexagon::ps_sub_lo.
| unsigned HexagonRegisterInfo::getRARegister | ( | ) | const |
Definition at line 214 of file HexagonRegisterInfo.cpp.
Referenced by llvm::HexagonPacketizerList::isCallDependent(), llvm::HexagonTargetLowering::LowerINLINEASM(), and llvm::HexagonTargetLowering::LowerRETURNADDR().
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Definition at line 136 of file HexagonRegisterInfo.cpp.
References PC, and llvm::BitVector::set().
| unsigned HexagonRegisterInfo::getStackRegister | ( | ) | const |
Definition at line 233 of file HexagonRegisterInfo.cpp.
Referenced by getFrameRegister(), llvm::HexagonPacketizerList::isCallDependent(), and llvm::HexagonPacketizerList::isLegalToPacketizeTogether().
Definition at line 50 of file HexagonRegisterInfo.cpp.
Definition at line 45 of file HexagonRegisterInfo.cpp.
References R2.
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Returns true.
Spill code for predicate registers might need an extra register.
Definition at line 53 of file HexagonRegisterInfo.h.
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Returns true since we may need scavenging for a temporary register when generating hardware loop instructions.
Definition at line 47 of file HexagonRegisterInfo.h.
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Definition at line 60 of file HexagonRegisterInfo.h.
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Returns true if the frame pointer is valid.
Definition at line 260 of file HexagonRegisterInfo.cpp.
References llvm::MachineFunction::getSubtarget().
1.8.6