LLVM  4.0.0
LanaiMCCodeEmitter.cpp
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1 //===-- LanaiMCCodeEmitter.cpp - Convert Lanai code to machine code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LanaiMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Lanai.h"
15 #include "LanaiAluCode.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/Support/Casting.h"
30 #include <cassert>
31 #include <cstdint>
32 
33 #define DEBUG_TYPE "mccodeemitter"
34 
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
36 
37 namespace llvm {
38 
39 namespace {
40 
41 class LanaiMCCodeEmitter : public MCCodeEmitter {
42 public:
43  LanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &C) {}
44  LanaiMCCodeEmitter(const LanaiMCCodeEmitter &) = delete;
45  void operator=(const LanaiMCCodeEmitter &) = delete;
46  ~LanaiMCCodeEmitter() override = default;
47 
48  // The functions below are called by TableGen generated functions for getting
49  // the binary encoding of instructions/opereands.
50 
51  // getBinaryCodeForInstr - TableGen'erated function for getting the
52  // binary encoding for an instruction.
53  uint64_t getBinaryCodeForInstr(const MCInst &Inst,
54  SmallVectorImpl<MCFixup> &Fixups,
55  const MCSubtargetInfo &SubtargetInfo) const;
56 
57  // getMachineOpValue - Return binary encoding of operand. If the machine
58  // operand requires relocation, record the relocation and return zero.
59  unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
60  SmallVectorImpl<MCFixup> &Fixups,
61  const MCSubtargetInfo &SubtargetInfo) const;
62 
63  unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
64  SmallVectorImpl<MCFixup> &Fixups,
65  const MCSubtargetInfo &SubtargetInfo) const;
66 
67  unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
68  SmallVectorImpl<MCFixup> &Fixups,
69  const MCSubtargetInfo &SubtargetInfo) const;
70 
71  unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
72  SmallVectorImpl<MCFixup> &Fixups,
73  const MCSubtargetInfo &SubtargetInfo) const;
74 
75  unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
76  SmallVectorImpl<MCFixup> &Fixups,
77  const MCSubtargetInfo &SubtargetInfo) const;
78 
79  void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
80  SmallVectorImpl<MCFixup> &Fixups,
81  const MCSubtargetInfo &SubtargetInfo) const override;
82 
83  unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
84  const MCSubtargetInfo &STI) const;
85 
86  unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
87  const MCSubtargetInfo &STI) const;
88 };
89 
90 } // end anonymous namespace
91 
93  if (isa<MCSymbolRefExpr>(Expr))
94  return Lanai::FIXUP_LANAI_21;
95  if (const LanaiMCExpr *McExpr = dyn_cast<LanaiMCExpr>(Expr)) {
96  LanaiMCExpr::VariantKind ExprKind = McExpr->getKind();
97  switch (ExprKind) {
99  return Lanai::FIXUP_LANAI_21;
104  }
105  }
106  return Lanai::Fixups(0);
107 }
108 
109 // getMachineOpValue - Return binary encoding of operand. If the machine
110 // operand requires relocation, record the relocation and return zero.
111 unsigned LanaiMCCodeEmitter::getMachineOpValue(
112  const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups,
113  const MCSubtargetInfo &SubtargetInfo) const {
114  if (MCOp.isReg())
115  return getLanaiRegisterNumbering(MCOp.getReg());
116  if (MCOp.isImm())
117  return static_cast<unsigned>(MCOp.getImm());
118 
119  // MCOp must be an expression
120  assert(MCOp.isExpr());
121  const MCExpr *Expr = MCOp.getExpr();
122 
123  // Extract the symbolic reference side of a binary expression.
124  if (Expr->getKind() == MCExpr::Binary) {
125  const MCBinaryExpr *BinaryExpr = static_cast<const MCBinaryExpr *>(Expr);
126  Expr = BinaryExpr->getLHS();
127  }
128 
129  assert(isa<LanaiMCExpr>(Expr) || Expr->getKind() == MCExpr::SymbolRef);
130  // Push fixup (all info is contained within)
131  Fixups.push_back(
132  MCFixup::create(0, MCOp.getExpr(), MCFixupKind(FixupKind(Expr))));
133  return 0;
134 }
135 
136 // Helper function to adjust P and Q bits on load and store instructions.
137 unsigned adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift,
138  unsigned QBitShift) {
139  const MCOperand AluOp = Inst.getOperand(3);
140  unsigned AluCode = AluOp.getImm();
141 
142  // Set the P bit to one iff the immediate is nonzero and not a post-op
143  // instruction.
144  const MCOperand Op2 = Inst.getOperand(2);
145  Value &= ~(1 << PBitShift);
146  if (!LPAC::isPostOp(AluCode) &&
147  ((Op2.isImm() && Op2.getImm() != 0) ||
148  (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
149  Value |= (1 << PBitShift);
150 
151  // Set the Q bit to one iff it is a post- or pre-op instruction.
152  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
153  "Expected register operand.");
154  Value &= ~(1 << QBitShift);
155  if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
156  (Op2.isReg() && Op2.getReg() != Lanai::R0)))
157  Value |= (1 << QBitShift);
158 
159  return Value;
160 }
161 
162 unsigned
163 LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
164  const MCSubtargetInfo &STI) const {
165  return adjustPqBits(Inst, Value, 17, 16);
166 }
167 
168 unsigned
169 LanaiMCCodeEmitter::adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
170  const MCSubtargetInfo &STI) const {
171  return adjustPqBits(Inst, Value, 11, 10);
172 }
173 
174 void LanaiMCCodeEmitter::encodeInstruction(
175  const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups,
176  const MCSubtargetInfo &SubtargetInfo) const {
177  // Get instruction encoding and emit it
178  unsigned Value = getBinaryCodeForInstr(Inst, Fixups, SubtargetInfo);
179  ++MCNumEmitted; // Keep track of the number of emitted insns.
180 
181  // Emit bytes in big-endian
182  for (int i = (4 - 1) * 8; i >= 0; i -= 8)
183  Ostream << static_cast<char>((Value >> i) & 0xff);
184 }
185 
186 // Encode Lanai Memory Operand
187 unsigned LanaiMCCodeEmitter::getRiMemoryOpValue(
188  const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
189  const MCSubtargetInfo &SubtargetInfo) const {
190  unsigned Encoding;
191  const MCOperand Op1 = Inst.getOperand(OpNo + 0);
192  const MCOperand Op2 = Inst.getOperand(OpNo + 1);
193  const MCOperand AluOp = Inst.getOperand(OpNo + 2);
194 
195  assert(Op1.isReg() && "First operand is not register.");
196  assert((Op2.isImm() || Op2.isExpr()) &&
197  "Second operand is neither an immediate nor an expression.");
198  assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
199  "Register immediate only supports addition operator");
200 
201  Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18);
202  if (Op2.isImm()) {
203  assert(isInt<16>(Op2.getImm()) &&
204  "Constant value truncated (limited to 16-bit)");
205 
206  Encoding |= (Op2.getImm() & 0xffff);
207  if (Op2.getImm() != 0) {
208  if (LPAC::isPreOp(AluOp.getImm()))
209  Encoding |= (0x3 << 16);
210  if (LPAC::isPostOp(AluOp.getImm()))
211  Encoding |= (0x1 << 16);
212  }
213  } else
214  getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
215 
216  return Encoding;
217 }
218 
219 unsigned LanaiMCCodeEmitter::getRrMemoryOpValue(
220  const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
221  const MCSubtargetInfo &SubtargetInfo) const {
222  unsigned Encoding;
223  const MCOperand Op1 = Inst.getOperand(OpNo + 0);
224  const MCOperand Op2 = Inst.getOperand(OpNo + 1);
225  const MCOperand AluMCOp = Inst.getOperand(OpNo + 2);
226 
227  assert(Op1.isReg() && "First operand is not register.");
228  Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15);
229  assert(Op2.isReg() && "Second operand is not register.");
230  Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);
231 
232  assert(AluMCOp.isImm() && "Third operator is not immediate.");
233  // Set BBB
234  unsigned AluOp = AluMCOp.getImm();
235  Encoding |= LPAC::encodeLanaiAluCode(AluOp) << 5;
236  // Set P and Q
237  if (LPAC::isPreOp(AluOp))
238  Encoding |= (0x3 << 8);
239  if (LPAC::isPostOp(AluOp))
240  Encoding |= (0x1 << 8);
241  // Set JJJJ
242  switch (LPAC::getAluOp(AluOp)) {
243  case LPAC::SHL:
244  case LPAC::SRL:
245  Encoding |= 0x10;
246  break;
247  case LPAC::SRA:
248  Encoding |= 0x18;
249  break;
250  default:
251  break;
252  }
253 
254  return Encoding;
255 }
256 
257 unsigned
258 LanaiMCCodeEmitter::getSplsOpValue(const MCInst &Inst, unsigned OpNo,
259  SmallVectorImpl<MCFixup> &Fixups,
260  const MCSubtargetInfo &SubtargetInfo) const {
261  unsigned Encoding;
262  const MCOperand Op1 = Inst.getOperand(OpNo + 0);
263  const MCOperand Op2 = Inst.getOperand(OpNo + 1);
264  const MCOperand AluOp = Inst.getOperand(OpNo + 2);
265 
266  assert(Op1.isReg() && "First operand is not register.");
267  assert((Op2.isImm() || Op2.isExpr()) &&
268  "Second operand is neither an immediate nor an expression.");
269  assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
270  "Register immediate only supports addition operator");
271 
272  Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12);
273  if (Op2.isImm()) {
274  assert(isInt<10>(Op2.getImm()) &&
275  "Constant value truncated (limited to 10-bit)");
276 
277  Encoding |= (Op2.getImm() & 0x3ff);
278  if (Op2.getImm() != 0) {
279  if (LPAC::isPreOp(AluOp.getImm()))
280  Encoding |= (0x3 << 10);
281  if (LPAC::isPostOp(AluOp.getImm()))
282  Encoding |= (0x1 << 10);
283  }
284  } else
285  getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
286 
287  return Encoding;
288 }
289 
291  const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
292  const MCSubtargetInfo &SubtargetInfo) const {
293  const MCOperand &MCOp = Inst.getOperand(OpNo);
294  if (MCOp.isReg() || MCOp.isImm())
295  return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
296 
297  Fixups.push_back(MCFixup::create(
298  0, MCOp.getExpr(), static_cast<MCFixupKind>(Lanai::FIXUP_LANAI_25)));
299 
300  return 0;
301 }
302 
303 #include "LanaiGenMCCodeEmitter.inc"
304 
305 } // end namespace llvm
306 
309  const MCRegisterInfo & /*MRI*/,
310  MCContext &context) {
311  return new LanaiMCCodeEmitter(InstrInfo, context);
312 }
size_t i
bool isReg() const
Definition: MCInst.h:56
static bool modifiesOp(unsigned AluOp)
Definition: LanaiAluCode.h:73
static unsigned getAluOp(unsigned AluOp)
Definition: LanaiAluCode.h:54
MCCodeEmitter * createLanaiMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
static unsigned getLanaiRegisterNumbering(unsigned Reg)
Definition: LanaiBaseInfo.h:41
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Context object for machine code objects.
Definition: MCContext.h:51
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
static bool isPreOp(unsigned AluOp)
Definition: LanaiAluCode.h:59
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
Lanai::Fixups FixupKind(const MCExpr *Expr)
bool isExpr() const
Definition: MCInst.h:59
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:82
STATISTIC(MCNumEmitted,"Number of MC instructions emitted")
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static bool isPostOp(unsigned AluOp)
Definition: LanaiAluCode.h:61
int64_t getImm() const
Definition: MCInst.h:74
unsigned adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift, unsigned QBitShift)
References to labels and assigned expressions.
Definition: MCExpr.h:39
static unsigned encodeLanaiAluCode(unsigned AluOp)
Definition: LanaiAluCode.h:49
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
Binary expressions.
Definition: MCExpr.h:37
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164