LLVM  4.0.0
ARMExpandPseudoInsts.cpp
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1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "ARM.h"
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
28 #include "llvm/IR/GlobalValue.h"
30 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "arm-pseudo"
36 
37 static cl::opt<bool>
38 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
39  cl::desc("Verify machine code after expanding ARM pseudos"));
40 
41 namespace {
42  class ARMExpandPseudo : public MachineFunctionPass {
43  public:
44  static char ID;
45  ARMExpandPseudo() : MachineFunctionPass(ID) {}
46 
47  const ARMBaseInstrInfo *TII;
48  const TargetRegisterInfo *TRI;
49  const ARMSubtarget *STI;
50  ARMFunctionInfo *AFI;
51 
52  bool runOnMachineFunction(MachineFunction &Fn) override;
53 
54  MachineFunctionProperties getRequiredProperties() const override {
57  }
58 
59  StringRef getPassName() const override {
60  return "ARM pseudo instruction expansion pass";
61  }
62 
63  private:
64  void TransferImpOps(MachineInstr &OldMI,
66  bool ExpandMI(MachineBasicBlock &MBB,
68  MachineBasicBlock::iterator &NextMBBI);
69  bool ExpandMBB(MachineBasicBlock &MBB);
70  void ExpandVLD(MachineBasicBlock::iterator &MBBI);
71  void ExpandVST(MachineBasicBlock::iterator &MBBI);
72  void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
73  void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
74  unsigned Opc, bool IsExt);
75  void ExpandMOV32BitImm(MachineBasicBlock &MBB,
77  bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
78  MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
79  unsigned StrexOp, unsigned UxtOp,
80  MachineBasicBlock::iterator &NextMBBI);
81 
82  bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
84  MachineBasicBlock::iterator &NextMBBI);
85  };
86  char ARMExpandPseudo::ID = 0;
87 }
88 
89 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
90 /// the instructions created from the expansion.
91 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
93  MachineInstrBuilder &DefMI) {
94  const MCInstrDesc &Desc = OldMI.getDesc();
95  for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
96  i != e; ++i) {
97  const MachineOperand &MO = OldMI.getOperand(i);
98  assert(MO.isReg() && MO.getReg());
99  if (MO.isUse())
100  UseMI.addOperand(MO);
101  else
102  DefMI.addOperand(MO);
103  }
104 }
105 
106 namespace {
107  // Constants for register spacing in NEON load/store instructions.
108  // For quad-register load-lane and store-lane pseudo instructors, the
109  // spacing is initially assumed to be EvenDblSpc, and that is changed to
110  // OddDblSpc depending on the lane number operand.
112  SingleSpc,
113  EvenDblSpc,
114  OddDblSpc
115  };
116 
117  // Entries for NEON load/store information table. The table is sorted by
118  // PseudoOpc for fast binary-search lookups.
119  struct NEONLdStTableEntry {
120  uint16_t PseudoOpc;
121  uint16_t RealOpc;
122  bool IsLoad;
123  bool isUpdating;
124  bool hasWritebackOperand;
125  uint8_t RegSpacing; // One of type NEONRegSpacing
126  uint8_t NumRegs; // D registers loaded or stored
127  uint8_t RegElts; // elements per D register; used for lane ops
128  // FIXME: Temporary flag to denote whether the real instruction takes
129  // a single register (like the encoding) or all of the registers in
130  // the list (like the asm syntax and the isel DAG). When all definitions
131  // are converted to take only the single encoded register, this will
132  // go away.
133  bool copyAllListRegs;
134 
135  // Comparison methods for binary search of the table.
136  bool operator<(const NEONLdStTableEntry &TE) const {
137  return PseudoOpc < TE.PseudoOpc;
138  }
139  friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
140  return TE.PseudoOpc < PseudoOpc;
141  }
142  friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
143  const NEONLdStTableEntry &TE) {
144  return PseudoOpc < TE.PseudoOpc;
145  }
146  };
147 }
148 
149 static const NEONLdStTableEntry NEONLdStTable[] = {
150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
155 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
156 
157 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
158 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
159 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
160 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
161 
162 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
163 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
164 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
165 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
166 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
167 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
168 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
169 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
170 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
171 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
172 
173 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
174 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
175 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
176 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
177 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
178 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
179 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
180 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
181 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
182 
183 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
184 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
185 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
186 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
187 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
188 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
189 
190 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
191 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
192 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
193 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
194 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
195 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
196 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
197 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
198 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
199 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
200 
201 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
202 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
203 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
204 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
205 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
206 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
207 
208 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
209 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
210 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
211 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
212 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
213 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
214 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
215 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
216 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
217 
218 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
219 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
220 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
221 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
222 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
223 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
224 
225 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
226 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
227 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
228 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
229 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
230 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
231 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
232 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
233 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
234 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
235 
236 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
237 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
238 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
239 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
240 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
241 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
242 
243 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
244 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
245 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
246 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
247 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
248 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
249 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
250 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
251 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
252 
253 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
254 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
255 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
256 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
257 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
258 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
259 
260 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
261 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
262 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
263 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
264 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
265 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
266 
267 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
268 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
269 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
270 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
271 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
272 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
273 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
274 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
275 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
276 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
277 
278 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
279 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
280 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
281 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
282 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
283 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
284 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
285 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
286 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
287 
288 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
289 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
290 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
291 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
292 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
293 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
294 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
295 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
296 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
297 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
298 
299 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
300 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
301 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
302 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
303 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
304 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
305 
306 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
307 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
308 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
309 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
310 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
311 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
312 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
313 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
314 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
315 
316 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
317 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
318 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
319 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
320 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
321 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
322 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
323 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
324 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
325 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
326 
327 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
328 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
329 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
330 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
331 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
332 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
333 
334 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
335 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
336 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
337 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
338 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
339 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
340 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
341 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
342 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
343 };
344 
345 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
346 /// load or store pseudo instruction.
347 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
348 #ifndef NDEBUG
349  // Make sure the table is sorted.
350  static bool TableChecked = false;
351  if (!TableChecked) {
353  "NEONLdStTable is not sorted!");
354  TableChecked = true;
355  }
356 #endif
357 
358  auto I = std::lower_bound(std::begin(NEONLdStTable),
359  std::end(NEONLdStTable), Opcode);
360  if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
361  return I;
362  return nullptr;
363 }
364 
365 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
366 /// corresponding to the specified register spacing. Not all of the results
367 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
368 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
369  const TargetRegisterInfo *TRI, unsigned &D0,
370  unsigned &D1, unsigned &D2, unsigned &D3) {
371  if (RegSpc == SingleSpc) {
372  D0 = TRI->getSubReg(Reg, ARM::dsub_0);
373  D1 = TRI->getSubReg(Reg, ARM::dsub_1);
374  D2 = TRI->getSubReg(Reg, ARM::dsub_2);
375  D3 = TRI->getSubReg(Reg, ARM::dsub_3);
376  } else if (RegSpc == EvenDblSpc) {
377  D0 = TRI->getSubReg(Reg, ARM::dsub_0);
378  D1 = TRI->getSubReg(Reg, ARM::dsub_2);
379  D2 = TRI->getSubReg(Reg, ARM::dsub_4);
380  D3 = TRI->getSubReg(Reg, ARM::dsub_6);
381  } else {
382  assert(RegSpc == OddDblSpc && "unknown register spacing");
383  D0 = TRI->getSubReg(Reg, ARM::dsub_1);
384  D1 = TRI->getSubReg(Reg, ARM::dsub_3);
385  D2 = TRI->getSubReg(Reg, ARM::dsub_5);
386  D3 = TRI->getSubReg(Reg, ARM::dsub_7);
387  }
388 }
389 
390 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
391 /// operands to real VLD instructions with D register operands.
392 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
393  MachineInstr &MI = *MBBI;
395 
396  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
397  assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
398  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
399  unsigned NumRegs = TableEntry->NumRegs;
400 
401  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
402  TII->get(TableEntry->RealOpc));
403  unsigned OpIdx = 0;
404 
405  bool DstIsDead = MI.getOperand(OpIdx).isDead();
406  unsigned DstReg = MI.getOperand(OpIdx++).getReg();
407  unsigned D0, D1, D2, D3;
408  GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
409  MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
410  if (NumRegs > 1 && TableEntry->copyAllListRegs)
411  MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
412  if (NumRegs > 2 && TableEntry->copyAllListRegs)
413  MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
414  if (NumRegs > 3 && TableEntry->copyAllListRegs)
415  MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
416 
417  if (TableEntry->isUpdating)
418  MIB.addOperand(MI.getOperand(OpIdx++));
419 
420  // Copy the addrmode6 operands.
421  MIB.addOperand(MI.getOperand(OpIdx++));
422  MIB.addOperand(MI.getOperand(OpIdx++));
423  // Copy the am6offset operand.
424  if (TableEntry->hasWritebackOperand)
425  MIB.addOperand(MI.getOperand(OpIdx++));
426 
427  // For an instruction writing double-spaced subregs, the pseudo instruction
428  // has an extra operand that is a use of the super-register. Record the
429  // operand index and skip over it.
430  unsigned SrcOpIdx = 0;
431  if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
432  SrcOpIdx = OpIdx++;
433 
434  // Copy the predicate operands.
435  MIB.addOperand(MI.getOperand(OpIdx++));
436  MIB.addOperand(MI.getOperand(OpIdx++));
437 
438  // Copy the super-register source operand used for double-spaced subregs over
439  // to the new instruction as an implicit operand.
440  if (SrcOpIdx != 0) {
441  MachineOperand MO = MI.getOperand(SrcOpIdx);
442  MO.setImplicit(true);
443  MIB.addOperand(MO);
444  }
445  // Add an implicit def for the super-register.
446  MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
447  TransferImpOps(MI, MIB, MIB);
448 
449  // Transfer memoperands.
450  MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
451 
452  MI.eraseFromParent();
453 }
454 
455 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
456 /// operands to real VST instructions with D register operands.
457 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
458  MachineInstr &MI = *MBBI;
459  MachineBasicBlock &MBB = *MI.getParent();
460 
461  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
462  assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
463  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
464  unsigned NumRegs = TableEntry->NumRegs;
465 
466  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
467  TII->get(TableEntry->RealOpc));
468  unsigned OpIdx = 0;
469  if (TableEntry->isUpdating)
470  MIB.addOperand(MI.getOperand(OpIdx++));
471 
472  // Copy the addrmode6 operands.
473  MIB.addOperand(MI.getOperand(OpIdx++));
474  MIB.addOperand(MI.getOperand(OpIdx++));
475  // Copy the am6offset operand.
476  if (TableEntry->hasWritebackOperand)
477  MIB.addOperand(MI.getOperand(OpIdx++));
478 
479  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
480  bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
481  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
482  unsigned D0, D1, D2, D3;
483  GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
484  MIB.addReg(D0, getUndefRegState(SrcIsUndef));
485  if (NumRegs > 1 && TableEntry->copyAllListRegs)
486  MIB.addReg(D1, getUndefRegState(SrcIsUndef));
487  if (NumRegs > 2 && TableEntry->copyAllListRegs)
488  MIB.addReg(D2, getUndefRegState(SrcIsUndef));
489  if (NumRegs > 3 && TableEntry->copyAllListRegs)
490  MIB.addReg(D3, getUndefRegState(SrcIsUndef));
491 
492  // Copy the predicate operands.
493  MIB.addOperand(MI.getOperand(OpIdx++));
494  MIB.addOperand(MI.getOperand(OpIdx++));
495 
496  if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
497  MIB->addRegisterKilled(SrcReg, TRI, true);
498  else if (!SrcIsUndef)
499  MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
500  TransferImpOps(MI, MIB, MIB);
501 
502  // Transfer memoperands.
503  MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
504 
505  MI.eraseFromParent();
506 }
507 
508 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
509 /// register operands to real instructions with D register operands.
510 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
511  MachineInstr &MI = *MBBI;
512  MachineBasicBlock &MBB = *MI.getParent();
513 
514  const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
515  assert(TableEntry && "NEONLdStTable lookup failed");
516  NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
517  unsigned NumRegs = TableEntry->NumRegs;
518  unsigned RegElts = TableEntry->RegElts;
519 
520  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
521  TII->get(TableEntry->RealOpc));
522  unsigned OpIdx = 0;
523  // The lane operand is always the 3rd from last operand, before the 2
524  // predicate operands.
525  unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
526 
527  // Adjust the lane and spacing as needed for Q registers.
528  assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
529  if (RegSpc == EvenDblSpc && Lane >= RegElts) {
530  RegSpc = OddDblSpc;
531  Lane -= RegElts;
532  }
533  assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
534 
535  unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
536  unsigned DstReg = 0;
537  bool DstIsDead = false;
538  if (TableEntry->IsLoad) {
539  DstIsDead = MI.getOperand(OpIdx).isDead();
540  DstReg = MI.getOperand(OpIdx++).getReg();
541  GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
542  MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
543  if (NumRegs > 1)
544  MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
545  if (NumRegs > 2)
546  MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
547  if (NumRegs > 3)
548  MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
549  }
550 
551  if (TableEntry->isUpdating)
552  MIB.addOperand(MI.getOperand(OpIdx++));
553 
554  // Copy the addrmode6 operands.
555  MIB.addOperand(MI.getOperand(OpIdx++));
556  MIB.addOperand(MI.getOperand(OpIdx++));
557  // Copy the am6offset operand.
558  if (TableEntry->hasWritebackOperand)
559  MIB.addOperand(MI.getOperand(OpIdx++));
560 
561  // Grab the super-register source.
562  MachineOperand MO = MI.getOperand(OpIdx++);
563  if (!TableEntry->IsLoad)
564  GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
565 
566  // Add the subregs as sources of the new instruction.
567  unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
568  getKillRegState(MO.isKill()));
569  MIB.addReg(D0, SrcFlags);
570  if (NumRegs > 1)
571  MIB.addReg(D1, SrcFlags);
572  if (NumRegs > 2)
573  MIB.addReg(D2, SrcFlags);
574  if (NumRegs > 3)
575  MIB.addReg(D3, SrcFlags);
576 
577  // Add the lane number operand.
578  MIB.addImm(Lane);
579  OpIdx += 1;
580 
581  // Copy the predicate operands.
582  MIB.addOperand(MI.getOperand(OpIdx++));
583  MIB.addOperand(MI.getOperand(OpIdx++));
584 
585  // Copy the super-register source to be an implicit source.
586  MO.setImplicit(true);
587  MIB.addOperand(MO);
588  if (TableEntry->IsLoad)
589  // Add an implicit def for the super-register.
590  MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
591  TransferImpOps(MI, MIB, MIB);
592  // Transfer memoperands.
593  MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
594  MI.eraseFromParent();
595 }
596 
597 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
598 /// register operands to real instructions with D register operands.
599 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
600  unsigned Opc, bool IsExt) {
601  MachineInstr &MI = *MBBI;
602  MachineBasicBlock &MBB = *MI.getParent();
603 
604  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
605  unsigned OpIdx = 0;
606 
607  // Transfer the destination register operand.
608  MIB.addOperand(MI.getOperand(OpIdx++));
609  if (IsExt)
610  MIB.addOperand(MI.getOperand(OpIdx++));
611 
612  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
613  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
614  unsigned D0, D1, D2, D3;
615  GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
616  MIB.addReg(D0);
617 
618  // Copy the other source register operand.
619  MIB.addOperand(MI.getOperand(OpIdx++));
620 
621  // Copy the predicate operands.
622  MIB.addOperand(MI.getOperand(OpIdx++));
623  MIB.addOperand(MI.getOperand(OpIdx++));
624 
625  // Add an implicit kill and use for the super-reg.
626  MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
627  TransferImpOps(MI, MIB, MIB);
628  MI.eraseFromParent();
629 }
630 
631 static bool IsAnAddressOperand(const MachineOperand &MO) {
632  // This check is overly conservative. Unless we are certain that the machine
633  // operand is not a symbol reference, we return that it is a symbol reference.
634  // This is important as the load pair may not be split up Windows.
635  switch (MO.getType()) {
640  return false;
642  return true;
644  return false;
651  return true;
654  return false;
657  return true;
659  return false;
662  llvm_unreachable("should not exist post-isel");
663  }
664  llvm_unreachable("unhandled machine operand type");
665 }
666 
667 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
669  MachineInstr &MI = *MBBI;
670  unsigned Opcode = MI.getOpcode();
671  unsigned PredReg = 0;
672  ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
673  unsigned DstReg = MI.getOperand(0).getReg();
674  bool DstIsDead = MI.getOperand(0).isDead();
675  bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
676  const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
677  bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
678  MachineInstrBuilder LO16, HI16;
679 
680  if (!STI->hasV6T2Ops() &&
681  (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
682  // FIXME Windows CE supports older ARM CPUs
683  assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
684 
685  // Expand into a movi + orr.
686  LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
687  HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
688  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
689  .addReg(DstReg);
690 
691  assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
692  unsigned ImmVal = (unsigned)MO.getImm();
693  unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
694  unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
695  LO16 = LO16.addImm(SOImmValV1);
696  HI16 = HI16.addImm(SOImmValV2);
697  LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
698  HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
699  LO16.addImm(Pred).addReg(PredReg).addReg(0);
700  HI16.addImm(Pred).addReg(PredReg).addReg(0);
701  TransferImpOps(MI, LO16, HI16);
702  MI.eraseFromParent();
703  return;
704  }
705 
706  unsigned LO16Opc = 0;
707  unsigned HI16Opc = 0;
708  if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
709  LO16Opc = ARM::t2MOVi16;
710  HI16Opc = ARM::t2MOVTi16;
711  } else {
712  LO16Opc = ARM::MOVi16;
713  HI16Opc = ARM::MOVTi16;
714  }
715 
716  LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
717  HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
718  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
719  .addReg(DstReg);
720 
721  switch (MO.getType()) {
723  unsigned Imm = MO.getImm();
724  unsigned Lo16 = Imm & 0xffff;
725  unsigned Hi16 = (Imm >> 16) & 0xffff;
726  LO16 = LO16.addImm(Lo16);
727  HI16 = HI16.addImm(Hi16);
728  break;
729  }
731  const char *ES = MO.getSymbolName();
732  unsigned TF = MO.getTargetFlags();
733  LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
734  HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
735  break;
736  }
737  default: {
738  const GlobalValue *GV = MO.getGlobal();
739  unsigned TF = MO.getTargetFlags();
740  LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
741  HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
742  break;
743  }
744  }
745 
746  LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
747  HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
748  LO16.addImm(Pred).addReg(PredReg);
749  HI16.addImm(Pred).addReg(PredReg);
750 
751  if (RequiresBundling)
752  finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
753 
754  TransferImpOps(MI, LO16, HI16);
755  MI.eraseFromParent();
756 }
757 
758 static void addPostLoopLiveIns(MachineBasicBlock *MBB, LivePhysRegs &LiveRegs) {
759  for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
760  MBB->addLiveIn(*I);
761 }
762 
763 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
764 /// possible. This only gets used at -O0 so we don't care about efficiency of the
765 /// generated code.
766 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
768  unsigned LdrexOp, unsigned StrexOp,
769  unsigned UxtOp,
770  MachineBasicBlock::iterator &NextMBBI) {
771  bool IsThumb = STI->isThumb();
772  MachineInstr &MI = *MBBI;
773  DebugLoc DL = MI.getDebugLoc();
774  MachineOperand &Dest = MI.getOperand(0);
775  unsigned StatusReg = MI.getOperand(1).getReg();
776  MachineOperand &Addr = MI.getOperand(2);
777  MachineOperand &Desired = MI.getOperand(3);
778  MachineOperand &New = MI.getOperand(4);
779 
780  LivePhysRegs LiveRegs(&TII->getRegisterInfo());
781  LiveRegs.addLiveOuts(MBB);
782  for (auto I = std::prev(MBB.end()); I != MBBI; --I)
783  LiveRegs.stepBackward(*I);
784 
785  MachineFunction *MF = MBB.getParent();
786  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
787  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
788  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
789 
790  MF->insert(++MBB.getIterator(), LoadCmpBB);
791  MF->insert(++LoadCmpBB->getIterator(), StoreBB);
792  MF->insert(++StoreBB->getIterator(), DoneBB);
793 
794  if (UxtOp) {
795  MachineInstrBuilder MIB =
796  BuildMI(MBB, MBBI, DL, TII->get(UxtOp), Desired.getReg())
797  .addReg(Desired.getReg(), RegState::Kill);
798  if (!IsThumb)
799  MIB.addImm(0);
800  AddDefaultPred(MIB);
801  }
802 
803  // .Lloadcmp:
804  // ldrex rDest, [rAddr]
805  // cmp rDest, rDesired
806  // bne .Ldone
807  LoadCmpBB->addLiveIn(Addr.getReg());
808  LoadCmpBB->addLiveIn(Dest.getReg());
809  LoadCmpBB->addLiveIn(Desired.getReg());
810  addPostLoopLiveIns(LoadCmpBB, LiveRegs);
811 
813  MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
814  MIB.addReg(Addr.getReg());
815  if (LdrexOp == ARM::t2LDREX)
816  MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
817  AddDefaultPred(MIB);
818 
819  unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
820  AddDefaultPred(BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
821  .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
822  .addOperand(Desired));
823  unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
824  BuildMI(LoadCmpBB, DL, TII->get(Bcc))
825  .addMBB(DoneBB)
826  .addImm(ARMCC::NE)
827  .addReg(ARM::CPSR, RegState::Kill);
828  LoadCmpBB->addSuccessor(DoneBB);
829  LoadCmpBB->addSuccessor(StoreBB);
830 
831  // .Lstore:
832  // strex rStatus, rNew, [rAddr]
833  // cmp rStatus, #0
834  // bne .Lloadcmp
835  StoreBB->addLiveIn(Addr.getReg());
836  StoreBB->addLiveIn(New.getReg());
837  addPostLoopLiveIns(StoreBB, LiveRegs);
838 
839 
840  MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg);
841  MIB.addOperand(New);
842  MIB.addOperand(Addr);
843  if (StrexOp == ARM::t2STREX)
844  MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
845  AddDefaultPred(MIB);
846 
847  unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
848  AddDefaultPred(BuildMI(StoreBB, DL, TII->get(CMPri))
849  .addReg(StatusReg, RegState::Kill)
850  .addImm(0));
851  BuildMI(StoreBB, DL, TII->get(Bcc))
852  .addMBB(LoadCmpBB)
853  .addImm(ARMCC::NE)
854  .addReg(ARM::CPSR, RegState::Kill);
855  StoreBB->addSuccessor(LoadCmpBB);
856  StoreBB->addSuccessor(DoneBB);
857 
858  DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
859  DoneBB->transferSuccessors(&MBB);
860  addPostLoopLiveIns(DoneBB, LiveRegs);
861 
862  MBB.addSuccessor(LoadCmpBB);
863 
864  NextMBBI = MBB.end();
865  MI.eraseFromParent();
866  return true;
867 }
868 
869 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
870 /// single GPRPair register), Thumb's take two separate registers so we need to
871 /// extract the subregs from the pair.
873  unsigned Flags, bool IsThumb,
874  const TargetRegisterInfo *TRI) {
875  if (IsThumb) {
876  unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
877  unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
878  MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead()));
879  MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead()));
880  } else
881  MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead()));
882 }
883 
884 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
885 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
887  MachineBasicBlock::iterator &NextMBBI) {
888  bool IsThumb = STI->isThumb();
889  MachineInstr &MI = *MBBI;
890  DebugLoc DL = MI.getDebugLoc();
891  MachineOperand &Dest = MI.getOperand(0);
892  unsigned StatusReg = MI.getOperand(1).getReg();
893  MachineOperand &Addr = MI.getOperand(2);
894  MachineOperand &Desired = MI.getOperand(3);
895  MachineOperand &New = MI.getOperand(4);
896 
897  unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
898  unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
899  unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0);
900  unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1);
901 
902  LivePhysRegs LiveRegs(&TII->getRegisterInfo());
903  LiveRegs.addLiveOuts(MBB);
904  for (auto I = std::prev(MBB.end()); I != MBBI; --I)
905  LiveRegs.stepBackward(*I);
906 
907  MachineFunction *MF = MBB.getParent();
908  auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
909  auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
910  auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
911 
912  MF->insert(++MBB.getIterator(), LoadCmpBB);
913  MF->insert(++LoadCmpBB->getIterator(), StoreBB);
914  MF->insert(++StoreBB->getIterator(), DoneBB);
915 
916  // .Lloadcmp:
917  // ldrexd rDestLo, rDestHi, [rAddr]
918  // cmp rDestLo, rDesiredLo
919  // sbcs rStatus<dead>, rDestHi, rDesiredHi
920  // bne .Ldone
921  LoadCmpBB->addLiveIn(Addr.getReg());
922  LoadCmpBB->addLiveIn(Dest.getReg());
923  LoadCmpBB->addLiveIn(Desired.getReg());
924  addPostLoopLiveIns(LoadCmpBB, LiveRegs);
925 
926  unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
928  MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
929  addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
930  MIB.addReg(Addr.getReg());
931  AddDefaultPred(MIB);
932 
933  unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
934  AddDefaultPred(BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
935  .addReg(DestLo, getKillRegState(Dest.isDead()))
936  .addReg(DesiredLo, getKillRegState(Desired.isDead())));
937 
938  BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
939  .addReg(DestHi, getKillRegState(Dest.isDead()))
940  .addReg(DesiredHi, getKillRegState(Desired.isDead()))
941  .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
942 
943  unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
944  BuildMI(LoadCmpBB, DL, TII->get(Bcc))
945  .addMBB(DoneBB)
946  .addImm(ARMCC::NE)
947  .addReg(ARM::CPSR, RegState::Kill);
948  LoadCmpBB->addSuccessor(DoneBB);
949  LoadCmpBB->addSuccessor(StoreBB);
950 
951  // .Lstore:
952  // strexd rStatus, rNewLo, rNewHi, [rAddr]
953  // cmp rStatus, #0
954  // bne .Lloadcmp
955  StoreBB->addLiveIn(Addr.getReg());
956  StoreBB->addLiveIn(New.getReg());
957  addPostLoopLiveIns(StoreBB, LiveRegs);
958 
959  unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
960  MIB = BuildMI(StoreBB, DL, TII->get(STREXD), StatusReg);
961  addExclusiveRegPair(MIB, New, 0, IsThumb, TRI);
962  MIB.addOperand(Addr);
963  AddDefaultPred(MIB);
964 
965  unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
966  AddDefaultPred(BuildMI(StoreBB, DL, TII->get(CMPri))
967  .addReg(StatusReg, RegState::Kill)
968  .addImm(0));
969  BuildMI(StoreBB, DL, TII->get(Bcc))
970  .addMBB(LoadCmpBB)
971  .addImm(ARMCC::NE)
972  .addReg(ARM::CPSR, RegState::Kill);
973  StoreBB->addSuccessor(LoadCmpBB);
974  StoreBB->addSuccessor(DoneBB);
975 
976  DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
977  DoneBB->transferSuccessors(&MBB);
978  addPostLoopLiveIns(DoneBB, LiveRegs);
979 
980  MBB.addSuccessor(LoadCmpBB);
981 
982  NextMBBI = MBB.end();
983  MI.eraseFromParent();
984  return true;
985 }
986 
987 
988 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
990  MachineBasicBlock::iterator &NextMBBI) {
991  MachineInstr &MI = *MBBI;
992  unsigned Opcode = MI.getOpcode();
993  switch (Opcode) {
994  default:
995  return false;
996 
997  case ARM::TCRETURNdi:
998  case ARM::TCRETURNri: {
1000  assert(MBBI->isReturn() &&
1001  "Can only insert epilog into returning blocks");
1002  unsigned RetOpcode = MBBI->getOpcode();
1003  DebugLoc dl = MBBI->getDebugLoc();
1004  const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1005  MBB.getParent()->getSubtarget().getInstrInfo());
1006 
1007  // Tail call return: adjust the stack pointer and jump to callee.
1008  MBBI = MBB.getLastNonDebugInstr();
1009  MachineOperand &JumpTarget = MBBI->getOperand(0);
1010 
1011  // Jump to label or value in register.
1012  if (RetOpcode == ARM::TCRETURNdi) {
1013  unsigned TCOpcode =
1014  STI->isThumb()
1015  ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1016  : ARM::TAILJMPd;
1017  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1018  if (JumpTarget.isGlobal())
1019  MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1020  JumpTarget.getTargetFlags());
1021  else {
1022  assert(JumpTarget.isSymbol());
1023  MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1024  JumpTarget.getTargetFlags());
1025  }
1026 
1027  // Add the default predicate in Thumb mode.
1028  if (STI->isThumb())
1029  MIB.addImm(ARMCC::AL).addReg(0);
1030  } else if (RetOpcode == ARM::TCRETURNri) {
1031  BuildMI(MBB, MBBI, dl,
1032  TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
1033  .addReg(JumpTarget.getReg(), RegState::Kill);
1034  }
1035 
1036  auto NewMI = std::prev(MBBI);
1037  for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1038  NewMI->addOperand(MBBI->getOperand(i));
1039 
1040  // Delete the pseudo instruction TCRETURN.
1041  MBB.erase(MBBI);
1042  MBBI = NewMI;
1043  return true;
1044  }
1045  case ARM::VMOVScc:
1046  case ARM::VMOVDcc: {
1047  unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1048  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1049  MI.getOperand(1).getReg())
1050  .addOperand(MI.getOperand(2))
1051  .addImm(MI.getOperand(3).getImm()) // 'pred'
1052  .addOperand(MI.getOperand(4));
1053 
1054  MI.eraseFromParent();
1055  return true;
1056  }
1057  case ARM::t2MOVCCr:
1058  case ARM::MOVCCr: {
1059  unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1060  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1061  MI.getOperand(1).getReg())
1062  .addOperand(MI.getOperand(2))
1063  .addImm(MI.getOperand(3).getImm()) // 'pred'
1064  .addOperand(MI.getOperand(4))
1065  .addReg(0); // 's' bit
1066 
1067  MI.eraseFromParent();
1068  return true;
1069  }
1070  case ARM::MOVCCsi: {
1071  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1072  (MI.getOperand(1).getReg()))
1073  .addOperand(MI.getOperand(2))
1074  .addImm(MI.getOperand(3).getImm())
1075  .addImm(MI.getOperand(4).getImm()) // 'pred'
1076  .addOperand(MI.getOperand(5))
1077  .addReg(0); // 's' bit
1078 
1079  MI.eraseFromParent();
1080  return true;
1081  }
1082  case ARM::MOVCCsr: {
1083  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1084  (MI.getOperand(1).getReg()))
1085  .addOperand(MI.getOperand(2))
1086  .addOperand(MI.getOperand(3))
1087  .addImm(MI.getOperand(4).getImm())
1088  .addImm(MI.getOperand(5).getImm()) // 'pred'
1089  .addOperand(MI.getOperand(6))
1090  .addReg(0); // 's' bit
1091 
1092  MI.eraseFromParent();
1093  return true;
1094  }
1095  case ARM::t2MOVCCi16:
1096  case ARM::MOVCCi16: {
1097  unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1098  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1099  MI.getOperand(1).getReg())
1100  .addImm(MI.getOperand(2).getImm())
1101  .addImm(MI.getOperand(3).getImm()) // 'pred'
1102  .addOperand(MI.getOperand(4));
1103  MI.eraseFromParent();
1104  return true;
1105  }
1106  case ARM::t2MOVCCi:
1107  case ARM::MOVCCi: {
1108  unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1109  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1110  MI.getOperand(1).getReg())
1111  .addImm(MI.getOperand(2).getImm())
1112  .addImm(MI.getOperand(3).getImm()) // 'pred'
1113  .addOperand(MI.getOperand(4))
1114  .addReg(0); // 's' bit
1115 
1116  MI.eraseFromParent();
1117  return true;
1118  }
1119  case ARM::t2MVNCCi:
1120  case ARM::MVNCCi: {
1121  unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1122  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1123  MI.getOperand(1).getReg())
1124  .addImm(MI.getOperand(2).getImm())
1125  .addImm(MI.getOperand(3).getImm()) // 'pred'
1126  .addOperand(MI.getOperand(4))
1127  .addReg(0); // 's' bit
1128 
1129  MI.eraseFromParent();
1130  return true;
1131  }
1132  case ARM::t2MOVCClsl:
1133  case ARM::t2MOVCClsr:
1134  case ARM::t2MOVCCasr:
1135  case ARM::t2MOVCCror: {
1136  unsigned NewOpc;
1137  switch (Opcode) {
1138  case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1139  case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1140  case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1141  case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1142  default: llvm_unreachable("unexpeced conditional move");
1143  }
1144  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1145  MI.getOperand(1).getReg())
1146  .addOperand(MI.getOperand(2))
1147  .addImm(MI.getOperand(3).getImm())
1148  .addImm(MI.getOperand(4).getImm()) // 'pred'
1149  .addOperand(MI.getOperand(5))
1150  .addReg(0); // 's' bit
1151  MI.eraseFromParent();
1152  return true;
1153  }
1154  case ARM::Int_eh_sjlj_dispatchsetup: {
1155  MachineFunction &MF = *MI.getParent()->getParent();
1156  const ARMBaseInstrInfo *AII =
1157  static_cast<const ARMBaseInstrInfo*>(TII);
1158  const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1159  // For functions using a base pointer, we rematerialize it (via the frame
1160  // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1161  // for us. Otherwise, expand to nothing.
1162  if (RI.hasBasePointer(MF)) {
1163  int32_t NumBytes = AFI->getFramePtrSpillOffset();
1164  unsigned FramePtr = RI.getFrameRegister(MF);
1165  assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1166  "base pointer without frame pointer?");
1167 
1168  if (AFI->isThumb2Function()) {
1169  emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1170  FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1171  } else if (AFI->isThumbFunction()) {
1173  FramePtr, -NumBytes, *TII, RI);
1174  } else {
1175  emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1176  FramePtr, -NumBytes, ARMCC::AL, 0,
1177  *TII);
1178  }
1179  // If there's dynamic realignment, adjust for it.
1180  if (RI.needsStackRealignment(MF)) {
1181  MachineFrameInfo &MFI = MF.getFrameInfo();
1182  unsigned MaxAlign = MFI.getMaxAlignment();
1183  assert (!AFI->isThumb1OnlyFunction());
1184  // Emit bic r6, r6, MaxAlign
1185  assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1186  "immediates larger than 256 with all lower "
1187  "bits set.");
1188  unsigned bicOpc = AFI->isThumbFunction() ?
1189  ARM::t2BICri : ARM::BICri;
1191  TII->get(bicOpc), ARM::R6)
1192  .addReg(ARM::R6, RegState::Kill)
1193  .addImm(MaxAlign-1)));
1194  }
1195 
1196  }
1197  MI.eraseFromParent();
1198  return true;
1199  }
1200 
1201  case ARM::MOVsrl_flag:
1202  case ARM::MOVsra_flag: {
1203  // These are just fancy MOVs instructions.
1204  AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1205  MI.getOperand(0).getReg())
1206  .addOperand(MI.getOperand(1))
1207  .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ?
1209  1)))
1210  .addReg(ARM::CPSR, RegState::Define);
1211  MI.eraseFromParent();
1212  return true;
1213  }
1214  case ARM::RRX: {
1215  // This encodes as "MOVs Rd, Rm, rrx
1216  MachineInstrBuilder MIB =
1217  AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi),
1218  MI.getOperand(0).getReg())
1219  .addOperand(MI.getOperand(1))
1220  .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0)))
1221  .addReg(0);
1222  TransferImpOps(MI, MIB, MIB);
1223  MI.eraseFromParent();
1224  return true;
1225  }
1226  case ARM::tTPsoft:
1227  case ARM::TPsoft: {
1228  const bool Thumb = Opcode == ARM::tTPsoft;
1229 
1230  MachineInstrBuilder MIB;
1231  if (STI->genLongCalls()) {
1232  MachineFunction *MF = MBB.getParent();
1233  MachineConstantPool *MCP = MF->getConstantPool();
1234  unsigned PCLabelID = AFI->createPICLabelUId();
1237  "__aeabi_read_tp", PCLabelID, 0);
1238  unsigned Reg = MI.getOperand(0).getReg();
1239  MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1240  TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1241  .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1242  if (!Thumb)
1243  MIB.addImm(0);
1244  MIB.addImm(static_cast<unsigned>(ARMCC::AL)).addReg(0);
1245 
1246  MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1247  TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1248  if (Thumb)
1249  MIB.addImm(static_cast<unsigned>(ARMCC::AL)).addReg(0);
1250  MIB.addReg(Reg, RegState::Kill);
1251  } else {
1252  MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1253  TII->get(Thumb ? ARM::tBL : ARM::BL));
1254  if (Thumb)
1255  MIB.addImm(static_cast<unsigned>(ARMCC::AL)).addReg(0);
1256  MIB.addExternalSymbol("__aeabi_read_tp", 0);
1257  }
1258 
1259  MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1260  TransferImpOps(MI, MIB, MIB);
1261  MI.eraseFromParent();
1262  return true;
1263  }
1264  case ARM::tLDRpci_pic:
1265  case ARM::t2LDRpci_pic: {
1266  unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1267  ? ARM::tLDRpci : ARM::t2LDRpci;
1268  unsigned DstReg = MI.getOperand(0).getReg();
1269  bool DstIsDead = MI.getOperand(0).isDead();
1270  MachineInstrBuilder MIB1 =
1271  AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
1272  TII->get(NewLdOpc), DstReg)
1273  .addOperand(MI.getOperand(1)));
1274  MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1275  MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1276  TII->get(ARM::tPICADD))
1277  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1278  .addReg(DstReg)
1279  .addOperand(MI.getOperand(2));
1280  TransferImpOps(MI, MIB1, MIB2);
1281  MI.eraseFromParent();
1282  return true;
1283  }
1284 
1285  case ARM::LDRLIT_ga_abs:
1286  case ARM::LDRLIT_ga_pcrel:
1287  case ARM::LDRLIT_ga_pcrel_ldr:
1288  case ARM::tLDRLIT_ga_abs:
1289  case ARM::tLDRLIT_ga_pcrel: {
1290  unsigned DstReg = MI.getOperand(0).getReg();
1291  bool DstIsDead = MI.getOperand(0).isDead();
1292  const MachineOperand &MO1 = MI.getOperand(1);
1293  const GlobalValue *GV = MO1.getGlobal();
1294  bool IsARM =
1295  Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1296  bool IsPIC =
1297  Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1298  unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1299  unsigned PICAddOpc =
1300  IsARM
1301  ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1302  : ARM::tPICADD;
1303 
1304  // We need a new const-pool entry to load from.
1306  unsigned ARMPCLabelIndex = 0;
1308 
1309  if (IsPIC) {
1310  unsigned PCAdj = IsARM ? 8 : 4;
1311  ARMPCLabelIndex = AFI->createPICLabelUId();
1312  CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
1313  ARMCP::CPValue, PCAdj);
1314  } else
1316 
1317  MachineInstrBuilder MIB =
1318  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1319  .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1320  if (IsARM)
1321  MIB.addImm(0);
1322  AddDefaultPred(MIB);
1323 
1324  if (IsPIC) {
1325  MachineInstrBuilder MIB =
1326  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1327  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1328  .addReg(DstReg)
1329  .addImm(ARMPCLabelIndex);
1330 
1331  if (IsARM)
1332  AddDefaultPred(MIB);
1333  }
1334 
1335  MI.eraseFromParent();
1336  return true;
1337  }
1338  case ARM::MOV_ga_pcrel:
1339  case ARM::MOV_ga_pcrel_ldr:
1340  case ARM::t2MOV_ga_pcrel: {
1341  // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1342  unsigned LabelId = AFI->createPICLabelUId();
1343  unsigned DstReg = MI.getOperand(0).getReg();
1344  bool DstIsDead = MI.getOperand(0).isDead();
1345  const MachineOperand &MO1 = MI.getOperand(1);
1346  const GlobalValue *GV = MO1.getGlobal();
1347  unsigned TF = MO1.getTargetFlags();
1348  bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1349  unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1350  unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1351  unsigned LO16TF = TF | ARMII::MO_LO16;
1352  unsigned HI16TF = TF | ARMII::MO_HI16;
1353  unsigned PICAddOpc = isARM
1354  ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1355  : ARM::tPICADD;
1356  MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1357  TII->get(LO16Opc), DstReg)
1358  .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1359  .addImm(LabelId);
1360 
1361  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1362  .addReg(DstReg)
1363  .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1364  .addImm(LabelId);
1365 
1366  MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1367  TII->get(PICAddOpc))
1368  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1369  .addReg(DstReg).addImm(LabelId);
1370  if (isARM) {
1371  AddDefaultPred(MIB3);
1372  if (Opcode == ARM::MOV_ga_pcrel_ldr)
1373  MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1374  }
1375  TransferImpOps(MI, MIB1, MIB3);
1376  MI.eraseFromParent();
1377  return true;
1378  }
1379 
1380  case ARM::MOVi32imm:
1381  case ARM::MOVCCi32imm:
1382  case ARM::t2MOVi32imm:
1383  case ARM::t2MOVCCi32imm:
1384  ExpandMOV32BitImm(MBB, MBBI);
1385  return true;
1386 
1387  case ARM::SUBS_PC_LR: {
1388  MachineInstrBuilder MIB =
1389  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1390  .addReg(ARM::LR)
1391  .addOperand(MI.getOperand(0))
1392  .addOperand(MI.getOperand(1))
1393  .addOperand(MI.getOperand(2))
1394  .addReg(ARM::CPSR, RegState::Undef);
1395  TransferImpOps(MI, MIB, MIB);
1396  MI.eraseFromParent();
1397  return true;
1398  }
1399  case ARM::VLDMQIA: {
1400  unsigned NewOpc = ARM::VLDMDIA;
1401  MachineInstrBuilder MIB =
1402  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1403  unsigned OpIdx = 0;
1404 
1405  // Grab the Q register destination.
1406  bool DstIsDead = MI.getOperand(OpIdx).isDead();
1407  unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1408 
1409  // Copy the source register.
1410  MIB.addOperand(MI.getOperand(OpIdx++));
1411 
1412  // Copy the predicate operands.
1413  MIB.addOperand(MI.getOperand(OpIdx++));
1414  MIB.addOperand(MI.getOperand(OpIdx++));
1415 
1416  // Add the destination operands (D subregs).
1417  unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1418  unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1419  MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1420  .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1421 
1422  // Add an implicit def for the super-register.
1423  MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1424  TransferImpOps(MI, MIB, MIB);
1426  MI.eraseFromParent();
1427  return true;
1428  }
1429 
1430  case ARM::VSTMQIA: {
1431  unsigned NewOpc = ARM::VSTMDIA;
1432  MachineInstrBuilder MIB =
1433  BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1434  unsigned OpIdx = 0;
1435 
1436  // Grab the Q register source.
1437  bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1438  unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1439 
1440  // Copy the destination register.
1441  MIB.addOperand(MI.getOperand(OpIdx++));
1442 
1443  // Copy the predicate operands.
1444  MIB.addOperand(MI.getOperand(OpIdx++));
1445  MIB.addOperand(MI.getOperand(OpIdx++));
1446 
1447  // Add the source operands (D subregs).
1448  unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1449  unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1450  MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1451  .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1452 
1453  if (SrcIsKill) // Add an implicit kill for the Q register.
1454  MIB->addRegisterKilled(SrcReg, TRI, true);
1455 
1456  TransferImpOps(MI, MIB, MIB);
1458  MI.eraseFromParent();
1459  return true;
1460  }
1461 
1462  case ARM::VLD2q8Pseudo:
1463  case ARM::VLD2q16Pseudo:
1464  case ARM::VLD2q32Pseudo:
1465  case ARM::VLD2q8PseudoWB_fixed:
1466  case ARM::VLD2q16PseudoWB_fixed:
1467  case ARM::VLD2q32PseudoWB_fixed:
1468  case ARM::VLD2q8PseudoWB_register:
1469  case ARM::VLD2q16PseudoWB_register:
1470  case ARM::VLD2q32PseudoWB_register:
1471  case ARM::VLD3d8Pseudo:
1472  case ARM::VLD3d16Pseudo:
1473  case ARM::VLD3d32Pseudo:
1474  case ARM::VLD1d64TPseudo:
1475  case ARM::VLD1d64TPseudoWB_fixed:
1476  case ARM::VLD3d8Pseudo_UPD:
1477  case ARM::VLD3d16Pseudo_UPD:
1478  case ARM::VLD3d32Pseudo_UPD:
1479  case ARM::VLD3q8Pseudo_UPD:
1480  case ARM::VLD3q16Pseudo_UPD:
1481  case ARM::VLD3q32Pseudo_UPD:
1482  case ARM::VLD3q8oddPseudo:
1483  case ARM::VLD3q16oddPseudo:
1484  case ARM::VLD3q32oddPseudo:
1485  case ARM::VLD3q8oddPseudo_UPD:
1486  case ARM::VLD3q16oddPseudo_UPD:
1487  case ARM::VLD3q32oddPseudo_UPD:
1488  case ARM::VLD4d8Pseudo:
1489  case ARM::VLD4d16Pseudo:
1490  case ARM::VLD4d32Pseudo:
1491  case ARM::VLD1d64QPseudo:
1492  case ARM::VLD1d64QPseudoWB_fixed:
1493  case ARM::VLD4d8Pseudo_UPD:
1494  case ARM::VLD4d16Pseudo_UPD:
1495  case ARM::VLD4d32Pseudo_UPD:
1496  case ARM::VLD4q8Pseudo_UPD:
1497  case ARM::VLD4q16Pseudo_UPD:
1498  case ARM::VLD4q32Pseudo_UPD:
1499  case ARM::VLD4q8oddPseudo:
1500  case ARM::VLD4q16oddPseudo:
1501  case ARM::VLD4q32oddPseudo:
1502  case ARM::VLD4q8oddPseudo_UPD:
1503  case ARM::VLD4q16oddPseudo_UPD:
1504  case ARM::VLD4q32oddPseudo_UPD:
1505  case ARM::VLD3DUPd8Pseudo:
1506  case ARM::VLD3DUPd16Pseudo:
1507  case ARM::VLD3DUPd32Pseudo:
1508  case ARM::VLD3DUPd8Pseudo_UPD:
1509  case ARM::VLD3DUPd16Pseudo_UPD:
1510  case ARM::VLD3DUPd32Pseudo_UPD:
1511  case ARM::VLD4DUPd8Pseudo:
1512  case ARM::VLD4DUPd16Pseudo:
1513  case ARM::VLD4DUPd32Pseudo:
1514  case ARM::VLD4DUPd8Pseudo_UPD:
1515  case ARM::VLD4DUPd16Pseudo_UPD:
1516  case ARM::VLD4DUPd32Pseudo_UPD:
1517  ExpandVLD(MBBI);
1518  return true;
1519 
1520  case ARM::VST2q8Pseudo:
1521  case ARM::VST2q16Pseudo:
1522  case ARM::VST2q32Pseudo:
1523  case ARM::VST2q8PseudoWB_fixed:
1524  case ARM::VST2q16PseudoWB_fixed:
1525  case ARM::VST2q32PseudoWB_fixed:
1526  case ARM::VST2q8PseudoWB_register:
1527  case ARM::VST2q16PseudoWB_register:
1528  case ARM::VST2q32PseudoWB_register:
1529  case ARM::VST3d8Pseudo:
1530  case ARM::VST3d16Pseudo:
1531  case ARM::VST3d32Pseudo:
1532  case ARM::VST1d64TPseudo:
1533  case ARM::VST3d8Pseudo_UPD:
1534  case ARM::VST3d16Pseudo_UPD:
1535  case ARM::VST3d32Pseudo_UPD:
1536  case ARM::VST1d64TPseudoWB_fixed:
1537  case ARM::VST1d64TPseudoWB_register:
1538  case ARM::VST3q8Pseudo_UPD:
1539  case ARM::VST3q16Pseudo_UPD:
1540  case ARM::VST3q32Pseudo_UPD:
1541  case ARM::VST3q8oddPseudo:
1542  case ARM::VST3q16oddPseudo:
1543  case ARM::VST3q32oddPseudo:
1544  case ARM::VST3q8oddPseudo_UPD:
1545  case ARM::VST3q16oddPseudo_UPD:
1546  case ARM::VST3q32oddPseudo_UPD:
1547  case ARM::VST4d8Pseudo:
1548  case ARM::VST4d16Pseudo:
1549  case ARM::VST4d32Pseudo:
1550  case ARM::VST1d64QPseudo:
1551  case ARM::VST4d8Pseudo_UPD:
1552  case ARM::VST4d16Pseudo_UPD:
1553  case ARM::VST4d32Pseudo_UPD:
1554  case ARM::VST1d64QPseudoWB_fixed:
1555  case ARM::VST1d64QPseudoWB_register:
1556  case ARM::VST4q8Pseudo_UPD:
1557  case ARM::VST4q16Pseudo_UPD:
1558  case ARM::VST4q32Pseudo_UPD:
1559  case ARM::VST4q8oddPseudo:
1560  case ARM::VST4q16oddPseudo:
1561  case ARM::VST4q32oddPseudo:
1562  case ARM::VST4q8oddPseudo_UPD:
1563  case ARM::VST4q16oddPseudo_UPD:
1564  case ARM::VST4q32oddPseudo_UPD:
1565  ExpandVST(MBBI);
1566  return true;
1567 
1568  case ARM::VLD1LNq8Pseudo:
1569  case ARM::VLD1LNq16Pseudo:
1570  case ARM::VLD1LNq32Pseudo:
1571  case ARM::VLD1LNq8Pseudo_UPD:
1572  case ARM::VLD1LNq16Pseudo_UPD:
1573  case ARM::VLD1LNq32Pseudo_UPD:
1574  case ARM::VLD2LNd8Pseudo:
1575  case ARM::VLD2LNd16Pseudo:
1576  case ARM::VLD2LNd32Pseudo:
1577  case ARM::VLD2LNq16Pseudo:
1578  case ARM::VLD2LNq32Pseudo:
1579  case ARM::VLD2LNd8Pseudo_UPD:
1580  case ARM::VLD2LNd16Pseudo_UPD:
1581  case ARM::VLD2LNd32Pseudo_UPD:
1582  case ARM::VLD2LNq16Pseudo_UPD:
1583  case ARM::VLD2LNq32Pseudo_UPD:
1584  case ARM::VLD3LNd8Pseudo:
1585  case ARM::VLD3LNd16Pseudo:
1586  case ARM::VLD3LNd32Pseudo:
1587  case ARM::VLD3LNq16Pseudo:
1588  case ARM::VLD3LNq32Pseudo:
1589  case ARM::VLD3LNd8Pseudo_UPD:
1590  case ARM::VLD3LNd16Pseudo_UPD:
1591  case ARM::VLD3LNd32Pseudo_UPD:
1592  case ARM::VLD3LNq16Pseudo_UPD:
1593  case ARM::VLD3LNq32Pseudo_UPD:
1594  case ARM::VLD4LNd8Pseudo:
1595  case ARM::VLD4LNd16Pseudo:
1596  case ARM::VLD4LNd32Pseudo:
1597  case ARM::VLD4LNq16Pseudo:
1598  case ARM::VLD4LNq32Pseudo:
1599  case ARM::VLD4LNd8Pseudo_UPD:
1600  case ARM::VLD4LNd16Pseudo_UPD:
1601  case ARM::VLD4LNd32Pseudo_UPD:
1602  case ARM::VLD4LNq16Pseudo_UPD:
1603  case ARM::VLD4LNq32Pseudo_UPD:
1604  case ARM::VST1LNq8Pseudo:
1605  case ARM::VST1LNq16Pseudo:
1606  case ARM::VST1LNq32Pseudo:
1607  case ARM::VST1LNq8Pseudo_UPD:
1608  case ARM::VST1LNq16Pseudo_UPD:
1609  case ARM::VST1LNq32Pseudo_UPD:
1610  case ARM::VST2LNd8Pseudo:
1611  case ARM::VST2LNd16Pseudo:
1612  case ARM::VST2LNd32Pseudo:
1613  case ARM::VST2LNq16Pseudo:
1614  case ARM::VST2LNq32Pseudo:
1615  case ARM::VST2LNd8Pseudo_UPD:
1616  case ARM::VST2LNd16Pseudo_UPD:
1617  case ARM::VST2LNd32Pseudo_UPD:
1618  case ARM::VST2LNq16Pseudo_UPD:
1619  case ARM::VST2LNq32Pseudo_UPD:
1620  case ARM::VST3LNd8Pseudo:
1621  case ARM::VST3LNd16Pseudo:
1622  case ARM::VST3LNd32Pseudo:
1623  case ARM::VST3LNq16Pseudo:
1624  case ARM::VST3LNq32Pseudo:
1625  case ARM::VST3LNd8Pseudo_UPD:
1626  case ARM::VST3LNd16Pseudo_UPD:
1627  case ARM::VST3LNd32Pseudo_UPD:
1628  case ARM::VST3LNq16Pseudo_UPD:
1629  case ARM::VST3LNq32Pseudo_UPD:
1630  case ARM::VST4LNd8Pseudo:
1631  case ARM::VST4LNd16Pseudo:
1632  case ARM::VST4LNd32Pseudo:
1633  case ARM::VST4LNq16Pseudo:
1634  case ARM::VST4LNq32Pseudo:
1635  case ARM::VST4LNd8Pseudo_UPD:
1636  case ARM::VST4LNd16Pseudo_UPD:
1637  case ARM::VST4LNd32Pseudo_UPD:
1638  case ARM::VST4LNq16Pseudo_UPD:
1639  case ARM::VST4LNq32Pseudo_UPD:
1640  ExpandLaneOp(MBBI);
1641  return true;
1642 
1643  case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1644  case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1645  case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1646  case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1647 
1648  case ARM::CMP_SWAP_8:
1649  if (STI->isThumb())
1650  return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1651  ARM::tUXTB, NextMBBI);
1652  else
1653  return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1654  ARM::UXTB, NextMBBI);
1655  case ARM::CMP_SWAP_16:
1656  if (STI->isThumb())
1657  return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1658  ARM::tUXTH, NextMBBI);
1659  else
1660  return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1661  ARM::UXTH, NextMBBI);
1662  case ARM::CMP_SWAP_32:
1663  if (STI->isThumb())
1664  return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1665  NextMBBI);
1666  else
1667  return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1668 
1669  case ARM::CMP_SWAP_64:
1670  return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1671  }
1672 }
1673 
1674 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1675  bool Modified = false;
1676 
1677  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1678  while (MBBI != E) {
1679  MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1680  Modified |= ExpandMI(MBB, MBBI, NMBBI);
1681  MBBI = NMBBI;
1682  }
1683 
1684  return Modified;
1685 }
1686 
1687 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1688  STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1689  TII = STI->getInstrInfo();
1690  TRI = STI->getRegisterInfo();
1691  AFI = MF.getInfo<ARMFunctionInfo>();
1692 
1693  bool Modified = false;
1694  for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1695  ++MFI)
1696  Modified |= ExpandMBB(*MFI);
1697  if (VerifyARMPseudo)
1698  MF.verify(this, "After expanding ARM pseudo instructions.");
1699  return Modified;
1700 }
1701 
1702 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1703 /// expansion pass.
1705  return new ARMExpandPseudo();
1706 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:241
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
const GlobalValue * getGlobal() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:226
static ARMConstantPoolSymbol * Create(LLVMContext &C, StringRef s, unsigned ID, unsigned char PCAdj)
size_t i
static cl::opt< bool > VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
static const NEONLdStTableEntry * LookupNEONLdSt(unsigned Opcode)
LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instructi...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
bool isDead() const
Address of indexed Jump Table for switch.
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:233
MachineBasicBlock reference.
const char * getSymbolName() const
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Mask of live-out registers.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Mask of preserved registers.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static const NEONLdStTableEntry NEONLdStTable[]
struct fuzzer::@269 Flags
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
MCCFIInstruction index.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Target-dependent index+offset operand.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isUndef() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
bool isKill() const
Immediate >64bit operand.
MachineBasicBlock * MBB
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
int64_t getImm() const
unsigned getUndefRegState(bool B)
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
unsigned getKillRegState(bool B)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
unsigned getDeadRegState(bool B)
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:359
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Address of a global value.
unsigned getTargetFlags() const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
static unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Address of a basic block.
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:150
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
int64_t getOffset() const
Return the offset from the symbol in this operand.
self_iterator getIterator()
Definition: ilist_node.h:81
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned getSubReg() const
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Abstract base class for all machine specific constantpool value subclasses.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:286
virtual const TargetFrameLowering * getFrameLowering() const
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
#define R6(n)
Generic predicate for ISel.
MachineOperand class - Representation of each machine instruction operand.
static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI)
ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register)...
MCSymbol reference (for debug/eh info)
bool hasBasePointer(const MachineFunction &MF) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
A set of live physical registers with functions to track liveness when walking backward/forward throu...
Definition: LivePhysRegs.h:45
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3)
GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified regis...
static void addPostLoopLiveIns(MachineBasicBlock *MBB, LivePhysRegs &LiveRegs)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
#define I(x, y, z)
Definition: MD5.cpp:54
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Abstract Stack Frame Index.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:326
virtual const TargetInstrInfo * getInstrInfo() const
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
Floating-point immediate operand.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
static bool IsAnAddressOperand(const MachineOperand &MO)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static const unsigned FramePtr
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
Address of indexed Constant in Constant Pool.
const_iterator end() const
Definition: LivePhysRegs.h:139
static unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
const_iterator begin() const
Definition: LivePhysRegs.h:138
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:290
Properties which a MachineFunction may have at a given point in time.
Metadata reference (for debug info)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:358
char * PC