LLVM  4.0.0
Macros | Typedefs | Enumerations | Functions | Variables
ARMISelLowering.cpp File Reference
#include "ARMISelLowering.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMSubtarget.h"
#include "ARMTargetMachine.h"
#include "ARMTargetObjectFile.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Type.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include <utility>
#include "ARMGenCallingConv.inc"
Include dependency graph for ARMISelLowering.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "arm-isel"
 

Typedefs

typedef std::pair< unsigned,
const TargetRegisterClass * > 
RCPair
 

Enumerations

enum  HABaseType {
  HA_UNKNOWN = 0, HA_FLOAT, HA_DOUBLE, HA_VECT64,
  HA_VECT128
}
 

Functions

 STATISTIC (NumTailCalls,"Number of tail calls")
 
 STATISTIC (NumMovwMovt,"Number of GAs materialized with movw + movt")
 
 STATISTIC (NumLoopByVals,"Number of loops generated for byval arguments")
 
 STATISTIC (NumConstpoolPromoted,"Number of constants with their storage promoted into constant pools")
 
static ARMCC::CondCodes IntCCToARMCC (ISD::CondCode CC)
 IntCCToARMCC - Convert a DAG integer condition code to an ARM CC. More...
 
static void FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
 FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. More...
 
static bool MatchingStackOffset (SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII)
 MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack. More...
 
static SDValue LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
 
static SDValue LowerWRITE_REGISTER (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerConstantPool (SDValue Op, SelectionDAG &DAG)
 
static bool allUsersAreInFunction (const Value *V, const Function *F)
 Return true if all users of V are within function F, looking through ConstantExprs. More...
 
static bool allUsersAreInFunctions (const Value *V)
 Return true if all users of V are within some (any) function, looking through ConstantExprs. More...
 
static bool isSimpleType (Type *T)
 
static SDValue promoteToConstantPool (const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, SDLoc dl)
 
static bool isReadOnly (const GlobalValue *GV)
 
static SDValue LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue LowerVASTART (SDValue Op, SelectionDAG &DAG)
 
static bool isFloatingPointZero (SDValue Op)
 isFloatingPointZero - Return true if this is +0.0. More...
 
static void checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)
 
static bool isGTorGE (ISD::CondCode CC)
 
static bool isLTorLE (ISD::CondCode CC)
 
static bool isLowerSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)
 
static bool isUpperSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)
 
static bool isSaturatingConditional (const SDValue &Op, SDValue &V, uint64_t &K)
 
static bool canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
 canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence. More...
 
static SDValue bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG)
 
static void expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)
 
static SDValue LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
 
static void ExpandREAD_REGISTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
 
static SDValue CombineVMOVDRRCandidateWithVecOp (const SDNode *BC, SelectionDAG &DAG)
 BC is a bitcast that is about to be turned into a VMOVDRR. More...
 
static SDValue ExpandBITCAST (SDNode *N, SelectionDAG &DAG)
 ExpandBITCAST - If the target supports VFP, this function is called to expand a bit convert where either the source or destination type is i64 to use a VMOVDRR or VMOVRRD node. More...
 
static SDValue getZeroVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl)
 getZeroVector - Returns a vector of specified type with all zero elements. More...
 
static SDValue LowerCTTZ (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue getCTPOP16BitCounts (SDNode *N, SelectionDAG &DAG)
 getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count for each 16-bit element from operand, repeated. More...
 
static SDValue lowerCTPOP16BitElements (SDNode *N, SelectionDAG &DAG)
 lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the bit-count for each 16-bit element from the operand. More...
 
static SDValue lowerCTPOP32BitElements (SDNode *N, SelectionDAG &DAG)
 lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the bit-count for each 32-bit element from the operand. More...
 
static SDValue LowerCTPOP (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue Expand64BitShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 
static SDValue LowerVSETCC (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerSETCCE (SDValue Op, SelectionDAG &DAG)
 
static SDValue isNEONModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, bool is128Bits, NEONModImmType type)
 isNEONModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON instruction with a "modified immediate" operand (e.g., VMOV). More...
 
static bool isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
 
static bool isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)
 
static bool isVREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize)
 isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize. More...
 
static bool isVTBLMask (ArrayRef< int > M, EVT VT)
 
static bool isVTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static bool isVUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static bool isVZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isVZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static unsigned isNEONTwoResultShuffleMask (ArrayRef< int > ShuffleMask, EVT VT, unsigned &WhichResult, bool &isV_UNDEF)
 Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't. More...
 
static bool isReverseMask (ArrayRef< int > M, EVT VT)
 
static SDValue IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl)
 
static SDValue GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
 GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More...
 
static SDValue LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
 
static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerINSERT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG)
 
static bool isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
 isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size. More...
 
static bool isSignExtended (SDNode *N, SelectionDAG &DAG)
 isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements. More...
 
static bool isZeroExtended (SDNode *N, SelectionDAG &DAG)
 isZeroExtended - Check if a node is a vector value that is zero-extended or a constant BUILD_VECTOR with zero-extended elements. More...
 
static EVT getExtensionTo64Bits (const EVT &OrigVT)
 
static SDValue AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
 AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits. More...
 
static SDValue SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG)
 SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension. More...
 
static SDValue SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG)
 SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value. More...
 
static bool isAddSubSExt (SDNode *N, SelectionDAG &DAG)
 
static bool isAddSubZExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue LowerMUL (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerSDIV_v4i8 (SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG)
 
static SDValue LowerSDIV_v4i16 (SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG)
 
static SDValue LowerSDIV (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerUDIV (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG)
 
static SDValue WinDBZCheckDenominator (SelectionDAG &DAG, SDNode *N, SDValue InChain)
 
static SDValue LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG)
 
static void ReplaceREADCYCLECOUNTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 
static SDValue createGPRPairNode (SelectionDAG &DAG, SDValue V)
 
static void ReplaceCMP_SWAP_64Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
 
static SDValue LowerFPOWI (SDValue Op, const ARMSubtarget &Subtarget, SelectionDAG &DAG)
 
static MachineBasicBlockOtherSucc (MachineBasicBlock *MBB, MachineBasicBlock *Succ)
 
static unsigned getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2)
 Return the load opcode for a given load size. More...
 
static unsigned getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2)
 Return the store opcode for a given store size. More...
 
static void emitPostLd (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
 Emit a post-increment load operation with given size. More...
 
static void emitPostSt (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
 Emit a post-increment store operation with given size. More...
 
static void attachMEMCPYScratchRegs (const ARMSubtarget *Subtarget, MachineInstr &MI, const SDNode *Node)
 Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM. More...
 
static bool isZeroOrAllOnes (SDValue N, bool AllOnes)
 
static bool isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
 
static SDValue combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)
 
static SDValue combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)
 
static bool IsVUZPShuffleNode (SDNode *N)
 
static SDValue AddCombineToVPADD (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue AddCombineVUZPToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue AddCombineBUILD_VECTORToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue findMUL_LOHI (SDValue V)
 
static SDValue AddCombineTo64bitMLAL (SDNode *AddcNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue AddCombineTo64bitUMAAL (SDNode *AddcNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformADDCCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformADDCCombine - Target-specific dag combine transform from ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL or ISD::ADDC, ISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL. More...
 
static SDValue PerformADDCombineWithOperands (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1. More...
 
static SDValue PerformADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. More...
 
static SDValue PerformSUBCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. More...
 
static SDValue PerformVMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding. More...
 
static SDValue PerformMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue PerformORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformORCombine - Target-specific dag combine xforms for ISD::OR. More...
 
static SDValue PerformXORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 
static SDValue ParseBFI (SDNode *N, APInt &ToMask, APInt &FromMask)
 
static bool BitsProperlyConcatenate (const APInt &A, const APInt &B)
 
static SDValue FindBFIToCombineWith (SDNode *N)
 
static SDValue PerformBFICombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformVMOVRRDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD. More...
 
static SDValue PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG)
 PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR. More...
 
static bool hasNormalLoadOperand (SDNode *N)
 hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads. More...
 
static SDValue PerformBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
 PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR. More...
 
static SDValue PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 Target-specific dag combine xforms for ARMISD::BUILD_VECTOR. More...
 
static SDValue PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT. More...
 
static SDValue PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG)
 PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE. More...
 
static SDValue CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates. More...
 
static SDValue PerformVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static bool CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs. More...
 
static SDValue PerformVDUPLANECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE. More...
 
static SDValue PerformVDUPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP. More...
 
static SDValue PerformLOADCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue PerformSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE. More...
 
static SDValue PerformVCVTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2. More...
 
static SDValue PerformVDIVCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
 PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2. More...
 
static bool getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
 Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More...
 
static bool isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
 isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More...
 
static bool isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
 isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More...
 
static SDValue PerformIntrinsicCombine (SDNode *N, SelectionDAG &DAG)
 PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. More...
 
static SDValue PerformShiftCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them. More...
 
static SDValue PerformExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
 PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. More...
 
static void computeKnownBits (SelectionDAG &DAG, SDValue Op, APInt &KnownZero, APInt &KnownOne)
 
static bool memOpAlign (unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck)
 
static bool isLegalT1AddressImmediate (int64_t V, EVT VT)
 
static bool isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
 
static bool isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
 isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type. More...
 
static bool getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
 
static bool getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
 
static RTLIB::Libcall getDivRemLibcall (const SDNode *N, MVT::SimpleValueType SVT)
 
static TargetLowering::ArgListTy getDivRemArgList (const SDNode *N, LLVMContext *Context, const ARMSubtarget *Subtarget)
 
static ConstantgetSequentialMask (IRBuilder<> &Builder, unsigned Start, unsigned NumElts)
 Get a mask consisting of sequential integers starting from Start. More...
 
static bool isHomogeneousAggregate (Type *Ty, HABaseType &Base, uint64_t &Members)
 

Variables

static cl::opt< boolARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
 
static cl::opt< boolEnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into ""constant pools"), cl::init(true))
 
static cl::opt< unsignedConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))
 
static cl::opt< unsignedConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))
 
static const MCPhysReg GPRArgRegs []
 

Macro Definition Documentation

#define DEBUG_TYPE   "arm-isel"

Definition at line 58 of file ARMISelLowering.cpp.

Typedef Documentation

typedef std::pair<unsigned, const TargetRegisterClass*> RCPair

Definition at line 12342 of file ARMISelLowering.cpp.

Enumeration Type Documentation

enum HABaseType
Enumerator
HA_UNKNOWN 
HA_FLOAT 
HA_DOUBLE 
HA_VECT64 
HA_VECT128 

Definition at line 13350 of file ARMISelLowering.cpp.

Function Documentation

static SDValue AddCombineBUILD_VECTORToVPADDL ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue AddCombineTo64bitMLAL ( SDNode AddcNode,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue AddCombineTo64bitUMAAL ( SDNode AddcNode,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue AddCombineToVPADD ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue AddCombineVUZPToVPADDL ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue AddRequiredExtensionForVMULL ( SDValue  N,
SelectionDAG DAG,
const EVT OrigTy,
const EVT ExtTy,
unsigned  ExtOpcode 
)
static

AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.

We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.

Definition at line 6846 of file ARMISelLowering.cpp.

References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), and llvm::EVT::is128BitVector().

Referenced by SkipExtensionForVMULL().

static bool allUsersAreInFunction ( const Value V,
const Function F 
)
static

Return true if all users of V are within function F, looking through ConstantExprs.

Definition at line 2884 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SmallVectorBase::empty(), F, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::Value::users().

Referenced by promoteToConstantPool().

static bool allUsersAreInFunctions ( const Value V)
static

Return true if all users of V are within some (any) function, looking through ConstantExprs.

In other words, are there any global constant users?

Definition at line 2905 of file ARMISelLowering.cpp.

References llvm::SmallVectorBase::empty(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::Value::users().

Referenced by promoteToConstantPool().

static void attachMEMCPYScratchRegs ( const ARMSubtarget Subtarget,
MachineInstr MI,
const SDNode Node 
)
static
static SDValue bitcastf32Toi32 ( SDValue  Op,
SelectionDAG DAG 
)
static
static bool BitsProperlyConcatenate ( const APInt A,
const APInt B 
)
static
static bool canChangeToInt ( SDValue  Op,
bool SeenZero,
const ARMSubtarget Subtarget 
)
static

canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.

Definition at line 4198 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), isFloatingPointZero(), llvm::ARMSubtarget::isFPBrccSlow(), and llvm::ISD::isNormalLoad().

static void checkVSELConstraints ( ISD::CondCode  CC,
ARMCC::CondCodes CondCode,
bool swpCmpOps,
bool swpVselOps 
)
static
static SDValue CombineBaseUpdate ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.

For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.

Definition at line 10394 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MemSDNode::getAlignment(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), i, llvm::MVT::i32, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::SDNode::isPredecessorOf(), llvm_unreachable, llvm::ISD::LOAD, llvm::makeArrayRef(), N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SmallVectorTemplateCommon< T >::size(), llvm::ISD::STORE, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD1DUP, llvm::ARMISD::VLD1DUP_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, and llvm::ARMISD::VST4LN_UPD.

Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().

static SDValue combineSelectAndUse ( SDNode N,
SDValue  Slct,
SDValue  OtherOp,
TargetLowering::DAGCombinerInfo DCI,
bool  AllOnes = false 
)
static
static SDValue combineSelectAndUseCommutative ( SDNode N,
bool  AllOnes,
TargetLowering::DAGCombinerInfo DCI 
)
static
static bool CombineVLDDUP ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue CombineVMOVDRRCandidateWithVecOp ( const SDNode BC,
SelectionDAG DAG 
)
static

BC is a bitcast that is about to be turned into a VMOVDRR.

When DstVT, the destination type of BC, is on the vector register bank and the source of bitcast, Op, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return The node that would replace BT, if the combine is possible.

Definition at line 4657 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, and llvm::EVT::isVector().

Referenced by ExpandBITCAST().

static void computeKnownBits ( SelectionDAG DAG,
SDValue  Op,
APInt KnownZero,
APInt KnownOne 
)
static
static SDValue createGPRPairNode ( SelectionDAG DAG,
SDValue  V 
)
static
static void emitPostLd ( MachineBasicBlock BB,
MachineBasicBlock::iterator  Pos,
const TargetInstrInfo TII,
const DebugLoc dl,
unsigned  LdSize,
unsigned  Data,
unsigned  AddrIn,
unsigned  AddrOut,
bool  IsThumb1,
bool  IsThumb2 
)
static

Emit a post-increment load operation with given size.

The instructions will be added to BB at Pos.

Definition at line 8218 of file ARMISelLowering.cpp.

References llvm::AddDefaultPred(), llvm::AddDefaultT1CC(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, llvm::MCInstrInfo::get(), and getLdOpcode().

static void emitPostSt ( MachineBasicBlock BB,
MachineBasicBlock::iterator  Pos,
const TargetInstrInfo TII,
const DebugLoc dl,
unsigned  StSize,
unsigned  Data,
unsigned  AddrIn,
unsigned  AddrOut,
bool  IsThumb1,
bool  IsThumb2 
)
static

Emit a post-increment store operation with given size.

The instructions will be added to BB at Pos.

Definition at line 8250 of file ARMISelLowering.cpp.

References llvm::AddDefaultPred(), llvm::AddDefaultT1CC(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MCInstrInfo::get(), and getStOpcode().

static SDValue Expand64BitShift ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static
static SDValue ExpandBITCAST ( SDNode N,
SelectionDAG DAG 
)
static
static void expandf64Toi32 ( SDValue  Op,
SelectionDAG DAG,
SDValue RetVal1,
SDValue RetVal2 
)
static
static void ExpandREAD_REGISTER ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
)
static
static SDValue FindBFIToCombineWith ( SDNode N)
static
static SDValue findMUL_LOHI ( SDValue  V)
static
static void FPCCToARMCC ( ISD::CondCode  CC,
ARMCC::CondCodes CondCode,
ARMCC::CondCodes CondCode2 
)
static
static SDValue GeneratePerfectShuffle ( unsigned  PFEntry,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
const SDLoc dl 
)
static
static bool getARMIndexedAddressParts ( SDNode Ptr,
EVT  VT,
bool  isSEXTLoad,
SDValue Base,
SDValue Offset,
bool isInc,
SelectionDAG DAG 
)
static
static SDValue getCTPOP16BitCounts ( SDNode N,
SelectionDAG DAG 
)
static

getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count for each 16-bit element from operand, repeated.

The basic idea is to leverage vcnt to get the 8-bit counts, gather and add the results.

Trace for v4i16: input = [v0 v1 v2 v3 ] (vi 16-bit element) cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element) vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi) vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6] [b0 b1 b2 b3 b4 b5 b6 b7] +[b1 b0 b3 b2 b5 b4 b7 b6] N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0, vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)

Definition at line 4966 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::CTPOP, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::is64BitVector(), llvm::MVT::v16i8, llvm::MVT::v8i8, llvm::ARMISD::VREV16, and llvm::ARMISD::VUZP.

Referenced by lowerCTPOP16BitElements().

static TargetLowering::ArgListTy getDivRemArgList ( const SDNode N,
LLVMContext Context,
const ARMSubtarget Subtarget 
)
static
static RTLIB::Libcall getDivRemLibcall ( const SDNode N,
MVT::SimpleValueType  SVT 
)
static
static EVT getExtensionTo64Bits ( const EVT OrigVT)
static
static unsigned getLdOpcode ( unsigned  LdSize,
bool  IsThumb1,
bool  IsThumb2 
)
static

Return the load opcode for a given load size.

If load size >= 8, neon opcode will be returned.

Definition at line 8180 of file ARMISelLowering.cpp.

Referenced by emitPostLd().

static Constant* getSequentialMask ( IRBuilder<> &  Builder,
unsigned  Start,
unsigned  NumElts 
)
static

Get a mask consisting of sequential integers starting from Start.

I.e. <Start, Start + 1, ..., Start + NumElts - 1>

Definition at line 13232 of file ARMISelLowering.cpp.

References llvm::ConstantVector::get(), llvm::IRBuilderBase::getInt32(), llvm::BitmaskEnumDetail::Mask(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by llvm::ARMTargetLowering::lowerInterleavedStore().

static unsigned getStOpcode ( unsigned  StSize,
bool  IsThumb1,
bool  IsThumb2 
)
static

Return the store opcode for a given store size.

If store size >= 8, neon opcode will be returned.

Definition at line 8199 of file ARMISelLowering.cpp.

Referenced by emitPostSt().

static bool getT2IndexedAddressParts ( SDNode Ptr,
EVT  VT,
bool  isSEXTLoad,
SDValue Base,
SDValue Offset,
bool isInc,
SelectionDAG DAG 
)
static
static bool getVShiftImm ( SDValue  Op,
unsigned  ElementBits,
int64_t &  Cnt 
)
static

Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 11024 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), and llvm::BuildVectorSDNode::isConstantSplat().

Referenced by isVShiftLImm(), and isVShiftRImm().

static SDValue getZeroVector ( EVT  VT,
SelectionDAG DAG,
const SDLoc dl 
)
static

getZeroVector - Returns a vector of specified type with all zero elements.

Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.

Definition at line 4756 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::is128BitVector(), llvm::EVT::isVector(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ARMISD::VMOVIMM.

Referenced by LowerCTTZ(), and LowerShift().

static bool hasNormalLoadOperand ( SDNode N)
static

hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.

If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.

Definition at line 10176 of file ARMISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), i, llvm::ISD::isNormalLoad(), and isVolatile().

Referenced by PerformBUILD_VECTORCombine().

static ARMCC::CondCodes IntCCToARMCC ( ISD::CondCode  CC)
static
static bool isAddSubSExt ( SDNode N,
SelectionDAG DAG 
)
static
static bool isAddSubZExt ( SDNode N,
SelectionDAG DAG 
)
static
static bool isConditionalZeroOrAllOnes ( SDNode N,
bool  AllOnes,
SDValue CC,
bool Invert,
SDValue OtherOp,
SelectionDAG DAG 
)
static
static bool isExtendedBUILD_VECTOR ( SDNode N,
SelectionDAG DAG,
bool  isSigned 
)
static
static bool isFloatingPointZero ( SDValue  Op)
static
static bool isGTorGE ( ISD::CondCode  CC)
static

Definition at line 3980 of file ARMISelLowering.cpp.

References llvm::ISD::SETGE, and llvm::ISD::SETGT.

Referenced by isLowerSaturate(), and isUpperSaturate().

static bool isHomogeneousAggregate ( Type Ty,
HABaseType Base,
uint64_t &  Members 
)
static
static bool isLegalAddressImmediate ( int64_t  V,
EVT  VT,
const ARMSubtarget Subtarget 
)
static

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

Definition at line 11830 of file ARMISelLowering.cpp.

References llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i8, isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().

static bool isLegalT1AddressImmediate ( int64_t  V,
EVT  VT 
)
static
static bool isLegalT2AddressImmediate ( int64_t  V,
EVT  VT,
const ARMSubtarget Subtarget 
)
static
static bool isLowerSaturate ( const SDValue  LHS,
const SDValue  RHS,
const SDValue  TrueVal,
const SDValue  FalseVal,
const ISD::CondCode  CC,
const SDValue  K 
)
static

Definition at line 3994 of file ARMISelLowering.cpp.

References isGTorGE(), and isLTorLE().

Referenced by isSaturatingConditional().

static bool isLTorLE ( ISD::CondCode  CC)
static

Definition at line 3984 of file ARMISelLowering.cpp.

References llvm::ISD::SETLE, and llvm::ISD::SETLT.

Referenced by isLowerSaturate(), and isUpperSaturate().

static SDValue isNEONModifiedImm ( uint64_t  SplatBits,
uint64_t  SplatUndef,
unsigned  SplatBitSize,
SelectionDAG DAG,
const SDLoc dl,
EVT VT,
bool  is128Bits,
NEONModImmType  type 
)
static

isNEONModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON instruction with a "modified immediate" operand (e.g., VMOV).

If so, return the encoded value.

Definition at line 5320 of file ARMISelLowering.cpp.

References assert(), llvm::ARM_AM::createNEONModImm(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getTargetConstant(), llvm::X86II::ImmMask, llvm::DataLayout::isBigEndian(), llvm_unreachable, llvm::OtherModImm, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::VMOVModImm.

Referenced by PerformANDCombine(), and PerformORCombine().

static unsigned isNEONTwoResultShuffleMask ( ArrayRef< int >  ShuffleMask,
EVT  VT,
unsigned WhichResult,
bool isV_UNDEF 
)
static

Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.

Definition at line 5887 of file ARMISelLowering.cpp.

References isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isReadOnly ( const GlobalValue GV)
static
static bool isReverseMask ( ArrayRef< int >  M,
EVT  VT 
)
static
Returns
true if this is a reverse operation on an vector.

Definition at line 5910 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), i, and llvm::ArrayRef< T >::size().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isSaturatingConditional ( const SDValue Op,
SDValue V,
uint64_t &  K 
)
static
static bool isSignExtended ( SDNode N,
SelectionDAG DAG 
)
static

isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.

Definition at line 6808 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), and llvm::ISD::SIGN_EXTEND.

Referenced by isAddSubSExt(), and LowerMUL().

static bool isSimpleType ( Type T)
static
static SDValue IsSingleInstrConstant ( SDValue  N,
SelectionDAG DAG,
const ARMSubtarget ST,
const SDLoc dl 
)
static
static bool isSingletonVEXTMask ( ArrayRef< int >  M,
EVT  VT,
unsigned Imm 
)
static

Definition at line 5559 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and i.

Referenced by LowerVECTOR_SHUFFLE().

static bool isUpperSaturate ( const SDValue  LHS,
const SDValue  RHS,
const SDValue  TrueVal,
const SDValue  FalseVal,
const ISD::CondCode  CC,
const SDValue  K 
)
static

Definition at line 4004 of file ARMISelLowering.cpp.

References isGTorGE(), and isLTorLE().

Referenced by isSaturatingConditional().

static bool isVEXTMask ( ArrayRef< int >  M,
EVT  VT,
bool ReverseVEXT,
unsigned Imm 
)
static
static bool isVREVMask ( ArrayRef< int >  M,
EVT  VT,
unsigned  BlockSize 
)
static

isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize.

(The order of the elements within each block of the vector is reversed.)

Definition at line 5627 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and i.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

static bool isVShiftLImm ( SDValue  Op,
EVT  VT,
bool  isLong,
int64_t &  Cnt 
)
static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 11044 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by PerformIntrinsicCombine(), and PerformShiftCombine().

static bool isVShiftRImm ( SDValue  Op,
EVT  VT,
bool  isNarrow,
bool  isIntrinsic,
int64_t &  Cnt 
)
static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.

For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 11058 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by PerformIntrinsicCombine(), and PerformShiftCombine().

static bool isVTBLMask ( ArrayRef< int >  M,
EVT  VT 
)
static
static bool isVTRN_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 5716 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

static bool isVTRNMask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static
static bool isVUZP_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 5781 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

static bool isVUZPMask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static
static bool IsVUZPShuffleNode ( SDNode N)
static
static bool isVZIP_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 5855 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), i, llvm::EVT::is64BitVector(), and llvm::ArrayRef< T >::size().

Referenced by isNEONTwoResultShuffleMask().

static bool isVZIPMask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static
static bool isZeroExtended ( SDNode N,
SelectionDAG DAG 
)
static

isZeroExtended - Check if a node is a vector value that is zero-extended or a constant BUILD_VECTOR with zero-extended elements.

Definition at line 6818 of file ARMISelLowering.cpp.

References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), and llvm::ISD::ZERO_EXTEND.

Referenced by isAddSubZExt(), and LowerMUL().

static bool isZeroOrAllOnes ( SDValue  N,
bool  AllOnes 
)
inlinestatic

Definition at line 8988 of file ARMISelLowering.cpp.

References llvm::isAllOnesConstant(), and llvm::isNullConstant().

Referenced by isConditionalZeroOrAllOnes().

static SDValue LowerADDC_ADDE_SUBC_SUBE ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerATOMIC_FENCE ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static
static SDValue LowerAtomicLoadStore ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerCONCAT_VECTORS ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerConstantPool ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerCTPOP ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static
static SDValue lowerCTPOP16BitElements ( SDNode N,
SelectionDAG DAG 
)
static

lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the bit-count for each 16-bit element from the operand.

We need slightly different sequencing for v4i16 and v8i16 to stay within NEON's available 64/128-bit registers.

Trace for v4i16: input = [v0 v1 v2 v3 ] (vi 16-bit element) v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi) v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ] v4i16:Extracted = [k0 k1 k2 k3 ]

Definition at line 4988 of file ARMISelLowering.cpp.

References llvm::ISD::EXTRACT_SUBVECTOR, getCTPOP16BitCounts(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getValueType(), llvm::EVT::is64BitVector(), llvm::MVT::v4i16, llvm::MVT::v8i16, llvm::MVT::v8i8, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerCTPOP(), and lowerCTPOP32BitElements().

static SDValue lowerCTPOP32BitElements ( SDNode N,
SelectionDAG DAG 
)
static

lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the bit-count for each 32-bit element from the operand.

The idea here is to split the vector into 16-bit elements, leverage the 16-bit count routine, and then combine the results.

Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged): input = [v0 v1 ] (vi: 32-bit elements) Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1]) Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi) vrev: N0 = [k1 k0 k3 k2 ] [k0 k1 k2 k3 ] N1 =+[k1 k0 k3 k2 ] [k0 k2 k1 k3 ] N2 =+[k1 k3 k0 k2 ] [k0 k2 k1 k3 ] Extended =+[k1 k3 k0 k2 ] [k0 k2 ] Extracted=+[k1 k3 ]

Definition at line 5023 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::MCID::Bitcast, llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::is64BitVector(), lowerCTPOP16BitElements(), llvm::MVT::v2i32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, llvm::ARMISD::VREV32, llvm::ARMISD::VUZP, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerCTPOP().

static SDValue LowerCTTZ ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static
static SDValue LowerEXTRACT_VECTOR_ELT ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerFPOWI ( SDValue  Op,
const ARMSubtarget Subtarget,
SelectionDAG DAG 
)
static
static SDValue LowerINSERT_VECTOR_ELT ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerInterruptReturn ( SmallVectorImpl< SDValue > &  RetOps,
const SDLoc DL,
SelectionDAG DAG 
)
static
static SDValue LowerMUL ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerPREFETCH ( SDValue  Op,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static
static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16 ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerSDIV ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerSDIV_v4i16 ( SDValue  N0,
SDValue  N1,
const SDLoc dl,
SelectionDAG DAG 
)
static
static SDValue LowerSDIV_v4i8 ( SDValue  X,
SDValue  Y,
const SDLoc dl,
SelectionDAG DAG 
)
static
static SDValue LowerSETCCE ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerShift ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static
static SDValue LowerUDIV ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerVASTART ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG DAG 
)
static

Definition at line 6535 of file ARMISelLowering.cpp.

References llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), i, isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SDValue::isUndef(), llvm::SDNode::isUndef(), isVEXTMask(), isVREVMask(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerVECTOR_SHUFFLEv8i8(), PerfectShuffleTable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, std::swap(), llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ARMISD::VREV64.

Referenced by llvm::ARMTargetLowering::LowerOperation().

static SDValue LowerVECTOR_SHUFFLEv8i8 ( SDValue  Op,
ArrayRef< int >  ShuffleMask,
SelectionDAG DAG 
)
static
static SDValue LowerVectorFP_TO_INT ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerVectorINT_TO_FP ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerVSETCC ( SDValue  Op,
SelectionDAG DAG 
)
static
static SDValue LowerWRITE_REGISTER ( SDValue  Op,
SelectionDAG DAG 
)
static
static bool MatchingStackOffset ( SDValue  Arg,
unsigned  Offset,
ISD::ArgFlagsTy  Flags,
MachineFrameInfo MFI,
const MachineRegisterInfo MRI,
const TargetInstrInfo TII 
)
static
static bool memOpAlign ( unsigned  DstAlign,
unsigned  SrcAlign,
unsigned  AlignCheck 
)
static

Definition at line 11662 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::getOptimalMemOpType().

static MachineBasicBlock* OtherSucc ( MachineBasicBlock MBB,
MachineBasicBlock Succ 
)
static
static SDValue ParseBFI ( SDNode N,
APInt ToMask,
APInt FromMask 
)
static
static SDValue PerformADDCCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformADDCCombine - Target-specific dag combine transform from ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL or ISD::ADDC, ISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.

Definition at line 9524 of file ARMISelLowering.cpp.

References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), and llvm::ARMSubtarget::isThumb1Only().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformADDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 9563 of file ARMISelLowering.cpp.

References llvm::SDNode::getOperand(), and PerformADDCombineWithOperands().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformADDCombineWithOperands ( SDNode N,
SDValue  N0,
SDValue  N1,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.

This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 9540 of file ARMISelLowering.cpp.

References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), and llvm::SDNode::hasOneUse().

Referenced by PerformADDCombine().

static SDValue PerformANDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue PerformARMBUILD_VECTORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue PerformBFICombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue PerformBUILD_VECTORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue PerformExtendCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static
static SDValue PerformInsertEltCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue PerformIntrinsicCombine ( SDNode N,
SelectionDAG DAG 
)
static
static SDValue PerformLOADCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue PerformMULCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue PerformORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue PerformShiftCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget ST 
)
static

PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.

As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.

Definition at line 11221 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BSWAP, llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::hasV6Ops(), llvm::TargetLoweringBase::isTypeLegal(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, llvm::SelectionDAG::MaskedValueIsZero(), llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ARMISD::VSHL, llvm::ARMISD::VSHRs, and llvm::ARMISD::VSHRu.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformSTORECombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.

Definition at line 10760 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::ISD::BITCAST, CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, E, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f64, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::SDNode::hasOneUse(), i, llvm::MVT::i64, llvm::MVT::i8, llvm::MVT::integer_valuetypes(), llvm::DataLayout::isBigEndian(), llvm::ISD::isNormalStore(), llvm::isPowerOf2_32(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), fuzzer::min(), N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::TokenFactor, and llvm::ARMISD::VMOVDRR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformSUBCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.

Definition at line 9579 of file ARMISelLowering.cpp.

References combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), and llvm::SDNode::hasOneUse().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVCVTCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static

PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3

Definition at line 10914 of file ARMISelLowering.cpp.

References llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::ARMSubtarget::hasNEON(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::TRUNCATE, llvm::MVT::v2i32, and llvm::MVT::v4i32.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVDIVCombine ( SDNode N,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static
static SDValue PerformVDUPCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue PerformVDUPLANECombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue PerformVECTOR_SHUFFLECombine ( SDNode N,
SelectionDAG DAG 
)
static
static SDValue PerformVLDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static
static SDValue PerformVMOVDRRCombine ( SDNode N,
SelectionDAG DAG 
)
static

PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.

This is also used for BUILD_VECTORs with 2 operands.

Definition at line 10156 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SDNode::getValueType(), and llvm::ARMISD::VMOVRRD.

Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

static SDValue PerformVMOVRRDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue PerformVMULCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static

PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.

vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2

Definition at line 9607 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ARMSubtarget::hasVMLxForwarding(), llvm::ISD::MUL, llvm::ISD::SUB, and std::swap().

Referenced by PerformMULCombine().

static SDValue PerformXORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const ARMSubtarget Subtarget 
)
static
static SDValue promoteToConstantPool ( const GlobalValue GV,
SelectionDAG DAG,
EVT  PtrVT,
SDLoc  dl 
)
static
static void ReplaceCMP_SWAP_64Results ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
)
static
static void ReplaceREADCYCLECOUNTER ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG,
const ARMSubtarget Subtarget 
)
static
static SDValue SkipExtensionForVMULL ( SDNode N,
SelectionDAG DAG 
)
static

SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.

The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.

Definition at line 6892 of file ARMISelLowering.cpp.

References AddRequiredExtensionForVMULL(), assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::getVectorVT(), i, llvm::MVT::i32, llvm::DataLayout::isBigEndian(), llvm::ARM_MB::LD, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::MVT::v2i32, llvm::MVT::v4i32, and llvm::ISD::ZERO_EXTEND.

Referenced by LowerMUL().

static SDValue SkipLoadExtensionForVMULL ( LoadSDNode LD,
SelectionDAG DAG 
)
static

SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.

If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.

Definition at line 6868 of file ARMISelLowering.cpp.

References llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), getExtensionTo64Bits(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getExtLoad(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), and llvm::MemSDNode::getPointerInfo().

Referenced by SkipExtensionForVMULL().

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)
STATISTIC ( NumMovwMovt  ,
"Number of GAs materialized with movw + movt"   
)
STATISTIC ( NumLoopByVals  ,
"Number of loops generated for byval arguments"   
)
STATISTIC ( NumConstpoolPromoted  ,
"Number of constants with their storage promoted into constant pools"   
)
static SDValue WinDBZCheckDenominator ( SelectionDAG DAG,
SDNode N,
SDValue  InChain 
)
static

Variable Documentation

cl::opt<bool> ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
static
cl::opt<unsigned> ConstpoolPromotionMaxSize("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))
static

Referenced by promoteToConstantPool().

cl::opt<unsigned> ConstpoolPromotionMaxTotal("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))
static

Referenced by promoteToConstantPool().

cl::opt<bool> EnableConstpoolPromotion("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into ""constant pools"), cl::init(true))
static

Referenced by promoteToConstantPool().

const MCPhysReg GPRArgRegs[]
static
Initial value:
= {
ARM::R0, ARM::R1, ARM::R2, ARM::R3
}
#define R2(n)

Definition at line 101 of file ARMISelLowering.cpp.

Referenced by llvm::f64AssignAAPCS().