32 #define DEBUG_TYPE "regalloc"
34 STATISTIC(NumFinished,
"Number of splits finished");
35 STATISTIC(NumSimple,
"Number of splits that were simple");
36 STATISTIC(NumCopies,
"Number of copies inserted for splitting");
37 STATISTIC(NumRemats,
"Number of rematerialized defs for splitting");
38 STATISTIC(NumRepairs,
"Number of invalid live ranges repaired");
46 : LIS(lis), LastInsertPoint(BBNum) {}
49 InsertPointAnalysis::computeLastInsertPoint(
const LiveInterval &CurLI,
52 std::pair<SlotIndex, SlotIndex> &LIP = LastInsertPoint[Num];
62 if (!LIP.first.isValid()) {
64 if (FirstTerm == MBB.
end())
70 if (EHPadSucessors.
empty())
73 LIP.second = LIP.first;
126 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis),
Loops(mli),
127 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
128 IPA(lis, MF.getNumBlockIDs()) {}
133 ThroughBlocks.
clear();
135 DidRepairRange =
false;
139 void SplitAnalysis::analyzeUses() {
140 assert(UseSlots.empty() &&
"Call clear first");
146 UseSlots.push_back(VNI->
def);
158 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
163 if (!calcLiveBlockInfo()) {
166 DidRepairRange =
true;
168 DEBUG(
dbgs() <<
"*** Fixing inconsistent live interval! ***\n");
170 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
172 ThroughBlocks.
clear();
173 bool fixed = calcLiveBlockInfo();
175 assert(fixed &&
"Couldn't fix broken live interval");
179 << UseSlots.size() <<
" instrs in "
180 << UseBlocks.size() <<
" blocks, through "
181 << NumThroughBlocks <<
" blocks.\n");
186 bool SplitAnalysis::calcLiveBlockInfo() {
188 NumThroughBlocks = NumGapBlocks = 0;
196 UseI = UseSlots.begin();
197 UseE = UseSlots.end();
211 if (UseI == UseE || *UseI >= Stop) {
213 ThroughBlocks.
set(BI.MBB->getNumber());
220 BI.FirstInstr = *UseI;
221 assert(BI.FirstInstr >= Start);
223 while (UseI != UseE && *UseI < Stop);
224 BI.LastInstr = UseI[-1];
225 assert(BI.LastInstr < Stop);
228 BI.LiveIn = LVI->start <= Start;
232 assert(LVI->start == LVI->valno->def &&
"Dangling Segment start");
233 assert(LVI->start == BI.FirstInstr &&
"First instr should be a def");
234 BI.FirstDef = BI.FirstInstr;
239 while (LVI->end < Stop) {
241 if (++LVI == LVE || LVI->start >= Stop) {
243 BI.LastInstr = LastStop;
247 if (LastStop < LVI->start) {
254 UseBlocks.push_back(BI);
255 UseBlocks.back().LastInstr = LastStop;
260 BI.FirstInstr = BI.FirstDef = LVI->start;
264 assert(LVI->start == LVI->valno->def &&
"Dangling Segment start");
266 BI.FirstDef = LVI->start;
269 UseBlocks.push_back(BI);
277 if (LVI->end == Stop && ++LVI == LVE)
281 if (LVI->start < Stop)
311 }
while (Stop <= LVI->start);
318 assert(!Orig.
empty() &&
"Splitting empty interval?");
322 if (I != Orig.
end() && I->start <= Idx)
323 return I->start == Idx;
326 return I != Orig.
begin() && (--
I)->
end == Idx;
345 : SA(sa), AA(aa), LIS(lis), VRM(vrm),
346 MRI(vrm.getMachineFunction().getRegInfo()), MDT(mdt),
347 TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
348 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
349 MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
371 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
373 if (RegAssign.
empty()) {
374 dbgs() <<
" empty\n";
379 dbgs() <<
" [" <<
I.start() <<
';' <<
I.stop() <<
"):" <<
I.value();
387 if (S.LaneMask == LM)
404 auto &
PS = getSubRangeForMask(S.LaneMask, Edit->
getParent());
406 if (PV !=
nullptr && PV->def == Def)
417 unsigned R = DefOp.getReg();
420 if (
unsigned SR = DefOp.getSubReg())
428 if ((S.LaneMask & LM).any())
433 VNInfo *SplitEditor::defValue(
unsigned RegIdx,
437 assert(ParentVNI &&
"Mapping NULL value");
445 bool Force = LI->hasSubRanges();
446 ValueForcePair FP(Force ?
nullptr : VNI, Force);
448 std::pair<ValueMap::iterator, bool> InsP =
449 Values.
insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->
id), FP));
453 if (!Force && InsP.second)
457 if (
VNInfo *OldVNI = InsP.first->second.getPointer()) {
458 addDeadDef(*LI, OldVNI, Original);
462 InsP.first->second = ValueForcePair(
nullptr, Force);
466 addDeadDef(*LI, VNI, Original);
470 void SplitEditor::forceRecompute(
unsigned RegIdx,
const VNInfo *ParentVNI) {
471 assert(ParentVNI &&
"Mapping NULL value");
472 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->
id)];
473 VNInfo *VNI = VFP.getPointer();
487 VFP = ValueForcePair(
nullptr,
true);
490 VNInfo *SplitEditor::defFromParent(
unsigned RegIdx,
501 bool Late = RegIdx != 0;
508 bool DidRemat =
false;
529 return defValue(RegIdx, ParentVNI, Def,
false);
539 OpenIdx = Edit->
size();
545 assert(Idx != 0 &&
"Cannot select the complement interval");
546 assert(Idx < Edit->size() &&
"Can only select previously opened interval");
547 DEBUG(
dbgs() <<
" selectIntv " << OpenIdx <<
" -> " << Idx <<
'\n');
552 assert(OpenIdx &&
"openIntv not called before enterIntvBefore");
553 DEBUG(
dbgs() <<
" enterIntvBefore " << Idx);
560 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
562 assert(MI &&
"enterIntvBefore called with invalid index");
569 assert(OpenIdx &&
"openIntv not called before enterIntvAfter");
570 DEBUG(
dbgs() <<
" enterIntvAfter " << Idx);
577 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
579 assert(MI &&
"enterIntvAfter called with invalid index");
587 assert(OpenIdx &&
"openIntv not called before enterIntvAtEnd");
596 DEBUG(
dbgs() <<
": valno " << ParentVNI->id);
597 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
599 RegAssign.
insert(VNI->
def, End, OpenIdx);
610 assert(OpenIdx &&
"openIntv not called before useIntv");
611 DEBUG(
dbgs() <<
" useIntv [" << Start <<
';' << End <<
"):");
612 RegAssign.
insert(Start, End, OpenIdx);
617 assert(OpenIdx &&
"openIntv not called before leaveIntvAfter");
618 DEBUG(
dbgs() <<
" leaveIntvAfter " << Idx);
627 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
629 assert(MI &&
"No instruction at index");
637 forceRecompute(0, ParentVNI);
638 defFromParent(0, ParentVNI, Idx, *MI->
getParent(),
MI);
648 assert(OpenIdx &&
"openIntv not called before leaveIntvBefore");
649 DEBUG(
dbgs() <<
" leaveIntvBefore " << Idx);
658 DEBUG(
dbgs() <<
": valno " << ParentVNI->
id <<
'\n');
661 assert(MI &&
"No instruction at index");
667 assert(OpenIdx &&
"openIntv not called before leaveIntvAtTop");
677 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
679 RegAssign.
insert(Start, VNI->
def, OpenIdx);
685 assert(OpenIdx &&
"openIntv not called before overlapIntv");
688 "Parent changes value in extended range");
690 "Range cannot span basic blocks");
694 forceRecompute(0, ParentVNI);
695 DEBUG(
dbgs() <<
" overlapIntv [" << Start <<
';' << End <<
"):");
696 RegAssign.
insert(Start, End, OpenIdx);
706 DEBUG(
dbgs() <<
"Removing " << Copies.
size() <<
" back-copies.\n");
708 AssignI.setMap(RegAssign);
710 for (
unsigned i = 0, e = Copies.
size();
i != e; ++
i) {
713 assert(MI &&
"No instruction for back-copy");
718 do AtBegin = MBBI == MBB->
begin();
719 while (!AtBegin && (--MBBI)->isDebugValue());
721 DEBUG(
dbgs() <<
"Removing " << Def <<
'\t' << *MI);
729 if (!AssignI.valid() || AssignI.start() >=
Def)
732 if (AssignI.stop() !=
Def)
734 unsigned RegIdx = AssignI.value();
735 if (AtBegin || !MBBI->readsVirtualRegister(Edit->
getReg())) {
736 DEBUG(
dbgs() <<
" cannot find simple kill of RegIdx " << RegIdx <<
'\n');
740 DEBUG(
dbgs() <<
" move kill to " << Kill <<
'\t' << *MBBI);
741 AssignI.setStop(Kill);
751 assert(MDT.
dominates(DefMBB, MBB) &&
"MBB must be dominated by the def.");
754 const MachineLoop *DefLoop = Loops.getLoopFor(DefMBB);
759 unsigned BestDepth = UINT_MAX;
773 if (Loop == DefLoop) {
775 << MBB->
getNumber() <<
" in the same loop\n");
781 if (Depth < BestDepth) {
785 << MBB->
getNumber() <<
" at depth " << Depth <<
'\n');
793 if (!IDom || !MDT.
dominates(DefDomNode, IDom))
800 void SplitEditor::computeRedundantBackCopies(
812 EqualVNs[ParentVNI->
id].insert(VNI);
819 if (!NotToHoistSet.
count(ParentVNI->
id))
823 for (; It1 != EqualVNs[ParentVNI->
id].end(); ++It1) {
825 for (++It2; It2 != EqualVNs[ParentVNI->
id].end(); ++It2) {
826 if (DominatedVNIs.count(*It1) || DominatedVNIs.count(*It2))
832 DominatedVNIs.
insert((*It1)->def < (*It2)->def ? (*It2) : (*It1));
834 DominatedVNIs.
insert(*It2);
836 DominatedVNIs.
insert(*It1);
840 if (!DominatedVNIs.
empty()) {
841 forceRecompute(0, ParentVNI);
842 for (
auto VNI : DominatedVNIs) {
845 DominatedVNIs.clear();
855 void SplitEditor::hoistCopies() {
862 typedef std::pair<MachineBasicBlock*, SlotIndex> DomPair;
876 assert(ParentVNI &&
"Parent not live at complement def");
885 DomPair &Dom = NearestDom[ParentVNI->
id];
890 if (VNI->
def == ParentVNI->
def) {
891 DEBUG(
dbgs() <<
"Direct complement def at " << VNI->
def <<
'\n');
892 Dom = DomPair(ValMBB, VNI->
def);
897 if (Values.
lookup(std::make_pair(0, ParentVNI->
id)).getPointer()) {
898 DEBUG(
dbgs() <<
"Single complement def at " << VNI->
def <<
'\n');
904 Dom = DomPair(ValMBB, VNI->
def);
905 }
else if (Dom.first == ValMBB) {
907 if (!Dom.second.isValid() || VNI->
def < Dom.second)
908 Dom.second = VNI->
def;
915 Dom = DomPair(ValMBB, VNI->
def);
916 else if (Near != Dom.first)
922 DEBUG(
dbgs() <<
"Multi-mapped complement " << VNI->
id <<
'@' << VNI->
def
923 <<
" for parent " << ParentVNI->
id <<
'@' << ParentVNI->
def
924 <<
" hoist to BB#" << Dom.first->getNumber() <<
' '
925 << Dom.second <<
'\n');
930 DomPair &Dom = NearestDom[
i];
931 if (!Dom.first || Dom.second.isValid())
937 Dom.first = findShallowDominator(Dom.first, DefMBB);
940 NotToHoistSet.
insert(ParentVNI->
id);
945 defFromParent(0, ParentVNI, Last, *Dom.first,
956 const DomPair &Dom = NearestDom[ParentVNI->
id];
957 if (!Dom.first || Dom.second == VNI->
def ||
958 NotToHoistSet.count(ParentVNI->
id))
961 forceRecompute(0, ParentVNI);
967 computeRedundantBackCopies(NotToHoistSet, BackCopies);
969 removeBackCopies(BackCopies);
975 bool SplitEditor::transferValues() {
976 bool Skipped =
false;
980 VNInfo *ParentVNI = S.valno;
983 AssignI.advanceTo(Start);
987 if (!AssignI.valid()) {
989 }
else if (AssignI.start() <= Start) {
990 RegIdx = AssignI.value();
991 if (AssignI.stop() <
End) {
992 End = AssignI.stop();
997 End =
std::min(End, AssignI.start());
1001 DEBUG(
dbgs() <<
" [" << Start <<
';' << End <<
")=" << RegIdx
1006 ValueForcePair VFP = Values.
lookup(std::make_pair(RegIdx, ParentVNI->
id));
1007 if (
VNInfo *VNI = VFP.getPointer()) {
1009 LI.
addSegment(LiveInterval::Segment(Start, End, VNI));
1032 if (Start != BlockStart) {
1034 assert(VNI &&
"Missing def for complex mapped value");
1035 DEBUG(
dbgs() <<
':' << VNI->
id <<
"*BB#" << MBB->getNumber());
1037 if (BlockEnd <= End)
1042 BlockStart = BlockEnd;
1046 assert(Start <= BlockStart &&
"Expected live-in block");
1047 while (BlockStart < End) {
1048 DEBUG(
dbgs() <<
">BB#" << MBB->getNumber());
1050 if (BlockStart == ParentVNI->
def) {
1052 assert(ParentVNI->
isPHIDef() &&
"Non-phi defined at block start?");
1054 assert(VNI &&
"Missing def for complex mapped parent PHI");
1055 if (End >= BlockEnd)
1068 BlockStart = BlockEnd;
1072 }
while (Start != S.end);
1105 LiveRange &PSR = !LM.
all() ? getSubRangeForMask(LM, PLI)
1108 LRC.
extend(LR, End, 0, Undefs);
1112 void SplitEditor::extendPHIKillRanges() {
1124 unsigned RegIdx = RegAssign.
lookup(V->
def);
1136 for (
const VNInfo *V :
PS.valnos) {
1139 unsigned RegIdx = RegAssign.
lookup(V->
def);
1150 extendPHIRange(B, SubLRC, S,
PS.LaneMask, Undefs);
1156 void SplitEditor::rewriteAssigned(
bool ExtendRanges) {
1159 : MO(O), RegIdx(R), Next(N) {}
1168 RE = MRI.
reg_end(); RI != RE;) {
1187 unsigned RegIdx = RegAssign.
lookup(Idx);
1191 << Idx <<
':' << RegIdx <<
'\t' << *
MI);
1194 if (!ExtendRanges || MO.
isUndef())
1216 ExtPoints.
push_back(ExtPoint(MO, RegIdx, Next));
1223 for (ExtPoint &EP : ExtPoints) {
1228 unsigned Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
1245 SubLRC.extend(S, EP.
Next, 0, Undefs);
1249 for (
unsigned R : *Edit) {
1259 void SplitEditor::deleteRematVictims() {
1270 assert(MI &&
"Missing instruction for dead def");
1276 DEBUG(
dbgs() <<
"All defs dead: " << *MI);
1284 Edit->eliminateDeadDefs(Dead,
None, &AA);
1294 for (
const VNInfo *ParentVNI : Edit->getParent().valnos) {
1297 unsigned RegIdx = RegAssign.
lookup(ParentVNI->
def);
1298 defValue(RegIdx, ParentVNI, ParentVNI->
def,
true);
1302 if (Edit->didRematerialize(ParentVNI))
1303 for (
unsigned i = 0, e = Edit->size();
i != e; ++
i)
1304 forceRecompute(
i, ParentVNI);
1308 switch (SpillMode) {
1319 bool Skipped = transferValues();
1322 rewriteAssigned(Skipped);
1325 extendPHIKillRanges();
1331 deleteRematVictims();
1334 for (
unsigned Reg : *Edit) {
1343 for (
unsigned i = 0, e = Edit->size();
i != e; ++
i)
1349 for (
unsigned i = 0, e = Edit->size();
i != e; ++
i) {
1351 unsigned VReg = Edit->get(
i);
1361 LRMap->
resize(Edit->size(),
i);
1367 assert(!LRMap || LRMap->
size() == Edit->size());
1376 bool SingleInstrs)
const {
1422 unsigned IntvOut,
SlotIndex EnterAfter){
1426 DEBUG(
dbgs() <<
"BB#" << MBBNum <<
" [" << Start <<
';' << Stop
1427 <<
") intf " << LeaveBefore <<
'-' << EnterAfter
1428 <<
", live-through " << IntvIn <<
" -> " << IntvOut);
1430 assert((IntvIn || IntvOut) &&
"Use splitSingleBlock for isolated blocks");
1432 assert((!LeaveBefore || LeaveBefore < Stop) &&
"Interference after block");
1433 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) &&
"Impossible intf");
1434 assert((!EnterAfter || EnterAfter >= Start) &&
"Interference before block");
1447 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1461 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1466 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
1467 DEBUG(
dbgs() <<
", straight through.\n");
1479 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) &&
"Impossible intf");
1481 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
1483 DEBUG(
dbgs() <<
", switch avoiding interference.\n");
1491 if (LeaveBefore && LeaveBefore < LSP) {
1499 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1500 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1504 DEBUG(
dbgs() <<
", create local intv for interference.\n");
1510 assert(LeaveBefore <= EnterAfter &&
"Missed case");
1515 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1520 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1525 unsigned IntvIn,
SlotIndex LeaveBefore) {
1531 <<
", reg-in " << IntvIn <<
", leave before " << LeaveBefore
1532 << (BI.
LiveOut ?
", stack-out" :
", killed in block"));
1534 assert(IntvIn &&
"Must have register in");
1536 assert((!LeaveBefore || LeaveBefore > Start) &&
"Bad interference");
1539 DEBUG(
dbgs() <<
" before interference.\n");
1564 DEBUG(
dbgs() <<
", spill after last use before interference.\n");
1568 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1570 DEBUG(
dbgs() <<
", spill before last split point.\n");
1575 assert((!LeaveBefore || Idx <= LeaveBefore) &&
"Interference");
1585 DEBUG(
dbgs() <<
", creating local interval " << LocalIntv <<
".\n");
1598 assert((!LeaveBefore || From <= LeaveBefore) &&
"Interference");
1613 assert((!LeaveBefore || From <= LeaveBefore) &&
"Interference");
1617 unsigned IntvOut,
SlotIndex EnterAfter) {
1623 <<
", reg-out " << IntvOut <<
", enter after " << EnterAfter
1624 << (BI.
LiveIn ?
", stack-in" :
", defined in block"));
1628 assert(IntvOut &&
"Must have register out");
1630 assert((!EnterAfter || EnterAfter < LSP) &&
"Bad interference");
1633 DEBUG(
dbgs() <<
" after interference.\n");
1645 DEBUG(
dbgs() <<
", reload after interference.\n");
1654 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
1661 DEBUG(
dbgs() <<
", interference overlaps uses.\n");
1670 assert((!EnterAfter || Idx >= EnterAfter) &&
"Interference");
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
ValT lookup(KeyT x, ValT NotFound=ValT()) const
lookup - Return the mapped value at x or NotFound.
void push_back(const T &Elt)
const_iterator end(StringRef path)
Get end iterator over path.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const_iterator begin() const
SlotIndex def
The index of the defining instruction.
STATISTIC(NumFunctions,"Total number of functions")
void RemoveMachineInstrFromMaps(MachineInstr &MI)
bool anyRematerializable(AliasAnalysis *)
anyRematerializable - Return true if any parent values may be rematerializable.
ValueT lookup(const KeyT &Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
MachineFunction & getMachineFunction() const
void reset(LiveRangeEdit &, ComplementSpillMode=SM_Partition)
reset - Prepare for a new split.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
SlotIndex getLastSplitPoint(unsigned Num)
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI)
setLiveOutValue - Indicate that VNI is live out from MBB.
Implements a dense probed hash-table based set.
static LaneBitmask getAll()
LiveInterval - This class represents the liveness of a register, or stack slot.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
SM_Speed - Overlap intervals to minimize the expected execution frequency of the inserted copies...
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
const MachineLoopInfo & Loops
ComplementSpillMode
ComplementSpillMode - Select how the complement live range should be created.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
A live range for subregisters.
This represents a simple continuous liveness interval for a value.
SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis, const MachineLoopInfo &mli)
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
friend class const_iterator
SlotIndex enterIntvAtEnd(MachineBasicBlock &MBB)
enterIntvAtEnd - Enter the open interval at the end of MBB.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
VNInfo - Value Number Information.
bool didRematerialize(const VNInfo *ParentVNI) const
didRematerialize - Return true if ParentVNI was rematerialized anywhere.
unsigned getNumValNums() const
void splitRegInBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvIn, SlotIndex LeaveBefore)
splitRegInBlock - Split CurLI in the given block such that it enters the block in IntvIn and leaves i...
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
BlockT * getHeader() const
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
iterator_range< succ_iterator > successors()
This class represents the liveness of a register, stack slot, etc.
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
void analyze(const LiveInterval *li)
analyze - set CurLI to the specified interval, and analyze how it may be split.
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
void clear()
clear - Clear all bits.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
void splitSingleBlock(const SplitAnalysis::BlockInfo &BI)
splitSingleBlock - Split CurLI into a separate live interval around the uses in a single block...
const HexagonInstrInfo * TII
SlotIndex getLastInsertPoint(const LiveInterval &CurLI, const MachineBasicBlock &MBB)
Return the base index of the last valid insert point for in .
VNInfo::Allocator & getVNInfoAllocator()
iterator_range< subrange_iterator > subranges()
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
SmallVectorImpl< unsigned >::const_iterator iterator
Iterator for accessing the new registers added by this edit.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Reg
All possible values of the reg field in the ModR/M byte.
void overlapIntv(SlotIndex Start, SlotIndex End)
overlapIntv - Indicate that all instructions in range should use the open interval, but also let the complement interval be live.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
unsigned openIntv()
Create a new virtual register and live interval.
LLVM_NODISCARD bool empty() const
bool isUnused() const
Returns true if this value is unused.
bool shouldSplitSingleBlock(const BlockInfo &BI, bool SingleInstrs) const
shouldSplitSingleBlock - Returns true if it would help to create a local live range for the instructi...
bool empty() const
empty - Return true when no intervals are mapped.
SlotIndex leaveIntvAfter(SlotIndex Idx)
leaveIntvAfter - Leave the open interval after the instruction at Idx.
SplitEditor(SplitAnalysis &SA, AliasAnalysis &AA, LiveIntervals &, VirtRegMap &, MachineDominatorTree &, MachineBlockFrequencyInfo &)
Create a new SplitEditor for editing the LiveInterval analyzed by SA.
void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill=SlotIndex())
addLiveInBlock - Add a block with an unknown live-in value.
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
void setIsSplitFromReg(unsigned virtReg, unsigned SReg)
records virtReg is a split live interval from SReg.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
Base class for the actual dominator tree node.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
void clear()
clear - Remove all entries.
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
const LiveIntervals & LIS
void finish(SmallVectorImpl< unsigned > *LRMap=nullptr)
finish - after all the new live ranges have been created, compute the remaining live range...
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B...
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
void dump() const
dump - print the current interval mapping to dbgs().
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
SlotIndex LastInstr
Last instr accessing current reg.
unsigned get(unsigned idx) const
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
MachineBasicBlock::iterator getLastInsertPointIter(const LiveInterval &CurLI, MachineBasicBlock &MBB)
Returns the last insert point as an iterator for in .
const MachineBasicBlock * getParent() const
bool isDebugValue() const
bool isEarlyClobber() const
void reset(const MachineFunction *MF, SlotIndexes *, MachineDominatorTree *, VNInfo::Allocator *)
reset - Prepare caches for a new set of non-overlapping live ranges.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
SlotIndexes * getSlotIndexes() const
bool isValid() const
Returns true if this is a valid index.
void useIntv(const MachineBasicBlock &MBB)
useIntv - indicate that all instructions in MBB should use OpenLI.
bool isOneInstr() const
isOneInstr - Returns true when this BlockInfo describes a single instruction.
unsigned const MachineRegisterInfo * MRI
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Use)
Attempt to extend a value defined after StartIdx to include Use.
unsigned getOriginal(unsigned VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting...
SM_Partition(Default) - Try to create the complement interval so it doesn't overlap any other interva...
SM_Size - Overlap intervals to minimize the number of inserted COPY instructions. ...
Greedy Register Allocator
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
static const unsigned End
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
self_iterator getIterator()
LiveInterval & getParent() const
iterator_range< pred_iterator > predecessors()
SlotIndex leaveIntvAtTop(MachineBasicBlock &MBB)
leaveIntvAtTop - Leave the interval at the top of MBB.
unsigned getSubReg() const
void selectIntv(unsigned Idx)
selectIntv - Select a previously opened interval index.
bool liveAt(SlotIndex index) const
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void insert(KeyT a, KeyT b, ValT y)
insert - Add a mapping of [a;b] to y, coalesce with adjacent intervals.
void splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvOut, SlotIndex EnterAfter)
splitRegOutBlock - Split CurLI in the given block such that it enters the block on the stack (or isn'...
MachineBasicBlock::iterator getLastSplitPointIter(MachineBasicBlock *BB)
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
SmallPtrSetIterator - This implements a const_iterator for SmallPtrSet.
unsigned id
The ID number of this value.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Segments::const_iterator const_iterator
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
const MachineFunction & MF
unsigned getNumLiveBlocks() const
getNumLiveBlocks - Return the number of blocks where CurLI is live.
SlotIndex FirstInstr
First instr accessing current reg.
SlotIndex leaveIntvBefore(SlotIndex Idx)
leaveIntvBefore - Leave the open interval before the instruction at Idx.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Additional information about basic blocks where the current variable is live.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
SplitAnalysis - Analyze a LiveInterval, looking for live range splitting opportunities.
LiveInterval & getInterval(unsigned Reg)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool LiveOut
Current reg is live out.
iterator insert(iterator I, T &&Elt)
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void clear()
clear - clear all data structures so SplitAnalysis is ready to analyze a new interval.
Representation of each machine instruction.
void splitLiveThroughBlock(unsigned MBBNum, unsigned IntvIn, SlotIndex LeaveBefore, unsigned IntvOut, SlotIndex EnterAfter)
splitLiveThroughBlock - Split CurLI in the given block such that it enters the block in IntvIn and le...
InsertPointAnalysis(const LiveIntervals &lis, unsigned BBNum)
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
size_type count(const ValueT &V) const
Return 1 if the specified key is in the set, 0 otherwise.
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
Represents a single loop in the control flow graph.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
SlotIndex enterIntvBefore(SlotIndex Idx)
enterIntvBefore - Enter the open interval before the instruction at Idx.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
constexpr bool all() const
static bool removeDeadSegment(SlotIndex Def, LiveRange &LR)
Remat - Information needed to rematerialize at a specific location.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned countLiveBlocks(const LiveInterval *li) const
countLiveBlocks - Return the number of blocks where li is live.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
LiveInterval & createEmptyInterval()
create - Create a new register with the same class and original slot as parent.
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
iterator SkipPHIsLabelsAndDebug(iterator I)
Return the first instruction in MBB after I that is not a PHI, label or debug.
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
reg_iterator reg_begin(unsigned RegNo) const
SlotIndex enterIntvAfter(SlotIndex Idx)
enterIntvAfter - Enter the open interval after the instruction at Idx.
SlotIndex getNextSlot() const
Returns the next slot in the index list.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
static reg_iterator reg_end()
bool LiveIn
Current reg is live in.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
SlotIndex - An opaque wrapper around machine indexes.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
unsigned getLoopDepth() const
Return the nesting level of this loop.
void calculateValues()
calculateValues - Calculate the value that will be live-in to each block added with addLiveInBlock...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isOriginalEndpoint(SlotIndex Idx) const
isOriginalEndpoint - Return true if the original live range was killed or (re-)defined at Idx...
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.