27 #define DEBUG_TYPE "mips-disassembler"
40 IsBigEndian(IsBigEndian) {}
42 bool hasMips2()
const {
return STI.
getFeatureBits()[Mips::FeatureMips2]; }
43 bool hasMips3()
const {
return STI.
getFeatureBits()[Mips::FeatureMips3]; }
44 bool hasMips32()
const {
return STI.
getFeatureBits()[Mips::FeatureMips32]; }
45 bool hasMips32r6()
const {
48 bool isFP64()
const {
return STI.
getFeatureBits()[Mips::FeatureFP64Bit]; }
50 bool isGP64()
const {
return STI.
getFeatureBits()[Mips::FeatureGP64Bit]; }
52 bool isPTR64()
const {
return STI.
getFeatureBits()[Mips::FeaturePTR64Bit]; }
54 bool hasCnMips()
const {
return STI.
getFeatureBits()[Mips::FeatureCnMips]; }
56 bool hasCOP3()
const {
58 return !hasMips32() && !hasMips3();
104 const void *Decoder);
109 const void *Decoder);
114 const void *Decoder);
119 const void *Decoder);
124 const void *Decoder);
129 const void *Decoder);
133 const void *Decoder);
138 const void *Decoder);
143 const void *Decoder);
148 const void *Decoder);
153 const void *Decoder);
158 const void *Decoder);
163 const void *Decoder);
168 const void *Decoder);
173 const void *Decoder);
178 const void *Decoder);
183 const void *Decoder);
188 const void *Decoder);
193 const void *Decoder);
198 const void *Decoder);
203 const void *Decoder);
208 const void *Decoder);
213 const void *Decoder);
218 const void *Decoder);
223 const void *Decoder);
230 const void *Decoder);
237 const void *Decoder);
244 const void *Decoder);
251 const void *Decoder);
258 const void *Decoder);
263 const void *Decoder);
268 const void *Decoder);
273 const void *Decoder);
278 const void *Decoder);
283 const void *Decoder);
288 const void *Decoder);
293 const void *Decoder);
298 const void *Decoder);
303 const void *Decoder);
308 const void *Decoder);
313 const void *Decoder);
316 uint64_t
Address,
const void *Decoder);
321 const void *Decoder);
326 const void *Decoder);
331 const void *Decoder);
336 const void *Decoder);
341 const void *Decoder);
346 const void *Decoder);
351 const void *Decoder);
355 const void *Decoder);
359 const void *Decoder);
363 const void *Decoder);
367 const void *Decoder);
371 const void *Decoder);
375 const void *Decoder);
380 const void *Decoder);
385 const void *Decoder);
390 const void *Decoder);
395 const void *Decoder);
397 template <
unsigned Bits,
int Offset,
int Scale>
400 const void *Decoder);
402 template <
unsigned Bits,
int Offset>
405 const void *Decoder) {
406 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value,
Address,
410 template <
unsigned Bits,
int Offset = 0,
int ScaleBy = 1>
413 const void *Decoder);
418 const void *Decoder);
421 uint64_t
Address,
const void *Decoder);
424 uint64_t
Address,
const void *Decoder);
427 uint64_t
Address,
const void *Decoder);
430 uint64_t
Address,
const void *Decoder);
433 uint64_t
Address,
const void *Decoder);
437 template <
typename InsnType>
439 const void *Decoder);
441 template <
typename InsnType>
443 const void *Decoder);
445 template <
typename InsnType>
447 const void *Decoder);
449 template <
typename InsnType>
451 const void *Decoder);
453 template <
typename InsnType>
455 const void *Decoder);
457 template <
typename InsnType>
460 const void *Decoder);
462 template <
typename InsnType>
465 const void *Decoder);
467 template <
typename InsnType>
470 const void *Decoder);
472 template <
typename InsnType>
475 const void *Decoder);
477 template <
typename InsnType>
480 const void *Decoder);
482 template <
typename InsnType>
485 const void *Decoder);
487 template <
typename InsnType>
490 const void *Decoder);
492 template <
typename InsnType>
495 const void *Decoder);
497 template <
typename InsnType>
500 const void *Decoder);
502 template <
typename InsnType>
505 const void *Decoder);
507 template <
typename InsnType>
510 const void *Decoder);
512 template <
typename InsnType>
515 const void *Decoder);
519 const void *Decoder);
523 const void *Decoder);
527 const void *Decoder);
540 return new MipsDisassembler(STI, Ctx,
true);
547 return new MipsDisassembler(STI, Ctx,
false);
562 #include "MipsGenDisassemblerTables.inc"
564 static unsigned getReg(
const void *
D,
unsigned RC,
unsigned RegNo) {
565 const MipsDisassembler *Dis =
static_cast<const MipsDisassembler*
>(
D);
566 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
570 template <
typename InsnType>
572 const void *Decoder) {
576 InsnType tmp = fieldFromInstruction(insn, 17, 5);
578 DecodeFN RegDecoder =
nullptr;
579 if ((tmp & 0x18) == 0x00) {
582 }
else if ((tmp & 0x1c) == 0x10) {
585 }
else if ((tmp & 0x1e) == 0x18) {
588 }
else if ((tmp & 0x1f) == 0x1c) {
594 assert(NSize != 0 && RegDecoder !=
nullptr);
597 tmp = fieldFromInstruction(insn, 6, 5);
604 tmp = fieldFromInstruction(insn, 16, NSize);
607 tmp = fieldFromInstruction(insn, 11, 5);
616 template <
typename InsnType>
618 const void *Decoder) {
619 InsnType Rs = fieldFromInstruction(insn, 16, 5);
620 InsnType Imm = fieldFromInstruction(insn, 0, 16);
630 template <
typename InsnType>
632 const void *Decoder) {
633 InsnType Rs = fieldFromInstruction(insn, 21, 5);
634 InsnType Imm = fieldFromInstruction(insn, 0, 16);
644 template <
typename InsnType>
647 const void *Decoder) {
658 InsnType Rs = fieldFromInstruction(insn, 21, 5);
659 InsnType Rt = fieldFromInstruction(insn, 16, 5);
660 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
666 }
else if (Rs != 0 && Rs < Rt) {
683 template <
typename InsnType>
686 const void *Decoder) {
687 InsnType Rt = fieldFromInstruction(insn, 21, 5);
688 InsnType Rs = fieldFromInstruction(insn, 16, 5);
697 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
698 }
else if (Rs != 0 && Rs < Rt) {
704 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
709 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
717 template <
typename InsnType>
720 const void *Decoder) {
731 InsnType Rs = fieldFromInstruction(insn, 21, 5);
732 InsnType Rt = fieldFromInstruction(insn, 16, 5);
733 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
739 }
else if (Rs != 0 && Rs < Rt) {
756 template <
typename InsnType>
759 const void *Decoder) {
760 InsnType Rt = fieldFromInstruction(insn, 21, 5);
761 InsnType Rs = fieldFromInstruction(insn, 16, 5);
770 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
771 }
else if (Rs != 0 && Rs < Rt) {
777 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
782 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
790 template <
typename InsnType>
793 const void *Decoder) {
801 InsnType Rt = fieldFromInstruction(insn, 21, 5);
802 InsnType Rs = fieldFromInstruction(insn, 16, 5);
803 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
829 template <
typename InsnType>
832 const void *Decoder) {
840 InsnType Rt = fieldFromInstruction(insn, 21, 5);
841 InsnType Rs = fieldFromInstruction(insn, 16, 5);
842 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
868 template <
typename InsnType>
871 const void *Decoder) {
883 InsnType Rs = fieldFromInstruction(insn, 21, 5);
884 InsnType Rt = fieldFromInstruction(insn, 16, 5);
885 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
911 template <
typename InsnType>
914 const void *Decoder) {
928 InsnType Rs = fieldFromInstruction(insn, 21, 5);
929 InsnType Rt = fieldFromInstruction(insn, 16, 5);
930 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
955 template <
typename InsnType>
958 const void *Decoder) {
970 InsnType Rs = fieldFromInstruction(insn, 21, 5);
971 InsnType Rt = fieldFromInstruction(insn, 16, 5);
972 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
979 }
else if (Rs == 0) {
982 }
else if (Rs == Rt) {
1004 template <
typename InsnType>
1007 const void *Decoder) {
1019 InsnType Rs = fieldFromInstruction(insn, 21, 5);
1020 InsnType Rt = fieldFromInstruction(insn, 16, 5);
1021 int64_t Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
1052 if (Bytes.
size() < 2) {
1058 Insn = (Bytes[0] << 8) | Bytes[1];
1060 Insn = (Bytes[1] << 8) | Bytes[0];
1070 bool IsBigEndian,
bool IsMicroMips) {
1072 if (Bytes.
size() < 4) {
1088 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
1091 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
1094 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
1115 if (hasMips32r6()) {
1116 DEBUG(
dbgs() <<
"Trying MicroMipsR616 table (16-bit instructions):\n");
1120 Address,
this, STI);
1127 DEBUG(
dbgs() <<
"Trying MicroMips16 table (16-bit instructions):\n");
1141 if (hasMips32r6()) {
1142 DEBUG(
dbgs() <<
"Trying MicroMips32r632 table (32-bit instructions):\n");
1152 DEBUG(
dbgs() <<
"Trying MicroMips32 table (32-bit instructions):\n");
1161 if (hasMips32r6() && isFP64()) {
1162 DEBUG(
dbgs() <<
"Trying MicroMips32r6FP64 table (32-bit opcodes):\n");
1164 Address,
this, STI);
1184 DEBUG(
dbgs() <<
"Trying COP3_ table (32-bit opcodes):\n");
1193 if (hasMips32r6() && isGP64()) {
1194 DEBUG(
dbgs() <<
"Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
1196 Address,
this, STI);
1203 if (hasMips32r6() && isPTR64()) {
1204 DEBUG(
dbgs() <<
"Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1206 Address,
this, STI);
1213 if (hasMips32r6()) {
1214 DEBUG(
dbgs() <<
"Trying Mips32r6_64r6 table (32-bit opcodes):\n");
1216 Address,
this, STI);
1223 if (hasMips2() && isPTR64()) {
1224 DEBUG(
dbgs() <<
"Trying Mips32r6_64r6 (PTR64) table (32-bit opcodes):\n");
1226 Address,
this, STI);
1234 DEBUG(
dbgs() <<
"Trying CnMips table (32-bit opcodes):\n");
1236 Address,
this, STI);
1244 DEBUG(
dbgs() <<
"Trying Mips64 (GPR64) table (32-bit opcodes):\n");
1246 Address,
this, STI);
1253 DEBUG(
dbgs() <<
"Trying Mips table (32-bit opcodes):\n");
1269 const void *Decoder) {
1278 const void *Decoder) {
1283 unsigned Reg =
getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1291 const void *Decoder) {
1294 unsigned Reg =
getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1302 const void *Decoder) {
1305 unsigned Reg =
getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1313 const void *Decoder) {
1316 unsigned Reg =
getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1324 const void *Decoder) {
1327 unsigned Reg =
getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1335 const void *Decoder) {
1336 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1345 const void *Decoder) {
1352 const void *Decoder) {
1356 unsigned Reg =
getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1364 const void *Decoder) {
1368 unsigned Reg =
getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1376 const void *Decoder) {
1379 unsigned Reg =
getReg(Decoder, Mips::CCRRegClassID, RegNo);
1387 const void *Decoder) {
1390 unsigned Reg =
getReg(Decoder, Mips::FCCRegClassID, RegNo);
1397 const void *Decoder) {
1401 unsigned Reg =
getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1409 const void *Decoder) {
1410 int Offset = SignExtend32<16>(Insn & 0xffff);
1411 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1412 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1414 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1415 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1431 const void *Decoder) {
1432 int Offset = SignExtend32<9>(Insn >> 7);
1433 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1434 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1436 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1437 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1452 const void *Decoder) {
1453 int Offset = SignExtend32<9>(Insn & 0x1ff);
1454 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1455 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1457 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1458 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1470 const void *Decoder) {
1471 int Offset = SignExtend32<16>(Insn & 0xffff);
1472 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1473 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1475 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1476 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1488 const void *Decoder) {
1489 int Offset = SignExtend32<16>(Insn & 0xffff);
1490 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1491 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1493 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1505 const void *Decoder) {
1506 int Offset = SignExtend32<12>(Insn & 0xfff);
1507 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1508 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1510 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1522 const void *Decoder) {
1523 int Offset = SignExtend32<9>(Insn & 0x1ff);
1524 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1525 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1527 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1539 const void *Decoder) {
1540 int Offset = SignExtend32<9>(Insn >> 7);
1541 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1542 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1544 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1556 const void *Decoder) {
1557 int Offset = SignExtend32<9>(Insn & 0x1ff);
1558 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1559 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1561 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1562 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1574 const void *Decoder) {
1575 int Offset = SignExtend32<16>(Insn & 0xffff);
1576 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1578 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1589 const void *Decoder) {
1590 int Immediate = SignExtend32<16>(Insn & 0xffff);
1591 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1593 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1602 uint64_t Address,
const void *Decoder) {
1603 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1604 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1605 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1607 Reg =
getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1608 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1623 assert (0 &&
"Unexpected instruction");
1650 const void *Decoder) {
1651 unsigned Offset = Insn & 0xf;
1652 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1653 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1656 case Mips::LBU16_MM:
1657 case Mips::LHU16_MM:
1664 case Mips::SB16_MMR6:
1666 case Mips::SH16_MMR6:
1668 case Mips::SW16_MMR6:
1680 case Mips::LBU16_MM:
1687 case Mips::SB16_MMR6:
1690 case Mips::LHU16_MM:
1692 case Mips::SH16_MMR6:
1697 case Mips::SW16_MMR6:
1708 const void *Decoder) {
1709 unsigned Offset = Insn & 0x1F;
1710 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1712 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1724 const void *Decoder) {
1725 unsigned Offset = Insn & 0x7F;
1726 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1728 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1740 const void *Decoder) {
1743 case Mips::LWM16_MMR6:
1744 case Mips::SWM16_MMR6:
1745 Offset = fieldFromInstruction(Insn, 4, 4);
1748 Offset = SignExtend32<4>(Insn & 0xf);
1765 const void *Decoder) {
1766 int Offset = SignExtend32<9>(Insn & 0x1ff);
1767 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1768 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1770 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1771 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1786 const void *Decoder) {
1787 int Offset = SignExtend32<12>(Insn & 0x0fff);
1788 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1789 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1791 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1792 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1795 case Mips::SWM32_MM:
1796 case Mips::LWM32_MM:
1822 const void *Decoder) {
1823 int Offset = SignExtend32<16>(Insn & 0xffff);
1824 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1825 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1827 Reg =
getReg(Decoder, Mips::GPR32RegClassID, Reg);
1828 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1840 const void *Decoder) {
1841 int Offset = SignExtend32<16>(Insn & 0xffff);
1842 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1843 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1845 Reg =
getReg(Decoder, Mips::FGR64RegClassID, Reg);
1846 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1856 uint64_t Address,
const void *Decoder) {
1859 int Offset = SignExtend32<16>(Insn & 0xffff);
1860 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1861 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1863 Reg =
getReg(Decoder, Mips::FGR64RegClassID, Reg);
1864 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1876 const void *Decoder) {
1877 int Offset = SignExtend32<16>(Insn & 0xffff);
1878 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1879 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1881 Reg =
getReg(Decoder, Mips::COP2RegClassID, Reg);
1882 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1894 const void *Decoder) {
1895 int Offset = SignExtend32<16>(Insn & 0xffff);
1896 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1897 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1899 Reg =
getReg(Decoder, Mips::COP3RegClassID, Reg);
1900 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1912 const void *Decoder) {
1913 int Offset = SignExtend32<11>(Insn & 0x07ff);
1914 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1915 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1917 Reg =
getReg(Decoder, Mips::COP2RegClassID, Reg);
1918 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1928 uint64_t Address,
const void *Decoder) {
1929 int Offset = SignExtend32<11>(Insn & 0x07ff);
1930 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1931 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1933 Reg =
getReg(Decoder, Mips::COP2RegClassID, Reg);
1934 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1946 const void *Decoder) {
1947 int64_t
Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1948 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1949 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1951 Rt =
getReg(Decoder, Mips::GPR32RegClassID, Rt);
1952 Base =
getReg(Decoder, Mips::GPR32RegClassID, Base);
1968 const void *Decoder) {
1979 const void *Decoder) {
1980 if (RegNo > 30 || RegNo %2)
1984 unsigned Reg =
getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1992 const void *Decoder) {
1996 unsigned Reg =
getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
2004 const void *Decoder) {
2008 unsigned Reg =
getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
2016 const void *Decoder) {
2020 unsigned Reg =
getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
2028 const void *Decoder) {
2032 unsigned Reg =
getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
2040 const void *Decoder) {
2044 unsigned Reg =
getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
2052 const void *Decoder) {
2056 unsigned Reg =
getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
2064 const void *Decoder) {
2068 unsigned Reg =
getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
2076 const void *Decoder) {
2080 unsigned Reg =
getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
2088 const void *Decoder) {
2092 unsigned Reg =
getReg(Decoder, Mips::COP0RegClassID, RegNo);
2100 const void *Decoder) {
2104 unsigned Reg =
getReg(Decoder, Mips::COP2RegClassID, RegNo);
2112 const void *Decoder) {
2113 int32_t BranchOffset = (SignExtend32<16>(
Offset) * 4) + 4;
2121 const void *Decoder) {
2122 int32_t BranchOffset = (SignExtend32<16>(
Offset) * 2);
2130 const void *Decoder) {
2132 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
2140 const void *Decoder) {
2141 int32_t BranchOffset = SignExtend32<21>(
Offset) * 4 + 4;
2150 const void *Decoder) {
2151 int32_t BranchOffset = SignExtend32<21>(
Offset) * 4 + 4;
2160 const void *Decoder) {
2161 int32_t BranchOffset = SignExtend32<26>(
Offset) * 4 + 4;
2170 const void *Decoder) {
2171 int32_t BranchOffset = SignExtend32<7>(
Offset) << 1;
2179 const void *Decoder) {
2180 int32_t BranchOffset = SignExtend32<10>(
Offset) << 1;
2188 const void *Decoder) {
2189 int32_t BranchOffset = SignExtend32<16>(
Offset) * 2 + 4;
2197 const void *Decoder) {
2198 int32_t BranchOffset = SignExtend32<26>(
Offset) << 1;
2207 const void *Decoder) {
2208 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
2216 const void *Decoder) {
2219 else if (Value == 0x7)
2229 const void *Decoder) {
2240 const void *Decoder) {
2245 template <
unsigned Bits,
int Offset,
int Scale>
2248 const void *Decoder) {
2249 Value &= ((1 <<
Bits) - 1);
2255 template <
unsigned Bits,
int Offset,
int ScaleBy>
2258 const void *Decoder) {
2259 int32_t Imm = SignExtend32<Bits>(Value) * ScaleBy;
2267 const void *Decoder) {
2270 int Size = (int) Insn - Pos + 1;
2276 uint64_t Address,
const void *Decoder) {
2282 uint64_t Address,
const void *Decoder) {
2288 uint64_t Address,
const void *Decoder) {
2289 int32_t DecodedValue;
2291 case 0: DecodedValue = 256;
break;
2292 case 1: DecodedValue = 257;
break;
2293 case 510: DecodedValue = -258;
break;
2294 case 511: DecodedValue = -257;
break;
2295 default: DecodedValue = SignExtend32<9>(Insn);
break;
2302 uint64_t Address,
const void *Decoder) {
2305 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
2314 const void *Decoder) {
2315 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
2316 Mips::S6, Mips::S7, Mips::FP};
2319 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
2325 RegNum = RegLst & 0xf;
2331 for (
unsigned i = 0;
i < RegNum;
i++)
2342 const void *Decoder) {
2343 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2347 RegLst = fieldFromInstruction(Insn, 4, 2);
2349 case Mips::LWM16_MMR6:
2350 case Mips::SWM16_MMR6:
2351 RegLst = fieldFromInstruction(Insn, 8, 2);
2354 unsigned RegNum = RegLst & 0x3;
2356 for (
unsigned i = 0;
i <= RegNum;
i++)
2365 uint64_t Address,
const void *Decoder) {
2367 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2410 uint64_t Address,
const void *Decoder) {
2415 template <
typename InsnType>
2418 const void *Decoder) {
2426 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2427 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2437 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2439 else if (Rs == Rt) {
2442 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2448 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
2464 template <
typename InsnType>
2467 const void *Decoder) {
2475 InsnType Rt = fieldFromInstruction(insn, 21, 5);
2476 InsnType Rs = fieldFromInstruction(insn, 16, 5);
2484 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2486 else if (Rs == Rt) {
2488 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4;
2493 Imm =
SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
Target & getTheMipselTarget()
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipsDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Reg
All possible values of the reg field in the ModR/M byte.
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Context object for machine code objects.
static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
Target & getTheMips64Target()
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createMipselDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Target & getTheMips64elTarget()
static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeMipsDisassembler()
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
void setOpcode(unsigned Op)
static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction16(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian)
Read two bytes from the ArrayRef and return 16 bit halfword sorted according to the given endianness...
static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
CHAIN = SC CHAIN, Imm128 - System call.
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
Target - Wrapper for Target specific information.
static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
Target & getTheMipsTarget()
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder)
iterator begin() const
begin/end - Return all of the registers in this class.
static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
LLVM Value Representation.
static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus readInstruction32(ArrayRef< uint8_t > Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips)
Read four bytes from the ArrayRef and return 32 bit word sorted according to the given endianness...
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadByte9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)