21 #define DEBUG_TYPE "regalloc"
23 void LiveRangeCalc::resetLiveOutMap() {
56 assert(MRI && Indexes &&
"call reset() first");
64 if (!MO.isDef() && !MO.readsReg())
67 unsigned SubReg = MO.getSubReg();
68 if (LI.
hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
93 assert(Common == S.LaneMask);
123 SubLRC.
reset(MF, Indexes, DomTree, Alloc);
124 SubLRC.extendToUses(S, Reg, S.LaneMask, &LI);
138 "Expect empty main liverange");
141 for (
const VNInfo *VNI : SR.valnos) {
151 assert(MRI && Indexes &&
"call reset() first");
167 bool IsSubRange = !Mask.
all();
178 if (!MO.readsReg() || (IsSubRange && MO.isDef()))
181 unsigned SubReg = MO.getSubReg();
187 if ((SLM & Mask).none())
196 assert(!MO.isDef() &&
"Cannot handle PHI def of partial register.");
202 bool isEarlyClobber =
false;
205 isEarlyClobber = MO.isEarlyClobber();
216 extend(LR, UseIdx, Reg, Undefs);
221 void LiveRangeCalc::updateFromLiveIns() {
223 for (
const LiveInBlock &
I : LiveIn) {
227 assert(
I.Value &&
"No live-in value found");
231 if (
I.Kill.isValid())
238 Map[
MBB] = LiveOutPair(
I.Value,
nullptr);
241 Updater.
add(Start, End,
I.Value);
249 assert(Indexes &&
"Missing SlotIndexes");
250 assert(DomTree &&
"Missing dominator tree");
253 assert(UseMBB &&
"No MBB at Use");
257 if (EP.first !=
nullptr || EP.second)
264 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs))
276 assert(Indexes &&
"Missing SlotIndexes");
277 assert(DomTree &&
"Missing dominator tree");
289 if (UndefOnEntry[BN])
295 DefOnEntry[S->getNumber()] =
true;
296 DefOnEntry[BN] =
true;
304 WorkList.
insert(
P->getNumber());
306 for (
unsigned i = 0;
i != WorkList.
size(); ++
i) {
308 unsigned N = WorkList[
i];
310 if (Seen[N] && Map[&B].first !=
nullptr)
311 return MarkDefined(B);
315 if (UB != LR.
begin()) {
317 if (Seg.
end > Begin) {
324 return MarkDefined(B);
330 if (UndefOnEntry[N] || LR.
isUndefIn(Undefs, Begin, End)) {
331 UndefOnEntry[
N] =
true;
335 return MarkDefined(B);
339 WorkList.
insert(
P->getNumber());
342 UndefOnEntry[BN] =
true;
355 bool UniqueVNI =
true;
358 bool FoundUndef =
false;
361 for (
unsigned i = 0;
i != WorkList.
size(); ++
i) {
368 <<
" does not have a corresponding definition on every path:\n";
371 errs() << Use <<
" " << *
MI;
380 <<
" needs to be live in to BB#" << MBB->
getNumber()
381 <<
", but is missing from the live-in list.\n";
388 PE = MBB->
pred_end(); PI != PE; ++PI) {
393 if (
VNInfo *VNI = Map[Pred].first) {
394 if (TheVNI && TheVNI != VNI)
408 FoundUndef |= EP.second;
411 if (TheVNI && TheVNI != VNI)
415 if (VNI || EP.second)
428 FoundUndef |= (TheVNI ==
nullptr);
429 if (Undefs.
size() > 0 && FoundUndef)
434 if (WorkList.
size() > 4)
439 assert(TheVNI !=
nullptr);
441 for (
unsigned BN : WorkList) {
445 if (BN == UseMBBNum && Use.
isValid())
449 Updater.
add(Start, End, TheVNI);
455 auto EF = EntryInfoMap.find(&LR);
456 if (
EF == EntryInfoMap.end()) {
459 EF->second.first.resize(N);
460 EF->second.second.resize(N);
467 LiveIn.reserve(WorkList.size());
468 for (
unsigned BN : WorkList) {
470 if (Undefs.
size() > 0 && !isDefOnEntry(LR, Undefs, *MBB, DefOnEntry, UndefOnEntry))
474 LiveIn.back().Kill = Use;
483 void LiveRangeCalc::updateSSA() {
484 assert(Indexes &&
"Missing SlotIndexes");
485 assert(DomTree &&
"Missing dominator tree");
493 for (LiveInBlock &
I : LiveIn) {
500 LiveOutPair IDomValue;
504 bool needPHI = !IDom || !Seen.
test(IDom->
getBlock()->getNumber());
513 if (IDomValue.first && !IDomValue.second)
514 Map[IDom->
getBlock()].second = IDomValue.second =
518 PE = MBB->
pred_end(); PI != PE; ++PI) {
519 LiveOutPair &
Value = Map[*PI];
520 if (!Value.first || Value.first == IDomValue.first)
531 if (DomTree->
dominates(IDom, Value.second)) {
541 LiveOutPair &LOP = Map[
MBB];
546 assert(Alloc &&
"Need VNInfo allocator to create PHI-defs");
556 if (
I.Kill.isValid()) {
558 LR.
addSegment(LiveInterval::Segment(Start,
I.Kill, VNI));
561 LR.
addSegment(LiveInterval::Segment(Start, End, VNI));
562 LOP = LiveOutPair(VNI, Node);
564 }
else if (IDomValue.first) {
566 I.Value = IDomValue.first;
569 if (
I.Kill.isValid())
574 if (LOP.first == IDomValue.first)
void add(LiveRange::Segment)
Add a segment to LR and coalesce when possible, just like LR.addSegment().
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
SlotIndex def
The index of the defining instruction.
void createDeadDefs(LiveRange &LR, unsigned Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI)
setLiveOutValue - Indicate that VNI is live out from MBB.
static LaneBitmask getAll()
LiveInterval - This class represents the liveness of a register, or stack slot.
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
A live range for subregisters.
This represents a simple continuous liveness interval for a value.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
SubRange * createSubRangeFrom(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, const LiveRange &CopyFrom)
Like createSubRange() but the new range is filled with a copy of the liveness information in CopyFrom...
VNInfo - Value Number Information.
iterator end()
Get an iterator to the end of the SetVector.
size_type size() const
Determine the number of elements in the SetVector.
This class represents the liveness of a register, stack slot, etc.
DomTreeNodeBase< NodeT > * getIDom() const
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
void clear()
clear - Clear all bits.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetRegisterInfo * getTargetRegisterInfo() const
A Use represents the edge between a Value definition and its users.
iterator_range< subrange_iterator > subranges()
Reg
All possible values of the reg field in the ModR/M byte.
constexpr bool any() const
LLVM_NODISCARD bool empty() const
bool isUnused() const
Returns true if this value is unused.
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
bool insert(const value_type &X)
Insert a new element into the SetVector.
void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill=SlotIndex())
addLiveInBlock - Add a block with an unknown live-in value.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
iterator begin()
Get an iterator to the beginning of the SetVector.
Base class for the actual dominator tree node.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
std::vector< MachineBasicBlock * >::iterator pred_iterator
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
size_t size() const
size - Get the array size.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
iterator_range< def_iterator > def_operands(unsigned Reg) const
bool isEarlyClobber() const
void reset(const MachineFunction *MF, SlotIndexes *, MachineDominatorTree *, VNInfo::Allocator *)
reset - Prepare caches for a new set of non-overlapping live ranges.
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
bool isValid() const
Returns true if this is a valid index.
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
constexpr bool none() const
Allocate memory in an ever growing pool, as if by bump-pointer.
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Use)
Attempt to extend a value defined after StartIdx to include Use.
const MachineOperand & getOperand(unsigned i) const
void setDest(LiveRange *lr)
Select a different destination live range.
void resize(typename StorageT::size_type s)
static const unsigned End
iterator_range< pred_iterator > predecessors()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
bool isUndefIn(ArrayRef< SlotIndex > Undefs, SlotIndex Begin, SlotIndex End) const
Returns true if there is an explicit "undef" between Begin End.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool test(unsigned Idx) const
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
constexpr bool all() const
static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc, LiveRange &LR, const MachineOperand &MO)
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Helper class for performant LiveRange bulk updates.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
A vector that has set insertion semantics.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
SlotIndex - An opaque wrapper around machine indexes.
void calculateValues()
calculateValues - Calculate the value that will be live-in to each block added with addLiveInBlock...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.