LLVM  4.0.0
ARMInstructionSelector.h
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1 //===- ARMInstructionSelector ------------------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the targeting of the InstructionSelector class for ARM.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_ARMINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_ARM_ARMINSTRUCTIONSELECTOR_H
15 
17 
18 namespace llvm {
19 class ARMBaseInstrInfo;
20 class ARMBaseRegisterInfo;
21 class ARMBaseTargetMachine;
22 class ARMRegisterBankInfo;
23 class ARMSubtarget;
24 
26 public:
28  const ARMRegisterBankInfo &RBI);
29 
30  virtual bool select(MachineInstr &I) const override;
31 
32 private:
33  const ARMBaseInstrInfo &TII;
34  const ARMBaseRegisterInfo &TRI;
35  const ARMRegisterBankInfo &RBI;
36 };
37 
38 } // End llvm namespace.
39 #endif
This class provides the information for the target register banks.
ARMInstructionSelector(const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
virtual bool select(MachineInstr &I) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:52
#define I(x, y, z)
Definition: MD5.cpp:54