LLVM  4.0.0
MachineBasicBlock.cpp
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1 //===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Collect the sequence of machine instructions for a basic block.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/IR/BasicBlock.h"
25 #include "llvm/IR/DataLayout.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/Support/DataTypes.h"
30 #include "llvm/Support/Debug.h"
36 #include <algorithm>
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "codegen"
40 
41 MachineBasicBlock::MachineBasicBlock(MachineFunction &MF, const BasicBlock *B)
42  : BB(B), Number(-1), xParent(&MF) {
43  Insts.Parent = this;
44 }
45 
46 MachineBasicBlock::~MachineBasicBlock() {
47 }
48 
49 /// Return the MCSymbol for this basic block.
51  if (!CachedMCSymbol) {
52  const MachineFunction *MF = getParent();
53  MCContext &Ctx = MF->getContext();
54  auto Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
55  assert(getNumber() >= 0 && "cannot get label for unreachable MBB");
56  CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
57  Twine(MF->getFunctionNumber()) +
58  "_" + Twine(getNumber()));
59  }
60 
61  return CachedMCSymbol;
62 }
63 
64 
66  MBB.print(OS);
67  return OS;
68 }
69 
70 /// When an MBB is added to an MF, we need to update the parent pointer of the
71 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
72 /// operand list for registers.
73 ///
74 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
75 /// gets the next available unique MBB number. If it is removed from a
76 /// MachineFunction, it goes back to being #-1.
79  MachineFunction &MF = *N->getParent();
80  N->Number = MF.addToMBBNumbering(N);
81 
82  // Make sure the instructions have their operands in the reginfo lists.
83  MachineRegisterInfo &RegInfo = MF.getRegInfo();
85  I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
86  I->AddRegOperandsToUseLists(RegInfo);
87 }
88 
90  MachineBasicBlock *N) {
91  N->getParent()->removeFromMBBNumbering(N->Number);
92  N->Number = -1;
93 }
94 
95 /// When we add an instruction to a basic block list, we update its parent
96 /// pointer and add its operands from reg use/def lists if appropriate.
98  assert(!N->getParent() && "machine instruction already in a basic block");
99  N->setParent(Parent);
100 
101  // Add the instruction's register operands to their corresponding
102  // use/def lists.
103  MachineFunction *MF = Parent->getParent();
104  N->AddRegOperandsToUseLists(MF->getRegInfo());
105 }
106 
107 /// When we remove an instruction from a basic block list, we update its parent
108 /// pointer and remove its operands from reg use/def lists if appropriate.
110  assert(N->getParent() && "machine instruction not in a basic block");
111 
112  // Remove from the use/def lists.
113  if (MachineFunction *MF = N->getParent()->getParent())
114  N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
115 
116  N->setParent(nullptr);
117 }
118 
119 /// When moving a range of instructions from one MBB list to another, we need to
120 /// update the parent pointers and the use/def lists.
122  instr_iterator First,
123  instr_iterator Last) {
124  assert(Parent->getParent() == FromList.Parent->getParent() &&
125  "MachineInstr parent mismatch!");
126  assert(this != &FromList && "Called without a real transfer...");
127  assert(Parent != FromList.Parent && "Two lists have the same parent?");
128 
129  // If splicing between two blocks within the same function, just update the
130  // parent pointers.
131  for (; First != Last; ++First)
132  First->setParent(Parent);
133 }
134 
136  assert(!MI->getParent() && "MI is still in a block!");
137  Parent->getParent()->DeleteMachineInstr(MI);
138 }
139 
142  while (I != E && I->isPHI())
143  ++I;
144  assert((I == E || !I->isInsideBundle()) &&
145  "First non-phi MI cannot be inside a bundle!");
146  return I;
147 }
148 
151  iterator E = end();
152  while (I != E && (I->isPHI() || I->isPosition()))
153  ++I;
154  // FIXME: This needs to change if we wish to bundle labels
155  // inside the bundle.
156  assert((I == E || !I->isInsideBundle()) &&
157  "First non-phi / non-label instruction is inside a bundle!");
158  return I;
159 }
160 
163  iterator E = end();
164  while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
165  ++I;
166  // FIXME: This needs to change if we wish to bundle labels / dbg_values
167  // inside the bundle.
168  assert((I == E || !I->isInsideBundle()) &&
169  "First non-phi / non-label / non-debug "
170  "instruction is inside a bundle!");
171  return I;
172 }
173 
175  iterator B = begin(), E = end(), I = E;
176  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
177  ; /*noop */
178  while (I != E && !I->isTerminator())
179  ++I;
180  return I;
181 }
182 
184  instr_iterator B = instr_begin(), E = instr_end(), I = E;
185  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
186  ; /*noop */
187  while (I != E && !I->isTerminator())
188  ++I;
189  return I;
190 }
191 
193  // Skip over begin-of-block dbg_value instructions.
195 }
196 
198  // Skip over end-of-block dbg_value instructions.
200  while (I != B) {
201  --I;
202  // Return instruction that starts a bundle.
203  if (I->isDebugValue() || I->isInsideBundle())
204  continue;
205  return I;
206  }
207  // The block is all debug values.
208  return end();
209 }
210 
212  for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
213  if ((*I)->isEHPad())
214  return true;
215  return false;
216 }
217 
218 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
220  print(dbgs());
221 }
222 #endif
223 
225  if (const BasicBlock *LBB = getBasicBlock())
226  return LBB->getName();
227  else
228  return "(null)";
229 }
230 
231 /// Return a hopefully unique identifier for this block.
232 std::string MachineBasicBlock::getFullName() const {
233  std::string Name;
234  if (getParent())
235  Name = (getParent()->getName() + ":").str();
236  if (getBasicBlock())
237  Name += getBasicBlock()->getName();
238  else
239  Name += ("BB" + Twine(getNumber())).str();
240  return Name;
241 }
242 
244  const {
245  const MachineFunction *MF = getParent();
246  if (!MF) {
247  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
248  << " is null\n";
249  return;
250  }
251  const Function *F = MF->getFunction();
252  const Module *M = F ? F->getParent() : nullptr;
253  ModuleSlotTracker MST(M);
254  print(OS, MST, Indexes);
255 }
256 
258  const SlotIndexes *Indexes) const {
259  const MachineFunction *MF = getParent();
260  if (!MF) {
261  OS << "Can't print out MachineBasicBlock because parent MachineFunction"
262  << " is null\n";
263  return;
264  }
265 
266  if (Indexes)
267  OS << Indexes->getMBBStartIdx(this) << '\t';
268 
269  OS << "BB#" << getNumber() << ": ";
270 
271  const char *Comma = "";
272  if (const BasicBlock *LBB = getBasicBlock()) {
273  OS << Comma << "derived from LLVM BB ";
274  LBB->printAsOperand(OS, /*PrintType=*/false, MST);
275  Comma = ", ";
276  }
277  if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
278  if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
279  if (Alignment)
280  OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
281  << " bytes)";
282 
283  OS << '\n';
284 
285  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
286  if (!livein_empty()) {
287  if (Indexes) OS << '\t';
288  OS << " Live Ins:";
289  for (const auto &LI : LiveIns) {
290  OS << ' ' << PrintReg(LI.PhysReg, TRI);
291  if (!LI.LaneMask.all())
292  OS << ':' << PrintLaneMask(LI.LaneMask);
293  }
294  OS << '\n';
295  }
296  // Print the preds of this block according to the CFG.
297  if (!pred_empty()) {
298  if (Indexes) OS << '\t';
299  OS << " Predecessors according to CFG:";
300  for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
301  OS << " BB#" << (*PI)->getNumber();
302  OS << '\n';
303  }
304 
305  for (auto &I : instrs()) {
306  if (Indexes) {
307  if (Indexes->hasIndex(I))
308  OS << Indexes->getInstructionIndex(I);
309  OS << '\t';
310  }
311  OS << '\t';
312  if (I.isInsideBundle())
313  OS << " * ";
314  I.print(OS, MST);
315  }
316 
317  // Print the successors of this block according to the CFG.
318  if (!succ_empty()) {
319  if (Indexes) OS << '\t';
320  OS << " Successors according to CFG:";
321  for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
322  OS << " BB#" << (*SI)->getNumber();
323  if (!Probs.empty())
324  OS << '(' << *getProbabilityIterator(SI) << ')';
325  }
326  OS << '\n';
327  }
328 }
329 
331  bool /*PrintType*/) const {
332  OS << "BB#" << getNumber();
333 }
334 
336  LiveInVector::iterator I = find_if(
337  LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
338  if (I == LiveIns.end())
339  return;
340 
341  I->LaneMask &= ~LaneMask;
342  if (I->LaneMask.none())
343  LiveIns.erase(I);
344 }
345 
348  LiveIns, [Reg](const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
349  return I != livein_end() && (I->LaneMask & LaneMask).any();
350 }
351 
353  std::sort(LiveIns.begin(), LiveIns.end(),
354  [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
355  return LI0.PhysReg < LI1.PhysReg;
356  });
357  // Liveins are sorted by physreg now we can merge their lanemasks.
358  LiveInVector::const_iterator I = LiveIns.begin();
359  LiveInVector::const_iterator J;
360  LiveInVector::iterator Out = LiveIns.begin();
361  for (; I != LiveIns.end(); ++Out, I = J) {
362  unsigned PhysReg = I->PhysReg;
363  LaneBitmask LaneMask = I->LaneMask;
364  for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
365  LaneMask |= J->LaneMask;
366  Out->PhysReg = PhysReg;
367  Out->LaneMask = LaneMask;
368  }
369  LiveIns.erase(Out, LiveIns.end());
370 }
371 
372 unsigned
374  assert(getParent() && "MBB must be inserted in function");
375  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
376  assert(RC && "Register class is required");
377  assert((isEHPad() || this == &getParent()->front()) &&
378  "Only the entry block and landing pads can have physreg live ins");
379 
380  bool LiveIn = isLiveIn(PhysReg);
384 
385  // Look for an existing copy.
386  if (LiveIn)
387  for (;I != E && I->isCopy(); ++I)
388  if (I->getOperand(1).getReg() == PhysReg) {
389  unsigned VirtReg = I->getOperand(0).getReg();
390  if (!MRI.constrainRegClass(VirtReg, RC))
391  llvm_unreachable("Incompatible live-in register class.");
392  return VirtReg;
393  }
394 
395  // No luck, create a virtual register.
396  unsigned VirtReg = MRI.createVirtualRegister(RC);
397  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
398  .addReg(PhysReg, RegState::Kill);
399  if (!LiveIn)
400  addLiveIn(PhysReg);
401  return VirtReg;
402 }
403 
405  getParent()->splice(NewAfter->getIterator(), getIterator());
406 }
407 
409  getParent()->splice(++NewBefore->getIterator(), getIterator());
410 }
411 
414  // A block with no successors has no concerns with fall-through edges.
415  if (this->succ_empty())
416  return;
417 
418  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
420  DebugLoc DL; // FIXME: this is nowhere
421  bool B = TII->analyzeBranch(*this, TBB, FBB, Cond);
422  (void) B;
423  assert(!B && "UpdateTerminators requires analyzable predecessors!");
424  if (Cond.empty()) {
425  if (TBB) {
426  // The block has an unconditional branch. If its successor is now its
427  // layout successor, delete the branch.
428  if (isLayoutSuccessor(TBB))
429  TII->removeBranch(*this);
430  } else {
431  // The block has an unconditional fallthrough. If its successor is not its
432  // layout successor, insert a branch. First we have to locate the only
433  // non-landing-pad successor, as that is the fallthrough block.
434  for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
435  if ((*SI)->isEHPad())
436  continue;
437  assert(!TBB && "Found more than one non-landing-pad successor!");
438  TBB = *SI;
439  }
440 
441  // If there is no non-landing-pad successor, the block has no fall-through
442  // edges to be concerned with.
443  if (!TBB)
444  return;
445 
446  // Finally update the unconditional successor to be reached via a branch
447  // if it would not be reached by fallthrough.
448  if (!isLayoutSuccessor(TBB))
449  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
450  }
451  return;
452  }
453 
454  if (FBB) {
455  // The block has a non-fallthrough conditional branch. If one of its
456  // successors is its layout successor, rewrite it to a fallthrough
457  // conditional branch.
458  if (isLayoutSuccessor(TBB)) {
459  if (TII->reverseBranchCondition(Cond))
460  return;
461  TII->removeBranch(*this);
462  TII->insertBranch(*this, FBB, nullptr, Cond, DL);
463  } else if (isLayoutSuccessor(FBB)) {
464  TII->removeBranch(*this);
465  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
466  }
467  return;
468  }
469 
470  // Walk through the successors and find the successor which is not a landing
471  // pad and is not the conditional branch destination (in TBB) as the
472  // fallthrough successor.
473  MachineBasicBlock *FallthroughBB = nullptr;
474  for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
475  if ((*SI)->isEHPad() || *SI == TBB)
476  continue;
477  assert(!FallthroughBB && "Found more than one fallthrough successor.");
478  FallthroughBB = *SI;
479  }
480 
481  if (!FallthroughBB) {
482  if (canFallThrough()) {
483  // We fallthrough to the same basic block as the conditional jump targets.
484  // Remove the conditional jump, leaving unconditional fallthrough.
485  // FIXME: This does not seem like a reasonable pattern to support, but it
486  // has been seen in the wild coming out of degenerate ARM test cases.
487  TII->removeBranch(*this);
488 
489  // Finally update the unconditional successor to be reached via a branch if
490  // it would not be reached by fallthrough.
491  if (!isLayoutSuccessor(TBB))
492  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
493  return;
494  }
495 
496  // We enter here iff exactly one successor is TBB which cannot fallthrough
497  // and the rest successors if any are EHPads. In this case, we need to
498  // change the conditional branch into unconditional branch.
499  TII->removeBranch(*this);
500  Cond.clear();
501  TII->insertBranch(*this, TBB, nullptr, Cond, DL);
502  return;
503  }
504 
505  // The block has a fallthrough conditional branch.
506  if (isLayoutSuccessor(TBB)) {
507  if (TII->reverseBranchCondition(Cond)) {
508  // We can't reverse the condition, add an unconditional branch.
509  Cond.clear();
510  TII->insertBranch(*this, FallthroughBB, nullptr, Cond, DL);
511  return;
512  }
513  TII->removeBranch(*this);
514  TII->insertBranch(*this, FallthroughBB, nullptr, Cond, DL);
515  } else if (!isLayoutSuccessor(FallthroughBB)) {
516  TII->removeBranch(*this);
517  TII->insertBranch(*this, TBB, FallthroughBB, Cond, DL);
518  }
519 }
520 
522 #ifndef NDEBUG
523  int64_t Sum = 0;
524  for (auto Prob : Probs)
525  Sum += Prob.getNumerator();
526  // Due to precision issue, we assume that the sum of probabilities is one if
527  // the difference between the sum of their numerators and the denominator is
528  // no greater than the number of successors.
530  Probs.size() &&
531  "The sum of successors's probabilities exceeds one.");
532 #endif // NDEBUG
533 }
534 
536  BranchProbability Prob) {
537  // Probability list is either empty (if successor list isn't empty, this means
538  // disabled optimization) or has the same size as successor list.
539  if (!(Probs.empty() && !Successors.empty()))
540  Probs.push_back(Prob);
541  Successors.push_back(Succ);
542  Succ->addPredecessor(this);
543 }
544 
546  // We need to make sure probability list is either empty or has the same size
547  // of successor list. When this function is called, we can safely delete all
548  // probability in the list.
549  Probs.clear();
550  Successors.push_back(Succ);
551  Succ->addPredecessor(this);
552 }
553 
555  bool NormalizeSuccProbs) {
556  succ_iterator I = find(Successors, Succ);
557  removeSuccessor(I, NormalizeSuccProbs);
558 }
559 
562  assert(I != Successors.end() && "Not a current successor!");
563 
564  // If probability list is empty it means we don't use it (disabled
565  // optimization).
566  if (!Probs.empty()) {
567  probability_iterator WI = getProbabilityIterator(I);
568  Probs.erase(WI);
569  if (NormalizeSuccProbs)
571  }
572 
573  (*I)->removePredecessor(this);
574  return Successors.erase(I);
575 }
576 
578  MachineBasicBlock *New) {
579  if (Old == New)
580  return;
581 
583  succ_iterator NewI = E;
584  succ_iterator OldI = E;
585  for (succ_iterator I = succ_begin(); I != E; ++I) {
586  if (*I == Old) {
587  OldI = I;
588  if (NewI != E)
589  break;
590  }
591  if (*I == New) {
592  NewI = I;
593  if (OldI != E)
594  break;
595  }
596  }
597  assert(OldI != E && "Old is not a successor of this block");
598 
599  // If New isn't already a successor, let it take Old's place.
600  if (NewI == E) {
601  Old->removePredecessor(this);
602  New->addPredecessor(this);
603  *OldI = New;
604  return;
605  }
606 
607  // New is already a successor.
608  // Update its probability instead of adding a duplicate edge.
609  if (!Probs.empty()) {
610  auto ProbIter = getProbabilityIterator(NewI);
611  if (!ProbIter->isUnknown())
612  *ProbIter += *getProbabilityIterator(OldI);
613  }
614  removeSuccessor(OldI);
615 }
616 
617 void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) {
618  Predecessors.push_back(Pred);
619 }
620 
621 void MachineBasicBlock::removePredecessor(MachineBasicBlock *Pred) {
622  pred_iterator I = find(Predecessors, Pred);
623  assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
624  Predecessors.erase(I);
625 }
626 
628  if (this == FromMBB)
629  return;
630 
631  while (!FromMBB->succ_empty()) {
632  MachineBasicBlock *Succ = *FromMBB->succ_begin();
633 
634  // If probability list is empty it means we don't use it (disabled optimization).
635  if (!FromMBB->Probs.empty()) {
636  auto Prob = *FromMBB->Probs.begin();
637  addSuccessor(Succ, Prob);
638  } else
640 
641  FromMBB->removeSuccessor(Succ);
642  }
643 }
644 
645 void
647  if (this == FromMBB)
648  return;
649 
650  while (!FromMBB->succ_empty()) {
651  MachineBasicBlock *Succ = *FromMBB->succ_begin();
652  if (!FromMBB->Probs.empty()) {
653  auto Prob = *FromMBB->Probs.begin();
654  addSuccessor(Succ, Prob);
655  } else
657  FromMBB->removeSuccessor(Succ);
658 
659  // Fix up any PHI nodes in the successor.
661  ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
662  for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
663  MachineOperand &MO = MI->getOperand(i);
664  if (MO.getMBB() == FromMBB)
665  MO.setMBB(this);
666  }
667  }
669 }
670 
672  return is_contained(predecessors(), MBB);
673 }
674 
676  return is_contained(successors(), MBB);
677 }
678 
681  return std::next(I) == MachineFunction::const_iterator(MBB);
682 }
683 
685  MachineFunction::iterator Fallthrough = getIterator();
686  ++Fallthrough;
687  // If FallthroughBlock is off the end of the function, it can't fall through.
688  if (Fallthrough == getParent()->end())
689  return false;
690 
691  // If FallthroughBlock isn't a successor, no fallthrough is possible.
692  if (!isSuccessor(&*Fallthrough))
693  return false;
694 
695  // Analyze the branches, if any, at the end of the block.
696  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
699  if (TII->analyzeBranch(*this, TBB, FBB, Cond)) {
700  // If we couldn't analyze the branch, examine the last instruction.
701  // If the block doesn't end in a known control barrier, assume fallthrough
702  // is possible. The isPredicated check is needed because this code can be
703  // called during IfConversion, where an instruction which is normally a
704  // Barrier is predicated and thus no longer an actual control barrier.
705  return empty() || !back().isBarrier() || TII->isPredicated(back());
706  }
707 
708  // If there is no branch, control always falls through.
709  if (!TBB) return true;
710 
711  // If there is some explicit branch to the fallthrough block, it can obviously
712  // reach, even though the branch should get folded to fall through implicitly.
713  if (MachineFunction::iterator(TBB) == Fallthrough ||
714  MachineFunction::iterator(FBB) == Fallthrough)
715  return true;
716 
717  // If it's an unconditional branch to some block not the fall through, it
718  // doesn't fall through.
719  if (Cond.empty()) return false;
720 
721  // Otherwise, if it is conditional and has no explicit false block, it falls
722  // through.
723  return FBB == nullptr;
724 }
725 
727  Pass &P) {
728  if (!canSplitCriticalEdge(Succ))
729  return nullptr;
730 
731  MachineFunction *MF = getParent();
732  DebugLoc DL; // FIXME: this is nowhere
733 
735  MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
736  DEBUG(dbgs() << "Splitting critical edge:"
737  " BB#" << getNumber()
738  << " -- BB#" << NMBB->getNumber()
739  << " -- BB#" << Succ->getNumber() << '\n');
740 
743  if (LIS)
744  LIS->insertMBBInMaps(NMBB);
745  else if (Indexes)
746  Indexes->insertMBBInMaps(NMBB);
747 
748  // On some targets like Mips, branches may kill virtual registers. Make sure
749  // that LiveVariables is properly updated after updateTerminator replaces the
750  // terminators.
752 
753  // Collect a list of virtual registers killed by the terminators.
754  SmallVector<unsigned, 4> KilledRegs;
755  if (LV)
757  I != E; ++I) {
758  MachineInstr *MI = &*I;
760  OE = MI->operands_end(); OI != OE; ++OI) {
761  if (!OI->isReg() || OI->getReg() == 0 ||
762  !OI->isUse() || !OI->isKill() || OI->isUndef())
763  continue;
764  unsigned Reg = OI->getReg();
766  LV->getVarInfo(Reg).removeKill(*MI)) {
767  KilledRegs.push_back(Reg);
768  DEBUG(dbgs() << "Removing terminator kill: " << *MI);
769  OI->setIsKill(false);
770  }
771  }
772  }
773 
774  SmallVector<unsigned, 4> UsedRegs;
775  if (LIS) {
777  I != E; ++I) {
778  MachineInstr *MI = &*I;
779 
781  OE = MI->operands_end(); OI != OE; ++OI) {
782  if (!OI->isReg() || OI->getReg() == 0)
783  continue;
784 
785  unsigned Reg = OI->getReg();
786  if (!is_contained(UsedRegs, Reg))
787  UsedRegs.push_back(Reg);
788  }
789  }
790  }
791 
792  ReplaceUsesOfBlockWith(Succ, NMBB);
793 
794  // If updateTerminator() removes instructions, we need to remove them from
795  // SlotIndexes.
796  SmallVector<MachineInstr*, 4> Terminators;
797  if (Indexes) {
799  I != E; ++I)
800  Terminators.push_back(&*I);
801  }
802 
804 
805  if (Indexes) {
806  SmallVector<MachineInstr*, 4> NewTerminators;
808  I != E; ++I)
809  NewTerminators.push_back(&*I);
810 
811  for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
812  E = Terminators.end(); I != E; ++I) {
813  if (!is_contained(NewTerminators, *I))
814  Indexes->removeMachineInstrFromMaps(**I);
815  }
816  }
817 
818  // Insert unconditional "jump Succ" instruction in NMBB if necessary.
819  NMBB->addSuccessor(Succ);
820  if (!NMBB->isLayoutSuccessor(Succ)) {
823  TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL);
824 
825  if (Indexes) {
826  for (MachineInstr &MI : NMBB->instrs()) {
827  // Some instructions may have been moved to NMBB by updateTerminator(),
828  // so we first remove any instruction that already has an index.
829  if (Indexes->hasIndex(MI))
830  Indexes->removeMachineInstrFromMaps(MI);
831  Indexes->insertMachineInstrInMaps(MI);
832  }
833  }
834  }
835 
836  // Fix PHI nodes in Succ so they refer to NMBB instead of this
838  i = Succ->instr_begin(),e = Succ->instr_end();
839  i != e && i->isPHI(); ++i)
840  for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
841  if (i->getOperand(ni+1).getMBB() == this)
842  i->getOperand(ni+1).setMBB(NMBB);
843 
844  // Inherit live-ins from the successor
845  for (const auto &LI : Succ->liveins())
846  NMBB->addLiveIn(LI);
847 
848  // Update LiveVariables.
849  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
850  if (LV) {
851  // Restore kills of virtual registers that were killed by the terminators.
852  while (!KilledRegs.empty()) {
853  unsigned Reg = KilledRegs.pop_back_val();
854  for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
855  if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
856  continue;
858  LV->getVarInfo(Reg).Kills.push_back(&*I);
859  DEBUG(dbgs() << "Restored terminator kill: " << *I);
860  break;
861  }
862  }
863  // Update relevant live-through information.
864  LV->addNewBlock(NMBB, this, Succ);
865  }
866 
867  if (LIS) {
868  // After splitting the edge and updating SlotIndexes, live intervals may be
869  // in one of two situations, depending on whether this block was the last in
870  // the function. If the original block was the last in the function, all
871  // live intervals will end prior to the beginning of the new split block. If
872  // the original block was not at the end of the function, all live intervals
873  // will extend to the end of the new split block.
874 
875  bool isLastMBB =
876  std::next(MachineFunction::iterator(NMBB)) == getParent()->end();
877 
878  SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
879  SlotIndex PrevIndex = StartIndex.getPrevSlot();
880  SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
881 
882  // Find the registers used from NMBB in PHIs in Succ.
883  SmallSet<unsigned, 8> PHISrcRegs;
885  I = Succ->instr_begin(), E = Succ->instr_end();
886  I != E && I->isPHI(); ++I) {
887  for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
888  if (I->getOperand(ni+1).getMBB() == NMBB) {
889  MachineOperand &MO = I->getOperand(ni);
890  unsigned Reg = MO.getReg();
891  PHISrcRegs.insert(Reg);
892  if (MO.isUndef())
893  continue;
894 
895  LiveInterval &LI = LIS->getInterval(Reg);
896  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
897  assert(VNI &&
898  "PHI sources should be live out of their predecessors.");
899  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
900  }
901  }
902  }
903 
905  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
907  if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
908  continue;
909 
910  LiveInterval &LI = LIS->getInterval(Reg);
911  if (!LI.liveAt(PrevIndex))
912  continue;
913 
914  bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
915  if (isLiveOut && isLastMBB) {
916  VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
917  assert(VNI && "LiveInterval should have VNInfo where it is live.");
918  LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
919  } else if (!isLiveOut && !isLastMBB) {
920  LI.removeSegment(StartIndex, EndIndex);
921  }
922  }
923 
924  // Update all intervals for registers whose uses may have been modified by
925  // updateTerminator().
926  LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
927  }
928 
929  if (MachineDominatorTree *MDT =
931  MDT->recordSplitCriticalEdge(this, Succ, NMBB);
932 
934  if (MachineLoop *TIL = MLI->getLoopFor(this)) {
935  // If one or the other blocks were not in a loop, the new block is not
936  // either, and thus LI doesn't need to be updated.
937  if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
938  if (TIL == DestLoop) {
939  // Both in the same loop, the NMBB joins loop.
940  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
941  } else if (TIL->contains(DestLoop)) {
942  // Edge from an outer loop to an inner loop. Add to the outer loop.
943  TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
944  } else if (DestLoop->contains(TIL)) {
945  // Edge from an inner loop to an outer loop. Add to the outer loop.
946  DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
947  } else {
948  // Edge from two loops with no containment relation. Because these
949  // are natural loops, we know that the destination block must be the
950  // header of its loop (adding a branch into a loop elsewhere would
951  // create an irreducible loop).
952  assert(DestLoop->getHeader() == Succ &&
953  "Should not create irreducible loops!");
954  if (MachineLoop *P = DestLoop->getParentLoop())
955  P->addBasicBlockToLoop(NMBB, MLI->getBase());
956  }
957  }
958  }
959 
960  return NMBB;
961 }
962 
964  const MachineBasicBlock *Succ) const {
965  // Splitting the critical edge to a landing pad block is non-trivial. Don't do
966  // it in this generic function.
967  if (Succ->isEHPad())
968  return false;
969 
970  const MachineFunction *MF = getParent();
971 
972  // Performance might be harmed on HW that implements branching using exec mask
973  // where both sides of the branches are always executed.
974  if (MF->getTarget().requiresStructuredCFG())
975  return false;
976 
977  // We may need to update this's terminator, but we can't do that if
978  // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
979  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
980  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
982  // AnalyzeBanch should modify this, since we did not allow modification.
983  if (TII->analyzeBranch(*const_cast<MachineBasicBlock *>(this), TBB, FBB, Cond,
984  /*AllowModify*/ false))
985  return false;
986 
987  // Avoid bugpoint weirdness: A block may end with a conditional branch but
988  // jumps to the same MBB is either case. We have duplicate CFG edges in that
989  // case that we can't handle. Since this never happens in properly optimized
990  // code, just skip those edges.
991  if (TBB && TBB == FBB) {
992  DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
993  << getNumber() << '\n');
994  return false;
995  }
996  return true;
997 }
998 
999 /// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
1000 /// neighboring instructions so the bundle won't be broken by removing MI.
1001 static void unbundleSingleMI(MachineInstr *MI) {
1002  // Removing the first instruction in a bundle.
1003  if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
1004  MI->unbundleFromSucc();
1005  // Removing the last instruction in a bundle.
1006  if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
1007  MI->unbundleFromPred();
1008  // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
1009  // are already fine.
1010 }
1011 
1014  unbundleSingleMI(&*I);
1015  return Insts.erase(I);
1016 }
1017 
1019  unbundleSingleMI(MI);
1022  return Insts.remove(MI);
1023 }
1024 
1026 MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
1027  assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
1028  "Cannot insert instruction with bundle flags");
1029  // Set the bundle flags when inserting inside a bundle.
1030  if (I != instr_end() && I->isBundledWithPred()) {
1033  }
1034  return Insts.insert(I, MI);
1035 }
1036 
1037 /// This method unlinks 'this' from the containing function, and returns it, but
1038 /// does not delete it.
1040  assert(getParent() && "Not embedded in a function!");
1041  getParent()->remove(this);
1042  return this;
1043 }
1044 
1045 /// This method unlinks 'this' from the containing function, and deletes it.
1047  assert(getParent() && "Not embedded in a function!");
1048  getParent()->erase(this);
1049 }
1050 
1051 /// Given a machine basic block that branched to 'Old', change the code and CFG
1052 /// so that it branches to 'New' instead.
1054  MachineBasicBlock *New) {
1055  assert(Old != New && "Cannot replace self with self!");
1056 
1058  while (I != instr_begin()) {
1059  --I;
1060  if (!I->isTerminator()) break;
1061 
1062  // Scan the operands of this machine instruction, replacing any uses of Old
1063  // with New.
1064  for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
1065  if (I->getOperand(i).isMBB() &&
1066  I->getOperand(i).getMBB() == Old)
1067  I->getOperand(i).setMBB(New);
1068  }
1069 
1070  // Update the successor information.
1071  replaceSuccessor(Old, New);
1072 }
1073 
1074 /// Various pieces of code can cause excess edges in the CFG to be inserted. If
1075 /// we have proven that MBB can only branch to DestA and DestB, remove any other
1076 /// MBB successors from the CFG. DestA and DestB can be null.
1077 ///
1078 /// Besides DestA and DestB, retain other edges leading to LandingPads
1079 /// (currently there can be only one; we don't check or require that here).
1080 /// Note it is possible that DestA and/or DestB are LandingPads.
1082  MachineBasicBlock *DestB,
1083  bool IsCond) {
1084  // The values of DestA and DestB frequently come from a call to the
1085  // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
1086  // values from there.
1087  //
1088  // 1. If both DestA and DestB are null, then the block ends with no branches
1089  // (it falls through to its successor).
1090  // 2. If DestA is set, DestB is null, and IsCond is false, then the block ends
1091  // with only an unconditional branch.
1092  // 3. If DestA is set, DestB is null, and IsCond is true, then the block ends
1093  // with a conditional branch that falls through to a successor (DestB).
1094  // 4. If DestA and DestB is set and IsCond is true, then the block ends with a
1095  // conditional branch followed by an unconditional branch. DestA is the
1096  // 'true' destination and DestB is the 'false' destination.
1097 
1098  bool Changed = false;
1099 
1100  MachineBasicBlock *FallThru = getNextNode();
1101 
1102  if (!DestA && !DestB) {
1103  // Block falls through to successor.
1104  DestA = FallThru;
1105  DestB = FallThru;
1106  } else if (DestA && !DestB) {
1107  if (IsCond)
1108  // Block ends in conditional jump that falls through to successor.
1109  DestB = FallThru;
1110  } else {
1111  assert(DestA && DestB && IsCond &&
1112  "CFG in a bad state. Cannot correct CFG edges");
1113  }
1114 
1115  // Remove superfluous edges. I.e., those which aren't destinations of this
1116  // basic block, duplicate edges, or landing pads.
1119  while (SI != succ_end()) {
1120  const MachineBasicBlock *MBB = *SI;
1121  if (!SeenMBBs.insert(MBB).second ||
1122  (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
1123  // This is a superfluous edge, remove it.
1124  SI = removeSuccessor(SI);
1125  Changed = true;
1126  } else {
1127  ++SI;
1128  }
1129  }
1130 
1131  if (Changed)
1133  return Changed;
1134 }
1135 
1136 /// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
1137 /// instructions. Return UnknownLoc if there is none.
1138 DebugLoc
1139 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
1140  // Skip debug declarations, we don't want a DebugLoc from them.
1141  MBBI = skipDebugInstructionsForward(MBBI, instr_end());
1142  if (MBBI != instr_end())
1143  return MBBI->getDebugLoc();
1144  return {};
1145 }
1146 
1147 /// Return probability of the edge from this block to MBB.
1149 MachineBasicBlock::getSuccProbability(const_succ_iterator Succ) const {
1150  if (Probs.empty())
1151  return BranchProbability(1, succ_size());
1152 
1153  const auto &Prob = *getProbabilityIterator(Succ);
1154  if (Prob.isUnknown()) {
1155  // For unknown probabilities, collect the sum of all known ones, and evenly
1156  // ditribute the complemental of the sum to each unknown probability.
1157  unsigned KnownProbNum = 0;
1158  auto Sum = BranchProbability::getZero();
1159  for (auto &P : Probs) {
1160  if (!P.isUnknown()) {
1161  Sum += P;
1162  KnownProbNum++;
1163  }
1164  }
1165  return Sum.getCompl() / (Probs.size() - KnownProbNum);
1166  } else
1167  return Prob;
1168 }
1169 
1170 /// Set successor probability of a given iterator.
1172  BranchProbability Prob) {
1173  assert(!Prob.isUnknown());
1174  if (Probs.empty())
1175  return;
1176  *getProbabilityIterator(I) = Prob;
1177 }
1178 
1179 /// Return probability iterator corresonding to the I successor iterator
1180 MachineBasicBlock::const_probability_iterator
1181 MachineBasicBlock::getProbabilityIterator(
1183  assert(Probs.size() == Successors.size() && "Async probability list!");
1184  const size_t index = std::distance(Successors.begin(), I);
1185  assert(index < Probs.size() && "Not a current successor!");
1186  return Probs.begin() + index;
1187 }
1188 
1189 /// Return probability iterator corresonding to the I successor iterator.
1190 MachineBasicBlock::probability_iterator
1191 MachineBasicBlock::getProbabilityIterator(MachineBasicBlock::succ_iterator I) {
1192  assert(Probs.size() == Successors.size() && "Async probability list!");
1193  const size_t index = std::distance(Successors.begin(), I);
1194  assert(index < Probs.size() && "Not a current successor!");
1195  return Probs.begin() + index;
1196 }
1197 
1198 /// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
1199 /// as of just before "MI".
1200 ///
1201 /// Search is localised to a neighborhood of
1202 /// Neighborhood instructions before (searching for defs or kills) and N
1203 /// instructions after (searching just for defs) MI.
1206  unsigned Reg, const_iterator Before,
1207  unsigned Neighborhood) const {
1208  unsigned N = Neighborhood;
1209 
1210  // Start by searching backwards from Before, looking for kills, reads or defs.
1211  const_iterator I(Before);
1212  // If this is the first insn in the block, don't search backwards.
1213  if (I != begin()) {
1214  do {
1215  --I;
1216 
1218  ConstMIOperands(*I).analyzePhysReg(Reg, TRI);
1219 
1220  // Defs happen after uses so they take precedence if both are present.
1221 
1222  // Register is dead after a dead def of the full register.
1223  if (Info.DeadDef)
1224  return LQR_Dead;
1225  // Register is (at least partially) live after a def.
1226  if (Info.Defined) {
1227  if (!Info.PartialDeadDef)
1228  return LQR_Live;
1229  // As soon as we saw a partial definition (dead or not),
1230  // we cannot tell if the value is partial live without
1231  // tracking the lanemasks. We are not going to do this,
1232  // so fall back on the remaining of the analysis.
1233  break;
1234  }
1235  // Register is dead after a full kill or clobber and no def.
1236  if (Info.Killed || Info.Clobbered)
1237  return LQR_Dead;
1238  // Register must be live if we read it.
1239  if (Info.Read)
1240  return LQR_Live;
1241  } while (I != begin() && --N > 0);
1242  }
1243 
1244  // Did we get to the start of the block?
1245  if (I == begin()) {
1246  // If so, the register's state is definitely defined by the live-in state.
1247  for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true); RAI.isValid();
1248  ++RAI)
1249  if (isLiveIn(*RAI))
1250  return LQR_Live;
1251 
1252  return LQR_Dead;
1253  }
1254 
1255  N = Neighborhood;
1256 
1257  // Try searching forwards from Before, looking for reads or defs.
1258  I = const_iterator(Before);
1259  // If this is the last insn in the block, don't search forwards.
1260  if (I != end()) {
1261  for (++I; I != end() && N > 0; ++I, --N) {
1263  ConstMIOperands(*I).analyzePhysReg(Reg, TRI);
1264 
1265  // Register is live when we read it here.
1266  if (Info.Read)
1267  return LQR_Live;
1268  // Register is dead if we can fully overwrite or clobber it here.
1269  if (Info.FullyDefined || Info.Clobbered)
1270  return LQR_Dead;
1271  }
1272  }
1273 
1274  // At this point we have no idea of the liveness of the register.
1275  return LQR_Unknown;
1276 }
1277 
1278 const uint32_t *
1280  // EH funclet entry does not preserve any registers.
1281  return isEHFuncletEntry() ? TRI->getNoPreservedMask() : nullptr;
1282 }
1283 
1284 const uint32_t *
1286  // If we see a return block with successors, this must be a funclet return,
1287  // which does not preserve any registers. If there are no successors, we don't
1288  // care what kind of return it is, putting a mask after it is a no-op.
1289  return isReturnBlock() && !succ_empty() ? TRI->getNoPreservedMask() : nullptr;
1290 }
1291 
1293  LiveIns.clear();
1294 }
1295 
1297  assert(getParent()->getProperties().hasProperty(
1299  "Liveness information is accurate");
1300  return LiveIns.begin();
1301 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:81
unsigned succ_size() const
void push_back(const T &Elt)
Definition: SmallVector.h:211
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isEHPad() const
Returns true if the block is a landing pad.
mop_iterator operands_end()
Definition: MachineInstr.h:296
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:243
instr_iterator instr_begin()
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:406
iterator_range< livein_iterator > liveins() const
instr_iterator instr_end()
MachineBasicBlock * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:274
iterator erase(iterator where)
Definition: ilist.h:280
size_t i
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:450
void addNodeToList(NodeTy *)
When an MBB is added to an MF, we need to update the parent pointer of the MBB, the MBB numbering...
Definition: ilist.h:66
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
iterator getFirstNonDebugInstr()
Returns an iterator to the first non-debug instruction in the basic block, or end().
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Template traits for intrusive list.
Definition: ilist.h:101
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
void addSuccessorWithoutProb(MachineBasicBlock *Succ)
Add Succ as a successor of this MachineBasicBlock.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
void moveAfter(MachineBasicBlock *NewBefore)
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Manage lifetime of a slot tracker for printing IR.
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
Instructions::iterator instr_iterator
MachineBasicBlock * removeFromParent()
This method unlinks 'this' from the containing function, and returns it, but does not delete it...
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:396
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
iterator_range< succ_iterator > successors()
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:191
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
Definition: LiveVariables.h:94
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
bool isPHI() const
Definition: MachineInstr.h:786
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
Definition: SlotIndexes.h:401
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
static void unbundleSingleMI(MachineInstr *MI)
Prepare MI to be removed from its bundle.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it...
PhysRegInfo analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI)
analyzePhysReg - Analyze how the current instruction or bundle uses a physical register.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
Context object for machine code objects.
Definition: MCContext.h:51
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:233
void unbundleFromPred()
Break bundle above this instruction.
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
#define F(x, y, z)
Definition: MD5.cpp:51
SlotIndexes pass.
Definition: SlotIndexes.h:323
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MachineBasicBlock * MBB
bool canFallThrough()
Return true if the block can implicitly transfer control to the block after it by falling off the end...
const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the start of this basic block.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
MCContext & getContext() const
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been <def>ined and not <kill>ed as of just before Before...
bool PartialDeadDef
Reg is Defined and all defs of reg or an overlapping register are dead.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:282
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
livein_iterator livein_begin() const
unsigned const MachineRegisterInfo * MRI
void insertMBBInMaps(MachineBasicBlock *mbb)
Add the given MachineBasicBlock into the maps.
Definition: SlotIndexes.h:637
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
livein_iterator livein_end() const
bool Read
Reg or one of its aliases is read.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
bool Clobbered
There is a regmask operand indicating Reg is clobbered.
void setMBB(MachineBasicBlock *MBB)
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
Register is known to be fully dead.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:166
MCRegAliasIterator enumerates all registers aliasing Reg.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:177
void clearLiveIns()
Clear live in list.
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
bool Killed
There is a use operand of reg or a super-register with kill flag set.
void remove(iterator MBBI)
self_iterator getIterator()
Definition: ilist_node.h:81
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:229
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:80
iterator_range< pred_iterator > predecessors()
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
Register is known to be (at least partially) live.
void moveBefore(MachineBasicBlock *NewAfter)
Move 'this' block before or after the specified block.
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:376
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
bool canSplitCriticalEdge(const MachineBasicBlock *Succ) const
Check if the edge between this block and the given successor Succ, can be split.
StringRef getPrivateLabelPrefix() const
Definition: MCAsmInfo.h:477
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:64
void addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB, MachineBasicBlock *SuccBB)
addNewBlock - Add a new basic block BB between DomBB and SuccBB.
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static uint32_t getDenominator()
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:757
BasicBlockListType::const_iterator const_iterator
void splice(iterator InsertPt, iterator MBBI)
void removeNodeFromList(NodeTy *)
Definition: ilist.h:67
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
void updateTerminator()
Update the terminator instructions in block to account for changes to the layout. ...
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
void validateSuccProbs() const
Validate successors' probabilities and check if the sum of them is approximate one.
bool FullyDefined
Reg or a super-register is defined.
static void deleteNode(NodeTy *V)
Definition: ilist.h:42
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
StringRef getName() const
Return the name of the corresponding LLVM basic block, or "(null)".
ConstMIOperands - Iterate over operands of a single const instruction.
void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New)
Replace successor OLD with NEW and update probability info.
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
pointer remove(iterator &IT)
Definition: ilist.h:264
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
iterator insert(iterator where, pointer New)
Definition: ilist.h:241
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:114
Register liveness not decidable from local neighborhood.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1099
Pair of physical register and lane mask.
const uint32_t * getEndClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the end of the basic block.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Information about how a physical register Reg is used by a set of operands.
void removeFromMBBNumbering(unsigned N)
removeFromMBBNumbering - Remove the specific machine basic block from our tracker, this is only really to be used by the MachineBasicBlock implementation.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:479
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1726
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
unsigned getReg() const
getReg - Returns the register number.
bool Defined
Reg or one of its aliases is defined.
void erase(iterator MBBI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P)
Split the critical edge from this block to the given successor block, and return the newly created bl...
void unbundleFromSucc()
Break bundle below this instruction.
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
virtual const TargetInstrInfo * getInstrInfo() const
unsigned addToMBBNumbering(MachineBasicBlock *MBB)
Adds the MBB to the internal numbering.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:537
mop_iterator operands_begin()
Definition: MachineInstr.h:295
static LLVM_ATTRIBUTE_UNUSED Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:82
LiveInVector::const_iterator livein_iterator
MachineInstrBundleIterator< const MachineInstr > const_iterator
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:100
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
iterator SkipPHIsLabelsAndDebug(iterator I)
Return the first instruction in MBB after I that is not a PHI, label or debug.
IRTranslator LLVM IR MI
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static BranchProbability getZero()
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(std::begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:764
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
bool requiresStructuredCFG() const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:431
bool CorrectExtraCFGEdges(MachineBasicBlock *DestA, MachineBasicBlock *DestB, bool IsCond)
Various pieces of code can cause excess edges in the CFG to be inserted.
void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator)
Callback before transferring nodes to this list.
Definition: ilist.h:73
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:783