LLVM  4.0.0
MachineVerifier.cpp
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1 //===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Pass to verify generated machine code. The following is checked:
11 //
12 // Operand counts: All explicit operands must be present.
13 //
14 // Register classes: All physical and virtual register operands must be
15 // compatible with the register class required by the instruction descriptor.
16 //
17 // Register live intervals: Registers must be defined only once, and must be
18 // defined before use.
19 //
20 // The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21 // command-line option -verify-machineinstrs, or by defining the environment
22 // variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23 // the verifier errors.
24 //===----------------------------------------------------------------------===//
25 
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/ADT/DenseSet.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/Support/Debug.h"
51 using namespace llvm;
52 
53 namespace {
54  struct MachineVerifier {
55 
56  MachineVerifier(Pass *pass, const char *b) :
57  PASS(pass),
58  Banner(b)
59  {}
60 
61  unsigned verify(MachineFunction &MF);
62 
63  Pass *const PASS;
64  const char *Banner;
65  const MachineFunction *MF;
66  const TargetMachine *TM;
67  const TargetInstrInfo *TII;
68  const TargetRegisterInfo *TRI;
69  const MachineRegisterInfo *MRI;
70 
71  unsigned foundErrors;
72 
73  // Avoid querying the MachineFunctionProperties for each operand.
74  bool isFunctionRegBankSelected;
75  bool isFunctionSelected;
76 
77  typedef SmallVector<unsigned, 16> RegVector;
78  typedef SmallVector<const uint32_t*, 4> RegMaskVector;
79  typedef DenseSet<unsigned> RegSet;
82 
83  const MachineInstr *FirstTerminator;
84  BlockSet FunctionBlocks;
85 
86  BitVector regsReserved;
87  RegSet regsLive;
88  RegVector regsDefined, regsDead, regsKilled;
89  RegMaskVector regMasks;
90  RegSet regsLiveInButUnused;
91 
92  SlotIndex lastIndex;
93 
94  // Add Reg and any sub-registers to RV
95  void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
96  RV.push_back(Reg);
98  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
99  RV.push_back(*SubRegs);
100  }
101 
102  struct BBInfo {
103  // Is this MBB reachable from the MF entry point?
104  bool reachable;
105 
106  // Vregs that must be live in because they are used without being
107  // defined. Map value is the user.
108  RegMap vregsLiveIn;
109 
110  // Regs killed in MBB. They may be defined again, and will then be in both
111  // regsKilled and regsLiveOut.
112  RegSet regsKilled;
113 
114  // Regs defined in MBB and live out. Note that vregs passing through may
115  // be live out without being mentioned here.
116  RegSet regsLiveOut;
117 
118  // Vregs that pass through MBB untouched. This set is disjoint from
119  // regsKilled and regsLiveOut.
120  RegSet vregsPassed;
121 
122  // Vregs that must pass through MBB because they are needed by a successor
123  // block. This set is disjoint from regsLiveOut.
124  RegSet vregsRequired;
125 
126  // Set versions of block's predecessor and successor lists.
127  BlockSet Preds, Succs;
128 
129  BBInfo() : reachable(false) {}
130 
131  // Add register to vregsPassed if it belongs there. Return true if
132  // anything changed.
133  bool addPassed(unsigned Reg) {
135  return false;
136  if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
137  return false;
138  return vregsPassed.insert(Reg).second;
139  }
140 
141  // Same for a full set.
142  bool addPassed(const RegSet &RS) {
143  bool changed = false;
144  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
145  if (addPassed(*I))
146  changed = true;
147  return changed;
148  }
149 
150  // Add register to vregsRequired if it belongs there. Return true if
151  // anything changed.
152  bool addRequired(unsigned Reg) {
154  return false;
155  if (regsLiveOut.count(Reg))
156  return false;
157  return vregsRequired.insert(Reg).second;
158  }
159 
160  // Same for a full set.
161  bool addRequired(const RegSet &RS) {
162  bool changed = false;
163  for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
164  if (addRequired(*I))
165  changed = true;
166  return changed;
167  }
168 
169  // Same for a full map.
170  bool addRequired(const RegMap &RM) {
171  bool changed = false;
172  for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
173  if (addRequired(I->first))
174  changed = true;
175  return changed;
176  }
177 
178  // Live-out registers are either in regsLiveOut or vregsPassed.
179  bool isLiveOut(unsigned Reg) const {
180  return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
181  }
182  };
183 
184  // Extra register info per MBB.
186 
187  bool isReserved(unsigned Reg) {
188  return Reg < regsReserved.size() && regsReserved.test(Reg);
189  }
190 
191  bool isAllocatable(unsigned Reg) {
192  return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
193  }
194 
195  // Analysis information if available
196  LiveVariables *LiveVars;
197  LiveIntervals *LiveInts;
198  LiveStacks *LiveStks;
199  SlotIndexes *Indexes;
200 
201  void visitMachineFunctionBefore();
202  void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
203  void visitMachineBundleBefore(const MachineInstr *MI);
204  void visitMachineInstrBefore(const MachineInstr *MI);
205  void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
206  void visitMachineInstrAfter(const MachineInstr *MI);
207  void visitMachineBundleAfter(const MachineInstr *MI);
208  void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
209  void visitMachineFunctionAfter();
210 
211  void report(const char *msg, const MachineFunction *MF);
212  void report(const char *msg, const MachineBasicBlock *MBB);
213  void report(const char *msg, const MachineInstr *MI);
214  void report(const char *msg, const MachineOperand *MO, unsigned MONum);
215 
216  void report_context(const LiveInterval &LI) const;
217  void report_context(const LiveRange &LR, unsigned VRegUnit,
218  LaneBitmask LaneMask) const;
219  void report_context(const LiveRange::Segment &S) const;
220  void report_context(const VNInfo &VNI) const;
221  void report_context(SlotIndex Pos) const;
222  void report_context_liverange(const LiveRange &LR) const;
223  void report_context_lanemask(LaneBitmask LaneMask) const;
224  void report_context_vreg(unsigned VReg) const;
225  void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
226 
227  void verifyInlineAsm(const MachineInstr *MI);
228 
229  void checkLiveness(const MachineOperand *MO, unsigned MONum);
230  void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
231  SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
232  LaneBitmask LaneMask = LaneBitmask::getNone());
233  void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
234  SlotIndex DefIdx, const LiveRange &LR, unsigned Reg,
235  LaneBitmask LaneMask = LaneBitmask::getNone());
236 
237  void markReachable(const MachineBasicBlock *MBB);
238  void calcRegsPassed();
239  void checkPHIOps(const MachineBasicBlock *MBB);
240 
241  void calcRegsRequired();
242  void verifyLiveVariables();
243  void verifyLiveIntervals();
244  void verifyLiveInterval(const LiveInterval&);
245  void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
246  LaneBitmask);
247  void verifyLiveRangeSegment(const LiveRange&,
248  const LiveRange::const_iterator I, unsigned,
249  LaneBitmask);
250  void verifyLiveRange(const LiveRange&, unsigned,
251  LaneBitmask LaneMask = LaneBitmask::getNone());
252 
253  void verifyStackFrame();
254 
255  void verifySlotIndexes() const;
256  void verifyProperties(const MachineFunction &MF);
257  };
258 
259  struct MachineVerifierPass : public MachineFunctionPass {
260  static char ID; // Pass ID, replacement for typeid
261  const std::string Banner;
262 
263  MachineVerifierPass(const std::string &banner = nullptr)
264  : MachineFunctionPass(ID), Banner(banner) {
266  }
267 
268  void getAnalysisUsage(AnalysisUsage &AU) const override {
269  AU.setPreservesAll();
271  }
272 
273  bool runOnMachineFunction(MachineFunction &MF) override {
274  unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
275  if (FoundErrors)
276  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
277  return false;
278  }
279  };
280 
281 }
282 
283 char MachineVerifierPass::ID = 0;
284 INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
285  "Verify generated machine code", false, false)
286 
287 FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
288  return new MachineVerifierPass(Banner);
289 }
290 
291 bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
292  const {
293  MachineFunction &MF = const_cast<MachineFunction&>(*this);
294  unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
295  if (AbortOnErrors && FoundErrors)
296  report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
297  return FoundErrors == 0;
298 }
299 
300 void MachineVerifier::verifySlotIndexes() const {
301  if (Indexes == nullptr)
302  return;
303 
304  // Ensure the IdxMBB list is sorted by slot indexes.
305  SlotIndex Last;
306  for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
307  E = Indexes->MBBIndexEnd(); I != E; ++I) {
308  assert(!Last.isValid() || I->first > Last);
309  Last = I->first;
310  }
311 }
312 
313 void MachineVerifier::verifyProperties(const MachineFunction &MF) {
314  // If a pass has introduced virtual registers without clearing the
315  // NoVRegs property (or set it without allocating the vregs)
316  // then report an error.
317  if (MF.getProperties().hasProperty(
319  MRI->getNumVirtRegs())
320  report("Function has NoVRegs property but there are VReg operands", &MF);
321 }
322 
324  foundErrors = 0;
325 
326  this->MF = &MF;
327  TM = &MF.getTarget();
328  TII = MF.getSubtarget().getInstrInfo();
329  TRI = MF.getSubtarget().getRegisterInfo();
330  MRI = &MF.getRegInfo();
331 
332  isFunctionRegBankSelected = MF.getProperties().hasProperty(
334  isFunctionSelected = MF.getProperties().hasProperty(
336 
337  LiveVars = nullptr;
338  LiveInts = nullptr;
339  LiveStks = nullptr;
340  Indexes = nullptr;
341  if (PASS) {
342  LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
343  // We don't want to verify LiveVariables if LiveIntervals is available.
344  if (!LiveInts)
345  LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
346  LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
347  Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
348  }
349 
350  verifySlotIndexes();
351 
352  verifyProperties(MF);
353 
354  visitMachineFunctionBefore();
355  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
356  MFI!=MFE; ++MFI) {
357  visitMachineBasicBlockBefore(&*MFI);
358  // Keep track of the current bundle header.
359  const MachineInstr *CurBundle = nullptr;
360  // Do we expect the next instruction to be part of the same bundle?
361  bool InBundle = false;
362 
363  for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
364  MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
365  if (MBBI->getParent() != &*MFI) {
366  report("Bad instruction parent pointer", &*MFI);
367  errs() << "Instruction: " << *MBBI;
368  continue;
369  }
370 
371  // Check for consistent bundle flags.
372  if (InBundle && !MBBI->isBundledWithPred())
373  report("Missing BundledPred flag, "
374  "BundledSucc was set on predecessor",
375  &*MBBI);
376  if (!InBundle && MBBI->isBundledWithPred())
377  report("BundledPred flag is set, "
378  "but BundledSucc not set on predecessor",
379  &*MBBI);
380 
381  // Is this a bundle header?
382  if (!MBBI->isInsideBundle()) {
383  if (CurBundle)
384  visitMachineBundleAfter(CurBundle);
385  CurBundle = &*MBBI;
386  visitMachineBundleBefore(CurBundle);
387  } else if (!CurBundle)
388  report("No bundle header", &*MBBI);
389  visitMachineInstrBefore(&*MBBI);
390  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
391  const MachineInstr &MI = *MBBI;
392  const MachineOperand &Op = MI.getOperand(I);
393  if (Op.getParent() != &MI) {
394  // Make sure to use correct addOperand / RemoveOperand / ChangeTo
395  // functions when replacing operands of a MachineInstr.
396  report("Instruction has operand with wrong parent set", &MI);
397  }
398 
399  visitMachineOperand(&Op, I);
400  }
401 
402  visitMachineInstrAfter(&*MBBI);
403 
404  // Was this the last bundled instruction?
405  InBundle = MBBI->isBundledWithSucc();
406  }
407  if (CurBundle)
408  visitMachineBundleAfter(CurBundle);
409  if (InBundle)
410  report("BundledSucc flag set on last instruction in block", &MFI->back());
411  visitMachineBasicBlockAfter(&*MFI);
412  }
413  visitMachineFunctionAfter();
414 
415  // Clean up.
416  regsLive.clear();
417  regsDefined.clear();
418  regsDead.clear();
419  regsKilled.clear();
420  regMasks.clear();
421  regsLiveInButUnused.clear();
422  MBBInfoMap.clear();
423 
424  return foundErrors;
425 }
426 
427 void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
428  assert(MF);
429  errs() << '\n';
430  if (!foundErrors++) {
431  if (Banner)
432  errs() << "# " << Banner << '\n';
433  if (LiveInts != nullptr)
434  LiveInts->print(errs());
435  else
436  MF->print(errs(), Indexes);
437  }
438  errs() << "*** Bad machine code: " << msg << " ***\n"
439  << "- function: " << MF->getName() << "\n";
440 }
441 
442 void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
443  assert(MBB);
444  report(msg, MBB->getParent());
445  errs() << "- basic block: BB#" << MBB->getNumber()
446  << ' ' << MBB->getName()
447  << " (" << (const void*)MBB << ')';
448  if (Indexes)
449  errs() << " [" << Indexes->getMBBStartIdx(MBB)
450  << ';' << Indexes->getMBBEndIdx(MBB) << ')';
451  errs() << '\n';
452 }
453 
454 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
455  assert(MI);
456  report(msg, MI->getParent());
457  errs() << "- instruction: ";
458  if (Indexes && Indexes->hasIndex(*MI))
459  errs() << Indexes->getInstructionIndex(*MI) << '\t';
460  MI->print(errs(), /*SkipOpers=*/true);
461  errs() << '\n';
462 }
463 
464 void MachineVerifier::report(const char *msg,
465  const MachineOperand *MO, unsigned MONum) {
466  assert(MO);
467  report(msg, MO->getParent());
468  errs() << "- operand " << MONum << ": ";
469  MO->print(errs(), TRI);
470  errs() << "\n";
471 }
472 
473 void MachineVerifier::report_context(SlotIndex Pos) const {
474  errs() << "- at: " << Pos << '\n';
475 }
476 
477 void MachineVerifier::report_context(const LiveInterval &LI) const {
478  errs() << "- interval: " << LI << '\n';
479 }
480 
481 void MachineVerifier::report_context(const LiveRange &LR, unsigned VRegUnit,
482  LaneBitmask LaneMask) const {
483  report_context_liverange(LR);
484  report_context_vreg_regunit(VRegUnit);
485  if (LaneMask.any())
486  report_context_lanemask(LaneMask);
487 }
488 
489 void MachineVerifier::report_context(const LiveRange::Segment &S) const {
490  errs() << "- segment: " << S << '\n';
491 }
492 
493 void MachineVerifier::report_context(const VNInfo &VNI) const {
494  errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
495 }
496 
497 void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
498  errs() << "- liverange: " << LR << '\n';
499 }
500 
501 void MachineVerifier::report_context_vreg(unsigned VReg) const {
502  errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n';
503 }
504 
505 void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
506  if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
507  report_context_vreg(VRegOrUnit);
508  } else {
509  errs() << "- regunit: " << PrintRegUnit(VRegOrUnit, TRI) << '\n';
510  }
511 }
512 
513 void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
514  errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
515 }
516 
517 void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
518  BBInfo &MInfo = MBBInfoMap[MBB];
519  if (!MInfo.reachable) {
520  MInfo.reachable = true;
522  SuE = MBB->succ_end(); SuI != SuE; ++SuI)
523  markReachable(*SuI);
524  }
525 }
526 
527 void MachineVerifier::visitMachineFunctionBefore() {
528  lastIndex = SlotIndex();
529  regsReserved = MRI->getReservedRegs();
530 
531  markReachable(&MF->front());
532 
533  // Build a set of the basic blocks in the function.
534  FunctionBlocks.clear();
535  for (const auto &MBB : *MF) {
536  FunctionBlocks.insert(&MBB);
537  BBInfo &MInfo = MBBInfoMap[&MBB];
538 
539  MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
540  if (MInfo.Preds.size() != MBB.pred_size())
541  report("MBB has duplicate entries in its predecessor list.", &MBB);
542 
543  MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
544  if (MInfo.Succs.size() != MBB.succ_size())
545  report("MBB has duplicate entries in its successor list.", &MBB);
546  }
547 
548  // Check that the register use lists are sane.
549  MRI->verifyUseLists();
550 
551  verifyStackFrame();
552 }
553 
554 // Does iterator point to a and b as the first two elements?
556  const MachineBasicBlock *a, const MachineBasicBlock *b) {
557  if (*i == a)
558  return *++i == b;
559  if (*i == b)
560  return *++i == a;
561  return false;
562 }
563 
564 void
565 MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
566  FirstTerminator = nullptr;
567 
568  if (!MF->getProperties().hasProperty(
569  MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
570  // If this block has allocatable physical registers live-in, check that
571  // it is an entry block or landing pad.
572  for (const auto &LI : MBB->liveins()) {
573  if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
574  MBB->getIterator() != MBB->getParent()->begin()) {
575  report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
576  }
577  }
578  }
579 
580  // Count the number of landing pad successors.
581  SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
583  E = MBB->succ_end(); I != E; ++I) {
584  if ((*I)->isEHPad())
585  LandingPadSuccs.insert(*I);
586  if (!FunctionBlocks.count(*I))
587  report("MBB has successor that isn't part of the function.", MBB);
588  if (!MBBInfoMap[*I].Preds.count(MBB)) {
589  report("Inconsistent CFG", MBB);
590  errs() << "MBB is not in the predecessor list of the successor BB#"
591  << (*I)->getNumber() << ".\n";
592  }
593  }
594 
595  // Check the predecessor list.
597  E = MBB->pred_end(); I != E; ++I) {
598  if (!FunctionBlocks.count(*I))
599  report("MBB has predecessor that isn't part of the function.", MBB);
600  if (!MBBInfoMap[*I].Succs.count(MBB)) {
601  report("Inconsistent CFG", MBB);
602  errs() << "MBB is not in the successor list of the predecessor BB#"
603  << (*I)->getNumber() << ".\n";
604  }
605  }
606 
607  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
608  const BasicBlock *BB = MBB->getBasicBlock();
609  const Function *Fn = MF->getFunction();
610  if (LandingPadSuccs.size() > 1 &&
611  !(AsmInfo &&
613  BB && isa<SwitchInst>(BB->getTerminator())) &&
615  report("MBB has more than one landing pad successor", MBB);
616 
617  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
618  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
620  if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
621  Cond)) {
622  // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
623  // check whether its answers match up with reality.
624  if (!TBB && !FBB) {
625  // Block falls through to its successor.
627  ++MBBI;
628  if (MBBI == MF->end()) {
629  // It's possible that the block legitimately ends with a noreturn
630  // call or an unreachable, in which case it won't actually fall
631  // out the bottom of the function.
632  } else if (MBB->succ_size() == LandingPadSuccs.size()) {
633  // It's possible that the block legitimately ends with a noreturn
634  // call or an unreachable, in which case it won't actuall fall
635  // out of the block.
636  } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
637  report("MBB exits via unconditional fall-through but doesn't have "
638  "exactly one CFG successor!", MBB);
639  } else if (!MBB->isSuccessor(&*MBBI)) {
640  report("MBB exits via unconditional fall-through but its successor "
641  "differs from its CFG successor!", MBB);
642  }
643  if (!MBB->empty() && MBB->back().isBarrier() &&
644  !TII->isPredicated(MBB->back())) {
645  report("MBB exits via unconditional fall-through but ends with a "
646  "barrier instruction!", MBB);
647  }
648  if (!Cond.empty()) {
649  report("MBB exits via unconditional fall-through but has a condition!",
650  MBB);
651  }
652  } else if (TBB && !FBB && Cond.empty()) {
653  // Block unconditionally branches somewhere.
654  // If the block has exactly one successor, that happens to be a
655  // landingpad, accept it as valid control flow.
656  if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
657  (MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
658  *MBB->succ_begin() != *LandingPadSuccs.begin())) {
659  report("MBB exits via unconditional branch but doesn't have "
660  "exactly one CFG successor!", MBB);
661  } else if (!MBB->isSuccessor(TBB)) {
662  report("MBB exits via unconditional branch but the CFG "
663  "successor doesn't match the actual successor!", MBB);
664  }
665  if (MBB->empty()) {
666  report("MBB exits via unconditional branch but doesn't contain "
667  "any instructions!", MBB);
668  } else if (!MBB->back().isBarrier()) {
669  report("MBB exits via unconditional branch but doesn't end with a "
670  "barrier instruction!", MBB);
671  } else if (!MBB->back().isTerminator()) {
672  report("MBB exits via unconditional branch but the branch isn't a "
673  "terminator instruction!", MBB);
674  }
675  } else if (TBB && !FBB && !Cond.empty()) {
676  // Block conditionally branches somewhere, otherwise falls through.
678  ++MBBI;
679  if (MBBI == MF->end()) {
680  report("MBB conditionally falls through out of function!", MBB);
681  } else if (MBB->succ_size() == 1) {
682  // A conditional branch with only one successor is weird, but allowed.
683  if (&*MBBI != TBB)
684  report("MBB exits via conditional branch/fall-through but only has "
685  "one CFG successor!", MBB);
686  else if (TBB != *MBB->succ_begin())
687  report("MBB exits via conditional branch/fall-through but the CFG "
688  "successor don't match the actual successor!", MBB);
689  } else if (MBB->succ_size() != 2) {
690  report("MBB exits via conditional branch/fall-through but doesn't have "
691  "exactly two CFG successors!", MBB);
692  } else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
693  report("MBB exits via conditional branch/fall-through but the CFG "
694  "successors don't match the actual successors!", MBB);
695  }
696  if (MBB->empty()) {
697  report("MBB exits via conditional branch/fall-through but doesn't "
698  "contain any instructions!", MBB);
699  } else if (MBB->back().isBarrier()) {
700  report("MBB exits via conditional branch/fall-through but ends with a "
701  "barrier instruction!", MBB);
702  } else if (!MBB->back().isTerminator()) {
703  report("MBB exits via conditional branch/fall-through but the branch "
704  "isn't a terminator instruction!", MBB);
705  }
706  } else if (TBB && FBB) {
707  // Block conditionally branches somewhere, otherwise branches
708  // somewhere else.
709  if (MBB->succ_size() == 1) {
710  // A conditional branch with only one successor is weird, but allowed.
711  if (FBB != TBB)
712  report("MBB exits via conditional branch/branch through but only has "
713  "one CFG successor!", MBB);
714  else if (TBB != *MBB->succ_begin())
715  report("MBB exits via conditional branch/branch through but the CFG "
716  "successor don't match the actual successor!", MBB);
717  } else if (MBB->succ_size() != 2) {
718  report("MBB exits via conditional branch/branch but doesn't have "
719  "exactly two CFG successors!", MBB);
720  } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
721  report("MBB exits via conditional branch/branch but the CFG "
722  "successors don't match the actual successors!", MBB);
723  }
724  if (MBB->empty()) {
725  report("MBB exits via conditional branch/branch but doesn't "
726  "contain any instructions!", MBB);
727  } else if (!MBB->back().isBarrier()) {
728  report("MBB exits via conditional branch/branch but doesn't end with a "
729  "barrier instruction!", MBB);
730  } else if (!MBB->back().isTerminator()) {
731  report("MBB exits via conditional branch/branch but the branch "
732  "isn't a terminator instruction!", MBB);
733  }
734  if (Cond.empty()) {
735  report("MBB exits via conditinal branch/branch but there's no "
736  "condition!", MBB);
737  }
738  } else {
739  report("AnalyzeBranch returned invalid data!", MBB);
740  }
741  }
742 
743  regsLive.clear();
744  if (MRI->tracksLiveness()) {
745  for (const auto &LI : MBB->liveins()) {
746  if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
747  report("MBB live-in list contains non-physical register", MBB);
748  continue;
749  }
750  for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
751  SubRegs.isValid(); ++SubRegs)
752  regsLive.insert(*SubRegs);
753  }
754  }
755  regsLiveInButUnused = regsLive;
756 
757  const MachineFrameInfo &MFI = MF->getFrameInfo();
758  BitVector PR = MFI.getPristineRegs(*MF);
759  for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
760  for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
761  SubRegs.isValid(); ++SubRegs)
762  regsLive.insert(*SubRegs);
763  }
764 
765  regsKilled.clear();
766  regsDefined.clear();
767 
768  if (Indexes)
769  lastIndex = Indexes->getMBBStartIdx(MBB);
770 }
771 
772 // This function gets called for all bundle headers, including normal
773 // stand-alone unbundled instructions.
774 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
775  if (Indexes && Indexes->hasIndex(*MI)) {
776  SlotIndex idx = Indexes->getInstructionIndex(*MI);
777  if (!(idx > lastIndex)) {
778  report("Instruction index out of order", MI);
779  errs() << "Last instruction was at " << lastIndex << '\n';
780  }
781  lastIndex = idx;
782  }
783 
784  // Ensure non-terminators don't follow terminators.
785  // Ignore predicated terminators formed by if conversion.
786  // FIXME: If conversion shouldn't need to violate this rule.
787  if (MI->isTerminator() && !TII->isPredicated(*MI)) {
788  if (!FirstTerminator)
789  FirstTerminator = MI;
790  } else if (FirstTerminator) {
791  report("Non-terminator instruction after the first terminator", MI);
792  errs() << "First terminator was:\t" << *FirstTerminator;
793  }
794 }
795 
796 // The operands on an INLINEASM instruction must follow a template.
797 // Verify that the flag operands make sense.
798 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
799  // The first two operands on INLINEASM are the asm string and global flags.
800  if (MI->getNumOperands() < 2) {
801  report("Too few operands on inline asm", MI);
802  return;
803  }
804  if (!MI->getOperand(0).isSymbol())
805  report("Asm string must be an external symbol", MI);
806  if (!MI->getOperand(1).isImm())
807  report("Asm flags must be an immediate", MI);
808  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
809  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
810  // and Extra_IsConvergent = 32.
811  if (!isUInt<6>(MI->getOperand(1).getImm()))
812  report("Unknown asm flags", &MI->getOperand(1), 1);
813 
814  static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
815 
816  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
817  unsigned NumOps;
818  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
819  const MachineOperand &MO = MI->getOperand(OpNo);
820  // There may be implicit ops after the fixed operands.
821  if (!MO.isImm())
822  break;
823  NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
824  }
825 
826  if (OpNo > MI->getNumOperands())
827  report("Missing operands in last group", MI);
828 
829  // An optional MDNode follows the groups.
830  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
831  ++OpNo;
832 
833  // All trailing operands must be implicit registers.
834  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
835  const MachineOperand &MO = MI->getOperand(OpNo);
836  if (!MO.isReg() || !MO.isImplicit())
837  report("Expected implicit register after groups", &MO, OpNo);
838  }
839 }
840 
841 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
842  const MCInstrDesc &MCID = MI->getDesc();
843  if (MI->getNumOperands() < MCID.getNumOperands()) {
844  report("Too few operands", MI);
845  errs() << MCID.getNumOperands() << " operands expected, but "
846  << MI->getNumOperands() << " given.\n";
847  }
848 
849  if (MI->isPHI() && MF->getProperties().hasProperty(
851  report("Found PHI instruction with NoPHIs property set", MI);
852 
853  // Check the tied operands.
854  if (MI->isInlineAsm())
855  verifyInlineAsm(MI);
856 
857  // Check the MachineMemOperands for basic consistency.
859  E = MI->memoperands_end(); I != E; ++I) {
860  if ((*I)->isLoad() && !MI->mayLoad())
861  report("Missing mayLoad flag", MI);
862  if ((*I)->isStore() && !MI->mayStore())
863  report("Missing mayStore flag", MI);
864  }
865 
866  // Debug values must not have a slot index.
867  // Other instructions must have one, unless they are inside a bundle.
868  if (LiveInts) {
869  bool mapped = !LiveInts->isNotInMIMap(*MI);
870  if (MI->isDebugValue()) {
871  if (mapped)
872  report("Debug instruction has a slot index", MI);
873  } else if (MI->isInsideBundle()) {
874  if (mapped)
875  report("Instruction inside bundle has a slot index", MI);
876  } else {
877  if (!mapped)
878  report("Missing slot index", MI);
879  }
880  }
881 
882  // Check types.
883  if (isPreISelGenericOpcode(MCID.getOpcode())) {
884  if (isFunctionSelected)
885  report("Unexpected generic instruction in a Selected function", MI);
886 
887  // Generic instructions specify equality constraints between some
888  // of their operands. Make sure these are consistent.
889  SmallVector<LLT, 4> Types;
890  for (unsigned i = 0; i < MCID.getNumOperands(); ++i) {
891  if (!MCID.OpInfo[i].isGenericType())
892  continue;
893  size_t TypeIdx = MCID.OpInfo[i].getGenericTypeIndex();
894  Types.resize(std::max(TypeIdx + 1, Types.size()));
895 
896  LLT OpTy = MRI->getType(MI->getOperand(i).getReg());
897  if (Types[TypeIdx].isValid() && Types[TypeIdx] != OpTy)
898  report("type mismatch in generic instruction", MI);
899  Types[TypeIdx] = OpTy;
900  }
901  }
902 
903  // Generic opcodes must not have physical register operands.
904  if (isPreISelGenericOpcode(MCID.getOpcode())) {
905  for (auto &Op : MI->operands()) {
907  report("Generic instruction cannot have physical register", MI);
908  }
909  }
910 
912  if (!TII->verifyInstruction(*MI, ErrorInfo))
913  report(ErrorInfo.data(), MI);
914 }
915 
916 void
917 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
918  const MachineInstr *MI = MO->getParent();
919  const MCInstrDesc &MCID = MI->getDesc();
920  unsigned NumDefs = MCID.getNumDefs();
921  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
922  NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
923 
924  // The first MCID.NumDefs operands must be explicit register defines
925  if (MONum < NumDefs) {
926  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
927  if (!MO->isReg())
928  report("Explicit definition must be a register", MO, MONum);
929  else if (!MO->isDef() && !MCOI.isOptionalDef())
930  report("Explicit definition marked as use", MO, MONum);
931  else if (MO->isImplicit())
932  report("Explicit definition marked as implicit", MO, MONum);
933  } else if (MONum < MCID.getNumOperands()) {
934  const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
935  // Don't check if it's the last operand in a variadic instruction. See,
936  // e.g., LDM_RET in the arm back end.
937  if (MO->isReg() &&
938  !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
939  if (MO->isDef() && !MCOI.isOptionalDef())
940  report("Explicit operand marked as def", MO, MONum);
941  if (MO->isImplicit())
942  report("Explicit operand marked as implicit", MO, MONum);
943  }
944 
945  int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
946  if (TiedTo != -1) {
947  if (!MO->isReg())
948  report("Tied use must be a register", MO, MONum);
949  else if (!MO->isTied())
950  report("Operand should be tied", MO, MONum);
951  else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
952  report("Tied def doesn't match MCInstrDesc", MO, MONum);
953  } else if (MO->isReg() && MO->isTied())
954  report("Explicit operand should not be tied", MO, MONum);
955  } else {
956  // ARM adds %reg0 operands to indicate predicates. We'll allow that.
957  if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
958  report("Extra explicit operand on non-variadic instruction", MO, MONum);
959  }
960 
961  switch (MO->getType()) {
963  const unsigned Reg = MO->getReg();
964  if (!Reg)
965  return;
966  if (MRI->tracksLiveness() && !MI->isDebugValue())
967  checkLiveness(MO, MONum);
968 
969  // Verify the consistency of tied operands.
970  if (MO->isTied()) {
971  unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
972  const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
973  if (!OtherMO.isReg())
974  report("Must be tied to a register", MO, MONum);
975  if (!OtherMO.isTied())
976  report("Missing tie flags on tied operand", MO, MONum);
977  if (MI->findTiedOperandIdx(OtherIdx) != MONum)
978  report("Inconsistent tie links", MO, MONum);
979  if (MONum < MCID.getNumDefs()) {
980  if (OtherIdx < MCID.getNumOperands()) {
981  if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
982  report("Explicit def tied to explicit use without tie constraint",
983  MO, MONum);
984  } else {
985  if (!OtherMO.isImplicit())
986  report("Explicit def should be tied to implicit use", MO, MONum);
987  }
988  }
989  }
990 
991  // Verify two-address constraints after leaving SSA form.
992  unsigned DefIdx;
993  if (!MRI->isSSA() && MO->isUse() &&
994  MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
995  Reg != MI->getOperand(DefIdx).getReg())
996  report("Two-address instruction operands must be identical", MO, MONum);
997 
998  // Check register classes.
999  if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
1000  unsigned SubIdx = MO->getSubReg();
1001 
1003  if (SubIdx) {
1004  report("Illegal subregister index for physical register", MO, MONum);
1005  return;
1006  }
1007  if (const TargetRegisterClass *DRC =
1008  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1009  if (!DRC->contains(Reg)) {
1010  report("Illegal physical register for instruction", MO, MONum);
1011  errs() << TRI->getName(Reg) << " is not a "
1012  << TRI->getRegClassName(DRC) << " register.\n";
1013  }
1014  }
1015  } else {
1016  // Virtual register.
1017  const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
1018  if (!RC) {
1019  // This is a generic virtual register.
1020 
1021  // If we're post-Select, we can't have gvregs anymore.
1022  if (isFunctionSelected) {
1023  report("Generic virtual register invalid in a Selected function",
1024  MO, MONum);
1025  return;
1026  }
1027 
1028  // The gvreg must have a type and it must not have a SubIdx.
1029  LLT Ty = MRI->getType(Reg);
1030  if (!Ty.isValid()) {
1031  report("Generic virtual register must have a valid type", MO,
1032  MONum);
1033  return;
1034  }
1035 
1036  const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
1037 
1038  // If we're post-RegBankSelect, the gvreg must have a bank.
1039  if (!RegBank && isFunctionRegBankSelected) {
1040  report("Generic virtual register must have a bank in a "
1041  "RegBankSelected function",
1042  MO, MONum);
1043  return;
1044  }
1045 
1046  // Make sure the register fits into its register bank if any.
1047  if (RegBank && Ty.isValid() &&
1048  RegBank->getSize() < Ty.getSizeInBits()) {
1049  report("Register bank is too small for virtual register", MO,
1050  MONum);
1051  errs() << "Register bank " << RegBank->getName() << " too small("
1052  << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
1053  << "-bits\n";
1054  return;
1055  }
1056  if (SubIdx) {
1057  report("Generic virtual register does not subregister index", MO,
1058  MONum);
1059  return;
1060  }
1061 
1062  // If this is a target specific instruction and this operand
1063  // has register class constraint, the virtual register must
1064  // comply to it.
1065  if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
1066  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1067  report("Virtual register does not match instruction constraint", MO,
1068  MONum);
1069  errs() << "Expect register class "
1070  << TRI->getRegClassName(
1071  TII->getRegClass(MCID, MONum, TRI, *MF))
1072  << " but got nothing\n";
1073  return;
1074  }
1075 
1076  break;
1077  }
1078  if (SubIdx) {
1079  const TargetRegisterClass *SRC =
1080  TRI->getSubClassWithSubReg(RC, SubIdx);
1081  if (!SRC) {
1082  report("Invalid subregister index for virtual register", MO, MONum);
1083  errs() << "Register class " << TRI->getRegClassName(RC)
1084  << " does not support subreg index " << SubIdx << "\n";
1085  return;
1086  }
1087  if (RC != SRC) {
1088  report("Invalid register class for subregister index", MO, MONum);
1089  errs() << "Register class " << TRI->getRegClassName(RC)
1090  << " does not fully support subreg index " << SubIdx << "\n";
1091  return;
1092  }
1093  }
1094  if (const TargetRegisterClass *DRC =
1095  TII->getRegClass(MCID, MONum, TRI, *MF)) {
1096  if (SubIdx) {
1097  const TargetRegisterClass *SuperRC =
1098  TRI->getLargestLegalSuperClass(RC, *MF);
1099  if (!SuperRC) {
1100  report("No largest legal super class exists.", MO, MONum);
1101  return;
1102  }
1103  DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
1104  if (!DRC) {
1105  report("No matching super-reg register class.", MO, MONum);
1106  return;
1107  }
1108  }
1109  if (!RC->hasSuperClassEq(DRC)) {
1110  report("Illegal virtual register for instruction", MO, MONum);
1111  errs() << "Expected a " << TRI->getRegClassName(DRC)
1112  << " register, but got a " << TRI->getRegClassName(RC)
1113  << " register\n";
1114  }
1115  }
1116  }
1117  }
1118  break;
1119  }
1120 
1122  regMasks.push_back(MO->getRegMask());
1123  break;
1124 
1126  if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
1127  report("PHI operand is not in the CFG", MO, MONum);
1128  break;
1129 
1131  if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
1132  LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1133  int FI = MO->getIndex();
1134  LiveInterval &LI = LiveStks->getInterval(FI);
1135  SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
1136 
1137  bool stores = MI->mayStore();
1138  bool loads = MI->mayLoad();
1139  // For a memory-to-memory move, we need to check if the frame
1140  // index is used for storing or loading, by inspecting the
1141  // memory operands.
1142  if (stores && loads) {
1143  for (auto *MMO : MI->memoperands()) {
1144  const PseudoSourceValue *PSV = MMO->getPseudoValue();
1145  if (PSV == nullptr) continue;
1148  if (Value == nullptr) continue;
1149  if (Value->getFrameIndex() != FI) continue;
1150 
1151  if (MMO->isStore())
1152  loads = false;
1153  else
1154  stores = false;
1155  break;
1156  }
1157  if (loads == stores)
1158  report("Missing fixed stack memoperand.", MI);
1159  }
1160  if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
1161  report("Instruction loads from dead spill slot", MO, MONum);
1162  errs() << "Live stack: " << LI << '\n';
1163  }
1164  if (stores && !LI.liveAt(Idx.getRegSlot())) {
1165  report("Instruction stores to dead spill slot", MO, MONum);
1166  errs() << "Live stack: " << LI << '\n';
1167  }
1168  }
1169  break;
1170 
1171  default:
1172  break;
1173  }
1174 }
1175 
1176 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
1177  unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
1178  LaneBitmask LaneMask) {
1179  LiveQueryResult LRQ = LR.Query(UseIdx);
1180  // Check if we have a segment at the use, note however that we only need one
1181  // live subregister range, the others may be dead.
1182  if (!LRQ.valueIn() && LaneMask.none()) {
1183  report("No live segment at use", MO, MONum);
1184  report_context_liverange(LR);
1185  report_context_vreg_regunit(VRegOrUnit);
1186  report_context(UseIdx);
1187  }
1188  if (MO->isKill() && !LRQ.isKill()) {
1189  report("Live range continues after kill flag", MO, MONum);
1190  report_context_liverange(LR);
1191  report_context_vreg_regunit(VRegOrUnit);
1192  if (LaneMask.any())
1193  report_context_lanemask(LaneMask);
1194  report_context(UseIdx);
1195  }
1196 }
1197 
1198 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
1199  unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
1200  LaneBitmask LaneMask) {
1201  if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
1202  assert(VNI && "NULL valno is not allowed");
1203  if (VNI->def != DefIdx) {
1204  report("Inconsistent valno->def", MO, MONum);
1205  report_context_liverange(LR);
1206  report_context_vreg_regunit(VRegOrUnit);
1207  if (LaneMask.any())
1208  report_context_lanemask(LaneMask);
1209  report_context(*VNI);
1210  report_context(DefIdx);
1211  }
1212  } else {
1213  report("No live segment at def", MO, MONum);
1214  report_context_liverange(LR);
1215  report_context_vreg_regunit(VRegOrUnit);
1216  if (LaneMask.any())
1217  report_context_lanemask(LaneMask);
1218  report_context(DefIdx);
1219  }
1220  // Check that, if the dead def flag is present, LiveInts agree.
1221  if (MO->isDead()) {
1222  LiveQueryResult LRQ = LR.Query(DefIdx);
1223  if (!LRQ.isDeadDef()) {
1224  // In case of physregs we can have a non-dead definition on another
1225  // operand.
1226  bool otherDef = false;
1227  if (!TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
1228  const MachineInstr &MI = *MO->getParent();
1229  for (const MachineOperand &MO : MI.operands()) {
1230  if (!MO.isReg() || !MO.isDef() || MO.isDead())
1231  continue;
1232  unsigned Reg = MO.getReg();
1233  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1234  if (*Units == VRegOrUnit) {
1235  otherDef = true;
1236  break;
1237  }
1238  }
1239  }
1240  }
1241 
1242  if (!otherDef) {
1243  report("Live range continues after dead def flag", MO, MONum);
1244  report_context_liverange(LR);
1245  report_context_vreg_regunit(VRegOrUnit);
1246  if (LaneMask.any())
1247  report_context_lanemask(LaneMask);
1248  }
1249  }
1250  }
1251 }
1252 
1253 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
1254  const MachineInstr *MI = MO->getParent();
1255  const unsigned Reg = MO->getReg();
1256 
1257  // Both use and def operands can read a register.
1258  if (MO->readsReg()) {
1259  regsLiveInButUnused.erase(Reg);
1260 
1261  if (MO->isKill())
1262  addRegWithSubRegs(regsKilled, Reg);
1263 
1264  // Check that LiveVars knows this kill.
1265  if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
1266  MO->isKill()) {
1267  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1268  if (!is_contained(VI.Kills, MI))
1269  report("Kill missing from LiveVariables", MO, MONum);
1270  }
1271 
1272  // Check LiveInts liveness and kill.
1273  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1274  SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
1275  // Check the cached regunit intervals.
1276  if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1277  for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1278  if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
1279  checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
1280  }
1281  }
1282 
1284  if (LiveInts->hasInterval(Reg)) {
1285  // This is a virtual register interval.
1286  const LiveInterval &LI = LiveInts->getInterval(Reg);
1287  checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
1288 
1289  if (LI.hasSubRanges() && !MO->isDef()) {
1290  unsigned SubRegIdx = MO->getSubReg();
1291  LaneBitmask MOMask = SubRegIdx != 0
1292  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1293  : MRI->getMaxLaneMaskForVReg(Reg);
1294  LaneBitmask LiveInMask;
1295  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1296  if ((MOMask & SR.LaneMask).none())
1297  continue;
1298  checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
1299  LiveQueryResult LRQ = SR.Query(UseIdx);
1300  if (LRQ.valueIn())
1301  LiveInMask |= SR.LaneMask;
1302  }
1303  // At least parts of the register has to be live at the use.
1304  if ((LiveInMask & MOMask).none()) {
1305  report("No live subrange at use", MO, MONum);
1306  report_context(LI);
1307  report_context(UseIdx);
1308  }
1309  }
1310  } else {
1311  report("Virtual register has no live interval", MO, MONum);
1312  }
1313  }
1314  }
1315 
1316  // Use of a dead register.
1317  if (!regsLive.count(Reg)) {
1319  // Reserved registers may be used even when 'dead'.
1320  bool Bad = !isReserved(Reg);
1321  // We are fine if just any subregister has a defined value.
1322  if (Bad) {
1323  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
1324  ++SubRegs) {
1325  if (regsLive.count(*SubRegs)) {
1326  Bad = false;
1327  break;
1328  }
1329  }
1330  }
1331  // If there is an additional implicit-use of a super register we stop
1332  // here. By definition we are fine if the super register is not
1333  // (completely) dead, if the complete super register is dead we will
1334  // get a report for its operand.
1335  if (Bad) {
1336  for (const MachineOperand &MOP : MI->uses()) {
1337  if (!MOP.isReg())
1338  continue;
1339  if (!MOP.isImplicit())
1340  continue;
1341  for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
1342  ++SubRegs) {
1343  if (*SubRegs == Reg) {
1344  Bad = false;
1345  break;
1346  }
1347  }
1348  }
1349  }
1350  if (Bad)
1351  report("Using an undefined physical register", MO, MONum);
1352  } else if (MRI->def_empty(Reg)) {
1353  report("Reading virtual register without a def", MO, MONum);
1354  } else {
1355  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1356  // We don't know which virtual registers are live in, so only complain
1357  // if vreg was killed in this MBB. Otherwise keep track of vregs that
1358  // must be live in. PHI instructions are handled separately.
1359  if (MInfo.regsKilled.count(Reg))
1360  report("Using a killed virtual register", MO, MONum);
1361  else if (!MI->isPHI())
1362  MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1363  }
1364  }
1365  }
1366 
1367  if (MO->isDef()) {
1368  // Register defined.
1369  // TODO: verify that earlyclobber ops are not used.
1370  if (MO->isDead())
1371  addRegWithSubRegs(regsDead, Reg);
1372  else
1373  addRegWithSubRegs(regsDefined, Reg);
1374 
1375  // Verify SSA form.
1376  if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1377  std::next(MRI->def_begin(Reg)) != MRI->def_end())
1378  report("Multiple virtual register defs in SSA form", MO, MONum);
1379 
1380  // Check LiveInts for a live segment, but only for virtual registers.
1381  if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1382  SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
1383  DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1384 
1386  if (LiveInts->hasInterval(Reg)) {
1387  const LiveInterval &LI = LiveInts->getInterval(Reg);
1388  checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
1389 
1390  if (LI.hasSubRanges()) {
1391  unsigned SubRegIdx = MO->getSubReg();
1392  LaneBitmask MOMask = SubRegIdx != 0
1393  ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1394  : MRI->getMaxLaneMaskForVReg(Reg);
1395  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1396  if ((SR.LaneMask & MOMask).none())
1397  continue;
1398  checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, SR.LaneMask);
1399  }
1400  }
1401  } else {
1402  report("Virtual register has no Live interval", MO, MONum);
1403  }
1404  }
1405  }
1406  }
1407 }
1408 
1409 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1410 }
1411 
1412 // This function gets called after visiting all instructions in a bundle. The
1413 // argument points to the bundle header.
1414 // Normal stand-alone instructions are also considered 'bundles', and this
1415 // function is called for all of them.
1416 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1417  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1418  set_union(MInfo.regsKilled, regsKilled);
1419  set_subtract(regsLive, regsKilled); regsKilled.clear();
1420  // Kill any masked registers.
1421  while (!regMasks.empty()) {
1422  const uint32_t *Mask = regMasks.pop_back_val();
1423  for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1426  regsDead.push_back(*I);
1427  }
1428  set_subtract(regsLive, regsDead); regsDead.clear();
1429  set_union(regsLive, regsDefined); regsDefined.clear();
1430 }
1431 
1432 void
1433 MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1434  MBBInfoMap[MBB].regsLiveOut = regsLive;
1435  regsLive.clear();
1436 
1437  if (Indexes) {
1438  SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1439  if (!(stop > lastIndex)) {
1440  report("Block ends before last instruction index", MBB);
1441  errs() << "Block ends at " << stop
1442  << " last instruction was at " << lastIndex << '\n';
1443  }
1444  lastIndex = stop;
1445  }
1446 }
1447 
1448 // Calculate the largest possible vregsPassed sets. These are the registers that
1449 // can pass through an MBB live, but may not be live every time. It is assumed
1450 // that all vregsPassed sets are empty before the call.
1451 void MachineVerifier::calcRegsPassed() {
1452  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1453  // have any vregsPassed.
1455  for (const auto &MBB : *MF) {
1456  BBInfo &MInfo = MBBInfoMap[&MBB];
1457  if (!MInfo.reachable)
1458  continue;
1460  SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1461  BBInfo &SInfo = MBBInfoMap[*SuI];
1462  if (SInfo.addPassed(MInfo.regsLiveOut))
1463  todo.insert(*SuI);
1464  }
1465  }
1466 
1467  // Iteratively push vregsPassed to successors. This will converge to the same
1468  // final state regardless of DenseSet iteration order.
1469  while (!todo.empty()) {
1470  const MachineBasicBlock *MBB = *todo.begin();
1471  todo.erase(MBB);
1472  BBInfo &MInfo = MBBInfoMap[MBB];
1474  SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1475  if (*SuI == MBB)
1476  continue;
1477  BBInfo &SInfo = MBBInfoMap[*SuI];
1478  if (SInfo.addPassed(MInfo.vregsPassed))
1479  todo.insert(*SuI);
1480  }
1481  }
1482 }
1483 
1484 // Calculate the set of virtual registers that must be passed through each basic
1485 // block in order to satisfy the requirements of successor blocks. This is very
1486 // similar to calcRegsPassed, only backwards.
1487 void MachineVerifier::calcRegsRequired() {
1488  // First push live-in regs to predecessors' vregsRequired.
1490  for (const auto &MBB : *MF) {
1491  BBInfo &MInfo = MBBInfoMap[&MBB];
1493  PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1494  BBInfo &PInfo = MBBInfoMap[*PrI];
1495  if (PInfo.addRequired(MInfo.vregsLiveIn))
1496  todo.insert(*PrI);
1497  }
1498  }
1499 
1500  // Iteratively push vregsRequired to predecessors. This will converge to the
1501  // same final state regardless of DenseSet iteration order.
1502  while (!todo.empty()) {
1503  const MachineBasicBlock *MBB = *todo.begin();
1504  todo.erase(MBB);
1505  BBInfo &MInfo = MBBInfoMap[MBB];
1507  PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1508  if (*PrI == MBB)
1509  continue;
1510  BBInfo &SInfo = MBBInfoMap[*PrI];
1511  if (SInfo.addRequired(MInfo.vregsRequired))
1512  todo.insert(*PrI);
1513  }
1514  }
1515 }
1516 
1517 // Check PHI instructions at the beginning of MBB. It is assumed that
1518 // calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1519 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1521  for (const auto &BBI : *MBB) {
1522  if (!BBI.isPHI())
1523  break;
1524  seen.clear();
1525 
1526  for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
1527  unsigned Reg = BBI.getOperand(i).getReg();
1528  const MachineBasicBlock *Pre = BBI.getOperand(i + 1).getMBB();
1529  if (!Pre->isSuccessor(MBB))
1530  continue;
1531  seen.insert(Pre);
1532  BBInfo &PrInfo = MBBInfoMap[Pre];
1533  if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1534  report("PHI operand is not live-out from predecessor",
1535  &BBI.getOperand(i), i);
1536  }
1537 
1538  // Did we see all predecessors?
1539  for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1540  PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1541  if (!seen.count(*PrI)) {
1542  report("Missing PHI operand", &BBI);
1543  errs() << "BB#" << (*PrI)->getNumber()
1544  << " is a predecessor according to the CFG.\n";
1545  }
1546  }
1547  }
1548 }
1549 
1550 void MachineVerifier::visitMachineFunctionAfter() {
1551  calcRegsPassed();
1552 
1553  for (const auto &MBB : *MF) {
1554  BBInfo &MInfo = MBBInfoMap[&MBB];
1555 
1556  // Skip unreachable MBBs.
1557  if (!MInfo.reachable)
1558  continue;
1559 
1560  checkPHIOps(&MBB);
1561  }
1562 
1563  // Now check liveness info if available
1564  calcRegsRequired();
1565 
1566  // Check for killed virtual registers that should be live out.
1567  for (const auto &MBB : *MF) {
1568  BBInfo &MInfo = MBBInfoMap[&MBB];
1569  for (RegSet::iterator
1570  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1571  ++I)
1572  if (MInfo.regsKilled.count(*I)) {
1573  report("Virtual register killed in block, but needed live out.", &MBB);
1574  errs() << "Virtual register " << PrintReg(*I)
1575  << " is used after the block.\n";
1576  }
1577  }
1578 
1579  if (!MF->empty()) {
1580  BBInfo &MInfo = MBBInfoMap[&MF->front()];
1581  for (RegSet::iterator
1582  I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1583  ++I) {
1584  report("Virtual register defs don't dominate all uses.", MF);
1585  report_context_vreg(*I);
1586  }
1587  }
1588 
1589  if (LiveVars)
1590  verifyLiveVariables();
1591  if (LiveInts)
1592  verifyLiveIntervals();
1593 }
1594 
1595 void MachineVerifier::verifyLiveVariables() {
1596  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1597  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1598  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1599  LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1600  for (const auto &MBB : *MF) {
1601  BBInfo &MInfo = MBBInfoMap[&MBB];
1602 
1603  // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1604  if (MInfo.vregsRequired.count(Reg)) {
1605  if (!VI.AliveBlocks.test(MBB.getNumber())) {
1606  report("LiveVariables: Block missing from AliveBlocks", &MBB);
1607  errs() << "Virtual register " << PrintReg(Reg)
1608  << " must be live through the block.\n";
1609  }
1610  } else {
1611  if (VI.AliveBlocks.test(MBB.getNumber())) {
1612  report("LiveVariables: Block should not be in AliveBlocks", &MBB);
1613  errs() << "Virtual register " << PrintReg(Reg)
1614  << " is not needed live through the block.\n";
1615  }
1616  }
1617  }
1618  }
1619 }
1620 
1621 void MachineVerifier::verifyLiveIntervals() {
1622  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1623  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1624  unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1625 
1626  // Spilling and splitting may leave unused registers around. Skip them.
1627  if (MRI->reg_nodbg_empty(Reg))
1628  continue;
1629 
1630  if (!LiveInts->hasInterval(Reg)) {
1631  report("Missing live interval for virtual register", MF);
1632  errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
1633  continue;
1634  }
1635 
1636  const LiveInterval &LI = LiveInts->getInterval(Reg);
1637  assert(Reg == LI.reg && "Invalid reg to interval mapping");
1638  verifyLiveInterval(LI);
1639  }
1640 
1641  // Verify all the cached regunit intervals.
1642  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1643  if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1644  verifyLiveRange(*LR, i);
1645 }
1646 
1647 void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1648  const VNInfo *VNI, unsigned Reg,
1649  LaneBitmask LaneMask) {
1650  if (VNI->isUnused())
1651  return;
1652 
1653  const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
1654 
1655  if (!DefVNI) {
1656  report("Value not live at VNInfo def and not marked unused", MF);
1657  report_context(LR, Reg, LaneMask);
1658  report_context(*VNI);
1659  return;
1660  }
1661 
1662  if (DefVNI != VNI) {
1663  report("Live segment at def has different VNInfo", MF);
1664  report_context(LR, Reg, LaneMask);
1665  report_context(*VNI);
1666  return;
1667  }
1668 
1669  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
1670  if (!MBB) {
1671  report("Invalid VNInfo definition index", MF);
1672  report_context(LR, Reg, LaneMask);
1673  report_context(*VNI);
1674  return;
1675  }
1676 
1677  if (VNI->isPHIDef()) {
1678  if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
1679  report("PHIDef VNInfo is not defined at MBB start", MBB);
1680  report_context(LR, Reg, LaneMask);
1681  report_context(*VNI);
1682  }
1683  return;
1684  }
1685 
1686  // Non-PHI def.
1687  const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
1688  if (!MI) {
1689  report("No instruction at VNInfo def index", MBB);
1690  report_context(LR, Reg, LaneMask);
1691  report_context(*VNI);
1692  return;
1693  }
1694 
1695  if (Reg != 0) {
1696  bool hasDef = false;
1697  bool isEarlyClobber = false;
1698  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
1699  if (!MOI->isReg() || !MOI->isDef())
1700  continue;
1702  if (MOI->getReg() != Reg)
1703  continue;
1704  } else {
1705  if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
1706  !TRI->hasRegUnit(MOI->getReg(), Reg))
1707  continue;
1708  }
1709  if (LaneMask.any() &&
1710  (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
1711  continue;
1712  hasDef = true;
1713  if (MOI->isEarlyClobber())
1714  isEarlyClobber = true;
1715  }
1716 
1717  if (!hasDef) {
1718  report("Defining instruction does not modify register", MI);
1719  report_context(LR, Reg, LaneMask);
1720  report_context(*VNI);
1721  }
1722 
1723  // Early clobber defs begin at USE slots, but other defs must begin at
1724  // DEF slots.
1725  if (isEarlyClobber) {
1726  if (!VNI->def.isEarlyClobber()) {
1727  report("Early clobber def must be at an early-clobber slot", MBB);
1728  report_context(LR, Reg, LaneMask);
1729  report_context(*VNI);
1730  }
1731  } else if (!VNI->def.isRegister()) {
1732  report("Non-PHI, non-early clobber def must be at a register slot", MBB);
1733  report_context(LR, Reg, LaneMask);
1734  report_context(*VNI);
1735  }
1736  }
1737 }
1738 
1739 void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
1741  unsigned Reg, LaneBitmask LaneMask)
1742 {
1743  const LiveRange::Segment &S = *I;
1744  const VNInfo *VNI = S.valno;
1745  assert(VNI && "Live segment has no valno");
1746 
1747  if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
1748  report("Foreign valno in live segment", MF);
1749  report_context(LR, Reg, LaneMask);
1750  report_context(S);
1751  report_context(*VNI);
1752  }
1753 
1754  if (VNI->isUnused()) {
1755  report("Live segment valno is marked unused", MF);
1756  report_context(LR, Reg, LaneMask);
1757  report_context(S);
1758  }
1759 
1760  const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
1761  if (!MBB) {
1762  report("Bad start of live segment, no basic block", MF);
1763  report_context(LR, Reg, LaneMask);
1764  report_context(S);
1765  return;
1766  }
1767  SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1768  if (S.start != MBBStartIdx && S.start != VNI->def) {
1769  report("Live segment must begin at MBB entry or valno def", MBB);
1770  report_context(LR, Reg, LaneMask);
1771  report_context(S);
1772  }
1773 
1774  const MachineBasicBlock *EndMBB =
1775  LiveInts->getMBBFromIndex(S.end.getPrevSlot());
1776  if (!EndMBB) {
1777  report("Bad end of live segment, no basic block", MF);
1778  report_context(LR, Reg, LaneMask);
1779  report_context(S);
1780  return;
1781  }
1782 
1783  // No more checks for live-out segments.
1784  if (S.end == LiveInts->getMBBEndIdx(EndMBB))
1785  return;
1786 
1787  // RegUnit intervals are allowed dead phis.
1788  if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
1789  S.start == VNI->def && S.end == VNI->def.getDeadSlot())
1790  return;
1791 
1792  // The live segment is ending inside EndMBB
1793  const MachineInstr *MI =
1794  LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
1795  if (!MI) {
1796  report("Live segment doesn't end at a valid instruction", EndMBB);
1797  report_context(LR, Reg, LaneMask);
1798  report_context(S);
1799  return;
1800  }
1801 
1802  // The block slot must refer to a basic block boundary.
1803  if (S.end.isBlock()) {
1804  report("Live segment ends at B slot of an instruction", EndMBB);
1805  report_context(LR, Reg, LaneMask);
1806  report_context(S);
1807  }
1808 
1809  if (S.end.isDead()) {
1810  // Segment ends on the dead slot.
1811  // That means there must be a dead def.
1812  if (!SlotIndex::isSameInstr(S.start, S.end)) {
1813  report("Live segment ending at dead slot spans instructions", EndMBB);
1814  report_context(LR, Reg, LaneMask);
1815  report_context(S);
1816  }
1817  }
1818 
1819  // A live segment can only end at an early-clobber slot if it is being
1820  // redefined by an early-clobber def.
1821  if (S.end.isEarlyClobber()) {
1822  if (I+1 == LR.end() || (I+1)->start != S.end) {
1823  report("Live segment ending at early clobber slot must be "
1824  "redefined by an EC def in the same instruction", EndMBB);
1825  report_context(LR, Reg, LaneMask);
1826  report_context(S);
1827  }
1828  }
1829 
1830  // The following checks only apply to virtual registers. Physreg liveness
1831  // is too weird to check.
1833  // A live segment can end with either a redefinition, a kill flag on a
1834  // use, or a dead flag on a def.
1835  bool hasRead = false;
1836  bool hasSubRegDef = false;
1837  bool hasDeadDef = false;
1838  for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
1839  if (!MOI->isReg() || MOI->getReg() != Reg)
1840  continue;
1841  unsigned Sub = MOI->getSubReg();
1842  LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
1843  : LaneBitmask::getAll();
1844  if (MOI->isDef()) {
1845  if (Sub != 0) {
1846  hasSubRegDef = true;
1847  // An operand vreg0:sub0<def> reads vreg0:sub1..n. Invert the lane
1848  // mask for subregister defs. Read-undef defs will be handled by
1849  // readsReg below.
1850  SLM = ~SLM;
1851  }
1852  if (MOI->isDead())
1853  hasDeadDef = true;
1854  }
1855  if (LaneMask.any() && (LaneMask & SLM).none())
1856  continue;
1857  if (MOI->readsReg())
1858  hasRead = true;
1859  }
1860  if (S.end.isDead()) {
1861  // Make sure that the corresponding machine operand for a "dead" live
1862  // range has the dead flag. We cannot perform this check for subregister
1863  // liveranges as partially dead values are allowed.
1864  if (LaneMask.none() && !hasDeadDef) {
1865  report("Instruction ending live segment on dead slot has no dead flag",
1866  MI);
1867  report_context(LR, Reg, LaneMask);
1868  report_context(S);
1869  }
1870  } else {
1871  if (!hasRead) {
1872  // When tracking subregister liveness, the main range must start new
1873  // values on partial register writes, even if there is no read.
1874  if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
1875  !hasSubRegDef) {
1876  report("Instruction ending live segment doesn't read the register",
1877  MI);
1878  report_context(LR, Reg, LaneMask);
1879  report_context(S);
1880  }
1881  }
1882  }
1883  }
1884 
1885  // Now check all the basic blocks in this live segment.
1887  // Is this live segment the beginning of a non-PHIDef VN?
1888  if (S.start == VNI->def && !VNI->isPHIDef()) {
1889  // Not live-in to any blocks.
1890  if (MBB == EndMBB)
1891  return;
1892  // Skip this block.
1893  ++MFI;
1894  }
1895  for (;;) {
1896  assert(LiveInts->isLiveInToMBB(LR, &*MFI));
1897  // We don't know how to track physregs into a landing pad.
1899  MFI->isEHPad()) {
1900  if (&*MFI == EndMBB)
1901  break;
1902  ++MFI;
1903  continue;
1904  }
1905 
1906  // Is VNI a PHI-def in the current block?
1907  bool IsPHI = VNI->isPHIDef() &&
1908  VNI->def == LiveInts->getMBBStartIdx(&*MFI);
1909 
1910  // Check that VNI is live-out of all predecessors.
1911  for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
1912  PE = MFI->pred_end(); PI != PE; ++PI) {
1913  SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1914  const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
1915 
1916  // All predecessors must have a live-out value if this is not a
1917  // subregister liverange.
1918  if (!PVNI && LaneMask.none()) {
1919  report("Register not marked live out of predecessor", *PI);
1920  report_context(LR, Reg, LaneMask);
1921  report_context(*VNI);
1922  errs() << " live into BB#" << MFI->getNumber()
1923  << '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
1924  << PEnd << '\n';
1925  continue;
1926  }
1927 
1928  // Only PHI-defs can take different predecessor values.
1929  if (!IsPHI && PVNI != VNI) {
1930  report("Different value live out of predecessor", *PI);
1931  report_context(LR, Reg, LaneMask);
1932  errs() << "Valno #" << PVNI->id << " live out of BB#"
1933  << (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id
1934  << " live into BB#" << MFI->getNumber() << '@'
1935  << LiveInts->getMBBStartIdx(&*MFI) << '\n';
1936  }
1937  }
1938  if (&*MFI == EndMBB)
1939  break;
1940  ++MFI;
1941  }
1942 }
1943 
1944 void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
1945  LaneBitmask LaneMask) {
1946  for (const VNInfo *VNI : LR.valnos)
1947  verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1948 
1949  for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
1950  verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1951 }
1952 
1953 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1954  unsigned Reg = LI.reg;
1956  verifyLiveRange(LI, Reg);
1957 
1958  LaneBitmask Mask;
1959  LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
1960  for (const LiveInterval::SubRange &SR : LI.subranges()) {
1961  if ((Mask & SR.LaneMask).any()) {
1962  report("Lane masks of sub ranges overlap in live interval", MF);
1963  report_context(LI);
1964  }
1965  if ((SR.LaneMask & ~MaxMask).any()) {
1966  report("Subrange lanemask is invalid", MF);
1967  report_context(LI);
1968  }
1969  if (SR.empty()) {
1970  report("Subrange must not be empty", MF);
1971  report_context(SR, LI.reg, SR.LaneMask);
1972  }
1973  Mask |= SR.LaneMask;
1974  verifyLiveRange(SR, LI.reg, SR.LaneMask);
1975  if (!LI.covers(SR)) {
1976  report("A Subrange is not covered by the main range", MF);
1977  report_context(LI);
1978  }
1979  }
1980 
1981  // Check the LI only has one connected component.
1982  ConnectedVNInfoEqClasses ConEQ(*LiveInts);
1983  unsigned NumComp = ConEQ.Classify(LI);
1984  if (NumComp > 1) {
1985  report("Multiple connected components in live interval", MF);
1986  report_context(LI);
1987  for (unsigned comp = 0; comp != NumComp; ++comp) {
1988  errs() << comp << ": valnos";
1990  E = LI.vni_end(); I!=E; ++I)
1991  if (comp == ConEQ.getEqClass(*I))
1992  errs() << ' ' << (*I)->id;
1993  errs() << '\n';
1994  }
1995  }
1996 }
1997 
1998 namespace {
1999  // FrameSetup and FrameDestroy can have zero adjustment, so using a single
2000  // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
2001  // value is zero.
2002  // We use a bool plus an integer to capture the stack state.
2003  struct StackStateOfBB {
2004  StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
2005  ExitIsSetup(false) { }
2006  StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
2007  EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
2008  ExitIsSetup(ExitSetup) { }
2009  // Can be negative, which means we are setting up a frame.
2010  int EntryValue;
2011  int ExitValue;
2012  bool EntryIsSetup;
2013  bool ExitIsSetup;
2014  };
2015 }
2016 
2017 /// Make sure on every path through the CFG, a FrameSetup <n> is always followed
2018 /// by a FrameDestroy <n>, stack adjustments are identical on all
2019 /// CFG edges to a merge point, and frame is destroyed at end of a return block.
2020 void MachineVerifier::verifyStackFrame() {
2021  unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
2022  unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
2023 
2025  SPState.resize(MF->getNumBlockIDs());
2027 
2028  // Visit the MBBs in DFS order.
2029  for (df_ext_iterator<const MachineFunction*,
2031  DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
2032  DFI != DFE; ++DFI) {
2033  const MachineBasicBlock *MBB = *DFI;
2034 
2035  StackStateOfBB BBState;
2036  // Check the exit state of the DFS stack predecessor.
2037  if (DFI.getPathLength() >= 2) {
2038  const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
2039  assert(Reachable.count(StackPred) &&
2040  "DFS stack predecessor is already visited.\n");
2041  BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
2042  BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
2043  BBState.ExitValue = BBState.EntryValue;
2044  BBState.ExitIsSetup = BBState.EntryIsSetup;
2045  }
2046 
2047  // Update stack state by checking contents of MBB.
2048  for (const auto &I : *MBB) {
2049  if (I.getOpcode() == FrameSetupOpcode) {
2050  // The first operand of a FrameOpcode should be i32.
2051  int Size = I.getOperand(0).getImm();
2052  assert(Size >= 0 &&
2053  "Value should be non-negative in FrameSetup and FrameDestroy.\n");
2054 
2055  if (BBState.ExitIsSetup)
2056  report("FrameSetup is after another FrameSetup", &I);
2057  BBState.ExitValue -= Size;
2058  BBState.ExitIsSetup = true;
2059  }
2060 
2061  if (I.getOpcode() == FrameDestroyOpcode) {
2062  // The first operand of a FrameOpcode should be i32.
2063  int Size = I.getOperand(0).getImm();
2064  assert(Size >= 0 &&
2065  "Value should be non-negative in FrameSetup and FrameDestroy.\n");
2066 
2067  if (!BBState.ExitIsSetup)
2068  report("FrameDestroy is not after a FrameSetup", &I);
2069  int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
2070  BBState.ExitValue;
2071  if (BBState.ExitIsSetup && AbsSPAdj != Size) {
2072  report("FrameDestroy <n> is after FrameSetup <m>", &I);
2073  errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
2074  << AbsSPAdj << ">.\n";
2075  }
2076  BBState.ExitValue += Size;
2077  BBState.ExitIsSetup = false;
2078  }
2079  }
2080  SPState[MBB->getNumber()] = BBState;
2081 
2082  // Make sure the exit state of any predecessor is consistent with the entry
2083  // state.
2084  for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
2085  E = MBB->pred_end(); I != E; ++I) {
2086  if (Reachable.count(*I) &&
2087  (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
2088  SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
2089  report("The exit stack state of a predecessor is inconsistent.", MBB);
2090  errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
2091  << SPState[(*I)->getNumber()].ExitValue << ", "
2092  << SPState[(*I)->getNumber()].ExitIsSetup
2093  << "), while BB#" << MBB->getNumber() << " has entry state ("
2094  << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
2095  }
2096  }
2097 
2098  // Make sure the entry state of any successor is consistent with the exit
2099  // state.
2100  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
2101  E = MBB->succ_end(); I != E; ++I) {
2102  if (Reachable.count(*I) &&
2103  (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
2104  SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
2105  report("The entry stack state of a successor is inconsistent.", MBB);
2106  errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
2107  << SPState[(*I)->getNumber()].EntryValue << ", "
2108  << SPState[(*I)->getNumber()].EntryIsSetup
2109  << "), while BB#" << MBB->getNumber() << " has exit state ("
2110  << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
2111  }
2112  }
2113 
2114  // Make sure a basic block with return ends with zero stack adjustment.
2115  if (!MBB->empty() && MBB->back().isReturn()) {
2116  if (BBState.ExitIsSetup)
2117  report("A return block ends with a FrameSetup.", MBB);
2118  if (BBState.ExitValue)
2119  report("A return block ends with a nonzero stack adjustment.", MBB);
2120  }
2121  }
2122 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:81
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:217
bool isImplicit() const
unsigned succ_size() const
void print(raw_ostream &OS, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isEHPad() const
Returns true if the block is a landing pad.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:157
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
const unsigned reg
Definition: LiveInterval.h:656
iterator_range< livein_iterator > liveins() const
bool isGenericType() const
Definition: MCInstrDesc.h:101
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
size_t i
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:334
bool hasProperty(Property P) const
MachineBasicBlock * getMBB() const
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
Implements a dense probed hash-table based set.
Definition: DenseSet.h:202
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:166
static LaneBitmask getAll()
Definition: LaneBitmask.h:75
DWARF-like instruction based exceptions.
vni_iterator vni_begin()
Definition: LiveInterval.h:213
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static bool matchPair(MachineBasicBlock::const_succ_iterator i, const MachineBasicBlock *a, const MachineBasicBlock *b)
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:380
bool isTied() const
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:108
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
A live range for subregisters.
Definition: LiveInterval.h:632
MachineBasicBlock reference.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
Definition: SlotIndexes.h:226
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:365
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
unsigned getNumValNums() const
Definition: LiveInterval.h:288
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:396
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
Definition: SlotIndexes.h:222
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
void initializeMachineVerifierPassPass(PassRegistry &)
Mask of preserved registers.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
safe Safe Stack instrumentation pass
Definition: SafeStack.cpp:796
bool test(unsigned Idx)
A description of a memory reference used in the backend.
void clear()
clear - Clear all bits.
Definition: BitVector.h:188
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
bool isPHI() const
Definition: MachineInstr.h:786
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
iterator end()
Definition: LiveInterval.h:206
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:710
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
Result of a LiveRange query.
Definition: LiveInterval.h:86
const MachineFunctionProperties & getProperties() const
Get the function properties.
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1218
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
Definition: SlotIndexes.h:219
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:252
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
Definition: LiveVariables.h:84
constexpr bool any() const
Definition: LaneBitmask.h:51
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:77
const MachineBasicBlock & front() const
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:229
bool isKill() const
SlotIndexes pass.
Definition: SlotIndexes.h:323
MachineBasicBlock * MBB
Function Alias Analysis false
int64_t getImm() const
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:216
INITIALIZE_PASS(MachineVerifierPass,"machineverifier","Verify generated machine code", false, false) FunctionPass *llvm
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:282
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:777
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:359
bool isDeadDef() const
Return true if this instruction has a dead def.
Definition: LiveInterval.h:113
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:516
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:144
unsigned const MachineRegisterInfo * MRI
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
constexpr bool none() const
Definition: LaneBitmask.h:50
size_type size() const
Definition: SmallPtrSet.h:99
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
unsigned getGenericTypeIndex() const
Definition: MCInstrDesc.h:106
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:404
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:538
iterator begin() const
Definition: SmallPtrSet.h:398
self_iterator getIterator()
Definition: ilist_node.h:81
LLVM_NODISCARD bool empty() const
Definition: SmallPtrSet.h:98
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:376
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:74
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:52
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
unsigned id
The ID number of this value.
Definition: LiveInterval.h:50
Iterator for intrusive lists based on ilist_node.
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
Definition: SmallPtrSet.h:375
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:190
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
Definition: LiveInterval.h:892
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:789
static LaneBitmask getNone()
Definition: LaneBitmask.h:74
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
This class implements the register bank concept.
Definition: RegisterBank.h:29
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or "(null)".
Special value supplied for machine level alias analysis.
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
void setPreservesAll()
Set by analyses that do not transform their input at all.
Base class for user error types.
VNInfoList valnos
Definition: LiveInterval.h:196
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
Definition: LiveInterval.h:292
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Definition: SetOperations.h:63
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
TerminatorInst * getTerminator()
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:124
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
bool isValid() const
Definition: LowLevelType.h:88
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:55
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
Abstract Stack Frame Index.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block) ...
Definition: SlotIndexes.h:500
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:247
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
aarch64 promote const
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:71
static LLVM_ATTRIBUTE_UNUSED Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:82
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:125
Primary interface to the complete machine description for the target machine.
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:104
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index...
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
ppc ctr loops verify
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:101
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:738
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range...
vni_iterator vni_end()
Definition: LiveInterval.h:214
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
Definition: SetOperations.h:23
unsigned pred_size() const
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:431
hexagon widen stores
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
Definition: LiveInterval.h:404
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:358
void resize(size_type N)
Definition: SmallVector.h:352
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:783