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LLVM
4.0.0
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#include <HexagonInstrInfo.h>
Definition at line 36 of file HexagonInstrInfo.h.
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explicit |
Definition at line 126 of file HexagonInstrInfo.cpp.
| bool HexagonInstrInfo::addLatencyToSchedule | ( | const MachineInstr & | MI1, |
| const MachineInstr & | MI2 | ||
| ) | const |
Definition at line 2847 of file HexagonInstrInfo.cpp.
References isV60VectorInstruction(), and isVecUsableNextPacket().
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Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g.
This function can analyze one/two way branching only and should (mostly) be called by target independent side.
it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
Note that removeBranch and insertBranch must be implemented to support cases where this method returns success.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
First entry is always the opcode of the branching instruction, except when the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a BB with only unconditional jump. Subsequent entries depend upon the opcode, e.g. Jump_c p will have Cond[0] = Jump_c Cond[1] = p HW-loop ENDLOOP: Cond[0] = ENDLOOP Cond[1] = MBB New value jump: Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 – specific opcode Cond[1] = R Cond[2] = Imm
Definition at line 366 of file HexagonInstrInfo.cpp.
References llvm::SmallVectorImpl< T >::clear(), llvm::MachineOperand::CreateImm(), llvm::dbgs(), DEBUG, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineBasicBlock::getNumber(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), isEndLoopN(), llvm::MachineBasicBlock::isLayoutSuccessor(), llvm::MachineOperand::isMBB(), isNewValueJump(), PredOpcodeHasJMP_c(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by insertBranch().
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For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 1514 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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Analyze the loop code, return true if it cannot be understood.
Analyze the loop code to find the loop induction variable and compare used to compute the number of iterations.
Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end.
Currently, we analyze loop that are controlled using hardware loops. In this case, the induction variable instruction is null. For all other cases, this function returns true, which means we're unable to analyze it.
Definition at line 660 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::end(), llvm::MachineLoop::getBottomBlock(), llvm::MachineBasicBlock::getFirstTerminator(), I, and isEndLoopN().
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Definition at line 1615 of file HexagonInstrInfo.cpp.
References getBaseAndOffset(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), isMemOp(), and llvm::MachineInstr::mayLoad().
| bool HexagonInstrInfo::canExecuteInBundle | ( | const MachineInstr & | First, |
| const MachineInstr & | Second | ||
| ) | const |
Can these instructions execute at the same time in a bundle.
Definition at line 2867 of file HexagonInstrInfo.cpp.
References DisableNVSchedule, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and mayBeNewStore().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), and llvm::HexagonPacketizerList::producesStall().
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Emit instructions to copy a pair of physical registers.
This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.
The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
Definition at line 753 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::dbgs(), llvm::getKillRegState(), llvm::MachineBasicBlock::getNumber(), getRegisterInfo(), llvm_unreachable, and llvm::PrintReg().
Referenced by expandPostRAPseudo().
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Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Definition at line 1501 of file HexagonInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::MachineFunction::getSubtarget(), llvm::ScheduleDAG::MF, and UseDFAHazardRec.
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Create machine specific model for scheduling.
Definition at line 1605 of file HexagonInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData().
| unsigned HexagonInstrInfo::createVR | ( | MachineFunction * | MF, |
| MVT | VT | ||
| ) | const |
Definition at line 1670 of file HexagonInstrInfo.cpp.
References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MVT::f32, llvm::MVT::f64, llvm::MachineFunction::getRegInfo(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm_unreachable, and MRI.
Referenced by reduceLoopCount().
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If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.
Definition at line 1411 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().
| bool HexagonInstrInfo::doesNotReturn | ( | const MachineInstr & | CallMI | ) | const |
Definition at line 2887 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isSchedulingBoundary().
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This function is called for all pseudo instructions that remain after register allocation.
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation.
Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Definition at line 998 of file HexagonInstrInfo.cpp.
References addOperand(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), copyPhysReg(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::getDebugLoc(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), getLiveRegsAt(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::RegState::Implicit, llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, MBB, llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), MI, MRI, Offset, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::RegState::Undef.
| void HexagonInstrInfo::genAllInsnTimingClasses | ( | MachineFunction & | MF | ) | const |
Definition at line 4106 of file HexagonInstrInfo.cpp.
References A, B, llvm::MachineBasicBlock::begin(), llvm::MachineFunction::begin(), llvm::BuildMI(), llvm::dbgs(), DEBUG, llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDesc(), getName(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), and I.
| short HexagonInstrInfo::getAbsoluteForm | ( | const MachineInstr & | MI | ) | const |
Definition at line 3039 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| unsigned HexagonInstrInfo::getAddrMode | ( | const MachineInstr & | MI | ) | const |
Definition at line 3043 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, F, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by getBaseAndOffset(), getNonExtOpcode(), hasNonExtEquivalent(), isAbsoluteSet(), and isPostIncrement().
| unsigned HexagonInstrInfo::getBaseAndOffset | ( | const MachineInstr & | MI, |
| int & | Offset, | ||
| unsigned & | AccessSize | ||
| ) | const |
Definition at line 3050 of file HexagonInstrInfo.cpp.
References assert(), llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), getBaseAndOffsetPosition(), llvm::MachineOperand::getImm(), getMemAccessSize(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), isMemOp(), and isPostIncrement().
Referenced by areMemAccessesTriviallyDisjoint(), getIncrementValue(), and getMemOpBaseRegImmOfs().
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For instructions with a base and offset, return the position of the base register and offset operands.
Return the position of the base and offset operands for this instruction.
Definition at line 3085 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), isMemOp(), isPostIncrement(), isPredicated(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by getBaseAndOffset().
| short HexagonInstrInfo::getBaseWithLongOffset | ( | short | Opcode | ) | const |
Definition at line 3176 of file HexagonInstrInfo.cpp.
| short HexagonInstrInfo::getBaseWithLongOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 3182 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| short HexagonInstrInfo::getBaseWithRegOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 3186 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| SmallVector< MachineInstr *, 2 > HexagonInstrInfo::getBranchingInstrs | ( | MachineBasicBlock & | MBB | ) | const |
Definition at line 3119 of file HexagonInstrInfo.cpp.
References I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
| unsigned HexagonInstrInfo::getCExtOpNum | ( | const MachineInstr & | MI | ) | const |
Definition at line 3191 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by immediateExtend(), and isConstExtended().
| HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3198 of file HexagonInstrInfo.cpp.
References contains(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, llvm::HexagonII::HCG_C, llvm::HexagonII::HCG_None, llvm::MachineOperand::isImm(), and isIntRegForSubInst().
Referenced by getCompoundOpcode().
| unsigned HexagonInstrInfo::getCompoundOpcode | ( | const MachineInstr & | GA, |
| const MachineInstr & | GB | ||
| ) | const |
Definition at line 3287 of file HexagonInstrInfo.cpp.
References assert(), getCompoundCandidateGroup(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::HexagonII::HCG_A, llvm::HexagonII::HCG_B, and llvm::MachineInstr::readsRegister().
| int HexagonInstrInfo::getCondOpcode | ( | int | Opc, |
| bool | sense | ||
| ) | const |
Definition at line 3304 of file HexagonInstrInfo.cpp.
References llvm_unreachable.
Referenced by PredicateInstruction().
| int HexagonInstrInfo::getDotCurOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3316 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm_unreachable.
Referenced by llvm::HexagonPacketizerList::promoteToDotCur().
| int HexagonInstrInfo::getDotNewOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 3412 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm_unreachable.
Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::HexagonHazardRecognizer::getHazardType(), and llvm::HexagonPacketizerList::promoteToDotNew().
| int HexagonInstrInfo::getDotNewPredJumpOp | ( | const MachineInstr & | MI, |
| const MachineBranchProbabilityInfo * | MBPI | ||
| ) | const |
Definition at line 3456 of file HexagonInstrInfo.cpp.
References llvm::MachineBranchProbabilityInfo::getEdgeProbability(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), and llvm_unreachable.
Referenced by getDotNewPredOp().
| int HexagonInstrInfo::getDotNewPredOp | ( | const MachineInstr & | MI, |
| const MachineBranchProbabilityInfo * | MBPI | ||
| ) | const |
Definition at line 3480 of file HexagonInstrInfo.cpp.
References assert(), getDotNewPredJumpOp(), and llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::promoteToDotNew().
| int HexagonInstrInfo::getDotOldOp | ( | const int | opc | ) | const |
Definition at line 3498 of file HexagonInstrInfo.cpp.
References assert(), isNewValueStore(), isPredicated(), and isPredicatedNew().
Referenced by llvm::HexagonPacketizerList::demoteToDotOld().
| HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup | ( | const MachineInstr & | MI | ) | const |
Definition at line 3515 of file HexagonInstrInfo.cpp.
References contains(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, isDblRegForSubInst(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), and isIntRegForSubInst().
Referenced by isDuplexPair().
| short HexagonInstrInfo::getEquivalentHWInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 3857 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| MachineInstr * HexagonInstrInfo::getFirstNonDbgInst | ( | MachineBasicBlock * | BB | ) | const |
Definition at line 3862 of file HexagonInstrInfo.cpp.
References llvm::WebAssembly::End, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isDebugValue(), and MI.
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If the instruction is an increment of a constant value, return the amount.
Definition at line 1656 of file HexagonInstrInfo.cpp.
References getBaseAndOffset(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and isPostIncrement().
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Measure the specified inline asm to determine an approximation of its length.
Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that. Hexagon counts the number of ##'s and adjust for that many constant exenders.
Definition at line 1475 of file HexagonInstrInfo.cpp.
References llvm::StringRef::count(), llvm::StringRef::data(), llvm::MCAsmInfo::getCommentString(), llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), and llvm::StringRef::size().
Referenced by getSize().
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Compute the instruction latency of a given instruction.
If the instruction has higher cost when predicated, it's returned via PredCost.
Definition at line 1599 of file HexagonInstrInfo.cpp.
References getInstrTimingClassLatency().
Referenced by getInstrTimingClassLatency().
| unsigned HexagonInstrInfo::getInstrTimingClassLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr & | MI | ||
| ) | const |
Definition at line 3873 of file HexagonInstrInfo.cpp.
References EnableTimingClassLatency, llvm::MachineInstr::getDesc(), getInstrLatency(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::getStageLatency(), llvm::MachineFunction::getSubtarget(), llvm::MachineInstr::isTransient(), and llvm::Latency.
Referenced by getInstrLatency().
Definition at line 3906 of file HexagonInstrInfo.cpp.
References isPredicatedTrue(), and llvm_unreachable.
Referenced by getInvertedPredSense(), invertAndChangeJumpTarget(), reverseBranchCondition(), and reversePredSense().
| bool HexagonInstrInfo::getInvertedPredSense | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const |
Definition at line 3897 of file HexagonInstrInfo.cpp.
References llvm::SmallVectorBase::empty(), and getInvertedPredicatedOpcode().
| int HexagonInstrInfo::getMaxValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 3917 of file HexagonInstrInfo.cpp.
References bits, llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by isConstExtended().
| unsigned HexagonInstrInfo::getMemAccessSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 3930 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::HexagonII::MemAccesSizeMask, llvm::HexagonII::MemAccessSizePos, and llvm::MCInstrDesc::TSFlags.
Referenced by getBaseAndOffset().
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Get the base register and byte offset of a load/store instr.
Definition at line 2856 of file HexagonInstrInfo.cpp.
References getBaseAndOffset().
| int HexagonInstrInfo::getMinValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 3936 of file HexagonInstrInfo.cpp.
References bits, llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by isConstExtended().
| short HexagonInstrInfo::getNonExtOpcode | ( | const MachineInstr & | MI | ) | const |
Definition at line 3950 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().
| bool HexagonInstrInfo::getPredReg | ( | ArrayRef< MachineOperand > | Cond, |
| unsigned & | PredReg, | ||
| unsigned & | PredRegPos, | ||
| unsigned & | PredRegFlags | ||
| ) | const |
Definition at line 3974 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), DEBUG, llvm::ArrayRef< T >::empty(), llvm::RegState::Implicit, isNewValueJump(), llvm::ArrayRef< T >::size(), and llvm::RegState::Undef.
Referenced by PredicateInstruction().
| short HexagonInstrInfo::getPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 3994 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| short HexagonInstrInfo::getRegForm | ( | const MachineInstr & | MI | ) | const |
Definition at line 3998 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
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HexagonInstrInfo specifics.
Definition at line 296 of file HexagonInstrInfo.h.
Referenced by copyPhysReg(), DefinesPredicate(), expandPostRAPseudo(), getDuplexCandidateGroup(), llvm::HexagonSubtarget::getRegisterInfo(), isDependent(), reduceLoopCount(), and llvm::VirtRegMap::runOnMachineFunction().
| unsigned HexagonInstrInfo::getSize | ( | const MachineInstr & | MI | ) | const |
Definition at line 4006 of file HexagonInstrInfo.cpp.
References assert(), BranchRelaxAsmLarge, llvm::MachineInstr::getDesc(), getInlineAsmLength(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), HEXAGON_INSTR_SIZE, llvm::ISD::INLINEASM, isConstExtended(), llvm::MachineInstr::isDebugValue(), llvm::MachineOperand::isDef(), isExtended(), llvm::MachineInstr::isPosition(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isSymbol(), and MBB.
| uint64_t HexagonInstrInfo::getType | ( | const MachineInstr & | MI | ) | const |
Definition at line 4040 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by cannotCoexistAsymm(), isCompoundBranchInstr(), and isV60VectorInstruction().
| unsigned HexagonInstrInfo::getUnits | ( | const MachineInstr & | MI | ) | const |
Definition at line 4045 of file HexagonInstrInfo.cpp.
References llvm::InstrItineraryData::beginStage(), llvm::MachineInstr::getDesc(), llvm::TargetSubtargetInfo::getInstrItineraryData(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSchedClass(), llvm::MachineFunction::getSubtarget(), llvm::InstrStage::getUnits(), and llvm::ARM_MB::ST.
Definition at line 4053 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::validSubTargetMask, and llvm::HexagonII::validSubTargetPos.
| bool HexagonInstrInfo::hasEHLabel | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 2892 of file HexagonInstrInfo.cpp.
References I.
| bool HexagonInstrInfo::hasNonExtEquivalent | ( | const MachineInstr & | MI | ) | const |
Definition at line 2901 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, llvm::HexagonII::BaseLongOffset, getAddrMode(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().
| bool HexagonInstrInfo::hasPseudoInstrPair | ( | const MachineInstr & | MI | ) | const |
Definition at line 2936 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| bool HexagonInstrInfo::hasUncondBranch | ( | const MachineBasicBlock * | B | ) | const |
Definition at line 2941 of file HexagonInstrInfo.cpp.
References E, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), and I.
| void HexagonInstrInfo::immediateExtend | ( | MachineInstr & | MI | ) | const |
immediateExtend - Changes the instruction in place to one using an immediate extender.
Definition at line 4073 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::addTargetFlag(), assert(), getCExtOpNum(), llvm::MachineInstr::getOperand(), llvm::HexagonII::HMOTF_ConstExtended, isConstExtended(), isExtendable(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isMBB().
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Insert branch code into the end of the specified MachineBasicBlock.
The operands to this method are the same as those returned by AnalyzeBranch. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions inserted.
It is also invoked by tail merging to add unconditional branches in cases where AnalyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.
Definition at line 559 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), analyzeBranch(), assert(), llvm::BuildMI(), llvm::dbgs(), DEBUG, llvm::ArrayRef< T >::empty(), llvm::MachineBasicBlock::end(), findLoopInstr(), fuzzer::Flags, llvm::MachineBasicBlock::getFirstTerminator(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getNumber(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getReg(), llvm::getUndefRegState(), isEndLoopN(), isNewValueJump(), isPredicated(), isReg(), llvm::MachineOperand::isUndef(), llvm_unreachable, removeBranch(), reverseBranchCondition(), llvm::MachineOperand::setMBB(), llvm::ArrayRef< T >::size(), and validateBranchCond().
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Insert a noop into the instruction stream at the specified point.
Definition at line 1331 of file HexagonInstrInfo.cpp.
References llvm::BuildMI().
| bool HexagonInstrInfo::invertAndChangeJumpTarget | ( | MachineInstr & | MI, |
| MachineBasicBlock * | NewTarget | ||
| ) | const |
Definition at line 4086 of file HexagonInstrInfo.cpp.
References assert(), llvm::dbgs(), DEBUG, llvm::MachineInstr::dump(), EnableBranchPrediction, getInvertedPredicatedOpcode(), llvm::MachineBasicBlock::getNumber(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isBranch(), llvm::MachineOperand::isMBB(), isPredicatedNew(), reversePrediction(), llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setMBB().
| bool HexagonInstrInfo::isAbsoluteSet | ( | const MachineInstr & | MI | ) | const |
Definition at line 1687 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AbsoluteSet, and getAddrMode().
| bool HexagonInstrInfo::isAccumulator | ( | const MachineInstr & | MI | ) | const |
Definition at line 1691 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::AccumulatorMask, llvm::HexagonII::AccumulatorPos, F, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
Referenced by isVecAcc().
| bool HexagonInstrInfo::isComplex | ( | const MachineInstr & | MI | ) | const |
Definition at line 1696 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isCall(), isMemOp(), llvm::MachineInstr::isReturn(), isTC1(), isTC2Early(), llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), and TII.
| bool HexagonInstrInfo::isCompoundBranchInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 1717 of file HexagonInstrInfo.cpp.
References getType(), llvm::MachineInstr::isBranch(), and llvm::HexagonII::TypeCOMPOUND.
| bool HexagonInstrInfo::isCondInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 1721 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::isBranch(), isConditionalALU32(), isConditionalLoad(), isConditionalTransfer(), isNewValueStore(), isPredicated(), isPredicatedNew(), and llvm::MachineInstr::mayStore().
Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew(), and llvm::HexagonPacketizerList::isNewifiable().
| bool HexagonInstrInfo::isConditionalALU32 | ( | const MachineInstr & | MI | ) | const |
Definition at line 1731 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isCondInst().
| bool HexagonInstrInfo::isConditionalLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 1790 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), isPredicated(), and llvm::MCInstrDesc::mayLoad().
Referenced by isCondInst().
| bool HexagonInstrInfo::isConditionalStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 1803 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| bool HexagonInstrInfo::isConditionalTransfer | ( | const MachineInstr & | MI | ) | const |
Definition at line 1856 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isCondInst().
| bool HexagonInstrInfo::isConstExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 1878 of file HexagonInstrInfo.cpp.
References assert(), llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F, getCExtOpNum(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), getMaxValue(), getMinValue(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getTargetFlags(), llvm::HexagonII::HMOTF_ConstExtended, llvm::MachineOperand::isBlockAddress(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isCPI(), isExtendable(), isExtended(), llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isJTI(), llvm::MachineOperand::isMBB(), llvm::MachineOperand::isSymbol(), and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonPacketizerList::addToPacket(), getSize(), and immediateExtend().
| bool HexagonInstrInfo::isDeallocRet | ( | const MachineInstr & | MI | ) | const |
Definition at line 1924 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonPacketizerList::hasV4SpecificDependence(), and llvm::HexagonPacketizerList::isCallDependent().
| bool HexagonInstrInfo::isDependent | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI | ||
| ) | const |
Definition at line 1939 of file HexagonInstrInfo.cpp.
References contains(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), getRegisterInfo(), llvm::MCRegisterInfo::DiffListIterator::isValid(), and parseOperands().
Referenced by producesStall().
| bool HexagonInstrInfo::isDotCurInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 1975 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::canPromoteToDotCur(), and llvm::HexagonPacketizerList::isLegalToPacketizeTogether().
| bool HexagonInstrInfo::isDotNewInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 1988 of file HexagonInstrInfo.cpp.
References isNewValueInst(), isPredicated(), and isPredicatedNew().
Referenced by llvm::HexagonPacketizerList::arePredicatesComplements(), llvm::HexagonPacketizerList::canPromoteToDotNew(), and llvm::HexagonPacketizerList::canPromoteToNewValueStore().
| bool HexagonInstrInfo::isDuplexPair | ( | const MachineInstr & | MIa, |
| const MachineInstr & | MIb | ||
| ) | const |
Symmetrical. See if these two instructions are fit for duplex pair.
Definition at line 1996 of file HexagonInstrInfo.cpp.
References getDuplexCandidateGroup(), and isDuplexPairMatch().
| bool HexagonInstrInfo::isEarlySourceInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2003 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), llvm::MachineInstr::isCompare(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by isLateInstrFeedsEarlyInstr().
Definition at line 2014 of file HexagonInstrInfo.cpp.
Referenced by analyzeBranch(), analyzeLoop(), insertBranch(), PredicateInstruction(), reduceLoopCount(), and reverseBranchCondition().
Definition at line 2019 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::MO_BlockAddress, llvm::MachineOperand::MO_ConstantPoolIndex, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_JumpTableIndex, and llvm::MachineOperand::MO_MachineBasicBlock.
| bool HexagonInstrInfo::isExtendable | ( | const MachineInstr & | MI | ) | const |
Definition at line 2033 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, F, llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), and llvm::MCInstrDesc::TSFlags.
Referenced by immediateExtend(), and isConstExtended().
| bool HexagonInstrInfo::isExtended | ( | const MachineInstr & | MI | ) | const |
Definition at line 2055 of file HexagonInstrInfo.cpp.
References E, llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F, llvm::MachineInstr::getDesc(), llvm::HexagonII::HMOTF_ConstExtended, I, llvm::MachineInstr::operands_begin(), llvm::MachineInstr::operands_end(), and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonPacketizerList::addToPacket(), getSize(), and isConstExtended().
| bool HexagonInstrInfo::isFloat | ( | const MachineInstr & | MI | ) | const |
Definition at line 2070 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::FPMask, llvm::HexagonII::FPPos, and llvm::MachineInstr::getOpcode().
| bool HexagonInstrInfo::isHVXMemWithAIndirect | ( | const MachineInstr & | I, |
| const MachineInstr & | J | ||
| ) | const |
Definition at line 2077 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::isIndirectBranch(), isIndirectCall(), isIndirectL4Return(), isV60VectorInstruction(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by cannotCoexistAsymm().
| bool HexagonInstrInfo::isIndirectCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2086 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::isCallDependent(), and isHVXMemWithAIndirect().
| bool HexagonInstrInfo::isIndirectL4Return | ( | const MachineInstr & | MI | ) | const |
Definition at line 2097 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by isHVXMemWithAIndirect().
| bool HexagonInstrInfo::isJumpR | ( | const MachineInstr & | MI | ) | const |
Definition at line 2111 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonPacketizerList::isCallDependent(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), and llvm::HexagonPacketizerList::isNewifiable().
| bool HexagonInstrInfo::isJumpWithinBranchRange | ( | const MachineInstr & | MI, |
| unsigned | offset | ||
| ) | const |
Definition at line 2129 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isNewValueJump().
| bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr | ( | const MachineInstr & | LRMI, |
| const MachineInstr & | ESMI | ||
| ) | const |
Definition at line 2169 of file HexagonInstrInfo.cpp.
References llvm::dbgs(), DEBUG, llvm::MachineInstr::dump(), isEarlySourceInstr(), and isLateResultInstr().
Referenced by llvm::HexagonPacketizerList::producesStall().
| bool HexagonInstrInfo::isLateResultInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2187 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), and llvm::ISD::INLINEASM.
Referenced by isLateInstrFeedsEarlyInstr().
| bool HexagonInstrInfo::isLateSourceInstr | ( | const MachineInstr & | MI | ) | const |
Definition at line 2223 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::getSchedClass().
Referenced by isVecUsableNextPacket().
|
override |
TargetInstrInfo overrides.
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot.
If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 249 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
| bool HexagonInstrInfo::isLoopN | ( | const MachineInstr & | MI | ) | const |
Definition at line 2229 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::hasControlDependence(), and llvm::HexagonPacketizerList::isLegalToPacketizeTogether().
| bool HexagonInstrInfo::isMemOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2241 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by areMemAccessesTriviallyDisjoint(), getBaseAndOffset(), getBaseAndOffsetPosition(), llvm::HexagonPacketizerList::hasV4SpecificDependence(), and isComplex().
| bool HexagonInstrInfo::isNewValue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2273 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::HexagonII::NewValueMask, llvm::HexagonII::NewValuePos, and llvm::MCInstrDesc::TSFlags.
Referenced by isNewValueJump(), and isPredictedTaken().
Definition at line 2278 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::NewValueMask, and llvm::HexagonII::NewValuePos.
| bool HexagonInstrInfo::isNewValueInst | ( | const MachineInstr & | MI | ) | const |
Definition at line 2283 of file HexagonInstrInfo.cpp.
References isNewValueJump(), and isNewValueStore().
Referenced by llvm::HexagonPacketizerList::hasV4SpecificDependence(), and isDotNewInst().
| bool HexagonInstrInfo::isNewValueJump | ( | const MachineInstr & | MI | ) | const |
Definition at line 2287 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::isBranch(), and isNewValue().
Referenced by analyzeBranch(), getPredReg(), llvm::HexagonPacketizerList::hasControlDependence(), insertBranch(), isJumpWithinBranchRange(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isNewValueInst(), and PredicateInstruction().
Definition at line 2291 of file HexagonInstrInfo.cpp.
References isBranch(), isNewValue(), and isPredicated().
| bool HexagonInstrInfo::isNewValueStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 2295 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::HexagonII::NVStoreMask, llvm::HexagonII::NVStorePos, and llvm::MCInstrDesc::TSFlags.
Referenced by getDotOldOp(), isCondInst(), and isNewValueInst().
Definition at line 2300 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.
| bool HexagonInstrInfo::isOperandExtended | ( | const MachineInstr & | MI, |
| unsigned | OperandNum | ||
| ) | const |
Definition at line 2306 of file HexagonInstrInfo.cpp.
References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.
|
override |
Return true for post-incremented instructions.
Definition at line 1337 of file HexagonInstrInfo.cpp.
References getAddrMode(), and llvm::HexagonII::PostInc.
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), getBaseAndOffset(), getBaseAndOffsetPosition(), getIncrementValue(), and getPostIncrementOperand().
|
override |
Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 1427 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isPredicable().
Referenced by PredicateInstruction().
|
override |
Returns true if the instruction is already predicated.
Definition at line 1349 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::HexagonII::PredicatedMask, llvm::HexagonII::PredicatedPos, and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore(), getBaseAndOffsetPosition(), getDotOldOp(), getPredicatedRegister(), getPredicateSense(), llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonPacketizerList::hasDeadDependence(), insertBranch(), llvm::HexagonPacketizerList::isCallDependent(), isCondInst(), isConditionalLoad(), isDotNewInst(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isNewValueJump(), isPredicatedNew(), predOpcodeHasNot(), and llvm::HexagonPacketizerList::restrictingDepExistInPacket().
Definition at line 2339 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
| bool HexagonInstrInfo::isPredicatedNew | ( | const MachineInstr & | MI | ) | const |
Definition at line 2313 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::MachineInstr::getDesc(), isPredicated(), llvm::HexagonII::PredicatedNewMask, llvm::HexagonII::PredicatedNewPos, and llvm::MCInstrDesc::TSFlags.
Referenced by getDotOldOp(), llvm::HexagonPacketizerList::hasControlDependence(), invertAndChangeJumpTarget(), isCondInst(), isDotNewInst(), and isPredictedTaken().
Definition at line 2319 of file HexagonInstrInfo.cpp.
References assert(), F, isPredicated(), llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.
| bool HexagonInstrInfo::isPredicatedTrue | ( | const MachineInstr & | MI | ) | const |
Definition at line 2325 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, and llvm::MCInstrDesc::TSFlags.
Referenced by getInvertedPredicatedOpcode(), getPredicateSense(), and predOpcodeHasNot().
Definition at line 2331 of file HexagonInstrInfo.cpp.
References assert(), F, llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.
Definition at line 2344 of file HexagonInstrInfo.cpp.
References F, llvm::HexagonII::PredicateLateMask, and llvm::HexagonII::PredicateLatePos.
Definition at line 2349 of file HexagonInstrInfo.cpp.
References assert(), F, isBranch(), isNewValue(), isPredicatedNew(), llvm::HexagonII::TakenMask, and llvm::HexagonII::TakenPos.
Referenced by reversePrediction().
|
override |
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion.
The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 748 of file HexagonInstrInfo.cpp.
|
override |
Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 735 of file HexagonInstrInfo.cpp.
References nonDbgBBSize().
|
override |
Second variant of isProfitableToIfCvt.
This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutally exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 741 of file HexagonInstrInfo.cpp.
References nonDbgBBSize().
| bool HexagonInstrInfo::isSaveCalleeSavedRegsCall | ( | const MachineInstr & | MI | ) | const |
Definition at line 2356 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::hasControlDependence().
|
override |
Test if the given instruction should be considered a scheduling boundary.
This primarily includes labels and terminators.
Definition at line 1431 of file HexagonInstrInfo.cpp.
References doesNotReturn(), llvm::MachineInstr::getDesc(), I, llvm::MachineInstr::isCall(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::isPosition(), llvm::MCInstrDesc::isTerminator(), ScheduleInlineAsm, and llvm::MachineBasicBlock::successors().
| bool HexagonInstrInfo::isSignExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2363 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
| bool HexagonInstrInfo::isSolo | ( | const MachineInstr & | MI | ) | const |
Definition at line 2441 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::HexagonII::SoloMask, llvm::HexagonII::SoloPos, and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonPacketizerList::isSoloInstruction().
| bool HexagonInstrInfo::isSpillPredRegOp | ( | const MachineInstr & | MI | ) | const |
Definition at line 2446 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
|
override |
If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot.
If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 299 of file HexagonInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().
|
override |
Definition at line 2456 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::isBranch(), and llvm::MachineInstr::operands().
Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().
| bool HexagonInstrInfo::isTC1 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2467 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::getSchedClass().
Referenced by isComplex().
| bool HexagonInstrInfo::isTC2 | ( | const MachineInstr & | MI | ) | const |
Definition at line 2485 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::getSchedClass().
| bool HexagonInstrInfo::isTC2Early | ( | const MachineInstr & | MI | ) | const |
Definition at line 2501 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::getSchedClass().
Referenced by isComplex().
| bool HexagonInstrInfo::isTC4x | ( | const MachineInstr & | MI | ) | const |
Definition at line 2521 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::getSchedClass().
| bool HexagonInstrInfo::isToBeScheduledASAP | ( | const MachineInstr & | MI1, |
| const MachineInstr & | MI2 | ||
| ) | const |
Definition at line 2527 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isReg(), mayBeCurLoad(), mayBeNewStore(), and N.
Referenced by llvm::HexagonSubtarget::adjustSchedDependency().
| bool HexagonInstrInfo::isV60VectorInstruction | ( | const MachineInstr & | MI | ) | const |
Definition at line 2545 of file HexagonInstrInfo.cpp.
References getType(), llvm::HexagonII::TypeCVI_FIRST, and llvm::HexagonII::TypeCVI_LAST.
Referenced by addLatencyToSchedule(), llvm::HexagonPacketizerList::canPromoteToDotCur(), isHVXMemWithAIndirect(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::HexagonPacketizerList::isNewifiable(), isVecAcc(), llvm::HexagonPacketizerList::producesStall(), and producesStall().
Definition at line 2552 of file HexagonInstrInfo.cpp.
References Hexagon_MEMB_AUTOINC_MAX, Hexagon_MEMB_AUTOINC_MIN, Hexagon_MEMD_AUTOINC_MAX, Hexagon_MEMD_AUTOINC_MIN, Hexagon_MEMH_AUTOINC_MAX, Hexagon_MEMH_AUTOINC_MIN, Hexagon_MEMV_AUTOINC_MAX, Hexagon_MEMV_AUTOINC_MAX_128B, Hexagon_MEMV_AUTOINC_MIN, Hexagon_MEMV_AUTOINC_MIN_128B, Hexagon_MEMW_AUTOINC_MAX, Hexagon_MEMW_AUTOINC_MIN, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, llvm::MVT::v128i8, llvm::MVT::v16i32, llvm::MVT::v16i64, llvm::MVT::v32i16, llvm::MVT::v32i32, llvm::MVT::v64i16, llvm::MVT::v64i8, and llvm::MVT::v8i64.
Definition at line 2588 of file HexagonInstrInfo.cpp.
References Hexagon_ADDI_OFFSET_MAX, Hexagon_ADDI_OFFSET_MIN, Hexagon_MEMB_OFFSET_MAX, Hexagon_MEMB_OFFSET_MIN, Hexagon_MEMD_OFFSET_MAX, Hexagon_MEMD_OFFSET_MIN, Hexagon_MEMH_OFFSET_MAX, Hexagon_MEMH_OFFSET_MIN, Hexagon_MEMV_OFFSET_MAX, Hexagon_MEMV_OFFSET_MAX_128B, Hexagon_MEMV_OFFSET_MIN, Hexagon_MEMV_OFFSET_MIN_128B, Hexagon_MEMW_OFFSET_MAX, Hexagon_MEMW_OFFSET_MIN, llvm::ISD::INLINEASM, llvm_unreachable, and Offset.
Referenced by llvm::HexagonPacketizerList::useCallersSP().
| bool HexagonInstrInfo::isVecAcc | ( | const MachineInstr & | MI | ) | const |
Definition at line 2742 of file HexagonInstrInfo.cpp.
References isAccumulator(), and isV60VectorInstruction().
Referenced by isVecUsableNextPacket().
| bool HexagonInstrInfo::isVecALU | ( | const MachineInstr & | MI | ) | const |
Definition at line 2746 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getOpcode(), llvm::HexagonII::TypeCVI_VA, llvm::HexagonII::TypeCVI_VA_DV, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.
Referenced by isVecUsableNextPacket().
| bool HexagonInstrInfo::isVecUsableNextPacket | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI | ||
| ) | const |
Definition at line 2754 of file HexagonInstrInfo.cpp.
References EnableACCForwarding, EnableALUForwarding, isLateSourceInstr(), isVecAcc(), isVecALU(), and mayBeNewStore().
Referenced by addLatencyToSchedule(), llvm::HexagonPacketizerList::producesStall(), and producesStall().
| bool HexagonInstrInfo::isZeroExtendingLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2768 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
|
override |
Load the specified register of the given register class from the specified stack frame index.
The load instruction is to be added to the given machine basic block before the specified machine instruction.
Definition at line 928 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm_unreachable, and llvm::MachineMemOperand::MOLoad.
| bool HexagonInstrInfo::mayBeCurLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 2953 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::HexagonII::mayCVLoadMask, llvm::HexagonII::mayCVLoadPos, and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonHazardRecognizer::EmitInstruction(), and isToBeScheduledASAP().
| bool HexagonInstrInfo::mayBeNewStore | ( | const MachineInstr & | MI | ) | const |
Definition at line 2961 of file HexagonInstrInfo.cpp.
References F, llvm::MachineInstr::getDesc(), llvm::HexagonII::mayNVStoreMask, llvm::HexagonII::mayNVStorePos, and llvm::MCInstrDesc::TSFlags.
Referenced by canExecuteInBundle(), llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::HexagonPacketizerList::canPromoteToNewValue(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::HexagonHazardRecognizer::getHazardType(), llvm::HexagonPacketizerList::isNewifiable(), isToBeScheduledASAP(), and isVecUsableNextPacket().
| unsigned HexagonInstrInfo::nonDbgBBSize | ( | const MachineBasicBlock * | BB | ) | const |
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Class information, if available.
Definition at line 4059 of file HexagonInstrInfo.cpp.
References llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), and nonDbgMICount().
Referenced by isProfitableToIfCvt().
| unsigned HexagonInstrInfo::nonDbgBundleSize | ( | MachineBasicBlock::const_iterator | BundleHead | ) | const |
Definition at line 4063 of file HexagonInstrInfo.cpp.
References assert(), llvm::getBundleEnd(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), and nonDbgMICount().
| bool HexagonInstrInfo::predCanBeUsedAsDotNew | ( | const MachineInstr & | MI, |
| unsigned | PredReg | ||
| ) | const |
Definition at line 3010 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), and llvm::MachineOperand::isReg().
Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew().
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override |
Convert the instruction into a predicated instruction.
It returns true if the operation was successful.
Definition at line 1354 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), B, llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::dbgs(), DEBUG, llvm::MachineInstr::dump(), llvm::ArrayRef< T >::empty(), llvm::MachineBasicBlock::erase(), getCondOpcode(), llvm::MachineInstr::getDebugLoc(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getPredReg(), llvm::MachineFunction::getRegInfo(), i, llvm::MachineOperand::isDef(), isEndLoopN(), llvm::MachineOperand::isImplicit(), isNewValueJump(), isPredicable(), llvm::MachineOperand::isReg(), MRI, predOpcodeHasNot(), llvm::MachineInstr::RemoveOperand(), and llvm::MachineInstr::setDesc().
Definition at line 3024 of file HexagonInstrInfo.cpp.
Referenced by analyzeBranch().
| bool HexagonInstrInfo::predOpcodeHasNot | ( | ArrayRef< MachineOperand > | Cond | ) | const |
Definition at line 3033 of file HexagonInstrInfo.cpp.
References llvm::ArrayRef< T >::empty(), isPredicated(), and isPredicatedTrue().
Referenced by PredicateInstruction().
| bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | ProdMI, |
| const MachineInstr & | ConsMI | ||
| ) | const |
Definition at line 2966 of file HexagonInstrInfo.cpp.
References isDependent(), isV60VectorInstruction(), and isVecUsableNextPacket().
Referenced by producesStall().
| bool HexagonInstrInfo::producesStall | ( | const MachineInstr & | MI, |
| MachineBasicBlock::const_instr_iterator | MII | ||
| ) | const |
Definition at line 2984 of file HexagonInstrInfo.cpp.
References isV60VectorInstruction(), isVecUsableNextPacket(), and producesStall().
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override |
Generate code to reduce the loop iteration by one and check if the loop is finished.
Return the value/register of the the new loop count. We need this function when peeling off one or more iterations of a loop. This function assumes the nth iteration is peeled first.
Return the value/register of the new loop count. this function assumes the nth iteration is peeled first.
Definition at line 678 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), assert(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::BuildMI(), llvm::SmallVectorImpl< T >::clear(), llvm::MachineOperand::CreateImm(), createVR(), E, llvm::SmallVectorTemplateCommon< T >::end(), llvm::MachineInstr::eraseFromParent(), findLoopInstr(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), I, llvm::MVT::i1, llvm::MVT::i32, isEndLoopN(), Offset, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineOperand::setImm(), and llvm::MachineInstr::substituteRegister().
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override |
Remove the branching code at the end of the specific MBB.
This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.
Definition at line 536 of file HexagonInstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::back(), llvm::MachineBasicBlock::begin(), llvm::dbgs(), DEBUG, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineBasicBlock::getNumber(), I, and llvm_unreachable.
Referenced by insertBranch().
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override |
Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Definition at line 1316 of file HexagonInstrInfo.cpp.
References assert(), llvm::SmallVectorBase::empty(), getInvertedPredicatedOpcode(), isBranch(), and isEndLoopN().
Referenced by insertBranch().
Definition at line 4134 of file HexagonInstrInfo.cpp.
References assert(), and isPredictedTaken().
Referenced by invertAndChangeJumpTarget().
| bool HexagonInstrInfo::reversePredSense | ( | MachineInstr & | MI | ) | const |
Definition at line 4127 of file HexagonInstrInfo.cpp.
References llvm::dbgs(), DEBUG, llvm::MachineInstr::dump(), getInvertedPredicatedOpcode(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::setDesc().
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override |
Store the specified register of the given register class to the specified stack frame index.
The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Definition at line 862 of file HexagonInstrInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm_unreachable, and llvm::MachineMemOperand::MOStore.
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override |
Returns true if the first specified predicate subsumes the second, e.g.
GE subsumes GT.
Definition at line 1405 of file HexagonInstrInfo.cpp.
| bool HexagonInstrInfo::validateBranchCond | ( | const ArrayRef< MachineOperand > & | Cond | ) | const |
Definition at line 4145 of file HexagonInstrInfo.cpp.
References llvm::ArrayRef< T >::empty(), and llvm::ArrayRef< T >::size().
Referenced by insertBranch().
| short HexagonInstrInfo::xformRegToImmOffset | ( | const MachineInstr & | MI | ) | const |
Definition at line 4150 of file HexagonInstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
1.8.6