30 #define DEBUG_TYPE "mips16-instrinfo"
61 const DebugLoc &DL,
unsigned DestReg,
62 unsigned SrcReg,
bool KillSrc)
const {
65 if (Mips::CPU16RegsRegClass.
contains(DestReg) &&
66 Mips::GPR32RegClass.
contains(SrcReg))
67 Opc = Mips::MoveR3216;
68 else if (Mips::GPR32RegClass.
contains(DestReg) &&
69 Mips::CPU16RegsRegClass.
contains(SrcReg))
70 Opc = Mips::Move32R16;
71 else if ((SrcReg == Mips::HI0) &&
72 (Mips::CPU16RegsRegClass.
contains(DestReg)))
73 Opc = Mips::Mfhi16, SrcReg = 0;
75 else if ((SrcReg == Mips::LO0) &&
76 (Mips::CPU16RegsRegClass.
contains(DestReg)))
77 Opc = Mips::Mflo16, SrcReg = 0;
80 assert(Opc &&
"Cannot copy registers");
93 unsigned SrcReg,
bool isKill,
int FI,
98 if (I != MBB.
end()) DL = I->getDebugLoc();
101 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
102 Opc = Mips::SwRxSpImmX16;
103 assert(Opc &&
"Register class not handled!");
105 addFrameIndex(FI).
addImm(Offset)
111 unsigned DestReg,
int FI,
116 if (I != MBB.
end()) DL = I->getDebugLoc();
120 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
121 Opc = Mips::LwRxSpImmX16;
122 assert(Opc &&
"Register class not handled!");
133 ExpandRetRA16(MBB, MI, Mips::JrcRa16);
145 case Mips::BeqzRxImmX16:
return Mips::BnezRxImmX16;
146 case Mips::BnezRxImmX16:
return Mips::BeqzRxImmX16;
147 case Mips::BeqzRxImm16:
return Mips::BnezRxImm16;
148 case Mips::BnezRxImm16:
return Mips::BeqzRxImm16;
149 case Mips::BteqzT8CmpX16:
return Mips::BtnezT8CmpX16;
150 case Mips::BteqzT8SltX16:
return Mips::BtnezT8SltX16;
151 case Mips::BteqzT8SltiX16:
return Mips::BtnezT8SltiX16;
152 case Mips::Btnez16:
return Mips::Bteqz16;
153 case Mips::BtnezX16:
return Mips::BteqzX16;
154 case Mips::BtnezT8CmpiX16:
return Mips::BteqzT8CmpiX16;
155 case Mips::BtnezT8SltuX16:
return Mips::BteqzT8SltuX16;
156 case Mips::BtnezT8SltiuX16:
return Mips::BteqzT8SltiuX16;
157 case Mips::Bteqz16:
return Mips::Btnez16;
158 case Mips::BteqzX16:
return Mips::BtnezX16;
159 case Mips::BteqzT8CmpiX16:
return Mips::BtnezT8CmpiX16;
160 case Mips::BteqzT8SltuX16:
return Mips::BtnezT8SltuX16;
161 case Mips::BteqzT8SltiuX16:
return Mips::BtnezT8SltiuX16;
162 case Mips::BtnezT8CmpX16:
return Mips::BteqzT8CmpX16;
163 case Mips::BtnezT8SltX16:
return Mips::BteqzT8SltX16;
164 case Mips::BtnezT8SltiX16:
return Mips::BteqzT8SltiX16;
170 const std::vector<CalleeSavedInfo> &CSI,
171 unsigned Flags = 0) {
172 for (
unsigned i = 0, e = CSI.size();
i != e; ++
i) {
178 unsigned Reg = CSI[e-
i-1].getReg();
201 bool SaveS2 = Reserved[Mips::S2];
203 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
204 MIB =
BuildMI(MBB, I, DL,
get(Opc));
209 if (isUInt<11>(FrameSize))
214 int64_t Remainder = FrameSize - Base;
219 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
231 bool SaveS2 = Reserved[Mips::S2];
233 unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
234 Mips::Restore16:Mips::RestoreX16;
236 if (!isUInt<11>(FrameSize)) {
237 unsigned Base = 2040;
238 int64_t Remainder = FrameSize - Base;
245 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
247 MIB =
BuildMI(MBB, I, DL,
get(Opc));
260 void Mips16InstrInfo::adjustStackPtrBig(
unsigned SP, int64_t Amount,
263 unsigned Reg1,
unsigned Reg2)
const {
284 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
300 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
309 unsigned &NewImm)
const {
323 int32_t lo = Imm & 0xFFFF;
337 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
339 for (
unsigned i = 0, e = II->getNumOperands();
i != e; ++
i) {
355 for (
unsigned i = 0, e = II->getNumOperands();
i != e; ++
i) {
364 Available &= Candidates;
369 unsigned FirstRegSaved =0, SecondRegSaved=0;
370 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
376 Candidates.
reset(Reg);
379 FirstRegSavedTo = Mips::T0;
380 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved,
true);
384 Available.
reset(Reg);
387 if (FrameReg == Mips::SP) {
392 if (DefReg!= SpReg) {
393 SecondRegSaved = SpReg;
397 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved,
true);
400 Available.
reset(SpReg);
406 BuildMI(MBB, II, DL,
get(Mips:: AdduRxRyRz16), Reg).
addReg(FrameReg)
408 if (FirstRegSaved || SecondRegSaved) {
411 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo,
true);
413 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo,
true);
418 unsigned Mips16InstrInfo::getAnalyzableBrOpc(
unsigned Opc)
const {
419 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
420 Opc == Mips::Bimm16 ||
421 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
422 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
423 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
424 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
425 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
426 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
427 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
428 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
429 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
430 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
435 unsigned Opc)
const {
436 BuildMI(MBB, I, I->getDebugLoc(),
get(Opc));
441 return get(Mips::AddiuSpImm16);
443 return get(Mips::AddiuSpImmX16);
459 case Mips::LbRxRyOffMemX16:
460 case Mips::LbuRxRyOffMemX16:
461 case Mips::LhRxRyOffMemX16:
462 case Mips::LhuRxRyOffMemX16:
463 case Mips::SbRxRyOffMemX16:
464 case Mips::ShRxRyOffMemX16:
465 case Mips::LwRxRyOffMemX16:
466 case Mips::SwRxRyOffMemX16:
467 case Mips::SwRxSpImmX16:
468 case Mips::LwRxSpImmX16:
470 case Mips::AddiuRxRyOffMemX16:
471 if ((Reg ==
Mips::PC) || (Reg == Mips::SP))
473 return isInt<15>(Amount);
494 bool atInsnStart =
true;
496 for (; *Str; ++Str) {
500 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
501 if (strncmp(Str,
".space", 6)==0) {
503 Sz = strtol(Str+6, &EStr, 10);
504 while (isspace(*EStr)) ++EStr;
506 DEBUG(
dbgs() <<
"parsed .space " << Sz <<
'\n');
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Describe properties that are true of each instruction in the target description file.
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
constexpr bool isInt< 16 >(int64_t x)
return AArch64::GPR64RegClass contains(Reg)
static void addSaveRestoreRegs(MachineInstrBuilder &MIB, const std::vector< CalleeSavedInfo > &CSI, unsigned Flags=0)
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
StringRef getCommentString() const
A description of a memory reference used in the backend.
struct fuzzer::@269 Flags
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void forward()
Move the internal MBB iterator and update register states.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
BitVector getReservedRegs(const MachineFunction &MF) const override
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
unsigned getKillRegState(bool B)
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
const MachineBasicBlock * getParent() const
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
This class is intended to be used as a base class for asm properties and features specific to the tar...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
self_iterator getIterator()
bool expandPostRAPseudo(MachineInstr &MI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool validSpImm8(int offset)
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getOpcode() const
Return the opcode number for this descriptor.
The memory access writes data.
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
MachineOperand class - Representation of each machine instruction operand.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
The memory access reads data.
Representation of each machine instruction.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
const char * getSeparatorString() const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
Mips16InstrInfo(const MipsSubtarget &STI)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getMaxInstLength() const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.