54 struct MachineVerifier {
56 MachineVerifier(
Pass *
pass,
const char *b) :
74 bool isFunctionRegBankSelected;
75 bool isFunctionSelected;
84 BlockSet FunctionBlocks;
88 RegVector regsDefined, regsDead, regsKilled;
89 RegMaskVector regMasks;
90 RegSet regsLiveInButUnused;
95 void addRegWithSubRegs(RegVector &RV,
unsigned Reg) {
99 RV.push_back(*SubRegs);
124 RegSet vregsRequired;
127 BlockSet Preds, Succs;
129 BBInfo() : reachable(
false) {}
133 bool addPassed(
unsigned Reg) {
136 if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
138 return vregsPassed.insert(Reg).second;
142 bool addPassed(
const RegSet &RS) {
143 bool changed =
false;
144 for (RegSet::const_iterator
I = RS.begin(),
E = RS.end();
I !=
E; ++
I)
152 bool addRequired(
unsigned Reg) {
155 if (regsLiveOut.count(Reg))
157 return vregsRequired.insert(Reg).second;
161 bool addRequired(
const RegSet &RS) {
162 bool changed =
false;
163 for (RegSet::const_iterator
I = RS.begin(),
E = RS.end();
I !=
E; ++
I)
170 bool addRequired(
const RegMap &
RM) {
171 bool changed =
false;
172 for (RegMap::const_iterator
I = RM.begin(),
E = RM.end();
I !=
E; ++
I)
173 if (addRequired(
I->first))
180 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
187 bool isReserved(
unsigned Reg) {
188 return Reg < regsReserved.size() && regsReserved.test(Reg);
191 bool isAllocatable(
unsigned Reg) {
192 return Reg < TRI->getNumRegs() &&
MRI->isAllocatable(Reg);
201 void visitMachineFunctionBefore();
205 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
209 void visitMachineFunctionAfter();
214 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum);
217 void report_context(
const LiveRange &LR,
unsigned VRegUnit,
220 void report_context(
const VNInfo &VNI)
const;
221 void report_context(
SlotIndex Pos)
const;
222 void report_context_liverange(
const LiveRange &LR)
const;
223 void report_context_lanemask(
LaneBitmask LaneMask)
const;
224 void report_context_vreg(
unsigned VReg)
const;
225 void report_context_vreg_regunit(
unsigned VRegOrRegUnit)
const;
238 void calcRegsPassed();
241 void calcRegsRequired();
242 void verifyLiveVariables();
243 void verifyLiveIntervals();
247 void verifyLiveRangeSegment(
const LiveRange&,
250 void verifyLiveRange(
const LiveRange&,
unsigned,
253 void verifyStackFrame();
255 void verifySlotIndexes()
const;
261 const std::string Banner;
263 MachineVerifierPass(
const std::string &banner =
nullptr)
274 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).
verify(MF);
285 "Verify generated machine code",
false,
false)
288 return new MachineVerifierPass(Banner);
294 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
295 if (AbortOnErrors && FoundErrors)
297 return FoundErrors == 0;
300 void MachineVerifier::verifySlotIndexes()
const {
301 if (Indexes ==
nullptr)
307 E = Indexes->MBBIndexEnd();
I !=
E; ++
I) {
319 MRI->getNumVirtRegs())
320 report(
"Function has NoVRegs property but there are VReg operands", &MF);
352 verifyProperties(MF);
354 visitMachineFunctionBefore();
357 visitMachineBasicBlockBefore(&*MFI);
361 bool InBundle =
false;
364 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
365 if (MBBI->getParent() != &*MFI) {
366 report(
"Bad instruction parent pointer", &*MFI);
367 errs() <<
"Instruction: " << *MBBI;
372 if (InBundle && !MBBI->isBundledWithPred())
373 report(
"Missing BundledPred flag, "
374 "BundledSucc was set on predecessor",
376 if (!InBundle && MBBI->isBundledWithPred())
377 report(
"BundledPred flag is set, "
378 "but BundledSucc not set on predecessor",
382 if (!MBBI->isInsideBundle()) {
384 visitMachineBundleAfter(CurBundle);
386 visitMachineBundleBefore(CurBundle);
387 }
else if (!CurBundle)
388 report(
"No bundle header", &*MBBI);
389 visitMachineInstrBefore(&*MBBI);
390 for (
unsigned I = 0,
E = MBBI->getNumOperands();
I !=
E; ++
I) {
396 report(
"Instruction has operand with wrong parent set", &MI);
399 visitMachineOperand(&Op,
I);
402 visitMachineInstrAfter(&*MBBI);
405 InBundle = MBBI->isBundledWithSucc();
408 visitMachineBundleAfter(CurBundle);
410 report(
"BundledSucc flag set on last instruction in block", &MFI->back());
411 visitMachineBasicBlockAfter(&*MFI);
413 visitMachineFunctionAfter();
421 regsLiveInButUnused.clear();
427 void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
430 if (!foundErrors++) {
432 errs() <<
"# " << Banner <<
'\n';
433 if (LiveInts !=
nullptr)
434 LiveInts->print(
errs());
438 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
439 <<
"- function: " << MF->
getName() <<
"\n";
447 <<
" (" << (
const void*)MBB <<
')';
449 errs() <<
" [" << Indexes->getMBBStartIdx(MBB)
450 <<
';' << Indexes->getMBBEndIdx(MBB) <<
')';
454 void MachineVerifier::report(
const char *msg,
const MachineInstr *MI) {
457 errs() <<
"- instruction: ";
458 if (Indexes && Indexes->hasIndex(*MI))
459 errs() << Indexes->getInstructionIndex(*MI) <<
'\t';
464 void MachineVerifier::report(
const char *msg,
468 errs() <<
"- operand " << MONum <<
": ";
473 void MachineVerifier::report_context(
SlotIndex Pos)
const {
474 errs() <<
"- at: " << Pos <<
'\n';
477 void MachineVerifier::report_context(
const LiveInterval &LI)
const {
478 errs() <<
"- interval: " << LI <<
'\n';
481 void MachineVerifier::report_context(
const LiveRange &LR,
unsigned VRegUnit,
483 report_context_liverange(LR);
484 report_context_vreg_regunit(VRegUnit);
486 report_context_lanemask(LaneMask);
490 errs() <<
"- segment: " << S <<
'\n';
493 void MachineVerifier::report_context(
const VNInfo &VNI)
const {
494 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
497 void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
498 errs() <<
"- liverange: " << LR <<
'\n';
501 void MachineVerifier::report_context_vreg(
unsigned VReg)
const {
502 errs() <<
"- v. register: " <<
PrintReg(VReg, TRI) <<
'\n';
505 void MachineVerifier::report_context_vreg_regunit(
unsigned VRegOrUnit)
const {
507 report_context_vreg(VRegOrUnit);
513 void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
518 BBInfo &MInfo = MBBInfoMap[
MBB];
519 if (!MInfo.reachable) {
520 MInfo.reachable =
true;
522 SuE = MBB->
succ_end(); SuI != SuE; ++SuI)
527 void MachineVerifier::visitMachineFunctionBefore() {
529 regsReserved =
MRI->getReservedRegs();
531 markReachable(&MF->
front());
534 FunctionBlocks.clear();
535 for (
const auto &MBB : *MF) {
536 FunctionBlocks.insert(&MBB);
537 BBInfo &MInfo = MBBInfoMap[&
MBB];
540 if (MInfo.Preds.size() != MBB.
pred_size())
541 report(
"MBB has duplicate entries in its predecessor list.", &MBB);
544 if (MInfo.Succs.size() != MBB.
succ_size())
545 report(
"MBB has duplicate entries in its successor list.", &MBB);
549 MRI->verifyUseLists();
566 FirstTerminator =
nullptr;
568 if (!MF->getProperties().hasProperty(
572 for (
const auto &LI : MBB->
liveins()) {
573 if (isAllocatable(LI.PhysReg) && !MBB->
isEHPad() &&
575 report(
"MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
586 if (!FunctionBlocks.count(*
I))
587 report(
"MBB has successor that isn't part of the function.", MBB);
588 if (!MBBInfoMap[*
I].Preds.count(MBB)) {
589 report(
"Inconsistent CFG", MBB);
590 errs() <<
"MBB is not in the predecessor list of the successor BB#"
591 << (*I)->getNumber() <<
".\n";
598 if (!FunctionBlocks.count(*
I))
599 report(
"MBB has predecessor that isn't part of the function.", MBB);
600 if (!MBBInfoMap[*
I].Succs.count(MBB)) {
601 report(
"Inconsistent CFG", MBB);
602 errs() <<
"MBB is not in the successor list of the predecessor BB#"
603 << (*I)->getNumber() <<
".\n";
609 const Function *Fn = MF->getFunction();
610 if (LandingPadSuccs.
size() > 1 &&
615 report(
"MBB has more than one landing pad successor", MBB);
628 if (MBBI == MF->end()) {
637 report(
"MBB exits via unconditional fall-through but doesn't have "
638 "exactly one CFG successor!", MBB);
640 report(
"MBB exits via unconditional fall-through but its successor "
641 "differs from its CFG successor!", MBB);
645 report(
"MBB exits via unconditional fall-through but ends with a "
646 "barrier instruction!", MBB);
649 report(
"MBB exits via unconditional fall-through but has a condition!",
652 }
else if (TBB && !FBB && Cond.
empty()) {
659 report(
"MBB exits via unconditional branch but doesn't have "
660 "exactly one CFG successor!", MBB);
662 report(
"MBB exits via unconditional branch but the CFG "
663 "successor doesn't match the actual successor!", MBB);
666 report(
"MBB exits via unconditional branch but doesn't contain "
667 "any instructions!", MBB);
669 report(
"MBB exits via unconditional branch but doesn't end with a "
670 "barrier instruction!", MBB);
672 report(
"MBB exits via unconditional branch but the branch isn't a "
673 "terminator instruction!", MBB);
675 }
else if (TBB && !FBB && !Cond.
empty()) {
679 if (MBBI == MF->end()) {
680 report(
"MBB conditionally falls through out of function!", MBB);
684 report(
"MBB exits via conditional branch/fall-through but only has "
685 "one CFG successor!", MBB);
687 report(
"MBB exits via conditional branch/fall-through but the CFG "
688 "successor don't match the actual successor!", MBB);
690 report(
"MBB exits via conditional branch/fall-through but doesn't have "
691 "exactly two CFG successors!", MBB);
693 report(
"MBB exits via conditional branch/fall-through but the CFG "
694 "successors don't match the actual successors!", MBB);
697 report(
"MBB exits via conditional branch/fall-through but doesn't "
698 "contain any instructions!", MBB);
700 report(
"MBB exits via conditional branch/fall-through but ends with a "
701 "barrier instruction!", MBB);
703 report(
"MBB exits via conditional branch/fall-through but the branch "
704 "isn't a terminator instruction!", MBB);
706 }
else if (TBB && FBB) {
712 report(
"MBB exits via conditional branch/branch through but only has "
713 "one CFG successor!", MBB);
715 report(
"MBB exits via conditional branch/branch through but the CFG "
716 "successor don't match the actual successor!", MBB);
718 report(
"MBB exits via conditional branch/branch but doesn't have "
719 "exactly two CFG successors!", MBB);
721 report(
"MBB exits via conditional branch/branch but the CFG "
722 "successors don't match the actual successors!", MBB);
725 report(
"MBB exits via conditional branch/branch but doesn't "
726 "contain any instructions!", MBB);
728 report(
"MBB exits via conditional branch/branch but doesn't end with a "
729 "barrier instruction!", MBB);
731 report(
"MBB exits via conditional branch/branch but the branch "
732 "isn't a terminator instruction!", MBB);
735 report(
"MBB exits via conditinal branch/branch but there's no "
739 report(
"AnalyzeBranch returned invalid data!", MBB);
744 if (
MRI->tracksLiveness()) {
745 for (
const auto &LI : MBB->
liveins()) {
747 report(
"MBB live-in list contains non-physical register", MBB);
752 regsLive.insert(*SubRegs);
755 regsLiveInButUnused = regsLive;
762 regsLive.insert(*SubRegs);
769 lastIndex = Indexes->getMBBStartIdx(MBB);
774 void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *MI) {
775 if (Indexes && Indexes->hasIndex(*MI)) {
776 SlotIndex idx = Indexes->getInstructionIndex(*MI);
777 if (!(idx > lastIndex)) {
778 report(
"Instruction index out of order", MI);
779 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
788 if (!FirstTerminator)
789 FirstTerminator =
MI;
790 }
else if (FirstTerminator) {
791 report(
"Non-terminator instruction after the first terminator", MI);
792 errs() <<
"First terminator was:\t" << *FirstTerminator;
798 void MachineVerifier::verifyInlineAsm(
const MachineInstr *MI) {
801 report(
"Too few operands on inline asm", MI);
805 report(
"Asm string must be an external symbol", MI);
807 report(
"Asm flags must be an immediate", MI);
812 report(
"Unknown asm flags", &MI->
getOperand(1), 1);
818 for (
unsigned e = MI->
getNumOperands(); OpNo < e; OpNo += NumOps) {
827 report(
"Missing operands in last group", MI);
837 report(
"Expected implicit register after groups", &MO, OpNo);
841 void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *MI) {
844 report(
"Too few operands", MI);
849 if (MI->
isPHI() && MF->getProperties().hasProperty(
851 report(
"Found PHI instruction with NoPHIs property set", MI);
860 if ((*I)->isLoad() && !MI->
mayLoad())
861 report(
"Missing mayLoad flag", MI);
862 if ((*I)->isStore() && !MI->
mayStore())
863 report(
"Missing mayStore flag", MI);
869 bool mapped = !LiveInts->isNotInMIMap(*MI);
872 report(
"Debug instruction has a slot index", MI);
875 report(
"Instruction inside bundle has a slot index", MI);
878 report(
"Missing slot index", MI);
884 if (isFunctionSelected)
885 report(
"Unexpected generic instruction in a Selected function", MI);
894 Types.
resize(std::max(TypeIdx + 1, Types.
size()));
897 if (Types[TypeIdx].
isValid() && Types[TypeIdx] != OpTy)
898 report(
"type mismatch in generic instruction", MI);
899 Types[TypeIdx] = OpTy;
907 report(
"Generic instruction cannot have physical register", MI);
912 if (!
TII->verifyInstruction(*MI, ErrorInfo))
913 report(ErrorInfo.
data(),
MI);
917 MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
921 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
922 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
925 if (MONum < NumDefs) {
928 report(
"Explicit definition must be a register", MO, MONum);
930 report(
"Explicit definition marked as use", MO, MONum);
932 report(
"Explicit definition marked as implicit", MO, MONum);
940 report(
"Explicit operand marked as def", MO, MONum);
942 report(
"Explicit operand marked as implicit", MO, MONum);
948 report(
"Tied use must be a register", MO, MONum);
950 report(
"Operand should be tied", MO, MONum);
952 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
954 report(
"Explicit operand should not be tied", MO, MONum);
958 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
963 const unsigned Reg = MO->
getReg();
967 checkLiveness(MO, MONum);
973 if (!OtherMO.
isReg())
974 report(
"Must be tied to a register", MO, MONum);
976 report(
"Missing tie flags on tied operand", MO, MONum);
978 report(
"Inconsistent tie links", MO, MONum);
982 report(
"Explicit def tied to explicit use without tie constraint",
986 report(
"Explicit def should be tied to implicit use", MO, MONum);
996 report(
"Two-address instruction operands must be identical", MO, MONum);
1004 report(
"Illegal subregister index for physical register", MO, MONum);
1008 TII->getRegClass(MCID, MONum, TRI, *MF)) {
1009 if (!DRC->contains(Reg)) {
1010 report(
"Illegal physical register for instruction", MO, MONum);
1011 errs() << TRI->getName(Reg) <<
" is not a "
1012 << TRI->getRegClassName(DRC) <<
" register.\n";
1022 if (isFunctionSelected) {
1023 report(
"Generic virtual register invalid in a Selected function",
1029 LLT Ty =
MRI->getType(Reg);
1031 report(
"Generic virtual register must have a valid type", MO,
1039 if (!RegBank && isFunctionRegBankSelected) {
1040 report(
"Generic virtual register must have a bank in a "
1041 "RegBankSelected function",
1047 if (RegBank && Ty.
isValid() &&
1049 report(
"Register bank is too small for virtual register", MO,
1051 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
1057 report(
"Generic virtual register does not subregister index", MO,
1066 TII->getRegClass(MCID, MONum, TRI, *MF)) {
1067 report(
"Virtual register does not match instruction constraint", MO,
1069 errs() <<
"Expect register class "
1070 << TRI->getRegClassName(
1071 TII->getRegClass(MCID, MONum, TRI, *MF))
1072 <<
" but got nothing\n";
1080 TRI->getSubClassWithSubReg(RC, SubIdx);
1082 report(
"Invalid subregister index for virtual register", MO, MONum);
1083 errs() <<
"Register class " << TRI->getRegClassName(RC)
1084 <<
" does not support subreg index " << SubIdx <<
"\n";
1088 report(
"Invalid register class for subregister index", MO, MONum);
1089 errs() <<
"Register class " << TRI->getRegClassName(RC)
1090 <<
" does not fully support subreg index " << SubIdx <<
"\n";
1095 TII->getRegClass(MCID, MONum, TRI, *MF)) {
1098 TRI->getLargestLegalSuperClass(RC, *MF);
1100 report(
"No largest legal super class exists.", MO, MONum);
1103 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
1105 report(
"No matching super-reg register class.", MO, MONum);
1110 report(
"Illegal virtual register for instruction", MO, MONum);
1111 errs() <<
"Expected a " << TRI->getRegClassName(DRC)
1112 <<
" register, but got a " << TRI->getRegClassName(RC)
1127 report(
"PHI operand is not in the CFG", MO, MONum);
1131 if (LiveStks && LiveStks->hasInterval(MO->
getIndex()) &&
1132 LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1135 SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
1142 if (stores && loads) {
1145 if (PSV ==
nullptr)
continue;
1148 if (Value ==
nullptr)
continue;
1157 if (loads == stores)
1158 report(
"Missing fixed stack memoperand.", MI);
1161 report(
"Instruction loads from dead spill slot", MO, MONum);
1162 errs() <<
"Live stack: " << LI <<
'\n';
1165 report(
"Instruction stores to dead spill slot", MO, MONum);
1166 errs() <<
"Live stack: " << LI <<
'\n';
1176 void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
1183 report(
"No live segment at use", MO, MONum);
1184 report_context_liverange(LR);
1185 report_context_vreg_regunit(VRegOrUnit);
1186 report_context(UseIdx);
1189 report(
"Live range continues after kill flag", MO, MONum);
1190 report_context_liverange(LR);
1191 report_context_vreg_regunit(VRegOrUnit);
1193 report_context_lanemask(LaneMask);
1194 report_context(UseIdx);
1198 void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
1202 assert(VNI &&
"NULL valno is not allowed");
1203 if (VNI->def != DefIdx) {
1204 report(
"Inconsistent valno->def", MO, MONum);
1205 report_context_liverange(LR);
1206 report_context_vreg_regunit(VRegOrUnit);
1208 report_context_lanemask(LaneMask);
1209 report_context(*VNI);
1210 report_context(DefIdx);
1213 report(
"No live segment at def", MO, MONum);
1214 report_context_liverange(LR);
1215 report_context_vreg_regunit(VRegOrUnit);
1217 report_context_lanemask(LaneMask);
1218 report_context(DefIdx);
1226 bool otherDef =
false;
1232 unsigned Reg = MO.
getReg();
1234 if (*Units == VRegOrUnit) {
1243 report(
"Live range continues after dead def flag", MO, MONum);
1244 report_context_liverange(LR);
1245 report_context_vreg_regunit(VRegOrUnit);
1247 report_context_lanemask(LaneMask);
1253 void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
1255 const unsigned Reg = MO->
getReg();
1259 regsLiveInButUnused.erase(Reg);
1262 addRegWithSubRegs(regsKilled, Reg);
1269 report(
"Kill missing from LiveVariables", MO, MONum);
1273 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1274 SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
1278 if (
const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
1279 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
1284 if (LiveInts->hasInterval(Reg)) {
1287 checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
1292 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1293 :
MRI->getMaxLaneMaskForVReg(Reg);
1296 if ((MOMask & SR.LaneMask).none())
1298 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
1301 LiveInMask |= SR.LaneMask;
1304 if ((LiveInMask & MOMask).none()) {
1305 report(
"No live subrange at use", MO, MONum);
1307 report_context(UseIdx);
1311 report(
"Virtual register has no live interval", MO, MONum);
1317 if (!regsLive.count(Reg)) {
1320 bool Bad = !isReserved(Reg);
1325 if (regsLive.count(*SubRegs)) {
1339 if (!MOP.isImplicit())
1343 if (*SubRegs == Reg) {
1351 report(
"Using an undefined physical register", MO, MONum);
1352 }
else if (
MRI->def_empty(Reg)) {
1353 report(
"Reading virtual register without a def", MO, MONum);
1355 BBInfo &MInfo = MBBInfoMap[MI->
getParent()];
1359 if (MInfo.regsKilled.count(Reg))
1360 report(
"Using a killed virtual register", MO, MONum);
1361 else if (!MI->
isPHI())
1362 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1371 addRegWithSubRegs(regsDead, Reg);
1373 addRegWithSubRegs(regsDefined, Reg);
1377 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
1378 report(
"Multiple virtual register defs in SSA form", MO, MONum);
1381 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
1382 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
1386 if (LiveInts->hasInterval(Reg)) {
1388 checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
1393 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
1394 :
MRI->getMaxLaneMaskForVReg(Reg);
1396 if ((SR.LaneMask & MOMask).none())
1398 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, SR.LaneMask);
1402 report(
"Virtual register has no Live interval", MO, MONum);
1409 void MachineVerifier::visitMachineInstrAfter(
const MachineInstr *MI) {
1416 void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *MI) {
1417 BBInfo &MInfo = MBBInfoMap[MI->
getParent()];
1418 set_union(MInfo.regsKilled, regsKilled);
1419 set_subtract(regsLive, regsKilled); regsKilled.clear();
1421 while (!regMasks.empty()) {
1423 for (RegSet::iterator
I = regsLive.begin(),
E = regsLive.end();
I !=
E; ++
I)
1426 regsDead.push_back(*
I);
1429 set_union(regsLive, regsDefined); regsDefined.clear();
1434 MBBInfoMap[
MBB].regsLiveOut = regsLive;
1438 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1439 if (!(stop > lastIndex)) {
1440 report(
"Block ends before last instruction index", MBB);
1441 errs() <<
"Block ends at " << stop
1442 <<
" last instruction was at " << lastIndex <<
'\n';
1451 void MachineVerifier::calcRegsPassed() {
1455 for (
const auto &MBB : *MF) {
1456 BBInfo &MInfo = MBBInfoMap[&
MBB];
1457 if (!MInfo.reachable)
1460 SuE = MBB.
succ_end(); SuI != SuE; ++SuI) {
1461 BBInfo &SInfo = MBBInfoMap[*SuI];
1462 if (SInfo.addPassed(MInfo.regsLiveOut))
1469 while (!todo.
empty()) {
1472 BBInfo &MInfo = MBBInfoMap[
MBB];
1474 SuE = MBB->
succ_end(); SuI != SuE; ++SuI) {
1477 BBInfo &SInfo = MBBInfoMap[*SuI];
1478 if (SInfo.addPassed(MInfo.vregsPassed))
1487 void MachineVerifier::calcRegsRequired() {
1490 for (
const auto &MBB : *MF) {
1491 BBInfo &MInfo = MBBInfoMap[&
MBB];
1493 PrE = MBB.
pred_end(); PrI != PrE; ++PrI) {
1494 BBInfo &PInfo = MBBInfoMap[*PrI];
1495 if (PInfo.addRequired(MInfo.vregsLiveIn))
1502 while (!todo.
empty()) {
1505 BBInfo &MInfo = MBBInfoMap[
MBB];
1507 PrE = MBB->
pred_end(); PrI != PrE; ++PrI) {
1510 BBInfo &SInfo = MBBInfoMap[*PrI];
1511 if (SInfo.addRequired(MInfo.vregsRequired))
1521 for (
const auto &BBI : *MBB) {
1526 for (
unsigned i = 1, e = BBI.getNumOperands();
i != e;
i += 2) {
1527 unsigned Reg = BBI.getOperand(
i).getReg();
1532 BBInfo &PrInfo = MBBInfoMap[Pre];
1533 if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1534 report(
"PHI operand is not live-out from predecessor",
1535 &BBI.getOperand(
i),
i);
1540 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1541 if (!seen.
count(*PrI)) {
1542 report(
"Missing PHI operand", &BBI);
1543 errs() <<
"BB#" << (*PrI)->getNumber()
1544 <<
" is a predecessor according to the CFG.\n";
1550 void MachineVerifier::visitMachineFunctionAfter() {
1553 for (
const auto &MBB : *MF) {
1554 BBInfo &MInfo = MBBInfoMap[&
MBB];
1557 if (!MInfo.reachable)
1567 for (
const auto &MBB : *MF) {
1568 BBInfo &MInfo = MBBInfoMap[&
MBB];
1569 for (RegSet::iterator
1570 I = MInfo.vregsRequired.begin(),
E = MInfo.vregsRequired.end();
I !=
E;
1572 if (MInfo.regsKilled.count(*
I)) {
1573 report(
"Virtual register killed in block, but needed live out.", &MBB);
1575 <<
" is used after the block.\n";
1580 BBInfo &MInfo = MBBInfoMap[&MF->front()];
1581 for (RegSet::iterator
1582 I = MInfo.vregsRequired.begin(),
E = MInfo.vregsRequired.end();
I !=
E;
1584 report(
"Virtual register defs don't dominate all uses.", MF);
1585 report_context_vreg(*
I);
1590 verifyLiveVariables();
1592 verifyLiveIntervals();
1595 void MachineVerifier::verifyLiveVariables() {
1596 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
1597 for (
unsigned i = 0, e =
MRI->getNumVirtRegs();
i != e; ++
i) {
1600 for (
const auto &MBB : *MF) {
1601 BBInfo &MInfo = MBBInfoMap[&
MBB];
1604 if (MInfo.vregsRequired.count(Reg)) {
1606 report(
"LiveVariables: Block missing from AliveBlocks", &MBB);
1608 <<
" must be live through the block.\n";
1612 report(
"LiveVariables: Block should not be in AliveBlocks", &MBB);
1614 <<
" is not needed live through the block.\n";
1621 void MachineVerifier::verifyLiveIntervals() {
1622 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
1623 for (
unsigned i = 0, e =
MRI->getNumVirtRegs();
i != e; ++
i) {
1627 if (
MRI->reg_nodbg_empty(Reg))
1630 if (!LiveInts->hasInterval(Reg)) {
1631 report(
"Missing live interval for virtual register", MF);
1632 errs() <<
PrintReg(Reg, TRI) <<
" still has defs or uses\n";
1637 assert(Reg == LI.
reg &&
"Invalid reg to interval mapping");
1638 verifyLiveInterval(LI);
1642 for (
unsigned i = 0, e = TRI->getNumRegUnits();
i != e; ++
i)
1643 if (
const LiveRange *LR = LiveInts->getCachedRegUnit(
i))
1644 verifyLiveRange(*LR,
i);
1647 void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
1648 const VNInfo *VNI,
unsigned Reg,
1656 report(
"Value not live at VNInfo def and not marked unused", MF);
1657 report_context(LR, Reg, LaneMask);
1658 report_context(*VNI);
1662 if (DefVNI != VNI) {
1663 report(
"Live segment at def has different VNInfo", MF);
1664 report_context(LR, Reg, LaneMask);
1665 report_context(*VNI);
1671 report(
"Invalid VNInfo definition index", MF);
1672 report_context(LR, Reg, LaneMask);
1673 report_context(*VNI);
1678 if (VNI->
def != LiveInts->getMBBStartIdx(MBB)) {
1679 report(
"PHIDef VNInfo is not defined at MBB start", MBB);
1680 report_context(LR, Reg, LaneMask);
1681 report_context(*VNI);
1689 report(
"No instruction at VNInfo def index", MBB);
1690 report_context(LR, Reg, LaneMask);
1691 report_context(*VNI);
1696 bool hasDef =
false;
1697 bool isEarlyClobber =
false;
1699 if (!MOI->isReg() || !MOI->isDef())
1702 if (MOI->getReg() !=
Reg)
1706 !TRI->hasRegUnit(MOI->getReg(),
Reg))
1709 if (LaneMask.
any() &&
1710 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
1713 if (MOI->isEarlyClobber())
1714 isEarlyClobber =
true;
1718 report(
"Defining instruction does not modify register", MI);
1719 report_context(LR, Reg, LaneMask);
1720 report_context(*VNI);
1725 if (isEarlyClobber) {
1727 report(
"Early clobber def must be at an early-clobber slot", MBB);
1728 report_context(LR, Reg, LaneMask);
1729 report_context(*VNI);
1732 report(
"Non-PHI, non-early clobber def must be at a register slot", MBB);
1733 report_context(LR, Reg, LaneMask);
1734 report_context(*VNI);
1739 void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
1745 assert(VNI &&
"Live segment has no valno");
1748 report(
"Foreign valno in live segment", MF);
1749 report_context(LR, Reg, LaneMask);
1751 report_context(*VNI);
1755 report(
"Live segment valno is marked unused", MF);
1756 report_context(LR, Reg, LaneMask);
1762 report(
"Bad start of live segment, no basic block", MF);
1763 report_context(LR, Reg, LaneMask);
1767 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
1769 report(
"Live segment must begin at MBB entry or valno def", MBB);
1770 report_context(LR, Reg, LaneMask);
1777 report(
"Bad end of live segment, no basic block", MF);
1778 report_context(LR, Reg, LaneMask);
1784 if (S.
end == LiveInts->getMBBEndIdx(EndMBB))
1796 report(
"Live segment doesn't end at a valid instruction", EndMBB);
1797 report_context(LR, Reg, LaneMask);
1804 report(
"Live segment ends at B slot of an instruction", EndMBB);
1805 report_context(LR, Reg, LaneMask);
1813 report(
"Live segment ending at dead slot spans instructions", EndMBB);
1814 report_context(LR, Reg, LaneMask);
1822 if (I+1 == LR.
end() || (I+1)->start != S.
end) {
1823 report(
"Live segment ending at early clobber slot must be "
1824 "redefined by an EC def in the same instruction", EndMBB);
1825 report_context(LR, Reg, LaneMask);
1835 bool hasRead =
false;
1836 bool hasSubRegDef =
false;
1837 bool hasDeadDef =
false;
1839 if (!MOI->isReg() || MOI->getReg() !=
Reg)
1841 unsigned Sub = MOI->getSubReg();
1842 LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
1846 hasSubRegDef =
true;
1855 if (LaneMask.
any() && (LaneMask & SLM).none())
1857 if (MOI->readsReg())
1864 if (LaneMask.
none() && !hasDeadDef) {
1865 report(
"Instruction ending live segment on dead slot has no dead flag",
1867 report_context(LR, Reg, LaneMask);
1874 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
1876 report(
"Instruction ending live segment doesn't read the register",
1878 report_context(LR, Reg, LaneMask);
1896 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
1900 if (&*MFI == EndMBB)
1908 VNI->
def == LiveInts->getMBBStartIdx(&*MFI);
1912 PE = MFI->pred_end(); PI != PE; ++PI) {
1913 SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
1918 if (!PVNI && LaneMask.
none()) {
1919 report(
"Register not marked live out of predecessor", *PI);
1920 report_context(LR, Reg, LaneMask);
1921 report_context(*VNI);
1922 errs() <<
" live into BB#" << MFI->getNumber()
1923 <<
'@' << LiveInts->getMBBStartIdx(&*MFI) <<
", not live before "
1929 if (!IsPHI && PVNI != VNI) {
1930 report(
"Different value live out of predecessor", *PI);
1931 report_context(LR, Reg, LaneMask);
1932 errs() <<
"Valno #" << PVNI->
id <<
" live out of BB#"
1933 << (*PI)->getNumber() <<
'@' << PEnd <<
"\nValno #" << VNI->
id
1934 <<
" live into BB#" << MFI->getNumber() <<
'@'
1935 << LiveInts->getMBBStartIdx(&*MFI) <<
'\n';
1938 if (&*MFI == EndMBB)
1944 void MachineVerifier::verifyLiveRange(
const LiveRange &LR,
unsigned Reg,
1947 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
1950 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
1953 void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
1954 unsigned Reg = LI.
reg;
1956 verifyLiveRange(LI, Reg);
1961 if ((Mask & SR.LaneMask).any()) {
1962 report(
"Lane masks of sub ranges overlap in live interval", MF);
1965 if ((SR.LaneMask & ~MaxMask).any()) {
1966 report(
"Subrange lanemask is invalid", MF);
1970 report(
"Subrange must not be empty", MF);
1971 report_context(SR, LI.
reg, SR.LaneMask);
1973 Mask |= SR.LaneMask;
1974 verifyLiveRange(SR, LI.
reg, SR.LaneMask);
1976 report(
"A Subrange is not covered by the main range", MF);
1983 unsigned NumComp = ConEQ.Classify(LI);
1985 report(
"Multiple connected components in live interval", MF);
1987 for (
unsigned comp = 0; comp != NumComp; ++comp) {
1988 errs() << comp <<
": valnos";
1991 if (comp == ConEQ.getEqClass(*I))
1992 errs() <<
' ' << (*I)->id;
2003 struct StackStateOfBB {
2004 StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(
false),
2005 ExitIsSetup(
false) { }
2006 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
2007 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
2008 ExitIsSetup(ExitSetup) { }
2020 void MachineVerifier::verifyStackFrame() {
2021 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
2022 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
2025 SPState.
resize(MF->getNumBlockIDs());
2032 DFI != DFE; ++DFI) {
2035 StackStateOfBB BBState;
2037 if (DFI.getPathLength() >= 2) {
2040 "DFS stack predecessor is already visited.\n");
2041 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
2042 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
2043 BBState.ExitValue = BBState.EntryValue;
2044 BBState.ExitIsSetup = BBState.EntryIsSetup;
2048 for (
const auto &I : *MBB) {
2049 if (I.getOpcode() == FrameSetupOpcode) {
2051 int Size = I.getOperand(0).getImm();
2053 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
2055 if (BBState.ExitIsSetup)
2056 report(
"FrameSetup is after another FrameSetup", &I);
2057 BBState.ExitValue -= Size;
2058 BBState.ExitIsSetup =
true;
2061 if (I.getOpcode() == FrameDestroyOpcode) {
2063 int Size = I.getOperand(0).getImm();
2065 "Value should be non-negative in FrameSetup and FrameDestroy.\n");
2067 if (!BBState.ExitIsSetup)
2068 report(
"FrameDestroy is not after a FrameSetup", &I);
2069 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
2071 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
2072 report(
"FrameDestroy <n> is after FrameSetup <m>", &I);
2073 errs() <<
"FrameDestroy <" << Size <<
"> is after FrameSetup <"
2074 << AbsSPAdj <<
">.\n";
2076 BBState.ExitValue += Size;
2077 BBState.ExitIsSetup =
false;
2080 SPState[MBB->getNumber()] = BBState;
2085 E = MBB->pred_end(); I !=
E; ++
I) {
2086 if (Reachable.
count(*I) &&
2087 (SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
2088 SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
2089 report(
"The exit stack state of a predecessor is inconsistent.", MBB);
2090 errs() <<
"Predecessor BB#" << (*I)->getNumber() <<
" has exit state ("
2091 << SPState[(*I)->getNumber()].ExitValue <<
", "
2092 << SPState[(*I)->getNumber()].ExitIsSetup
2093 <<
"), while BB#" << MBB->getNumber() <<
" has entry state ("
2094 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
2101 E = MBB->succ_end(); I !=
E; ++
I) {
2102 if (Reachable.
count(*I) &&
2103 (SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
2104 SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
2105 report(
"The entry stack state of a successor is inconsistent.", MBB);
2106 errs() <<
"Successor BB#" << (*I)->getNumber() <<
" has entry state ("
2107 << SPState[(*I)->getNumber()].EntryValue <<
", "
2108 << SPState[(*I)->getNumber()].EntryIsSetup
2109 <<
"), while BB#" << MBB->getNumber() <<
" has exit state ("
2110 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
2115 if (!MBB->empty() && MBB->back().isReturn()) {
2116 if (BBState.ExitIsSetup)
2117 report(
"A return block ends with a FrameSetup.", MBB);
2118 if (BBState.ExitValue)
2119 report(
"A return block ends with a nonzero stack adjustment.", MBB);
Pass interface - Implemented by all 'passes'.
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
unsigned succ_size() const
void print(raw_ostream &OS, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isEHPad() const
Returns true if the block is a landing pad.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
iterator_range< livein_iterator > liveins() const
bool isGenericType() const
SlotIndex def
The index of the defining instruction.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
bool hasProperty(Property P) const
MachineBasicBlock * getMBB() const
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Implements a dense probed hash-table based set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
static LaneBitmask getAll()
DWARF-like instruction based exceptions.
LiveInterval - This class represents the liveness of a register, or stack slot.
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static bool matchPair(MachineBasicBlock::const_succ_iterator i, const MachineBasicBlock *a, const MachineBasicBlock *b)
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
bool isKill() const
Return true if the live-in value is killed by this instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
A live range for subregisters.
MachineBasicBlock reference.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
iterator_range< mmo_iterator > memoperands()
VNInfo - Value Number Information.
iterator_range< mop_iterator > operands()
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
This class represents the liveness of a register, stack slot, etc.
void initializeMachineVerifierPassPass(PassRegistry &)
Mask of preserved registers.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
safe Safe Stack instrumentation pass
A description of a memory reference used in the backend.
void clear()
clear - Clear all bits.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const HexagonInstrInfo * TII
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Result of a LiveRange query.
const MachineFunctionProperties & getProperties() const
Get the function properties.
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
SparseBitVector AliveBlocks
AliveBlocks - Set of blocks in which this value is alive completely through.
constexpr bool any() const
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isUnused() const
Returns true if this value is unused.
const MachineBasicBlock & front() const
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Function Alias Analysis false
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
VNInfoList::const_iterator const_vni_iterator
INITIALIZE_PASS(MachineVerifierPass,"machineverifier","Verify generated machine code", false, false) FunctionPass *llvm
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
mmo_iterator memoperands_end() const
bool isDeadDef() const
Return true if this instruction has a dead def.
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
bool isValid() const
Returns true if this is a valid index.
unsigned const MachineRegisterInfo * MRI
LLVM Basic Block Representation.
constexpr bool none() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
bool isOptionalDef() const
Set if this operand is a optional def.
const MachineOperand & getOperand(unsigned i) const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
unsigned getGenericTypeIndex() const
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
FunctionPass class - This class is used to implement most global optimizations.
ExceptionHandling getExceptionHandlingType() const
self_iterator getIterator()
LLVM_NODISCARD bool empty() const
succ_iterator succ_begin()
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
MCSubRegIterator enumerates all sub-registers of Reg.
bool liveAt(SlotIndex index) const
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
unsigned getOpcode() const
Return the opcode number for this descriptor.
const char * getName() const
Get a user friendly name of this register bank.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
unsigned id
The ID number of this value.
Iterator for intrusive lists based on ilist_node.
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
MachineOperand class - Representation of each machine instruction operand.
static LaneBitmask getNone()
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
This class implements the register bank concept.
int getFrameIndex() const
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or "(null)".
Special value supplied for machine level alias analysis.
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
void setPreservesAll()
Set by analyses that do not transform their input at all.
Base class for user error types.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TerminatorInst * getTerminator()
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
Abstract Stack Frame Index.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block) ...
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
static LLVM_ATTRIBUTE_UNUSED Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Primary interface to the complete machine description for the target machine.
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index...
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
SlotIndex - An opaque wrapper around machine indexes.
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range...
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
unsigned pred_size() const
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.