LLVM  4.0.0
WebAssemblyPrepareForLiveIntervals.cpp
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1 //===- WebAssemblyPrepareForLiveIntervals.cpp - Prepare for LiveIntervals -===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief Fix up code to meet LiveInterval's requirements.
12 ///
13 /// Some CodeGen passes don't preserve LiveInterval's requirements, because
14 /// they run after register allocation and it isn't important. However,
15 /// WebAssembly runs LiveIntervals in a late pass. This pass transforms code
16 /// to meet LiveIntervals' requirements; primarily, it ensures that all
17 /// virtual register uses have definitions (IMPLICIT_DEF definitions if
18 /// nothing else).
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #include "WebAssembly.h"
25 #include "WebAssemblySubtarget.h"
26 #include "WebAssemblyUtilities.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/Support/Debug.h"
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "wasm-prepare-for-live-intervals"
36 
37 namespace {
38 class WebAssemblyPrepareForLiveIntervals final : public MachineFunctionPass {
39 public:
40  static char ID; // Pass identification, replacement for typeid
41  WebAssemblyPrepareForLiveIntervals() : MachineFunctionPass(ID) {}
42 
43 private:
44  StringRef getPassName() const override {
45  return "WebAssembly Prepare For LiveIntervals";
46  }
47 
48  void getAnalysisUsage(AnalysisUsage &AU) const override {
49  AU.setPreservesCFG();
51  }
52 
53  bool runOnMachineFunction(MachineFunction &MF) override;
54 };
55 } // end anonymous namespace
56 
59  return new WebAssemblyPrepareForLiveIntervals();
60 }
61 
62 // Test whether the given register has an ARGUMENT def.
63 static bool HasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) {
64  for (const auto &Def : MRI.def_instructions(Reg))
66  return true;
67  return false;
68 }
69 
70 bool WebAssemblyPrepareForLiveIntervals::runOnMachineFunction(MachineFunction &MF) {
71  DEBUG({
72  dbgs() << "********** Prepare For LiveIntervals **********\n"
73  << "********** Function: " << MF.getName() << '\n';
74  });
75 
76  bool Changed = false;
78  const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
79  MachineBasicBlock &Entry = *MF.begin();
80 
81  assert(!mustPreserveAnalysisID(LiveIntervalsID) &&
82  "LiveIntervals shouldn't be active yet!");
83 
84  // We don't preserve SSA form.
85  MRI.leaveSSA();
86 
87  // BranchFolding and perhaps other passes don't preserve IMPLICIT_DEF
88  // instructions. LiveIntervals requires that all paths to virtual register
89  // uses provide a definition. Insert IMPLICIT_DEFs in the entry block to
90  // conservatively satisfy this.
91  //
92  // TODO: This is fairly heavy-handed; find a better approach.
93  //
94  for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) {
96 
97  // Skip unused registers.
98  if (MRI.use_nodbg_empty(Reg))
99  continue;
100 
101  // Skip registers that have an ARGUMENT definition.
102  if (HasArgumentDef(Reg, MRI))
103  continue;
104 
105  BuildMI(Entry, Entry.begin(), DebugLoc(),
106  TII.get(WebAssembly::IMPLICIT_DEF), Reg);
107  Changed = true;
108  }
109 
110  // Move ARGUMENT_* instructions to the top of the entry block, so that their
111  // liveness reflects the fact that these really are live-in values.
112  for (auto MII = Entry.begin(), MIE = Entry.end(); MII != MIE; ) {
113  MachineInstr &MI = *MII++;
114  if (WebAssembly::isArgument(MI)) {
115  MI.removeFromParent();
116  Entry.insert(Entry.begin(), &MI);
117  }
118  }
119 
120  // Ok, we're now ready to run LiveIntervalAnalysis again.
122 
123  return Changed;
124 }
size_t i
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static bool HasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI)
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
A debug info location.
Definition: DebugLoc.h:34
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
const MachineFunctionProperties & getProperties() const
Get the function properties.
Reg
All possible values of the reg field in the ModR/M byte.
FunctionPass * createWebAssemblyPrepareForLiveIntervals()
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
This file contains the declaration of the WebAssembly-specific utility functions. ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This file provides WebAssembly-specific target descriptions.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
This file declares the WebAssembly-specific subclass of TargetSubtarget.
bool isArgument(const MachineInstr &MI)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This file declares WebAssembly-specific per-machine-function information.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
StringRef getName() const
getName - Return the name of the corresponding LLVM function.