20 #define DEBUG_TYPE "ppc-disassembler"
43 return new PPCDisassembler(STI, Ctx,
false);
49 return new PPCDisassembler(STI, Ctx,
true);
66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
71 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
72 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
73 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
74 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
75 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
76 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
77 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
78 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
81 static const unsigned FRegs[] = {
82 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
83 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
84 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
85 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
86 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
87 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
88 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
89 PPC::F28, PPC::F29, PPC::F30, PPC::F31
93 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
94 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
95 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
96 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
97 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
98 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
99 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
100 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
104 PPC::V0, PPC::V1,
PPC::V2, PPC::V3,
105 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
106 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
107 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
108 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
109 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
110 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
111 PPC::V28, PPC::V29, PPC::V30, PPC::V31
115 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
116 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
117 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
118 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
119 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
120 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
121 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
122 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
124 PPC::V0, PPC::V1,
PPC::V2, PPC::V3,
125 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
126 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
127 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
128 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
129 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
130 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
131 PPC::V28, PPC::V29, PPC::V30, PPC::V31
135 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
136 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
137 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
138 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
139 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
140 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
141 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
142 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
144 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
145 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
146 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
147 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
148 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
149 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
150 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
151 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
155 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
156 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
157 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
158 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
159 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
160 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
161 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
162 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
164 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
165 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
166 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
167 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
168 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
169 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
170 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
171 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
175 PPC::R0, PPC::R1,
PPC::R2, PPC::R3,
177 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
178 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
182 PPC::R28, PPC::R29, PPC::R30, PPC::R31
186 PPC::ZERO, PPC::R1,
PPC::R2, PPC::R3,
188 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
189 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
190 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
191 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
192 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
193 PPC::R28, PPC::R29, PPC::R30, PPC::R31
197 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
198 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
199 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
200 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
201 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
202 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
203 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
204 PPC::X28, PPC::X29, PPC::X30, PPC::X31
208 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
209 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
210 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
211 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
212 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
213 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
214 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
215 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
218 template <std::
size_t N>
220 const unsigned (&
Regs)[
N]) {
221 assert(RegNo < N &&
"Invalid register number");
228 const void *Decoder) {
234 const void *Decoder) {
240 const void *Decoder) {
246 const void *Decoder) {
252 const void *Decoder) {
258 const void *Decoder) {
264 const void *Decoder) {
270 const void *Decoder) {
276 const void *Decoder) {
282 const void *Decoder) {
288 const void *Decoder) {
294 const void *Decoder) {
300 const void *Decoder) {
304 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
305 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
309 const void *Decoder) {
313 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
314 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
318 int64_t
Address,
const void *Decoder) {
319 assert(isUInt<N>(Imm) &&
"Invalid immediate");
326 int64_t
Address,
const void *Decoder) {
327 assert(isUInt<N>(Imm) &&
"Invalid immediate");
333 int64_t
Address,
const void *Decoder) {
337 uint64_t Base = Imm >> 16;
338 uint64_t Disp = Imm & 0xFFFF;
340 assert(Base < 32 &&
"Invalid base register");
368 int64_t
Address,
const void *Decoder) {
372 uint64_t Base = Imm >> 14;
373 uint64_t Disp = Imm & 0x3FFF;
375 assert(Base < 32 &&
"Invalid base register");
389 int64_t
Address,
const void *Decoder) {
393 uint64_t Base = Imm >> 12;
394 uint64_t Disp = Imm & 0xFFF;
396 assert(Base < 32 &&
"Invalid base register");
404 int64_t
Address,
const void *Decoder) {
408 assert(Zeros < 8 &&
"Invalid CR bit value");
414 #include "PPCGenDisassemblerTables.inc"
422 if (Bytes.
size() < 4) {
431 if (STI.getFeatureBits()[PPC::FeatureQPX]) {
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static const unsigned GPRegs[]
static const unsigned VSSRegs[]
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
Target & getThePPC32Target()
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createPPCDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static MCOperand createReg(unsigned Reg)
uint32_t read32be(const void *P)
static const unsigned VFRegs[]
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static MCDisassembler * createPPCLEDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Context object for machine code objects.
static const unsigned VSRegs[]
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
Target & getThePPC64Target()
static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static const unsigned GP0Regs[]
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
iterator insert(iterator I, const MCOperand &Op)
Instances of this class represent a single low-level machine instruction.
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static const unsigned G8Regs[]
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static const unsigned FRegs[]
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static const unsigned CRRegs[]
static const unsigned VSFRegs[]
unsigned getOpcode() const
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static const unsigned QFRegs[]
static const unsigned VRegs[]
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned(&Regs)[N])
void LLVMInitializePowerPCDisassembler()
uint32_t read32le(const void *P)
MCSubtargetInfo - Generic base class for all target subtargets.
static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const unsigned CRBITRegs[]
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
static MCOperand createImm(int64_t Val)