54 SIMCCodeEmitter(
const SIMCCodeEmitter &) =
delete;
55 SIMCCodeEmitter &operator=(
const SIMCCodeEmitter &) =
delete;
69 unsigned getSOPPBrEncoding(
const MCInst &
MI,
unsigned OpNo,
79 return new SIMCCodeEmitter(MCII, MRI, Ctx);
84 template <
typename IntTy>
86 if (Imm >= 0 && Imm <= 64)
89 if (Imm >= -16 && Imm <= -1)
160 if (Val == 0x3e22f983 &&
196 if (Val == 0x3fc45f306dc9c882 &&
238 verifyInstructionPredicates(MI,
241 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
243 unsigned bytes = Desc.
getSize();
245 for (
unsigned i = 0;
i < bytes;
i++) {
246 OS.
write((uint8_t) ((Encoding >> (8 *
i)) & 0xff));
261 if (getLitEncoding(Op, Desc.
OpInfo[
i], STI) != 255)
270 if (
const auto *
C = dyn_cast<MCConstantExpr>(Op.
getExpr()))
276 for (
unsigned j = 0; j < 4; j++) {
277 OS.
write((uint8_t) ((Imm >> (8 * j)) & 0xff));
285 unsigned SIMCCodeEmitter::getSOPPBrEncoding(
const MCInst &MI,
unsigned OpNo,
297 return getMachineOpValue(MI, MO, Fixups, STI);
300 uint64_t SIMCCodeEmitter::getMachineOpValue(
const MCInst &MI,
305 return MRI.getEncodingValue(MO.
getReg());
310 if (Expr && Expr->getSymbol().isExternal())
327 if (Enc != ~0U && (Enc != 255 || Desc.
getSize() == 4))
330 }
else if (MO.
isImm())
void push_back(const T &Elt)
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Represent a reference to a symbol from inside an expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI)
Instances of this class represent a single low-level machine instruction.
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI)
MCCodeEmitter - Generic instruction encoding interface.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static uint32_t getIntInlineImmEncoding(IntTy Imm)
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
raw_ostream & write(unsigned char C)
static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI)
A four-byte pc relative fixup.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
uint64_t DoubleToBits(double Double)
DoubleToBits - This function takes a double and returns the bit equivalent 64-bit integer...
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned getOpcode() const
Provides AMDGPU specific target descriptions.
unsigned getNumOperands() const
16-bit PC relative fixup for SOPP branch instructions.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCSubtargetInfo - Generic base class for all target subtargets.
CodeEmitter interface for R600 and SI codegen.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCOperandInfo * OpInfo
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
This class implements an extremely fast bulk output stream that can only output to a stream...
This holds information about one operand of a machine instruction, indicating the register class for ...
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const