LLVM  4.0.0
AArch64InstPrinter.h
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1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an AArch64 MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
15 #define LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
16 
18 #include "llvm/MC/MCInstPrinter.h"
19 
20 namespace llvm {
21 
23 public:
25  const MCRegisterInfo &MRI);
26 
27  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
28  const MCSubtargetInfo &STI) override;
29  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
30 
31  // Autogenerated by tblgen.
32  virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
33  raw_ostream &O);
34  virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
35  raw_ostream &O);
36  virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
37  unsigned PrintMethodIdx,
38  const MCSubtargetInfo &STI,
39  raw_ostream &O);
40  virtual StringRef getRegName(unsigned RegNo) const {
41  return getRegisterName(RegNo);
42  }
43  static const char *getRegisterName(unsigned RegNo,
44  unsigned AltIdx = AArch64::NoRegAltName);
45 
46 protected:
47  bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
48  raw_ostream &O);
49  // Operand printers
50  void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
51  raw_ostream &O);
52  void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
53  raw_ostream &O);
54  void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
55  raw_ostream &O);
56  void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
57  raw_ostream &O);
58  template <int Amount>
59  void printPostIncOperand(const MCInst *MI, unsigned OpNo,
60  const MCSubtargetInfo &STI, raw_ostream &O) {
61  printPostIncOperand(MI, OpNo, Amount, O);
62  }
63 
64  void printVRegOperand(const MCInst *MI, unsigned OpNo,
65  const MCSubtargetInfo &STI, raw_ostream &O);
66  void printSysCROperand(const MCInst *MI, unsigned OpNo,
67  const MCSubtargetInfo &STI, raw_ostream &O);
68  void printAddSubImm(const MCInst *MI, unsigned OpNum,
69  const MCSubtargetInfo &STI, raw_ostream &O);
70  void printLogicalImm32(const MCInst *MI, unsigned OpNum,
71  const MCSubtargetInfo &STI, raw_ostream &O);
72  void printLogicalImm64(const MCInst *MI, unsigned OpNum,
73  const MCSubtargetInfo &STI, raw_ostream &O);
74  void printShifter(const MCInst *MI, unsigned OpNum,
75  const MCSubtargetInfo &STI, raw_ostream &O);
76  void printShiftedRegister(const MCInst *MI, unsigned OpNum,
77  const MCSubtargetInfo &STI, raw_ostream &O);
78  void printExtendedRegister(const MCInst *MI, unsigned OpNum,
79  const MCSubtargetInfo &STI, raw_ostream &O);
80  void printArithExtend(const MCInst *MI, unsigned OpNum,
81  const MCSubtargetInfo &STI, raw_ostream &O);
82 
83  void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
84  char SrcRegKind, unsigned Width);
85  template <char SrcRegKind, unsigned Width>
86  void printMemExtend(const MCInst *MI, unsigned OpNum,
87  const MCSubtargetInfo &STI, raw_ostream &O) {
88  printMemExtend(MI, OpNum, O, SrcRegKind, Width);
89  }
90 
91  void printCondCode(const MCInst *MI, unsigned OpNum,
92  const MCSubtargetInfo &STI, raw_ostream &O);
93  void printInverseCondCode(const MCInst *MI, unsigned OpNum,
94  const MCSubtargetInfo &STI, raw_ostream &O);
95  void printAlignedLabel(const MCInst *MI, unsigned OpNum,
96  const MCSubtargetInfo &STI, raw_ostream &O);
97  void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
98  raw_ostream &O);
99  void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
100  raw_ostream &O);
101 
102  template <int Scale>
103  void printUImm12Offset(const MCInst *MI, unsigned OpNum,
104  const MCSubtargetInfo &STI, raw_ostream &O) {
105  printUImm12Offset(MI, OpNum, Scale, O);
106  }
107 
108  template <int BitWidth>
109  void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
110  const MCSubtargetInfo &STI, raw_ostream &O) {
111  printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
112  }
113 
114  void printAMNoIndex(const MCInst *MI, unsigned OpNum,
115  const MCSubtargetInfo &STI, raw_ostream &O);
116 
117  template <int Scale>
118  void printImmScale(const MCInst *MI, unsigned OpNum,
119  const MCSubtargetInfo &STI, raw_ostream &O);
120 
121  void printPrefetchOp(const MCInst *MI, unsigned OpNum,
122  const MCSubtargetInfo &STI, raw_ostream &O);
123 
124  void printPSBHintOp(const MCInst *MI, unsigned OpNum,
125  const MCSubtargetInfo &STI, raw_ostream &O);
126 
127  void printFPImmOperand(const MCInst *MI, unsigned OpNum,
128  const MCSubtargetInfo &STI, raw_ostream &O);
129 
130  void printVectorList(const MCInst *MI, unsigned OpNum,
131  const MCSubtargetInfo &STI, raw_ostream &O,
132  StringRef LayoutSuffix);
133 
134  /// Print a list of vector registers where the type suffix is implicit
135  /// (i.e. attached to the instruction rather than the registers).
136  void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
137  const MCSubtargetInfo &STI,
138  raw_ostream &O);
139 
140  template <unsigned NumLanes, char LaneKind>
141  void printTypedVectorList(const MCInst *MI, unsigned OpNum,
142  const MCSubtargetInfo &STI, raw_ostream &O);
143 
144  void printVectorIndex(const MCInst *MI, unsigned OpNum,
145  const MCSubtargetInfo &STI, raw_ostream &O);
146  void printAdrpLabel(const MCInst *MI, unsigned OpNum,
147  const MCSubtargetInfo &STI, raw_ostream &O);
148  void printBarrierOption(const MCInst *MI, unsigned OpNum,
149  const MCSubtargetInfo &STI, raw_ostream &O);
150  void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
151  const MCSubtargetInfo &STI, raw_ostream &O);
152  void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
153  const MCSubtargetInfo &STI, raw_ostream &O);
154  void printSystemPStateField(const MCInst *MI, unsigned OpNum,
155  const MCSubtargetInfo &STI, raw_ostream &O);
156  void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
157  const MCSubtargetInfo &STI, raw_ostream &O);
158  template<unsigned size>
159  void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
160  const MCSubtargetInfo &STI,
161  raw_ostream &O);
162 };
163 
165 public:
167  const MCRegisterInfo &MRI);
168 
169  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
170  const MCSubtargetInfo &STI) override;
171 
172  void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
173  raw_ostream &O) override;
174  bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
175  raw_ostream &O) override;
176  void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
177  unsigned PrintMethodIdx,
178  const MCSubtargetInfo &STI,
179  raw_ostream &O) override;
180  StringRef getRegName(unsigned RegNo) const override {
181  return getRegisterName(RegNo);
182  }
183  static const char *getRegisterName(unsigned RegNo,
184  unsigned AltIdx = AArch64::NoRegAltName);
185 };
186 }
187 
188 #endif
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printLogicalImm32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
StringRef getRegName(unsigned RegNo) const override
void printLogicalImm64(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) override
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
void printAlignedLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) override
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, const MCSubtargetInfo &STI, raw_ostream &O)
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, const MCSubtargetInfo &STI, raw_ostream &O) override
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrpLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIncOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
virtual StringRef getRegName(unsigned RegNo) const
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:41
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
MCSubtargetInfo - Generic base class for all target subtargets.
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
const MCInstrInfo & MII
Definition: MCInstPrinter.h:48
void printUImm12Offset(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:49
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)