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LLVM
4.0.0
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#include <AArch64InstructionSelector.h>
Public Member Functions | |
| AArch64InstructionSelector (const AArch64TargetMachine &TM, const AArch64Subtarget &STI, const AArch64RegisterBankInfo &RBI) | |
| bool | select (MachineInstr &I) const override |
Select the (possibly generic) instruction I to only use target-specific opcodes. More... | |
Public Member Functions inherited from llvm::InstructionSelector | |
| virtual | ~InstructionSelector () |
Additional Inherited Members | |
Protected Member Functions inherited from llvm::InstructionSelector | |
| InstructionSelector () | |
| bool | constrainSelectedInstRegOperands (MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const |
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands to the instruction's register class. More... | |
Definition at line 27 of file AArch64InstructionSelector.h.
| AArch64InstructionSelector::AArch64InstructionSelector | ( | const AArch64TargetMachine & | TM, |
| const AArch64Subtarget & | STI, | ||
| const AArch64RegisterBankInfo & | RBI | ||
| ) |
Definition at line 41 of file AArch64InstructionSelector.cpp.
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overridevirtual |
Select the (possibly generic) instruction I to only use target-specific opcodes.
It is OK to insert multiple instructions, but they cannot be generic pre-isel instructions.
Implements llvm::InstructionSelector.
Definition at line 476 of file AArch64InstructionSelector.cpp.
References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addUse(), llvm::AArch64CC::AL, assert(), llvm::APFloat::bitcastToAPInt(), llvm::BuildMI(), changeFCMPPredToAArch64CC(), changeICMPPredToAArch64CC(), llvm::MachineOperand::ChangeToImmediate(), llvm::AArch64Subtarget::ClassifyGlobalReference(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::dbgs(), DEBUG, llvm::PointerUnion< PT1, PT2 >::dyn_cast(), llvm::AArch64_AM::encodeLogicalImmediate(), llvm::MachineInstr::eraseFromParent(), llvm::AArch64::FPRRegBankID, llvm::PointerUnion< PT1, PT2 >::get(), llvm::MachineOperand::getCImm(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getFPImm(), llvm::MachineOperand::getGlobal(), llvm::RegisterBank::getID(), llvm::CmpInst::getInversePredicate(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getPredicate(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), getRegClassForTypeOnBank(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::ConstantFP::getValueAPF(), llvm::ConstantInt::getZExtValue(), llvm::APInt::getZExtValue(), llvm::AArch64::GPRRegBankID, llvm::MachineInstr::isCopy(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::LLT::isPointer(), llvm::isPreISelGenericOpcode(), llvm::MachineOperand::isReg(), llvm::LLT::isScalar(), llvm::LLT::isValid(), llvm::AArch64ISD::LOADgot, MBB, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, MRI, llvm::AArch64CC::NE, llvm::LLT::pointer(), llvm::LLT::scalar(), selectBinaryOp(), selectCopy(), selectFPConvOpc(), selectLoadStoreUIOp(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), llvm::MachineOperand::setTargetFlags(), unsupportedBinOp(), and llvm::LLT::vector().
1.8.6