LLVM  4.0.0
BPFRegisterInfo.cpp
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1 //===-- BPFRegisterInfo.cpp - BPF Register Information ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the BPF implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "BPF.h"
15 #include "BPFRegisterInfo.h"
16 #include "BPFSubtarget.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "BPFGenRegisterInfo.inc"
27 using namespace llvm;
28 
30  : BPFGenRegisterInfo(BPF::R0) {}
31 
32 const MCPhysReg *
34  return CSR_SaveList;
35 }
36 
38  BitVector Reserved(getNumRegs());
39  Reserved.set(BPF::R10); // R10 is read only frame pointer
40  Reserved.set(BPF::R11); // R11 is pseudo stack pointer
41  return Reserved;
42 }
43 
45  int SPAdj, unsigned FIOperandNum,
46  RegScavenger *RS) const {
47  assert(SPAdj == 0 && "Unexpected");
48 
49  unsigned i = 0;
50  MachineInstr &MI = *II;
51  MachineFunction &MF = *MI.getParent()->getParent();
52  DebugLoc DL = MI.getDebugLoc();
53 
54  while (!MI.getOperand(i).isFI()) {
55  ++i;
56  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
57  }
58 
59  unsigned FrameReg = getFrameRegister(MF);
60  int FrameIndex = MI.getOperand(i).getIndex();
63 
64  if (MI.getOpcode() == BPF::MOV_rr) {
65  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
66 
67  MI.getOperand(i).ChangeToRegister(FrameReg, false);
68  unsigned reg = MI.getOperand(i - 1).getReg();
69  BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
70  .addReg(reg)
71  .addImm(Offset);
72  return;
73  }
74 
75  int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
76  MI.getOperand(i + 1).getImm();
77 
78  if (!isInt<32>(Offset))
79  llvm_unreachable("bug in frame offset");
80 
81  if (MI.getOpcode() == BPF::FI_ri) {
82  // architecture does not really support FI_ri, replace it with
83  // MOV_rr <target_reg>, frame_reg
84  // ADD_ri <target_reg>, imm
85  unsigned reg = MI.getOperand(i - 1).getReg();
86 
87  BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
88  .addReg(FrameReg);
89  BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
90  .addReg(reg)
91  .addImm(Offset);
92 
93  // Remove FI_ri instruction
94  MI.eraseFromParent();
95  } else {
96  MI.getOperand(i).ChangeToRegister(FrameReg, false);
97  MI.getOperand(i + 1).ChangeToImmediate(Offset);
98  }
99 }
100 
102  return BPF::R10;
103 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:219
unsigned getFrameRegister(const MachineFunction &MF) const override
size_t i
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
A debug info location.
Definition: DebugLoc.h:34
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineBasicBlock * MBB
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
uint32_t Offset
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:274
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
IRTranslator LLVM IR MI
BitVector getReservedRegs(const MachineFunction &MF) const override