LLVM  4.0.0
SystemZFrameLowering.cpp
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1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZFrameLowering.h"
11 #include "SystemZCallingConv.h"
12 #include "SystemZInstrBuilder.h"
13 #include "SystemZInstrInfo.h"
15 #include "SystemZRegisterInfo.h"
16 #include "SystemZSubtarget.h"
20 #include "llvm/IR/Function.h"
21 
22 using namespace llvm;
23 
24 namespace {
25 // The ABI-defined register save slots, relative to the incoming stack
26 // pointer.
27 static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
28  { SystemZ::R2D, 0x10 },
29  { SystemZ::R3D, 0x18 },
30  { SystemZ::R4D, 0x20 },
31  { SystemZ::R5D, 0x28 },
32  { SystemZ::R6D, 0x30 },
33  { SystemZ::R7D, 0x38 },
34  { SystemZ::R8D, 0x40 },
35  { SystemZ::R9D, 0x48 },
36  { SystemZ::R10D, 0x50 },
37  { SystemZ::R11D, 0x58 },
38  { SystemZ::R12D, 0x60 },
39  { SystemZ::R13D, 0x68 },
40  { SystemZ::R14D, 0x70 },
41  { SystemZ::R15D, 0x78 },
42  { SystemZ::F0D, 0x80 },
43  { SystemZ::F2D, 0x88 },
44  { SystemZ::F4D, 0x90 },
45  { SystemZ::F6D, 0x98 }
46 };
47 } // end anonymous namespace
48 
50  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
51  -SystemZMC::CallFrameSize, 8,
52  false /* StackRealignable */) {
53  // Create a mapping from register number to save slot offset.
54  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
55  for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
56  RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
57 }
58 
61  NumEntries = array_lengthof(SpillOffsetTable);
62  return SpillOffsetTable;
63 }
64 
66  BitVector &SavedRegs,
67  RegScavenger *RS) const {
69 
70  MachineFrameInfo &MFFrame = MF.getFrameInfo();
72  bool HasFP = hasFP(MF);
74  bool IsVarArg = MF.getFunction()->isVarArg();
75 
76  // va_start stores incoming FPR varargs in the normal way, but delegates
77  // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
78  // Record these pending uses, which typically include the call-saved
79  // argument register R6D.
80  if (IsVarArg)
81  for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
82  SavedRegs.set(SystemZ::ArgGPRs[I]);
83 
84  // If there are any landing pads, entering them will modify r6/r7.
85  if (!MF.getLandingPads().empty()) {
86  SavedRegs.set(SystemZ::R6D);
87  SavedRegs.set(SystemZ::R7D);
88  }
89 
90  // If the function requires a frame pointer, record that the hard
91  // frame pointer will be clobbered.
92  if (HasFP)
93  SavedRegs.set(SystemZ::R11D);
94 
95  // If the function calls other functions, record that the return
96  // address register will be clobbered.
97  if (MFFrame.hasCalls())
98  SavedRegs.set(SystemZ::R14D);
99 
100  // If we are saving GPRs other than the stack pointer, we might as well
101  // save and restore the stack pointer at the same time, via STMG and LMG.
102  // This allows the deallocation to be done by the LMG, rather than needing
103  // a separate %r15 addition.
104  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
105  for (unsigned I = 0; CSRegs[I]; ++I) {
106  unsigned Reg = CSRegs[I];
107  if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
108  SavedRegs.set(SystemZ::R15D);
109  break;
110  }
111  }
112 }
113 
114 // Add GPR64 to the save instruction being built by MIB, which is in basic
115 // block MBB. IsImplicit says whether this is an explicit operand to the
116 // instruction, or an implicit one that comes between the explicit start
117 // and end registers.
119  unsigned GPR64, bool IsImplicit) {
120  const TargetRegisterInfo *RI =
122  unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
123  bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
124  if (!IsLive || !IsImplicit) {
125  MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
126  if (!IsLive)
127  MBB.addLiveIn(GPR64);
128  }
129 }
130 
134  const std::vector<CalleeSavedInfo> &CSI,
135  const TargetRegisterInfo *TRI) const {
136  if (CSI.empty())
137  return false;
138 
139  MachineFunction &MF = *MBB.getParent();
142  bool IsVarArg = MF.getFunction()->isVarArg();
143  DebugLoc DL;
144 
145  // Scan the call-saved GPRs and find the bounds of the register spill area.
146  unsigned LowGPR = 0;
147  unsigned HighGPR = SystemZ::R15D;
148  unsigned StartOffset = -1U;
149  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
150  unsigned Reg = CSI[I].getReg();
151  if (SystemZ::GR64BitRegClass.contains(Reg)) {
152  unsigned Offset = RegSpillOffsets[Reg];
153  assert(Offset && "Unexpected GPR save");
154  if (StartOffset > Offset) {
155  LowGPR = Reg;
156  StartOffset = Offset;
157  }
158  }
159  }
160 
161  // Save the range of call-saved registers, for use by the epilogue inserter.
162  ZFI->setLowSavedGPR(LowGPR);
163  ZFI->setHighSavedGPR(HighGPR);
164 
165  // Include the GPR varargs, if any. R6D is call-saved, so would
166  // be included by the loop above, but we also need to handle the
167  // call-clobbered argument registers.
168  if (IsVarArg) {
169  unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
170  if (FirstGPR < SystemZ::NumArgGPRs) {
171  unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
172  unsigned Offset = RegSpillOffsets[Reg];
173  if (StartOffset > Offset) {
174  LowGPR = Reg; StartOffset = Offset;
175  }
176  }
177  }
178 
179  // Save GPRs
180  if (LowGPR) {
181  assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
182 
183  // Build an STMG instruction.
184  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
185 
186  // Add the explicit register operands.
187  addSavedGPR(MBB, MIB, LowGPR, false);
188  addSavedGPR(MBB, MIB, HighGPR, false);
189 
190  // Add the address.
191  MIB.addReg(SystemZ::R15D).addImm(StartOffset);
192 
193  // Make sure all call-saved GPRs are included as operands and are
194  // marked as live on entry.
195  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
196  unsigned Reg = CSI[I].getReg();
197  if (SystemZ::GR64BitRegClass.contains(Reg))
198  addSavedGPR(MBB, MIB, Reg, true);
199  }
200 
201  // ...likewise GPR varargs.
202  if (IsVarArg)
203  for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
204  addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
205  }
206 
207  // Save FPRs in the normal TargetInstrInfo way.
208  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
209  unsigned Reg = CSI[I].getReg();
210  if (SystemZ::FP64BitRegClass.contains(Reg)) {
211  MBB.addLiveIn(Reg);
212  TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
213  &SystemZ::FP64BitRegClass, TRI);
214  }
215  }
216 
217  return true;
218 }
219 
223  const std::vector<CalleeSavedInfo> &CSI,
224  const TargetRegisterInfo *TRI) const {
225  if (CSI.empty())
226  return false;
227 
228  MachineFunction &MF = *MBB.getParent();
231  bool HasFP = hasFP(MF);
232  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
233 
234  // Restore FPRs in the normal TargetInstrInfo way.
235  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
236  unsigned Reg = CSI[I].getReg();
237  if (SystemZ::FP64BitRegClass.contains(Reg))
238  TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
239  &SystemZ::FP64BitRegClass, TRI);
240  }
241 
242  // Restore call-saved GPRs (but not call-clobbered varargs, which at
243  // this point might hold return values).
244  unsigned LowGPR = ZFI->getLowSavedGPR();
245  unsigned HighGPR = ZFI->getHighSavedGPR();
246  unsigned StartOffset = RegSpillOffsets[LowGPR];
247  if (LowGPR) {
248  // If we saved any of %r2-%r5 as varargs, we should also be saving
249  // and restoring %r6. If we're saving %r6 or above, we should be
250  // restoring it too.
251  assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
252 
253  // Build an LMG instruction.
254  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
255 
256  // Add the explicit register operands.
257  MIB.addReg(LowGPR, RegState::Define);
258  MIB.addReg(HighGPR, RegState::Define);
259 
260  // Add the address.
261  MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
262  MIB.addImm(StartOffset);
263 
264  // Do a second scan adding regs as being defined by instruction
265  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
266  unsigned Reg = CSI[I].getReg();
267  if (Reg != LowGPR && Reg != HighGPR &&
268  SystemZ::GR64BitRegClass.contains(Reg))
270  }
271  }
272 
273  return true;
274 }
275 
278  RegScavenger *RS) const {
279  MachineFrameInfo &MFFrame = MF.getFrameInfo();
280  uint64_t MaxReach = (MFFrame.estimateStackSize(MF) +
282  if (!isUInt<12>(MaxReach)) {
283  // We may need register scavenging slots if some parts of the frame
284  // are outside the reach of an unsigned 12-bit displacement.
285  // Create 2 for the case where both addresses in an MVC are
286  // out of range.
287  RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
288  RS->addScavengingFrameIndex(MFFrame.CreateStackObject(8, 8, false));
289  }
290 }
291 
292 // Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
295  const DebugLoc &DL,
296  unsigned Reg, int64_t NumBytes,
297  const TargetInstrInfo *TII) {
298  while (NumBytes) {
299  unsigned Opcode;
300  int64_t ThisVal = NumBytes;
301  if (isInt<16>(NumBytes))
302  Opcode = SystemZ::AGHI;
303  else {
304  Opcode = SystemZ::AGFI;
305  // Make sure we maintain 8-byte stack alignment.
306  int64_t MinVal = -uint64_t(1) << 31;
307  int64_t MaxVal = (int64_t(1) << 31) - 8;
308  if (ThisVal < MinVal)
309  ThisVal = MinVal;
310  else if (ThisVal > MaxVal)
311  ThisVal = MaxVal;
312  }
313  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
314  .addReg(Reg).addImm(ThisVal);
315  // The CC implicit def is dead.
316  MI->getOperand(3).setIsDead();
317  NumBytes -= ThisVal;
318  }
319 }
320 
322  MachineBasicBlock &MBB) const {
323  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
324  MachineFrameInfo &MFFrame = MF.getFrameInfo();
325  auto *ZII =
326  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
328  MachineBasicBlock::iterator MBBI = MBB.begin();
329  MachineModuleInfo &MMI = MF.getMMI();
330  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
331  const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
332  bool HasFP = hasFP(MF);
333 
334  // Debug location must be unknown since the first debug location is used
335  // to determine the end of the prologue.
336  DebugLoc DL;
337 
338  // The current offset of the stack pointer from the CFA.
339  int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
340 
341  if (ZFI->getLowSavedGPR()) {
342  // Skip over the GPR saves.
343  if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
344  ++MBBI;
345  else
346  llvm_unreachable("Couldn't skip over GPR saves");
347 
348  // Add CFI for the GPR saves.
349  for (auto &Save : CSI) {
350  unsigned Reg = Save.getReg();
351  if (SystemZ::GR64BitRegClass.contains(Reg)) {
352  int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
353  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
354  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
355  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
356  .addCFIIndex(CFIIndex);
357  }
358  }
359  }
360 
361  uint64_t StackSize = getAllocatedStackSize(MF);
362  if (StackSize) {
363  // Determine if we want to store a backchain.
364  bool StoreBackchain = MF.getFunction()->hasFnAttribute("backchain");
365 
366  // If we need backchain, save current stack pointer. R1 is free at this
367  // point.
368  if (StoreBackchain)
369  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
370  .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
371 
372  // Allocate StackSize bytes.
373  int64_t Delta = -int64_t(StackSize);
374  emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
375 
376  // Add CFI for the allocation.
377  unsigned CFIIndex = MF.addFrameInst(
378  MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
379  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
380  .addCFIIndex(CFIIndex);
381  SPOffsetFromCFA += Delta;
382 
383  if (StoreBackchain)
384  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
385  .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
386  }
387 
388  if (HasFP) {
389  // Copy the base of the frame to R11.
390  BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
391  .addReg(SystemZ::R15D);
392 
393  // Add CFI for the new frame location.
394  unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
395  unsigned CFIIndex = MF.addFrameInst(
396  MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
397  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
398  .addCFIIndex(CFIIndex);
399 
400  // Mark the FramePtr as live at the beginning of every block except
401  // the entry block. (We'll have marked R11 as live on entry when
402  // saving the GPRs.)
403  for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
404  I->addLiveIn(SystemZ::R11D);
405  }
406 
407  // Skip over the FPR saves.
408  SmallVector<unsigned, 8> CFIIndexes;
409  for (auto &Save : CSI) {
410  unsigned Reg = Save.getReg();
411  if (SystemZ::FP64BitRegClass.contains(Reg)) {
412  if (MBBI != MBB.end() &&
413  (MBBI->getOpcode() == SystemZ::STD ||
414  MBBI->getOpcode() == SystemZ::STDY))
415  ++MBBI;
416  else
417  llvm_unreachable("Couldn't skip over FPR save");
418 
419  // Add CFI for the this save.
420  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
421  unsigned IgnoredFrameReg;
422  int64_t Offset =
423  getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
424 
425  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
426  nullptr, DwarfReg, SPOffsetFromCFA + Offset));
427  CFIIndexes.push_back(CFIIndex);
428  }
429  }
430  // Complete the CFI for the FPR saves, modelling them as taking effect
431  // after the last save.
432  for (auto CFIIndex : CFIIndexes) {
433  BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
434  .addCFIIndex(CFIIndex);
435  }
436 }
437 
439  MachineBasicBlock &MBB) const {
441  auto *ZII =
442  static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
444 
445  // Skip the return instruction.
446  assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
447 
448  uint64_t StackSize = getAllocatedStackSize(MF);
449  if (ZFI->getLowSavedGPR()) {
450  --MBBI;
451  unsigned Opcode = MBBI->getOpcode();
452  if (Opcode != SystemZ::LMG)
453  llvm_unreachable("Expected to see callee-save register restore code");
454 
455  unsigned AddrOpNo = 2;
456  DebugLoc DL = MBBI->getDebugLoc();
457  uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
458  unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
459 
460  // If the offset is too large, use the largest stack-aligned offset
461  // and add the rest to the base register (the stack or frame pointer).
462  if (!NewOpcode) {
463  uint64_t NumBytes = Offset - 0x7fff8;
464  emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
465  NumBytes, ZII);
466  Offset -= NumBytes;
467  NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
468  assert(NewOpcode && "No restore instruction available");
469  }
470 
471  MBBI->setDesc(ZII->get(NewOpcode));
472  MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
473  } else if (StackSize) {
474  DebugLoc DL = MBBI->getDebugLoc();
475  emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
476  }
477 }
478 
480  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
482  MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
483 }
484 
486  int FI,
487  unsigned &FrameReg) const {
488  const MachineFrameInfo &MFFrame = MF.getFrameInfo();
490 
491  // Fill in FrameReg output argument.
492  FrameReg = RI->getFrameRegister(MF);
493 
494  // Start with the offset of FI from the top of the caller-allocated frame
495  // (i.e. the top of the 160 bytes allocated by the caller). This initial
496  // offset is therefore negative.
497  int64_t Offset = (MFFrame.getObjectOffset(FI) +
498  MFFrame.getOffsetAdjustment());
499 
500  // Make the offset relative to the incoming stack pointer.
501  Offset -= getOffsetOfLocalArea();
502 
503  // Make the offset relative to the bottom of the frame.
504  Offset += getAllocatedStackSize(MF);
505 
506  return Offset;
507 }
508 
509 uint64_t SystemZFrameLowering::
511  const MachineFrameInfo &MFFrame = MF.getFrameInfo();
512 
513  // Start with the size of the local variables and spill slots.
514  uint64_t StackSize = MFFrame.getStackSize();
515 
516  // We need to allocate the ABI-defined 160-byte base area whenever
517  // we allocate stack space for our own use and whenever we call another
518  // function.
519  if (StackSize || MFFrame.hasVarSizedObjects() || MFFrame.hasCalls())
520  StackSize += SystemZMC::CallFrameSize;
521 
522  return StackSize;
523 }
524 
525 bool
527  // The ABI requires us to allocate 160 bytes of stack space for the callee,
528  // with any outgoing stack arguments being placed above that. It seems
529  // better to make that area a permanent feature of the frame even if
530  // we're using a frame pointer.
531  return true;
532 }
533 
538  switch (MI->getOpcode()) {
539  case SystemZ::ADJCALLSTACKDOWN:
540  case SystemZ::ADJCALLSTACKUP:
542  "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
543  return MBB.erase(MI);
544  break;
545 
546  default:
547  llvm_unreachable("Unexpected call frame instruction");
548  }
549 }
void push_back(const T &Elt)
Definition: SmallVector.h:211
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:219
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const int64_t CallFrameSize
static void emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII)
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:396
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned NumArgGPRs
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:383
return AArch64::GPR64RegClass contains(Reg)
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineBasicBlock & front() const
int getOffsetAdjustment() const
Return the correction for frame offsets.
MachineBasicBlock * MBB
Function Alias Analysis false
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
unsigned getKillRegState(bool B)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:376
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
const int64_t CFAOffsetFromInitialSP
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
uint32_t Offset
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool hasCalls() const
Return true if the current function has any function calls.
static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, unsigned GPR64, bool IsImplicit)
const MCContext & getContext() const
uint64_t getAllocatedStackSize(const MachineFunction &MF) const
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
bool test(unsigned Idx) const
Definition: BitVector.h:323
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
Information about stack frame layout on the target.
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:245
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1132
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBII, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getImplRegState(bool B)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
void grow(IndexT n)
Definition: IndexedMap.h:68
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
const MCPhysReg ArgGPRs[NumArgGPRs]
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineModuleInfo & getMMI() const
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.cpp:234
This class contains meta information specific to a module.