LLVM  4.0.0
ScheduleDAGInstrs.h
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1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ScheduleDAGInstrs class, which implements
11 // scheduling for a MachineInstr-based dependency graph.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
17 
18 #include "llvm/ADT/MapVector.h"
20 #include "llvm/ADT/SparseSet.h"
23 #include "llvm/Support/Compiler.h"
25 #include <list>
26 
27 namespace llvm {
28  class MachineFrameInfo;
29  class MachineLoopInfo;
30  class MachineDominatorTree;
31  class RegPressureTracker;
32  class PressureDiffs;
33 
34  /// An individual mapping from virtual register number to SUnit.
35  struct VReg2SUnit {
36  unsigned VirtReg;
39 
41  : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
42 
43  unsigned getSparseSetIndex() const {
45  }
46  };
47 
48  /// Mapping from virtual register to SUnit including an operand index.
49  struct VReg2SUnitOperIdx : public VReg2SUnit {
50  unsigned OperandIndex;
51 
53  unsigned OperandIndex, SUnit *SU)
54  : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
55  };
56 
57  /// Record a physical register access.
58  /// For non-data-dependent uses, OpIdx == -1.
59  struct PhysRegSUOper {
61  int OpIdx;
62  unsigned Reg;
63 
64  PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
65 
66  unsigned getSparseSetIndex() const { return Reg; }
67  };
68 
69  /// Use a SparseMultiSet to track physical registers. Storage is only
70  /// allocated once for the pass. It can be cleared in constant time and reused
71  /// without any frees.
72  typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
74 
75  /// Use SparseSet as a SparseMap by relying on the fact that it never
76  /// compares ValueT's, only unsigned keys. This allows the set to be cleared
77  /// between scheduling regions in constant time as long as ValueT does not
78  /// require a destructor.
80 
81  /// Track local uses of virtual registers. These uses are gathered by the DAG
82  /// builder and may be consulted by the scheduler to avoid iterating an entire
83  /// vreg use list.
85 
88 
90  struct UnderlyingObject : PointerIntPair<ValueType, 1, bool> {
92  : PointerIntPair<ValueType, 1, bool>(V, MayAlias) {}
93  ValueType getValue() const { return getPointer(); }
94  bool mayAlias() const { return getInt(); }
95  };
97 
98  /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
99  /// MachineInstrs.
101  protected:
104 
105  /// TargetSchedModel provides an interface to the machine model.
107 
108  /// True if the DAG builder should remove kill flags (in preparation for
109  /// rescheduling).
111 
112  /// The standard DAG builder does not normally include terminators as DAG
113  /// nodes because it does not create the necessary dependencies to prevent
114  /// reordering. A specialized scheduler can override
115  /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate
116  /// it has taken responsibility for scheduling the terminator correctly.
118 
119  /// Whether lane masks should get tracked.
121 
122  /// State specific to the current scheduling region.
123  /// ------------------------------------------------
124 
125  /// The block in which to insert instructions
127 
128  /// The beginning of the range to be scheduled.
130 
131  /// The end of the range to be scheduled.
133 
134  /// Instructions in this region (distance(RegionBegin, RegionEnd)).
135  unsigned NumRegionInstrs;
136 
137  /// After calling BuildSchedGraph, each machine instruction in the current
138  /// scheduling region is mapped to an SUnit.
140 
141  /// State internal to DAG building.
142  /// -------------------------------
143 
144  /// Defs, Uses - Remember where defs and uses of each register are as we
145  /// iterate upward through the instructions. This is allocated here instead
146  /// of inside BuildSchedGraph to avoid the need for it to be initialized and
147  /// destructed for each block.
150 
151  /// Tracks the last instruction(s) in this region defining each virtual
152  /// register. There may be multiple current definitions for a register with
153  /// disjunct lanemasks.
155  /// Tracks the last instructions in this region using each virtual register.
157 
159 
160  /// Remember a generic side-effecting instruction as we proceed.
161  /// No other SU ever gets scheduled around it (except in the special
162  /// case of a huge region that gets reduced).
164 
165  public:
166 
167  /// A list of SUnits, used in Value2SUsMap, during DAG construction.
168  /// Note: to gain speed it might be worth investigating an optimized
169  /// implementation of this data structure, such as a singly linked list
170  /// with a memory pool (SmallVector was tried but slow and SparseSet is not
171  /// applicable).
172  typedef std::list<SUnit *> SUList;
173  protected:
174  /// A map from ValueType to SUList, used during DAG construction,
175  /// as a means of remembering which SUs depend on which memory
176  /// locations.
177  class Value2SUsMap;
178 
179  /// Remove in FIFO order some SUs from huge maps.
181  Value2SUsMap &loads, unsigned N);
182 
183  /// Add a chain edge between SUa and SUb, but only if both AliasAnalysis
184  /// and Target fail to deny the dependency.
185  void addChainDependency(SUnit *SUa, SUnit *SUb,
186  unsigned Latency = 0);
187 
188  /// Add dependencies as needed from all SUs in list to SU.
189  void addChainDependencies(SUnit *SU, SUList &sus, unsigned Latency) {
190  for (auto *su : sus)
191  addChainDependency(SU, su, Latency);
192  }
193 
194  /// Add dependencies as needed from all SUs in map, to SU.
195  void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);
196 
197  /// Add dependencies as needed to SU, from all SUs mapped to V.
198  void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap,
199  ValueType V);
200 
201  /// Add barrier chain edges from all SUs in map, and then clear
202  /// the map. This is equivalent to insertBarrierChain(), but
203  /// optimized for the common case where the new BarrierChain (a
204  /// global memory object) has a higher NodeNum than all SUs in
205  /// map. It is assumed BarrierChain has been set before calling
206  /// this.
207  void addBarrierChain(Value2SUsMap &map);
208 
209  /// Insert a barrier chain in a huge region, far below current
210  /// SU. Add barrier chain edges from all SUs in map with higher
211  /// NodeNums than this new BarrierChain, and remove them from
212  /// map. It is assumed BarrierChain has been set before calling
213  /// this.
214  void insertBarrierChain(Value2SUsMap &map);
215 
216  /// For an unanalyzable memory access, this Value is used in maps.
218 
219  /// DbgValues - Remember instruction that precedes DBG_VALUE.
220  /// These are generated by buildSchedGraph but persist so they can be
221  /// referenced when emitting the final schedule.
222  typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
226 
227  /// Set of live physical registers for updating kill flags.
229 
230  public:
231  explicit ScheduleDAGInstrs(MachineFunction &mf,
232  const MachineLoopInfo *mli,
233  bool RemoveKillFlags = false);
234 
235  ~ScheduleDAGInstrs() override {}
236 
237  /// \brief Get the machine model for instruction scheduling.
238  const TargetSchedModel *getSchedModel() const { return &SchedModel; }
239 
240  /// \brief Resolve and cache a resolved scheduling class for an SUnit.
244  return SU->SchedClass;
245  }
246 
247  /// begin - Return an iterator to the top of the current scheduling region.
249 
250  /// end - Return an iterator to the bottom of the current scheduling region.
252 
253  /// newSUnit - Creates a new SUnit and return a ptr to it.
255 
256  /// getSUnit - Return an existing SUnit for this MI, or NULL.
257  SUnit *getSUnit(MachineInstr *MI) const;
258 
259  /// startBlock - Prepare to perform scheduling in the given block.
260  virtual void startBlock(MachineBasicBlock *BB);
261 
262  /// finishBlock - Clean up after scheduling in the given block.
263  virtual void finishBlock();
264 
265  /// Initialize the scheduler state for the next scheduling region.
266  virtual void enterRegion(MachineBasicBlock *bb,
269  unsigned regioninstrs);
270 
271  /// Notify that the scheduler has finished scheduling the current region.
272  virtual void exitRegion();
273 
274  /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are
275  /// input.
277  RegPressureTracker *RPTracker = nullptr,
278  PressureDiffs *PDiffs = nullptr,
279  LiveIntervals *LIS = nullptr,
280  bool TrackLaneMasks = false);
281 
282  /// addSchedBarrierDeps - Add dependencies from instructions in the current
283  /// list of instructions being scheduled to scheduling barrier. We want to
284  /// make sure instructions which define registers that are either used by
285  /// the terminator or are live-out are properly scheduled. This is
286  /// especially important when the definition latency of the return value(s)
287  /// are too high to be hidden by the branch or when the liveout registers
288  /// used by instructions in the fallthrough block.
289  void addSchedBarrierDeps();
290 
291  /// schedule - Order nodes according to selected style, filling
292  /// in the Sequence member.
293  ///
294  /// Typically, a scheduling algorithm will implement schedule() without
295  /// overriding enterRegion() or exitRegion().
296  virtual void schedule() = 0;
297 
298  /// finalizeSchedule - Allow targets to perform final scheduling actions at
299  /// the level of the whole MachineFunction. By default does nothing.
300  virtual void finalizeSchedule() {}
301 
302  void dumpNode(const SUnit *SU) const override;
303 
304  /// Return a label for a DAG node that points to an instruction.
305  std::string getGraphNodeLabel(const SUnit *SU) const override;
306 
307  /// Return a label for the region of code covered by the DAG.
308  std::string getDAGName() const override;
309 
310  /// \brief Fix register kill flags that scheduling has made invalid.
312  protected:
313  void initSUnits();
314  void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
315  void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
316  void addVRegDefDeps(SUnit *SU, unsigned OperIdx);
317  void addVRegUseDeps(SUnit *SU, unsigned OperIdx);
318 
319  /// \brief PostRA helper for rewriting kill flags.
321 
322  /// \brief Toggle a register operand kill flag.
323  ///
324  /// Other adjustments may be made to the instruction if necessary. Return
325  /// true if the operand has been deleted, false if not.
327 
328  /// Returns a mask for which lanes get read/written by the given (register)
329  /// machine operand.
331  };
332 
333  /// newSUnit - Creates a new SUnit and return a ptr to it.
335 #ifndef NDEBUG
336  const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0];
337 #endif
338  SUnits.emplace_back(MI, (unsigned)SUnits.size());
339  assert((Addr == nullptr || Addr == &SUnits[0]) &&
340  "SUnits std::vector reallocated on the fly!");
341  return &SUnits.back();
342  }
343 
344  /// getSUnit - Return an existing SUnit for this MI, or NULL.
347  if (I == MISUnitMap.end())
348  return nullptr;
349  return I->second;
350  }
351 } // namespace llvm
352 
353 #endif
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
unsigned getSparseSetIndex() const
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Record a physical register access.
void addVRegDefDeps(SUnit *SU, unsigned OperIdx)
addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur...
bool TrackLaneMasks
Whether lane masks should get tracked.
void dumpNode(const SUnit *SU) const override
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:389
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
MachineBasicBlock::iterator begin() const
begin - Return an iterator to the top of the current scheduling region.
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolve and cache a resolved scheduling class for an SUnit.
SmallVector< UnderlyingObject, 4 > UnderlyingObjectsVector
#define op(i)
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
void fixupKills(MachineBasicBlock *MBB)
Fix register kill flags that scheduling has made invalid.
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
The two locations may or may not alias. This is the least precise result.
Definition: AliasAnalysis.h:81
void insertBarrierChain(Value2SUsMap &map)
Insert a barrier chain in a huge region, far below current SU.
const TargetSchedModel * getSchedModel() const
Get the machine model for instruction scheduling.
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
void addSchedBarrierDeps()
addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being sc...
Provide an instruction scheduling machine model to CodeGen passes.
'undef' values are things that do not have specified contents.
Definition: Constants.h:1258
An individual mapping from virtual register number to SUnit.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
void addVRegUseDeps(SUnit *SU, unsigned OperIdx)
addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register ...
MachineBasicBlock * MBB
void addChainDependencies(SUnit *SU, SUList &sus, unsigned Latency)
Add dependencies as needed from all SUs in list to SU.
SUnit * BarrierChain
Remember a generic side-effecting instruction as we proceed.
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
SparseMultiSet< VReg2SUnitOperIdx, VirtReg2IndexFunctor > VReg2SUnitOperIdxMultiMap
Array of PressureDiffs.
PointerIntPair - This class implements a pair of a pointer and small integer.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
Track the current register pressure at some position in the instruction stream, and remember the high...
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
const MCSchedClassDesc * SchedClass
Definition: ScheduleDAG.h:255
const MachineFrameInfo & MFI
std::string getDAGName() const override
Return a label for the region of code covered by the DAG.
void addPhysRegDeps(SUnit *SU, unsigned OperIdx)
addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following inst...
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
std::string getGraphNodeLabel(const SUnit *SU) const override
Return a label for a DAG node that points to an instruction.
PhysRegSUOper(SUnit *su, int op, unsigned R)
void reduceHugeMemNodeMaps(Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
Remove in FIFO order some SUs from huge maps.
bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO)
Toggle a register operand kill flag.
ValueType getValue() const
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
MachineOperand class - Representation of each machine instruction operand.
LaneBitmask LaneMask
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU)
Reg2SUnitsMap Defs
State internal to DAG building.
const MachineLoopInfo * MLI
SparseMultiSet< VReg2SUnit, VirtReg2IndexFunctor > VReg2SUnitMultiMap
Track local uses of virtual registers.
VReg2SUnitOperIdxMultiMap CurrentVRegUses
Tracks the last instructions in this region using each virtual register.
virtual void finalizeSchedule()
finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole Machin...
virtual void schedule()=0
schedule - Order nodes according to selected style, filling in the Sequence member.
MachineBasicBlock::iterator end() const
end - Return an iterator to the bottom of the current scheduling region.
VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
SUnit * getSUnit(MachineInstr *MI) const
getSUnit - Return an existing SUnit for this MI, or NULL.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
Representation of each machine instruction.
Definition: MachineInstr.h:52
SparseSet - Fast set implmentation for objects that can be identified by small unsigned keys...
Definition: SparseSet.h:123
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
Mapping from virtual register to SUnit including an operand index.
void addChainDependency(SUnit *SUa, SUnit *SUb, unsigned Latency=0)
Add a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the depe...
unsigned getSparseSetIndex() const
ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
SUnit * newSUnit(MachineInstr *MI)
newSUnit - Creates a new SUnit and return a ptr to it.
void addBarrierChain(Value2SUsMap &map)
Add barrier chain edges from all SUs in map, and then clear the map.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const
Returns a mask for which lanes get read/written by the given (register) machine operand.
void startBlockForKills(MachineBasicBlock *BB)
PostRA helper for rewriting kill flags.
SparseSet< VReg2SUnit, VirtReg2IndexFunctor > VReg2SUnitMap
Use SparseSet as a SparseMap by relying on the fact that it never compares ValueT's, only unsigned keys.
void initSUnits()
Create an SUnit for each real instruction, numbered in top-down topological order.
SparseMultiSet< PhysRegSUOper, llvm::identity< unsigned >, uint16_t > Reg2SUnitsMap
Use a SparseMultiSet to track physical registers.
UnderlyingObject(ValueType V, bool MayAlias)
MachineBasicBlock * BB
State specific to the current scheduling region.
IRTranslator LLVM IR MI
std::vector< SUnit > SUnits
Definition: ScheduleDAG.h:583
VReg2SUnitMultiMap CurrentVRegDefs
Tracks the last instruction(s) in this region defining each virtual register.
PointerUnion< const Value *, const PseudoSourceValue * > ValueType
BitVector LiveRegs
Set of live physical registers for updating kill flags.
hexagon widen stores
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
DbgValues - Remember instruction that precedes DBG_VALUE.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:244
std::list< SUnit * > SUList
A list of SUnits, used in Value2SUsMap, during DAG construction.