217 for (
MVT VT : ScalarIntVTs) {
239 if (std::next(I) == I->getParent()->end())
275 case AMDGPU::CLAMP_R600: {
283 case AMDGPU::FABS_R600: {
291 case AMDGPU::FNEG_R600: {
299 case AMDGPU::MASK_WRITE: {
307 case AMDGPU::MOV_IMM_F32:
315 case AMDGPU::MOV_IMM_I32:
320 case AMDGPU::MOV_IMM_GLOBAL_ADDR: {
330 case AMDGPU::CONST_COPY: {
338 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
339 case AMDGPU::RAT_WRITE_CACHELESS_64_eg:
340 case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
347 case AMDGPU::RAT_STORE_TYPED_eg:
360 case AMDGPU::BRANCH_COND_f32: {
363 AMDGPU::PREDICATE_BIT)
365 .addImm(AMDGPU::PRED_SETNE)
374 case AMDGPU::BRANCH_COND_i32: {
377 AMDGPU::PREDICATE_BIT)
379 .addImm(AMDGPU::PRED_SETNE_INT)
388 case AMDGPU::EG_ExportSwz:
389 case AMDGPU::R600_ExportSwz: {
391 bool isLastInstructionOfItsType =
true;
394 EndBlock = BB->
end(); NextExportInst != EndBlock;
395 NextExportInst = std::next(NextExportInst)) {
396 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
397 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
398 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
400 if (CurrentInstExportType == InstExportType) {
401 isLastInstructionOfItsType =
false;
407 if (!EOP && !isLastInstructionOfItsType)
409 unsigned CfInst = (MI.
getOpcode() == AMDGPU::EG_ExportSwz) ? 84 : 40;
448 case ISD::FSIN:
return LowerTrig(Op, DAG);
452 SDValue Result = LowerLOAD(Op, DAG);
455 "Load should return a value and a chain");
464 unsigned IntrinsicID =
465 cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
466 switch (IntrinsicID) {
467 case AMDGPUIntrinsic::r600_store_swizzle: {
489 unsigned IntrinsicID =
490 cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
493 switch(IntrinsicID) {
495 case AMDGPUIntrinsic::r600_tex:
496 case AMDGPUIntrinsic::r600_texc: {
498 switch (IntrinsicID) {
499 case AMDGPUIntrinsic::r600_tex:
502 case AMDGPUIntrinsic::r600_texc:
532 case AMDGPUIntrinsic::r600_dot4: {
554 case Intrinsic::r600_implicitarg_ptr: {
559 case Intrinsic::r600_read_ngroups_x:
560 return LowerImplicitParameter(DAG, VT, DL, 0);
561 case Intrinsic::r600_read_ngroups_y:
562 return LowerImplicitParameter(DAG, VT, DL, 1);
563 case Intrinsic::r600_read_ngroups_z:
564 return LowerImplicitParameter(DAG, VT, DL, 2);
565 case Intrinsic::r600_read_global_size_x:
566 return LowerImplicitParameter(DAG, VT, DL, 3);
567 case Intrinsic::r600_read_global_size_y:
568 return LowerImplicitParameter(DAG, VT, DL, 4);
569 case Intrinsic::r600_read_global_size_z:
570 return LowerImplicitParameter(DAG, VT, DL, 5);
571 case Intrinsic::r600_read_local_size_x:
572 return LowerImplicitParameter(DAG, VT, DL, 6);
573 case Intrinsic::r600_read_local_size_y:
574 return LowerImplicitParameter(DAG, VT, DL, 7);
575 case Intrinsic::r600_read_local_size_z:
576 return LowerImplicitParameter(DAG, VT, DL, 8);
578 case Intrinsic::r600_read_tgid_x:
581 case Intrinsic::r600_read_tgid_y:
584 case Intrinsic::r600_read_tgid_z:
587 case Intrinsic::r600_read_tidig_x:
590 case Intrinsic::r600_read_tidig_y:
593 case Intrinsic::r600_read_tidig_z:
597 case Intrinsic::r600_recipsqrt_ieee:
600 case Intrinsic::r600_recipsqrt_clamped:
675 if (isa<ConstantSDNode>(Index) ||
679 Vector = vectorToVerticalVector(DAG, Vector);
691 if (isa<ConstantSDNode>(Index) ||
695 Vector = vectorToVerticalVector(DAG, Vector);
697 Vector, Value, Index);
698 return vectorToVerticalVector(DAG, Insert);
825 unsigned mainop,
unsigned ovf)
const {
864 unsigned DwordOffset)
const {
865 unsigned ByteOffset = DwordOffset * 4;
877 bool R600TargetLowering::isZero(
SDValue Op)
const {
879 return Cst->isNullValue();
881 return CstFP->isZero();
887 bool R600TargetLowering::isHWTrueValue(
SDValue Op)
const {
889 return CFP->isExactlyValue(1.0);
894 bool R600TargetLowering::isHWFalseValue(
SDValue Op)
const {
896 return CFP->getValueAPF().isZero();
937 if (isHWTrueValue(False) && isHWFalseValue(True)) {
951 if (isHWTrueValue(True) && isHWFalseValue(False) &&
952 (CompareVT == VT || VT ==
MVT::i32)) {
990 if (CompareVT != VT) {
1025 }
else if (CompareVT ==
MVT::i32) {
1049 unsigned StackWidth,
1052 switch(StackWidth) {
1070 void R600TargetLowering::getStackAddress(
unsigned StackWidth,
1073 unsigned &PtrIncr)
const {
1074 switch (StackWidth) {
1085 Channel = ElemIdx % 2;
1160 MaskedValue, ShiftAmt);
1213 StoreNode = cast<StoreSDNode>(NewStore);
1263 SDValue Args[3] = { Chain, Input, DWordAddr };
1285 return lowerPrivateTruncStore(StoreNode, DAG);
1301 switch (AddressSpace) {
1307 return 512 + 4096 * 2;
1309 return 512 + 4096 * 3;
1311 return 512 + 4096 * 4;
1313 return 512 + 4096 * 5;
1315 return 512 + 4096 * 6;
1317 return 512 + 4096 * 7;
1319 return 512 + 4096 * 8;
1321 return 512 + 4096 * 9;
1323 return 512 + 4096 * 10;
1325 return 512 + 4096 * 11;
1327 return 512 + 4096 * 12;
1329 return 512 + 4096 * 13;
1331 return 512 + 4096 * 14;
1333 return 512 + 4096 * 15;
1402 return lowerPrivateExtLoad(Op, DAG);
1417 if (ConstantBlock > -1 &&
1423 isa<ConstantSDNode>(Ptr)) {
1425 for (
unsigned i = 0;
i < 4;
i++) {
1436 unsigned NumElements = 4;
1480 SDValue MergedValues[2] = { Res, Chain };
1515 unsigned IgnoredFrameReg;
1543 for (
unsigned i = 0, e = Ins.
size();
i < e; ++
i) {
1554 unsigned Reg = MF.addLiveIn(VA.
getLocReg(), &AMDGPU::R600_Reg128RegClass);
1612 bool *IsFast)
const {
1641 for (
unsigned i = 0;
i < 4;
i++) {
1642 if (NewBldVec[
i].isUndef())
1646 RemapSwizzle[
i] = 7;
1649 RemapSwizzle[
i] = 4;
1651 }
else if (
C->isExactlyValue(1.0)) {
1652 RemapSwizzle[
i] = 5;
1657 if (NewBldVec[i].isUndef())
1659 for (
unsigned j = 0; j <
i; j++) {
1660 if (NewBldVec[i] == NewBldVec[j]) {
1662 RemapSwizzle[
i] = j;
1682 bool isUnmovable[4] = {
false,
false,
false,
false };
1683 for (
unsigned i = 0;
i < 4;
i++) {
1684 RemapSwizzle[
i] =
i;
1689 isUnmovable[Idx] =
true;
1693 for (
unsigned i = 0;
i < 4;
i++) {
1697 if (isUnmovable[Idx])
1701 std::swap(RemapSwizzle[i], RemapSwizzle[Idx]);
1712 const SDLoc &DL)
const {
1718 for (
unsigned i = 0;
i < 4;
i++) {
1719 unsigned Idx = cast<ConstantSDNode>(Swz[
i])->getZExtValue();
1720 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1724 SwizzleRemap.clear();
1726 for (
unsigned i = 0;
i < 4;
i++) {
1727 unsigned Idx = cast<ConstantSDNode>(Swz[
i])->getZExtValue();
1728 if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
1802 if (!isa<ConstantSDNode>(EltNo))
1804 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
1821 if (Elt < Ops.
size()) {
1824 EVT OpVT = Ops[0].getValueType();
1842 unsigned Element = Const->getZExtValue();
1851 unsigned Element = Const->getZExtValue();
1921 NewArgs[1] = OptimizeSwizzle(N->
getOperand(1), &NewArgs[4], DAG, DL);
1950 NewArgs[1] = OptimizeSwizzle(N->
getOperand(1), &NewArgs[2], DAG, DL);
1959 bool R600TargetLowering::FoldOperand(
SDNode *ParentNode,
unsigned SrcIdx,
1968 case AMDGPU::FNEG_R600:
1974 case AMDGPU::FABS_R600:
1980 case AMDGPU::CONST_COPY: {
1982 bool HasDst = TII->
getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
1992 int SrcIndices[] = {
2005 std::vector<unsigned> Consts;
2006 for (
int OtherSrcIdx : SrcIndices) {
2007 int OtherSelIdx = TII->
getSelIdx(Opcode, OtherSrcIdx);
2008 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
2015 dyn_cast<RegisterSDNode>(ParentNode->
getOperand(OtherSrcIdx))) {
2016 if (
Reg->getReg() == AMDGPU::ALU_CONST) {
2018 = cast<ConstantSDNode>(ParentNode->
getOperand(OtherSelIdx));
2034 case AMDGPU::MOV_IMM_GLOBAL_ADDR:
2036 if (cast<ConstantSDNode>(Imm)->getZExtValue())
2041 case AMDGPU::MOV_IMM_I32:
2042 case AMDGPU::MOV_IMM_F32: {
2043 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
2044 uint64_t ImmValue = 0;
2049 if (FloatValue == 0.0) {
2050 ImmReg = AMDGPU::ZERO;
2051 }
else if (FloatValue == 0.5) {
2052 ImmReg = AMDGPU::HALF;
2053 }
else if (FloatValue == 1.0) {
2054 ImmReg = AMDGPU::ONE;
2062 ImmReg = AMDGPU::ZERO;
2063 }
else if (Value == 1) {
2064 ImmReg = AMDGPU::ONE_INT;
2073 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
2102 if (Opcode == AMDGPU::DOT_4) {
2103 int OperandIdx[] = {
2133 for (
unsigned i = 0;
i < 8;
i++) {
2134 if (OperandIdx[
i] < 0)
2136 SDValue &Src = Ops[OperandIdx[
i] - 1];
2139 bool HasDst = TII->
getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2140 int SelIdx = TII->
getSelIdx(Opcode, OperandIdx[
i]);
2143 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2144 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG))
2147 }
else if (Opcode == AMDGPU::REG_SEQUENCE) {
2148 for (
unsigned i = 1, e = Node->
getNumOperands(); i < e; i += 2) {
2150 if (FoldOperand(Node, i, Src, FakeOp, FakeOp, FakeOp, FakeOp, DAG))
2153 }
else if (Opcode == AMDGPU::CLAMP_R600) {
2159 AMDGPU::OpName::clamp);
2170 int OperandIdx[] = {
2185 for (
unsigned i = 0; i < 3; i++) {
2186 if (OperandIdx[i] < 0)
2188 SDValue &Src = Ops[OperandIdx[
i] - 1];
2191 SDValue &Abs = (AbsIdx[
i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2192 bool HasDst = TII->
getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
2193 int SelIdx = TII->
getSelIdx(Opcode, OperandIdx[i]);
2194 int ImmIdx = TII->
getOperandIdx(Opcode, AMDGPU::OpName::literal);
2199 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2201 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
static SDValue CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap< unsigned, unsigned > &RemapSwizzle)
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
SDValue getValue(unsigned R) const
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Flags getFlags() const
Return the raw flags of the source value,.
LLVMContext * getContext() const
AMDGPU specific subclass of TargetSubtarget.
uint64_t getZExtValue() const
Get zero extended value.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
BR_CC - Conditional branch.
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Interface definition for R600InstrInfo.
const ConstantFP * getFPImm() const
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
float convertToFloat() const
SDVTList getVTList() const
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
Carry-setting nodes for multiple precision addition and subtraction.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const GlobalValue * getGlobal() const
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
Function Alias Analysis Results
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getNumOperands() const
Return the number of values used by this operation.
constexpr bool isInt< 16 >(int64_t x)
const SDValue & getOperand(unsigned Num) const
Address space for local memory.
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const
Expand float(f32) to SINT(i64) conversion.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Turn load of vector type into a load of the individual elements.
const SDValue & getBasePtr() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors...
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
Pointer to the start of the shader's constant data.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
MachineFunction & getMachineFunction() const
int getLDSNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
unsigned getAddressSpace() const
Reg
All possible values of the reg field in the ModR/M byte.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
APInt bitcastToAPInt() const
The memory access is dereferenceable (i.e., doesn't trap).
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
unsigned getMachineOpcode() const
bool bitsGE(EVT VT) const
bitsGE - Return true if this has no less bits than VT.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Interface to describe a layout of a stack frame on an AMDGPU target.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This file implements a class to represent arbitrary precision integral constant values and operations...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool hasInstrModifiers(unsigned Opcode) const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
const AMDGPUSubtarget * Subtarget
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Simple integer binary arithmetic operators.
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Class to represent pointers.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
const R600FrameLowering * getFrameLowering() const override
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getScalarSizeInBits() const
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
unsigned const MachineRegisterInfo * MRI
static ConstantPointerNull * get(PointerType *T)
Static factory methods - Return objects of the specified value.
MVT - Machine Value Type.
bool isShader(CallingConv::ID cc)
const SDValue & getOperand(unsigned i) const
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Address space for constant memory (VTX2)
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
static int ConstantAddressBlock(unsigned AddressSpace)
Address space for private memory.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
bool isBeforeLegalizeOps() const
Carry-using nodes for multiple precision addition and subtraction.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
const R600InstrInfo * getInstrInfo() const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel fun...
The memory access is non-temporal.
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
const SDValue & getValue() const
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
EVT - Extended Value Type.
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
const APFloat & getValueAPF() const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap< unsigned, unsigned > &RemapSwizzle)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
const MachinePointerInfo & getPointerInfo() const
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
const SDValue & getOffset() const
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
const R600RegisterInfo * getRegisterInfo() const override
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
CCState - This class holds information needed while lowering arguments and return values...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
An SDNode that represents everything that will be needed to construct a MachineInstr.
const SDValue & getChain() const
Promote Memory to Register
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const R600Subtarget * getSubtarget() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool isMachineOpcode() const
unsigned getStackWidth(const MachineFunction &MF) const
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
const Value * getValue() const
Return the base address of the memory access.
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
Select(COND, TRUEVAL, FALSEVAL).
Interface for the AMDGPU Implementation of the Intrinsic Info class.
op_iterator op_begin() const
ANY_EXTEND - Used for integer types. The high bits are undefined.
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
unsigned getAddressSpace() const
Return the address space for the associated pointer.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
Bitwise operators - logical and, logical or, logical xor.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI)
R600 DAG Lowering interface definition.
Address space for indirect addressible parameter memory (VTX1)
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
The memory access always returns the same value (or traps).
op_iterator op_end() const
unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument...
const SDValue & getOffset() const
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
SDValue getCondCode(ISD::CondCode Cond)
LLVM_NODISCARD bool empty() const
const APFloat & getValueAPF() const
void setABIArgOffset(unsigned NewOffset)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static bool isEOP(MachineBasicBlock::iterator I)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
Primary interface to the complete machine description for the target machine.
SetCC operator - This evaluates to a true value iff the condition is true.
uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
unsigned getLocMemOffset() const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
bool isLDSRetInstr(unsigned Opcode) const
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override
Return the ValueType of the result of SETCC operations.
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Address space for global memory (RAT0, VTX0).
uint64_t getZExtValue() const
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.