22 #define DEBUG_TYPE "systemz-isel"
26 struct SystemZAddressingMode {
61 bool IncludesDynAlloc;
63 SystemZAddressingMode(AddrForm form, DispRange dr)
64 :
Form(form), DR(dr), Base(), Disp(0), Index(),
65 IncludesDynAlloc(
false) {}
68 bool hasIndexField() {
return Form != FormBD; }
71 bool isDynAlloc() {
return Form == FormBDXDynAlloc; }
74 errs() <<
"SystemZAddressingMode " <<
this <<
'\n';
78 Base.getNode()->dump();
82 if (hasIndexField()) {
85 Index.getNode()->dump();
90 errs() <<
" Disp " << Disp;
92 errs() <<
" + ADJDYNALLOC";
98 static uint64_t
allOnes(
unsigned int Count) {
102 return (uint64_t(1) << Count) - 1;
118 struct RxSBGOperands {
137 inline SDValue getImm(
const SDNode *Node, uint64_t Imm)
const {
146 return Subtarget->getInstrInfo();
151 bool expandAddress(SystemZAddressingMode &AM,
bool IsBase)
const;
154 bool selectAddress(
SDValue N, SystemZAddressingMode &AM)
const;
157 void getAddressOperands(
const SystemZAddressingMode &AM,
EVT VT,
159 void getAddressOperands(
const SystemZAddressingMode &AM,
EVT VT,
165 bool selectBDAddr(SystemZAddressingMode::DispRange DR,
SDValue Addr,
171 bool selectMVIAddr(SystemZAddressingMode::DispRange DR,
SDValue Addr,
177 bool selectBDXAddr(SystemZAddressingMode::AddrForm
Form,
178 SystemZAddressingMode::DispRange DR,
SDValue Addr,
192 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp);
195 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
198 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp);
201 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
206 return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
209 return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
215 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
216 SystemZAddressingMode::Disp12Only,
217 Addr, Base, Disp, Index);
221 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
222 SystemZAddressingMode::Disp12Pair,
223 Addr, Base, Disp, Index);
227 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc,
228 SystemZAddressingMode::Disp12Only,
229 Addr, Base, Disp, Index);
233 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
234 SystemZAddressingMode::Disp20Only,
235 Addr, Base, Disp, Index);
239 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
240 SystemZAddressingMode::Disp20Only128,
241 Addr, Base, Disp, Index);
245 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
246 SystemZAddressingMode::Disp20Pair,
247 Addr, Base, Disp, Index);
251 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
252 SystemZAddressingMode::Disp12Pair,
253 Addr, Base, Disp, Index);
257 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
258 SystemZAddressingMode::Disp20Pair,
259 Addr, Base, Disp, Index);
272 bool detectOrAndInsertion(
SDValue &
Op, uint64_t InsertMask)
const;
276 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t
Mask)
const;
280 bool expandRxSBG(RxSBGOperands &RxSBG)
const;
290 bool tryRISBGZero(
SDNode *N);
294 bool tryRxSBG(
SDNode *N,
unsigned Opcode);
303 void splitLargeImmediate(
unsigned Opcode,
SDNode *Node,
SDValue Op0,
304 uint64_t UpperVal, uint64_t LowerVal);
307 bool tryGather(
SDNode *N,
unsigned Opcode);
325 bool storeLoadCanUseMVC(
SDNode *N)
const;
330 bool storeLoadCanUseBlockBinary(
SDNode *N,
unsigned I)
const;
343 return "SystemZ DAG->DAG Pattern Instruction Selection";
348 bool SelectInlineAsmMemoryOperand(
const SDValue &Op,
unsigned ConstraintID,
349 std::vector<SDValue> &OutOps)
override;
352 #include "SystemZGenDAGISel.inc"
358 return new SystemZDAGToDAGISel(TM, OptLevel);
364 static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
366 case SystemZAddressingMode::Disp12Only:
367 return isUInt<12>(Val);
369 case SystemZAddressingMode::Disp12Pair:
370 case SystemZAddressingMode::Disp20Only:
371 case SystemZAddressingMode::Disp20Pair:
372 return isInt<20>(Val);
374 case SystemZAddressingMode::Disp20Only128:
375 return isInt<20>(Val) && isInt<20>(Val + 8);
395 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) {
397 AM.IncludesDynAlloc =
true;
407 if (AM.hasIndexField() && !AM.Index.getNode()) {
417 static bool expandDisp(SystemZAddressingMode &AM,
bool IsBase,
420 int64_t TestDisp = AM.Disp + Op1;
432 bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM,
434 SDValue N = IsBase ? AM.Base : AM.Index;
440 if (Opcode ==
ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
454 cast<ConstantSDNode>(Op0)->getSExtValue());
457 cast<ConstantSDNode>(Op1)->getSExtValue());
467 cast<GlobalAddressSDNode>(Anchor)->
getOffset());
475 static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
478 case SystemZAddressingMode::Disp12Only:
479 case SystemZAddressingMode::Disp20Only:
480 case SystemZAddressingMode::Disp20Only128:
483 case SystemZAddressingMode::Disp12Pair:
485 return isUInt<12>(Val);
487 case SystemZAddressingMode::Disp20Pair:
489 return !isUInt<12>(Val);
513 if (isUInt<12>(Disp))
532 unsigned IndexOpcode = Index->
getOpcode();
547 bool SystemZDAGToDAGISel::selectAddress(
SDValue Addr,
548 SystemZAddressingMode &AM)
const {
556 cast<ConstantSDNode>(Addr)->getSExtValue()))
564 while (expandAddress(AM,
true) ||
565 (AM.Index.getNode() && expandAddress(AM,
false)))
569 if (AM.Form == SystemZAddressingMode::FormBDXLA &&
570 !
shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode()))
578 if (AM.isDynAlloc() && !AM.IncludesDynAlloc)
598 void SystemZDAGToDAGISel::getAddressOperands(
const SystemZAddressingMode &AM,
604 Base = CurDAG->getRegister(0, VT);
607 int64_t
FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
608 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
612 "Unexpected truncation");
620 Disp = CurDAG->getTargetConstant(AM.Disp,
SDLoc(Base), VT);
623 void SystemZDAGToDAGISel::getAddressOperands(
const SystemZAddressingMode &AM,
627 getAddressOperands(AM, VT, Base, Disp);
632 Index = CurDAG->getRegister(0, VT);
635 bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
638 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR);
639 if (!selectAddress(Addr, AM))
642 getAddressOperands(AM, Addr.
getValueType(), Base, Disp);
646 bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR,
649 SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR);
650 if (!selectAddress(Addr, AM) || AM.Index.getNode())
653 getAddressOperands(AM, Addr.
getValueType(), Base, Disp);
657 bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm
Form,
658 SystemZAddressingMode::DispRange DR,
661 SystemZAddressingMode AM(Form, DR);
662 if (!selectAddress(Addr, AM))
665 getAddressOperands(AM, Addr.
getValueType(), Base, Disp, Index);
669 bool SystemZDAGToDAGISel::selectBDVAddr12Only(
SDValue Addr,
SDValue Elem,
674 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) &&
675 Regs[0].getNode() && Regs[1].getNode()) {
676 for (
unsigned int I = 0;
I < 2; ++
I) {
693 bool SystemZDAGToDAGISel::detectOrAndInsertion(
SDValue &
Op,
694 uint64_t InsertMask)
const {
707 if (InsertMask & AndMask)
713 if (Used != (AndMask | InsertMask)) {
714 APInt KnownZero, KnownOne;
715 CurDAG->computeKnownBits(Op.
getOperand(0), KnownZero, KnownOne);
716 if (Used != (AndMask | InsertMask | KnownZero.
getZExtValue()))
724 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG,
725 uint64_t
Mask)
const {
727 if (RxSBG.Rotate != 0)
728 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
730 if (TII->
isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
740 if (RxSBG.Rotate != 0)
741 Mask = ((Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate)));
742 return (Mask & RxSBG.Mask) != 0;
745 bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG)
const {
750 if (RxSBG.Opcode == SystemZ::RNSBG)
753 uint64_t Mask =
allOnes(BitSize);
754 if (!refineRxSBGMask(RxSBG, Mask))
760 if (RxSBG.Opcode == SystemZ::RNSBG)
768 uint64_t Mask = MaskNode->getZExtValue();
769 if (!refineRxSBGMask(RxSBG, Mask)) {
773 APInt KnownZero, KnownOne;
774 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
776 if (!refineRxSBGMask(RxSBG, Mask))
784 if (RxSBG.Opcode != SystemZ::RNSBG)
792 uint64_t Mask = ~MaskNode->getZExtValue();
793 if (!refineRxSBGMask(RxSBG, Mask)) {
797 APInt KnownZero, KnownOne;
798 CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
800 if (!refineRxSBGMask(RxSBG, Mask))
815 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
826 if (RxSBG.Opcode != SystemZ::RNSBG) {
829 if (!refineRxSBGMask(RxSBG,
allOnes(InnerBitSize)))
855 if (Count < 1 || Count >= BitSize)
858 if (RxSBG.Opcode == SystemZ::RNSBG) {
865 if (!refineRxSBGMask(RxSBG,
allOnes(BitSize - Count) << Count))
869 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
882 if (Count < 1 || Count >= BitSize)
885 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode ==
ISD::SRA) {
893 if (!refineRxSBGMask(RxSBG,
allOnes(BitSize - Count)))
897 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
907 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, VT);
914 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32,
917 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N);
922 bool SystemZDAGToDAGISel::tryRISBGZero(
SDNode *N) {
927 RxSBGOperands RISBG(SystemZ::RISBG,
SDValue(N, 0));
929 while (expandRxSBG(RISBG))
947 if (RISBG.Rotate == 0) {
948 bool PreferAnd =
false;
954 else if (RISBG.Mask == 0xff ||
955 RISBG.Mask == 0xffff ||
956 RISBG.Mask == 0x7fffffff ||
962 else if (
auto *
Load = dyn_cast<LoadSDNode>(RISBG.Input)) {
966 RISBG.Mask == 0xffffff00 &&
967 Subtarget->hasLoadAndZeroRightmostByte())
974 SDValue In = convertTo(DL, VT, RISBG.Input);
975 SDValue Mask = CurDAG->getConstant(RISBG.Mask, DL, VT);
989 unsigned Opcode = SystemZ::RISBG;
991 if (Subtarget->hasMiscellaneousExtensions())
992 Opcode = SystemZ::RISBGN;
994 if (VT ==
MVT::i32 && Subtarget->hasHighWord()) {
995 Opcode = SystemZ::RISBMux;
1001 getUNDEF(DL, OpcodeVT),
1002 convertTo(DL, OpcodeVT, RISBG.Input),
1003 CurDAG->getTargetConstant(RISBG.Start, DL,
MVT::i32),
1004 CurDAG->getTargetConstant(RISBG.End | 128, DL,
MVT::i32),
1005 CurDAG->getTargetConstant(RISBG.Rotate, DL,
MVT::i32)
1008 DL, VT,
SDValue(CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops), 0));
1009 ReplaceUses(N, New.
getNode());
1010 CurDAG->RemoveDeadNode(N);
1014 bool SystemZDAGToDAGISel::tryRxSBG(
SDNode *N,
unsigned Opcode) {
1021 RxSBGOperands RxSBG[] = {
1025 unsigned Count[] = { 0, 0 };
1026 for (
unsigned I = 0;
I < 2; ++
I)
1027 while (expandRxSBG(RxSBG[
I]))
1036 if (Count[0] == 0 && Count[1] == 0)
1040 unsigned I = Count[0] > Count[1] ? 0 : 1;
1044 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
1045 if (
auto *
Load = dyn_cast<LoadSDNode>(Op0.
getNode()))
1051 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask)) {
1052 Opcode = SystemZ::RISBG;
1054 if (Subtarget->hasMiscellaneousExtensions())
1055 Opcode = SystemZ::RISBGN;
1060 convertTo(DL,
MVT::i64, RxSBG[I].Input),
1061 CurDAG->getTargetConstant(RxSBG[I].Start, DL,
MVT::i32),
1062 CurDAG->getTargetConstant(RxSBG[I].
End, DL,
MVT::i32),
1063 CurDAG->getTargetConstant(RxSBG[I].Rotate, DL,
MVT::i32)
1066 DL, VT,
SDValue(CurDAG->getMachineNode(Opcode, DL,
MVT::i64, Ops), 0));
1067 ReplaceNode(N, New.
getNode());
1071 void SystemZDAGToDAGISel::splitLargeImmediate(
unsigned Opcode,
SDNode *Node,
1072 SDValue Op0, uint64_t UpperVal,
1073 uint64_t LowerVal) {
1078 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
1099 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
1101 ReplaceUses(Node, Or.
getNode());
1102 CurDAG->RemoveDeadNode(Node);
1107 bool SystemZDAGToDAGISel::tryGather(
SDNode *N,
unsigned Opcode) {
1113 unsigned Elem = ElemN->getZExtValue();
1121 if (
Load->getMemoryVT().getSizeInBits() !=
1122 Load->getValueType(0).getSizeInBits())
1126 if (!selectBDVAddr12Only(
Load->getBasePtr(), ElemV, Base, Disp, Index) ||
1133 CurDAG->getTargetConstant(Elem, DL,
MVT::i32),
Load->getChain()
1137 ReplaceNode(N, Res);
1141 bool SystemZDAGToDAGISel::tryScatter(
StoreSDNode *
Store,
unsigned Opcode) {
1155 unsigned Elem = ElemN->getZExtValue();
1160 if (!selectBDVAddr12Only(Store->
getBasePtr(), ElemV, Base, Disp, Index) ||
1166 Vec, Base, Disp, Index, CurDAG->getTargetConstant(Elem, DL,
MVT::i32),
1169 ReplaceNode(Store, CurDAG->getMachineNode(Opcode, DL,
MVT::Other, Ops));
1173 bool SystemZDAGToDAGISel::canUseBlockOperation(
StoreSDNode *Store,
1197 if (V1 == V2 && End1 == End2)
1204 bool SystemZDAGToDAGISel::storeLoadCanUseMVC(
SDNode *N)
const {
1205 auto *Store = cast<StoreSDNode>(
N);
1206 auto *Load = cast<LoadSDNode>(Store->
getValue());
1211 if (Size > 1 && Size <= 8) {
1220 return canUseBlockOperation(Store, Load);
1223 bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(
SDNode *N,
1225 auto *StoreA = cast<StoreSDNode>(
N);
1226 auto *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
1227 auto *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
1228 return !LoadA->isVolatile() && canUseBlockOperation(StoreA, LoadB);
1246 if (tryRxSBG(Node, SystemZ::ROSBG))
1252 if (tryRxSBG(Node, SystemZ::RXSBG))
1259 if (
auto *Op1 = dyn_cast<ConstantSDNode>(Node->
getOperand(1))) {
1260 uint64_t Val = Op1->getZExtValue();
1262 splitLargeImmediate(Opcode, Node, Node->
getOperand(0),
1271 if (tryRxSBG(Node, SystemZ::RNSBG))
1278 if (tryRISBGZero(Node))
1286 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
1301 (Subtarget->hasLoadStoreOnCond2() &&
1304 isInt<16>(cast<ConstantSDNode>(Op1)->getSExtValue()) &&
1306 isInt<16>(cast<ConstantSDNode>(Op0)->getSExtValue())))) {
1309 uint64_t ConstCCValid =
1310 cast<ConstantSDNode>(CCValid.
getNode())->getZExtValue();
1311 uint64_t ConstCCMask =
1312 cast<ConstantSDNode>(CCMask.
getNode())->getZExtValue();
1314 CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
SDLoc(Node),
1317 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
1325 if (ElemBitSize == 32) {
1326 if (tryGather(Node, SystemZ::VGEF))
1328 }
else if (ElemBitSize == 64) {
1329 if (tryGather(Node, SystemZ::VGEG))
1336 auto *Store = cast<StoreSDNode>(Node);
1338 if (ElemBitSize == 32) {
1339 if (tryScatter(Store, SystemZ::VSCEF))
1341 }
else if (ElemBitSize == 64) {
1342 if (tryScatter(Store, SystemZ::VSCEG))
1352 bool SystemZDAGToDAGISel::
1353 SelectInlineAsmMemoryOperand(
const SDValue &Op,
1354 unsigned ConstraintID,
1355 std::vector<SDValue> &OutOps) {
1356 SystemZAddressingMode::AddrForm
Form;
1357 SystemZAddressingMode::DispRange DispRange;
1360 switch(ConstraintID) {
1366 Form = SystemZAddressingMode::FormBD;
1367 DispRange = SystemZAddressingMode::Disp12Only;
1371 Form = SystemZAddressingMode::FormBDXNormal;
1372 DispRange = SystemZAddressingMode::Disp12Only;
1376 Form = SystemZAddressingMode::FormBD;
1377 DispRange = SystemZAddressingMode::Disp20Only;
1383 Form = SystemZAddressingMode::FormBDXNormal;
1384 DispRange = SystemZAddressingMode::Disp20Only;
1388 if (selectBDXAddr(Form, DispRange, Op, Base, Disp, Index)) {
1390 Subtarget->getRegisterInfo()->getPointerRegClass(*MF);
1399 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1407 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1412 OutOps.push_back(Base);
1413 OutOps.push_back(Disp);
1414 OutOps.push_back(Index);
static bool isImmHF(uint64_t Val)
SDValue getValue(unsigned R) const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N)
uint64_t getZExtValue() const
Get zero extended value.
bool hasOneUse() const
Return true if there is exactly one use of this node.
static bool isImmLF(uint64_t Val)
static bool maskMatters(RxSBGOperands &RxSBG, uint64_t Mask)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
unsigned getID() const
Return the register class ID number.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
constexpr bool isInt< 16 >(int64_t x)
const SDValue & getOperand(unsigned Num) const
void setNodeId(int Id)
Set unique node id.
int64_t getSrcValueOffset() const
static uint64_t allOnes(unsigned int Count)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
Shift and rotation operations.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
FunctionPass * createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Simple integer binary arithmetic operators.
static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase, SDValue Value)
const SDValue & getBasePtr() const
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
EVT getMemoryVT() const
Return the type of the in-memory value.
static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index)
This class is used to represent ISD::STORE nodes.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
const SDValue & getOperand(unsigned i) const
static bool expandDisp(SystemZAddressingMode &AM, bool IsBase, SDValue Op0, uint64_t Op1)
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
void RepositionNode(allnodes_iterator Position, SDNode *N)
Move node N in the AllNodes list to be immediately before the given iterator Position.
static const unsigned End
static void changeComponent(SystemZAddressingMode &AM, bool IsBase, SDValue Value)
unsigned getOpcode() const
FunctionPass class - This class is used to implement most global optimizations.
self_iterator getIterator()
bool isPCREL(unsigned Opcode)
const SDValue & getValue() const
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
EVT - Extended Value Type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Representation for a specific memory location.
constexpr bool isInt< 32 >(int64_t x)
void dump() const
Dump this node, for debugging.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const SDValue & getChain() const
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool isDereferenceable() const
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
const Value * getValue() const
Return the base address of the memory access.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
ANY_EXTEND - Used for integer types. The high bits are undefined.
Bitwise operators - logical and, logical or, logical xor.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
int getNodeId() const
Return the unique node id.
EVT getValueType() const
Return the ValueType of the referenced return value.
static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val)
This class is used to form a handle around another node that is persistent and is updated across invo...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool expandIndex(SystemZAddressingMode &AM, SDValue Base, SDValue Index)
LLVM Value Representation.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val)
StringRef - Represent a constant reference to a string, i.e.
TRUNCATE - Completely drop the high bits.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
uint64_t getZExtValue() const
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.