22 #define GET_SUBTARGETINFO_ENUM
23 #include "AMDGPUGenSubtargetInfo.inc"
24 #undef GET_SUBTARGETINFO_ENUM
26 #define GET_REGINFO_ENUM
27 #include "AMDGPUGenRegisterInfo.inc"
28 #undef GET_REGINFO_ENUM
30 #define GET_INSTRINFO_NAMED_OPS
31 #define GET_INSTRINFO_ENUM
32 #include "AMDGPUGenInstrInfo.inc"
33 #undef GET_INSTRINFO_NAMED_OPS
34 #undef GET_INSTRINFO_ENUM
39 unsigned getBitMask(
unsigned Shift,
unsigned Width) {
40 return ((1 << Width) - 1) << Shift;
46 unsigned packBits(
unsigned Src,
unsigned Dst,
unsigned Shift,
unsigned Width) {
47 Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
48 Dst |= (Src << Shift) & getBitMask(Shift, Width);
55 unsigned unpackBits(
unsigned Src,
unsigned Shift,
unsigned Width) {
56 return (Src & getBitMask(Shift, Width)) >> Shift;
60 unsigned getVmcntBitShift() {
return 0; }
63 unsigned getVmcntBitWidth() {
return 4; }
66 unsigned getExpcntBitShift() {
return 4; }
69 unsigned getExpcntBitWidth() {
return 3; }
72 unsigned getLgkmcntBitShift() {
return 8; }
75 unsigned getLgkmcntBitWidth() {
return 4; }
84 if (Features.test(FeatureISAVersion7_0_0))
87 if (Features.test(FeatureISAVersion7_0_1))
90 if (Features.test(FeatureISAVersion7_0_2))
93 if (Features.test(FeatureISAVersion8_0_0))
96 if (Features.test(FeatureISAVersion8_0_1))
99 if (Features.test(FeatureISAVersion8_0_2))
102 if (Features.test(FeatureISAVersion8_0_3))
105 if (Features.test(FeatureISAVersion8_0_4))
108 if (Features.test(FeatureISAVersion8_1_0))
119 memset(&Header, 0,
sizeof(Header));
182 int Result = Default;
188 Ctx.
emitError(
"can't parse integer attribute " + Name);
197 std::pair<int, int> Default,
198 bool OnlyFirstRequired) {
204 std::pair<int, int> Ints = Default;
206 if (Strs.first.trim().getAsInteger(0, Ints.first)) {
207 Ctx.
emitError(
"can't parse first integer attribute " + Name);
210 if (Strs.second.trim().getAsInteger(0, Ints.second)) {
211 if (!OnlyFirstRequired || Strs.second.trim().size()) {
212 Ctx.
emitError(
"can't parse second integer attribute " + Name);
221 unsigned Vmcnt = getBitMask(getVmcntBitShift(), getVmcntBitWidth());
222 unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
223 unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
224 return Vmcnt | Expcnt | Lgkmcnt;
228 return (1 << getVmcntBitWidth()) - 1;
232 return (1 << getExpcntBitWidth()) - 1;
236 return (1 << getLgkmcntBitWidth()) - 1;
240 return unpackBits(Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
244 return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
248 return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
252 unsigned &Vmcnt,
unsigned &Expcnt,
unsigned &Lgkmcnt) {
259 return packBits(Vmcnt, Waitcnt, getVmcntBitShift(), getVmcntBitWidth());
263 return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
267 return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
271 unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt) {
315 case AMDGPU::FLAT_SCR:
317 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
319 case AMDGPU::FLAT_SCR_LO:
321 return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
323 case AMDGPU::FLAT_SCR_HI:
325 return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
361 case AMDGPU::SGPR_32RegClassID:
362 case AMDGPU::VGPR_32RegClassID:
363 case AMDGPU::VS_32RegClassID:
364 case AMDGPU::SReg_32RegClassID:
365 case AMDGPU::SReg_32_XM0RegClassID:
367 case AMDGPU::SGPR_64RegClassID:
368 case AMDGPU::VS_64RegClassID:
369 case AMDGPU::SReg_64RegClassID:
370 case AMDGPU::VReg_64RegClassID:
372 case AMDGPU::VReg_96RegClassID:
374 case AMDGPU::SGPR_128RegClassID:
375 case AMDGPU::SReg_128RegClassID:
376 case AMDGPU::VReg_128RegClassID:
378 case AMDGPU::SReg_256RegClassID:
379 case AMDGPU::VReg_256RegClassID:
381 case AMDGPU::SReg_512RegClassID:
382 case AMDGPU::VReg_512RegClassID:
400 if (Literal >= -16 && Literal <= 64)
403 uint64_t Val =
static_cast<uint64_t
>(Literal);
413 (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
417 if (Literal >= -16 && Literal <= 64)
439 (Val == 0x3e22f983 && HasInv2Pi);
445 if (Literal >= -16 && Literal <= 64)
448 uint16_t Val =
static_cast<uint16_t
>(Literal);
449 return Val == 0x3C00 ||
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
unsigned getExpcntBitMask(IsaVersion Version)
Instances of this class represent a uniqued identifier for a section in the current translation unit...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt)
unsigned getVmcntBitMask(IsaVersion Version)
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
Calling convention used for Mesa vertex shaders.
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
MCSection * getHSATextSection(MCContext &Ctx)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
unsigned getAddressSpace() const
Return the address space of the Pointer type.
MCSection * getHSARodataReadonlyAgentSection(MCContext &Ctx)
Address space for local memory.
unsigned getWaitcntBitMask(IsaVersion Version)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
uint32_t amd_kernel_code_version_major
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
uint16_t amd_machine_version_major
Reg
All possible values of the reg field in the ModR/M byte.
unsigned encodeWaitcnt(IsaVersion Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt)
Context object for machine code objects.
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
uint8_t OperandType
Information about the type of the operand.
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment...
uint8_t group_segment_alignment
bool isGroupSegment(const GlobalValue *GV)
bool isReadOnlySegment(const GlobalValue *GV)
uint16_t amd_machine_version_minor
unsigned getID() const
getID() - Return the register class ID number.
uint32_t amd_kernel_code_version_minor
MCRegisterClass - Base class of TargetRegisterClass.
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
MCSection * getHSADataGlobalAgentSection(MCContext &Ctx)
MCSection * getHSADataGlobalProgramSection(MCContext &Ctx)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool isSI(const MCSubtargetInfo &STI)
unsigned const MachineRegisterInfo * MRI
IsaVersion getIsaVersion(const FeatureBitset &Features)
bool isShader(CallingConv::ID cc)
This is an important class for using LLVM in a threaded context.
Address space for constant memory (VTX2)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isCompute(CallingConv::ID cc)
unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt)
uint8_t private_segment_alignment
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
Calling convention used for Mesa pixel shaders.
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const FeatureBitset &Features)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt)
unsigned getLgkmcntBitMask(IsaVersion Version)
Calling convention used for Mesa geometry shaders.
void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
uint16_t amd_machine_version_stepping
uint8_t wavefront_size
Wavefront size expressed as a power of two.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
uint64_t DoubleToBits(double Double)
DoubleToBits - This function takes a double and returns the bit equivalent 64-bit integer...
unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt)
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt)
bool isCI(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
PointerType * getType() const
Global values are always pointers.
bool isVI(const MCSubtargetInfo &STI)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
MCSubtargetInfo - Generic base class for all target subtargets.
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isStringAttribute() const
Return true if the attribute is a string (target-dependent) attribute.
Calling convention used for Mesa compute shaders.
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel's entry point instru...
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
StringRef getValueAsString() const
Return the attribute's value as a string.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const FeatureBitset Features
const MCOperandInfo * OpInfo
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
uint16_t amd_machine_kind
StringRef - Represent a constant reference to a string, i.e.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
Address space for global memory (RAT0, VTX0).