42 #define DEBUG_TYPE "regalloc"
48 struct CompSpillWeight {
67 std::unique_ptr<Spiller> SpillerInstance;
68 std::priority_queue<LiveInterval*, std::vector<LiveInterval*>,
69 CompSpillWeight>
Queue;
79 StringRef getPassName()
const override {
return "Basic Register Allocator"; }
84 void releaseMemory()
override;
86 Spiller &spiller()
override {
return *SpillerInstance; }
114 bool spillInterferences(
LiveInterval &VirtReg,
unsigned PhysReg,
158 MachineFunctionPass::getAnalysisUsage(AU);
161 void RABasic::releaseMemory() {
162 SpillerInstance.reset();
169 bool RABasic::spillInterferences(
LiveInterval &VirtReg,
unsigned PhysReg,
188 DEBUG(
dbgs() <<
"spilling " << TRI->getName(PhysReg) <<
189 " interferences with " << VirtReg <<
"\n");
193 for (
unsigned i = 0, e = Intfs.
size();
i != e; ++
i) {
197 if (!VRM->hasPhys(Spill.
reg))
205 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM,
nullptr, &DeadRemats);
206 spiller().spill(LRE);
230 while (
unsigned PhysReg = Order.next()) {
232 switch (
Matrix->checkInterference(VirtReg, PhysReg)) {
233 case LiveRegMatrix::IK_Free:
237 case LiveRegMatrix::IK_VirtReg:
250 PhysRegE = PhysRegSpillCands.
end(); PhysRegI != PhysRegE; ++PhysRegI) {
251 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs))
254 assert(!
Matrix->checkInterference(VirtReg, *PhysRegI) &&
255 "Interference after spill.");
261 DEBUG(
dbgs() <<
"spilling: " << VirtReg <<
'\n');
264 LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM,
nullptr, &DeadRemats);
265 spiller().spill(LRE);
273 DEBUG(
dbgs() <<
"********** BASIC REGISTER ALLOCATION **********\n"
274 <<
"********** Function: "
279 getAnalysis<LiveIntervals>(),
280 getAnalysis<LiveRegMatrix>());
283 getAnalysis<MachineLoopInfo>(),
284 getAnalysis<MachineBlockFrequencyInfo>());
292 DEBUG(
dbgs() <<
"Post alloc VirtRegMap:\n" << *VRM <<
"\n");
300 return new RABasic();
void push_back(const T &Elt)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
void initializeLiveDebugVariablesPass(PassRegistry &)
bool isSpillable() const
isSpillable - Can this interval be spilled?
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
void initializeMachineLoopInfoPass(PassRegistry &)
void initializeRegisterCoalescerPass(PassRegistry &)
AnalysisUsage & addRequired()
Query interferences between a single live virtual register and a live interval union.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static RegisterRegAlloc basicRegAlloc("basic","basic register allocator", createBasicRegisterAllocator)
RegAllocBase provides the register allocation driver and interface that can be extended to add intere...
LLVM_NODISCARD bool empty() const
const SmallVectorImpl< LiveInterval * > & interferingVRegs() const
AnalysisUsage & addPreservedID(const void *ID)
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
RegisterRegAlloc class - Track the registration of register allocators.
void initializeMachineDominatorTreePass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
void initializeSlotIndexesPass(PassRegistry &)
void initializeLiveStacksPass(PassRegistry &)
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Represent the analysis usage information of a pass.
void initializeLiveIntervalsPass(PassRegistry &)
FunctionPass class - This class is used to implement most global optimizations.
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, VirtRegMap *VRM, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
AnalysisUsage & addRequiredID(const void *ID)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
void setPreservesCFG()
This function should be called by the pass, iff they do not:
bool seenUnspillableVReg() const
void initializeMachineSchedulerPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineFunctionProperties & set(Property P)
void initializeVirtRegMapPass(PassRegistry &)
Spiller * createInlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
Create and return a spiller that will insert spill code directly instead of deferring though VirtRegM...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
void initializeLiveRegMatrixPass(PassRegistry &)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
unsigned collectInterferingVRegs(unsigned MaxInterferingRegs=UINT_MAX)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef - Represent a constant reference to a string, i.e.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
Properties which a MachineFunction may have at a given point in time.