16 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
17 #define LLVM_CODEGEN_SCHEDULEDAG_H
29 class MachineConstantPool;
30 class MachineFunction;
31 class MachineRegisterInfo;
33 struct MCSchedClassDesc;
34 class TargetRegisterInfo;
37 class TargetInstrInfo;
40 class TargetRegisterClass;
102 : Dep(S, kind), Contents() {
109 "SDep::Anti and SDep::Output must use a non-zero Reg!");
120 : Dep(S,
Order), Contents(), Latency(0) {
121 Contents.OrdKind = kind;
128 return overlaps(Other) && Latency == Other.Latency;
220 "getReg called on non-register dependence edge!");
231 "setReg called on non-register dependence edge!");
233 "SDep::Anti edge cannot use the zero register!");
235 "SDep::Output edge cannot use the zero register!");
246 enum :
unsigned { BoundaryID = ~0u };
295 bool isDepthCurrent : 1;
296 bool isHeightCurrent : 1;
365 assert(!Instr &&
"Setting SDNode of SUnit with MachineInstr!");
372 assert(!Instr &&
"Reading SDNode of SUnit with MachineInstr!");
383 assert(!Node &&
"Setting MachineInstr of SUnit with SDNode!");
390 assert(!Node &&
"Reading MachineInstr of SUnit with SDNode!");
404 unsigned TrueMemOrderLatency =
419 const_cast<SUnit *
>(
this)->ComputeDepth();
426 if (!isHeightCurrent)
427 const_cast<SUnit *
>(
this)->ComputeHeight();
453 for (
unsigned i = 0, e = (
unsigned)
Preds.size();
i != e; ++
i)
461 for (
unsigned i = 0, e = (
unsigned)
Succs.size();
i != e; ++
i)
484 void ComputeHeight();
489 if (Dep != Other.Dep)
491 switch (Dep.getInt()) {
495 return Contents.Reg == Other.Contents.
Reg;
497 return Contents.OrdKind == Other.Contents.
OrdKind;
520 virtual void anchor();
525 CurCycle(0), HasReadyFilter(rf) {}
530 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
535 virtual bool empty()
const = 0;
542 assert(!HasReadyFilter &&
"The ready filter must override isReady()");
548 for (std::vector<SUnit *>::const_iterator
I = Nodes.begin(),
549 E = Nodes.end();
I !=
E; ++
I)
555 virtual void remove(
SUnit *SU) = 0;
604 return getNodeDesc(SU->
getNode());
645 return Operand == x.Operand;
650 return Node->
Preds[Operand].getSUnit();
677 return Node->
Preds[Operand];
696 return nodes_iterator(G->
SUnits.begin());
699 return nodes_iterator(G->
SUnits.end());
711 std::vector<SUnit> &SUnits;
715 std::vector<int> Index2Node;
717 std::vector<int> Node2Index;
724 void DFS(
const SUnit *SU,
int UpperBound,
bool& HasLoop);
728 void Shift(
BitVector& Visited,
int LowerBound,
int UpperBound);
731 void Allocate(
int n,
int index);
static nodes_iterator nodes_begin(ScheduleDAG *G)
Weak DAG edge linking a chain of clustered instrs.
bool isCtrl() const
isCtrl - Shorthand for getKind() != SDep::Data.
std::vector< int >::const_reverse_iterator const_reverse_iterator
std::vector< int >::reverse_iterator reverse_iterator
virtual void initNodes(std::vector< SUnit > &SUnits)=0
bool isArtificialDep() const
unsigned OrdKind
Order - Additional information about Order dependencies.
bool isSucc(SUnit *N)
isSucc - Test if node N is a successor of this node.
void setNode(SDNode *N)
setNode - Assign the representative SDNode for this SUnit.
virtual void updateNode(const SUnit *SU)=0
void print(raw_ostream &O, const ScheduleDAG *G) const
const_iterator end() const
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
virtual void push(SUnit *U)=0
bool isInstr() const
isInstr - Return true if this SUnit refers to a machine instruction as opposed to an SDNode...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool operator!=(const SUnitIterator &x) const
virtual std::string getGraphNodeLabel(const SUnit *SU) const =0
getGraphNodeLabel - Return a label for an SUnit node in a visualization of the ScheduleDAG.
std::vector< int >::iterator iterator
void removePred(const SDep &D)
removePred - This removes the specified edge as a pred of the current node if it exists.
Kind
Kind - These are the different kinds of scheduling dependencies.
bool overlaps(const SDep &Other) const
Return true if the specified SDep is equivalent except for latency.
bool isAssignedRegDep() const
isAssignedRegDep - Test if this is a Data dependence that is associated with a register.
static NodeRef getEntryNode(SUnit *N)
SmallVectorImpl< SDep >::iterator succ_iterator
const TargetRegisterClass * CopyDstRC
SUnit()
SUnit - Construct a placeholder SUnit.
bool isArtificial() const
isArtificial - Test if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness.
SmallVector< SDep, 4 > Preds
virtual void viewGraph()
Out-of-line implementation with no arguments is handy for gdb.
A register anti-dependedence (aka WAR).
void dumpAll(const ScheduleDAG *G) const
SchedulingPriorityQueue - This interface is used to plug different priorities computation algorithms ...
unsigned getHeight() const
getHeight - Return the height of this node, which is the length of the maximum path down to any node ...
const SUnit * getNode() const
SmallVectorImpl< SDep >::iterator pred_iterator
virtual void unscheduledNode(SUnit *)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
bool isWeak() const
isWeak - Test if this a weak dependence.
virtual void releaseState()=0
Kind getKind() const
getKind - Return an enum value representing the kind of the dependence.
void setInstr(MachineInstr *MI)
setInstr - Assign the instruction for the SUnit.
SmallVectorImpl< SDep >::const_iterator const_pred_iterator
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
Regular data dependence (aka true-dependence).
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
unsigned getCurCycle() const
unsigned Reg
Reg - For Data, Anti, and Output dependencies, the associated register.
virtual std::string getDAGName() const =0
getDAGLabel - Return a label for the region of code covered by the DAG.
void setCurCycle(unsigned Cycle)
void InitDAGTopologicalSorting()
InitDAGTopologicalSorting - create the initial topological ordering from the DAG to be scheduled...
SchedulingPriorityQueue(bool rf=false)
SDep()
SDep - Construct a null SDep.
pointer operator*() const
A register output-dependence (aka WAW).
bool isMustAlias() const
isMustAlias - Test if this is an Order dependence that is marked as "must alias", meaning that the SU...
Function Alias Analysis false
bool isPred(SUnit *N)
isPred - Test if node N is a predecessor of this node.
virtual bool isReady(SUnit *) const
bool isNormalMemory() const
isNormalMemory - Test if this is an Order dependence between two memory accesses where both sides of ...
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
TargetInstrInfo - Interface to description of machine instruction set.
bool operator==(const SDep &Other) const
void setDepthToAtLeast(unsigned NewDepth)
setDepthToAtLeast - If NewDepth is greater than this node's depth value, set it to be the new depth v...
SDep - Scheduling dependency.
bool operator==(const SUnitIterator &x) const
void setHeightToAtLeast(unsigned NewHeight)
setDepthToAtLeast - If NewDepth is greater than this node's depth value, set it to be the new height ...
virtual void dump(ScheduleDAG *) const
void setDepthDirty()
setDepthDirty - Set a flag in this node to indicate that its stored Depth value will require recomput...
reverse_iterator rbegin()
bool WillCreateCycle(SUnit *TargetSU, SUnit *SU)
WillCreateCycle - Return true if addPred(TargetSU, SU) creates a cycle.
void clearDAG()
clearDAG - clear the DAG state (between regions).
PointerIntPair - This class implements a pair of a pointer and small integer.
SDNode * getNode() const
getNode - Return the representative SDNode for this SUnit.
virtual void addCustomGraphFeatures(GraphWriter< ScheduleDAG * > &) const
addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG.
virtual void addNode(const SUnit *SU)=0
virtual bool empty() const =0
pointer operator->() const
Summarize the scheduling resources required for an instruction of a particular scheduling class...
static SUnitIterator begin(SUnit *N)
unsigned getLatency() const
getLatency - Return the latency value for this edge, which roughly means the minimum number of cycles...
static ChildIteratorType child_begin(NodeRef N)
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
SUnitIterator operator++(int)
const MCSchedClassDesc * SchedClass
void RemovePred(SUnit *M, SUnit *N)
RemovePred - Updates the topological ordering to accommodate an an edge to be removed from the specif...
void push_all(const std::vector< SUnit * > &Nodes)
Sched::Preference SchedulingPref
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Any other ordering dependency.
static SUnitIterator end(SUnit *N)
const SDep & getSDep() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
pointer_iterator< std::vector< SUnit >::iterator > nodes_iterator
const_reverse_iterator rbegin() const
SUnitIterator ChildIteratorType
SUnitIterator & operator++()
SDep(SUnit *S, OrderKind kind)
An unknown scheduling barrier.
isPodLike - This is a type trait that is used to determine whether a given type can be copied around ...
virtual bool isBottomUp() const =0
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isCtrlDep() const
isCtrlDep - Test if this is not an SDep::Data dependence.
Nonvolatile load/Store instructions that may alias.
Represents one node in the SelectionDAG.
const TargetRegisterClass * CopySrcRC
bool addPredBarrier(SUnit *SU)
addPredBarrier - This adds a barrier edge to SU by calling addPred(), with latency 0 generally or lat...
void setReg(unsigned Reg)
setReg - Assign the associated register for this edge.
std::vector< int >::const_iterator const_iterator
bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
IsReachable - Checks if SU is reachable from TargetSU.
void biasCriticalPath()
Order this node's predecessor edges such that the critical path edge occurs first.
virtual void scheduledNode(SUnit *)
scheduledNode - As each node is scheduled, this method is invoked.
ScheduleDAG(MachineFunction &mf)
SmallVectorImpl< SDep >::const_iterator const_succ_iterator
static ChildIteratorType child_end(NodeRef N)
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
unsigned getDepth() const
getDepth - Return the depth of this node, which is the length of the maximum path up to any node whic...
void setLatency(unsigned Lat)
setLatency - Set the latency for this edge.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isCluster() const
isCluster - Test if this is an Order dependence that is marked as "cluster", meaning it is artificial...
unsigned VerifyScheduledDAG(bool isBottomUp)
VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent...
Representation of each machine instruction.
unsigned getOperand() const
const TargetRegisterInfo * TRI
SUnit(SDNode *node, unsigned nodenum)
SUnit - Construct an SUnit for pre-regalloc scheduling to represent an SDNode and any nodes flagged t...
bool operator!=(const SDep &Other) const
bool hasReadyFilter() const
unsigned short NumRegDefsLeft
virtual ~SchedulingPriorityQueue()
const TargetInstrInfo * TII
virtual bool tracksRegPressure() const
void setHeightDirty()
setHeightDirty - Set a flag in this node to indicate that its stored Height value will require recomp...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const_iterator begin() const
virtual void dumpNode(const SUnit *SU) const =0
bool isNormalMemoryOrBarrier() const
isNormalMemoryOrBarrier - Test if this is could be any kind of memory dependence. ...
bool addPred(const SDep &D, bool Required=true)
addPred - This adds the specified edge as a pred of the current node if not already.
SUnit(MachineInstr *instr, unsigned nodenum)
SUnit - Construct an SUnit for post-regalloc scheduling to represent a MachineInstr.
SmallVector< SDep, 4 > Succs
bool isBottomReady() const
Arbitrary strong DAG edge (no real dependence).
This class implements an extremely fast bulk output stream that can only output to a stream...
Primary interface to the complete machine description for the target machine.
void AddPred(SUnit *Y, SUnit *X)
AddPred - Updates the topological ordering to accommodate an edge to be added from SUnit X to SUnit Y...
static nodes_iterator nodes_end(ScheduleDAG *G)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
const MCInstrDesc * getInstrDesc(const SUnit *SU) const
getInstrDesc - Return the MCInstrDesc of this SUnit.
MachineRegisterInfo & MRI
std::vector< SUnit > SUnits
unsigned getReg() const
getReg - Return the register associated with this edge.
ScheduleDAGTopologicalSort is a class that computes a topological ordering for SUnits and provides me...
SDep(SUnit *S, Kind kind, unsigned Reg)
SDep - Construct an SDep with the specified values.
const_reverse_iterator rend() const
ScheduleDAGTopologicalSort(std::vector< SUnit > &SUnits, SUnit *ExitSU)
void dump(const ScheduleDAG *G) const
SUnit - Scheduling unit.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Nonvolatile load/Store instructions that must alias.
This file describes how to lower LLVM code to machine code.
bool isBarrier() const
isBarrier - Test if this is an Order dependence that is marked as a barrier.