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LLVM
4.0.0
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#include "ARM.h"#include "ARMBaseInstrInfo.h"#include "ARMBaseRegisterInfo.h"#include "ARMISelLowering.h"#include "ARMMachineFunctionInfo.h"#include "ARMSubtarget.h"#include "MCTargetDesc/ARMAddressingModes.h"#include "ThumbRegisterInfo.h"#include "llvm/ADT/DenseMap.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/SmallPtrSet.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/RegisterClassInfo.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/CodeGen/LivePhysRegs.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/Support/Allocator.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetInstrInfo.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetRegisterInfo.h"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "arm-ldst-opt" |
| #define | ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass" |
| #define | ARM_PREALLOC_LOAD_STORE_OPT_NAME "ARM pre- register allocation load / store optimization pass" |
Functions | |
| STATISTIC (NumLDMGened,"Number of ldm instructions generated") | |
| STATISTIC (NumSTMGened,"Number of stm instructions generated") | |
| STATISTIC (NumVLDMGened,"Number of vldm instructions generated") | |
| STATISTIC (NumVSTMGened,"Number of vstm instructions generated") | |
| STATISTIC (NumLdStMoved,"Number of load / store instructions moved") | |
| STATISTIC (NumLDRDFormed,"Number of ldrd created before allocation") | |
| STATISTIC (NumSTRDFormed,"Number of strd created before allocation") | |
| STATISTIC (NumLDRD2LDM,"Number of ldrd instructions turned back into ldm") | |
| STATISTIC (NumSTRD2STM,"Number of strd instructions turned back into stm") | |
| STATISTIC (NumLDRD2LDR,"Number of ldrd instructions turned back into ldr's") | |
| STATISTIC (NumSTRD2STR,"Number of strd instructions turned back into str's") | |
| INITIALIZE_PASS (ARMLoadStoreOpt,"arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false, false) static bool definesCPSR(const MachineInstr &MI) | |
| static int | getMemoryOpOffset (const MachineInstr &MI) |
| static const MachineOperand & | getLoadStoreBaseOp (const MachineInstr &MI) |
| static const MachineOperand & | getLoadStoreRegOp (const MachineInstr &MI) |
| static int | getLoadStoreMultipleOpcode (unsigned Opcode, ARM_AM::AMSubMode Mode) |
| static ARM_AM::AMSubMode | getLoadStoreMultipleSubMode (unsigned Opcode) |
| static bool | isT1i32Load (unsigned Opc) |
| static bool | isT2i32Load (unsigned Opc) |
| static bool | isi32Load (unsigned Opc) |
| static bool | isT1i32Store (unsigned Opc) |
| static bool | isT2i32Store (unsigned Opc) |
| static bool | isi32Store (unsigned Opc) |
| static bool | isLoadSingle (unsigned Opc) |
| static unsigned | getImmScale (unsigned Opc) |
| static unsigned | getLSMultipleTransferSize (const MachineInstr *MI) |
| static bool | ContainsReg (const ArrayRef< std::pair< unsigned, bool >> &Regs, unsigned Reg) |
| static bool | isValidLSDoubleOffset (int Offset) |
| static bool | mayCombineMisaligned (const TargetSubtargetInfo &STI, const MachineInstr &MI) |
| Return true for loads/stores that can be combined to a double/multi operation without increasing the requirements for alignment. More... | |
| static unsigned | getUpdatingLSMultipleOpcode (unsigned Opc, ARM_AM::AMSubMode Mode) |
| static int | isIncrementOrDecrement (const MachineInstr &MI, unsigned Reg, ARMCC::CondCodes Pred, unsigned PredReg) |
| Check if the given instruction increments or decrements a register and return the amount it is incremented/decremented. More... | |
| static MachineBasicBlock::iterator | findIncDecBefore (MachineBasicBlock::iterator MBBI, unsigned Reg, ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) |
Searches for an increment or decrement of Reg before MBBI. More... | |
| static MachineBasicBlock::iterator | findIncDecAfter (MachineBasicBlock::iterator MBBI, unsigned Reg, ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) |
Searches for a increment or decrement of Reg after MBBI. More... | |
| static unsigned | getPreIndexedLoadStoreOpcode (unsigned Opc, ARM_AM::AddrOpc Mode) |
| static unsigned | getPostIndexedLoadStoreOpcode (unsigned Opc, ARM_AM::AddrOpc Mode) |
| static bool | isMemoryOp (const MachineInstr &MI) |
| Returns true if instruction is a memory operation that this pass is capable of operating on. More... | |
| static void | InsertLDR_STR (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, const DebugLoc &DL, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) |
| INITIALIZE_PASS (ARMPreAllocLoadStoreOpt,"arm-prera-ldst-opt", ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) bool ARMPreAllocLoadStoreOpt | |
| static bool | IsSafeAndProfitableToMove (bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSetImpl< MachineInstr * > &MemOps, SmallSet< unsigned, 4 > &MemRegs, const TargetRegisterInfo *TRI) |
Variables | |
| static cl::opt< bool > | AssumeMisalignedLoadStores ("arm-assume-misaligned-load-store", cl::Hidden, cl::init(false), cl::desc("Be more conservative in ARM load/store opt")) |
| This switch disables formation of double/multi instructions that could potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP disabled. More... | |
| #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass" |
Definition at line 72 of file ARMLoadStoreOptimizer.cpp.
| #define ARM_PREALLOC_LOAD_STORE_OPT_NAME "ARM pre- register allocation load / store optimization pass" |
Definition at line 1935 of file ARMLoadStoreOptimizer.cpp.
| #define DEBUG_TYPE "arm-ldst-opt" |
Definition at line 49 of file ARMLoadStoreOptimizer.cpp.
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Definition at line 575 of file ARMLoadStoreOptimizer.cpp.
References Regs.
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Searches for a increment or decrement of Reg after MBBI.
Definition at line 1169 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineBasicBlock::end(), and isIncrementOrDecrement().
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Searches for an increment or decrement of Reg before MBBI.
Definition at line 1149 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), and isIncrementOrDecrement().
Definition at line 386 of file ARMLoadStoreOptimizer.cpp.
References llvm_unreachable.
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Definition at line 211 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineInstr::getOperand().
Referenced by mayCombineMisaligned().
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Definition at line 219 of file ARMLoadStoreOptimizer.cpp.
References llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::ARM_AM::ia, llvm::ARM_AM::ib, and llvm_unreachable.
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Definition at line 304 of file ARMLoadStoreOptimizer.cpp.
References llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::ARM_AM::ia, llvm::ARM_AM::ib, and llvm_unreachable.
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Definition at line 215 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineInstr::getOperand().
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Definition at line 403 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), and llvm::MachineInstr::getOpcode().
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Definition at line 183 of file ARMLoadStoreOptimizer.cpp.
References llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::ARM_AM::getAM5Offset(), llvm::ARM_AM::getAM5Op(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), Offset, and llvm::ARM_AM::sub.
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Definition at line 1296 of file ARMLoadStoreOptimizer.cpp.
References llvm::ARM_AM::add, and llvm_unreachable.
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Definition at line 1271 of file ARMLoadStoreOptimizer.cpp.
References llvm::ARM_AM::add, and llvm_unreachable.
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Definition at line 1049 of file ARMLoadStoreOptimizer.cpp.
References llvm::ARM_AM::da, llvm::ARM_AM::db, llvm::ARM_AM::ia, llvm::ARM_AM::ib, and llvm_unreachable.
| INITIALIZE_PASS | ( | ARMLoadStoreOpt | , |
| "arm-ldst-opt" | , | ||
| ARM_LOAD_STORE_OPT_NAME | , | ||
| false | , | ||
| false | |||
| ) | const |
Definition at line 167 of file ARMLoadStoreOptimizer.cpp.
| INITIALIZE_PASS | ( | ARMPreAllocLoadStoreOpt | , |
| "arm-prera-ldst-opt" | , | ||
| ARM_PREALLOC_LOAD_STORE_OPT_NAME | , | ||
| false | , | ||
| false | |||
| ) |
Definition at line 1974 of file ARMLoadStoreOptimizer.cpp.
References AssumeMisalignedLoadStores, and MRI.
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Definition at line 1542 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MCInstrInfo::get(), llvm::getDeadRegState(), llvm::getDefRegState(), llvm::getKillRegState(), and llvm::getUndefRegState().
Definition at line 366 of file ARMLoadStoreOptimizer.cpp.
References isT1i32Load(), and isT2i32Load().
Referenced by isLoadSingle(), and mayCombineMisaligned().
Definition at line 378 of file ARMLoadStoreOptimizer.cpp.
References isT1i32Store(), and isT2i32Store().
Referenced by mayCombineMisaligned().
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Check if the given instruction increments or decrements a register and return the amount it is incremented/decremented.
Returns 0 if the CPSR flags generated by the instruction are possibly read as well.
Definition at line 1119 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineOperand::getImm(), llvm::getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
Referenced by findIncDecAfter(), and findIncDecBefore().
Definition at line 382 of file ARMLoadStoreOptimizer.cpp.
References isi32Load().
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Returns true if instruction is a memory operation that this pass is capable of operating on.
Definition at line 1489 of file ARMLoadStoreOptimizer.cpp.
References llvm::MachineMemOperand::getAlignment(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineMemOperand::isVolatile(), and llvm::MachineInstr::memoperands_begin().
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Definition at line 1995 of file ARMLoadStoreOptimizer.cpp.
References llvm::SmallSet< T, N, C >::count(), llvm::SmallPtrSetImpl< PtrType >::count(), llvm::MachineOperand::getReg(), llvm::SmallSet< T, N, C >::insert(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::regsOverlap(), and llvm::SmallSet< T, N, C >::size().
Definition at line 358 of file ARMLoadStoreOptimizer.cpp.
Referenced by isi32Load().
Definition at line 370 of file ARMLoadStoreOptimizer.cpp.
Referenced by isi32Store().
Definition at line 362 of file ARMLoadStoreOptimizer.cpp.
Referenced by isi32Load().
Definition at line 374 of file ARMLoadStoreOptimizer.cpp.
Referenced by isi32Store().
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Definition at line 923 of file ARMLoadStoreOptimizer.cpp.
References llvm::abs().
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Return true for loads/stores that can be combined to a double/multi operation without increasing the requirements for alignment.
Definition at line 932 of file ARMLoadStoreOptimizer.cpp.
References llvm::TargetSubtargetInfo::getFrameLowering(), getLoadStoreBaseOp(), llvm::MachineInstr::getOpcode(), getReg(), llvm::TargetFrameLowering::getTransientStackAlignment(), isi32Load(), and isi32Store().
| STATISTIC | ( | NumLDMGened | , |
| "Number of ldm instructions generated" | |||
| ) |
| STATISTIC | ( | NumSTMGened | , |
| "Number of stm instructions generated" | |||
| ) |
| STATISTIC | ( | NumVLDMGened | , |
| "Number of vldm instructions generated" | |||
| ) |
| STATISTIC | ( | NumVSTMGened | , |
| "Number of vstm instructions generated" | |||
| ) |
| STATISTIC | ( | NumLdStMoved | , |
| "Number of load / store instructions moved" | |||
| ) |
| STATISTIC | ( | NumLDRDFormed | , |
| "Number of ldrd created before allocation" | |||
| ) |
| STATISTIC | ( | NumSTRDFormed | , |
| "Number of strd created before allocation" | |||
| ) |
| STATISTIC | ( | NumLDRD2LDM | , |
| "Number of ldrd instructions turned back into ldm" | |||
| ) |
| STATISTIC | ( | NumSTRD2STM | , |
| "Number of strd instructions turned back into stm" | |||
| ) |
| STATISTIC | ( | NumLDRD2LDR | , |
| "Number of ldrd instructions turned back into ldr's" | |||
| ) |
| STATISTIC | ( | NumSTRD2STR | , |
| "Number of strd instructions turned back into str's" | |||
| ) |
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This switch disables formation of double/multi instructions that could potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP disabled.
This can be used to create libraries that are robust even when users provoke undefined behaviour by supplying misaligned pointers.
Referenced by INITIALIZE_PASS().
1.8.6