29 #define DEBUG_TYPE "mccodeemitter"
41 : MCII(mcii),
MRI(mri), IsLittleEndian(IsLittleEndian) {}
42 BPFMCCodeEmitter(
const BPFMCCodeEmitter &) =
delete;
43 void operator=(
const BPFMCCodeEmitter &) =
delete;
44 ~BPFMCCodeEmitter()
override =
default;
48 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
58 uint64_t getMemoryOpValue(
const MCInst &MI,
unsigned Op,
67 uint64_t computeAvailableFeatures(
const FeatureBitset &FB)
const;
68 void verifyInstructionPredicates(
const MCInst &MI,
69 uint64_t AvailableFeatures)
const;
77 return new BPFMCCodeEmitter(MCII, MRI,
true);
83 return new BPFMCCodeEmitter(MCII, MRI,
false);
86 unsigned BPFMCCodeEmitter::getMachineOpValue(
const MCInst &
MI,
93 return static_cast<unsigned>(MO.
getImm());
104 else if (MI.
getOpcode() == BPF::LD_imm64)
115 return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
121 verifyInstructionPredicates(MI,
128 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
129 uint64_t
Value = getBinaryCodeForInstr(MI, Fixups, STI);
130 LE.write<uint8_t>(Value >> 56);
132 LE.write<uint8_t>((Value >> 48) & 0xff);
134 LE.write<uint8_t>(
SwapBits((Value >> 48) & 0xff));
135 LE.write<uint16_t>(0);
139 BE.write<
uint32_t>(Value & 0xffffFFFF);
142 uint64_t Imm = MO.
isImm() ? MO.getImm() : 0;
143 LE.write<uint8_t>(0);
144 LE.write<uint8_t>(0);
145 LE.write<uint16_t>(0);
152 uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
153 LE.write<uint8_t>(Value >> 56);
154 if (IsLittleEndian) {
155 LE.write<uint8_t>((Value >> 48) & 0xff);
156 LE.write<uint16_t>((Value >> 32) & 0xffff);
159 LE.write<uint8_t>(
SwapBits((Value >> 48) & 0xff));
160 BE.write<uint16_t>((Value >> 32) & 0xffff);
161 BE.write<
uint32_t>(Value & 0xffffFFFF);
167 uint64_t BPFMCCodeEmitter::getMemoryOpValue(
const MCInst &MI,
unsigned Op,
172 assert(Op1.
isReg() &&
"First operand is not register.");
173 Encoding =
MRI.getEncodingValue(Op1.
getReg());
176 assert(Op2.
isImm() &&
"Second operand is not immediate.");
177 Encoding |= Op2.
getImm() & 0xffff;
181 #define ENABLE_INSTR_PREDICATE_VERIFIER
182 #include "BPFGenMCCodeEmitter.inc"
void push_back(const T &Elt)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
A four-byte section relative fixup.
Context object for machine code objects.
MCCodeEmitter * createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
static uint8_t SwapBits(uint8_t Val)
A two-byte pc relative fixup.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
A eight-byte section relative fixup.
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
MCCodeEmitter * createBPFMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const