34 #define DEBUG_TYPE "packets"
38 cl::desc(
"Disable Hexagon packetizer pass"));
42 cl::desc(
"Allow non-solo packetization of volatile memory references"));
49 cl::desc(
"Disable vector double new-value-stores"));
77 StringRef getPassName()
const override {
return "Hexagon Packetizer"; }
108 addMutation(make_unique<HexagonSubtarget::HexagonDAGMutation>());
115 for (
auto &MO : FirstI.
operands()) {
116 if (!MO.isReg() || !MO.isDef())
118 unsigned R = MO.getReg();
132 InsertPt = std::next(BundleIt).getInstrIterator();
153 for (++I; I != E && I->isBundledWithPred(); ++
I)
166 BundleIt->eraseFromParent();
177 auto &MLI = getAnalysis<MachineLoopInfo>();
178 auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
179 auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
182 HII->genAllInsnTimingClasses(MF);
200 for (
auto &MB : MF) {
202 auto MI = MB.begin();
204 auto NextI = std::next(
MI);
214 for (
auto &MB : MF) {
215 auto Begin = MB.begin(),
End = MB.end();
216 while (Begin !=
End) {
220 while (RB !=
End && HII->isSchedulingBoundary(*RB, &MB, MF))
225 while (RE !=
End && !HII->isSchedulingBoundary(*RE, &MB, MF))
257 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext),
DebugLoc());
259 if (Reserve && Avail)
261 MF.DeleteMachineInstr(ExtMI);
278 if (RC == &Hexagon::PredRegsRegClass)
292 if (MO.
getReg() == DepReg)
304 return MI.
getOpcode() == Hexagon::J2_jump;
309 case Hexagon::Y2_barrier:
336 if (NewRC == &Hexagon::PredRegsRegClass)
351 MI.
setDesc(HII->get(CurOpcode));
358 DEBUG(
dbgs() <<
"Cleanup packet has "; BI->dump(););
359 if (BI->getOpcode() == Hexagon::V6_vL32b_cur_ai) {
364 for (
auto &MO : BI->operands())
372 MI->
setDesc(HII->get(Hexagon::V6_vL32b_ai));
397 DEBUG(
dbgs() <<
"Can we DOT Cur Vector MI\n";
399 dbgs() <<
"in packet\n";);
402 dbgs() <<
"Checking CUR against ";
406 bool FoundMatch =
false;
407 for (
auto &MO : MJ.operands())
408 if (MO.isReg() && MO.getReg() == DestReg)
416 DEBUG(
dbgs() <<
"packet has "; BI->dump(););
417 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
434 if (RC == &Hexagon::PredRegsRegClass)
438 MI.
setDesc(HII->get(NewOpcode));
444 MI.
setDesc(HII->get(NewOpcode));
451 case Hexagon::S2_storerd_io:
452 case Hexagon::S2_storeri_io:
453 case Hexagon::S2_storerh_io:
454 case Hexagon::S2_storerb_io:
459 unsigned FrameSize = MF.getFrameInfo().getStackSize();
472 case Hexagon::S2_storerd_io:
473 case Hexagon::S2_storeri_io:
474 case Hexagon::S2_storerh_io:
475 case Hexagon::S2_storerb_io:
480 unsigned FrameSize = MF.getFrameInfo().getStackSize();
511 if (MO.isReg() && MO.isDef())
512 DefRegsSet.
insert(MO.getReg());
515 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
521 assert(Op1.
isReg() &&
"Post increment operand has be to a register.");
527 assert(Op0.
isReg() &&
"Post increment operand has be to a register.");
532 llvm_unreachable(
"mayLoad or mayStore not set for Post Increment operation");
544 case Hexagon::L4_loadrd_ap:
545 case Hexagon::L4_loadrb_ap:
546 case Hexagon::L4_loadrh_ap:
547 case Hexagon::L4_loadrub_ap:
548 case Hexagon::L4_loadruh_ap:
549 case Hexagon::L4_loadri_ap:
594 if (PacketRC == &Hexagon::DoubleRegsRegClass)
633 unsigned predRegNumSrc = 0;
634 unsigned predRegNumDst = 0;
638 for (
auto &MO : PacketMI.
operands()) {
641 predRegNumSrc = MO.getReg();
642 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
643 if (predRegClass == &Hexagon::PredRegsRegClass)
646 assert((predRegClass == &Hexagon::PredRegsRegClass) &&
647 "predicate register not found in a predicated PacketMI instruction");
653 predRegNumDst = MO.getReg();
654 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
655 if (predRegClass == &Hexagon::PredRegsRegClass)
658 assert((predRegClass == &Hexagon::PredRegsRegClass) &&
659 "predicate register not found in a predicated MI instruction");
669 if (predRegNumDst != predRegNumSrc ||
683 unsigned StartCheck = 0;
685 for (
auto I : CurrentPacketMIs) {
692 if (&TempMI != &PacketMI && !StartCheck)
696 if (&TempMI == &PacketMI)
711 for (
unsigned opNum = 0; opNum < MI.
getNumOperands()-1; opNum++) {
722 for (
auto &MO : PacketMI.
operands()) {
723 if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
726 if (R == DepReg || HRI->isSuperRegister(DepReg, R))
736 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
746 const SUnit *PacketSU,
unsigned DepReg,
763 if (MO.isReg() && MO.isDef() && (MO.getReg() == DepReg) && MO.isImplicit())
805 if (RC == &Hexagon::PredRegsRegClass)
809 if (RC != &Hexagon::PredRegsRegClass && !HII->
mayBeNewStore(MI))
818 MF.DeleteMachineInstr(NewMI);
819 if (!ResourcesAvailable)
857 if (PacketSU->
isSucc(PacketSUDep)) {
858 for (
unsigned i = 0;
i < PacketSU->
Succs.size(); ++
i) {
859 auto &Dep = PacketSU->
Succs[
i];
860 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() ==
SDep::Anti &&
861 Dep.getReg() == DepReg)
879 if (
Op.isReg() &&
Op.getReg() &&
Op.isUse() &&
880 Hexagon::PredRegsRegClass.contains(
Op.getReg()))
922 if (PacketSU->
isSucc(SU)) {
923 for (
unsigned i = 0;
i < PacketSU->
Succs.size(); ++
i) {
924 auto Dep = PacketSU->
Succs[
i];
929 if (Dep.getSUnit() == SU && Dep.getKind() ==
SDep::Data &&
930 Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
949 return PReg1 == PReg2 &&
950 Hexagon::PredRegsRegClass.contains(PReg1) &&
951 Hexagon::PredRegsRegClass.contains(PReg2) &&
959 PromotedToDotNew =
false;
960 GlueToNewValueJump =
false;
961 GlueAllocframeStore =
false;
962 FoundSequentialDependence =
false;
985 unsigned FuncUnits = IS->
getUnits();
1040 case (Hexagon::S2_storew_locked):
1041 case (Hexagon::S4_stored_locked):
1042 case (Hexagon::L2_loadw_locked):
1043 case (Hexagon::L4_loadd_locked):
1044 case (Hexagon::Y4_l2fetch): {
1048 unsigned TJ = HII.
getType(MJ);
1070 for (
auto &
B : MF) {
1073 for (
auto I =
B.instr_begin(),
E =
B.instr_end();
I !=
E;
I = NextI) {
1074 NextI = std::next(
I);
1087 bool InsertBeforeBundle;
1091 InsertBeforeBundle =
true;
1095 BundleIt =
moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1104 case Hexagon::Y2_barrier:
1105 case Hexagon::Y2_dcfetchbo:
1121 BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1123 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1125 DeadDefs[MO.getReg()] =
true;
1129 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1131 unsigned R = MO.getReg();
1132 if (R != Hexagon::USR_OVF && DeadDefs[R])
1163 if (HII->
isLoopN(I) && isBadForLoopN(J))
1165 if (HII->
isLoopN(J) && isBadForLoopN(I))
1178 if ((SysI && StoreJ) || (SysJ && StoreI))
1181 if (StoreI && StoreJ) {
1187 bool MopStI = HII->
isMemOp(I) || StoreI;
1188 bool MopStJ = HII->
isMemOp(J) || StoreJ;
1189 if (MopStI && MopStJ)
1206 IgnoreDepMIs.clear();
1230 if (NextMII != I.getParent()->end() && HII->
isNewValueJump(*NextMII)) {
1233 bool secondRegMatch =
false;
1237 if (NOp1.
isReg() && I.getOperand(0).getReg() == NOp1.
getReg())
1238 secondRegMatch =
true;
1271 GlueToNewValueJump =
true;
1278 for (
unsigned i = 0;
i < SUJ->
Succs.size(); ++
i) {
1279 if (FoundSequentialDependence)
1282 if (SUJ->
Succs[
i].getSUnit() != SUI)
1301 unsigned DepReg = 0;
1304 DepReg = SUJ->
Succs[
i].getReg();
1305 RC = HRI->getMinimalPhysRegClass(DepReg);
1331 PromotedToDotNew =
true;
1355 auto Itr =
find(IgnoreDepMIs, &J);
1356 if (Itr != IgnoreDepMIs.end()) {
1360 IgnoreDepMIs.push_back(&I);
1372 if (I.isConditionalBranch() && DepType !=
SDep::Data &&
1391 unsigned DepReg = SUJ->
Succs[
i].getReg();
1396 FoundSequentialDependence =
true;
1410 FoundSequentialDependence =
true;
1416 bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1421 FoundSequentialDependence =
true;
1424 }
else if (!LoadJ || (!LoadI && !StoreI)) {
1427 FoundSequentialDependence =
true;
1442 unsigned Opc = I.getOpcode();
1444 case Hexagon::S2_storerd_io:
1445 case Hexagon::S2_storeri_io:
1446 case Hexagon::S2_storerh_io:
1447 case Hexagon::S2_storerb_io:
1454 if (GlueAllocframeStore)
1473 if (!I.modifiesRegister(*P, HRI))
1475 FoundSequentialDependence =
true;
1487 FoundSequentialDependence =
true;
1492 if (FoundSequentialDependence) {
1513 if (PromotedToDotNew)
1520 if (GlueAllocframeStore) {
1522 GlueAllocframeStore =
false;
1533 if (Hexagon::IntRegsRegClass.
contains(R)) {
1544 if (GlueToNewValueJump) {
1561 if (Good && ExtNvjMI)
1587 if (PromotedToDotNew)
1589 if (GlueAllocframeStore) {
1591 GlueAllocframeStore =
false;
1620 if (
Op.isReg() &&
Op.isUse() &&
Op.getReg() == DstReg)
1636 if (!OldPacketMIs.empty()) {
1637 auto *OldBB = OldPacketMIs.front()->getParent();
1645 for (
auto J : OldPacketMIs) {
1663 for (
auto J : OldPacketMIs) {
1682 return new HexagonPacketizer();
bool canReserveResources(const llvm::MCInstrDesc *MID)
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
std::vector< MachineInstr * > CurrentPacketMIs
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
bool isIndirectCall(const MachineInstr &MI) const
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static bool hasWriteToReadDep(const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_end()
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
bool isSucc(SUnit *N)
isSucc - Test if node N is a successor of this node.
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
bool isNewValueInst(const MachineInstr &MI) const
Implements a dense probed hash-table based set.
bool mayStore() const
Return true if this instruction could possibly modify memory.
Describe properties that are true of each instruction in the target description file.
bool isPredicatedTrue(const MachineInstr &MI) const
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
const MachineLoopInfo * MLI
unsigned getRARegister() const
bool demoteToDotOld(MachineInstr &MI)
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isMemOp(const MachineInstr &MI) const
static cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
bool isTailCall(const MachineInstr &MI) const override
bool isCFIInstruction() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Kind
Kind - These are the different kinds of scheduling dependencies.
iterator_range< mop_iterator > operands()
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
return AArch64::GPR64RegClass contains(Reg)
A register anti-dependedence (aka WAR).
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
static cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
std::map< MachineInstr *, SUnit * > MIToSUnit
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool shouldAddToPacket(const MachineInstr &MI) override
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
bool isCall() const
Return true if the instruction is a call.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
Regular data dependence (aka true-dependence).
virtual void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI)
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
unsigned getUnits() const
Returns the choice of FUs.
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
const InstrItineraryData * getInstrItins() const
bool isCondInst(const MachineInstr &MI) const
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isLoopN(const MachineInstr &MI) const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
static bool doesModifyCalleeSavedReg(const MachineInstr &MI, const TargetRegisterInfo *TRI)
Returns true if the instruction modifies a callee-saved register.
void unbundleFromPred()
Break bundle above this instruction.
const MachineBranchProbabilityInfo * MBPI
A handle to the branch probability pass.
A register output-dependence (aka WAW).
static bool isControlFlow(const MachineInstr &MI)
DFAPacketizer * ResourceTracker
void initializeHexagonPacketizerPass(PassRegistry &)
static bool isImplicitDependency(const MachineInstr &I, unsigned DepReg)
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
void reserveResources(const llvm::MCInstrDesc *MID)
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
bool isJumpR(const MachineInstr &MI) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
bool hasV60TOpsOnly() const
static unsigned getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII)
Gets the predicate register of a predicated instruction.
bool isDebugValue() const
bool isImplicitDef() const
int getDotOldOp(const int opc) const
static const MachineOperand & getAbsSetOperand(const MachineInstr &MI)
bool isSoloInstruction(const MachineInstr &MI) override
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
initializer< Ty > init(const Ty &Val)
bool isReturn(QueryType Type=AnyInBundle) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
static bool isSystemInstr(const MachineInstr &MI)
FunctionPass * createHexagonPacketizer()
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
std::pair< iterator, bool > insert(const ValueT &V)
const MCPhysReg * ImplicitDefs
Represent the analysis usage information of a pass.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
self_iterator getIterator()
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
static bool isRegDependence(const SDep::Kind DepType)
bool tryAllocateResourcesForConstExt(bool Reserve)
bool isDotCurInst(const MachineInstr &MI) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isExtended(const MachineInstr &MI) const
Any other ordering dependency.
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
static const MachineOperand & getPostIncrementOperand(const MachineInstr &MI, const HexagonInstrInfo *HII)
bool useBSBScheduling() const
#define HEXAGON_LRFP_SIZE
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineOperand class - Representation of each machine instruction operand.
INITIALIZE_PASS_BEGIN(HexagonPacketizer,"packets","Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
static cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
instr_iterator getInstrIterator() const
void dump(const TargetInstrInfo *TII=nullptr) const
bool isV60VectorInstruction(const MachineInstr &MI) const
void setPreservesCFG()
This function should be called by the pass, iff they do not:
void initPacketizerState() override
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool canReserveResourcesForConstExt()
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
bool isPredicatedNew(const MachineInstr &MI) const
static const MachineOperand & getStoreValueOperand(const MachineInstr &MI)
bool isDeallocRet(const MachineInstr &MI) const
static bool isLoadAbsSet(const MachineInstr &MI)
static PredicateKind getPredicateSense(const MachineInstr &MI, const HexagonInstrInfo *HII)
Returns true if an instruction is predicated on p0 and false if it's predicated on !p0...
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
bool isDotNewInst(const MachineInstr &MI) const
static bool isSchedBarrier(const MachineInstr &MI)
void reserveResourcesForConstExt()
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
int getDotNewOp(const MachineInstr &MI) const
static bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI)
cl::opt< bool > ScheduleInlineAsm
bool isCall(QueryType Type=AnyInBundle) const
int getDotCurOp(const MachineInstr &MI) const
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
bool useCallersSP(MachineInstr &MI)
bool mayBeNewStore(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
unsigned getStackRegister() const
unsigned getReg() const
getReg - Returns the register number.
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
bool mayBeCurLoad(const MachineInstr &MI) const
SmallVector< SDep, 4 > Succs
void useCalleesSP(MachineInstr &MI)
StringRef - Represent a constant reference to a string, i.e.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
void unpacketizeSoloInstrs(MachineFunction &MF)
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
Dependence - This class represents a dependence between two memory memory references in a function...
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
bool isConstExtended(const MachineInstr &MI) const
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
static bool isDirectJump(const MachineInstr &MI)
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
uint64_t getType(const MachineInstr &MI) const
bool producesStall(const MachineInstr &MI)
Properties which a MachineFunction may have at a given point in time.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
bool isNewValueJump(const MachineInstr &MI) const
bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J)