LLVM  4.0.0
AMDGPUISelLowering.h
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1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
18 
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
28 private:
29  /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
30  /// legalized from a smaller type VT. Need to match pre-legalized type because
31  /// the generic legalization inserts the add/sub between the select and
32  /// compare.
33  SDValue getFFBH_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL) const;
34 
35 protected:
37 
41  /// \brief Split a vector store into multiple scalar stores.
42  /// \returns The resulting chain.
43 
44  SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
45  SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
46  SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
47  SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
49 
50  SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
51  SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
52  SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
53  SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
54 
55  SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
56 
57  SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58  SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
61 
62  SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
66 
68 
69 protected:
70  bool shouldCombineMemoryType(EVT VT) const;
73 
75  unsigned Opc, SDValue LHS,
76  uint32_t ValLo, uint32_t ValHi) const;
84  SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
85  SDValue RHS, DAGCombinerInfo &DCI) const;
88 
90 
92  SelectionDAG &DAG) const;
93 
94  /// Return 64-bit value Op as two 32-bit integers.
95  std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
96  SelectionDAG &DAG) const;
97  SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
98  SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
99 
100  /// \brief Split a vector load into 2 loads of half the vector.
102 
103  /// \brief Split a vector store into 2 stores of half the vector.
105 
106  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
107  SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
108  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
109  SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
110  void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
113  const SmallVectorImpl<ISD::InputArg> &Ins) const;
114  void AnalyzeFormalArguments(CCState &State,
115  const SmallVectorImpl<ISD::InputArg> &Ins) const;
116  void AnalyzeReturn(CCState &State,
117  const SmallVectorImpl<ISD::OutputArg> &Outs) const;
118 
119 public:
120  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
121 
122  bool mayIgnoreSignedZero(SDValue Op) const {
123  if (getTargetMachine().Options.UnsafeFPMath) // FIXME: nsz only
124  return true;
125 
126  if (const auto *BO = dyn_cast<BinaryWithFlagsSDNode>(Op))
127  return BO->Flags.hasNoSignedZeros();
128 
129  return false;
130  }
131 
132  bool isFAbsFree(EVT VT) const override;
133  bool isFNegFree(EVT VT) const override;
134  bool isTruncateFree(EVT Src, EVT Dest) const override;
135  bool isTruncateFree(Type *Src, Type *Dest) const override;
136 
137  bool isZExtFree(Type *Src, Type *Dest) const override;
138  bool isZExtFree(EVT Src, EVT Dest) const override;
139  bool isZExtFree(SDValue Val, EVT VT2) const override;
140 
141  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
142 
143  MVT getVectorIdxTy(const DataLayout &) const override;
144  bool isSelectSupported(SelectSupportKind) const override;
145 
146  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
147  bool ShouldShrinkFPConstant(EVT VT) const override;
149  ISD::LoadExtType ExtType,
150  EVT ExtVT) const override;
151 
152  bool isLoadBitCastBeneficial(EVT, EVT) const final;
153 
155  unsigned NumElem,
156  unsigned AS) const override;
157  bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
158  bool isCheapToSpeculateCttz() const override;
159  bool isCheapToSpeculateCtlz() const override;
160 
161  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
162  const SmallVectorImpl<ISD::OutputArg> &Outs,
163  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
164  SelectionDAG &DAG) const override;
165  SDValue LowerCall(CallLoweringInfo &CLI,
166  SmallVectorImpl<SDValue> &InVals) const override;
167 
169  SelectionDAG &DAG) const;
170 
171  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
172  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
173  void ReplaceNodeResults(SDNode * N,
175  SelectionDAG &DAG) const override;
176 
177  SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
178  SDValue RHS, SDValue True, SDValue False,
179  SDValue CC, DAGCombinerInfo &DCI) const;
180 
181  const char* getTargetNodeName(unsigned Opcode) const override;
182 
183  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
184  return true;
185  }
187  int &RefinementSteps, bool &UseOneConstNR,
188  bool Reciprocal) const override;
190  int &RefinementSteps) const override;
191 
193  SelectionDAG &DAG) const = 0;
194 
195  /// \brief Determine which of the bits specified in \p Mask are known to be
196  /// either zero or one and return them in the \p KnownZero and \p KnownOne
197  /// bitsets.
199  APInt &KnownZero,
200  APInt &KnownOne,
201  const SelectionDAG &DAG,
202  unsigned Depth = 0) const override;
203 
204  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
205  unsigned Depth = 0) const override;
206 
207  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
208  /// MachineFunction.
209  ///
210  /// \returns a RegisterSDNode representing Reg.
212  const TargetRegisterClass *RC,
213  unsigned Reg, EVT VT) const;
214 
219  };
220 
221  /// \brief Helper function that returns the byte offset of the given
222  /// type of implicit parameter.
224  const ImplicitParameter Param) const;
225 };
226 
227 namespace AMDGPUISD {
228 
229 enum NodeType : unsigned {
230  // AMDIL ISD Opcodes
232  CALL, // Function call based on a single integer
233  UMUL, // 32bit unsigned multiplication
235  // End AMDIL ISD Opcodes
241  // This is SETCC with the full mask result which is used for a compare with a
242  // result bit per item in the wavefront.
245  // FP ops with input and output chain.
248 
249  // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
250  // Denormals handled on some parts.
268  TRIG_PREOP, // 1 ULP max error for f64
269 
270  // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
271  // For f64, max error 2^29 ULP, handles denormals.
283  BFE_U32, // Extract range of bits with zero extension to 32-bits.
284  BFE_I32, // Extract range of bits with sign extension to 32-bits.
285  BFI, // (src0 & src1) | (~src0 & src2)
286  BFM, // Insert a range of bits into a 32-bit word.
287  FFBH_U32, // ctlz with -1 if input is zero.
298  EXPORT, // exp on SI+
299  EXPORT_DONE, // exp on SI+ with done bit set
309 
310  // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
315  /// This node is for VLIW targets and it is used to represent a vector
316  /// that is stored in consecutive registers with the same channel.
317  /// For example:
318  /// |X |Y|Z|W|
319  /// T0|v.x| | | |
320  /// T1|v.y| | | |
321  /// T2|v.z| | | |
322  /// T3|v.w| | | |
324  /// Pointer to the start of the shader's constant data.
344 };
345 
346 
347 } // End namespace AMDGPUISD
348 
349 } // End namespace llvm
350 
351 #endif
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
LLVMContext & Context
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
const TargetMachine & getTargetMachine() const
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const
Function Alias Analysis Results
virtual SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
Pointer to the start of the shader's constant data.
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override
Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const AMDGPUSubtarget * Subtarget
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
MVT - Machine Value Type.
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:818
bool shouldCombineMemoryType(EVT VT) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isLoadBitCastBeneficial(EVT, EVT) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On archi...
SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
Definition: ValueTypes.h:31
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
CCState - This class holds information needed while lowering arguments and return values...
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
An SDNode that represents everything that will be needed to construct a MachineInstr.
SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:769
Represents one node in the SelectionDAG.
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
Class for arbitrary precision integers.
Definition: APInt.h:77
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
void AnalyzeReturn(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs) const
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
#define N
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
aarch64 promote const
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
bool mayIgnoreSignedZero(SDValue Op) const
This file describes how to lower LLVM code to machine code.
bool isSelectSupported(SelectSupportKind) const override
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const