LLVM  4.0.0
AVRRegisterInfo.cpp
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1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRRegisterInfo.h"
15 
16 #include "llvm/ADT/BitVector.h"
20 #include "llvm/IR/Function.h"
22 
23 #include "AVR.h"
24 #include "AVRInstrInfo.h"
25 #include "AVRTargetMachine.h"
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "AVRGenRegisterInfo.inc"
30 
31 namespace llvm {
32 
34 
35 const uint16_t *
38 
39  return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
40  ? CSR_Interrupts_SaveList
41  : CSR_Normal_SaveList);
42 }
43 
44 const uint32_t *
46  CallingConv::ID CC) const {
47  return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
48  ? CSR_Interrupts_RegMask
49  : CSR_Normal_RegMask);
50 }
51 
53  BitVector Reserved(getNumRegs());
54  const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
56 
57  // Reserve the intermediate result registers r1 and r2
58  // The result of instructions like 'mul' is always stored here.
59  Reserved.set(AVR::R0);
60  Reserved.set(AVR::R1);
61  Reserved.set(AVR::R1R0);
62 
63  // Reserve the stack pointer.
64  Reserved.set(AVR::SPL);
65  Reserved.set(AVR::SPH);
66  Reserved.set(AVR::SP);
67 
68  // Reserve the frame pointer registers r28 and r29 if the function requires one.
69  if (TFI->hasFP(MF)) {
70  Reserved.set(AVR::R28);
71  Reserved.set(AVR::R29);
72  Reserved.set(AVR::R29R28);
73  }
74 
75  return Reserved;
76 }
77 
78 const TargetRegisterClass *
80  const MachineFunction &MF) const {
81  if (RC->hasType(MVT::i16)) {
82  return &AVR::DREGSRegClass;
83  }
84 
85  if (RC->hasType(MVT::i8)) {
86  return &AVR::GPR8RegClass;
87  }
88 
89  llvm_unreachable("Invalid register size");
90 }
91 
92 /// Fold a frame offset shared between two add instructions into a single one.
93 static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) {
94  int Opcode = MI.getOpcode();
95 
96  // Don't bother trying if the next instruction is not an add or a sub.
97  if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
98  return;
99  }
100 
101  // Check that DstReg matches with next instruction, otherwise the instruction
102  // is not related to stack address manipulation.
103  if (DstReg != MI.getOperand(0).getReg()) {
104  return;
105  }
106 
107  // Add the offset in the next instruction to our offset.
108  switch (Opcode) {
109  case AVR::SUBIWRdK:
110  Offset += -MI.getOperand(2).getImm();
111  break;
112  case AVR::ADIWRdK:
113  Offset += MI.getOperand(2).getImm();
114  break;
115  }
116 
117  // Finally remove the instruction.
118  MI.eraseFromParent();
119 }
120 
122  int SPAdj, unsigned FIOperandNum,
123  RegScavenger *RS) const {
124  assert(SPAdj == 0 && "Unexpected SPAdj value");
125 
126  MachineInstr &MI = *II;
127  DebugLoc dl = MI.getDebugLoc();
129  const MachineFunction &MF = *MBB.getParent();
130  const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
132  const MachineFrameInfo &MFI = MF.getFrameInfo();
134  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
135  int Offset = MFI.getObjectOffset(FrameIndex);
136 
137  // Add one to the offset because SP points to an empty slot.
138  Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
139  // Fold incoming offset.
140  Offset += MI.getOperand(FIOperandNum + 1).getImm();
141 
142  // This is actually "load effective address" of the stack slot
143  // instruction. We have only two-address instructions, thus we need to
144  // expand it into move + add.
145  if (MI.getOpcode() == AVR::FRMIDX) {
146  MI.setDesc(TII.get(AVR::MOVWRdRr));
147  MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
148 
149  assert(Offset > 0 && "Invalid offset");
150 
151  // We need to materialize the offset via an add instruction.
152  unsigned Opcode;
153  unsigned DstReg = MI.getOperand(0).getReg();
154  assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
155 
156  // Generally, to load a frame address two add instructions are emitted that
157  // could get folded into a single one:
158  // movw r31:r30, r29:r28
159  // adiw r31:r30, 29
160  // adiw r31:r30, 16
161  // to:
162  // movw r31:r30, r29:r28
163  // adiw r31:r30, 45
164  foldFrameOffset(*std::next(II), Offset, DstReg);
165 
166  // Select the best opcode based on DstReg and the offset size.
167  switch (DstReg) {
168  case AVR::R25R24:
169  case AVR::R27R26:
170  case AVR::R31R30: {
171  if (isUInt<6>(Offset)) {
172  Opcode = AVR::ADIWRdK;
173  break;
174  }
176  }
177  default: {
178  // This opcode will get expanded into a pair of subi/sbci.
179  Opcode = AVR::SUBIWRdK;
180  Offset = -Offset;
181  break;
182  }
183  }
184 
185  MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg)
186  .addReg(DstReg, RegState::Kill)
187  .addImm(Offset);
188  New->getOperand(3).setIsDead();
189 
190  return;
191  }
192 
193  // If the offset is too big we have to adjust and restore the frame pointer
194  // to materialize a valid load/store with displacement.
195  //:TODO: consider using only one adiw/sbiw chain for more than one frame index
196  if (Offset > 63) {
197  unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
198  int AddOffset = Offset - 63 + 1;
199 
200  // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
201  if ((Offset - 63 + 1) > 63) {
202  AddOpc = AVR::SUBIWRdK;
203  SubOpc = AVR::SUBIWRdK;
204  AddOffset = -AddOffset;
205  }
206 
207  // It is possible that the spiller places this frame instruction in between
208  // a compare and branch, invalidating the contents of SREG set by the
209  // compare instruction because of the add/sub pairs. Conservatively save and
210  // restore SREG before and after each add/sub pair.
211  BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
212 
213  MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
214  .addReg(AVR::R29R28, RegState::Kill)
215  .addImm(AddOffset);
216  New->getOperand(3).setIsDead();
217 
218  // Restore SREG.
219  BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
220  .addImm(0x3f)
221  .addReg(AVR::R0, RegState::Kill);
222 
223  // No need to set SREG as dead here otherwise if the next instruction is a
224  // cond branch it will be using a dead register.
225  New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
226  .addReg(AVR::R29R28, RegState::Kill)
227  .addImm(Offset - 63 + 1);
228 
229  Offset = 62;
230  }
231 
232  MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
233  assert(isUInt<6>(Offset) && "Offset is out of range");
234  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
235 }
236 
239  if (TFI->hasFP(MF)) {
240  // The Y pointer register
241  return AVR::R28;
242  }
243 
244  return AVR::SP;
245 }
246 
247 const TargetRegisterClass *
249  unsigned Kind) const {
250  // FIXME: Currently we're using avr-gcc as reference, so we restrict
251  // ptrs to Y and Z regs. Though avr-gcc has buggy implementation
252  // of memory constraint, so we can fix it and bit avr-gcc here ;-)
253  return &AVR::PTRDISPREGSRegClass;
254 }
255 
257  unsigned &LoReg,
258  unsigned &HiReg) const {
259  assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
260 
261  LoReg = getSubReg(Reg, AVR::sub_lo);
262  HiReg = getSubReg(Reg, AVR::sub_hi);
263 }
264 
265 } // end of namespace llvm
266 
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg)
Fold a frame offset shared between two add instructions into a single one.
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:43
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:219
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const AVRSubtarget * getSubtargetImpl() const
BitVector getReservedRegs(const MachineFunction &MF) const override
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
return AArch64::GPR64RegClass contains(Reg)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
A generic AVR implementation.
const uint16_t * getCalleeSavedRegs(const MachineFunction *MF=0) const override
MachineBasicBlock * MBB
int64_t getImm() const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=NULL) const override
Stack Frame Processing Methods.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
uint32_t Offset
Used for AVR interrupt routines.
Definition: CallingConv.h:172
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual const TargetFrameLowering * getFrameLowering() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Information about stack frame layout on the target.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
Representation of each machine instruction.
Definition: MachineInstr.h:52
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const
Splits a 16-bit DREGS register into the lo/hi register pair.
const unsigned Kind
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getFrameRegister(const MachineFunction &MF) const override
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
const TargetFrameLowering * getFrameLowering() const override
Definition: AVRSubtarget.h:44
Calling convention used for AVR signal routines.
Definition: CallingConv.h:175
IRTranslator LLVM IR MI
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.