15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
25 class MachineRegisterInfo;
26 class SIMachineFunctionInfo;
35 void reserveRegisterTuples(
BitVector &,
unsigned Reg)
const;
36 void classifyPressureSet(
unsigned PSetID,
unsigned Reg,
64 int Idx)
const override;
69 unsigned BaseReg,
int FrameIdx,
70 int64_t Offset)
const override;
73 int64_t Offset)
const override;
76 int64_t Offset)
const override;
88 unsigned FIOperandNum,
92 return getEncodingValue(Reg) & 0xff;
133 unsigned SubIdx)
const;
138 unsigned SrcSubReg)
const override;
192 return SGPRPressureSets.
test(SetID) && !VGPRPressureSets.
test(SetID);
195 return VGPRPressureSets.
test(SetID) && !SGPRPressureSets.
test(SetID);
220 bool Addressable)
const;
265 unsigned EltSize)
const;
269 unsigned LoadStoreOp,
273 unsigned ScratchRsrcReg,
274 unsigned ScratchOffsetReg,
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool opCanUseInlineConstant(unsigned OpType) const
bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
bool isSGPRPressureSet(unsigned SetID) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
bool isSGPRClass(const TargetRegisterClass *RC) const
unsigned getNumReservedSGPRs(const SISubtarget &ST, const SIMachineFunctionInfo &MFI) const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
unsigned getHWRegIndex(unsigned Reg) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
A description of a memory reference used in the backend.
unsigned getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU, bool Addressable) const
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
static int getRegClass(RegisterKind Is, unsigned RegWidth)
unsigned getVGPRAllocGranule() const
bool opCanUseLiteralConstant(unsigned OpType) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
int64_t getMUBUFInstrOffset(const MachineInstr *MI) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
unsigned getVGPRPressureSet() const
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
unsigned const MachineRegisterInfo * MRI
bool hasVGPRs(const TargetRegisterClass *RC) const
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
bool isSGPRClassID(unsigned RCID) const
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getSGPRAllocGranule() const
unsigned getNumAddressableSGPRs(const SISubtarget &ST) const
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
unsigned getNumDebuggerReservedVGPRs(const SISubtarget &ST) const
bool test(unsigned Idx) const
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
void spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
Returns a register that is not used at any point in the function.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
unsigned getTotalNumSGPRs(const SISubtarget &ST) const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
unsigned getSGPRPressureSet() const
unsigned getMinNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU) const
bool isVGPRPressureSet(unsigned SetID) const
LLVM Value Representation.
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
unsigned getTotalNumVGPRs() const