LLVM  4.0.0
X86Subtarget.cpp
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1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86Subtarget.h"
15 #include "X86InstrInfo.h"
16 #include "X86TargetMachine.h"
17 #include "llvm/IR/Attributes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/GlobalValue.h"
21 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/Host.h"
27 
28 #if defined(_MSC_VER)
29 #include <intrin.h>
30 #endif
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "subtarget"
35 
36 #define GET_SUBTARGETINFO_TARGET_DESC
37 #define GET_SUBTARGETINFO_CTOR
38 #include "X86GenSubtargetInfo.inc"
39 
40 // Temporary option to control early if-conversion for x86 while adding machine
41 // models.
42 static cl::opt<bool>
43 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
44  cl::desc("Enable early if-conversion on X86"));
45 
46 
47 /// Classify a blockaddress reference for the current subtarget according to how
48 /// we should reference it in a non-pcrel context.
50  return classifyLocalReference(nullptr);
51 }
52 
53 /// Classify a global variable reference for the current subtarget according to
54 /// how we should reference it in a non-pcrel context.
55 unsigned char
57  return classifyGlobalReference(GV, *GV->getParent());
58 }
59 
60 unsigned char
62  // 64 bits can use %rip addressing for anything local.
63  if (is64Bit())
64  return X86II::MO_NO_FLAG;
65 
66  // If this is for a position dependent executable, the static linker can
67  // figure it out.
68  if (!isPositionIndependent())
69  return X86II::MO_NO_FLAG;
70 
71  // The COFF dynamic linker just patches the executable sections.
72  if (isTargetCOFF())
73  return X86II::MO_NO_FLAG;
74 
75  if (isTargetDarwin()) {
76  // 32 bit macho has no relocation for a-b if a is undefined, even if
77  // b is in the section that is being relocated.
78  // This means we have to use o load even for GVs that are known to be
79  // local to the dso.
80  if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
82 
84  }
85 
86  return X86II::MO_GOTOFF;
87 }
88 
90  const Module &M) const {
91  // Large model never uses stubs.
93  return X86II::MO_NO_FLAG;
94 
95  // Absolute symbols can be referenced directly.
96  if (GV && GV->isAbsoluteSymbolRef())
97  return X86II::MO_NO_FLAG;
98 
99  if (TM.shouldAssumeDSOLocal(M, GV))
100  return classifyLocalReference(GV);
101 
102  if (isTargetCOFF())
103  return X86II::MO_DLLIMPORT;
104 
105  if (is64Bit())
106  return X86II::MO_GOTPCREL;
107 
108  if (isTargetDarwin()) {
109  if (!isPositionIndependent())
112  }
113 
114  return X86II::MO_GOT;
115 }
116 
117 unsigned char
119  return classifyGlobalFunctionReference(GV, *GV->getParent());
120 }
121 
122 unsigned char
124  const Module &M) const {
125  if (TM.shouldAssumeDSOLocal(M, GV))
126  return X86II::MO_NO_FLAG;
127 
128  assert(!isTargetCOFF());
129 
130  if (isTargetELF())
131  return X86II::MO_PLT;
132 
133  if (is64Bit()) {
134  auto *F = dyn_cast_or_null<Function>(GV);
135  if (F && F->hasFnAttribute(Attribute::NonLazyBind))
136  // If the function is marked as non-lazy, generate an indirect call
137  // which loads from the GOT directly. This avoids runtime overhead
138  // at the cost of eager binding (and one extra byte of encoding).
139  return X86II::MO_GOTPCREL;
140  return X86II::MO_NO_FLAG;
141  }
142 
143  return X86II::MO_NO_FLAG;
144 }
145 
146 /// This function returns the name of a function which has an interface like
147 /// the non-standard bzero function, if such a function exists on the
148 /// current subtarget and it is considered preferable over memset with zero
149 /// passed as the second argument. Otherwise it returns null.
150 const char *X86Subtarget::getBZeroEntry() const {
151  // Darwin 10 has a __bzero entry point for this purpose.
152  if (getTargetTriple().isMacOSX() &&
153  !getTargetTriple().isMacOSXVersionLT(10, 6))
154  return "__bzero";
155 
156  return nullptr;
157 }
158 
160  return getTargetTriple().isMacOSX() &&
162  is64Bit();
163 }
164 
165 /// Return true if the subtarget allows calls to immediate address.
167  // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32
168  // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does,
169  // the following check for Win32 should be removed.
170  if (In64BitMode || isTargetWin32())
171  return false;
173 }
174 
175 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
176  std::string CPUName = CPU;
177  if (CPUName.empty())
178  CPUName = "generic";
179 
180  // Make sure 64-bit features are available in 64-bit mode. (But make sure
181  // SSE2 can be turned off explicitly.)
182  std::string FullFS = FS;
183  if (In64BitMode) {
184  if (!FullFS.empty())
185  FullFS = "+64bit,+sse2," + FullFS;
186  else
187  FullFS = "+64bit,+sse2";
188  }
189 
190  // LAHF/SAHF are always supported in non-64-bit mode.
191  if (!In64BitMode) {
192  if (!FullFS.empty())
193  FullFS = "+sahf," + FullFS;
194  else
195  FullFS = "+sahf";
196  }
197 
198 
199  // Parse features string and set the CPU.
200  ParseSubtargetFeatures(CPUName, FullFS);
201 
202  // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
203  // 16-bytes and under that are reasonably fast. These features were
204  // introduced with Intel's Nehalem/Silvermont and AMD's Family10h
205  // micro-architectures respectively.
206  if (hasSSE42() || hasSSE4A())
207  IsUAMem16Slow = false;
208 
209  InstrItins = getInstrItineraryForCPU(CPUName);
210 
211  // It's important to keep the MCSubtargetInfo feature bits in sync with
212  // target data structure which is shared with MC code emitter, etc.
213  if (In64BitMode)
214  ToggleFeature(X86::Mode64Bit);
215  else if (In32BitMode)
216  ToggleFeature(X86::Mode32Bit);
217  else if (In16BitMode)
218  ToggleFeature(X86::Mode16Bit);
219  else
220  llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!");
221 
222  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
223  << ", 3DNowLevel " << X863DNowLevel
224  << ", 64bit " << HasX86_64 << "\n");
225  assert((!In64BitMode || HasX86_64) &&
226  "64-bit code requested on a subtarget that doesn't support it!");
227 
228  // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both
229  // 32 and 64 bit) and for all 64-bit targets.
230  if (StackAlignOverride)
231  stackAlignment = StackAlignOverride;
232  else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
233  isTargetKFreeBSD() || In64BitMode)
234  stackAlignment = 16;
235 }
236 
237 void X86Subtarget::initializeEnvironment() {
238  X86SSELevel = NoSSE;
240  HasX87 = false;
241  HasCMov = false;
242  HasX86_64 = false;
243  HasPOPCNT = false;
244  HasSSE4A = false;
245  HasAES = false;
246  HasFXSR = false;
247  HasXSAVE = false;
248  HasXSAVEOPT = false;
249  HasXSAVEC = false;
250  HasXSAVES = false;
251  HasPCLMUL = false;
252  HasFMA = false;
253  HasFMA4 = false;
254  HasXOP = false;
255  HasTBM = false;
256  HasMOVBE = false;
257  HasRDRAND = false;
258  HasF16C = false;
259  HasFSGSBase = false;
260  HasLZCNT = false;
261  HasBMI = false;
262  HasBMI2 = false;
263  HasVBMI = false;
264  HasIFMA = false;
265  HasRTM = false;
266  HasHLE = false;
267  HasERI = false;
268  HasCDI = false;
269  HasPFI = false;
270  HasDQI = false;
271  HasBWI = false;
272  HasVLX = false;
273  HasADX = false;
274  HasPKU = false;
275  HasSHA = false;
276  HasPRFCHW = false;
277  HasRDSEED = false;
278  HasLAHFSAHF = false;
279  HasMWAITX = false;
280  HasMPX = false;
281  IsBTMemSlow = false;
282  IsPMULLDSlow = false;
283  IsSHLDSlow = false;
284  IsUAMem16Slow = false;
285  IsUAMem32Slow = false;
286  HasSSEUnalignedMem = false;
287  HasCmpxchg16b = false;
288  UseLeaForSP = false;
289  HasFastPartialYMMWrite = false;
290  HasFastScalarFSQRT = false;
291  HasFastVectorFSQRT = false;
292  HasFastLZCNT = false;
293  HasSlowDivide32 = false;
294  HasSlowDivide64 = false;
295  PadShortFunctions = false;
296  CallRegIndirect = false;
297  LEAUsesAG = false;
298  SlowLEA = false;
299  SlowIncDec = false;
300  stackAlignment = 4;
301  // FIXME: this is a known good value for Yonah. How about others?
303  UseSoftFloat = false;
304 }
305 
306 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
307  StringRef FS) {
308  initializeEnvironment();
309  initSubtargetFeatures(CPU, FS);
310  return *this;
311 }
312 
314  const X86TargetMachine &TM,
315  unsigned StackAlignOverride)
316  : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others),
317  PICStyle(PICStyles::None), TM(TM), TargetTriple(TT),
318  StackAlignOverride(StackAlignOverride),
319  In64BitMode(TargetTriple.getArch() == Triple::x86_64),
320  In32BitMode(TargetTriple.getArch() == Triple::x86 &&
321  TargetTriple.getEnvironment() != Triple::CODE16),
322  In16BitMode(TargetTriple.getArch() == Triple::x86 &&
323  TargetTriple.getEnvironment() == Triple::CODE16),
324  TSInfo(), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
325  TLInfo(TM, *this), FrameLowering(*this, getStackAlignment()) {
326  // Determine the PICStyle based on the target selected.
327  if (!isPositionIndependent())
329  else if (is64Bit())
331  else if (isTargetCOFF())
333  else if (isTargetDarwin())
335  else if (isTargetELF())
337 }
338 
340  assert(GISel && "Access to GlobalISel APIs not set");
341  return GISel->getCallLowering();
342 }
343 
345  assert(GISel && "Access to GlobalISel APIs not set");
346  return GISel->getInstructionSelector();
347 }
348 
350  assert(GISel && "Access to GlobalISel APIs not set");
351  return GISel->getLegalizerInfo();
352 }
353 
355  assert(GISel && "Access to GlobalISel APIs not set");
356  return GISel->getRegBankInfo();
357 }
358 
360  return hasCMov() && X86EarlyIfConv;
361 }
362 
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:161
const NoneType None
Definition: None.h:23
bool HasFXSR
Target has FXSAVE/FXRESTOR instructions.
Definition: X86Subtarget.h:95
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:119
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:140
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
bool HasLAHFSAHF
Processor has LAHF/SAHF instructions.
Definition: X86Subtarget.h:167
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:251
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:92
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:406
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:412
const TargetMachine & TM
Definition: X86Subtarget.h:67
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:248
unsigned MaxInlineSizeThreshold
Max.
Definition: X86Subtarget.h:298
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:236
const LegalizerInfo * getLegalizerInfo() const override
bool HasFastScalarFSQRT
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Rap...
Definition: X86Subtarget.h:209
static cl::opt< bool > X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, cl::desc("Enable early if-conversion on X86"))
bool IsUAMem32Slow
True if unaligned memory accesses of 32-bytes are slow.
Definition: X86Subtarget.h:189
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:97
bool IsPMULLDSlow
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition: X86Subtarget.h:183
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:125
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:110
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:427
bool HasFastVectorFSQRT
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS fo...
Definition: X86Subtarget.h:213
Holds all the information related to register banks.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:197
bool isTargetSolaris() const
Definition: X86Subtarget.h:501
bool hasCommonLinkage() const
Definition: GlobalValue.h:419
bool isTargetDarwin() const
Definition: X86Subtarget.h:498
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:86
bool HasPKU
Processor has PKU extenstions.
Definition: X86Subtarget.h:263
const InstructionSelector * getInstructionSelector() const override
This file contains the simple types necessary to represent the attributes associated with functions a...
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:496
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:217
bool HasFastPartialYMMWrite
True if there is no performance penalty to writing only the lower parts of a YMM register without cle...
Definition: X86Subtarget.h:205
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:245
#define F(x, y, z)
Definition: MD5.cpp:51
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:82
bool HasIFMA
Processor has Integer Fused Multiply Add.
Definition: X86Subtarget.h:146
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:381
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:197
bool HasX87
True if the processor supports X87 instructions.
Definition: X86Subtarget.h:76
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:201
X863DNowEnum X863DNowLevel
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:73
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:192
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:89
bool CallRegIndirect
True if the Calls with memory reference should be converted to a register-based indirect call...
Definition: X86Subtarget.h:232
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:134
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:128
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:242
X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
CodeModel::Model getCodeModel() const
Returns the code model.
bool isTargetCOFF() const
Definition: X86Subtarget.h:505
bool HasMWAITX
Processor has MONITORX/MWAITX instructions.
Definition: X86Subtarget.h:170
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
bool IsBTMemSlow
True if BT (bit test) of memory instructions are slow.
Definition: X86Subtarget.h:176
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:155
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:257
bool isPositionIndependent() const
Definition: X86Subtarget.h:560
bool isTargetWin32() const
Definition: X86Subtarget.h:549
std::unique_ptr< GISelAccessor > GISel
Gather the accessor points to GlobalISel-related APIs.
Definition: X86Subtarget.h:309
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:116
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:239
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:254
bool enableEarlyIfConversion() const override
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:179
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:304
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:131
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
bool IsUAMem16Slow
True if unaligned memory accesses of 16-bytes are slow.
Definition: X86Subtarget.h:186
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool hasSSE4A() const
Definition: X86Subtarget.h:421
bool HasMPX
Processor supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:266
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:83
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:193
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
bool HasXSAVES
Target has XSAVES instructions.
Definition: X86Subtarget.h:104
bool isTargetELF() const
Definition: X86Subtarget.h:504
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:158
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:137
bool isTargetLinux() const
Definition: X86Subtarget.h:508
bool HasHLE
Processor has HLE.
Definition: X86Subtarget.h:152
bool HasVBMI
Processor has VBMI instructions.
Definition: X86Subtarget.h:143
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:290
bool hasCMov() const
Definition: X86Subtarget.h:409
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:107
Provides the logic to select generic machine instructions.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:89
bool HasXSAVEOPT
Target has XSAVEOPT instructions.
Definition: X86Subtarget.h:100
bool hasSSE42() const
Definition: X86Subtarget.h:415
X86SSEEnum X86SSELevel
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:70
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
bool HasXSAVE
Target has XSAVE instructions.
Definition: X86Subtarget.h:98
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:104
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:80
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:537
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:113
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:149
const RegisterBankInfo * getRegBankInfo() const override
#define DEBUG(X)
Definition: Debug.h:100
bool HasXSAVEC
Target has XSAVEC instructions.
Definition: X86Subtarget.h:102
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:260
bool HasFastLZCNT
True if LZCNT instruction is fast.
Definition: X86Subtarget.h:224
const char * getBZeroEntry() const
This function returns the name of a function which has an interface like the non-standard bzero funct...
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:75
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:164
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:294
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:509
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
bool isDeclarationForLinker() const
Definition: GlobalValue.h:496
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:122
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:228
bool isAbsoluteSymbolRef() const
Returns whether this is a reference to an absolute symbol.
Definition: Globals.cpp:251
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:187
bool HasSlowDivide64
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:221