| AMDGPURegisterInfo() | llvm::AMDGPURegisterInfo | |
| DISPATCH_ID enum value | llvm::SIRegisterInfo | |
| DISPATCH_PTR enum value | llvm::SIRegisterInfo | |
| eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override | llvm::SIRegisterInfo | |
| findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| FIRST_VGPR_VALUE enum value | llvm::SIRegisterInfo | |
| FLAT_SCRATCH_INIT enum value | llvm::SIRegisterInfo | |
| getCalleeSavedRegs(const MachineFunction *MF) const override | llvm::AMDGPURegisterInfo | |
| getEquivalentSGPRClass(const TargetRegisterClass *VRC) const | llvm::SIRegisterInfo | |
| getEquivalentVGPRClass(const TargetRegisterClass *SRC) const | llvm::SIRegisterInfo | |
| getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override | llvm::SIRegisterInfo | |
| getFrameRegister(const MachineFunction &MF) const override | llvm::AMDGPURegisterInfo | |
| getHWRegIndex(unsigned Reg) const | llvm::SIRegisterInfo | inline |
| getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU, bool Addressable) const | llvm::SIRegisterInfo | |
| getMaxNumSGPRs(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getMaxNumVGPRs(unsigned WavesPerEU) const | llvm::SIRegisterInfo | |
| getMaxNumVGPRs(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| getMinNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU) const | llvm::SIRegisterInfo | |
| getMinNumVGPRs(unsigned WavesPerEU) const | llvm::SIRegisterInfo | |
| getMUBUFInstrOffset(const MachineInstr *MI) const | llvm::SIRegisterInfo | |
| getNumAddressableSGPRs(const SISubtarget &ST) const | llvm::SIRegisterInfo | |
| getNumDebuggerReservedVGPRs(const SISubtarget &ST) const | llvm::SIRegisterInfo | |
| getNumReservedSGPRs(const SISubtarget &ST, const SIMachineFunctionInfo &MFI) const | llvm::SIRegisterInfo | |
| getPhysRegClass(unsigned Reg) const | llvm::SIRegisterInfo | |
| getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override | llvm::SIRegisterInfo | |
| getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const | llvm::SIRegisterInfo | |
| getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const | llvm::SIRegisterInfo | |
| getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const | llvm::SIRegisterInfo | |
| getReservedRegs(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| getSGPRAllocGranule() const | llvm::SIRegisterInfo | inline |
| getSGPRPressureSet() const | llvm::SIRegisterInfo | inline |
| getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const | llvm::SIRegisterInfo | |
| getSubRegFromChannel(unsigned Channel) const | llvm::AMDGPURegisterInfo | |
| getTotalNumSGPRs(const SISubtarget &ST) const | llvm::SIRegisterInfo | |
| getTotalNumVGPRs() const | llvm::SIRegisterInfo | inline |
| getVGPRAllocGranule() const | llvm::SIRegisterInfo | inline |
| getVGPRPressureSet() const | llvm::SIRegisterInfo | inline |
| hasVGPRs(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | |
| isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override | llvm::SIRegisterInfo | |
| isSGPRClass(const TargetRegisterClass *RC) const | llvm::SIRegisterInfo | inline |
| isSGPRClassID(unsigned RCID) const | llvm::SIRegisterInfo | inline |
| isSGPRPressureSet(unsigned SetID) const | llvm::SIRegisterInfo | inline |
| isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const | llvm::SIRegisterInfo | inline |
| isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const | llvm::SIRegisterInfo | |
| isVGPRPressureSet(unsigned SetID) const | llvm::SIRegisterInfo | inline |
| KERNARG_SEGMENT_PTR enum value | llvm::SIRegisterInfo | |
| materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override | llvm::SIRegisterInfo | |
| needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override | llvm::SIRegisterInfo | |
| opCanUseInlineConstant(unsigned OpType) const | llvm::SIRegisterInfo | inline |
| opCanUseLiteralConstant(unsigned OpType) const | llvm::SIRegisterInfo | inline |
| PreloadedValue enum name | llvm::SIRegisterInfo | |
| PRIVATE_SEGMENT_BUFFER enum value | llvm::SIRegisterInfo | |
| PRIVATE_SEGMENT_WAVE_BYTE_OFFSET enum value | llvm::SIRegisterInfo | |
| QUEUE_PTR enum value | llvm::SIRegisterInfo | |
| requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| requiresFrameIndexScavenging(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| requiresRegisterScavenging(const MachineFunction &Fn) const override | llvm::SIRegisterInfo | |
| requiresVirtualBaseRegisters(const MachineFunction &Fn) const override | llvm::SIRegisterInfo | |
| reservedPrivateSegmentBufferReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const | llvm::SIRegisterInfo | |
| resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override | llvm::SIRegisterInfo | |
| restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const | llvm::SIRegisterInfo | |
| shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override | llvm::SIRegisterInfo | |
| SIRegisterInfo() | llvm::SIRegisterInfo | |
| spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const | llvm::SIRegisterInfo | |
| trackLivenessAfterRegAlloc(const MachineFunction &MF) const override | llvm::SIRegisterInfo | |
| WORKGROUP_ID_X enum value | llvm::SIRegisterInfo | |
| WORKGROUP_ID_Y enum value | llvm::SIRegisterInfo | |
| WORKGROUP_ID_Z enum value | llvm::SIRegisterInfo | |
| WORKITEM_ID_X enum value | llvm::SIRegisterInfo | |
| WORKITEM_ID_Y enum value | llvm::SIRegisterInfo | |
| WORKITEM_ID_Z enum value | llvm::SIRegisterInfo | |