46 #include "AMDGPUGenCallingConv.inc"
54 assert(StoreSize % 32 == 0 &&
"Store size not a multiple of 32");
275 for (
MVT VT : ScalarIntVTs) {
346 for (
MVT VT : VectorIntTypes) {
391 for (
MVT VT : FloatVectorTypes) {
547 return (OldSize < 32);
561 return (LScalarSize < CastScalarSize) ||
562 (CastScalarSize >= 32);
615 return DestSize < SrcSize && DestSize % 32 == 0 ;
625 return SrcSize >= 32;
627 return DestSize < SrcSize && DestSize % 32 == 0;
635 return DestSize >= 32;
637 return SrcSize == 32 && DestSize == 64;
698 for (
unsigned i = 0, e = Ins.
size();
i != e; ++
i) {
708 }
else if (NumRegs == 1) {
740 assert(MemoryBits % NumElements == 0);
744 MemoryBits / NumElements);
801 FuncName =
G->getSymbol();
803 FuncName =
G->getGlobal()->getName();
806 Fn,
"unsupported call to function " + FuncName, CLI.
DL.
getDebugLoc());
822 SDLoc(Op).getDebugLoc());
834 "instruction is not implemented yet!");
899 "Do not know what to do with an non-zero offset");
912 Fn,
"unsupported initializer for address space",
SDLoc(Op).getDebugLoc());
931 unsigned Start = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
941 unsigned IntrinsicID = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
945 switch (IntrinsicID) {
947 case AMDGPUIntrinsic::AMDGPU_clamp:
951 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
957 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
974 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1042 std::pair<SDValue, SDValue>
1054 return std::make_pair(Lo, Hi);
1081 if (VT.getVectorNumElements() == 2)
1092 EVT LoMemVT, HiMemVT;
1097 std::tie(Lo, Hi) = DAG.
SplitVector(Op, SL, LoVT, HiVT);
1101 unsigned HiAlign =
MinAlign(BaseAlign, Size);
1104 Load->
getChain(), BasePtr, SrcValue, LoMemVT,
1110 HiPtr, SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1126 EVT VT = Val.getValueType();
1139 EVT LoMemVT, HiMemVT;
1144 std::tie(Lo, Hi) = DAG.
SplitVector(Val, SL, LoVT, HiVT);
1154 unsigned HiAlign =
MinAlign(BaseAlign, Size);
1157 DAG.
getTruncStore(Chain, SL, Lo, BasePtr, SrcValue, LoMemVT, BaseAlign,
1179 if (LHSSignBits < 9)
1183 if (RHSSignBits < 9)
1187 unsigned SignBits =
std::min(LHSSignBits, RHSSignBits);
1188 unsigned DivBits = BitSize - SignBits;
1321 for (
unsigned i = 0;
i < halfBitWidth; ++
i) {
1322 const unsigned bitPos = halfBitWidth -
i - 1;
1568 const unsigned FractBits = 52;
1569 const unsigned ExpBits = 11;
1598 const unsigned FractBits = 52;
1835 SrcIsZero, Bits32, NewCtlz);
1952 "operation should be legal");
1979 "operation should be legal");
2044 const unsigned ExpMask = 0x7ff;
2045 const unsigned ExpBiasf64 = 1023;
2046 const unsigned ExpBiasf16 = 15;
2190 for (
unsigned I = 0;
I < NElts; ++
I)
2201 APInt KnownZero, KnownOne;
2226 APInt KnownZero, KnownOne;
2234 template <
typename IntTy>
2237 if (Width + Offset < 32) {
2239 IntTy Result =
static_cast<IntTy
>(Shl) >> (32 - Width);
2248 if (
MemSDNode *M = dyn_cast<MemSDNode>(U)) {
2249 if (M->isVolatile())
2267 if ((Size == 1 || Size == 2 || Size == 4) && !VT.
isVector())
2270 if (Size == 3 || (Size > 4 && (Size % 4 != 0)))
2557 Mul =
getMul24(DAG, DL, N0, N1, Size,
false);
2561 Mul =
getMul24(DAG, DL, N0, N1, Size,
true);
2644 return C->isAllOnesValue();
2654 const SDLoc &DL)
const {
2694 return getFFBH_U32(DAG, CmpLHS, SL);
2702 return getFFBH_U32(DAG, CmpLHS, SL);
2720 return DAG.
getNode(Op, SL, VT, NewSelect);
2741 SDLoc(N), Cond, LHS, RHS);
2760 bool ShouldFoldNeg =
true;
2765 ShouldFoldNeg =
false;
2767 ShouldFoldNeg =
false;
2770 if (ShouldFoldNeg) {
2780 Cond, NewLHS, NewRHS);
2944 return DAG.
getNode(Opc, SL, VT, Neg);
3015 uint64_t CVal =
C->getZExtValue();
3022 const APInt &Val =
C->getValueAPF().bitcastToAPInt();
3077 "Vector handling of BFE not implemented");
3082 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
3095 if (OffsetVal == 0) {
3097 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
3100 if (OpSignBits >= SignBits)
3120 return constantFoldBFE<int32_t>(DAG,
3121 CVal->getSExtValue(),
3127 return constantFoldBFE<uint32_t>(DAG,
3128 CVal->getZExtValue(),
3134 if ((OffsetVal + WidthVal) >= 32) {
3137 BitsFrom, ShiftVal);
3143 OffsetVal + WidthVal);
3145 APInt KnownZero, KnownOne;
3149 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
3150 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
3151 KnownZero, KnownOne, TLO)) {
3172 unsigned Reg,
EVT VT)
const {
3175 unsigned VirtualRegister;
3193 return ArgOffset + 4;
3198 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
3303 int &RefinementSteps,
3304 bool &UseOneConstNR,
3305 bool Reciprocal)
const {
3309 RefinementSteps = 0;
3321 int &RefinementSteps)
const {
3330 RefinementSteps = 0;
3345 unsigned Depth)
const {
3368 unsigned BitWidth = 32;
3382 unsigned Depth)
const {
3395 return std::max(SignBits, Op0SignBits);
3400 return Width ? 32 - (Width->
getZExtValue() & 0x1f) : 1;
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
void push_back(const T &Elt)
A parsed version of the target data layout string in and methods for querying it. ...
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
CombineLevel getDAGCombineLevel()
unsigned allocateLDSGlobal(const DataLayout &DL, const GlobalValue &GV)
SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Flags getFlags() const
Return the raw flags of the source value,.
LLVMContext * getContext() const
static SDValue distributeOpThroughSelect(TargetLowering::DAGCombinerInfo &DCI, unsigned Op, const SDLoc &SL, SDValue Cond, SDValue N1, SDValue N2)
Diagnostic information for unsupported feature in backend.
AMDGPU specific subclass of TargetSubtarget.
uint64_t getZExtValue() const
Get zero extended value.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const
void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const override
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
const TargetMachine & getTargetMachine() const
SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isCalledByLegalizer() const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
constexpr uint32_t Lo_32(uint64_t Value)
Lo_32 - This function returns the low 32 bits of a 64 bit value.
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
Carry-setting nodes for multiple precision addition and subtraction.
bool isExtended() const
isExtended - Test if the given EVT is extended (as opposed to being simple).
SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
const GlobalValue * getGlobal() const
void setHasFloatingPointExceptions(bool FPExceptions=true)
Tells the code generator that this target supports floating point exceptions and cares about preservi...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
static bool fnegFoldsIntoOp(unsigned Opc)
Function Alias Analysis Results
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
static SDValue extractF64Exponent(SDValue Hi, const SDLoc &SL, SelectionDAG &DAG)
SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const
Address space for local memory.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If zero
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
const MachinePointerInfo & getPointerInfo() const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Turn load of vector type into a load of the individual elements.
SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const
const Constant * getInitializer() const
getInitializer - Return the initializer for this global variable.
const SDValue & getBasePtr() const
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
LLVMContext & getContext() const
bool hasFPExceptions() const
SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
static bool simplifyI24(SDNode *Node24, unsigned OpIdx, TargetLowering::DAGCombinerInfo &DCI)
SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const override
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
APInt Not(const APInt &APIVal)
Bitwise complement function.
SDValue CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const
Generate Min/Max node.
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
bool isNegative() const
Return true if the value is negative.
uint64_t allocateKernArg(uint64_t Size, unsigned Align)
SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
Pointer to the start of the shader's constant data.
int64_t getOffset() const
unsigned getABIArgOffset() const
SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const
Shift and rotation operations.
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
void addLoc(const CCValAssign &V)
SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const override
Return a reciprocal estimate value for the input operand.
unsigned getAddressSpace() const
Reg
All possible values of the reg field in the ModR/M byte.
MachinePointerInfo getWithOffset(int64_t O) const
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
MVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
static bool isI24(SDValue Op, SelectionDAG &DAG)
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const
Interface to describe a layout of a stack frame on an AMDGPU target.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SmallVector< ISD::InputArg, 32 > Ins
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
TargetRegisterInfo interface that is implemented by all hw codegen targets.
MachineFunction & getMachineFunction() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
const AMDGPUSubtarget * Subtarget
bool isLiveIn(unsigned Reg) const
SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Simple integer binary arithmetic operators.
static bool hasVolatileUser(SDNode *Val)
const SDValue & getBasePtr() const
EVT getHalfSizedIntegerVT(LLVMContext &Context) const
getHalfSizedIntegerVT - Finds the smallest simple value type that is greater than or equal to half th...
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
static mvt_range integer_vector_valuetypes()
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
static SDValue getMul24(SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed)
Generation getGeneration() const
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
This class is used to represent ISD::STORE nodes.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
static bool isCtlzOpc(unsigned Opc)
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const
static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL)
SDNode * getNode() const
get the SDNode which holds the desired result
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
unsigned getScalarSizeInBits() const
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const
Split a vector store into multiple scalar stores.
unsigned getStoreSizeInBits() const
getStoreSizeInBits - Return the number of bits overwritten by a store of the specified value type...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
unsigned const MachineRegisterInfo * MRI
unsigned getVectorNumElements() const
MVT - Machine Value Type.
SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const
bool isVector() const
isVector - Return true if this is a vector value type.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isBeforeLegalizeOps() const
Carry-using nodes for multiple precision addition and subtraction.
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
bool shouldCombineMemoryType(EVT VT) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
static bool hasDefinedInitializer(const GlobalValue *GV)
void AddToWorklist(SDNode *N)
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
unsigned getBitWidth() const
Return the number of bits in the APInt.
static bool allocateKernArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
bool hasFP32Denormals() const
bool isLoadBitCastBeneficial(EVT, EVT) const final
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On archi...
bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded, DAGCombinerInfo &DCI)
Helper for SimplifyDemandedBits that can simplify an operation with multiple uses.
const SDValue & getValue() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
bool has16BitInsts() const
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const
This structure contains all information that is necessary for lowering calls.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
void setHasExtractBitsInsn(bool hasExtractInsn=true)
Tells the code generator that the target has BitExtract instructions.
SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
static bool isU24(SDValue Op, SelectionDAG &DAG)
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
TokenFactor - This node takes multiple tokens as input and produces a single token result...
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
CCState - This class holds information needed while lowering arguments and return values...
const DebugLoc & getDebugLoc() const
void dump() const
Dump this node, for debugging.
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isFAbsFree(EVT VT) const override
Return true if an fabs operation is free to the point where it is never worthwhile to replace it with...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provides VTs and return the low/high part...
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Interface definition of the TargetLowering class that is common to all AMD GPUs.
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
const SDValue & getChain() const
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
SDValue performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0)
Append the extracted elements from Start to Count out of the vector Op in Args.
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
double BitsToDouble(uint64_t Bits)
BitsToDouble - This function takes a 64-bit integer and returns the bit equivalent double...
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
bool hasInitializer() const
Definitions have initializers, declarations don't.
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
iterator_range< use_iterator > uses()
Select(COND, TRUEVAL, FALSEVAL).
Interface for the AMDGPU Implementation of the Intrinsic Info class.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
static const fltSemantics & IEEEdouble()
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isConstantValueOfAnyType(SDValue N)
SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const
BR_JT - Jumptable branch.
unsigned countLeadingOnes() const
Count the number of leading one bits.
Represents a use of a SDNode.
Interface definition for SIInstrInfo.
void AnalyzeReturn(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs) const
Bitwise operators - logical and, logical or, logical xor.
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
SelectSupportKind
Enum that describes what type of support for selects the target has.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Modify anything using 'From' to use 'To' instead.
ArrayRef< SDUse > ops() const
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
bool isTruncateFree(EVT Src, EVT Dest) const override
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)
#define NODE_NAME_CASE(node)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
static bool isNegativeOne(SDValue Val)
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
bool isFNegFree(EVT VT) const override
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
EVT getPow2VectorType(LLVMContext &Context) const
getPow2VectorType - Widens the length of the given vector EVT up to the nearest power of 2 and return...
SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
constexpr uint32_t Hi_32(uint64_t Value)
Hi_32 - This function returns the high 32 bits of a 64 bit value.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
const TargetLowering & getTargetLoweringInfo() const
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
static EVT getEquivalentMemType(LLVMContext &Context, EVT VT)
Primary interface to the complete machine description for the target machine.
static SDValue foldFreeOpFromSelect(TargetLowering::DAGCombinerInfo &DCI, SDValue N)
bool hasBCNT(unsigned Size) const
bool isZExtFree(Type *Src, Type *Dest) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
StringRef - Represent a constant reference to a string, i.e.
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
SetCC operator - This evaluates to a true value iff the condition is true.
uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned getOrigAlign() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
MVT getVectorIdxTy(const DataLayout &) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const override
Hooks for building estimates in place of slower divisions and square roots.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
bool mayIgnoreSignedZero(SDValue Op) const
void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO)
bool isSelectSupported(SelectSupportKind) const override
uint64_t getZExtValue() const
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
unsigned getAlignmentForImplicitArgPtr() const
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const