LLVM  4.0.0
PHIElimination.cpp
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1 //===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass eliminates machine instruction PHI nodes by inserting copy
11 // instructions. This destroys SSA information, but is the desired input for
12 // some register allocators.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "PHIEliminationUtils.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallPtrSet.h"
19 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Function.h"
30 #include "llvm/Support/Debug.h"
34 #include <algorithm>
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "phielim"
38 
39 static cl::opt<bool>
40 DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false),
41  cl::Hidden, cl::desc("Disable critical edge splitting "
42  "during PHI elimination"));
43 
44 static cl::opt<bool>
45 SplitAllCriticalEdges("phi-elim-split-all-critical-edges", cl::init(false),
46  cl::Hidden, cl::desc("Split all critical edges during "
47  "PHI elimination"));
48 
50  "no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden,
51  cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."));
52 
53 namespace {
54  class PHIElimination : public MachineFunctionPass {
55  MachineRegisterInfo *MRI; // Machine register information
56  LiveVariables *LV;
57  LiveIntervals *LIS;
58 
59  public:
60  static char ID; // Pass identification, replacement for typeid
61  PHIElimination() : MachineFunctionPass(ID) {
63  }
64 
65  bool runOnMachineFunction(MachineFunction &Fn) override;
66  void getAnalysisUsage(AnalysisUsage &AU) const override;
67 
68  private:
69  /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions
70  /// in predecessor basic blocks.
71  ///
72  bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB);
73  void LowerPHINode(MachineBasicBlock &MBB,
74  MachineBasicBlock::iterator LastPHIIt);
75 
76  /// analyzePHINodes - Gather information about the PHI nodes in
77  /// here. In particular, we want to map the number of uses of a virtual
78  /// register which is used in a PHI node. We map that to the BB the
79  /// vreg is coming from. This is used later to determine when the vreg
80  /// is killed in the BB.
81  ///
82  void analyzePHINodes(const MachineFunction& Fn);
83 
84  /// Split critical edges where necessary for good coalescer performance.
85  bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
86  MachineLoopInfo *MLI);
87 
88  // These functions are temporary abstractions around LiveVariables and
89  // LiveIntervals, so they can go away when LiveVariables does.
90  bool isLiveIn(unsigned Reg, const MachineBasicBlock *MBB);
91  bool isLiveOutPastPHIs(unsigned Reg, const MachineBasicBlock *MBB);
92 
93  typedef std::pair<unsigned, unsigned> BBVRegPair;
94  typedef DenseMap<BBVRegPair, unsigned> VRegPHIUse;
95 
96  VRegPHIUse VRegPHIUseCount;
97 
98  // Defs of PHI sources which are implicit_def.
100 
101  // Map reusable lowered PHI node -> incoming join register.
102  typedef DenseMap<MachineInstr*, unsigned,
103  MachineInstrExpressionTrait> LoweredPHIMap;
104  LoweredPHIMap LoweredPHIs;
105  };
106 }
107 
108 STATISTIC(NumLowered, "Number of phis lowered");
109 STATISTIC(NumCriticalEdgesSplit, "Number of critical edges split");
110 STATISTIC(NumReused, "Number of reused lowered phis");
111 
112 char PHIElimination::ID = 0;
114 
115 INITIALIZE_PASS_BEGIN(PHIElimination, "phi-node-elimination",
116  "Eliminate PHI nodes for register allocation",
117  false, false)
119 INITIALIZE_PASS_END(PHIElimination, "phi-node-elimination",
120  "Eliminate PHI nodes for register allocation", false, false)
121 
122 void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
123  AU.addUsedIfAvailable<LiveVariables>();
124  AU.addPreserved<LiveVariables>();
125  AU.addPreserved<SlotIndexes>();
126  AU.addPreserved<LiveIntervals>();
127  AU.addPreserved<MachineDominatorTree>();
128  AU.addPreserved<MachineLoopInfo>();
130 }
131 
132 bool PHIElimination::runOnMachineFunction(MachineFunction &MF) {
133  MRI = &MF.getRegInfo();
134  LV = getAnalysisIfAvailable<LiveVariables>();
135  LIS = getAnalysisIfAvailable<LiveIntervals>();
136 
137  bool Changed = false;
138 
139  // This pass takes the function out of SSA form.
140  MRI->leaveSSA();
141 
142  // Split critical edges to help the coalescer. This does not yet support
143  // updating LiveIntervals, so we disable it.
144  if (!DisableEdgeSplitting && (LV || LIS)) {
145  MachineLoopInfo *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
146  for (auto &MBB : MF)
147  Changed |= SplitPHIEdges(MF, MBB, MLI);
148  }
149 
150  // Populate VRegPHIUseCount
151  analyzePHINodes(MF);
152 
153  // Eliminate PHI instructions by inserting copies into predecessor blocks.
154  for (auto &MBB : MF)
155  Changed |= EliminatePHINodes(MF, MBB);
156 
157  // Remove dead IMPLICIT_DEF instructions.
158  for (MachineInstr *DefMI : ImpDefs) {
159  unsigned DefReg = DefMI->getOperand(0).getReg();
160  if (MRI->use_nodbg_empty(DefReg)) {
161  if (LIS)
162  LIS->RemoveMachineInstrFromMaps(*DefMI);
163  DefMI->eraseFromParent();
164  }
165  }
166 
167  // Clean up the lowered PHI instructions.
168  for (auto &I : LoweredPHIs) {
169  if (LIS)
170  LIS->RemoveMachineInstrFromMaps(*I.first);
171  MF.DeleteMachineInstr(I.first);
172  }
173 
174  LoweredPHIs.clear();
175  ImpDefs.clear();
176  VRegPHIUseCount.clear();
177 
178  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
179 
180  return Changed;
181 }
182 
183 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
184 /// predecessor basic blocks.
185 ///
186 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
188  if (MBB.empty() || !MBB.front().isPHI())
189  return false; // Quick exit for basic blocks without PHIs.
190 
191  // Get an iterator to the first instruction after the last PHI node (this may
192  // also be the end of the basic block).
193  MachineBasicBlock::iterator LastPHIIt =
194  std::prev(MBB.SkipPHIsAndLabels(MBB.begin()));
195 
196  while (MBB.front().isPHI())
197  LowerPHINode(MBB, LastPHIIt);
198 
199  return true;
200 }
201 
202 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
203 /// This includes registers with no defs.
204 static bool isImplicitlyDefined(unsigned VirtReg,
205  const MachineRegisterInfo *MRI) {
206  for (MachineInstr &DI : MRI->def_instructions(VirtReg))
207  if (!DI.isImplicitDef())
208  return false;
209  return true;
210 }
211 
212 /// isSourceDefinedByImplicitDef - Return true if all sources of the phi node
213 /// are implicit_def's.
215  const MachineRegisterInfo *MRI) {
216  for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
217  if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
218  return false;
219  return true;
220 }
221 
222 
223 /// LowerPHINode - Lower the PHI node at the top of the specified block,
224 ///
225 void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
226  MachineBasicBlock::iterator LastPHIIt) {
227  ++NumLowered;
228 
229  MachineBasicBlock::iterator AfterPHIsIt = std::next(LastPHIIt);
230 
231  // Unlink the PHI node from the basic block, but don't delete the PHI yet.
232  MachineInstr *MPhi = MBB.remove(&*MBB.begin());
233 
234  unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
235  unsigned DestReg = MPhi->getOperand(0).getReg();
236  assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
237  bool isDead = MPhi->getOperand(0).isDead();
238 
239  // Create a new register for the incoming PHI arguments.
240  MachineFunction &MF = *MBB.getParent();
241  unsigned IncomingReg = 0;
242  bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
243 
244  // Insert a register to register copy at the top of the current block (but
245  // after any remaining phi nodes) which copies the new incoming register
246  // into the phi node destination.
249  // If all sources of a PHI node are implicit_def, just emit an
250  // implicit_def instead of a copy.
251  BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
252  TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
253  else {
254  // Can we reuse an earlier PHI node? This only happens for critical edges,
255  // typically those created by tail duplication.
256  unsigned &entry = LoweredPHIs[MPhi];
257  if (entry) {
258  // An identical PHI node was already lowered. Reuse the incoming register.
259  IncomingReg = entry;
260  reusedIncoming = true;
261  ++NumReused;
262  DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
263  } else {
264  const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
265  entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
266  }
267  BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
268  TII->get(TargetOpcode::COPY), DestReg)
269  .addReg(IncomingReg);
270  }
271 
272  // Update live variable information if there is any.
273  if (LV) {
274  MachineInstr &PHICopy = *std::prev(AfterPHIsIt);
275 
276  if (IncomingReg) {
277  LiveVariables::VarInfo &VI = LV->getVarInfo(IncomingReg);
278 
279  // Increment use count of the newly created virtual register.
280  LV->setPHIJoin(IncomingReg);
281 
282  // When we are reusing the incoming register, it may already have been
283  // killed in this block. The old kill will also have been inserted at
284  // AfterPHIsIt, so it appears before the current PHICopy.
285  if (reusedIncoming)
286  if (MachineInstr *OldKill = VI.findKill(&MBB)) {
287  DEBUG(dbgs() << "Remove old kill from " << *OldKill);
288  LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
289  DEBUG(MBB.dump());
290  }
291 
292  // Add information to LiveVariables to know that the incoming value is
293  // killed. Note that because the value is defined in several places (once
294  // each for each incoming block), the "def" block and instruction fields
295  // for the VarInfo is not filled in.
296  LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
297  }
298 
299  // Since we are going to be deleting the PHI node, if it is the last use of
300  // any registers, or if the value itself is dead, we need to move this
301  // information over to the new copy we just inserted.
302  LV->removeVirtualRegistersKilled(*MPhi);
303 
304  // If the result is dead, update LV.
305  if (isDead) {
306  LV->addVirtualRegisterDead(DestReg, PHICopy);
307  LV->removeVirtualRegisterDead(DestReg, *MPhi);
308  }
309  }
310 
311  // Update LiveIntervals for the new copy or implicit def.
312  if (LIS) {
313  SlotIndex DestCopyIndex =
314  LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
315 
316  SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
317  if (IncomingReg) {
318  // Add the region from the beginning of MBB to the copy instruction to
319  // IncomingReg's live interval.
320  LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
321  VNInfo *IncomingVNI = IncomingLI.getVNInfoAt(MBBStartIndex);
322  if (!IncomingVNI)
323  IncomingVNI = IncomingLI.getNextValue(MBBStartIndex,
324  LIS->getVNInfoAllocator());
325  IncomingLI.addSegment(LiveInterval::Segment(MBBStartIndex,
326  DestCopyIndex.getRegSlot(),
327  IncomingVNI));
328  }
329 
330  LiveInterval &DestLI = LIS->getInterval(DestReg);
331  assert(DestLI.begin() != DestLI.end() &&
332  "PHIs should have nonempty LiveIntervals.");
333  if (DestLI.endIndex().isDead()) {
334  // A dead PHI's live range begins and ends at the start of the MBB, but
335  // the lowered copy, which will still be dead, needs to begin and end at
336  // the copy instruction.
337  VNInfo *OrigDestVNI = DestLI.getVNInfoAt(MBBStartIndex);
338  assert(OrigDestVNI && "PHI destination should be live at block entry.");
339  DestLI.removeSegment(MBBStartIndex, MBBStartIndex.getDeadSlot());
340  DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
341  LIS->getVNInfoAllocator());
342  DestLI.removeValNo(OrigDestVNI);
343  } else {
344  // Otherwise, remove the region from the beginning of MBB to the copy
345  // instruction from DestReg's live interval.
346  DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
347  VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
348  assert(DestVNI && "PHI destination should be live at its definition.");
349  DestVNI->def = DestCopyIndex.getRegSlot();
350  }
351  }
352 
353  // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
354  for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2)
355  --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
356  MPhi->getOperand(i).getReg())];
357 
358  // Now loop over all of the incoming arguments, changing them to copy into the
359  // IncomingReg register in the corresponding predecessor basic block.
360  SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto;
361  for (int i = NumSrcs - 1; i >= 0; --i) {
362  unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
363  unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
364  bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
365  isImplicitlyDefined(SrcReg, MRI);
367  "Machine PHI Operands must all be virtual registers!");
368 
369  // Get the MachineBasicBlock equivalent of the BasicBlock that is the source
370  // path the PHI.
371  MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
372 
373  // Check to make sure we haven't already emitted the copy for this block.
374  // This can happen because PHI nodes may have multiple entries for the same
375  // basic block.
376  if (!MBBsInsertedInto.insert(&opBlock).second)
377  continue; // If the copy has already been emitted, we're done.
378 
379  // Find a safe location to insert the copy, this may be the first terminator
380  // in the block (or end()).
381  MachineBasicBlock::iterator InsertPos =
382  findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
383 
384  // Insert the copy.
385  MachineInstr *NewSrcInstr = nullptr;
386  if (!reusedIncoming && IncomingReg) {
387  if (SrcUndef) {
388  // The source register is undefined, so there is no need for a real
389  // COPY, but we still need to ensure joint dominance by defs.
390  // Insert an IMPLICIT_DEF instruction.
391  NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
392  TII->get(TargetOpcode::IMPLICIT_DEF),
393  IncomingReg);
394 
395  // Clean up the old implicit-def, if there even was one.
396  if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
397  if (DefMI->isImplicitDef())
398  ImpDefs.insert(DefMI);
399  } else {
400  NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
401  TII->get(TargetOpcode::COPY), IncomingReg)
402  .addReg(SrcReg, 0, SrcSubReg);
403  }
404  }
405 
406  // We only need to update the LiveVariables kill of SrcReg if this was the
407  // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
408  // out of the predecessor. We can also ignore undef sources.
409  if (LV && !SrcUndef &&
410  !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
411  !LV->isLiveOut(SrcReg, opBlock)) {
412  // We want to be able to insert a kill of the register if this PHI (aka,
413  // the copy we just inserted) is the last use of the source value. Live
414  // variable analysis conservatively handles this by saying that the value
415  // is live until the end of the block the PHI entry lives in. If the value
416  // really is dead at the PHI copy, there will be no successor blocks which
417  // have the value live-in.
418 
419  // Okay, if we now know that the value is not live out of the block, we
420  // can add a kill marker in this block saying that it kills the incoming
421  // value!
422 
423  // In our final twist, we have to decide which instruction kills the
424  // register. In most cases this is the copy, however, terminator
425  // instructions at the end of the block may also use the value. In this
426  // case, we should mark the last such terminator as being the killing
427  // block, not the copy.
428  MachineBasicBlock::iterator KillInst = opBlock.end();
429  MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
430  for (MachineBasicBlock::iterator Term = FirstTerm;
431  Term != opBlock.end(); ++Term) {
432  if (Term->readsRegister(SrcReg))
433  KillInst = Term;
434  }
435 
436  if (KillInst == opBlock.end()) {
437  // No terminator uses the register.
438 
439  if (reusedIncoming || !IncomingReg) {
440  // We may have to rewind a bit if we didn't insert a copy this time.
441  KillInst = FirstTerm;
442  while (KillInst != opBlock.begin()) {
443  --KillInst;
444  if (KillInst->isDebugValue())
445  continue;
446  if (KillInst->readsRegister(SrcReg))
447  break;
448  }
449  } else {
450  // We just inserted this copy.
451  KillInst = std::prev(InsertPos);
452  }
453  }
454  assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
455 
456  // Finally, mark it killed.
457  LV->addVirtualRegisterKilled(SrcReg, *KillInst);
458 
459  // This vreg no longer lives all of the way through opBlock.
460  unsigned opBlockNum = opBlock.getNumber();
461  LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
462  }
463 
464  if (LIS) {
465  if (NewSrcInstr) {
466  LIS->InsertMachineInstrInMaps(*NewSrcInstr);
467  LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
468  }
469 
470  if (!SrcUndef &&
471  !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]) {
472  LiveInterval &SrcLI = LIS->getInterval(SrcReg);
473 
474  bool isLiveOut = false;
475  for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
476  SE = opBlock.succ_end(); SI != SE; ++SI) {
477  SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
478  VNInfo *VNI = SrcLI.getVNInfoAt(startIdx);
479 
480  // Definitions by other PHIs are not truly live-in for our purposes.
481  if (VNI && VNI->def != startIdx) {
482  isLiveOut = true;
483  break;
484  }
485  }
486 
487  if (!isLiveOut) {
488  MachineBasicBlock::iterator KillInst = opBlock.end();
489  MachineBasicBlock::iterator FirstTerm = opBlock.getFirstTerminator();
490  for (MachineBasicBlock::iterator Term = FirstTerm;
491  Term != opBlock.end(); ++Term) {
492  if (Term->readsRegister(SrcReg))
493  KillInst = Term;
494  }
495 
496  if (KillInst == opBlock.end()) {
497  // No terminator uses the register.
498 
499  if (reusedIncoming || !IncomingReg) {
500  // We may have to rewind a bit if we didn't just insert a copy.
501  KillInst = FirstTerm;
502  while (KillInst != opBlock.begin()) {
503  --KillInst;
504  if (KillInst->isDebugValue())
505  continue;
506  if (KillInst->readsRegister(SrcReg))
507  break;
508  }
509  } else {
510  // We just inserted this copy.
511  KillInst = std::prev(InsertPos);
512  }
513  }
514  assert(KillInst->readsRegister(SrcReg) &&
515  "Cannot find kill instruction");
516 
517  SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
518  SrcLI.removeSegment(LastUseIndex.getRegSlot(),
519  LIS->getMBBEndIdx(&opBlock));
520  }
521  }
522  }
523  }
524 
525  // Really delete the PHI instruction now, if it is not in the LoweredPHIs map.
526  if (reusedIncoming || !IncomingReg) {
527  if (LIS)
528  LIS->RemoveMachineInstrFromMaps(*MPhi);
529  MF.DeleteMachineInstr(MPhi);
530  }
531 }
532 
533 /// analyzePHINodes - Gather information about the PHI nodes in here. In
534 /// particular, we want to map the number of uses of a virtual register which is
535 /// used in a PHI node. We map that to the BB the vreg is coming from. This is
536 /// used later to determine when the vreg is killed in the BB.
537 ///
538 void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
539  for (const auto &MBB : MF)
540  for (const auto &BBI : MBB) {
541  if (!BBI.isPHI())
542  break;
543  for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
544  ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
545  BBI.getOperand(i).getReg())];
546  }
547 }
548 
549 bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
550  MachineBasicBlock &MBB,
551  MachineLoopInfo *MLI) {
552  if (MBB.empty() || !MBB.front().isPHI() || MBB.isEHPad())
553  return false; // Quick exit for basic blocks without PHIs.
554 
555  const MachineLoop *CurLoop = MLI ? MLI->getLoopFor(&MBB) : nullptr;
556  bool IsLoopHeader = CurLoop && &MBB == CurLoop->getHeader();
557 
558  bool Changed = false;
559  for (MachineBasicBlock::iterator BBI = MBB.begin(), BBE = MBB.end();
560  BBI != BBE && BBI->isPHI(); ++BBI) {
561  for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
562  unsigned Reg = BBI->getOperand(i).getReg();
563  MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
564  // Is there a critical edge from PreMBB to MBB?
565  if (PreMBB->succ_size() == 1)
566  continue;
567 
568  // Avoid splitting backedges of loops. It would introduce small
569  // out-of-line blocks into the loop which is very bad for code placement.
570  if (PreMBB == &MBB && !SplitAllCriticalEdges)
571  continue;
572  const MachineLoop *PreLoop = MLI ? MLI->getLoopFor(PreMBB) : nullptr;
573  if (IsLoopHeader && PreLoop == CurLoop && !SplitAllCriticalEdges)
574  continue;
575 
576  // LV doesn't consider a phi use live-out, so isLiveOut only returns true
577  // when the source register is live-out for some other reason than a phi
578  // use. That means the copy we will insert in PreMBB won't be a kill, and
579  // there is a risk it may not be coalesced away.
580  //
581  // If the copy would be a kill, there is no need to split the edge.
582  bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
583  if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
584  continue;
585  if (ShouldSplit) {
586  DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
587  << PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
588  << ": " << *BBI);
589  }
590 
591  // If Reg is not live-in to MBB, it means it must be live-in to some
592  // other PreMBB successor, and we can avoid the interference by splitting
593  // the edge.
594  //
595  // If Reg *is* live-in to MBB, the interference is inevitable and a copy
596  // is likely to be left after coalescing. If we are looking at a loop
597  // exiting edge, split it so we won't insert code in the loop, otherwise
598  // don't bother.
599  ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
600 
601  // Check for a loop exiting edge.
602  if (!ShouldSplit && CurLoop != PreLoop) {
603  DEBUG({
604  dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
605  if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
606  if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
607  });
608  // This edge could be entering a loop, exiting a loop, or it could be
609  // both: Jumping directly form one loop to the header of a sibling
610  // loop.
611  // Split unless this edge is entering CurLoop from an outer loop.
612  ShouldSplit = PreLoop && !PreLoop->contains(CurLoop);
613  }
614  if (!ShouldSplit && !SplitAllCriticalEdges)
615  continue;
616  if (!PreMBB->SplitCriticalEdge(&MBB, *this)) {
617  DEBUG(dbgs() << "Failed to split critical edge.\n");
618  continue;
619  }
620  Changed = true;
621  ++NumCriticalEdgesSplit;
622  }
623  }
624  return Changed;
625 }
626 
627 bool PHIElimination::isLiveIn(unsigned Reg, const MachineBasicBlock *MBB) {
628  assert((LV || LIS) &&
629  "isLiveIn() requires either LiveVariables or LiveIntervals");
630  if (LIS)
631  return LIS->isLiveInToMBB(LIS->getInterval(Reg), MBB);
632  else
633  return LV->isLiveIn(Reg, *MBB);
634 }
635 
636 bool PHIElimination::isLiveOutPastPHIs(unsigned Reg,
637  const MachineBasicBlock *MBB) {
638  assert((LV || LIS) &&
639  "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
640  // LiveVariables considers uses in PHIs to be in the predecessor basic block,
641  // so that a register used only in a PHI is not live out of the block. In
642  // contrast, LiveIntervals considers uses in PHIs to be on the edge rather than
643  // in the predecessor basic block, so that a register used only in a PHI is live
644  // out of the block.
645  if (LIS) {
646  const LiveInterval &LI = LIS->getInterval(Reg);
647  for (const MachineBasicBlock *SI : MBB->successors())
648  if (LI.liveAt(LIS->getMBBStartIdx(SI)))
649  return true;
650  return false;
651  } else {
652  return LV->isLiveOut(Reg, *MBB);
653  }
654 }
unsigned succ_size() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isEHPad() const
Returns true if the block is a landing pad.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
STATISTIC(NumFunctions,"Total number of functions")
size_t i
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, unsigned SrcReg)
findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...
phi node Eliminate PHI nodes for register false
static cl::opt< bool > DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), cl::Hidden, cl::desc("Disable critical edge splitting ""during PHI elimination"))
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
unsigned SplitAllCriticalEdges(Function &F, const CriticalEdgeSplittingOptions &Options=CriticalEdgeSplittingOptions())
Loop over all of the edges in the CFG, breaking critical edges as they are found. ...
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
static bool isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI)
isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:396
BlockT * getHeader() const
Definition: LoopInfo.h:102
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
iterator_range< succ_iterator > successors()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:786
iterator end()
Definition: LiveInterval.h:206
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
Definition: SlotIndexes.h:252
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
Definition: SlotIndexes.h:229
SlotIndexes pass.
Definition: SlotIndexes.h:323
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MachineBasicBlock * MBB
static cl::opt< bool > NoPhiElimLiveOutEarlyExit("no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden, cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."))
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
TargetInstrInfo - Interface to description of machine instruction set.
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
Represent the analysis usage information of a pass.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:109
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
unsigned getSubReg() const
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:376
void initializePHIEliminationPass(PassRegistry &)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
phi node elimination
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
INITIALIZE_PASS_BEGIN(PHIElimination,"phi-node-elimination","Eliminate PHI nodes for register allocation", false, false) INITIALIZE_PASS_END(PHIElimination
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
phi node Eliminate PHI nodes for register allocation
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
Definition: LiveInterval.h:367
#define I(x, y, z)
Definition: MD5.cpp:54
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:247
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P)
Split the critical edge from this block to the given successor block, and return the newly created bl...
static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, const MachineRegisterInfo *MRI)
isSourceDefinedByImplicitDef - Return true if all sources of the phi node are implicit_def's.
virtual const TargetInstrInfo * getInstrInfo() const
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
#define DEBUG(X)
Definition: Debug.h:100
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...