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AMDGPU
SIDefines.h
Go to the documentation of this file.
1
//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
4
//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#include "
llvm/MC/MCInstrDesc.h
"
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
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#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
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namespace
llvm {
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18
namespace
SIInstrFlags {
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// This needs to be kept in sync with the field bits in InstSI.
20
enum
: uint64_t {
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// Low bits - basic encoding information.
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SALU
= 1 << 0,
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VALU
= 1 << 1,
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// SALU instruction formats.
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SOP1
= 1 << 2,
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SOP2
= 1 << 3,
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SOPC
= 1 << 4,
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SOPK
= 1 << 5,
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SOPP
= 1 << 6,
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// VALU instruction formats.
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VOP1
= 1 << 7,
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VOP2
= 1 << 8,
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VOPC
= 1 << 9,
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// TODO: Should this be spilt into VOP3 a and b?
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VOP3
= 1 << 10,
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VINTRP
= 1 << 13,
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SDWA
= 1 << 14,
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DPP
= 1 << 15,
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// Memory instruction formats.
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MUBUF
= 1 << 16,
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MTBUF
= 1 << 17,
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SMRD
= 1 << 18,
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MIMG
= 1 << 19,
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EXP
= 1 << 20,
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FLAT
= 1 << 21,
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DS
= 1 << 22,
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// Pseudo instruction formats.
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VGPRSpill
= 1 << 23,
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SGPRSpill
= 1 << 24,
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// High bits - other information.
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VM_CNT
= UINT64_C(1) << 32,
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EXP_CNT
= UINT64_C(1) << 33,
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LGKM_CNT
= UINT64_C(1) << 34,
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WQM
= UINT64_C(1) << 35,
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DisableWQM
= UINT64_C(1) << 36,
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Gather4
= UINT64_C(1) << 37,
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SOPK_ZEXT
= UINT64_C(1) << 38,
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SCALAR_STORE
= UINT64_C(1) << 39,
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FIXED_SIZE
= UINT64_C(1) << 40,
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VOPAsmPrefer32Bit
= UINT64_C(1) << 41
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};
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// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
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// The result is true if any of these tests are true.
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enum
ClassFlags
{
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S_NAN
= 1 << 0,
// Signaling NaN
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Q_NAN
= 1 << 1,
// Quiet NaN
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N_INFINITY
= 1 << 2,
// Negative infinity
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N_NORMAL
= 1 << 3,
// Negative normal
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N_SUBNORMAL
= 1 << 4,
// Negative subnormal
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N_ZERO
= 1 << 5,
// Negative zero
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P_ZERO
= 1 << 6,
// Positive zero
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P_SUBNORMAL
= 1 << 7,
// Positive subnormal
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P_NORMAL
= 1 << 8,
// Positive normal
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P_INFINITY
= 1 << 9
// Positive infinity
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};
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}
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namespace
AMDGPU {
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enum
OperandType
{
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/// Operands with register or 32-bit immediate
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OPERAND_REG_IMM_INT32
=
MCOI::OPERAND_FIRST_TARGET
,
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OPERAND_REG_IMM_INT64
,
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OPERAND_REG_IMM_INT16
,
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OPERAND_REG_IMM_FP32
,
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OPERAND_REG_IMM_FP64
,
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OPERAND_REG_IMM_FP16
,
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/// Operands with register or inline constant
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OPERAND_REG_INLINE_C_INT16
,
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OPERAND_REG_INLINE_C_INT32
,
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OPERAND_REG_INLINE_C_INT64
,
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OPERAND_REG_INLINE_C_FP16
,
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OPERAND_REG_INLINE_C_FP32
,
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OPERAND_REG_INLINE_C_FP64
,
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OPERAND_REG_IMM_FIRST
=
OPERAND_REG_IMM_INT32
,
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OPERAND_REG_IMM_LAST
=
OPERAND_REG_IMM_FP16
,
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OPERAND_REG_INLINE_C_FIRST
=
OPERAND_REG_INLINE_C_INT16
,
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OPERAND_REG_INLINE_C_LAST
=
OPERAND_REG_INLINE_C_FP64
,
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OPERAND_SRC_FIRST
=
OPERAND_REG_IMM_INT32
,
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OPERAND_SRC_LAST
=
OPERAND_REG_INLINE_C_LAST
,
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// Operand for source modifiers for VOP instructions
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OPERAND_INPUT_MODS
,
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/// Operand with 32-bit immediate that uses the constant bus.
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OPERAND_KIMM32
,
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OPERAND_KIMM16
121
};
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}
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// Input operand modifiers bit-masks
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// NEG and SEXT share same bit-mask because they can't be set simultaneously.
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namespace
SISrcMods {
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enum
{
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NEG
= 1 << 0,
// Floating-point negate modifier
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ABS
= 1 << 1,
// Floating-point absolute modifier
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SEXT
= 1 << 0
// Integer sign-extend modifier
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};
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}
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namespace
SIOutMods {
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enum
{
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NONE
= 0,
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MUL2
= 1,
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MUL4
= 2,
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DIV2
= 3
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};
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}
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143
namespace
VGPRIndexMode {
144
enum
{
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SRC0_ENABLE
= 1 << 0,
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SRC1_ENABLE
= 1 << 1,
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SRC2_ENABLE
= 1 << 2,
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DST_ENABLE
= 1 << 3
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};
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}
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namespace
AMDGPUAsmVariants {
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enum
{
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DEFAULT
= 0,
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VOP3
= 1,
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SDWA
= 2,
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DPP
= 3
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};
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}
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namespace
AMDGPU {
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namespace
EncValues {
// Encoding values of enum9/8/7 operands
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enum
{
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SGPR_MIN
= 0,
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SGPR_MAX
= 101,
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TTMP_MIN
= 112,
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TTMP_MAX
= 123,
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INLINE_INTEGER_C_MIN
= 128,
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INLINE_INTEGER_C_POSITIVE_MAX
= 192,
// 64
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INLINE_INTEGER_C_MAX
= 208,
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INLINE_FLOATING_C_MIN
= 240,
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INLINE_FLOATING_C_MAX
= 248,
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LITERAL_CONST
= 255,
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VGPR_MIN
= 256,
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VGPR_MAX
= 511
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};
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}
// namespace EncValues
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}
// namespace AMDGPU
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namespace
AMDGPU {
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namespace
SendMsg {
// Encoding of SIMM16 used in s_sendmsg* insns.
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enum
Id
{
// Message ID, width(4) [3:0].
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ID_UNKNOWN_
= -1,
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ID_INTERRUPT
= 1,
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ID_GS
,
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ID_GS_DONE
,
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ID_SYSMSG
= 15,
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ID_GAPS_LAST_
,
// Indicate that sequence has gaps.
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ID_GAPS_FIRST_
=
ID_INTERRUPT
,
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ID_SHIFT_
= 0,
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ID_WIDTH_
= 4,
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ID_MASK_
= (((1 <<
ID_WIDTH_
) - 1) <<
ID_SHIFT_
)
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};
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enum
Op
{
// Both GS and SYS operation IDs.
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OP_UNKNOWN_
= -1,
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OP_SHIFT_
= 4,
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// width(2) [5:4]
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OP_GS_NOP
= 0,
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OP_GS_CUT
,
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OP_GS_EMIT
,
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OP_GS_EMIT_CUT
,
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OP_GS_LAST_
,
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OP_GS_FIRST_
=
OP_GS_NOP
,
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OP_GS_WIDTH_
= 2,
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OP_GS_MASK_
= (((1 <<
OP_GS_WIDTH_
) - 1) <<
OP_SHIFT_
),
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// width(3) [6:4]
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OP_SYS_ECC_ERR_INTERRUPT
= 1,
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OP_SYS_REG_RD
,
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OP_SYS_HOST_TRAP_ACK
,
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OP_SYS_TTRACE_PC
,
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OP_SYS_LAST_
,
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OP_SYS_FIRST_
=
OP_SYS_ECC_ERR_INTERRUPT
,
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OP_SYS_WIDTH_
= 3,
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OP_SYS_MASK_
= (((1 <<
OP_SYS_WIDTH_
) - 1) <<
OP_SHIFT_
)
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};
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enum
StreamId
{
// Stream ID, (2) [9:8].
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STREAM_ID_DEFAULT_
= 0,
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STREAM_ID_LAST_
= 4,
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STREAM_ID_FIRST_
=
STREAM_ID_DEFAULT_
,
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STREAM_ID_SHIFT_
= 8,
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STREAM_ID_WIDTH_
= 2,
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STREAM_ID_MASK_
= (((1 <<
STREAM_ID_WIDTH_
) - 1) <<
STREAM_ID_SHIFT_
)
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};
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}
// namespace SendMsg
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namespace
Hwreg {
// Encoding of SIMM16 used in s_setreg/getreg* insns.
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enum
Id
{
// HwRegCode, (6) [5:0]
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ID_UNKNOWN_
= -1,
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ID_SYMBOLIC_FIRST_
= 1,
// There are corresponding symbolic names defined.
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ID_MODE
= 1,
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ID_STATUS
= 2,
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ID_TRAPSTS
= 3,
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ID_HW_ID
= 4,
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ID_GPR_ALLOC
= 5,
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ID_LDS_ALLOC
= 6,
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ID_IB_STS
= 7,
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ID_SYMBOLIC_LAST_
= 8,
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ID_SHIFT_
= 0,
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ID_WIDTH_
= 6,
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ID_MASK_
= (((1 <<
ID_WIDTH_
) - 1) <<
ID_SHIFT_
)
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};
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enum
Offset
{
// Offset, (5) [10:6]
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OFFSET_DEFAULT_
= 0,
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OFFSET_SHIFT_
= 6,
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OFFSET_WIDTH_
= 5,
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OFFSET_MASK_
= (((1 <<
OFFSET_WIDTH_
) - 1) <<
OFFSET_SHIFT_
)
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};
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enum
WidthMinusOne
{
// WidthMinusOne, (5) [15:11]
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WIDTH_M1_DEFAULT_
= 31,
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WIDTH_M1_SHIFT_
= 11,
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WIDTH_M1_WIDTH_
= 5,
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WIDTH_M1_MASK_
= (((1 <<
WIDTH_M1_WIDTH_
) - 1) <<
WIDTH_M1_SHIFT_
)
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};
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}
// namespace Hwreg
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266
namespace
SDWA
{
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enum
SdwaSel
{
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BYTE_0
= 0,
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BYTE_1
= 1,
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BYTE_2
= 2,
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BYTE_3
= 3,
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WORD_0
= 4,
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WORD_1
= 5,
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DWORD
= 6,
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};
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enum
DstUnused
{
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UNUSED_PAD
= 0,
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UNUSED_SEXT
= 1,
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UNUSED_PRESERVE
= 2,
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};
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}
// namespace SDWA
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}
// namespace AMDGPU
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#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
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#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
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#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
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#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
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#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
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#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
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#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
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#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
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#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
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#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
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#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
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#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
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#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
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#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
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#define C_00B84C_USER_SGPR 0xFFFFFFC1
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#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
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#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
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#define C_00B84C_TGID_X_EN 0xFFFFFF7F
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#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
307
#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
308
#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
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#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
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#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
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#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
312
#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
313
#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
314
#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
315
#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
316
#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
317
#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
318
/* CIK */
319
#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
320
#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
321
#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
322
/* */
323
#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
324
#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
325
#define C_00B84C_LDS_SIZE 0xFF007FFF
326
#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
327
#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
328
#define C_00B84C_EXCP_EN
329
330
#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
331
#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
332
333
#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
334
#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
335
#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
336
#define C_00B848_VGPRS 0xFFFFFFC0
337
#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
338
#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
339
#define C_00B848_SGPRS 0xFFFFFC3F
340
#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
341
#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
342
#define C_00B848_PRIORITY 0xFFFFF3FF
343
#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
344
#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
345
#define C_00B848_FLOAT_MODE 0xFFF00FFF
346
#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
347
#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
348
#define C_00B848_PRIV 0xFFEFFFFF
349
#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
350
#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
351
#define C_00B848_DX10_CLAMP 0xFFDFFFFF
352
#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
353
#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
354
#define C_00B848_DEBUG_MODE 0xFFBFFFFF
355
#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
356
#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
357
#define C_00B848_IEEE_MODE 0xFF7FFFFF
358
359
360
// Helpers for setting FLOAT_MODE
361
#define FP_ROUND_ROUND_TO_NEAREST 0
362
#define FP_ROUND_ROUND_TO_INF 1
363
#define FP_ROUND_ROUND_TO_NEGINF 2
364
#define FP_ROUND_ROUND_TO_ZERO 3
365
366
// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
367
// precision.
368
#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
369
#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
370
371
#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
372
#define FP_DENORM_FLUSH_OUT 1
373
#define FP_DENORM_FLUSH_IN 2
374
#define FP_DENORM_FLUSH_NONE 3
375
376
377
// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
378
// precision.
379
#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
380
#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
381
382
#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
383
#define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12)
384
385
#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
386
#define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12)
387
388
#define R_SPILLED_SGPRS 0x4
389
#define R_SPILLED_VGPRS 0x8
390
391
}
// End namespace llvm
392
393
#endif
llvm::AMDGPU::Hwreg::WidthMinusOne
WidthMinusOne
Definition:
SIDefines.h:257
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
Definition:
SIDefines.h:216
llvm::SIInstrFlags::VOPC
Definition:
SIDefines.h:35
llvm::SIInstrFlags::P_INFINITY
Definition:
SIDefines.h:84
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
Definition:
SIDefines.h:109
llvm::AMDGPU::Hwreg::ID_LDS_ALLOC
Definition:
SIDefines.h:242
llvm::AMDGPU::OPERAND_KIMM16
Definition:
SIDefines.h:120
llvm::AMDGPU::EncValues::SGPR_MIN
Definition:
SIDefines.h:165
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
Definition:
SIDefines.h:102
llvm::AMDGPU::SendMsg::OP_GS_MASK_
Definition:
SIDefines.h:209
llvm::SIInstrFlags::MUBUF
Definition:
SIDefines.h:45
llvm::SIInstrFlags::VOPAsmPrefer32Bit
Definition:
SIDefines.h:68
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
Definition:
SIDefines.h:199
llvm::AMDGPU::SendMsg::ID_INTERRUPT
Definition:
SIDefines.h:187
llvm::SIInstrFlags::SALU
Definition:
SIDefines.h:22
llvm::SIInstrFlags::EXP_CNT
Definition:
SIDefines.h:59
llvm::AMDGPU::SendMsg::OP_SYS_WIDTH_
Definition:
SIDefines.h:217
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX
Definition:
SIDefines.h:170
llvm::SIInstrFlags::DisableWQM
Definition:
SIDefines.h:63
llvm::AMDGPU::OPERAND_REG_IMM_INT64
Definition:
SIDefines.h:92
llvm::AMDGPU::Hwreg::OFFSET_WIDTH_
Definition:
SIDefines.h:253
llvm::SIInstrFlags::SMRD
Definition:
SIDefines.h:47
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
Definition:
SIDefines.h:101
llvm::AMDGPU::SDWA::BYTE_0
Definition:
SIDefines.h:269
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN
Definition:
SIDefines.h:169
llvm::SIInstrFlags::WQM
Definition:
SIDefines.h:62
llvm::AMDGPU::SendMsg::OP_GS_NOP
Definition:
SIDefines.h:202
llvm::AMDGPU::SendMsg::STREAM_ID_DEFAULT_
Definition:
SIDefines.h:222
llvm::AMDGPU::SendMsg::OP_SYS_MASK_
Definition:
SIDefines.h:218
llvm::SIInstrFlags::N_SUBNORMAL
Definition:
SIDefines.h:79
llvm::SIInstrFlags::VOP1
Definition:
SIDefines.h:33
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
Definition:
SIDefines.h:224
llvm::AMDGPU::EncValues::LITERAL_CONST
Definition:
SIDefines.h:174
llvm::AMDGPU::SendMsg::ID_GS
Definition:
SIDefines.h:188
llvm::AMDGPUAsmVariants::DEFAULT
Definition:
SIDefines.h:154
llvm::SIInstrFlags::P_NORMAL
Definition:
SIDefines.h:83
llvm::AMDGPU::Hwreg::WIDTH_M1_DEFAULT_
Definition:
SIDefines.h:258
llvm::SIInstrFlags::VGPRSpill
Definition:
SIDefines.h:54
llvm::SIInstrFlags::MIMG
Definition:
SIDefines.h:48
llvm::SIInstrFlags::VOP3
Definition:
SIDefines.h:38
llvm::AMDGPU::SendMsg::OP_SYS_TTRACE_PC
Definition:
SIDefines.h:214
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX
Definition:
SIDefines.h:173
llvm::SIInstrFlags::SOPK
Definition:
SIDefines.h:29
llvm::AMDGPU::OPERAND_SRC_LAST
Definition:
SIDefines.h:113
llvm::AMDGPU::Hwreg::WIDTH_M1_WIDTH_
Definition:
SIDefines.h:260
llvm::AMDGPU::SendMsg::Id
Id
Definition:
SIDefines.h:185
llvm::SIInstrFlags::VINTRP
Definition:
SIDefines.h:40
llvm::AMDGPU::SendMsg::ID_UNKNOWN_
Definition:
SIDefines.h:186
llvm::MCOI::OPERAND_FIRST_TARGET
Definition:
MCInstrDesc.h:60
llvm::AMDGPU::Hwreg::ID_STATUS
Definition:
SIDefines.h:238
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
Definition:
SIDefines.h:110
llvm::AMDGPU::Hwreg::ID_MODE
Definition:
SIDefines.h:237
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
Definition:
SIDefines.h:104
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
Definition:
SIDefines.h:100
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN
Definition:
SIDefines.h:172
llvm::AMDGPU::EncValues::VGPR_MIN
Definition:
SIDefines.h:175
llvm::SIInstrFlags::FLAT
Definition:
SIDefines.h:50
llvm::VGPRIndexMode::SRC2_ENABLE
Definition:
SIDefines.h:147
llvm::AMDGPU::Hwreg::ID_GPR_ALLOC
Definition:
SIDefines.h:241
llvm::SIInstrFlags::EXP
Definition:
SIDefines.h:49
llvm::SIInstrFlags::Q_NAN
Definition:
SIDefines.h:76
llvm::AMDGPU::SendMsg::ID_GS_DONE
Definition:
SIDefines.h:189
llvm::SISrcMods::SEXT
Definition:
SIDefines.h:130
llvm::AMDGPUAsmVariants::DPP
Definition:
SIDefines.h:157
llvm::AMDGPU::SendMsg::OP_GS_EMIT_CUT
Definition:
SIDefines.h:205
llvm::AMDGPU::OPERAND_REG_IMM_LAST
Definition:
SIDefines.h:107
llvm::AMDGPU::SendMsg::OP_GS_CUT
Definition:
SIDefines.h:203
llvm::AMDGPU::EncValues::SGPR_MAX
Definition:
SIDefines.h:166
llvm::AMDGPU::SDWA::BYTE_1
Definition:
SIDefines.h:270
llvm::SIOutMods::DIV2
Definition:
SIDefines.h:139
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
Definition:
SIDefines.h:227
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
Definition:
SIDefines.h:252
llvm::AMDGPU::SDWA::DstUnused
DstUnused
Definition:
SIDefines.h:278
llvm::AMDGPU::OPERAND_REG_IMM_FIRST
Definition:
SIDefines.h:106
llvm::SIInstrFlags::P_SUBNORMAL
Definition:
SIDefines.h:82
llvm::AMDGPU::OPERAND_REG_IMM_INT16
Definition:
SIDefines.h:93
llvm::SIInstrFlags::SOPP
Definition:
SIDefines.h:30
llvm::SISrcMods::ABS
Definition:
SIDefines.h:129
llvm::AMDGPU::SendMsg::OP_SYS_HOST_TRAP_ACK
Definition:
SIDefines.h:213
llvm::AMDGPU::EncValues::VGPR_MAX
Definition:
SIDefines.h:176
llvm::AMDGPU::SendMsg::OP_GS_WIDTH_
Definition:
SIDefines.h:208
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX
Definition:
SIDefines.h:171
llvm::SIInstrFlags::N_NORMAL
Definition:
SIDefines.h:78
llvm::AMDGPU::OPERAND_REG_IMM_FP64
Definition:
SIDefines.h:95
llvm::AMDGPU::EncValues::TTMP_MAX
Definition:
SIDefines.h:168
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
Definition:
SIDefines.h:259
llvm::AMDGPU::OPERAND_INPUT_MODS
Definition:
SIDefines.h:116
llvm::AMDGPUAsmVariants::VOP3
Definition:
SIDefines.h:155
llvm::SIInstrFlags::MTBUF
Definition:
SIDefines.h:46
llvm::AMDGPU::SendMsg::ID_GAPS_LAST_
Definition:
SIDefines.h:191
llvm::SIInstrFlags::SOP2
Definition:
SIDefines.h:27
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_LAST_
Definition:
SIDefines.h:244
llvm::AMDGPU::Hwreg::ID_TRAPSTS
Definition:
SIDefines.h:239
llvm::SIOutMods::NONE
Definition:
SIDefines.h:136
llvm::SIInstrFlags::Gather4
Definition:
SIDefines.h:64
llvm::VGPRIndexMode::SRC0_ENABLE
Definition:
SIDefines.h:145
llvm::SIOutMods::MUL2
Definition:
SIDefines.h:137
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition:
SIDefines.h:99
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
Definition:
SIDefines.h:261
llvm::SIInstrFlags::SOP1
Definition:
SIDefines.h:26
llvm::SIInstrFlags::S_NAN
Definition:
SIDefines.h:75
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
Definition:
SIDefines.h:207
llvm::AMDGPU::Hwreg::Offset
Offset
Definition:
SIDefines.h:250
llvm::SIInstrFlags::FIXED_SIZE
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SIDefines.h:67
llvm::AMDGPU::SendMsg::OP_GS_LAST_
Definition:
SIDefines.h:206
llvm::AMDGPU::SDWA::SdwaSel
SdwaSel
Definition:
SIDefines.h:268
llvm::SIInstrFlags::SGPRSpill
Definition:
SIDefines.h:55
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition:
SIDefines.h:221
llvm::VGPRIndexMode::SRC1_ENABLE
Definition:
SIDefines.h:146
llvm::AMDGPU::SendMsg::ID_WIDTH_
Definition:
SIDefines.h:194
llvm::SIInstrFlags::N_ZERO
Definition:
SIDefines.h:80
llvm::SIInstrFlags::P_ZERO
Definition:
SIDefines.h:81
llvm::SIInstrFlags::SCALAR_STORE
Definition:
SIDefines.h:66
llvm::SIInstrFlags::SOPK_ZEXT
Definition:
SIDefines.h:65
llvm::AMDGPU::EncValues::TTMP_MIN
Definition:
SIDefines.h:167
llvm::AMDGPU::SendMsg::ID_SHIFT_
Definition:
SIDefines.h:193
llvm::SIInstrFlags::SDWA
Definition:
SIDefines.h:41
llvm::SIInstrFlags::VOP2
Definition:
SIDefines.h:34
llvm::AMDGPU::SendMsg::OP_SYS_ECC_ERR_INTERRUPT
Definition:
SIDefines.h:211
llvm::AMDGPU::SDWA::UNUSED_PAD
Definition:
SIDefines.h:279
llvm::AMDGPU::SDWA::BYTE_2
Definition:
SIDefines.h:271
llvm::SIOutMods::MUL4
Definition:
SIDefines.h:138
llvm::AMDGPU::OperandType
OperandType
Definition:
SIDefines.h:89
llvm::SIInstrFlags::DS
Definition:
SIDefines.h:51
llvm::AMDGPU::Hwreg::Id
Id
Definition:
SIDefines.h:234
llvm::SISrcMods::NEG
Definition:
SIDefines.h:128
llvm::SIInstrFlags::N_INFINITY
Definition:
SIDefines.h:77
llvm::AMDGPU::Hwreg::ID_SYMBOLIC_FIRST_
Definition:
SIDefines.h:236
llvm::AMDGPU::SDWA::UNUSED_SEXT
Definition:
SIDefines.h:280
llvm::AMDGPUAsmVariants::SDWA
Definition:
SIDefines.h:156
llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_
Definition:
SIDefines.h:251
llvm::AMDGPU::OPERAND_SRC_FIRST
Definition:
SIDefines.h:112
llvm::SIInstrFlags::DPP
Definition:
SIDefines.h:42
llvm::AMDGPU::SendMsg::ID_MASK_
Definition:
SIDefines.h:195
llvm::AMDGPU::Hwreg::ID_IB_STS
Definition:
SIDefines.h:243
llvm::AMDGPU::SDWA::BYTE_3
Definition:
SIDefines.h:272
llvm::AMDGPU::OPERAND_REG_IMM_FP16
Definition:
SIDefines.h:96
llvm::AMDGPU::OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition:
SIDefines.h:91
llvm::AMDGPU::SendMsg::STREAM_ID_WIDTH_
Definition:
SIDefines.h:226
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
Definition:
SIDefines.h:223
llvm::AMDGPU::Hwreg::OFFSET_MASK_
Definition:
SIDefines.h:254
llvm::AMDGPU::SendMsg::OP_GS_EMIT
Definition:
SIDefines.h:204
llvm::AMDGPU::OPERAND_REG_IMM_FP32
Definition:
SIDefines.h:94
llvm::AMDGPU::SDWA::DWORD
Definition:
SIDefines.h:275
llvm::AMDGPU::OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition:
SIDefines.h:119
llvm::SIInstrFlags::VALU
Definition:
SIDefines.h:23
llvm::AMDGPU::SendMsg::OP_SYS_REG_RD
Definition:
SIDefines.h:212
llvm::AMDGPU::SendMsg::Op
Op
Definition:
SIDefines.h:198
llvm::AMDGPU::SendMsg::ID_SYSMSG
Definition:
SIDefines.h:190
llvm::AMDGPU::SendMsg::OP_SHIFT_
Definition:
SIDefines.h:200
MCInstrDesc.h
llvm::SIInstrFlags::LGKM_CNT
Definition:
SIDefines.h:60
llvm::AMDGPU::SendMsg::ID_GAPS_FIRST_
Definition:
SIDefines.h:192
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
Definition:
SIDefines.h:215
llvm::SIInstrFlags::ClassFlags
ClassFlags
Definition:
SIDefines.h:74
llvm::SIInstrFlags::VM_CNT
Definition:
SIDefines.h:58
llvm::AMDGPU::SDWA::WORD_0
Definition:
SIDefines.h:273
llvm::AMDGPU::SDWA::UNUSED_PRESERVE
Definition:
SIDefines.h:281
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
Definition:
SIDefines.h:225
llvm::VGPRIndexMode::DST_ENABLE
Definition:
SIDefines.h:148
llvm::SIInstrFlags::SOPC
Definition:
SIDefines.h:28
llvm::AMDGPU::SDWA::WORD_1
Definition:
SIDefines.h:274
llvm::AMDGPU::Hwreg::ID_HW_ID
Definition:
SIDefines.h:240
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
Definition:
SIDefines.h:103
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