28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "LanaiGenInstrInfo.inc"
38 unsigned DestinationRegister,
39 unsigned SourceRegister,
40 bool KillSource)
const {
41 if (!Lanai::GPRRegClass.
contains(DestinationRegister, SourceRegister)) {
45 BuildMI(MBB, Position, DL,
get(Lanai::OR_I_LO), DestinationRegister)
52 unsigned SourceRegister,
bool IsKill,
int FrameIndex,
56 if (Position != MBB.
end()) {
57 DL = Position->getDebugLoc();
60 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
63 BuildMI(MBB, Position, DL,
get(Lanai::SW_RI))
76 if (Position != MBB.
end()) {
77 DL = Position->getDebugLoc();
80 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) {
83 BuildMI(MBB, Position, DL,
get(Lanai::LDW_RI), DestinationRegister)
104 unsigned BaseRegA = 0, BaseRegB = 0;
105 int64_t OffsetA = 0, OffsetB = 0;
106 unsigned int WidthA = 0, WidthB = 0;
109 if (BaseRegA == BaseRegB) {
110 int LowOffset =
std::min(OffsetA, OffsetB);
111 int HighOffset = std::max(OffsetA, OffsetB);
112 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
113 if (LowOffset + LowWidth <= HighOffset)
163 std::pair<unsigned, unsigned>
165 return std::make_pair(TF, 0u);
170 using namespace LanaiII;
171 static const std::pair<unsigned, const char *>
TargetFlags[] = {
179 unsigned &SrcReg2,
int &CmpMask,
180 int &CmpValue)
const {
184 case Lanai::SFSUB_F_RI_LO:
185 case Lanai::SFSUB_F_RI_HI:
191 case Lanai::SFSUB_F_RR:
207 unsigned SrcReg2,
int ImmValue,
209 if (CmpI->
getOpcode() == Lanai::SFSUB_F_RR &&
217 if (((CmpI->
getOpcode() == Lanai::SFSUB_F_RI_LO &&
219 (CmpI->
getOpcode() == Lanai::SFSUB_F_RI_HI &&
229 case Lanai::ADD_I_HI:
230 return Lanai::ADD_F_I_HI;
231 case Lanai::ADD_I_LO:
232 return Lanai::ADD_F_I_LO;
234 return Lanai::ADD_F_R;
235 case Lanai::ADDC_I_HI:
236 return Lanai::ADDC_F_I_HI;
237 case Lanai::ADDC_I_LO:
238 return Lanai::ADDC_F_I_LO;
240 return Lanai::ADDC_F_R;
241 case Lanai::AND_I_HI:
242 return Lanai::AND_F_I_HI;
243 case Lanai::AND_I_LO:
244 return Lanai::AND_F_I_LO;
246 return Lanai::AND_F_R;
248 return Lanai::OR_F_I_HI;
250 return Lanai::OR_F_I_LO;
252 return Lanai::OR_F_R;
254 return Lanai::SL_F_I;
256 return Lanai::SRL_F_R;
258 return Lanai::SA_F_I;
260 return Lanai::SRA_F_R;
261 case Lanai::SUB_I_HI:
262 return Lanai::SUB_F_I_HI;
263 case Lanai::SUB_I_LO:
264 return Lanai::SUB_F_I_LO;
266 return Lanai::SUB_F_R;
267 case Lanai::SUBB_I_HI:
268 return Lanai::SUBB_F_I_HI;
269 case Lanai::SUBB_I_LO:
270 return Lanai::SUBB_F_I_LO;
272 return Lanai::SUBB_F_R;
273 case Lanai::XOR_I_HI:
274 return Lanai::XOR_F_I_HI;
275 case Lanai::XOR_I_LO:
276 return Lanai::XOR_F_I_LO;
278 return Lanai::XOR_F_R;
285 MachineInstr &CmpInstr,
unsigned SrcReg,
unsigned SrcReg2,
int ,
312 if (CmpInstr.
getOpcode() == Lanai::SFSUB_F_RI_LO)
321 for (--I; I !=
E; --
I) {
356 while (!isSafe && ++I != E) {
358 for (
unsigned IO = 0, EO = Instr.
getNumOperands(); !isSafe && IO != EO;
386 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
425 if ((*SI)->isLiveIn(Lanai::SR))
441 unsigned &TrueOp,
unsigned &FalseOp,
442 bool &Optimizable)
const {
487 bool DontMoveAcrossStores =
true;
500 bool Invert = !DefMI;
510 if (!MRI.constrainRegClass(DestReg, PreviousClass))
519 for (
unsigned i = 1, e = DefDesc.getNumOperands();
520 i != e && !DefDesc.OpInfo[
i].isPredicate(); ++
i)
539 SeenMIs.
erase(DefMI);
567 bool AllowModify)
const {
573 while (Instruction != MBB.
begin()) {
577 if (Instruction->isDebugValue())
582 if (!isUnpredicatedTerminator(*Instruction))
587 if (!Instruction->isBranch())
591 if (Instruction->getOpcode() ==
Lanai::BT) {
593 TrueBlock = Instruction->getOperand(0).getMBB();
598 while (std::next(Instruction) != MBB.
end()) {
599 std::next(Instruction)->eraseFromParent();
603 FalseBlock =
nullptr;
608 Instruction->eraseFromParent();
609 Instruction = MBB.
end();
614 TrueBlock = Instruction->getOperand(0).getMBB();
619 unsigned Opcode = Instruction->getOpcode();
620 if (Opcode != Lanai::BRCC)
625 if (Condition.
empty()) {
630 FalseBlock = TrueBlock;
631 TrueBlock = Instruction->getOperand(0).getMBB();
650 "Lanai branch conditions should have one component.");
666 int *BytesAdded)
const {
668 assert(TrueBlock &&
"insertBranch must not be told to insert a fallthrough");
669 assert(!BytesAdded &&
"code size not handled");
672 if (Condition.
empty()) {
673 assert(!FalseBlock &&
"Unconditional branch with multiple successors!");
680 "Lanai branch conditions should have one component.");
681 unsigned ConditionalCode = Condition[0].getImm();
694 int *BytesRemoved)
const {
695 assert(!BytesRemoved &&
"code size not handled");
700 while (Instruction != MBB.
begin()) {
702 if (Instruction->isDebugValue())
704 if (Instruction->getOpcode() !=
Lanai::BT &&
705 Instruction->getOpcode() != Lanai::BRCC) {
710 Instruction->eraseFromParent();
711 Instruction = MBB.
end();
737 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Describe properties that are true of each instruction in the target description file.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
return AArch64::GPR64RegClass contains(Reg)
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
void clearKillInfo()
Clears kill flags on all operands.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
A description of a memory reference used in the backend.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool expandPostRAPseudo(MachineInstr &MI) const override
static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Condition) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
size_t size() const
size - Get the array size.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool PreferFalse) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual const LanaiRegisterInfo & getRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
const MachineOperand & getOperand(unsigned i) const
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool empty() const
empty - Check if the array is empty.
succ_iterator succ_begin()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
static LPCC::CondCode getOppositeCondition(LPCC::CondCode CC)
MachineOperand class - Representation of each machine instruction operand.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const override
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Select(COND, TRUEVAL, FALSEVAL).
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachineInstr * canFoldIntoSelect(unsigned Reg, const MachineRegisterInfo &MRI)
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static unsigned flagSettingOpcodeVariant(unsigned OldOpcode)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const override
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, unsigned DestinationRegister, unsigned SourceRegister, bool KillSource) const override
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.