|
LLVM
4.0.0
|
#include <ARMSubtarget.h>
Public Types | |
| enum | ARMLdStMultipleTiming { DoubleIssue, DoubleIssueCheckUnalignedAccess, SingleIssue, SingleIssuePlusExtras } |
| What kind of timing do load multiple/store multiple instructions have. More... | |
Protected Types | |
| enum | ARMProcFamilyEnum { Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexR52, CortexM3, CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73, Krait, Swift, ExynosM1 } |
| enum | ARMProcClassEnum { None, AClass, RClass, MClass } |
| enum | ARMArchEnum { ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline, ARMv8r } |
Protected Attributes | |
| ARMProcFamilyEnum | ARMProcFamily = Others |
| ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. More... | |
| ARMProcClassEnum | ARMProcClass = None |
| ARMProcClass - ARM processor class: None, AClass, RClass or MClass. More... | |
| ARMArchEnum | ARMArch = ARMv4t |
| ARMArch - ARM architecture. More... | |
| bool | HasV4TOps = false |
| HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants. More... | |
| bool | HasV5TOps = false |
| bool | HasV5TEOps = false |
| bool | HasV6Ops = false |
| bool | HasV6MOps = false |
| bool | HasV6KOps = false |
| bool | HasV6T2Ops = false |
| bool | HasV7Ops = false |
| bool | HasV8Ops = false |
| bool | HasV8_1aOps = false |
| bool | HasV8_2aOps = false |
| bool | HasV8MBaselineOps = false |
| bool | HasV8MMainlineOps = false |
| bool | HasVFPv2 = false |
| HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported. More... | |
| bool | HasVFPv3 = false |
| bool | HasVFPv4 = false |
| bool | HasFPARMv8 = false |
| bool | HasNEON = false |
| bool | UseNEONForSinglePrecisionFP = false |
| UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified. More... | |
| bool | UseMulOps = false |
| UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used. More... | |
| bool | SlowFPVMLx = false |
| SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them). More... | |
| bool | HasVMLxForwarding = false |
| HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back. More... | |
| bool | SlowFPBrcc = false |
| SlowFPBrcc - True if floating point compare + branch is slow. More... | |
| bool | InThumbMode = false |
| InThumbMode - True if compiling for Thumb, false for ARM. More... | |
| bool | UseSoftFloat = false |
| UseSoftFloat - True if we're using software floating point features. More... | |
| bool | HasThumb2 = false |
| HasThumb2 - True if Thumb2 instructions are supported. More... | |
| bool | NoARM = false |
| NoARM - True if subtarget does not support ARM mode execution. More... | |
| bool | ReserveR9 = false |
| ReserveR9 - True if R9 is not available as a general purpose register. More... | |
| bool | NoMovt = false |
| NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global addresses). More... | |
| bool | SupportsTailCall = false |
| SupportsTailCall - True if the OS supports tail call. More... | |
| bool | HasFP16 = false |
| HasFP16 - True if subtarget supports half-precision FP conversions. More... | |
| bool | HasFullFP16 = false |
| HasFullFP16 - True if subtarget supports half-precision FP operations. More... | |
| bool | HasD16 = false |
| HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3. More... | |
| bool | HasHardwareDivide = false |
| HasHardwareDivide - True if subtarget supports [su]div. More... | |
| bool | HasHardwareDivideInARM = false |
| HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode. More... | |
| bool | HasT2ExtractPack = false |
| HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions. More... | |
| bool | HasDataBarrier = false |
| HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions. More... | |
| bool | HasV7Clrex = false |
| HasV7Clrex - True if the subtarget supports CLREX instructions. More... | |
| bool | HasAcquireRelease = false |
| HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions. More... | |
| bool | Pref32BitThumb = false |
| Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones. More... | |
| bool | AvoidCPSRPartialUpdate = false |
| AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction. More... | |
| bool | AvoidMOVsShifterOperand = false |
| AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e. More... | |
| bool | HasRetAddrStack = false |
| HasRetAddrStack - Some processors perform return stack prediction. More... | |
| bool | HasMPExtension = false |
| HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only). More... | |
| bool | HasVirtualization = false |
| HasVirtualization - True if the subtarget supports the Virtualization extension. More... | |
| bool | FPOnlySP = false |
| FPOnlySP - If true, the floating point unit only supports single precision. More... | |
| bool | HasPerfMon = false |
| If true, the processor supports the Performance Monitor Extensions. More... | |
| bool | HasTrustZone = false |
| HasTrustZone - if true, processor supports TrustZone security extensions. More... | |
| bool | Has8MSecExt = false |
| Has8MSecExt - if true, processor supports ARMv8-M Security Extensions. More... | |
| bool | HasCrypto = false |
| HasCrypto - if true, processor supports Cryptography extensions. More... | |
| bool | HasCRC = false |
| HasCRC - if true, processor supports CRC instructions. More... | |
| bool | HasRAS = false |
| HasRAS - if true, the processor supports RAS extensions. More... | |
| bool | HasZeroCycleZeroing = false |
| If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register. More... | |
| bool | HasFPAO = false |
| HasFPAO - if true, processor does positive address offset computation faster. More... | |
| bool | IsProfitableToUnpredicate = false |
| If true, if conversion may decide to leave some instructions unpredicated. More... | |
| bool | HasSlowVGETLNi32 = false |
| If true, VMOV will be favored over VGETLNi32. More... | |
| bool | HasSlowVDUP32 = false |
| If true, VMOV will be favored over VDUP. More... | |
| bool | PreferVMOVSR = false |
| If true, VMOVSR will be favored over VMOVDRR. More... | |
| bool | PreferISHST = false |
| If true, ISHST barriers will be used for Release semantics. More... | |
| bool | SlowOddRegister = false |
| If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than single VLDRS/VSTRS. More... | |
| bool | SlowLoadDSubregister = false |
| If true, loading into a D subregister will be penalized. More... | |
| bool | HasMuxedUnits = false |
| If true, the AGU and NEON/FPU units are multiplexed. More... | |
| bool | DontWidenVMOVS = false |
| If true, VMOVS will never be widened to VMOVD. More... | |
| bool | ExpandMLx = false |
| If true, run the MLx expansion pass. More... | |
| bool | HasVMLxHazards = false |
| If true, VFP/NEON VMLA/VMLS have special RAW hazards. More... | |
| bool | UseNEONForFPMovs = false |
| If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON. More... | |
| bool | CheckVLDnAlign = false |
| If true, VLDn instructions take an extra cycle for unaligned accesses. More... | |
| bool | NonpipelinedVFP = false |
| If true, VFP instructions are not pipelined. More... | |
| bool | StrictAlign = false |
| StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types. More... | |
| bool | RestrictIT = false |
| RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule. More... | |
| bool | HasDSP = false |
| HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions. More... | |
| bool | UseNaClTrap = false |
| NaCl TRAP instruction is generated instead of the regular TRAP. More... | |
| bool | GenLongCalls = false |
| Generate calls via indirect call instructions. More... | |
| bool | GenExecuteOnly = false |
| Generate code that does not contain data access to code sections. More... | |
| bool | UnsafeFPMath = false |
| Target machine allowed unsafe FP math (such as use of NEON fp) More... | |
| bool | UseSjLjEH = false |
| UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). More... | |
| unsigned | stackAlignment = 4 |
| stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More... | |
| std::string | CPUString |
| CPUString - String name of used CPU. More... | |
| unsigned | MaxInterleaveFactor = 1 |
| unsigned | PartialUpdateClearance = 0 |
| Clearance before partial register updates (in number of instructions) More... | |
| ARMLdStMultipleTiming | LdStMultipleTiming = SingleIssue |
| What kind of timing do load multiple/store multiple have (double issue, single issue etc). More... | |
| int | PreISelOperandLatencyAdjustment = 2 |
| The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands. More... | |
| bool | IsLittle |
| IsLittle - The target is Little Endian. More... | |
| Triple | TargetTriple |
| TargetTriple - What processor and OS we're targeting. More... | |
| MCSchedModel | SchedModel |
| SchedModel - Processor specific instruction costs. More... | |
| InstrItineraryData | InstrItins |
| Selected instruction itineraries (one entry per itinerary class.) More... | |
| const TargetOptions & | Options |
| Options passed via command line that could influence the target. More... | |
| const ARMBaseTargetMachine & | TM |
Definition at line 43 of file ARMSubtarget.h.
|
protected |
Definition at line 54 of file ARMSubtarget.h.
What kind of timing do load multiple/store multiple instructions have.
Definition at line 63 of file ARMSubtarget.h.
|
protected |
| Enumerator | |
|---|---|
| None | |
| AClass | |
| RClass | |
| MClass | |
Definition at line 51 of file ARMSubtarget.h.
|
protected |
Definition at line 45 of file ARMSubtarget.h.
| ARMSubtarget::ARMSubtarget | ( | const Triple & | TT, |
| const std::string & | CPU, | ||
| const std::string & | FS, | ||
| const ARMBaseTargetMachine & | TM, | ||
| bool | IsLittle | ||
| ) |
This constructor initializes the data members to match that of the specified triple.
Definition at line 93 of file ARMSubtarget.cpp.
|
inline |
Definition at line 607 of file ARMSubtarget.h.
References StrictAlign.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses().
|
inline |
Definition at line 492 of file ARMSubtarget.h.
References AvoidCPSRPartialUpdate.
|
inline |
Definition at line 493 of file ARMSubtarget.h.
References AvoidMOVsShifterOperand.
|
inline |
Definition at line 489 of file ARMSubtarget.h.
References CheckVLDnAlign.
Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().
| void llvm::ARMSubtarget::computeIssueWidth | ( | ) |
|
inline |
Definition at line 487 of file ARMSubtarget.h.
References DontWidenVMOVS.
Referenced by llvm::ARMBaseInstrInfo::expandPostRAPseudo().
|
override |
Definition at line 352 of file ARMSubtarget.cpp.
References hasAnyDataBarrier().
|
override |
Returns true if machine scheduler should be enabled.
Definition at line 336 of file ARMSubtarget.cpp.
References isSwift().
|
override |
True for some subtargets at > -O0.
Definition at line 344 of file ARMSubtarget.cpp.
References hasThumb2(), isSwift(), and isThumb().
|
inline |
Definition at line 482 of file ARMSubtarget.h.
References ExpandMLx.
|
inline |
Definition at line 500 of file ARMSubtarget.h.
References GenExecuteOnly.
Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex(), emitThumbRegPlusImmInReg(), llvm::ARMElfTargetObjectFile::Initialize(), llvm::ARMAsmPrinter::lowerOperand(), llvm::ARMTargetLowering::LowerOperation(), llvm::ARMAsmPrinter::printOperand(), and useMovt().
|
inline |
Definition at line 499 of file ARMSubtarget.h.
References GenLongCalls.
|
override |
Definition at line 109 of file ARMSubtarget.cpp.
References assert().
|
inline |
Definition at line 611 of file ARMSubtarget.h.
References CPUString.
Referenced by llvm::ARMTargetMachine::ARMTargetMachine().
|
inlineoverride |
Definition at line 382 of file ARMSubtarget.h.
Referenced by llvm::ThumbRegisterInfo::eliminateFrameIndex(), and llvm::ARMFrameLowering::emitPrologue().
|
inlineoverride |
Definition at line 376 of file ARMSubtarget.h.
Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), emitThumb1LoadConstPool(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::ThumbRegisterInfo::saveScavengerRegister(), and llvm::Thumb1FrameLowering::spillCalleeSavedRegisters().
|
inlineoverride |
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition at line 632 of file ARMSubtarget.h.
References InstrItins.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
override |
Definition at line 114 of file ARMSubtarget.cpp.
References assert().
|
inline |
Definition at line 645 of file ARMSubtarget.h.
References LdStMultipleTiming.
Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().
|
override |
Definition at line 119 of file ARMSubtarget.cpp.
References assert().
|
inline |
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition at line 362 of file ARMSubtarget.h.
Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy().
|
inline |
Definition at line 641 of file ARMSubtarget.h.
References MaxInterleaveFactor.
Referenced by llvm::ARMTTIImpl::getMaxInterleaveFactor().
| unsigned ARMSubtarget::getMispredictionPenalty | ( | ) | const |
Definition at line 327 of file ARMSubtarget.cpp.
References llvm::MCSchedModel::MispredictPenalty, and SchedModel.
Referenced by llvm::ARMBaseInstrInfo::isProfitableToIfCvt().
|
inline |
Definition at line 643 of file ARMSubtarget.h.
References PartialUpdateClearance.
Referenced by llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance().
|
inline |
Definition at line 649 of file ARMSubtarget.h.
References PreISelOperandLatencyAdjustment.
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().
|
override |
Definition at line 124 of file ARMSubtarget.cpp.
References assert().
|
inlineoverride |
|
inlineoverride |
Definition at line 373 of file ARMSubtarget.h.
|
inline |
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.
Definition at line 639 of file ARMSubtarget.h.
References stackAlignment.
|
inlineoverride |
Definition at line 379 of file ARMSubtarget.h.
Referenced by llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), and llvm::ARMBaseRegisterInfo::getCallPreservedMask().
Definition at line 506 of file ARMSubtarget.h.
References TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), hasSinCos(), LowerFPOWI(), and llvm::ARMTargetLowering::LowerOperation().
|
inline |
Definition at line 474 of file ARMSubtarget.h.
References Has8MSecExt.
Referenced by getMClassRegisterMask().
|
inline |
Definition at line 463 of file ARMSubtarget.h.
References HasAcquireRelease.
|
inline |
Definition at line 464 of file ARMSubtarget.h.
References HasDataBarrier, hasV6Ops(), and isThumb().
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and enableAtomicExpand().
|
inline |
Definition at line 443 of file ARMSubtarget.h.
References NoARM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetMachine::ARMTargetMachine(), and isXRaySupported().
|
inline |
Definition at line 451 of file ARMSubtarget.h.
References HasCRC.
|
inline |
Definition at line 450 of file ARMSubtarget.h.
References HasCrypto.
|
inline |
Definition at line 503 of file ARMSubtarget.h.
References HasD16.
Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs().
|
inline |
Definition at line 461 of file ARMSubtarget.h.
References HasDataBarrier.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), LowerATOMIC_FENCE(), and llvm::ARMTargetLowering::makeDMB().
|
inline |
Definition at line 458 of file ARMSubtarget.h.
References HasHardwareDivide.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 459 of file ARMSubtarget.h.
References HasHardwareDivideInARM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 496 of file ARMSubtarget.h.
References HasDSP.
Referenced by AddCombineTo64bitUMAAL(), llvm::ARMTargetLowering::ARMTargetLowering(), getArchForCPU(), and getMClassRegisterMask().
|
inline |
Definition at line 502 of file ARMSubtarget.h.
References HasFP16.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 476 of file ARMSubtarget.h.
References HasFPAO.
Referenced by llvm::ARMTargetLowering::getScalingFactorCost().
|
inline |
Definition at line 448 of file ARMSubtarget.h.
References HasFPARMv8.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 504 of file ARMSubtarget.h.
References HasFullFP16.
|
inline |
Definition at line 495 of file ARMSubtarget.h.
References HasMPExtension.
Referenced by LowerPREFETCH().
|
inline |
Definition at line 486 of file ARMSubtarget.h.
References HasMuxedUnits.
Referenced by llvm::ARMHazardRecognizer::getHazardType().
|
inline |
Definition at line 449 of file ARMSubtarget.h.
References HasNEON.
Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::canCombineStoreAndExtract(), llvm::ARMTTIImpl::getArithmeticInstrCost(), llvm::ARMTTIImpl::getCastInstrCost(), llvm::ARMTTIImpl::getCmpSelInstrCost(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::ARMTTIImpl::getNumberOfRegisters(), llvm::ARMTargetLowering::getOptimalMemOpType(), llvm::ARMTargetLowering::getRegClassFor(), llvm::ARMTTIImpl::getRegisterBitWidth(), LowerCTPOP(), LowerCTTZ(), llvm::ARMTargetLowering::lowerInterleavedLoad(), llvm::ARMTargetLowering::lowerInterleavedStore(), LowerShift(), llvm::ARMTargetLowering::LowerXConstraint(), PerformExtendCombine(), PerformORCombine(), PerformShiftCombine(), PerformVCVTCombine(), PerformVDIVCombine(), llvm::ARMBaseInstrInfo::setExecutionDomain(), and useNEONForSinglePrecisionFP().
|
inline |
Definition at line 472 of file ARMSubtarget.h.
References HasPerfMon.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 452 of file ARMSubtarget.h.
References HasRAS.
|
inline |
Definition at line 494 of file ARMSubtarget.h.
References HasRetAddrStack.
| bool ARMSubtarget::hasSinCos | ( | ) | const |
This function returns true if the target has sincos() routine in its compiler runtime or math libraries.
Definition at line 331 of file ARMSubtarget.cpp.
References getTargetTriple(), llvm::Triple::isOSVersionLT(), isTargetIOS(), and isTargetWatchOS().
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 485 of file ARMSubtarget.h.
References SlowLoadDSubregister.
Referenced by llvm::ARMTTIImpl::getVectorInstrCost().
|
inline |
Definition at line 484 of file ARMSubtarget.h.
References SlowOddRegister.
|
inline |
Definition at line 479 of file ARMSubtarget.h.
References HasSlowVDUP32.
|
inline |
Definition at line 478 of file ARMSubtarget.h.
References HasSlowVGETLNi32.
|
inline |
Definition at line 460 of file ARMSubtarget.h.
References HasT2ExtractPack.
Referenced by PerformORCombine().
|
inline |
Definition at line 579 of file ARMSubtarget.h.
References HasThumb2.
Referenced by AddCombineTo64bitUMAAL(), and enablePostRAScheduler().
|
inline |
Definition at line 473 of file ARMSubtarget.h.
References HasTrustZone.
|
inline |
|
inline |
Definition at line 416 of file ARMSubtarget.h.
References HasV5TEOps.
Referenced by getArchForCPU(), llvm::ARMBaseInstrInfo::loadRegFromStackSlot(), LowerPREFETCH(), and llvm::ARMBaseInstrInfo::storeRegToStackSlot().
|
inline |
Definition at line 415 of file ARMSubtarget.h.
References HasV5TOps.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::EmitInstruction(), getArchForCPU(), and llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters().
|
inline |
Definition at line 419 of file ARMSubtarget.h.
References HasV6KOps.
|
inline |
|
inline |
Definition at line 417 of file ARMSubtarget.h.
References HasV6Ops.
Referenced by AddCombineTo64bitUMAAL(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::Thumb1InstrInfo::copyPhysReg(), llvm::ARMTargetLowering::ExpandInlineAsm(), getArchForCPU(), hasAnyDataBarrier(), isXRaySupported(), LowerATOMIC_FENCE(), llvm::ARMTargetLowering::makeDMB(), PerformShiftCombine(), llvm::ARMTargetLowering::shouldAlignPointerArgs(), and useFastISel().
|
inline |
Definition at line 420 of file ARMSubtarget.h.
References HasV6T2Ops.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), emitAligningInstructions(), getArchForCPU(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTargetLowering::isCheapToSpeculateCtlz(), llvm::ARMTargetLowering::isCheapToSpeculateCttz(), isV8M(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerCTTZ(), llvm::ARMTargetLowering::PerformCMOVCombine(), and PerformORCombine().
|
inline |
Definition at line 462 of file ARMSubtarget.h.
References HasV7Clrex.
|
inline |
Definition at line 421 of file ARMSubtarget.h.
References HasV7Ops.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), emitAligningInstructions(), llvm::ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(), getArchForCPU(), getMClassRegisterMask(), and LowerPREFETCH().
|
inline |
Definition at line 423 of file ARMSubtarget.h.
References HasV8_1aOps.
|
inline |
Definition at line 424 of file ARMSubtarget.h.
References HasV8_2aOps.
|
inline |
Definition at line 425 of file ARMSubtarget.h.
References HasV8MBaselineOps.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), getArchForCPU(), isV8M(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), and useMovt().
|
inline |
Definition at line 426 of file ARMSubtarget.h.
References HasV8MMainlineOps.
Referenced by getArchForCPU(), getMClassRegisterMask(), and isV8M().
|
inline |
Definition at line 422 of file ARMSubtarget.h.
References HasV8Ops.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and getArchForCPU().
|
inline |
Definition at line 445 of file ARMSubtarget.h.
References HasVFPv2.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMTTIImpl::getFPOpCost(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), isLegalAddressImmediate(), isLegalT2AddressImmediate(), and llvm::ARMTargetLowering::LowerXConstraint().
|
inline |
Definition at line 446 of file ARMSubtarget.h.
References HasVFPv3.
Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs(), and llvm::ARMTargetLowering::isFPImmLegal().
|
inline |
Definition at line 447 of file ARMSubtarget.h.
References HasVFPv4.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 453 of file ARMSubtarget.h.
References HasVirtualization.
|
inline |
Definition at line 469 of file ARMSubtarget.h.
References HasVMLxForwarding.
Referenced by PerformVMULCombine().
|
inline |
Definition at line 483 of file ARMSubtarget.h.
References HasVMLxHazards.
|
inline |
Definition at line 475 of file ARMSubtarget.h.
References HasZeroCycleZeroing.
| ARMSubtarget & ARMSubtarget::initializeSubtargetDependencies | ( | StringRef | CPU, |
| StringRef | FS | ||
| ) |
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.
Definition at line 72 of file ARMSubtarget.cpp.
| bool ARMSubtarget::isAAPCS16_ABI | ( | ) | const |
Definition at line 299 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.
Referenced by isTargetHardFloat().
| bool ARMSubtarget::isAAPCS_ABI | ( | ) | const |
Definition at line 294 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS, llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering().
|
inline |
Definition at line 582 of file ARMSubtarget.h.
References AClass, and ARMProcClass.
| bool ARMSubtarget::isAPCS_ABI | ( | ) | const |
Definition at line 290 of file ARMSubtarget.cpp.
References llvm::ARMBaseTargetMachine::ARM_ABI_APCS, llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN, assert(), llvm::ARMBaseTargetMachine::TargetABI, and TM.
|
inline |
Definition at line 435 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA15.
Referenced by isLikeA9().
|
inline |
These functions are obsolete, please consider adding subtarget features or properties instead of calling them.
Definition at line 431 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA5.
|
inline |
Definition at line 432 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA7.
Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().
|
inline |
Definition at line 433 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA8.
Referenced by adjustDefLatency(), llvm::ARMBaseInstrInfo::getExecutionDomain(), and llvm::ARMBaseInstrInfo::getOperandLatency().
|
inline |
Definition at line 434 of file ARMSubtarget.h.
References ARMProcFamily, and CortexA9.
Referenced by isLikeA9().
|
inline |
Definition at line 437 of file ARMSubtarget.h.
References ARMProcFamily, and CortexM3.
|
inline |
Definition at line 439 of file ARMSubtarget.h.
References ARMProcFamily, and CortexR5.
|
inline |
Definition at line 470 of file ARMSubtarget.h.
References SlowFPBrcc.
Referenced by canChangeToInt().
|
inline |
Definition at line 471 of file ARMSubtarget.h.
References FPOnlySP.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::ARMTTIImpl::getFPOpCost(), llvm::ARMTargetLowering::isFPImmLegal(), and PerformVMOVRRDCombine().
| bool ARMSubtarget::isGVIndirectSymbol | ( | const GlobalValue * | GV | ) | const |
True if the GV will be accessed via an indirect symbol.
Definition at line 313 of file ARMSubtarget.cpp.
References llvm::GlobalValue::getParent(), llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::isDeclarationForLinker(), llvm::TargetMachine::isPositionIndependent(), isTargetMachO(), llvm::TargetMachine::shouldAssumeDSOLocal(), and TM.
Referenced by llvm::ARMBaseInstrInfo::expandLoadStackGuardBase().
|
inline |
Definition at line 440 of file ARMSubtarget.h.
References ARMProcFamily, and Krait.
Referenced by isLikeA9().
|
inline |
Definition at line 438 of file ARMSubtarget.h.
References isCortexA15(), isCortexA9(), and isKrait().
Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().
|
inline |
Definition at line 613 of file ARMSubtarget.h.
References IsLittle.
Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::ARMTargetLowering::emitLoadLinked(), and llvm::ARMTargetLowering::emitStoreConditional().
|
inline |
Definition at line 580 of file ARMSubtarget.h.
References ARMProcClass, and MClass.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyFromCPSR(), llvm::ARMBaseInstrInfo::copyToCPSR(), getArchForCPU(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), LowerATOMIC_FENCE(), llvm::ARMTargetLowering::makeDMB(), llvm::ARMTargetLowering::shouldAlignPointerArgs(), llvm::ARMTargetLowering::shouldExpandAtomicLoadInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), and llvm::ARMTargetLowering::shouldExpandAtomicStoreInIR().
|
inline |
Definition at line 477 of file ARMSubtarget.h.
References IsProfitableToUnpredicate.
Referenced by llvm::ARMBaseInstrInfo::isProfitableToUnpredicate().
|
inline |
Definition at line 584 of file ARMSubtarget.h.
References HasV6Ops, isTargetMachO(), and ReserveR9.
Referenced by llvm::ARMBaseRegisterInfo::getRegPressureLimit(), and llvm::ARMBaseRegisterInfo::getReservedRegs().
|
inline |
Definition at line 581 of file ARMSubtarget.h.
References ARMProcClass, and RClass.
Referenced by getArchForCPU().
| bool ARMSubtarget::isROPI | ( | ) | const |
Definition at line 304 of file ARMSubtarget.cpp.
References llvm::TargetMachine::getRelocationModel(), llvm::Reloc::ROPI, llvm::Reloc::ROPI_RWPI, and TM.
Referenced by llvm::ARMAsmPrinter::EmitJumpTableAddrs(), llvm::ARMBaseInstrInfo::expandLoadStackGuardBase(), and llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant().
| bool ARMSubtarget::isRWPI | ( | ) | const |
Definition at line 308 of file ARMSubtarget.cpp.
References llvm::TargetMachine::getRelocationModel(), llvm::Reloc::ROPI_RWPI, llvm::Reloc::RWPI, and TM.
Referenced by llvm::ARMBaseInstrInfo::expandLoadStackGuardBase(), and llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant().
|
inline |
Definition at line 436 of file ARMSubtarget.h.
References ARMProcFamily, and Swift.
Referenced by adjustDefLatency(), enableMachineScheduler(), enablePostRAScheduler(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::ARMBaseInstrInfo::getOperandLatency(), and useStride4VFPs().
|
inline |
Definition at line 528 of file ARMSubtarget.h.
References llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), isTargetDarwin(), isTargetWindows(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMAsmPrinter::EmitEndOfAsmFile().
|
inline |
Definition at line 564 of file ARMSubtarget.h.
References llvm::Triple::isAndroid(), and TargetTriple.
Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::ARMTargetLowering::ARMTargetLowering(), and isTargetEHABICompatible().
|
inline |
Definition at line 517 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatCOFF(), and TargetTriple.
Referenced by llvm::ARMAsmPrinter::runOnMachineFunction().
|
inline |
Definition at line 508 of file ARMSubtarget.h.
References llvm::Triple::isOSDarwin(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseRegisterInfo::getCalleeSavedRegs(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask(), llvm::ARMBaseRegisterInfo::getTLSCallPreservedMask(), llvm::ARMTTIImpl::isFPVectorizationPotentiallyUnsafe(), isTargetAEABI(), isTargetEHABICompatible(), isTargetGNUAEABI(), isTargetMuslAEABI(), and useR7AsFramePointer().
|
inline |
Definition at line 546 of file ARMSubtarget.h.
References llvm::Triple::EABI, llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, isTargetAndroid(), isTargetDarwin(), isTargetWindows(), llvm::Triple::MuslEABI, llvm::Triple::MuslEABIHF, and TargetTriple.
Referenced by llvm::ARMAsmPrinter::EmitInstruction().
|
inline |
Definition at line 518 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatELF(), and TargetTriple.
Referenced by llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), and llvm::ARMAsmPrinter::EmitXXStructor().
|
inline |
Definition at line 533 of file ARMSubtarget.h.
References llvm::Triple::getEnvironment(), llvm::Triple::GNUEABI, llvm::Triple::GNUEABIHF, isTargetDarwin(), isTargetWindows(), and TargetTriple.
Referenced by llvm::ARMBaseTargetMachine::ARMBaseTargetMachine(), llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMAsmPrinter::EmitEndOfAsmFile().
|
inline |
Definition at line 557 of file ARMSubtarget.h.
References llvm::Triple::EABIHF, llvm::Triple::getEnvironment(), llvm::Triple::GNUEABIHF, isAAPCS16_ABI(), isTargetWindows(), llvm::Triple::MuslEABIHF, and TargetTriple.
Referenced by llvm::ARMBaseTargetMachine::ARMBaseTargetMachine().
|
inline |
Definition at line 509 of file ARMSubtarget.h.
References llvm::Triple::isiOS(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and hasSinCos().
|
inline |
Definition at line 512 of file ARMSubtarget.h.
References llvm::Triple::isOSLinux(), and TargetTriple.
Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), and useFastISel().
|
inline |
Definition at line 519 of file ARMSubtarget.h.
References llvm::Triple::isOSBinFormatMachO(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitMachineConstantPoolValue(), isGVIndirectSymbol(), isR9Reserved(), useFastISel(), and llvm::ARMTargetLowering::useLoadStackGuardNode().
|
inline |
Definition at line 538 of file ARMSubtarget.h.
References llvm::Triple::getEnvironment(), isTargetDarwin(), isTargetWindows(), llvm::Triple::MuslEABI, llvm::Triple::MuslEABIHF, and TargetTriple.
Referenced by llvm::ARMBaseTargetMachine::ARMBaseTargetMachine(), llvm::ARMTargetLowering::ARMTargetLowering(), and llvm::ARMAsmPrinter::EmitEndOfAsmFile().
|
inline |
Definition at line 513 of file ARMSubtarget.h.
References llvm::Triple::isOSNaCl(), and TargetTriple.
Referenced by useFastISel().
|
inline |
Definition at line 514 of file ARMSubtarget.h.
References llvm::Triple::isOSNetBSD(), and TargetTriple.
|
inline |
Definition at line 511 of file ARMSubtarget.h.
References llvm::Triple::isWatchABI(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and useStride4VFPs().
|
inline |
Definition at line 510 of file ARMSubtarget.h.
References llvm::Triple::isWatchOS(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and hasSinCos().
|
inline |
Definition at line 515 of file ARMSubtarget.h.
References llvm::Triple::isOSWindows(), and TargetTriple.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::emitPrologue(), getDivRemArgList(), isTargetAEABI(), isTargetEHABICompatible(), isTargetGNUAEABI(), isTargetHardFloat(), isTargetMuslAEABI(), isXRaySupported(), llvm::ARMTargetLowering::LowerOperation(), llvm::ARMTargetLowering::ReplaceNodeResults(), useMovt(), and useR7AsFramePointer().
|
inline |
Definition at line 576 of file ARMSubtarget.h.
References InThumbMode.
Referenced by AddCombineTo64bitUMAAL(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyFromCPSR(), llvm::ARMBaseInstrInfo::copyToCPSR(), enablePostRAScheduler(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getSingleConstraintMatchWeight(), hasAnyDataBarrier(), llvm::ARMTargetLowering::isLegalAddImmediate(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerATOMIC_FENCE(), LowerPREFETCH(), llvm::ARMTargetLowering::makeDMB(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), llvm::ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(), llvm::ARMTargetLowering::shouldExpandAtomicRMWInIR(), useFastISel(), and useR7AsFramePointer().
|
inline |
Definition at line 577 of file ARMSubtarget.h.
References HasThumb2, and InThumbMode.
Referenced by llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::ARMBaseInstrInfo::areLoadsFromSameBasePtr(), llvm::ARMTargetLowering::ARMTargetLowering(), attachMEMCPYScratchRegs(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::ThumbRegisterInfo::emitLoadConstPool(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), Expand64BitShift(), llvm::ARMTTIImpl::getFPOpCost(), llvm::ThumbRegisterInfo::getLargestLegalSuperClass(), llvm::ARMTTIImpl::getNumberOfRegisters(), llvm::ThumbRegisterInfo::getPointerRegClass(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), IsSingleInstrConstant(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), LowerPREFETCH(), PerformADDCCombine(), PerformANDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), PerformMULCombine(), PerformORCombine(), PerformXORCombine(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::ThumbRegisterInfo::saveScavengerRegister(), llvm::ARMBaseInstrInfo::shouldScheduleLoadsNear(), splitFramePushPop(), and useFastISel().
|
inline |
Definition at line 578 of file ARMSubtarget.h.
References HasThumb2, and InThumbMode.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTTIImpl::getIntImmCost(), llvm::ARMTargetLowering::getPostIndexedAddressParts(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::ARMTargetLowering::isLegalAddImmediate(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::ARMTargetLowering::isLegalICmpImmediate(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), and LowerPREFETCH().
|
overridevirtual |
Definition at line 129 of file ARMSubtarget.cpp.
References hasARMOps(), hasV6Ops(), and isTargetWindows().
|
inline |
Definition at line 490 of file ARMSubtarget.h.
References NonpipelinedVFP.
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Definition of function is auto generated by tblgen.
|
inline |
Definition at line 481 of file ARMSubtarget.h.
References PreferISHST.
Referenced by llvm::ARMTargetLowering::emitLeadingFence(), and LowerATOMIC_FENCE().
|
inline |
Definition at line 491 of file ARMSubtarget.h.
References Pref32BitThumb.
|
inline |
Definition at line 480 of file ARMSubtarget.h.
References PreferVMOVSR.
|
inline |
Definition at line 609 of file ARMSubtarget.h.
References RestrictIT.
Referenced by llvm::ARMBaseInstrInfo::isPredicable().
|
inline |
This object will take onwership of GISelAccessor.
Definition at line 358 of file ARMSubtarget.h.
|
inline |
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr.
This is always required on Thumb1-only targets, as the push and pop instructions can't access the high registers.
Definition at line 595 of file ARMSubtarget.h.
References llvm::TargetOptions::DisableFramePointerElim(), llvm::MachineFunction::getTarget(), isThumb1Only(), llvm::TargetMachine::Options, and useR7AsFramePointer().
Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), and llvm::ARMBaseRegisterInfo::getCalleeSavedRegs().
|
inline |
Definition at line 605 of file ARMSubtarget.h.
References SupportsTailCall.
| bool ARMSubtarget::useFastISel | ( | ) | const |
True if fast-isel is used.
Definition at line 369 of file ARMSubtarget.cpp.
References llvm::TargetOptions::EnableFastISel, ForceFastISel, hasV6Ops(), isTargetLinux(), isTargetMachO(), isTargetNaCl(), isThumb(), isThumb1Only(), llvm::TargetMachine::Options, and TM.
Referenced by llvm::ARM::createFastISel().
|
inline |
Definition at line 468 of file ARMSubtarget.h.
References SlowFPVMLx.
| bool ARMSubtarget::useMovt | ( | const MachineFunction & | MF | ) | const |
Definition at line 361 of file ARMSubtarget.cpp.
References genExecuteOnly(), llvm::MachineFunction::getFunction(), hasV8MBaselineOps(), isTargetWindows(), NoMovt, and llvm::Function::optForMinSize().
|
inline |
Definition at line 467 of file ARMSubtarget.h.
References UseMulOps.
|
inline |
Definition at line 497 of file ARMSubtarget.h.
References UseNaClTrap.
|
inline |
Definition at line 488 of file ARMSubtarget.h.
References UseNEONForFPMovs.
Referenced by llvm::ARMBaseInstrInfo::getExecutionDomain().
|
inline |
Definition at line 454 of file ARMSubtarget.h.
References hasNEON(), and UseNEONForSinglePrecisionFP.
Referenced by llvm::ARMTargetLowering::findRepresentativeClass().
|
inline |
Definition at line 588 of file ARMSubtarget.h.
References isTargetDarwin(), isTargetWindows(), and isThumb().
Referenced by getFramePointerReg(), and splitFramePushPop().
|
inline |
Definition at line 498 of file ARMSubtarget.h.
References UseSjLjEH.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMTargetLowering::getExceptionPointerRegister(), and llvm::ARMTargetLowering::getExceptionSelectorRegister().
|
inline |
Definition at line 575 of file ARMSubtarget.h.
References UseSoftFloat.
Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(), and llvm::ARMTargetLowering::useSoftFloat().
| bool ARMSubtarget::useStride4VFPs | ( | const MachineFunction & | MF | ) | const |
Definition at line 354 of file ARMSubtarget.cpp.
References llvm::MachineFunction::getFunction(), isSwift(), isTargetWatchABI(), and llvm::Function::optForMinSize().
|
protected |
ARMArch - ARM architecture.
Definition at line 84 of file ARMSubtarget.h.
|
protected |
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition at line 81 of file ARMSubtarget.h.
Referenced by isAClass(), isMClass(), and isRClass().
|
protected |
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition at line 78 of file ARMSubtarget.h.
Referenced by isCortexA15(), isCortexA5(), isCortexA7(), isCortexA8(), isCortexA9(), isCortexM3(), isCortexR5(), isKrait(), and isSwift().
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction.
Definition at line 193 of file ARMSubtarget.h.
Referenced by avoidCPSRPartialUpdate().
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e.
asr, lsl, lsr).
Definition at line 197 of file ARMSubtarget.h.
Referenced by avoidMOVsShifterOperand().
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition at line 280 of file ARMSubtarget.h.
Referenced by checkVLDnAccessAlignment().
|
protected |
CPUString - String name of used CPU.
Definition at line 318 of file ARMSubtarget.h.
Referenced by getCPUString().
If true, VMOVS will never be widened to VMOVD.
Definition at line 268 of file ARMSubtarget.h.
Referenced by dontWidenVMOVS().
If true, run the MLx expansion pass.
Definition at line 271 of file ARMSubtarget.h.
Referenced by expandMLx().
FPOnlySP - If true, the floating point unit only supports single precision.
Definition at line 213 of file ARMSubtarget.h.
Referenced by isFPOnlySP().
Generate code that does not contain data access to code sections.
Definition at line 305 of file ARMSubtarget.h.
Referenced by genExecuteOnly().
Generate calls via indirect call instructions.
Definition at line 302 of file ARMSubtarget.h.
Referenced by genLongCalls().
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition at line 224 of file ARMSubtarget.h.
Referenced by has8MSecExt().
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition at line 184 of file ARMSubtarget.h.
Referenced by hasAcquireRelease().
HasCRC - if true, processor supports CRC instructions.
Definition at line 230 of file ARMSubtarget.h.
Referenced by hasCRC().
HasCrypto - if true, processor supports Cryptography extensions.
Definition at line 227 of file ARMSubtarget.h.
Referenced by hasCrypto().
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition at line 163 of file ARMSubtarget.h.
Referenced by hasD16().
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition at line 177 of file ARMSubtarget.h.
Referenced by hasAnyDataBarrier(), and hasDataBarrier().
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition at line 296 of file ARMSubtarget.h.
Referenced by hasDSP().
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition at line 156 of file ARMSubtarget.h.
Referenced by hasFP16().
HasFPAO - if true, processor does positive address offset computation faster.
Definition at line 240 of file ARMSubtarget.h.
Referenced by hasFPAO().
Definition at line 108 of file ARMSubtarget.h.
Referenced by hasFPARMv8().
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition at line 159 of file ARMSubtarget.h.
Referenced by hasFullFP16().
HasHardwareDivide - True if subtarget supports [su]div.
Definition at line 166 of file ARMSubtarget.h.
Referenced by hasDivide().
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition at line 169 of file ARMSubtarget.h.
Referenced by hasDivideInARMMode().
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition at line 205 of file ARMSubtarget.h.
Referenced by hasMPExtension().
If true, the AGU and NEON/FPU units are multiplexed.
Definition at line 265 of file ARMSubtarget.h.
Referenced by hasMuxedUnits().
Definition at line 109 of file ARMSubtarget.h.
Referenced by hasNEON().
If true, the processor supports the Performance Monitor Extensions.
These include a generic cycle-counter as well as more fine-grained (often implementation-specific) events.
Definition at line 218 of file ARMSubtarget.h.
Referenced by hasPerfMon().
HasRAS - if true, the processor supports RAS extensions.
Definition at line 233 of file ARMSubtarget.h.
Referenced by hasRAS().
HasRetAddrStack - Some processors perform return stack prediction.
CodeGen should avoid issue "normal" call instructions to callees which do not return.
Definition at line 201 of file ARMSubtarget.h.
Referenced by hasRetAddrStack().
If true, VMOV will be favored over VDUP.
Definition at line 249 of file ARMSubtarget.h.
Referenced by hasSlowVDUP32().
If true, VMOV will be favored over VGETLNi32.
Definition at line 246 of file ARMSubtarget.h.
Referenced by hasSlowVGETLNi32().
HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.
Definition at line 173 of file ARMSubtarget.h.
Referenced by hasT2ExtractPack().
HasThumb2 - True if Thumb2 instructions are supported.
Definition at line 138 of file ARMSubtarget.h.
Referenced by hasThumb2(), isThumb1Only(), and isThumb2().
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition at line 221 of file ARMSubtarget.h.
Referenced by hasTrustZone().
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition at line 89 of file ARMSubtarget.h.
Referenced by hasV4TOps().
Definition at line 91 of file ARMSubtarget.h.
Referenced by hasV5TEOps().
Definition at line 90 of file ARMSubtarget.h.
Referenced by hasV5TOps().
Definition at line 94 of file ARMSubtarget.h.
Referenced by hasV6KOps().
Definition at line 93 of file ARMSubtarget.h.
Referenced by hasV6MOps().
Definition at line 92 of file ARMSubtarget.h.
Referenced by hasV6Ops(), and isR9Reserved().
Definition at line 95 of file ARMSubtarget.h.
Referenced by hasV6T2Ops().
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition at line 180 of file ARMSubtarget.h.
Referenced by hasV7Clrex().
Definition at line 96 of file ARMSubtarget.h.
Referenced by hasV7Ops().
Definition at line 98 of file ARMSubtarget.h.
Referenced by hasV8_1aOps().
Definition at line 99 of file ARMSubtarget.h.
Referenced by hasV8_2aOps().
Definition at line 100 of file ARMSubtarget.h.
Referenced by hasV8MBaselineOps().
Definition at line 101 of file ARMSubtarget.h.
Referenced by hasV8MMainlineOps().
Definition at line 97 of file ARMSubtarget.h.
Referenced by hasV8Ops().
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported.
Definition at line 105 of file ARMSubtarget.h.
Referenced by hasVFP2().
Definition at line 106 of file ARMSubtarget.h.
Referenced by hasVFP3().
Definition at line 107 of file ARMSubtarget.h.
Referenced by hasVFP4().
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition at line 209 of file ARMSubtarget.h.
Referenced by hasVirtualization().
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back.
Definition at line 126 of file ARMSubtarget.h.
Referenced by hasVMLxForwarding().
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition at line 274 of file ARMSubtarget.h.
Referenced by hasVMLxHazards().
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register.
Definition at line 237 of file ARMSubtarget.h.
Referenced by hasZeroCycleZeroing().
|
protected |
Selected instruction itineraries (one entry per itinerary class.)
Definition at line 343 of file ARMSubtarget.h.
Referenced by getInstrItineraryData().
InThumbMode - True if compiling for Thumb, false for ARM.
Definition at line 132 of file ARMSubtarget.h.
Referenced by isThumb(), isThumb1Only(), and isThumb2().
|
protected |
IsLittle - The target is Little Endian.
Definition at line 334 of file ARMSubtarget.h.
Referenced by isLittle().
If true, if conversion may decide to leave some instructions unpredicated.
Definition at line 243 of file ARMSubtarget.h.
Referenced by isProfitableToUnpredicate().
|
protected |
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition at line 327 of file ARMSubtarget.h.
Referenced by getLdStMultipleTiming().
|
protected |
Definition at line 320 of file ARMSubtarget.h.
Referenced by getMaxInterleaveFactor().
NoARM - True if subtarget does not support ARM mode execution.
Definition at line 141 of file ARMSubtarget.h.
Referenced by hasARMOps().
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global addresses).
Definition at line 148 of file ARMSubtarget.h.
Referenced by useMovt().
If true, VFP instructions are not pipelined.
Definition at line 283 of file ARMSubtarget.h.
Referenced by nonpipelinedVFP().
|
protected |
Options passed via command line that could influence the target.
Definition at line 346 of file ARMSubtarget.h.
|
protected |
Clearance before partial register updates (in number of instructions)
Definition at line 323 of file ARMSubtarget.h.
Referenced by getPartialUpdateClearance().
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones.
Definition at line 188 of file ARMSubtarget.h.
Referenced by prefers32BitThumb().
If true, ISHST barriers will be used for Release semantics.
Definition at line 255 of file ARMSubtarget.h.
Referenced by preferISHSTBarriers().
If true, VMOVSR will be favored over VMOVDRR.
Definition at line 252 of file ARMSubtarget.h.
Referenced by preferVMOVSR().
|
protected |
The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.
Definition at line 331 of file ARMSubtarget.h.
Referenced by getPreISelOperandLatencyAdjustment().
ReserveR9 - True if R9 is not available as a general purpose register.
Definition at line 144 of file ARMSubtarget.h.
Referenced by isR9Reserved().
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule.
Definition at line 292 of file ARMSubtarget.h.
Referenced by restrictIT().
|
protected |
SchedModel - Processor specific instruction costs.
Definition at line 340 of file ARMSubtarget.h.
Referenced by getMispredictionPenalty().
SlowFPBrcc - True if floating point compare + branch is slow.
Definition at line 129 of file ARMSubtarget.h.
Referenced by isFPBrccSlow().
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them).
Definition at line 122 of file ARMSubtarget.h.
Referenced by useFPVMLx().
If true, loading into a D subregister will be penalized.
Definition at line 262 of file ARMSubtarget.h.
Referenced by hasSlowLoadDSubregister().
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than single VLDRS/VSTRS.
Definition at line 259 of file ARMSubtarget.h.
Referenced by hasSlowOddRegister().
|
protected |
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.
Definition at line 315 of file ARMSubtarget.h.
Referenced by getStackAlignment().
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types.
For details, see ARMTargetLowering::allowsMisalignedMemoryAccesses().
Definition at line 288 of file ARMSubtarget.h.
Referenced by allowsUnalignedMem().
SupportsTailCall - True if the OS supports tail call.
The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.
Definition at line 153 of file ARMSubtarget.h.
Referenced by supportsTailCall().
|
protected |
TargetTriple - What processor and OS we're targeting.
Definition at line 337 of file ARMSubtarget.h.
Referenced by getTargetTriple(), isTargetAEABI(), isTargetAndroid(), isTargetCOFF(), isTargetDarwin(), isTargetEHABICompatible(), isTargetELF(), isTargetGNUAEABI(), isTargetHardFloat(), isTargetIOS(), isTargetLinux(), isTargetMachO(), isTargetMuslAEABI(), isTargetNaCl(), isTargetNetBSD(), isTargetWatchABI(), isTargetWatchOS(), and isTargetWindows().
|
protected |
Definition at line 348 of file ARMSubtarget.h.
Referenced by isAAPCS16_ABI(), isAAPCS_ABI(), isAPCS_ABI(), isGVIndirectSymbol(), isROPI(), isRWPI(), and useFastISel().
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition at line 308 of file ARMSubtarget.h.
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.
Definition at line 118 of file ARMSubtarget.h.
Referenced by useMulOps().
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition at line 299 of file ARMSubtarget.h.
Referenced by useNaClTrap().
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition at line 277 of file ARMSubtarget.h.
Referenced by useNEONForFPMovs().
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Use the method useNEONForSinglePrecisionFP() to determine if NEON should actually be used.
Definition at line 114 of file ARMSubtarget.h.
Referenced by useNEONForSinglePrecisionFP().
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition at line 311 of file ARMSubtarget.h.
Referenced by useSjLjEH().
UseSoftFloat - True if we're using software floating point features.
Definition at line 135 of file ARMSubtarget.h.
Referenced by useSoftFloat().
1.8.6