LLVM  4.0.0
MipsSEISelDAGToDAG.h
Go to the documentation of this file.
1 //===-- MipsSEISelDAGToDAG.h - A Dag to Dag Inst Selector for MipsSE -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H
16 
17 #include "MipsISelDAGToDAG.h"
18 
19 namespace llvm {
20 
22 
23 public:
25  : MipsDAGToDAGISel(TM, OL) {}
26 
27 private:
28 
29  bool runOnMachineFunction(MachineFunction &MF) override;
30 
31  void getAnalysisUsage(AnalysisUsage &AU) const override;
32 
33  void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
35 
36  unsigned getMSACtrlReg(const SDValue RegIdx) const;
37 
38  bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
39 
40  std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
41  const SDLoc &dl, EVT Ty, bool HasLo,
42  bool HasHi);
43 
44  void selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
45  const SDLoc &DL, SDNode *Node) const;
46 
47  bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
48  bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
49  unsigned OffsetBits,
50  unsigned ShiftAmount) const;
51 
52  bool selectAddrRegImm(SDValue Addr, SDValue &Base,
53  SDValue &Offset) const override;
54 
55  bool selectAddrDefault(SDValue Addr, SDValue &Base,
56  SDValue &Offset) const override;
57 
58  bool selectIntAddr(SDValue Addr, SDValue &Base,
59  SDValue &Offset) const override;
60 
61  bool selectAddrRegImm9(SDValue Addr, SDValue &Base,
62  SDValue &Offset) const;
63 
64  bool selectAddrRegImm11(SDValue Addr, SDValue &Base,
65  SDValue &Offset) const;
66 
67  bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
68  SDValue &Offset) const;
69 
70  bool selectAddrRegImm16(SDValue Addr, SDValue &Base,
71  SDValue &Offset) const;
72 
73  bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
74  SDValue &Offset) const override;
75 
76  bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
77  SDValue &Offset) const override;
78 
79  bool selectIntAddr16MM(SDValue Addr, SDValue &Base,
80  SDValue &Offset) const override;
81 
82  bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
83  SDValue &Offset) const override;
84 
85  bool selectIntAddrSImm10(SDValue Addr, SDValue &Base,
86  SDValue &Offset) const override;
87 
88  bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
89  SDValue &Offset) const override;
90 
91  bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
92  SDValue &Offset) const override;
93 
94  bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
95  SDValue &Offset) const override;
96 
97  /// \brief Select constant vector splats.
98  bool selectVSplat(SDNode *N, APInt &Imm,
99  unsigned MinSizeInBits) const override;
100  /// \brief Select constant vector splats whose value fits in a given integer.
101  bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
102  unsigned ImmBitSize) const;
103  /// \brief Select constant vector splats whose value fits in a uimm1.
104  bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
105  /// \brief Select constant vector splats whose value fits in a uimm2.
106  bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
107  /// \brief Select constant vector splats whose value fits in a uimm3.
108  bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
109  /// \brief Select constant vector splats whose value fits in a uimm4.
110  bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
111  /// \brief Select constant vector splats whose value fits in a uimm5.
112  bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
113  /// \brief Select constant vector splats whose value fits in a uimm6.
114  bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
115  /// \brief Select constant vector splats whose value fits in a uimm8.
116  bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
117  /// \brief Select constant vector splats whose value fits in a simm5.
118  bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
119  /// \brief Select constant vector splats whose value is a power of 2.
120  bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const override;
121  /// \brief Select constant vector splats whose value is the inverse of a
122  /// power of 2.
123  bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const override;
124  /// \brief Select constant vector splats whose value is a run of set bits
125  /// ending at the most significant bit
126  bool selectVSplatMaskL(SDValue N, SDValue &Imm) const override;
127  /// \brief Select constant vector splats whose value is a run of set bits
128  /// starting at bit zero.
129  bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override;
130 
131  bool trySelect(SDNode *Node) override;
132 
133  void processFunctionAfterISel(MachineFunction &MF) override;
134 
135  // Insert instructions to initialize the global base register in the
136  // first MBB of the function.
137  void initGlobalBaseReg(MachineFunction &MF);
138 
139  bool SelectInlineAsmMemoryOperand(const SDValue &Op,
140  unsigned ConstraintID,
141  std::vector<SDValue> &OutOps) override;
142 };
143 
144 FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM,
145  CodeGenOpt::Level OptLevel);
146 }
147 
148 #endif
FunctionPass * createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
MachineFunction * MF
unsigned const MachineRegisterInfo * MRI
Represent the analysis usage information of a pass.
uint32_t Offset
EVT - Extended Value Type.
Definition: ValueTypes.h:31
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Class for arbitrary precision integers.
Definition: APInt.h:77
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
#define N
MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
IRTranslator LLVM IR MI
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...