26 #define DEBUG_TYPE "post-RA-sched"
29 DEBUG(
dbgs() <<
"Reset hazard recognizer\n");
40 if (!MI || TII->isZeroCost(MI->
getOpcode()))
44 DEBUG(
dbgs() <<
"*** Hazard in cycle " << PacketNum <<
", " << *MI);
66 if (SU == UsesDotCur && DotCurPNum != (
int)PacketNum) {
67 DEBUG(
dbgs() <<
"*** .cur Hazard in cycle " << PacketNum <<
", " << *MI);
75 DEBUG(
dbgs() <<
"Advance cycle, clear state\n");
77 if (DotCurPNum != -1 && DotCurPNum != (
int)PacketNum) {
90 return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (
int)PacketNum));
101 if (MO.isReg() && MO.isDef() && !MO.isImplicit())
102 RegDefs.
insert(MO.getReg());
113 MF->CreateMachineInstr(TII->get(TII->
getDotNewOp(*MI)),
117 MF->DeleteMachineInstr(NewMI);
121 DEBUG(
dbgs() <<
" Add instruction " << *MI);
129 for (
auto &S : SU->
Succs)
130 if (S.isAssignedRegDep() && S.getLatency() == 0 &&
131 SU->
getHeight() == S.getSUnit()->getHeight()) {
132 UsesDotCur = S.getSUnit();
133 DotCurPNum = PacketNum;
136 if (SU == UsesDotCur) {
137 UsesDotCur =
nullptr;
bool canReserveResources(const llvm::MCInstrDesc *MID)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool ShouldPreferAnother(SUnit *) override
This callback may be invoked if getHazardType returns NoHazard.
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
iterator_range< mop_iterator > operands()
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
void EmitInstruction(SUnit *) override
This callback is invoked when an instruction is emitted to be scheduled, to advance the hazard state...
unsigned getHeight() const
getHeight - Return the height of this node, which is the length of the maximum path down to any node ...
void AdvanceCycle() override
This callback is invoked whenever the next top-down instruction to be scheduled cannot issue in the c...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
HazardType getHazardType(SUnit *SU, int stalls) override
Return the hazard type of emitting this node.
void Reset() override
This callback is invoked when a new block of instructions is about to be scheduled.
void reserveResources(const llvm::MCInstrDesc *MID)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
const MachineOperand & getOperand(unsigned i) const
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Representation of each machine instruction.
int getDotNewOp(const MachineInstr &MI) const
bool mayBeNewStore(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool mayBeCurLoad(const MachineInstr &MI) const
SmallVector< SDep, 4 > Succs
SUnit - Scheduling unit. This is a node in the scheduling DAG.