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LLVM
4.0.0
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#include "ARM.h"#include "ARMBaseInstrInfo.h"#include "ARMBaseRegisterInfo.h"#include "ARMConstantPoolValue.h"#include "ARMFeatures.h"#include "ARMHazardRecognizer.h"#include "ARMMachineFunctionInfo.h"#include "MCTargetDesc/ARMAddressingModes.h"#include "llvm/ADT/STLExtras.h"#include "llvm/CodeGen/LiveVariables.h"#include "llvm/CodeGen/MachineConstantPool.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/CodeGen/TargetSchedule.h"#include "llvm/IR/Constants.h"#include "llvm/IR/Function.h"#include "llvm/IR/GlobalValue.h"#include "llvm/MC/MCAsmInfo.h"#include "llvm/MC/MCExpr.h"#include "llvm/Support/BranchProbability.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/raw_ostream.h"#include "ARMGenInstrInfo.inc"Go to the source code of this file.
Classes | |
| struct | ARM_MLxEntry |
| ARM_MLxEntry - Record information about MLA / MLS instructions. More... | |
| struct | AddSubFlagsOpcodePair |
| Map pseudo instructions that imply an 'S' bit onto real opcodes. More... | |
Namespaces | |
| llvm | |
| Compute iterated dominance frontiers using a linear time algorithm. | |
Macros | |
| #define | DEBUG_TYPE "arm-instrinfo" |
| #define | GET_INSTRINFO_CTOR_DTOR |
Enumerations | |
| enum | ARMExeDomain { ExeGeneric = 0, ExeVFP = 1, ExeNEON = 2 } |
Functions | |
| static bool | isCPSRDefined (const MachineInstr *MI) |
| static bool | isEligibleForITBlock (const MachineInstr *MI) |
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| bool | llvm::IsCPSRDead< MachineInstr > (MachineInstr *MI) |
| static unsigned | duplicateCPV (MachineFunction &MF, unsigned &CPI) |
| Create a copy of a const pool value. More... | |
| static MachineInstr * | canFoldIntoMOVCC (unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII) |
| Identify instructions that can be folded into a MOVCC instruction, and return the defining instruction. More... | |
| static bool | isSuitableForMask (MachineInstr *&MI, unsigned SrcReg, int CmpMask, bool CommonUse) |
| isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register and applies the same mask as a 'tst' instruction. More... | |
| static ARMCC::CondCodes | getSwappedCondition (ARMCC::CondCodes CC) |
| getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a). More... | |
| static bool | isRedundantFlagInstr (MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) |
| isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant. More... | |
| static unsigned | getNumMicroOpsSwiftLdSt (const InstrItineraryData *ItinData, const MachineInstr &MI) |
| static unsigned | getNumMicroOpsSingleIssuePlusExtras (unsigned Opc, unsigned NumRegs) |
| static const MachineInstr * | getBundledDefMI (const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) |
| static const MachineInstr * | getBundledUseMI (const TargetRegisterInfo *TRI, const MachineInstr &MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) |
| static int | adjustDefLatency (const ARMSubtarget &Subtarget, const MachineInstr &DefMI, const MCInstrDesc &DefMCID, unsigned DefAlign) |
| Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode and alignment. More... | |
| static unsigned | getCorrespondingDRegAndLane (const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) |
| static bool | getImplicitSPRUseForDPRUse (const TargetRegisterInfo *TRI, MachineInstr &MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) |
| getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register number that must be marked as implicit-use or zero if no register needs to be defined as implicit-use. More... | |
Variables | |
| static cl::opt< bool > | EnableARM3Addr ("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv")) |
| static const ARM_MLxEntry | ARM_MLxTable [] |
| static const AddSubFlagsOpcodePair | AddSubFlagsOpcodeMap [] |
| #define DEBUG_TYPE "arm-instrinfo" |
Definition at line 45 of file ARMBaseInstrInfo.cpp.
| #define GET_INSTRINFO_CTOR_DTOR |
Definition at line 47 of file ARMBaseInstrInfo.cpp.
| enum ARMExeDomain |
| Enumerator | |
|---|---|
| ExeGeneric | |
| ExeVFP | |
| ExeNEON | |
Definition at line 4220 of file ARMBaseInstrInfo.cpp.
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Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode and alignment.
The caller will ensure that adjusted latency is at least one cycle.
Definition at line 3535 of file ARMBaseInstrInfo.cpp.
References llvm::ARMSubtarget::checkVLDnAccessAlignment(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::ARMSubtarget::isLikeA9(), llvm::ARMSubtarget::isSwift(), llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, and llvm::ARM_AM::sub.
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Identify instructions that can be folded into a MOVCC instruction, and return the defining instruction.
Definition at line 1836 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), i, llvm::MachineOperand::isCPI(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isJTI(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineInstr::isPredicable(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), llvm::MachineOperand::isTied(), llvm::TargetRegisterInfo::isVirtualRegister(), and MI.
Referenced by llvm::ARMBaseInstrInfo::optimizeSelect().
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Create a copy of a const pool value.
Update CPI to the new index and return the label UID.
Definition at line 1371 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::ARMCP::CPBlockAddress, llvm::ARMCP::CPLSDA, llvm::ARMCP::CPValue, llvm::ARMConstantPoolConstant::Create(), llvm::ARMFunctionInfo::createPICLabelUId(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::MachineConstantPool::getConstants(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::object::getSymbol(), and llvm_unreachable.
Referenced by llvm::ARMBaseInstrInfo::duplicate(), and llvm::ARMBaseInstrInfo::reMaterialize().
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Definition at line 3480 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), I, and MI.
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 3503 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), and llvm::MachineBasicBlock::instr_end().
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency().
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Definition at line 4262 of file ARMBaseInstrInfo.cpp.
References assert(), and llvm::TargetRegisterInfo::getMatchingSuperReg().
Referenced by llvm::ARMBaseInstrInfo::setExecutionDomain().
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getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register number that must be marked as implicit-use or zero if no register needs to be defined as implicit-use.
If the function cannot determine if an SPR should be marked implicit use or not, it returns false.
This function handles cases where an instruction is being modified from taking an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict with an earlier def of an SPR corresponding to DPRLane^1.
If the other SPR is defined, an implicit-use of it should be added. Else, (including the case where the DPR itself is defined), it should not.
Definition at line 4292 of file ARMBaseInstrInfo.cpp.
References llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::getParent(), llvm::MCRegisterInfo::getSubReg(), llvm::MachineBasicBlock::LQR_Live, llvm::MachineBasicBlock::LQR_Unknown, and llvm::MachineInstr::readsRegister().
Referenced by llvm::ARMBaseInstrInfo::setExecutionDomain().
Definition at line 3071 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().
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Definition at line 2813 of file ARMBaseInstrInfo.cpp.
References assert(), Desc, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::InstrItineraryData::getNumMicroOps(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MCInstrDesc::getSchedClass(), llvm::ARM_AM::lsl, and llvm::ARM_AM::sub.
Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().
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getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
Definition at line 2360 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ARMCC::NE.
Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().
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Definition at line 540 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::operands().
Referenced by isEligibleForITBlock().
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Definition at line 547 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isCPSRDefined().
Referenced by llvm::ARMBaseInstrInfo::isPredicable().
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isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant.
CMPrr can be made redundant by SUBrr if the operands are the same. CMPri can be made redundant by SUBri if the operands are the same. This function can be extended later on.
Definition at line 2381 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().
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isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register and applies the same mask as a 'tst' instruction.
Provide a limited look-through for copies. When successful, MI will hold the found instruction.
Definition at line 2342 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr().
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Definition at line 1971 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::convertAddSubFlagsOpcode().
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Definition at line 63 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMBaseInstrInfo::ARMBaseInstrInfo(), and llvm::ARMBaseInstrInfo::isFpMLxInstruction().
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Referenced by llvm::ARMBaseInstrInfo::convertToThreeAddress().
1.8.6