LLVM  4.0.0
AArch64InstrInfo.h
Go to the documentation of this file.
1 //===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
16 
17 #include "AArch64.h"
18 #include "AArch64RegisterInfo.h"
21 
22 #define GET_INSTRINFO_HEADER
23 #include "AArch64GenInstrInfo.inc"
24 
25 namespace llvm {
26 
27 class AArch64Subtarget;
28 class AArch64TargetMachine;
29 
30 class AArch64InstrInfo final : public AArch64GenInstrInfo {
31  const AArch64RegisterInfo RI;
32  const AArch64Subtarget &Subtarget;
33 
34 public:
35  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
36 
37  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38  /// such, whenever a client has an instance of instruction info, it should
39  /// always be able to get register info as well (through this method).
40  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
41 
42  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
43 
44  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
45 
46  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
47  unsigned &DstReg, unsigned &SubIdx) const override;
48 
49  bool
51  AliasAnalysis *AA = nullptr) const override;
52 
53  unsigned isLoadFromStackSlot(const MachineInstr &MI,
54  int &FrameIndex) const override;
55  unsigned isStoreToStackSlot(const MachineInstr &MI,
56  int &FrameIndex) const override;
57 
58  /// Returns true if there is a shiftable register and that the shift value
59  /// is non-zero.
60  bool hasShiftedReg(const MachineInstr &MI) const;
61 
62  /// Returns true if there is an extendable register and that the extending
63  /// value is non-zero.
64  bool hasExtendedReg(const MachineInstr &MI) const;
65 
66  /// \brief Does this instruction set its full destination register to zero?
67  bool isGPRZero(const MachineInstr &MI) const;
68 
69  /// \brief Does this instruction rename a GPR without modifying bits?
70  bool isGPRCopy(const MachineInstr &MI) const;
71 
72  /// \brief Does this instruction rename an FPR without modifying bits?
73  bool isFPRCopy(const MachineInstr &MI) const;
74 
75  /// Return true if this is load/store scales or extends its register offset.
76  /// This refers to scaling a dynamic index as opposed to scaled immediates.
77  /// MI should be a memory op that allows scaled addressing.
78  bool isScaledAddr(const MachineInstr &MI) const;
79 
80  /// Return true if pairing the given load or store is hinted to be
81  /// unprofitable.
82  bool isLdStPairSuppressed(const MachineInstr &MI) const;
83 
84  /// Return true if this is an unscaled load/store.
85  bool isUnscaledLdSt(unsigned Opc) const;
86 
87  /// Return true if this is an unscaled load/store.
88  bool isUnscaledLdSt(MachineInstr &MI) const;
89 
90  static bool isPairableLdStInst(const MachineInstr &MI) {
91  switch (MI.getOpcode()) {
92  default:
93  return false;
94  // Scaled instructions.
95  case AArch64::STRSui:
96  case AArch64::STRDui:
97  case AArch64::STRQui:
98  case AArch64::STRXui:
99  case AArch64::STRWui:
100  case AArch64::LDRSui:
101  case AArch64::LDRDui:
102  case AArch64::LDRQui:
103  case AArch64::LDRXui:
104  case AArch64::LDRWui:
105  case AArch64::LDRSWui:
106  // Unscaled instructions.
107  case AArch64::STURSi:
108  case AArch64::STURDi:
109  case AArch64::STURQi:
110  case AArch64::STURWi:
111  case AArch64::STURXi:
112  case AArch64::LDURSi:
113  case AArch64::LDURDi:
114  case AArch64::LDURQi:
115  case AArch64::LDURWi:
116  case AArch64::LDURXi:
117  case AArch64::LDURSWi:
118  return true;
119  }
120  }
121 
122  /// Return true if this is a load/store that can be potentially paired/merged.
124 
125  /// Hint that pairing the given load or store is unprofitable.
126  void suppressLdStPair(MachineInstr &MI) const;
127 
128  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
129  int64_t &Offset,
130  const TargetRegisterInfo *TRI) const override;
131 
132  bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
133  int64_t &Offset, unsigned &Width,
134  const TargetRegisterInfo *TRI) const;
135 
136  bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt,
137  unsigned NumLoads) const override;
138 
139  bool shouldScheduleAdjacent(const MachineInstr &First,
140  const MachineInstr &Second) const override;
141 
143  uint64_t Offset, const MDNode *Var,
144  const MDNode *Expr,
145  const DebugLoc &DL) const;
147  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
148  bool KillSrc, unsigned Opcode,
149  llvm::ArrayRef<unsigned> Indices) const;
151  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
152  bool KillSrc) const override;
153 
155  MachineBasicBlock::iterator MBBI, unsigned SrcReg,
156  bool isKill, int FrameIndex,
157  const TargetRegisterClass *RC,
158  const TargetRegisterInfo *TRI) const override;
159 
161  MachineBasicBlock::iterator MBBI, unsigned DestReg,
162  int FrameIndex, const TargetRegisterClass *RC,
163  const TargetRegisterInfo *TRI) const override;
164 
165  // This tells target independent code that it is okay to pass instructions
166  // with subreg operands to foldMemoryOperandImpl.
167  bool isSubregFoldable() const override { return true; }
168 
170  MachineInstr *
172  ArrayRef<unsigned> Ops,
174  LiveIntervals *LIS = nullptr) const override;
175 
176  /// \returns true if a branch from an instruction with opcode \p BranchOpc
177  /// bytes is capable of jumping to a position \p BrOffset bytes away.
178  bool isBranchOffsetInRange(unsigned BranchOpc,
179  int64_t BrOffset) const override;
180 
181  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
182 
184  MachineBasicBlock *&FBB,
186  bool AllowModify = false) const override;
188  int *BytesRemoved = nullptr) const override;
191  const DebugLoc &DL,
192  int *BytesAdded = nullptr) const override;
193  bool
196  unsigned, unsigned, int &, int &, int &) const override;
198  const DebugLoc &DL, unsigned DstReg,
199  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
200  unsigned FalseReg) const override;
201  void getNoopForMachoTarget(MCInst &NopInst) const override;
202 
203  /// analyzeCompare - For a comparison instruction, return the source registers
204  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
205  /// Return true if the comparison instruction can be analyzed.
206  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
207  unsigned &SrcReg2, int &CmpMask,
208  int &CmpValue) const override;
209  /// optimizeCompareInstr - Convert the instruction supplying the argument to
210  /// the comparison into one that sets the zero bit in the flags register.
211  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
212  unsigned SrcReg2, int CmpMask, int CmpValue,
213  const MachineRegisterInfo *MRI) const override;
214  bool optimizeCondBranch(MachineInstr &MI) const override;
215 
216  /// Return true when a code sequence can improve throughput. It
217  /// should be called only for instructions in loops.
218  /// \param Pattern - combiner pattern
219  bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
220  /// Return true when there is potentially a faster code sequence
221  /// for an instruction chain ending in <Root>. All potential patterns are
222  /// listed in the <Patterns> array.
225  const override;
226  /// Return true when Inst is associative and commutative so that it can be
227  /// reassociated.
228  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
229  /// When getMachineCombinerPatterns() finds patterns, this function generates
230  /// the instructions that could replace the original code sequence
232  MachineInstr &Root, MachineCombinerPattern Pattern,
235  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
236  /// AArch64 supports MachineCombiner.
237  bool useMachineCombiner() const override;
238 
239  bool expandPostRAPseudo(MachineInstr &MI) const override;
240 
241  std::pair<unsigned, unsigned>
242  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
247 
248 private:
249  void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
250  MachineBasicBlock *TBB,
251  ArrayRef<MachineOperand> Cond) const;
252  bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
253  const MachineRegisterInfo *MRI) const;
254 };
255 
256 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
257 /// plus Offset. This is intended to be used from within the prolog/epilog
258 /// insertion (PEI) pass, where a virtual scratch register may be allocated
259 /// if necessary, to be replaced by the scavenger at the end of PEI.
260 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
261  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
262  int Offset, const TargetInstrInfo *TII,
264  bool SetNZCV = false);
265 
266 /// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
267 /// FP. Return false if the offset could not be handled directly in MI, and
268 /// return the left-over portion by reference.
269 bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
270  unsigned FrameReg, int &Offset,
271  const AArch64InstrInfo *TII);
272 
273 /// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
275  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
276  AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
277  AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
278 };
279 
280 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
281 /// The returned value reports the validity of the frame offset for @p MI.
282 /// It uses the values defined by AArch64FrameOffsetStatus for that.
283 /// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
284 /// use an offset.eq
285 /// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
286 /// rewriten in @p MI.
287 /// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
288 /// amount that is off the limit of the legal offset.
289 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
290 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
291 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
292 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
293 /// is a legal offset.
294 int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
295  bool *OutUseUnscaledOp = nullptr,
296  unsigned *OutUnscaledOp = nullptr,
297  int *EmittableOffset = nullptr);
298 
299 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
300 
301 static inline bool isCondBranchOpcode(int Opc) {
302  switch (Opc) {
303  case AArch64::Bcc:
304  case AArch64::CBZW:
305  case AArch64::CBZX:
306  case AArch64::CBNZW:
307  case AArch64::CBNZX:
308  case AArch64::TBZW:
309  case AArch64::TBZX:
310  case AArch64::TBNZW:
311  case AArch64::TBNZX:
312  return true;
313  default:
314  return false;
315  }
316 }
317 
318 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
319 
320 } // end namespace llvm
321 
322 #endif
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isGPRZero(const MachineInstr &MI) const
Does this instruction set its full destination register to zero?
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
bool hasShiftedReg(const MachineInstr &MI) const
Returns true if there is a shiftable register and that the shift value is non-zero.
void suppressLdStPair(MachineInstr &MI) const
Hint that pairing the given load or store is unprofitable.
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
Offset can apply, at least partly.
bool shouldScheduleAdjacent(const MachineInstr &First, const MachineInstr &Second) const override
MachineInstrBundleIterator< MachineInstr > iterator
bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt, unsigned NumLoads) const override
Detect opportunities for ldp/stp formation.
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:830
void getNoopForMachoTarget(MCInst &NopInst) const override
bool hasExtendedReg(const MachineInstr &MI) const
Returns true if there is an extendable register and that the extending value is non-zero.
bool isUnscaledLdSt(unsigned Opc) const
Return true if this is an unscaled load/store.
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Return true when Inst is associative and commutative so that it can be reassociated.
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool useMachineCombiner() const override
AArch64 supports MachineCombiner.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
AArch64InstrInfo(const AArch64Subtarget &STI)
MachineBasicBlock * MBB
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
static bool isCondBranchOpcode(int Opc)
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:551
unsigned const MachineRegisterInfo * MRI
bool isFPRCopy(const MachineInstr &MI) const
Does this instruction rename an FPR without modifying bits?
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var, const MDNode *Expr, const DebugLoc &DL) const
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
uint32_t Offset
static bool isPairableLdStInst(const MachineInstr &MI)
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isThroughputPattern(MachineCombinerPattern Pattern) const override
Return true when a code sequence can improve throughput.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
AArch64FrameOffsetStatus
Use to report the frame offset status in isAArch64FrameOffsetLegal.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool optimizeCondBranch(MachineInstr &MI) const override
Replace csincr-branch sequence by simple conditional branch.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isSubregFoldable() const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2...
bool isScaledAddr(const MachineInstr &MI) const
Return true if this is load/store scales or extends its register offset.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
#define I(x, y, z)
Definition: MD5.cpp:54
bool isLdStPairSuppressed(const MachineInstr &MI) const
Return true if pairing the given load or store is hinted to be unprofitable.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
bool isGPRCopy(const MachineInstr &MI) const
Does this instruction rename a GPR without modifying bits?
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
IRTranslator LLVM IR MI
bool isCandidateToMergeOrPair(MachineInstr &MI) const
Return true if this is a load/store that can be potentially paired/merged.