28 AMDGPUAsmBackend(
const Target &
T)
37 bool &IsResolved)
override;
39 void applyFixup(
const MCFixup &Fixup,
char *Data,
unsigned DataSize,
40 uint64_t
Value,
bool IsPCRel)
const override;
41 bool fixupNeedsRelaxation(
const MCFixup &Fixup, uint64_t
Value,
47 MCInst &Res)
const override {
50 bool mayNeedRelaxation(
const MCInst &Inst)
const override {
return false; }
51 bool writeNopData(uint64_t Count,
MCObjectWriter *OW)
const override;
82 int64_t SignedValue =
static_cast<int64_t
>(Value);
86 int64_t BrImm = (SignedValue - 4) / 4;
132 void AMDGPUAsmBackend::applyFixup(
const MCFixup &Fixup,
char *Data,
133 unsigned DataSize, uint64_t Value,
134 bool IsPCRel)
const {
145 assert(Offset + NumBytes <= DataSize &&
"Invalid fixup offset!");
149 for (
unsigned i = 0;
i != NumBytes; ++
i)
150 Data[Offset +
i] |= static_cast<uint8_t>((Value >> (
i * 8)) & 0xff);
166 bool AMDGPUAsmBackend::writeNopData(uint64_t Count,
MCObjectWriter *OW)
const {
178 class ELFAMDGPUAsmBackend :
public AMDGPUAsmBackend {
180 bool HasRelocationAddend;
183 ELFAMDGPUAsmBackend(
const Target &
T,
const Triple &TT) :
184 AMDGPUAsmBackend(T), Is64Bit(TT.getArch() ==
Triple::amdgcn),
185 HasRelocationAddend(TT.getOS() ==
Triple::AMDHSA) { }
199 return new ELFAMDGPUAsmBackend(T, TT);
void WriteZeros(unsigned N)
This represents an "assembler immediate".
constexpr bool isInt< 16 >(int64_t x)
MCContext & getContext() const
Defines the object file and target independent interfaces used by the assembler backend to write nati...
unsigned TargetOffset
The bit offset to write the relocation into.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Encapsulates the layout of an assembly file at a particular point in time.
A four-byte section relative fixup.
Context object for machine code objects.
A two-byte section relative fixup.
bool isAbsolute() const
Is this an absolute (as opposed to relocatable) value.
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
uint32_t getOffset() const
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
MCObjectWriter * createAMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend, raw_pwrite_stream &OS)
const MCExpr * getValue() const
unsigned const MachineRegisterInfo * MRI
bool evaluateAsValue(MCValue &Res, const MCAsmLayout &Layout) const
Try to evaluate the expression to the form (a - b + constant) where neither a nor b are variables...
MCFixupKind
Extensible enumeration to represent the type of a fixup.
void reportError(SMLoc L, const Twine &Msg)
MCFixupKind getKind() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
A four-byte pc relative fixup.
Target - Wrapper for Target specific information.
A one-byte section relative fixup.
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
Provides AMDGPU specific target descriptions.
static unsigned getFixupKindNumBytes(unsigned Kind)
A eight-byte section relative fixup.
16-bit PC relative fixup for SOPP branch instructions.
MCSubtargetInfo - Generic base class for all target subtargets.
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int64_t getConstant() const
LLVM Value Representation.
Generic interface to target specific assembler backends.
StringRef - Represent a constant reference to a string, i.e.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.