LLVM  4.0.0
MSP430ISelLowering.cpp
Go to the documentation of this file.
1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MSP430TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MSP430ISelLowering.h"
15 #include "MSP430.h"
17 #include "MSP430Subtarget.h"
18 #include "MSP430TargetMachine.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Intrinsics.h"
34 #include "llvm/Support/Debug.h"
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "msp430-lower"
40 
41 typedef enum {
46 
48 HWMultMode("msp430-hwmult-mode", cl::Hidden,
49  cl::desc("Hardware multiplier use mode"),
51  cl::values(
52  clEnumValN(NoHWMult, "no",
53  "Do not use hardware multiplier"),
54  clEnumValN(HWMultIntr, "interrupts",
55  "Assume hardware multiplier can be used inside interrupts"),
56  clEnumValN(HWMultNoIntr, "use",
57  "Assume hardware multiplier cannot be used inside interrupts")));
58 
60  const MSP430Subtarget &STI)
61  : TargetLowering(TM) {
62 
63  // Set up the register classes.
64  addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
65  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
66 
67  // Compute derived properties from the register classes
69 
70  // Provide all sorts of operation actions
73  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
74 
75  // We have post-incremented loads / stores.
78 
79  for (MVT VT : MVT::integer_valuetypes()) {
85  }
86 
87  // We don't have any truncstores
89 
116 
123 
130 
132 
133  // FIXME: Implement efficiently multiplication by a constant
144 
157 
158  // varargs support
164 
165  // Libcalls names.
166  if (HWMultMode == HWMultIntr) {
167  setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
168  setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
169  } else if (HWMultMode == HWMultNoIntr) {
170  setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
171  setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
172  }
173 
176 }
177 
179  SelectionDAG &DAG) const {
180  switch (Op.getOpcode()) {
181  case ISD::SHL: // FALLTHROUGH
182  case ISD::SRL:
183  case ISD::SRA: return LowerShifts(Op, DAG);
184  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
185  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
186  case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
187  case ISD::SETCC: return LowerSETCC(Op, DAG);
188  case ISD::BR_CC: return LowerBR_CC(Op, DAG);
189  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
190  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
191  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
192  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
193  case ISD::VASTART: return LowerVASTART(Op, DAG);
194  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
195  default:
196  llvm_unreachable("unimplemented operand");
197  }
198 }
199 
200 //===----------------------------------------------------------------------===//
201 // MSP430 Inline Assembly Support
202 //===----------------------------------------------------------------------===//
203 
204 /// getConstraintType - Given a constraint letter, return the type of
205 /// constraint it is for this target.
208  if (Constraint.size() == 1) {
209  switch (Constraint[0]) {
210  case 'r':
211  return C_RegisterClass;
212  default:
213  break;
214  }
215  }
216  return TargetLowering::getConstraintType(Constraint);
217 }
218 
219 std::pair<unsigned, const TargetRegisterClass *>
221  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
222  if (Constraint.size() == 1) {
223  // GCC Constraint Letters
224  switch (Constraint[0]) {
225  default: break;
226  case 'r': // GENERAL_REGS
227  if (VT == MVT::i8)
228  return std::make_pair(0U, &MSP430::GR8RegClass);
229 
230  return std::make_pair(0U, &MSP430::GR16RegClass);
231  }
232  }
233 
234  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
235 }
236 
237 //===----------------------------------------------------------------------===//
238 // Calling Convention Implementation
239 //===----------------------------------------------------------------------===//
240 
241 #include "MSP430GenCallingConv.inc"
242 
243 /// For each argument in a function store the number of pieces it is composed
244 /// of.
245 template<typename ArgT>
248  unsigned CurrentArgIndex = ~0U;
249  for (unsigned i = 0, e = Args.size(); i != e; i++) {
250  if (CurrentArgIndex == Args[i].OrigArgIndex) {
251  Out.back()++;
252  } else {
253  Out.push_back(1);
254  CurrentArgIndex++;
255  }
256  }
257 }
258 
259 static void AnalyzeVarArgs(CCState &State,
260  const SmallVectorImpl<ISD::OutputArg> &Outs) {
261  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
262 }
263 
264 static void AnalyzeVarArgs(CCState &State,
266  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
267 }
268 
269 /// Analyze incoming and outgoing function arguments. We need custom C++ code
270 /// to handle special constraints in the ABI like reversing the order of the
271 /// pieces of splitted arguments. In addition, all pieces of a certain argument
272 /// have to be passed either using registers or the stack but never mixing both.
273 template<typename ArgT>
274 static void AnalyzeArguments(CCState &State,
276  const SmallVectorImpl<ArgT> &Args) {
277  static const MCPhysReg RegList[] = {
278  MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
279  };
280  static const unsigned NbRegs = array_lengthof(RegList);
281 
282  if (State.isVarArg()) {
283  AnalyzeVarArgs(State, Args);
284  return;
285  }
286 
287  SmallVector<unsigned, 4> ArgsParts;
288  ParseFunctionArgs(Args, ArgsParts);
289 
290  unsigned RegsLeft = NbRegs;
291  bool UseStack = false;
292  unsigned ValNo = 0;
293 
294  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
295  MVT ArgVT = Args[ValNo].VT;
296  ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
297  MVT LocVT = ArgVT;
299 
300  // Promote i8 to i16
301  if (LocVT == MVT::i8) {
302  LocVT = MVT::i16;
303  if (ArgFlags.isSExt())
304  LocInfo = CCValAssign::SExt;
305  else if (ArgFlags.isZExt())
306  LocInfo = CCValAssign::ZExt;
307  else
308  LocInfo = CCValAssign::AExt;
309  }
310 
311  // Handle byval arguments
312  if (ArgFlags.isByVal()) {
313  State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
314  continue;
315  }
316 
317  unsigned Parts = ArgsParts[i];
318 
319  if (!UseStack && Parts <= RegsLeft) {
320  unsigned FirstVal = ValNo;
321  for (unsigned j = 0; j < Parts; j++) {
322  unsigned Reg = State.AllocateReg(RegList);
323  State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
324  RegsLeft--;
325  }
326 
327  // Reverse the order of the pieces to agree with the "big endian" format
328  // required in the calling convention ABI.
329  SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
330  std::reverse(B, B + Parts);
331  } else {
332  UseStack = true;
333  for (unsigned j = 0; j < Parts; j++)
334  CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
335  }
336  }
337 }
338 
339 static void AnalyzeRetResult(CCState &State,
341  State.AnalyzeCallResult(Ins, RetCC_MSP430);
342 }
343 
344 static void AnalyzeRetResult(CCState &State,
345  const SmallVectorImpl<ISD::OutputArg> &Outs) {
346  State.AnalyzeReturn(Outs, RetCC_MSP430);
347 }
348 
349 template<typename ArgT>
350 static void AnalyzeReturnValues(CCState &State,
352  const SmallVectorImpl<ArgT> &Args) {
353  AnalyzeRetResult(State, Args);
354 
355  // Reverse splitted return values to get the "big endian" format required
356  // to agree with the calling convention ABI.
357  std::reverse(RVLocs.begin(), RVLocs.end());
358 }
359 
360 SDValue MSP430TargetLowering::LowerFormalArguments(
361  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
362  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
363  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
364 
365  switch (CallConv) {
366  default:
367  llvm_unreachable("Unsupported calling convention");
368  case CallingConv::C:
369  case CallingConv::Fast:
370  return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
372  if (Ins.empty())
373  return Chain;
374  report_fatal_error("ISRs cannot have arguments");
375  }
376 }
377 
378 SDValue
379 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
380  SmallVectorImpl<SDValue> &InVals) const {
381  SelectionDAG &DAG = CLI.DAG;
382  SDLoc &dl = CLI.DL;
384  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
386  SDValue Chain = CLI.Chain;
387  SDValue Callee = CLI.Callee;
388  bool &isTailCall = CLI.IsTailCall;
389  CallingConv::ID CallConv = CLI.CallConv;
390  bool isVarArg = CLI.IsVarArg;
391 
392  // MSP430 target does not yet support tail call optimization.
393  isTailCall = false;
394 
395  switch (CallConv) {
396  default:
397  llvm_unreachable("Unsupported calling convention");
398  case CallingConv::Fast:
399  case CallingConv::C:
400  return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
401  Outs, OutVals, Ins, dl, DAG, InVals);
403  report_fatal_error("ISRs cannot be called directly");
404  }
405 }
406 
407 /// LowerCCCArguments - transform physical registers into virtual registers and
408 /// generate load operations for arguments places on the stack.
409 // FIXME: struct return stuff
410 SDValue MSP430TargetLowering::LowerCCCArguments(
411  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
412  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
413  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
415  MachineFrameInfo &MFI = MF.getFrameInfo();
416  MachineRegisterInfo &RegInfo = MF.getRegInfo();
418 
419  // Assign locations to all of the incoming arguments.
421  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
422  *DAG.getContext());
423  AnalyzeArguments(CCInfo, ArgLocs, Ins);
424 
425  // Create frame index for the start of the first vararg value
426  if (isVarArg) {
427  unsigned Offset = CCInfo.getNextStackOffset();
428  FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true));
429  }
430 
431  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
432  CCValAssign &VA = ArgLocs[i];
433  if (VA.isRegLoc()) {
434  // Arguments passed in registers
435  EVT RegVT = VA.getLocVT();
436  switch (RegVT.getSimpleVT().SimpleTy) {
437  default:
438  {
439 #ifndef NDEBUG
440  errs() << "LowerFormalArguments Unhandled argument type: "
441  << RegVT.getEVTString() << "\n";
442 #endif
443  llvm_unreachable(nullptr);
444  }
445  case MVT::i16:
446  unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
447  RegInfo.addLiveIn(VA.getLocReg(), VReg);
448  SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
449 
450  // If this is an 8-bit value, it is really passed promoted to 16
451  // bits. Insert an assert[sz]ext to capture this, then truncate to the
452  // right size.
453  if (VA.getLocInfo() == CCValAssign::SExt)
454  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
455  DAG.getValueType(VA.getValVT()));
456  else if (VA.getLocInfo() == CCValAssign::ZExt)
457  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
458  DAG.getValueType(VA.getValVT()));
459 
460  if (VA.getLocInfo() != CCValAssign::Full)
461  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
462 
463  InVals.push_back(ArgValue);
464  }
465  } else {
466  // Sanity check
467  assert(VA.isMemLoc());
468 
469  SDValue InVal;
470  ISD::ArgFlagsTy Flags = Ins[i].Flags;
471 
472  if (Flags.isByVal()) {
473  int FI = MFI.CreateFixedObject(Flags.getByValSize(),
474  VA.getLocMemOffset(), true);
475  InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
476  } else {
477  // Load the argument to a virtual register
478  unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
479  if (ObjSize > 2) {
480  errs() << "LowerFormalArguments Unhandled argument type: "
481  << EVT(VA.getLocVT()).getEVTString()
482  << "\n";
483  }
484  // Create the frame index object for this incoming parameter...
485  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
486 
487  // Create the SelectionDAG nodes corresponding to a load
488  //from this parameter
489  SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
490  InVal = DAG.getLoad(
491  VA.getLocVT(), dl, Chain, FIN,
493  }
494 
495  InVals.push_back(InVal);
496  }
497  }
498 
499  return Chain;
500 }
501 
502 SDValue
503 MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
504  bool isVarArg,
506  const SmallVectorImpl<SDValue> &OutVals,
507  const SDLoc &dl, SelectionDAG &DAG) const {
508 
509  // CCValAssign - represent the assignment of the return value to a location
511 
512  // ISRs cannot return any value.
513  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
514  report_fatal_error("ISRs cannot return any value");
515 
516  // CCState - Info about the registers and stack slot.
517  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
518  *DAG.getContext());
519 
520  // Analize return values.
521  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
522 
523  SDValue Flag;
524  SmallVector<SDValue, 4> RetOps(1, Chain);
525 
526  // Copy the result values into the output registers.
527  for (unsigned i = 0; i != RVLocs.size(); ++i) {
528  CCValAssign &VA = RVLocs[i];
529  assert(VA.isRegLoc() && "Can only return in registers!");
530 
531  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
532  OutVals[i], Flag);
533 
534  // Guarantee that all emitted copies are stuck together,
535  // avoiding something bad.
536  Flag = Chain.getValue(1);
537  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
538  }
539 
540  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
542 
543  RetOps[0] = Chain; // Update chain.
544 
545  // Add the flag if we have it.
546  if (Flag.getNode())
547  RetOps.push_back(Flag);
548 
549  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
550 }
551 
552 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
553 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
554 // TODO: sret.
555 SDValue MSP430TargetLowering::LowerCCCCallTo(
556  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
557  bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs,
558  const SmallVectorImpl<SDValue> &OutVals,
559  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
560  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
561  // Analyze operands of the call, assigning locations to each operand.
563  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
564  *DAG.getContext());
565  AnalyzeArguments(CCInfo, ArgLocs, Outs);
566 
567  // Get a count of how many bytes are to be pushed on the stack.
568  unsigned NumBytes = CCInfo.getNextStackOffset();
569  auto PtrVT = getPointerTy(DAG.getDataLayout());
570 
571  Chain = DAG.getCALLSEQ_START(Chain,
572  DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
573 
575  SmallVector<SDValue, 12> MemOpChains;
576  SDValue StackPtr;
577 
578  // Walk the register/memloc assignments, inserting copies/loads.
579  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
580  CCValAssign &VA = ArgLocs[i];
581 
582  SDValue Arg = OutVals[i];
583 
584  // Promote the value if needed.
585  switch (VA.getLocInfo()) {
586  default: llvm_unreachable("Unknown loc info!");
587  case CCValAssign::Full: break;
588  case CCValAssign::SExt:
589  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
590  break;
591  case CCValAssign::ZExt:
592  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
593  break;
594  case CCValAssign::AExt:
595  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
596  break;
597  }
598 
599  // Arguments that can be passed on register must be kept at RegsToPass
600  // vector
601  if (VA.isRegLoc()) {
602  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
603  } else {
604  assert(VA.isMemLoc());
605 
606  if (!StackPtr.getNode())
607  StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
608 
609  SDValue PtrOff =
610  DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
611  DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
612 
613  SDValue MemOp;
614  ISD::ArgFlagsTy Flags = Outs[i].Flags;
615 
616  if (Flags.isByVal()) {
617  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
618  MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
619  Flags.getByValAlign(),
620  /*isVolatile*/false,
621  /*AlwaysInline=*/true,
622  /*isTailCall=*/false,
625  } else {
626  MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());
627  }
628 
629  MemOpChains.push_back(MemOp);
630  }
631  }
632 
633  // Transform all store nodes into one single node because all store nodes are
634  // independent of each other.
635  if (!MemOpChains.empty())
636  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
637 
638  // Build a sequence of copy-to-reg nodes chained together with token chain and
639  // flag operands which copy the outgoing args into registers. The InFlag in
640  // necessary since all emitted instructions must be stuck together.
641  SDValue InFlag;
642  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
643  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
644  RegsToPass[i].second, InFlag);
645  InFlag = Chain.getValue(1);
646  }
647 
648  // If the callee is a GlobalAddress node (quite common, every direct call is)
649  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
650  // Likewise ExternalSymbol -> TargetExternalSymbol.
651  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
652  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
653  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
654  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
655 
656  // Returns a chain & a flag for retval copy to use.
657  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
659  Ops.push_back(Chain);
660  Ops.push_back(Callee);
661 
662  // Add argument registers to the end of the list so that they are
663  // known live into the call.
664  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
665  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
666  RegsToPass[i].second.getValueType()));
667 
668  if (InFlag.getNode())
669  Ops.push_back(InFlag);
670 
671  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
672  InFlag = Chain.getValue(1);
673 
674  // Create the CALLSEQ_END node.
675  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
676  DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
677  InFlag = Chain.getValue(1);
678 
679  // Handle result values, copying them out of physregs into vregs that we
680  // return.
681  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
682  DAG, InVals);
683 }
684 
685 /// LowerCallResult - Lower the result values of a call into the
686 /// appropriate copies out of appropriate physical registers.
687 ///
688 SDValue MSP430TargetLowering::LowerCallResult(
689  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
690  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
691  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
692 
693  // Assign locations to each value returned by this call.
695  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
696  *DAG.getContext());
697 
698  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
699 
700  // Copy all of the result registers out of their specified physreg.
701  for (unsigned i = 0; i != RVLocs.size(); ++i) {
702  Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
703  RVLocs[i].getValVT(), InFlag).getValue(1);
704  InFlag = Chain.getValue(2);
705  InVals.push_back(Chain.getValue(0));
706  }
707 
708  return Chain;
709 }
710 
712  SelectionDAG &DAG) const {
713  unsigned Opc = Op.getOpcode();
714  SDNode* N = Op.getNode();
715  EVT VT = Op.getValueType();
716  SDLoc dl(N);
717 
718  // Expand non-constant shifts to loops:
719  if (!isa<ConstantSDNode>(N->getOperand(1)))
720  switch (Opc) {
721  default: llvm_unreachable("Invalid shift opcode!");
722  case ISD::SHL:
723  return DAG.getNode(MSP430ISD::SHL, dl,
724  VT, N->getOperand(0), N->getOperand(1));
725  case ISD::SRA:
726  return DAG.getNode(MSP430ISD::SRA, dl,
727  VT, N->getOperand(0), N->getOperand(1));
728  case ISD::SRL:
729  return DAG.getNode(MSP430ISD::SRL, dl,
730  VT, N->getOperand(0), N->getOperand(1));
731  }
732 
733  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
734 
735  // Expand the stuff into sequence of shifts.
736  // FIXME: for some shift amounts this might be done better!
737  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
738  SDValue Victim = N->getOperand(0);
739 
740  if (Opc == ISD::SRL && ShiftAmount) {
741  // Emit a special goodness here:
742  // srl A, 1 => clrc; rrc A
743  Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
744  ShiftAmount -= 1;
745  }
746 
747  while (ShiftAmount--)
748  Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
749  dl, VT, Victim);
750 
751  return Victim;
752 }
753 
755  SelectionDAG &DAG) const {
756  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
757  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
758  auto PtrVT = getPointerTy(DAG.getDataLayout());
759 
760  // Create the TargetGlobalAddress node, folding in the constant offset.
761  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
762  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
763 }
764 
766  SelectionDAG &DAG) const {
767  SDLoc dl(Op);
768  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
769  auto PtrVT = getPointerTy(DAG.getDataLayout());
770  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
771 
772  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
773 }
774 
776  SelectionDAG &DAG) const {
777  SDLoc dl(Op);
778  auto PtrVT = getPointerTy(DAG.getDataLayout());
779  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
780  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
781 
782  return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
783 }
784 
785 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
786  ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) {
787  // FIXME: Handle bittests someday
788  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
789 
790  // FIXME: Handle jump negative someday
792  switch (CC) {
793  default: llvm_unreachable("Invalid integer condition!");
794  case ISD::SETEQ:
795  TCC = MSP430CC::COND_E; // aka COND_Z
796  // Minor optimization: if LHS is a constant, swap operands, then the
797  // constant can be folded into comparison.
798  if (LHS.getOpcode() == ISD::Constant)
799  std::swap(LHS, RHS);
800  break;
801  case ISD::SETNE:
802  TCC = MSP430CC::COND_NE; // aka COND_NZ
803  // Minor optimization: if LHS is a constant, swap operands, then the
804  // constant can be folded into comparison.
805  if (LHS.getOpcode() == ISD::Constant)
806  std::swap(LHS, RHS);
807  break;
808  case ISD::SETULE:
809  std::swap(LHS, RHS);
811  case ISD::SETUGE:
812  // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
813  // fold constant into instruction.
814  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
815  LHS = RHS;
816  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
817  TCC = MSP430CC::COND_LO;
818  break;
819  }
820  TCC = MSP430CC::COND_HS; // aka COND_C
821  break;
822  case ISD::SETUGT:
823  std::swap(LHS, RHS);
825  case ISD::SETULT:
826  // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
827  // fold constant into instruction.
828  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
829  LHS = RHS;
830  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
831  TCC = MSP430CC::COND_HS;
832  break;
833  }
834  TCC = MSP430CC::COND_LO; // aka COND_NC
835  break;
836  case ISD::SETLE:
837  std::swap(LHS, RHS);
839  case ISD::SETGE:
840  // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
841  // fold constant into instruction.
842  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
843  LHS = RHS;
844  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
845  TCC = MSP430CC::COND_L;
846  break;
847  }
848  TCC = MSP430CC::COND_GE;
849  break;
850  case ISD::SETGT:
851  std::swap(LHS, RHS);
853  case ISD::SETLT:
854  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
855  // fold constant into instruction.
856  if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
857  LHS = RHS;
858  RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
859  TCC = MSP430CC::COND_GE;
860  break;
861  }
862  TCC = MSP430CC::COND_L;
863  break;
864  }
865 
866  TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
867  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
868 }
869 
870 
872  SDValue Chain = Op.getOperand(0);
873  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
874  SDValue LHS = Op.getOperand(2);
875  SDValue RHS = Op.getOperand(3);
876  SDValue Dest = Op.getOperand(4);
877  SDLoc dl (Op);
878 
879  SDValue TargetCC;
880  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
881 
882  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
883  Chain, Dest, TargetCC, Flag);
884 }
885 
887  SDValue LHS = Op.getOperand(0);
888  SDValue RHS = Op.getOperand(1);
889  SDLoc dl (Op);
890 
891  // If we are doing an AND and testing against zero, then the CMP
892  // will not be generated. The AND (or BIT) will generate the condition codes,
893  // but they are different from CMP.
894  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
895  // lowering & isel wouldn't diverge.
896  bool andCC = false;
897  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
898  if (RHSC->isNullValue() && LHS.hasOneUse() &&
899  (LHS.getOpcode() == ISD::AND ||
900  (LHS.getOpcode() == ISD::TRUNCATE &&
901  LHS.getOperand(0).getOpcode() == ISD::AND))) {
902  andCC = true;
903  }
904  }
905  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
906  SDValue TargetCC;
907  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
908 
909  // Get the condition codes directly from the status register, if its easy.
910  // Otherwise a branch will be generated. Note that the AND and BIT
911  // instructions generate different flags than CMP, the carry bit can be used
912  // for NE/EQ.
913  bool Invert = false;
914  bool Shift = false;
915  bool Convert = true;
916  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
917  default:
918  Convert = false;
919  break;
920  case MSP430CC::COND_HS:
921  // Res = SR & 1, no processing is required
922  break;
923  case MSP430CC::COND_LO:
924  // Res = ~(SR & 1)
925  Invert = true;
926  break;
927  case MSP430CC::COND_NE:
928  if (andCC) {
929  // C = ~Z, thus Res = SR & 1, no processing is required
930  } else {
931  // Res = ~((SR >> 1) & 1)
932  Shift = true;
933  Invert = true;
934  }
935  break;
936  case MSP430CC::COND_E:
937  Shift = true;
938  // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
939  // Res = (SR >> 1) & 1 is 1 word shorter.
940  break;
941  }
942  EVT VT = Op.getValueType();
943  SDValue One = DAG.getConstant(1, dl, VT);
944  if (Convert) {
945  SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
946  MVT::i16, Flag);
947  if (Shift)
948  // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
949  SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
950  SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
951  if (Invert)
952  SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
953  return SR;
954  } else {
955  SDValue Zero = DAG.getConstant(0, dl, VT);
956  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
957  SDValue Ops[] = {One, Zero, TargetCC, Flag};
958  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
959  }
960 }
961 
963  SelectionDAG &DAG) const {
964  SDValue LHS = Op.getOperand(0);
965  SDValue RHS = Op.getOperand(1);
966  SDValue TrueV = Op.getOperand(2);
967  SDValue FalseV = Op.getOperand(3);
968  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
969  SDLoc dl (Op);
970 
971  SDValue TargetCC;
972  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
973 
974  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
975  SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
976 
977  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
978 }
979 
981  SelectionDAG &DAG) const {
982  SDValue Val = Op.getOperand(0);
983  EVT VT = Op.getValueType();
984  SDLoc dl(Op);
985 
986  assert(VT == MVT::i16 && "Only support i16 for now!");
987 
988  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
989  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
990  DAG.getValueType(Val.getValueType()));
991 }
992 
993 SDValue
997  int ReturnAddrIndex = FuncInfo->getRAIndex();
998  auto PtrVT = getPointerTy(MF.getDataLayout());
999 
1000  if (ReturnAddrIndex == 0) {
1001  // Set up a frame object for the return address.
1002  uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1003  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize,
1004  true);
1005  FuncInfo->setRAIndex(ReturnAddrIndex);
1006  }
1007 
1008  return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1009 }
1010 
1012  SelectionDAG &DAG) const {
1014  MFI.setReturnAddressIsTaken(true);
1015 
1017  return SDValue();
1018 
1019  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1020  SDLoc dl(Op);
1021  auto PtrVT = getPointerTy(DAG.getDataLayout());
1022 
1023  if (Depth > 0) {
1024  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1025  SDValue Offset =
1027  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1028  DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1029  MachinePointerInfo());
1030  }
1031 
1032  // Just load the return address.
1033  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1034  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1035  MachinePointerInfo());
1036 }
1037 
1039  SelectionDAG &DAG) const {
1041  MFI.setFrameAddressIsTaken(true);
1042 
1043  EVT VT = Op.getValueType();
1044  SDLoc dl(Op); // FIXME probably not meaningful
1045  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1046  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1047  MSP430::FP, VT);
1048  while (Depth--)
1049  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1050  MachinePointerInfo());
1051  return FrameAddr;
1052 }
1053 
1055  SelectionDAG &DAG) const {
1056  MachineFunction &MF = DAG.getMachineFunction();
1058  auto PtrVT = getPointerTy(DAG.getDataLayout());
1059 
1060  // Frame index of first vararg argument
1062  DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1063  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1064 
1065  // Create a store of the frame index to the location operand
1066  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1),
1067  MachinePointerInfo(SV));
1068 }
1069 
1071  SelectionDAG &DAG) const {
1072  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1073  auto PtrVT = getPointerTy(DAG.getDataLayout());
1074  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1075  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1076 }
1077 
1078 /// getPostIndexedAddressParts - returns true by value, base pointer and
1079 /// offset pointer and addressing mode by reference if this node can be
1080 /// combined with a load / store to form a post-indexed load / store.
1081 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1082  SDValue &Base,
1083  SDValue &Offset,
1084  ISD::MemIndexedMode &AM,
1085  SelectionDAG &DAG) const {
1086 
1087  LoadSDNode *LD = cast<LoadSDNode>(N);
1088  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1089  return false;
1090 
1091  EVT VT = LD->getMemoryVT();
1092  if (VT != MVT::i8 && VT != MVT::i16)
1093  return false;
1094 
1095  if (Op->getOpcode() != ISD::ADD)
1096  return false;
1097 
1098  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1099  uint64_t RHSC = RHS->getZExtValue();
1100  if ((VT == MVT::i16 && RHSC != 2) ||
1101  (VT == MVT::i8 && RHSC != 1))
1102  return false;
1103 
1104  Base = Op->getOperand(0);
1105  Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1106  AM = ISD::POST_INC;
1107  return true;
1108  }
1109 
1110  return false;
1111 }
1112 
1113 
1114 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1115  switch ((MSP430ISD::NodeType)Opcode) {
1116  case MSP430ISD::FIRST_NUMBER: break;
1117  case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1118  case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1119  case MSP430ISD::RRA: return "MSP430ISD::RRA";
1120  case MSP430ISD::RLA: return "MSP430ISD::RLA";
1121  case MSP430ISD::RRC: return "MSP430ISD::RRC";
1122  case MSP430ISD::CALL: return "MSP430ISD::CALL";
1123  case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1124  case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1125  case MSP430ISD::CMP: return "MSP430ISD::CMP";
1126  case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1127  case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1128  case MSP430ISD::SHL: return "MSP430ISD::SHL";
1129  case MSP430ISD::SRA: return "MSP430ISD::SRA";
1130  case MSP430ISD::SRL: return "MSP430ISD::SRL";
1131  }
1132  return nullptr;
1133 }
1134 
1136  Type *Ty2) const {
1137  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1138  return false;
1139 
1140  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1141 }
1142 
1144  if (!VT1.isInteger() || !VT2.isInteger())
1145  return false;
1146 
1147  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1148 }
1149 
1151  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1152  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1153 }
1154 
1156  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1157  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1158 }
1159 
1161  return isZExtFree(Val.getValueType(), VT2);
1162 }
1163 
1164 //===----------------------------------------------------------------------===//
1165 // Other Lowering Code
1166 //===----------------------------------------------------------------------===//
1167 
1170  MachineBasicBlock *BB) const {
1171  MachineFunction *F = BB->getParent();
1172  MachineRegisterInfo &RI = F->getRegInfo();
1173  DebugLoc dl = MI.getDebugLoc();
1174  const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1175 
1176  unsigned Opc;
1177  const TargetRegisterClass * RC;
1178  switch (MI.getOpcode()) {
1179  default: llvm_unreachable("Invalid shift opcode!");
1180  case MSP430::Shl8:
1181  Opc = MSP430::SHL8r1;
1182  RC = &MSP430::GR8RegClass;
1183  break;
1184  case MSP430::Shl16:
1185  Opc = MSP430::SHL16r1;
1186  RC = &MSP430::GR16RegClass;
1187  break;
1188  case MSP430::Sra8:
1189  Opc = MSP430::SAR8r1;
1190  RC = &MSP430::GR8RegClass;
1191  break;
1192  case MSP430::Sra16:
1193  Opc = MSP430::SAR16r1;
1194  RC = &MSP430::GR16RegClass;
1195  break;
1196  case MSP430::Srl8:
1197  Opc = MSP430::SAR8r1c;
1198  RC = &MSP430::GR8RegClass;
1199  break;
1200  case MSP430::Srl16:
1201  Opc = MSP430::SAR16r1c;
1202  RC = &MSP430::GR16RegClass;
1203  break;
1204  }
1205 
1206  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1208 
1209  // Create loop block
1210  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1211  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1212 
1213  F->insert(I, LoopBB);
1214  F->insert(I, RemBB);
1215 
1216  // Update machine-CFG edges by transferring all successors of the current
1217  // block to the block containing instructions after shift.
1218  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1219  BB->end());
1221 
1222  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1223  BB->addSuccessor(LoopBB);
1224  BB->addSuccessor(RemBB);
1225  LoopBB->addSuccessor(RemBB);
1226  LoopBB->addSuccessor(LoopBB);
1227 
1228  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1229  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1230  unsigned ShiftReg = RI.createVirtualRegister(RC);
1231  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1232  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1233  unsigned SrcReg = MI.getOperand(1).getReg();
1234  unsigned DstReg = MI.getOperand(0).getReg();
1235 
1236  // BB:
1237  // cmp 0, N
1238  // je RemBB
1239  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1240  .addReg(ShiftAmtSrcReg).addImm(0);
1241  BuildMI(BB, dl, TII.get(MSP430::JCC))
1242  .addMBB(RemBB)
1244 
1245  // LoopBB:
1246  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1247  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1248  // ShiftReg2 = shift ShiftReg
1249  // ShiftAmt2 = ShiftAmt - 1;
1250  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1251  .addReg(SrcReg).addMBB(BB)
1252  .addReg(ShiftReg2).addMBB(LoopBB);
1253  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1254  .addReg(ShiftAmtSrcReg).addMBB(BB)
1255  .addReg(ShiftAmtReg2).addMBB(LoopBB);
1256  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1257  .addReg(ShiftReg);
1258  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1259  .addReg(ShiftAmtReg).addImm(1);
1260  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1261  .addMBB(LoopBB)
1263 
1264  // RemBB:
1265  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1266  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1267  .addReg(SrcReg).addMBB(BB)
1268  .addReg(ShiftReg2).addMBB(LoopBB);
1269 
1270  MI.eraseFromParent(); // The pseudo instruction is gone now.
1271  return RemBB;
1272 }
1273 
1276  MachineBasicBlock *BB) const {
1277  unsigned Opc = MI.getOpcode();
1278 
1279  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1280  Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1281  Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1282  return EmitShiftInstr(MI, BB);
1283 
1284  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1285  DebugLoc dl = MI.getDebugLoc();
1286 
1287  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1288  "Unexpected instr type to insert");
1289 
1290  // To "insert" a SELECT instruction, we actually have to insert the diamond
1291  // control-flow pattern. The incoming instruction knows the destination vreg
1292  // to set, the condition code register to branch on, the true/false values to
1293  // select between, and a branch opcode to use.
1294  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1296 
1297  // thisMBB:
1298  // ...
1299  // TrueVal = ...
1300  // cmpTY ccX, r1, r2
1301  // jCC copy1MBB
1302  // fallthrough --> copy0MBB
1303  MachineBasicBlock *thisMBB = BB;
1304  MachineFunction *F = BB->getParent();
1305  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1306  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1307  F->insert(I, copy0MBB);
1308  F->insert(I, copy1MBB);
1309  // Update machine-CFG edges by transferring all successors of the current
1310  // block to the new block which will contain the Phi node for the select.
1311  copy1MBB->splice(copy1MBB->begin(), BB,
1312  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1313  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1314  // Next, add the true and fallthrough blocks as its successors.
1315  BB->addSuccessor(copy0MBB);
1316  BB->addSuccessor(copy1MBB);
1317 
1318  BuildMI(BB, dl, TII.get(MSP430::JCC))
1319  .addMBB(copy1MBB)
1320  .addImm(MI.getOperand(3).getImm());
1321 
1322  // copy0MBB:
1323  // %FalseValue = ...
1324  // # fallthrough to copy1MBB
1325  BB = copy0MBB;
1326 
1327  // Update machine-CFG edges
1328  BB->addSuccessor(copy1MBB);
1329 
1330  // copy1MBB:
1331  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1332  // ...
1333  BB = copy1MBB;
1334  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1335  .addReg(MI.getOperand(2).getReg())
1336  .addMBB(copy0MBB)
1337  .addReg(MI.getOperand(1).getReg())
1338  .addMBB(thisMBB);
1339 
1340  MI.eraseFromParent(); // The pseudo instruction is gone now.
1341  return BB;
1342 }
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
Definition: SmallVector.h:211
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
MVT getValVT() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
LLVMContext * getContext() const
Definition: SelectionDAG.h:333
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:724
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
size_t i
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:572
LocInfo getLocInfo() const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
Definition: CallingConv.h:105
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Y = RRC X, rotate right via carry.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
unsigned getByValSize() const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
A debug info location.
Definition: DebugLoc.h:34
const SDValue & getOperand(unsigned Num) const
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:369
bool isRegLoc() const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:388
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:822
std::string getEVTString() const
getEVTString - This function returns value type as a string, e.g.
Definition: ValueTypes.cpp:120
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterInfo * getRegisterInfo() const override
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:344
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:327
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:123
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
SmallVector< ISD::InputArg, 32 > Ins
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:241
Same as RET_FLAG, but used for returning from ISRs.
unsigned getLocReg() const
#define F(x, y, z)
Definition: MD5.cpp:51
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
int64_t getImm() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:328
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: Object/ELF.h:236
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
ValuesClass values(OptsTy...Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:615
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
MVT getLocVT() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:637
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isVarArg() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
uint32_t Offset
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:81
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:628
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
This class contains a discriminated union of information about pointers in memory operands...
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValAlign() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:540
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:566
const DataFlowGraph & G
Definition: RDFGraph.cpp:206
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:584
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:715
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:354
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:195
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:400
bool isMemLoc() const
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:403
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:590
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:560
Representation of each machine instruction.
Definition: MachineInstr.h:52
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:633
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:578
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:333
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:610
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:418
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:256
static cl::opt< HWMultUseMode > HWMultMode("msp430-hwmult-mode", cl::Hidden, cl::desc("Hardware multiplier use mode"), cl::init(HWMultNoIntr), cl::values(clEnumValN(NoHWMult,"no","Do not use hardware multiplier"), clEnumValN(HWMultIntr,"interrupts","Assume hardware multiplier can be used inside interrupts"), clEnumValN(HWMultNoIntr,"use","Assume hardware multiplier cannot be used inside interrupts")))
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
static volatile int Zero
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
CondCodes
Definition: MSP430.h:23
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
unsigned getReg() const
getReg - Returns the register number.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:118
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setReturnAddressIsTaken(bool s)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:108
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:71
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:377
unsigned getLocMemOffset() const
Conversion operators.
Definition: ISDOpcodes.h:397
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:381
SHL, SRA, SRL - Non-constant shifts.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:406
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:608
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:226
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:529
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:799
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:326
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:545