LLVM  4.0.0
LanaiAsmBackend.cpp
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1 //===-- LanaiAsmBackend.cpp - Lanai Assembler Backend ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "LanaiFixupKinds.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCAssembler.h"
14 #include "llvm/MC/MCDirectives.h"
17 #include "llvm/MC/MCObjectWriter.h"
21 
22 using namespace llvm;
23 
24 // Prepare value for the target space
25 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
26  switch (Kind) {
27  case FK_Data_1:
28  case FK_Data_2:
29  case FK_Data_4:
30  case FK_Data_8:
31  return Value;
38  return Value;
39  default:
40  llvm_unreachable("Unknown fixup kind!");
41  }
42 }
43 
44 namespace {
45 class LanaiAsmBackend : public MCAsmBackend {
46  Triple::OSType OSType;
47 
48 public:
49  LanaiAsmBackend(const Target &T, Triple::OSType OST)
50  : MCAsmBackend(), OSType(OST) {}
51 
52  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
53  uint64_t Value, bool IsPCRel) const override;
54 
55  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
56 
57  // No instruction requires relaxation
58  bool fixupNeedsRelaxation(const MCFixup & /*Fixup*/, uint64_t /*Value*/,
59  const MCRelaxableFragment * /*DF*/,
60  const MCAsmLayout & /*Layout*/) const override {
61  return false;
62  }
63 
64  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
65 
66  unsigned getNumFixupKinds() const override {
68  }
69 
70  bool mayNeedRelaxation(const MCInst & /*Inst*/) const override {
71  return false;
72  }
73 
74  void relaxInstruction(const MCInst & /*Inst*/,
75  const MCSubtargetInfo & /*STI*/,
76  MCInst & /*Res*/) const override {}
77 
78  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
79 };
80 
81 bool LanaiAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
82  if ((Count % 4) != 0)
83  return false;
84 
85  for (uint64_t i = 0; i < Count; i += 4)
86  OW->write32(0x15000000);
87 
88  return true;
89 }
90 
91 void LanaiAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
92  unsigned /*DataSize*/, uint64_t Value,
93  bool /*IsPCRel*/) const {
94  MCFixupKind Kind = Fixup.getKind();
95  Value = adjustFixupValue(static_cast<unsigned>(Kind), Value);
96 
97  if (!Value)
98  return; // This value doesn't change the encoding
99 
100  // Where in the object and where the number of bytes that need
101  // fixing up
102  unsigned Offset = Fixup.getOffset();
103  unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
104  unsigned FullSize = 4;
105 
106  // Grab current value, if any, from bits.
107  uint64_t CurVal = 0;
108 
109  // Load instruction and apply value
110  for (unsigned i = 0; i != NumBytes; ++i) {
111  unsigned Idx = (FullSize - 1 - i);
112  CurVal |= static_cast<uint64_t>(static_cast<uint8_t>(Data[Offset + Idx]))
113  << (i * 8);
114  }
115 
116  uint64_t Mask =
117  (static_cast<uint64_t>(-1) >> (64 - getFixupKindInfo(Kind).TargetSize));
118  CurVal |= Value & Mask;
119 
120  // Write out the fixed up bytes back to the code/data bits.
121  for (unsigned i = 0; i != NumBytes; ++i) {
122  unsigned Idx = (FullSize - 1 - i);
123  Data[Offset + Idx] = static_cast<uint8_t>((CurVal >> (i * 8)) & 0xff);
124  }
125 }
126 
128 LanaiAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
129  return createLanaiELFObjectWriter(OS,
131 }
132 
133 const MCFixupKindInfo &
134 LanaiAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
135  static const MCFixupKindInfo Infos[Lanai::NumTargetFixupKinds] = {
136  // This table *must* be in same the order of fixup_* kinds in
137  // LanaiFixupKinds.h.
138  // Note: The number of bits indicated here are assumed to be contiguous.
139  // This does not hold true for LANAI_21 and LANAI_21_F which are applied
140  // to bits 0x7cffff and 0x7cfffc, respectively. Since the 'bits' counts
141  // here are used only for cosmetic purposes, we set the size to 16 bits
142  // for these 21-bit relocation as llvm/lib/MC/MCAsmStreamer.cpp checks
143  // no bits are set in the fixup range.
144  //
145  // name offset bits flags
146  {"FIXUP_LANAI_NONE", 0, 32, 0},
147  {"FIXUP_LANAI_21", 16, 16 /*21*/, 0},
148  {"FIXUP_LANAI_21_F", 16, 16 /*21*/, 0},
149  {"FIXUP_LANAI_25", 7, 25, 0},
150  {"FIXUP_LANAI_32", 0, 32, 0},
151  {"FIXUP_LANAI_HI16", 16, 16, 0},
152  {"FIXUP_LANAI_LO16", 16, 16, 0}};
153 
154  if (Kind < FirstTargetFixupKind)
155  return MCAsmBackend::getFixupKindInfo(Kind);
156 
157  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
158  "Invalid kind!");
159  return Infos[Kind - FirstTargetFixupKind];
160 }
161 
162 } // namespace
163 
165  const MCRegisterInfo & /*MRI*/,
166  const Triple &TT, StringRef /*CPU*/,
167  const MCTargetOptions & /*Options*/) {
168  if (!TT.isOSBinFormatELF())
169  llvm_unreachable("OS not supported");
170 
171  return new LanaiAsmBackend(T, TT.getOS());
172 }
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:279
size_t i
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:66
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
A four-byte fixup.
Definition: MCFixup.h:26
MCObjectWriter * createLanaiELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI)
uint32_t getOffset() const
Definition: MCFixup.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:249
void write32(uint32_t Value)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
MCAsmBackend * createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TheTriple, StringRef CPU, const MCTargetOptions &Options)
uint32_t Offset
MCFixupKind getKind() const
Definition: MCFixup.h:93
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:24
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
static unsigned adjustFixupValue(unsigned Kind, uint64_t Value)
Target - Wrapper for Target specific information.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
MCSubtargetInfo - Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:27
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:333
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
A two-byte fixup.
Definition: MCFixup.h:25