44 #define DEBUG_TYPE "x86-instr-info"
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
51 cl::desc(
"Disable fusing of spill code into instructions"));
54 cl::desc(
"Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
59 cl::desc(
"Re-materialize load from stub in PIC mode"),
63 cl::desc(
"Clearance between two register writes "
64 "for inserting XOR to avoid partial "
69 cl::desc(
"How many idle instructions we would like before "
70 "certain undef register reads"),
113 void X86InstrInfo::anchor() {}
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
121 (STI.
is64Bit() ? X86::RETQ : X86::RETL)),
122 Subtarget(STI), RI(STI.getTargetTriple()) {
125 { X86::ADC32ri, X86::ADC32mi, 0 },
126 { X86::ADC32ri8, X86::ADC32mi8, 0 },
127 { X86::ADC32rr, X86::ADC32mr, 0 },
128 { X86::ADC64ri32, X86::ADC64mi32, 0 },
129 { X86::ADC64ri8, X86::ADC64mi8, 0 },
130 { X86::ADC64rr, X86::ADC64mr, 0 },
131 { X86::ADD16ri, X86::ADD16mi, 0 },
132 { X86::ADD16ri8, X86::ADD16mi8, 0 },
135 { X86::ADD16rr, X86::ADD16mr, 0 },
137 { X86::ADD32ri, X86::ADD32mi, 0 },
138 { X86::ADD32ri8, X86::ADD32mi8, 0 },
141 { X86::ADD32rr, X86::ADD32mr, 0 },
143 { X86::ADD64ri32, X86::ADD64mi32, 0 },
144 { X86::ADD64ri8, X86::ADD64mi8, 0 },
147 { X86::ADD64rr, X86::ADD64mr, 0 },
149 { X86::ADD8ri, X86::ADD8mi, 0 },
150 { X86::ADD8rr, X86::ADD8mr, 0 },
151 { X86::AND16ri, X86::AND16mi, 0 },
152 { X86::AND16ri8, X86::AND16mi8, 0 },
153 { X86::AND16rr, X86::AND16mr, 0 },
154 { X86::AND32ri, X86::AND32mi, 0 },
155 { X86::AND32ri8, X86::AND32mi8, 0 },
156 { X86::AND32rr, X86::AND32mr, 0 },
157 { X86::AND64ri32, X86::AND64mi32, 0 },
158 { X86::AND64ri8, X86::AND64mi8, 0 },
159 { X86::AND64rr, X86::AND64mr, 0 },
160 { X86::AND8ri, X86::AND8mi, 0 },
161 { X86::AND8rr, X86::AND8mr, 0 },
162 { X86::DEC16r, X86::DEC16m, 0 },
163 { X86::DEC32r, X86::DEC32m, 0 },
164 { X86::DEC64r, X86::DEC64m, 0 },
165 { X86::DEC8r, X86::DEC8m, 0 },
166 { X86::INC16r, X86::INC16m, 0 },
167 { X86::INC32r, X86::INC32m, 0 },
168 { X86::INC64r, X86::INC64m, 0 },
169 { X86::INC8r, X86::INC8m, 0 },
170 { X86::NEG16r, X86::NEG16m, 0 },
171 { X86::NEG32r, X86::NEG32m, 0 },
172 { X86::NEG64r, X86::NEG64m, 0 },
173 { X86::NEG8r, X86::NEG8m, 0 },
174 { X86::NOT16r, X86::NOT16m, 0 },
175 { X86::NOT32r, X86::NOT32m, 0 },
176 { X86::NOT64r, X86::NOT64m, 0 },
177 { X86::NOT8r, X86::NOT8m, 0 },
178 { X86::OR16ri, X86::OR16mi, 0 },
179 { X86::OR16ri8, X86::OR16mi8, 0 },
180 { X86::OR16rr, X86::OR16mr, 0 },
181 { X86::OR32ri, X86::OR32mi, 0 },
182 { X86::OR32ri8, X86::OR32mi8, 0 },
183 { X86::OR32rr, X86::OR32mr, 0 },
184 { X86::OR64ri32, X86::OR64mi32, 0 },
185 { X86::OR64ri8, X86::OR64mi8, 0 },
186 { X86::OR64rr, X86::OR64mr, 0 },
187 { X86::OR8ri, X86::OR8mi, 0 },
188 { X86::OR8rr, X86::OR8mr, 0 },
189 { X86::ROL16r1, X86::ROL16m1, 0 },
190 { X86::ROL16rCL, X86::ROL16mCL, 0 },
191 { X86::ROL16ri, X86::ROL16mi, 0 },
192 { X86::ROL32r1, X86::ROL32m1, 0 },
193 { X86::ROL32rCL, X86::ROL32mCL, 0 },
194 { X86::ROL32ri, X86::ROL32mi, 0 },
195 { X86::ROL64r1, X86::ROL64m1, 0 },
196 { X86::ROL64rCL, X86::ROL64mCL, 0 },
197 { X86::ROL64ri, X86::ROL64mi, 0 },
198 { X86::ROL8r1, X86::ROL8m1, 0 },
199 { X86::ROL8rCL, X86::ROL8mCL, 0 },
200 { X86::ROL8ri, X86::ROL8mi, 0 },
201 { X86::ROR16r1, X86::ROR16m1, 0 },
202 { X86::ROR16rCL, X86::ROR16mCL, 0 },
203 { X86::ROR16ri, X86::ROR16mi, 0 },
204 { X86::ROR32r1, X86::ROR32m1, 0 },
205 { X86::ROR32rCL, X86::ROR32mCL, 0 },
206 { X86::ROR32ri, X86::ROR32mi, 0 },
207 { X86::ROR64r1, X86::ROR64m1, 0 },
208 { X86::ROR64rCL, X86::ROR64mCL, 0 },
209 { X86::ROR64ri, X86::ROR64mi, 0 },
210 { X86::ROR8r1, X86::ROR8m1, 0 },
211 { X86::ROR8rCL, X86::ROR8mCL, 0 },
212 { X86::ROR8ri, X86::ROR8mi, 0 },
213 { X86::SAR16r1, X86::SAR16m1, 0 },
214 { X86::SAR16rCL, X86::SAR16mCL, 0 },
215 { X86::SAR16ri, X86::SAR16mi, 0 },
216 { X86::SAR32r1, X86::SAR32m1, 0 },
217 { X86::SAR32rCL, X86::SAR32mCL, 0 },
218 { X86::SAR32ri, X86::SAR32mi, 0 },
219 { X86::SAR64r1, X86::SAR64m1, 0 },
220 { X86::SAR64rCL, X86::SAR64mCL, 0 },
221 { X86::SAR64ri, X86::SAR64mi, 0 },
222 { X86::SAR8r1, X86::SAR8m1, 0 },
223 { X86::SAR8rCL, X86::SAR8mCL, 0 },
224 { X86::SAR8ri, X86::SAR8mi, 0 },
225 { X86::SBB32ri, X86::SBB32mi, 0 },
226 { X86::SBB32ri8, X86::SBB32mi8, 0 },
227 { X86::SBB32rr, X86::SBB32mr, 0 },
228 { X86::SBB64ri32, X86::SBB64mi32, 0 },
229 { X86::SBB64ri8, X86::SBB64mi8, 0 },
230 { X86::SBB64rr, X86::SBB64mr, 0 },
231 { X86::SHL16r1, X86::SHL16m1, 0 },
232 { X86::SHL16rCL, X86::SHL16mCL, 0 },
233 { X86::SHL16ri, X86::SHL16mi, 0 },
234 { X86::SHL32r1, X86::SHL32m1, 0 },
235 { X86::SHL32rCL, X86::SHL32mCL, 0 },
236 { X86::SHL32ri, X86::SHL32mi, 0 },
237 { X86::SHL64r1, X86::SHL64m1, 0 },
238 { X86::SHL64rCL, X86::SHL64mCL, 0 },
239 { X86::SHL64ri, X86::SHL64mi, 0 },
240 { X86::SHL8r1, X86::SHL8m1, 0 },
241 { X86::SHL8rCL, X86::SHL8mCL, 0 },
242 { X86::SHL8ri, X86::SHL8mi, 0 },
243 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
244 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
245 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
246 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
247 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
248 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
249 { X86::SHR16r1, X86::SHR16m1, 0 },
250 { X86::SHR16rCL, X86::SHR16mCL, 0 },
251 { X86::SHR16ri, X86::SHR16mi, 0 },
252 { X86::SHR32r1, X86::SHR32m1, 0 },
253 { X86::SHR32rCL, X86::SHR32mCL, 0 },
254 { X86::SHR32ri, X86::SHR32mi, 0 },
255 { X86::SHR64r1, X86::SHR64m1, 0 },
256 { X86::SHR64rCL, X86::SHR64mCL, 0 },
257 { X86::SHR64ri, X86::SHR64mi, 0 },
258 { X86::SHR8r1, X86::SHR8m1, 0 },
259 { X86::SHR8rCL, X86::SHR8mCL, 0 },
260 { X86::SHR8ri, X86::SHR8mi, 0 },
261 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
262 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
263 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
264 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
265 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
266 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
267 { X86::SUB16ri, X86::SUB16mi, 0 },
268 { X86::SUB16ri8, X86::SUB16mi8, 0 },
269 { X86::SUB16rr, X86::SUB16mr, 0 },
270 { X86::SUB32ri, X86::SUB32mi, 0 },
271 { X86::SUB32ri8, X86::SUB32mi8, 0 },
272 { X86::SUB32rr, X86::SUB32mr, 0 },
273 { X86::SUB64ri32, X86::SUB64mi32, 0 },
274 { X86::SUB64ri8, X86::SUB64mi8, 0 },
275 { X86::SUB64rr, X86::SUB64mr, 0 },
276 { X86::SUB8ri, X86::SUB8mi, 0 },
277 { X86::SUB8rr, X86::SUB8mr, 0 },
278 { X86::XOR16ri, X86::XOR16mi, 0 },
279 { X86::XOR16ri8, X86::XOR16mi8, 0 },
280 { X86::XOR16rr, X86::XOR16mr, 0 },
281 { X86::XOR32ri, X86::XOR32mi, 0 },
282 { X86::XOR32ri8, X86::XOR32mi8, 0 },
283 { X86::XOR32rr, X86::XOR32mr, 0 },
284 { X86::XOR64ri32, X86::XOR64mi32, 0 },
285 { X86::XOR64ri8, X86::XOR64mi8, 0 },
286 { X86::XOR64rr, X86::XOR64mr, 0 },
287 { X86::XOR8ri, X86::XOR8mi, 0 },
288 { X86::XOR8rr, X86::XOR8mr, 0 }
292 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
293 Entry.RegOp, Entry.MemOp,
445 { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr,
TB_FOLDED_STORE },
446 { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr,
TB_FOLDED_STORE },
447 { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr,
TB_FOLDED_STORE },
448 { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr,
TB_FOLDED_STORE },
487 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
488 Entry.RegOp, Entry.MemOp,
TB_INDEX_0 | Entry.Flags);
492 { X86::BSF16rr, X86::BSF16rm, 0 },
493 { X86::BSF32rr, X86::BSF32rm, 0 },
494 { X86::BSF64rr, X86::BSF64rm, 0 },
495 { X86::BSR16rr, X86::BSR16rm, 0 },
496 { X86::BSR32rr, X86::BSR32rm, 0 },
497 { X86::BSR64rr, X86::BSR64rm, 0 },
498 { X86::CMP16rr, X86::CMP16rm, 0 },
499 { X86::CMP32rr, X86::CMP32rm, 0 },
500 { X86::CMP64rr, X86::CMP64rm, 0 },
501 { X86::CMP8rr, X86::CMP8rm, 0 },
502 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
503 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
504 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
505 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
506 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
507 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
508 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
509 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
510 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
511 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
512 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
513 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
514 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
515 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
516 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
517 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
530 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm,
TB_ALIGN_16 },
531 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm,
TB_ALIGN_16 },
532 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,
TB_NO_REVERSE },
533 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,
TB_NO_REVERSE },
534 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,
TB_NO_REVERSE },
535 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,
TB_NO_REVERSE },
538 { X86::MOV16rr, X86::MOV16rm, 0 },
539 { X86::MOV32rr, X86::MOV32rm, 0 },
540 { X86::MOV64rr, X86::MOV64rm, 0 },
541 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
542 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
543 { X86::MOV8rr, X86::MOV8rm, 0 },
547 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
548 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
550 { X86::MOVDQUrr, X86::MOVDQUrm, 0 },
553 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
554 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
555 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
556 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
557 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
558 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
559 { X86::MOVUPDrr, X86::MOVUPDrm, 0 },
560 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
562 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
563 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
564 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
565 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
569 { X86::PCMPESTRIrr, X86::PCMPESTRIrm,
TB_ALIGN_16 },
570 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm,
TB_ALIGN_16 },
571 { X86::PCMPISTRIrr, X86::PCMPISTRIrm,
TB_ALIGN_16 },
572 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm,
TB_ALIGN_16 },
573 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,
TB_ALIGN_16 },
591 { X86::RCPSSr, X86::RCPSSm, 0 },
595 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
596 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
598 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
602 { X86::SQRTSDr, X86::SQRTSDm, 0 },
604 { X86::SQRTSSr, X86::SQRTSSm, 0 },
606 { X86::TEST16rr, X86::TEST16rm, 0 },
607 { X86::TEST32rr, X86::TEST32rm, 0 },
608 { X86::TEST64rr, X86::TEST64rm, 0 },
609 { X86::TEST8rr, X86::TEST8rm, 0 },
611 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
612 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
615 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
616 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
617 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
618 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
619 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
620 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
621 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
622 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
623 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
624 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
627 { X86::PF2IDrr, X86::PF2IDrm, 0 },
628 { X86::PF2IWrr, X86::PF2IWrm, 0 },
629 { X86::PFRCPrr, X86::PFRCPrm, 0 },
630 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
631 { X86::PI2FDrr, X86::PI2FDrm, 0 },
632 { X86::PI2FWrr, X86::PI2FWrm, 0 },
633 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
640 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
641 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,
TB_NO_REVERSE },
642 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
643 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,
TB_NO_REVERSE },
644 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
645 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,
TB_NO_REVERSE },
646 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
647 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,
TB_NO_REVERSE },
653 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
654 { X86::VCVTPD2DQrr, X86::VCVTPD2DQrm, 0 },
655 { X86::VCVTPD2PSrr, X86::VCVTPD2PSrm, 0 },
656 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
658 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, 0 },
659 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
660 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
661 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
665 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
666 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
668 { X86::VMOVDQUrr, X86::VMOVDQUrm, 0 },
669 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
670 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
671 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
672 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
674 { X86::VPABSBrr, X86::VPABSBrm, 0 },
675 { X86::VPABSDrr, X86::VPABSDrm, 0 },
676 { X86::VPABSWrr, X86::VPABSWrm, 0 },
677 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
678 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
679 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
680 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
681 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
682 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
683 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
696 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
697 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
698 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
699 { X86::VPTESTrr, X86::VPTESTrm, 0 },
700 { X86::VRCPPSr, X86::VRCPPSm, 0 },
701 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
702 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
703 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
704 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
705 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
706 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
707 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
708 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
709 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
713 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
714 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
715 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
716 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
718 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
719 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
722 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
724 { X86::VMOVDQUYrr, X86::VMOVDQUYrm, 0 },
725 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
726 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
727 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
728 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
729 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
730 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
731 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
732 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
733 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
734 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
735 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
736 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
737 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
738 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
739 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
749 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,
TB_NO_REVERSE },
750 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,
TB_NO_REVERSE },
751 { X86::VPABSBYrr, X86::VPABSBYrm, 0 },
752 { X86::VPABSDYrr, X86::VPABSDYrm, 0 },
753 { X86::VPABSWYrr, X86::VPABSWYrm, 0 },
755 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,
TB_NO_REVERSE },
757 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,
TB_NO_REVERSE },
759 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,
TB_NO_REVERSE },
761 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,
TB_NO_REVERSE },
762 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
763 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
766 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
767 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
768 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
772 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
773 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
774 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
776 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
777 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
778 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
781 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
782 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
783 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
784 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
785 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
786 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
787 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
788 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
789 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
790 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
791 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
792 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
793 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
794 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
795 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
796 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
797 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
798 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
799 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
800 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
801 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
802 { X86::VPROTBri, X86::VPROTBmi, 0 },
803 { X86::VPROTBrr, X86::VPROTBmr, 0 },
804 { X86::VPROTDri, X86::VPROTDmi, 0 },
805 { X86::VPROTDrr, X86::VPROTDmr, 0 },
806 { X86::VPROTQri, X86::VPROTQmi, 0 },
807 { X86::VPROTQrr, X86::VPROTQmr, 0 },
808 { X86::VPROTWri, X86::VPROTWmi, 0 },
809 { X86::VPROTWrr, X86::VPROTWmr, 0 },
810 { X86::VPSHABrr, X86::VPSHABmr, 0 },
811 { X86::VPSHADrr, X86::VPSHADmr, 0 },
812 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
813 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
814 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
815 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
816 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
817 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
820 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
821 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
822 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
823 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
824 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
825 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
826 { X86::BLCI32rr, X86::BLCI32rm, 0 },
827 { X86::BLCI64rr, X86::BLCI64rm, 0 },
828 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
829 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
830 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
831 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
832 { X86::BLCS32rr, X86::BLCS32rm, 0 },
833 { X86::BLCS64rr, X86::BLCS64rm, 0 },
834 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
835 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
836 { X86::BLSI32rr, X86::BLSI32rm, 0 },
837 { X86::BLSI64rr, X86::BLSI64rm, 0 },
838 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
839 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
840 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
841 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
842 { X86::BLSR32rr, X86::BLSR32rm, 0 },
843 { X86::BLSR64rr, X86::BLSR64rm, 0 },
844 { X86::BZHI32rr, X86::BZHI32rm, 0 },
845 { X86::BZHI64rr, X86::BZHI64rm, 0 },
846 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
847 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
848 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
849 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
850 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
851 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
852 { X86::RORX32ri, X86::RORX32mi, 0 },
853 { X86::RORX64ri, X86::RORX64mi, 0 },
854 { X86::SARX32rr, X86::SARX32rm, 0 },
855 { X86::SARX64rr, X86::SARX64rm, 0 },
856 { X86::SHRX32rr, X86::SHRX32rm, 0 },
857 { X86::SHRX64rr, X86::SHRX64rm, 0 },
858 { X86::SHLX32rr, X86::SHLX32rm, 0 },
859 { X86::SHLX64rr, X86::SHLX64rm, 0 },
860 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
861 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
862 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
863 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
864 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
865 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
866 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
870 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm,
TB_NO_REVERSE },
872 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm,
TB_NO_REVERSE },
873 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
874 { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm,
TB_NO_REVERSE },
875 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
878 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm,
TB_ALIGN_64 },
879 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm,
TB_ALIGN_64 },
880 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
881 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
882 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
883 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
884 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
885 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
886 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
887 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
888 { X86::VPERMILPDZri, X86::VPERMILPDZmi, 0 },
889 { X86::VPERMILPSZri, X86::VPERMILPSZmi, 0 },
890 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
891 { X86::VPERMQZri, X86::VPERMQZmi, 0 },
892 { X86::VPMOVSXBDZrr, X86::VPMOVSXBDZrm, 0 },
894 { X86::VPMOVSXBWZrr, X86::VPMOVSXBWZrm, 0 },
895 { X86::VPMOVSXDQZrr, X86::VPMOVSXDQZrm, 0 },
896 { X86::VPMOVSXWDZrr, X86::VPMOVSXWDZrm, 0 },
897 { X86::VPMOVSXWQZrr, X86::VPMOVSXWQZrm, 0 },
898 { X86::VPMOVZXBDZrr, X86::VPMOVZXBDZrm, 0 },
900 { X86::VPMOVZXBWZrr, X86::VPMOVZXBWZrm, 0 },
901 { X86::VPMOVZXDQZrr, X86::VPMOVZXDQZrm, 0 },
902 { X86::VPMOVZXWDZrr, X86::VPMOVZXWDZrm, 0 },
903 { X86::VPMOVZXWQZrr, X86::VPMOVZXWQZrm, 0 },
904 { X86::VPSHUFDZri, X86::VPSHUFDZmi, 0 },
905 { X86::VPSHUFHWZri, X86::VPSHUFHWZmi, 0 },
906 { X86::VPSHUFLWZri, X86::VPSHUFLWZmi, 0 },
909 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m,
TB_NO_REVERSE },
910 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m,
TB_NO_REVERSE },
911 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m,
TB_NO_REVERSE },
912 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m,
TB_NO_REVERSE },
913 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm,
TB_ALIGN_32 },
914 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm,
TB_ALIGN_32 },
915 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm,
TB_ALIGN_32 },
916 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm,
TB_ALIGN_32 },
917 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
918 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
919 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
920 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
921 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
922 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
923 { X86::VPERMILPDZ256ri, X86::VPERMILPDZ256mi, 0 },
924 { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256mi, 0 },
925 { X86::VPERMPDZ256ri, X86::VPERMPDZ256mi, 0 },
926 { X86::VPERMQZ256ri, X86::VPERMQZ256mi, 0 },
927 { X86::VPMOVSXBDZ256rr, X86::VPMOVSXBDZ256rm,
TB_NO_REVERSE },
928 { X86::VPMOVSXBQZ256rr, X86::VPMOVSXBQZ256rm,
TB_NO_REVERSE },
929 { X86::VPMOVSXBWZ256rr, X86::VPMOVSXBWZ256rm, 0 },
930 { X86::VPMOVSXDQZ256rr, X86::VPMOVSXDQZ256rm, 0 },
931 { X86::VPMOVSXWDZ256rr, X86::VPMOVSXWDZ256rm, 0 },
932 { X86::VPMOVSXWQZ256rr, X86::VPMOVSXWQZ256rm,
TB_NO_REVERSE },
933 { X86::VPMOVZXBDZ256rr, X86::VPMOVZXBDZ256rm,
TB_NO_REVERSE },
934 { X86::VPMOVZXBQZ256rr, X86::VPMOVZXBQZ256rm,
TB_NO_REVERSE },
935 { X86::VPMOVZXBWZ256rr, X86::VPMOVZXBWZ256rm, 0 },
936 { X86::VPMOVZXDQZ256rr, X86::VPMOVZXDQZ256rm, 0 },
937 { X86::VPMOVZXWDZ256rr, X86::VPMOVZXWDZ256rm, 0 },
938 { X86::VPMOVZXWQZ256rr, X86::VPMOVZXWQZ256rm,
TB_NO_REVERSE },
939 { X86::VPSHUFDZ256ri, X86::VPSHUFDZ256mi, 0 },
940 { X86::VPSHUFHWZ256ri, X86::VPSHUFHWZ256mi, 0 },
941 { X86::VPSHUFLWZ256ri, X86::VPSHUFLWZ256mi, 0 },
944 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m,
TB_NO_REVERSE },
945 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m,
TB_NO_REVERSE },
946 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm,
TB_ALIGN_16 },
947 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm,
TB_ALIGN_16 },
948 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm,
TB_ALIGN_16 },
949 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm,
TB_ALIGN_16 },
950 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
951 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
952 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
953 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
954 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
955 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
956 { X86::VPERMILPDZ128ri, X86::VPERMILPDZ128mi, 0 },
957 { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128mi, 0 },
958 { X86::VPMOVSXBDZ128rr, X86::VPMOVSXBDZ128rm,
TB_NO_REVERSE },
959 { X86::VPMOVSXBQZ128rr, X86::VPMOVSXBQZ128rm,
TB_NO_REVERSE },
960 { X86::VPMOVSXBWZ128rr, X86::VPMOVSXBWZ128rm,
TB_NO_REVERSE },
961 { X86::VPMOVSXDQZ128rr, X86::VPMOVSXDQZ128rm,
TB_NO_REVERSE },
962 { X86::VPMOVSXWDZ128rr, X86::VPMOVSXWDZ128rm,
TB_NO_REVERSE },
963 { X86::VPMOVSXWQZ128rr, X86::VPMOVSXWQZ128rm,
TB_NO_REVERSE },
964 { X86::VPMOVZXBDZ128rr, X86::VPMOVZXBDZ128rm,
TB_NO_REVERSE },
965 { X86::VPMOVZXBQZ128rr, X86::VPMOVZXBQZ128rm,
TB_NO_REVERSE },
966 { X86::VPMOVZXBWZ128rr, X86::VPMOVZXBWZ128rm,
TB_NO_REVERSE },
967 { X86::VPMOVZXDQZ128rr, X86::VPMOVZXDQZ128rm,
TB_NO_REVERSE },
968 { X86::VPMOVZXWDZ128rr, X86::VPMOVZXWDZ128rm,
TB_NO_REVERSE },
969 { X86::VPMOVZXWQZ128rr, X86::VPMOVZXWQZ128rm,
TB_NO_REVERSE },
970 { X86::VPSHUFDZ128ri, X86::VPSHUFDZ128mi, 0 },
971 { X86::VPSHUFHWZ128ri, X86::VPSHUFHWZ128mi, 0 },
972 { X86::VPSHUFLWZ128ri, X86::VPSHUFLWZ128mi, 0 },
975 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
976 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
980 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm,
TB_ALIGN_16 },
981 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
982 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
986 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
987 Entry.RegOp, Entry.MemOp,
993 { X86::ADC32rr, X86::ADC32rm, 0 },
994 { X86::ADC64rr, X86::ADC64rm, 0 },
995 { X86::ADD16rr, X86::ADD16rm, 0 },
997 { X86::ADD32rr, X86::ADD32rm, 0 },
999 { X86::ADD64rr, X86::ADD64rm, 0 },
1001 { X86::ADD8rr, X86::ADD8rm, 0 },
1004 { X86::ADDSDrr, X86::ADDSDrm, 0 },
1006 { X86::ADDSSrr, X86::ADDSSrm, 0 },
1008 { X86::ADDSUBPDrr, X86::ADDSUBPDrm,
TB_ALIGN_16 },
1009 { X86::ADDSUBPSrr, X86::ADDSUBPSrm,
TB_ALIGN_16 },
1010 { X86::AND16rr, X86::AND16rm, 0 },
1011 { X86::AND32rr, X86::AND32rm, 0 },
1012 { X86::AND64rr, X86::AND64rm, 0 },
1013 { X86::AND8rr, X86::AND8rm, 0 },
1018 { X86::BLENDPDrri, X86::BLENDPDrmi,
TB_ALIGN_16 },
1019 { X86::BLENDPSrri, X86::BLENDPSrmi,
TB_ALIGN_16 },
1020 { X86::BLENDVPDrr0, X86::BLENDVPDrm0,
TB_ALIGN_16 },
1021 { X86::BLENDVPSrr0, X86::BLENDVPSrm0,
TB_ALIGN_16 },
1022 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
1023 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
1024 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
1025 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
1026 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
1027 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
1028 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
1029 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
1030 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
1031 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
1032 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
1033 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
1034 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
1035 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
1036 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
1037 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
1038 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
1039 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
1040 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
1041 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
1042 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
1043 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
1044 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
1045 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
1046 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
1047 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
1048 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
1049 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
1050 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
1051 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
1052 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
1053 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
1054 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
1055 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
1056 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
1057 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
1058 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
1059 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
1060 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
1061 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
1062 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
1063 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
1064 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
1065 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
1066 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
1067 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
1068 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
1069 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
1072 { X86::CMPSDrr, X86::CMPSDrm, 0 },
1073 { X86::CMPSSrr, X86::CMPSSrm, 0 },
1074 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
1075 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
1078 { X86::DIVSDrr, X86::DIVSDrm, 0 },
1080 { X86::DIVSSrr, X86::DIVSSrm, 0 },
1088 { X86::IMUL16rr, X86::IMUL16rm, 0 },
1089 { X86::IMUL32rr, X86::IMUL32rm, 0 },
1090 { X86::IMUL64rr, X86::IMUL64rm, 0 },
1093 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm,
TB_NO_REVERSE },
1094 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1095 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1096 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1097 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1098 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm,
TB_NO_REVERSE },
1103 { X86::MAXSDrr, X86::MAXSDrm, 0 },
1104 { X86::MAXCSDrr, X86::MAXCSDrm, 0 },
1106 { X86::MAXSSrr, X86::MAXSSrm, 0 },
1107 { X86::MAXCSSrr, X86::MAXCSSrm, 0 },
1113 { X86::MINSDrr, X86::MINSDrm, 0 },
1114 { X86::MINCSDrr, X86::MINCSDrm, 0 },
1116 { X86::MINSSrr, X86::MINSSrm, 0 },
1117 { X86::MINCSSrr, X86::MINCSSrm, 0 },
1120 { X86::MPSADBWrri, X86::MPSADBWrmi,
TB_ALIGN_16 },
1123 { X86::MULSDrr, X86::MULSDrm, 0 },
1125 { X86::MULSSrr, X86::MULSSrm, 0 },
1127 { X86::OR16rr, X86::OR16rm, 0 },
1128 { X86::OR32rr, X86::OR32rm, 0 },
1129 { X86::OR64rr, X86::OR64rm, 0 },
1130 { X86::OR8rr, X86::OR8rm, 0 },
1133 { X86::PACKSSDWrr, X86::PACKSSDWrm,
TB_ALIGN_16 },
1134 { X86::PACKSSWBrr, X86::PACKSSWBrm,
TB_ALIGN_16 },
1135 { X86::PACKUSDWrr, X86::PACKUSDWrm,
TB_ALIGN_16 },
1136 { X86::PACKUSWBrr, X86::PACKUSWBrm,
TB_ALIGN_16 },
1145 { X86::PALIGNRrri, X86::PALIGNRrmi,
TB_ALIGN_16 },
1150 { X86::PBLENDVBrr0, X86::PBLENDVBrm0,
TB_ALIGN_16 },
1151 { X86::PBLENDWrri, X86::PBLENDWrmi,
TB_ALIGN_16 },
1152 { X86::PCLMULQDQrr, X86::PCLMULQDQrm,
TB_ALIGN_16 },
1163 { X86::PHADDSWrr128, X86::PHADDSWrm128,
TB_ALIGN_16 },
1165 { X86::PHSUBSWrr128, X86::PHSUBSWrm128,
TB_ALIGN_16 },
1167 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1168 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1169 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1170 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
1171 { X86::PMADDUBSWrr, X86::PMADDUBSWrm,
TB_ALIGN_16 },
1186 { X86::PMULHRSWrr, X86::PMULHRSWrm,
TB_ALIGN_16 },
1195 { X86::PSIGNBrr128, X86::PSIGNBrm128,
TB_ALIGN_16 },
1196 { X86::PSIGNWrr128, X86::PSIGNWrm128,
TB_ALIGN_16 },
1197 { X86::PSIGNDrr128, X86::PSIGNDrm128,
TB_ALIGN_16 },
1214 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm,
TB_ALIGN_16 },
1215 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm,
TB_ALIGN_16 },
1216 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm,
TB_ALIGN_16 },
1217 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm,
TB_ALIGN_16 },
1218 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm,
TB_ALIGN_16 },
1219 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm,
TB_ALIGN_16 },
1220 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm,
TB_ALIGN_16 },
1221 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm,
TB_ALIGN_16 },
1225 { X86::SBB32rr, X86::SBB32rm, 0 },
1226 { X86::SBB64rr, X86::SBB64rm, 0 },
1229 { X86::SUB16rr, X86::SUB16rm, 0 },
1230 { X86::SUB32rr, X86::SUB32rm, 0 },
1231 { X86::SUB64rr, X86::SUB64rm, 0 },
1232 { X86::SUB8rr, X86::SUB8rm, 0 },
1235 { X86::SUBSDrr, X86::SUBSDrm, 0 },
1237 { X86::SUBSSrr, X86::SUBSSrm, 0 },
1240 { X86::UNPCKHPDrr, X86::UNPCKHPDrm,
TB_ALIGN_16 },
1241 { X86::UNPCKHPSrr, X86::UNPCKHPSrm,
TB_ALIGN_16 },
1242 { X86::UNPCKLPDrr, X86::UNPCKLPDrm,
TB_ALIGN_16 },
1243 { X86::UNPCKLPSrr, X86::UNPCKLPSrm,
TB_ALIGN_16 },
1244 { X86::XOR16rr, X86::XOR16rm, 0 },
1245 { X86::XOR32rr, X86::XOR32rm, 0 },
1246 { X86::XOR64rr, X86::XOR64rm, 0 },
1247 { X86::XOR8rr, X86::XOR8rm, 0 },
1252 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1253 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1254 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1255 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1256 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1257 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1258 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1259 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1260 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1261 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1262 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1263 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1264 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1265 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1266 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1267 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1268 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1269 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1270 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1271 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1272 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1273 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1274 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1275 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1276 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1277 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1278 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1279 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1280 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1281 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1282 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1283 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1284 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1285 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1286 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1287 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1288 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1289 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1290 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1291 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1292 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1293 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1294 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1295 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1296 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1297 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1298 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1299 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1300 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1301 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1302 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1303 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1304 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1305 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1306 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1307 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1308 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1309 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1310 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1311 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1312 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1313 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1314 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1315 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1316 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1317 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1318 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1319 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1320 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1321 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1324 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1325 { X86::PFACCrr, X86::PFACCrm, 0 },
1326 { X86::PFADDrr, X86::PFADDrm, 0 },
1327 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1328 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1329 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1330 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1331 { X86::PFMINrr, X86::PFMINrm, 0 },
1332 { X86::PFMULrr, X86::PFMULrm, 0 },
1333 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1334 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1335 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1336 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1337 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1338 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1339 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1340 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1343 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1344 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm,
TB_NO_REVERSE },
1345 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1346 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1347 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1348 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1349 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1350 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1351 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1352 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
1353 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1354 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm,
TB_NO_REVERSE },
1355 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1356 { X86::VADDPSrr, X86::VADDPSrm, 0 },
1357 { X86::VADDSDrr, X86::VADDSDrm, 0 },
1359 { X86::VADDSSrr, X86::VADDSSrm, 0 },
1361 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1362 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1363 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1364 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1365 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1366 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1367 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1368 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1369 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1370 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1371 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1372 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
1373 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1374 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
1375 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1376 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
1377 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
1379 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
1381 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1382 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
1383 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1384 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1385 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1386 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
1389 { X86::VMAXCPDrr, X86::VMAXCPDrm, 0 },
1390 { X86::VMAXCPSrr, X86::VMAXCPSrm, 0 },
1391 { X86::VMAXCSDrr, X86::VMAXCSDrm, 0 },
1392 { X86::VMAXCSSrr, X86::VMAXCSSrm, 0 },
1393 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
1394 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
1395 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
1397 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
1399 { X86::VMINCPDrr, X86::VMINCPDrm, 0 },
1400 { X86::VMINCPSrr, X86::VMINCPSrm, 0 },
1401 { X86::VMINCSDrr, X86::VMINCSDrm, 0 },
1402 { X86::VMINCSSrr, X86::VMINCSSrm, 0 },
1403 { X86::VMINPDrr, X86::VMINPDrm, 0 },
1404 { X86::VMINPSrr, X86::VMINPSrm, 0 },
1405 { X86::VMINSDrr, X86::VMINSDrm, 0 },
1407 { X86::VMINSSrr, X86::VMINSSrm, 0 },
1410 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1411 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1412 { X86::VMULPSrr, X86::VMULPSrm, 0 },
1413 { X86::VMULSDrr, X86::VMULSDrm, 0 },
1415 { X86::VMULSSrr, X86::VMULSSrm, 0 },
1417 { X86::VORPDrr, X86::VORPDrm, 0 },
1418 { X86::VORPSrr, X86::VORPSrm, 0 },
1419 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1420 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1421 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1422 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1423 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1424 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1425 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1426 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1427 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1428 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1429 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1430 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1431 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
1432 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1433 { X86::VPANDrr, X86::VPANDrm, 0 },
1434 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1435 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
1436 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
1437 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
1438 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
1439 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1440 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1441 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1442 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1443 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1444 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1445 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1446 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1447 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1448 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1449 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1450 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1451 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1452 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1453 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1454 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
1455 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1456 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1457 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
1458 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1459 { X86::VPMADDUBSWrr, X86::VPMADDUBSWrm, 0 },
1460 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1461 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1462 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1463 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1464 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1465 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1466 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1467 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1468 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1469 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1470 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1471 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1472 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1473 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1474 { X86::VPMULHRSWrr, X86::VPMULHRSWrm, 0 },
1475 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1476 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1477 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1478 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1479 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1480 { X86::VPORrr, X86::VPORrm, 0 },
1481 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1482 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1483 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1484 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1485 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
1486 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1487 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1488 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1489 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1490 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1491 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1492 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1493 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1494 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1495 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
1496 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
1497 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1498 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
1499 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1500 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
1501 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1502 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1503 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1504 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1505 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1506 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1507 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1508 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1509 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1510 { X86::VPXORrr, X86::VPXORrm, 0 },
1511 { X86::VRCPSSr, X86::VRCPSSm, 0 },
1513 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
1515 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1517 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
1519 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1520 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1521 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
1523 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
1525 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1526 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
1527 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
1529 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
1531 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1532 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1533 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1534 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1535 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1536 { X86::VXORPSrr, X86::VXORPSrm, 0 },
1539 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1540 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1541 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1542 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1543 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1544 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1545 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1546 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1547 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1548 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1549 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1550 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1551 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1552 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1553 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1554 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
1555 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
1556 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1557 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1558 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1559 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1560 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1561 { X86::VMAXCPDYrr, X86::VMAXCPDYrm, 0 },
1562 { X86::VMAXCPSYrr, X86::VMAXCPSYrm, 0 },
1563 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
1564 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
1565 { X86::VMINCPDYrr, X86::VMINCPDYrm, 0 },
1566 { X86::VMINCPSYrr, X86::VMINCPSYrm, 0 },
1567 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
1568 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
1569 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1570 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1571 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1572 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1573 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1574 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1575 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1576 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1577 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1578 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1579 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1580 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1581 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1582 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1583 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1584 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1585 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
1588 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1589 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1590 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1591 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1592 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1593 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1594 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1595 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1596 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1597 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1598 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1599 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1600 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1601 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
1602 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1603 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1604 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1605 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1606 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1607 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
1608 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
1609 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1610 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1611 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1612 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1613 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1614 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1615 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1616 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1617 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1618 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1619 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
1620 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
1621 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1622 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1623 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1624 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1625 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1626 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1627 { X86::VPMADDUBSWYrr, X86::VPMADDUBSWYrm, 0 },
1628 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1629 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1630 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1631 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1632 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1633 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1634 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1635 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1636 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1637 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1638 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1639 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1640 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1641 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1642 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1643 { X86::VPMULHRSWYrr, X86::VPMULHRSWYrm, 0 },
1644 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1645 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1646 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1647 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1648 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1649 { X86::VPORYrr, X86::VPORYrm, 0 },
1650 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1651 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1652 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1653 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1654 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
1655 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1656 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1657 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1658 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1659 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1660 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1661 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1662 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1663 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1664 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1665 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1666 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1667 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1668 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1669 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1670 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1671 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1672 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1673 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1674 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
1675 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
1676 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1677 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
1678 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1679 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
1680 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1681 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1682 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1683 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1684 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1685 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1686 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1687 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1688 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1689 { X86::VPXORYrr, X86::VPXORYrm, 0 },
1693 { X86::VFMADDSS4rr_Int, X86::VFMADDSS4mr_Int,
TB_NO_REVERSE },
1695 { X86::VFMADDSD4rr_Int, X86::VFMADDSD4mr_Int,
TB_NO_REVERSE },
1701 { X86::VFNMADDSS4rr_Int, X86::VFNMADDSS4mr_Int,
TB_NO_REVERSE },
1703 { X86::VFNMADDSD4rr_Int, X86::VFNMADDSD4mr_Int,
TB_NO_REVERSE },
1709 { X86::VFMSUBSS4rr_Int, X86::VFMSUBSS4mr_Int,
TB_NO_REVERSE },
1711 { X86::VFMSUBSD4rr_Int, X86::VFMSUBSD4mr_Int,
TB_NO_REVERSE },
1717 { X86::VFNMSUBSS4rr_Int, X86::VFNMSUBSS4mr_Int,
TB_NO_REVERSE },
1719 { X86::VFNMSUBSD4rr_Int, X86::VFNMSUBSD4mr_Int,
TB_NO_REVERSE },
1724 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr,
TB_ALIGN_NONE },
1725 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr,
TB_ALIGN_NONE },
1726 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Ymr,
TB_ALIGN_NONE },
1727 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Ymr,
TB_ALIGN_NONE },
1728 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr,
TB_ALIGN_NONE },
1729 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr,
TB_ALIGN_NONE },
1730 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Ymr,
TB_ALIGN_NONE },
1731 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Ymr,
TB_ALIGN_NONE },
1734 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1735 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
1736 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1737 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1738 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1739 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1740 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1741 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1742 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1743 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1744 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1745 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1746 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1747 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1748 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1749 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1750 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1751 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1752 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1753 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1754 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1755 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1756 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1757 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1758 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1759 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1760 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
1761 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1762 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1763 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1764 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1765 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1766 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1767 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1768 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1769 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1770 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1771 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1772 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1775 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1776 { X86::ANDN64rr, X86::ANDN64rm, 0 },
1777 { X86::MULX32rr, X86::MULX32rm, 0 },
1778 { X86::MULX64rr, X86::MULX64rm, 0 },
1779 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1780 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1781 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1782 { X86::PEXT64rr, X86::PEXT64rm, 0 },
1785 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1786 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1787 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1788 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1791 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1792 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1793 { X86::VADDSDZrr, X86::VADDSDZrm, 0 },
1795 { X86::VADDSSZrr, X86::VADDSSZrm, 0 },
1797 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
1798 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1799 { X86::VANDNPDZrr, X86::VANDNPDZrm, 0 },
1800 { X86::VANDNPSZrr, X86::VANDNPSZrm, 0 },
1801 { X86::VANDPDZrr, X86::VANDPDZrm, 0 },
1802 { X86::VANDPSZrr, X86::VANDPSZrm, 0 },
1803 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz,
TB_NO_REVERSE },
1804 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz,
TB_NO_REVERSE },
1805 { X86::VCMPPDZrri, X86::VCMPPDZrmi, 0 },
1806 { X86::VCMPPSZrri, X86::VCMPPSZrmi, 0 },
1807 { X86::VCMPSDZrr, X86::VCMPSDZrm, 0 },
1809 { X86::VCMPSSZrr, X86::VCMPSSZrm, 0 },
1811 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1812 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1813 { X86::VDIVSDZrr, X86::VDIVSDZrm, 0 },
1815 { X86::VDIVSSZrr, X86::VDIVSSZrm, 0 },
1817 { X86::VINSERTF32x4Zrr, X86::VINSERTF32x4Zrm, 0 },
1818 { X86::VINSERTF32x8Zrr, X86::VINSERTF32x8Zrm, 0 },
1819 { X86::VINSERTF64x2Zrr, X86::VINSERTF64x2Zrm, 0 },
1820 { X86::VINSERTF64x4Zrr, X86::VINSERTF64x4Zrm, 0 },
1821 { X86::VINSERTI32x4Zrr, X86::VINSERTI32x4Zrm, 0 },
1822 { X86::VINSERTI32x8Zrr, X86::VINSERTI32x8Zrm, 0 },
1823 { X86::VINSERTI64x2Zrr, X86::VINSERTI64x2Zrm, 0 },
1824 { X86::VINSERTI64x4Zrr, X86::VINSERTI64x4Zrm, 0 },
1825 { X86::VMAXCPDZrr, X86::VMAXCPDZrm, 0 },
1826 { X86::VMAXCPSZrr, X86::VMAXCPSZrm, 0 },
1827 { X86::VMAXCSDZrr, X86::VMAXCSDZrm, 0 },
1828 { X86::VMAXCSSZrr, X86::VMAXCSSZrm, 0 },
1829 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
1830 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1831 { X86::VMAXSDZrr, X86::VMAXSDZrm, 0 },
1833 { X86::VMAXSSZrr, X86::VMAXSSZrm, 0 },
1835 { X86::VMINCPDZrr, X86::VMINCPDZrm, 0 },
1836 { X86::VMINCPSZrr, X86::VMINCPSZrm, 0 },
1837 { X86::VMINCSDZrr, X86::VMINCSDZrm, 0 },
1838 { X86::VMINCSSZrr, X86::VMINCSSZrm, 0 },
1839 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1840 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1841 { X86::VMINSDZrr, X86::VMINSDZrm, 0 },
1843 { X86::VMINSSZrr, X86::VMINSSZrm, 0 },
1845 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1846 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1847 { X86::VMULSDZrr, X86::VMULSDZrm, 0 },
1849 { X86::VMULSSZrr, X86::VMULSSZrm, 0 },
1851 { X86::VORPDZrr, X86::VORPDZrm, 0 },
1852 { X86::VORPSZrr, X86::VORPSZrm, 0 },
1853 { X86::VPADDBZrr, X86::VPADDBZrm, 0 },
1854 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1855 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
1856 { X86::VPADDSBZrr, X86::VPADDSBZrm, 0 },
1857 { X86::VPADDSWZrr, X86::VPADDSWZrm, 0 },
1858 { X86::VPADDUSBZrr, X86::VPADDUSBZrm, 0 },
1859 { X86::VPADDUSWZrr, X86::VPADDUSWZrm, 0 },
1860 { X86::VPADDWZrr, X86::VPADDWZrm, 0 },
1861 { X86::VPALIGNRZrri, X86::VPALIGNRZrmi, 0 },
1862 { X86::VPANDDZrr, X86::VPANDDZrm, 0 },
1863 { X86::VPANDNDZrr, X86::VPANDNDZrm, 0 },
1864 { X86::VPANDNQZrr, X86::VPANDNQZrm, 0 },
1865 { X86::VPANDQZrr, X86::VPANDQZrm, 0 },
1866 { X86::VPCMPBZrri, X86::VPCMPBZrmi, 0 },
1867 { X86::VPCMPDZrri, X86::VPCMPDZrmi, 0 },
1868 { X86::VPCMPEQBZrr, X86::VPCMPEQBZrm, 0 },
1869 { X86::VPCMPEQDZrr, X86::VPCMPEQDZrm, 0 },
1870 { X86::VPCMPEQQZrr, X86::VPCMPEQQZrm, 0 },
1871 { X86::VPCMPEQWZrr, X86::VPCMPEQWZrm, 0 },
1872 { X86::VPCMPGTBZrr, X86::VPCMPGTBZrm, 0 },
1873 { X86::VPCMPGTDZrr, X86::VPCMPGTDZrm, 0 },
1874 { X86::VPCMPGTQZrr, X86::VPCMPGTQZrm, 0 },
1875 { X86::VPCMPGTWZrr, X86::VPCMPGTWZrm, 0 },
1876 { X86::VPCMPQZrri, X86::VPCMPQZrmi, 0 },
1877 { X86::VPCMPUBZrri, X86::VPCMPUBZrmi, 0 },
1878 { X86::VPCMPUDZrri, X86::VPCMPUDZrmi, 0 },
1879 { X86::VPCMPUQZrri, X86::VPCMPUQZrmi, 0 },
1880 { X86::VPCMPUWZrri, X86::VPCMPUWZrmi, 0 },
1881 { X86::VPCMPWZrri, X86::VPCMPWZrmi, 0 },
1882 { X86::VPERMBZrr, X86::VPERMBZrm, 0 },
1883 { X86::VPERMDZrr, X86::VPERMDZrm, 0 },
1884 { X86::VPERMILPDZrr, X86::VPERMILPDZrm, 0 },
1885 { X86::VPERMILPSZrr, X86::VPERMILPSZrm, 0 },
1886 { X86::VPERMPDZrr, X86::VPERMPDZrm, 0 },
1887 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
1888 { X86::VPERMQZrr, X86::VPERMQZrm, 0 },
1889 { X86::VPERMWZrr, X86::VPERMWZrm, 0 },
1890 { X86::VPMADDUBSWZrr, X86::VPMADDUBSWZrm, 0 },
1891 { X86::VPMADDWDZrr, X86::VPMADDWDZrm, 0 },
1892 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1893 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1894 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1895 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1896 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1897 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1898 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1899 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1900 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
1901 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
1902 { X86::VPORDZrr, X86::VPORDZrm, 0 },
1903 { X86::VPORQZrr, X86::VPORQZrm, 0 },
1904 { X86::VPSHUFBZrr, X86::VPSHUFBZrm, 0 },
1905 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1906 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1907 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1908 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1909 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
1910 { X86::VPSUBBZrr, X86::VPSUBBZrm, 0 },
1911 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1912 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
1913 { X86::VPSUBSBZrr, X86::VPSUBSBZrm, 0 },
1914 { X86::VPSUBSWZrr, X86::VPSUBSWZrm, 0 },
1915 { X86::VPSUBUSBZrr, X86::VPSUBUSBZrm, 0 },
1916 { X86::VPSUBUSWZrr, X86::VPSUBUSWZrm, 0 },
1917 { X86::VPSUBWZrr, X86::VPSUBWZrm, 0 },
1918 { X86::VPUNPCKHBWZrr, X86::VPUNPCKHBWZrm, 0 },
1919 { X86::VPUNPCKHDQZrr, X86::VPUNPCKHDQZrm, 0 },
1920 { X86::VPUNPCKHQDQZrr, X86::VPUNPCKHQDQZrm, 0 },
1921 { X86::VPUNPCKHWDZrr, X86::VPUNPCKHWDZrm, 0 },
1922 { X86::VPUNPCKLBWZrr, X86::VPUNPCKLBWZrm, 0 },
1923 { X86::VPUNPCKLDQZrr, X86::VPUNPCKLDQZrm, 0 },
1924 { X86::VPUNPCKLQDQZrr, X86::VPUNPCKLQDQZrm, 0 },
1925 { X86::VPUNPCKLWDZrr, X86::VPUNPCKLWDZrm, 0 },
1926 { X86::VPXORDZrr, X86::VPXORDZrm, 0 },
1927 { X86::VPXORQZrr, X86::VPXORQZrm, 0 },
1928 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1929 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
1930 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1931 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1932 { X86::VSUBSDZrr, X86::VSUBSDZrm, 0 },
1934 { X86::VSUBSSZrr, X86::VSUBSSZrm, 0 },
1936 { X86::VUNPCKHPDZrr, X86::VUNPCKHPDZrm, 0 },
1937 { X86::VUNPCKHPSZrr, X86::VUNPCKHPSZrm, 0 },
1938 { X86::VUNPCKLPDZrr, X86::VUNPCKLPDZrm, 0 },
1939 { X86::VUNPCKLPSZrr, X86::VUNPCKLPSZrm, 0 },
1940 { X86::VXORPDZrr, X86::VXORPDZrm, 0 },
1941 { X86::VXORPSZrr, X86::VXORPSZrm, 0 },
1944 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1945 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1946 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1947 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1948 { X86::VALIGNDZ128rri, X86::VALIGNDZ128rmi, 0 },
1949 { X86::VALIGNDZ256rri, X86::VALIGNDZ256rmi, 0 },
1950 { X86::VALIGNQZ128rri, X86::VALIGNQZ128rmi, 0 },
1951 { X86::VALIGNQZ256rri, X86::VALIGNQZ256rmi, 0 },
1952 { X86::VANDNPDZ128rr, X86::VANDNPDZ128rm, 0 },
1953 { X86::VANDNPDZ256rr, X86::VANDNPDZ256rm, 0 },
1954 { X86::VANDNPSZ128rr, X86::VANDNPSZ128rm, 0 },
1955 { X86::VANDNPSZ256rr, X86::VANDNPSZ256rm, 0 },
1956 { X86::VANDPDZ128rr, X86::VANDPDZ128rm, 0 },
1957 { X86::VANDPDZ256rr, X86::VANDPDZ256rm, 0 },
1958 { X86::VANDPSZ128rr, X86::VANDPSZ128rm, 0 },
1959 { X86::VANDPSZ256rr, X86::VANDPSZ256rm, 0 },
1960 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz,
TB_NO_REVERSE },
1961 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz,
TB_NO_REVERSE },
1962 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz,
TB_NO_REVERSE },
1963 { X86::VCMPPDZ128rri, X86::VCMPPDZ128rmi, 0 },
1964 { X86::VCMPPDZ256rri, X86::VCMPPDZ256rmi, 0 },
1965 { X86::VCMPPSZ128rri, X86::VCMPPSZ128rmi, 0 },
1966 { X86::VCMPPSZ256rri, X86::VCMPPSZ256rmi, 0 },
1967 { X86::VDIVPDZ128rr, X86::VDIVPDZ128rm, 0 },
1968 { X86::VDIVPDZ256rr, X86::VDIVPDZ256rm, 0 },
1969 { X86::VDIVPSZ128rr, X86::VDIVPSZ128rm, 0 },
1970 { X86::VDIVPSZ256rr, X86::VDIVPSZ256rm, 0 },
1971 { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm, 0 },
1972 { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm, 0 },
1973 { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm, 0 },
1974 { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm, 0 },
1975 { X86::VMAXCPDZ128rr, X86::VMAXCPDZ128rm, 0 },
1976 { X86::VMAXCPDZ256rr, X86::VMAXCPDZ256rm, 0 },
1977 { X86::VMAXCPSZ128rr, X86::VMAXCPSZ128rm, 0 },
1978 { X86::VMAXCPSZ256rr, X86::VMAXCPSZ256rm, 0 },
1979 { X86::VMAXPDZ128rr, X86::VMAXPDZ128rm, 0 },
1980 { X86::VMAXPDZ256rr, X86::VMAXPDZ256rm, 0 },
1981 { X86::VMAXPSZ128rr, X86::VMAXPSZ128rm, 0 },
1982 { X86::VMAXPSZ256rr, X86::VMAXPSZ256rm, 0 },
1983 { X86::VMINCPDZ128rr, X86::VMINCPDZ128rm, 0 },
1984 { X86::VMINCPDZ256rr, X86::VMINCPDZ256rm, 0 },
1985 { X86::VMINCPSZ128rr, X86::VMINCPSZ128rm, 0 },
1986 { X86::VMINCPSZ256rr, X86::VMINCPSZ256rm, 0 },
1987 { X86::VMINPDZ128rr, X86::VMINPDZ128rm, 0 },
1988 { X86::VMINPDZ256rr, X86::VMINPDZ256rm, 0 },
1989 { X86::VMINPSZ128rr, X86::VMINPSZ128rm, 0 },
1990 { X86::VMINPSZ256rr, X86::VMINPSZ256rm, 0 },
1991 { X86::VMULPDZ128rr, X86::VMULPDZ128rm, 0 },
1992 { X86::VMULPDZ256rr, X86::VMULPDZ256rm, 0 },
1993 { X86::VMULPSZ128rr, X86::VMULPSZ128rm, 0 },
1994 { X86::VMULPSZ256rr, X86::VMULPSZ256rm, 0 },
1995 { X86::VORPDZ128rr, X86::VORPDZ128rm, 0 },
1996 { X86::VORPDZ256rr, X86::VORPDZ256rm, 0 },
1997 { X86::VORPSZ128rr, X86::VORPSZ128rm, 0 },
1998 { X86::VORPSZ256rr, X86::VORPSZ256rm, 0 },
1999 { X86::VPADDBZ128rr, X86::VPADDBZ128rm, 0 },
2000 { X86::VPADDBZ256rr, X86::VPADDBZ256rm, 0 },
2001 { X86::VPADDDZ128rr, X86::VPADDDZ128rm, 0 },
2002 { X86::VPADDDZ256rr, X86::VPADDDZ256rm, 0 },
2003 { X86::VPADDQZ128rr, X86::VPADDQZ128rm, 0 },
2004 { X86::VPADDQZ256rr, X86::VPADDQZ256rm, 0 },
2005 { X86::VPADDSBZ128rr, X86::VPADDSBZ128rm, 0 },
2006 { X86::VPADDSBZ256rr, X86::VPADDSBZ256rm, 0 },
2007 { X86::VPADDSWZ128rr, X86::VPADDSWZ128rm, 0 },
2008 { X86::VPADDSWZ256rr, X86::VPADDSWZ256rm, 0 },
2009 { X86::VPADDUSBZ128rr, X86::VPADDUSBZ128rm, 0 },
2010 { X86::VPADDUSBZ256rr, X86::VPADDUSBZ256rm, 0 },
2011 { X86::VPADDUSWZ128rr, X86::VPADDUSWZ128rm, 0 },
2012 { X86::VPADDUSWZ256rr, X86::VPADDUSWZ256rm, 0 },
2013 { X86::VPADDWZ128rr, X86::VPADDWZ128rm, 0 },
2014 { X86::VPADDWZ256rr, X86::VPADDWZ256rm, 0 },
2015 { X86::VPALIGNRZ128rri, X86::VPALIGNRZ128rmi, 0 },
2016 { X86::VPALIGNRZ256rri, X86::VPALIGNRZ256rmi, 0 },
2017 { X86::VPANDDZ128rr, X86::VPANDDZ128rm, 0 },
2018 { X86::VPANDDZ256rr, X86::VPANDDZ256rm, 0 },
2019 { X86::VPANDNDZ128rr, X86::VPANDNDZ128rm, 0 },
2020 { X86::VPANDNDZ256rr, X86::VPANDNDZ256rm, 0 },
2021 { X86::VPANDNQZ128rr, X86::VPANDNQZ128rm, 0 },
2022 { X86::VPANDNQZ256rr, X86::VPANDNQZ256rm, 0 },
2023 { X86::VPANDQZ128rr, X86::VPANDQZ128rm, 0 },
2024 { X86::VPANDQZ256rr, X86::VPANDQZ256rm, 0 },
2025 { X86::VPCMPBZ128rri, X86::VPCMPBZ128rmi, 0 },
2026 { X86::VPCMPBZ256rri, X86::VPCMPBZ256rmi, 0 },
2027 { X86::VPCMPDZ128rri, X86::VPCMPDZ128rmi, 0 },
2028 { X86::VPCMPDZ256rri, X86::VPCMPDZ256rmi, 0 },
2029 { X86::VPCMPEQBZ128rr, X86::VPCMPEQBZ128rm, 0 },
2030 { X86::VPCMPEQBZ256rr, X86::VPCMPEQBZ256rm, 0 },
2031 { X86::VPCMPEQDZ128rr, X86::VPCMPEQDZ128rm, 0 },
2032 { X86::VPCMPEQDZ256rr, X86::VPCMPEQDZ256rm, 0 },
2033 { X86::VPCMPEQQZ128rr, X86::VPCMPEQQZ128rm, 0 },
2034 { X86::VPCMPEQQZ256rr, X86::VPCMPEQQZ256rm, 0 },
2035 { X86::VPCMPEQWZ128rr, X86::VPCMPEQWZ128rm, 0 },
2036 { X86::VPCMPEQWZ256rr, X86::VPCMPEQWZ256rm, 0 },
2037 { X86::VPCMPGTBZ128rr, X86::VPCMPGTBZ128rm, 0 },
2038 { X86::VPCMPGTBZ256rr, X86::VPCMPGTBZ256rm, 0 },
2039 { X86::VPCMPGTDZ128rr, X86::VPCMPGTDZ128rm, 0 },
2040 { X86::VPCMPGTDZ256rr, X86::VPCMPGTDZ256rm, 0 },
2041 { X86::VPCMPGTQZ128rr, X86::VPCMPGTQZ128rm, 0 },
2042 { X86::VPCMPGTQZ256rr, X86::VPCMPGTQZ256rm, 0 },
2043 { X86::VPCMPGTWZ128rr, X86::VPCMPGTWZ128rm, 0 },
2044 { X86::VPCMPGTWZ256rr, X86::VPCMPGTWZ256rm, 0 },
2045 { X86::VPCMPQZ128rri, X86::VPCMPQZ128rmi, 0 },
2046 { X86::VPCMPQZ256rri, X86::VPCMPQZ256rmi, 0 },
2047 { X86::VPCMPUBZ128rri, X86::VPCMPUBZ128rmi, 0 },
2048 { X86::VPCMPUBZ256rri, X86::VPCMPUBZ256rmi, 0 },
2049 { X86::VPCMPUDZ128rri, X86::VPCMPUDZ128rmi, 0 },
2050 { X86::VPCMPUDZ256rri, X86::VPCMPUDZ256rmi, 0 },
2051 { X86::VPCMPUQZ128rri, X86::VPCMPUQZ128rmi, 0 },
2052 { X86::VPCMPUQZ256rri, X86::VPCMPUQZ256rmi, 0 },
2053 { X86::VPCMPUWZ128rri, X86::VPCMPUWZ128rmi, 0 },
2054 { X86::VPCMPUWZ256rri, X86::VPCMPUWZ256rmi, 0 },
2055 { X86::VPCMPWZ128rri, X86::VPCMPWZ128rmi, 0 },
2056 { X86::VPCMPWZ256rri, X86::VPCMPWZ256rmi, 0 },
2057 { X86::VPERMBZ128rr, X86::VPERMBZ128rm, 0 },
2058 { X86::VPERMBZ256rr, X86::VPERMBZ256rm, 0 },
2059 { X86::VPERMDZ256rr, X86::VPERMDZ256rm, 0 },
2060 { X86::VPERMILPDZ128rr, X86::VPERMILPDZ128rm, 0 },
2061 { X86::VPERMILPDZ256rr, X86::VPERMILPDZ256rm, 0 },
2062 { X86::VPERMILPSZ128rr, X86::VPERMILPSZ128rm, 0 },
2063 { X86::VPERMILPSZ256rr, X86::VPERMILPSZ256rm, 0 },
2064 { X86::VPERMPDZ256rr, X86::VPERMPDZ256rm, 0 },
2065 { X86::VPERMPSZ256rr, X86::VPERMPSZ256rm, 0 },
2066 { X86::VPERMQZ256rr, X86::VPERMQZ256rm, 0 },
2067 { X86::VPERMWZ128rr, X86::VPERMWZ128rm, 0 },
2068 { X86::VPERMWZ256rr, X86::VPERMWZ256rm, 0 },
2069 { X86::VPMADDUBSWZ128rr, X86::VPMADDUBSWZ128rm, 0 },
2070 { X86::VPMADDUBSWZ256rr, X86::VPMADDUBSWZ256rm, 0 },
2071 { X86::VPMADDWDZ128rr, X86::VPMADDWDZ128rm, 0 },
2072 { X86::VPMADDWDZ256rr, X86::VPMADDWDZ256rm, 0 },
2073 { X86::VPORDZ128rr, X86::VPORDZ128rm, 0 },
2074 { X86::VPORDZ256rr, X86::VPORDZ256rm, 0 },
2075 { X86::VPORQZ128rr, X86::VPORQZ128rm, 0 },
2076 { X86::VPORQZ256rr, X86::VPORQZ256rm, 0 },
2077 { X86::VPSHUFBZ128rr, X86::VPSHUFBZ128rm, 0 },
2078 { X86::VPSHUFBZ256rr, X86::VPSHUFBZ256rm, 0 },
2079 { X86::VPSUBBZ128rr, X86::VPSUBBZ128rm, 0 },
2080 { X86::VPSUBBZ256rr, X86::VPSUBBZ256rm, 0 },
2081 { X86::VPSUBDZ128rr, X86::VPSUBDZ128rm, 0 },
2082 { X86::VPSUBDZ256rr, X86::VPSUBDZ256rm, 0 },
2083 { X86::VPSUBQZ128rr, X86::VPSUBQZ128rm, 0 },
2084 { X86::VPSUBQZ256rr, X86::VPSUBQZ256rm, 0 },
2085 { X86::VPSUBSBZ128rr, X86::VPSUBSBZ128rm, 0 },
2086 { X86::VPSUBSBZ256rr, X86::VPSUBSBZ256rm, 0 },
2087 { X86::VPSUBSWZ128rr, X86::VPSUBSWZ128rm, 0 },
2088 { X86::VPSUBSWZ256rr, X86::VPSUBSWZ256rm, 0 },
2089 { X86::VPSUBUSBZ128rr, X86::VPSUBUSBZ128rm, 0 },
2090 { X86::VPSUBUSBZ256rr, X86::VPSUBUSBZ256rm, 0 },
2091 { X86::VPSUBUSWZ128rr, X86::VPSUBUSWZ128rm, 0 },
2092 { X86::VPSUBUSWZ256rr, X86::VPSUBUSWZ256rm, 0 },
2093 { X86::VPSUBWZ128rr, X86::VPSUBWZ128rm, 0 },
2094 { X86::VPSUBWZ256rr, X86::VPSUBWZ256rm, 0 },
2095 { X86::VPUNPCKHBWZ128rr, X86::VPUNPCKHBWZ128rm, 0 },
2096 { X86::VPUNPCKHBWZ256rr, X86::VPUNPCKHBWZ256rm, 0 },
2097 { X86::VPUNPCKHDQZ128rr, X86::VPUNPCKHDQZ128rm, 0 },
2098 { X86::VPUNPCKHDQZ256rr, X86::VPUNPCKHDQZ256rm, 0 },
2099 { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm, 0 },
2100 { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm, 0 },
2101 { X86::VPUNPCKHWDZ128rr, X86::VPUNPCKHWDZ128rm, 0 },
2102 { X86::VPUNPCKHWDZ256rr, X86::VPUNPCKHWDZ256rm, 0 },
2103 { X86::VPUNPCKLBWZ128rr, X86::VPUNPCKLBWZ128rm, 0 },
2104 { X86::VPUNPCKLBWZ256rr, X86::VPUNPCKLBWZ256rm, 0 },
2105 { X86::VPUNPCKLDQZ128rr, X86::VPUNPCKLDQZ128rm, 0 },
2106 { X86::VPUNPCKLDQZ256rr, X86::VPUNPCKLDQZ256rm, 0 },
2107 { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm, 0 },
2108 { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm, 0 },
2109 { X86::VPUNPCKLWDZ128rr, X86::VPUNPCKLWDZ128rm, 0 },
2110 { X86::VPUNPCKLWDZ256rr, X86::VPUNPCKLWDZ256rm, 0 },
2111 { X86::VPXORDZ128rr, X86::VPXORDZ128rm, 0 },
2112 { X86::VPXORDZ256rr, X86::VPXORDZ256rm, 0 },
2113 { X86::VPXORQZ128rr, X86::VPXORQZ128rm, 0 },
2114 { X86::VPXORQZ256rr, X86::VPXORQZ256rm, 0 },
2115 { X86::VSUBPDZ128rr, X86::VSUBPDZ128rm, 0 },
2116 { X86::VSUBPDZ256rr, X86::VSUBPDZ256rm, 0 },
2117 { X86::VSUBPSZ128rr, X86::VSUBPSZ128rm, 0 },
2118 { X86::VSUBPSZ256rr, X86::VSUBPSZ256rm, 0 },
2119 { X86::VUNPCKHPDZ128rr, X86::VUNPCKHPDZ128rm, 0 },
2120 { X86::VUNPCKHPDZ256rr, X86::VUNPCKHPDZ256rm, 0 },
2121 { X86::VUNPCKHPSZ128rr, X86::VUNPCKHPSZ128rm, 0 },
2122 { X86::VUNPCKHPSZ256rr, X86::VUNPCKHPSZ256rm, 0 },
2123 { X86::VUNPCKLPDZ128rr, X86::VUNPCKLPDZ128rm, 0 },
2124 { X86::VUNPCKLPDZ256rr, X86::VUNPCKLPDZ256rm, 0 },
2125 { X86::VUNPCKLPSZ128rr, X86::VUNPCKLPSZ128rm, 0 },
2126 { X86::VUNPCKLPSZ256rr, X86::VUNPCKLPSZ256rm, 0 },
2127 { X86::VXORPDZ128rr, X86::VXORPDZ128rm, 0 },
2128 { X86::VXORPDZ256rr, X86::VXORPDZ256rm, 0 },
2129 { X86::VXORPSZ128rr, X86::VXORPSZ128rm, 0 },
2130 { X86::VXORPSZ256rr, X86::VXORPSZ256rm, 0 },
2133 { X86::VPERMILPDZrikz, X86::VPERMILPDZmikz, 0 },
2134 { X86::VPERMILPSZrikz, X86::VPERMILPSZmikz, 0 },
2135 { X86::VPERMPDZrikz, X86::VPERMPDZmikz, 0 },
2136 { X86::VPERMQZrikz, X86::VPERMQZmikz, 0 },
2137 { X86::VPMOVSXBDZrrkz, X86::VPMOVSXBDZrmkz, 0 },
2138 { X86::VPMOVSXBQZrrkz, X86::VPMOVSXBQZrmkz,
TB_NO_REVERSE },
2139 { X86::VPMOVSXBWZrrkz, X86::VPMOVSXBWZrmkz, 0 },
2140 { X86::VPMOVSXDQZrrkz, X86::VPMOVSXDQZrmkz, 0 },
2141 { X86::VPMOVSXWDZrrkz, X86::VPMOVSXWDZrmkz, 0 },
2142 { X86::VPMOVSXWQZrrkz, X86::VPMOVSXWQZrmkz, 0 },
2143 { X86::VPMOVZXBDZrrkz, X86::VPMOVZXBDZrmkz, 0 },
2144 { X86::VPMOVZXBQZrrkz, X86::VPMOVZXBQZrmkz,
TB_NO_REVERSE },
2145 { X86::VPMOVZXBWZrrkz, X86::VPMOVZXBWZrmkz, 0 },
2146 { X86::VPMOVZXDQZrrkz, X86::VPMOVZXDQZrmkz, 0 },
2147 { X86::VPMOVZXWDZrrkz, X86::VPMOVZXWDZrmkz, 0 },
2148 { X86::VPMOVZXWQZrrkz, X86::VPMOVZXWQZrmkz, 0 },
2149 { X86::VPSHUFDZrikz, X86::VPSHUFDZmikz, 0 },
2150 { X86::VPSHUFHWZrikz, X86::VPSHUFHWZmikz, 0 },
2151 { X86::VPSHUFLWZrikz, X86::VPSHUFLWZmikz, 0 },
2154 { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz, 0 },
2155 { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz, 0 },
2156 { X86::VPERMPDZ256rikz, X86::VPERMPDZ256mikz, 0 },
2157 { X86::VPERMQZ256rikz, X86::VPERMQZ256mikz, 0 },
2158 { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz,
TB_NO_REVERSE },
2159 { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz,
TB_NO_REVERSE },
2160 { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz, 0 },
2161 { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz, 0 },
2162 { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz, 0 },
2163 { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz,
TB_NO_REVERSE },
2164 { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz,
TB_NO_REVERSE },
2165 { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz,
TB_NO_REVERSE },
2166 { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz, 0 },
2167 { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz, 0 },
2168 { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz, 0 },
2169 { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz,
TB_NO_REVERSE },
2170 { X86::VPSHUFDZ256rikz, X86::VPSHUFDZ256mikz, 0 },
2171 { X86::VPSHUFHWZ256rikz, X86::VPSHUFHWZ256mikz, 0 },
2172 { X86::VPSHUFLWZ256rikz, X86::VPSHUFLWZ256mikz, 0 },
2175 { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz, 0 },
2176 { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz, 0 },
2177 { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz,
TB_NO_REVERSE },
2178 { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz,
TB_NO_REVERSE },
2179 { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz,
TB_NO_REVERSE },
2180 { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz,
TB_NO_REVERSE },
2181 { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz,
TB_NO_REVERSE },
2182 { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz,
TB_NO_REVERSE },
2183 { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz,
TB_NO_REVERSE },
2184 { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz,
TB_NO_REVERSE },
2185 { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz,
TB_NO_REVERSE },
2186 { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz,
TB_NO_REVERSE },
2187 { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz,
TB_NO_REVERSE },
2188 { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz,
TB_NO_REVERSE },
2189 { X86::VPSHUFDZ128rikz, X86::VPSHUFDZ128mikz, 0 },
2190 { X86::VPSHUFHWZ128rikz, X86::VPSHUFHWZ128mikz, 0 },
2191 { X86::VPSHUFLWZ128rikz, X86::VPSHUFLWZ128mikz, 0 },
2194 { X86::AESDECLASTrr, X86::AESDECLASTrm,
TB_ALIGN_16 },
2196 { X86::AESENCLASTrr, X86::AESENCLASTrm,
TB_ALIGN_16 },
2198 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
2199 { X86::VAESDECrr, X86::VAESDECrm, 0 },
2200 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
2201 { X86::VAESENCrr, X86::VAESENCrm, 0 },
2204 { X86::SHA1MSG1rr, X86::SHA1MSG1rm,
TB_ALIGN_16 },
2205 { X86::SHA1MSG2rr, X86::SHA1MSG2rm,
TB_ALIGN_16 },
2206 { X86::SHA1NEXTErr, X86::SHA1NEXTErm,
TB_ALIGN_16 },
2207 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi,
TB_ALIGN_16 },
2208 { X86::SHA256MSG1rr, X86::SHA256MSG1rm,
TB_ALIGN_16 },
2209 { X86::SHA256MSG2rr, X86::SHA256MSG2rm,
TB_ALIGN_16 },
2210 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm,
TB_ALIGN_16 }
2214 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2215 Entry.RegOp, Entry.MemOp,
2223 { X86::VFMADDSS4rr_Int, X86::VFMADDSS4rm_Int,
TB_NO_REVERSE },
2225 { X86::VFMADDSD4rr_Int, X86::VFMADDSD4rm_Int,
TB_NO_REVERSE },
2231 { X86::VFNMADDSS4rr_Int, X86::VFNMADDSS4rm_Int,
TB_NO_REVERSE },
2233 { X86::VFNMADDSD4rr_Int, X86::VFNMADDSD4rm_Int,
TB_NO_REVERSE },
2239 { X86::VFMSUBSS4rr_Int, X86::VFMSUBSS4rm_Int,
TB_NO_REVERSE },
2241 { X86::VFMSUBSD4rr_Int, X86::VFMSUBSD4rm_Int,
TB_NO_REVERSE },
2247 { X86::VFNMSUBSS4rr_Int, X86::VFNMSUBSS4rm_Int,
TB_NO_REVERSE },
2249 { X86::VFNMSUBSD4rr_Int, X86::VFNMSUBSD4rm_Int,
TB_NO_REVERSE },
2254 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm,
TB_ALIGN_NONE },
2255 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm,
TB_ALIGN_NONE },
2256 { X86::VFMADDSUBPS4Yrr, X86::VFMADDSUBPS4Yrm,
TB_ALIGN_NONE },
2257 { X86::VFMADDSUBPD4Yrr, X86::VFMADDSUBPD4Yrm,
TB_ALIGN_NONE },
2258 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm,
TB_ALIGN_NONE },
2259 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm,
TB_ALIGN_NONE },
2260 { X86::VFMSUBADDPS4Yrr, X86::VFMSUBADDPS4Yrm,
TB_ALIGN_NONE },
2261 { X86::VFMSUBADDPD4Yrr, X86::VFMSUBADDPD4Yrm,
TB_ALIGN_NONE },
2264 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
2265 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
2266 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
2267 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
2268 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
2269 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
2270 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
2273 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
2274 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
2275 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
2276 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
2277 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk,
TB_NO_REVERSE },
2278 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk,
TB_NO_REVERSE },
2279 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk,
TB_NO_REVERSE },
2280 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk,
TB_NO_REVERSE },
2281 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk,
TB_NO_REVERSE },
2282 { X86::VPERMI2Brr, X86::VPERMI2Brm, 0 },
2283 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
2284 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
2285 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
2286 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
2287 { X86::VPERMI2Wrr, X86::VPERMI2Wrm, 0 },
2288 { X86::VPERMT2Brr, X86::VPERMT2Brm, 0 },
2289 { X86::VPERMT2Drr, X86::VPERMT2Drm, 0 },
2290 { X86::VPERMT2PSrr, X86::VPERMT2PSrm, 0 },
2291 { X86::VPERMT2PDrr, X86::VPERMT2PDrm, 0 },
2292 { X86::VPERMT2Qrr, X86::VPERMT2Qrm, 0 },
2293 { X86::VPERMT2Wrr, X86::VPERMT2Wrm, 0 },
2294 { X86::VPTERNLOGDZrri, X86::VPTERNLOGDZrmi, 0 },
2295 { X86::VPTERNLOGQZrri, X86::VPTERNLOGQZrmi, 0 },
2298 { X86::VPERMI2B256rr, X86::VPERMI2B256rm, 0 },
2299 { X86::VPERMI2D256rr, X86::VPERMI2D256rm, 0 },
2300 { X86::VPERMI2PD256rr, X86::VPERMI2PD256rm, 0 },
2301 { X86::VPERMI2PS256rr, X86::VPERMI2PS256rm, 0 },
2302 { X86::VPERMI2Q256rr, X86::VPERMI2Q256rm, 0 },
2303 { X86::VPERMI2W256rr, X86::VPERMI2W256rm, 0 },
2304 { X86::VPERMT2B256rr, X86::VPERMT2B256rm, 0 },
2305 { X86::VPERMT2D256rr, X86::VPERMT2D256rm, 0 },
2306 { X86::VPERMT2PD256rr, X86::VPERMT2PD256rm, 0 },
2307 { X86::VPERMT2PS256rr, X86::VPERMT2PS256rm, 0 },
2308 { X86::VPERMT2Q256rr, X86::VPERMT2Q256rm, 0 },
2309 { X86::VPERMT2W256rr, X86::VPERMT2W256rm, 0 },
2310 { X86::VPTERNLOGDZ256rri, X86::VPTERNLOGDZ256rmi, 0 },
2311 { X86::VPTERNLOGQZ256rri, X86::VPTERNLOGQZ256rmi, 0 },
2314 { X86::VPERMI2B128rr, X86::VPERMI2B128rm, 0 },
2315 { X86::VPERMI2D128rr, X86::VPERMI2D128rm, 0 },
2316 { X86::VPERMI2PD128rr, X86::VPERMI2PD128rm, 0 },
2317 { X86::VPERMI2PS128rr, X86::VPERMI2PS128rm, 0 },
2318 { X86::VPERMI2Q128rr, X86::VPERMI2Q128rm, 0 },
2319 { X86::VPERMI2W128rr, X86::VPERMI2W128rm, 0 },
2320 { X86::VPERMT2B128rr, X86::VPERMT2B128rm, 0 },
2321 { X86::VPERMT2D128rr, X86::VPERMT2D128rm, 0 },
2322 { X86::VPERMT2PD128rr, X86::VPERMT2PD128rm, 0 },
2323 { X86::VPERMT2PS128rr, X86::VPERMT2PS128rm, 0 },
2324 { X86::VPERMT2Q128rr, X86::VPERMT2Q128rm, 0 },
2325 { X86::VPERMT2W128rr, X86::VPERMT2W128rm, 0 },
2326 { X86::VPTERNLOGDZ128rri, X86::VPTERNLOGDZ128rmi, 0 },
2327 { X86::VPTERNLOGQZ128rri, X86::VPTERNLOGQZ128rmi, 0 },
2330 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
2331 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
2332 { X86::VALIGNDZrrikz, X86::VALIGNDZrmikz, 0 },
2333 { X86::VALIGNQZrrikz, X86::VALIGNQZrmikz, 0 },
2334 { X86::VANDNPDZrrkz, X86::VANDNPDZrmkz, 0 },
2335 { X86::VANDNPSZrrkz, X86::VANDNPSZrmkz, 0 },
2336 { X86::VANDPDZrrkz, X86::VANDPDZrmkz, 0 },
2337 { X86::VANDPSZrrkz, X86::VANDPSZrmkz, 0 },
2338 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
2339 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
2340 { X86::VINSERTF32x4Zrrkz, X86::VINSERTF32x4Zrmkz, 0 },
2341 { X86::VINSERTF32x8Zrrkz, X86::VINSERTF32x8Zrmkz, 0 },
2342 { X86::VINSERTF64x2Zrrkz, X86::VINSERTF64x2Zrmkz, 0 },
2343 { X86::VINSERTF64x4Zrrkz, X86::VINSERTF64x4Zrmkz, 0 },
2344 { X86::VINSERTI32x4Zrrkz, X86::VINSERTI32x4Zrmkz, 0 },
2345 { X86::VINSERTI32x8Zrrkz, X86::VINSERTI32x8Zrmkz, 0 },
2346 { X86::VINSERTI64x2Zrrkz, X86::VINSERTI64x2Zrmkz, 0 },
2347 { X86::VINSERTI64x4Zrrkz, X86::VINSERTI64x4Zrmkz, 0 },
2348 { X86::VMAXCPDZrrkz, X86::VMAXCPDZrmkz, 0 },
2349 { X86::VMAXCPSZrrkz, X86::VMAXCPSZrmkz, 0 },
2350 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
2351 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
2352 { X86::VMINCPDZrrkz, X86::VMINCPDZrmkz, 0 },
2353 { X86::VMINCPSZrrkz, X86::VMINCPSZrmkz, 0 },
2354 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
2355 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
2356 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
2357 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
2358 { X86::VORPDZrrkz, X86::VORPDZrmkz, 0 },
2359 { X86::VORPSZrrkz, X86::VORPSZrmkz, 0 },
2360 { X86::VPADDBZrrkz, X86::VPADDBZrmkz, 0 },
2361 { X86::VPADDDZrrkz, X86::VPADDDZrmkz, 0 },
2362 { X86::VPADDQZrrkz, X86::VPADDQZrmkz, 0 },
2363 { X86::VPADDSBZrrkz, X86::VPADDSBZrmkz, 0 },
2364 { X86::VPADDSWZrrkz, X86::VPADDSWZrmkz, 0 },
2365 { X86::VPADDUSBZrrkz, X86::VPADDUSBZrmkz, 0 },
2366 { X86::VPADDUSWZrrkz, X86::VPADDUSWZrmkz, 0 },
2367 { X86::VPADDWZrrkz, X86::VPADDWZrmkz, 0 },
2368 { X86::VPALIGNRZrrikz, X86::VPALIGNRZrmikz, 0 },
2369 { X86::VPANDDZrrkz, X86::VPANDDZrmkz, 0 },
2370 { X86::VPANDNDZrrkz, X86::VPANDNDZrmkz, 0 },
2371 { X86::VPANDNQZrrkz, X86::VPANDNQZrmkz, 0 },
2372 { X86::VPANDQZrrkz, X86::VPANDQZrmkz, 0 },
2373 { X86::VPERMBZrrkz, X86::VPERMBZrmkz, 0 },
2374 { X86::VPERMDZrrkz, X86::VPERMDZrmkz, 0 },
2375 { X86::VPERMILPDZrrkz, X86::VPERMILPDZrmkz, 0 },
2376 { X86::VPERMILPSZrrkz, X86::VPERMILPSZrmkz, 0 },
2377 { X86::VPERMPDZrrkz, X86::VPERMPDZrmkz, 0 },
2378 { X86::VPERMPSZrrkz, X86::VPERMPSZrmkz, 0 },
2379 { X86::VPERMQZrrkz, X86::VPERMQZrmkz, 0 },
2380 { X86::VPERMWZrrkz, X86::VPERMWZrmkz, 0 },
2381 { X86::VPMADDUBSWZrrkz, X86::VPMADDUBSWZrmkz, 0 },
2382 { X86::VPMADDWDZrrkz, X86::VPMADDWDZrmkz, 0 },
2383 { X86::VPORDZrrkz, X86::VPORDZrmkz, 0 },
2384 { X86::VPORQZrrkz, X86::VPORQZrmkz, 0 },
2385 { X86::VPSHUFBZrrkz, X86::VPSHUFBZrmkz, 0 },
2386 { X86::VPSUBBZrrkz, X86::VPSUBBZrmkz, 0 },
2387 { X86::VPSUBDZrrkz, X86::VPSUBDZrmkz, 0 },
2388 { X86::VPSUBQZrrkz, X86::VPSUBQZrmkz, 0 },
2389 { X86::VPSUBSBZrrkz, X86::VPSUBSBZrmkz, 0 },
2390 { X86::VPSUBSWZrrkz, X86::VPSUBSWZrmkz, 0 },
2391 { X86::VPSUBUSBZrrkz, X86::VPSUBUSBZrmkz, 0 },
2392 { X86::VPSUBUSWZrrkz, X86::VPSUBUSWZrmkz, 0 },
2393 { X86::VPSUBWZrrkz, X86::VPSUBWZrmkz, 0 },
2394 { X86::VPUNPCKHBWZrrkz, X86::VPUNPCKHBWZrmkz, 0 },
2395 { X86::VPUNPCKHDQZrrkz, X86::VPUNPCKHDQZrmkz, 0 },
2396 { X86::VPUNPCKHQDQZrrkz, X86::VPUNPCKHQDQZrmkz, 0 },
2397 { X86::VPUNPCKHWDZrrkz, X86::VPUNPCKHWDZrmkz, 0 },
2398 { X86::VPUNPCKLBWZrrkz, X86::VPUNPCKLBWZrmkz, 0 },
2399 { X86::VPUNPCKLDQZrrkz, X86::VPUNPCKLDQZrmkz, 0 },
2400 { X86::VPUNPCKLQDQZrrkz, X86::VPUNPCKLQDQZrmkz, 0 },
2401 { X86::VPUNPCKLWDZrrkz, X86::VPUNPCKLWDZrmkz, 0 },
2402 { X86::VPXORDZrrkz, X86::VPXORDZrmkz, 0 },
2403 { X86::VPXORQZrrkz, X86::VPXORQZrmkz, 0 },
2404 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
2405 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
2406 { X86::VUNPCKHPDZrrkz, X86::VUNPCKHPDZrmkz, 0 },
2407 { X86::VUNPCKHPSZrrkz, X86::VUNPCKHPSZrmkz, 0 },
2408 { X86::VUNPCKLPDZrrkz, X86::VUNPCKLPDZrmkz, 0 },
2409 { X86::VUNPCKLPSZrrkz, X86::VUNPCKLPSZrmkz, 0 },
2410 { X86::VXORPDZrrkz, X86::VXORPDZrmkz, 0 },
2411 { X86::VXORPSZrrkz, X86::VXORPSZrmkz, 0 },
2414 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
2415 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
2416 { X86::VALIGNDZ256rrikz, X86::VALIGNDZ256rmikz, 0 },
2417 { X86::VALIGNQZ256rrikz, X86::VALIGNQZ256rmikz, 0 },
2418 { X86::VANDNPDZ256rrkz, X86::VANDNPDZ256rmkz, 0 },
2419 { X86::VANDNPSZ256rrkz, X86::VANDNPSZ256rmkz, 0 },
2420 { X86::VANDPDZ256rrkz, X86::VANDPDZ256rmkz, 0 },
2421 { X86::VANDPSZ256rrkz, X86::VANDPSZ256rmkz, 0 },
2422 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
2423 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
2424 { X86::VINSERTF32x4Z256rrkz, X86::VINSERTF32x4Z256rmkz, 0 },
2425 { X86::VINSERTF64x2Z256rrkz, X86::VINSERTF64x2Z256rmkz, 0 },
2426 { X86::VINSERTI32x4Z256rrkz, X86::VINSERTI32x4Z256rmkz, 0 },
2427 { X86::VINSERTI64x2Z256rrkz, X86::VINSERTI64x2Z256rmkz, 0 },
2428 { X86::VMAXCPDZ256rrkz, X86::VMAXCPDZ256rmkz, 0 },
2429 { X86::VMAXCPSZ256rrkz, X86::VMAXCPSZ256rmkz, 0 },
2430 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
2431 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
2432 { X86::VMINCPDZ256rrkz, X86::VMINCPDZ256rmkz, 0 },
2433 { X86::VMINCPSZ256rrkz, X86::VMINCPSZ256rmkz, 0 },
2434 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
2435 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
2436 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
2437 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
2438 { X86::VORPDZ256rrkz, X86::VORPDZ256rmkz, 0 },
2439 { X86::VORPSZ256rrkz, X86::VORPSZ256rmkz, 0 },
2440 { X86::VPADDBZ256rrkz, X86::VPADDBZ256rmkz, 0 },
2441 { X86::VPADDDZ256rrkz, X86::VPADDDZ256rmkz, 0 },
2442 { X86::VPADDQZ256rrkz, X86::VPADDQZ256rmkz, 0 },
2443 { X86::VPADDSBZ256rrkz, X86::VPADDSBZ256rmkz, 0 },
2444 { X86::VPADDSWZ256rrkz, X86::VPADDSWZ256rmkz, 0 },
2445 { X86::VPADDUSBZ256rrkz, X86::VPADDUSBZ256rmkz, 0 },
2446 { X86::VPADDUSWZ256rrkz, X86::VPADDUSWZ256rmkz, 0 },
2447 { X86::VPADDWZ256rrkz, X86::VPADDWZ256rmkz, 0 },
2448 { X86::VPALIGNRZ256rrikz, X86::VPALIGNRZ256rmikz, 0 },
2449 { X86::VPANDDZ256rrkz, X86::VPANDDZ256rmkz, 0 },
2450 { X86::VPANDNDZ256rrkz, X86::VPANDNDZ256rmkz, 0 },
2451 { X86::VPANDNQZ256rrkz, X86::VPANDNQZ256rmkz, 0 },
2452 { X86::VPANDQZ256rrkz, X86::VPANDQZ256rmkz, 0 },
2453 { X86::VPERMBZ256rrkz, X86::VPERMBZ256rmkz, 0 },
2454 { X86::VPERMDZ256rrkz, X86::VPERMDZ256rmkz, 0 },
2455 { X86::VPERMILPDZ256rrkz, X86::VPERMILPDZ256rmkz, 0 },
2456 { X86::VPERMILPSZ256rrkz, X86::VPERMILPSZ256rmkz, 0 },
2457 { X86::VPERMPDZ256rrkz, X86::VPERMPDZ256rmkz, 0 },
2458 { X86::VPERMPSZ256rrkz, X86::VPERMPSZ256rmkz, 0 },
2459 { X86::VPERMQZ256rrkz, X86::VPERMQZ256rmkz, 0 },
2460 { X86::VPERMWZ256rrkz, X86::VPERMWZ256rmkz, 0 },
2461 { X86::VPMADDUBSWZ256rrkz, X86::VPMADDUBSWZ256rmkz, 0 },
2462 { X86::VPMADDWDZ256rrkz, X86::VPMADDWDZ256rmkz, 0 },
2463 { X86::VPORDZ256rrkz, X86::VPORDZ256rmkz, 0 },
2464 { X86::VPORQZ256rrkz, X86::VPORQZ256rmkz, 0 },
2465 { X86::VPSHUFBZ256rrkz, X86::VPSHUFBZ256rmkz, 0 },
2466 { X86::VPSUBBZ256rrkz, X86::VPSUBBZ256rmkz, 0 },
2467 { X86::VPSUBDZ256rrkz, X86::VPSUBDZ256rmkz, 0 },
2468 { X86::VPSUBQZ256rrkz, X86::VPSUBQZ256rmkz, 0 },
2469 { X86::VPSUBSBZ256rrkz, X86::VPSUBSBZ256rmkz, 0 },
2470 { X86::VPSUBSWZ256rrkz, X86::VPSUBSWZ256rmkz, 0 },
2471 { X86::VPSUBUSBZ256rrkz, X86::VPSUBUSBZ256rmkz, 0 },
2472 { X86::VPSUBUSWZ256rrkz, X86::VPSUBUSWZ256rmkz, 0 },
2473 { X86::VPSUBWZ256rrkz, X86::VPSUBWZ256rmkz, 0 },
2474 { X86::VPUNPCKHBWZ256rrkz, X86::VPUNPCKHBWZ256rmkz, 0 },
2475 { X86::VPUNPCKHDQZ256rrkz, X86::VPUNPCKHDQZ256rmkz, 0 },
2476 { X86::VPUNPCKHQDQZ256rrkz, X86::VPUNPCKHQDQZ256rmkz, 0 },
2477 { X86::VPUNPCKHWDZ256rrkz, X86::VPUNPCKHWDZ256rmkz, 0 },
2478 { X86::VPUNPCKLBWZ256rrkz, X86::VPUNPCKLBWZ256rmkz, 0 },
2479 { X86::VPUNPCKLDQZ256rrkz, X86::VPUNPCKLDQZ256rmkz, 0 },
2480 { X86::VPUNPCKLQDQZ256rrkz, X86::VPUNPCKLQDQZ256rmkz, 0 },
2481 { X86::VPUNPCKLWDZ256rrkz, X86::VPUNPCKLWDZ256rmkz, 0 },
2482 { X86::VPXORDZ256rrkz, X86::VPXORDZ256rmkz, 0 },
2483 { X86::VPXORQZ256rrkz, X86::VPXORQZ256rmkz, 0 },
2484 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
2485 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
2486 { X86::VUNPCKHPDZ256rrkz, X86::VUNPCKHPDZ256rmkz, 0 },
2487 { X86::VUNPCKHPSZ256rrkz, X86::VUNPCKHPSZ256rmkz, 0 },
2488 { X86::VUNPCKLPDZ256rrkz, X86::VUNPCKLPDZ256rmkz, 0 },
2489 { X86::VUNPCKLPSZ256rrkz, X86::VUNPCKLPSZ256rmkz, 0 },
2490 { X86::VXORPDZ256rrkz, X86::VXORPDZ256rmkz, 0 },
2491 { X86::VXORPSZ256rrkz, X86::VXORPSZ256rmkz, 0 },
2494 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
2495 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
2496 { X86::VALIGNDZ128rrikz, X86::VALIGNDZ128rmikz, 0 },
2497 { X86::VALIGNQZ128rrikz, X86::VALIGNQZ128rmikz, 0 },
2498 { X86::VANDNPDZ128rrkz, X86::VANDNPDZ128rmkz, 0 },
2499 { X86::VANDNPSZ128rrkz, X86::VANDNPSZ128rmkz, 0 },
2500 { X86::VANDPDZ128rrkz, X86::VANDPDZ128rmkz, 0 },
2501 { X86::VANDPSZ128rrkz, X86::VANDPSZ128rmkz, 0 },
2502 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
2503 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
2504 { X86::VMAXCPDZ128rrkz, X86::VMAXCPDZ128rmkz, 0 },
2505 { X86::VMAXCPSZ128rrkz, X86::VMAXCPSZ128rmkz, 0 },
2506 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 },
2507 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
2508 { X86::VMINCPDZ128rrkz, X86::VMINCPDZ128rmkz, 0 },
2509 { X86::VMINCPSZ128rrkz, X86::VMINCPSZ128rmkz, 0 },
2510 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
2511 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
2512 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
2513 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
2514 { X86::VORPDZ128rrkz, X86::VORPDZ128rmkz, 0 },
2515 { X86::VORPSZ128rrkz, X86::VORPSZ128rmkz, 0 },
2516 { X86::VPADDBZ128rrkz, X86::VPADDBZ128rmkz, 0 },
2517 { X86::VPADDDZ128rrkz, X86::VPADDDZ128rmkz, 0 },
2518 { X86::VPADDQZ128rrkz, X86::VPADDQZ128rmkz, 0 },
2519 { X86::VPADDSBZ128rrkz, X86::VPADDSBZ128rmkz, 0 },
2520 { X86::VPADDSWZ128rrkz, X86::VPADDSWZ128rmkz, 0 },
2521 { X86::VPADDUSBZ128rrkz, X86::VPADDUSBZ128rmkz, 0 },
2522 { X86::VPADDUSWZ128rrkz, X86::VPADDUSWZ128rmkz, 0 },
2523 { X86::VPADDWZ128rrkz, X86::VPADDWZ128rmkz, 0 },
2524 { X86::VPALIGNRZ128rrikz, X86::VPALIGNRZ128rmikz, 0 },
2525 { X86::VPANDDZ128rrkz, X86::VPANDDZ128rmkz, 0 },
2526 { X86::VPANDNDZ128rrkz, X86::VPANDNDZ128rmkz, 0 },
2527 { X86::VPANDNQZ128rrkz, X86::VPANDNQZ128rmkz, 0 },
2528 { X86::VPANDQZ128rrkz, X86::VPANDQZ128rmkz, 0 },
2529 { X86::VPERMBZ128rrkz, X86::VPERMBZ128rmkz, 0 },
2530 { X86::VPERMILPDZ128rrkz, X86::VPERMILPDZ128rmkz, 0 },
2531 { X86::VPERMILPSZ128rrkz, X86::VPERMILPSZ128rmkz, 0 },
2532 { X86::VPERMWZ128rrkz, X86::VPERMWZ128rmkz, 0 },
2533 { X86::VPMADDUBSWZ128rrkz, X86::VPMADDUBSWZ128rmkz, 0 },
2534 { X86::VPMADDWDZ128rrkz, X86::VPMADDWDZ128rmkz, 0 },
2535 { X86::VPORDZ128rrkz, X86::VPORDZ128rmkz, 0 },
2536 { X86::VPORQZ128rrkz, X86::VPORQZ128rmkz, 0 },
2537 { X86::VPSHUFBZ128rrkz, X86::VPSHUFBZ128rmkz, 0 },
2538 { X86::VPSUBBZ128rrkz, X86::VPSUBBZ128rmkz, 0 },
2539 { X86::VPSUBDZ128rrkz, X86::VPSUBDZ128rmkz, 0 },
2540 { X86::VPSUBQZ128rrkz, X86::VPSUBQZ128rmkz, 0 },
2541 { X86::VPSUBSBZ128rrkz, X86::VPSUBSBZ128rmkz, 0 },
2542 { X86::VPSUBSWZ128rrkz, X86::VPSUBSWZ128rmkz, 0 },
2543 { X86::VPSUBUSBZ128rrkz, X86::VPSUBUSBZ128rmkz, 0 },
2544 { X86::VPSUBUSWZ128rrkz, X86::VPSUBUSWZ128rmkz, 0 },
2545 { X86::VPSUBWZ128rrkz, X86::VPSUBWZ128rmkz, 0 },
2546 { X86::VPUNPCKHBWZ128rrkz, X86::VPUNPCKHBWZ128rmkz, 0 },
2547 { X86::VPUNPCKHDQZ128rrkz, X86::VPUNPCKHDQZ128rmkz, 0 },
2548 { X86::VPUNPCKHQDQZ128rrkz, X86::VPUNPCKHQDQZ128rmkz, 0 },
2549 { X86::VPUNPCKHWDZ128rrkz, X86::VPUNPCKHWDZ128rmkz, 0 },
2550 { X86::VPUNPCKLBWZ128rrkz, X86::VPUNPCKLBWZ128rmkz, 0 },
2551 { X86::VPUNPCKLDQZ128rrkz, X86::VPUNPCKLDQZ128rmkz, 0 },
2552 { X86::VPUNPCKLQDQZ128rrkz, X86::VPUNPCKLQDQZ128rmkz, 0 },
2553 { X86::VPUNPCKLWDZ128rrkz, X86::VPUNPCKLWDZ128rmkz, 0 },
2554 { X86::VPXORDZ128rrkz, X86::VPXORDZ128rmkz, 0 },
2555 { X86::VPXORQZ128rrkz, X86::VPXORQZ128rmkz, 0 },
2556 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
2557 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
2558 { X86::VUNPCKHPDZ128rrkz, X86::VUNPCKHPDZ128rmkz, 0 },
2559 { X86::VUNPCKHPSZ128rrkz, X86::VUNPCKHPSZ128rmkz, 0 },
2560 { X86::VUNPCKLPDZ128rrkz, X86::VUNPCKLPDZ128rmkz, 0 },
2561 { X86::VUNPCKLPSZ128rrkz, X86::VUNPCKLPSZ128rmkz, 0 },
2562 { X86::VXORPDZ128rrkz, X86::VXORPDZ128rmkz, 0 },
2563 { X86::VXORPSZ128rrkz, X86::VXORPSZ128rmkz, 0 },
2566 { X86::VPERMILPDZrik, X86::VPERMILPDZmik, 0 },
2567 { X86::VPERMILPSZrik, X86::VPERMILPSZmik, 0 },
2568 { X86::VPERMPDZrik, X86::VPERMPDZmik, 0 },
2569 { X86::VPERMQZrik, X86::VPERMQZmik, 0 },
2570 { X86::VPMOVSXBDZrrk, X86::VPMOVSXBDZrmk, 0 },
2572 { X86::VPMOVSXBWZrrk, X86::VPMOVSXBWZrmk, 0 },
2573 { X86::VPMOVSXDQZrrk, X86::VPMOVSXDQZrmk, 0 },
2574 { X86::VPMOVSXWDZrrk, X86::VPMOVSXWDZrmk, 0 },
2575 { X86::VPMOVSXWQZrrk, X86::VPMOVSXWQZrmk, 0 },
2576 { X86::VPMOVZXBDZrrk, X86::VPMOVZXBDZrmk, 0 },
2578 { X86::VPMOVZXBWZrrk, X86::VPMOVZXBWZrmk, 0 },
2579 { X86::VPMOVZXDQZrrk, X86::VPMOVZXDQZrmk, 0 },
2580 { X86::VPMOVZXWDZrrk, X86::VPMOVZXWDZrmk, 0 },
2581 { X86::VPMOVZXWQZrrk, X86::VPMOVZXWQZrmk, 0 },
2582 { X86::VPSHUFDZrik, X86::VPSHUFDZmik, 0 },
2583 { X86::VPSHUFHWZrik, X86::VPSHUFHWZmik, 0 },
2584 { X86::VPSHUFLWZrik, X86::VPSHUFLWZmik, 0 },
2587 { X86::VPERMILPDZ256rik, X86::VPERMILPDZ256mik, 0 },
2588 { X86::VPERMILPSZ256rik, X86::VPERMILPSZ256mik, 0 },
2589 { X86::VPERMPDZ256rik, X86::VPERMPDZ256mik, 0 },
2590 { X86::VPERMQZ256rik, X86::VPERMQZ256mik, 0 },
2591 { X86::VPMOVSXBDZ256rrk, X86::VPMOVSXBDZ256rmk,
TB_NO_REVERSE },
2592 { X86::VPMOVSXBQZ256rrk, X86::VPMOVSXBQZ256rmk,
TB_NO_REVERSE },
2593 { X86::VPMOVSXBWZ256rrk, X86::VPMOVSXBWZ256rmk, 0 },
2594 { X86::VPMOVSXDQZ256rrk, X86::VPMOVSXDQZ256rmk, 0 },
2595 { X86::VPMOVSXWDZ256rrk, X86::VPMOVSXWDZ256rmk, 0 },
2596 { X86::VPMOVSXWQZ256rrk, X86::VPMOVSXWQZ256rmk,
TB_NO_REVERSE },
2597 { X86::VPMOVZXBDZ256rrk, X86::VPMOVZXBDZ256rmk,
TB_NO_REVERSE },
2598 { X86::VPMOVZXBQZ256rrk, X86::VPMOVZXBQZ256rmk,
TB_NO_REVERSE },
2599 { X86::VPMOVZXBWZ256rrk, X86::VPMOVZXBWZ256rmk, 0 },
2600 { X86::VPMOVZXDQZ256rrk, X86::VPMOVZXDQZ256rmk, 0 },
2601 { X86::VPMOVZXWDZ256rrk, X86::VPMOVZXWDZ256rmk, 0 },
2602 { X86::VPMOVZXWQZ256rrk, X86::VPMOVZXWQZ256rmk,
TB_NO_REVERSE },
2603 { X86::VPSHUFDZ256rik, X86::VPSHUFDZ256mik, 0 },
2604 { X86::VPSHUFHWZ256rik, X86::VPSHUFHWZ256mik, 0 },
2605 { X86::VPSHUFLWZ256rik, X86::VPSHUFLWZ256mik, 0 },
2608 { X86::VPERMILPDZ128rik, X86::VPERMILPDZ128mik, 0 },
2609 { X86::VPERMILPSZ128rik, X86::VPERMILPSZ128mik, 0 },
2610 { X86::VPMOVSXBDZ128rrk, X86::VPMOVSXBDZ128rmk,
TB_NO_REVERSE },
2611 { X86::VPMOVSXBQZ128rrk, X86::VPMOVSXBQZ128rmk,
TB_NO_REVERSE },
2612 { X86::VPMOVSXBWZ128rrk, X86::VPMOVSXBWZ128rmk,
TB_NO_REVERSE },
2613 { X86::VPMOVSXDQZ128rrk, X86::VPMOVSXDQZ128rmk,
TB_NO_REVERSE },
2614 { X86::VPMOVSXWDZ128rrk, X86::VPMOVSXWDZ128rmk,
TB_NO_REVERSE },
2615 { X86::VPMOVSXWQZ128rrk, X86::VPMOVSXWQZ128rmk,
TB_NO_REVERSE },
2616 { X86::VPMOVZXBDZ128rrk, X86::VPMOVZXBDZ128rmk,
TB_NO_REVERSE },
2617 { X86::VPMOVZXBQZ128rrk, X86::VPMOVZXBQZ128rmk,
TB_NO_REVERSE },
2618 { X86::VPMOVZXBWZ128rrk, X86::VPMOVZXBWZ128rmk,
TB_NO_REVERSE },
2619 { X86::VPMOVZXDQZ128rrk, X86::VPMOVZXDQZ128rmk,
TB_NO_REVERSE },
2620 { X86::VPMOVZXWDZ128rrk, X86::VPMOVZXWDZ128rmk,
TB_NO_REVERSE },
2621 { X86::VPMOVZXWQZ128rrk, X86::VPMOVZXWQZ128rmk,
TB_NO_REVERSE },
2622 { X86::VPSHUFDZ128rik, X86::VPSHUFDZ128mik, 0 },
2623 { X86::VPSHUFHWZ128rik, X86::VPSHUFHWZ128mik, 0 },
2624 { X86::VPSHUFLWZ128rik, X86::VPSHUFLWZ128mik, 0 },
2628 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2629 Entry.RegOp, Entry.MemOp,
2635 for (;
I !=
E; ++
I) {
2636 if (!
I.getGroup()->isKMasked()) {
2638 if (
I.getGroup()->isIntrinsic()) {
2639 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2640 I.getRegOpcode(),
I.getMemOpcode(),
2643 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2644 I.getRegOpcode(),
I.getMemOpcode(),
2652 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
2653 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
2654 { X86::VALIGNDZrrik, X86::VALIGNDZrmik, 0 },
2655 { X86::VALIGNQZrrik, X86::VALIGNQZrmik, 0 },
2656 { X86::VANDNPDZrrk, X86::VANDNPDZrmk, 0 },
2657 { X86::VANDNPSZrrk, X86::VANDNPSZrmk, 0 },
2658 { X86::VANDPDZrrk, X86::VANDPDZrmk, 0 },
2659 { X86::VANDPSZrrk, X86::VANDPSZrmk, 0 },
2660 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2661 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2662 { X86::VINSERTF32x4Zrrk, X86::VINSERTF32x4Zrmk, 0 },
2663 { X86::VINSERTF32x8Zrrk, X86::VINSERTF32x8Zrmk, 0 },
2664 { X86::VINSERTF64x2Zrrk, X86::VINSERTF64x2Zrmk, 0 },
2665 { X86::VINSERTF64x4Zrrk, X86::VINSERTF64x4Zrmk, 0 },
2666 { X86::VINSERTI32x4Zrrk, X86::VINSERTI32x4Zrmk, 0 },
2667 { X86::VINSERTI32x8Zrrk, X86::VINSERTI32x8Zrmk, 0 },
2668 { X86::VINSERTI64x2Zrrk, X86::VINSERTI64x2Zrmk, 0 },
2669 { X86::VINSERTI64x4Zrrk, X86::VINSERTI64x4Zrmk, 0 },
2670 { X86::VMAXCPDZrrk, X86::VMAXCPDZrmk, 0 },
2671 { X86::VMAXCPSZrrk, X86::VMAXCPSZrmk, 0 },
2672 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
2673 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2674 { X86::VMINCPDZrrk, X86::VMINCPDZrmk, 0 },
2675 { X86::VMINCPSZrrk, X86::VMINCPSZrmk, 0 },
2676 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
2677 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2678 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2679 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2680 { X86::VORPDZrrk, X86::VORPDZrmk, 0 },
2681 { X86::VORPSZrrk, X86::VORPSZrmk, 0 },
2682 { X86::VPADDBZrrk, X86::VPADDBZrmk, 0 },
2683 { X86::VPADDDZrrk, X86::VPADDDZrmk, 0 },
2684 { X86::VPADDQZrrk, X86::VPADDQZrmk, 0 },
2685 { X86::VPADDSBZrrk, X86::VPADDSBZrmk, 0 },
2686 { X86::VPADDSWZrrk, X86::VPADDSWZrmk, 0 },
2687 { X86::VPADDUSBZrrk, X86::VPADDUSBZrmk, 0 },
2688 { X86::VPADDUSWZrrk, X86::VPADDUSWZrmk, 0 },
2689 { X86::VPADDWZrrk, X86::VPADDWZrmk, 0 },
2690 { X86::VPALIGNRZrrik, X86::VPALIGNRZrmik, 0 },
2691 { X86::VPANDDZrrk, X86::VPANDDZrmk, 0 },
2692 { X86::VPANDNDZrrk, X86::VPANDNDZrmk, 0 },
2693 { X86::VPANDNQZrrk, X86::VPANDNQZrmk, 0 },
2694 { X86::VPANDQZrrk, X86::VPANDQZrmk, 0 },
2695 { X86::VPERMBZrrk, X86::VPERMBZrmk, 0 },
2696 { X86::VPERMDZrrk, X86::VPERMDZrmk, 0 },
2697 { X86::VPERMI2Brrk, X86::VPERMI2Brmk, 0 },
2698 { X86::VPERMI2Drrk, X86::VPERMI2Drmk, 0 },
2699 { X86::VPERMI2PSrrk, X86::VPERMI2PSrmk, 0 },
2700 { X86::VPERMI2PDrrk, X86::VPERMI2PDrmk, 0 },
2701 { X86::VPERMI2Qrrk, X86::VPERMI2Qrmk, 0 },
2702 { X86::VPERMI2Wrrk, X86::VPERMI2Wrmk, 0 },
2703 { X86::VPERMILPDZrrk, X86::VPERMILPDZrmk, 0 },
2704 { X86::VPERMILPSZrrk, X86::VPERMILPSZrmk, 0 },
2705 { X86::VPERMPDZrrk, X86::VPERMPDZrmk, 0 },
2706 { X86::VPERMPSZrrk, X86::VPERMPSZrmk, 0 },
2707 { X86::VPERMQZrrk, X86::VPERMQZrmk, 0 },
2708 { X86::VPERMT2Brrk, X86::VPERMT2Brmk, 0 },
2709 { X86::VPERMT2Drrk, X86::VPERMT2Drmk, 0 },
2710 { X86::VPERMT2PSrrk, X86::VPERMT2PSrmk, 0 },
2711 { X86::VPERMT2PDrrk, X86::VPERMT2PDrmk, 0 },
2712 { X86::VPERMT2Qrrk, X86::VPERMT2Qrmk, 0 },
2713 { X86::VPERMT2Wrrk, X86::VPERMT2Wrmk, 0 },
2714 { X86::VPERMWZrrk, X86::VPERMWZrmk, 0 },
2715 { X86::VPMADDUBSWZrrk, X86::VPMADDUBSWZrmk, 0 },
2716 { X86::VPMADDWDZrrk, X86::VPMADDWDZrmk, 0 },
2717 { X86::VPORDZrrk, X86::VPORDZrmk, 0 },
2718 { X86::VPORQZrrk, X86::VPORQZrmk, 0 },
2719 { X86::VPSHUFBZrrk, X86::VPSHUFBZrmk, 0 },
2720 { X86::VPSUBBZrrk, X86::VPSUBBZrmk, 0 },
2721 { X86::VPSUBDZrrk, X86::VPSUBDZrmk, 0 },
2722 { X86::VPSUBQZrrk, X86::VPSUBQZrmk, 0 },
2723 { X86::VPSUBSBZrrk, X86::VPSUBSBZrmk, 0 },
2724 { X86::VPSUBSWZrrk, X86::VPSUBSWZrmk, 0 },
2725 { X86::VPSUBUSBZrrk, X86::VPSUBUSBZrmk, 0 },
2726 { X86::VPSUBUSWZrrk, X86::VPSUBUSWZrmk, 0 },
2727 { X86::VPTERNLOGDZrrik, X86::VPTERNLOGDZrmik, 0 },
2728 { X86::VPTERNLOGQZrrik, X86::VPTERNLOGQZrmik, 0 },
2729 { X86::VPUNPCKHBWZrrk, X86::VPUNPCKHBWZrmk, 0 },
2730 { X86::VPUNPCKHDQZrrk, X86::VPUNPCKHDQZrmk, 0 },
2731 { X86::VPUNPCKHQDQZrrk, X86::VPUNPCKHQDQZrmk, 0 },
2732 { X86::VPUNPCKHWDZrrk, X86::VPUNPCKHWDZrmk, 0 },
2733 { X86::VPUNPCKLBWZrrk, X86::VPUNPCKLBWZrmk, 0 },
2734 { X86::VPUNPCKLDQZrrk, X86::VPUNPCKLDQZrmk, 0 },
2735 { X86::VPUNPCKLQDQZrrk, X86::VPUNPCKLQDQZrmk, 0 },
2736 { X86::VPUNPCKLWDZrrk, X86::VPUNPCKLWDZrmk, 0 },
2737 { X86::VPXORDZrrk, X86::VPXORDZrmk, 0 },
2738 { X86::VPXORQZrrk, X86::VPXORQZrmk, 0 },
2739 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2740 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2741 { X86::VUNPCKHPDZrrk, X86::VUNPCKHPDZrmk, 0 },
2742 { X86::VUNPCKHPSZrrk, X86::VUNPCKHPSZrmk, 0 },
2743 { X86::VUNPCKLPDZrrk, X86::VUNPCKLPDZrmk, 0 },
2744 { X86::VUNPCKLPSZrrk, X86::VUNPCKLPSZrmk, 0 },
2745 { X86::VXORPDZrrk, X86::VXORPDZrmk, 0 },
2746 { X86::VXORPSZrrk, X86::VXORPSZrmk, 0 },
2749 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2750 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2751 { X86::VALIGNDZ256rrik, X86::VALIGNDZ256rmik, 0 },
2752 { X86::VALIGNQZ256rrik, X86::VALIGNQZ256rmik, 0 },
2753 { X86::VANDNPDZ256rrk, X86::VANDNPDZ256rmk, 0 },
2754 { X86::VANDNPSZ256rrk, X86::VANDNPSZ256rmk, 0 },
2755 { X86::VANDPDZ256rrk, X86::VANDPDZ256rmk, 0 },
2756 { X86::VANDPSZ256rrk, X86::VANDPSZ256rmk, 0 },
2757 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2758 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2759 { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk, 0 },
2760 { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk, 0 },
2761 { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk, 0 },
2762 { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk, 0 },
2763 { X86::VMAXCPDZ256rrk, X86::VMAXCPDZ256rmk, 0 },
2764 { X86::VMAXCPSZ256rrk, X86::VMAXCPSZ256rmk, 0 },
2765 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2766 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2767 { X86::VMINCPDZ256rrk, X86::VMINCPDZ256rmk, 0 },
2768 { X86::VMINCPSZ256rrk, X86::VMINCPSZ256rmk, 0 },
2769 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2770 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2771 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2772 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2773 { X86::VORPDZ256rrk, X86::VORPDZ256rmk, 0 },
2774 { X86::VORPSZ256rrk, X86::VORPSZ256rmk, 0 },
2775 { X86::VPADDBZ256rrk, X86::VPADDBZ256rmk, 0 },
2776 { X86::VPADDDZ256rrk, X86::VPADDDZ256rmk, 0 },
2777 { X86::VPADDQZ256rrk, X86::VPADDQZ256rmk, 0 },
2778 { X86::VPADDSBZ256rrk, X86::VPADDSBZ256rmk, 0 },
2779 { X86::VPADDSWZ256rrk, X86::VPADDSWZ256rmk, 0 },
2780 { X86::VPADDUSBZ256rrk, X86::VPADDUSBZ256rmk, 0 },
2781 { X86::VPADDUSWZ256rrk, X86::VPADDUSWZ256rmk, 0 },
2782 { X86::VPADDWZ256rrk, X86::VPADDWZ256rmk, 0 },
2783 { X86::VPALIGNRZ256rrik, X86::VPALIGNRZ256rmik, 0 },
2784 { X86::VPANDDZ256rrk, X86::VPANDDZ256rmk, 0 },
2785 { X86::VPANDNDZ256rrk, X86::VPANDNDZ256rmk, 0 },
2786 { X86::VPANDNQZ256rrk, X86::VPANDNQZ256rmk, 0 },
2787 { X86::VPANDQZ256rrk, X86::VPANDQZ256rmk, 0 },
2788 { X86::VPERMBZ256rrk, X86::VPERMBZ256rmk, 0 },
2789 { X86::VPERMDZ256rrk, X86::VPERMDZ256rmk, 0 },
2790 { X86::VPERMI2B256rrk, X86::VPERMI2B256rmk, 0 },
2791 { X86::VPERMI2D256rrk, X86::VPERMI2D256rmk, 0 },
2792 { X86::VPERMI2PD256rrk, X86::VPERMI2PD256rmk, 0 },
2793 { X86::VPERMI2PS256rrk, X86::VPERMI2PS256rmk, 0 },
2794 { X86::VPERMI2Q256rrk, X86::VPERMI2Q256rmk, 0 },
2795 { X86::VPERMI2W256rrk, X86::VPERMI2W256rmk, 0 },
2796 { X86::VPERMILPDZ256rrk, X86::VPERMILPDZ256rmk, 0 },
2797 { X86::VPERMILPSZ256rrk, X86::VPERMILPSZ256rmk, 0 },
2798 { X86::VPERMPDZ256rrk, X86::VPERMPDZ256rmk, 0 },
2799 { X86::VPERMPSZ256rrk, X86::VPERMPSZ256rmk, 0 },
2800 { X86::VPERMQZ256rrk, X86::VPERMQZ256rmk, 0 },
2801 { X86::VPERMT2B256rrk, X86::VPERMT2B256rmk, 0 },
2802 { X86::VPERMT2D256rrk, X86::VPERMT2D256rmk, 0 },
2803 { X86::VPERMT2PD256rrk, X86::VPERMT2PD256rmk, 0 },
2804 { X86::VPERMT2PS256rrk, X86::VPERMT2PS256rmk, 0 },
2805 { X86::VPERMT2Q256rrk, X86::VPERMT2Q256rmk, 0 },
2806 { X86::VPERMT2W256rrk, X86::VPERMT2W256rmk, 0 },
2807 { X86::VPERMWZ256rrk, X86::VPERMWZ256rmk, 0 },
2808 { X86::VPMADDUBSWZ256rrk, X86::VPMADDUBSWZ256rmk, 0 },
2809 { X86::VPMADDWDZ256rrk, X86::VPMADDWDZ256rmk, 0 },
2810 { X86::VPORDZ256rrk, X86::VPORDZ256rmk, 0 },
2811 { X86::VPORQZ256rrk, X86::VPORQZ256rmk, 0 },
2812 { X86::VPSHUFBZ256rrk, X86::VPSHUFBZ256rmk, 0 },
2813 { X86::VPSUBBZ256rrk, X86::VPSUBBZ256rmk, 0 },
2814 { X86::VPSUBDZ256rrk, X86::VPSUBDZ256rmk, 0 },
2815 { X86::VPSUBQZ256rrk, X86::VPSUBQZ256rmk, 0 },
2816 { X86::VPSUBSBZ256rrk, X86::VPSUBSBZ256rmk, 0 },
2817 { X86::VPSUBSWZ256rrk, X86::VPSUBSWZ256rmk, 0 },
2818 { X86::VPSUBUSBZ256rrk, X86::VPSUBUSBZ256rmk, 0 },
2819 { X86::VPSUBUSWZ256rrk, X86::VPSUBUSWZ256rmk, 0 },
2820 { X86::VPSUBWZ256rrk, X86::VPSUBWZ256rmk, 0 },
2821 { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik, 0 },
2822 { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik, 0 },
2823 { X86::VPUNPCKHBWZ256rrk, X86::VPUNPCKHBWZ256rmk, 0 },
2824 { X86::VPUNPCKHDQZ256rrk, X86::VPUNPCKHDQZ256rmk, 0 },
2825 { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk, 0 },
2826 { X86::VPUNPCKHWDZ256rrk, X86::VPUNPCKHWDZ256rmk, 0 },
2827 { X86::VPUNPCKLBWZ256rrk, X86::VPUNPCKLBWZ256rmk, 0 },
2828 { X86::VPUNPCKLDQZ256rrk, X86::VPUNPCKLDQZ256rmk, 0 },
2829 { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk, 0 },
2830 { X86::VPUNPCKLWDZ256rrk, X86::VPUNPCKLWDZ256rmk, 0 },
2831 { X86::VPXORDZ256rrk, X86::VPXORDZ256rmk, 0 },
2832 { X86::VPXORQZ256rrk, X86::VPXORQZ256rmk, 0 },
2833 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2834 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2835 { X86::VUNPCKHPDZ256rrk, X86::VUNPCKHPDZ256rmk, 0 },
2836 { X86::VUNPCKHPSZ256rrk, X86::VUNPCKHPSZ256rmk, 0 },
2837 { X86::VUNPCKLPDZ256rrk, X86::VUNPCKLPDZ256rmk, 0 },
2838 { X86::VUNPCKLPSZ256rrk, X86::VUNPCKLPSZ256rmk, 0 },
2839 { X86::VXORPDZ256rrk, X86::VXORPDZ256rmk, 0 },
2840 { X86::VXORPSZ256rrk, X86::VXORPSZ256rmk, 0 },
2843 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2844 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2845 { X86::VALIGNDZ128rrik, X86::VALIGNDZ128rmik, 0 },
2846 { X86::VALIGNQZ128rrik, X86::VALIGNQZ128rmik, 0 },
2847 { X86::VANDNPDZ128rrk, X86::VANDNPDZ128rmk, 0 },
2848 { X86::VANDNPSZ128rrk, X86::VANDNPSZ128rmk, 0 },
2849 { X86::VANDPDZ128rrk, X86::VANDPDZ128rmk, 0 },
2850 { X86::VANDPSZ128rrk, X86::VANDPSZ128rmk, 0 },
2851 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2852 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2853 { X86::VMAXCPDZ128rrk, X86::VMAXCPDZ128rmk, 0 },
2854 { X86::VMAXCPSZ128rrk, X86::VMAXCPSZ128rmk, 0 },
2855 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 },
2856 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2857 { X86::VMINCPDZ128rrk, X86::VMINCPDZ128rmk, 0 },
2858 { X86::VMINCPSZ128rrk, X86::VMINCPSZ128rmk, 0 },
2859 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2860 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2861 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2862 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2863 { X86::VORPDZ128rrk, X86::VORPDZ128rmk, 0 },
2864 { X86::VORPSZ128rrk, X86::VORPSZ128rmk, 0 },
2865 { X86::VPADDBZ128rrk, X86::VPADDBZ128rmk, 0 },
2866 { X86::VPADDDZ128rrk, X86::VPADDDZ128rmk, 0 },
2867 { X86::VPADDQZ128rrk, X86::VPADDQZ128rmk, 0 },
2868 { X86::VPADDSBZ128rrk, X86::VPADDSBZ128rmk, 0 },
2869 { X86::VPADDSWZ128rrk, X86::VPADDSWZ128rmk, 0 },
2870 { X86::VPADDUSBZ128rrk, X86::VPADDUSBZ128rmk, 0 },
2871 { X86::VPADDUSWZ128rrk, X86::VPADDUSWZ128rmk, 0 },
2872 { X86::VPADDWZ128rrk, X86::VPADDWZ128rmk, 0 },
2873 { X86::VPALIGNRZ128rrik, X86::VPALIGNRZ128rmik, 0 },
2874 { X86::VPANDDZ128rrk, X86::VPANDDZ128rmk, 0 },
2875 { X86::VPANDNDZ128rrk, X86::VPANDNDZ128rmk, 0 },
2876 { X86::VPANDNQZ128rrk, X86::VPANDNQZ128rmk, 0 },
2877 { X86::VPANDQZ128rrk, X86::VPANDQZ128rmk, 0 },
2878 { X86::VPERMBZ128rrk, X86::VPERMBZ128rmk, 0 },
2879 { X86::VPERMI2B128rrk, X86::VPERMI2B128rmk, 0 },
2880 { X86::VPERMI2D128rrk, X86::VPERMI2D128rmk, 0 },
2881 { X86::VPERMI2PD128rrk, X86::VPERMI2PD128rmk, 0 },
2882 { X86::VPERMI2PS128rrk, X86::VPERMI2PS128rmk, 0 },
2883 { X86::VPERMI2Q128rrk, X86::VPERMI2Q128rmk, 0 },
2884 { X86::VPERMI2W128rrk, X86::VPERMI2W128rmk, 0 },
2885 { X86::VPERMILPDZ128rrk, X86::VPERMILPDZ128rmk, 0 },
2886 { X86::VPERMILPSZ128rrk, X86::VPERMILPSZ128rmk, 0 },
2887 { X86::VPERMT2B128rrk, X86::VPERMT2B128rmk, 0 },
2888 { X86::VPERMT2D128rrk, X86::VPERMT2D128rmk, 0 },
2889 { X86::VPERMT2PD128rrk, X86::VPERMT2PD128rmk, 0 },
2890 { X86::VPERMT2PS128rrk, X86::VPERMT2PS128rmk, 0 },
2891 { X86::VPERMT2Q128rrk, X86::VPERMT2Q128rmk, 0 },
2892 { X86::VPERMT2W128rrk, X86::VPERMT2W128rmk, 0 },
2893 { X86::VPERMWZ128rrk, X86::VPERMWZ128rmk, 0 },
2894 { X86::VPMADDUBSWZ128rrk, X86::VPMADDUBSWZ128rmk, 0 },
2895 { X86::VPMADDWDZ128rrk, X86::VPMADDWDZ128rmk, 0 },
2896 { X86::VPORDZ128rrk, X86::VPORDZ128rmk, 0 },
2897 { X86::VPORQZ128rrk, X86::VPORQZ128rmk, 0 },
2898 { X86::VPSHUFBZ128rrk, X86::VPSHUFBZ128rmk, 0 },
2899 { X86::VPSUBBZ128rrk, X86::VPSUBBZ128rmk, 0 },
2900 { X86::VPSUBDZ128rrk, X86::VPSUBDZ128rmk, 0 },
2901 { X86::VPSUBQZ128rrk, X86::VPSUBQZ128rmk, 0 },
2902 { X86::VPSUBSBZ128rrk, X86::VPSUBSBZ128rmk, 0 },
2903 { X86::VPSUBSWZ128rrk, X86::VPSUBSWZ128rmk, 0 },
2904 { X86::VPSUBUSBZ128rrk, X86::VPSUBUSBZ128rmk, 0 },
2905 { X86::VPSUBUSWZ128rrk, X86::VPSUBUSWZ128rmk, 0 },
2906 { X86::VPSUBWZ128rrk, X86::VPSUBWZ128rmk, 0 },
2907 { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik, 0 },
2908 { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik, 0 },
2909 { X86::VPUNPCKHBWZ128rrk, X86::VPUNPCKHBWZ128rmk, 0 },
2910 { X86::VPUNPCKHDQZ128rrk, X86::VPUNPCKHDQZ128rmk, 0 },
2911 { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk, 0 },
2912 { X86::VPUNPCKHWDZ128rrk, X86::VPUNPCKHWDZ128rmk, 0 },
2913 { X86::VPUNPCKLBWZ128rrk, X86::VPUNPCKLBWZ128rmk, 0 },
2914 { X86::VPUNPCKLDQZ128rrk, X86::VPUNPCKLDQZ128rmk, 0 },
2915 { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk, 0 },
2916 { X86::VPUNPCKLWDZ128rrk, X86::VPUNPCKLWDZ128rmk, 0 },
2917 { X86::VPXORDZ128rrk, X86::VPXORDZ128rmk, 0 },
2918 { X86::VPXORQZ128rrk, X86::VPXORQZ128rmk, 0 },
2919 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2920 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2921 { X86::VUNPCKHPDZ128rrk, X86::VUNPCKHPDZ128rmk, 0 },
2922 { X86::VUNPCKHPSZ128rrk, X86::VUNPCKHPSZ128rmk, 0 },
2923 { X86::VUNPCKLPDZ128rrk, X86::VUNPCKLPDZ128rmk, 0 },
2924 { X86::VUNPCKLPSZ128rrk, X86::VUNPCKLPSZ128rmk, 0 },
2925 { X86::VXORPDZ128rrk, X86::VXORPDZ128rmk, 0 },
2926 { X86::VXORPSZ128rrk, X86::VXORPSZ128rmk, 0 },
2929 { X86::VPERMI2Brrkz, X86::VPERMI2Brmkz, 0 },
2930 { X86::VPERMI2Drrkz, X86::VPERMI2Drmkz, 0 },
2931 { X86::VPERMI2PSrrkz, X86::VPERMI2PSrmkz, 0 },
2932 { X86::VPERMI2PDrrkz, X86::VPERMI2PDrmkz, 0 },
2933 { X86::VPERMI2Qrrkz, X86::VPERMI2Qrmkz, 0 },
2934 { X86::VPERMI2Wrrkz, X86::VPERMI2Wrmkz, 0 },
2935 { X86::VPERMT2Brrkz, X86::VPERMT2Brmkz, 0 },
2936 { X86::VPERMT2Drrkz, X86::VPERMT2Drmkz, 0 },
2937 { X86::VPERMT2PSrrkz, X86::VPERMT2PSrmkz, 0 },
2938 { X86::VPERMT2PDrrkz, X86::VPERMT2PDrmkz, 0 },
2939 { X86::VPERMT2Qrrkz, X86::VPERMT2Qrmkz, 0 },
2940 { X86::VPERMT2Wrrkz, X86::VPERMT2Wrmkz, 0 },
2941 { X86::VPTERNLOGDZrrikz, X86::VPTERNLOGDZrmikz, 0 },
2942 { X86::VPTERNLOGQZrrikz, X86::VPTERNLOGQZrmikz, 0 },
2945 { X86::VPERMI2B256rrkz, X86::VPERMI2B256rmkz, 0 },
2946 { X86::VPERMI2D256rrkz, X86::VPERMI2D256rmkz, 0 },
2947 { X86::VPERMI2PD256rrkz, X86::VPERMI2PD256rmkz, 0 },
2948 { X86::VPERMI2PS256rrkz, X86::VPERMI2PS256rmkz, 0 },
2949 { X86::VPERMI2Q256rrkz, X86::VPERMI2Q256rmkz, 0 },
2950 { X86::VPERMI2W256rrkz, X86::VPERMI2W256rmkz, 0 },
2951 { X86::VPERMT2B256rrkz, X86::VPERMT2B256rmkz, 0 },
2952 { X86::VPERMT2D256rrkz, X86::VPERMT2D256rmkz, 0 },
2953 { X86::VPERMT2PD256rrkz, X86::VPERMT2PD256rmkz, 0 },
2954 { X86::VPERMT2PS256rrkz, X86::VPERMT2PS256rmkz, 0 },
2955 { X86::VPERMT2Q256rrkz, X86::VPERMT2Q256rmkz, 0 },
2956 { X86::VPERMT2W256rrkz, X86::VPERMT2W256rmkz, 0 },
2957 { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz, 0 },
2958 { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz, 0 },
2961 { X86::VPERMI2B128rrkz, X86::VPERMI2B128rmkz, 0 },
2962 { X86::VPERMI2D128rrkz, X86::VPERMI2D128rmkz, 0 },
2963 { X86::VPERMI2PD128rrkz, X86::VPERMI2PD128rmkz, 0 },
2964 { X86::VPERMI2PS128rrkz, X86::VPERMI2PS128rmkz, 0 },
2965 { X86::VPERMI2Q128rrkz, X86::VPERMI2Q128rmkz, 0 },
2966 { X86::VPERMI2W128rrkz, X86::VPERMI2W128rmkz, 0 },
2967 { X86::VPERMT2B128rrkz, X86::VPERMT2B128rmkz, 0 },
2968 { X86::VPERMT2D128rrkz, X86::VPERMT2D128rmkz, 0 },
2969 { X86::VPERMT2PD128rrkz, X86::VPERMT2PD128rmkz, 0 },
2970 { X86::VPERMT2PS128rrkz, X86::VPERMT2PS128rmkz, 0 },
2971 { X86::VPERMT2Q128rrkz, X86::VPERMT2Q128rmkz, 0 },
2972 { X86::VPERMT2W128rrkz, X86::VPERMT2W128rmkz, 0 },
2973 { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz, 0 },
2974 { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz, 0 },
2978 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2979 Entry.RegOp, Entry.MemOp,
2984 if (
I.getGroup()->isKMasked()) {
2986 if (
I.getGroup()->isIntrinsic()) {
2987 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2988 I.getRegOpcode(),
I.getMemOpcode(),
2991 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2992 I.getRegOpcode(),
I.getMemOpcode(),
3000 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
3001 MemOp2RegOpTableType &M2RTable,
3002 uint16_t RegOp, uint16_t MemOp, uint16_t
Flags) {
3004 assert(!R2MTable.count(RegOp) &&
"Duplicate entry!");
3005 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
3008 assert(!M2RTable.count(MemOp) &&
3009 "Duplicated entries in unfolding maps?");
3010 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
3016 unsigned &SrcReg,
unsigned &DstReg,
3017 unsigned &SubIdx)
const {
3020 case X86::MOVSX16rr8:
3021 case X86::MOVZX16rr8:
3022 case X86::MOVSX32rr8:
3023 case X86::MOVZX32rr8:
3024 case X86::MOVSX64rr8:
3029 case X86::MOVSX32rr16:
3030 case X86::MOVZX32rr16:
3031 case X86::MOVSX64rr16:
3032 case X86::MOVSX64rr32: {
3040 case X86::MOVSX16rr8:
3041 case X86::MOVZX16rr8:
3042 case X86::MOVSX32rr8:
3043 case X86::MOVZX32rr8:
3044 case X86::MOVSX64rr8:
3045 SubIdx = X86::sub_8bit;
3047 case X86::MOVSX32rr16:
3048 case X86::MOVZX32rr16:
3049 case X86::MOVSX64rr16:
3050 SubIdx = X86::sub_16bit;
3052 case X86::MOVSX64rr32:
3053 SubIdx = X86::sub_32bit;
3066 if (MI.
getOpcode() == getCallFrameSetupOpcode() ||
3067 MI.
getOpcode() == getCallFrameDestroyOpcode()) {
3074 if (MI.
getOpcode() == getCallFrameSetupOpcode())
3086 for (
auto E = MBB->
end();
I !=
E; ++
I) {
3087 if (
I->getOpcode() == getCallFrameDestroyOpcode() ||
3094 if (
I->getOpcode() != getCallFrameDestroyOpcode())
3097 return -(
I->getOperand(1).getImm());
3107 case X86::PUSH32rmm:
3108 case X86::PUSH32rmr:
3113 case X86::PUSH64rmm:
3114 case X86::PUSH64rmr:
3115 case X86::PUSH64i32:
3156 case X86::VMOVAPSrm:
3157 case X86::VMOVUPSrm:
3158 case X86::VMOVAPDrm:
3159 case X86::VMOVUPDrm:
3160 case X86::VMOVDQArm:
3161 case X86::VMOVDQUrm:
3162 case X86::VMOVUPSYrm:
3163 case X86::VMOVAPSYrm:
3164 case X86::VMOVUPDYrm:
3165 case X86::VMOVAPDYrm:
3166 case X86::VMOVDQUYrm:
3167 case X86::VMOVDQAYrm:
3168 case X86::MMX_MOVD64rm:
3169 case X86::MMX_MOVQ64rm:
3170 case X86::VMOVSSZrm:
3171 case X86::VMOVSDZrm:
3172 case X86::VMOVAPSZrm:
3173 case X86::VMOVAPSZ128rm:
3174 case X86::VMOVAPSZ256rm:
3175 case X86::VMOVAPSZ128rm_NOVLX:
3176 case X86::VMOVAPSZ256rm_NOVLX:
3177 case X86::VMOVUPSZrm:
3178 case X86::VMOVUPSZ128rm:
3179 case X86::VMOVUPSZ256rm:
3180 case X86::VMOVUPSZ128rm_NOVLX:
3181 case X86::VMOVUPSZ256rm_NOVLX:
3182 case X86::VMOVAPDZrm:
3183 case X86::VMOVAPDZ128rm:
3184 case X86::VMOVAPDZ256rm:
3185 case X86::VMOVUPDZrm:
3186 case X86::VMOVUPDZ128rm:
3187 case X86::VMOVUPDZ256rm:
3188 case X86::VMOVDQA32Zrm:
3189 case X86::VMOVDQA32Z128rm:
3190 case X86::VMOVDQA32Z256rm:
3191 case X86::VMOVDQU32Zrm:
3192 case X86::VMOVDQU32Z128rm:
3193 case X86::VMOVDQU32Z256rm:
3194 case X86::VMOVDQA64Zrm:
3195 case X86::VMOVDQA64Z128rm:
3196 case X86::VMOVDQA64Z256rm:
3197 case X86::VMOVDQU64Zrm:
3198 case X86::VMOVDQU64Z128rm:
3199 case X86::VMOVDQU64Z256rm:
3200 case X86::VMOVDQU8Zrm:
3201 case X86::VMOVDQU8Z128rm:
3202 case X86::VMOVDQU8Z256rm:
3203 case X86::VMOVDQU16Zrm:
3204 case X86::VMOVDQU16Z128rm:
3205 case X86::VMOVDQU16Z256rm:
3221 case X86::ST_FpP64m:
3232 case X86::VMOVAPSmr:
3233 case X86::VMOVUPSmr:
3234 case X86::VMOVAPDmr:
3235 case X86::VMOVUPDmr:
3236 case X86::VMOVDQAmr:
3237 case X86::VMOVDQUmr:
3238 case X86::VMOVUPSYmr:
3239 case X86::VMOVAPSYmr:
3240 case X86::VMOVUPDYmr:
3241 case X86::VMOVAPDYmr:
3242 case X86::VMOVDQUYmr:
3243 case X86::VMOVDQAYmr:
3244 case X86::VMOVSSZmr:
3245 case X86::VMOVSDZmr:
3246 case X86::VMOVUPSZmr:
3247 case X86::VMOVUPSZ128mr:
3248 case X86::VMOVUPSZ256mr:
3249 case X86::VMOVUPSZ128mr_NOVLX:
3250 case X86::VMOVUPSZ256mr_NOVLX:
3251 case X86::VMOVAPSZmr:
3252 case X86::VMOVAPSZ128mr:
3253 case X86::VMOVAPSZ256mr:
3254 case X86::VMOVAPSZ128mr_NOVLX:
3255 case X86::VMOVAPSZ256mr_NOVLX:
3256 case X86::VMOVUPDZmr:
3257 case X86::VMOVUPDZ128mr:
3258 case X86::VMOVUPDZ256mr:
3259 case X86::VMOVAPDZmr:
3260 case X86::VMOVAPDZ128mr:
3261 case X86::VMOVAPDZ256mr:
3262 case X86::VMOVDQA32Zmr:
3263 case X86::VMOVDQA32Z128mr:
3264 case X86::VMOVDQA32Z256mr:
3265 case X86::VMOVDQU32Zmr:
3266 case X86::VMOVDQU32Z128mr:
3267 case X86::VMOVDQU32Z256mr:
3268 case X86::VMOVDQA64Zmr:
3269 case X86::VMOVDQA64Z128mr:
3270 case X86::VMOVDQA64Z256mr:
3271 case X86::VMOVDQU64Zmr:
3272 case X86::VMOVDQU64Z128mr:
3273 case X86::VMOVDQU64Z256mr:
3274 case X86::VMOVDQU8Zmr:
3275 case X86::VMOVDQU8Z128mr:
3276 case X86::VMOVDQU8Z256mr:
3277 case X86::VMOVDQU16Zmr:
3278 case X86::VMOVDQU16Z128mr:
3279 case X86::VMOVDQU16Z256mr:
3280 case X86::MMX_MOVD64mr:
3281 case X86::MMX_MOVQ64mr:
3282 case X86::MMX_MOVNTQmr:
3293 int &FrameIndex)
const {
3301 int &FrameIndex)
const {
3308 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
3314 int &FrameIndex)
const {
3317 isFrameOperand(MI, 0, FrameIndex))
3323 int &FrameIndex)
const {
3330 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
3340 bool isPICBase =
false;
3344 if (DefMI->
getOpcode() != X86::MOVPC32r)
3346 assert(!isPICBase &&
"More than one PIC base?");
3357 case X86::MOV8rm_NOREX:
3372 case X86::VMOVAPSrm:
3373 case X86::VMOVUPSrm:
3374 case X86::VMOVAPDrm:
3375 case X86::VMOVUPDrm:
3376 case X86::VMOVDQArm:
3377 case X86::VMOVDQUrm:
3378 case X86::VMOVAPSYrm:
3379 case X86::VMOVUPSYrm:
3380 case X86::VMOVAPDYrm:
3381 case X86::VMOVUPDYrm:
3382 case X86::VMOVDQAYrm:
3383 case X86::VMOVDQUYrm:
3384 case X86::MMX_MOVD64rm:
3385 case X86::MMX_MOVQ64rm:
3387 case X86::VMOVSSZrm:
3388 case X86::VMOVSDZrm:
3389 case X86::VMOVAPDZ128rm:
3390 case X86::VMOVAPDZ256rm:
3391 case X86::VMOVAPDZrm:
3392 case X86::VMOVAPSZ128rm:
3393 case X86::VMOVAPSZ256rm:
3394 case X86::VMOVAPSZ128rm_NOVLX:
3395 case X86::VMOVAPSZ256rm_NOVLX:
3396 case X86::VMOVAPSZrm:
3397 case X86::VMOVDQA32Z128rm:
3398 case X86::VMOVDQA32Z256rm:
3399 case X86::VMOVDQA32Zrm:
3400 case X86::VMOVDQA64Z128rm:
3401 case X86::VMOVDQA64Z256rm:
3402 case X86::VMOVDQA64Zrm:
3403 case X86::VMOVDQU16Z128rm:
3404 case X86::VMOVDQU16Z256rm:
3405 case X86::VMOVDQU16Zrm:
3406 case X86::VMOVDQU32Z128rm:
3407 case X86::VMOVDQU32Z256rm:
3408 case X86::VMOVDQU32Zrm:
3409 case X86::VMOVDQU64Z128rm:
3410 case X86::VMOVDQU64Z256rm:
3411 case X86::VMOVDQU64Zrm:
3412 case X86::VMOVDQU8Z128rm:
3413 case X86::VMOVDQU8Z256rm:
3414 case X86::VMOVDQU8Zrm:
3415 case X86::VMOVUPDZ128rm:
3416 case X86::VMOVUPDZ256rm:
3417 case X86::VMOVUPDZrm:
3418 case X86::VMOVUPSZ128rm:
3419 case X86::VMOVUPSZ256rm:
3420 case X86::VMOVUPSZ128rm_NOVLX:
3421 case X86::VMOVUPSZ256rm_NOVLX:
3422 case X86::VMOVUPSZrm: {
3430 if (BaseReg == 0 || BaseReg == X86::RIP)
3476 for (
unsigned i = 0; Iter != E &&
i < 4; ++
i) {
3477 bool SeenDef =
false;
3478 for (
unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
3484 if (MO.
getReg() == X86::EFLAGS) {
3496 while (Iter != E && Iter->isDebugValue())
3504 if (S->isLiveIn(X86::EFLAGS))
3511 for (
unsigned i = 0; i < 4; ++
i) {
3519 while (Iter != B && Iter->isDebugValue())
3522 bool SawKill =
false;
3523 for (
unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
3531 if (MO.
isKill()) SawKill =
true;
3547 unsigned DestReg,
unsigned SubIdx,
3550 bool ClobbersEFLAGS =
false;
3552 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3553 ClobbersEFLAGS =
true;
3563 case X86::MOV32r0: Value = 0;
break;
3564 case X86::MOV32r1: Value = 1;
break;
3565 case X86::MOV32r_1: Value = -1;
break;
3571 BuildMI(MBB, I, DL,
get(X86::MOV32ri))
3597 unsigned ShiftAmtOperandIdx) {
3601 return Imm & ShiftCountMask;
3612 return ShAmt < 4 && ShAmt > 0;
3616 unsigned Opc,
bool AllowSP,
unsigned &NewSrc,
3617 bool &isKill,
bool &isUndef,
3623 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
3625 RC = Opc != X86::LEA32r ?
3626 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
3628 unsigned SrcReg = Src.
getReg();
3632 if (Opc != X86::LEA64_32r) {
3658 get(TargetOpcode::COPY))
3677 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
3688 unsigned Opc, leaInReg;
3690 Opc = X86::LEA64_32r;
3714 case X86::SHL16ri: {
3728 case X86::ADD16ri_DB:
3729 case X86::ADD16ri8_DB:
3733 case X86::ADD16rr_DB: {
3736 unsigned leaInReg2 = 0;
3741 addRegReg(MIB, leaInReg,
true, leaInReg,
false);
3753 addRegReg(MIB, leaInReg,
true, leaInReg2,
true);
3755 if (LV && isKill2 && InsMI2)
3808 bool DisableLEA16 =
true;
3813 default:
return nullptr;
3814 case X86::SHL64ri: {
3822 &X86::GR64_NOSPRegClass))
3834 case X86::SHL32ri: {
3839 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3842 bool isKill, isUndef;
3846 SrcReg, isKill, isUndef, ImplicitOp, LV))
3857 if (ImplicitOp.
getReg() != 0)
3863 case X86::SHL16ri: {
3869 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3883 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
3884 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3885 bool isKill, isUndef;
3889 SrcReg, isKill, isUndef, ImplicitOp, LV))
3897 if (ImplicitOp.
getReg() != 0)
3905 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3916 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
3917 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3919 bool isKill, isUndef;
3923 SrcReg, isKill, isUndef, ImplicitOp, LV))
3930 if (ImplicitOp.
getReg() != 0)
3939 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3948 case X86::ADD64rr_DB:
3950 case X86::ADD32rr_DB: {
3953 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3956 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3958 bool isKill, isUndef;
3962 SrcReg, isKill, isUndef, ImplicitOp, LV))
3966 bool isKill2, isUndef2;
3970 SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
3975 if (ImplicitOp.
getReg() != 0)
3977 if (ImplicitOp2.
getReg() != 0)
3980 NewMI =
addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3983 NewMI->getOperand(1).setIsUndef(isUndef);
3984 NewMI->getOperand(3).setIsUndef(isUndef2);
3991 case X86::ADD16rr_DB: {
3993 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4005 NewMI->getOperand(1).setIsUndef(isUndef);
4006 NewMI->getOperand(3).setIsUndef(isUndef2);
4012 case X86::ADD64ri32:
4014 case X86::ADD64ri32_DB:
4015 case X86::ADD64ri8_DB:
4024 case X86::ADD32ri_DB:
4025 case X86::ADD32ri8_DB: {
4027 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4029 bool isKill, isUndef;
4033 SrcReg, isKill, isUndef, ImplicitOp, LV))
4040 if (ImplicitOp.
getReg() != 0)
4048 case X86::ADD16ri_DB:
4049 case X86::ADD16ri8_DB:
4051 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4061 if (!NewMI)
return nullptr;
4082 unsigned SrcOpIdx2) {
4084 if (SrcOpIdx1 > SrcOpIdx2)
4087 unsigned Op1 = 1, Op2 = 2, Op3 = 3;
4113 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
4115 if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
4117 if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
4123 const MachineInstr &MI,
unsigned SrcOpIdx1,
unsigned SrcOpIdx2,
4129 if (SrcOpIdx1 > SrcOpIdx2)
4149 const unsigned Form132Index = 0;
4150 const unsigned Form213Index = 1;
4151 const unsigned Form231Index = 2;
4152 static const unsigned FormMapping[][3] = {
4157 { Form231Index, Form213Index, Form132Index },
4162 { Form132Index, Form231Index, Form213Index },
4167 { Form213Index, Form132Index, Form231Index }
4170 unsigned FMAForms[3];
4181 for (FormIndex = 0; FormIndex < 3; FormIndex++)
4182 if (Opc == FMAForms[FormIndex])
4186 FormIndex = FormMapping[Case][FormIndex];
4187 return FMAForms[FormIndex];
4191 unsigned SrcOpIdx2) {
4200 static const uint8_t SwapMasks[3][4] = {
4201 { 0x04, 0x10, 0x08, 0x20 },
4202 { 0x02, 0x10, 0x08, 0x40 },
4203 { 0x02, 0x04, 0x20, 0x40 },
4208 uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
4209 SwapMasks[Case][2] | SwapMasks[Case][3]);
4211 if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
4212 if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
4213 if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
4214 if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
4223 #define VPERM_CASES(Suffix) \
4224 case X86::VPERMI2##Suffix##128rr: case X86::VPERMT2##Suffix##128rr: \
4225 case X86::VPERMI2##Suffix##256rr: case X86::VPERMT2##Suffix##256rr: \
4226 case X86::VPERMI2##Suffix##rr: case X86::VPERMT2##Suffix##rr: \
4227 case X86::VPERMI2##Suffix##128rm: case X86::VPERMT2##Suffix##128rm: \
4228 case X86::VPERMI2##Suffix##256rm: case X86::VPERMT2##Suffix##256rm: \
4229 case X86::VPERMI2##Suffix##rm: case X86::VPERMT2##Suffix##rm: \
4230 case X86::VPERMI2##Suffix##128rrkz: case X86::VPERMT2##Suffix##128rrkz: \
4231 case X86::VPERMI2##Suffix##256rrkz: case X86::VPERMT2##Suffix##256rrkz: \
4232 case X86::VPERMI2##Suffix##rrkz: case X86::VPERMT2##Suffix##rrkz: \
4233 case X86::VPERMI2##Suffix##128rmkz: case X86::VPERMT2##Suffix##128rmkz: \
4234 case X86::VPERMI2##Suffix##256rmkz: case X86::VPERMT2##Suffix##256rmkz: \
4235 case X86::VPERMI2##Suffix##rmkz: case X86::VPERMT2##Suffix##rmkz:
4237 #define VPERM_CASES_BROADCAST(Suffix) \
4238 VPERM_CASES(Suffix) \
4239 case X86::VPERMI2##Suffix##128rmb: case X86::VPERMT2##Suffix##128rmb: \
4240 case X86::VPERMI2##Suffix##256rmb: case X86::VPERMT2##Suffix##256rmb: \
4241 case X86::VPERMI2##Suffix##rmb: case X86::VPERMT2##Suffix##rmb: \
4242 case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
4243 case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
4244 case X86::VPERMI2##Suffix##rmbkz: case X86::VPERMT2##Suffix##rmbkz:
4247 default:
return false;
4256 #undef VPERM_CASES_BROADCAST
4263 #define VPERM_CASES(Orig, New) \
4264 case X86::Orig##128rr: return X86::New##128rr; \
4265 case X86::Orig##128rrkz: return X86::New##128rrkz; \
4266 case X86::Orig##128rm: return X86::New##128rm; \
4267 case X86::Orig##128rmkz: return X86::New##128rmkz; \
4268 case X86::Orig##256rr: return X86::New##256rr; \
4269 case X86::Orig##256rrkz: return X86::New##256rrkz; \
4270 case X86::Orig##256rm: return X86::New##256rm; \
4271 case X86::Orig##256rmkz: return X86::New##256rmkz; \
4272 case X86::Orig##rr: return X86::New##rr; \
4273 case X86::Orig##rrkz: return X86::New##rrkz; \
4274 case X86::Orig##rm: return X86::New##rm; \
4275 case X86::Orig##rmkz: return X86::New##rmkz;
4277 #define VPERM_CASES_BROADCAST(Orig, New) \
4278 VPERM_CASES(Orig, New) \
4279 case X86::Orig##128rmb: return X86::New##128rmb; \
4280 case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
4281 case X86::Orig##256rmb: return X86::New##256rmb; \
4282 case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
4283 case X86::Orig##rmb: return X86::New##rmb; \
4284 case X86::Orig##rmbkz: return X86::New##rmbkz;
4302 #undef VPERM_CASES_BROADCAST
4308 unsigned OpIdx2)
const {
4316 case X86::SHRD16rri8:
4317 case X86::SHLD16rri8:
4318 case X86::SHRD32rri8:
4319 case X86::SHLD32rri8:
4320 case X86::SHRD64rri8:
4321 case X86::SHLD64rri8:{
4326 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8;
break;
4327 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8;
break;
4328 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8;
break;
4329 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8;
break;
4330 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8;
break;
4331 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8;
break;
4334 auto &WorkingMI = cloneIfNew(MI);
4335 WorkingMI.setDesc(
get(Opc));
4336 WorkingMI.getOperand(3).setImm(Size - Amt);
4340 case X86::BLENDPDrri:
4341 case X86::BLENDPSrri:
4342 case X86::PBLENDWrri:
4343 case X86::VBLENDPDrri:
4344 case X86::VBLENDPSrri:
4345 case X86::VBLENDPDYrri:
4346 case X86::VBLENDPSYrri:
4347 case X86::VPBLENDDrri:
4348 case X86::VPBLENDWrri:
4349 case X86::VPBLENDDYrri:
4350 case X86::VPBLENDWYrri:{
4354 case X86::BLENDPDrri: Mask = 0x03;
break;
4355 case X86::BLENDPSrri: Mask = 0x0F;
break;
4356 case X86::PBLENDWrri: Mask = 0xFF;
break;
4357 case X86::VBLENDPDrri: Mask = 0x03;
break;
4358 case X86::VBLENDPSrri: Mask = 0x0F;
break;
4359 case X86::VBLENDPDYrri: Mask = 0x0F;
break;
4360 case X86::VBLENDPSYrri: Mask = 0xFF;
break;
4361 case X86::VPBLENDDrri: Mask = 0x0F;
break;
4362 case X86::VPBLENDWrri: Mask = 0xFF;
break;
4363 case X86::VPBLENDDYrri: Mask = 0xFF;
break;
4364 case X86::VPBLENDWYrri: Mask = 0xFF;
break;
4368 auto &WorkingMI = cloneIfNew(MI);
4369 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
4376 case X86::VMOVSSrr:{
4384 case X86::MOVSDrr: Opc = X86::BLENDPDrri; Mask = 0x02;
break;
4385 case X86::MOVSSrr: Opc = X86::BLENDPSrri; Mask = 0x0E;
break;
4386 case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02;
break;
4387 case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E;
break;
4394 unsigned VR128 =
MRI.createVirtualRegister(VR128RC);
4399 auto &WorkingMI = cloneIfNew(MI);
4400 WorkingMI.setDesc(
get(Opc));
4401 WorkingMI.getOperand(2).setReg(VR128);
4406 case X86::PCLMULQDQrr:
4407 case X86::VPCLMULQDQrr:{
4411 unsigned Src1Hi = Imm & 0x01;
4412 unsigned Src2Hi = Imm & 0x10;
4413 auto &WorkingMI = cloneIfNew(MI);
4414 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
4424 case X86::VCMPPDrri:
4425 case X86::VCMPPSrri:
4426 case X86::VCMPPDYrri:
4427 case X86::VCMPPSYrri:
4428 case X86::VCMPSDZrr:
4429 case X86::VCMPSSZrr:
4430 case X86::VCMPPDZrri:
4431 case X86::VCMPPSZrri:
4432 case X86::VCMPPDZ128rri:
4433 case X86::VCMPPSZ128rri:
4434 case X86::VCMPPDZ256rri:
4435 case X86::VCMPPSZ256rri: {
4449 case X86::VPCMPBZ128rri:
case X86::VPCMPUBZ128rri:
4450 case X86::VPCMPBZ256rri:
case X86::VPCMPUBZ256rri:
4451 case X86::VPCMPBZrri:
case X86::VPCMPUBZrri:
4452 case X86::VPCMPDZ128rri:
case X86::VPCMPUDZ128rri:
4453 case X86::VPCMPDZ256rri:
case X86::VPCMPUDZ256rri:
4454 case X86::VPCMPDZrri:
case X86::VPCMPUDZrri:
4455 case X86::VPCMPQZ128rri:
case X86::VPCMPUQZ128rri:
4456 case X86::VPCMPQZ256rri:
case X86::VPCMPUQZ256rri:
4457 case X86::VPCMPQZrri:
case X86::VPCMPUQZrri:
4458 case X86::VPCMPWZ128rri:
case X86::VPCMPUWZ128rri:
4459 case X86::VPCMPWZ256rri:
case X86::VPCMPUWZ256rri:
4460 case X86::VPCMPWZrri:
case X86::VPCMPUWZrri: {
4465 case 0x01: Imm = 0x06;
break;
4466 case 0x02: Imm = 0x05;
break;
4467 case 0x05: Imm = 0x02;
break;
4468 case 0x06: Imm = 0x01;
break;
4475 auto &WorkingMI = cloneIfNew(MI);
4476 WorkingMI.getOperand(3).setImm(Imm);
4480 case X86::VPCOMBri:
case X86::VPCOMUBri:
4481 case X86::VPCOMDri:
case X86::VPCOMUDri:
4482 case X86::VPCOMQri:
case X86::VPCOMUQri:
4483 case X86::VPCOMWri:
case X86::VPCOMUWri: {
4488 case 0x00: Imm = 0x02;
break;
4489 case 0x01: Imm = 0x03;
break;
4490 case 0x02: Imm = 0x00;
break;
4491 case 0x03: Imm = 0x01;
break;
4498 auto &WorkingMI = cloneIfNew(MI);
4499 WorkingMI.getOperand(3).setImm(Imm);
4503 case X86::VPERM2F128rr:
4504 case X86::VPERM2I128rr: {
4509 auto &WorkingMI = cloneIfNew(MI);
4510 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
4514 case X86::MOVHLPSrr:
4515 case X86::UNPCKHPDrr: {
4522 case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr;
break;
4523 case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr;
break;
4525 auto &WorkingMI = cloneIfNew(MI);
4526 WorkingMI.setDesc(
get(Opc));
4530 case X86::CMOVB16rr:
case X86::CMOVB32rr:
case X86::CMOVB64rr:
4531 case X86::CMOVAE16rr:
case X86::CMOVAE32rr:
case X86::CMOVAE64rr:
4532 case X86::CMOVE16rr:
case X86::CMOVE32rr:
case X86::CMOVE64rr:
4533 case X86::CMOVNE16rr:
case X86::CMOVNE32rr:
case X86::CMOVNE64rr:
4534 case X86::CMOVBE16rr:
case X86::CMOVBE32rr:
case X86::CMOVBE64rr:
4535 case X86::CMOVA16rr:
case X86::CMOVA32rr:
case X86::CMOVA64rr:
4536 case X86::CMOVL16rr:
case X86::CMOVL32rr:
case X86::CMOVL64rr:
4537 case X86::CMOVGE16rr:
case X86::CMOVGE32rr:
case X86::CMOVGE64rr:
4538 case X86::CMOVLE16rr:
case X86::CMOVLE32rr:
case X86::CMOVLE64rr:
4539 case X86::CMOVG16rr:
case X86::CMOVG32rr:
case X86::CMOVG64rr:
4540 case X86::CMOVS16rr:
case X86::CMOVS32rr:
case X86::CMOVS64rr:
4541 case X86::CMOVNS16rr:
case X86::CMOVNS32rr:
case X86::CMOVNS64rr:
4542 case X86::CMOVP16rr:
case X86::CMOVP32rr:
case X86::CMOVP64rr:
4543 case X86::CMOVNP16rr:
case X86::CMOVNP32rr:
case X86::CMOVNP64rr:
4544 case X86::CMOVO16rr:
case X86::CMOVO32rr:
case X86::CMOVO64rr:
4545 case X86::CMOVNO16rr:
case X86::CMOVNO32rr:
case X86::CMOVNO64rr: {
4549 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr;
break;
4550 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr;
break;
4551 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr;
break;
4552 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr;
break;
4553 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr;
break;
4554 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr;
break;
4555 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr;
break;
4556 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr;
break;
4557 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr;
break;
4558 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr;
break;
4559 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr;
break;
4560 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr;
break;
4561 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr;
break;
4562 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr;
break;
4563 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr;
break;
4564 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr;
break;
4565 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr;
break;
4566 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr;
break;
4567 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr;
break;
4568 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr;
break;
4569 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr;
break;
4570 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr;
break;
4571 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr;
break;
4572 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr;
break;
4573 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr;
break;
4574 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr;
break;
4575 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr;
break;
4576 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr;
break;
4577 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr;
break;
4578 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr;
break;
4579 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr;
break;
4580 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr;
break;
4581 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr;
break;
4582 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr;
break;
4583 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr;
break;
4584 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr;
break;
4585 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr;
break;
4586 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr;
break;
4587 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr;
break;
4588 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr;
break;
4589 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr;
break;
4590 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr;
break;
4591 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr;
break;
4592 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr;
break;
4593 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr;
break;
4594 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr;
break;
4595 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr;
break;
4596 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr;
break;
4598 auto &WorkingMI = cloneIfNew(MI);
4599 WorkingMI.setDesc(
get(Opc));
4603 case X86::VPTERNLOGDZrri:
case X86::VPTERNLOGDZrmi:
4604 case X86::VPTERNLOGDZ128rri:
case X86::VPTERNLOGDZ128rmi:
4605 case X86::VPTERNLOGDZ256rri:
case X86::VPTERNLOGDZ256rmi:
4606 case X86::VPTERNLOGQZrri:
case X86::VPTERNLOGQZrmi:
4607 case X86::VPTERNLOGQZ128rri:
case X86::VPTERNLOGQZ128rmi:
4608 case X86::VPTERNLOGQZ256rri:
case X86::VPTERNLOGQZ256rmi:
4609 case X86::VPTERNLOGDZrrik:
case X86::VPTERNLOGDZrmik:
4610 case X86::VPTERNLOGDZ128rrik:
case X86::VPTERNLOGDZ128rmik:
4611 case X86::VPTERNLOGDZ256rrik:
case X86::VPTERNLOGDZ256rmik:
4612 case X86::VPTERNLOGQZrrik:
case X86::VPTERNLOGQZrmik:
4613 case X86::VPTERNLOGQZ128rrik:
case X86::VPTERNLOGQZ128rmik:
4614 case X86::VPTERNLOGQZ256rrik:
case X86::VPTERNLOGQZ256rmik:
4615 case X86::VPTERNLOGDZrrikz:
case X86::VPTERNLOGDZrmikz:
4616 case X86::VPTERNLOGDZ128rrikz:
case X86::VPTERNLOGDZ128rmikz:
4617 case X86::VPTERNLOGDZ256rrikz:
case X86::VPTERNLOGDZ256rmikz:
4618 case X86::VPTERNLOGQZrrikz:
case X86::VPTERNLOGQZrmikz:
4619 case X86::VPTERNLOGQZ128rrikz:
case X86::VPTERNLOGQZ128rmikz:
4620 case X86::VPTERNLOGQZ256rrikz:
case X86::VPTERNLOGQZ256rmikz: {
4621 auto &WorkingMI = cloneIfNew(MI);
4630 auto &WorkingMI = cloneIfNew(MI);
4631 WorkingMI.setDesc(
get(Opc));
4643 auto &WorkingMI = cloneIfNew(MI);
4644 WorkingMI.setDesc(
get(Opc));
4655 const MachineInstr &MI,
unsigned &SrcOpIdx1,
unsigned &SrcOpIdx2,
4658 if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
4666 bool X86InstrInfo::findThreeSrcCommutedOpIndices(
const MachineInstr &MI,
4667 unsigned &SrcOpIdx1,
4668 unsigned &SrcOpIdx2)
const {
4671 unsigned FirstCommutableVecOp = 1;
4672 unsigned LastCommutableVecOp = 3;
4673 unsigned KMaskOp = 0;
4681 FirstCommutableVecOp = 3;
4683 LastCommutableVecOp++;
4686 if (
isMem(MI, LastCommutableVecOp))
4687 LastCommutableVecOp--;
4692 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
4693 (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
4694 SrcOpIdx1 == KMaskOp))
4696 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
4697 (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
4698 SrcOpIdx2 == KMaskOp))
4703 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
4704 SrcOpIdx2 == CommuteAnyOperandIndex) {
4705 unsigned CommutableOpIdx1 = SrcOpIdx1;
4706 unsigned CommutableOpIdx2 = SrcOpIdx2;
4710 if (SrcOpIdx1 == SrcOpIdx2)
4713 CommutableOpIdx2 = LastCommutableVecOp;
4714 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
4716 CommutableOpIdx2 = SrcOpIdx1;
4721 for (CommutableOpIdx1 = LastCommutableVecOp;
4722 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
4724 if (CommutableOpIdx1 == KMaskOp)
4735 if (CommutableOpIdx1 < FirstCommutableVecOp)
4740 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
4741 CommutableOpIdx1, CommutableOpIdx2))
4749 unsigned &SrcOpIdx2)
const {
4761 case X86::VCMPPDrri:
4762 case X86::VCMPPSrri:
4763 case X86::VCMPPDYrri:
4764 case X86::VCMPPSYrri:
4765 case X86::VCMPSDZrr:
4766 case X86::VCMPSSZrr:
4767 case X86::VCMPPDZrri:
4768 case X86::VCMPPSZrri:
4769 case X86::VCMPPDZ128rri:
4770 case X86::VCMPPSZ128rri:
4771 case X86::VCMPPDZ256rri:
4772 case X86::VCMPPSZ256rri: {
4783 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
4790 case X86::VMOVSSrr: {
4795 case X86::VPTERNLOGDZrri:
case X86::VPTERNLOGDZrmi:
4796 case X86::VPTERNLOGDZ128rri:
case X86::VPTERNLOGDZ128rmi:
4797 case X86::VPTERNLOGDZ256rri:
case X86::VPTERNLOGDZ256rmi:
4798 case X86::VPTERNLOGQZrri:
case X86::VPTERNLOGQZrmi:
4799 case X86::VPTERNLOGQZ128rri:
case X86::VPTERNLOGQZ128rmi:
4800 case X86::VPTERNLOGQZ256rri:
case X86::VPTERNLOGQZ256rmi:
4801 case X86::VPTERNLOGDZrrik:
case X86::VPTERNLOGDZrmik:
4802 case X86::VPTERNLOGDZ128rrik:
case X86::VPTERNLOGDZ128rmik:
4803 case X86::VPTERNLOGDZ256rrik:
case X86::VPTERNLOGDZ256rmik:
4804 case X86::VPTERNLOGQZrrik:
case X86::VPTERNLOGQZrmik:
4805 case X86::VPTERNLOGQZ128rrik:
case X86::VPTERNLOGQZ128rmik:
4806 case X86::VPTERNLOGQZ256rrik:
case X86::VPTERNLOGQZ256rmik:
4807 case X86::VPTERNLOGDZrrikz:
case X86::VPTERNLOGDZrmikz:
4808 case X86::VPTERNLOGDZ128rrikz:
case X86::VPTERNLOGDZ128rmikz:
4809 case X86::VPTERNLOGDZ256rrikz:
case X86::VPTERNLOGDZ256rmikz:
4810 case X86::VPTERNLOGQZrrikz:
case X86::VPTERNLOGQZrmikz:
4811 case X86::VPTERNLOGQZ128rrikz:
case X86::VPTERNLOGQZ128rmikz:
4812 case X86::VPTERNLOGQZ256rrikz:
case X86::VPTERNLOGQZ256rmikz:
4813 return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4824 unsigned CommutableOpIdx1 = Desc.
getNumDefs() + 1;
4825 unsigned CommutableOpIdx2 = Desc.
getNumDefs() + 2;
4843 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
4844 CommutableOpIdx1, CommutableOpIdx2))
4885 case X86::SETAr:
case X86::SETAm:
return X86::COND_A;
4886 case X86::SETAEr:
case X86::SETAEm:
return X86::COND_AE;
4887 case X86::SETBr:
case X86::SETBm:
return X86::COND_B;
4888 case X86::SETBEr:
case X86::SETBEm:
return X86::COND_BE;
4889 case X86::SETEr:
case X86::SETEm:
return X86::COND_E;
4890 case X86::SETGr:
case X86::SETGm:
return X86::COND_G;
4891 case X86::SETGEr:
case X86::SETGEm:
return X86::COND_GE;
4892 case X86::SETLr:
case X86::SETLm:
return X86::COND_L;
4893 case X86::SETLEr:
case X86::SETLEm:
return X86::COND_LE;
4894 case X86::SETNEr:
case X86::SETNEm:
return X86::COND_NE;
4895 case X86::SETNOr:
case X86::SETNOm:
return X86::COND_NO;
4896 case X86::SETNPr:
case X86::SETNPm:
return X86::COND_NP;
4897 case X86::SETNSr:
case X86::SETNSm:
return X86::COND_NS;
4898 case X86::SETOr:
case X86::SETOm:
return X86::COND_O;
4899 case X86::SETPr:
case X86::SETPm:
return X86::COND_P;
4900 case X86::SETSr:
case X86::SETSm:
return X86::COND_S;
4908 case X86::CMOVA16rm:
case X86::CMOVA16rr:
case X86::CMOVA32rm:
4909 case X86::CMOVA32rr:
case X86::CMOVA64rm:
case X86::CMOVA64rr:
4911 case X86::CMOVAE16rm:
case X86::CMOVAE16rr:
case X86::CMOVAE32rm:
4912 case X86::CMOVAE32rr:
case X86::CMOVAE64rm:
case X86::CMOVAE64rr:
4914 case X86::CMOVB16rm:
case X86::CMOVB16rr:
case X86::CMOVB32rm:
4915 case X86::CMOVB32rr:
case X86::CMOVB64rm:
case X86::CMOVB64rr:
4917 case X86::CMOVBE16rm:
case X86::CMOVBE16rr:
case X86::CMOVBE32rm:
4918 case X86::CMOVBE32rr:
case X86::CMOVBE64rm:
case X86::CMOVBE64rr:
4920 case X86::CMOVE16rm:
case X86::CMOVE16rr:
case X86::CMOVE32rm:
4921 case X86::CMOVE32rr:
case X86::CMOVE64rm:
case X86::CMOVE64rr:
4923 case X86::CMOVG16rm:
case X86::CMOVG16rr:
case X86::CMOVG32rm:
4924 case X86::CMOVG32rr:
case X86::CMOVG64rm:
case X86::CMOVG64rr:
4926 case X86::CMOVGE16rm:
case X86::CMOVGE16rr:
case X86::CMOVGE32rm:
4927 case X86::CMOVGE32rr:
case X86::CMOVGE64rm:
case X86::CMOVGE64rr:
4929 case X86::CMOVL16rm:
case X86::CMOVL16rr:
case X86::CMOVL32rm:
4930 case X86::CMOVL32rr:
case X86::CMOVL64rm:
case X86::CMOVL64rr:
4932 case X86::CMOVLE16rm:
case X86::CMOVLE16rr:
case X86::CMOVLE32rm:
4933 case X86::CMOVLE32rr:
case X86::CMOVLE64rm:
case X86::CMOVLE64rr:
4935 case X86::CMOVNE16rm:
case X86::CMOVNE16rr:
case X86::CMOVNE32rm:
4936 case X86::CMOVNE32rr:
case X86::CMOVNE64rm:
case X86::CMOVNE64rr:
4938 case X86::CMOVNO16rm:
case X86::CMOVNO16rr:
case X86::CMOVNO32rm:
4939 case X86::CMOVNO32rr:
case X86::CMOVNO64rm:
case X86::CMOVNO64rr:
4941 case X86::CMOVNP16rm:
case X86::CMOVNP16rr:
case X86::CMOVNP32rm:
4942 case X86::CMOVNP32rr:
case X86::CMOVNP64rm:
case X86::CMOVNP64rr:
4944 case X86::CMOVNS16rm:
case X86::CMOVNS16rr:
case X86::CMOVNS32rm:
4945 case X86::CMOVNS32rr:
case X86::CMOVNS64rm:
case X86::CMOVNS64rr:
4947 case X86::CMOVO16rm:
case X86::CMOVO16rr:
case X86::CMOVO32rm:
4948 case X86::CMOVO32rr:
case X86::CMOVO64rm:
case X86::CMOVO64rr:
4950 case X86::CMOVP16rm:
case X86::CMOVP16rr:
case X86::CMOVP32rm:
4951 case X86::CMOVP32rr:
case X86::CMOVP64rm:
case X86::CMOVP64rr:
4953 case X86::CMOVS16rm:
case X86::CMOVS16rr:
case X86::CMOVS32rm:
4954 case X86::CMOVS32rr:
case X86::CMOVS64rm:
case X86::CMOVS64rr:
5028 static const uint16_t Opc[16][2] = {
5029 { X86::SETAr, X86::SETAm },
5030 { X86::SETAEr, X86::SETAEm },
5031 { X86::SETBr, X86::SETBm },
5032 { X86::SETBEr, X86::SETBEm },
5033 { X86::SETEr, X86::SETEm },
5034 { X86::SETGr, X86::SETGm },
5035 { X86::SETGEr, X86::SETGEm },
5036 { X86::SETLr, X86::SETLm },
5037 { X86::SETLEr, X86::SETLEm },
5038 { X86::SETNEr, X86::SETNEm },
5039 { X86::SETNOr, X86::SETNOm },
5040 { X86::SETNPr, X86::SETNPm },
5041 { X86::SETNSr, X86::SETNSm },
5042 { X86::SETOr, X86::SETOm },
5043 { X86::SETPr, X86::SETPm },
5044 { X86::SETSr, X86::SETSm }
5048 return Opc[CC][HasMemoryOperand ? 1 : 0];
5054 bool HasMemoryOperand) {
5055 static const uint16_t Opc[32][3] = {
5056 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
5057 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
5058 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
5059 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
5060 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
5061 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
5062 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
5063 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
5064 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
5065 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
5066 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
5067 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
5068 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
5069 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
5070 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
5071 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
5072 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
5073 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
5074 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
5075 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
5076 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
5077 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
5078 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
5079 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
5080 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
5081 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
5082 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
5083 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
5084 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
5085 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
5086 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
5087 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
5090 assert(CC < 16 &&
"Can only handle standard cond codes");
5091 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
5094 case 2:
return Opc[Idx][0];
5095 case 4:
return Opc[Idx][1];
5096 case 8:
return Opc[Idx][2];
5122 if ((*SI)->isEHPad() || (*
SI == TBB && FallthroughBB))
5125 if (FallthroughBB && FallthroughBB != TBB)
5127 FallthroughBB = *
SI;
5129 return FallthroughBB;
5132 bool X86InstrInfo::AnalyzeBranchImpl(
5141 while (I != MBB.
begin()) {
5143 if (I->isDebugValue())
5157 if (I->getOpcode() == X86::JMP_1) {
5161 TBB = I->getOperand(0).getMBB();
5166 while (std::next(I) != MBB.
end())
5167 std::next(I)->eraseFromParent();
5175 I->eraseFromParent();
5177 UnCondBrIter = MBB.
end();
5182 TBB = I->getOperand(0).getMBB();
5194 if (AllowModify && UnCondBrIter != MBB.
end() &&
5218 .
addMBB(UnCondBrIter->getOperand(0).getMBB());
5222 OldInst->eraseFromParent();
5223 UnCondBrIter->eraseFromParent();
5226 UnCondBrIter = MBB.
end();
5232 TBB = I->getOperand(0).getMBB();
5246 auto NewTBB = I->getOperand(0).getMBB();
5247 if (OldBranchCode == BranchCode && TBB == NewTBB)
5253 if (TBB == NewTBB &&
5286 Cond[0].setImm(BranchCode);
5297 bool AllowModify)
const {
5299 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
5303 MachineBranchPredicate &MBP,
5304 bool AllowModify)
const {
5305 using namespace std::placeholders;
5309 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
5313 if (Cond.
size() != 1)
5316 assert(MBP.TrueDest &&
"expected!");
5324 bool SingleUseCondition =
true;
5326 for (
auto I = std::next(MBB.
rbegin()),
E = MBB.
rend(); I !=
E; ++
I) {
5327 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
5332 if (I->readsRegister(X86::EFLAGS, TRI))
5333 SingleUseCondition =
false;
5339 if (SingleUseCondition) {
5341 if (Succ->isLiveIn(X86::EFLAGS))
5342 SingleUseCondition =
false;
5345 MBP.ConditionDef = ConditionDef;
5346 MBP.SingleUseCondition = SingleUseCondition;
5353 const unsigned TestOpcode =
5354 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
5356 if (ConditionDef->getOpcode() == TestOpcode &&
5357 ConditionDef->getNumOperands() == 3 &&
5358 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
5360 MBP.LHS = ConditionDef->getOperand(0);
5372 int *BytesRemoved)
const {
5373 assert(!BytesRemoved &&
"code size not handled");
5378 while (I != MBB.
begin()) {
5380 if (I->isDebugValue())
5382 if (I->getOpcode() != X86::JMP_1 &&
5386 I->eraseFromParent();
5399 int *BytesAdded)
const {
5401 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
5403 "X86 branch conditions have one component!");
5404 assert(!BytesAdded &&
"code size not handled");
5408 assert(!FBB &&
"Unconditional branch with multiple successors!");
5414 bool FallThru = FBB ==
nullptr;
5429 if (FBB ==
nullptr) {
5431 assert(FBB &&
"MBB cannot be the last block in function when the false "
5432 "body is a fall-through.");
5457 unsigned TrueReg,
unsigned FalseReg,
5458 int &CondCycles,
int &TrueCycles,
int &FalseCycles)
const {
5462 if (Cond.
size() != 1)
5476 if (X86::GR16RegClass.hasSubClassEq(RC) ||
5477 X86::GR32RegClass.hasSubClassEq(RC) ||
5478 X86::GR64RegClass.hasSubClassEq(RC)) {
5493 const DebugLoc &DL,
unsigned DstReg,
5495 unsigned FalseReg)
const {
5497 assert(Cond.
size() == 1 &&
"Invalid Cond array");
5506 return X86::GR8_ABCD_HRegClass.contains(Reg);
5512 bool HasAVX = Subtarget.
hasAVX();
5521 if (X86::VK16RegClass.
contains(SrcReg)) {
5522 if (X86::GR64RegClass.
contains(DestReg)) {
5524 return X86::KMOVQrk;
5526 if (X86::GR32RegClass.
contains(DestReg))
5527 return Subtarget.
hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
5528 if (X86::GR16RegClass.
contains(DestReg)) {
5530 return X86::KMOVWrk;
5532 if (X86::GR8RegClass.
contains(DestReg)) {
5534 return Subtarget.
hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
5544 if (X86::VK16RegClass.
contains(DestReg)) {
5545 if (X86::GR64RegClass.
contains(SrcReg)) {
5547 return X86::KMOVQkr;
5549 if (X86::GR32RegClass.
contains(SrcReg))
5550 return Subtarget.
hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
5551 if (X86::GR16RegClass.
contains(SrcReg)) {
5553 return X86::KMOVWkr;
5555 if (X86::GR8RegClass.
contains(SrcReg)) {
5557 return Subtarget.
hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
5567 if (X86::GR64RegClass.
contains(DestReg)) {
5568 if (X86::VR128XRegClass.
contains(SrcReg))
5570 return HasAVX512 ? X86::VMOVPQIto64Zrr :
5571 HasAVX ? X86::VMOVPQIto64rr :
5573 if (X86::VR64RegClass.
contains(SrcReg))
5575 return X86::MMX_MOVD64from64rr;
5576 }
else if (X86::GR64RegClass.
contains(SrcReg)) {
5578 if (X86::VR128XRegClass.
contains(DestReg))
5579 return HasAVX512 ? X86::VMOV64toPQIZrr :
5580 HasAVX ? X86::VMOV64toPQIrr :
5583 if (X86::VR64RegClass.
contains(DestReg))
5584 return X86::MMX_MOVD64to64rr;
5590 if (X86::GR32RegClass.
contains(DestReg) &&
5591 X86::FR32XRegClass.
contains(SrcReg))
5593 return HasAVX512 ? X86::VMOVSS2DIZrr :
5594 HasAVX ? X86::VMOVSS2DIrr :
5597 if (X86::FR32XRegClass.
contains(DestReg) &&
5598 X86::GR32RegClass.
contains(SrcReg))
5600 return HasAVX512 ? X86::VMOVDI2SSZrr :
5601 HasAVX ? X86::VMOVDI2SSrr :
5608 const DebugLoc &DL,
unsigned DestReg,
5609 unsigned SrcReg,
bool KillSrc)
const {
5611 bool HasAVX = Subtarget.
hasAVX();
5612 bool HasVLX = Subtarget.
hasVLX();
5614 if (X86::GR64RegClass.
contains(DestReg, SrcReg))
5616 else if (X86::GR32RegClass.
contains(DestReg, SrcReg))
5618 else if (X86::GR16RegClass.
contains(DestReg, SrcReg))
5620 else if (X86::GR8RegClass.
contains(DestReg, SrcReg)) {
5625 Opc = X86::MOV8rr_NOREX;
5628 "8-bit H register can not be copied outside GR8_NOREX");
5632 else if (X86::VR64RegClass.
contains(DestReg, SrcReg))
5633 Opc = X86::MMX_MOVQ64rr;
5634 else if (X86::VR128XRegClass.
contains(DestReg, SrcReg)) {
5636 Opc = X86::VMOVAPSZ128rr;
5637 else if (X86::VR128RegClass.
contains(DestReg, SrcReg))
5638 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
5642 Opc = X86::VMOVAPSZrr;
5645 &X86::VR512RegClass);
5647 &X86::VR512RegClass);
5649 }
else if (X86::VR256XRegClass.
contains(DestReg, SrcReg)) {
5651 Opc = X86::VMOVAPSZ256rr;
5652 else if (X86::VR256RegClass.
contains(DestReg, SrcReg))
5653 Opc = X86::VMOVAPSYrr;
5657 Opc = X86::VMOVAPSZrr;
5660 &X86::VR512RegClass);
5662 &X86::VR512RegClass);
5664 }
else if (X86::VR512RegClass.
contains(DestReg, SrcReg))
5665 Opc = X86::VMOVAPSZrr;
5667 else if (X86::VK16RegClass.
contains(DestReg, SrcReg))
5668 Opc = Subtarget.
hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
5673 BuildMI(MBB, MI, DL,
get(Opc), DestReg)
5678 bool FromEFLAGS = SrcReg == X86::EFLAGS;
5679 bool ToEFLAGS = DestReg == X86::EFLAGS;
5680 int Reg = FromEFLAGS ? DestReg : SrcReg;
5681 bool is32 = X86::GR32RegClass.contains(Reg);
5682 bool is64 = X86::GR64RegClass.contains(Reg);
5684 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
5685 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
5686 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
5687 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
5688 int Pop = is64 ? X86::POP64r : X86::POP32r;
5689 int PopF = is64 ? X86::POPF64 : X86::POPF32;
5690 int AX = is64 ? X86::RAX : X86::EAX;
5694 "Not having LAHF/SAHF only happens on 64-bit.");
5699 BuildMI(MBB, MI, DL,
get(PushF));
5700 BuildMI(MBB, MI, DL,
get(Pop), DestReg);
5703 BuildMI(MBB, MI, DL,
get(Push))
5705 BuildMI(MBB, MI, DL,
get(PopF));
5760 BuildMI(MBB, MI, DL,
get(X86::SETOr), X86::AL);
5761 BuildMI(MBB, MI, DL,
get(X86::LAHF));
5766 BuildMI(MBB, MI, DL,
get(X86::ADD8ri), X86::AL)
5772 BuildMI(MBB, MI, DL,
get(Pop), AX);
5776 DEBUG(
dbgs() <<
"Cannot copy " << RI.getName(SrcReg)
5777 <<
" to " << RI.getName(DestReg) <<
'\n');
5783 bool isStackAligned,
5786 bool HasAVX = STI.
hasAVX();
5788 bool HasVLX = STI.
hasVLX();
5794 assert(X86::GR8RegClass.hasSubClassEq(RC) &&
"Unknown 1-byte regclass");
5798 if (
isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
5799 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
5800 return load ? X86::MOV8rm : X86::MOV8mr;
5802 if (X86::VK16RegClass.hasSubClassEq(RC))
5803 return load ? X86::KMOVWkm : X86::KMOVWmk;
5804 assert(X86::GR16RegClass.hasSubClassEq(RC) &&
"Unknown 2-byte regclass");
5805 return load ? X86::MOV16rm : X86::MOV16mr;
5807 if (X86::GR32RegClass.hasSubClassEq(RC))
5808 return load ? X86::MOV32rm : X86::MOV32mr;
5809 if (X86::FR32XRegClass.hasSubClassEq(RC))
5811 (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
5812 (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
5813 if (X86::RFP32RegClass.hasSubClassEq(RC))
5814 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
5815 if (X86::VK32RegClass.hasSubClassEq(RC))
5816 return load ? X86::KMOVDkm : X86::KMOVDmk;
5819 if (X86::GR64RegClass.hasSubClassEq(RC))
5820 return load ? X86::MOV64rm : X86::MOV64mr;
5821 if (X86::FR64XRegClass.hasSubClassEq(RC))
5823 (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
5824 (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
5825 if (X86::VR64RegClass.hasSubClassEq(RC))
5826 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
5827 if (X86::RFP64RegClass.hasSubClassEq(RC))
5828 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
5829 if (X86::VK64RegClass.hasSubClassEq(RC))
5830 return load ? X86::KMOVQkm : X86::KMOVQmk;
5833 assert(X86::RFP80RegClass.hasSubClassEq(RC) &&
"Unknown 10-byte regclass");
5834 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
5836 assert(X86::VR128XRegClass.hasSubClassEq(RC) &&
"Unknown 16-byte regclass");
5840 (HasVLX ? X86::VMOVAPSZ128rm :
5841 HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
5842 HasAVX ? X86::VMOVAPSrm :
5844 (HasVLX ? X86::VMOVAPSZ128mr :
5845 HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
5846 HasAVX ? X86::VMOVAPSmr :
5850 (HasVLX ? X86::VMOVUPSZ128rm :
5851 HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
5852 HasAVX ? X86::VMOVUPSrm :
5854 (HasVLX ? X86::VMOVUPSZ128mr :
5855 HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
5856 HasAVX ? X86::VMOVUPSmr :
5860 assert(X86::VR256XRegClass.hasSubClassEq(RC) &&
"Unknown 32-byte regclass");
5864 (HasVLX ? X86::VMOVAPSZ256rm :
5865 HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
5867 (HasVLX ? X86::VMOVAPSZ256mr :
5868 HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
5872 (HasVLX ? X86::VMOVUPSZ256rm :
5873 HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
5875 (HasVLX ? X86::VMOVUPSZ256mr :
5876 HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
5879 assert(X86::VR512RegClass.hasSubClassEq(RC) &&
"Unknown 64-byte regclass");
5882 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
5884 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
5893 if (MemRefBegin < 0)
5899 if (!BaseMO.
isReg())
5902 BaseReg = BaseMO.
getReg();
5913 if (!DispMO.
isImm())
5916 Offset = DispMO.
getImm();
5923 bool isStackAligned,
5931 bool isStackAligned,
5938 unsigned SrcReg,
bool isKill,
int FrameIdx,
5943 "Stack slot too small for store");
5944 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
5961 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
5967 for (
unsigned i = 0, e = Addr.
size();
i != e; ++
i)
5977 unsigned DestReg,
int FrameIdx,
5981 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
5996 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
6002 for (
unsigned i = 0, e = Addr.
size();
i != e; ++
i)
6009 unsigned &SrcReg2,
int &CmpMask,
6010 int &CmpValue)
const {
6013 case X86::CMP64ri32:
6046 case X86::SUB64ri32:
6092 unsigned SrcReg2,
int ImmValue,
6104 if (((FlagI.
getOpcode() == X86::CMP64ri32 &&
6125 default:
return false;
6129 case X86::SAR8ri:
case X86::SAR16ri:
case X86::SAR32ri:
case X86::SAR64ri:
6130 case X86::SHR8ri:
case X86::SHR16ri:
case X86::SHR32ri:
case X86::SHR64ri:
6135 case X86::SHL8ri:
case X86::SHL16ri:
case X86::SHL32ri:
case X86::SHL64ri:{
6141 case X86::SHRD16rri8:
case X86::SHRD32rri8:
case X86::SHRD64rri8:
6142 case X86::SHLD16rri8:
case X86::SHLD32rri8:
case X86::SHLD64rri8:
6145 case X86::SUB64ri32:
case X86::SUB64ri8:
case X86::SUB32ri:
6146 case X86::SUB32ri8:
case X86::SUB16ri:
case X86::SUB16ri8:
6147 case X86::SUB8ri:
case X86::SUB64rr:
case X86::SUB32rr:
6148 case X86::SUB16rr:
case X86::SUB8rr:
case X86::SUB64rm:
6149 case X86::SUB32rm:
case X86::SUB16rm:
case X86::SUB8rm:
6150 case X86::DEC64r:
case X86::DEC32r:
case X86::DEC16r:
case X86::DEC8r:
6151 case X86::ADD64ri32:
case X86::ADD64ri8:
case X86::ADD32ri:
6152 case X86::ADD32ri8:
case X86::ADD16ri:
case X86::ADD16ri8:
6153 case X86::ADD8ri:
case X86::ADD64rr:
case X86::ADD32rr:
6154 case X86::ADD16rr:
case X86::ADD8rr:
case X86::ADD64rm:
6155 case X86::ADD32rm:
case X86::ADD16rm:
case X86::ADD8rm:
6156 case X86::INC64r:
case X86::INC32r:
case X86::INC16r:
case X86::INC8r:
6157 case X86::AND64ri32:
case X86::AND64ri8:
case X86::AND32ri:
6158 case X86::AND32ri8:
case X86::AND16ri:
case X86::AND16ri8:
6159 case X86::AND8ri:
case X86::AND64rr:
case X86::AND32rr:
6160 case X86::AND16rr:
case X86::AND8rr:
case X86::AND64rm:
6161 case X86::AND32rm:
case X86::AND16rm:
case X86::AND8rm:
6162 case X86::XOR64ri32:
case X86::XOR64ri8:
case X86::XOR32ri:
6163 case X86::XOR32ri8:
case X86::XOR16ri:
case X86::XOR16ri8:
6164 case X86::XOR8ri:
case X86::XOR64rr:
case X86::XOR32rr:
6165 case X86::XOR16rr:
case X86::XOR8rr:
case X86::XOR64rm:
6166 case X86::XOR32rm:
case X86::XOR16rm:
case X86::XOR8rm:
6167 case X86::OR64ri32:
case X86::OR64ri8:
case X86::OR32ri:
6168 case X86::OR32ri8:
case X86::OR16ri:
case X86::OR16ri8:
6169 case X86::OR8ri:
case X86::OR64rr:
case X86::OR32rr:
6170 case X86::OR16rr:
case X86::OR8rr:
case X86::OR64rm:
6171 case X86::OR32rm:
case X86::OR16rm:
case X86::OR8rm:
6172 case X86::NEG8r:
case X86::NEG16r:
case X86::NEG32r:
case X86::NEG64r:
6173 case X86::SAR8r1:
case X86::SAR16r1:
case X86::SAR32r1:
case X86::SAR64r1:
6174 case X86::SHR8r1:
case X86::SHR16r1:
case X86::SHR32r1:
case X86::SHR64r1:
6175 case X86::SHL8r1:
case X86::SHL16r1:
case X86::SHL32r1:
case X86::SHL64r1:
6176 case X86::ADC32ri:
case X86::ADC32ri8:
6177 case X86::ADC32rr:
case X86::ADC64ri32:
6178 case X86::ADC64ri8:
case X86::ADC64rr:
6179 case X86::SBB32ri:
case X86::SBB32ri8:
6180 case X86::SBB32rr:
case X86::SBB64ri32:
6181 case X86::SBB64ri8:
case X86::SBB64rr:
6182 case X86::ANDN32rr:
case X86::ANDN32rm:
6183 case X86::ANDN64rr:
case X86::ANDN64rm:
6184 case X86::BEXTR32rr:
case X86::BEXTR64rr:
6185 case X86::BEXTR32rm:
case X86::BEXTR64rm:
6186 case X86::BLSI32rr:
case X86::BLSI32rm:
6187 case X86::BLSI64rr:
case X86::BLSI64rm:
6188 case X86::BLSMSK32rr:
case X86::BLSMSK32rm:
6189 case X86::BLSMSK64rr:
case X86::BLSMSK64rm:
6190 case X86::BLSR32rr:
case X86::BLSR32rm:
6191 case X86::BLSR64rr:
case X86::BLSR64rm:
6192 case X86::BZHI32rr:
case X86::BZHI32rm:
6193 case X86::BZHI64rr:
case X86::BZHI64rm:
6194 case X86::LZCNT16rr:
case X86::LZCNT16rm:
6195 case X86::LZCNT32rr:
case X86::LZCNT32rm:
6196 case X86::LZCNT64rr:
case X86::LZCNT64rm:
6197 case X86::POPCNT16rr:
case X86::POPCNT16rm:
6198 case X86::POPCNT32rr:
case X86::POPCNT32rm:
6199 case X86::POPCNT64rr:
case X86::POPCNT64rm:
6200 case X86::TZCNT16rr:
case X86::TZCNT16rm:
6201 case X86::TZCNT32rr:
case X86::TZCNT32rm:
6202 case X86::TZCNT64rr:
case X86::TZCNT64rm:
6211 case X86::LZCNT16rr:
case X86::LZCNT16rm:
6212 case X86::LZCNT32rr:
case X86::LZCNT32rm:
6213 case X86::LZCNT64rr:
case X86::LZCNT64rm:
6215 case X86::POPCNT16rr:
case X86::POPCNT16rm:
6216 case X86::POPCNT32rr:
case X86::POPCNT32rm:
6217 case X86::POPCNT64rr:
case X86::POPCNT64rm:
6219 case X86::TZCNT16rr:
case X86::TZCNT16rm:
6220 case X86::TZCNT32rr:
case X86::TZCNT32rm:
6221 case X86::TZCNT64rr:
case X86::TZCNT64rm:
6230 unsigned SrcReg2,
int CmpMask,
6234 unsigned NewOpcode = 0;
6237 case X86::SUB64ri32:
6257 case X86::SUB64rm: NewOpcode = X86::CMP64rm;
break;
6258 case X86::SUB32rm: NewOpcode = X86::CMP32rm;
break;
6259 case X86::SUB16rm: NewOpcode = X86::CMP16rm;
break;
6260 case X86::SUB8rm: NewOpcode = X86::CMP8rm;
break;
6261 case X86::SUB64rr: NewOpcode = X86::CMP64rr;
break;
6262 case X86::SUB32rr: NewOpcode = X86::CMP32rr;
break;
6263 case X86::SUB16rr: NewOpcode = X86::CMP16rr;
break;
6264 case X86::SUB8rr: NewOpcode = X86::CMP8rr;
break;
6265 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32;
break;
6266 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8;
break;
6267 case X86::SUB32ri: NewOpcode = X86::CMP32ri;
break;
6268 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8;
break;
6269 case X86::SUB16ri: NewOpcode = X86::CMP16ri;
break;
6270 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8;
break;
6271 case X86::SUB8ri: NewOpcode = X86::CMP8ri;
break;
6273 CmpInstr.
setDesc(
get(NewOpcode));
6276 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
6277 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
6284 if (!MI)
return false;
6291 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
6298 bool ShouldUpdateCC =
false;
6307 J->getOperand(1).getReg() == SrcReg) {
6308 assert(J->definesRegister(X86::EFLAGS) &&
"Must be an EFLAGS def!");
6309 ShouldUpdateCC =
true;
6338 for (; RI != RE; ++RI) {
6354 if (!Movr0Inst && Instr.
getOpcode() == X86::MOV32r0 &&
6366 if (!IsCmpZero && !Sub)
6369 bool IsSwapped = (SrcReg2 != 0 && Sub->
getOperand(1).
getReg() == SrcReg2 &&
6376 bool IsSafe =
false;
6379 for (++I; I !=
E; ++
I) {
6380 const MachineInstr &Instr = *
I;
6384 if (!UseEFLAGS && ModifyEFLAGS) {
6389 if (!UseEFLAGS && !ModifyEFLAGS)
6394 bool OpcIsSET =
false;
6395 if (IsCmpZero || IsSwapped) {
6432 }
else if (IsSwapped) {
6440 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
6457 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
6459 if (ModifyEFLAGS || Instr.
killsRegister(X86::EFLAGS, TRI)) {
6468 if ((IsCmpZero || IsSwapped) && !IsSafe) {
6476 Sub = IsCmpZero ? MI : Sub;
6483 for (; InsertI != InsertE; ++InsertI) {
6484 MachineInstr *Instr = &*InsertI;
6493 if (InsertI == InsertE)
6499 for (; i != e; ++
i) {
6506 assert(i != e &&
"Unable to locate a def EFLAGS operand");
6511 for (
auto &Op : OpsToUpdate)
6512 Op.first->setDesc(
get(Op.second));
6522 unsigned &FoldAsLoadDefReg,
6538 if (Reg != FoldAsLoadDefReg)
6545 if (SrcOperandIds.
empty())
6549 if (
MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
6550 FoldAsLoadDefReg = 0;
6605 MIB->
setDesc(TII.
get(MinusOne ? X86::DEC32r : X86::INC32r));
6617 assert(Imm != 0 &&
"Using push/pop for 0 is not efficient.");
6624 MIB->
getOpcode() == X86::MOV32ImmSExti8);
6629 if (X86FI->getUsesRedZone()) {
6631 X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
6637 StackAdjustment = 8;
6638 BuildMI(MBB, I, DL, TII.
get(X86::PUSH64i8)).addImm(Imm);
6644 StackAdjustment = 4;
6645 BuildMI(MBB, I, DL, TII.
get(X86::PUSH32i8)).addImm(Imm);
6653 bool NeedsDwarfCFI =
6656 bool EmitCFI = !TFL->
hasFP(MF) && NeedsDwarfCFI;
6660 TFL->
BuildCFI(MBB, std::next(I), DL,
6739 bool HasAVX = Subtarget.
hasAVX();
6748 case X86::MOV32ImmSExti8:
6749 case X86::MOV64ImmSExti8:
6753 case X86::SETB_C16r:
6755 case X86::SETB_C32r:
6757 case X86::SETB_C64r:
6764 assert(HasAVX &&
"AVX not supported");
6766 case X86::AVX512_128_SET0:
6768 case X86::AVX512_256_SET0:
6770 case X86::AVX512_512_SET0:
6772 case X86::AVX512_FsFLD0SS:
6773 case X86::AVX512_FsFLD0SD:
6775 case X86::V_SETALLONES:
6776 return Expand2AddrUndef(MIB,
get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
6777 case X86::AVX2_SETALLONES:
6779 case X86::AVX512_512_SETALLONES: {
6781 MIB->
setDesc(
get(X86::VPTERNLOGDZrri));
6788 case X86::AVX512_512_SEXT_MASK_32:
6789 case X86::AVX512_512_SEXT_MASK_64: {
6793 unsigned Opc = (MI.
getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
6794 X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
6803 case X86::VMOVAPSZ128rm_NOVLX:
6805 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
6806 case X86::VMOVUPSZ128rm_NOVLX:
6808 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
6809 case X86::VMOVAPSZ256rm_NOVLX:
6811 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
6812 case X86::VMOVUPSZ256rm_NOVLX:
6814 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
6815 case X86::VMOVAPSZ128mr_NOVLX:
6817 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6818 case X86::VMOVUPSZ128mr_NOVLX:
6820 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6821 case X86::VMOVAPSZ256mr_NOVLX:
6823 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6824 case X86::VMOVUPSZ256mr_NOVLX:
6826 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6827 case X86::TEST8ri_NOREX:
6828 MI.
setDesc(
get(X86::TEST8ri));
6830 case X86::MOV32ri64:
6831 MI.
setDesc(
get(X86::MOV32ri));
6842 case X86::KSET0W:
return Expand2AddrKreg(MIB,
get(X86::KXORWrr), X86::K0);
6843 case X86::KSET0D:
return Expand2AddrKreg(MIB,
get(X86::KXORDrr), X86::K0);
6844 case X86::KSET0Q:
return Expand2AddrKreg(MIB,
get(X86::KXORQrr), X86::K0);
6846 case X86::KSET1W:
return Expand2AddrKreg(MIB,
get(X86::KXNORWrr), X86::K0);
6847 case X86::KSET1D:
return Expand2AddrKreg(MIB,
get(X86::KXNORDrr), X86::K0);
6848 case X86::KSET1Q:
return Expand2AddrKreg(MIB,
get(X86::KXNORQrr), X86::K0);
6849 case TargetOpcode::LOAD_STACK_GUARD:
6857 int PtrOffset = 0) {
6858 unsigned NumAddrOps = MOs.
size();
6860 if (NumAddrOps < 4) {
6862 for (
unsigned i = 0;
i != NumAddrOps; ++
i)
6868 assert(MOs.
size() == 5 &&
"Unexpected memory operand list length");
6869 for (
unsigned i = 0;
i != NumAddrOps; ++
i) {
6871 if (
i == 3 && PtrOffset != 0) {
6894 for (
unsigned i = 0;
i != NumOps; ++
i) {
6904 MBB->
insert(InsertPt, NewMI);
6913 int PtrOffset = 0) {
6922 assert(MO.
isReg() &&
"Expected to fold into reg operand!");
6930 MBB->
insert(InsertPt, NewMI);
6948 unsigned Size,
unsigned Align)
const {
6950 case X86::INSERTPSrr:
6951 case X86::VINSERTPSrr:
6952 case X86::VINSERTPSZrr:
6957 unsigned ZMask = Imm & 15;
6958 unsigned DstIdx = (Imm >> 4) & 3;
6959 unsigned SrcIdx = (Imm >> 6) & 3;
6962 if (Size <= RCSize && 4 <= Align) {
6963 int PtrOffset = SrcIdx * 4;
6964 unsigned NewImm = (DstIdx << 4) | ZMask;
6965 unsigned NewOpCode =
6966 (MI.
getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
6967 (MI.
getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm :
6970 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *
this, PtrOffset);
6976 case X86::MOVHLPSrr:
6977 case X86::VMOVHLPSrr:
6978 case X86::VMOVHLPSZrr:
6984 if (Size <= RCSize && 8 <= Align) {
6985 unsigned NewOpCode =
6986 (MI.
getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
6987 (MI.
getOpcode() == X86::VMOVHLPSrr) ? X86::VMOVLPSrm :
6990 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *
this, 8);
7003 unsigned Size,
unsigned Align,
bool AllowCommute)
const {
7005 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr =
nullptr;
7007 bool isTwoAddrFold =
false;
7032 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
7038 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.
getOperand(0).
isReg() &&
7041 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
7042 isTwoAddrFold =
true;
7043 }
else if (OpNum == 0) {
7045 NewMI =
MakeM0Inst(*
this, X86::MOV32mi, MOs, InsertPt, MI);
7050 OpcodeTablePtr = &RegOp2MemOpTable0;
7051 }
else if (OpNum == 1) {
7052 OpcodeTablePtr = &RegOp2MemOpTable1;
7053 }
else if (OpNum == 2) {
7054 OpcodeTablePtr = &RegOp2MemOpTable2;
7055 }
else if (OpNum == 3) {
7056 OpcodeTablePtr = &RegOp2MemOpTable3;
7057 }
else if (OpNum == 4) {
7058 OpcodeTablePtr = &RegOp2MemOpTable4;
7062 if (OpcodeTablePtr) {
7064 auto I = OpcodeTablePtr->find(MI.
getOpcode());
7065 if (I != OpcodeTablePtr->end()) {
7066 unsigned Opcode = I->second.first;
7068 if (Align < MinAlign)
7070 bool NarrowToMOV32rm =
false;
7073 if (Size < RCSize) {
7076 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
7083 Opcode = X86::MOV32rm;
7084 NarrowToMOV32rm =
true;
7091 NewMI =
FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *
this);
7093 if (NarrowToMOV32rm) {
7110 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
7123 if ((HasDef && Reg0 == Reg1 && Tied1) ||
7124 (HasDef && Reg0 == Reg2 && Tied2))
7128 commuteInstruction(MI,
false, CommuteOpIdx1, CommuteOpIdx2);
7133 if (CommutedMI != &MI) {
7141 Size, Align,
false);
7147 commuteInstruction(MI,
false, CommuteOpIdx1, CommuteOpIdx2);
7148 if (!UncommutedMI) {
7152 if (UncommutedMI != &MI) {
7165 dbgs() <<
"We failed to fuse operand " << OpNum <<
" in " <<
MI;
7187 case X86::CVTSI2SSrr:
7188 case X86::CVTSI2SSrm:
7189 case X86::CVTSI2SS64rr:
7190 case X86::CVTSI2SS64rm:
7191 case X86::CVTSI2SDrr:
7192 case X86::CVTSI2SDrm:
7193 case X86::CVTSI2SD64rr:
7194 case X86::CVTSI2SD64rm:
7195 case X86::CVTSD2SSrr:
7196 case X86::CVTSD2SSrm:
7197 case X86::CVTSS2SDrr:
7198 case X86::CVTSS2SDrm:
7205 case X86::RCPSSr_Int:
7206 case X86::RCPSSm_Int:
7213 case X86::RSQRTSSr_Int:
7214 case X86::RSQRTSSm_Int:
7217 case X86::SQRTSSr_Int:
7218 case X86::SQRTSSm_Int:
7221 case X86::SQRTSDr_Int:
7222 case X86::SQRTSDm_Int:
7258 case X86::VCVTSI2SSrr:
7259 case X86::VCVTSI2SSrm:
7260 case X86::Int_VCVTSI2SSrr:
7261 case X86::Int_VCVTSI2SSrm:
7262 case X86::VCVTSI2SS64rr:
7263 case X86::VCVTSI2SS64rm:
7264 case X86::Int_VCVTSI2SS64rr:
7265 case X86::Int_VCVTSI2SS64rm:
7266 case X86::VCVTSI2SDrr:
7267 case X86::VCVTSI2SDrm:
7268 case X86::Int_VCVTSI2SDrr:
7269 case X86::Int_VCVTSI2SDrm:
7270 case X86::VCVTSI2SD64rr:
7271 case X86::VCVTSI2SD64rm:
7272 case X86::Int_VCVTSI2SD64rr:
7273 case X86::Int_VCVTSI2SD64rm:
7274 case X86::VCVTSD2SSrr:
7275 case X86::VCVTSD2SSrm:
7276 case X86::Int_VCVTSD2SSrr:
7277 case X86::Int_VCVTSD2SSrm:
7278 case X86::VCVTSS2SDrr:
7279 case X86::VCVTSS2SDrm:
7280 case X86::Int_VCVTSS2SDrr:
7281 case X86::Int_VCVTSS2SDrm:
7283 case X86::VRCPSSr_Int:
7285 case X86::VRCPSSm_Int:
7286 case X86::VROUNDSDr:
7287 case X86::VROUNDSDm:
7288 case X86::VROUNDSDr_Int:
7289 case X86::VROUNDSDm_Int:
7290 case X86::VROUNDSSr:
7291 case X86::VROUNDSSm:
7292 case X86::VROUNDSSr_Int:
7293 case X86::VROUNDSSm_Int:
7294 case X86::VRSQRTSSr:
7295 case X86::VRSQRTSSr_Int:
7296 case X86::VRSQRTSSm:
7297 case X86::VRSQRTSSm_Int:
7299 case X86::VSQRTSSr_Int:
7301 case X86::VSQRTSSm_Int:
7303 case X86::VSQRTSDr_Int:
7305 case X86::VSQRTSDm_Int:
7307 case X86::VCVTSI2SSZrr:
7308 case X86::VCVTSI2SSZrm:
7309 case X86::VCVTSI2SSZrr_Int:
7310 case X86::VCVTSI2SSZrrb_Int:
7311 case X86::VCVTSI2SSZrm_Int:
7312 case X86::VCVTSI642SSZrr:
7313 case X86::VCVTSI642SSZrm:
7314 case X86::VCVTSI642SSZrr_Int:
7315 case X86::VCVTSI642SSZrrb_Int:
7316 case X86::VCVTSI642SSZrm_Int:
7317 case X86::VCVTSI2SDZrr:
7318 case X86::VCVTSI2SDZrm:
7319 case X86::VCVTSI2SDZrr_Int:
7320 case X86::VCVTSI2SDZrrb_Int:
7321 case X86::VCVTSI2SDZrm_Int:
7322 case X86::VCVTSI642SDZrr:
7323 case X86::VCVTSI642SDZrm:
7324 case X86::VCVTSI642SDZrr_Int:
7325 case X86::VCVTSI642SDZrrb_Int:
7326 case X86::VCVTSI642SDZrm_Int:
7327 case X86::VCVTUSI2SSZrr:
7328 case X86::VCVTUSI2SSZrm:
7329 case X86::VCVTUSI2SSZrr_Int:
7330 case X86::VCVTUSI2SSZrrb_Int:
7331 case X86::VCVTUSI2SSZrm_Int:
7332 case X86::VCVTUSI642SSZrr:
7333 case X86::VCVTUSI642SSZrm:
7334 case X86::VCVTUSI642SSZrr_Int:
7335 case X86::VCVTUSI642SSZrrb_Int:
7336 case X86::VCVTUSI642SSZrm_Int:
7337 case X86::VCVTUSI2SDZrr:
7338 case X86::VCVTUSI2SDZrm:
7339 case X86::VCVTUSI2SDZrr_Int:
7340 case X86::VCVTUSI2SDZrm_Int:
7341 case X86::VCVTUSI642SDZrr:
7342 case X86::VCVTUSI642SDZrm:
7343 case X86::VCVTUSI642SDZrr_Int:
7344 case X86::VCVTUSI642SDZrrb_Int:
7345 case X86::VCVTUSI642SDZrm_Int:
7346 case X86::VCVTSD2SSZrr:
7347 case X86::VCVTSD2SSZrrb:
7348 case X86::VCVTSD2SSZrm:
7349 case X86::VCVTSS2SDZrr:
7350 case X86::VCVTSS2SDZrrb:
7351 case X86::VCVTSS2SDZrm:
7352 case X86::VRNDSCALESDr:
7353 case X86::VRNDSCALESDrb:
7354 case X86::VRNDSCALESDm:
7355 case X86::VRNDSCALESSr:
7356 case X86::VRNDSCALESSrb:
7357 case X86::VRNDSCALESSm:
7358 case X86::VRCP14SSrr:
7359 case X86::VRCP14SSrm:
7360 case X86::VRSQRT14SSrr:
7361 case X86::VRSQRT14SSrm:
7362 case X86::VSQRTSSZr:
7363 case X86::VSQRTSSZr_Int:
7364 case X86::VSQRTSSZrb_Int:
7365 case X86::VSQRTSSZm:
7366 case X86::VSQRTSSZm_Int:
7367 case X86::VSQRTSDZr:
7368 case X86::VSQRTSDZr_Int:
7369 case X86::VSQRTSDZrb_Int:
7370 case X86::VSQRTSDZm:
7371 case X86::VSQRTSDZm_Int:
7415 if (X86::VR128RegClass.
contains(Reg)) {
7418 unsigned Opc = Subtarget.
hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
7423 }
else if (X86::VR256RegClass.
contains(Reg)) {
7426 unsigned XReg = TRI->
getSubReg(Reg, X86::sub_xmm);
7450 for (
auto Op : Ops) {
7462 if (!RI.needsStackRealignment(MF))
7465 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7466 unsigned NewOpc = 0;
7467 unsigned RCSize = 0;
7469 default:
return nullptr;
7470 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1;
break;
7471 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2;
break;
7472 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4;
break;
7473 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8;
break;
7482 }
else if (Ops.size() != 1)
7487 Size, Alignment,
true);
7512 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
7518 case X86::ADDSSrr_Int:
case X86::VADDSSrr_Int:
case X86::VADDSSZrr_Int:
7519 case X86::Int_CMPSSrr:
case X86::Int_VCMPSSrr:
case X86::VCMPSSZrr_Int:
7520 case X86::DIVSSrr_Int:
case X86::VDIVSSrr_Int:
case X86::VDIVSSZrr_Int:
7521 case X86::MAXSSrr_Int:
case X86::VMAXSSrr_Int:
case X86::VMAXSSZrr_Int:
7522 case X86::MINSSrr_Int:
case X86::VMINSSrr_Int:
case X86::VMINSSZrr_Int:
7523 case X86::MULSSrr_Int:
case X86::VMULSSrr_Int:
case X86::VMULSSZrr_Int:
7524 case X86::SUBSSrr_Int:
case X86::VSUBSSrr_Int:
case X86::VSUBSSZrr_Int:
7525 case X86::VFMADDSS4rr_Int:
case X86::VFNMADDSS4rr_Int:
7526 case X86::VFMSUBSS4rr_Int:
case X86::VFNMSUBSS4rr_Int:
7527 case X86::VFMADD132SSr_Int:
case X86::VFNMADD132SSr_Int:
7528 case X86::VFMADD213SSr_Int:
case X86::VFNMADD213SSr_Int:
7529 case X86::VFMADD231SSr_Int:
case X86::VFNMADD231SSr_Int:
7530 case X86::VFMSUB132SSr_Int:
case X86::VFNMSUB132SSr_Int:
7531 case X86::VFMSUB213SSr_Int:
case X86::VFNMSUB213SSr_Int:
7532 case X86::VFMSUB231SSr_Int:
case X86::VFNMSUB231SSr_Int:
7533 case X86::VFMADD132SSZr_Int:
case X86::VFNMADD132SSZr_Int:
7534 case X86::VFMADD213SSZr_Int:
case X86::VFNMADD213SSZr_Int:
7535 case X86::VFMADD231SSZr_Int:
case X86::VFNMADD231SSZr_Int:
7536 case X86::VFMSUB132SSZr_Int:
case X86::VFNMSUB132SSZr_Int:
7537 case X86::VFMSUB213SSZr_Int:
case X86::VFNMSUB213SSZr_Int:
7538 case X86::VFMSUB231SSZr_Int:
case X86::VFNMSUB231SSZr_Int:
7545 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
7551 case X86::ADDSDrr_Int:
case X86::VADDSDrr_Int:
case X86::VADDSDZrr_Int:
7552 case X86::Int_CMPSDrr:
case X86::Int_VCMPSDrr:
case X86::VCMPSDZrr_Int:
7553 case X86::DIVSDrr_Int:
case X86::VDIVSDrr_Int:
case X86::VDIVSDZrr_Int:
7554 case X86::MAXSDrr_Int:
case X86::VMAXSDrr_Int:
case X86::VMAXSDZrr_Int:
7555 case X86::MINSDrr_Int:
case X86::VMINSDrr_Int:
case X86::VMINSDZrr_Int:
7556 case X86::MULSDrr_Int:
case X86::VMULSDrr_Int:
case X86::VMULSDZrr_Int:
7557 case X86::SUBSDrr_Int:
case X86::VSUBSDrr_Int:
case X86::VSUBSDZrr_Int:
7558 case X86::VFMADDSD4rr_Int:
case X86::VFNMADDSD4rr_Int:
7559 case X86::VFMSUBSD4rr_Int:
case X86::VFNMSUBSD4rr_Int:
7560 case X86::VFMADD132SDr_Int:
case X86::VFNMADD132SDr_Int:
7561 case X86::VFMADD213SDr_Int:
case X86::VFNMADD213SDr_Int:
7562 case X86::VFMADD231SDr_Int:
case X86::VFNMADD231SDr_Int:
7563 case X86::VFMSUB132SDr_Int:
case X86::VFNMSUB132SDr_Int:
7564 case X86::VFMSUB213SDr_Int:
case X86::VFNMSUB213SDr_Int:
7565 case X86::VFMSUB231SDr_Int:
case X86::VFNMSUB231SDr_Int:
7566 case X86::VFMADD132SDZr_Int:
case X86::VFNMADD132SDZr_Int:
7567 case X86::VFMADD213SDZr_Int:
case X86::VFNMADD213SDZr_Int:
7568 case X86::VFMADD231SDZr_Int:
case X86::VFNMADD231SDZr_Int:
7569 case X86::VFMSUB132SDZr_Int:
case X86::VFNMSUB132SDZr_Int:
7570 case X86::VFMSUB213SDZr_Int:
case X86::VFNMSUB213SDZr_Int:
7571 case X86::VFMSUB231SDZr_Int:
case X86::VFNMSUB231SDZr_Int:
7588 for (
auto Op : Ops) {
7610 unsigned Alignment = 0;
7615 case X86::AVX512_512_SET0:
7616 case X86::AVX512_512_SETALLONES:
7619 case X86::AVX2_SETALLONES:
7621 case X86::AVX512_256_SET0:
7625 case X86::V_SETALLONES:
7626 case X86::AVX512_128_SET0:
7630 case X86::AVX512_FsFLD0SD:
7634 case X86::AVX512_FsFLD0SS:
7640 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7641 unsigned NewOpc = 0;
7643 default:
return nullptr;
7644 case X86::TEST8rr: NewOpc = X86::CMP8ri;
break;
7645 case X86::TEST16rr: NewOpc = X86::CMP16ri8;
break;
7646 case X86::TEST32rr: NewOpc = X86::CMP32ri8;
break;
7647 case X86::TEST64rr: NewOpc = X86::CMP64ri8;
break;
7652 }
else if (Ops.size() != 1)
7663 case X86::V_SETALLONES:
7664 case X86::AVX2_SETALLONES:
7666 case X86::AVX512_128_SET0:
7667 case X86::AVX512_256_SET0:
7668 case X86::AVX512_512_SET0:
7669 case X86::AVX512_512_SETALLONES:
7671 case X86::AVX512_FsFLD0SD:
7673 case X86::AVX512_FsFLD0SS: {
7683 unsigned PICBase = 0;
7699 if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
7701 else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
7703 else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
7705 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
7706 Opc == X86::AVX512_256_SET0)
7711 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
7712 Opc == X86::AVX512_512_SETALLONES);
7736 0, Alignment,
true);
7743 if (I == MemOp2RegOpTable.
end())
7745 unsigned Opc = I->second.first;
7749 if (UnfoldLoad && !FoldedLoad)
7751 UnfoldLoad &= FoldedLoad;
7752 if (UnfoldStore && !FoldedStore)
7754 UnfoldStore &= FoldedStore;
7783 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
7785 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
7809 MIB.
addReg(ImpOp.getReg(),
7819 case X86::CMP64ri32:
7833 case X86::CMP64ri32: NewOpc = X86::TEST64rr;
break;
7835 case X86::CMP32ri: NewOpc = X86::TEST32rr;
break;
7837 case X86::CMP16ri: NewOpc = X86::TEST16rr;
break;
7838 case X86::CMP8ri: NewOpc = X86::TEST8rr;
break;
7850 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
7852 storeRegToAddr(MF, Reg,
true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
7865 if (I == MemOp2RegOpTable.
end())
7867 unsigned Opc = I->second.first;
7874 unsigned NumDefs = MCID.
NumDefs;
7875 std::vector<SDValue> AddrOps;
7876 std::vector<SDValue> BeforeOps;
7877 std::vector<SDValue> AfterOps;
7880 for (
unsigned i = 0;
i != NumOps-1; ++
i) {
7883 AddrOps.push_back(Op);
7884 else if (
i < Index-NumDefs)
7885 BeforeOps.push_back(Op);
7886 else if (
i > Index-NumDefs)
7887 AfterOps.push_back(Op);
7890 AddrOps.push_back(Chain);
7897 MachineInstr::mmo_iterator> MMOs =
7899 cast<MachineSDNode>(N)->memoperands_end());
7900 if (!(*MMOs.first) &&
7901 RC == &X86::VR128RegClass &&
7907 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
7909 (*MMOs.first)->getAlignment() >= Alignment;
7915 cast<MachineSDNode>(
Load)->setMemRefs(MMOs.first, MMOs.second);
7919 std::vector<EVT> VTs;
7931 BeforeOps.push_back(
SDValue(Load, 0));
7932 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
7939 AddrOps.push_back(
SDValue(NewNode, 0));
7940 AddrOps.push_back(Chain);
7942 MachineInstr::mmo_iterator> MMOs =
7944 cast<MachineSDNode>(N)->memoperands_end());
7945 if (!(*MMOs.first) &&
7946 RC == &X86::VR128RegClass &&
7952 unsigned Alignment = std::max<uint32_t>(RC->
getSize(), 16);
7954 (*MMOs.first)->getAlignment() >= Alignment;
7961 cast<MachineSDNode>(
Store)->setMemRefs(MMOs.first, MMOs.second);
7968 bool UnfoldLoad,
bool UnfoldStore,
7969 unsigned *LoadRegIndex)
const {
7970 auto I = MemOp2RegOpTable.
find(Opc);
7971 if (I == MemOp2RegOpTable.
end())
7975 if (UnfoldLoad && !FoldedLoad)
7977 if (UnfoldStore && !FoldedStore)
7981 return I->second.first;
7986 int64_t &Offset1, int64_t &Offset2)
const {
7992 default:
return false;
8002 case X86::MMX_MOVD64rm:
8003 case X86::MMX_MOVQ64rm:
8013 case X86::VMOVAPSrm:
8014 case X86::VMOVUPSrm:
8015 case X86::VMOVAPDrm:
8016 case X86::VMOVUPDrm:
8017 case X86::VMOVDQArm:
8018 case X86::VMOVDQUrm:
8019 case X86::VMOVAPSYrm:
8020 case X86::VMOVUPSYrm:
8021 case X86::VMOVAPDYrm:
8022 case X86::VMOVUPDYrm:
8023 case X86::VMOVDQAYrm:
8024 case X86::VMOVDQUYrm:
8026 case X86::VMOVSSZrm:
8027 case X86::VMOVSDZrm:
8028 case X86::VMOVAPSZ128rm:
8029 case X86::VMOVUPSZ128rm:
8030 case X86::VMOVAPSZ128rm_NOVLX:
8031 case X86::VMOVUPSZ128rm_NOVLX:
8032 case X86::VMOVAPDZ128rm:
8033 case X86::VMOVUPDZ128rm:
8034 case X86::VMOVDQU8Z128rm:
8035 case X86::VMOVDQU16Z128rm:
8036 case X86::VMOVDQA32Z128rm:
8037 case X86::VMOVDQU32Z128rm:
8038 case X86::VMOVDQA64Z128rm:
8039 case X86::VMOVDQU64Z128rm:
8040 case X86::VMOVAPSZ256rm:
8041 case X86::VMOVUPSZ256rm:
8042 case X86::VMOVAPSZ256rm_NOVLX:
8043 case X86::VMOVUPSZ256rm_NOVLX:
8044 case X86::VMOVAPDZ256rm:
8045 case X86::VMOVUPDZ256rm:
8046 case X86::VMOVDQU8Z256rm:
8047 case X86::VMOVDQU16Z256rm:
8048 case X86::VMOVDQA32Z256rm:
8049 case X86::VMOVDQU32Z256rm:
8050 case X86::VMOVDQA64Z256rm:
8051 case X86::VMOVDQU64Z256rm:
8052 case X86::VMOVAPSZrm:
8053 case X86::VMOVUPSZrm:
8054 case X86::VMOVAPDZrm:
8055 case X86::VMOVUPDZrm:
8056 case X86::VMOVDQU8Zrm:
8057 case X86::VMOVDQU16Zrm:
8058 case X86::VMOVDQA32Zrm:
8059 case X86::VMOVDQU32Zrm:
8060 case X86::VMOVDQA64Zrm:
8061 case X86::VMOVDQU64Zrm:
8069 default:
return false;
8079 case X86::MMX_MOVD64rm:
8080 case X86::MMX_MOVQ64rm:
8090 case X86::VMOVAPSrm:
8091 case X86::VMOVUPSrm:
8092 case X86::VMOVAPDrm:
8093 case X86::VMOVUPDrm:
8094 case X86::VMOVDQArm:
8095 case X86::VMOVDQUrm:
8096 case X86::VMOVAPSYrm:
8097 case X86::VMOVUPSYrm:
8098 case X86::VMOVAPDYrm:
8099 case X86::VMOVUPDYrm:
8100 case X86::VMOVDQAYrm:
8101 case X86::VMOVDQUYrm:
8103 case X86::VMOVSSZrm:
8104 case X86::VMOVSDZrm:
8105 case X86::VMOVAPSZ128rm:
8106 case X86::VMOVUPSZ128rm:
8107 case X86::VMOVAPSZ128rm_NOVLX:
8108 case X86::VMOVUPSZ128rm_NOVLX:
8109 case X86::VMOVAPDZ128rm:
8110 case X86::VMOVUPDZ128rm:
8111 case X86::VMOVDQU8Z128rm:
8112 case X86::VMOVDQU16Z128rm:
8113 case X86::VMOVDQA32Z128rm:
8114 case X86::VMOVDQU32Z128rm:
8115 case X86::VMOVDQA64Z128rm:
8116 case X86::VMOVDQU64Z128rm:
8117 case X86::VMOVAPSZ256rm:
8118 case X86::VMOVUPSZ256rm:
8119 case X86::VMOVAPSZ256rm_NOVLX:
8120 case X86::VMOVUPSZ256rm_NOVLX:
8121 case X86::VMOVAPDZ256rm:
8122 case X86::VMOVUPDZ256rm:
8123 case X86::VMOVDQU8Z256rm:
8124 case X86::VMOVDQU16Z256rm:
8125 case X86::VMOVDQA32Z256rm:
8126 case X86::VMOVDQU32Z256rm:
8127 case X86::VMOVDQA64Z256rm:
8128 case X86::VMOVDQU64Z256rm:
8129 case X86::VMOVAPSZrm:
8130 case X86::VMOVUPSZrm:
8131 case X86::VMOVAPDZrm:
8132 case X86::VMOVUPDZrm:
8133 case X86::VMOVDQU8Zrm:
8134 case X86::VMOVDQU16Zrm:
8135 case X86::VMOVDQA32Zrm:
8136 case X86::VMOVDQU32Zrm:
8137 case X86::VMOVDQA64Zrm:
8138 case X86::VMOVDQU64Zrm:
8156 if (cast<ConstantSDNode>(Load1->
getOperand(1))->getZExtValue() != 1)
8160 if (isa<ConstantSDNode>(Load1->
getOperand(3)) &&
8162 Offset1 = cast<ConstantSDNode>(Load1->
getOperand(3))->getSExtValue();
8163 Offset2 = cast<ConstantSDNode>(Load2->
getOperand(3))->getSExtValue();
8171 int64_t Offset1, int64_t Offset2,
8172 unsigned NumLoads)
const {
8173 assert(Offset2 > Offset1);
8174 if ((Offset2 - Offset1) / 8 > 64)
8187 case X86::MMX_MOVD64rm:
8188 case X86::MMX_MOVQ64rm:
8200 }
else if (NumLoads) {
8255 FuseKind = FuseTest;
8268 case X86::TEST32i32:
8269 case X86::TEST64i32:
8270 case X86::TEST64ri32:
8275 case X86::TEST8ri_NOREX:
8287 case X86::AND64ri32:
8307 case X86::CMP64ri32:
8318 case X86::ADD16ri8_DB:
8319 case X86::ADD16ri_DB:
8322 case X86::ADD16rr_DB:
8326 case X86::ADD32ri8_DB:
8327 case X86::ADD32ri_DB:
8330 case X86::ADD32rr_DB:
8332 case X86::ADD64ri32:
8333 case X86::ADD64ri32_DB:
8335 case X86::ADD64ri8_DB:
8338 case X86::ADD64rr_DB:
8356 case X86::SUB64ri32:
8364 return FuseKind == FuseCmp || FuseKind == FuseInc;
8373 return FuseKind == FuseInc;
8379 assert(Cond.
size() == 1 &&
"Invalid X86 branch condition!");
8389 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
8390 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
8401 "X86-64 PIC uses RIP relative addressing");
8405 if (GlobalBaseReg != 0)
8412 X86FI->setGlobalBaseReg(GlobalBaseReg);
8421 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
8422 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
8423 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
8424 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
8425 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
8426 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
8427 { X86::MOVSSmr, X86::MOVSSmr, X86::MOVPDI2DImr },
8428 { X86::MOVSDrm, X86::MOVSDrm, X86::MOVQI2PQIrm },
8429 { X86::MOVSSrm, X86::MOVSSrm, X86::MOVDI2PDIrm },
8430 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
8431 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
8432 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
8433 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
8434 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
8435 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
8436 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
8437 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
8438 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
8440 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
8441 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
8442 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
8443 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
8444 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
8445 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
8446 { X86::VMOVSSmr, X86::VMOVSSmr, X86::VMOVPDI2DImr },
8447 { X86::VMOVSDrm, X86::VMOVSDrm, X86::VMOVQI2PQIrm },
8448 { X86::VMOVSSrm, X86::VMOVSSrm, X86::VMOVDI2PDIrm },
8449 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
8450 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
8451 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
8452 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
8453 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
8454 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
8455 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
8456 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
8457 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
8459 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
8460 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
8461 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
8462 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
8463 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
8464 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr },
8466 { X86::VMOVLPSZ128mr, X86::VMOVLPDZ128mr, X86::VMOVPQI2QIZmr },
8467 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
8468 { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
8469 { X86::VMOVNTPSZmr, X86::VMOVNTPDZmr, X86::VMOVNTDQZmr },
8470 { X86::VMOVSDZmr, X86::VMOVSDZmr, X86::VMOVPQI2QIZmr },
8471 { X86::VMOVSSZmr, X86::VMOVSSZmr, X86::VMOVPDI2DIZmr },
8472 { X86::VMOVSDZrm, X86::VMOVSDZrm, X86::VMOVQI2PQIZrm },
8473 { X86::VMOVSSZrm, X86::VMOVSSZrm, X86::VMOVDI2PDIZrm },
8474 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
8475 { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
8476 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
8477 { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
8478 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZr, X86::VPBROADCASTDZr },
8479 { X86::VBROADCASTSSZm, X86::VBROADCASTSSZm, X86::VPBROADCASTDZm },
8480 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
8481 { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
8482 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZr, X86::VPBROADCASTQZr },
8483 { X86::VBROADCASTSDZm, X86::VBROADCASTSDZm, X86::VPBROADCASTQZm },
8488 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
8489 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
8490 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
8491 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
8492 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
8493 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
8494 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
8495 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
8496 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
8497 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
8498 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
8499 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
8500 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
8501 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
8502 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
8503 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
8504 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
8505 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
8506 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
8507 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
8508 { X86::VBROADCASTF128, X86::VBROADCASTF128, X86::VBROADCASTI128 },
8514 { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr },
8515 { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm },
8516 { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr },
8517 { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr },
8518 { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm },
8519 { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr },
8520 { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm },
8521 { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr },
8522 { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr },
8523 { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm },
8524 { X86::VMOVAPSZmr, X86::VMOVAPDZmr, X86::VMOVDQA64Zmr, X86::VMOVDQA32Zmr },
8525 { X86::VMOVAPSZrm, X86::VMOVAPDZrm, X86::VMOVDQA64Zrm, X86::VMOVDQA32Zrm },
8526 { X86::VMOVAPSZrr, X86::VMOVAPDZrr, X86::VMOVDQA64Zrr, X86::VMOVDQA32Zrr },
8527 { X86::VMOVUPSZmr, X86::VMOVUPDZmr, X86::VMOVDQU64Zmr, X86::VMOVDQU32Zmr },
8528 { X86::VMOVUPSZrm, X86::VMOVUPDZrm, X86::VMOVDQU64Zrm, X86::VMOVDQU32Zrm },
8534 { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
8535 { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
8536 { X86::VANDPSZ128rm, X86::VANDPDZ128rm, X86::VPANDQZ128rm, X86::VPANDDZ128rm },
8537 { X86::VANDPSZ128rr, X86::VANDPDZ128rr, X86::VPANDQZ128rr, X86::VPANDDZ128rr },
8538 { X86::VORPSZ128rm, X86::VORPDZ128rm, X86::VPORQZ128rm, X86::VPORDZ128rm },
8539 { X86::VORPSZ128rr, X86::VORPDZ128rr, X86::VPORQZ128rr, X86::VPORDZ128rr },
8540 { X86::VXORPSZ128rm, X86::VXORPDZ128rm, X86::VPXORQZ128rm, X86::VPXORDZ128rm },
8541 { X86::VXORPSZ128rr, X86::VXORPDZ128rr, X86::VPXORQZ128rr, X86::VPXORDZ128rr },
8542 { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
8543 { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
8544 { X86::VANDPSZ256rm, X86::VANDPDZ256rm, X86::VPANDQZ256rm, X86::VPANDDZ256rm },
8545 { X86::VANDPSZ256rr, X86::VANDPDZ256rr, X86::VPANDQZ256rr, X86::VPANDDZ256rr },
8546 { X86::VORPSZ256rm, X86::VORPDZ256rm, X86::VPORQZ256rm, X86::VPORDZ256rm },
8547 { X86::VORPSZ256rr, X86::VORPDZ256rr, X86::VPORQZ256rr, X86::VPORDZ256rr },
8548 { X86::VXORPSZ256rm, X86::VXORPDZ256rm, X86::VPXORQZ256rm, X86::VPXORDZ256rm },
8549 { X86::VXORPSZ256rr, X86::VXORPDZ256rr, X86::VPXORQZ256rr, X86::VPXORDZ256rr },
8550 { X86::VANDNPSZrm, X86::VANDNPDZrm, X86::VPANDNQZrm, X86::VPANDNDZrm },
8551 { X86::VANDNPSZrr, X86::VANDNPDZrr, X86::VPANDNQZrr, X86::VPANDNDZrr },
8552 { X86::VANDPSZrm, X86::VANDPDZrm, X86::VPANDQZrm, X86::VPANDDZrm },
8553 { X86::VANDPSZrr, X86::VANDPDZrr, X86::VPANDQZrr, X86::VPANDDZrr },
8554 { X86::VORPSZrm, X86::VORPDZrm, X86::VPORQZrm, X86::VPORDZrm },
8555 { X86::VORPSZrr, X86::VORPDZrr, X86::VPORQZrr, X86::VPORDZrr },
8556 { X86::VXORPSZrm, X86::VXORPDZrm, X86::VPXORQZrm, X86::VPXORDZrm },
8557 { X86::VXORPSZrr, X86::VXORPDZrr, X86::VPXORQZrr, X86::VPXORDZrr },
8564 { X86::VANDNPSZ128rmk, X86::VANDNPDZ128rmk,
8565 X86::VPANDNQZ128rmk, X86::VPANDNDZ128rmk },
8566 { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
8567 X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
8568 { X86::VANDNPSZ128rrk, X86::VANDNPDZ128rrk,
8569 X86::VPANDNQZ128rrk, X86::VPANDNDZ128rrk },
8570 { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
8571 X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
8572 { X86::VANDPSZ128rmk, X86::VANDPDZ128rmk,
8573 X86::VPANDQZ128rmk, X86::VPANDDZ128rmk },
8574 { X86::VANDPSZ128rmkz, X86::VANDPDZ128rmkz,
8575 X86::VPANDQZ128rmkz, X86::VPANDDZ128rmkz },
8576 { X86::VANDPSZ128rrk, X86::VANDPDZ128rrk,
8577 X86::VPANDQZ128rrk, X86::VPANDDZ128rrk },
8578 { X86::VANDPSZ128rrkz, X86::VANDPDZ128rrkz,
8579 X86::VPANDQZ128rrkz, X86::VPANDDZ128rrkz },
8580 { X86::VORPSZ128rmk, X86::VORPDZ128rmk,
8581 X86::VPORQZ128rmk, X86::VPORDZ128rmk },
8582 { X86::VORPSZ128rmkz, X86::VORPDZ128rmkz,
8583 X86::VPORQZ128rmkz, X86::VPORDZ128rmkz },
8584 { X86::VORPSZ128rrk, X86::VORPDZ128rrk,
8585 X86::VPORQZ128rrk, X86::VPORDZ128rrk },
8586 { X86::VORPSZ128rrkz, X86::VORPDZ128rrkz,
8587 X86::VPORQZ128rrkz, X86::VPORDZ128rrkz },
8588 { X86::VXORPSZ128rmk, X86::VXORPDZ128rmk,
8589 X86::VPXORQZ128rmk, X86::VPXORDZ128rmk },
8590 { X86::VXORPSZ128rmkz, X86::VXORPDZ128rmkz,
8591 X86::VPXORQZ128rmkz, X86::VPXORDZ128rmkz },
8592 { X86::VXORPSZ128rrk, X86::VXORPDZ128rrk,
8593 X86::VPXORQZ128rrk, X86::VPXORDZ128rrk },
8594 { X86::VXORPSZ128rrkz, X86::VXORPDZ128rrkz,
8595 X86::VPXORQZ128rrkz, X86::VPXORDZ128rrkz },
8596 { X86::VANDNPSZ256rmk, X86::VANDNPDZ256rmk,
8597 X86::VPANDNQZ256rmk, X86::VPANDNDZ256rmk },
8598 { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
8599 X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
8600 { X86::VANDNPSZ256rrk, X86::VANDNPDZ256rrk,
8601 X86::VPANDNQZ256rrk, X86::VPANDNDZ256rrk },
8602 { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
8603 X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
8604 { X86::VANDPSZ256rmk, X86::VANDPDZ256rmk,
8605 X86::VPANDQZ256rmk, X86::VPANDDZ256rmk },
8606 { X86::VANDPSZ256rmkz, X86::VANDPDZ256rmkz,
8607 X86::VPANDQZ256rmkz, X86::VPANDDZ256rmkz },
8608 { X86::VANDPSZ256rrk, X86::VANDPDZ256rrk,
8609 X86::VPANDQZ256rrk, X86::VPANDDZ256rrk },
8610 { X86::VANDPSZ256rrkz, X86::VANDPDZ256rrkz,
8611 X86::VPANDQZ256rrkz, X86::VPANDDZ256rrkz },
8612 { X86::VORPSZ256rmk, X86::VORPDZ256rmk,
8613 X86::VPORQZ256rmk, X86::VPORDZ256rmk },
8614 { X86::VORPSZ256rmkz, X86::VORPDZ256rmkz,
8615 X86::VPORQZ256rmkz, X86::VPORDZ256rmkz },
8616 { X86::VORPSZ256rrk, X86::VORPDZ256rrk,
8617 X86::VPORQZ256rrk, X86::VPORDZ256rrk },
8618 { X86::VORPSZ256rrkz, X86::VORPDZ256rrkz,
8619 X86::VPORQZ256rrkz, X86::VPORDZ256rrkz },
8620 { X86::VXORPSZ256rmk, X86::VXORPDZ256rmk,
8621 X86::VPXORQZ256rmk, X86::VPXORDZ256rmk },
8622 { X86::VXORPSZ256rmkz, X86::VXORPDZ256rmkz,
8623 X86::VPXORQZ256rmkz, X86::VPXORDZ256rmkz },
8624 { X86::VXORPSZ256rrk, X86::VXORPDZ256rrk,
8625 X86::VPXORQZ256rrk, X86::VPXORDZ256rrk },
8626 { X86::VXORPSZ256rrkz, X86::VXORPDZ256rrkz,
8627 X86::VPXORQZ256rrkz, X86::VPXORDZ256rrkz },
8628 { X86::VANDNPSZrmk, X86::VANDNPDZrmk,
8629 X86::VPANDNQZrmk, X86::VPANDNDZrmk },
8630 { X86::VANDNPSZrmkz, X86::VANDNPDZrmkz,
8631 X86::VPANDNQZrmkz, X86::VPANDNDZrmkz },
8632 { X86::VANDNPSZrrk, X86::VANDNPDZrrk,
8633 X86::VPANDNQZrrk, X86::VPANDNDZrrk },
8634 { X86::VANDNPSZrrkz, X86::VANDNPDZrrkz,
8635 X86::VPANDNQZrrkz, X86::VPANDNDZrrkz },
8636 { X86::VANDPSZrmk, X86::VANDPDZrmk,
8637 X86::VPANDQZrmk, X86::VPANDDZrmk },
8638 { X86::VANDPSZrmkz, X86::VANDPDZrmkz,
8639 X86::VPANDQZrmkz, X86::VPANDDZrmkz },
8640 { X86::VANDPSZrrk, X86::VANDPDZrrk,
8641 X86::VPANDQZrrk, X86::VPANDDZrrk },
8642 { X86::VANDPSZrrkz, X86::VANDPDZrrkz,
8643 X86::VPANDQZrrkz, X86::VPANDDZrrkz },
8644 { X86::VORPSZrmk, X86::VORPDZrmk,
8645 X86::VPORQZrmk, X86::VPORDZrmk },
8646 { X86::VORPSZrmkz, X86::VORPDZrmkz,
8647 X86::VPORQZrmkz, X86::VPORDZrmkz },
8648 { X86::VORPSZrrk, X86::VORPDZrrk,
8649 X86::VPORQZrrk, X86::VPORDZrrk },
8650 { X86::VORPSZrrkz, X86::VORPDZrrkz,
8651 X86::VPORQZrrkz, X86::VPORDZrrkz },
8652 { X86::VXORPSZrmk, X86::VXORPDZrmk,
8653 X86::VPXORQZrmk, X86::VPXORDZrmk },
8654 { X86::VXORPSZrmkz, X86::VXORPDZrmkz,
8655 X86::VPXORQZrmkz, X86::VPXORDZrmkz },
8656 { X86::VXORPSZrrk, X86::VXORPDZrrk,
8657 X86::VPXORQZrrk, X86::VPXORDZrrk },
8658 { X86::VXORPSZrrkz, X86::VXORPDZrrkz,
8659 X86::VPXORQZrrkz, X86::VPXORDZrrkz },
8662 { X86::VANDNPSZ128rmb, X86::VANDNPDZ128rmb,
8663 X86::VPANDNQZ128rmb, X86::VPANDNDZ128rmb },
8664 { X86::VANDPSZ128rmb, X86::VANDPDZ128rmb,
8665 X86::VPANDQZ128rmb, X86::VPANDDZ128rmb },
8666 { X86::VORPSZ128rmb, X86::VORPDZ128rmb,
8667 X86::VPORQZ128rmb, X86::VPORDZ128rmb },
8668 { X86::VXORPSZ128rmb, X86::VXORPDZ128rmb,
8669 X86::VPXORQZ128rmb, X86::VPXORDZ128rmb },
8670 { X86::VANDNPSZ256rmb, X86::VANDNPDZ256rmb,
8671 X86::VPANDNQZ256rmb, X86::VPANDNDZ256rmb },
8672 { X86::VANDPSZ256rmb, X86::VANDPDZ256rmb,
8673 X86::VPANDQZ256rmb, X86::VPANDDZ256rmb },
8674 { X86::VORPSZ256rmb, X86::VORPDZ256rmb,
8675 X86::VPORQZ256rmb, X86::VPORDZ256rmb },
8676 { X86::VXORPSZ256rmb, X86::VXORPDZ256rmb,
8677 X86::VPXORQZ256rmb, X86::VPXORDZ256rmb },
8678 { X86::VANDNPSZrmb, X86::VANDNPDZrmb,
8679 X86::VPANDNQZrmb, X86::VPANDNDZrmb },
8680 { X86::VANDPSZrmb, X86::VANDPDZrmb,
8681 X86::VPANDQZrmb, X86::VPANDDZrmb },
8682 { X86::VANDPSZrmb, X86::VANDPDZrmb,
8683 X86::VPANDQZrmb, X86::VPANDDZrmb },
8684 { X86::VORPSZrmb, X86::VORPDZrmb,
8685 X86::VPORQZrmb, X86::VPORDZrmb },
8686 { X86::VXORPSZrmb, X86::VXORPDZrmb,
8687 X86::VPXORQZrmb, X86::VPXORDZrmb },
8688 { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
8689 X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
8690 { X86::VANDPSZ128rmbk, X86::VANDPDZ128rmbk,
8691 X86::VPANDQZ128rmbk, X86::VPANDDZ128rmbk },
8692 { X86::VORPSZ128rmbk, X86::VORPDZ128rmbk,
8693 X86::VPORQZ128rmbk, X86::VPORDZ128rmbk },
8694 { X86::VXORPSZ128rmbk, X86::VXORPDZ128rmbk,
8695 X86::VPXORQZ128rmbk, X86::VPXORDZ128rmbk },
8696 { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
8697 X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
8698 { X86::VANDPSZ256rmbk, X86::VANDPDZ256rmbk,
8699 X86::VPANDQZ256rmbk, X86::VPANDDZ256rmbk },
8700 { X86::VORPSZ256rmbk, X86::VORPDZ256rmbk,
8701 X86::VPORQZ256rmbk, X86::VPORDZ256rmbk },
8702 { X86::VXORPSZ256rmbk, X86::VXORPDZ256rmbk,
8703 X86::VPXORQZ256rmbk, X86::VPXORDZ256rmbk },
8704 { X86::VANDNPSZrmbk, X86::VANDNPDZrmbk,
8705 X86::VPANDNQZrmbk, X86::VPANDNDZrmbk },
8706 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
8707 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
8708 { X86::VANDPSZrmbk, X86::VANDPDZrmbk,
8709 X86::VPANDQZrmbk, X86::VPANDDZrmbk },
8710 { X86::VORPSZrmbk, X86::VORPDZrmbk,
8711 X86::VPORQZrmbk, X86::VPORDZrmbk },
8712 { X86::VXORPSZrmbk, X86::VXORPDZrmbk,
8713 X86::VPXORQZrmbk, X86::VPXORDZrmbk },
8714 { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
8715 X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
8716 { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
8717 X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
8718 { X86::VORPSZ128rmbkz, X86::VORPDZ128rmbkz,
8719 X86::VPORQZ128rmbkz, X86::VPORDZ128rmbkz },
8720 { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
8721 X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
8722 { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
8723 X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
8724 { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
8725 X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
8726 { X86::VORPSZ256rmbkz, X86::VORPDZ256rmbkz,
8727 X86::VPORQZ256rmbkz, X86::VPORDZ256rmbkz },
8728 { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
8729 X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
8730 { X86::VANDNPSZrmbkz, X86::VANDNPDZrmbkz,
8731 X86::VPANDNQZrmbkz, X86::VPANDNDZrmbkz },
8732 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
8733 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
8734 { X86::VANDPSZrmbkz, X86::VANDPDZrmbkz,
8735 X86::VPANDQZrmbkz, X86::VPANDDZrmbkz },
8736 { X86::VORPSZrmbkz, X86::VORPDZrmbkz,
8737 X86::VPORQZrmbkz, X86::VPORDZrmbkz },
8738 { X86::VXORPSZrmbkz, X86::VXORPDZrmbkz,
8739 X86::VPXORQZrmbkz, X86::VPXORDZrmbkz },
8745 static const uint16_t *
lookup(
unsigned opcode,
unsigned domain,
8747 for (
const uint16_t (&Row)[3] : Table)
8748 if (Row[domain-1] == opcode)
8756 for (
const uint16_t (&Row)[4] : Table)
8757 if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
8762 std::pair<uint16_t, uint16_t>
8766 uint16_t validDomains = 0;
8770 }
else if (
lookup(opcode, domain, ReplaceableInstrsAVX2)) {
8771 validDomains = Subtarget.
hasAVX2() ? 0xe : 0x6;
8772 }
else if (
lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
8774 }
else if (
lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) {
8775 validDomains = Subtarget.
hasDQI() ? 0xe : 0x8;
8776 }
else if (
const uint16_t *table =
lookupAVX512(opcode, domain,
8777 ReplaceableInstrsAVX512DQMasked)) {
8778 if (domain == 1 || (domain == 3 && table[3] == opcode))
8779 validDomains = Subtarget.
hasDQI() ? 0xa : 0x8;
8781 validDomains = Subtarget.
hasDQI() ? 0xc : 0x8;
8784 return std::make_pair(domain, validDomains);
8788 assert(Domain>0 && Domain<4 &&
"Invalid execution domain");
8790 assert(dom &&
"Not an SSE instruction");
8794 "256-bit vector operations only available in AVX2");
8801 if (table && Domain == 3 && table[3] == MI.
getOpcode())
8805 assert((Subtarget.
hasDQI() || Domain >= 3) &&
"Requires AVX-512DQ");
8809 if (table && Domain == 3 && (dom == 1 || table[3] == MI.
getOpcode()))
8813 assert((Subtarget.
hasDQI() || Domain >= 3) &&
"Requires AVX-512DQ");
8815 if (table && Domain == 3 && (dom == 1 || table[3] == MI.
getOpcode()))
8818 assert(table &&
"Cannot change domain");
8819 MI.
setDesc(
get(table[Domain - 1]));
8829 default:
return false;
8835 case X86::DIVSDrm_Int:
8837 case X86::DIVSDrr_Int:
8839 case X86::DIVSSrm_Int:
8841 case X86::DIVSSrr_Int:
8847 case X86::SQRTSDm_Int:
8849 case X86::SQRTSDr_Int:
8851 case X86::SQRTSSm_Int:
8853 case X86::SQRTSSr_Int:
8857 case X86::VDIVPDYrm:
8858 case X86::VDIVPDYrr:
8861 case X86::VDIVPSYrm:
8862 case X86::VDIVPSYrr:
8864 case X86::VDIVSDrm_Int:
8866 case X86::VDIVSDrr_Int:
8868 case X86::VDIVSSrm_Int:
8870 case X86::VDIVSSrr_Int:
8873 case X86::VSQRTPDYm:
8874 case X86::VSQRTPDYr:
8877 case X86::VSQRTPSYm:
8878 case X86::VSQRTPSYr:
8880 case X86::VSQRTSDm_Int:
8882 case X86::VSQRTSDr_Int:
8884 case X86::VSQRTSSm_Int:
8886 case X86::VSQRTSSr_Int:
8888 case X86::VDIVPDZ128rm:
8889 case X86::VDIVPDZ128rmb:
8890 case X86::VDIVPDZ128rmbk:
8891 case X86::VDIVPDZ128rmbkz:
8892 case X86::VDIVPDZ128rmk:
8893 case X86::VDIVPDZ128rmkz:
8894 case X86::VDIVPDZ128rr:
8895 case X86::VDIVPDZ128rrk:
8896 case X86::VDIVPDZ128rrkz:
8897 case X86::VDIVPDZ256rm:
8898 case X86::VDIVPDZ256rmb:
8899 case X86::VDIVPDZ256rmbk:
8900 case X86::VDIVPDZ256rmbkz:
8901 case X86::VDIVPDZ256rmk:
8902 case X86::VDIVPDZ256rmkz:
8903 case X86::VDIVPDZ256rr:
8904 case X86::VDIVPDZ256rrk:
8905 case X86::VDIVPDZ256rrkz:
8906 case X86::VDIVPDZrb:
8907 case X86::VDIVPDZrbk:
8908 case X86::VDIVPDZrbkz:
8909 case X86::VDIVPDZrm:
8910 case X86::VDIVPDZrmb:
8911 case X86::VDIVPDZrmbk:
8912 case X86::VDIVPDZrmbkz:
8913 case X86::VDIVPDZrmk:
8914 case X86::VDIVPDZrmkz:
8915 case X86::VDIVPDZrr:
8916 case X86::VDIVPDZrrk:
8917 case X86::VDIVPDZrrkz:
8918 case X86::VDIVPSZ128rm:
8919 case X86::VDIVPSZ128rmb:
8920 case X86::VDIVPSZ128rmbk:
8921 case X86::VDIVPSZ128rmbkz:
8922 case X86::VDIVPSZ128rmk:
8923 case X86::VDIVPSZ128rmkz:
8924 case X86::VDIVPSZ128rr:
8925 case X86::VDIVPSZ128rrk:
8926 case X86::VDIVPSZ128rrkz:
8927 case X86::VDIVPSZ256rm:
8928 case X86::VDIVPSZ256rmb:
8929 case X86::VDIVPSZ256rmbk:
8930 case X86::VDIVPSZ256rmbkz:
8931 case X86::VDIVPSZ256rmk:
8932 case X86::VDIVPSZ256rmkz:
8933 case X86::VDIVPSZ256rr:
8934 case X86::VDIVPSZ256rrk:
8935 case X86::VDIVPSZ256rrkz:
8936 case X86::VDIVPSZrb:
8937 case X86::VDIVPSZrbk:
8938 case X86::VDIVPSZrbkz:
8939 case X86::VDIVPSZrm:
8940 case X86::VDIVPSZrmb:
8941 case X86::VDIVPSZrmbk:
8942 case X86::VDIVPSZrmbkz:
8943 case X86::VDIVPSZrmk:
8944 case X86::VDIVPSZrmkz:
8945 case X86::VDIVPSZrr:
8946 case X86::VDIVPSZrrk:
8947 case X86::VDIVPSZrrkz:
8948 case X86::VDIVSDZrm:
8949 case X86::VDIVSDZrr:
8950 case X86::VDIVSDZrm_Int:
8951 case X86::VDIVSDZrm_Intk:
8952 case X86::VDIVSDZrm_Intkz:
8953 case X86::VDIVSDZrr_Int:
8954 case X86::VDIVSDZrr_Intk:
8955 case X86::VDIVSDZrr_Intkz:
8956 case X86::VDIVSDZrrb:
8957 case X86::VDIVSDZrrbk:
8958 case X86::VDIVSDZrrbkz:
8959 case X86::VDIVSSZrm:
8960 case X86::VDIVSSZrr:
8961 case X86::VDIVSSZrm_Int:
8962 case X86::VDIVSSZrm_Intk:
8963 case X86::VDIVSSZrm_Intkz:
8964 case X86::VDIVSSZrr_Int:
8965 case X86::VDIVSSZrr_Intk:
8966 case X86::VDIVSSZrr_Intkz:
8967 case X86::VDIVSSZrrb:
8968 case X86::VDIVSSZrrbk:
8969 case X86::VDIVSSZrrbkz:
8970 case X86::VSQRTPDZ128m:
8971 case X86::VSQRTPDZ128mb:
8972 case X86::VSQRTPDZ128mbk:
8973 case X86::VSQRTPDZ128mbkz:
8974 case X86::VSQRTPDZ128mk:
8975 case X86::VSQRTPDZ128mkz:
8976 case X86::VSQRTPDZ128r:
8977 case X86::VSQRTPDZ128rk:
8978 case X86::VSQRTPDZ128rkz:
8979 case X86::VSQRTPDZ256m:
8980 case X86::VSQRTPDZ256mb:
8981 case X86::VSQRTPDZ256mbk:
8982 case X86::VSQRTPDZ256mbkz:
8983 case X86::VSQRTPDZ256mk:
8984 case X86::VSQRTPDZ256mkz:
8985 case X86::VSQRTPDZ256r:
8986 case X86::VSQRTPDZ256rk:
8987 case X86::VSQRTPDZ256rkz:
8988 case X86::VSQRTPDZm:
8989 case X86::VSQRTPDZmb:
8990 case X86::VSQRTPDZmbk:
8991 case X86::VSQRTPDZmbkz:
8992 case X86::VSQRTPDZmk:
8993 case X86::VSQRTPDZmkz:
8994 case X86::VSQRTPDZr:
8995 case X86::VSQRTPDZrb:
8996 case X86::VSQRTPDZrbk:
8997 case X86::VSQRTPDZrbkz:
8998 case X86::VSQRTPDZrk:
8999 case X86::VSQRTPDZrkz:
9000 case X86::VSQRTPSZ128m:
9001 case X86::VSQRTPSZ128mb:
9002 case X86::VSQRTPSZ128mbk:
9003 case X86::VSQRTPSZ128mbkz:
9004 case X86::VSQRTPSZ128mk:
9005 case X86::VSQRTPSZ128mkz:
9006 case X86::VSQRTPSZ128r:
9007 case X86::VSQRTPSZ128rk:
9008 case X86::VSQRTPSZ128rkz:
9009 case X86::VSQRTPSZ256m:
9010 case X86::VSQRTPSZ256mb:
9011 case X86::VSQRTPSZ256mbk:
9012 case X86::VSQRTPSZ256mbkz:
9013 case X86::VSQRTPSZ256mk:
9014 case X86::VSQRTPSZ256mkz:
9015 case X86::VSQRTPSZ256r:
9016 case X86::VSQRTPSZ256rk:
9017 case X86::VSQRTPSZ256rkz:
9018 case X86::VSQRTPSZm:
9019 case X86::VSQRTPSZmb:
9020 case X86::VSQRTPSZmbk:
9021 case X86::VSQRTPSZmbkz:
9022 case X86::VSQRTPSZmk:
9023 case X86::VSQRTPSZmkz:
9024 case X86::VSQRTPSZr:
9025 case X86::VSQRTPSZrb:
9026 case X86::VSQRTPSZrbk:
9027 case X86::VSQRTPSZrbkz:
9028 case X86::VSQRTPSZrk:
9029 case X86::VSQRTPSZrkz:
9030 case X86::VSQRTSDZm:
9031 case X86::VSQRTSDZm_Int:
9032 case X86::VSQRTSDZm_Intk:
9033 case X86::VSQRTSDZm_Intkz:
9034 case X86::VSQRTSDZr:
9035 case X86::VSQRTSDZr_Int:
9036 case X86::VSQRTSDZr_Intk:
9037 case X86::VSQRTSDZr_Intkz:
9038 case X86::VSQRTSDZrb_Int:
9039 case X86::VSQRTSDZrb_Intk:
9040 case X86::VSQRTSDZrb_Intkz:
9041 case X86::VSQRTSSZm:
9042 case X86::VSQRTSSZm_Int:
9043 case X86::VSQRTSSZm_Intk:
9044 case X86::VSQRTSSZm_Intkz:
9045 case X86::VSQRTSSZr:
9046 case X86::VSQRTSSZr_Int:
9047 case X86::VSQRTSSZr_Intk:
9048 case X86::VSQRTSSZr_Intkz:
9049 case X86::VSQRTSSZrb_Int:
9050 case X86::VSQRTSSZrb_Intk:
9051 case X86::VSQRTSSZrb_Intkz:
9053 case X86::VGATHERDPDYrm:
9054 case X86::VGATHERDPDZ128rm:
9055 case X86::VGATHERDPDZ256rm:
9056 case X86::VGATHERDPDZrm:
9057 case X86::VGATHERDPDrm:
9058 case X86::VGATHERDPSYrm:
9059 case X86::VGATHERDPSZ128rm:
9060 case X86::VGATHERDPSZ256rm:
9061 case X86::VGATHERDPSZrm:
9062 case X86::VGATHERDPSrm:
9063 case X86::VGATHERPF0DPDm:
9064 case X86::VGATHERPF0DPSm:
9065 case X86::VGATHERPF0QPDm:
9066 case X86::VGATHERPF0QPSm:
9067 case X86::VGATHERPF1DPDm:
9068 case X86::VGATHERPF1DPSm:
9069 case X86::VGATHERPF1QPDm:
9070 case X86::VGATHERPF1QPSm:
9071 case X86::VGATHERQPDYrm:
9072 case X86::VGATHERQPDZ128rm:
9073 case X86::VGATHERQPDZ256rm:
9074 case X86::VGATHERQPDZrm:
9075 case X86::VGATHERQPDrm:
9076 case X86::VGATHERQPSYrm:
9077 case X86::VGATHERQPSZ128rm:
9078 case X86::VGATHERQPSZ256rm:
9079 case X86::VGATHERQPSZrm:
9080 case X86::VGATHERQPSrm:
9081 case X86::VPGATHERDDYrm:
9082 case X86::VPGATHERDDZ128rm:
9083 case X86::VPGATHERDDZ256rm:
9084 case X86::VPGATHERDDZrm:
9085 case X86::VPGATHERDDrm:
9086 case X86::VPGATHERDQYrm:
9087 case X86::VPGATHERDQZ128rm:
9088 case X86::VPGATHERDQZ256rm:
9089 case X86::VPGATHERDQZrm:
9090 case X86::VPGATHERDQrm:
9091 case X86::VPGATHERQDYrm:
9092 case X86::VPGATHERQDZ128rm:
9093 case X86::VPGATHERQDZ256rm:
9094 case X86::VPGATHERQDZrm:
9095 case X86::VPGATHERQDrm:
9096 case X86::VPGATHERQQYrm:
9097 case X86::VPGATHERQQZ128rm:
9098 case X86::VPGATHERQQZ256rm:
9099 case X86::VPGATHERQQZrm:
9100 case X86::VPGATHERQQrm:
9101 case X86::VSCATTERDPDZ128mr:
9102 case X86::VSCATTERDPDZ256mr:
9103 case X86::VSCATTERDPDZmr:
9104 case X86::VSCATTERDPSZ128mr:
9105 case X86::VSCATTERDPSZ256mr:
9106 case X86::VSCATTERDPSZmr:
9107 case X86::VSCATTERPF0DPDm:
9108 case X86::VSCATTERPF0DPSm:
9109 case X86::VSCATTERPF0QPDm:
9110 case X86::VSCATTERPF0QPSm:
9111 case X86::VSCATTERPF1DPDm:
9112 case X86::VSCATTERPF1DPSm:
9113 case X86::VSCATTERPF1QPDm:
9114 case X86::VSCATTERPF1QPSm:
9115 case X86::VSCATTERQPDZ128mr:
9116 case X86::VSCATTERQPDZ256mr:
9117 case X86::VSCATTERQPDZmr:
9118 case X86::VSCATTERQPSZ128mr:
9119 case X86::VSCATTERQPSZ256mr:
9120 case X86::VSCATTERQPSZmr:
9121 case X86::VPSCATTERDDZ128mr:
9122 case X86::VPSCATTERDDZ256mr:
9123 case X86::VPSCATTERDDZmr:
9124 case X86::VPSCATTERDQZ128mr:
9125 case X86::VPSCATTERDQZ256mr:
9126 case X86::VPSCATTERDQZmr:
9127 case X86::VPSCATTERQDZ128mr:
9128 case X86::VPSCATTERQDZ256mr:
9129 case X86::VPSCATTERQDZmr:
9130 case X86::VPSCATTERQQZ128mr:
9131 case X86::VPSCATTERQQZ256mr:
9132 case X86::VPSCATTERQQZmr:
9142 unsigned UseIdx)
const {
9149 "Reassociation needs binary operators");
9160 "Unexpected operand in reassociable instruction");
9204 case X86::VPANDDZ128rr:
9205 case X86::VPANDDZ256rr:
9206 case X86::VPANDDZrr:
9207 case X86::VPANDQZ128rr:
9208 case X86::VPANDQZ256rr:
9209 case X86::VPANDQZrr:
9212 case X86::VPORDZ128rr:
9213 case X86::VPORDZ256rr:
9215 case X86::VPORQZ128rr:
9216 case X86::VPORQZ256rr:
9220 case X86::VPXORDZ128rr:
9221 case X86::VPXORDZ256rr:
9222 case X86::VPXORDZrr:
9223 case X86::VPXORQZ128rr:
9224 case X86::VPXORQZ256rr:
9225 case X86::VPXORQZrr:
9228 case X86::VANDPDYrr:
9229 case X86::VANDPSYrr:
9230 case X86::VANDPDZ128rr:
9231 case X86::VANDPSZ128rr:
9232 case X86::VANDPDZ256rr:
9233 case X86::VANDPSZ256rr:
9234 case X86::VANDPDZrr:
9235 case X86::VANDPSZrr:
9240 case X86::VORPDZ128rr:
9241 case X86::VORPSZ128rr:
9242 case X86::VORPDZ256rr:
9243 case X86::VORPSZ256rr:
9248 case X86::VXORPDYrr:
9249 case X86::VXORPSYrr:
9250 case X86::VXORPDZ128rr:
9251 case X86::VXORPSZ128rr:
9252 case X86::VXORPDZ256rr:
9253 case X86::VXORPSZ256rr:
9254 case X86::VXORPDZrr:
9255 case X86::VXORPSZrr:
9276 case X86::VPADDBYrr:
9277 case X86::VPADDWYrr:
9278 case X86::VPADDDYrr:
9279 case X86::VPADDQYrr:
9280 case X86::VPADDBZ128rr:
9281 case X86::VPADDWZ128rr:
9282 case X86::VPADDDZ128rr:
9283 case X86::VPADDQZ128rr:
9284 case X86::VPADDBZ256rr:
9285 case X86::VPADDWZ256rr:
9286 case X86::VPADDDZ256rr:
9287 case X86::VPADDQZ256rr:
9288 case X86::VPADDBZrr:
9289 case X86::VPADDWZrr:
9290 case X86::VPADDDZrr:
9291 case X86::VPADDQZrr:
9292 case X86::VPMULLWrr:
9293 case X86::VPMULLWYrr:
9294 case X86::VPMULLWZ128rr:
9295 case X86::VPMULLWZ256rr:
9296 case X86::VPMULLWZrr:
9297 case X86::VPMULLDrr:
9298 case X86::VPMULLDYrr:
9299 case X86::VPMULLDZ128rr:
9300 case X86::VPMULLDZ256rr:
9301 case X86::VPMULLDZrr:
9302 case X86::VPMULLQZ128rr:
9303 case X86::VPMULLQZ256rr:
9304 case X86::VPMULLQZrr:
9316 case X86::VMAXCPDrr:
9317 case X86::VMAXCPSrr:
9318 case X86::VMAXCPDYrr:
9319 case X86::VMAXCPSYrr:
9320 case X86::VMAXCPDZ128rr:
9321 case X86::VMAXCPSZ128rr:
9322 case X86::VMAXCPDZ256rr:
9323 case X86::VMAXCPSZ256rr:
9324 case X86::VMAXCPDZrr:
9325 case X86::VMAXCPSZrr:
9326 case X86::VMAXCSDrr:
9327 case X86::VMAXCSSrr:
9328 case X86::VMAXCSDZrr:
9329 case X86::VMAXCSSZrr:
9330 case X86::VMINCPDrr:
9331 case X86::VMINCPSrr:
9332 case X86::VMINCPDYrr:
9333 case X86::VMINCPSYrr:
9334 case X86::VMINCPDZ128rr:
9335 case X86::VMINCPSZ128rr:
9336 case X86::VMINCPDZ256rr:
9337 case X86::VMINCPSZ256rr:
9338 case X86::VMINCPDZrr:
9339 case X86::VMINCPSZrr:
9340 case X86::VMINCSDrr:
9341 case X86::VMINCSSrr:
9342 case X86::VMINCSDZrr:
9343 case X86::VMINCSSZrr:
9355 case X86::VADDPDYrr:
9356 case X86::VADDPSYrr:
9357 case X86::VADDPDZ128rr:
9358 case X86::VADDPSZ128rr:
9359 case X86::VADDPDZ256rr:
9360 case X86::VADDPSZ256rr:
9361 case X86::VADDPDZrr:
9362 case X86::VADDPSZrr:
9365 case X86::VADDSDZrr:
9366 case X86::VADDSSZrr:
9369 case X86::VMULPDYrr:
9370 case X86::VMULPSYrr:
9371 case X86::VMULPDZ128rr:
9372 case X86::VMULPSZ128rr:
9373 case X86::VMULPDZ256rr:
9374 case X86::VMULPSZ256rr:
9375 case X86::VMULPDZrr:
9376 case X86::VMULPSZrr:
9379 case X86::VMULSDZrr:
9380 case X86::VMULSSZrr:
9399 "Unexpected instruction type for reassociation");
9406 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
9407 "Must have dead EFLAGS operand in reassociable instruction");
9409 "Must have dead EFLAGS operand in reassociable instruction");
9415 "Unexpected operand in reassociable instruction");
9417 "Unexpected operand in reassociable instruction");
9427 std::pair<unsigned, unsigned>
9429 return std::make_pair(TF, 0u);
9434 using namespace X86II;
9435 static const std::pair<unsigned, const char *>
TargetFlags[] = {
9462 case X86::TCRETURNdi:
9463 case X86::TCRETURNmi:
9464 case X86::TCRETURNri:
9465 case X86::TCRETURNdi64:
9466 case X86::TCRETURNmi64:
9467 case X86::TCRETURNri64:
9471 case X86::TAILJMPd64:
9472 case X86::TAILJMPm64:
9473 case X86::TAILJMPr64:
9474 case X86::TAILJMPm64_REX:
9475 case X86::TAILJMPr64_REX:
9507 if (GlobalBaseReg == 0)
9525 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r),
PC).addImm(0);
9539 StringRef getPassName()
const override {
9540 return "X86 PIC Global Base Reg Initialization";
9580 bool Changed =
false;
9585 switch (I->getOpcode()) {
9586 case X86::TLS_base_addr32:
9587 case X86::TLS_base_addr64:
9589 I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
9591 I = SetRegister(*I, &TLSBaseAddrReg);
9602 Changed |= VisitNode(*I, TLSBaseAddrReg);
9611 unsigned TLSBaseAddrReg) {
9620 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
9621 .addReg(TLSBaseAddrReg);
9634 const bool is64Bit = STI.
is64Bit();
9640 ? &X86::GR64RegClass
9641 : &X86::GR32RegClass);
9647 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
9648 .addReg(is64Bit ? X86::RAX : X86::EAX);
9653 StringRef getPassName()
const override {
9654 return "Local Dynamic TLS Access Clean-up";
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
unsigned GetCondBranchFromCond(CondCode CC)
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
static bool hasUndefRegUpdate(unsigned Opcode)
static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, unsigned Reg)
Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
static Type * getDoubleTy(LLVMContext &C)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI)
Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
MO_TLSLDM - Represents the offset into the global offset table at which.
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool shouldScheduleAdjacent(const MachineInstr &First, const MachineInstr &Second) const override
static unsigned getTruncatedShiftCount(MachineInstr &MI, unsigned ShiftAmtOperandIdx)
Check whether the shift count for a machine operand is non-zero.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const X86InstrInfo * getInstrInfo() const override
CondCode getCondFromCMovOpc(unsigned Opc)
Return condition code of a CMov opcode.
MachineDomTreeNode * getRootNode() const
const X86FrameLowering * getFrameLowering() const override
MO_TLSGD - Represents the offset into the global offset table at which.
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
bool isHighLatencyDef(int opc) const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update...
static cl::opt< bool > ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
static X86::CondCode getCondFromBranchOpc(unsigned BrOpc)
static unsigned getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
static const X86InstrFMA3Group * getFMA3Group(unsigned Opcode)
Returns a reference to a group of FMA3 opcodes to where the given Opcode is included.
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register rea...
unsigned getNumOperands() const
Return the number of values used by this operation.
static MachineInstr * FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII)
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
const SDValue & getOperand(unsigned Num) const
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
iterator_range< mop_iterator > operands()
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
static bool isAligned(const Value *Base, const APInt &Offset, unsigned Align, const DataLayout &DL)
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
static bool expandNOVLXStore(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx)
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
static MachineInstr * MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI)
bool findFMA3CommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns true if the routine could find two commutable operands in the given FMA instruction MI...
static cl::opt< unsigned > UndefRegClearance("undef-reg-clearance", cl::desc("How many idle instructions we would like before ""certain undef register reads"), cl::init(128), cl::Hidden)
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
AnalysisUsage & addRequired()
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
static Type * getFloatTy(LLVMContext &C)
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
MachineFunction & getMachineFunction() const
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
static bool hasPartialRegUpdate(unsigned Opcode)
Return true for all instructions that only update the first 32 or 64-bits of the destination register...
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
MachineMemOperand ** mmo_iterator
static int getRegClass(RegisterKind Is, unsigned RegWidth)
unsigned getNumLocalDynamicTLSAccesses() const
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const
Wraps up getting a CFI index and building a MachineInstr for it.
The memory access is dereferenceable (i.e., doesn't trap).
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
std::pair< MachineInstr::mmo_iterator, MachineInstr::mmo_iterator > extractLoadMemRefs(MachineInstr::mmo_iterator Begin, MachineInstr::mmo_iterator End)
extractLoadMemRefs - Allocate an array and populate it with just the load information from the given ...
bool hasDebugInfo() const
Returns true if valid debug info is present.
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction...
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
static const uint16_t * lookup(unsigned opcode, unsigned domain, ArrayRef< uint16_t[3]> Table)
static bool isMem(const MachineInstr &MI, unsigned Op)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static const uint16_t ReplaceableInstrsAVX512DQMasked[][4]
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
uint16_t StackAdjustment(const RuntimeFunction &RF)
StackAdjustment - calculated stack adjustment in words.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineBasicBlock & front() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static unsigned getAlignment(GlobalVariable *GV)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
static X86::CondCode getCondFromSETOpc(unsigned Opc)
Return condition code of a SET opcode.
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
static def_instr_iterator def_instr_end()
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
static const uint16_t ReplaceableInstrsAVX512DQ[][4]
Base class for the actual dominator tree node.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr &OI)
Check whether the first instruction, whose only purpose is to update flags, can be made redundant...
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp, LiveVariables *LV) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg, const X86Subtarget &Subtarget)
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
unsigned getReg132Opcode() const
Returns the 132 form of FMA register opcode.
unsigned getUndefRegState(bool B)
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been <def>ined and not <kill>ed as of just before Before...
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget)
size_t size() const
size - Get the array size.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
reverse_iterator rbegin()
Instances of this class represent a single low-level machine instruction.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
static X86::CondCode isUseDefConvertible(MachineInstr &MI)
Check whether the use can be converted to remove a comparison against zero.
unsigned getDeadRegState(bool B)
mmo_iterator memoperands_end() const
unsigned getGlobalBaseReg() const
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned getDefRegState(bool B)
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isFrameLoadOpcode(int Opcode)
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
static unsigned getCommutedVPERMV3Opcode(unsigned Opcode)
initializer< Ty > init(const Ty &Val)
unsigned getTargetFlags() const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
AddrNumOperands - Total number of operands in a memory reference.
unsigned getMem132Opcode() const
Returns the 132 form of FMA memory opcode.
unsigned getReg213Opcode() const
Returns the 213 form of FMA register opcode.
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction. ...
unsigned const MachineRegisterInfo * MRI
static bool isTruncatedShiftCountForLEA(unsigned ShAmt)
Check whether the given shift count is appropriate can be represented by a LEA instruction.
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned char TargetFlags=0)
CodeModel::Model getCodeModel() const
Returns the code model.
The instances of the Type class are immutable: once they are created, they are never changed...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static const uint16_t ReplaceableInstrs[][3]
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
This is an important base class in LLVM.
static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
static void expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static bool is64Bit(const char *name)
const MachineOperand & getOperand(unsigned i) const
static bool expandNOVLXLoad(MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx)
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static cl::opt< bool > PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden)
unsigned getMem231Opcode() const
Returns the 231 form of FMA memory opcode.
static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
This determines which of three possible cases of a three source commute the source indexes correspond...
Register is known to be fully dead.
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle): Remove Defs, add uses.
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset]...
X86InstrInfo(X86Subtarget &STI)
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
bool isPositionIndependent() const
bool contains(unsigned Reg) const
Returns true if register Reg is contained in the set.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
static void addOperands(MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0)
FunctionPass class - This class is used to implement most global optimizations.
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
#define VPERM_CASES(Suffix)
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute any additional adjustment needed to the offset to the start of the memory op...
self_iterator getIterator()
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned getReg231Opcode() const
Returns the 231 form of FMA register opcode.
bool empty() const
empty - Check if the array is empty.
This class is used to group {132, 213, 231} forms of FMA opcodes together.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
static Constant * getAllOnesValue(Type *Ty)
Get the all ones value.
Register is known to be (at least partially) live.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
bool isPICStyleGOT() const
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc. ...
succ_iterator succ_begin()
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand=false)
Return a set opcode for the given condition and whether it has a memory operand.
unsigned getSubReg() const
EVT - Extended Value Type.
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
static const uint16_t * lookupAVX512(unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table)
static bool isHReg(unsigned Reg)
Test if the given register is a physical h register.
void setIsKill(bool Val=true)
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS c...
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
virtual const TargetFrameLowering * getFrameLowering() const
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
#define VPERM_CASES_BROADCAST(Suffix)
Iterator for intrusive lists based on ilist_node.
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
void setOpcode(unsigned Op)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
MachineOperand class - Representation of each machine instruction operand.
static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
static const MachineInstrBuilder & addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2)
addRegReg - This function is used to add a memory reference of the form: [Reg + Reg].
Information about stack frame layout on the target.
bool isIntrinsic() const
Returns true iff the group of FMA opcodes holds intrinsic opcodes.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Represents one node in the SelectionDAG.
bool isKMergeMasked(uint64_t TSFlags)
isKMergedMasked - Is this a merge masked instruction.
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void getNoopForMachoTarget(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF)
Check if LoadMI is a partial register load that we can't fold into MI because the latter uses content...
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given condition, register size in bytes, and operand type...
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
static MachineBasicBlock * getFallThroughMBB(MachineBasicBlock *MBB, MachineBasicBlock *TBB)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static rm_iterator rm_end()
Returns the last rm_iterator.
CATCHRET - Represents a return from a catch block funclet.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when Inst has reassociable operands in the same MBB.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
bool isRegOpcodeFromGroup(unsigned Opcode) const
Returns true iff the given Opcode is a register opcode from the groups of FMA opcodes.
def_instr_iterator def_instr_begin(unsigned RegNo) const
unsigned getMem213Opcode() const
Returns the 213 form of FMA memory opcode.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
A set of live physical registers with functions to track liveness when walking backward/forward throu...
static const MachineInstrBuilder & addOffset(const MachineInstrBuilder &MIB, int Offset)
static unsigned getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
Register liveness not decidable from local neighborhood.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
bool isCall(QueryType Type=AnyInBundle) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static MachineInstr * FuseInst(MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0)
static cl::opt< unsigned > PartialRegUpdateClearance("partial-reg-update-clearance", cl::desc("Clearance between two register writes ""for inserting XOR to avoid partial ""register update"), cl::init(64), cl::Hidden)
void setSubReg(unsigned subReg)
The memory access always returns the same value (or traps).
bool isKMasked(uint64_t TSFlags)
isKMasked - Is this a masked instruction.
iterator find(const KeyT &Val)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool isUnalignedMem16Slow() const
static rm_iterator rm_begin()
Returns rm_iterator pointing to the first entry of OpcodeToGroup map with a register FMA opcode havin...
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool canRealignStack(const MachineFunction &MF) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
bool isTailCall(const MachineInstr &Inst) const override
unsigned getReg() const
getReg - Returns the register number.
std::pair< MachineInstr::mmo_iterator, MachineInstr::mmo_iterator > extractStoreMemRefs(MachineInstr::mmo_iterator Begin, MachineInstr::mmo_iterator End)
extractStoreMemRefs - Allocate an array and populate it with just the store information from the give...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
std::vector< DomTreeNodeBase< NodeT > * >::iterator iterator
static const uint16_t ReplaceableInstrsAVX2[][3]
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
mop_iterator operands_begin()
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static VectorType * get(Type *ElementType, unsigned NumElements)
This static method is the primary way to construct an VectorType.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
MachineInstrBundleIterator< const MachineInstr > const_iterator
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static bool isDefConvertible(MachineInstr &MI)
Check whether the definition can be converted to remove a comparison against zero.
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
bool callRegIndirect() const
StringRef - Represent a constant reference to a string, i.e.
vt_iterator vt_begin() const
vt_begin / vt_end - Loop over all of the value types that can be represented by values in this regist...
MachineModuleInfo & getMMI() const
static const uint16_t ReplaceableInstrsAVX512[][4]
static bool isFrameStoreOpcode(int Opcode)
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction...
static X86::CondCode getSwappedCondition(X86::CondCode CC)
Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such t...
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
static bool Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register...
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
static MachineOperand CreateFI(int Idx)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
static bool isCommutableVPERMV3Instruction(unsigned Opcode)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
static cl::opt< bool > NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"))
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool usesWindowsCFI() const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...