LLVM  4.0.0
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
16 
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
23 #include "llvm/IR/DataLayout.h"
25 #include <string>
26 
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
29 
30 namespace llvm {
31 class GlobalValue;
32 class StringRef;
33 class Triple;
34 
36 public:
37  enum ARMProcFamilyEnum : uint8_t {
49  };
50 
51 protected:
52  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
54 
55  bool HasV8_1aOps = false;
56  bool HasV8_2aOps = false;
57 
58  bool HasFPARMv8 = false;
59  bool HasNEON = false;
60  bool HasCrypto = false;
61  bool HasCRC = false;
62  bool HasLSE = false;
63  bool HasRAS = false;
64  bool HasPerfMon = false;
65  bool HasFullFP16 = false;
66  bool HasSPE = false;
67 
68  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
69  bool HasZeroCycleRegMove = false;
70 
71  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
72  bool HasZeroCycleZeroing = false;
73 
74  // StrictAlign - Disallow unaligned memory accesses.
75  bool StrictAlign = false;
76  bool UseAA = false;
78  bool BalanceFPOps = false;
79  bool CustomAsCheapAsMove = false;
80  bool UsePostRAScheduler = false;
82  bool Paired128IsSlow = false;
84  bool HasArithmeticBccFusion = false;
85  bool HasArithmeticCbzFusion = false;
87  bool UseRSqrt = false;
88  uint8_t MaxInterleaveFactor = 2;
90  uint16_t CacheLineSize = 0;
91  uint16_t PrefetchDistance = 0;
92  uint16_t MinPrefetchStride = 1;
93  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
94  unsigned PrefFunctionAlignment = 0;
95  unsigned PrefLoopAlignment = 0;
96  unsigned MaxJumpTableSize = 0;
97 
98  // ReserveX18 - X18 is not available as a general purpose register.
99  bool ReserveX18;
100 
101  bool IsLittle;
102 
103  /// TargetTriple - What processor and OS we're targeting.
105 
110  /// Gather the accessor points to GlobalISel-related APIs.
111  /// This is used to avoid ifndefs spreading around while GISel is
112  /// an optional library.
113  std::unique_ptr<GISelAccessor> GISel;
114 
115 private:
116  /// initializeSubtargetDependencies - Initializes using CPUString and the
117  /// passed in feature string so that we can use initializer lists for
118  /// subtarget initialization.
119  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
120  StringRef CPUString);
121 
122  /// Initialize properties based on the selected processor family.
123  void initializeProperties();
124 
125 public:
126  /// This constructor initializes the data members to match that
127  /// of the specified triple.
128  AArch64Subtarget(const Triple &TT, const std::string &CPU,
129  const std::string &FS, const TargetMachine &TM,
130  bool LittleEndian);
131 
132  /// This object will take onwership of \p GISelAccessor.
134  this->GISel.reset(&GISel);
135  }
136 
138  return &TSInfo;
139  }
140  const AArch64FrameLowering *getFrameLowering() const override {
141  return &FrameLowering;
142  }
143  const AArch64TargetLowering *getTargetLowering() const override {
144  return &TLInfo;
145  }
146  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
147  const AArch64RegisterInfo *getRegisterInfo() const override {
148  return &getInstrInfo()->getRegisterInfo();
149  }
150  const CallLowering *getCallLowering() const override;
151  const InstructionSelector *getInstructionSelector() const override;
152  const LegalizerInfo *getLegalizerInfo() const override;
153  const RegisterBankInfo *getRegBankInfo() const override;
154  const Triple &getTargetTriple() const { return TargetTriple; }
155  bool enableMachineScheduler() const override { return true; }
156  bool enablePostRAScheduler() const override {
157  return UsePostRAScheduler;
158  }
159 
160  /// Returns ARM processor family.
161  /// Avoid this function! CPU specifics should be kept local to this class
162  /// and preferably modeled with SubtargetFeatures or properties in
163  /// initializeProperties().
165  return ARMProcFamily;
166  }
167 
168  bool hasV8_1aOps() const { return HasV8_1aOps; }
169  bool hasV8_2aOps() const { return HasV8_2aOps; }
170 
171  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
172 
173  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
174 
175  bool requiresStrictAlign() const { return StrictAlign; }
176 
177  bool isXRaySupported() const override { return true; }
178 
179  bool isX18Reserved() const { return ReserveX18; }
180  bool hasFPARMv8() const { return HasFPARMv8; }
181  bool hasNEON() const { return HasNEON; }
182  bool hasCrypto() const { return HasCrypto; }
183  bool hasCRC() const { return HasCRC; }
184  bool hasLSE() const { return HasLSE; }
185  bool hasRAS() const { return HasRAS; }
186  bool balanceFPOps() const { return BalanceFPOps; }
189  }
192  bool isPaired128Slow() const { return Paired128IsSlow; }
195  }
198  bool useRSqrt() const { return UseRSqrt; }
199  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
202  }
203  unsigned getCacheLineSize() const { return CacheLineSize; }
204  unsigned getPrefetchDistance() const { return PrefetchDistance; }
205  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
206  unsigned getMaxPrefetchIterationsAhead() const {
208  }
209  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
210  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
211 
212  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
213 
214  /// CPU has TBI (top byte of addresses is ignored during HW address
215  /// translation) and OS enables it.
216  bool supportsAddressTopByteIgnored() const;
217 
218  bool hasPerfMon() const { return HasPerfMon; }
219  bool hasFullFP16() const { return HasFullFP16; }
220  bool hasSPE() const { return HasSPE; }
221 
222  bool isLittleEndian() const { return IsLittle; }
223 
224  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
225  bool isTargetIOS() const { return TargetTriple.isiOS(); }
226  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
227  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
228  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
229 
230  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
231  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
232  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
233 
234  bool useAA() const override { return UseAA; }
235 
236  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
237  /// that still makes it profitable to inline the call.
238  unsigned getMaxInlineSizeThreshold() const { return 64; }
239 
240  /// ParseSubtargetFeatures - Parses features string setting specified
241  /// subtarget options. Definition of function is auto generated by tblgen.
243 
244  /// ClassifyGlobalReference - Find the target operand flags that describe
245  /// how a global value should be referenced for the current subtarget.
246  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
247  const TargetMachine &TM) const;
248 
249  /// This function returns the name of a function which has an interface
250  /// like the non-standard bzero function, if such a function exists on
251  /// the current subtarget and it is considered prefereable over
252  /// memset with zero passed as the second argument. Otherwise it
253  /// returns null.
254  const char *getBZeroEntry() const;
255 
257  unsigned NumRegionInstrs) const override;
258 
259  bool enableEarlyIfConversion() const override;
260 
261  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
262 };
263 } // End llvm namespace
264 
265 #endif
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
Definition: GISelAccessor.h:29
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool isTargetAndroid() const
bool requiresStrictAlign() const
unsigned getVectorInsertExtractBaseCost() const
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:575
bool hasZeroCycleRegMove() const
const InstructionSelector * getInstructionSelector() const override
bool hasZeroCycleZeroing() const
bool hasCustomCheapAsMoveHandling() const
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
const CallLowering * getCallLowering() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:593
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:540
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool isPaired128Slow() const
Holds all the information related to register banks.
unsigned getMaximumJumpTableSize() const
bool useAlternateSExtLoadCVTF32Pattern() const
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
unsigned getMinPrefetchStride() const
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:550
const AArch64RegisterInfo * getRegisterInfo() const override
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
bool useAA() const override
unsigned getPrefetchDistance() const
bool enableMachineScheduler() const override
const Triple & getTargetTriple() const
bool enableEarlyIfConversion() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:436
const AArch64TargetLowering * getTargetLowering() const override
bool isXRaySupported() const override
unsigned getMaxPrefetchIterationsAhead() const
bool isLittleEndian() const
void setGISelAccessor(GISelAccessor &GISel)
This object will take onwership of GISelAccessor.
bool isMisaligned128StoreSlow() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:570
bool predictableSelectIsExpensive() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:455
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
AArch64InstrInfo InstrInfo
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getMaxInterleaveFactor() const
const char * getBZeroEntry() const
This function returns the name of a function which has an interface like the non-standard bzero funct...
unsigned getCacheLineSize() const
bool enablePostRAScheduler() const override
bool hasArithmeticBccFusion() const
bool isTargetDarwin() const
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
bool isTargetWindows() const
bool hasArithmeticCbzFusion() const
AArch64FrameLowering FrameLowering
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
const AArch64InstrInfo * getInstrInfo() const override
const RegisterBankInfo * getRegBankInfo() const override
unsigned getPrefFunctionAlignment() const
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
unsigned getPrefLoopAlignment() const
AArch64TargetLowering TLInfo
std::unique_ptr< GISelAccessor > GISel
Gather the accessor points to GlobalISel-related APIs.