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| static cl::opt< bool > | DisablePostRASched ("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler")) |
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| static cl::opt< bool > | DisableBranchFold ("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding")) |
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| static cl::opt< bool > | DisableTailDuplicate ("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication")) |
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| static cl::opt< bool > | DisableEarlyTailDup ("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication")) |
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| static cl::opt< bool > | DisableBlockPlacement ("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement")) |
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| static cl::opt< bool > | EnableBlockPlacementStats ("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats")) |
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| static cl::opt< bool > | DisableSSC ("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring")) |
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| static cl::opt< bool > | DisableMachineDCE ("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination")) |
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| static cl::opt< bool > | DisableEarlyIfConversion ("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion")) |
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| static cl::opt< bool > | DisableMachineLICM ("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM")) |
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| static cl::opt< bool > | DisableMachineCSE ("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination")) |
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| static cl::opt< cl::boolOrDefault > | OptimizeRegAlloc ("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path.")) |
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| static cl::opt< bool > | DisablePostRAMachineLICM ("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM")) |
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| static cl::opt< bool > | DisableMachineSink ("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking")) |
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| static cl::opt< bool > | DisableLSR ("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass")) |
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| static cl::opt< bool > | DisableConstantHoisting ("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting")) |
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| static cl::opt< bool > | DisableCGP ("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare")) |
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| static cl::opt< bool > | DisableCopyProp ("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass")) |
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| static cl::opt< bool > | DisablePartialLibcallInlining ("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining")) |
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| static cl::opt< bool > | EnableImplicitNullChecks ("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false)) |
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| static cl::opt< bool > | PrintLSR ("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass")) |
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| static cl::opt< bool > | PrintISelInput ("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass")) |
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| static cl::opt< bool > | PrintGCInfo ("print-gc", cl::Hidden, cl::desc("Dump garbage collector data")) |
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| static cl::opt< bool > | VerifyMachineCode ("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(false), cl::ZeroOrMore) |
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| static cl::opt< std::string > | PrintMachineInstrs ("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified")) |
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| static cl::opt< int > | EnableGlobalISelAbort ("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection ""fails to lower/select an instruction: 0 disable the abort, ""1 enable the abort, and ""2 disable the abort but emit a diagnostic on failure"), cl::init(1)) |
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| cl::opt< bool > | MISchedPostRA ("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")) |
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| static cl::opt< bool > | EarlyLiveIntervals ("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline")) |
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| static cl::opt< CFLAAType > | UseCFLAA ("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None,"none","Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard,"steens","Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen,"anders","Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both,"both","Enable both variants of CFL-AA"))) |
| |
| static RegisterRegAlloc | defaultRegAlloc ("default","pick register allocator based on -O option", useDefaultRegisterAllocator) |
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static cl::opt
< RegisterRegAlloc::FunctionPassCtor,
false, RegisterPassParser
< RegisterRegAlloc > > | RegAlloc ("regalloc", cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use")) |
| | -regalloc=... command line option. More...
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Allow standard passes to be disabled by the command line, regardless of who is adding the pass.
StandardID is the pass identified in the standard pass pipeline and provided to addPass(). It may be a target-specific ID in the case that the target directly adds its own pass, but in that case we harmlessly fall through.
TargetID is the pass that the target has configured to override StandardID.
StandardID may be a pseudo ID. In that case TargetID is the name of the real pass to run. This allows multiple options to control a single pass depending on where in the pipeline that pass is added.
Definition at line 157 of file TargetPassConfig.cpp.
References applyDisable(), llvm::BranchFolderPassID, llvm::DeadMachineInstructionElimID, DisableBlockPlacement, DisableBranchFold, DisableCopyProp, DisableEarlyIfConversion, DisableEarlyTailDup, DisableMachineCSE, DisableMachineDCE, DisableMachineLICM, DisableMachineSink, DisablePostRAMachineLICM, DisablePostRASched, DisableSSC, DisableTailDuplicate, llvm::EarlyIfConverterID, llvm::TargetPassConfig::EarlyTailDuplicateID, llvm::MachineBlockPlacementID, llvm::MachineCopyPropagationID, llvm::MachineCSEID, llvm::MachineLICMID, llvm::MachineSinkingID, llvm::TargetPassConfig::PostRAMachineLICMID, llvm::PostRASchedulerID, llvm::StackSlotColoringID, and llvm::TailDuplicateID.
Referenced by llvm::TargetPassConfig::addPass(), and llvm::TargetPassConfig::isPassSubstitutedOrOverridden().