LLVM  4.0.0
NVPTXFrameLowering.cpp
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1 //=======- NVPTXFrameLowering.cpp - NVPTX Frame Information ---*- C++ -*-=====//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the NVPTX implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXFrameLowering.h"
15 #include "NVPTX.h"
16 #include "NVPTXRegisterInfo.h"
17 #include "NVPTXSubtarget.h"
18 #include "NVPTXTargetMachine.h"
25 
26 using namespace llvm;
27 
29  : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 8, 0) {}
30 
31 bool NVPTXFrameLowering::hasFP(const MachineFunction &MF) const { return true; }
32 
34  MachineBasicBlock &MBB) const {
35  if (MF.getFrameInfo().hasStackObjects()) {
36  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
37  MachineInstr *MI = &MBB.front();
39 
40  // This instruction really occurs before first instruction
41  // in the BB, so giving it no debug location.
42  DebugLoc dl = DebugLoc();
43 
44  // Emits
45  // mov %SPL, %depot;
46  // cvta.local %SP, %SPL;
47  // for local address accesses in MF.
48  bool Is64Bit =
49  static_cast<const NVPTXTargetMachine &>(MF.getTarget()).is64Bit();
50  unsigned CvtaLocalOpcode =
51  (Is64Bit ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes);
52  unsigned MovDepotOpcode =
53  (Is64Bit ? NVPTX::MOV_DEPOT_ADDR_64 : NVPTX::MOV_DEPOT_ADDR);
54  if (!MR.use_empty(NVPTX::VRFrame)) {
55  // If %SP is not used, do not bother emitting "cvta.local %SP, %SPL".
56  MI = BuildMI(MBB, MI, dl,
57  MF.getSubtarget().getInstrInfo()->get(CvtaLocalOpcode),
58  NVPTX::VRFrame)
59  .addReg(NVPTX::VRFrameLocal);
60  }
61  BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
62  NVPTX::VRFrameLocal)
63  .addImm(MF.getFunctionNumber());
64  }
65 }
66 
68  MachineBasicBlock &MBB) const {}
69 
70 // This function eliminates ADJCALLSTACKDOWN,
71 // ADJCALLSTACKUP pseudo instructions
75  // Simply discard ADJCALLSTACKDOWN,
76  // ADJCALLSTACKUP instructions.
77  return MBB.erase(I);
78 }
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
A debug info location.
Definition: DebugLoc.h:34
unsigned getFunctionNumber() const
getFunctionNumber - Return a unique ID for the current function.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineBasicBlock & front() const
bool hasStackObjects() const
Return true if there are any stack objects in this function.
MachineBasicBlock * MBB
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool is64Bit(const char *name)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
Information about stack frame layout on the target.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
NVPTXTargetMachine.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
#define I(x, y, z)
Definition: MD5.cpp:54
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
IRTranslator LLVM IR MI
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.