41 #define DEBUG_TYPE "regalloc"
43 STATISTIC(NumSpillSlots,
"Number of spill slots allocated");
44 STATISTIC(NumIdCopies,
"Number of identity moves eliminated after rewriting");
55 MRI = &mf.getRegInfo();
56 TII = mf.getSubtarget().getInstrInfo();
61 Virt2StackSlotMap.clear();
62 Virt2SplitMap.clear();
70 Virt2PhysMap.resize(NumRegs);
71 Virt2StackSlotMap.resize(NumRegs);
72 Virt2SplitMap.resize(NumRegs);
88 return getPhys(VirtReg) == Hint;
103 "attempt to assign stack slot to already spilled register");
105 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
111 "attempt to assign stack slot to already spilled register");
114 "illegal fixed frame index");
115 Virt2StackSlotMap[virtReg] = SS;
119 OS <<
"********** REGISTER MAP **********\n";
123 OS <<
'[' <<
PrintReg(Reg, TRI) <<
" -> "
124 <<
PrintReg(Virt2PhysMap[Reg], TRI) <<
"] "
132 OS <<
'[' <<
PrintReg(Reg, TRI) <<
" -> fi#" << Virt2StackSlotMap[
Reg]
139 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
166 void addMBBLiveIns();
168 void addLiveInsForSubRanges(
const LiveInterval &LI,
unsigned PhysReg)
const;
188 "Virtual Register Rewriter",
false,
false)
197 char VirtRegRewriter::
ID = 0;
199 void VirtRegRewriter::getAnalysisUsage(
AnalysisUsage &AU)
const {
200 AU.setPreservesCFG();
213 TM = &MF->getTarget();
214 TRI = MF->getSubtarget().getRegisterInfo();
215 TII = MF->getSubtarget().getInstrInfo();
216 MRI = &MF->getRegInfo();
217 Indexes = &getAnalysis<SlotIndexes>();
218 LIS = &getAnalysis<LiveIntervals>();
219 VRM = &getAnalysis<VirtRegMap>();
220 DEBUG(
dbgs() <<
"********** REWRITE VIRTUAL REGISTERS **********\n"
221 <<
"********** Function: "
222 << MF->getName() <<
'\n');
226 LIS->addKillFlags(VRM);
235 getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
240 MRI->clearVirtRegs();
244 void VirtRegRewriter::addLiveInsForSubRanges(
const LiveInterval &LI,
245 unsigned PhysReg)
const {
254 for (
const LiveInterval::SubRange &SR : LI.
subranges()) {
255 SubRanges.
push_back(std::make_pair(&SR, SR.begin()));
256 if (!First.
isValid() || SR.segments.front().start < First)
257 First = SR.segments.front().start;
258 if (!Last.
isValid() || SR.segments.back().end > Last)
259 Last = SR.segments.back().end;
265 MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
270 for (
auto &RangeIterPair : SubRanges) {
271 const LiveInterval::SubRange *SR = RangeIterPair.first;
273 while (SRI != SR->
end() && SRI->end <= MBBBegin)
275 if (SRI == SR->
end())
277 if (SRI->start <= MBBBegin)
289 void VirtRegRewriter::addMBBLiveIns() {
290 for (
unsigned Idx = 0, IdxE =
MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
292 if (
MRI->reg_nodbg_empty(VirtReg))
295 if (LI.
empty() || LIS->intervalIsInOneMBB(LI))
299 unsigned PhysReg = VRM->getPhys(VirtReg);
303 addLiveInsForSubRanges(LI, PhysReg);
309 for (
const auto &Seg : LI) {
310 I = Indexes->advanceMBBIndex(I, Seg.start);
311 for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++
I) {
327 bool VirtRegRewriter::readsUndefSubreg(
const MachineOperand &MO)
const {
335 SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
339 "Reads of completely dead register should be marked undef already");
342 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
344 for (
const LiveInterval::SubRange &SR : LI.
subranges()) {
351 void VirtRegRewriter::handleIdentityCopy(
MachineInstr &MI)
const {
354 DEBUG(
dbgs() <<
"Identity copy: " << MI);
370 Indexes->removeMachineInstrFromMaps(MI);
375 void VirtRegRewriter::rewrite() {
376 bool NoSubRegLiveness = !
MRI->subRegLivenessEnabled();
382 MBBI != MBBE; ++MBBI) {
385 MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
399 unsigned VirtReg = MO.
getReg();
400 unsigned PhysReg = VRM->getPhys(VirtReg);
402 "Instruction uses unmapped VirtReg");
403 assert(!
MRI->isReserved(PhysReg) &&
"Reserved register assignment");
408 if (NoSubRegLiveness) {
424 if (readsUndefSubreg(MO))
429 }
else if (!MO.
isDead()) {
442 PhysReg = TRI->getSubReg(PhysReg, SubReg);
443 assert(PhysReg &&
"Invalid SubReg for physical register");
453 while (!SuperKills.
empty())
456 while (!SuperDeads.
empty())
459 while (!SuperDefs.
empty())
465 handleIdentityCopy(*MI);
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
void push_back(const T &Elt)
mop_iterator operands_end()
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
STATISTIC(NumFunctions,"Total number of functions")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
LiveInterval - This class represents the liveness of a register, or stack slot.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
A live range for subregisters.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
#define INITIALIZE_PASS_DEPENDENCY(depName)
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
int getObjectIndexBegin() const
Return the minimum frame object index.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
TargetInstrInfo - Interface to description of machine instruction set.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isValid() const
Returns true if this is a valid index.
unsigned const MachineRegisterInfo * MRI
constexpr bool none() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
bool hasPreferredPhys(unsigned VirtReg)
returns true if VirtReg is assigned to its preferred physreg.
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
bool hasKnownPreference(unsigned VirtReg)
returns true if VirtReg has a known preferred register.
unsigned getSubReg() const
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Iterator for intrusive lists based on ilist_node.
Segments::const_iterator const_iterator
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Promote Memory to Register
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
LLVM_NODISCARD T pop_back_val()
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Virtual Register Rewriter
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setSubReg(unsigned subReg)
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block) ...
INITIALIZE_PASS_BEGIN(VirtRegRewriter,"virtregrewriter","Virtual Register Rewriter", false, false) INITIALIZE_PASS_END(VirtRegRewriter
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
mop_iterator operands_begin()
char & VirtRegRewriterID
VirtRegRewriter pass.
This class implements an extremely fast bulk output stream that can only output to a stream...
int assignVirt2StackSlot(unsigned virtReg)
create a mapping for the specifed virtual register to the next available stack slot ...
Primary interface to the complete machine description for the target machine.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
SlotIndex - An opaque wrapper around machine indexes.
Properties which a MachineFunction may have at a given point in time.