LLVM  4.0.0
MipsDelaySlotFiller.cpp
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1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Simple pass to fill delay slots with useful instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "Mips.h"
16 #include "MipsInstrInfo.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/Statistic.h"
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "delay-slot-filler"
36 
37 STATISTIC(FilledSlots, "Number of delay slots filled");
38 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
39  " are not NOP.");
40 
42  "disable-mips-delay-filler",
43  cl::init(false),
44  cl::desc("Fill all delay slots with NOPs."),
45  cl::Hidden);
46 
48  "disable-mips-df-forward-search",
49  cl::init(true),
50  cl::desc("Disallow MIPS delay filler to search forward."),
51  cl::Hidden);
52 
54  "disable-mips-df-succbb-search",
55  cl::init(true),
56  cl::desc("Disallow MIPS delay filler to search successor basic blocks."),
57  cl::Hidden);
58 
60  "disable-mips-df-backward-search",
61  cl::init(false),
62  cl::desc("Disallow MIPS delay filler to search backward."),
63  cl::Hidden);
64 
66  CB_Never, ///< The policy 'never' may in some circumstances or for some
67  ///< ISAs not be absolutely adhered to.
68  CB_Optimal, ///< Optimal is the default and will produce compact branches
69  ///< when delay slots cannot be filled.
70  CB_Always ///< 'always' may in some circumstances may not be
71  ///< absolutely adhered to there may not be a corresponding
72  ///< compact form of a branch.
73 };
74 
76  "mips-compact-branches",cl::Optional,
78  cl::desc("MIPS Specific: Compact branch policy."),
79  cl::values(
80  clEnumValN(CB_Never, "never", "Do not use compact branches if possible."),
81  clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropiate (default)."),
82  clEnumValN(CB_Always, "always", "Always use compact branches if possible.")
83  )
84 );
85 
86 namespace {
87  typedef MachineBasicBlock::iterator Iter;
88  typedef MachineBasicBlock::reverse_iterator ReverseIter;
90 
91  class RegDefsUses {
92  public:
93  RegDefsUses(const TargetRegisterInfo &TRI);
94  void init(const MachineInstr &MI);
95 
96  /// This function sets all caller-saved registers in Defs.
97  void setCallerSaved(const MachineInstr &MI);
98 
99  /// This function sets all unallocatable registers in Defs.
100  void setUnallocatableRegs(const MachineFunction &MF);
101 
102  /// Set bits in Uses corresponding to MBB's live-out registers except for
103  /// the registers that are live-in to SuccBB.
104  void addLiveOut(const MachineBasicBlock &MBB,
105  const MachineBasicBlock &SuccBB);
106 
107  bool update(const MachineInstr &MI, unsigned Begin, unsigned End);
108 
109  private:
110  bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
111  bool IsDef) const;
112 
113  /// Returns true if Reg or its alias is in RegSet.
114  bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
115 
116  const TargetRegisterInfo &TRI;
117  BitVector Defs, Uses;
118  };
119 
120  /// Base class for inspecting loads and stores.
121  class InspectMemInstr {
122  public:
123  InspectMemInstr(bool ForbidMemInstr_)
124  : OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false),
125  SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {}
126 
127  /// Return true if MI cannot be moved to delay slot.
128  bool hasHazard(const MachineInstr &MI);
129 
130  virtual ~InspectMemInstr() {}
131 
132  protected:
133  /// Flags indicating whether loads or stores have been seen.
134  bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore;
135 
136  /// Memory instructions are not allowed to move to delay slot if this flag
137  /// is true.
138  bool ForbidMemInstr;
139 
140  private:
141  virtual bool hasHazard_(const MachineInstr &MI) = 0;
142  };
143 
144  /// This subclass rejects any memory instructions.
145  class NoMemInstr : public InspectMemInstr {
146  public:
147  NoMemInstr() : InspectMemInstr(true) {}
148  private:
149  bool hasHazard_(const MachineInstr &MI) override { return true; }
150  };
151 
152  /// This subclass accepts loads from stacks and constant loads.
153  class LoadFromStackOrConst : public InspectMemInstr {
154  public:
155  LoadFromStackOrConst() : InspectMemInstr(false) {}
156  private:
157  bool hasHazard_(const MachineInstr &MI) override;
158  };
159 
160  /// This subclass uses memory dependence information to determine whether a
161  /// memory instruction can be moved to a delay slot.
162  class MemDefsUses : public InspectMemInstr {
163  public:
164  MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI);
165 
166  private:
168 
169  bool hasHazard_(const MachineInstr &MI) override;
170 
171  /// Update Defs and Uses. Return true if there exist dependences that
172  /// disqualify the delay slot candidate between V and values in Uses and
173  /// Defs.
174  bool updateDefsUses(ValueType V, bool MayStore);
175 
176  /// Get the list of underlying objects of MI's memory operand.
178  SmallVectorImpl<ValueType> &Objects) const;
179 
180  const MachineFrameInfo *MFI;
181  SmallPtrSet<ValueType, 4> Uses, Defs;
182  const DataLayout &DL;
183 
184  /// Flags indicating whether loads or stores with no underlying objects have
185  /// been seen.
186  bool SeenNoObjLoad, SeenNoObjStore;
187  };
188 
189  class Filler : public MachineFunctionPass {
190  public:
191  Filler(TargetMachine &tm)
192  : MachineFunctionPass(ID), TM(tm) { }
193 
194  StringRef getPassName() const override { return "Mips Delay Slot Filler"; }
195 
196  bool runOnMachineFunction(MachineFunction &F) override {
197  bool Changed = false;
198  for (MachineFunction::iterator FI = F.begin(), FE = F.end();
199  FI != FE; ++FI)
200  Changed |= runOnMachineBasicBlock(*FI);
201 
202  // This pass invalidates liveness information when it reorders
203  // instructions to fill delay slot. Without this, -verify-machineinstrs
204  // will fail.
205  if (Changed)
207 
208  return Changed;
209  }
210 
211  MachineFunctionProperties getRequiredProperties() const override {
214  }
215 
216  void getAnalysisUsage(AnalysisUsage &AU) const override {
219  }
220 
221  private:
222  bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
223 
224  Iter replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch,
225  const DebugLoc &DL);
226 
227  /// This function checks if it is valid to move Candidate to the delay slot
228  /// and returns true if it isn't. It also updates memory and register
229  /// dependence information.
230  bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
231  InspectMemInstr &IM) const;
232 
233  /// This function searches range [Begin, End) for an instruction that can be
234  /// moved to the delay slot. Returns true on success.
235  template<typename IterTy>
236  bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
237  RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot,
238  IterTy &Filler) const;
239 
240  /// This function searches in the backward direction for an instruction that
241  /// can be moved to the delay slot. Returns true on success.
242  bool searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const;
243 
244  /// This function searches MBB in the forward direction for an instruction
245  /// that can be moved to the delay slot. Returns true on success.
246  bool searchForward(MachineBasicBlock &MBB, Iter Slot) const;
247 
248  /// This function searches one of MBB's successor blocks for an instruction
249  /// that can be moved to the delay slot and inserts clones of the
250  /// instruction into the successor's predecessor blocks.
251  bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const;
252 
253  /// Pick a successor block of MBB. Return NULL if MBB doesn't have a
254  /// successor block that is not a landing pad.
255  MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const;
256 
257  /// This function analyzes MBB and returns an instruction with an unoccupied
258  /// slot that branches to Dst.
259  std::pair<MipsInstrInfo::BranchType, MachineInstr *>
260  getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const;
261 
262  /// Examine Pred and see if it is possible to insert an instruction into
263  /// one of its branches delay slot or its end.
264  bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
265  RegDefsUses &RegDU, bool &HasMultipleSuccs,
266  BB2BrMap &BrMap) const;
267 
268  bool terminateSearch(const MachineInstr &Candidate) const;
269 
270  TargetMachine &TM;
271 
272  static char ID;
273  };
274  char Filler::ID = 0;
275 } // end of anonymous namespace
276 
277 static bool hasUnoccupiedSlot(const MachineInstr *MI) {
278  return MI->hasDelaySlot() && !MI->isBundledWithSucc();
279 }
280 
281 /// This function inserts clones of Filler into predecessor blocks.
282 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
283  MachineFunction *MF = Filler->getParent()->getParent();
284 
285  for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
286  if (I->second) {
287  MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
288  ++UsefulSlots;
289  } else {
290  I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
291  }
292  }
293 }
294 
295 /// This function adds registers Filler defines to MBB's live-in register list.
296 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
297  for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
298  const MachineOperand &MO = Filler->getOperand(I);
299  unsigned R;
300 
301  if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
302  continue;
303 
304 #ifndef NDEBUG
305  const MachineFunction &MF = *MBB.getParent();
307  "Shouldn't move an instruction with unallocatable registers across "
308  "basic block boundaries.");
309 #endif
310 
311  if (!MBB.isLiveIn(R))
312  MBB.addLiveIn(R);
313  }
314 }
315 
316 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI)
317  : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
318 
319 void RegDefsUses::init(const MachineInstr &MI) {
320  // Add all register operands which are explicit and non-variadic.
321  update(MI, 0, MI.getDesc().getNumOperands());
322 
323  // If MI is a call, add RA to Defs to prevent users of RA from going into
324  // delay slot.
325  if (MI.isCall())
326  Defs.set(Mips::RA);
327 
328  // Add all implicit register operands of branch instructions except
329  // register AT.
330  if (MI.isBranch()) {
331  update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
332  Defs.reset(Mips::AT);
333  }
334 }
335 
336 void RegDefsUses::setCallerSaved(const MachineInstr &MI) {
337  assert(MI.isCall());
338 
339  // Add RA/RA_64 to Defs to prevent users of RA/RA_64 from going into
340  // the delay slot. The reason is that RA/RA_64 must not be changed
341  // in the delay slot so that the callee can return to the caller.
342  if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) {
343  Defs.set(Mips::RA);
344  Defs.set(Mips::RA_64);
345  }
346 
347  // If MI is a call, add all caller-saved registers to Defs.
348  BitVector CallerSavedRegs(TRI.getNumRegs(), true);
349 
350  CallerSavedRegs.reset(Mips::ZERO);
351  CallerSavedRegs.reset(Mips::ZERO_64);
352 
353  for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent());
354  *R; ++R)
355  for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI)
356  CallerSavedRegs.reset(*AI);
357 
358  Defs |= CallerSavedRegs;
359 }
360 
361 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {
362  BitVector AllocSet = TRI.getAllocatableSet(MF);
363 
364  for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R))
365  for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)
366  AllocSet.set(*AI);
367 
368  AllocSet.set(Mips::ZERO);
369  AllocSet.set(Mips::ZERO_64);
370 
371  Defs |= AllocSet.flip();
372 }
373 
374 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
375  const MachineBasicBlock &SuccBB) {
377  SE = MBB.succ_end(); SI != SE; ++SI)
378  if (*SI != &SuccBB)
379  for (const auto &LI : (*SI)->liveins())
380  Uses.set(LI.PhysReg);
381 }
382 
383 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
384  BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
385  bool HasHazard = false;
386 
387  for (unsigned I = Begin; I != End; ++I) {
388  const MachineOperand &MO = MI.getOperand(I);
389 
390  if (MO.isReg() && MO.getReg())
391  HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
392  }
393 
394  Defs |= NewDefs;
395  Uses |= NewUses;
396 
397  return HasHazard;
398 }
399 
400 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses,
401  unsigned Reg, bool IsDef) const {
402  if (IsDef) {
403  NewDefs.set(Reg);
404  // check whether Reg has already been defined or used.
405  return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg));
406  }
407 
408  NewUses.set(Reg);
409  // check whether Reg has already been defined.
410  return isRegInSet(Defs, Reg);
411 }
412 
413 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const {
414  // Check Reg and all aliased Registers.
415  for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
416  if (RegSet.test(*AI))
417  return true;
418  return false;
419 }
420 
421 bool InspectMemInstr::hasHazard(const MachineInstr &MI) {
422  if (!MI.mayStore() && !MI.mayLoad())
423  return false;
424 
425  if (ForbidMemInstr)
426  return true;
427 
428  OrigSeenLoad = SeenLoad;
429  OrigSeenStore = SeenStore;
430  SeenLoad |= MI.mayLoad();
431  SeenStore |= MI.mayStore();
432 
433  // If MI is an ordered or volatile memory reference, disallow moving
434  // subsequent loads and stores to delay slot.
435  if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) {
436  ForbidMemInstr = true;
437  return true;
438  }
439 
440  return hasHazard_(MI);
441 }
442 
443 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) {
444  if (MI.mayStore())
445  return true;
446 
447  if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue())
448  return true;
449 
450  if (const PseudoSourceValue *PSV =
451  (*MI.memoperands_begin())->getPseudoValue()) {
452  if (isa<FixedStackPseudoSourceValue>(PSV))
453  return false;
454  return !PSV->isConstant(nullptr) && !PSV->isStack();
455  }
456 
457  return true;
458 }
459 
460 MemDefsUses::MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI_)
461  : InspectMemInstr(false), MFI(MFI_), DL(DL), SeenNoObjLoad(false),
462  SeenNoObjStore(false) {}
463 
464 bool MemDefsUses::hasHazard_(const MachineInstr &MI) {
465  bool HasHazard = false;
467 
468  // Check underlying object list.
469  if (getUnderlyingObjects(MI, Objs)) {
471  I != Objs.end(); ++I)
472  HasHazard |= updateDefsUses(*I, MI.mayStore());
473 
474  return HasHazard;
475  }
476 
477  // No underlying objects found.
478  HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore);
479  HasHazard |= MI.mayLoad() || OrigSeenStore;
480 
481  SeenNoObjLoad |= MI.mayLoad();
482  SeenNoObjStore |= MI.mayStore();
483 
484  return HasHazard;
485 }
486 
487 bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) {
488  if (MayStore)
489  return !Defs.insert(V).second || Uses.count(V) || SeenNoObjStore ||
490  SeenNoObjLoad;
491 
492  Uses.insert(V);
493  return Defs.count(V) || SeenNoObjStore;
494 }
495 
496 bool MemDefsUses::
498  SmallVectorImpl<ValueType> &Objects) const {
499  if (!MI.hasOneMemOperand() ||
500  (!(*MI.memoperands_begin())->getValue() &&
501  !(*MI.memoperands_begin())->getPseudoValue()))
502  return false;
503 
504  if (const PseudoSourceValue *PSV =
505  (*MI.memoperands_begin())->getPseudoValue()) {
506  if (!PSV->isAliased(MFI))
507  return false;
508  Objects.push_back(PSV);
509  return true;
510  }
511 
512  const Value *V = (*MI.memoperands_begin())->getValue();
513 
515  GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL);
516 
517  for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end();
518  I != E; ++I) {
519  if (!isIdentifiedObject(V))
520  return false;
521 
522  Objects.push_back(*I);
523  }
524 
525  return true;
526 }
527 
528 // Replace Branch with the compact branch instruction.
529 Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch,
530  const DebugLoc &DL) {
531  const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
532  const MipsInstrInfo *TII = STI.getInstrInfo();
533 
534  unsigned NewOpcode = TII->getEquivalentCompactForm(Branch);
535  Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
536 
537  std::next(Branch)->eraseFromParent();
538  return Branch;
539 }
540 
541 // For given opcode returns opcode of corresponding instruction with short
542 // delay slot.
543 // For the pseudo TAILCALL*_MM instrunctions return the short delay slot
544 // form. Unfortunately, TAILCALL<->b16 is denied as b16 has a limited range
545 // that is too short to make use of for tail calls.
546 static int getEquivalentCallShort(int Opcode) {
547  switch (Opcode) {
548  case Mips::BGEZAL:
549  return Mips::BGEZALS_MM;
550  case Mips::BLTZAL:
551  return Mips::BLTZALS_MM;
552  case Mips::JAL:
553  return Mips::JALS_MM;
554  case Mips::JALR:
555  return Mips::JALRS_MM;
556  case Mips::JALR16_MM:
557  return Mips::JALRS16_MM;
558  case Mips::TAILCALL_MM:
559  llvm_unreachable("Attempting to shorten the TAILCALL_MM pseudo!");
560  case Mips::TAILCALLREG:
561  return Mips::JR16_MM;
562  default:
563  llvm_unreachable("Unexpected call instruction for microMIPS.");
564  }
565 }
566 
567 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
568 /// We assume there is only one delay slot per delayed instruction.
569 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
570  bool Changed = false;
571  const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
572  bool InMicroMipsMode = STI.inMicroMipsMode();
573  const MipsInstrInfo *TII = STI.getInstrInfo();
574 
575  if (InMicroMipsMode && STI.hasMips32r6()) {
576  // This is microMIPS32r6 or microMIPS64r6 processor. Delay slot for
577  // branching instructions is not needed.
578  return Changed;
579  }
580 
581  for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
582  if (!hasUnoccupiedSlot(&*I))
583  continue;
584 
585  ++FilledSlots;
586  Changed = true;
587 
588  // Delay slot filling is disabled at -O0.
589  if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
590  bool Filled = false;
591 
592  if (MipsCompactBranchPolicy.getValue() != CB_Always ||
593  !TII->getEquivalentCompactForm(I)) {
594  if (searchBackward(MBB, *I)) {
595  Filled = true;
596  } else if (I->isTerminator()) {
597  if (searchSuccBBs(MBB, I)) {
598  Filled = true;
599  }
600  } else if (searchForward(MBB, I)) {
601  Filled = true;
602  }
603  }
604 
605  if (Filled) {
606  // Get instruction with delay slot.
607  MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
608 
609  if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
610  DSI->isCall()) {
611  // If instruction in delay slot is 16b change opcode to
612  // corresponding instruction with short delay slot.
613 
614  // TODO: Implement an instruction mapping table of 16bit opcodes to
615  // 32bit opcodes so that an instruction can be expanded. This would
616  // save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop.
617  // TODO: Permit b16 when branching backwards to the the same function
618  // if it is in range.
619  DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
620  }
621  continue;
622  }
623  }
624 
625  // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
626  // instead of adding NOP replace this instruction with the corresponding
627  // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
628  // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
629  // be replaced with JRC16_MM.
630 
631  // For MIPSR6 attempt to produce the corresponding compact (no delay slot)
632  // form of the CTI. For indirect jumps this will not require inserting a
633  // NOP and for branches will hopefully avoid requiring a NOP.
634  if ((InMicroMipsMode ||
636  TII->getEquivalentCompactForm(I)) {
637  I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
638  continue;
639  }
640 
641  // Bundle the NOP to the instruction with the delay slot.
642  BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
643  MIBundleBuilder(MBB, I, std::next(I, 2));
644  }
645 
646  return Changed;
647 }
648 
649 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
650 /// slots in Mips MachineFunctions
652  return new Filler(tm);
653 }
654 
655 template<typename IterTy>
656 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
657  RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,
658  IterTy &Filler) const {
659  for (IterTy I = Begin; I != End;) {
660  IterTy CurrI = I;
661  ++I;
662 
663  // skip debug value
664  if (CurrI->isDebugValue())
665  continue;
666 
667  if (terminateSearch(*CurrI))
668  break;
669 
670  assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
671  "Cannot put calls, returns or branches in delay slot.");
672 
673  if (CurrI->isKill()) {
674  CurrI->eraseFromParent();
675  continue;
676  }
677 
678  if (delayHasHazard(*CurrI, RegDU, IM))
679  continue;
680 
681  const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
682  if (STI.isTargetNaCl()) {
683  // In NaCl, instructions that must be masked are forbidden in delay slots.
684  // We only check for loads, stores and SP changes. Calls, returns and
685  // branches are not checked because non-NaCl targets never put them in
686  // delay slots.
687  unsigned AddrIdx;
688  if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
689  baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
690  CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
691  continue;
692  }
693 
694  bool InMicroMipsMode = STI.inMicroMipsMode();
695  const MipsInstrInfo *TII = STI.getInstrInfo();
696  unsigned Opcode = (*Slot).getOpcode();
697  // This is complicated by the tail call optimization. For non-PIC code
698  // there is only a 32bit sized unconditional branch which can be assumed
699  // to be able to reach the target. b16 only has a range of +/- 1 KB.
700  // It's entirely possible that the target function is reachable with b16
701  // but we don't have enough information to make that decision.
702  if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
703  (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
704  Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL))
705  continue;
706 
707  Filler = CurrI;
708  return true;
709  }
710 
711  return false;
712 }
713 
714 bool Filler::searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const {
716  return false;
717 
718  auto *Fn = MBB.getParent();
719  RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo());
720  MemDefsUses MemDU(Fn->getDataLayout(), &Fn->getFrameInfo());
721  ReverseIter Filler;
722 
723  RegDU.init(Slot);
724 
725  MachineBasicBlock::iterator SlotI = Slot;
726  if (!searchRange(MBB, ++SlotI.getReverse(), MBB.rend(), RegDU, MemDU, Slot,
727  Filler))
728  return false;
729 
730  MBB.splice(std::next(SlotI), &MBB, Filler.getReverse());
731  MIBundleBuilder(MBB, SlotI, std::next(SlotI, 2));
732  ++UsefulSlots;
733  return true;
734 }
735 
736 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const {
737  // Can handle only calls.
738  if (DisableForwardSearch || !Slot->isCall())
739  return false;
740 
741  RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
742  NoMemInstr NM;
743  Iter Filler;
744 
745  RegDU.setCallerSaved(*Slot);
746 
747  if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler))
748  return false;
749 
750  MBB.splice(std::next(Slot), &MBB, Filler);
751  MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
752  ++UsefulSlots;
753  return true;
754 }
755 
756 bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const {
758  return false;
759 
760  MachineBasicBlock *SuccBB = selectSuccBB(MBB);
761 
762  if (!SuccBB)
763  return false;
764 
765  RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo());
766  bool HasMultipleSuccs = false;
767  BB2BrMap BrMap;
768  std::unique_ptr<InspectMemInstr> IM;
769  Iter Filler;
770  auto *Fn = MBB.getParent();
771 
772  // Iterate over SuccBB's predecessor list.
773  for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(),
774  PE = SuccBB->pred_end(); PI != PE; ++PI)
775  if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap))
776  return false;
777 
778  // Do not allow moving instructions which have unallocatable register operands
779  // across basic block boundaries.
780  RegDU.setUnallocatableRegs(*Fn);
781 
782  // Only allow moving loads from stack or constants if any of the SuccBB's
783  // predecessors have multiple successors.
784  if (HasMultipleSuccs) {
785  IM.reset(new LoadFromStackOrConst());
786  } else {
787  const MachineFrameInfo &MFI = Fn->getFrameInfo();
788  IM.reset(new MemDefsUses(Fn->getDataLayout(), &MFI));
789  }
790 
791  if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Slot,
792  Filler))
793  return false;
794 
795  insertDelayFiller(Filler, BrMap);
796  addLiveInRegs(Filler, *SuccBB);
797  Filler->eraseFromParent();
798 
799  return true;
800 }
801 
802 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
803  if (B.succ_empty())
804  return nullptr;
805 
806  // Select the successor with the larget edge weight.
807  auto &Prob = getAnalysis<MachineBranchProbabilityInfo>();
808  MachineBasicBlock *S = *std::max_element(
809  B.succ_begin(), B.succ_end(),
810  [&](const MachineBasicBlock *Dst0, const MachineBasicBlock *Dst1) {
811  return Prob.getEdgeProbability(&B, Dst0) <
812  Prob.getEdgeProbability(&B, Dst1);
813  });
814  return S->isEHPad() ? nullptr : S;
815 }
816 
817 std::pair<MipsInstrInfo::BranchType, MachineInstr *>
818 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
819  const MipsInstrInfo *TII =
820  MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
821  MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr;
822  SmallVector<MachineInstr*, 2> BranchInstrs;
824 
826  TII->analyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs);
827 
828  if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch))
829  return std::make_pair(R, nullptr);
830 
831  if (R != MipsInstrInfo::BT_CondUncond) {
832  if (!hasUnoccupiedSlot(BranchInstrs[0]))
833  return std::make_pair(MipsInstrInfo::BT_None, nullptr);
834 
835  assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst)));
836 
837  return std::make_pair(R, BranchInstrs[0]);
838  }
839 
840  assert((TrueBB == &Dst) || (FalseBB == &Dst));
841 
842  // Examine the conditional branch. See if its slot is occupied.
843  if (hasUnoccupiedSlot(BranchInstrs[0]))
844  return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]);
845 
846  // If that fails, try the unconditional branch.
847  if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst))
848  return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]);
849 
850  return std::make_pair(MipsInstrInfo::BT_None, nullptr);
851 }
852 
853 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
854  RegDefsUses &RegDU, bool &HasMultipleSuccs,
855  BB2BrMap &BrMap) const {
856  std::pair<MipsInstrInfo::BranchType, MachineInstr *> P =
857  getBranch(Pred, Succ);
858 
859  // Return if either getBranch wasn't able to analyze the branches or there
860  // were no branches with unoccupied slots.
861  if (P.first == MipsInstrInfo::BT_None)
862  return false;
863 
864  if ((P.first != MipsInstrInfo::BT_Uncond) &&
865  (P.first != MipsInstrInfo::BT_NoBranch)) {
866  HasMultipleSuccs = true;
867  RegDU.addLiveOut(Pred, Succ);
868  }
869 
870  BrMap[&Pred] = P.second;
871  return true;
872 }
873 
874 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
875  InspectMemInstr &IM) const {
876  assert(!Candidate.isKill() &&
877  "KILL instructions should have been eliminated at this point.");
878 
879  bool HasHazard = Candidate.isImplicitDef();
880 
881  HasHazard |= IM.hasHazard(Candidate);
882  HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());
883 
884  return HasHazard;
885 }
886 
887 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
888  return (Candidate.isTerminator() || Candidate.isCall() ||
889  Candidate.isPosition() || Candidate.isInlineAsm() ||
890  Candidate.hasUnmodeledSideEffects());
891 }
const NoneType None
Definition: None.h:23
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isEHPad() const
Returns true if the block is a landing pad.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
BitVector & set()
Definition: BitVector.h:219
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:157
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:448
STATISTIC(NumFunctions,"Total number of functions")
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, bool *IsStore=nullptr)
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:166
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
const MipsInstrInfo * getInstrInfo() const override
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Optimal is the default and will produce compact branches when delay slots cannot be filled...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
static bool hasUnoccupiedSlot(const MachineInstr *MI)
A debug info location.
Definition: DebugLoc.h:34
void GetUnderlyingObjects(Value *V, SmallVectorImpl< Value * > &Objects, const DataLayout &DL, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to GetUnderlyingObject except that it can look through phi and select instruct...
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
static cl::opt< bool > DisableDelaySlotFiller("disable-mips-delay-filler", cl::init(false), cl::desc("Fill all delay slots with NOPs."), cl::Hidden)
AnalysisUsage & addRequired()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool baseRegNeedsLoadStoreMask(unsigned Reg)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isIdentifiedObject(const Value *V)
Return true if this pointer refers to a distinct and identifiable object.
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:233
static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB)
This function adds registers Filler defines to MBB's live-in register list.
static cl::opt< CompactBranchPolicy > MipsCompactBranchPolicy("mips-compact-branches", cl::Optional, cl::init(CB_Optimal), cl::desc("MIPS Specific: Compact branch policy."), cl::values(clEnumValN(CB_Never,"never","Do not use compact branches if possible."), clEnumValN(CB_Optimal,"optimal","Use compact branches where appropiate (default)."), clEnumValN(CB_Always,"always","Always use compact branches if possible.")))
#define F(x, y, z)
Definition: MD5.cpp:51
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:526
MachineBasicBlock * MBB
static cl::opt< bool > DisableBackwardSearch("disable-mips-df-backward-search", cl::init(false), cl::desc("Disallow MIPS delay filler to search backward."), cl::Hidden)
Function Alias Analysis false
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
std::vector< MachineBasicBlock * >::iterator pred_iterator
static cl::opt< bool > DisableForwardSearch("disable-mips-df-forward-search", cl::init(true), cl::desc("Disallow MIPS delay filler to search forward."), cl::Hidden)
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
reverse_iterator rend()
static void getUnderlyingObjects(MachineInstr *MI, SmallVectorImpl< Value * > &Objs, const DataLayout &DL)
Return the underlying objects for the memory references of an instruction.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool isImplicitDef() const
Definition: MachineInstr.h:788
ValuesClass values(OptsTy...Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:615
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
'always' may in some circumstances may not be absolutely adhered to there may not be a corresponding ...
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
BitVector & reset()
Definition: BitVector.h:260
bool isPosition() const
Definition: MachineInstr.h:775
CompactBranchPolicy
static const unsigned End
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:373
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
bool inMicroMipsMode() const
static cl::opt< bool > DisableSuccBBSearch("disable-mips-df-succbb-search", cl::init(true), cl::desc("Disallow MIPS delay filler to search successor basic blocks."), cl::Hidden)
bool hasMips32r6() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:895
Iterator for intrusive lists based on ilist_node.
bool isTargetNaCl() const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
const MipsRegisterInfo * getRegisterInfo() const override
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool test(unsigned Idx) const
Definition: BitVector.h:323
bool isInlineAsm() const
Definition: MachineInstr.h:789
bool isKill() const
Definition: MachineInstr.h:787
BitVector & flip()
Definition: BitVector.h:299
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
FunctionPass * createMipsDelaySlotFillerPass(MipsTargetMachine &TM)
createMipsDelaySlotFillerPass - Returns a pass that fills in delay slots in Mips MachineFunctions ...
Special value supplied for machine level alias analysis.
static int getEquivalentCallShort(int Opcode)
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:590
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:52
Basic Alias true
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap)
This function inserts clones of Filler into predecessor blocks.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
The policy 'never' may in some circumstances or for some ISAs not be absolutely adhered to...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
unsigned getReg() const
getReg - Returns the register number.
MIBundleBuilder & append(MachineInstr *MI)
Insert MI into MBB by appending it to the instructions in the bundle.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
LLVM Value Representation.
Definition: Value.h:71
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
PointerUnion< const Value *, const PseudoSourceValue * > ValueType
Properties which a MachineFunction may have at a given point in time.
Helper class for constructing bundles of MachineInstrs.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:358