LLVM  4.0.0
Public Member Functions | Protected Member Functions | Protected Attributes | List of all members
llvm::ScheduleDAGMILive Class Reference

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure. More...

#include <MachineScheduler.h>

Inheritance diagram for llvm::ScheduleDAGMILive:
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Collaboration diagram for llvm::ScheduleDAGMILive:
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Public Member Functions

 ScheduleDAGMILive (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
 
 ~ScheduleDAGMILive () override
 
bool hasVRegLiveness () const override
 Return true if this DAG supports VReg liveness and RegPressure. More...
 
bool isTrackingPressure () const
 Return true if register pressure tracking is enabled. More...
 
const IntervalPressuregetTopPressure () const
 Get current register pressure for the top scheduled instructions. More...
 
const RegPressureTrackergetTopRPTracker () const
 
const IntervalPressuregetBotPressure () const
 Get current register pressure for the bottom scheduled instructions. More...
 
const RegPressureTrackergetBotRPTracker () const
 
const IntervalPressuregetRegPressure () const
 Get register pressure for the entire scheduling region before scheduling. More...
 
const std::vector
< PressureChange > & 
getRegionCriticalPSets () const
 
PressureDiffgetPressureDiff (const SUnit *SU)
 
void computeDFSResult ()
 Compute a DFSResult after DAG building is complete, and before any queue comparisons. More...
 
const SchedDFSResultgetDFSResult () const
 Return a non-null DFS result if the scheduling strategy initialized it. More...
 
BitVectorgetScheduledTrees ()
 
void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
 Implement the ScheduleDAGInstrs interface for handling the next scheduling region. More...
 
void schedule () override
 Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions. More...
 
unsigned computeCyclicCriticalPath ()
 Compute the cyclic critical path through the DAG. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGMI
 ScheduleDAGMI (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags)
 
 ~ScheduleDAGMI () override
 
LiveIntervalsgetLIS () const
 
void addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation)
 Add a postprocessing step to the DAG builder. More...
 
bool canAddEdge (SUnit *SuccSU, SUnit *PredSU)
 True if an edge can be added from PredSU to SuccSU without creating a cycle. More...
 
bool addEdge (SUnit *SuccSU, const SDep &PredDep)
 Add a DAG edge to the given SU with the given predecessor dependence data. More...
 
MachineBasicBlock::iterator top () const
 
MachineBasicBlock::iterator bottom () const
 
void moveInstruction (MachineInstr *MI, MachineBasicBlock::iterator InsertPos)
 Change the position of an instruction within the basic block and update live ranges and region boundary iterators. More...
 
const SUnitgetNextClusterPred () const
 
const SUnitgetNextClusterSucc () const
 
void viewGraph (const Twine &Name, const Twine &Title) override
 viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'. More...
 
void viewGraph () override
 Out-of-line implementation with no arguments is handy for gdb. More...
 
- Public Member Functions inherited from llvm::ScheduleDAGInstrs
 ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
 
 ~ScheduleDAGInstrs () override
 
const TargetSchedModelgetSchedModel () const
 Get the machine model for instruction scheduling. More...
 
const MCSchedClassDescgetSchedClass (SUnit *SU) const
 Resolve and cache a resolved scheduling class for an SUnit. More...
 
MachineBasicBlock::iterator begin () const
 begin - Return an iterator to the top of the current scheduling region. More...
 
MachineBasicBlock::iterator end () const
 end - Return an iterator to the bottom of the current scheduling region. More...
 
SUnitnewSUnit (MachineInstr *MI)
 newSUnit - Creates a new SUnit and return a ptr to it. More...
 
SUnitgetSUnit (MachineInstr *MI) const
 getSUnit - Return an existing SUnit for this MI, or NULL. More...
 
virtual void startBlock (MachineBasicBlock *BB)
 startBlock - Prepare to perform scheduling in the given block. More...
 
virtual void finishBlock ()
 finishBlock - Clean up after scheduling in the given block. More...
 
virtual void exitRegion ()
 Notify that the scheduler has finished scheduling the current region. More...
 
void buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
 buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input. More...
 
void addSchedBarrierDeps ()
 addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More...
 
virtual void finalizeSchedule ()
 finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More...
 
void dumpNode (const SUnit *SU) const override
 
std::string getGraphNodeLabel (const SUnit *SU) const override
 Return a label for a DAG node that points to an instruction. More...
 
std::string getDAGName () const override
 Return a label for the region of code covered by the DAG. More...
 
void fixupKills (MachineBasicBlock *MBB)
 Fix register kill flags that scheduling has made invalid. More...
 
- Public Member Functions inherited from llvm::ScheduleDAG
 ScheduleDAG (MachineFunction &mf)
 
virtual ~ScheduleDAG ()
 
void clearDAG ()
 clearDAG - clear the DAG state (between regions). More...
 
const MCInstrDescgetInstrDesc (const SUnit *SU) const
 getInstrDesc - Return the MCInstrDesc of this SUnit. More...
 
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
 addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG. More...
 
unsigned VerifyScheduledDAG (bool isBottomUp)
 VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent. More...
 

Protected Member Functions

void buildDAGWithRegPressure ()
 Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled. More...
 
void initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
 Release ExitSU predecessors and setup scheduler queues. More...
 
void scheduleMI (SUnit *SU, bool IsTopNode)
 Move an instruction and update register pressure. More...
 
void initRegPressure ()
 
void updatePressureDiffs (ArrayRef< RegisterMaskPair > LiveUses)
 Update the PressureDiff array for liveness after scheduling this instruction. More...
 
void updateScheduledPressure (const SUnit *SU, const std::vector< unsigned > &NewMaxPressure)
 
void collectVRegUses (SUnit &SU)
 
- Protected Member Functions inherited from llvm::ScheduleDAGMI
void postprocessDAG ()
 Apply each ScheduleDAGMutation step in order. More...
 
void initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
 Release ExitSU predecessors and setup scheduler queues. More...
 
void updateQueues (SUnit *SU, bool IsTopNode)
 Update scheduler DAG and queues after scheduling an instruction. More...
 
void placeDebugValues ()
 Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues. More...
 
void dumpSchedule () const
 dump the scheduled Sequence. More...
 
bool checkSchedLimit ()
 
void findRootsAndBiasEdges (SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots)
 
void releaseSucc (SUnit *SU, SDep *SuccEdge)
 ReleaseSucc - Decrement the NumPredsLeft count of a successor. More...
 
void releaseSuccessors (SUnit *SU)
 releaseSuccessors - Call releaseSucc on each of SU's successors. More...
 
void releasePred (SUnit *SU, SDep *PredEdge)
 ReleasePred - Decrement the NumSuccsLeft count of a predecessor. More...
 
void releasePredecessors (SUnit *SU)
 releasePredecessors - Call releasePred on each of SU's predecessors. More...
 
- Protected Member Functions inherited from llvm::ScheduleDAGInstrs
void reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
 Remove in FIFO order some SUs from huge maps. More...
 
void addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0)
 Add a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency. More...
 
void addChainDependencies (SUnit *SU, SUList &sus, unsigned Latency)
 Add dependencies as needed from all SUs in list to SU. More...
 
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap)
 Add dependencies as needed from all SUs in map, to SU. More...
 
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V)
 Add dependencies as needed to SU, from all SUs mapped to V. More...
 
void addBarrierChain (Value2SUsMap &map)
 Add barrier chain edges from all SUs in map, and then clear the map. More...
 
void insertBarrierChain (Value2SUsMap &map)
 Insert a barrier chain in a huge region, far below current SU. More...
 
void initSUnits ()
 Create an SUnit for each real instruction, numbered in top-down topological order. More...
 
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
 MO is an operand of SU's instruction that defines a physical register. More...
 
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
 addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More...
 
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
 addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More...
 
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
 addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More...
 
void startBlockForKills (MachineBasicBlock *BB)
 PostRA helper for rewriting kill flags. More...
 
bool toggleKillFlag (MachineInstr *MI, MachineOperand &MO)
 Toggle a register operand kill flag. More...
 
LaneBitmask getLaneMaskForMO (const MachineOperand &MO) const
 Returns a mask for which lanes get read/written by the given (register) machine operand. More...
 

Protected Attributes

RegisterClassInfoRegClassInfo
 
SchedDFSResultDFSResult
 Information about DAG subtrees. More...
 
BitVector ScheduledTrees
 
MachineBasicBlock::iterator LiveRegionEnd
 
VReg2SUnitMultiMap VRegUses
 Maps vregs to the SUnits of their uses in the current scheduling region. More...
 
PressureDiffs SUPressureDiffs
 
bool ShouldTrackPressure
 Register pressure in this region computed by initRegPressure. More...
 
bool ShouldTrackLaneMasks
 
IntervalPressure RegPressure
 
RegPressureTracker RPTracker
 
std::vector< PressureChangeRegionCriticalPSets
 List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing set ID order. More...
 
IntervalPressure TopPressure
 The top of the unscheduled zone. More...
 
RegPressureTracker TopRPTracker
 
IntervalPressure BotPressure
 The bottom of the unscheduled zone. More...
 
RegPressureTracker BotRPTracker
 
bool DisconnectedComponentsRenamed
 True if disconnected subregister components are already renamed. More...
 
- Protected Attributes inherited from llvm::ScheduleDAGMI
AliasAnalysisAA
 
LiveIntervalsLIS
 
std::unique_ptr
< MachineSchedStrategy
SchedImpl
 
ScheduleDAGTopologicalSort Topo
 Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries. More...
 
std::vector< std::unique_ptr
< ScheduleDAGMutation > > 
Mutations
 Ordered list of DAG postprocessing steps. More...
 
MachineBasicBlock::iterator CurrentTop
 The top of the unscheduled zone. More...
 
MachineBasicBlock::iterator CurrentBottom
 The bottom of the unscheduled zone. More...
 
const SUnitNextClusterPred
 Record the next node in a scheduled cluster. More...
 
const SUnitNextClusterSucc
 
unsigned NumInstrsScheduled
 The number of instructions scheduled so far. More...
 
- Protected Attributes inherited from llvm::ScheduleDAGInstrs
const MachineLoopInfoMLI
 
const MachineFrameInfoMFI
 
TargetSchedModel SchedModel
 TargetSchedModel provides an interface to the machine model. More...
 
bool RemoveKillFlags
 True if the DAG builder should remove kill flags (in preparation for rescheduling). More...
 
bool CanHandleTerminators
 The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More...
 
bool TrackLaneMasks
 Whether lane masks should get tracked. More...
 
MachineBasicBlockBB
 State specific to the current scheduling region. More...
 
MachineBasicBlock::iterator RegionBegin
 The beginning of the range to be scheduled. More...
 
MachineBasicBlock::iterator RegionEnd
 The end of the range to be scheduled. More...
 
unsigned NumRegionInstrs
 Instructions in this region (distance(RegionBegin, RegionEnd)). More...
 
DenseMap< MachineInstr *, SUnit * > MISUnitMap
 After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More...
 
Reg2SUnitsMap Defs
 State internal to DAG building. More...
 
Reg2SUnitsMap Uses
 
VReg2SUnitMultiMap CurrentVRegDefs
 Tracks the last instruction(s) in this region defining each virtual register. More...
 
VReg2SUnitOperIdxMultiMap CurrentVRegUses
 Tracks the last instructions in this region using each virtual register. More...
 
AliasAnalysisAAForDep
 
SUnitBarrierChain
 Remember a generic side-effecting instruction as we proceed. More...
 
UndefValueUnknownValue
 For an unanalyzable memory access, this Value is used in maps. More...
 
DbgValueVector DbgValues
 
MachineInstrFirstDbgValue
 
BitVector LiveRegs
 Set of live physical registers for updating kill flags. More...
 

Additional Inherited Members

- Public Types inherited from llvm::ScheduleDAGInstrs
typedef std::list< SUnit * > SUList
 A list of SUnits, used in Value2SUsMap, during DAG construction. More...
 
- Public Attributes inherited from llvm::ScheduleDAG
const TargetMachineTM
 
const TargetInstrInfoTII
 
const TargetRegisterInfoTRI
 
MachineFunctionMF
 
MachineRegisterInfoMRI
 
std::vector< SUnitSUnits
 
SUnit EntrySU
 
SUnit ExitSU
 
bool StressSched
 
- Protected Types inherited from llvm::ScheduleDAGInstrs
typedef std::vector< std::pair
< MachineInstr *, MachineInstr * > > 
DbgValueVector
 DbgValues - Remember instruction that precedes DBG_VALUE. More...
 

Detailed Description

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure.

Definition at line 372 of file MachineScheduler.h.

Constructor & Destructor Documentation

llvm::ScheduleDAGMILive::ScheduleDAGMILive ( MachineSchedContext C,
std::unique_ptr< MachineSchedStrategy S 
)
inline

Definition at line 415 of file MachineScheduler.h.

ScheduleDAGMILive::~ScheduleDAGMILive ( )
override

Definition at line 859 of file MachineScheduler.cpp.

References DFSResult.

Member Function Documentation

void ScheduleDAGMILive::buildDAGWithRegPressure ( )
protected

Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled.

Build the DAG and setup three register pressure trackers.

This sets up three trackers. RPTracker will cover the entire DAG region, TopTracker and BottomTracker will be initialized to the top and bottom of the DAG region without covereing any unscheduled instruction.

Definition at line 1188 of file MachineScheduler.cpp.

References llvm::ScheduleDAGInstrs::BB, llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::RegPressureTracker::init(), initRegPressure(), llvm::ScheduleDAGMI::LIS, LiveRegionEnd, llvm::RegPressureTracker::recede(), RegClassInfo, RegionCriticalPSets, llvm::ScheduleDAGInstrs::RegionEnd, llvm::RegPressureTracker::reset(), RPTracker, ShouldTrackLaneMasks, ShouldTrackPressure, and SUPressureDiffs.

Referenced by llvm::VLIWMachineScheduler::schedule(), llvm::SIScheduleDAGMI::schedule(), and schedule().

void ScheduleDAGMILive::collectVRegUses ( SUnit SU)
protected
unsigned ScheduleDAGMILive::computeCyclicCriticalPath ( )

Compute the cyclic critical path through the DAG.

Compute the max cyclic critical path through the DAG.

The scheduling DAG only provides the critical path for single block loops. To handle loops that span blocks, we could use the vreg path latencies provided by MachineTraceMetrics instead. However, MachineTraceMetrics is not currently available for use in the scheduler.

The cyclic path estimation identifies a def-use pair that crosses the back edge and considers the depth and height of the nodes. For example, consider the following instruction sequence where each instruction has unit latency and defines an epomymous virtual register:

a->b(a,c)->c(b)->d(c)->exit

The cyclic critical path is a two cycles: b->c->b The acyclic critical path is four cycles: a->b->c->d->exit LiveOutHeight = height(c) = len(c->d->exit) = 2 LiveOutDepth = depth(c) + 1 = len(a->b->c) + 1 = 3 LiveInHeight = height(b) + 1 = len(b->c->d->exit) + 1 = 4 LiveInDepth = depth(b) = len(a->b) = 1

LiveOutDepth - LiveInDepth = 3 - 1 = 2 LiveInHeight - LiveOutHeight = 4 - 2 = 2 CyclicCriticalPath = min(2, 2) = 2

This could be relevant to PostRA scheduling, but is currently implemented assuming LiveIntervals.

Definition at line 1247 of file MachineScheduler.cpp.

References llvm::ScheduleDAGInstrs::BB, llvm::dbgs(), DEBUG, llvm::VNInfo::def, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::ScheduleDAG::ExitSU, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::SUnit::getDepth(), llvm::SUnit::getHeight(), llvm::SUnit::getInstr(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::LiveIntervals::getMBBEndIdx(), llvm::RegPressureTracker::getPressure(), llvm::ScheduleDAGInstrs::getSUnit(), llvm::LiveRange::getVNInfoBefore(), llvm::VNInfo::isPHIDef(), llvm::MachineBasicBlock::isSuccessor(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::SUnit::Latency, llvm::ScheduleDAGMI::LIS, llvm::RegisterPressure::LiveOutRegs, llvm::make_range(), llvm::SUnit::NodeNum, P, llvm::LiveRange::Query(), RPTracker, llvm::ScheduleDAG::TRI, llvm::LiveQueryResult::valueIn(), and VRegUses.

void ScheduleDAGMILive::computeDFSResult ( )
void ScheduleDAGMILive::enterRegion ( MachineBasicBlock bb,
MachineBasicBlock::iterator  begin,
MachineBasicBlock::iterator  end,
unsigned  regioninstrs 
)
overridevirtual

Implement the ScheduleDAGInstrs interface for handling the next scheduling region.

enterRegion - Called back from MachineScheduler::runOnMachineFunction after crossing a scheduling boundary.

This covers all instructions in a block, while schedule() may only cover a subset.

[begin, end) includes all instructions in the region, including the boundary itself and single-instruction regions that don't get scheduled.

Reimplemented from llvm::ScheduleDAGMI.

Definition at line 905 of file MachineScheduler.cpp.

References assert(), llvm::PressureDiffs::clear(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAGMI::enterRegion(), LiveRegionEnd, llvm::ScheduleDAGInstrs::RegionEnd, llvm::ScheduleDAGMI::SchedImpl, ShouldTrackLaneMasks, ShouldTrackPressure, and SUPressureDiffs.

const IntervalPressure& llvm::ScheduleDAGMILive::getBotPressure ( ) const
inline

Get current register pressure for the bottom scheduled instructions.

Definition at line 436 of file MachineScheduler.h.

References BotPressure.

const RegPressureTracker& llvm::ScheduleDAGMILive::getBotRPTracker ( ) const
inline

Definition at line 437 of file MachineScheduler.h.

References BotRPTracker.

Referenced by llvm::GCNMaxOccupancySchedStrategy::pickNode().

const SchedDFSResult* llvm::ScheduleDAGMILive::getDFSResult ( ) const
inline

Return a non-null DFS result if the scheduling strategy initialized it.

Definition at line 455 of file MachineScheduler.h.

References DFSResult.

PressureDiff& llvm::ScheduleDAGMILive::getPressureDiff ( const SUnit SU)
inline
const std::vector<PressureChange>& llvm::ScheduleDAGMILive::getRegionCriticalPSets ( ) const
inline

Definition at line 442 of file MachineScheduler.h.

References RegionCriticalPSets.

const IntervalPressure& llvm::ScheduleDAGMILive::getRegPressure ( ) const
inline

Get register pressure for the entire scheduling region before scheduling.

Definition at line 440 of file MachineScheduler.h.

References RegPressure.

BitVector& llvm::ScheduleDAGMILive::getScheduledTrees ( )
inline

Definition at line 457 of file MachineScheduler.h.

References ScheduledTrees.

const IntervalPressure& llvm::ScheduleDAGMILive::getTopPressure ( ) const
inline

Get current register pressure for the top scheduled instructions.

Definition at line 432 of file MachineScheduler.h.

References TopPressure.

const RegPressureTracker& llvm::ScheduleDAGMILive::getTopRPTracker ( ) const
inline

Definition at line 433 of file MachineScheduler.h.

References TopRPTracker.

Referenced by llvm::GCNMaxOccupancySchedStrategy::pickNode().

bool llvm::ScheduleDAGMILive::hasVRegLiveness ( ) const
inlineoverridevirtual

Return true if this DAG supports VReg liveness and RegPressure.

Reimplemented from llvm::ScheduleDAGMI.

Definition at line 426 of file MachineScheduler.h.

void ScheduleDAGMILive::initQueues ( ArrayRef< SUnit * >  TopRoots,
ArrayRef< SUnit * >  BotRoots 
)
protected

Release ExitSU predecessors and setup scheduler queues.

Re-position the Top RP tracker in case the region beginning has changed.

Definition at line 1308 of file MachineScheduler.cpp.

References assert(), llvm::ScheduleDAGMI::CurrentTop, llvm::RegPressureTracker::getPos(), llvm::ScheduleDAGMI::initQueues(), llvm::ScheduleDAGInstrs::RegionBegin, llvm::RegPressureTracker::setPos(), ShouldTrackPressure, and TopRPTracker.

Referenced by llvm::VLIWMachineScheduler::schedule(), llvm::SIScheduleDAGMI::schedule(), and schedule().

void ScheduleDAGMILive::initRegPressure ( )
protected
bool llvm::ScheduleDAGMILive::isTrackingPressure ( ) const
inline

Return true if register pressure tracking is enabled.

Definition at line 429 of file MachineScheduler.h.

References ShouldTrackPressure.

void ScheduleDAGMILive::schedule ( )
overridevirtual

Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

schedule - Called back from MachineScheduler::runOnMachineFunction after setting up the current scheduling region.

[RegionBegin, RegionEnd) only includes instructions that have DAG nodes, not scheduling boundaries.

This is a skeletal driver, with all the functionality pushed into helpers, so that it can be easily extended by experimental schedulers. Generally, implementing MachineSchedStrategy should be sufficient to implement a new scheduling algorithm. However, if a scheduler further subclasses ScheduleDAGMILive then it will want to override this virtual method in order to update any specialized state.

Reimplemented from llvm::ScheduleDAGMI.

Reimplemented in llvm::SIScheduleDAGMI, and llvm::VLIWMachineScheduler.

Definition at line 1114 of file MachineScheduler.cpp.

References assert(), llvm::ScheduleDAGInstrs::begin(), buildDAGWithRegPressure(), llvm::ScheduleDAGMI::checkSchedLimit(), llvm::ScheduleDAGMI::CurrentBottom, llvm::ScheduleDAGMI::CurrentTop, llvm::dbgs(), DEBUG, DFSResult, llvm::PressureDiff::dump(), llvm::SUnit::dumpAll(), llvm::ScheduleDAGMI::dumpSchedule(), llvm::ScheduleDAG::EntrySU, llvm::ScheduleDAG::ExitSU, llvm::ScheduleDAGMI::findRootsAndBiasEdges(), llvm::SUnit::getInstr(), getPressureDiff(), llvm::SchedDFSResult::getSubtreeID(), llvm::ScheduleDAGTopologicalSort::InitDAGTopologicalSorting(), initQueues(), llvm::SUnit::isScheduled, llvm::ScheduleDAGMI::placeDebugValues(), llvm::ScheduleDAGMI::postprocessDAG(), llvm::ScheduleDAGMI::SchedImpl, ScheduledTrees, scheduleMI(), llvm::SchedDFSResult::scheduleTree(), llvm::BitVector::set(), ShouldTrackPressure, llvm::ScheduleDAG::SUnits, llvm::BitVector::test(), llvm::ScheduleDAGMI::Topo, llvm::ScheduleDAG::TRI, llvm::ScheduleDAGMI::updateQueues(), llvm::ScheduleDAGMI::viewGraph(), and ViewMISchedDAGs.

void ScheduleDAGMILive::scheduleMI ( SUnit SU,
bool  IsTopNode 
)
protected
void ScheduleDAGMILive::updatePressureDiffs ( ArrayRef< RegisterMaskPair LiveUses)
protected
void ScheduleDAGMILive::updateScheduledPressure ( const SUnit SU,
const std::vector< unsigned > &  NewMaxPressure 
)
protected

Member Data Documentation

IntervalPressure llvm::ScheduleDAGMILive::BotPressure
protected

The bottom of the unscheduled zone.

Definition at line 407 of file MachineScheduler.h.

Referenced by getBotPressure().

RegPressureTracker llvm::ScheduleDAGMILive::BotRPTracker
protected
SchedDFSResult* llvm::ScheduleDAGMILive::DFSResult
protected

Information about DAG subtrees.

If DFSResult is NULL, then SchedulerTrees will be empty.

Definition at line 378 of file MachineScheduler.h.

Referenced by computeDFSResult(), getDFSResult(), schedule(), and ~ScheduleDAGMILive().

bool llvm::ScheduleDAGMILive::DisconnectedComponentsRenamed
protected

True if disconnected subregister components are already renamed.

The renaming is only done on demand if lane masks are tracked.

Definition at line 412 of file MachineScheduler.h.

MachineBasicBlock::iterator llvm::ScheduleDAGMILive::LiveRegionEnd
protected

Definition at line 381 of file MachineScheduler.h.

Referenced by buildDAGWithRegPressure(), enterRegion(), and initRegPressure().

RegisterClassInfo* llvm::ScheduleDAGMILive::RegClassInfo
protected
std::vector<PressureChange> llvm::ScheduleDAGMILive::RegionCriticalPSets
protected

List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing set ID order.

Each pressure set is paired with its max pressure in the currently scheduled regions.

Definition at line 400 of file MachineScheduler.h.

Referenced by buildDAGWithRegPressure(), getRegionCriticalPSets(), initRegPressure(), and updateScheduledPressure().

IntervalPressure llvm::ScheduleDAGMILive::RegPressure
protected

Definition at line 394 of file MachineScheduler.h.

Referenced by getRegPressure().

RegPressureTracker llvm::ScheduleDAGMILive::RPTracker
protected
BitVector llvm::ScheduleDAGMILive::ScheduledTrees
protected

Definition at line 379 of file MachineScheduler.h.

Referenced by computeDFSResult(), getScheduledTrees(), and schedule().

bool llvm::ScheduleDAGMILive::ShouldTrackLaneMasks
protected
bool llvm::ScheduleDAGMILive::ShouldTrackPressure
protected

Register pressure in this region computed by initRegPressure.

Definition at line 392 of file MachineScheduler.h.

Referenced by buildDAGWithRegPressure(), enterRegion(), initQueues(), isTrackingPressure(), schedule(), and scheduleMI().

PressureDiffs llvm::ScheduleDAGMILive::SUPressureDiffs
protected

Definition at line 389 of file MachineScheduler.h.

Referenced by buildDAGWithRegPressure(), enterRegion(), and getPressureDiff().

IntervalPressure llvm::ScheduleDAGMILive::TopPressure
protected

The top of the unscheduled zone.

Definition at line 403 of file MachineScheduler.h.

Referenced by getTopPressure().

RegPressureTracker llvm::ScheduleDAGMILive::TopRPTracker
protected
VReg2SUnitMultiMap llvm::ScheduleDAGMILive::VRegUses
protected

Maps vregs to the SUnits of their uses in the current scheduling region.

Definition at line 384 of file MachineScheduler.h.

Referenced by collectVRegUses(), computeCyclicCriticalPath(), initRegPressure(), and updatePressureDiffs().


The documentation for this class was generated from the following files: