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LLVM
4.0.0
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#include "HexagonRegisterInfo.h"#include "HexagonSubtarget.h"#include "HexagonTargetMachine.h"#include "HexagonVLIWPacketizer.h"#include "llvm/Analysis/AliasAnalysis.h"#include "llvm/CodeGen/MachineDominators.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/MachineLoopInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/Passes.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"Go to the source code of this file.
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| llvm | |
| Compute iterated dominance frontiers using a linear time algorithm. | |
Macros | |
| #define | DEBUG_TYPE "packets" |
Enumerations | |
| enum | PredicateKind { PK_False, PK_True, PK_Unknown } |
Variables | |
| static cl::opt< bool > | DisablePacketizer ("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass")) |
| static cl::opt< bool > | PacketizeVolatiles ("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references")) |
| static cl::opt< bool > | EnableGenAllInsnClass ("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC")) |
| static cl::opt< bool > | DisableVecDblNVStores ("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores")) |
| cl::opt< bool > | ScheduleInlineAsm |
| packets | |
| Hexagon | Packetizer |
| Hexagon | false |
| #define DEBUG_TYPE "packets" |
Definition at line 34 of file HexagonVLIWPacketizer.cpp.
| enum PredicateKind |
| Enumerator | |
|---|---|
| PK_False | |
| PK_True | |
| PK_Unknown | |
Definition at line 485 of file HexagonVLIWPacketizer.cpp.
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Definition at line 1024 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::HexagonInstrInfo::getType(), llvm::HexagonSubtarget::hasV60TOpsOnly(), llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isCall(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::isTerminator(), and llvm::HexagonII::TypeALU32.
Referenced by llvm::HexagonPacketizerList::cannotCoexist().
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Returns true if the instruction modifies a callee-saved register.
Definition at line 321 of file HexagonVLIWPacketizer.cpp.
References llvm::TargetRegisterInfo::getCalleeSavedRegs(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), and llvm::MachineInstr::modifiesRegister().
Referenced by llvm::HexagonPacketizerList::hasControlDependence().
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Definition at line 555 of file HexagonVLIWPacketizer.cpp.
References assert(), llvm::MachineInstr::getOperand(), and isLoadAbsSet().
Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore().
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Definition at line 502 of file HexagonVLIWPacketizer.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::HexagonInstrInfo::isPostIncrement(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::MachineInstr::mayLoad(), llvm::MCInstrDesc::mayStore(), and llvm::MachineInstr::operands().
Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore().
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Gets the predicate register of a predicated instruction.
We use the following rule: The first predicate register that is a use is the predicate register of a predicated instruction.
Definition at line 872 of file HexagonVLIWPacketizer.cpp.
References assert(), llvm::HexagonInstrInfo::isPredicated(), llvm_unreachable, and llvm::MachineInstr::operands().
Referenced by llvm::HexagonPacketizerList::arePredicatesComplements().
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Returns true if an instruction is predicated on p0 and false if it's predicated on !p0.
Definition at line 493 of file HexagonVLIWPacketizer.cpp.
References llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonInstrInfo::isPredicatedTrue(), PK_False, PK_True, and PK_Unknown.
Referenced by llvm::HexagonPacketizerList::arePredicatesComplements(), and llvm::HexagonPacketizerList::canPromoteToNewValueStore().
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Definition at line 536 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getNumOperands(), and llvm::MachineInstr::getOperand().
Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore().
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Definition at line 112 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::operands(), and llvm::MachineInstr::readsRegister().
Referenced by llvm::HexagonPacketizerList::unpacketizeSoloInstrs().
| INITIALIZE_PASS_BEGIN | ( | HexagonPacketizer | , |
| "packets" | , | ||
| "Hexagon Packetizer" | , | ||
| false | , | ||
| false | |||
| ) |
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Definition at line 315 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::isCall(), and llvm::MCInstrDesc::isTerminator().
Referenced by llvm::HexagonPacketizerList::hasControlDependence().
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Definition at line 1613 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), and llvm::MachineInstr::operands().
Referenced by llvm::MemoryDepChecker::areDepsSafe(), and llvm::HexagonPacketizerList::producesStall().
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Definition at line 303 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().
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Definition at line 761 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::operands().
Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew().
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Definition at line 541 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::canPromoteToNewValueStore(), and getAbsSetOperand().
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Definition at line 298 of file HexagonVLIWPacketizer.cpp.
References llvm::SDep::Anti, llvm::SDep::Data, and llvm::SDep::Output.
Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().
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Definition at line 307 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::isSoloInstruction().
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Definition at line 1101 of file HexagonVLIWPacketizer.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by llvm::HexagonPacketizerList::hasV4SpecificDependence().
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Definition at line 126 of file HexagonVLIWPacketizer.cpp.
References assert(), B, llvm::MachineInstr::BundledPred, llvm::MachineInstr::BundledSucc, llvm::MachineInstr::clearFlag(), E, llvm::MachineInstrBundleIterator< Ty, IsReverse >::getInstrIterator(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), I, llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isBundledWithPred(), llvm::MachineInstr::isBundledWithSucc(), llvm::MachineBasicBlock::splice(), and llvm::MachineInstr::unbundleFromPred().
Referenced by llvm::HexagonPacketizerList::unpacketizeSoloInstrs().
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Referenced by llvm::HexagonPacketizerList::canPromoteToDotNew().
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| Hexagon false |
Definition at line 98 of file HexagonVLIWPacketizer.cpp.
| Hexagon Packetizer |
Definition at line 98 of file HexagonVLIWPacketizer.cpp.
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Referenced by llvm::HexagonPacketizerList::isLegalToPacketizeTogether().
| packets |
Definition at line 98 of file HexagonVLIWPacketizer.cpp.
| cl::opt<bool> ScheduleInlineAsm |
1.8.6