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LLVM
4.0.0
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#include <ARMBaseInstrInfo.h>
Protected Member Functions | |
| ARMBaseInstrInfo (const ARMSubtarget &STI) | |
| void | expandLoadStackGuardBase (MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const |
| bool | getRegSequenceLikeInputs (const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. More... | |
| bool | getExtractSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. More... | |
| bool | getInsertSubregLikeInputs (const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. More... | |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override |
| Commutes the operands in the given instruction. More... | |
Definition at line 31 of file ARMBaseInstrInfo.h.
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Definition at line 86 of file ARMBaseInstrInfo.cpp.
References ARM_MLxTable, llvm::array_lengthof(), i, llvm::SmallSet< T, N, C >::insert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm_unreachable, and ARM_MLxEntry::MLxOpc.
| const MachineInstrBuilder & ARMBaseInstrInfo::AddDReg | ( | MachineInstrBuilder & | MIB, |
| unsigned | Reg, | ||
| unsigned | SubIdx, | ||
| unsigned | State, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Definition at line 860 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MCRegisterInfo::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().
Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot(), loadRegFromStackSlot(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), and storeRegToStackSlot().
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Definition at line 293 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), llvm::SmallVectorImpl< T >::clear(), llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), I, llvm::isCondBranchOpcode(), llvm::isIndirectBranchOpcode(), llvm::isJumpTableBranchOpcode(), isPredicated(), llvm::isUncondBranchOpcode(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 2306 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
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Definition at line 1872 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
It should only return true if the base pointers are the same and the only differences between the two addresses is the offset. It also returns the offsets by reference.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 1553 of file ARMBaseInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::isMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
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Definition at line 4588 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addRegisterKilled(), assert(), llvm::BuildMI(), contains(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MCRegisterInfo::isSuperRegister(), and MI.
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when scheduled after (within 4-cycle window) a fp MLA / MLS instruction.
Definition at line 395 of file ARMBaseInstrInfo.h.
References llvm::SmallSet< T, N, C >::count().
Referenced by llvm::ARMHazardRecognizer::getHazardType().
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Commutes the operands in the given instruction.
The commutable operands are specified by their indices OpIdx1 and OpIdx2.
Do not call this method for a non-commutable instruction or for non-commutable pair of operand indices OpIdx1 and OpIdx2. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 1808 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getInstrPredicate(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::ARMCC::getOppositeCondition().
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Definition at line 118 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMII::AddrMode2, llvm::ARMII::AddrMode3, llvm::ARMII::AddrModeMask, llvm::LiveVariables::addVirtualRegisterDead(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::BuildMI(), EnableARM3Addr, llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2Op(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::ARM_AM::getAM3Offset(), llvm::ARM_AM::getAM3Op(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getSORegOpc(), getUnindexedOpcode(), llvm::LiveVariables::getVarInfo(), i, llvm::ARMII::IndexModeMask, llvm::ARMII::IndexModePost, llvm::ARMII::IndexModePre, llvm::ARMII::IndexModeShift, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, llvm::MachineInstr::mayStore(), Offset, llvm::MachineInstr::readsRegister(), llvm::LiveVariables::VarInfo::removeKill(), llvm::MachineOperand::setIsDead(), llvm::ARM_AM::sub, llvm::MCInstrDesc::TSFlags, and VI.
| void ARMBaseInstrInfo::copyFromCPSR | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | DestReg, | ||
| bool | KillSrc, | ||
| const ARMSubtarget & | Subtarget | ||
| ) | const |
Definition at line 685 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::getKillRegState(), llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), and llvm::ARMSubtarget::isThumb().
Referenced by copyPhysReg().
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Definition at line 728 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), assert(), llvm::BuildMI(), contains(), copyFromCPSR(), copyToCPSR(), llvm::SmallSet< T, N, C >::count(), llvm::getKillRegState(), getRegisterInfo(), llvm::MCRegisterInfo::getSubReg(), i, llvm::SmallSet< T, N, C >::insert(), llvm::ARMSubtarget::isFPOnlySP(), llvm::ARMSubtarget::isThumb2(), and llvm::TargetRegisterInfo::regsOverlap().
Referenced by llvm::Thumb2InstrInfo::copyPhysReg().
| void ARMBaseInstrInfo::copyToCPSR | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| unsigned | SrcReg, | ||
| bool | KillSrc, | ||
| const ARMSubtarget & | Subtarget | ||
| ) | const |
Definition at line 706 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Define, llvm::getKillRegState(), llvm::RegState::Implicit, llvm::ARMSubtarget::isMClass(), and llvm::ARMSubtarget::isThumb().
Referenced by copyPhysReg().
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Definition at line 100 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetHazardRecognizer().
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Definition at line 111 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer(), llvm::ARMSubtarget::hasVFP2(), and llvm::ARMSubtarget::isThumb2().
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Definition at line 525 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::clobbersPhysReg(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isRegMask().
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Definition at line 1442 of file ARMBaseInstrInfo.cpp.
References llvm::TargetInstrInfo::duplicate(), duplicateCPV(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setIndex().
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Definition at line 4159 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addGlobalAddress(), assert(), llvm::BuildMI(), fuzzer::Flags, llvm::MachinePointerInfo::getGOT(), llvm::ARMSubtarget::isGVIndirectSymbol(), llvm::ARMSubtarget::isROPI(), llvm::ARMSubtarget::isRWPI(), llvm::RegState::Kill, MBB, llvm::ARMII::MO_NONLAZY, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, and llvm::MachineMemOperand::MOLoad.
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Definition at line 1289 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstr::addRegisterKilled(), assert(), contains(), llvm::dbgs(), DEBUG, llvm::MachineInstr::definesRegister(), llvm::ARMSubtarget::dontWidenVMOVS(), llvm::MachineBasicBlock::erase(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSubtarget(), llvm::RegState::Implicit, llvm::MachineInstr::isCopy(), llvm::MachineOperand::isDead(), llvm::ARMSubtarget::isFPOnlySP(), llvm::MachineOperand::isKill(), llvm::RTLIB::MEMCPY, MI, llvm::MachineInstr::readsRegister(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), and llvm::MachineOperand::setReg().
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FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
Definition at line 2679 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::ARM_AM::getT2SOImmTwoPartFirst(), llvm::ARM_AM::getT2SOImmTwoPartSecond(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MCInstrDesc::hasOptionalDef(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), llvm::ARM_AM::isSOImmTwoPartVal(), llvm::ARM_AM::isT2SOImmTwoPartVal(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), and UseMI.
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VFP/NEON execution domains.
Definition at line 4229 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::ARMII::DomainNEONA8, llvm::ARMII::DomainVFP, ExeGeneric, ExeNEON, ExeVFP, llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::ARMSubtarget::hasNEON(), llvm::ARMSubtarget::isCortexA8(), isPredicated(), llvm::MCInstrDesc::TSFlags, and llvm::ARMSubtarget::useNEONForFPMovs().
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Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
[out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
MI, DefIdx. False otherwise.Definition at line 4665 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isExtractSubregLike(), llvm_unreachable, llvm::MachineOperand::Reg, and llvm::ARMISD::VMOVRRD.
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Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
[out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
MI, DefIdx. False otherwise.Definition at line 4686 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isInsertSubregLike(), llvm_unreachable, and llvm::MachineOperand::Reg.
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GetInstSize - Returns the size of the specified MachineInstr.
GetInstSize - Return the size of the specified MachineInstr.
Definition at line 621 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, and MBB.
Referenced by llvm::computeBlockSize(), and GetFunctionSizeInBytes().
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Definition at line 103 of file ARMBaseInstrInfo.h.
| unsigned ARMBaseInstrInfo::getNumLDMAddresses | ( | const MachineInstr & | MI | ) | const |
Get the number of addresses by LDM or VLDM or zero for unknown.
Definition at line 3061 of file ARMBaseInstrInfo.cpp.
References E, I, llvm::MachineInstr::memoperands_begin(), and llvm::MachineInstr::memoperands_end().
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Definition at line 3110 of file ARMBaseInstrInfo.cpp.
References Desc, llvm::ARMSubtarget::DoubleIssue, llvm::ARMSubtarget::DoubleIssueCheckUnalignedAccess, getAlignment(), llvm::MachineInstr::getDesc(), llvm::ARMSubtarget::getLdStMultipleTiming(), llvm::InstrItineraryData::getNumMicroOps(), getNumMicroOpsSingleIssuePlusExtras(), getNumMicroOpsSwiftLdSt(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::getSchedClass(), llvm::MachineInstr::hasOneMemOperand(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isSwift(), llvm_unreachable, llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), llvm::MachineInstr::memoperands_begin(), llvm::ARMSubtarget::SingleIssue, and llvm::ARMSubtarget::SingleIssuePlusExtras.
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Definition at line 3713 of file ARMBaseInstrInfo.cpp.
References getBundledDefMI(), getBundledUseMI(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineInstr::isBundle(), llvm::MachineInstr::isCopyLike(), llvm::InstrItineraryData::isEmpty(), llvm::MachineInstr::isImplicitDef(), llvm::MachineInstr::isInsertSubreg(), llvm::MachineInstr::isRegSequence(), and UseMI.
Referenced by getOperandLatency().
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Definition at line 3810 of file ARMBaseInstrInfo.cpp.
References llvm::ARMSubtarget::checkVLDnAccessAlignment(), llvm::dyn_cast(), getAlignment(), llvm::ARM_AM::getAM2Offset(), llvm::ARM_AM::getAM2ShiftOpc(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getOpcode(), llvm::SDNode::getOperand(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment(), llvm::MCInstrDesc::getSchedClass(), llvm::ARMSubtarget::isCortexA7(), llvm::ARMSubtarget::isCortexA8(), llvm::InstrItineraryData::isEmpty(), llvm::ARMSubtarget::isLikeA9(), llvm::SDNode::isMachineOpcode(), llvm::ARMSubtarget::isSwift(), llvm::Latency, llvm::ARM_AM::lsl, llvm::ARM_AM::lsr, llvm::MCInstrDesc::mayLoad(), llvm::MachineSDNode::memoperands_begin(), llvm::MachineSDNode::memoperands_empty(), llvm::MCInstrDesc::Opcode, and Threshold.
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Definition at line 4527 of file ARMBaseInstrInfo.cpp.
References assert(), contains(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMSubtarget::getPartialUpdateClearance(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineOperand::readsReg(), and llvm::MachineInstr::readsVirtualRegister().
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Definition at line 144 of file ARMBaseInstrInfo.h.
References llvm::ARMCC::AL, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), and llvm::MachineInstr::getOperand().
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Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
[out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce two elements:
MI, DefIdx. False otherwise.Definition at line 4640 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isRegSequenceLike(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ARMISD::VMOVDRR.
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Definition at line 116 of file ARMBaseInstrInfo.h.
Referenced by expandPostRAPseudo(), llvm::ARMHazardRecognizer::getHazardType(), and isPredicable().
Implemented in llvm::Thumb2InstrInfo, llvm::ARMInstrInfo, and llvm::Thumb1InstrInfo.
Referenced by convertToThreeAddress().
| bool ARMBaseInstrInfo::hasNOP | ( | ) | const |
Definition at line 4622 of file ARMBaseInstrInfo.cpp.
Referenced by llvm::ARMInstrInfo::getNoopForMachoTarget().
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Definition at line 412 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), B, llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::MachineFunction::getInfo(), llvm::MachineBasicBlock::getParent(), isThumb(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::ARMFunctionInfo::isThumbFunction(), and llvm::ArrayRef< T >::size().
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
Definition at line 381 of file ARMBaseInstrInfo.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::count().
Referenced by llvm::ARMHazardRecognizer::getHazardType().
| bool ARMBaseInstrInfo::isFpMLxInstruction | ( | unsigned | Opcode, |
| unsigned & | MulOpc, | ||
| unsigned & | AddSubOpc, | ||
| bool & | NegAcc, | ||
| bool & | HasLane | ||
| ) | const |
isFpMLxInstruction - This version also returns the multiply opcode and the addition / subtraction opcode to expand to.
Return true for 'HasLane' for the MLX instructions with an extra lane operand.
Definition at line 4194 of file ARMBaseInstrInfo.cpp.
References ARM_MLxEntry::AddSubOpc, ARM_MLxTable, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), ARM_MLxEntry::HasLane, ARM_MLxEntry::MulOpc, and ARM_MLxEntry::NegAcc.
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Definition at line 1187 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
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Definition at line 1230 of file ARMBaseInstrInfo.cpp.
References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayLoad().
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isPredicable - Return true if the specified instruction can be predicated.
By default, this returns true for every instruction with a PredicateOperand.
Definition at line 579 of file ARMBaseInstrInfo.cpp.
References llvm::ARMII::DomainMask, llvm::ARMII::DomainNEON, llvm::MachineInstr::getDesc(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getSubtarget(), llvm::MachineInstr::isBundle(), isEligibleForITBlock(), llvm::MachineInstr::isPredicable(), llvm::ARMFunctionInfo::isThumb2Function(), llvm::isV8EligibleForIT(), llvm::ARMSubtarget::restrictIT(), and llvm::MCInstrDesc::TSFlags.
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Definition at line 462 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, E, llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), I, llvm::MachineBasicBlock::instr_end(), and llvm::MachineInstr::isBundle().
Referenced by analyzeBranch(), getExecutionDomain(), optimizeCompareInstr(), and setExecutionDomain().
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Definition at line 247 of file ARMBaseInstrInfo.h.
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Definition at line 1708 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::empty(), llvm::MachineFunction::getFunction(), llvm::getInstrPredicate(), llvm::ARMSubtarget::getMispredictionPenalty(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::isARMLowRegister(), llvm::Function::optForSize(), P, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::rbegin(), and llvm::BranchProbability::scale().
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Definition at line 1751 of file ARMBaseInstrInfo.cpp.
References llvm::BranchProbability::getCompl(), llvm::ARMSubtarget::getMispredictionPenalty(), and llvm::BranchProbability::scale().
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Definition at line 1774 of file ARMBaseInstrInfo.cpp.
References llvm::ARMSubtarget::isProfitableToUnpredicate().
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Definition at line 1664 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::isPosition(), llvm::MachineInstr::isTerminator(), and MI.
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Definition at line 1005 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
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Definition at line 1048 of file ARMBaseInstrInfo.cpp.
References llvm::NVPTXISD::Dummy, and llvm::MachineInstr::mayStore().
| bool ARMBaseInstrInfo::isSwiftFastImmShift | ( | const MachineInstr * | MI | ) | const |
Returns true if the instruction has a shift by immediate that can be executed in one cycle less.
Definition at line 4626 of file ARMBaseInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::ARM_AM::getSORegOffset(), llvm::ARM_AM::getSORegShOp(), llvm::ARM_AM::lsl, and llvm::ARM_AM::lsr.
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Definition at line 1055 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::DefineNoRead, llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::ARMSubtarget::hasV5TEOps(), llvm::RegState::ImplicitDefine, llvm::TargetRegisterInfo::isPhysicalRegister(), llvm_unreachable, and llvm::MachineMemOperand::MOLoad.
Referenced by llvm::Thumb2InstrInfo::loadRegFromStackSlot().
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optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparison with zero"; Remove a redundant CMP instruction if the flags can be updated in the same way by an earlier instruction such as SUB.
optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register; Remove a redundant Compare instruction if an earlier instruction can set the flags in the same way as Compare.
E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the condition code of instructions which use the flags.
Definition at line 2411 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, assert(), B, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), E, llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineInstr::eraseFromParent(), llvm::ARMCC::GE, llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, I, i, llvm::MachineOperand::isDef(), isPredicated(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), isSuitableForMask(), llvm::ARMCC::LE, LLVM_FALLTHROUGH, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, MBB, llvm::ARMCC::MI, MI, llvm::MachineInstr::modifiesRegister(), llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::readsRegister(), llvm::MachineOperand::setIsDef(), llvm::MachineOperand::setReg(), SI, llvm::SmallVectorTemplateCommon< T >::size(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::MachineRegisterInfo::use_instr_begin(), llvm::MachineRegisterInfo::use_instr_end(), llvm::ARMCC::VC, and llvm::ARMCC::VS.
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Definition at line 1894 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultCC(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), assert(), llvm::BuildMI(), canFoldIntoMOVCC(), llvm::MachineInstr::clearKillInfo(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::hasOptionalDef(), i, llvm::SmallPtrSetImpl< PtrType >::insert(), MI, MRI, llvm::MachineOperand::setImplicit(), and llvm::MachineInstr::tieOperands().
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Definition at line 478 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::getMatchingCondBranchOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), getReg(), llvm::isUncondBranchOpcode(), MI, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
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Definition at line 1458 of file ARMBaseInstrInfo.cpp.
References llvm::MachineConstantPoolEntry::ConstVal, llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstants(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getNumOperands(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::ARMConstantPoolValue::hasSameValue(), i, llvm::MachineInstr::IgnoreVRegDefs, llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineConstantPoolEntry::MachineCPVal, and llvm::MachineConstantPoolEntry::Val.
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Definition at line 1414 of file ARMBaseInstrInfo.cpp.
References llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), duplicateCPV(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::MachineInstr::setMemRefs(), and llvm::MachineInstr::substituteRegister().
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Definition at line 385 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), I, llvm::isCondBranchOpcode(), and llvm::isUncondBranchOpcode().
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Definition at line 456 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::getOppositeCondition().
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Definition at line 4319 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::RegState::Define, ExeNEON, getCorrespondingDRegAndLane(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), getImplicitSPRUseForDPRUse(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::getUndefRegState(), llvm::ARMSubtarget::hasNEON(), i, llvm::RegState::Implicit, isPredicated(), llvm_unreachable, MI, llvm::MachineInstr::readsRegister(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
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shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched is permanently disabled.
Definition at line 1634 of file ARMBaseInstrInfo.cpp.
References assert(), llvm::SDNode::getMachineOpcode(), and llvm::ARMSubtarget::isThumb1Only().
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Definition at line 872 of file ARMBaseInstrInfo.cpp.
References llvm::AddDefaultPred(), AddDReg(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::ARMSubtarget::hasV5TEOps(), llvm_unreachable, and llvm::MachineMemOperand::MOStore.
Referenced by llvm::Thumb2InstrInfo::storeRegToStackSlot().
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Definition at line 499 of file ARMBaseInstrInfo.cpp.
References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, and llvm::ArrayRef< T >::size().
1.8.6