90 using namespace llvm::X86Disassembler;
92 #define DEBUG_TYPE "x86-disassembler"
96 dbgs() << file <<
":" << line <<
": " << s;
105 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s));
135 std::unique_ptr<const MCInstrInfo> MII;
138 std::unique_ptr<const MCInstrInfo> MII);
151 X86GenericDisassembler::X86GenericDisassembler(
154 std::unique_ptr<const MCInstrInfo> MII)
157 if (FB[X86::Mode16Bit]) {
160 }
else if (FB[X86::Mode32Bit]) {
163 }
else if (FB[X86::Mode64Bit]) {
186 auto *R =
static_cast<const Region *
>(Arg);
188 unsigned Index = Address - R->Base;
189 if (Bytes.
size() <= Index)
191 *Byte = Bytes[Index];
201 static void logger(
void* arg,
const char* log) {
206 vStream << log <<
"\n";
216 CommentStream = &CStream;
221 if (&VStream == &
nulls())
227 LoggerFn, (
void *)&VStream,
228 (
const void *)MII.get(),
Address, fMode);
234 Size = InternalInstr.
length;
249 #define ENTRY(x) X86::x,
250 uint8_t llvmRegnums[] = {
256 uint8_t llvmRegnum = llvmRegnums[reg];
280 uint64_t Address, uint64_t
Offset,
295 const void *Decoder) {
371 if (type == TYPE_RELv) {
380 immediate |= ~(0xffull);
383 if(immediate & 0x8000)
384 immediate |= ~(0xffffull);
387 if(immediate & 0x80000000)
388 immediate |= ~(0xffffffffull);
395 else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
396 type == TYPE_IMM64 || type == TYPE_IMMv) {
402 immediate |= ~(0xffull);
405 if(immediate & 0x8000)
406 immediate |= ~(0xffffull);
409 if(immediate & 0x80000000)
410 immediate |= ~(0xffffffffull);
415 }
else if (type == TYPE_IMM3) {
417 if (immediate >= 8) {
421 case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt;
break;
422 case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt;
break;
423 case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt;
break;
424 case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt;
break;
425 case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt;
break;
426 case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt;
break;
427 case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt;
break;
428 case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt;
break;
429 case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt;
break;
430 case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt;
break;
431 case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt;
break;
432 case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt;
break;
433 case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt;
break;
434 case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt;
break;
435 case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt;
break;
436 case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt;
break;
437 case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt;
break;
438 case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt;
break;
439 case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt;
break;
440 case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt;
break;
441 case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt;
break;
442 case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt;
break;
443 case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt;
break;
444 case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt;
break;
449 }
else if (type == TYPE_IMM5) {
451 if (immediate >= 32) {
455 case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt;
break;
456 case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt;
break;
457 case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt;
break;
458 case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt;
break;
459 case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt;
break;
460 case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt;
break;
461 case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt;
break;
462 case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt;
break;
463 case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt;
break;
464 case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt;
break;
465 case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt;
break;
466 case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt;
break;
467 case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt;
break;
468 case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt;
break;
469 case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt;
break;
470 case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt;
break;
471 case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt;
break;
472 case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt;
break;
473 case X86::VCMPPDZ128rmi: NewOpc = X86::VCMPPDZ128rmi_alt;
break;
474 case X86::VCMPPDZ128rri: NewOpc = X86::VCMPPDZ128rri_alt;
break;
475 case X86::VCMPPSZ128rmi: NewOpc = X86::VCMPPSZ128rmi_alt;
break;
476 case X86::VCMPPSZ128rri: NewOpc = X86::VCMPPSZ128rri_alt;
break;
477 case X86::VCMPPDZ256rmi: NewOpc = X86::VCMPPDZ256rmi_alt;
break;
478 case X86::VCMPPDZ256rri: NewOpc = X86::VCMPPDZ256rri_alt;
break;
479 case X86::VCMPPSZ256rmi: NewOpc = X86::VCMPPSZ256rmi_alt;
break;
480 case X86::VCMPPSZ256rri: NewOpc = X86::VCMPPSZ256rri_alt;
break;
481 case X86::VCMPSDZrm_Int: NewOpc = X86::VCMPSDZrmi_alt;
break;
482 case X86::VCMPSDZrr_Int: NewOpc = X86::VCMPSDZrri_alt;
break;
483 case X86::VCMPSDZrrb_Int: NewOpc = X86::VCMPSDZrrb_alt;
break;
484 case X86::VCMPSSZrm_Int: NewOpc = X86::VCMPSSZrmi_alt;
break;
485 case X86::VCMPSSZrr_Int: NewOpc = X86::VCMPSSZrri_alt;
break;
486 case X86::VCMPSSZrrb_Int: NewOpc = X86::VCMPSSZrrb_alt;
break;
491 }
else if (type == TYPE_AVX512ICC) {
492 if (immediate >= 8 || ((immediate & 0x3) == 3)) {
496 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt;
break;
497 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt;
break;
498 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt;
break;
499 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt;
break;
500 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt;
break;
501 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt;
break;
502 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt;
break;
503 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt;
break;
504 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt;
break;
505 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt;
break;
506 case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt;
break;
507 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt;
break;
508 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt;
break;
509 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt;
break;
510 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt;
break;
511 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt;
break;
512 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt;
break;
513 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt;
break;
514 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt;
break;
515 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt;
break;
516 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt;
break;
517 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt;
break;
518 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt;
break;
519 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt;
break;
520 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt;
break;
521 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt;
break;
522 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt;
break;
523 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt;
break;
524 case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt;
break;
525 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt;
break;
526 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt;
break;
527 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt;
break;
528 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt;
break;
529 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt;
break;
530 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt;
break;
531 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt;
break;
532 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt;
break;
533 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt;
break;
534 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt;
break;
535 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt;
break;
536 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt;
break;
537 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt;
break;
538 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt;
break;
539 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt;
break;
540 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt;
break;
541 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt;
break;
542 case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt;
break;
543 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt;
break;
544 case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt;
break;
545 case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt;
break;
546 case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt;
break;
547 case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt;
break;
548 case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt;
break;
549 case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt;
break;
550 case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt;
break;
551 case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt;
break;
552 case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt;
break;
553 case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt;
break;
554 case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt;
break;
555 case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt;
break;
556 case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt;
break;
557 case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt;
break;
558 case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt;
break;
559 case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt;
break;
560 case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt;
break;
561 case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt;
break;
562 case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt;
break;
563 case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt;
break;
564 case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt;
break;
565 case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt;
break;
566 case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt;
break;
567 case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt;
break;
568 case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt;
break;
569 case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt;
break;
570 case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt;
break;
571 case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt;
break;
572 case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt;
break;
573 case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt;
break;
574 case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt;
break;
575 case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt;
break;
576 case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt;
break;
577 case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt;
break;
578 case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt;
break;
579 case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt;
break;
580 case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt;
break;
581 case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt;
break;
582 case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt;
break;
583 case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt;
break;
584 case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt;
break;
585 case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt;
break;
586 case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt;
break;
587 case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt;
break;
588 case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt;
break;
589 case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt;
break;
590 case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt;
break;
591 case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt;
break;
592 case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt;
break;
593 case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt;
break;
594 case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt;
break;
595 case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt;
break;
596 case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt;
break;
597 case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt;
break;
598 case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt;
break;
599 case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt;
break;
600 case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt;
break;
601 case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt;
break;
602 case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt;
break;
603 case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt;
break;
604 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt;
break;
605 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt;
break;
606 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt;
break;
607 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt;
break;
608 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt;
break;
609 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt;
break;
610 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt;
break;
611 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt;
break;
612 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt;
break;
613 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt;
break;
614 case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt;
break;
615 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt;
break;
639 if (immediate & 0x80)
640 immediate |= ~(0xffull);
645 if (immediate & 0x8000)
646 immediate |= ~(0xffffull);
652 if(immediate & 0x80000000)
653 immediate |= ~(0xffffffffull);
665 if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
666 type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
681 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
682 debug(
"A R/M register operand may not have a SIB byte");
688 debug(
"Unexpected EA base register");
691 debug(
"EA_BASE_NONE for ModR/M base");
693 #define ENTRY(x) case EA_BASE_##x:
696 debug(
"A R/M register operand may not have a base; "
697 "the operand must be a register.");
701 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
738 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
742 debug(
"Unexpected sibBase");
746 baseReg = MCOperand::createReg(X86::x); break;
761 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
762 Opcode == X86::VGATHERDPDYrm ||
763 Opcode == X86::VGATHERQPDrm ||
764 Opcode == X86::VGATHERDPSrm ||
765 Opcode == X86::VGATHERQPSrm ||
766 Opcode == X86::VPGATHERDQrm ||
767 Opcode == X86::VPGATHERDQYrm ||
768 Opcode == X86::VPGATHERQQrm ||
769 Opcode == X86::VPGATHERDDrm ||
770 Opcode == X86::VPGATHERQDrm);
771 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
772 Opcode == X86::VGATHERDPSYrm ||
773 Opcode == X86::VGATHERQPSYrm ||
774 Opcode == X86::VGATHERDPDZrm ||
775 Opcode == X86::VPGATHERDQZrm ||
776 Opcode == X86::VPGATHERQQYrm ||
777 Opcode == X86::VPGATHERDDYrm ||
778 Opcode == X86::VPGATHERQDYrm);
779 bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
780 Opcode == X86::VGATHERDPSZrm ||
781 Opcode == X86::VGATHERQPSZrm ||
782 Opcode == X86::VPGATHERQQZrm ||
783 Opcode == X86::VPGATHERDDZrm ||
784 Opcode == X86::VPGATHERQDZrm);
785 if (IndexIs128 || IndexIs256 || IndexIs512) {
786 unsigned IndexOffset = insn.
sibIndex -
787 (insn.
addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
788 SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
789 IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
797 debug(
"Unexpected sibIndex");
800 case SIB_INDEX_##x: \
801 indexReg = MCOperand::createReg(X86::x); break;
818 debug(
"EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
854 debug(
"Unexpected eaBase");
862 baseReg = MCOperand::createReg(X86::x); break;
865 #define ENTRY(x) case EA_REG_##x:
868 debug(
"A R/M memory operand may not be a register; "
869 "the base field must be a base.");
902 switch (operand.
type) {
904 debug(
"Unexpected type for a R/M operand");
925 case TYPE_CONTROLREG:
965 uint8_t maskRegNum) {
966 if (maskRegNum >= 8) {
967 debug(
"Invalid mask register number");
987 debug(
"Unhandled operand encoding during translation");
992 case ENCODING_WRITEMASK:
1041 debug(
"Instruction has no specification");
1051 if(mcInst.
getOpcode() == X86::REP_PREFIX)
1053 else if(mcInst.
getOpcode() == X86::REPNE_PREFIX)
1060 if (
Op.encoding != ENCODING_NONE) {
1074 return new X86GenericDisassembler(STI, Ctx, std::move(MII));
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
SIBIndex
All possible values of the SIB index field.
static MCOperand createReg(unsigned Reg)
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Reg
All possible values of the reg field in the ModR/M byte.
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst...
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form, and appends it to an MCInst.
Context object for machine code objects.
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register, and appends it as an operand to an MCInst.
uint8_t numImmediatesTranslated
SegmentOverride segmentOverride
static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
Region(BasicBlock *Entry, BasicBlock *Exit, RegionInfo *RI, DominatorTree *DT, Region *Parent=nullptr)
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
uint8_t prefixPresent[0x100]
size_t size() const
size - Get the array size.
Instances of this class represent a single low-level machine instruction.
The specification for how to extract and interpret one operand.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address)
A callback function that wraps the readByte method from Region.
Interface to description of machine instruction set.
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
dot regions Print regions of function to dot file(with no function bodies)"
void Debug(const char *file, unsigned line, const char *s)
Print a message to debugs()
The x86 internal instruction, which is produced by the decoder.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
StringRef GetInstrName(unsigned Opcode, const void *mii)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EADisplacement eaDisplacement
void setOpcode(unsigned Op)
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
ArrayRef< OperandSpecifier > operands
const InstructionSpecifier * spec
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void(* dlog_t)(void *arg, const char *log)
Type for the logging function that the consumer can provide to get debugging output from the decoder...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void LLVMInitializeX86Disassembler()
unsigned getOpcode() const
Target - Wrapper for Target specific information.
uint8_t displacementOffset
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
OperandType
Types of operands to CF instructions.
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
MCSubtargetInfo - Generic base class for all target subtargets.
static void logger(void *arg, const char *log)
logger - a callback function that wraps the operator<< method from raw_ostream.
Target & getTheX86_32Target()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
LLVM Value Representation.
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Dis)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
Instances of this class represent operands of the MCInst class.
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
Target & getTheX86_64Target()
static MCOperand createImm(int64_t Val)
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
DisassemblerMode
Decoding mode for the Intel disassembler.