16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
32 class MCSubtargetInfo;
120 bool IsBranch, uint64_t
Offset,
121 uint64_t InstSize)
override;
130 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
~AMDGPUDisassembler() override=default
std::unique_ptr< MCRelocationInfo > RelInfo
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Superclass for all disassemblers.
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeOperand_VS_64(unsigned Val) const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
MCOperand decodeOperand_VReg_96(unsigned Val) const
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Context object for machine code objects.
const MCSubtargetInfo & STI
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeSpecialReg32(unsigned Val) const
Instances of this class represent a single low-level machine instruction.
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
MCOperand decodeOperand_SReg_512(unsigned Val) const
Symbolize and annotate disassembled instructions.
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
MCOperand decodeOperand_SReg_128(unsigned Val) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeOperand_VSrc16(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
MCOperand decodeOperand_VReg_128(unsigned Val) const
static MCOperand decodeIntImmed(unsigned Imm)
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
MCOperand decodeSpecialReg64(unsigned Val) const
MCSubtargetInfo - Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
unsigned getVgprClassId(const OpWidthTy Width) const
LLVM Value Representation.
MCOperand decodeOperand_SReg_64(unsigned Val) const
This class implements an extremely fast bulk output stream that can only output to a stream...
MCOperand decodeLiteralConstant() const
MCOperand decodeOperand_SReg_256(unsigned Val) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Instances of this class represent operands of the MCInst class.