LLVM  4.0.0
X86Subtarget.h
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1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
16 
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
23 #include "llvm/IR/CallingConv.h"
25 #include <string>
26 
27 #define GET_SUBTARGETINFO_HEADER
28 #include "X86GenSubtargetInfo.inc"
29 
30 namespace llvm {
31 class GlobalValue;
32 class StringRef;
33 class TargetMachine;
34 
35 /// The X86 backend supports a number of different styles of PIC.
36 ///
37 namespace PICStyles {
38 enum Style {
39  StubPIC, // Used on i386-darwin in pic mode.
40  GOT, // Used on 32 bit elf on when in pic mode.
41  RIPRel, // Used on X86-64 when in pic mode.
42  None // Set when not in pic mode.
43 };
44 }
45 
46 class X86Subtarget final : public X86GenSubtargetInfo {
47 
48 protected:
49  enum X86SSEEnum {
51  };
52 
53  enum X863DNowEnum {
55  };
56 
59  };
60 
61  /// X86 processor family: Intel Atom, and others
63 
64  /// Which PIC style to use
66 
67  const TargetMachine &TM;
68 
69  /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
71 
72  /// MMX, 3DNow, 3DNow Athlon, or none supported.
74 
75  /// True if the processor supports X87 instructions.
76  bool HasX87;
77 
78  /// True if this processor has conditional move instructions
79  /// (generally pentium pro+).
80  bool HasCMov;
81 
82  /// True if the processor supports X86-64 instructions.
83  bool HasX86_64;
84 
85  /// True if the processor supports POPCNT.
86  bool HasPOPCNT;
87 
88  /// True if the processor supports SSE4A instructions.
89  bool HasSSE4A;
90 
91  /// Target has AES instructions
92  bool HasAES;
93 
94  /// Target has FXSAVE/FXRESTOR instructions
95  bool HasFXSR;
96 
97  /// Target has XSAVE instructions
98  bool HasXSAVE;
99  /// Target has XSAVEOPT instructions
101  /// Target has XSAVEC instructions
102  bool HasXSAVEC;
103  /// Target has XSAVES instructions
104  bool HasXSAVES;
105 
106  /// Target has carry-less multiplication
107  bool HasPCLMUL;
108 
109  /// Target has 3-operand fused multiply-add
110  bool HasFMA;
111 
112  /// Target has 4-operand fused multiply-add
113  bool HasFMA4;
114 
115  /// Target has XOP instructions
116  bool HasXOP;
117 
118  /// Target has TBM instructions.
119  bool HasTBM;
120 
121  /// True if the processor has the MOVBE instruction.
122  bool HasMOVBE;
123 
124  /// True if the processor has the RDRAND instruction.
125  bool HasRDRAND;
126 
127  /// Processor has 16-bit floating point conversion instructions.
128  bool HasF16C;
129 
130  /// Processor has FS/GS base insturctions.
132 
133  /// Processor has LZCNT instruction.
134  bool HasLZCNT;
135 
136  /// Processor has BMI1 instructions.
137  bool HasBMI;
138 
139  /// Processor has BMI2 instructions.
140  bool HasBMI2;
141 
142  /// Processor has VBMI instructions.
143  bool HasVBMI;
144 
145  /// Processor has Integer Fused Multiply Add
146  bool HasIFMA;
147 
148  /// Processor has RTM instructions.
149  bool HasRTM;
150 
151  /// Processor has HLE.
152  bool HasHLE;
153 
154  /// Processor has ADX instructions.
155  bool HasADX;
156 
157  /// Processor has SHA instructions.
158  bool HasSHA;
159 
160  /// Processor has PRFCHW instructions.
161  bool HasPRFCHW;
162 
163  /// Processor has RDSEED instructions.
164  bool HasRDSEED;
165 
166  /// Processor has LAHF/SAHF instructions.
168 
169  /// Processor has MONITORX/MWAITX instructions.
170  bool HasMWAITX;
171 
172  /// Processor has Prefetch with intent to Write instruction
174 
175  /// True if BT (bit test) of memory instructions are slow.
177 
178  /// True if SHLD instructions are slow.
180 
181  /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
182  // PMULUDQ.
184 
185  /// True if unaligned memory accesses of 16-bytes are slow.
187 
188  /// True if unaligned memory accesses of 32-bytes are slow.
190 
191  /// True if SSE operations can have unaligned memory operands.
192  /// This may require setting a configuration bit in the processor.
194 
195  /// True if this processor has the CMPXCHG16B instruction;
196  /// this is true for most x86-64 chips, but not the first AMD chips.
198 
199  /// True if the LEA instruction should be used for adjusting
200  /// the stack pointer. This is an optimization for Intel Atom processors.
202 
203  /// True if there is no performance penalty to writing only the lower parts
204  /// of a YMM register without clearing the upper part.
206 
207  /// True if hardware SQRTSS instruction is at least as fast (latency) as
208  /// RSQRTSS followed by a Newton-Raphson iteration.
210 
211  /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
212  /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
214 
215  /// True if 8-bit divisions are significantly faster than
216  /// 32-bit divisions and should be used when possible.
218 
219  /// True if 32-bit divides are significantly faster than
220  /// 64-bit divisions and should be used when possible.
222 
223  /// True if LZCNT instruction is fast.
225 
226  /// True if the short functions should be padded to prevent
227  /// a stall when returning too early.
229 
230  /// True if the Calls with memory reference should be converted
231  /// to a register-based indirect call.
233 
234  /// True if the LEA instruction inputs have to be ready at address generation
235  /// (AG) time.
236  bool LEAUsesAG;
237 
238  /// True if the LEA instruction with certain arguments is slow
239  bool SlowLEA;
240 
241  /// True if INC and DEC instructions are slow when writing to flags
243 
244  /// Processor has AVX-512 PreFetch Instructions
245  bool HasPFI;
246 
247  /// Processor has AVX-512 Exponential and Reciprocal Instructions
248  bool HasERI;
249 
250  /// Processor has AVX-512 Conflict Detection Instructions
251  bool HasCDI;
252 
253  /// Processor has AVX-512 Doubleword and Quadword instructions
254  bool HasDQI;
255 
256  /// Processor has AVX-512 Byte and Word instructions
257  bool HasBWI;
258 
259  /// Processor has AVX-512 Vector Length eXtenstions
260  bool HasVLX;
261 
262  /// Processor has PKU extenstions
263  bool HasPKU;
264 
265  /// Processor supports MPX - Memory Protection Extensions
266  bool HasMPX;
267 
268  /// Processor supports Invalidate Process-Context Identifier
270 
271  /// Processor has VM Functions
272  bool HasVMFUNC;
273 
274  /// Processor has Supervisor Mode Access Protection
275  bool HasSMAP;
276 
277  /// Processor has Software Guard Extensions
278  bool HasSGX;
279 
280  /// Processor supports Flush Cache Line instruction
282 
283  /// Processor has Persistent Commit feature
285 
286  /// Processor supports Cache Line Write Back instruction
287  bool HasCLWB;
288 
289  /// Use software floating point for code generation.
291 
292  /// The minimum alignment known to hold of the stack frame on
293  /// entry to the function and which must be maintained by every function.
294  unsigned stackAlignment;
295 
296  /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
297  ///
299 
300  /// What processor and OS we're targeting.
302 
303  /// Instruction itineraries for scheduling
305 
306  /// Gather the accessor points to GlobalISel-related APIs.
307  /// This is used to avoid ifndefs spreading around while GISel is
308  /// an optional library.
309  std::unique_ptr<GISelAccessor> GISel;
310 private:
311 
312  /// Override the stack alignment.
313  unsigned StackAlignOverride;
314 
315  /// True if compiling for 64-bit, false for 16-bit or 32-bit.
316  bool In64BitMode;
317 
318  /// True if compiling for 32-bit, false for 16-bit or 64-bit.
319  bool In32BitMode;
320 
321  /// True if compiling for 16-bit, false for 32-bit or 64-bit.
322  bool In16BitMode;
323 
324  X86SelectionDAGInfo TSInfo;
325  // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
326  // X86TargetLowering needs.
327  X86InstrInfo InstrInfo;
328  X86TargetLowering TLInfo;
329  X86FrameLowering FrameLowering;
330 
331 public:
332  /// This constructor initializes the data members to match that
333  /// of the specified triple.
334  ///
335  X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
336  const X86TargetMachine &TM, unsigned StackAlignOverride);
337 
338  /// This object will take onwership of \p GISelAccessor.
339  void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); }
340 
341  const X86TargetLowering *getTargetLowering() const override {
342  return &TLInfo;
343  }
344  const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
345  const X86FrameLowering *getFrameLowering() const override {
346  return &FrameLowering;
347  }
348  const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
349  return &TSInfo;
350  }
351  const X86RegisterInfo *getRegisterInfo() const override {
352  return &getInstrInfo()->getRegisterInfo();
353  }
354 
355  /// Returns the minimum alignment known to hold of the
356  /// stack frame on entry to the function and which must be maintained by every
357  /// function for this subtarget.
358  unsigned getStackAlignment() const { return stackAlignment; }
359 
360  /// Returns the maximum memset / memcpy size
361  /// that still makes it profitable to inline the call.
363 
364  /// ParseSubtargetFeatures - Parses features string setting specified
365  /// subtarget options. Definition of function is auto generated by tblgen.
367 
368  /// Methods used by Global ISel
369  const CallLowering *getCallLowering() const override;
370  const InstructionSelector *getInstructionSelector() const override;
371  const LegalizerInfo *getLegalizerInfo() const override;
372  const RegisterBankInfo *getRegBankInfo() const override;
373 private:
374  /// Initialize the full set of dependencies so we can use an initializer
375  /// list for X86Subtarget.
376  X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
377  void initializeEnvironment();
378  void initSubtargetFeatures(StringRef CPU, StringRef FS);
379 public:
380  /// Is this x86_64? (disregarding specific ABI / programming model)
381  bool is64Bit() const {
382  return In64BitMode;
383  }
384 
385  bool is32Bit() const {
386  return In32BitMode;
387  }
388 
389  bool is16Bit() const {
390  return In16BitMode;
391  }
392 
393  /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
394  bool isTarget64BitILP32() const {
395  return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
397  }
398 
399  /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
400  bool isTarget64BitLP64() const {
401  return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
403  }
404 
407 
408  bool hasX87() const { return HasX87; }
409  bool hasCMov() const { return HasCMov; }
410  bool hasSSE1() const { return X86SSELevel >= SSE1; }
411  bool hasSSE2() const { return X86SSELevel >= SSE2; }
412  bool hasSSE3() const { return X86SSELevel >= SSE3; }
413  bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
414  bool hasSSE41() const { return X86SSELevel >= SSE41; }
415  bool hasSSE42() const { return X86SSELevel >= SSE42; }
416  bool hasAVX() const { return X86SSELevel >= AVX; }
417  bool hasAVX2() const { return X86SSELevel >= AVX2; }
418  bool hasAVX512() const { return X86SSELevel >= AVX512F; }
419  bool hasFp256() const { return hasAVX(); }
420  bool hasInt256() const { return hasAVX2(); }
421  bool hasSSE4A() const { return HasSSE4A; }
422  bool hasMMX() const { return X863DNowLevel >= MMX; }
423  bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
424  bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
425  bool hasPOPCNT() const { return HasPOPCNT; }
426  bool hasAES() const { return HasAES; }
427  bool hasFXSR() const { return HasFXSR; }
428  bool hasXSAVE() const { return HasXSAVE; }
429  bool hasXSAVEOPT() const { return HasXSAVEOPT; }
430  bool hasXSAVEC() const { return HasXSAVEC; }
431  bool hasXSAVES() const { return HasXSAVES; }
432  bool hasPCLMUL() const { return HasPCLMUL; }
433  // Prefer FMA4 to FMA - its better for commutation/memory folding and
434  // has equal or better performance on all supported targets.
435  bool hasFMA() const { return HasFMA && !HasFMA4; }
436  bool hasFMA4() const { return HasFMA4; }
437  bool hasAnyFMA() const { return hasFMA() || hasFMA4() || hasAVX512(); }
438  bool hasXOP() const { return HasXOP; }
439  bool hasTBM() const { return HasTBM; }
440  bool hasMOVBE() const { return HasMOVBE; }
441  bool hasRDRAND() const { return HasRDRAND; }
442  bool hasF16C() const { return HasF16C; }
443  bool hasFSGSBase() const { return HasFSGSBase; }
444  bool hasLZCNT() const { return HasLZCNT; }
445  bool hasBMI() const { return HasBMI; }
446  bool hasBMI2() const { return HasBMI2; }
447  bool hasVBMI() const { return HasVBMI; }
448  bool hasIFMA() const { return HasIFMA; }
449  bool hasRTM() const { return HasRTM; }
450  bool hasHLE() const { return HasHLE; }
451  bool hasADX() const { return HasADX; }
452  bool hasSHA() const { return HasSHA; }
453  bool hasPRFCHW() const { return HasPRFCHW; }
454  bool hasRDSEED() const { return HasRDSEED; }
455  bool hasLAHFSAHF() const { return HasLAHFSAHF; }
456  bool hasMWAITX() const { return HasMWAITX; }
457  bool isBTMemSlow() const { return IsBTMemSlow; }
458  bool isSHLDSlow() const { return IsSHLDSlow; }
459  bool isPMULLDSlow() const { return IsPMULLDSlow; }
460  bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
461  bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
462  bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
463  bool hasCmpxchg16b() const { return HasCmpxchg16b; }
464  bool useLeaForSP() const { return UseLeaForSP; }
466  bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
467  bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
468  bool hasFastLZCNT() const { return HasFastLZCNT; }
469  bool hasSlowDivide32() const { return HasSlowDivide32; }
470  bool hasSlowDivide64() const { return HasSlowDivide64; }
471  bool padShortFunctions() const { return PadShortFunctions; }
472  bool callRegIndirect() const { return CallRegIndirect; }
473  bool LEAusesAG() const { return LEAUsesAG; }
474  bool slowLEA() const { return SlowLEA; }
475  bool slowIncDec() const { return SlowIncDec; }
476  bool hasCDI() const { return HasCDI; }
477  bool hasPFI() const { return HasPFI; }
478  bool hasERI() const { return HasERI; }
479  bool hasDQI() const { return HasDQI; }
480  bool hasBWI() const { return HasBWI; }
481  bool hasVLX() const { return HasVLX; }
482  bool hasPKU() const { return HasPKU; }
483  bool hasMPX() const { return HasMPX; }
484 
485  virtual bool isXRaySupported() const override { return is64Bit(); }
486 
487  bool isAtom() const { return X86ProcFamily == IntelAtom; }
488  bool isSLM() const { return X86ProcFamily == IntelSLM; }
489  bool useSoftFloat() const { return UseSoftFloat; }
490 
491  /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
492  /// no-sse2). There isn't any reason to disable it if the target processor
493  /// supports it.
494  bool hasMFence() const { return hasSSE2() || is64Bit(); }
495 
496  const Triple &getTargetTriple() const { return TargetTriple; }
497 
498  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
499  bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
500  bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
501  bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
502  bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
503 
504  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
505  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
506  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
507 
508  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
509  bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
510  bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
511  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
512  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
513  bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
514  bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
515  bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
516 
517  bool isTargetWindowsMSVC() const {
519  }
520 
523  }
524 
525  bool isTargetWindowsCoreCLR() const {
527  }
528 
529  bool isTargetWindowsCygwin() const {
531  }
532 
533  bool isTargetWindowsGNU() const {
535  }
536 
537  bool isTargetWindowsItanium() const {
539  }
540 
541  bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
542 
543  bool isOSWindows() const { return TargetTriple.isOSWindows(); }
544 
545  bool isTargetWin64() const {
546  return In64BitMode && TargetTriple.isOSWindows();
547  }
548 
549  bool isTargetWin32() const {
550  return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
551  }
552 
553  bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
554  bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
555 
556  bool isPICStyleStubPIC() const {
557  return PICStyle == PICStyles::StubPIC;
558  }
559 
560  bool isPositionIndependent() const { return TM.isPositionIndependent(); }
561 
563  switch (CC) {
564  // On Win64, all these conventions just use the default convention.
565  case CallingConv::C:
566  case CallingConv::Fast:
572  return isTargetWin64();
573  // This convention allows using the Win64 convention on other targets.
575  return true;
576  // This convention allows using the SysV convention on Windows targets.
578  return false;
579  // Otherwise, who knows what this is.
580  default:
581  return false;
582  }
583  }
584 
585  /// Classify a global variable reference for the current subtarget according
586  /// to how we should reference it in a non-pcrel context.
587  unsigned char classifyLocalReference(const GlobalValue *GV) const;
588 
589  unsigned char classifyGlobalReference(const GlobalValue *GV,
590  const Module &M) const;
591  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
592 
593  /// Classify a global function reference for the current subtarget.
594  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
595  const Module &M) const;
596  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
597 
598  /// Classify a blockaddress reference for the current subtarget according to
599  /// how we should reference it in a non-pcrel context.
600  unsigned char classifyBlockAddressReference() const;
601 
602  /// Return true if the subtarget allows calls to immediate address.
603  bool isLegalToCallImmediateAddr() const;
604 
605  /// This function returns the name of a function which has an interface
606  /// like the non-standard bzero function, if such a function exists on
607  /// the current subtarget and it is considered prefereable over
608  /// memset with zero passed as the second argument. Otherwise it
609  /// returns null.
610  const char *getBZeroEntry() const;
611 
612  /// This function returns true if the target has sincos() routine in its
613  /// compiler runtime or math libraries.
614  bool hasSinCos() const;
615 
616  /// Enable the MachineScheduler pass for all X86 subtargets.
617  bool enableMachineScheduler() const override { return true; }
618 
619  bool enableEarlyIfConversion() const override;
620 
621  /// Return the instruction itineraries based on the subtarget selection.
622  const InstrItineraryData *getInstrItineraryData() const override {
623  return &InstrItins;
624  }
625 
626  AntiDepBreakMode getAntiDepBreakMode() const override {
628  }
629 };
630 
631 } // End llvm namespace
632 
633 #endif
bool hasIFMA() const
Definition: X86Subtarget.h:448
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call...
Definition: X86Subtarget.h:362
bool HasPRFCHW
Processor has PRFCHW instructions.
Definition: X86Subtarget.h:161
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:183
bool hasF16C() const
Definition: X86Subtarget.h:442
bool HasFXSR
Target has FXSAVE/FXRESTOR instructions.
Definition: X86Subtarget.h:95
bool HasTBM
Target has TBM instructions.
Definition: X86Subtarget.h:119
bool hasDQI() const
Definition: X86Subtarget.h:479
bool HasBMI2
Processor has BMI2 instructions.
Definition: X86Subtarget.h:140
bool hasFastVectorFSQRT() const
Definition: X86Subtarget.h:467
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
Definition: GISelAccessor.h:29
bool hasSSE3() const
Definition: X86Subtarget.h:412
bool isOSKFreeBSD() const
Tests whether the OS is kFreeBSD.
Definition: Triple.h:555
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:139
bool isTargetWindowsCygwin() const
Definition: X86Subtarget.h:529
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:575
bool HasSGX
Processor has Software Guard Extensions.
Definition: X86Subtarget.h:278
const CallLowering * getCallLowering() const override
Methods used by Global ISel.
bool HasPCOMMIT
Processor has Persistent Commit feature.
Definition: X86Subtarget.h:284
bool hasX87() const
Definition: X86Subtarget.h:408
bool hasPFI() const
Definition: X86Subtarget.h:477
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
bool HasLAHFSAHF
Processor has LAHF/SAHF instructions.
Definition: X86Subtarget.h:167
bool hasXSAVES() const
Definition: X86Subtarget.h:431
bool isTargetCygMing() const
Definition: X86Subtarget.h:541
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:344
bool HasCDI
Processor has AVX-512 Conflict Detection Instructions.
Definition: X86Subtarget.h:251
bool slowIncDec() const
Definition: X86Subtarget.h:475
bool HasAES
Target has AES instructions.
Definition: X86Subtarget.h:92
bool isTargetMachO() const
Definition: X86Subtarget.h:506
const X86FrameLowering * getFrameLowering() const override
Definition: X86Subtarget.h:345
void setPICStyle(PICStyles::Style Style)
Definition: X86Subtarget.h:406
const TargetMachine & TM
Definition: X86Subtarget.h:67
bool isTargetPS4() const
Definition: X86Subtarget.h:502
bool HasERI
Processor has AVX-512 Exponential and Reciprocal Instructions.
Definition: X86Subtarget.h:248
bool enableMachineScheduler() const override
Enable the MachineScheduler pass for all X86 subtargets.
Definition: X86Subtarget.h:617
bool hasFMA4() const
Definition: X86Subtarget.h:436
bool hasFSGSBase() const
Definition: X86Subtarget.h:443
bool hasBMI() const
Definition: X86Subtarget.h:445
unsigned MaxInlineSizeThreshold
Max.
Definition: X86Subtarget.h:298
bool hasXSAVEOPT() const
Definition: X86Subtarget.h:429
bool LEAUsesAG
True if the LEA instruction inputs have to be ready at address generation (AG) time.
Definition: X86Subtarget.h:236
const LegalizerInfo * getLegalizerInfo() const override
bool hasFastPartialYMMWrite() const
Definition: X86Subtarget.h:465
bool hasVLX() const
Definition: X86Subtarget.h:481
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:521
bool HasFastScalarFSQRT
True if hardware SQRTSS instruction is at least as fast (latency) as RSQRTSS followed by a Newton-Rap...
Definition: X86Subtarget.h:209
bool hasSSE41() const
Definition: X86Subtarget.h:414
bool IsUAMem32Slow
True if unaligned memory accesses of 32-bytes are slow.
Definition: X86Subtarget.h:189
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:525
bool isOSIAMCU() const
Definition: Triple.h:485
bool isOSDragonFly() const
Definition: Triple.h:475
bool IsPMULLDSlow
True if the PMULLD instruction is slow compared to PMULLW/PMULHW and.
Definition: X86Subtarget.h:183
bool HasRDRAND
True if the processor has the RDRAND instruction.
Definition: X86Subtarget.h:125
bool hasRDSEED() const
Definition: X86Subtarget.h:454
bool hasBWI() const
Definition: X86Subtarget.h:480
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:463
bool hasPCLMUL() const
Definition: X86Subtarget.h:432
bool hasLAHFSAHF() const
Definition: X86Subtarget.h:455
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:593
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:540
bool HasCLWB
Processor supports Cache Line Write Back instruction.
Definition: X86Subtarget.h:287
bool hasHLE() const
Definition: X86Subtarget.h:450
bool isOSCygMing() const
Tests for either Cygwin or MinGW OS.
Definition: Triple.h:529
bool HasFMA
Target has 3-operand fused multiply-add.
Definition: X86Subtarget.h:110
bool HasFastVectorFSQRT
True if hardware SQRTPS/VSQRTPS instructions are at least as fast (throughput) as RSQRTPS/VRSQRTPS fo...
Definition: X86Subtarget.h:213
bool isTargetNaCl64() const
Definition: X86Subtarget.h:514
Holds all the information related to register banks.
void setGISelAccessor(GISelAccessor &GISel)
This object will take onwership of GISelAccessor.
Definition: X86Subtarget.h:339
bool isTargetAndroid() const
Definition: X86Subtarget.h:511
bool is16Bit() const
Definition: X86Subtarget.h:389
bool isTargetSolaris() const
Definition: X86Subtarget.h:501
const InstrItineraryData * getInstrItineraryData() const override
Return the instruction itineraries based on the subtarget selection.
Definition: X86Subtarget.h:622
bool hasVBMI() const
Definition: X86Subtarget.h:447
PICStyles::Style getPICStyle() const
Definition: X86Subtarget.h:405
bool isTargetDarwin() const
Definition: X86Subtarget.h:498
bool HasCLFLUSHOPT
Processor supports Flush Cache Line instruction.
Definition: X86Subtarget.h:281
bool HasPOPCNT
True if the processor supports POPCNT.
Definition: X86Subtarget.h:86
bool HasPKU
Processor has PKU extenstions.
Definition: X86Subtarget.h:263
bool isTargetGlibc() const
Definition: X86Subtarget.h:510
const InstructionSelector * getInstructionSelector() const override
bool hasAES() const
Definition: X86Subtarget.h:426
bool hasMPX() const
Definition: X86Subtarget.h:483
bool hasSHA() const
Definition: X86Subtarget.h:452
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:496
bool HasSlowDivide32
True if 8-bit divisions are significantly faster than 32-bit divisions and should be used when possib...
Definition: X86Subtarget.h:217
bool isTargetWindowsItanium() const
Definition: X86Subtarget.h:537
unsigned getStackAlignment() const
Returns the minimum alignment known to hold of the stack frame on entry to the function and which mus...
Definition: X86Subtarget.h:358
bool HasFastPartialYMMWrite
True if there is no performance penalty to writing only the lower parts of a YMM register without cle...
Definition: X86Subtarget.h:205
X86_ThisCall - Similar to X86_StdCall.
Definition: CallingConv.h:110
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:501
bool hasMMX() const
Definition: X86Subtarget.h:422
bool hasADX() const
Definition: X86Subtarget.h:451
bool HasPFI
Processor has AVX-512 PreFetch Instructions.
Definition: X86Subtarget.h:245
bool hasLZCNT() const
Definition: X86Subtarget.h:444
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:550
bool hasFastLZCNT() const
Definition: X86Subtarget.h:468
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:545
bool HasIFMA
Processor has Integer Fused Multiply Add.
Definition: X86Subtarget.h:146
bool hasTBM() const
Definition: X86Subtarget.h:439
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:381
bool HasCmpxchg16b
True if this processor has the CMPXCHG16B instruction; this is true for most x86-64 chips...
Definition: X86Subtarget.h:197
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:533
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:554
bool slowLEA() const
Definition: X86Subtarget.h:474
X86_FastCall - 'fast' analog of X86_StdCall.
Definition: CallingConv.h:91
bool HasX87
True if the processor supports X87 instructions.
Definition: X86Subtarget.h:76
bool isTargetMCU() const
Definition: X86Subtarget.h:515
Itinerary data supplied by a subtarget to be used by a target.
bool hasSSSE3() const
Definition: X86Subtarget.h:413
bool UseLeaForSP
True if the LEA instruction should be used for adjusting the stack pointer.
Definition: X86Subtarget.h:201
X863DNowEnum X863DNowLevel
MMX, 3DNow, 3DNow Athlon, or none supported.
Definition: X86Subtarget.h:73
bool HasSSE4A
True if the processor supports SSE4A instructions.
Definition: X86Subtarget.h:89
bool CallRegIndirect
True if the Calls with memory reference should be converted to a register-based indirect call...
Definition: X86Subtarget.h:232
bool HasLZCNT
Processor has LZCNT instruction.
Definition: X86Subtarget.h:134
bool HasF16C
Processor has 16-bit floating point conversion instructions.
Definition: X86Subtarget.h:128
bool SlowIncDec
True if INC and DEC instructions are slow when writing to flags.
Definition: X86Subtarget.h:242
bool hasSSE2() const
Definition: X86Subtarget.h:411
bool HasInvPCId
Processor supports Invalidate Process-Context Identifier.
Definition: X86Subtarget.h:269
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:341
X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, unsigned StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool useSoftFloat() const
Definition: X86Subtarget.h:489
bool hasSSEUnalignedMem() const
Definition: X86Subtarget.h:462
bool hasAnyFMA() const
Definition: X86Subtarget.h:437
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:562
bool hasBMI2() const
Definition: X86Subtarget.h:446
bool isWindowsGNUEnvironment() const
Definition: Triple.h:524
bool isTargetCOFF() const
Definition: X86Subtarget.h:505
bool HasMWAITX
Processor has MONITORX/MWAITX instructions.
Definition: X86Subtarget.h:170
bool HasPFPREFETCHWT1
Processor has Prefetch with intent to Write instruction.
Definition: X86Subtarget.h:173
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:556
bool IsBTMemSlow
True if BT (bit test) of memory instructions are slow.
Definition: X86Subtarget.h:176
X86_StdCall - stdcall is the calling conventions mostly used by the Win32 API.
Definition: CallingConv.h:86
bool useLeaForSP() const
Definition: X86Subtarget.h:464
bool HasADX
Processor has ADX instructions.
Definition: X86Subtarget.h:155
bool HasBWI
Processor has AVX-512 Byte and Word instructions.
Definition: X86Subtarget.h:257
bool isPositionIndependent() const
Definition: X86Subtarget.h:560
bool hasAVX2() const
Definition: X86Subtarget.h:417
bool isTargetWin32() const
Definition: X86Subtarget.h:549
bool hasSlowDivide64() const
Definition: X86Subtarget.h:470
std::unique_ptr< GISelAccessor > GISel
Gather the accessor points to GlobalISel-related APIs.
Definition: X86Subtarget.h:309
bool hasMOVBE() const
Definition: X86Subtarget.h:440
bool isPositionIndependent() const
PICStyles::Style PICStyle
Which PIC style to use.
Definition: X86Subtarget.h:65
bool hasFp256() const
Definition: X86Subtarget.h:419
bool HasXOP
Target has XOP instructions.
Definition: X86Subtarget.h:116
bool hasPKU() const
Definition: X86Subtarget.h:482
bool SlowLEA
True if the LEA instruction with certain arguments is slow.
Definition: X86Subtarget.h:239
bool HasDQI
Processor has AVX-512 Doubleword and Quadword instructions.
Definition: X86Subtarget.h:254
bool enableEarlyIfConversion() const override
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
bool has3DNowA() const
Definition: X86Subtarget.h:424
bool isSHLDSlow() const
Definition: X86Subtarget.h:458
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:570
bool isWindowsCoreCLREnvironment() const
Definition: Triple.h:512
bool isOSWindows() const
Definition: X86Subtarget.h:543
bool IsSHLDSlow
True if SHLD instructions are slow.
Definition: X86Subtarget.h:179
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
Definition: CallingConv.h:153
bool isPICStyleGOT() const
Definition: X86Subtarget.h:553
InstrItineraryData InstrItins
Instruction itineraries for scheduling.
Definition: X86Subtarget.h:304
bool hasMWAITX() const
Definition: X86Subtarget.h:456
bool HasFSGSBase
Processor has FS/GS base insturctions.
Definition: X86Subtarget.h:131
bool HasVMFUNC
Processor has VM Functions.
Definition: X86Subtarget.h:272
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
bool IsUAMem16Slow
True if unaligned memory accesses of 16-bytes are slow.
Definition: X86Subtarget.h:186
bool hasRDRAND() const
Definition: X86Subtarget.h:441
bool isOSSolaris() const
Definition: Triple.h:477
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
virtual bool isXRaySupported() const override
Definition: X86Subtarget.h:485
bool hasXOP() const
Definition: X86Subtarget.h:438
bool hasXSAVE() const
Definition: X86Subtarget.h:428
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:351
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:455
bool hasSSE4A() const
Definition: X86Subtarget.h:421
bool HasMPX
Processor supports MPX - Memory Protection Extensions.
Definition: X86Subtarget.h:266
X86ProcFamilyEnum X86ProcFamily
X86 processor family: Intel Atom, and others.
Definition: X86Subtarget.h:62
bool HasX86_64
True if the processor supports X86-64 instructions.
Definition: X86Subtarget.h:83
bool HasSSEUnalignedMem
True if SSE operations can have unaligned memory operands.
Definition: X86Subtarget.h:193
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:517
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
bool HasXSAVES
Target has XSAVES instructions.
Definition: X86Subtarget.h:104
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:394
bool isTargetELF() const
Definition: X86Subtarget.h:504
bool HasSHA
Processor has SHA instructions.
Definition: X86Subtarget.h:158
bool HasBMI
Processor has BMI1 instructions.
Definition: X86Subtarget.h:137
bool hasFXSR() const
Definition: X86Subtarget.h:427
bool isUnalignedMem32Slow() const
Definition: X86Subtarget.h:461
bool isTargetLinux() const
Definition: X86Subtarget.h:508
bool HasHLE
Processor has HLE.
Definition: X86Subtarget.h:152
bool HasVBMI
Processor has VBMI instructions.
Definition: X86Subtarget.h:143
bool hasCDI() const
Definition: X86Subtarget.h:476
bool has3DNow() const
Definition: X86Subtarget.h:423
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:143
bool UseSoftFloat
Use software floating point for code generation.
Definition: X86Subtarget.h:290
bool hasInt256() const
Definition: X86Subtarget.h:420
The C convention as implemented on Windows/x86-64.
Definition: CallingConv.h:149
bool hasCMov() const
Definition: X86Subtarget.h:409
bool isTargetDragonFly() const
Definition: X86Subtarget.h:500
bool hasPOPCNT() const
Definition: X86Subtarget.h:425
bool hasSSE1() const
Definition: X86Subtarget.h:410
bool HasPCLMUL
Target has carry-less multiplication.
Definition: X86Subtarget.h:107
bool hasPRFCHW() const
Definition: X86Subtarget.h:453
Provides the logic to select generic machine instructions.
bool isAtom() const
Definition: X86Subtarget.h:487
bool hasFastScalarFSQRT() const
Definition: X86Subtarget.h:466
bool is32Bit() const
Definition: X86Subtarget.h:385
bool isBTMemSlow() const
Definition: X86Subtarget.h:457
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
const X86SelectionDAGInfo * getSelectionDAGInfo() const override
Definition: X86Subtarget.h:348
bool HasXSAVEOPT
Target has XSAVEOPT instructions.
Definition: X86Subtarget.h:100
bool isOSGlibc() const
Tests whether the OS uses glibc.
Definition: Triple.h:560
bool hasSSE42() const
Definition: X86Subtarget.h:415
bool isWindowsCygwinEnvironment() const
Definition: Triple.h:520
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:400
X86SSEEnum X86SSELevel
SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
Definition: X86Subtarget.h:70
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
bool hasAVX512() const
Definition: X86Subtarget.h:418
bool LEAusesAG() const
Definition: X86Subtarget.h:473
bool isPS4CPU() const
Tests whether the target is the PS4 CPU.
Definition: Triple.h:580
bool HasXSAVE
Target has XSAVE instructions.
Definition: X86Subtarget.h:98
bool isUnalignedMem16Slow() const
Definition: X86Subtarget.h:460
bool isOSFreeBSD() const
Definition: Triple.h:467
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:288
bool hasRTM() const
Definition: X86Subtarget.h:449
bool HasCMov
True if this processor has conditional move instructions (generally pentium pro+).
Definition: X86Subtarget.h:80
bool isTargetWin64() const
Definition: X86Subtarget.h:545
bool isSLM() const
Definition: X86Subtarget.h:488
bool isKnownWindowsMSVCEnvironment() const
Checks if the environment is MSVC.
Definition: Triple.h:508
bool HasFMA4
Target has 4-operand fused multiply-add.
Definition: X86Subtarget.h:113
bool HasRTM
Processor has RTM instructions.
Definition: X86Subtarget.h:149
bool isWindowsItaniumEnvironment() const
Definition: Triple.h:516
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:499
const RegisterBankInfo * getRegBankInfo() const override
bool HasXSAVEC
Target has XSAVEC instructions.
Definition: X86Subtarget.h:102
Primary interface to the complete machine description for the target machine.
bool HasVLX
Processor has AVX-512 Vector Length eXtenstions.
Definition: X86Subtarget.h:260
bool HasFastLZCNT
True if LZCNT instruction is fast.
Definition: X86Subtarget.h:224
const char * getBZeroEntry() const
This function returns the name of a function which has an interface like the non-standard bzero funct...
bool padShortFunctions() const
Definition: X86Subtarget.h:471
bool hasERI() const
Definition: X86Subtarget.h:478
bool callRegIndirect() const
Definition: X86Subtarget.h:472
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool HasRDSEED
Processor has RDSEED instructions.
Definition: X86Subtarget.h:164
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: X86Subtarget.h:626
unsigned stackAlignment
The minimum alignment known to hold of the stack frame on entry to the function and which must be mai...
Definition: X86Subtarget.h:294
bool hasMFence() const
Use mfence if we have SSE2 or we're on x86-64 (even if we asked for no-sse2).
Definition: X86Subtarget.h:494
bool isTargetKFreeBSD() const
Definition: X86Subtarget.h:509
bool hasFMA() const
Definition: X86Subtarget.h:435
bool isTargetNaCl32() const
Definition: X86Subtarget.h:513
bool isPMULLDSlow() const
Definition: X86Subtarget.h:459
Triple TargetTriple
What processor and OS we're targeting.
Definition: X86Subtarget.h:301
bool isLegalToCallImmediateAddr() const
Return true if the subtarget allows calls to immediate address.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool HasMOVBE
True if the processor has the MOVBE instruction.
Definition: X86Subtarget.h:122
bool HasSMAP
Processor has Supervisor Mode Access Protection.
Definition: X86Subtarget.h:275
bool PadShortFunctions
True if the short functions should be padded to prevent a stall when returning too early...
Definition: X86Subtarget.h:228
bool hasAVX() const
Definition: X86Subtarget.h:416
bool hasXSAVEC() const
Definition: X86Subtarget.h:430
bool hasSlowDivide32() const
Definition: X86Subtarget.h:469
bool isTargetNaCl() const
Definition: X86Subtarget.h:512
bool HasSlowDivide64
True if 32-bit divides are significantly faster than 64-bit divisions and should be used when possibl...
Definition: X86Subtarget.h:221