30 #define DEBUG_TYPE "asm-printer"
33 #define PRINT_ALIAS_INSTR
34 #include "X86GenAsmWriter.inc"
43 uint64_t TSFlags = Desc.
TSFlags;
47 HasCustomInstComment =
59 if (MI->
getOpcode() == X86::CALLpcrel32 &&
77 case 0: O <<
"eq";
break;
78 case 1: O <<
"lt";
break;
79 case 2: O <<
"le";
break;
80 case 3: O <<
"unord";
break;
81 case 4: O <<
"neq";
break;
82 case 5: O <<
"nlt";
break;
83 case 6: O <<
"nle";
break;
84 case 7: O <<
"ord";
break;
85 case 8: O <<
"eq_uq";
break;
86 case 9: O <<
"nge";
break;
87 case 0xa: O <<
"ngt";
break;
88 case 0xb: O <<
"false";
break;
89 case 0xc: O <<
"neq_oq";
break;
90 case 0xd: O <<
"ge";
break;
91 case 0xe: O <<
"gt";
break;
92 case 0xf: O <<
"true";
break;
93 case 0x10: O <<
"eq_os";
break;
94 case 0x11: O <<
"lt_oq";
break;
95 case 0x12: O <<
"le_oq";
break;
96 case 0x13: O <<
"unord_s";
break;
97 case 0x14: O <<
"neq_us";
break;
98 case 0x15: O <<
"nlt_uq";
break;
99 case 0x16: O <<
"nle_uq";
break;
100 case 0x17: O <<
"ord_s";
break;
101 case 0x18: O <<
"eq_us";
break;
102 case 0x19: O <<
"nge_uq";
break;
103 case 0x1a: O <<
"ngt_uq";
break;
104 case 0x1b: O <<
"false_os";
break;
105 case 0x1c: O <<
"neq_os";
break;
106 case 0x1d: O <<
"ge_oq";
break;
107 case 0x1e: O <<
"gt_oq";
break;
108 case 0x1f: O <<
"true_us";
break;
117 case 0: O <<
"lt";
break;
118 case 1: O <<
"le";
break;
119 case 2: O <<
"gt";
break;
120 case 3: O <<
"ge";
break;
121 case 4: O <<
"eq";
break;
122 case 5: O <<
"neq";
break;
123 case 6: O <<
"false";
break;
124 case 7: O <<
"true";
break;
132 case 0: O <<
"{rn-sae}";
break;
133 case 1: O <<
"{rd-sae}";
break;
134 case 2: O <<
"{ru-sae}";
break;
135 case 3: O <<
"{rz-sae}";
break;
148 assert(Op.
isExpr() &&
"unknown pcrel immediate operand");
153 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
167 }
else if (Op.
isImm()) {
169 int64_t Imm = Op.
getImm();
178 if (
CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
180 if (Imm == (int16_t)(Imm))
182 else if (Imm == (int32_t)(Imm))
188 assert(Op.
isExpr() &&
"unknown operand kind in printOperand");
189 O <<
markup(
"<imm:") <<
'$';
210 if (DispSpec.
isImm()) {
211 int64_t DispVal = DispSpec.
getImm();
212 if (DispVal || (!IndexReg.
getReg() && !BaseReg.
getReg()))
215 assert(DispSpec.
isExpr() &&
"non-immediate displacement for LEA?");
229 O <<
',' <<
markup(
"<imm:") << ScaleVal
282 if (DispSpec.
isImm()) {
285 assert(DispSpec.
isExpr() &&
"non-immediate displacement?");
void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
static const char * getRegisterName(unsigned RegNo)
format_object< int64_t > formatHex(int64_t Value) const
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
AddrSegmentReg - The operand # of the segment in the memory operand.
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
void printInstruction(const MCInst *MI, raw_ostream &OS)
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
const MCExpr * getExpr() const
void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS)
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS)
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
unsigned getOpcode() const
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
printPCRelImm - This is used to print an immediate value that ends up being encoded as a pc-relative ...
MCSubtargetInfo - Generic base class for all target subtargets.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
This class implements an extremely fast bulk output stream that can only output to a stream...
bool printAliasInstr(const MCInst *MI, raw_ostream &OS)
StringRef - Represent a constant reference to a string, i.e.
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const
void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS)
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const char *(*getRegName)(unsigned))
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...