LLVM  4.0.0
AVRFrameLowering.cpp
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1 //===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AVR implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AVRFrameLowering.h"
15 
16 #include "AVR.h"
17 #include "AVRInstrInfo.h"
18 #include "AVRMachineFunctionInfo.h"
19 #include "AVRTargetMachine.h"
21 
27 #include "llvm/IR/Function.h"
28 
29 #include <vector>
30 
31 namespace llvm {
32 
34  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 1, -2) {}
35 
37  const MachineFunction &MF) const {
38  // Always simplify call frame pseudo instructions, even when
39  // hasReservedCallFrame is false.
40  return true;
41 }
42 
44  // Reserve call frame memory in function prologue under the following
45  // conditions:
46  // - Y pointer is reserved to be the frame pointer.
47  // - The function does not contain variable sized objects.
48 
49  const MachineFrameInfo &MFI = MF.getFrameInfo();
50  return hasFP(MF) && !MFI.hasVarSizedObjects();
51 }
52 
54  MachineBasicBlock &MBB) const {
56  CallingConv::ID CallConv = MF.getFunction()->getCallingConv();
57  DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
58  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
59  const AVRInstrInfo &TII = *STI.getInstrInfo();
60 
61  // Interrupt handlers re-enable interrupts in function entry.
62  if (CallConv == CallingConv::AVR_INTR) {
63  BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
64  .addImm(0x07)
66  }
67 
68  // Emit special prologue code to save R1, R0 and SREG in interrupt/signal
69  // handlers before saving any other registers.
70  if (CallConv == CallingConv::AVR_INTR ||
71  CallConv == CallingConv::AVR_SIGNAL) {
72  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
73  .addReg(AVR::R1R0, RegState::Kill)
75  BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
76  .addImm(0x3f)
78  BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
79  .addReg(AVR::R0, RegState::Kill)
81  BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
82  .addReg(AVR::R0, RegState::Define)
83  .addReg(AVR::R0, RegState::Kill)
84  .addReg(AVR::R0, RegState::Kill)
86  }
87 
88  // Early exit if the frame pointer is not needed in this function.
89  if (!hasFP(MF)) {
90  return;
91  }
92 
93  const MachineFrameInfo &MFI = MF.getFrameInfo();
95  unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
96 
97  // Skip the callee-saved push instructions.
98  while (
99  (MBBI != MBB.end()) && MBBI->getFlag(MachineInstr::FrameSetup) &&
100  (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
101  ++MBBI;
102  }
103 
104  // Update Y with the new base value.
105  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
106  .addReg(AVR::SP)
108 
109  // Mark the FramePtr as live-in in every block except the entry.
110  for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
111  I != E; ++I) {
112  I->addLiveIn(AVR::R29R28);
113  }
114 
115  if (!FrameSize) {
116  return;
117  }
118 
119  // Reserve the necessary frame memory by doing FP -= <size>.
120  unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK;
121 
122  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
123  .addReg(AVR::R29R28, RegState::Kill)
124  .addImm(FrameSize)
126  // The SREG implicit def is dead.
127  MI->getOperand(3).setIsDead();
128 
129  // Write back R29R28 to SP and temporarily disable interrupts.
130  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
131  .addReg(AVR::R29R28)
133 }
134 
136  MachineBasicBlock &MBB) const {
137  CallingConv::ID CallConv = MF.getFunction()->getCallingConv();
138  bool isHandler = (CallConv == CallingConv::AVR_INTR ||
139  CallConv == CallingConv::AVR_SIGNAL);
140 
141  // Early exit if the frame pointer is not needed in this function except for
142  // signal/interrupt handlers where special code generation is required.
143  if (!hasFP(MF) && !isHandler) {
144  return;
145  }
146 
148  assert(MBBI->getDesc().isReturn() &&
149  "Can only insert epilog into returning blocks");
150 
151  DebugLoc DL = MBBI->getDebugLoc();
152  const MachineFrameInfo &MFI = MF.getFrameInfo();
154  unsigned FrameSize = MFI.getStackSize() - AFI->getCalleeSavedFrameSize();
155  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
156  const AVRInstrInfo &TII = *STI.getInstrInfo();
157 
158  // Emit special epilogue code to restore R1, R0 and SREG in interrupt/signal
159  // handlers at the very end of the function, just before reti.
160  if (isHandler) {
161  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
162  BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
163  .addImm(0x3f)
164  .addReg(AVR::R0, RegState::Kill);
165  BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0);
166  }
167 
168  // Early exit if there is no need to restore the frame pointer.
169  if (!FrameSize) {
170  return;
171  }
172 
173  // Skip the callee-saved pop instructions.
174  while (MBBI != MBB.begin()) {
175  MachineBasicBlock::iterator PI = std::prev(MBBI);
176  int Opc = PI->getOpcode();
177 
178  if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
179  break;
180  }
181 
182  --MBBI;
183  }
184 
185  unsigned Opcode;
186 
187  // Select the optimal opcode depending on how big it is.
188  if (isUInt<6>(FrameSize)) {
189  Opcode = AVR::ADIWRdK;
190  } else {
191  Opcode = AVR::SUBIWRdK;
192  FrameSize = -FrameSize;
193  }
194 
195  // Restore the frame pointer by doing FP += <size>.
196  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
197  .addReg(AVR::R29R28, RegState::Kill)
198  .addImm(FrameSize);
199  // The SREG implicit def is dead.
200  MI->getOperand(3).setIsDead();
201 
202  // Write back R29R28 to SP and temporarily disable interrupts.
203  BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
204  .addReg(AVR::R29R28, RegState::Kill);
205 }
206 
207 // Return true if the specified function should have a dedicated frame
208 // pointer register. This is true if the function meets any of the following
209 // conditions:
210 // - a register has been spilled
211 // - has allocas
212 // - input arguments are passed using the stack
213 //
214 // Notice that strictly this is not a frame pointer because it contains SP after
215 // frame allocation instead of having the original SP in function entry.
217  const AVRMachineFunctionInfo *FuncInfo = MF.getInfo<AVRMachineFunctionInfo>();
218 
219  return (FuncInfo->getHasSpills() || FuncInfo->getHasAllocas() ||
220  FuncInfo->getHasStackArgs());
221 }
222 
225  const std::vector<CalleeSavedInfo> &CSI,
226  const TargetRegisterInfo *TRI) const {
227  if (CSI.empty()) {
228  return false;
229  }
230 
231  unsigned CalleeFrameSize = 0;
232  DebugLoc DL = MBB.findDebugLoc(MI);
233  MachineFunction &MF = *MBB.getParent();
234  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
235  const TargetInstrInfo &TII = *STI.getInstrInfo();
237 
238  for (unsigned i = CSI.size(); i != 0; --i) {
239  unsigned Reg = CSI[i - 1].getReg();
240  bool IsNotLiveIn = !MBB.isLiveIn(Reg);
241 
242  assert(TRI->getMinimalPhysRegClass(Reg)->getSize() == 1 &&
243  "Invalid register size");
244 
245  // Add the callee-saved register as live-in only if it is not already a
246  // live-in register, this usually happens with arguments that are passed
247  // through callee-saved registers.
248  if (IsNotLiveIn) {
249  MBB.addLiveIn(Reg);
250  }
251 
252  // Do not kill the register when it is an input argument.
253  BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr))
254  .addReg(Reg, getKillRegState(IsNotLiveIn))
255  .setMIFlag(MachineInstr::FrameSetup);
256  ++CalleeFrameSize;
257  }
258 
259  AVRFI->setCalleeSavedFrameSize(CalleeFrameSize);
260 
261  return true;
262 }
263 
266  const std::vector<CalleeSavedInfo> &CSI,
267  const TargetRegisterInfo *TRI) const {
268  if (CSI.empty()) {
269  return false;
270  }
271 
272  DebugLoc DL = MBB.findDebugLoc(MI);
273  const MachineFunction &MF = *MBB.getParent();
274  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
275  const TargetInstrInfo &TII = *STI.getInstrInfo();
276 
277  for (const CalleeSavedInfo &CCSI : CSI) {
278  unsigned Reg = CCSI.getReg();
279 
280  assert(TRI->getMinimalPhysRegClass(Reg)->getSize() == 1 &&
281  "Invalid register size");
282 
283  BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
284  }
285 
286  return true;
287 }
288 
289 /// Replace pseudo store instructions that pass arguments through the stack with
290 /// real instructions. If insertPushes is true then all instructions are
291 /// replaced with push instructions, otherwise regular std instructions are
292 /// inserted.
295  const TargetInstrInfo &TII, bool insertPushes) {
296  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
297  const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
298 
299  // Iterate through the BB until we hit a call instruction or we reach the end.
300  for (auto I = MI, E = MBB.end(); I != E && !I->isCall();) {
301  MachineBasicBlock::iterator NextMI = std::next(I);
302  MachineInstr &MI = *I;
303  unsigned Opcode = I->getOpcode();
304 
305  // Only care of pseudo store instructions where SP is the base pointer.
306  if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) {
307  I = NextMI;
308  continue;
309  }
310 
311  assert(MI.getOperand(0).getReg() == AVR::SP &&
312  "Invalid register, should be SP!");
313  if (insertPushes) {
314  // Replace this instruction with a push.
315  unsigned SrcReg = MI.getOperand(2).getReg();
316  bool SrcIsKill = MI.getOperand(2).isKill();
317 
318  // We can't use PUSHWRr here because when expanded the order of the new
319  // instructions are reversed from what we need. Perform the expansion now.
320  if (Opcode == AVR::STDWSPQRr) {
321  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
322  .addReg(TRI.getSubReg(SrcReg, AVR::sub_hi),
323  getKillRegState(SrcIsKill));
324  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
325  .addReg(TRI.getSubReg(SrcReg, AVR::sub_lo),
326  getKillRegState(SrcIsKill));
327  } else {
328  BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
329  .addReg(SrcReg, getKillRegState(SrcIsKill));
330  }
331 
332  MI.eraseFromParent();
333  I = NextMI;
334  continue;
335  }
336 
337  // Replace this instruction with a regular store. Use Y as the base
338  // pointer since it is guaranteed to contain a copy of SP.
339  unsigned STOpc =
340  (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr;
341 
342  MI.setDesc(TII.get(STOpc));
343  MI.getOperand(0).setReg(AVR::R29R28);
344 
345  I = NextMI;
346  }
347 }
348 
352  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
353  const TargetFrameLowering &TFI = *STI.getFrameLowering();
354  const AVRInstrInfo &TII = *STI.getInstrInfo();
355 
356  // There is nothing to insert when the call frame memory is allocated during
357  // function entry. Delete the call frame pseudo and replace all pseudo stores
358  // with real store instructions.
359  if (TFI.hasReservedCallFrame(MF)) {
360  fixStackStores(MBB, MI, TII, false);
361  return MBB.erase(MI);
362  }
363 
364  DebugLoc DL = MI->getDebugLoc();
365  unsigned int Opcode = MI->getOpcode();
366  int Amount = MI->getOperand(0).getImm();
367 
368  // Adjcallstackup does not need to allocate stack space for the call, instead
369  // we insert push instructions that will allocate the necessary stack.
370  // For adjcallstackdown we convert it into an 'adiw reg, <amt>' handling
371  // the read and write of SP in I/O space.
372  if (Amount != 0) {
373  assert(TFI.getStackAlignment() == 1 && "Unsupported stack alignment");
374 
375  if (Opcode == TII.getCallFrameSetupOpcode()) {
376  fixStackStores(MBB, MI, TII, true);
377  } else {
378  assert(Opcode == TII.getCallFrameDestroyOpcode());
379 
380  // Select the best opcode to adjust SP based on the offset size.
381  unsigned addOpcode;
382  if (isUInt<6>(Amount)) {
383  addOpcode = AVR::ADIWRdK;
384  } else {
385  addOpcode = AVR::SUBIWRdK;
386  Amount = -Amount;
387  }
388 
389  // Build the instruction sequence.
390  BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
391 
392  MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(addOpcode), AVR::R31R30)
393  .addReg(AVR::R31R30, RegState::Kill)
394  .addImm(Amount);
395  New->getOperand(3).setIsDead();
396 
397  BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
398  .addReg(AVR::R31R30, RegState::Kill);
399  }
400  }
401 
402  return MBB.erase(MI);
403 }
404 
406  BitVector &SavedRegs,
407  RegScavenger *RS) const {
409 
410  // Spill register Y when it is used as the frame pointer.
411  if (hasFP(MF)) {
412  SavedRegs.set(AVR::R29R28);
413  SavedRegs.set(AVR::R29);
414  SavedRegs.set(AVR::R28);
415  }
416 }
417 /// The frame analyzer pass.
418 ///
419 /// Scans the function for allocas and used arguments
420 /// that are passed through the stack.
422  static char ID;
424 
426  const MachineFrameInfo &MFI = MF.getFrameInfo();
428 
429  // If there are no fixed frame indexes during this stage it means there
430  // are allocas present in the function.
431  if (MFI.getNumObjects() != MFI.getNumFixedObjects()) {
432  // Check for the type of allocas present in the function. We only care
433  // about fixed size allocas so do not give false positives if only
434  // variable sized allocas are present.
435  for (unsigned i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
436  // Variable sized objects have size 0.
437  if (MFI.getObjectSize(i)) {
438  FuncInfo->setHasAllocas(true);
439  break;
440  }
441  }
442  }
443 
444  // If there are fixed frame indexes present, scan the function to see if
445  // they are really being used.
446  if (MFI.getNumFixedObjects() == 0) {
447  return false;
448  }
449 
450  // Ok fixed frame indexes present, now scan the function to see if they
451  // are really being used, otherwise we can ignore them.
452  for (const MachineBasicBlock &BB : MF) {
453  for (const MachineInstr &MI : BB) {
454  int Opcode = MI.getOpcode();
455 
456  if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) &&
457  (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr)) {
458  continue;
459  }
460 
461  for (const MachineOperand &MO : MI.operands()) {
462  if (!MO.isFI()) {
463  continue;
464  }
465 
466  if (MFI.isFixedObjectIndex(MO.getIndex())) {
467  FuncInfo->setHasStackArgs(true);
468  return false;
469  }
470  }
471  }
472  }
473 
474  return false;
475  }
476 
477  StringRef getPassName() const { return "AVR Frame Analyzer"; }
478 };
479 
480 char AVRFrameAnalyzer::ID = 0;
481 
482 /// Creates instance of the frame analyzer pass.
484 
485 /// Create the Dynalloca Stack Pointer Save/Restore pass.
486 /// Insert a copy of SP before allocating the dynamic stack memory and restore
487 /// it in function exit to restore the original SP state. This avoids the need
488 /// of reserving a register pair for a frame pointer.
490  static char ID;
492 
494  // Early exit when there are no variable sized objects in the function.
495  if (!MF.getFrameInfo().hasVarSizedObjects()) {
496  return false;
497  }
498 
499  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
500  const TargetInstrInfo &TII = *STI.getInstrInfo();
501  MachineBasicBlock &EntryMBB = MF.front();
502  MachineBasicBlock::iterator MBBI = EntryMBB.begin();
503  DebugLoc DL = EntryMBB.findDebugLoc(MBBI);
504 
505  unsigned SPCopy =
506  MF.getRegInfo().createVirtualRegister(&AVR::DREGSRegClass);
507 
508  // Create a copy of SP in function entry before any dynallocas are
509  // inserted.
510  BuildMI(EntryMBB, MBBI, DL, TII.get(AVR::COPY), SPCopy).addReg(AVR::SP);
511 
512  // Restore SP in all exit basic blocks.
513  for (MachineBasicBlock &MBB : MF) {
514  // If last instruction is a return instruction, add a restore copy.
515  if (!MBB.empty() && MBB.back().isReturn()) {
516  MBBI = MBB.getLastNonDebugInstr();
517  DL = MBBI->getDebugLoc();
518  BuildMI(MBB, MBBI, DL, TII.get(AVR::COPY), AVR::SP)
519  .addReg(SPCopy, RegState::Kill);
520  }
521  }
522 
523  return true;
524  }
525 
527  return "AVR dynalloca stack pointer save/restore";
528  }
529 };
530 
531 char AVRDynAllocaSR::ID = 0;
532 
533 /// createAVRDynAllocaSRPass - returns an instance of the dynalloca stack
534 /// pointer save/restore pass.
536 
537 } // end of namespace llvm
538 
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:43
bool runOnMachineFunction(MachineFunction &MF)
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:219
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
size_t i
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
unsigned getNumObjects() const
Return the number of objects.
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
const HexagonInstrInfo * TII
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - When possible, it's best to simplify the call frame pseudo ops before d...
const MachineBasicBlock & front() const
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:65
bool isKill() const
MachineBasicBlock * MBB
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
unsigned getNumFixedObjects() const
Return the number of fixed objects.
unsigned getKillRegState(bool B)
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
TargetInstrInfo - Interface to description of machine instruction set.
The frame analyzer pass.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Contains AVR-specific information for each MachineFunction.
StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
Used for AVR interrupt routines.
Definition: CallingConv.h:172
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
Information about stack frame layout on the target.
void setCalleeSavedFrameSize(unsigned Bytes)
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
A specific AVR target MCU.
Definition: AVRSubtarget.h:33
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void fixStackStores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const TargetInstrInfo &TII, bool insertPushes)
Replace pseudo store instructions that pass arguments through the stack with real instructions...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
FunctionPass * createAVRFrameAnalyzerPass()
Creates instance of the frame analyzer pass.
const TargetFrameLowering * getFrameLowering() const override
Definition: AVRSubtarget.h:44
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:47
Calling convention used for AVR signal routines.
Definition: CallingConv.h:175
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
int getObjectIndexEnd() const
Return one past the maximum frame object index.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
FunctionPass * createAVRDynAllocaSRPass()
createAVRDynAllocaSRPass - returns an instance of the dynalloca stack pointer save/restore pass...
bool runOnMachineFunction(MachineFunction &MF)
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Create the Dynalloca Stack Pointer Save/Restore pass.