LLVM  4.0.0
LiveRangeEdit.cpp
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1 //===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
29 STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
30 STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
31 
32 void LiveRangeEdit::Delegate::anchor() { }
33 
35  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
36  if (VRM) {
37  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
38  }
39  LiveInterval &LI = LIS.createEmptyInterval(VReg);
40  // Create empty subranges if the OldReg's interval has them. Do not create
41  // the main range here---it will be constructed later after the subranges
42  // have been finalized.
43  LiveInterval &OldLI = LIS.getInterval(OldReg);
45  for (LiveInterval::SubRange &S : OldLI.subranges())
46  LI.createSubRange(Alloc, S.LaneMask);
47  return LI;
48 }
49 
50 unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
51  unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
52  if (VRM) {
53  VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
54  }
55  return VReg;
56 }
57 
59  const MachineInstr *DefMI,
60  AliasAnalysis *aa) {
61  assert(DefMI && "Missing instruction");
62  ScannedRemattable = true;
63  if (!TII.isTriviallyReMaterializable(*DefMI, aa))
64  return false;
65  Remattable.insert(VNI);
66  return true;
67 }
68 
69 void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
70  for (VNInfo *VNI : getParent().valnos) {
71  if (VNI->isUnused())
72  continue;
73  unsigned Original = VRM->getOriginal(getReg());
74  LiveInterval &OrigLI = LIS.getInterval(Original);
75  VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
76  if (!OrigVNI)
77  continue;
78  MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
79  if (!DefMI)
80  continue;
81  checkRematerializable(OrigVNI, DefMI, aa);
82  }
83  ScannedRemattable = true;
84 }
85 
87  if (!ScannedRemattable)
88  scanRemattable(aa);
89  return !Remattable.empty();
90 }
91 
92 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
93 /// OrigIdx are also available with the same value at UseIdx.
94 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
95  SlotIndex OrigIdx,
96  SlotIndex UseIdx) const {
97  OrigIdx = OrigIdx.getRegSlot(true);
98  UseIdx = UseIdx.getRegSlot(true);
99  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
100  const MachineOperand &MO = OrigMI->getOperand(i);
101  if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
102  continue;
103 
104  // We can't remat physreg uses, unless it is a constant.
106  if (MRI.isConstantPhysReg(MO.getReg()))
107  continue;
108  return false;
109  }
110 
111  LiveInterval &li = LIS.getInterval(MO.getReg());
112  const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
113  if (!OVNI)
114  continue;
115 
116  // Don't allow rematerialization immediately after the original def.
117  // It would be incorrect if OrigMI redefines the register.
118  // See PR14098.
119  if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
120  return false;
121 
122  if (OVNI != li.getVNInfoAt(UseIdx))
123  return false;
124  }
125  return true;
126 }
127 
129  SlotIndex UseIdx, bool cheapAsAMove) {
130  assert(ScannedRemattable && "Call anyRematerializable first");
131 
132  // Use scanRemattable info.
133  if (!Remattable.count(OrigVNI))
134  return false;
135 
136  // No defining instruction provided.
137  SlotIndex DefIdx;
138  assert(RM.OrigMI && "No defining instruction for remattable value");
139  DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
140 
141  // If only cheap remats were requested, bail out early.
142  if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
143  return false;
144 
145  // Verify that all used registers are available with the same values.
146  if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
147  return false;
148 
149  return true;
150 }
151 
154  unsigned DestReg,
155  const Remat &RM,
156  const TargetRegisterInfo &tri,
157  bool Late) {
158  assert(RM.OrigMI && "Invalid remat");
159  TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri);
160  // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
161  // to false anyway in case the isDead flag of RM.OrigMI's dest register
162  // is true.
163  (*--MI).getOperand(0).setIsDead(false);
164  Rematted.insert(RM.ParentVNI);
165  return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
166 }
167 
169  if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
170  LIS.removeInterval(Reg);
171 }
172 
173 bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
175  MachineInstr *DefMI = nullptr, *UseMI = nullptr;
176 
177  // Check that there is a single def and a single use.
178  for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
179  MachineInstr *MI = MO.getParent();
180  if (MO.isDef()) {
181  if (DefMI && DefMI != MI)
182  return false;
183  if (!MI->canFoldAsLoad())
184  return false;
185  DefMI = MI;
186  } else if (!MO.isUndef()) {
187  if (UseMI && UseMI != MI)
188  return false;
189  // FIXME: Targets don't know how to fold subreg uses.
190  if (MO.getSubReg())
191  return false;
192  UseMI = MI;
193  }
194  }
195  if (!DefMI || !UseMI)
196  return false;
197 
198  // Since we're moving the DefMI load, make sure we're not extending any live
199  // ranges.
200  if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI),
201  LIS.getInstructionIndex(*UseMI)))
202  return false;
203 
204  // We also need to make sure it is safe to move the load.
205  // Assume there are stores between DefMI and UseMI.
206  bool SawStore = true;
207  if (!DefMI->isSafeToMove(nullptr, SawStore))
208  return false;
209 
210  DEBUG(dbgs() << "Try to fold single def: " << *DefMI
211  << " into single use: " << *UseMI);
212 
214  if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
215  return false;
216 
217  MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
218  if (!FoldMI)
219  return false;
220  DEBUG(dbgs() << " folded: " << *FoldMI);
221  LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
223  DefMI->addRegisterDead(LI->reg, nullptr);
224  Dead.push_back(DefMI);
225  ++NumDCEFoldedLoads;
226  return true;
227 }
228 
229 bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
230  const MachineOperand &MO) const {
231  const MachineInstr &MI = *MO.getParent();
232  SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
233  if (LI.Query(Idx).isKill())
234  return true;
235  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
236  unsigned SubReg = MO.getSubReg();
237  LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
238  for (const LiveInterval::SubRange &S : LI.subranges()) {
239  if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
240  return true;
241  }
242  return false;
243 }
244 
245 /// Find all live intervals that need to shrink, then remove the instruction.
246 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
247  AliasAnalysis *AA) {
248  assert(MI->allDefsAreDead() && "Def isn't really dead");
249  SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
250 
251  // Never delete a bundled instruction.
252  if (MI->isBundled()) {
253  return;
254  }
255  // Never delete inline asm.
256  if (MI->isInlineAsm()) {
257  DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
258  return;
259  }
260 
261  // Use the same criteria as DeadMachineInstructionElim.
262  bool SawStore = false;
263  if (!MI->isSafeToMove(nullptr, SawStore)) {
264  DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
265  return;
266  }
267 
268  DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
269 
270  // Collect virtual registers to be erased after MI is gone.
271  SmallVector<unsigned, 8> RegsToErase;
272  bool ReadsPhysRegs = false;
273  bool isOrigDef = false;
274  unsigned Dest;
275  // Only optimize rematerialize case when the instruction has one def, since
276  // otherwise we could leave some dead defs in the code. This case is
277  // extremely rare.
278  if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
279  MI->getDesc().getNumDefs() == 1) {
280  Dest = MI->getOperand(0).getReg();
281  unsigned Original = VRM->getOriginal(Dest);
282  LiveInterval &OrigLI = LIS.getInterval(Original);
283  VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
284  // The original live-range may have been shrunk to
285  // an empty live-range. It happens when it is dead, but
286  // we still keep it around to be able to rematerialize
287  // other values that depend on it.
288  if (OrigVNI)
289  isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
290  }
291 
292  // Check for live intervals that may shrink
294  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
295  if (!MOI->isReg())
296  continue;
297  unsigned Reg = MOI->getReg();
299  // Check if MI reads any unreserved physregs.
300  if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
301  ReadsPhysRegs = true;
302  else if (MOI->isDef())
303  LIS.removePhysRegDefAt(Reg, Idx);
304  continue;
305  }
306  LiveInterval &LI = LIS.getInterval(Reg);
307 
308  // Shrink read registers, unless it is likely to be expensive and
309  // unlikely to change anything. We typically don't want to shrink the
310  // PIC base register that has lots of uses everywhere.
311  // Always shrink COPY uses that probably come from live range splitting.
312  if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
313  (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
314  ToShrink.insert(&LI);
315 
316  // Remove defined value.
317  if (MOI->isDef()) {
318  if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
319  TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
320  LIS.removeVRegDefAt(LI, Idx);
321  if (LI.empty())
322  RegsToErase.push_back(Reg);
323  }
324  }
325 
326  // Currently, we don't support DCE of physreg live ranges. If MI reads
327  // any unreserved physregs, don't erase the instruction, but turn it into
328  // a KILL instead. This way, the physreg live ranges don't end up
329  // dangling.
330  // FIXME: It would be better to have something like shrinkToUses() for
331  // physregs. That could potentially enable more DCE and it would free up
332  // the physreg. It would not happen often, though.
333  if (ReadsPhysRegs) {
334  MI->setDesc(TII.get(TargetOpcode::KILL));
335  // Remove all operands that aren't physregs.
336  for (unsigned i = MI->getNumOperands(); i; --i) {
337  const MachineOperand &MO = MI->getOperand(i-1);
339  continue;
340  MI->RemoveOperand(i-1);
341  }
342  DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
343  } else {
344  // If the dest of MI is an original reg and MI is reMaterializable,
345  // don't delete the inst. Replace the dest with a new reg, and keep
346  // the inst for remat of other siblings. The inst is saved in
347  // LiveRangeEdit::DeadRemats and will be deleted after all the
348  // allocations of the func are done.
349  if (isOrigDef && DeadRemats && TII.isTriviallyReMaterializable(*MI, AA)) {
350  LiveInterval &NewLI = createEmptyIntervalFrom(Dest);
351  NewLI.removeEmptySubRanges();
352  VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
353  NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
354  pop_back();
355  markDeadRemat(MI);
356  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
357  MI->substituteRegister(Dest, NewLI.reg, 0, TRI);
358  MI->getOperand(0).setIsDead(true);
359  } else {
360  if (TheDelegate)
361  TheDelegate->LRE_WillEraseInstruction(MI);
363  MI->eraseFromParent();
364  ++NumDCEDeleted;
365  }
366  }
367 
368  // Erase any virtregs that are now empty and unused. There may be <undef>
369  // uses around. Keep the empty live range in that case.
370  for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
371  unsigned Reg = RegsToErase[i];
372  if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
373  ToShrink.remove(&LIS.getInterval(Reg));
374  eraseVirtReg(Reg);
375  }
376  }
377 }
378 
380  ArrayRef<unsigned> RegsBeingSpilled,
381  AliasAnalysis *AA) {
382  ToShrinkSet ToShrink;
383 
384  for (;;) {
385  // Erase all dead defs.
386  while (!Dead.empty())
387  eliminateDeadDef(Dead.pop_back_val(), ToShrink, AA);
388 
389  if (ToShrink.empty())
390  break;
391 
392  // Shrink just one live interval. Then delete new dead defs.
393  LiveInterval *LI = ToShrink.back();
394  ToShrink.pop_back();
395  if (foldAsLoad(LI, Dead))
396  continue;
397  unsigned VReg = LI->reg;
398  if (TheDelegate)
399  TheDelegate->LRE_WillShrinkVirtReg(VReg);
400  if (!LIS.shrinkToUses(LI, &Dead))
401  continue;
402 
403  // Don't create new intervals for a register being spilled.
404  // The new intervals would have to be spilled anyway so its not worth it.
405  // Also they currently aren't spilled so creating them and not spilling
406  // them results in incorrect code.
407  bool BeingSpilled = false;
408  for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
409  if (VReg == RegsBeingSpilled[i]) {
410  BeingSpilled = true;
411  break;
412  }
413  }
414 
415  if (BeingSpilled) continue;
416 
417  // LI may have been separated, create new intervals.
418  LI->RenumberValues();
420  LIS.splitSeparateComponents(*LI, SplitLIs);
421  if (!SplitLIs.empty())
422  ++NumFracRanges;
423 
424  unsigned Original = VRM ? VRM->getOriginal(VReg) : 0;
425  for (const LiveInterval *SplitLI : SplitLIs) {
426  // If LI is an original interval that hasn't been split yet, make the new
427  // intervals their own originals instead of referring to LI. The original
428  // interval must contain all the split products, and LI doesn't.
429  if (Original != VReg && Original != 0)
430  VRM->setIsSplitFromReg(SplitLI->reg, Original);
431  if (TheDelegate)
432  TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg, VReg);
433  }
434  }
435 }
436 
437 // Keep track of new virtual registers created via
438 // MachineRegisterInfo::createVirtualRegister.
439 void
440 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
441 {
442  if (VRM)
443  VRM->grow();
444 
445  if (Parent && !Parent->isSpillable())
446  LIS.getInterval(VReg).markNotSpillable();
447 
448  NewRegs.push_back(VReg);
449 }
450 
451 void
453  const MachineLoopInfo &Loops,
454  const MachineBlockFrequencyInfo &MBFI) {
455  VirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
456  for (unsigned I = 0, Size = size(); I < Size; ++I) {
457  LiveInterval &LI = LIS.getInterval(get(I));
458  if (MRI.recomputeRegClass(LI.reg))
459  DEBUG({
460  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
461  dbgs() << "Inflated " << PrintReg(LI.reg) << " to "
462  << TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
463  });
465  }
466 }
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
mop_iterator operands_end()
Definition: MachineInstr.h:296
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const unsigned reg
Definition: LiveInterval.h:656
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
STATISTIC(NumFunctions,"Total number of functions")
void RemoveMachineInstrFromMaps(MachineInstr &MI)
size_t i
bool anyRematerializable(AliasAnalysis *)
anyRematerializable - Return true if any parent values may be rematerializable.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:754
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:873
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:108
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
A live range for subregisters.
Definition: LiveInterval.h:632
void setIsDead(bool Val=true)
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:538
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
bool empty() const
Definition: LiveInterval.h:357
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:396
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
Hexagon Hardware Loops
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterInfo * getTargetRegisterInfo() const
VNInfo::Allocator & getVNInfoAllocator()
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:710
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
unsigned SubReg
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
void pop_back()
Remove the last element of the SetVector.
Definition: SetVector.h:216
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void markDeadRemat(MachineInstr *inst)
void setIsSplitFromReg(unsigned virtReg, unsigned SReg)
records virtReg is a split live interval from SReg.
Definition: VirtRegMap.h:138
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, LiveIntervals *LIS=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
MachineBasicBlock * MBB
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:223
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses...
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:73
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:565
unsigned createFrom(unsigned OldReg)
createFrom - Create a new virtual register based on OldReg.
SlotIndexes * getSlotIndexes() const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:516
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:720
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:138
void removeInterval(unsigned Reg)
unsigned getOriginal(unsigned VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting...
Definition: VirtRegMap.h:151
MachineInstrBuilder & UseMI
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< unsigned > RegsBeingSpilled=None, AliasAnalysis *AA=nullptr)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
bool isCopy() const
Definition: MachineInstr.h:807
virtual bool LRE_CanEraseVirtReg(unsigned)
Called when a virtual register is no longer used.
Definition: LiveRangeEdit.h:48
LiveInterval & getParent() const
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
Definition: LiveRangeEdit.h:44
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:190
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:789
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:382
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:759
LiveInterval & getInterval(unsigned Reg)
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
LiveInterval & createEmptyInterval(unsigned Reg)
virtual void LRE_WillShrinkVirtReg(unsigned)
Called before shrinking the live range of a virtual register.
Definition: LiveRangeEdit.h:51
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old)
Called after cloning a virtual register.
Definition: LiveRangeEdit.h:55
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
const T & back() const
Return the last element of the SetVector.
Definition: SetVector.h:123
bool hasInterval(unsigned Reg) const
Remat - Information needed to rematerialize at a specific location.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:247
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
mop_iterator operands_begin()
Definition: MachineInstr.h:295
LiveInterval & createEmptyIntervalFrom(unsigned OldReg)
createEmptyIntervalFrom - Create a new empty interval based on OldReg.
A vector that has set insertion semantics.
Definition: SetVector.h:41
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
#define DEBUG(X)
Definition: Debug.h:100
void calculateRegClassAndHint(MachineFunction &, const MachineLoopInfo &, const MachineBlockFrequencyInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void eraseVirtReg(unsigned Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS...
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
unsigned size() const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
unsigned getReg() const
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...