LLVM  4.0.0
ProcessImplicitDefs.cpp
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1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "llvm/ADT/SetVector.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Support/Debug.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "processimplicitdefs"
24 
25 namespace {
26 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
27 /// for each use. Add isUndef marker to implicit_def defs and their uses.
28 class ProcessImplicitDefs : public MachineFunctionPass {
29  const TargetInstrInfo *TII;
30  const TargetRegisterInfo *TRI;
32 
34 
35  void processImplicitDef(MachineInstr *MI);
36  bool canTurnIntoImplicitDef(MachineInstr *MI);
37 
38 public:
39  static char ID;
40 
41  ProcessImplicitDefs() : MachineFunctionPass(ID) {
43  }
44 
45  void getAnalysisUsage(AnalysisUsage &au) const override;
46 
47  bool runOnMachineFunction(MachineFunction &fn) override;
48 };
49 } // end anonymous namespace
50 
53 
54 INITIALIZE_PASS_BEGIN(ProcessImplicitDefs, "processimpdefs",
55  "Process Implicit Definitions", false, false)
56 INITIALIZE_PASS_END(ProcessImplicitDefs, "processimpdefs",
58 
59 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
60  AU.setPreservesCFG();
61  AU.addPreserved<AAResultsWrapperPass>();
63 }
64 
65 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
66  if (!MI->isCopyLike() &&
67  !MI->isInsertSubreg() &&
68  !MI->isRegSequence() &&
69  !MI->isPHI())
70  return false;
71  for (const MachineOperand &MO : MI->operands())
72  if (MO.isReg() && MO.isUse() && MO.readsReg())
73  return false;
74  return true;
75 }
76 
77 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
78  DEBUG(dbgs() << "Processing " << *MI);
79  unsigned Reg = MI->getOperand(0).getReg();
80 
82  // For virtual registers, mark all uses as <undef>, and convert users to
83  // implicit-def when possible.
84  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
85  MO.setIsUndef();
86  MachineInstr *UserMI = MO.getParent();
87  if (!canTurnIntoImplicitDef(UserMI))
88  continue;
89  DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
90  UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
91  WorkList.insert(UserMI);
92  }
93  MI->eraseFromParent();
94  return;
95  }
96 
97  // This is a physreg implicit-def.
98  // Look for the first instruction to use or define an alias.
101  bool Found = false;
102  for (++UserMI; UserMI != UserE; ++UserMI) {
103  for (MachineOperand &MO : UserMI->operands()) {
104  if (!MO.isReg())
105  continue;
106  unsigned UserReg = MO.getReg();
108  !TRI->regsOverlap(Reg, UserReg))
109  continue;
110  // UserMI uses or redefines Reg. Set <undef> flags on all uses.
111  Found = true;
112  if (MO.isUse())
113  MO.setIsUndef();
114  }
115  if (Found)
116  break;
117  }
118 
119  // If we found the using MI, we can erase the IMPLICIT_DEF.
120  if (Found) {
121  DEBUG(dbgs() << "Physreg user: " << *UserMI);
122  MI->eraseFromParent();
123  return;
124  }
125 
126  // Using instr wasn't found, it could be in another block.
127  // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
128  for (unsigned i = MI->getNumOperands() - 1; i; --i)
129  MI->RemoveOperand(i);
130  DEBUG(dbgs() << "Keeping physreg: " << *MI);
131 }
132 
133 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
134 /// <undef> operands.
135 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
136 
137  DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
138  << "********** Function: " << MF.getName() << '\n');
139 
140  bool Changed = false;
141 
142  TII = MF.getSubtarget().getInstrInfo();
143  TRI = MF.getSubtarget().getRegisterInfo();
144  MRI = &MF.getRegInfo();
145  assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
146  assert(WorkList.empty() && "Inconsistent worklist state");
147 
148  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
149  MFI != MFE; ++MFI) {
150  // Scan the basic block for implicit defs.
151  for (MachineBasicBlock::instr_iterator MBBI = MFI->instr_begin(),
152  MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
153  if (MBBI->isImplicitDef())
154  WorkList.insert(&*MBBI);
155 
156  if (WorkList.empty())
157  continue;
158 
159  DEBUG(dbgs() << "BB#" << MFI->getNumber() << " has " << WorkList.size()
160  << " implicit defs.\n");
161  Changed = true;
162 
163  // Drain the WorkList to recursively process any new implicit defs.
164  do processImplicitDef(WorkList.pop_back_val());
165  while (!WorkList.empty());
166  }
167  return Changed;
168 }
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_end()
size_t i
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
INITIALIZE_PASS_BEGIN(ProcessImplicitDefs,"processimpdefs","Process Implicit Definitions", false, false) INITIALIZE_PASS_END(ProcessImplicitDefs
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:786
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Process Implicit Definitions
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:819
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isInsertSubreg() const
Definition: MachineInstr.h:795
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Represent the analysis usage information of a pass.
void initializeProcessImplicitDefsPass(PassRegistry &)
Process Implicit false
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
self_iterator getIterator()
Definition: ilist_node.h:81
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:292
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
A collection of legacy interfaces for querying information about the current executing process...
Definition: Process.h:44
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
bool isRegSequence() const
Definition: MachineInstr.h:801