LLVM  4.0.0
Namespaces | Macros | Enumerations | Functions | Variables
HexagonVLIWPacketizer.cpp File Reference
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "HexagonTargetMachine.h"
#include "HexagonVLIWPacketizer.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
Include dependency graph for HexagonVLIWPacketizer.cpp:

Go to the source code of this file.

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Macros

#define DEBUG_TYPE   "packets"
 

Enumerations

enum  PredicateKind { PK_False, PK_True, PK_Unknown }
 

Functions

FunctionPassllvm::createHexagonPacketizer ()
 
void llvm::initializeHexagonPacketizerPass (PassRegistry &)
 
 INITIALIZE_PASS_BEGIN (HexagonPacketizer,"packets","Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
 
static bool hasWriteToReadDep (const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
 
static MachineBasicBlock::iterator moveInstrOut (MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
 
static bool isRegDependence (const SDep::Kind DepType)
 
static bool isDirectJump (const MachineInstr &MI)
 
static bool isSchedBarrier (const MachineInstr &MI)
 
static bool isControlFlow (const MachineInstr &MI)
 
static bool doesModifyCalleeSavedReg (const MachineInstr &MI, const TargetRegisterInfo *TRI)
 Returns true if the instruction modifies a callee-saved register. More...
 
static PredicateKind getPredicateSense (const MachineInstr &MI, const HexagonInstrInfo *HII)
 Returns true if an instruction is predicated on p0 and false if it's predicated on !p0. More...
 
static const MachineOperandgetPostIncrementOperand (const MachineInstr &MI, const HexagonInstrInfo *HII)
 
static const MachineOperandgetStoreValueOperand (const MachineInstr &MI)
 
static bool isLoadAbsSet (const MachineInstr &MI)
 
static const MachineOperandgetAbsSetOperand (const MachineInstr &MI)
 
static bool isImplicitDependency (const MachineInstr &I, unsigned DepReg)
 
static unsigned getPredicatedRegister (MachineInstr &MI, const HexagonInstrInfo *QII)
 Gets the predicate register of a predicated instruction. More...
 
static bool cannotCoexistAsymm (const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
 
static bool isSystemInstr (const MachineInstr &MI)
 
static bool isDependent (const MachineInstr &ProdMI, const MachineInstr &ConsMI)
 

Variables

static cl::opt< boolDisablePacketizer ("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
 
static cl::opt< boolPacketizeVolatiles ("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
 
static cl::opt< boolEnableGenAllInsnClass ("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
 
static cl::opt< boolDisableVecDblNVStores ("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
 
cl::opt< boolScheduleInlineAsm
 
 packets
 
Hexagon Packetizer
 
Hexagon false
 

Macro Definition Documentation

#define DEBUG_TYPE   "packets"

Definition at line 34 of file HexagonVLIWPacketizer.cpp.

Enumeration Type Documentation

Enumerator
PK_False 
PK_True 
PK_Unknown 

Definition at line 485 of file HexagonVLIWPacketizer.cpp.

Function Documentation

static bool cannotCoexistAsymm ( const MachineInstr MI,
const MachineInstr MJ,
const HexagonInstrInfo HII 
)
static
static bool doesModifyCalleeSavedReg ( const MachineInstr MI,
const TargetRegisterInfo TRI 
)
static
static const MachineOperand& getAbsSetOperand ( const MachineInstr MI)
static
static const MachineOperand& getPostIncrementOperand ( const MachineInstr MI,
const HexagonInstrInfo HII 
)
static
static unsigned getPredicatedRegister ( MachineInstr MI,
const HexagonInstrInfo QII 
)
static

Gets the predicate register of a predicated instruction.

We use the following rule: The first predicate register that is a use is the predicate register of a predicated instruction.

Definition at line 872 of file HexagonVLIWPacketizer.cpp.

References assert(), llvm::HexagonInstrInfo::isPredicated(), llvm_unreachable, and llvm::MachineInstr::operands().

Referenced by llvm::HexagonPacketizerList::arePredicatesComplements().

static PredicateKind getPredicateSense ( const MachineInstr MI,
const HexagonInstrInfo HII 
)
static

Returns true if an instruction is predicated on p0 and false if it's predicated on !p0.

Definition at line 493 of file HexagonVLIWPacketizer.cpp.

References llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonInstrInfo::isPredicatedTrue(), PK_False, PK_True, and PK_Unknown.

Referenced by llvm::HexagonPacketizerList::arePredicatesComplements(), and llvm::HexagonPacketizerList::canPromoteToNewValueStore().

static const MachineOperand& getStoreValueOperand ( const MachineInstr MI)
static
static bool hasWriteToReadDep ( const MachineInstr FirstI,
const MachineInstr SecondI,
const TargetRegisterInfo TRI 
)
static
INITIALIZE_PASS_BEGIN ( HexagonPacketizer  ,
"packets"  ,
"Hexagon Packetizer ,
false  ,
false   
)
static bool isControlFlow ( const MachineInstr MI)
static
static bool isDependent ( const MachineInstr ProdMI,
const MachineInstr ConsMI 
)
static
static bool isDirectJump ( const MachineInstr MI)
static
static bool isImplicitDependency ( const MachineInstr I,
unsigned  DepReg 
)
static
static bool isLoadAbsSet ( const MachineInstr MI)
static
static bool isRegDependence ( const SDep::Kind  DepType)
static
static bool isSchedBarrier ( const MachineInstr MI)
static
static bool isSystemInstr ( const MachineInstr MI)
static
static MachineBasicBlock::iterator moveInstrOut ( MachineInstr MI,
MachineBasicBlock::iterator  BundleIt,
bool  Before 
)
static

Variable Documentation

cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
static
cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
static
cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
static
Hexagon false

Definition at line 98 of file HexagonVLIWPacketizer.cpp.

Hexagon Packetizer

Definition at line 98 of file HexagonVLIWPacketizer.cpp.

cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
static
packets

Definition at line 98 of file HexagonVLIWPacketizer.cpp.

cl::opt<bool> ScheduleInlineAsm