14 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
15 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
24 class ScheduleDAGInstrs;
26 struct MachineSchedContext;
63 assert(!IsInstance &&
"Not a Pass ID");
67 assert(IsInstance &&
"Not a Pass Instance");
103 bool AddingMachinePasses;
128 template<
typename TMC> TMC &
getTM()
const {
129 return *
static_cast<TMC*
>(
TM);
149 assert(!(StartBefore && StartAfter) &&
150 "Start after and start before passes are given");
151 assert(!(StopBefore && StopAfter) &&
152 "Stop after and stop before passed are given");
153 this->StartBefore = StartBefore;
154 this->StartAfter = StartAfter;
155 this->StopBefore = StopBefore;
156 this->StopAfter = StopAfter;
157 Started = (StartAfter ==
nullptr) && (StartBefore ==
nullptr);
172 bool VerifyAfter =
true,
bool PrintAfter =
true);
301 void setOpt(
bool &Opt,
bool Val);
391 bool printAfter =
true);
400 void addPass(
Pass *
P,
bool verifyAfter =
true,
bool printAfter =
true);
Pass interface - Implemented by all 'passes'.
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void setDisableVerify(bool Disable)
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
bool getEnableShrinkWrap() const
Return true if shrink wrapping is enabled.
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Pass * getInstance() const
CodeGenOpt::Level getOptLevel() const
TMC & getTM() const
Get the right type of TargetMachine for this target.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
IdentifyingPassPtr(Pass *InstancePtr)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
Target-Independent Code Generator Pass Configuration Options.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter, AnalysisID StopBefore, AnalysisID StopAfter)
Set the StartAfter, StartBefore and StopAfter passes to allow running only a portion of the normal co...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
Function Alias Analysis false
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
static char PostRAMachineLICMID
PostRAMachineLICM - A clone of the LICM pass that runs during late machine optimization after regallo...
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
void setEnableTailMerge(bool Enable)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
bool getEnableTailMerge() const
FunctionPass class - This class is used to implement most global optimizations.
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void pm(uint64_t &Value)
Adjusts a program memory address.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
isPodLike - This is a type trait that is used to determine whether a given type can be copied around ...
ImmutablePass class - This class is used to provide information that does not need to be run...
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
~TargetPassConfig() override
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
virtual void addBlockPlacement()
Add standard basic block placement passes.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
void setOpt(bool &Opt, bool Val)
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static char EarlyTailDuplicateID
Pseudo Pass IDs.
IdentifyingPassPtr(AnalysisID IDPtr)
Primary interface to the complete machine description for the target machine.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
bool EnableTailMerge
Default setting for -enable-tail-merge on this target.