33 #define DEBUG_TYPE "mccodeemitter"
35 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
41 class LanaiMCCodeEmitter :
public MCCodeEmitter {
43 LanaiMCCodeEmitter(
const MCInstrInfo &MCII, MCContext &
C) {}
44 LanaiMCCodeEmitter(
const LanaiMCCodeEmitter &) =
delete;
45 void operator=(
const LanaiMCCodeEmitter &) =
delete;
46 ~LanaiMCCodeEmitter()
override =
default;
53 uint64_t getBinaryCodeForInstr(
const MCInst &Inst,
54 SmallVectorImpl<MCFixup> &
Fixups,
55 const MCSubtargetInfo &SubtargetInfo)
const;
59 unsigned getMachineOpValue(
const MCInst &Inst,
const MCOperand &MCOp,
60 SmallVectorImpl<MCFixup> &
Fixups,
61 const MCSubtargetInfo &SubtargetInfo)
const;
63 unsigned getRiMemoryOpValue(
const MCInst &Inst,
unsigned OpNo,
64 SmallVectorImpl<MCFixup> &
Fixups,
65 const MCSubtargetInfo &SubtargetInfo)
const;
67 unsigned getRrMemoryOpValue(
const MCInst &Inst,
unsigned OpNo,
68 SmallVectorImpl<MCFixup> &
Fixups,
69 const MCSubtargetInfo &SubtargetInfo)
const;
71 unsigned getSplsOpValue(
const MCInst &Inst,
unsigned OpNo,
72 SmallVectorImpl<MCFixup> &
Fixups,
73 const MCSubtargetInfo &SubtargetInfo)
const;
76 SmallVectorImpl<MCFixup> &
Fixups,
77 const MCSubtargetInfo &SubtargetInfo)
const;
79 void encodeInstruction(
const MCInst &Inst, raw_ostream &Ostream,
80 SmallVectorImpl<MCFixup> &
Fixups,
81 const MCSubtargetInfo &SubtargetInfo)
const override;
83 unsigned adjustPqBitsRmAndRrm(
const MCInst &Inst,
unsigned Value,
84 const MCSubtargetInfo &STI)
const;
86 unsigned adjustPqBitsSpls(
const MCInst &Inst,
unsigned Value,
87 const MCSubtargetInfo &STI)
const;
93 if (isa<MCSymbolRefExpr>(Expr))
95 if (
const LanaiMCExpr *McExpr = dyn_cast<LanaiMCExpr>(Expr)) {
111 unsigned LanaiMCCodeEmitter::getMachineOpValue(
112 const MCInst &Inst,
const MCOperand &MCOp, SmallVectorImpl<MCFixup> &
Fixups,
113 const MCSubtargetInfo &SubtargetInfo)
const {
117 return static_cast<unsigned>(MCOp.getImm());
121 const MCExpr *Expr = MCOp.getExpr();
125 const MCBinaryExpr *BinaryExpr =
static_cast<const MCBinaryExpr *
>(Expr);
126 Expr = BinaryExpr->getLHS();
138 unsigned QBitShift) {
145 Value &= ~(1 << PBitShift);
149 Value |= (1 << PBitShift);
153 "Expected register operand.");
154 Value &= ~(1 << QBitShift);
157 Value |= (1 << QBitShift);
163 LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(
const MCInst &Inst,
unsigned Value,
164 const MCSubtargetInfo &STI)
const {
169 LanaiMCCodeEmitter::adjustPqBitsSpls(
const MCInst &Inst,
unsigned Value,
170 const MCSubtargetInfo &STI)
const {
174 void LanaiMCCodeEmitter::encodeInstruction(
175 const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups,
176 const MCSubtargetInfo &SubtargetInfo)
const {
178 unsigned Value = getBinaryCodeForInstr(Inst, Fixups, SubtargetInfo);
182 for (
int i = (4 - 1) * 8;
i >= 0;
i -= 8)
183 Ostream << static_cast<char>((Value >>
i) & 0xff);
187 unsigned LanaiMCCodeEmitter::getRiMemoryOpValue(
188 const MCInst &Inst,
unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
189 const MCSubtargetInfo &SubtargetInfo)
const {
191 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
192 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
193 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
195 assert(Op1.isReg() &&
"First operand is not register.");
196 assert((Op2.isImm() || Op2.isExpr()) &&
197 "Second operand is neither an immediate nor an expression.");
199 "Register immediate only supports addition operator");
204 "Constant value truncated (limited to 16-bit)");
206 Encoding |= (Op2.getImm() & 0xffff);
207 if (Op2.getImm() != 0) {
209 Encoding |= (0x3 << 16);
211 Encoding |= (0x1 << 16);
214 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
219 unsigned LanaiMCCodeEmitter::getRrMemoryOpValue(
220 const MCInst &Inst,
unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
221 const MCSubtargetInfo &SubtargetInfo)
const {
223 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
224 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
225 const MCOperand AluMCOp = Inst.getOperand(OpNo + 2);
227 assert(Op1.isReg() &&
"First operand is not register.");
229 assert(Op2.isReg() &&
"Second operand is not register.");
232 assert(AluMCOp.isImm() &&
"Third operator is not immediate.");
234 unsigned AluOp = AluMCOp.getImm();
238 Encoding |= (0x3 << 8);
240 Encoding |= (0x1 << 8);
258 LanaiMCCodeEmitter::getSplsOpValue(
const MCInst &Inst,
unsigned OpNo,
259 SmallVectorImpl<MCFixup> &Fixups,
260 const MCSubtargetInfo &SubtargetInfo)
const {
262 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
263 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
264 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
266 assert(Op1.isReg() &&
"First operand is not register.");
267 assert((Op2.isImm() || Op2.isExpr()) &&
268 "Second operand is neither an immediate nor an expression.");
270 "Register immediate only supports addition operator");
274 assert(isInt<10>(Op2.getImm()) &&
275 "Constant value truncated (limited to 10-bit)");
277 Encoding |= (Op2.getImm() & 0x3ff);
278 if (Op2.getImm() != 0) {
280 Encoding |= (0x3 << 10);
282 Encoding |= (0x1 << 10);
285 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
291 const MCInst &Inst,
unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
292 const MCSubtargetInfo &SubtargetInfo)
const {
293 const MCOperand &MCOp = Inst.getOperand(OpNo);
294 if (MCOp.isReg() || MCOp.isImm())
295 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
303 #include "LanaiGenMCCodeEmitter.inc"
311 return new LanaiMCCodeEmitter(InstrInfo, context);
static bool modifiesOp(unsigned AluOp)
static unsigned getAluOp(unsigned AluOp)
MCCodeEmitter * createLanaiMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
static unsigned getLanaiRegisterNumbering(unsigned Reg)
constexpr bool isInt< 16 >(int64_t x)
Base class for the full range of assembler expressions which are needed for parsing.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static bool isPreOp(unsigned AluOp)
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Lanai::Fixups FixupKind(const MCExpr *Expr)
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
STATISTIC(MCNumEmitted,"Number of MC instructions emitted")
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static bool isPostOp(unsigned AluOp)
unsigned adjustPqBits(const MCInst &Inst, unsigned Value, unsigned PBitShift, unsigned QBitShift)
References to labels and assigned expressions.
static unsigned encodeLanaiAluCode(unsigned AluOp)
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const