15 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
16 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H
28 class MachineFrameInfo;
29 class MachineLoopInfo;
30 class MachineDominatorTree;
31 class RegPressureTracker;
41 :
VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
54 :
VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
72 typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
222 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
269 unsigned regioninstrs);
340 "SUnits std::vector reallocated on the fly!");
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
unsigned getSparseSetIndex() const
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Record a physical register access.
void addVRegDefDeps(SUnit *SU, unsigned OperIdx)
addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur...
bool TrackLaneMasks
Whether lane masks should get tracked.
void dumpNode(const SUnit *SU) const override
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
MachineBasicBlock::iterator begin() const
begin - Return an iterator to the top of the current scheduling region.
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolve and cache a resolved scheduling class for an SUnit.
SmallVector< UnderlyingObject, 4 > UnderlyingObjectsVector
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
void fixupKills(MachineBasicBlock *MBB)
Fix register kill flags that scheduling has made invalid.
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
The two locations may or may not alias. This is the least precise result.
void insertBarrierChain(Value2SUsMap &map)
Insert a barrier chain in a huge region, far below current SU.
const TargetSchedModel * getSchedModel() const
Get the machine model for instruction scheduling.
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
void addSchedBarrierDeps()
addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being sc...
Provide an instruction scheduling machine model to CodeGen passes.
'undef' values are things that do not have specified contents.
An individual mapping from virtual register number to SUnit.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
ValueType getPointer() const
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
void addVRegUseDeps(SUnit *SU, unsigned OperIdx)
addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register ...
void addChainDependencies(SUnit *SU, SUList &sus, unsigned Latency)
Add dependencies as needed from all SUs in list to SU.
SUnit * BarrierChain
Remember a generic side-effecting instruction as we proceed.
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
SparseMultiSet< VReg2SUnitOperIdx, VirtReg2IndexFunctor > VReg2SUnitOperIdxMultiMap
PointerIntPair - This class implements a pair of a pointer and small integer.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Track the current register pressure at some position in the instruction stream, and remember the high...
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
const MCSchedClassDesc * SchedClass
const MachineFrameInfo & MFI
std::string getDAGName() const override
Return a label for the region of code covered by the DAG.
void addPhysRegDeps(SUnit *SU, unsigned OperIdx)
addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following inst...
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
std::string getGraphNodeLabel(const SUnit *SU) const override
Return a label for a DAG node that points to an instruction.
PhysRegSUOper(SUnit *su, int op, unsigned R)
void reduceHugeMemNodeMaps(Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
Remove in FIFO order some SUs from huge maps.
bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO)
Toggle a register operand kill flag.
ValueType getValue() const
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU)
Reg2SUnitsMap Defs
State internal to DAG building.
const MachineLoopInfo * MLI
SparseMultiSet< VReg2SUnit, VirtReg2IndexFunctor > VReg2SUnitMultiMap
Track local uses of virtual registers.
VReg2SUnitOperIdxMultiMap CurrentVRegUses
Tracks the last instructions in this region using each virtual register.
virtual void finalizeSchedule()
finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole Machin...
virtual void schedule()=0
schedule - Order nodes according to selected style, filling in the Sequence member.
MachineBasicBlock::iterator end() const
end - Return an iterator to the bottom of the current scheduling region.
VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
SUnit * getSUnit(MachineInstr *MI) const
getSUnit - Return an existing SUnit for this MI, or NULL.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
Representation of each machine instruction.
SparseSet - Fast set implmentation for objects that can be identified by small unsigned keys...
Mapping from virtual register to SUnit including an operand index.
void addChainDependency(SUnit *SUa, SUnit *SUb, unsigned Latency=0)
Add a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the depe...
unsigned getSparseSetIndex() const
ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
SUnit * newSUnit(MachineInstr *MI)
newSUnit - Creates a new SUnit and return a ptr to it.
void addBarrierChain(Value2SUsMap &map)
Add barrier chain edges from all SUs in map, and then clear the map.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const
Returns a mask for which lanes get read/written by the given (register) machine operand.
void startBlockForKills(MachineBasicBlock *BB)
PostRA helper for rewriting kill flags.
SparseSet< VReg2SUnit, VirtReg2IndexFunctor > VReg2SUnitMap
Use SparseSet as a SparseMap by relying on the fact that it never compares ValueT's, only unsigned keys.
void initSUnits()
Create an SUnit for each real instruction, numbered in top-down topological order.
SparseMultiSet< PhysRegSUOper, llvm::identity< unsigned >, uint16_t > Reg2SUnitsMap
Use a SparseMultiSet to track physical registers.
MachineInstr * FirstDbgValue
UnderlyingObject(ValueType V, bool MayAlias)
MachineBasicBlock * BB
State specific to the current scheduling region.
std::vector< SUnit > SUnits
VReg2SUnitMultiMap CurrentVRegDefs
Tracks the last instruction(s) in this region defining each virtual register.
PointerUnion< const Value *, const PseudoSourceValue * > ValueType
BitVector LiveRegs
Set of live physical registers for updating kill flags.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
DbgValues - Remember instruction that precedes DBG_VALUE.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
std::list< SUnit * > SUList
A list of SUnits, used in Value2SUsMap, during DAG construction.
~ScheduleDAGInstrs() override