32 case TargetOpcode::COPY: {
43 EM.insert(std::make_pair(DstR, SrcR));
46 case TargetOpcode::REG_SEQUENCE:
54 CopyMap.insert(std::make_pair(SA.
Id, EM));
55 Copies.push_back(SA.
Id);
58 auto FS = DefM.find(
I.second.Reg);
59 if (FS == DefM.end() || FS->second.empty())
61 RDefMap[
I.second][SA.
Id] = FS->second.top()->Id;
71 RRs.insert(RA.Addr->getRegRef(DFG));
73 for (
auto &R : RDefMap) {
74 if (!RRs.count(R.first))
82 for (
auto &R : RDefMap) {
83 if (!RRs.count(R.first))
85 auto F = DefM.find(R.first.Reg);
86 if (
F == DefM.end() ||
F->second.empty())
88 R.second[IA.
Id] =
F->second.top()->Id;
95 auto BA = DFG.
getFunc().Addr->findBlock(B, DFG);
112 Changed |= scanBlock(
I->getBlock());
123 dbgs() <<
"Copies:\n";
124 for (
auto I : Copies) {
127 for (
auto J : CopyMap[
I])
132 dbgs() <<
"\nRDef map:\n";
133 for (
auto R : RDefMap) {
135 for (
auto &M : R.second)
142 bool Changed =
false;
144 bool HasLimit =
CpLimit.getNumOccurrences() > 0;
147 auto MinPhysReg = [
this] (
RegisterRef RR) ->
unsigned {
154 return S.getSubReg();
159 for (
auto C : Copies) {
165 auto FS = CopyMap.find(SA.
Id);
166 if (FS == CopyMap.end())
172 auto FR = EM.find(DR);
179 auto &RDefSR = RDefMap[SR];
182 for (
NodeId N = DA.Addr->getReachedUse(), NextN;
N; N = NextN) {
185 uint16_t
F = UA.Addr->getFlags();
188 if (UA.Addr->getRegRef(DFG) != DR)
193 if (RDefSR[IA.
Id] != RDefSR_SA)
205 unsigned NewReg = MinPhysReg(SR);
209 if (RDefSR_SA != 0) {
210 UA.Addr->linkToDef(UA.Id, DFG.
addr<
DefNode*>(RDefSR_SA));
212 UA.Addr->setReachingDef(0);
213 UA.Addr->setSibling(0);
223 auto FC = CopyMap.find(IA.
Id);
224 if (
FC != CopyMap.end()) {
226 auto &M =
FC->second;
NodeList members(const DataFlowGraph &G) const
void pushDefs(NodeAddr< InstrNode * > IA, DefStackMap &DM)
MachineFunction & getMF() const
static cl::opt< unsigned > CpLimit("rdf-cp-limit", cl::init(0), cl::Hidden)
std::map< RegisterRef, RegisterRef > EqualityMap
bool isValid() const
Returns true if this iterator is not yet at the end.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
void unlinkUse(NodeAddr< UseNode * > UA, bool RemoveFromOwner)
void releaseBlock(NodeId B, DefStackMap &DefM)
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
const MachineBasicBlock & front() const
static bool IsDef(const NodeAddr< NodeBase * > BA)
Base class for the actual dominator tree node.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
NodeList members_if(Predicate P, const DataFlowGraph &G) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const TargetRegisterInfo & getTRI() const
initializer< Ty > init(const Ty &Val)
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
const MachineOperand & getOperand(unsigned i) const
static bool IsCode(const NodeAddr< NodeBase * > BA)
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM)
void markBlock(NodeId B, DefStackMap &DefM)
MachineOperand class - Representation of each machine instruction operand.
NodeId getSibling() const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
NodeAddr< FuncNode * > getFunc() const
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setSubReg(unsigned subReg)
const LaneBitmask LaneMask
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstr * getCode() const
NodeAddr< T > addr(NodeId N) const
std::set< RegisterRef > RegisterSet