LLVM  4.0.0
AArch64DeadRegisterDefinitionsPass.cpp
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1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file When allowed by the instruction, replace a dead definition of a GPR
10 /// with the zero register. This makes the code a bit friendlier towards the
11 /// hardware's register renamer.
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64.h"
15 #include "AArch64RegisterInfo.h"
16 #include "llvm/ADT/Statistic.h"
21 #include "llvm/Support/Debug.h"
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "aarch64-dead-defs"
28 
29 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
30 
31 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
32 
33 namespace {
34 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
35 private:
36  const TargetRegisterInfo *TRI;
37  const MachineRegisterInfo *MRI;
38  const TargetInstrInfo *TII;
39  bool Changed;
40  void processMachineBasicBlock(MachineBasicBlock &MBB);
41 public:
42  static char ID; // Pass identification, replacement for typeid.
43  AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
46  }
47 
48  bool runOnMachineFunction(MachineFunction &F) override;
49 
50  StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
51 
52  void getAnalysisUsage(AnalysisUsage &AU) const override {
53  AU.setPreservesCFG();
55  }
56 };
58 } // end anonymous namespace
59 
60 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
61  AARCH64_DEAD_REG_DEF_NAME, false, false)
62 
63 static bool usesFrameIndex(const MachineInstr &MI) {
64  for (const MachineOperand &MO : MI.uses())
65  if (MO.isFI())
66  return true;
67  return false;
68 }
69 
70 void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
72  const MachineFunction &MF = *MBB.getParent();
73  for (MachineInstr &MI : MBB) {
74  if (usesFrameIndex(MI)) {
75  // We need to skip this instruction because while it appears to have a
76  // dead def it uses a frame index which might expand into a multi
77  // instruction sequence during EPI.
78  DEBUG(dbgs() << " Ignoring, operand is frame index\n");
79  continue;
80  }
81  if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
82  // It is not allowed to write to the same register (not even the zero
83  // register) twice in a single instruction.
84  DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n");
85  continue;
86  }
87  const MCInstrDesc &Desc = MI.getDesc();
88  for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
89  MachineOperand &MO = MI.getOperand(I);
90  if (!MO.isReg() || !MO.isDef())
91  continue;
92  // We should not have any relevant physreg defs that are replacable by
93  // zero before register allocation. So we just check for dead vreg defs.
94  unsigned Reg = MO.getReg();
96  (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
97  continue;
98  assert(!MO.isImplicit() && "Unexpected implicit def!");
99  DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
100  MI.print(dbgs()));
101  // Be careful not to change the register if it's a tied operand.
102  if (MI.isRegTiedToUseOperand(I)) {
103  DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
104  continue;
105  }
106  const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
107  unsigned NewReg;
108  if (RC == nullptr) {
109  DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
110  continue;
111  } else if (RC->contains(AArch64::WZR))
112  NewReg = AArch64::WZR;
113  else if (RC->contains(AArch64::XZR))
114  NewReg = AArch64::XZR;
115  else {
116  DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
117  continue;
118  }
119  DEBUG(dbgs() << " Replacing with zero register. New:\n ");
120  MO.setReg(NewReg);
121  MO.setIsDead();
122  DEBUG(MI.print(dbgs()));
123  ++NumDeadDefsReplaced;
124  Changed = true;
125  // Only replace one dead register, see check for zero register above.
126  break;
127  }
128  }
129 }
130 
131 // Scan the function for instructions that have a dead definition of a
132 // register. Replace that register with the zero register when possible.
133 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
134  if (skipFunction(*MF.getFunction()))
135  return false;
136 
137  TRI = MF.getSubtarget().getRegisterInfo();
138  TII = MF.getSubtarget().getInstrInfo();
139  MRI = &MF.getRegInfo();
140  DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
141  Changed = false;
142  for (auto &MBB : MF)
143  processMachineBasicBlock(MBB);
144  return Changed;
145 }
146 
148  return new AArch64DeadRegisterDefinitions();
149 }
bool isImplicit() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
STATISTIC(NumFunctions,"Total number of functions")
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
INITIALIZE_PASS(AArch64DeadRegisterDefinitions,"aarch64-dead-defs", AARCH64_DEAD_REG_DEF_NAME, false, false) static bool usesFrameIndex(const MachineInstr &MI)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
#define F(x, y, z)
Definition: MD5.cpp:51
MachineBasicBlock * MBB
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
#define AARCH64_DEAD_REG_DEF_NAME
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
virtual const TargetInstrInfo * getInstrInfo() const
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
FunctionPass * createAArch64DeadRegisterDefinitions()
virtual void print(raw_ostream &O, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:117
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.