45 : MF(MF), SM(&SM), IRSlots(IRSlots) {
49 auto I =
VRegInfos.insert(std::make_pair(Num,
nullptr));
54 I.first->second = Info;
56 return *
I.first->second;
63 struct ParsedMachineOperand {
71 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
74 "Only used register operands can be tied");
109 void lex(
unsigned SkipChar = 0);
123 bool parseBasicBlocks();
126 bool parseStandaloneNamedRegister(
unsigned &
Reg);
127 bool parseStandaloneVirtualRegister(
VRegInfo *&Info);
128 bool parseStandaloneRegister(
unsigned &
Reg);
129 bool parseStandaloneStackObject(
int &FI);
130 bool parseStandaloneMDNode(
MDNode *&Node);
138 bool parseNamedRegister(
unsigned &
Reg);
139 bool parseVirtualRegister(
VRegInfo *&Info);
141 bool parseRegisterFlag(
unsigned &
Flags);
142 bool parseSubRegisterIndex(
unsigned &
SubReg);
143 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
155 bool parseStackFrameIndex(
int &FI);
157 bool parseFixedStackFrameIndex(
int &FI);
167 bool parseCFIOffset(
int &
Offset);
168 bool parseCFIRegister(
unsigned &
Reg);
180 bool parseOffset(int64_t &
Offset);
181 bool parseAlignment(
unsigned &Alignment);
183 bool parseIRValue(
const Value *&V);
193 bool getUnsigned(
unsigned &Result);
198 bool getUint64(uint64_t &Result);
204 bool getHexUint(
APInt &Result);
214 void initNames2InstrOpCodes();
218 bool parseInstrName(
StringRef InstrName,
unsigned &OpCode);
220 bool parseInstruction(
unsigned &OpCode,
unsigned &
Flags);
228 void initNames2Regs();
232 bool getRegisterByName(
StringRef RegName,
unsigned &
Reg);
234 void initNames2RegMasks();
241 void initNames2SubRegIndices();
251 const Value *getIRValue(
unsigned Slot);
253 void initNames2TargetIndices();
260 void initNames2DirectTargetFlags();
268 void initNames2BitmaskTargetFlags();
281 : MF(PFS.MF), Error(Error), Source(Source), CurrentSource(Source), PFS(PFS)
284 void MIParser::lex(
unsigned SkipChar) {
286 CurrentSource.data() + SkipChar,
Token,
322 return "<unknown token>";
327 if (
Token.isNot(TokenKind))
334 if (
Token.isNot(TokenKind))
340 bool MIParser::parseBasicBlockDefinition(
346 auto Loc =
Token.location();
349 bool HasAddressTaken =
false;
350 bool IsLandingPad =
false;
351 unsigned Alignment = 0;
356 switch (
Token.kind()) {
358 HasAddressTaken =
true;
366 if (parseAlignment(Alignment))
371 if (parseIRBlock(BB, *MF.getFunction()))
386 BB = dyn_cast_or_null<BasicBlock>(
387 MF.getFunction()->getValueSymbolTable()->lookup(
Name));
390 "' is not defined in the function '" +
393 auto *
MBB = MF.CreateMachineBasicBlock(BB);
395 bool WasInserted = MBBSlots.
insert(std::make_pair(ID,
MBB)).second;
397 return error(Loc,
Twine(
"redefinition of machine basic block with id #") +
407 bool MIParser::parseBasicBlockDefinitions(
413 if (
Token.isErrorOrEOF())
414 return Token.isError();
416 return error(
"expected a basic block definition before instructions");
417 unsigned BraceDepth = 0;
419 if (parseBasicBlockDefinition(MBBSlots))
421 bool IsAfterNewline =
false;
425 Token.isErrorOrEOF())
428 return error(
"basic block definition should be located at the start of "
431 IsAfterNewline =
true;
434 IsAfterNewline =
false;
439 return error(
"extraneous closing brace ('}')");
445 if (!
Token.isError() && BraceDepth)
446 return error(
"expected '}'");
447 }
while (!
Token.isErrorOrEOF());
448 return Token.isError();
456 if (
Token.isNewlineOrEOF())
460 return error(
"expected a named register");
462 if (parseNamedRegister(Reg))
470 return error(
"expected a lane mask");
472 "Use correct get-function for lane mask");
475 return error(
"invalid lane mask value");
489 if (
Token.isNewlineOrEOF())
493 return error(
"expected a machine basic block reference");
502 return error(
"expected an integer literal after '('");
503 if (getUnsigned(Weight))
537 if (parseBasicBlockSuccessors(MBB))
540 if (parseBasicBlockLiveins(MBB))
546 if (!
Token.isNewlineOrEOF())
547 return error(
"expected line break at the end of a list");
552 bool IsInBundle =
false;
577 return error(
"nested instruction bundles are not allowed");
586 assert(
Token.isNewlineOrEOF() &&
"MI is not fully parsed");
592 bool MIParser::parseBasicBlocks() {
597 if (
Token.isErrorOrEOF())
598 return Token.isError();
606 if (parseBasicBlock(*MBB))
619 while (
Token.isRegister() ||
Token.isRegisterFlag()) {
620 auto Loc =
Token.location();
622 if (parseRegisterOperand(MO, TiedDefIdx,
true))
625 ParsedMachineOperand(MO, Loc,
Token.location(), TiedDefIdx));
633 unsigned OpCode,
Flags = 0;
634 if (
Token.isError() || parseInstruction(OpCode, Flags))
640 auto Loc =
Token.location();
642 if (parseMachineOperandAndTargetFlags(MO, TiedDefIdx))
645 ParsedMachineOperand(MO, Loc,
Token.location(), TiedDefIdx));
650 return error(
"expected ',' before the next machine operand");
658 return error(
"expected a metadata node after 'debug-location'");
669 while (!
Token.isNewlineOrEOF()) {
671 if (parseMachineMemoryOperand(MemOp))
674 if (
Token.isNewlineOrEOF())
677 return error(
"expected ',' before the next machine memory operand");
682 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
683 if (!MCID.isVariadic()) {
685 if (verifyImplicitOperands(Operands, MCID))
690 MI = MF.CreateMachineInstr(MCID, DebugLocation,
true);
692 for (
const auto &Operand : Operands)
694 if (assignRegisterTies(*MI, Operands))
696 if (MemOperands.
empty())
699 MF.allocateMemRefsArray(MemOperands.
size());
700 std::copy(MemOperands.
begin(), MemOperands.
end(), MemRefs);
708 return error(
"expected a machine basic block reference");
714 "expected end of string after the machine basic block reference");
718 bool MIParser::parseStandaloneNamedRegister(
unsigned &Reg) {
721 return error(
"expected a named register");
722 if (parseNamedRegister(Reg))
726 return error(
"expected end of string after the register reference");
730 bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
733 return error(
"expected a virtual register");
734 if (parseVirtualRegister(Info))
738 return error(
"expected end of string after the register reference");
742 bool MIParser::parseStandaloneRegister(
unsigned &Reg) {
746 return error(
"expected either a named or virtual register");
749 if (parseRegister(Reg, Info))
754 return error(
"expected end of string after the register reference");
758 bool MIParser::parseStandaloneStackObject(
int &FI) {
761 return error(
"expected a stack object");
762 if (parseStackFrameIndex(FI))
765 return error(
"expected end of string after the stack object reference");
769 bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
772 return error(
"expected a metadata node");
776 return error(
"expected end of string after the metadata node");
782 return MO.
isDef() ?
"implicit-def" :
"implicit";
794 for (
const auto &
I : Operands) {
819 const auto *TRI = MF.getSubtarget().getRegisterInfo();
820 assert(TRI &&
"Expected target register info");
821 for (
const auto &
I : ImplicitOperands) {
825 Twine(
"missing implicit register operand '") +
832 bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
838 return error(
"expected a machine instruction");
840 if (parseInstrName(InstrName, OpCode))
841 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
846 bool MIParser::parseNamedRegister(
unsigned &Reg) {
849 if (getRegisterByName(Name, Reg))
850 return error(
Twine(
"unknown register name '") + Name +
"'");
854 bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
859 Info = &PFS.getVRegInfo(ID);
863 bool MIParser::parseRegister(
unsigned &Reg,
VRegInfo *&Info) {
864 switch (
Token.kind()) {
869 return parseNamedRegister(Reg);
871 if (parseVirtualRegister(Info))
881 bool MIParser::parseRegisterFlag(
unsigned &Flags) {
882 const unsigned OldFlags =
Flags;
883 switch (
Token.kind()) {
914 if (OldFlags == Flags)
917 return error(
"duplicate '" +
Token.stringValue() +
"' register flag");
922 bool MIParser::parseSubRegisterIndex(
unsigned &
SubReg) {
926 return error(
"expected a subregister index after '.'");
927 auto Name =
Token.stringValue();
928 SubReg = getSubRegIndex(Name);
930 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
935 bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
939 return error(
"expected an integer literal after 'tied-def'");
940 if (getUnsigned(TiedDefIdx))
951 for (
unsigned I = 0,
E = Operands.
size();
I !=
E; ++
I) {
952 if (!Operands[
I].TiedDefIdx)
956 unsigned DefIdx = Operands[
I].TiedDefIdx.getValue();
958 return error(Operands[
I].Begin,
959 Twine(
"use of invalid tied-def operand index '" +
960 Twine(DefIdx) +
"'; instruction has only ") +
962 const auto &DefOperand = Operands[DefIdx].Operand;
963 if (!DefOperand.isReg() || !DefOperand.isDef())
965 return error(Operands[
I].Begin,
966 Twine(
"use of invalid tied-def operand index '") +
967 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
968 " isn't a defined register");
970 for (
const auto &TiedPair : TiedRegisterPairs) {
971 if (TiedPair.first == DefIdx)
972 return error(Operands[
I].Begin,
973 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
974 " is already tied with another register operand");
976 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
980 for (
const auto &TiedPair : TiedRegisterPairs)
989 while (
Token.isRegisterFlag()) {
990 if (parseRegisterFlag(Flags))
993 if (!
Token.isRegister())
994 return error(
"expected a register after register flags");
997 if (parseRegister(Reg, RegInfo))
1000 unsigned SubReg = 0;
1002 if (parseSubRegisterIndex(SubReg))
1005 return error(
"subregister index expects a virtual register");
1011 if (!parseRegisterTiedDefIndex(Idx))
1016 if (parseLowLevelType(
Token.location(), Ty))
1017 return error(
"expected tied-def or low-level type after '('");
1023 return error(
"inconsistent type for generic virtual register");
1031 return error(
"unexpected type on physical register");
1034 if (parseLowLevelType(
Token.location(), Ty))
1041 return error(
"inconsistent type for generic virtual register");
1050 return error(
"generic virtual registers must have a type");
1063 if (Int.getMinSignedBits() > 64)
1064 return error(
"integer literal is too large to be an immediate operand");
1082 if (parseIRConstant(Loc,
StringRef(Loc,
Token.range().end() - Loc), C))
1094 const DataLayout &
DL = MF.getFunction()->getParent()->getDataLayout();
1095 unsigned AS =
APSInt(
Token.range().drop_front()).getZExtValue();
1104 "expected unsized, pN, sN or <N x sM> for GlobalISel type");
1109 return error(Loc,
"expected <N x sM> for vctor type");
1110 uint64_t NumElements =
Token.integerValue().getZExtValue();
1114 return error(Loc,
"expected '<N x sM>' for vector type");
1118 return error(Loc,
"expected '<N x sM>' for vector type");
1119 uint64_t ScalarSize =
APSInt(
Token.range().drop_front()).getZExtValue();
1123 return error(Loc,
"expected '<N x sM>' for vector type");
1130 bool MIParser::parseTypedImmediateOperand(
MachineOperand &Dest) {
1132 auto Loc =
Token.location();
1135 return error(
"expected an integer literal");
1137 if (parseIRConstant(Loc, C))
1144 auto Loc =
Token.location();
1148 return error(
"expected a floating point literal");
1150 if (parseIRConstant(Loc, C))
1156 bool MIParser::getUnsigned(
unsigned &Result) {
1157 if (
Token.hasIntegerValue()) {
1158 const uint64_t Limit = uint64_t(std::numeric_limits<unsigned>::max()) + 1;
1159 uint64_t Val64 =
Token.integerValue().getLimitedValue(Limit);
1161 return error(
"expected 32-bit integer (too large)");
1170 return error(
"expected 32-bit integer (too large)");
1181 if (getUnsigned(Number))
1183 auto MBBInfo = PFS.MBBSlots.find(Number);
1184 if (MBBInfo == PFS.MBBSlots.end())
1185 return error(
Twine(
"use of undefined machine basic block #") +
1187 MBB = MBBInfo->second;
1189 return error(
Twine(
"the name of machine basic block #") +
Twine(Number) +
1190 " isn't '" +
Token.stringValue() +
"'");
1203 bool MIParser::parseStackFrameIndex(
int &FI) {
1206 if (getUnsigned(ID))
1208 auto ObjectInfo = PFS.StackObjectSlots.find(ID);
1209 if (ObjectInfo == PFS.StackObjectSlots.end())
1210 return error(
Twine(
"use of undefined stack object '%stack.") +
Twine(ID) +
1213 if (
const auto *Alloca =
1214 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
1215 Name = Alloca->getName();
1217 return error(
Twine(
"the name of the stack object '%stack.") +
Twine(ID) +
1218 "' isn't '" +
Token.stringValue() +
"'");
1220 FI = ObjectInfo->second;
1226 if (parseStackFrameIndex(FI))
1232 bool MIParser::parseFixedStackFrameIndex(
int &FI) {
1235 if (getUnsigned(ID))
1237 auto ObjectInfo = PFS.FixedStackObjectSlots.find(ID);
1238 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
1239 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
1242 FI = ObjectInfo->second;
1246 bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
1248 if (parseFixedStackFrameIndex(FI))
1254 bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
1255 switch (
Token.kind()) {
1260 return error(
Twine(
"use of undefined global value '") +
Token.range() +
1266 if (getUnsigned(GVIdx))
1268 if (GVIdx >= PFS.IRSlots.GlobalValues.size())
1269 return error(
Twine(
"use of undefined global value '@") +
Twine(GVIdx) +
1271 GV = PFS.IRSlots.GlobalValues[GVIdx];
1282 if (parseGlobalValue(GV))
1286 if (parseOperandsOffset(Dest))
1291 bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
1294 if (getUnsigned(ID))
1298 return error(
"use of undefined constant '%const." +
Twine(ID) +
"'");
1301 if (parseOperandsOffset(Dest))
1306 bool MIParser::parseJumpTableIndexOperand(
MachineOperand &Dest) {
1309 if (getUnsigned(ID))
1311 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(ID);
1312 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
1313 return error(
"use of undefined jump table '%jump-table." +
Twine(ID) +
"'");
1319 bool MIParser::parseExternalSymbolOperand(
MachineOperand &Dest) {
1321 const char *
Symbol = MF.createExternalSymbolName(
Token.stringValue());
1324 if (parseOperandsOffset(Dest))
1329 bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
1332 unsigned SubRegIndex = getSubRegIndex(
Token.stringValue());
1333 if (SubRegIndex == 0)
1334 return error(
Twine(
"unknown subregister index '") + Name +
"'");
1342 auto Loc =
Token.location();
1345 return error(
"expected metadata id after '!'");
1347 if (getUnsigned(ID))
1349 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(ID);
1350 if (NodeInfo == PFS.IRSlots.MetadataNodes.end())
1351 return error(Loc,
"use of undefined metadata '!" +
Twine(ID) +
"'");
1353 Node = NodeInfo->second.
get();
1365 bool MIParser::parseCFIOffset(
int &
Offset) {
1367 return error(
"expected a cfi offset");
1368 if (
Token.integerValue().getMinSignedBits() > 32)
1369 return error(
"expected a 32 bit integer (the cfi offset is too large)");
1370 Offset = (int)
Token.integerValue().getExtValue();
1375 bool MIParser::parseCFIRegister(
unsigned &Reg) {
1377 return error(
"expected a cfi register");
1379 if (parseNamedRegister(LLVMReg))
1381 const auto *TRI = MF.getSubtarget().getRegisterInfo();
1382 assert(TRI &&
"Expected target register info");
1383 int DwarfReg = TRI->getDwarfRegNum(LLVMReg,
true);
1385 return error(
"invalid DWARF register");
1399 if (parseCFIRegister(Reg))
1405 parseCFIOffset(Offset))
1411 if (parseCFIRegister(Reg))
1417 if (parseCFIOffset(Offset))
1420 CFIIndex = MF.addFrameInst(
1425 parseCFIOffset(Offset))
1440 switch (
Token.kind()) {
1442 BB = dyn_cast_or_null<BasicBlock>(
1445 return error(
Twine(
"use of undefined IR block '") +
Token.range() +
"'");
1449 unsigned SlotNumber = 0;
1450 if (getUnsigned(SlotNumber))
1452 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber, F));
1454 return error(
Twine(
"use of undefined IR block '%ir-block.") +
1455 Twine(SlotNumber) +
"'");
1471 return error(
"expected a global value");
1473 if (parseGlobalValue(GV))
1477 return error(
"expected an IR function reference");
1483 return error(
"expected an IR block reference");
1484 if (parseIRBlock(BB, *F))
1490 if (parseOperandsOffset(Dest))
1499 return error(
"expected syntax intrinsic(@llvm.whatever)");
1502 return error(
"expected syntax intrinsic(@llvm.whatever)");
1504 std::string Name =
Token.stringValue();
1508 return error(
"expected ')' to terminate intrinsic name");
1518 return error(
"unknown intrinsic name");
1530 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
1533 return error(
"whatever");
1556 return error(
"invalid floating-point predicate");
1571 return error(
"invalid integer predicate");
1577 return error(
"predicate should be terminated by ')'.");
1588 return error(
"expected the name of the target index");
1590 if (getTargetIndex(
Token.stringValue(), Index))
1591 return error(
"use of undefined target index '" +
Token.stringValue() +
"'");
1596 if (parseOperandsOffset(Dest))
1601 bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
1603 const auto *TRI = MF.getSubtarget().getRegisterInfo();
1604 assert(TRI &&
"Expected target register info");
1605 uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
1611 return error(
"expected a named register");
1613 if (parseNamedRegister(Reg))
1616 Mask[Reg / 32] |= 1U << (Reg % 32);
1630 switch (
Token.kind()) {
1643 return parseRegisterOperand(Dest, TiedDefIdx);
1645 return parseImmediateOperand(Dest);
1647 return parseTypedImmediateOperand(Dest);
1654 return parseFPImmediateOperand(Dest);
1656 return parseMBBOperand(Dest);
1658 return parseStackObjectOperand(Dest);
1660 return parseFixedStackObjectOperand(Dest);
1663 return parseGlobalAddressOperand(Dest);
1665 return parseConstantPoolIndexOperand(Dest);
1667 return parseJumpTableIndexOperand(Dest);
1669 return parseExternalSymbolOperand(Dest);
1671 return parseSubRegisterIndexOperand(Dest);
1673 return parseMetadataOperand(Dest);
1679 return parseCFIOperand(Dest);
1681 return parseBlockAddressOperand(Dest);
1683 return parseIntrinsicOperand(Dest);
1685 return parseTargetIndexOperand(Dest);
1687 return parseLiveoutRegisterMaskOperand(Dest);
1690 return parsePredicateOperand(Dest);
1694 if (
const auto *RegMask = getRegMask(
Token.stringValue())) {
1702 return error(
"expected a machine operand");
1707 bool MIParser::parseMachineOperandAndTargetFlags(
1710 bool HasTargetFlags =
false;
1712 HasTargetFlags =
true;
1717 return error(
"expected the name of the target flag");
1718 if (getDirectTargetFlag(
Token.stringValue(), TF)) {
1719 if (getBitmaskTargetFlag(
Token.stringValue(), TF))
1720 return error(
"use of undefined target flag '" +
Token.stringValue() +
1727 return error(
"expected the name of the target flag");
1728 unsigned BitFlag = 0;
1729 if (getBitmaskTargetFlag(
Token.stringValue(), BitFlag))
1730 return error(
"use of undefined target flag '" +
Token.stringValue() +
1739 auto Loc =
Token.location();
1740 if (parseMachineOperand(Dest, TiedDefIdx))
1742 if (!HasTargetFlags)
1745 return error(Loc,
"register operands can't have target flags");
1750 bool MIParser::parseOffset(int64_t &Offset) {
1757 return error(
"expected an integer literal after '" + Sign +
"'");
1758 if (
Token.integerValue().getMinSignedBits() > 64)
1759 return error(
"expected 64-bit integer (too large)");
1760 Offset =
Token.integerValue().getExtValue();
1767 bool MIParser::parseAlignment(
unsigned &Alignment) {
1771 return error(
"expected an integer literal after 'align'");
1772 if (getUnsigned(Alignment))
1780 if (parseOffset(Offset))
1786 bool MIParser::parseIRValue(
const Value *&V) {
1787 switch (
Token.kind()) {
1789 V = MF.getFunction()->getValueSymbolTable()->lookup(
Token.stringValue());
1793 unsigned SlotNumber = 0;
1794 if (getUnsigned(SlotNumber))
1796 V = getIRValue(SlotNumber);
1802 if (parseGlobalValue(GV))
1809 if (parseIRConstant(
Token.location(),
Token.stringValue(),
C))
1818 return error(
Twine(
"use of undefined IR value '") +
Token.range() +
"'");
1822 bool MIParser::getUint64(uint64_t &Result) {
1823 if (
Token.hasIntegerValue()) {
1824 if (
Token.integerValue().getActiveBits() > 64)
1825 return error(
"expected 64-bit integer (too large)");
1826 Result =
Token.integerValue().getZExtValue();
1834 return error(
"expected 64-bit integer (too large)");
1841 bool MIParser::getHexUint(
APInt &Result) {
1844 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
1846 if (!isxdigit(S[2]))
1856 const auto OldFlags =
Flags;
1857 switch (
Token.kind()) {
1874 if (OldFlags == Flags)
1877 return error(
"duplicate '" +
Token.stringValue() +
"' memory operand flag");
1883 switch (
Token.kind()) {
1885 PSV = MF.getPSVManager().getStack();
1888 PSV = MF.getPSVManager().getGOT();
1891 PSV = MF.getPSVManager().getJumpTable();
1894 PSV = MF.getPSVManager().getConstantPool();
1898 if (parseFixedStackFrameIndex(FI))
1900 PSV = MF.getPSVManager().getFixedStack(FI);
1906 if (parseStackFrameIndex(FI))
1908 PSV = MF.getPSVManager().getFixedStack(FI);
1914 switch (
Token.kind()) {
1918 if (parseGlobalValue(GV))
1920 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
1924 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
1925 MF.createExternalSymbolName(
Token.stringValue()));
1929 "expected a global value or an external symbol after 'call-entry'");
1946 if (parseMemoryPseudoSourceValue(PSV))
1949 if (parseOffset(Offset))
1958 return error(
"expected an IR value reference");
1959 const Value *V =
nullptr;
1960 if (parseIRValue(V))
1963 return error(
"expected a pointer IR value");
1966 if (parseOffset(Offset))
1976 while (
Token.isMemoryOperandFlag()) {
1977 if (parseMemoryOperandFlag(Flags))
1981 (
Token.stringValue() !=
"load" &&
Token.stringValue() !=
"store"))
1982 return error(
"expected 'load' or 'store' memory operation");
1983 if (
Token.stringValue() ==
"load")
1990 return error(
"expected the size integer literal after memory operation");
1992 if (getUint64(Size))
2000 return error(
Twine(
"expected '") + Word +
"'");
2003 if (parseMachinePointerInfo(Ptr))
2006 unsigned BaseAlignment = Size;
2010 switch (
Token.kind()) {
2012 if (parseAlignment(BaseAlignment))
2037 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
2038 "'!noalias' or '!range'");
2044 MF.getMachineMemOperand(Ptr, Flags, Size, BaseAlignment, AAInfo, Range);
2048 void MIParser::initNames2InstrOpCodes() {
2049 if (!Names2InstrOpCodes.empty())
2051 const auto *TII = MF.getSubtarget().getInstrInfo();
2052 assert(TII &&
"Expected target instruction info");
2053 for (
unsigned I = 0,
E = TII->getNumOpcodes();
I <
E; ++
I)
2057 bool MIParser::parseInstrName(
StringRef InstrName,
unsigned &OpCode) {
2058 initNames2InstrOpCodes();
2059 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
2060 if (InstrInfo == Names2InstrOpCodes.end())
2062 OpCode = InstrInfo->getValue();
2066 void MIParser::initNames2Regs() {
2067 if (!Names2Regs.empty())
2070 Names2Regs.insert(std::make_pair(
"noreg", 0));
2071 const auto *TRI = MF.getSubtarget().getRegisterInfo();
2072 assert(TRI &&
"Expected target register info");
2073 for (
unsigned I = 0, E = TRI->getNumRegs();
I <
E; ++
I) {
2075 Names2Regs.insert(std::make_pair(
StringRef(TRI->getName(
I)).lower(),
I))
2078 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
2082 bool MIParser::getRegisterByName(
StringRef RegName,
unsigned &Reg) {
2084 auto RegInfo = Names2Regs.find(RegName);
2085 if (RegInfo == Names2Regs.end())
2087 Reg = RegInfo->getValue();
2091 void MIParser::initNames2RegMasks() {
2092 if (!Names2RegMasks.empty())
2094 const auto *TRI = MF.getSubtarget().getRegisterInfo();
2095 assert(TRI &&
"Expected target register info");
2099 for (
size_t I = 0, E = RegMasks.
size();
I <
E; ++
I)
2100 Names2RegMasks.insert(
2101 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[I]));
2105 initNames2RegMasks();
2106 auto RegMaskInfo = Names2RegMasks.find(Identifier);
2107 if (RegMaskInfo == Names2RegMasks.end())
2109 return RegMaskInfo->getValue();
2112 void MIParser::initNames2SubRegIndices() {
2113 if (!Names2SubRegIndices.empty())
2117 Names2SubRegIndices.insert(
2121 unsigned MIParser::getSubRegIndex(
StringRef Name) {
2122 initNames2SubRegIndices();
2123 auto SubRegInfo = Names2SubRegIndices.find(Name);
2124 if (SubRegInfo == Names2SubRegIndices.end())
2126 return SubRegInfo->getValue();
2134 for (
auto &BB : F) {
2137 int Slot = MST.getLocalSlot(&BB);
2140 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
2147 auto BlockInfo = Slots2BasicBlocks.
find(Slot);
2148 if (BlockInfo == Slots2BasicBlocks.
end())
2150 return BlockInfo->second;
2153 const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
2154 if (Slots2BasicBlocks.empty())
2160 if (&F == MF.getFunction())
2161 return getIRBlock(Slot);
2172 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
2180 for (
const auto &Arg : F.
args())
2182 for (
const auto &BB : F) {
2184 for (
const auto &I : BB)
2189 const Value *MIParser::getIRValue(
unsigned Slot) {
2190 if (Slots2Values.empty())
2192 auto ValueInfo = Slots2Values.find(Slot);
2198 void MIParser::initNames2TargetIndices() {
2199 if (!Names2TargetIndices.empty())
2201 const auto *TII = MF.getSubtarget().getInstrInfo();
2202 assert(TII &&
"Expected target instruction info");
2203 auto Indices = TII->getSerializableTargetIndices();
2204 for (
const auto &I : Indices)
2205 Names2TargetIndices.insert(std::make_pair(
StringRef(I.second), I.first));
2208 bool MIParser::getTargetIndex(
StringRef Name,
int &Index) {
2209 initNames2TargetIndices();
2210 auto IndexInfo = Names2TargetIndices.find(Name);
2211 if (IndexInfo == Names2TargetIndices.end())
2213 Index = IndexInfo->second;
2217 void MIParser::initNames2DirectTargetFlags() {
2218 if (!Names2DirectTargetFlags.empty())
2220 const auto *TII = MF.getSubtarget().getInstrInfo();
2221 assert(TII &&
"Expected target instruction info");
2222 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
2223 for (
const auto &I : Flags)
2224 Names2DirectTargetFlags.insert(
2225 std::make_pair(
StringRef(I.second), I.first));
2228 bool MIParser::getDirectTargetFlag(
StringRef Name,
unsigned &
Flag) {
2229 initNames2DirectTargetFlags();
2230 auto FlagInfo = Names2DirectTargetFlags.find(Name);
2231 if (FlagInfo == Names2DirectTargetFlags.end())
2233 Flag = FlagInfo->second;
2237 void MIParser::initNames2BitmaskTargetFlags() {
2238 if (!Names2BitmaskTargetFlags.empty())
2240 const auto *TII = MF.getSubtarget().getInstrInfo();
2241 assert(TII &&
"Expected target instruction info");
2242 auto Flags = TII->getSerializableBitmaskMachineOperandTargetFlags();
2243 for (
const auto &I : Flags)
2244 Names2BitmaskTargetFlags.insert(
2245 std::make_pair(
StringRef(I.second), I.first));
2248 bool MIParser::getBitmaskTargetFlag(
StringRef Name,
unsigned &Flag) {
2249 initNames2BitmaskTargetFlags();
2250 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
2251 if (FlagInfo == Names2BitmaskTargetFlags.end())
2253 Flag = FlagInfo->second;
2260 return MIParser(PFS, Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
2265 return MIParser(PFS, Error, Src).parseBasicBlocks();
2271 return MIParser(PFS, Error, Src).parseStandaloneMBB(MBB);
2277 return MIParser(PFS, Error, Src).parseStandaloneRegister(Reg);
2283 return MIParser(PFS, Error, Src).parseStandaloneNamedRegister(Reg);
2289 return MIParser(PFS, Error, Src).parseStandaloneVirtualRegister(Info);
2295 return MIParser(PFS, Error, Src).parseStandaloneStackObject(FI);
2300 return MIParser(PFS, Error, Src).parseStandaloneMDNode(Node);
void push_back(const T &Elt)
A parsed version of the target data layout string in and methods for querying it. ...
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
static MachineOperand CreateCImm(const ConstantInt *CI)
uint64_t getZExtValue() const
Get zero extended value.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
MDNode * Scope
The tag for alias scope specification (used with noalias).
const char * getBufferStart() const
MDNode * TBAA
The tag for type-based alias analysis.
Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
void setTargetFlags(unsigned F)
A Module instance is used to store all the information related to an LLVM module. ...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
static BranchProbability getRaw(uint32_t N)
static LaneBitmask getAll()
static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags=0)
Describe properties that are true of each instruction in the target description file.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
0 1 0 0 True if ordered and less than
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
1 1 1 0 True if unordered or not equal
DenseMap< unsigned, VRegInfo * > VRegInfos
Manage lifetime of a slot tracker for printing IR.
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
void setAlignment(unsigned Align)
Set alignment of the basic block.
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
1 0 0 1 True if unordered or equal
unsigned getMainFileID() const
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
std::string str() const
Return the twine contents as a std::string.
A description of a memory reference used in the backend.
std::string toString(Error E)
Write all error messages (if any) in E to a string.
struct fuzzer::@269 Flags
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const HexagonInstrInfo * TII
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isCall() const
Return true if the instruction is a call.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Reg
All possible values of the reg field in the ModR/M byte.
0 1 0 1 True if ordered and less than or equal
The memory access is dereferenceable (i.e., doesn't trap).
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
LLVM_NODISCARD bool empty() const
static std::string getRegisterName(const TargetRegisterInfo *TRI, unsigned Reg)
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
StringRef getMessage() const
virtual unsigned lookupName(const char *Name, unsigned Len) const =0
Look up target intrinsic by name.
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned getActiveBits() const
Compute the number of active bits in the value.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
static MachineOperand CreatePredicate(unsigned Pred)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
size_t size() const
size - Get the array size.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
VRegInfo & getVRegInfo(unsigned VReg)
The memory access is volatile.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register)
.cfi_same_value Current value of Register is the same as in the previous frame.
A switch()-like statement whose cases are string literals.
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
static Intrinsic::ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned char TargetFlags=0)
LLVM Basic Block Representation.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
static BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static MachineOperand CreateFPImm(const ConstantFP *CFP)
This is an important base class in LLVM.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
This file contains the declarations for the subclasses of Constant, which represent the different fla...
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots)
const MCPhysReg * ImplicitDefs
bool isIntPredicate() const
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
BumpPtrAllocator Allocator
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned char TargetFlags=0)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg, StringRef Src, SMDiagnostic &Error)
void setFlag(MIFlag Flag)
Set a MI flag.
unsigned createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
unsigned getBitWidth() const
Return the number of bits in the APInt.
static const unsigned End
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned char TargetFlags=0)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned char TargetFlags=0)
0 1 1 1 True if ordered (no nans)
The memory access is non-temporal.
bool empty() const
empty - Check if the array is empty.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling...
void setOffset(int64_t Offset)
1 1 1 1 Always true (always folded)
void incorporateFunction(const Function &F)
Incorporate the given function.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
bool isPointerTy() const
True if this is an instance of PointerType.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class contains a discriminated union of information about pointers in memory operands...
1 1 0 1 True if unordered, less than, or equal
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const T & back() const
back - Get the last element.
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
TargetIntrinsicInfo - Interface to description of machine instruction set.
Struct to hold value either by GUID or GlobalValue*.
The memory access writes data.
0 0 1 0 True if ordered and greater than
static MachineOperand CreateMetadata(const MDNode *Meta)
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
void setFlags(unsigned flags)
enum llvm::VRegInfo::uint8_t Kind
MachineOperand class - Representation of each machine instruction operand.
1 1 0 0 True if unordered or less than
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAlias
The tag specifying the noalias scope.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
This interface provides simple read-only access to a block of memory, and provides simple methods for...
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or "(null)".
Class for arbitrary precision integers.
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
Special value supplied for machine level alias analysis.
static MachineOperand CreateES(const char *SymName, unsigned char TargetFlags=0)
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
This struct contains the mappings from the slot numbers to unnamed metadata nodes, global values and types.
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool isFPPredicate() const
static SMLoc getFromPointer(const char *Ptr)
Flags
Flags values. These may be or'd together.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
const MemoryBuffer * getMemoryBuffer(unsigned i) const
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned greater or equal
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
The memory access always returns the same value (or traps).
0 1 1 0 True if ordered and operands are unequal
iterator find(const KeyT &Val)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
1 0 1 0 True if unordered or greater than
const char * getBufferEnd() const
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
0 0 0 1 True if ordered and equal
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
static LLT pointer(uint16_t AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space (defaulting to 0).
A token produced by the machine instruction lexer.
1 0 1 1 True if unordered, greater than, or equal
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Lightweight error class with error context and mandatory checking.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
StringRef - Represent a constant reference to a string, i.e.
SMDiagnostic GetMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg, ArrayRef< SMRange > Ranges=None, ArrayRef< SMFixIt > FixIts=None) const
Return an SMDiagnostic at the specified location with the specified string.
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
Represents a location in source code.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg, StringRef Src, SMDiagnostic &Error)
0 0 1 1 True if ordered and greater than or equal
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
static MachineOperand CreateFI(int Idx)
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
iterator_range< arg_iterator > args()
0 0 0 0 Always false (always folded)
const MCPhysReg * ImplicitUses
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
unsigned getNumWords() const
Get the number of words.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.