LLVM  4.0.0
SystemZDisassembler.cpp
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1 //===-- SystemZDisassembler.cpp - Disassembler for SystemZ ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "SystemZ.h"
13 #include "llvm/MC/MCInst.h"
16 
17 using namespace llvm;
18 
19 #define DEBUG_TYPE "systemz-disassembler"
20 
22 
23 namespace {
24 class SystemZDisassembler : public MCDisassembler {
25 public:
26  SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
27  : MCDisassembler(STI, Ctx) {}
28  ~SystemZDisassembler() override {}
29 
30  DecodeStatus getInstruction(MCInst &instr, uint64_t &Size,
31  ArrayRef<uint8_t> Bytes, uint64_t Address,
32  raw_ostream &VStream,
33  raw_ostream &CStream) const override;
34 };
35 } // end anonymous namespace
36 
38  const MCSubtargetInfo &STI,
39  MCContext &Ctx) {
40  return new SystemZDisassembler(STI, Ctx);
41 }
42 
44  // Register the disassembler.
47 }
48 
49 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
50 /// immediate Value in the MCInst.
51 ///
52 /// @param Value - The immediate Value, has had any PC adjustment made by
53 /// the caller.
54 /// @param isBranch - If the instruction is a branch instruction
55 /// @param Address - The starting address of the instruction
56 /// @param Offset - The byte offset to this immediate in the instruction
57 /// @param Width - The byte width of this immediate in the instruction
58 ///
59 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
60 /// called then that function is called to get any symbolic information for the
61 /// immediate in the instruction using the Address, Offset and Width. If that
62 /// returns non-zero then the symbolic information it returns is used to create
63 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
64 /// returns zero and isBranch is true then a symbol look up for immediate Value
65 /// is done and if a symbol is found an MCExpr is created with that, else
66 /// an MCExpr with the immediate Value is created. This function returns true
67 /// if it adds an operand to the MCInst and false otherwise.
68 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
69  uint64_t Address, uint64_t Offset,
70  uint64_t Width, MCInst &MI,
71  const void *Decoder) {
72  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
73  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
74  Offset, Width);
75 }
76 
77 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
78  const unsigned *Regs, unsigned Size) {
79  assert(RegNo < Size && "Invalid register");
80  RegNo = Regs[RegNo];
81  if (RegNo == 0)
82  return MCDisassembler::Fail;
83  Inst.addOperand(MCOperand::createReg(RegNo));
85 }
86 
87 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
88  uint64_t Address,
89  const void *Decoder) {
90  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
91 }
92 
93 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
94  uint64_t Address,
95  const void *Decoder) {
96  return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
97 }
98 
99 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
100  uint64_t Address,
101  const void *Decoder) {
102  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
103 }
104 
105 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
106  uint64_t Address,
107  const void *Decoder) {
108  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16);
109 }
110 
111 static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
112  uint64_t Address,
113  const void *Decoder) {
114  return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
115 }
116 
117 static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
118  uint64_t Address,
119  const void *Decoder) {
120  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP32Regs, 16);
121 }
122 
123 static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
124  uint64_t Address,
125  const void *Decoder) {
126  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP64Regs, 16);
127 }
128 
129 static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
130  uint64_t Address,
131  const void *Decoder) {
132  return decodeRegisterClass(Inst, RegNo, SystemZMC::FP128Regs, 16);
133 }
134 
135 static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
136  uint64_t Address,
137  const void *Decoder) {
138  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR32Regs, 32);
139 }
140 
141 static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
142  uint64_t Address,
143  const void *Decoder) {
144  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR64Regs, 32);
145 }
146 
147 static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
148  uint64_t Address,
149  const void *Decoder) {
150  return decodeRegisterClass(Inst, RegNo, SystemZMC::VR128Regs, 32);
151 }
152 
153 static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
154  uint64_t Address,
155  const void *Decoder) {
156  return decodeRegisterClass(Inst, RegNo, SystemZMC::AR32Regs, 16);
157 }
158 
159 template<unsigned N>
160 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
161  if (!isUInt<N>(Imm))
162  return MCDisassembler::Fail;
163  Inst.addOperand(MCOperand::createImm(Imm));
165 }
166 
167 template<unsigned N>
168 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
169  if (!isUInt<N>(Imm))
170  return MCDisassembler::Fail;
171  Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
173 }
174 
175 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
176  uint64_t Address, const void *Decoder) {
177  return decodeUImmOperand<1>(Inst, Imm);
178 }
179 
180 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm,
181  uint64_t Address, const void *Decoder) {
182  return decodeUImmOperand<2>(Inst, Imm);
183 }
184 
185 static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm,
186  uint64_t Address, const void *Decoder) {
187  return decodeUImmOperand<3>(Inst, Imm);
188 }
189 
190 static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm,
191  uint64_t Address, const void *Decoder) {
192  return decodeUImmOperand<4>(Inst, Imm);
193 }
194 
195 static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm,
196  uint64_t Address, const void *Decoder) {
197  return decodeUImmOperand<6>(Inst, Imm);
198 }
199 
200 static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm,
201  uint64_t Address, const void *Decoder) {
202  return decodeUImmOperand<8>(Inst, Imm);
203 }
204 
205 static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm,
206  uint64_t Address, const void *Decoder) {
207  return decodeUImmOperand<12>(Inst, Imm);
208 }
209 
210 static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm,
211  uint64_t Address, const void *Decoder) {
212  return decodeUImmOperand<16>(Inst, Imm);
213 }
214 
215 static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm,
216  uint64_t Address, const void *Decoder) {
217  return decodeUImmOperand<32>(Inst, Imm);
218 }
219 
220 static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm,
221  uint64_t Address, const void *Decoder) {
222  return decodeSImmOperand<8>(Inst, Imm);
223 }
224 
225 static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm,
226  uint64_t Address, const void *Decoder) {
227  return decodeSImmOperand<16>(Inst, Imm);
228 }
229 
230 static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm,
231  uint64_t Address, const void *Decoder) {
232  return decodeSImmOperand<32>(Inst, Imm);
233 }
234 
235 template<unsigned N>
236 static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm,
237  uint64_t Address,
238  bool isBranch,
239  const void *Decoder) {
240  assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
241  uint64_t Value = SignExtend64<N>(Imm) * 2 + Address;
242 
243  if (!tryAddingSymbolicOperand(Value, isBranch, Address, 2, N / 8,
244  Inst, Decoder))
245  Inst.addOperand(MCOperand::createImm(Value));
246 
248 }
249 
250 static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm,
251  uint64_t Address,
252  const void *Decoder) {
253  return decodePCDBLOperand<12>(Inst, Imm, Address, true, Decoder);
254 }
255 
256 static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm,
257  uint64_t Address,
258  const void *Decoder) {
259  return decodePCDBLOperand<16>(Inst, Imm, Address, true, Decoder);
260 }
261 
262 static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm,
263  uint64_t Address,
264  const void *Decoder) {
265  return decodePCDBLOperand<24>(Inst, Imm, Address, true, Decoder);
266 }
267 
268 static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm,
269  uint64_t Address,
270  const void *Decoder) {
271  return decodePCDBLOperand<32>(Inst, Imm, Address, true, Decoder);
272 }
273 
274 static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm,
275  uint64_t Address,
276  const void *Decoder) {
277  return decodePCDBLOperand<32>(Inst, Imm, Address, false, Decoder);
278 }
279 
281  const unsigned *Regs) {
282  uint64_t Base = Field >> 12;
283  uint64_t Disp = Field & 0xfff;
284  assert(Base < 16 && "Invalid BDAddr12");
285  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
286  Inst.addOperand(MCOperand::createImm(Disp));
288 }
289 
291  const unsigned *Regs) {
292  uint64_t Base = Field >> 20;
293  uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
294  assert(Base < 16 && "Invalid BDAddr20");
295  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
296  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
298 }
299 
301  const unsigned *Regs) {
302  uint64_t Index = Field >> 16;
303  uint64_t Base = (Field >> 12) & 0xf;
304  uint64_t Disp = Field & 0xfff;
305  assert(Index < 16 && "Invalid BDXAddr12");
306  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
307  Inst.addOperand(MCOperand::createImm(Disp));
308  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
310 }
311 
313  const unsigned *Regs) {
314  uint64_t Index = Field >> 24;
315  uint64_t Base = (Field >> 20) & 0xf;
316  uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
317  assert(Index < 16 && "Invalid BDXAddr20");
318  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
319  Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
320  Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index]));
322 }
323 
325  const unsigned *Regs) {
326  uint64_t Length = Field >> 16;
327  uint64_t Base = (Field >> 12) & 0xf;
328  uint64_t Disp = Field & 0xfff;
329  assert(Length < 256 && "Invalid BDLAddr12Len8");
330  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
331  Inst.addOperand(MCOperand::createImm(Disp));
332  Inst.addOperand(MCOperand::createImm(Length + 1));
334 }
335 
337  const unsigned *Regs) {
338  uint64_t Length = Field >> 16;
339  uint64_t Base = (Field >> 12) & 0xf;
340  uint64_t Disp = Field & 0xfff;
341  assert(Length < 16 && "Invalid BDRAddr12");
342  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
343  Inst.addOperand(MCOperand::createImm(Disp));
344  Inst.addOperand(MCOperand::createReg(Regs[Length]));
346 }
347 
349  const unsigned *Regs) {
350  uint64_t Index = Field >> 16;
351  uint64_t Base = (Field >> 12) & 0xf;
352  uint64_t Disp = Field & 0xfff;
353  assert(Index < 32 && "Invalid BDVAddr12");
354  Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
355  Inst.addOperand(MCOperand::createImm(Disp));
358 }
359 
361  uint64_t Address,
362  const void *Decoder) {
363  return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR32Regs);
364 }
365 
367  uint64_t Address,
368  const void *Decoder) {
369  return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR32Regs);
370 }
371 
373  uint64_t Address,
374  const void *Decoder) {
375  return decodeBDAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
376 }
377 
379  uint64_t Address,
380  const void *Decoder) {
381  return decodeBDAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
382 }
383 
385  uint64_t Address,
386  const void *Decoder) {
387  return decodeBDXAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
388 }
389 
391  uint64_t Address,
392  const void *Decoder) {
393  return decodeBDXAddr20Operand(Inst, Field, SystemZMC::GR64Regs);
394 }
395 
397  uint64_t Field,
398  uint64_t Address,
399  const void *Decoder) {
400  return decodeBDLAddr12Len8Operand(Inst, Field, SystemZMC::GR64Regs);
401 }
402 
404  uint64_t Field,
405  uint64_t Address,
406  const void *Decoder) {
407  return decodeBDRAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
408 }
409 
411  uint64_t Address,
412  const void *Decoder) {
413  return decodeBDVAddr12Operand(Inst, Field, SystemZMC::GR64Regs);
414 }
415 
416 #include "SystemZGenDisassemblerTables.inc"
417 
418 DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
419  ArrayRef<uint8_t> Bytes,
420  uint64_t Address,
421  raw_ostream &OS,
422  raw_ostream &CS) const {
423  // Get the first two bytes of the instruction.
424  Size = 0;
425  if (Bytes.size() < 2)
426  return MCDisassembler::Fail;
427 
428  // The top 2 bits of the first byte specify the size.
429  const uint8_t *Table;
430  if (Bytes[0] < 0x40) {
431  Size = 2;
432  Table = DecoderTable16;
433  } else if (Bytes[0] < 0xc0) {
434  Size = 4;
435  Table = DecoderTable32;
436  } else {
437  Size = 6;
438  Table = DecoderTable48;
439  }
440 
441  // Read any remaining bytes.
442  if (Bytes.size() < Size)
443  return MCDisassembler::Fail;
444 
445  // Construct the instruction.
446  uint64_t Inst = 0;
447  for (uint64_t I = 0; I < Size; ++I)
448  Inst = (Inst << 8) | Bytes[I];
449 
450  return decodeInstruction(Table, MI, Inst, Address, this, STI);
451 }
static DecodeStatus decodeBDAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
const unsigned GR32Regs[16]
static DecodeStatus decodePCDBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, bool isBranch, const void *Decoder)
const unsigned FP128Regs[16]
static DecodeStatus decodeBDAddr32Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static DecodeStatus decodeBDAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
Superclass for all disassemblers.
static DecodeStatus decodePC32DBLOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodePC16DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDXAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
static DecodeStatus DecodeADDR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
const unsigned FP32Regs[16]
static DecodeStatus DecodeFP32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDVAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDVAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFP128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
const unsigned VR64Regs[32]
static DecodeStatus decodeS32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
static DecodeStatus decodeU6ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
const unsigned AR32Regs[16]
static DecodeStatus decodeBDXAddr20Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
const unsigned GRH32Regs[16]
static MCDisassembler * createSystemZDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Context object for machine code objects.
Definition: MCContext.h:51
static DecodeStatus decodeU16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
const RegList & Regs
static DecodeStatus decodeBDAddr32Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static DecodeStatus decodeBDXAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus decodePC12DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeS8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDLAddr12Len8Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeU32ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
uint32_t Offset
static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm)
static DecodeStatus decodeBDXAddr64Disp20Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeS16ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus decodeBDRAddr12Operand(MCInst &Inst, uint64_t Field, const unsigned *Regs)
static DecodeStatus decodeBDLAddr64Disp12Len8Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
const unsigned FP64Regs[16]
const unsigned GR128Regs[16]
const unsigned GR64Regs[16]
static DecodeStatus decodeU8ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
Target - Wrapper for Target specific information.
static DecodeStatus decodeU12ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
Target & getTheSystemZTarget()
static DecodeStatus decodeU4ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm)
const unsigned VR32Regs[32]
static DecodeStatus decodeU3ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
void LLVMInitializeSystemZDisassembler()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
static DecodeStatus DecodeVR128BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
LLVM Value Representation.
Definition: Value.h:71
static DecodeStatus decodePC24DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeFP64BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size)
static DecodeStatus decodePC32DBLBranchOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
const unsigned VR128Regs[32]
static DecodeStatus decodeBDRAddr64Disp12Operand(MCInst &Inst, uint64_t Field, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVR32BitRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder)