30 #define DEBUG_TYPE "mlx-expansion"
37 STATISTIC(NumExpand,
"Number of fp MLA / MLS instructions expanded");
47 return "ARM MLA / MLS expansion pass";
69 unsigned MulOpc,
unsigned AddSubOpc,
70 bool NegAcc,
bool HasLane);
76 void MLxExpansion::clearStack() {
77 std::fill(LastMIs, LastMIs + 4,
nullptr);
102 DefMI =
MRI->getVRegDef(Reg);
108 DefMI =
MRI->getVRegDef(Reg);
117 unsigned MLxExpansion::getDefReg(
MachineInstr *MI)
const {
120 !
MRI->hasOneNonDBGUse(Reg))
131 !
MRI->hasOneNonDBGUse(Reg))
133 UseMI = &*
MRI->use_instr_nodbg_begin(Reg);
143 bool MLxExpansion::hasLoopHazard(
MachineInstr *MI)
const {
155 if (DefMI->
isPHI()) {
160 DefMI =
MRI->getVRegDef(SrcReg);
168 DefMI =
MRI->getVRegDef(Reg);
174 DefMI =
MRI->getVRegDef(Reg);
230 IgnoreStall.insert(DefMI);
240 if (IgnoreStall.count(MI))
248 unsigned Limit1 = isLikeA9 ? 1 : 4;
249 unsigned Limit2 = isLikeA9 ? 1 : 4;
250 for (
unsigned i = 1;
i <= 4; ++
i) {
251 int Idx = ((int)MIIdx -
i + 4) % 4;
273 unsigned MulOpc,
unsigned AddSubOpc,
274 bool NegAcc,
bool HasLane) {
283 unsigned NextOp = HasLane ? 5 : 4;
290 unsigned TmpReg =
MRI->createVirtualRegister(
291 TII->getRegClass(MCID1, 0, TRI, MF));
304 bool AccKill =
MRI->hasOneNonDBGUse(AccReg);
313 dbgs() <<
"Expanding: " << *
MI;
316 MII = std::prev(MII);
318 MII = std::prev(MII);
320 dbgs() <<
" " << MI1;
321 dbgs() <<
" " << MI2;
329 bool Changed =
false;
357 unsigned MulOpc, AddSubOpc;
358 bool NegAcc, HasLane;
360 MulOpc, AddSubOpc, NegAcc, HasLane) ||
364 ExpandFPMLxInstruction(MBB, MI, MulOpc, AddSubOpc, NegAcc, HasLane);
386 bool Modified =
false;
388 Modified |= ExpandFPMLxInstructions(MBB);
394 return new MLxExpansion();
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
FunctionPass * createMLxExpansionPass()
STATISTIC(NumFunctions,"Total number of functions")
MachineBasicBlock * getMBB() const
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
static cl::opt< unsigned > ExpandLimit("expand-limit", cl::init(~0U), cl::Hidden)
static cl::opt< bool > ForceExapnd("expand-all-fp-mlx", cl::init(false), cl::Hidden)
bool isCopyLike() const
Return true if the instruction behaves like a copy.
reverse_iterator rbegin()
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
unsigned getDeadRegState(bool B)
bool isImplicitDef() const
bool isInsertSubreg() const
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
FunctionPass class - This class is used to implement most global optimizations.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getOpcode() const
Return the opcode number for this descriptor.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI)
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getReg() const
getReg - Returns the register number.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
static bool isFpMulInstruction(unsigned Opcode)