LLVM  4.0.0
llvm::MipsSubtarget Member List

This is the complete list of members for llvm::MipsSubtarget, including all inherited members.

allowMixed16_32() const llvm::MipsSubtargetinline
enableLongBranchPass() const llvm::MipsSubtargetinline
enablePostRAScheduler() const overridellvm::MipsSubtarget
getABI() const llvm::MipsSubtarget
getCriticalPathRCs(RegClassVector &CriticalPathRCs) const overridellvm::MipsSubtarget
getFrameLowering() const overridellvm::MipsSubtargetinline
getGPRSizeInBytes() const llvm::MipsSubtargetinline
getInstrInfo() const overridellvm::MipsSubtargetinline
getInstrItineraryData() const overridellvm::MipsSubtargetinline
getOptLevelToEnablePostRAScheduler() const overridellvm::MipsSubtarget
getRegisterInfo() const overridellvm::MipsSubtargetinline
getRelocationModel() const llvm::MipsSubtarget
getSelectionDAGInfo() const overridellvm::MipsSubtargetinline
getTargetLowering() const overridellvm::MipsSubtargetinline
hasCnMips() const llvm::MipsSubtargetinline
hasDSP() const llvm::MipsSubtargetinline
hasDSPR2() const llvm::MipsSubtargetinline
hasDSPR3() const llvm::MipsSubtargetinline
hasEVA() const llvm::MipsSubtargetinline
hasExtractInsert() const llvm::MipsSubtargetinline
hasMips1() const llvm::MipsSubtargetinline
hasMips2() const llvm::MipsSubtargetinline
hasMips3() const llvm::MipsSubtargetinline
hasMips32() const llvm::MipsSubtargetinline
hasMips32r2() const llvm::MipsSubtargetinline
hasMips32r3() const llvm::MipsSubtargetinline
hasMips32r5() const llvm::MipsSubtargetinline
hasMips32r6() const llvm::MipsSubtargetinline
hasMips4() const llvm::MipsSubtargetinline
hasMips4_32() const llvm::MipsSubtargetinline
hasMips4_32r2() const llvm::MipsSubtargetinline
hasMips5() const llvm::MipsSubtargetinline
hasMips64() const llvm::MipsSubtargetinline
hasMips64r2() const llvm::MipsSubtargetinline
hasMips64r3() const llvm::MipsSubtargetinline
hasMips64r5() const llvm::MipsSubtargetinline
hasMips64r6() const llvm::MipsSubtargetinline
hasMSA() const llvm::MipsSubtargetinline
hasMTHC1() const llvm::MipsSubtargetinline
hasStandardEncoding() const llvm::MipsSubtargetinline
hasVFPU() const llvm::MipsSubtargetinline
initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)llvm::MipsSubtarget
inMicroMips32r6Mode() const llvm::MipsSubtargetinline
inMicroMips64r6Mode() const llvm::MipsSubtargetinline
inMicroMipsMode() const llvm::MipsSubtargetinline
inMips16HardFloat() const llvm::MipsSubtargetinline
inMips16Mode() const llvm::MipsSubtargetinline
inMips16ModeDefault() const llvm::MipsSubtargetinline
isABI_FPXX() const llvm::MipsSubtargetinline
isABI_N32() const llvm::MipsSubtarget
isABI_N64() const llvm::MipsSubtarget
isABI_O32() const llvm::MipsSubtarget
isABICalls() const llvm::MipsSubtargetinline
isFP64bit() const llvm::MipsSubtargetinline
isFPXX() const llvm::MipsSubtargetinline
isGP32bit() const llvm::MipsSubtargetinline
isGP64bit() const llvm::MipsSubtargetinline
isLittle() const llvm::MipsSubtargetinline
isNaN2008() const llvm::MipsSubtargetinline
isPositionIndependent() const llvm::MipsSubtarget
isPTR32bit() const llvm::MipsSubtargetinline
isPTR64bit() const llvm::MipsSubtargetinline
isSingleFloat() const llvm::MipsSubtargetinline
isTargetNaCl() const llvm::MipsSubtargetinline
MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, bool little, const MipsTargetMachine &TM)llvm::MipsSubtarget
noOddSPReg() const llvm::MipsSubtargetinline
os16() const llvm::MipsSubtargetinline
ParseSubtargetFeatures(StringRef CPU, StringRef FS)llvm::MipsSubtarget
setHelperClassesMips16()llvm::MipsSubtarget
setHelperClassesMipsSE()llvm::MipsSubtarget
stackAlignment() const llvm::MipsSubtargetinline
systemSupportsUnalignedAccess() const llvm::MipsSubtargetinline
useConstantIslands()llvm::MipsSubtargetstatic
useOddSPReg() const llvm::MipsSubtargetinline
useSmallSection() const llvm::MipsSubtargetinline
useSoftFloat() const llvm::MipsSubtargetinline