LLVM  4.0.0
WebAssemblyMachineFunctionInfo.h
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1 // WebAssemblyMachineFunctionInfo.h-WebAssembly machine function info-*- C++ -*-
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// \file
11 /// \brief This file declares WebAssembly-specific per-machine-function
12 /// information.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
17 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
18 
21 
22 namespace llvm {
23 
24 /// This class is derived from MachineFunctionInfo and contains private
25 /// WebAssembly-specific information for each MachineFunction.
27  MachineFunction &MF;
28 
29  std::vector<MVT> Params;
30  std::vector<MVT> Results;
31  std::vector<MVT> Locals;
32 
33  /// A mapping from CodeGen vreg index to WebAssembly register number.
34  std::vector<unsigned> WARegs;
35 
36  /// A mapping from CodeGen vreg index to a boolean value indicating whether
37  /// the given register is considered to be "stackified", meaning it has been
38  /// determined or made to meet the stack requirements:
39  /// - single use (per path)
40  /// - single def (per path)
41  /// - defined and used in LIFO order with other stack registers
42  BitVector VRegStackified;
43 
44  // A virtual register holding the pointer to the vararg buffer for vararg
45  // functions. It is created and set in TLI::LowerFormalArguments and read by
46  // TLI::LowerVASTART
47  unsigned VarargVreg = -1U;
48 
49  // A virtual register holding the base pointer for functions that have
50  // overaligned values on the user stack.
51  unsigned BasePtrVreg = -1U;
52 
53  public:
54  explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {}
55  ~WebAssemblyFunctionInfo() override;
56 
57  void addParam(MVT VT) { Params.push_back(VT); }
58  const std::vector<MVT> &getParams() const { return Params; }
59 
60  void addResult(MVT VT) { Results.push_back(VT); }
61  const std::vector<MVT> &getResults() const { return Results; }
62 
63  void addLocal(MVT VT) { Locals.push_back(VT); }
64  const std::vector<MVT> &getLocals() const { return Locals; }
65 
66  unsigned getVarargBufferVreg() const {
67  assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
68  return VarargVreg;
69  }
70  void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; }
71 
72  unsigned getBasePointerVreg() const {
73  assert(BasePtrVreg != -1U && "Base ptr vreg hasn't been set");
74  return BasePtrVreg;
75  }
76  void setBasePointerVreg(unsigned Reg) { BasePtrVreg = Reg; }
77 
78  static const unsigned UnusedReg = -1u;
79 
80  void stackifyVReg(unsigned VReg) {
82  if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
83  VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1);
84  VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg));
85  }
86  bool isVRegStackified(unsigned VReg) const {
87  if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
88  return false;
89  return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg));
90  }
91 
92  void initWARegs();
93  void setWAReg(unsigned VReg, unsigned WAReg) {
94  assert(WAReg != UnusedReg);
95  assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size());
96  WARegs[TargetRegisterInfo::virtReg2Index(VReg)] = WAReg;
97  }
98  unsigned getWAReg(unsigned Reg) const {
99  assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size());
100  return WARegs[TargetRegisterInfo::virtReg2Index(Reg)];
101  }
102 
103  // For a given stackified WAReg, return the id number to print with push/pop.
104  static unsigned getWARegStackId(unsigned Reg) {
105  assert(Reg & INT32_MIN);
106  return Reg & INT32_MAX;
107  }
108 };
109 
110 void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM,
111  Type *Ty, SmallVectorImpl<MVT> &ValueVTs);
112 
113 void ComputeSignatureVTs(const Function &F, const TargetMachine &TM,
114  SmallVectorImpl<MVT> &Params,
115  SmallVectorImpl<MVT> &Results);
116 
117 } // end namespace llvm
118 
119 #endif
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:193
BitVector & set()
Definition: BitVector.h:219
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:119
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Function Alias Analysis Results
void setWAReg(unsigned VReg, unsigned WAReg)
bool isVRegStackified(unsigned VReg) const
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
void ComputeLegalValueVTs(const Function &F, const TargetMachine &TM, Type *Ty, SmallVectorImpl< MVT > &ValueVTs)
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getWAReg(unsigned Reg) const
#define F(x, y, z)
Definition: MD5.cpp:51
MVT - Machine Value Type.
void ComputeSignatureVTs(const Function &F, const TargetMachine &TM, SmallVectorImpl< MVT > &Params, SmallVectorImpl< MVT > &Results)
This file provides WebAssembly-specific target descriptions.
const std::vector< MVT > & getResults() const
bool test(unsigned Idx) const
Definition: BitVector.h:323
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const std::vector< MVT > & getParams() const
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const std::vector< MVT > & getLocals() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned getWARegStackId(unsigned Reg)