|
LLVM
4.0.0
|
#include "PPCISelLowering.h"#include "MCTargetDesc/PPCPredicates.h"#include "PPCCallingConv.h"#include "PPCCCState.h"#include "PPCMachineFunctionInfo.h"#include "PPCPerfectShuffle.h"#include "PPCTargetMachine.h"#include "PPCTargetObjectFile.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/StringSwitch.h"#include "llvm/ADT/Triple.h"#include "llvm/CodeGen/CallingConvLower.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineLoopInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"#include "llvm/IR/CallingConv.h"#include "llvm/IR/Constants.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/Intrinsics.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/Format.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetOptions.h"#include <list>#include "PPCGenCallingConv.inc"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "ppc-lowering" |
Functions | |
| STATISTIC (NumTailCalls,"Number of tail calls") | |
| STATISTIC (NumSiblingCalls,"Number of sibling calls") | |
| static void | getMaxByValAlign (Type *Ty, unsigned &MaxAlign, unsigned MaxMaxAlign) |
| getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment. More... | |
| static bool | isFloatingPointZero (SDValue Op) |
| isFloatingPointZero - Return true if this is 0.0 or -0.0. More... | |
| static bool | isConstantOrUndef (int Op, int Val) |
| isConstantOrUndef - Op is either an undef node or a ConstantSDNode. More... | |
| static bool | isVMerge (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart) |
| isVMerge - Common function, used to match vmrg* shuffles. More... | |
| static bool | isVMerge (ShuffleVectorSDNode *N, unsigned IndexOffset, unsigned RHSStartValue) |
| Common function used to match vmrgew and vmrgow shuffles. More... | |
| static bool | isIntS16Immediate (SDNode *N, short &Imm) |
| isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value. More... | |
| static bool | isIntS16Immediate (SDValue Op, short &Imm) |
| static void | fixupFuncForFI (SelectionDAG &DAG, int FrameIdx, EVT VT) |
| static void | getLabelAccessInfo (bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr) |
| Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. More... | |
| static SDValue | LowerLabelRef (SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG) |
| static void | setUsesTOCBasePtr (MachineFunction &MF) |
| static void | setUsesTOCBasePtr (SelectionDAG &DAG) |
| static SDValue | getTOCEntry (SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit, SDValue GA) |
| static unsigned | CalculateStackSlotSize (EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize) |
| CalculateStackSlotSize - Calculates the size reserved for this argument on the stack. More... | |
| static unsigned | CalculateStackSlotAlignment (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize) |
| CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack. More... | |
| static bool | CalculateStackSlotUsed (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs, bool HasQPX) |
| CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers). More... | |
| static unsigned | EnsureStackAlignment (const PPCFrameLowering *Lowering, unsigned NumBytes) |
| EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target. More... | |
| static int | CalculateTailCallSPDiff (SelectionDAG &DAG, bool isTailCall, unsigned ParamSize) |
| CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall. More... | |
| static bool | isFunctionGlobalAddress (SDValue Callee) |
| static bool | resideInSameSection (const Function *Caller, SDValue Callee, const TargetMachine &TM) |
| static bool | needStackSlotPassParameters (const PPCSubtarget &Subtarget, const SmallVectorImpl< ISD::OutputArg > &Outs) |
| static bool | hasSameArgumentList (const Function *CallerFn, ImmutableCallSite *CS) |
| static SDNode * | isBLACompatibleAddress (SDValue Op, SelectionDAG &DAG) |
| isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction. More... | |
| static void | StoreTailCallArgumentsToStackSlot (SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, const SDLoc &dl) |
| StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. More... | |
| static SDValue | EmitTailCallStoreFPAndRetAddr (SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl) |
| EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call. More... | |
| static void | CalculateTailCallArgDest (SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments) |
| CalculateTailCallArgDest - Remember Argument for later processing. More... | |
| static SDValue | CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) |
| CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size". More... | |
| static void | LowerMemOpCallTo (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl) |
| LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls. More... | |
| static void | PrepareTailCall (SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments) |
| static unsigned | PrepareCall (SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, SDValue CallSeqStart, const SDLoc &dl, int SPDiff, bool isTailCall, bool isPatchPoint, bool hasNest, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &Ops, std::vector< EVT > &NodeTys, ImmutableCallSite *CS, const PPCSubtarget &Subtarget) |
| static SDValue | BuildSplatI (int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl) |
| BuildSplatI - Build a canonical splati of Val with an element size of SplatSize. More... | |
| static SDValue | BuildIntrinsicOp (unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other) |
| BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID. More... | |
| static SDValue | BuildIntrinsicOp (unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other) |
| BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID. More... | |
| static SDValue | BuildIntrinsicOp (unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other) |
| BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID. More... | |
| static SDValue | BuildVSLDOI (SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl) |
| BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount. More... | |
| static bool | haveEfficientBuildVectorPattern (BuildVectorSDNode *V, bool HasDirectMove) |
| Do we have an efficient pattern in a .td file for this node? More... | |
| static SDValue | GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) |
| GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More... | |
| static bool | getVectorCompareInfo (SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget) |
| getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison. More... | |
| static Instruction * | callIntrinsic (IRBuilder<> &Builder, Intrinsic::ID Id) |
| static int | getEstimateRefinementSteps (EVT VT, const PPCSubtarget &Subtarget) |
| static void | getBaseWithConstantOffset (SDValue Loc, SDValue &Base, int64_t &Offset, SelectionDAG &DAG) |
| static bool | isConsecutiveLSLoc (SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) |
| static bool | isConsecutiveLS (SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) |
| static bool | findConsecutiveLoad (LoadSDNode *LD, SelectionDAG &DAG) |
| static SDValue | generateEquivalentSub (SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG) |
| This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR. More... | |
| static SDValue | combineBVOfConsecutiveLoads (SDNode *N, SelectionDAG &DAG) |
| Reduce the number of loads when building a vector. More... | |
Variables | |
| static cl::opt< bool > | DisablePPCPreinc ("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden) |
| static cl::opt< bool > | DisableILPPref ("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden) |
| static cl::opt< bool > | DisablePPCUnaligned ("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden) |
| static cl::opt< bool > | DisableSCO ("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden) |
| cl::opt< bool > | ANDIGlueBug |
| static const MCPhysReg | FPR [] |
| FPR - The set of FP registers that should be allocated for arguments, on Darwin. More... | |
| static const MCPhysReg | QFPR [] |
| QFPR - The set of QPX registers that should be allocated for arguments. More... | |
| #define DEBUG_TYPE "ppc-lowering" |
Definition at line 50 of file PPCISelLowering.cpp.
|
static |
BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.
Definition at line 7092 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.
Referenced by llvm::PPCTargetLowering::PerformDAGCombine().
|
static |
BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID.
Definition at line 7101 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.
|
static |
BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID.
Definition at line 7111 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.
|
static |
BuildSplatI - Build a canonical splati of Val with an element size of SplatSize.
Cast the result to VT.
Definition at line 7070 of file PPCISelLowering.cpp.
References assert(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::Other, llvm::MVT::v16i8, llvm::MVT::v4i32, and llvm::MVT::v8i16.
|
static |
BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.
The result has the specified value type.
Definition at line 7121 of file PPCISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), i, and llvm::MVT::v16i8.
Referenced by GeneratePerfectShuffle().
|
static |
CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack.
Definition at line 2822 of file PPCISelLowering.cpp.
References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::EVT::getStoreSize(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegs(), llvm::ISD::ArgFlagsTy::isSplit(), llvm_unreachable, llvm::MVT::ppcf128, llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::MVT::v8i16.
Referenced by CalculateStackSlotUsed().
|
static |
CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.
Definition at line 2806 of file PPCISelLowering.cpp.
References AMDGPU::RuntimeMD::KeyName::ArgSize, llvm::ISD::ArgFlagsTy::getByValSize(), llvm::EVT::getStoreSize(), llvm::ISD::ArgFlagsTy::isByVal(), and llvm::ISD::ArgFlagsTy::isInConsecutiveRegs().
Referenced by CalculateStackSlotUsed().
|
static |
CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers).
ArgOffset, AvailableFPRs, and AvailableVRs must hold the current argument position, and will be updated to account for this argument.
Definition at line 2868 of file PPCISelLowering.cpp.
References CalculateStackSlotAlignment(), CalculateStackSlotSize(), llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegsLast(), llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i1, llvm::MVT::v4i32, and llvm::MVT::v8i16.
Referenced by needStackSlotPassParameters().
|
static |
CalculateTailCallArgDest - Remember Argument for later processing.
Calculate the position of the argument.
Definition at line 4285 of file PPCISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SDValue::getValueSizeInBits(), llvm::MVT::i32, llvm::MVT::i64, Offset, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by LowerMemOpCallTo().
|
static |
CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall.
Definition at line 3966 of file PPCISelLowering.cpp.
References llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::PPCFunctionInfo::getMinReservedArea(), and llvm::PPCFunctionInfo::setTailCallSPDelta().
|
static |
Definition at line 8570 of file PPCISelLowering.cpp.
References llvm::IRBuilder< T, Inserter >::CreateCall(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::BasicBlock::getParent(), and llvm::GlobalValue::getParent().
Referenced by llvm::PPCTargetLowering::emitLeadingFence(), and llvm::PPCTargetLowering::emitTrailingFence().
|
static |
Reduce the number of loads when building a vector.
Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. If the loads are consecutive but in descending order, a shuffle is added at the end to reorder the vector.
Definition at line 10764 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::ISD::EXTLOAD, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), i, isConsecutiveLS(), llvm::MipsISD::LDL, llvm::SPII::Load, llvm::ISD::LOAD, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
|
static |
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size".
Alignment information is specified by the specific parameter attribute. The copy will be passed as a byval function parameter. Sometimes what we are copying is the end of a larger object, the part that does not fit in registers.
Definition at line 4330 of file PPCISelLowering.cpp.
References llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), and llvm::MVT::i32.
|
static |
EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call.
Definition at line 4249 of file PPCISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::PPCSubtarget::getFrameLowering(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), llvm::MachineFunction::getSubtarget(), llvm::MVT::i32, llvm::MVT::i64, llvm::PPCSubtarget::isDarwinABI(), and llvm::PPCSubtarget::isPPC64().
Referenced by PrepareTailCall().
|
static |
EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target.
Definition at line 2923 of file PPCISelLowering.cpp.
References llvm::TargetFrameLowering::getStackAlignment().
|
static |
Definition at line 9968 of file PPCISelLowering.cpp.
References llvm::SmallVectorImpl< T >::clear(), llvm::MemSDNode::getChain(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::EVT::getStoreSize(), I, llvm::ARM_PROC::IE, llvm::SmallSet< T, N, C >::insert(), llvm::SmallVectorImpl< T >::insert(), isConsecutiveLS(), llvm::SDNode::ops(), AMDGPU::RuntimeMD::KernelArg::Queue, llvm::ISD::TokenFactor, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by llvm::PPCTargetLowering::PerformDAGCombine().
|
static |
Definition at line 1832 of file PPCISelLowering.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MVT::i64, and llvm::PPCFunctionInfo::setHasNonRISpills().
Referenced by llvm::PPCTargetLowering::SelectAddressRegImm().
|
static |
This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR.
This function is purely for codegen purposes and has some flags to guide the codegen process.
Definition at line 10036 of file PPCISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MVT::i1, llvm::MVT::i64, llvm::ISD::SETCC, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
|
static |
GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
Definition at line 7479 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, BuildVSLDOI(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), i, llvm_unreachable, PerfectShuffleTable, and llvm::MVT::v16i8.
|
static |
Definition at line 9803 of file PPCISelLowering.cpp.
References llvm::SDValue::getOperand(), llvm::SelectionDAG::isBaseWithConstantOffset(), and Offset.
Referenced by isConsecutiveLSLoc().
|
static |
Definition at line 9731 of file PPCISelLowering.cpp.
References llvm::MVT::f64, llvm::EVT::getScalarType(), and llvm::PPCSubtarget::hasRecipPrec().
|
static |
Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
Definition at line 2083 of file PPCISelLowering.cpp.
References llvm::PPCSubtarget::hasLazyResolverStub(), llvm::PPCII::MO_HA, llvm::PPCII::MO_LO, llvm::PPCII::MO_NLP_FLAG, llvm::PPCII::MO_NLP_HIDDEN_FLAG, and llvm::PPCII::MO_PIC_FLAG.
getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.
Definition at line 979 of file PPCISelLowering.cpp.
Referenced by llvm::PPCTargetLowering::getByValTypeAlignment().
|
static |
Definition at line 2136 of file PPCISelLowering.cpp.
References llvm::MachinePointerInfo::getGOT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getVTList(), llvm::PPCISD::GlobalBaseReg, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::Other, and llvm::PPCISD::TOC_ENTRY.
|
static |
getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.
If it is, return true and fill in Opc/isDot with information about the intrinsic.
Definition at line 7792 of file PPCISelLowering.cpp.
References llvm::SDValue::getOperand(), llvm::PPCSubtarget::hasP8Altivec(), llvm::PPCSubtarget::hasP9Altivec(), llvm::PPCSubtarget::hasVSX(), and llvm_unreachable.
Referenced by llvm::PPCTargetLowering::PerformDAGCombine().
|
static |
Definition at line 4068 of file PPCISelLowering.cpp.
References llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::arg_begin(), llvm::Function::arg_begin(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::arg_end(), llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::arg_size(), llvm::Function::getArgumentList(), and llvm::Value::getType().
|
static |
Do we have an efficient pattern in a .td file for this node?
| V | - pointer to the BuildVectorSDNode being matched |
| HasDirectMove | - does this subtarget have VSR <-> GPR direct moves? |
There are some patterns where it is beneficial to keep a BUILD_VECTOR node as a BUILD_VECTOR node rather than expanding it. The patterns where the opposite is true (expansion is beneficial) are:
Definition at line 7146 of file PPCISelLowering.cpp.
References llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), i, llvm::BuildVectorSDNode::isConstant(), llvm::SDNode::isOnlyUserOf(), llvm::SDValue::isUndef(), llvm::ISD::LOAD, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, and llvm::MVT::v4i32.
|
static |
isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction.
Definition at line 4204 of file PPCISelLowering.cpp.
References llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ConstantSDNode::getZExtValue().
Referenced by PrepareCall().
|
static |
Definition at line 9855 of file PPCISelLowering.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isConsecutiveLSLoc(), llvm::AArch64CC::LS, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v4f32, llvm::MVT::v4f64, and llvm::MVT::v4i32.
Referenced by combineBVOfConsecutiveLoads(), and findConsecutiveLoad().
|
static |
Definition at line 9815 of file PPCISelLowering.cpp.
References llvm::AMDGPUISD::BFI, llvm::ISD::FrameIndex, llvm::MemSDNode::getBasePtr(), getBaseWithConstantOffset(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::TargetLowering::isGAPlusOffset().
Referenced by isConsecutiveLS().
|
static |
isConstantOrUndef - Op is either an undef node or a ConstantSDNode.
Return true if Op is undef or if it matches the specified value.
Definition at line 1160 of file PPCISelLowering.cpp.
Referenced by llvm::PPC::isQVALIGNIShuffleMask(), isVMerge(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), and llvm::PPC::isVSLDOIShuffleMask().
isFloatingPointZero - Return true if this is 0.0 or -0.0.
Definition at line 1146 of file PPCISelLowering.cpp.
References llvm::HexagonISD::CP, llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::ISD::isEXTLoad(), and llvm::ISD::isNON_EXTLoad().
Definition at line 4390 of file PPCISelLowering.cpp.
References G, llvm::SDValue::getOpcode(), llvm::ISD::GlobalTLSAddress, and llvm::ISD::TargetGlobalTLSAddress.
Referenced by PrepareCall().
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value.
If so, this returns true and the immediate.
Definition at line 1766 of file PPCISelLowering.cpp.
References llvm::SDNode::getValueType(), llvm::MVT::i32, and N.
Referenced by isIntS16Immediate(), llvm::PPCTargetLowering::SelectAddressRegImm(), and llvm::PPCTargetLowering::SelectAddressRegReg().
Definition at line 1776 of file PPCISelLowering.cpp.
References llvm::SDValue::getNode(), and isIntS16Immediate().
|
static |
isVMerge - Common function, used to match vmrg* shuffles.
Definition at line 1282 of file PPCISelLowering.cpp.
References assert(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), i, isConstantOrUndef(), and llvm::MVT::v16i8.
Referenced by llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), and llvm::PPC::isVMRGLShuffleMask().
|
static |
Common function used to match vmrgew and vmrgow shuffles.
The indexOffset determines whether to look for even or odd words in the shuffle mask. This is based on the of the endianness of the target machine.
The mask to the shuffle vector instruction specifies the indices of the elements from the two input vectors to place in the result. The elements are numbered in array-access order, starting with the first vector. These vectors are always of type v16i8, thus each vector will contain 16 elements of size
The RHSStartValue indicates whether the same input vectors are used (unary) or two different input vectors are used, based on the following:
| [in] | N | The shuffle vector SD Node to analyze |
| [in] | IndexOffset | Specifies whether to look for even or odd elements |
| [in] | RHSStartValue | Specifies the starting index for the righthand input vector to the shuffle_vector instruction |
Definition at line 1392 of file PPCISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), i, isConstantOrUndef(), and llvm::MVT::v16i8.
|
static |
Definition at line 2108 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::PPCISD::GlobalBaseReg, llvm::MipsISD::Hi, llvm::PPCISD::Hi, llvm::MipsISD::Lo, llvm::PPCISD::Lo, and Zero.
|
static |
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.
Definition at line 4341 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, CalculateTailCallArgDest(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i64, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
|
static |
Definition at line 4030 of file PPCISelLowering.cpp.
References llvm::array_lengthof(), assert(), CalculateStackSlotUsed(), llvm::PPCSubtarget::getFrameLowering(), llvm::PPCFrameLowering::getLinkageSize(), llvm::PPCSubtarget::hasQPX(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isSVR4ABI(), llvm::NVPTX::PTXLdStInstCode::V2, and llvm::NVPTX::PTXLdStInstCode::V4.
|
static |
Definition at line 4403 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::PPCISD::BCTRL, llvm::PPCISD::CALL, G, llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getCalledValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::Glue, llvm::PPCSubtarget::hasInvariantFunctionDescriptors(), i, llvm::MVT::i64, isBLACompatibleAddress(), llvm::PPCSubtarget::isELFv2ABI(), isFunctionGlobalAddress(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isSVR4ABI(), llvm::PPCSubtarget::isTargetELF(), llvm::makeArrayRef(), llvm::PPCII::MO_PLT, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MONone, llvm::PPCISD::MTCTR, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SDValue::setNode(), setUsesTOCBasePtr(), llvm::TargetMachine::shouldAssumeDSOLocal(), and llvm::SystemZISD::TM.
|
static |
Definition at line 4365 of file PPCISelLowering.cpp.
References EmitTailCallStoreFPAndRetAddr(), llvm::SmallVectorBase::empty(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::MVT::Other, StoreTailCallArgumentsToStackSlot(), and llvm::ISD::TokenFactor.
|
static |
Definition at line 3984 of file PPCISelLowering.cpp.
References llvm::dyn_cast(), F, G, llvm::TargetMachine::getFunctionSections(), llvm::GlobalAddressSDNode::getGlobal(), llvm::GlobalValue::getParent(), llvm::GlobalObject::getSection(), llvm::GlobalValue::getSection(), llvm::Function::getSectionPrefix(), llvm::GlobalObject::hasComdat(), llvm::GlobalValue::hasComdat(), llvm::GlobalValue::isStrongDefinitionForLinker(), and llvm::TargetMachine::shouldAssumeDSOLocal().
|
static |
Definition at line 2127 of file PPCISelLowering.cpp.
References llvm::MachineFunction::getInfo(), and llvm::PPCFunctionInfo::setUsesTOCBasePtr().
Referenced by llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), PrepareCall(), and setUsesTOCBasePtr().
|
static |
Definition at line 2132 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getMachineFunction(), and setUsesTOCBasePtr().
| STATISTIC | ( | NumTailCalls | , |
| "Number of tail calls" | |||
| ) |
| STATISTIC | ( | NumSiblingCalls | , |
| "Number of sibling calls" | |||
| ) |
|
static |
StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
Definition at line 4232 of file PPCISelLowering.cpp.
References llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), i, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by PrepareTailCall().
| cl::opt<bool> ANDIGlueBug |
Referenced by llvm::PPCTargetLowering::PPCTargetLowering().
|
static |
Referenced by llvm::PPCTargetLowering::getSchedulingPreference().
|
static |
Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().
|
static |
Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses().
|
static |
FPR - The set of FP registers that should be allocated for arguments, on Darwin.
Definition at line 2795 of file PPCISelLowering.cpp.
Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), and llvm::SystemZMachineFunctionInfo::setVarArgsFirstFPR().
QFPR - The set of QPX registers that should be allocated for arguments.
Definition at line 2800 of file PPCISelLowering.cpp.
1.8.6