LLVM  4.0.0
MipsInstrInfo.h
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1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips implementation of the TargetInstrInfo class.
11 //
12 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
13 // order for MipsLongBranch pass to work correctly when the code has inline
14 // assembly. The returned value doesn't have to be the asm instruction's exact
15 // size in bytes; MipsLongBranch only expects it to be the correct upper bound.
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
20 
21 #include "Mips.h"
22 #include "MipsRegisterInfo.h"
26 
27 #define GET_INSTRINFO_HEADER
28 #include "MipsGenInstrInfo.inc"
29 
30 namespace llvm {
31 class MipsSubtarget;
33  virtual void anchor();
34 protected:
36  unsigned UncondBrOpc;
37 
38 public:
39  enum BranchType {
40  BT_None, // Couldn't analyze branch.
41  BT_NoBranch, // No branches found.
42  BT_Uncond, // One unconditional branch.
43  BT_Cond, // One conditional branch.
44  BT_CondUncond, // A conditional branch followed by an unconditional branch.
45  BT_Indirect // One indirct branch.
46  };
47 
48  explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
49 
50  static const MipsInstrInfo *create(MipsSubtarget &STI);
51 
52  /// Branch Analysis
54  MachineBasicBlock *&FBB,
56  bool AllowModify) const override;
57 
59  int *BytesRemoved = nullptr) const override;
60 
63  const DebugLoc &DL,
64  int *BytesAdded = nullptr) const override;
65 
66  bool
68 
70  MachineBasicBlock *&FBB,
72  bool AllowModify,
73  SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
74 
75  /// Determine the opcode of a non-delay slot form for a branch if one exists.
77 
78  /// Predicate to determine if an instruction can go in a forbidden slot.
79  bool SafeInForbiddenSlot(const MachineInstr &MI) const;
80 
81  /// Predicate to determine if an instruction has a forbidden slot.
82  bool HasForbiddenSlot(const MachineInstr &MI) const;
83 
84  /// Insert nop instruction when hazard condition is found
86  MachineBasicBlock::iterator MI) const override;
87 
88  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
89  /// such, whenever a client has an instance of instruction info, it should
90  /// always be able to get register info as well (through this method).
91  ///
92  virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
93 
94  virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
95 
96  /// Return the number of bytes of code the specified instruction may be.
97  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
98 
101  unsigned SrcReg, bool isKill, int FrameIndex,
102  const TargetRegisterClass *RC,
103  const TargetRegisterInfo *TRI) const override {
104  storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
105  }
106 
109  unsigned DestReg, int FrameIndex,
110  const TargetRegisterClass *RC,
111  const TargetRegisterInfo *TRI) const override {
112  loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
113  }
114 
115  virtual void storeRegToStack(MachineBasicBlock &MBB,
117  unsigned SrcReg, bool isKill, int FrameIndex,
118  const TargetRegisterClass *RC,
119  const TargetRegisterInfo *TRI,
120  int64_t Offset) const = 0;
121 
122  virtual void loadRegFromStack(MachineBasicBlock &MBB,
124  unsigned DestReg, int FrameIndex,
125  const TargetRegisterClass *RC,
126  const TargetRegisterInfo *TRI,
127  int64_t Offset) const = 0;
128 
129  virtual void adjustStackPtr(unsigned SP, int64_t Amount,
131  MachineBasicBlock::iterator I) const = 0;
132 
133  /// Create an instruction which has the same operands and memory operands
134  /// as MI but has a new opcode.
135  MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
137 
138 protected:
139  bool isZeroImm(const MachineOperand &op) const;
140 
143 
144 private:
145  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
146 
147  void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
148  MachineBasicBlock *&BB,
149  SmallVectorImpl<MachineOperand> &Cond) const;
150 
151  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
152  const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
153 };
154 
155 /// Create MipsInstrInfo objects.
156 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
157 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
158 
159 }
160 
161 #endif
bool isZeroImm(const MachineOperand &op) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
A debug info location.
Definition: DebugLoc.h:34
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
#define op(i)
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
virtual const MipsRegisterInfo & getRegisterInfo() const =0
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
struct fuzzer::@269 Flags
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:35
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock * MBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
uint32_t Offset
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: MipsInstrInfo.h:99
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
MachineOperand class - Representation of each machine instruction operand.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
Flags
Flags values. These may be or'd together.
Representation of each machine instruction.
Definition: MachineInstr.h:52
#define I(x, y, z)
Definition: MD5.cpp:54
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
IRTranslator LLVM IR MI
static const MipsInstrInfo * create(MipsSubtarget &STI)
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override