24 #define DEBUG_TYPE "systemz-shorten-inst"
33 return "SystemZ Instruction Shortening";
48 bool shortenOn001AddCC(
MachineInstr &MI,
unsigned Opcode);
60 return new SystemZShortenInst(TM);
76 bool SystemZShortenInst::shortenIIF(
MachineInstr &
MI,
unsigned LLIxL,
81 unsigned thisSubRegIdx =
82 (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
83 : SystemZ::subreg_l32);
84 unsigned otherSubRegIdx =
85 (thisSubRegIdx == SystemZ::subreg_l32 ? SystemZ::subreg_h32
86 : SystemZ::subreg_l32);
88 TRI->getMatchingSuperReg(Reg, thisSubRegIdx, &SystemZ::GR64BitRegClass);
89 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
90 if (LiveRegs.contains(OtherReg))
109 bool SystemZShortenInst::shortenOn0(
MachineInstr &MI,
unsigned Opcode) {
119 bool SystemZShortenInst::shortenOn01(
MachineInstr &MI,
unsigned Opcode) {
131 bool SystemZShortenInst::shortenOn001(
MachineInstr &MI,
unsigned Opcode) {
144 bool SystemZShortenInst::shortenOn001AddCC(
MachineInstr &MI,
unsigned Opcode) {
145 if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
157 bool SystemZShortenInst::shortenFPConv(
MachineInstr &MI,
unsigned Opcode) {
173 .addOperand(Suppress);
181 bool Changed =
false;
185 LiveRegs.addLiveOuts(MBB);
188 for (
auto MBBI = MBB.
rbegin(), MBBE = MBB.
rend(); MBBI != MBBE; ++MBBI) {
192 Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
196 Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
200 Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
204 Changed |= shortenOn001(MI, SystemZ::DDBR);
208 Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
212 Changed |= shortenOn01(MI, SystemZ::LDEBR);
216 Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
220 Changed |= shortenOn001(MI, SystemZ::MDBR);
223 case SystemZ::WFLCDB:
224 Changed |= shortenOn01(MI, SystemZ::LCDFR);
227 case SystemZ::WFLNDB:
228 Changed |= shortenOn01(MI, SystemZ::LNDFR);
231 case SystemZ::WFLPDB:
232 Changed |= shortenOn01(MI, SystemZ::LPDFR);
235 case SystemZ::WFSQDB:
236 Changed |= shortenOn01(MI, SystemZ::SQDBR);
240 Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
244 Changed |= shortenOn01(MI, SystemZ::CDBR);
249 Changed |= shortenOn0(MI, SystemZ::LDE32);
253 Changed |= shortenOn0(MI, SystemZ::STE);
261 Changed |= shortenOn0(MI, SystemZ::STD);
265 LiveRegs.stepBackward(MI);
280 bool Changed =
false;
282 Changed |= processBlock(MBB);
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getFirstReg(unsigned Reg)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
const MachineOperand & getOperand(unsigned i) const
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool isImmLH(uint64_t Val)
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
const SystemZInstrInfo * getInstrInfo() const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
unsigned getRegAsGR64(unsigned Reg)
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
A set of live physical registers with functions to track liveness when walking backward/forward throu...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned getReg() const
getReg - Returns the register number.
static void tieOpsIfNeeded(MachineInstr &MI)
static bool isImmLL(uint64_t Val)
StringRef - Represent a constant reference to a string, i.e.
const SystemZRegisterInfo * getRegisterInfo() const override
Properties which a MachineFunction may have at a given point in time.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.