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LLVM
4.0.0
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Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this: More...
#include "AMDGPU.h"#include "AMDGPUSubtarget.h"#include "SIInstrInfo.h"#include "llvm/CodeGen/MachineDominators.h"#include "llvm/CodeGen/MachineFunctionPass.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/Support/Debug.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetMachine.h"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "si-fix-sgpr-copies" |
Variables | |
| DEBUG_TYPE | |
| SI Fix SGPR | copies |
| SI Fix SGPR | false |
Copies from VGPR to SGPR registers are illegal and the register coalescer will sometimes generate these illegal copies in situations like this:
Register Class <vsrc> is the union of <vgpr> and <sgpr>
BB0: vreg0 <sgpr> = SCALAR_INST vreg1 <vsrc> = COPY vreg0 <sgpr> ... BRANCH cond BB1, BB2 BB1: vreg2 <vgpr> = VECTOR_INST vreg3 <vsrc> = COPY vreg2 <vgpr> BB2: vreg4 <vsrc> = PHI vreg1 <vsrc>, <BB#0>, vreg3 <vrsc>, <BB#1> vreg5 <vgpr> = VECTOR_INST vreg4 <vsrc>
The coalescer will begin at BB0 and eliminate its copy, then the resulting code will look like this:
BB0: vreg0 <sgpr> = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: vreg2 <vgpr> = VECTOR_INST vreg3 <vsrc> = COPY vreg2 <vgpr> BB2: vreg4 <sgpr> = PHI vreg0 <sgpr>, <BB#0>, vreg3 <vsrc>, <BB#1> vreg5 <vgpr> = VECTOR_INST vreg4 <sgpr>
Now that the result of the PHI instruction is an SGPR, the register allocator is now forced to constrain the register class of vreg3 to <sgpr> so we end up with final code like this:
BB0: vreg0 <sgpr> = SCALAR_INST ... BRANCH cond BB1, BB2 BB1: vreg2 <vgpr> = VECTOR_INST vreg3 <sgpr> = COPY vreg2 <vgpr> BB2: vreg4 <sgpr> = PHI vreg0 <sgpr>, <BB#0>, vreg3 <sgpr>, <BB#1> vreg5 <vgpr> = VECTOR_INST vreg4 <sgpr>
Now this code contains an illegal copy from a VGPR to an SGPR.
In order to avoid this problem, this pass searches for PHI instructions which define a <vsrc> register and constrains its definition class to <vgpr> if the user of the PHI's definition register is a vector instruction. If the PHI's definition class is constrained to <vgpr> then the coalescer will be unable to perform the COPY removal from the above example which ultimately led to the creation of an illegal COPY.
Definition in file SIFixSGPRCopies.cpp.
| #define DEBUG_TYPE "si-fix-sgpr-copies" |
Definition at line 81 of file SIFixSGPRCopies.cpp.
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Definition at line 184 of file SIFixSGPRCopies.cpp.
References addOperand(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::eraseFromParent(), getCopyRegClasses(), llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::SIRegisterInfo::getSubRegClass(), llvm::MachineRegisterInfo::hasOneUse(), I, llvm::MachineInstr::isCopy(), llvm::MachineInstr::isRegSequence(), llvm::SIRegisterInfo::isSGPRClass(), isSGPRToVGPRCopy(), MI, N, llvm::MachineOperand::setReg(), llvm::MachineRegisterInfo::setRegClass(), SubReg, and llvm::MachineRegisterInfo::use_instr_begin().
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Definition at line 137 of file SIFixSGPRCopies.cpp.
References llvm::MachineInstr::getOperand(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by foldVGPRCopyIntoRegSequence().
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Definition at line 287 of file SIFixSGPRCopies.cpp.
References E, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), and I.
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Definition at line 123 of file SIFixSGPRCopies.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVGPRs(), i, llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), and MRI.
| INITIALIZE_PASS_BEGIN | ( | SIFixSGPRCopies | , |
| DEBUG_TYPE | , | ||
| "SI Fix SGPR copies" | , | ||
| false | , | ||
| false | |||
| ) |
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Definition at line 297 of file SIFixSGPRCopies.cpp.
References llvm::MachineOperand::getImm(), llvm::SIInstrInfo::getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), and llvm::MachineInstr::isMoveImmediate().
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Definition at line 165 of file SIFixSGPRCopies.cpp.
References llvm::SIRegisterInfo::hasVGPRs(), and llvm::SIRegisterInfo::isSGPRClass().
Referenced by foldVGPRCopyIntoRegSequence().
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Definition at line 159 of file SIFixSGPRCopies.cpp.
References llvm::SIRegisterInfo::hasVGPRs(), and llvm::SIRegisterInfo::isSGPRClass().
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Definition at line 259 of file SIFixSGPRCopies.cpp.
References assert(), llvm::SmallSet< T, N, C >::count(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), i, and llvm::SmallSet< T, N, C >::insert().
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Definition at line 247 of file SIFixSGPRCopies.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::SIRegisterInfo::hasVGPRs(), and i.
| SI Fix SGPR copies |
Definition at line 111 of file SIFixSGPRCopies.cpp.
| DEBUG_TYPE |
Definition at line 111 of file SIFixSGPRCopies.cpp.
| SI Fix SGPR false |
Definition at line 111 of file SIFixSGPRCopies.cpp.
1.8.6