89 #define DEBUG_TYPE "expand-condsets"
119 using namespace llvm;
139 HexagonExpandCondsets() :
141 LIS(nullptr), CoaLimitActive(
false),
142 TfrLimitActive(
false), CoaCounter(0), TfrCounter(0) {
150 StringRef getPassName()
const override {
return "Hexagon Expand Condsets"; }
170 bool CoaLimitActive, TfrLimitActive;
171 unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter;
175 Sub(Op.getSubReg()) {}
176 RegisterRef(
unsigned R = 0,
unsigned S = 0) :
Reg(R), Sub(S) {}
179 return Reg == RR.Reg && Sub == RR.Sub;
183 return Reg < RR.Reg || (
Reg == RR.Reg && Sub < RR.Sub);
190 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
191 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
192 unsigned getMaskForSub(
unsigned Sub);
196 void addRefToMap(RegisterRef RR, ReferenceMap &Map,
unsigned Exec);
197 bool isRefInMap(RegisterRef, ReferenceMap &Map,
unsigned Exec);
200 void updateKillFlags(
unsigned Reg);
201 void updateDeadFlags(
unsigned Reg);
202 void recalculateLiveInterval(
unsigned Reg);
205 bool UpdateKills,
bool UpdateDeads);
211 bool ReadUndef,
bool ImpUse);
217 bool canMoveOver(
MachineInstr &
MI, ReferenceMap &Defs, ReferenceMap &Uses);
222 std::set<unsigned> &UpdRegs);
223 void renameInRange(RegisterRef RO, RegisterRef
RN,
unsigned PredR,
226 bool predicate(
MachineInstr &TfrI,
bool Cond, std::set<unsigned> &UpdRegs);
228 std::set<unsigned> &UpdRegs);
230 bool isIntReg(RegisterRef RR,
unsigned &BW);
232 bool coalesceRegisters(RegisterRef R1, RegisterRef
R2);
234 std::set<unsigned> &UpdRegs);
248 "Hexagon Expand Condsets",
false,
false)
255 unsigned HexagonExpandCondsets::getMaskForSub(
unsigned Sub) {
257 case Hexagon::isub_lo:
258 case Hexagon::vsub_lo:
260 case Hexagon::isub_hi:
261 case Hexagon::vsub_hi:
263 case Hexagon::NoSubRegister:
272 case Hexagon::C2_mux:
273 case Hexagon::C2_muxii:
274 case Hexagon::C2_muxir:
275 case Hexagon::C2_muxri:
276 case Hexagon::PS_pselect:
283 LaneBitmask HexagonExpandCondsets::getLaneMask(
unsigned Reg,
unsigned Sub) {
285 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
286 :
MRI->getMaxLaneMaskForVReg(Reg);
289 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
291 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
292 ReferenceMap::iterator
F = Map.find(RR.Reg);
294 Map.insert(std::make_pair(RR.Reg, Mask));
299 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
301 ReferenceMap::iterator F = Map.find(RR.Reg);
304 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
305 if (Mask & F->second)
310 void HexagonExpandCondsets::updateKillFlags(
unsigned Reg) {
315 if (!
Op.isReg() || !
Op.isUse() ||
Op.getReg() !=
Reg)
318 if ((SLM & LM) == SLM) {
329 if (!
I->end.isRegister())
333 auto NextI = std::next(
I);
334 if (NextI !=
E && NextI->start.isRegister()) {
335 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
336 if (HII->isPredicated(*DefI))
339 bool WholeReg =
true;
343 return F != S.end() &&
I->end == F->end;
349 KillAt(
I->end, S.LaneMask);
355 KillAt(
I->end,
MRI->getMaxLaneMaskForVReg(Reg));
359 void HexagonExpandCondsets::updateDeadsInRange(
unsigned Reg,
LaneBitmask LM,
366 if (!
Op.isReg() || !
Op.isDef())
368 unsigned DR =
Op.getReg(), DSR =
Op.getSubReg();
372 return (SLM & LM).any();
385 if (
D != Dest && MDT->dominates(
D, Dest))
390 for (
unsigned i = 0;
i < Work.size(); ++
i) {
407 for (
auto &Seg : Range) {
408 if (!Seg.start.isRegister())
410 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
412 if (HII->isPredicated(*DefI))
420 for (
auto &SI : PredDefs) {
422 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB),
SI);
423 if (
P.first !=
nullptr ||
P.second)
430 for (
auto &SI : PredDefs) {
446 if (Dominate(Defs, BB))
451 LIS->extendToIndices(Range, ExtTo, Undefs);
456 std::set<RegisterRef> DefRegs;
457 for (
auto &Seg : Range) {
458 if (!Seg.start.isRegister())
460 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
462 if (Seg.start.isDead() || !IsRegDef(
Op))
471 for (
auto &Seg : Range) {
472 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
474 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
475 if (!HII->isPredicated(*DefI))
479 std::set<RegisterRef> ImpUses;
481 if (
Op.isReg() &&
Op.isDef() && DefRegs.count(
Op))
486 for (RegisterRef R : ImpUses)
491 void HexagonExpandCondsets::updateDeadFlags(
unsigned Reg) {
495 updateDeadsInRange(Reg, S.LaneMask, S);
496 LIS->shrinkToUses(S, Reg);
499 LIS->constructMainRangeFromSubranges(LI);
501 updateDeadsInRange(Reg,
MRI->getMaxLaneMaskForVReg(Reg), LI);
505 void HexagonExpandCondsets::recalculateLiveInterval(
unsigned Reg) {
506 LIS->removeInterval(Reg);
507 LIS->createAndComputeVirtRegInterval(Reg);
510 void HexagonExpandCondsets::removeInstr(
MachineInstr &MI) {
511 LIS->RemoveMachineInstrFromMaps(MI);
516 bool Recalc,
bool UpdateKills,
bool UpdateDeads) {
517 UpdateKills |= UpdateDeads;
518 for (
auto R : RegSet) {
520 recalculateLiveInterval(R);
522 MRI->clearKillFlags(R);
529 LIS->getInterval(R).verify();
535 unsigned HexagonExpandCondsets::getCondTfrOpcode(
const MachineOperand &SO,
537 using namespace Hexagon;
545 PhysR = *VC->
begin();
550 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
554 return IfTrue ? A2_tfrt : A2_tfrf;
556 return IfTrue ? A2_tfrpt : A2_tfrpf;
561 return IfTrue ? C2_cmoveit : C2_cmoveif;
572 bool PredSense,
bool ReadUndef,
bool ImpUse) {
583 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
590 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
591 SrcState &= ~RegState
::Kill;
593 .addReg(DstR, DstState, DstSR)
598 .addReg(DstR, DstState, DstSR)
603 DEBUG(
dbgs() <<
"created an initial copy: " << *MIB);
610 std::set<unsigned> &UpdRegs) {
611 if (TfrLimitActive) {
612 if (TfrCounter >= TfrLimit)
621 unsigned DR = MD.getReg(), DSR = MD.getSubReg();
622 bool ReadUndef = MD.isUndef();
632 if (RT == RegisterRef(SF)) {
633 MI.
setDesc(HII->get(TargetOpcode::COPY));
647 genCondTfrFor(ST, At, DR, DSR, MP,
true, ReadUndef,
false);
649 genCondTfrFor(SF, At, DR, DSR, MP,
false, ReadUndef,
true);
650 LIS->InsertMachineInstrInMaps(*TfrT);
651 LIS->InsertMachineInstrInMaps(*TfrF);
656 UpdRegs.insert(
Op.getReg());
662 bool HexagonExpandCondsets::isPredicable(
MachineInstr *MI) {
663 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
670 if (!
Op.isReg() || !
Op.isDef())
677 if (Mo->isVolatile())
685 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
692 bool PredValid =
true;
698 if (PredValid && HII->isPredicated(*MI)) {
699 if (MI->
readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
706 if (!
Op.isReg() || !
Op.isDef())
709 if (RR.Reg == PredR) {
713 if (RR.Reg != RD.Reg)
718 if (RR.Sub == RD.Sub)
720 if (RR.Sub == 0 || RD.Sub == 0)
734 bool HexagonExpandCondsets::canMoveOver(
MachineInstr &MI, ReferenceMap &Defs,
735 ReferenceMap &Uses) {
749 if (isRefInMap(RR, Defs, Exec_Then))
752 if (
Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
763 if (!IsLoad && !IsStore)
765 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
785 bool Conflict = (L && IsStore) || S;
794 void HexagonExpandCondsets::predicateAt(
const MachineOperand &DefOp,
798 std::set<unsigned> &UpdRegs) {
813 unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
839 for (
unsigned i = 0;
i < NR; ++
i)
845 LIS->InsertMachineInstrInMaps(*NewI);
849 UpdRegs.insert(
Op.getReg());
855 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef
RN,
863 if (!HII->isPredicated(*MI))
865 if (!MI->
readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
869 if (!
Op.isReg() || RO != RegisterRef(
Op))
872 Op.setSubReg(RN.Sub);
874 assert(!
Op.isDef() &&
"Not expecting a def");
882 bool HexagonExpandCondsets::predicate(
MachineInstr &TfrI,
bool Cond,
883 std::set<unsigned> &UpdRegs) {
887 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
888 DEBUG(
dbgs() <<
"\nattempt to predicate if-" << (Cond ?
"true" :
"false")
905 unsigned PredR = MP.
getReg();
906 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
907 if (!DefI || !isPredicable(DefI))
910 DEBUG(
dbgs() <<
"Source def: " << *DefI);
915 ReferenceMap Uses, Defs;
921 bool PredValid =
true;
923 if (!I->modifiesRegister(PredR,
nullptr))
935 unsigned Exec = Exec_Then | Exec_Else;
936 if (PredValid && HII->isPredicated(*MI) && MI->
readsRegister(PredR))
937 Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
953 ReferenceMap &Map =
Op.isDef() ? Defs : Uses;
954 if (
Op.isDef() &&
Op.isUndef()) {
955 assert(RR.Sub &&
"Expecting a subregister on <def,read-undef>");
961 addRefToMap(RR, Map, Exec);
978 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else))
987 bool CanUp = canMoveOver(TfrI, Defs, Uses);
988 bool CanDown = canMoveOver(*DefI, Defs, Uses);
992 if (!canMoveMemTo(*DefI, TfrI,
true))
995 DEBUG(
dbgs() <<
"Can move up: " << (CanUp ?
"yes" :
"no")
996 <<
", can move down: " << (CanDown ?
"yes\n" :
"no\n"));
999 predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs);
1001 predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs);
1006 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt);
1007 UpdRegs.insert(RT.Reg);
1017 std::set<unsigned> &UpdRegs) {
1018 bool Changed =
false;
1020 for (I = B.
begin(), E = B.
end(); I !=
E; I = NextI) {
1021 NextI = std::next(I);
1022 unsigned Opc = I->getOpcode();
1023 if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
1024 bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
1028 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1029 for (
auto &
Op : I->operands())
1031 UpdRegs.insert(
Op.getReg());
1045 if (RC == &Hexagon::IntRegsRegClass) {
1049 if (RC == &Hexagon::DoubleRegsRegClass) {
1050 BW = (RR.Sub != 0) ? 32 : 64;
1056 bool HexagonExpandCondsets::isIntraBlocks(
LiveInterval &LI) {
1069 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef
R2) {
1070 if (CoaLimitActive) {
1071 if (CoaCounter >= CoaLimit)
1078 if (
MRI->isLiveIn(R1.Reg))
1080 if (
MRI->isLiveIn(R2.Reg))
1091 DEBUG(
dbgs() <<
"compatible registers: ("
1092 << (Overlap ?
"overlap" :
"disjoint") <<
")\n "
1093 <<
PrintReg(R1.Reg, TRI, R1.Sub) <<
" " << L1 <<
"\n "
1094 <<
PrintReg(R2.Reg, TRI, R2.Sub) <<
" " << L2 <<
"\n");
1095 if (R1.Sub || R2.Sub)
1103 if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
1106 MRI->replaceRegWith(R2.Reg, R1.Reg);
1112 VNInfo *NewVN, *OldVN = I->valno;
1113 ValueInfoMap::iterator F = VM.find(OldVN);
1114 if (F == VM.end()) {
1115 NewVN = L1.
getNextValue(I->valno->def, LIS->getVNInfoAllocator());
1116 VM.insert(std::make_pair(OldVN, NewVN));
1124 LIS->removeInterval(R2.Reg);
1126 updateKillFlags(R1.Reg);
1127 DEBUG(
dbgs() <<
"coalesced: " << L1 <<
"\n");
1136 bool HexagonExpandCondsets::coalesceSegments(
1138 std::set<unsigned> &UpdRegs) {
1142 if (!S1.
isReg() && !S2.isReg())
1147 bool Changed =
false;
1149 RegisterRef RD = CI->getOperand(0);
1150 RegisterRef
RP = CI->getOperand(1);
1172 RegisterRef RS = S1;
1173 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg,
true);
1175 Done = coalesceRegisters(RD, RegisterRef(S1));
1177 UpdRegs.insert(RD.Reg);
1178 UpdRegs.insert(S1.
getReg());
1182 if (!Done && S2.isReg()) {
1183 RegisterRef RS = S2;
1184 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg,
false);
1186 Done = coalesceRegisters(RD, RegisterRef(S2));
1188 UpdRegs.insert(RD.Reg);
1189 UpdRegs.insert(S2.getReg());
1198 bool HexagonExpandCondsets::runOnMachineFunction(
MachineFunction &MF) {
1204 MDT = &getAnalysis<MachineDominatorTree>();
1205 LIS = &getAnalysis<LiveIntervals>();
1208 DEBUG(LIS->print(
dbgs() <<
"Before expand-condsets\n",
1211 bool Changed =
false;
1212 std::set<unsigned> CoalUpd, PredUpd;
1222 Changed |= coalesceSegments(Condsets, CoalUpd);
1229 std::set<unsigned> KillUpd;
1232 if (
Op.isReg() &&
Op.isUse())
1233 if (!CoalUpd.count(
Op.getReg()))
1234 KillUpd.insert(
Op.getReg());
1236 DEBUG(LIS->print(
dbgs() <<
"After coalescing\n",
1237 MF.getFunction()->getParent()));
1244 Changed |=
split(*MI, PredUpd);
1253 DEBUG(LIS->print(
dbgs() <<
"After splitting\n",
1254 MF.getFunction()->getParent()));
1261 Changed |= predicateInBlock(B, PredUpd);
1262 DEBUG(LIS->print(
dbgs() <<
"After predicating\n",
1263 MF.getFunction()->getParent()));
1265 PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
1270 LIS->print(
dbgs() <<
"After expand-condsets\n",
1271 MF.getFunction()->getParent());
1282 return new HexagonExpandCondsets();
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
char & HexagonExpandCondsetsID
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Segments::iterator iterator
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
static void updateLiveness(MachineFunction &MF)
Helper function to update the liveness information for the callee-saved registers.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
FunctionPass * createHexagonExpandCondsets()
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
A live range for subregisters.
This represents a simple continuous liveness interval for a value.
static std::pair< StringRef, StringRef > split(StringRef Str, char Separator)
Checked version of split, to ensure mandatory subparts.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
iterator_range< mmo_iterator > memoperands()
VNInfo - Value Number Information.
iterator_range< mop_iterator > operands()
This class represents the liveness of a register, stack slot, etc.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
void clearKillInfo()
Clears kill flags on all operands.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
expand Hexagon Expand Condsets
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineBasicBlock & front() const
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
bool insert(const value_type &X)
Insert a new element into the SetVector.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
mmo_iterator memoperands_end() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
static cl::opt< unsigned > OptCoaLimit("expand-condsets-coa-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"))
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
FunctionPass class - This class is used to implement most global optimizations.
iterator_range< pred_iterator > predecessors()
static Expected< BitVector > expand(StringRef S, StringRef Original)
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
expand Hexagon Expand false
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static cl::opt< unsigned > OptTfrLimit("expand-condsets-tfr-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"))
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
bool operator!=(uint64_t V1, const APInt &V2)
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void verify(const MachineRegisterInfo *MRI=nullptr) const
Walks the interval and assert if any invariants fail to hold.
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool operator<(int64_t V1, const APSInt &V2)
virtual const TargetInstrInfo * getInstrInfo() const
Module * getParent()
Get the module that this global value is contained inside of...
A vector that has set insertion semantics.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool isIntReg(unsigned Reg)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
bool operator==(uint64_t V1, const APInt &V2)
INITIALIZE_PASS_BEGIN(HexagonExpandCondsets,"expand-condsets","Hexagon Expand Condsets", false, false) INITIALIZE_PASS_END(HexagonExpandCondsets
bool hasSubRanges() const
Returns true if subregister liveness information is available.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SlotIndex - An opaque wrapper around machine indexes.
void initializeHexagonExpandCondsetsPass(PassRegistry &)
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.