49 if (ARM::tGPRRegClass.hasSubClassEq(RC))
50 return &ARM::tGPRRegClass;
56 unsigned Kind)
const {
59 return &ARM::tGPRRegClass;
64 const DebugLoc &dl,
unsigned DestReg,
65 unsigned SubIdx,
int Val,
84 const DebugLoc &dl,
unsigned DestReg,
85 unsigned SubIdx,
int Val,
105 const DebugLoc &dl,
unsigned DestReg,
unsigned SubIdx,
int Val,
111 "Thumb1 does not have ldr to high register");
125 const DebugLoc &dl,
unsigned DestReg,
unsigned BaseReg,
int NumBytes,
137 if (NumBytes < 0 && !isHigh && CanChangeCC) {
139 NumBytes = -NumBytes;
141 unsigned LdReg = DestReg;
142 if (DestReg == ARM::SP)
143 assert(BaseReg == ARM::SP &&
"Unexpected!");
147 if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
151 }
else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
159 BuildMI(MBB, MBBI, dl, TII.
get(ARM::t2MOVi32imm), LdReg)
166 int Opc = (isSub) ? ARM::tSUBrr
167 : ((isHigh || !CanChangeCC) ? ARM::tADDhirr : ARM::tADDrr);
169 if (Opc != ARM::tADDhirr)
171 if (DestReg == ARM::SP || isSub)
184 const DebugLoc &dl,
unsigned DestReg,
185 unsigned BaseReg,
int NumBytes,
189 bool isSub = NumBytes < 0;
190 unsigned Bytes = (
unsigned)NumBytes;
191 if (isSub) Bytes = -NumBytes;
194 unsigned CopyBits = 0;
195 unsigned CopyScale = 1;
196 bool CopyNeedsCC =
false;
198 unsigned ExtraBits = 0;
199 unsigned ExtraScale = 1;
200 bool ExtraNeedsCC =
false;
215 if (DestReg == ARM::SP) {
216 if (BaseReg == ARM::SP) {
221 CopyOpc = ARM::tMOVr;
224 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
228 if (BaseReg == ARM::SP) {
230 assert(!isSub &&
"Thumb1 does not have tSUBrSPi");
231 CopyOpc = ARM::tADDrSPi;
234 }
else if (DestReg == BaseReg) {
239 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
244 CopyOpc = ARM::tMOVr;
247 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
251 if (DestReg == BaseReg) {
256 CopyOpc = ARM::tMOVr;
264 assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
265 "Unaligned offset, but all instructions require alignment");
267 unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
269 if (CopyOpc && Bytes < CopyScale) {
270 CopyOpc = ARM::tMOVr;
275 unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale;
276 unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0;
277 unsigned RangeAfterCopy = (CopyRange > Bytes) ? 0 : (Bytes - CopyRange);
281 assert(RangeAfterCopy % ExtraScale == 0 &&
282 "Extra instruction requires immediate to be aligned");
284 unsigned RequiredExtraInstrs;
286 RequiredExtraInstrs =
alignTo(RangeAfterCopy, ExtraRange) / ExtraRange;
287 else if (RangeAfterCopy > 0)
289 RequiredExtraInstrs = 1000000;
291 RequiredExtraInstrs = 0;
292 unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
293 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
296 if (RequiredInstrs > Threshold) {
298 DestReg, BaseReg, NumBytes,
true,
305 unsigned CopyImm =
std::min(Bytes, CopyRange) / CopyScale;
306 Bytes -= CopyImm * CopyScale;
312 if (CopyOpc != ARM::tMOVr) {
322 unsigned ExtraImm =
std::min(Bytes, ExtraRange) / ExtraScale;
323 Bytes -= ExtraImm * ExtraScale;
355 unsigned FrameRegIdx,
356 unsigned FrameReg,
int &
Offset,
361 "This isn't needed for thumb2!");
368 if (Opcode == ARM::tADDframe) {
380 unsigned ImmIdx = FrameRegIdx + 1;
382 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
385 Offset += InstrOffs * Scale;
386 assert((Offset & (Scale - 1)) == 0 &&
"Can't encode this offset!");
390 int ImmedOffset = Offset / Scale;
391 unsigned Mask = (1 << NumBits) - 1;
393 if ((
unsigned)Offset <= Mask * Scale) {
401 if (NewOpc != Opcode && FrameReg != ARM::SP)
408 Mask = (1 << NumBits) - 1;
412 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
416 ImmedOffset = ImmedOffset &
Mask;
418 Offset &= ~(Mask * Scale);
441 assert (Done &&
"Unable to resolve frame index!");
450 unsigned Reg)
const {
454 return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg);
472 if (II->isDebugValue())
475 for (
unsigned i = 0, e = II->getNumOperands();
i != e; ++
i) {
485 if (MO.
getReg() == ARM::R12) {
500 int SPAdj,
unsigned FIOperandNum,
516 unsigned FrameReg = ARM::SP;
539 "Cannot use SP to access the emergency spill slot in "
540 "functions without a reserved call frame");
542 "Cannot use SP to access the emergency spill slot in "
543 "functions with variable sized frame objects");
549 MI.
getOperand(FIOperandNum). ChangeToRegister(FrameReg,
false );
556 "This eliminateFrameIndex only supports Thumb1!");
563 assert(Offset &&
"This code isn't needed if offset already handled!");
576 if (Opcode == ARM::tLDRspi) {
579 Offset,
false, TII, *
this);
589 MI.
setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
600 if (Opcode == ARM::tSTRspi) {
603 Offset,
false, TII, *
this);
611 MI.
setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
static void removeOperands(MachineInstr &MI, unsigned i)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isThumbFunction() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
static void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=MachineInstr::NoFlags)
emitThumbRegPlusImmInReg - Emits a series of instructions to materialize a destreg = basereg + immedi...
bool isThumb1Only() const
static unsigned convertToNonSPOpcode(unsigned Opcode)
convertToNonSPOpcode - Change the opcode to the non-SP version, because we're replacing the frame ind...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const ARMBaseInstrInfo * getInstrInfo() const override
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const override
saveScavengerRegister - Spill the register so it can be used by the register scavenger.
static void emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static void emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
This is an important base class in LLVM.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getFramePtrSpillOffset() const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const ARMFrameLowering * getFrameLowering() const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool genExecuteOnly() const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0, unsigned MIFlags=MachineInstr::NoFlags) const override
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasBasePointer(const MachineFunction &MF) const
AddrMode
ARM Addressing Modes.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
cl::opt< bool > ReuseFrameIndexVals
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
unsigned BasePtr
BasePtr - ARM physical register used as a base ptr in complex stack frames.
bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)