63 #define DEBUG_TYPE "ppcfastisel"
82 : BaseType(RegBase),
Offset(0) {
87 class PPCFastISel final :
public FastISel {
102 TII(*PPCSubTarget->getInstrInfo()),
103 TLI(*PPCSubTarget->getTargetLowering()),
108 bool fastSelectInstruction(
const Instruction *
I)
override;
109 unsigned fastMaterializeConstant(
const Constant *
C)
override;
110 unsigned fastMaterializeAlloca(
const AllocaInst *AI)
override;
113 bool fastLowerArguments()
override;
114 unsigned fastEmit_i(
MVT Ty,
MVT RetTy,
unsigned Opc, uint64_t Imm)
override;
115 unsigned fastEmitInst_ri(
unsigned MachineInstOpcode,
117 unsigned Op0,
bool Op0IsKill,
119 unsigned fastEmitInst_r(
unsigned MachineInstOpcode,
121 unsigned Op0,
bool Op0IsKill);
122 unsigned fastEmitInst_rr(
unsigned MachineInstOpcode,
124 unsigned Op0,
bool Op0IsKill,
125 unsigned Op1,
bool Op1IsKill);
127 bool fastLowerCall(CallLoweringInfo &CLI)
override;
137 bool SelectIToFP(
const Instruction *I,
bool IsSigned);
138 bool SelectFPToI(
const Instruction *I,
bool IsSigned);
139 bool SelectBinaryIntOp(
const Instruction *I,
unsigned ISDOpcode);
146 bool isTypeLegal(
Type *Ty,
MVT &VT);
147 bool isLoadTypeLegal(
Type *Ty,
MVT &VT);
148 bool isValueAvailable(
const Value *V)
const;
150 return RC->
getID() == PPC::VSFRCRegClassID;
153 return RC->
getID() == PPC::VSSRCRegClassID;
155 bool PPCEmitCmp(
const Value *Src1Value,
const Value *Src2Value,
156 bool isZExt,
unsigned DestReg);
157 bool PPCEmitLoad(
MVT VT,
unsigned &ResultReg,
Address &Addr,
159 unsigned FP64LoadOpc = PPC::LFD);
160 bool PPCEmitStore(
MVT VT,
unsigned SrcReg,
Address &Addr);
161 bool PPCComputeAddress(
const Value *Obj,
Address &Addr);
162 void PPCSimplifyAddress(
Address &Addr,
bool &UseOffset,
164 bool PPCEmitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
165 unsigned DestReg,
bool IsZExt);
169 bool UseSExt =
true);
170 unsigned PPCMaterialize32BitInt(int64_t Imm,
172 unsigned PPCMaterialize64BitInt(int64_t Imm,
175 unsigned SrcReg,
bool IsSigned);
176 unsigned PPCMoveToFPReg(
MVT VT,
unsigned SrcReg,
bool IsSigned);
188 bool finishCall(
MVT RetVT, CallLoweringInfo &CLI,
unsigned &NumBytes);
192 #include "PPCGenFastISel.inc"
198 #include "PPCGenCallingConv.inc"
204 return CC_PPC32_SVR4;
206 return CC_PPC32_SVR4_ByVal;
208 return CC_PPC32_SVR4_VarArg;
282 bool PPCFastISel::isTypeLegal(
Type *Ty,
MVT &VT) {
283 EVT Evt = TLI.getValueType(DL, Ty,
true);
291 return TLI.isTypeLegal(VT);
296 bool PPCFastISel::isLoadTypeLegal(
Type *Ty,
MVT &VT) {
297 if (isTypeLegal(Ty, VT))
return true;
308 bool PPCFastISel::isValueAvailable(
const Value *V)
const {
309 if (!isa<Instruction>(V))
312 const auto *
I = cast<Instruction>(V);
313 return FuncInfo.MBBMap[
I->getParent()] == FuncInfo.MBB;
318 bool PPCFastISel::PPCComputeAddress(
const Value *Obj,
Address &Addr) {
319 const User *U =
nullptr;
320 unsigned Opcode = Instruction::UserOp1;
321 if (
const Instruction *
I = dyn_cast<Instruction>(Obj)) {
324 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
325 FuncInfo.MBBMap[
I->getParent()] == FuncInfo.MBB) {
326 Opcode =
I->getOpcode();
329 }
else if (
const ConstantExpr *
C = dyn_cast<ConstantExpr>(Obj)) {
330 Opcode =
C->getOpcode();
337 case Instruction::BitCast:
339 return PPCComputeAddress(U->
getOperand(0), Addr);
340 case Instruction::IntToPtr:
343 TLI.getPointerTy(DL))
344 return PPCComputeAddress(U->
getOperand(0), Addr);
346 case Instruction::PtrToInt:
348 if (TLI.getValueType(DL, U->
getType()) == TLI.getPointerTy(DL))
349 return PPCComputeAddress(U->
getOperand(0), Addr);
351 case Instruction::GetElementPtr: {
353 long TmpOffset = Addr.Offset;
359 II !=
IE; ++II, ++GTI) {
363 unsigned Idx = cast<ConstantInt>(
Op)->getZExtValue();
368 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
370 TmpOffset += CI->getSExtValue() * S;
373 if (canFoldAddIntoGEP(U, Op)) {
376 cast<ConstantInt>(cast<AddOperator>(
Op)->getOperand(1));
379 Op = cast<AddOperator>(
Op)->getOperand(0);
383 goto unsupported_gep;
389 Addr.Offset = TmpOffset;
390 if (PPCComputeAddress(U->
getOperand(0), Addr))
return true;
398 case Instruction::Alloca: {
401 FuncInfo.StaticAllocaMap.find(AI);
402 if (SI != FuncInfo.StaticAllocaMap.end()) {
403 Addr.BaseType = Address::FrameIndexBase;
404 Addr.Base.FI = SI->second;
418 if (Addr.Base.Reg == 0)
419 Addr.Base.Reg = getRegForValue(Obj);
423 if (Addr.Base.Reg != 0)
424 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
426 return Addr.Base.Reg != 0;
432 void PPCFastISel::PPCSimplifyAddress(
Address &Addr,
bool &UseOffset,
433 unsigned &IndexReg) {
442 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
443 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
444 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDI8),
445 ResultReg).addFrameIndex(Addr.Base.FI).
addImm(0);
446 Addr.Base.Reg = ResultReg;
447 Addr.BaseType = Address::RegBase;
454 IndexReg = PPCMaterializeInt(Offset,
MVT::i64);
455 assert(IndexReg &&
"Unexpected error in PPCMaterializeInt!");
462 bool PPCFastISel::PPCEmitLoad(
MVT VT,
unsigned &ResultReg,
Address &Addr,
464 bool IsZExt,
unsigned FP64LoadOpc) {
466 bool UseOffset =
true;
476 (ResultReg ?
MRI.getRegClass(ResultReg) :
478 (VT ==
MVT::f64 ? &PPC::F8RCRegClass :
479 (VT ==
MVT::f32 ? &PPC::F4RCRegClass :
480 (VT ==
MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
481 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
489 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
492 Opc = (IsZExt ? (Is32BitInt ? PPC::LHZ : PPC::LHZ8)
493 : (Is32BitInt ? PPC::LHA : PPC::LHA8));
496 Opc = (IsZExt ? (Is32BitInt ? PPC::LWZ : PPC::LWZ8)
497 : (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
498 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
504 "64-bit load with 32-bit target??");
505 UseOffset = ((Addr.Offset & 3) == 0);
517 unsigned IndexReg = 0;
518 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
522 bool IsVSSRC = isVSSRCRegClass(UseRC);
523 bool IsVSFRC = isVSFRCRegClass(UseRC);
524 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
525 bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD;
526 if ((Is32VSXLoad || Is64VSXLoad) &&
527 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
528 (Addr.Offset == 0)) {
533 ResultReg = createResultReg(UseRC);
538 if (Addr.BaseType == Address::FrameIndexBase) {
540 if (Is32VSXLoad || Is64VSXLoad)
return false;
546 MFI.getObjectAlignment(Addr.Base.FI));
548 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
552 }
else if (UseOffset) {
554 if (Is32VSXLoad || Is64VSXLoad)
return false;
556 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
557 .addImm(Addr.Offset).
addReg(Addr.Base.Reg);
566 case PPC::LBZ: Opc = PPC::LBZX;
break;
567 case PPC::LBZ8: Opc = PPC::LBZX8;
break;
568 case PPC::LHZ: Opc = PPC::LHZX;
break;
569 case PPC::LHZ8: Opc = PPC::LHZX8;
break;
570 case PPC::LHA: Opc = PPC::LHAX;
break;
571 case PPC::LHA8: Opc = PPC::LHAX8;
break;
572 case PPC::LWZ: Opc = PPC::LWZX;
break;
573 case PPC::LWZ8: Opc = PPC::LWZX8;
break;
574 case PPC::LWA: Opc = PPC::LWAX;
break;
575 case PPC::LWA_32: Opc = PPC::LWAX_32;
break;
576 case PPC::LD: Opc = PPC::LDX;
break;
577 case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX;
break;
578 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX;
break;
581 auto MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc),
605 if (!isLoadTypeLegal(I->
getType(), VT))
610 if (!PPCComputeAddress(I->
getOperand(0), Addr))
616 unsigned AssignedReg = FuncInfo.ValueMap[
I];
618 AssignedReg ?
MRI.getRegClass(AssignedReg) :
nullptr;
620 unsigned ResultReg = 0;
621 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
623 updateValueMap(I, ResultReg);
628 bool PPCFastISel::PPCEmitStore(
MVT VT,
unsigned SrcReg,
Address &Addr) {
629 assert(SrcReg &&
"Nothing to store!");
631 bool UseOffset =
true;
640 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
643 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
646 assert(Is32BitInt &&
"Not GPRC for i32??");
651 UseOffset = ((Addr.Offset & 3) == 0);
663 unsigned IndexReg = 0;
664 PPCSimplifyAddress(Addr, UseOffset, IndexReg);
668 bool IsVSSRC = isVSSRCRegClass(RC);
669 bool IsVSFRC = isVSFRCRegClass(RC);
670 bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
671 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
672 if ((Is32VSXStore || Is64VSXStore) &&
673 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
674 (Addr.Offset == 0)) {
681 if (Addr.BaseType == Address::FrameIndexBase) {
683 if (Is32VSXStore || Is64VSXStore)
return false;
689 MFI.getObjectAlignment(Addr.Base.FI));
691 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc))
698 }
else if (UseOffset) {
700 if (Is32VSXStore || Is64VSXStore)
703 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc))
704 .addReg(SrcReg).
addImm(Addr.Offset).
addReg(Addr.Base.Reg);
713 case PPC::STB: Opc = PPC::STBX;
break;
714 case PPC::STH : Opc = PPC::STHX;
break;
715 case PPC::STW : Opc = PPC::STWX;
break;
716 case PPC::STB8: Opc = PPC::STBX8;
break;
717 case PPC::STH8: Opc = PPC::STHX8;
break;
718 case PPC::STW8: Opc = PPC::STWX8;
break;
719 case PPC::STD: Opc = PPC::STDX;
break;
720 case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX;
break;
721 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX;
break;
724 auto MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc))
732 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
734 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
741 bool PPCFastISel::SelectStore(
const Instruction *I) {
751 if (!isLoadTypeLegal(Op0->
getType(), VT))
755 SrcReg = getRegForValue(Op0);
761 if (!PPCComputeAddress(I->
getOperand(1), Addr))
764 if (!PPCEmitStore(VT, SrcReg, Addr))
771 bool PPCFastISel::SelectBranch(
const Instruction *I) {
779 if (isValueAvailable(CI)) {
787 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
792 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
794 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
798 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::BCC))
800 finishCondBranch(BI->
getParent(), TBB, FBB);
805 uint64_t Imm = CI->getZExtValue();
807 fastEmitBranch(Target, DbgLoc);
822 bool PPCFastISel::PPCEmitCmp(
const Value *SrcValue1,
const Value *SrcValue2,
823 bool IsZExt,
unsigned DestReg) {
825 EVT SrcEVT = TLI.getValueType(DL, Ty,
true);
830 if (SrcVT ==
MVT::i1 && PPCSubTarget->useCRBits())
842 if (
const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
845 const APInt &CIVal = ConstInt->getValue();
853 bool NeedsExt =
false;
855 default:
return false;
857 CmpOpc = PPC::FCMPUS;
860 CmpOpc = PPC::FCMPUD;
869 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
871 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
875 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
877 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
881 unsigned SrcReg1 = getRegForValue(SrcValue1);
885 unsigned SrcReg2 = 0;
887 SrcReg2 = getRegForValue(SrcValue2);
893 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
894 if (!PPCEmitIntExt(SrcVT, SrcReg1,
MVT::i32, ExtReg, IsZExt))
899 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
900 if (!PPCEmitIntExt(SrcVT, SrcReg2,
MVT::i32, ExtReg, IsZExt))
907 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(CmpOpc), DestReg)
908 .addReg(SrcReg1).
addReg(SrcReg2);
910 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(CmpOpc), DestReg)
911 .addReg(SrcReg1).
addImm(Imm);
917 bool PPCFastISel::SelectFPExt(
const Instruction *I) {
919 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
920 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
925 unsigned SrcReg = getRegForValue(Src);
930 updateValueMap(I, SrcReg);
935 bool PPCFastISel::SelectFPTrunc(
const Instruction *I) {
937 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
938 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
943 unsigned SrcReg = getRegForValue(Src);
948 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
949 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::FRSP), DestReg)
952 updateValueMap(I, DestReg);
963 unsigned PPCFastISel::PPCMoveToFPReg(
MVT SrcVT,
unsigned SrcReg,
968 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
976 Addr.BaseType = Address::FrameIndexBase;
977 Addr.Base.FI = MFI.CreateStackObject(8, 8,
false);
980 if (!PPCEmitStore(
MVT::i64, SrcReg, Addr))
985 unsigned LoadOpc = PPC::LFD;
990 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
991 }
else if (PPCSubTarget->hasLFIWAX()) {
993 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
998 unsigned ResultReg = 0;
999 if (!PPCEmitLoad(
MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
1008 bool PPCFastISel::SelectIToFP(
const Instruction *I,
bool IsSigned) {
1011 if (!isTypeLegal(DstTy, DstVT))
1018 EVT SrcEVT = TLI.getValueType(DL, Src->
getType(),
true);
1028 unsigned SrcReg = getRegForValue(Src);
1034 if (!IsSigned && !PPCSubTarget->hasFPCVT())
1042 if (DstVT ==
MVT::f32 && !PPCSubTarget->hasFPCVT())
1047 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1048 if (!PPCEmitIntExt(SrcVT, SrcReg,
MVT::i64, TmpReg, !IsSigned))
1055 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1061 unsigned DestReg = createResultReg(RC);
1070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1073 updateValueMap(I, DestReg);
1082 unsigned PPCFastISel::PPCMoveToIntReg(
const Instruction *I,
MVT VT,
1083 unsigned SrcReg,
bool IsSigned) {
1089 Addr.BaseType = Address::FrameIndexBase;
1090 Addr.Base.FI = MFI.CreateStackObject(8, 8,
false);
1093 if (!PPCEmitStore(
MVT::f64, SrcReg, Addr))
1099 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
1103 unsigned AssignedReg = FuncInfo.ValueMap[
I];
1105 AssignedReg ?
MRI.getRegClass(AssignedReg) :
nullptr;
1107 unsigned ResultReg = 0;
1108 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1117 bool PPCFastISel::SelectFPToI(
const Instruction *I,
bool IsSigned) {
1120 if (!isTypeLegal(DstTy, DstVT))
1127 if (DstVT ==
MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT())
1132 if (!isTypeLegal(SrcTy, SrcVT))
1138 unsigned SrcReg = getRegForValue(Src);
1145 if (InRC == &PPC::F4RCRegClass) {
1146 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1147 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1148 TII.get(TargetOpcode::COPY), TmpReg)
1155 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1167 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1171 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1175 updateValueMap(I, IntReg);
1181 bool PPCFastISel::SelectBinaryIntOp(
const Instruction *I,
unsigned ISDOpcode) {
1182 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
1192 unsigned AssignedReg = FuncInfo.ValueMap[
I];
1194 (AssignedReg ?
MRI.getRegClass(AssignedReg) :
1195 &PPC::GPRC_and_GPRC_NOR0RegClass);
1199 switch (ISDOpcode) {
1200 default:
return false;
1202 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1205 Opc = IsGPRC ?
PPC::OR : PPC::OR8;
1208 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1212 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1213 unsigned SrcReg1 = getRegForValue(I->
getOperand(0));
1214 if (SrcReg1 == 0)
return false;
1218 const APInt &CIVal = ConstInt->getValue();
1227 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1231 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1244 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1253 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1260 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc),
1264 updateValueMap(I, ResultReg);
1271 unsigned SrcReg2 = getRegForValue(I->
getOperand(1));
1272 if (SrcReg2 == 0)
return false;
1278 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ResultReg)
1279 .addReg(SrcReg1).
addReg(SrcReg2);
1280 updateValueMap(I, ResultReg);
1298 unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1299 CCInfo.AllocateStack(LinkageSize, 8);
1301 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1304 for (
unsigned I = 0,
E = ArgLocs.
size(); I !=
E; ++
I) {
1320 NumBytes = CCInfo.getNextStackOffset();
1328 NumBytes = std::max(NumBytes, LinkageSize + 64);
1331 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1332 TII.get(
TII.getCallFrameSetupOpcode()))
1338 unsigned NextGPR = PPC::X3;
1339 unsigned NextFPR = PPC::F1;
1342 for (
unsigned I = 0,
E = ArgLocs.
size(); I !=
E; ++
I) {
1344 unsigned Arg = ArgRegs[VA.
getValNo()];
1356 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1357 unsigned TmpReg = createResultReg(RC);
1358 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg,
false))
1368 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1369 unsigned TmpReg = createResultReg(RC);
1370 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg,
true))
1392 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1393 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1402 bool PPCFastISel::finishCall(
MVT RetVT, CallLoweringInfo &CLI,
unsigned &NumBytes) {
1406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1407 TII.get(
TII.getCallFrameDestroyOpcode()))
1416 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1418 assert(RVLocs.
size() == 1 &&
"No support for multi-reg return values!");
1422 MVT CopyVT = DestVT;
1429 unsigned SourcePhysReg = VA.
getLocReg();
1430 unsigned ResultReg = 0;
1432 if (RetVT == CopyVT) {
1434 ResultReg = createResultReg(CpyRC);
1436 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1437 TII.get(TargetOpcode::COPY), ResultReg)
1438 .addReg(SourcePhysReg);
1442 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1443 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::FRSP),
1444 ResultReg).addReg(SourcePhysReg);
1451 ResultReg = createResultReg(&PPC::GPRCRegClass);
1453 SourcePhysReg -= PPC::X0 - PPC::R0;
1454 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1455 TII.get(TargetOpcode::COPY), ResultReg)
1456 .addReg(SourcePhysReg);
1459 assert(ResultReg &&
"ResultReg unset!");
1460 CLI.InRegs.push_back(SourcePhysReg);
1461 CLI.ResultReg = ResultReg;
1462 CLI.NumResultRegs = 1;
1468 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1470 bool IsTailCall = CLI.IsTailCall;
1471 bool IsVarArg = CLI.IsVarArg;
1472 const Value *Callee = CLI.Callee;
1475 if (!Callee && !Symbol)
1488 Type *RetTy = CLI.RetTy;
1492 else if (!isTypeLegal(RetTy, RetVT) && RetVT !=
MVT::i16 &&
1495 else if (RetVT ==
MVT::i1 && PPCSubTarget->useCRBits())
1505 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1506 if (RVLocs.
size() > 1)
1512 unsigned NumArgs = CLI.OutVals.size();
1527 for (
unsigned i = 0, ie = NumArgs;
i != ie; ++
i) {
1535 Value *ArgValue = CLI.OutVals[
i];
1538 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT !=
MVT::i16 && ArgVT !=
MVT::i8)
1544 unsigned Arg = getRegForValue(ArgValue);
1558 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1559 RegArgs, CC, NumBytes, IsVarArg))
1572 if (CLI.IsPatchPoint)
1573 MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::NOP));
1579 MIB =
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1580 TII.get(PPC::BL8_NOP));
1586 for (
unsigned II = 0,
IE = RegArgs.
size(); II !=
IE; ++II)
1591 PPCFuncInfo->setUsesTOCBasePtr();
1596 MIB.
addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1601 return finishCall(RetVT, CLI, NumBytes);
1605 bool PPCFastISel::SelectRet(
const Instruction *I) {
1607 if (!FuncInfo.CanLowerReturn)
1610 if (TLI.supportSplitCSR(FuncInfo.MF))
1626 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *
Context);
1631 if (ValLocs.size() > 1)
1636 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1647 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1648 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1653 unsigned Reg = getRegForValue(RV);
1659 for (
unsigned i = 0;
i < ValLocs.size(); ++
i) {
1664 unsigned SrcReg = Reg + VA.
getValNo();
1666 EVT RVEVT = TLI.getValueType(DL, RV->
getType());
1672 if (RVVT != DestVT && RVVT !=
MVT::i8 &&
1676 if (RVVT != DestVT) {
1685 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1686 unsigned TmpReg = createResultReg(RC);
1687 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg,
true))
1694 (DestVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1695 unsigned TmpReg = createResultReg(RC);
1696 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg,
false))
1704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1705 TII.get(TargetOpcode::COPY), RetRegs[
i])
1712 TII.get(PPC::BLR8));
1714 for (
unsigned i = 0, e = RetRegs.
size();
i != e; ++
i)
1723 bool PPCFastISel::PPCEmitIntExt(
MVT SrcVT,
unsigned SrcReg,
MVT DestVT,
1724 unsigned DestReg,
bool IsZExt) {
1734 Opc = (DestVT ==
MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1736 Opc = (DestVT ==
MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1739 Opc = PPC::EXTSW_32_64;
1741 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1750 assert(SrcVT ==
MVT::i16 &&
"Unsigned extend from i32 to i32??");
1753 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::RLWINM),
1766 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1767 TII.get(PPC::RLDICL_32_64), DestReg)
1775 bool PPCFastISel::SelectIndirectBr(
const Instruction *I) {
1776 unsigned AddrReg = getRegForValue(I->
getOperand(0));
1780 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::MTCTR8))
1782 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::BCTR8));
1785 for (
const BasicBlock *SuccBB : IB->successors())
1786 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1792 bool PPCFastISel::SelectTrunc(
const Instruction *I) {
1794 EVT SrcVT = TLI.getValueType(DL, Src->
getType(),
true);
1795 EVT DestVT = TLI.getValueType(DL, I->
getType(),
true);
1803 unsigned SrcReg = getRegForValue(Src);
1809 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1810 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1811 TII.get(TargetOpcode::COPY),
1812 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1816 updateValueMap(I, SrcReg);
1821 bool PPCFastISel::SelectIntExt(
const Instruction *I) {
1826 bool IsZExt = isa<ZExtInst>(
I);
1827 unsigned SrcReg = getRegForValue(Src);
1828 if (!SrcReg)
return false;
1830 EVT SrcEVT, DestEVT;
1831 SrcEVT = TLI.getValueType(DL, SrcTy,
true);
1832 DestEVT = TLI.getValueType(DL, DestTy,
true);
1845 unsigned AssignedReg = FuncInfo.ValueMap[
I];
1847 (AssignedReg ?
MRI.getRegClass(AssignedReg) :
1848 (DestVT ==
MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1849 &PPC::GPRC_and_GPRC_NOR0RegClass));
1850 unsigned ResultReg = createResultReg(RC);
1852 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1855 updateValueMap(I, ResultReg);
1861 bool PPCFastISel::fastSelectInstruction(
const Instruction *I) {
1865 return SelectLoad(I);
1867 return SelectStore(I);
1868 case Instruction::Br:
1869 return SelectBranch(I);
1870 case Instruction::IndirectBr:
1871 return SelectIndirectBr(I);
1872 case Instruction::FPExt:
1873 return SelectFPExt(I);
1874 case Instruction::FPTrunc:
1875 return SelectFPTrunc(I);
1876 case Instruction::SIToFP:
1877 return SelectIToFP(I,
true);
1878 case Instruction::UIToFP:
1879 return SelectIToFP(I,
false);
1880 case Instruction::FPToSI:
1881 return SelectFPToI(I,
true);
1882 case Instruction::FPToUI:
1883 return SelectFPToI(I,
false);
1885 return SelectBinaryIntOp(I,
ISD::ADD);
1887 return SelectBinaryIntOp(I,
ISD::OR);
1888 case Instruction::Sub:
1889 return SelectBinaryIntOp(I,
ISD::SUB);
1891 return selectCall(I);
1893 return SelectRet(I);
1894 case Instruction::Trunc:
1895 return SelectTrunc(I);
1896 case Instruction::ZExt:
1897 case Instruction::SExt:
1898 return SelectIntExt(I);
1910 unsigned PPCFastISel::PPCMaterializeFP(
const ConstantFP *CFP,
MVT VT) {
1916 unsigned Align =
DL.getPrefTypeAlignment(CFP->
getType());
1917 assert(Align > 0 &&
"Unexpectedly missing alignment information!");
1918 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1920 (VT ==
MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass;
1921 unsigned DestReg = createResultReg(RC);
1928 unsigned Opc = (VT ==
MVT::f32) ? PPC::LFS : PPC::LFD;
1929 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1931 PPCFuncInfo->setUsesTOCBasePtr();
1934 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtocCPT),
1936 .addConstantPoolIndex(Idx).
addReg(PPC::X2);
1937 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDIStocHA),
1946 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1947 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtocL),
1948 TmpReg2).addConstantPoolIndex(Idx).
addReg(TmpReg);
1949 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1953 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), DestReg)
1964 unsigned PPCFastISel::PPCMaterializeGV(
const GlobalValue *GV,
MVT VT) {
1967 unsigned DestReg = createResultReg(RC);
1982 PPCFuncInfo->setUsesTOCBasePtr();
1985 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtoc),
1987 .addGlobalAddress(GV)
1998 unsigned HighPartReg = createResultReg(RC);
1999 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDIStocHA),
2002 unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
2004 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::LDtocL),
2005 DestReg).addGlobalAddress(GV).
addReg(HighPartReg);
2008 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDItocL),
2018 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2020 unsigned Lo = Imm & 0xFFFF;
2021 unsigned Hi = (Imm >> 16) & 0xFFFF;
2023 unsigned ResultReg = createResultReg(RC);
2027 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2028 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2032 unsigned TmpReg = createResultReg(RC);
2033 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2034 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2036 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2037 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2038 .addReg(TmpReg).
addImm(Lo);
2041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2042 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2050 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2052 unsigned Remainder = 0;
2058 Shift = countTrailingZeros<uint64_t>(Imm);
2059 int64_t ImmSh =
static_cast<uint64_t
>(Imm) >> Shift;
2072 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2080 TmpReg2 = createResultReg(RC);
2081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::RLDICR),
2082 TmpReg2).addReg(TmpReg1).
addImm(Shift).
addImm(63 - Shift);
2086 unsigned TmpReg3,
Hi,
Lo;
2087 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2088 TmpReg3 = createResultReg(RC);
2089 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ORIS8),
2090 TmpReg3).addReg(TmpReg2).
addImm(Hi);
2094 if ((Lo = Remainder & 0xFFFF)) {
2095 unsigned ResultReg = createResultReg(RC);
2096 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ORI8),
2097 ResultReg).addReg(TmpReg3).
addImm(Lo);
2106 unsigned PPCFastISel::PPCMaterializeInt(
const ConstantInt *CI,
MVT VT,
2110 if (VT ==
MVT::i1 && PPCSubTarget->useCRBits()) {
2111 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2112 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2113 TII.get(CI->
isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2122 ((VT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass);
2130 unsigned Opc = (VT ==
MVT::i64) ? PPC::LI8 : PPC::LI;
2131 unsigned ImmReg = createResultReg(RC);
2132 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc), ImmReg)
2139 return PPCMaterialize64BitInt(Imm, RC);
2141 return PPCMaterialize32BitInt(Imm, RC);
2148 unsigned PPCFastISel::fastMaterializeConstant(
const Constant *
C) {
2149 EVT CEVT = TLI.getValueType(DL, C->
getType(),
true);
2155 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2156 return PPCMaterializeFP(CFP, VT);
2157 else if (
const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2158 return PPCMaterializeGV(GV, VT);
2159 else if (
const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2165 return PPCMaterializeInt(CI, VT,
false);
2172 unsigned PPCFastISel::fastMaterializeAlloca(
const AllocaInst *AI) {
2174 if (!FuncInfo.StaticAllocaMap.count(AI))
return 0;
2177 if (!isLoadTypeLegal(AI->
getType(), VT))
return 0;
2180 FuncInfo.StaticAllocaMap.
find(AI);
2182 if (SI != FuncInfo.StaticAllocaMap.
end()) {
2183 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::ADDI8),
2185 ResultReg).addFrameIndex(SI->second).
addImm(0);
2200 bool PPCFastISel::tryToFoldLoadIntoMI(
MachineInstr *
MI,
unsigned OpNo,
2204 if (!isLoadTypeLegal(LI->
getType(), VT))
2208 bool IsZExt =
false;
2214 case PPC::RLDICL_32_64: {
2217 if ((VT ==
MVT::i8 && MB <= 56) ||
2225 case PPC::RLWINM8: {
2228 if ((VT ==
MVT::i8 && MB <= 24) ||
2236 case PPC::EXTSB8_32_64:
2242 case PPC::EXTSH8_32_64: {
2249 case PPC::EXTSW_32_64: {
2258 if (!PPCComputeAddress(LI->
getOperand(0), Addr))
2263 if (!PPCEmitLoad(VT, ResultReg, Addr,
nullptr, IsZExt))
2272 bool PPCFastISel::fastLowerArguments() {
2282 unsigned PPCFastISel::fastEmit_i(
MVT Ty,
MVT VT,
unsigned Opc, uint64_t Imm) {
2289 if (VT ==
MVT::i1 && PPCSubTarget->useCRBits()) {
2290 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2291 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2292 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2301 &PPC::GPRCRegClass);
2303 return PPCMaterialize64BitInt(Imm, RC);
2305 return PPCMaterialize32BitInt(Imm, RC);
2319 unsigned PPCFastISel::fastEmitInst_ri(
unsigned MachineInstOpcode,
2321 unsigned Op0,
bool Op0IsKill,
2323 if (MachineInstOpcode == PPC::ADDI)
2324 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2325 else if (MachineInstOpcode == PPC::ADDI8)
2326 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2329 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2330 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2333 Op0, Op0IsKill, Imm);
2339 unsigned PPCFastISel::fastEmitInst_r(
unsigned MachineInstOpcode,
2341 unsigned Op0,
bool Op0IsKill) {
2343 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2344 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2352 unsigned PPCFastISel::fastEmitInst_rr(
unsigned MachineInstOpcode,
2354 unsigned Op0,
bool Op0IsKill,
2355 unsigned Op1,
bool Op1IsKill) {
2357 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2358 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2371 return new PPCFastISel(FuncInfo, LibInfo);
Return a value (possibly void), from a function.
void push_back(const T &Elt)
Type * getIndexedType() const
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
This class is the base class for the comparison instructions.
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
uint64_t getZExtValue() const
Get zero extended value.
LocInfo getLocInfo() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
unsigned getNumOperands() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
0 1 0 0 True if ordered and less than
unsigned getID() const
Return the register class ID number.
unsigned getSizeInBits() const
1 1 1 0 True if unordered or not equal
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const Function * getParent() const
Return the enclosing method, or null if none.
constexpr bool isInt< 16 >(int64_t x)
An instruction for reading from memory.
static IntegerType * getInt64Ty(LLVMContext &C)
void reserve(size_type N)
unsigned getValNo() const
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
1 0 0 1 True if unordered or equal
unsigned fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
StructType * getStructTypeOrNull() const
Used to lazily calculate structure layout information for a target machine, based on the DataLayout s...
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
Class to represent struct types.
A Use represents the edge between a Value definition and its users.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
unsigned fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill)
Emit a MachineInstr with one register operand and a result register in the given register class...
Reg
All possible values of the reg field in the ModR/M byte.
0 1 0 1 True if ordered and less than or equal
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
A constant value that is initialized with an expression using other constant values.
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
const T & getValue() const LLVM_LVALUE_FUNCTION
Simple integer binary arithmetic operators.
BasicBlock * getSuccessor(unsigned i) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
uint64_t getElementOffset(unsigned Idx) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
MVT - Machine Value Type.
LLVM Basic Block Representation.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
Conditional or Unconditional Branch instruction.
This is an important base class in LLVM.
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
PointerType * getType() const
Overload to return most specific pointer type.
bool isVector() const
isVector - Return true if this is a vector value type.
int64_t getSExtValue() const
Get sign extended value.
const MachineOperand & getOperand(unsigned i) const
Indirect Branch Instruction.
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
static ManagedStatic< OptionRegistry > OR
ConstantFP - Floating Point Values [float, double].
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
#define LLVM_ATTRIBUTE_UNUSED
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Value * getOperand(unsigned i) const
0 1 1 1 True if ordered (no nans)
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
Class to represent integer types.
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
1 1 1 1 Always true (always folded)
EVT - Extended Value Type.
static bool isAtomic(Instruction *I)
1 1 0 1 True if unordered, less than, or equal
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
The memory access writes data.
0 0 1 0 True if ordered and greater than
CCState - This class holds information needed while lowering arguments and return values...
This is the shared class of boolean and integer constants.
constexpr bool isInt< 32 >(int64_t x)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
1 1 0 0 True if unordered or less than
Type * getType() const
All values are typed, get the type of this value.
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill)
Emit a MachineInstr with two register operands and a result register in the given register class...
static ConstantInt * getSigned(IntegerType *Ty, int64_t V)
Return a ConstantInt with the specified value for the specified type.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
This file defines the FastISel class.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
Value * getCondition() const
unsigned greater or equal
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
0 1 1 0 True if ordered and operands are unequal
iterator find(const KeyT &Val)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
1 0 1 0 True if unordered or greater than
constexpr bool isUInt< 16 >(uint64_t x)
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
0 0 0 1 True if ordered and equal
LLVM Value Representation.
1 0 1 1 True if unordered, greater than, or equal
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
Primary interface to the complete machine description for the target machine.
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
static Optional< PPC::Predicate > getComparePred(CmpInst::Predicate Pred)
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
int64_t getSExtValue() const
Return the constant as a 64-bit integer value after it has been sign extended as appropriate for the ...
0 0 1 1 True if ordered and greater than or equal
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
const BasicBlock * getParent() const
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
0 0 0 0 Always false (always folded)
This file describes how to lower LLVM code to machine code.
bool isVoidTy() const
Return true if this is 'void'.
an instruction to allocate memory on the stack
gep_type_iterator gep_type_begin(const User *GEP)