LLVM  4.0.0
llvm::TargetPassConfig Member List

This is the complete list of members for llvm::TargetPassConfig, including all inherited members.

addBlockPlacement()llvm::TargetPassConfigprotectedvirtual
addCodeGenPrepare()llvm::TargetPassConfigvirtual
addFastRegAlloc(FunctionPass *RegAllocPass)llvm::TargetPassConfigprotectedvirtual
addGCPasses()llvm::TargetPassConfigprotectedvirtual
addGlobalInstructionSelect()llvm::TargetPassConfiginlinevirtual
addILPOpts()llvm::TargetPassConfiginlineprotectedvirtual
addInstSelector()llvm::TargetPassConfiginlinevirtual
addIRPasses()llvm::TargetPassConfigvirtual
addIRTranslator()llvm::TargetPassConfiginlinevirtual
addISelPrepare()llvm::TargetPassConfigvirtual
addLegalizeMachineIR()llvm::TargetPassConfiginlinevirtual
addMachineLateOptimization()llvm::TargetPassConfigprotectedvirtual
addMachinePasses()llvm::TargetPassConfigvirtual
addMachineSSAOptimization()llvm::TargetPassConfigprotectedvirtual
addOptimizedRegAlloc(FunctionPass *RegAllocPass)llvm::TargetPassConfigprotectedvirtual
addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)llvm::TargetPassConfigprotected
addPass(Pass *P, bool verifyAfter=true, bool printAfter=true)llvm::TargetPassConfigprotected
addPassesToHandleExceptions()llvm::TargetPassConfig
addPostRegAlloc()llvm::TargetPassConfiginlineprotectedvirtual
addPreEmitPass()llvm::TargetPassConfiginlineprotectedvirtual
addPreGlobalInstructionSelect()llvm::TargetPassConfiginlinevirtual
addPreISel()llvm::TargetPassConfiginlineprotectedvirtual
addPreLegalizeMachineIR()llvm::TargetPassConfiginlinevirtual
addPreRegAlloc()llvm::TargetPassConfiginlineprotectedvirtual
addPreRegBankSelect()llvm::TargetPassConfiginlinevirtual
addPreRewrite()llvm::TargetPassConfiginlineprotectedvirtual
addPreSched2()llvm::TargetPassConfiginlineprotectedvirtual
addPrintPass(const std::string &Banner)llvm::TargetPassConfig
addRegBankSelect()llvm::TargetPassConfiginlinevirtual
addVerifyPass(const std::string &Banner)llvm::TargetPassConfig
assignPassManager(PMStack &PMS, PassManagerType T) overridellvm::ModulePassvirtual
createPass(AnalysisID ID)llvm::Passstatic
createPostMachineScheduler(MachineSchedContext *C) const llvm::TargetPassConfiginlinevirtual
createPrinterPass(raw_ostream &O, const std::string &Banner) const overridellvm::ModulePassvirtual
createRegAllocPass(bool Optimized)llvm::TargetPassConfigprotected
createTargetRegisterAllocator(bool Optimized)llvm::TargetPassConfigprotectedvirtual
default(generic) machine scheduler.*/virtual ScheduleDAGInstrs *createMachineScheduler(MachineSchedContext *C) const llvm::TargetPassConfiginline
disablePass(AnalysisID PassID)llvm::TargetPassConfiginline
DisableVerifyllvm::TargetPassConfigprotected
doFinalization(Module &)llvm::Passinlinevirtual
doInitialization(Module &)llvm::Passinlinevirtual
dump() const llvm::Pass
dumpPassStructure(unsigned Offset=0)llvm::Passvirtual
EarlyTailDuplicateIDllvm::TargetPassConfigstatic
enablePass(AnalysisID PassID)llvm::TargetPassConfiginline
EnableTailMergellvm::TargetPassConfigprotected
getAdjustedAnalysisPointer(AnalysisID ID)llvm::Passvirtual
getAnalysis() const llvm::Pass
getAnalysis(Function &F)llvm::Pass
getAnalysisID(AnalysisID PI) const llvm::Pass
getAnalysisID(AnalysisID PI, Function &F)llvm::Pass
getAnalysisIfAvailable() const llvm::Pass
getAnalysisUsage(AnalysisUsage &) const llvm::Passvirtual
getAsImmutablePass() overridellvm::ImmutablePassinlinevirtual
getAsPMDataManager()llvm::Passvirtual
getEnableShrinkWrap() const llvm::TargetPassConfig
getEnableTailMerge() const llvm::TargetPassConfiginline
getOptimizeRegAlloc() const llvm::TargetPassConfig
getOptLevel() const llvm::TargetPassConfig
getPassID() const llvm::Passinline
getPassKind() const llvm::Passinline
getPassName() const llvm::Passvirtual
getPassSubstitution(AnalysisID StandardID) const llvm::TargetPassConfig
getPotentialPassManagerType() const overridellvm::ModulePassvirtual
getResolver() const llvm::Passinline
getTM() const llvm::TargetPassConfiginline
IDllvm::TargetPassConfigstatic
ImmutablePass(char &pid)llvm::ImmutablePassinlineexplicit
Implllvm::TargetPassConfigprotected
Initializedllvm::TargetPassConfigprotected
initializePass()llvm::ImmutablePassvirtual
insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)llvm::TargetPassConfig
isGlobalISelAbortEnabled() const llvm::TargetPassConfigvirtual
isPassSubstitutedOrOverridden(AnalysisID ID) const llvm::TargetPassConfig
lookupPassInfo(const void *TI)llvm::Passstatic
lookupPassInfo(StringRef Arg)llvm::Passstatic
ModulePass(char &pid)llvm::ModulePassinlineexplicit
mustPreserveAnalysisID(char &AID) const llvm::Pass
Pass(PassKind K, char &pid)llvm::Passinlineexplicit
PostRAMachineLICMIDllvm::TargetPassConfigstatic
preparePassManager(PMStack &)llvm::Passvirtual
print(raw_ostream &O, const Module *M) const llvm::Passvirtual
printAndVerify(const std::string &Banner)llvm::TargetPassConfig
releaseMemory()llvm::Passvirtual
reportDiagnosticWhenGlobalISelFallback() const llvm::TargetPassConfigvirtual
runOnModule(Module &) overridellvm::ImmutablePassinlinevirtual
setDisableVerify(bool Disable)llvm::TargetPassConfiginline
setEnableTailMerge(bool Enable)llvm::TargetPassConfiginline
setInitialized()llvm::TargetPassConfiginline
setOpt(bool &Opt, bool Val)llvm::TargetPassConfigprotected
setResolver(AnalysisResolver *AR)llvm::Pass
setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter, AnalysisID StopBefore, AnalysisID StopAfter)llvm::TargetPassConfiginline
skipModule(Module &M) const llvm::ModulePassprotected
substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)llvm::TargetPassConfig
TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)llvm::TargetPassConfig
TargetPassConfig()llvm::TargetPassConfig
TMllvm::TargetPassConfigprotected
usingDefaultRegAlloc() const llvm::TargetPassConfig
verifyAnalysis() const llvm::Passvirtual
~ImmutablePass() overridellvm::ImmutablePass
~ModulePass() overridellvm::ModulePass
~Pass()llvm::Passvirtual
~TargetPassConfig() overridellvm::TargetPassConfig