38 cl::desc(
"Disable Hexagon Addressing Mode Optimization"));
42 cl::desc(
"Disable Hexagon CFG Optimization"));
67 cl::desc(
"Enable converting conditional transfers into MUX instructions"));
71 "predicate instructions"));
75 cl::desc(
"Enable loop data prefetch on Hexagon"));
78 cl::desc(
"Disable splitting double registers"));
91 cl::desc(
"Enable Hexagon Vector print instr pass"));
163 T,
"e-m:e-p:32:32:32-a:0-n16:32-"
164 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
165 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
188 auto &
I = SubtargetMap[CPU + FS];
194 I = llvm::make_unique<HexagonSubtarget>(
TargetTriple, CPU, FS, *
this);
216 return getTM<HexagonTargetMachine>();
224 void addIRPasses()
override;
225 bool addInstSelector()
override;
226 void addPreRegAlloc()
override;
227 void addPostRegAlloc()
override;
228 void addPreSched2()
override;
229 void addPreEmitPass()
override;
234 return new HexagonPassConfig(
this, PM);
237 void HexagonPassConfig::addIRPasses() {
253 bool HexagonPassConfig::addInstSelector() {
276 printAndVerify(
"After hexagon peephole pass");
291 void HexagonPassConfig::addPreRegAlloc() {
304 void HexagonPassConfig::addPostRegAlloc() {
315 void HexagonPassConfig::addPreSched2() {
322 void HexagonPassConfig::addPreEmitPass() {
FunctionPass * createHexagonCopyToCombine()
char & HexagonExpandCondsetsID
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createHexagonVectorPrint()
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable loop data prefetch on Hexagon"))
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Analysis pass providing the TargetTransformInfo.
static cl::opt< bool > DisableHCP("disable-hcp", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"))
static MachineSchedRegistry SchedCustomRegistry("hexagon","Run Hexagon's custom scheduler", createVLIWMachineSched)
FunctionPass * createHexagonHardwareLoops()
MachineSchedRegistry provides a selection of available machine instruction schedulers.
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
FunctionPass * createHexagonGenPredicate()
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHexagonCommonGEP()
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable RDF-based optimizations"))
FunctionPass * createHexagonOptimizeSZextends()
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
No attributes have been set.
Target-Independent Code Generator Pass Configuration Options.
~HexagonTargetMachine() override
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
FunctionPass * createHexagonBitSimplify()
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to ""predicate instructions"))
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Early expansion of MUX"))
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable early if-conversion"))
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
FunctionPass * createHexagonConstPropagationPass()
initializer< Ty > init(const Ty &Val)
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector print instr pass"))
FunctionPass * createHexagonEarlyIfConversion()
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&...args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
FunctionPass * createHexagonPacketizer()
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"))
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon Addressing Mode Optimization"))
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon CFG Optimization"))
FunctionPass class - This class is used to implement most global optimizations.
FunctionPass * createHexagonSplitDoubleRegs()
FunctionPass * createHexagonLoopRescheduling()
TargetIRAnalysis getTargetIRAnalysis() override
Get a TargetIRAnalysis implementation for the target.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
FunctionPass * createHexagonStoreWidening()
Triple - Helper class for working with autoconf configuration names.
FunctionPass * createHexagonBranchRelaxation()
FunctionPass * createHexagonNewValueJump()
FunctionPass * createHexagonRDFOpt()
Module.h This file contains the declarations for the Module class.
FunctionPass * createHexagonGenMux()
FunctionPass * createHexagonPeephole()
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
FunctionPass * createHexagonGenInsert()
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
AttributeSet getAttributes() const
Return the attribute list for this Function.
Target - Wrapper for Target specific information.
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
FunctionPass * createHexagonCallFrameInformation()
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
FunctionPass * createHexagonSplitConst32AndConst64()
FunctionPass * createHexagonFixupHwLoops()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
Attribute getAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return the attribute object that exists at the given index.
StringRef getValueAsString() const
Return the attribute's value as a string.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
FunctionPass * createHexagonGenExtract()
FunctionPass * createHexagonOptAddrMode()
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
StringRef - Represent a constant reference to a string, i.e.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
void initializeHexagonExpandCondsetsPass(PassRegistry &)
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
void LLVMInitializeHexagonTarget()
Target & getTheHexagonTarget()
FunctionPass * createHexagonCFGOptimizer()