LLVM  4.0.0
MIRPrinter.cpp
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1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MIRPrinter.h"
16 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/IR/BasicBlock.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
30 #include "llvm/IR/Instructions.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/IR/Module.h"
34 #include "llvm/MC/MCSymbol.h"
35 #include "llvm/Support/Format.h"
42 
43 using namespace llvm;
44 
45 namespace {
46 
47 /// This structure describes how to print out stack object references.
48 struct FrameIndexOperand {
49  std::string Name;
50  unsigned ID;
51  bool IsFixed;
52 
53  FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
54  : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
55 
56  /// Return an ordinary stack object reference.
57  static FrameIndexOperand create(StringRef Name, unsigned ID) {
58  return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
59  }
60 
61  /// Return a fixed stack object reference.
62  static FrameIndexOperand createFixed(unsigned ID) {
63  return FrameIndexOperand("", ID, /*IsFixed=*/true);
64  }
65 };
66 
67 } // end anonymous namespace
68 
69 namespace llvm {
70 
71 /// This class prints out the machine functions using the MIR serialization
72 /// format.
73 class MIRPrinter {
74  raw_ostream &OS;
76  /// Maps from stack object indices to operand indices which will be used when
77  /// printing frame index machine operands.
78  DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
79 
80 public:
81  MIRPrinter(raw_ostream &OS) : OS(OS) {}
82 
83  void print(const MachineFunction &MF);
84 
85  void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
86  const TargetRegisterInfo *TRI);
88  const MachineFrameInfo &MFI);
92  const MachineJumpTableInfo &JTI);
94  const MachineFunction &MF, ModuleSlotTracker &MST);
95 
96 private:
97  void initRegisterMaskIds(const MachineFunction &MF);
98 };
99 
100 /// This class prints out the machine instructions using the MIR serialization
101 /// format.
102 class MIPrinter {
103  raw_ostream &OS;
104  ModuleSlotTracker &MST;
105  const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
106  const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
107 
108 public:
110  const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
111  const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
112  : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
113  StackObjectOperandMapping(StackObjectOperandMapping) {}
114 
115  void print(const MachineBasicBlock &MBB);
116 
117  void print(const MachineInstr &MI);
119  void printIRBlockReference(const BasicBlock &BB);
120  void printIRValueReference(const Value &V);
122  void printOffset(int64_t Offset);
123  void printTargetFlags(const MachineOperand &Op);
124  void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
125  unsigned I, bool ShouldPrintRegisterTies,
126  LLT TypeToPrint, bool IsDef = false);
127  void print(const MachineMemOperand &Op);
128 
129  void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
130 };
131 
132 } // end namespace llvm
133 
134 namespace llvm {
135 namespace yaml {
136 
137 /// This struct serializes the LLVM IR module.
138 template <> struct BlockScalarTraits<Module> {
139  static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
140  Mod.print(OS, nullptr);
141  }
142  static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
143  llvm_unreachable("LLVM Module is supposed to be parsed separately");
144  return "";
145  }
146 };
147 
148 } // end namespace yaml
149 } // end namespace llvm
150 
151 static void printReg(unsigned Reg, raw_ostream &OS,
152  const TargetRegisterInfo *TRI) {
153  // TODO: Print Stack Slots.
154  if (!Reg)
155  OS << '_';
157  OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
158  else if (Reg < TRI->getNumRegs())
159  OS << '%' << StringRef(TRI->getName(Reg)).lower();
160  else
161  llvm_unreachable("Can't print this kind of register yet");
162 }
163 
164 static void printReg(unsigned Reg, yaml::StringValue &Dest,
165  const TargetRegisterInfo *TRI) {
166  raw_string_ostream OS(Dest.Value);
167  printReg(Reg, OS, TRI);
168 }
169 
171  initRegisterMaskIds(MF);
172 
173  yaml::MachineFunction YamlMF;
174  YamlMF.Name = MF.getName();
175  YamlMF.Alignment = MF.getAlignment();
177 
178  YamlMF.Legalized = MF.getProperties().hasProperty(
182  YamlMF.Selected = MF.getProperties().hasProperty(
184 
185  convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
187  MST.incorporateFunction(*MF.getFunction());
188  convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
189  convertStackObjects(YamlMF, MF, MST);
190  if (const auto *ConstantPool = MF.getConstantPool())
191  convert(YamlMF, *ConstantPool);
192  if (const auto *JumpTableInfo = MF.getJumpTableInfo())
193  convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
194  raw_string_ostream StrOS(YamlMF.Body.Value.Value);
195  bool IsNewlineNeeded = false;
196  for (const auto &MBB : MF) {
197  if (IsNewlineNeeded)
198  StrOS << "\n";
199  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
200  .print(MBB);
201  IsNewlineNeeded = true;
202  }
203  StrOS.flush();
204  yaml::Output Out(OS);
205  Out << YamlMF;
206 }
207 
209  const MachineRegisterInfo &RegInfo,
210  const TargetRegisterInfo *TRI) {
211  MF.TracksRegLiveness = RegInfo.tracksLiveness();
212 
213  // Print the virtual register definitions.
214  for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
217  VReg.ID = I;
218  if (RegInfo.getRegClassOrNull(Reg))
219  VReg.Class =
220  StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
221  else if (RegInfo.getRegBankOrNull(Reg))
222  VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
223  else {
224  VReg.Class = std::string("_");
225  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
226  "Generic registers must have a valid type");
227  }
228  unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
229  if (PreferredReg)
230  printReg(PreferredReg, VReg.PreferredRegister, TRI);
231  MF.VirtualRegisters.push_back(VReg);
232  }
233 
234  // Print the live ins.
235  for (auto I = RegInfo.livein_begin(), E = RegInfo.livein_end(); I != E; ++I) {
237  printReg(I->first, LiveIn.Register, TRI);
238  if (I->second)
239  printReg(I->second, LiveIn.VirtualRegister, TRI);
240  MF.LiveIns.push_back(LiveIn);
241  }
242  // The used physical register mask is printed as an inverted callee saved
243  // register mask.
244  const BitVector &UsedPhysRegMask = RegInfo.getUsedPhysRegsMask();
245  if (UsedPhysRegMask.none())
246  return;
247  std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
248  for (unsigned I = 0, E = UsedPhysRegMask.size(); I != E; ++I) {
249  if (!UsedPhysRegMask[I]) {
251  printReg(I, Reg, TRI);
252  CalleeSavedRegisters.push_back(Reg);
253  }
254  }
255  MF.CalleeSavedRegisters = CalleeSavedRegisters;
256 }
257 
259  yaml::MachineFrameInfo &YamlMFI,
260  const MachineFrameInfo &MFI) {
263  YamlMFI.HasStackMap = MFI.hasStackMap();
264  YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
265  YamlMFI.StackSize = MFI.getStackSize();
266  YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
267  YamlMFI.MaxAlignment = MFI.getMaxAlignment();
268  YamlMFI.AdjustsStack = MFI.adjustsStack();
269  YamlMFI.HasCalls = MFI.hasCalls();
270  YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
272  YamlMFI.HasVAStart = MFI.hasVAStart();
274  if (MFI.getSavePoint()) {
275  raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
276  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
278  }
279  if (MFI.getRestorePoint()) {
280  raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
281  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
283  }
284 }
285 
287  const MachineFunction &MF,
288  ModuleSlotTracker &MST) {
289  const MachineFrameInfo &MFI = MF.getFrameInfo();
290  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
291  // Process fixed stack objects.
292  unsigned ID = 0;
293  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
294  if (MFI.isDeadObjectIndex(I))
295  continue;
296 
298  YamlObject.ID = ID;
299  YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
302  YamlObject.Offset = MFI.getObjectOffset(I);
303  YamlObject.Size = MFI.getObjectSize(I);
304  YamlObject.Alignment = MFI.getObjectAlignment(I);
305  YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
306  YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
307  YMF.FixedStackObjects.push_back(YamlObject);
308  StackObjectOperandMapping.insert(
309  std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
310  }
311 
312  // Process ordinary stack objects.
313  ID = 0;
314  for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
315  if (MFI.isDeadObjectIndex(I))
316  continue;
317 
318  yaml::MachineStackObject YamlObject;
319  YamlObject.ID = ID;
320  if (const auto *Alloca = MFI.getObjectAllocation(I))
321  YamlObject.Name.Value =
322  Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
323  YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
328  YamlObject.Offset = MFI.getObjectOffset(I);
329  YamlObject.Size = MFI.getObjectSize(I);
330  YamlObject.Alignment = MFI.getObjectAlignment(I);
331 
332  YMF.StackObjects.push_back(YamlObject);
333  StackObjectOperandMapping.insert(std::make_pair(
334  I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
335  }
336 
337  for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
339  printReg(CSInfo.getReg(), Reg, TRI);
340  auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
341  assert(StackObjectInfo != StackObjectOperandMapping.end() &&
342  "Invalid stack object index");
343  const FrameIndexOperand &StackObject = StackObjectInfo->second;
344  if (StackObject.IsFixed)
345  YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
346  else
347  YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
348  }
349  for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
350  auto LocalObject = MFI.getLocalFrameObjectMap(I);
351  auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
352  assert(StackObjectInfo != StackObjectOperandMapping.end() &&
353  "Invalid stack object index");
354  const FrameIndexOperand &StackObject = StackObjectInfo->second;
355  assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
356  YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
357  }
358 
359  // Print the stack object references in the frame information class after
360  // converting the stack objects.
361  if (MFI.hasStackProtectorIndex()) {
363  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
365  }
366 
367  // Print the debug variable information.
368  for (const MachineFunction::VariableDbgInfo &DebugVar :
369  MF.getVariableDbgInfo()) {
370  auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
371  assert(StackObjectInfo != StackObjectOperandMapping.end() &&
372  "Invalid stack object index");
373  const FrameIndexOperand &StackObject = StackObjectInfo->second;
374  assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
375  auto &Object = YMF.StackObjects[StackObject.ID];
376  {
377  raw_string_ostream StrOS(Object.DebugVar.Value);
378  DebugVar.Var->printAsOperand(StrOS, MST);
379  }
380  {
381  raw_string_ostream StrOS(Object.DebugExpr.Value);
382  DebugVar.Expr->printAsOperand(StrOS, MST);
383  }
384  {
385  raw_string_ostream StrOS(Object.DebugLoc.Value);
386  DebugVar.Loc->printAsOperand(StrOS, MST);
387  }
388  }
389 }
390 
393  unsigned ID = 0;
394  for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
395  // TODO: Serialize target specific constant pool entries.
396  if (Constant.isMachineConstantPoolEntry())
397  llvm_unreachable("Can't print target specific constant pool entries yet");
398 
399  yaml::MachineConstantPoolValue YamlConstant;
400  std::string Str;
401  raw_string_ostream StrOS(Str);
402  Constant.Val.ConstVal->printAsOperand(StrOS);
403  YamlConstant.ID = ID++;
404  YamlConstant.Value = StrOS.str();
405  YamlConstant.Alignment = Constant.getAlignment();
406  MF.Constants.push_back(YamlConstant);
407  }
408 }
409 
411  yaml::MachineJumpTable &YamlJTI,
412  const MachineJumpTableInfo &JTI) {
413  YamlJTI.Kind = JTI.getEntryKind();
414  unsigned ID = 0;
415  for (const auto &Table : JTI.getJumpTables()) {
416  std::string Str;
418  Entry.ID = ID++;
419  for (const auto *MBB : Table.MBBs) {
420  raw_string_ostream StrOS(Str);
421  MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
423  Entry.Blocks.push_back(StrOS.str());
424  Str.clear();
425  }
426  YamlJTI.Entries.push_back(Entry);
427  }
428 }
429 
430 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
431  const auto *TRI = MF.getSubtarget().getRegisterInfo();
432  unsigned I = 0;
433  for (const uint32_t *Mask : TRI->getRegMasks())
434  RegisterMaskIds.insert(std::make_pair(Mask, I++));
435 }
436 
438  assert(MBB.getNumber() >= 0 && "Invalid MBB number");
439  OS << "bb." << MBB.getNumber();
440  bool HasAttributes = false;
441  if (const auto *BB = MBB.getBasicBlock()) {
442  if (BB->hasName()) {
443  OS << "." << BB->getName();
444  } else {
445  HasAttributes = true;
446  OS << " (";
447  int Slot = MST.getLocalSlot(BB);
448  if (Slot == -1)
449  OS << "<ir-block badref>";
450  else
451  OS << (Twine("%ir-block.") + Twine(Slot)).str();
452  }
453  }
454  if (MBB.hasAddressTaken()) {
455  OS << (HasAttributes ? ", " : " (");
456  OS << "address-taken";
457  HasAttributes = true;
458  }
459  if (MBB.isEHPad()) {
460  OS << (HasAttributes ? ", " : " (");
461  OS << "landing-pad";
462  HasAttributes = true;
463  }
464  if (MBB.getAlignment()) {
465  OS << (HasAttributes ? ", " : " (");
466  OS << "align " << MBB.getAlignment();
467  HasAttributes = true;
468  }
469  if (HasAttributes)
470  OS << ")";
471  OS << ":\n";
472 
473  bool HasLineAttributes = false;
474  // Print the successors
475  if (!MBB.succ_empty()) {
476  OS.indent(2) << "successors: ";
477  for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
478  if (I != MBB.succ_begin())
479  OS << ", ";
480  printMBBReference(**I);
481  if (MBB.hasSuccessorProbabilities())
482  OS << '('
483  << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
484  << ')';
485  }
486  OS << "\n";
487  HasLineAttributes = true;
488  }
489 
490  // Print the live in registers.
491  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
492  if (MRI.tracksLiveness() && !MBB.livein_empty()) {
493  const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
494  OS.indent(2) << "liveins: ";
495  bool First = true;
496  for (const auto &LI : MBB.liveins()) {
497  if (!First)
498  OS << ", ";
499  First = false;
500  printReg(LI.PhysReg, OS, &TRI);
501  if (!LI.LaneMask.all())
502  OS << ":0x" << PrintLaneMask(LI.LaneMask);
503  }
504  OS << "\n";
505  HasLineAttributes = true;
506  }
507 
508  if (HasLineAttributes)
509  OS << "\n";
510  bool IsInBundle = false;
511  for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
512  const MachineInstr &MI = *I;
513  if (IsInBundle && !MI.isInsideBundle()) {
514  OS.indent(2) << "}\n";
515  IsInBundle = false;
516  }
517  OS.indent(IsInBundle ? 4 : 2);
518  print(MI);
519  if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
520  OS << " {";
521  IsInBundle = true;
522  }
523  OS << "\n";
524  }
525  if (IsInBundle)
526  OS.indent(2) << "}\n";
527 }
528 
529 /// Return true when an instruction has tied register that can't be determined
530 /// by the instruction's descriptor.
532  const MCInstrDesc &MCID = MI.getDesc();
533  for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
534  const auto &Operand = MI.getOperand(I);
535  if (!Operand.isReg() || Operand.isDef())
536  // Ignore the defined registers as MCID marks only the uses as tied.
537  continue;
538  int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
539  int TiedIdx = Operand.isTied() ? int(MI.findTiedOperandIdx(I)) : -1;
540  if (ExpectedTiedIdx != TiedIdx)
541  return true;
542  }
543  return false;
544 }
545 
546 static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx,
547  SmallBitVector &PrintedTypes,
548  const MachineRegisterInfo &MRI) {
549  const MachineOperand &Op = MI.getOperand(OpIdx);
550  if (!Op.isReg())
551  return LLT{};
552 
553  if (MI.isVariadic() || OpIdx >= MI.getNumExplicitOperands())
554  return MRI.getType(Op.getReg());
555 
556  auto &OpInfo = MI.getDesc().OpInfo[OpIdx];
557  if (!OpInfo.isGenericType())
558  return MRI.getType(Op.getReg());
559 
560  if (PrintedTypes[OpInfo.getGenericTypeIndex()])
561  return LLT{};
562 
563  PrintedTypes.set(OpInfo.getGenericTypeIndex());
564  return MRI.getType(Op.getReg());
565 }
566 
568  const auto *MF = MI.getParent()->getParent();
569  const auto &MRI = MF->getRegInfo();
570  const auto &SubTarget = MF->getSubtarget();
571  const auto *TRI = SubTarget.getRegisterInfo();
572  assert(TRI && "Expected target register info");
573  const auto *TII = SubTarget.getInstrInfo();
574  assert(TII && "Expected target instruction info");
575  if (MI.isCFIInstruction())
576  assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
577 
578  SmallBitVector PrintedTypes(8);
579  bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI);
580  unsigned I = 0, E = MI.getNumOperands();
581  for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
582  !MI.getOperand(I).isImplicit();
583  ++I) {
584  if (I)
585  OS << ", ";
586  print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
587  getTypeToPrint(MI, I, PrintedTypes, MRI),
588  /*IsDef=*/true);
589  }
590 
591  if (I)
592  OS << " = ";
594  OS << "frame-setup ";
595  OS << TII->getName(MI.getOpcode());
596  if (I < E)
597  OS << ' ';
598 
599  bool NeedComma = false;
600  for (; I < E; ++I) {
601  if (NeedComma)
602  OS << ", ";
603  print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies,
604  getTypeToPrint(MI, I, PrintedTypes, MRI));
605  NeedComma = true;
606  }
607 
608  if (MI.getDebugLoc()) {
609  if (NeedComma)
610  OS << ',';
611  OS << " debug-location ";
612  MI.getDebugLoc()->printAsOperand(OS, MST);
613  }
614 
615  if (!MI.memoperands_empty()) {
616  OS << " :: ";
617  bool NeedComma = false;
618  for (const auto *Op : MI.memoperands()) {
619  if (NeedComma)
620  OS << ", ";
621  print(*Op);
622  NeedComma = true;
623  }
624  }
625 }
626 
628  OS << "%bb." << MBB.getNumber();
629  if (const auto *BB = MBB.getBasicBlock()) {
630  if (BB->hasName())
631  OS << '.' << BB->getName();
632  }
633 }
634 
635 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
636  if (Slot == -1)
637  OS << "<badref>";
638  else
639  OS << Slot;
640 }
641 
643  OS << "%ir-block.";
644  if (BB.hasName()) {
646  return;
647  }
648  const Function *F = BB.getParent();
649  int Slot;
650  if (F == MST.getCurrentFunction()) {
651  Slot = MST.getLocalSlot(&BB);
652  } else {
653  ModuleSlotTracker CustomMST(F->getParent(),
654  /*ShouldInitializeAllMetadata=*/false);
655  CustomMST.incorporateFunction(*F);
656  Slot = CustomMST.getLocalSlot(&BB);
657  }
658  printIRSlotNumber(OS, Slot);
659 }
660 
662  if (isa<GlobalValue>(V)) {
663  V.printAsOperand(OS, /*PrintType=*/false, MST);
664  return;
665  }
666  if (isa<Constant>(V)) {
667  // Machine memory operands can load/store to/from constant value pointers.
668  OS << '`';
669  V.printAsOperand(OS, /*PrintType=*/true, MST);
670  OS << '`';
671  return;
672  }
673  OS << "%ir.";
674  if (V.hasName()) {
676  return;
677  }
678  printIRSlotNumber(OS, MST.getLocalSlot(&V));
679 }
680 
682  auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
683  assert(ObjectInfo != StackObjectOperandMapping.end() &&
684  "Invalid frame index");
685  const FrameIndexOperand &Operand = ObjectInfo->second;
686  if (Operand.IsFixed) {
687  OS << "%fixed-stack." << Operand.ID;
688  return;
689  }
690  OS << "%stack." << Operand.ID;
691  if (!Operand.Name.empty())
692  OS << '.' << Operand.Name;
693 }
694 
696  if (Offset == 0)
697  return;
698  if (Offset < 0) {
699  OS << " - " << -Offset;
700  return;
701  }
702  OS << " + " << Offset;
703 }
704 
705 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
707  for (const auto &I : Flags) {
708  if (I.first == TF) {
709  return I.second;
710  }
711  }
712  return nullptr;
713 }
714 
716  if (!Op.getTargetFlags())
717  return;
718  const auto *TII =
720  assert(TII && "expected instruction info");
721  auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
722  OS << "target-flags(";
723  const bool HasDirectFlags = Flags.first;
724  const bool HasBitmaskFlags = Flags.second;
725  if (!HasDirectFlags && !HasBitmaskFlags) {
726  OS << "<unknown>) ";
727  return;
728  }
729  if (HasDirectFlags) {
730  if (const auto *Name = getTargetFlagName(TII, Flags.first))
731  OS << Name;
732  else
733  OS << "<unknown target flag>";
734  }
735  if (!HasBitmaskFlags) {
736  OS << ") ";
737  return;
738  }
739  bool IsCommaNeeded = HasDirectFlags;
740  unsigned BitMask = Flags.second;
741  auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
742  for (const auto &Mask : BitMasks) {
743  // Check if the flag's bitmask has the bits of the current mask set.
744  if ((BitMask & Mask.first) == Mask.first) {
745  if (IsCommaNeeded)
746  OS << ", ";
747  IsCommaNeeded = true;
748  OS << Mask.second;
749  // Clear the bits which were serialized from the flag's bitmask.
750  BitMask &= ~(Mask.first);
751  }
752  }
753  if (BitMask) {
754  // When the resulting flag's bitmask isn't zero, we know that we didn't
755  // serialize all of the bit flags.
756  if (IsCommaNeeded)
757  OS << ", ";
758  OS << "<unknown bitmask target flag>";
759  }
760  OS << ") ";
761 }
762 
763 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
764  const auto *TII = MF.getSubtarget().getInstrInfo();
765  assert(TII && "expected instruction info");
766  auto Indices = TII->getSerializableTargetIndices();
767  for (const auto &I : Indices) {
768  if (I.first == Index) {
769  return I.second;
770  }
771  }
772  return nullptr;
773 }
774 
776  unsigned I, bool ShouldPrintRegisterTies, LLT TypeToPrint,
777  bool IsDef) {
778  printTargetFlags(Op);
779  switch (Op.getType()) {
781  if (Op.isImplicit())
782  OS << (Op.isDef() ? "implicit-def " : "implicit ");
783  else if (!IsDef && Op.isDef())
784  // Print the 'def' flag only when the operand is defined after '='.
785  OS << "def ";
786  if (Op.isInternalRead())
787  OS << "internal ";
788  if (Op.isDead())
789  OS << "dead ";
790  if (Op.isKill())
791  OS << "killed ";
792  if (Op.isUndef())
793  OS << "undef ";
794  if (Op.isEarlyClobber())
795  OS << "early-clobber ";
796  if (Op.isDebug())
797  OS << "debug-use ";
798  printReg(Op.getReg(), OS, TRI);
799  // Print the sub register.
800  if (Op.getSubReg() != 0)
801  OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
802  if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
803  OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
804  if (TypeToPrint.isValid())
805  OS << '(' << TypeToPrint << ')';
806  break;
808  OS << Op.getImm();
809  break;
811  Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
812  break;
814  Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
815  break;
817  printMBBReference(*Op.getMBB());
818  break;
821  break;
823  OS << "%const." << Op.getIndex();
824  printOffset(Op.getOffset());
825  break;
827  OS << "target-index(";
828  if (const auto *Name = getTargetIndexName(
829  *Op.getParent()->getParent()->getParent(), Op.getIndex()))
830  OS << Name;
831  else
832  OS << "<unknown>";
833  OS << ')';
834  printOffset(Op.getOffset());
835  break;
836  }
838  OS << "%jump-table." << Op.getIndex();
839  break;
841  OS << '$';
843  printOffset(Op.getOffset());
844  break;
846  Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
847  printOffset(Op.getOffset());
848  break;
850  OS << "blockaddress(";
851  Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
852  MST);
853  OS << ", ";
855  OS << ')';
856  printOffset(Op.getOffset());
857  break;
859  auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
860  if (RegMaskInfo != RegisterMaskIds.end())
861  OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
862  else
863  llvm_unreachable("Can't print this machine register mask yet.");
864  break;
865  }
867  const uint32_t *RegMask = Op.getRegLiveOut();
868  OS << "liveout(";
869  bool IsCommaNeeded = false;
870  for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
871  if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
872  if (IsCommaNeeded)
873  OS << ", ";
874  printReg(Reg, OS, TRI);
875  IsCommaNeeded = true;
876  }
877  }
878  OS << ")";
879  break;
880  }
882  Op.getMetadata()->printAsOperand(OS, MST);
883  break;
885  OS << "<mcsymbol " << *Op.getMCSymbol() << ">";
886  break;
888  const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
889  print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
890  break;
891  }
894  if (ID < Intrinsic::num_intrinsics)
895  OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
896  else {
897  const MachineFunction &MF = *Op.getParent()->getParent()->getParent();
899  OS << "intrinsic(@" << TII->getName(ID) << ')';
900  }
901  break;
902  }
904  auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate());
905  OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
906  << CmpInst::getPredicateName(Pred) << ')';
907  break;
908  }
909  }
910 }
911 
913  OS << '(';
914  // TODO: Print operand's target specific flags.
915  if (Op.isVolatile())
916  OS << "volatile ";
917  if (Op.isNonTemporal())
918  OS << "non-temporal ";
919  if (Op.isDereferenceable())
920  OS << "dereferenceable ";
921  if (Op.isInvariant())
922  OS << "invariant ";
923  if (Op.isLoad())
924  OS << "load ";
925  else {
926  assert(Op.isStore() && "Non load machine operand must be a store");
927  OS << "store ";
928  }
929  OS << Op.getSize();
930  if (const Value *Val = Op.getValue()) {
931  OS << (Op.isLoad() ? " from " : " into ");
932  printIRValueReference(*Val);
933  } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
934  OS << (Op.isLoad() ? " from " : " into ");
935  assert(PVal && "Expected a pseudo source value");
936  switch (PVal->kind()) {
938  OS << "stack";
939  break;
941  OS << "got";
942  break;
944  OS << "jump-table";
945  break;
947  OS << "constant-pool";
948  break;
951  cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
952  break;
954  OS << "call-entry ";
955  cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
956  OS, /*PrintType=*/false, MST);
957  break;
959  OS << "call-entry $";
961  OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
962  break;
964  llvm_unreachable("TargetCustom pseudo source values are not supported");
965  break;
966  }
967  }
968  printOffset(Op.getOffset());
969  if (Op.getBaseAlignment() != Op.getSize())
970  OS << ", align " << Op.getBaseAlignment();
971  auto AAInfo = Op.getAAInfo();
972  if (AAInfo.TBAA) {
973  OS << ", !tbaa ";
974  AAInfo.TBAA->printAsOperand(OS, MST);
975  }
976  if (AAInfo.Scope) {
977  OS << ", !alias.scope ";
978  AAInfo.Scope->printAsOperand(OS, MST);
979  }
980  if (AAInfo.NoAlias) {
981  OS << ", !noalias ";
982  AAInfo.NoAlias->printAsOperand(OS, MST);
983  }
984  if (Op.getRanges()) {
985  OS << ", !range ";
986  Op.getRanges()->printAsOperand(OS, MST);
987  }
988  OS << ')';
989 }
990 
991 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
992  const TargetRegisterInfo *TRI) {
993  int Reg = TRI->getLLVMRegNum(DwarfReg, true);
994  if (Reg == -1) {
995  OS << "<badreg>";
996  return;
997  }
998  printReg(Reg, OS, TRI);
999 }
1000 
1002  const TargetRegisterInfo *TRI) {
1003  switch (CFI.getOperation()) {
1005  OS << "same_value ";
1006  if (CFI.getLabel())
1007  OS << "<mcsymbol> ";
1008  printCFIRegister(CFI.getRegister(), OS, TRI);
1009  break;
1011  OS << "offset ";
1012  if (CFI.getLabel())
1013  OS << "<mcsymbol> ";
1014  printCFIRegister(CFI.getRegister(), OS, TRI);
1015  OS << ", " << CFI.getOffset();
1016  break;
1018  OS << "def_cfa_register ";
1019  if (CFI.getLabel())
1020  OS << "<mcsymbol> ";
1021  printCFIRegister(CFI.getRegister(), OS, TRI);
1022  break;
1024  OS << "def_cfa_offset ";
1025  if (CFI.getLabel())
1026  OS << "<mcsymbol> ";
1027  OS << CFI.getOffset();
1028  break;
1030  OS << "def_cfa ";
1031  if (CFI.getLabel())
1032  OS << "<mcsymbol> ";
1033  printCFIRegister(CFI.getRegister(), OS, TRI);
1034  OS << ", " << CFI.getOffset();
1035  break;
1036  default:
1037  // TODO: Print the other CFI Operations.
1038  OS << "<unserializable cfi operation>";
1039  break;
1040  }
1041 }
1042 
1043 void llvm::printMIR(raw_ostream &OS, const Module &M) {
1044  yaml::Output Out(OS);
1045  Out << const_cast<Module &>(M);
1046 }
1047 
1049  MIRPrinter Printer(OS);
1050  Printer.print(MF);
1051 }
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:217
bool isImplicit() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isEHPad() const
Returns true if the block is a landing pad.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getAlignment() const
getAlignment - Return the alignment (log2, not bytes) of the function.
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:119
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
instr_iterator instr_begin()
iterator_range< livein_iterator > liveins() const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
static StringRef input(StringRef Str, void *Ctxt, Module &Mod)
Definition: MIRPrinter.cpp:142
instr_iterator instr_end()
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
bool hasName() const
Definition: Value.h:236
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:151
livein_iterator livein_end() const
bool hasProperty(Property P) const
const ConstantFP * getFPImm() const
MachineBasicBlock * getMBB() const
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
static void printIRSlotNumber(raw_ostream &OS, int Slot)
Definition: MIRPrinter.cpp:635
static const char * getTargetFlagName(const TargetInstrInfo *TII, unsigned TF)
Definition: MIRPrinter.cpp:705
This class prints out the machine functions using the MIR serialization format.
Definition: MIRPrinter.cpp:73
MachineBasicBlock * getRestorePoint() const
Optional< std::vector< FlowStringValue > > CalleeSavedRegisters
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
const BitVector & getUsedPhysRegsMask() const
bool isTied() const
raw_ostream & indent(unsigned NumSpaces)
indent - Insert 'NumSpaces' spaces.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
Definition: AsmWriter.cpp:734
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
uint32_t getNumerator() const
static LLT getTypeToPrint(const MachineInstr &MI, unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI)
Definition: MIRPrinter.cpp:546
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
MachineBasicBlock reference.
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:100
const char * getSymbolName() const
bool isCFIInstruction() const
Definition: MachineInstr.h:770
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Manage lifetime of a slot tracker for printing IR.
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:365
const MDNode * getMetadata() const
Mask of live-out registers.
print alias Alias Set Printer
bool hasStackProtectorIndex() const
VariableDbgInfoMapTy & getVariableDbgInfo()
unsigned getRegister() const
Definition: MCDwarf.h:464
void printTargetFlags(const MachineOperand &Op)
Definition: MIRPrinter.cpp:715
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:191
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Mask of preserved registers.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:172
const std::vector< MachineJumpTableEntry > & getJumpTables() const
int getOffset() const
Definition: MCDwarf.h:477
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName(ID id)
Return the LLVM name for an intrinsic, such as "llvm.ppc.altivec.lvx".
Definition: Function.cpp:555
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
unsigned getCFIIndex() const
const TargetRegisterInfo * getTargetRegisterInfo() const
Serializable representation of the fixed stack object from the MachineFrameInfo class.
MCCFIInstruction index.
void print(const MachineBasicBlock &MBB)
Definition: MIRPrinter.cpp:437
static const char * getTargetIndexName(const MachineFunction &MF, int Index)
Definition: MIRPrinter.cpp:763
Target-dependent index+offset operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Name of external global symbol.
const MachineFunctionProperties & getProperties() const
Get the function properties.
static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MIRPrinter.cpp:991
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isUndef() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isVariableSizedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a variable sized object.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
#define F(x, y, z)
Definition: MD5.cpp:51
bool isKill() const
int getObjectIndexBegin() const
Return the minimum frame object index.
std::vector< VirtualRegisterDefinition > VirtualRegisters
Immediate >64bit operand.
int getOffsetAdjustment() const
Return the correction for frame offsets.
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
Definition: AsmWriter.cpp:3473
MachineBasicBlock * MBB
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
This class is a data container for one entry in a MachineConstantPool.
bool isImmutableObjectIndex(int ObjectIdx) const
isImmutableObjectIndex - Returns true if the specified index corresponds to an immutable object...
int64_t getImm() const
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: Object/ELF.h:236
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
int64_t getLocalFrameObjectCount() const
Return the number of objects allocated into the local object block.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
TargetInstrInfo - Interface to description of machine instruction set.
std::pair< int, int64_t > getLocalFrameObjectMap(int i) const
Get the local offset mapping for a for an object.
bool isEarlyClobber() const
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
Address of a global value.
Intrinsic::ID getIntrinsicID() const
unsigned getTargetFlags() const
MIRPrinter(raw_ostream &OS)
Definition: MIRPrinter.cpp:81
std::vector< FlowStringValue > Blocks
unsigned const MachineRegisterInfo * MRI
Serializable representation of stack object from the MachineFrameInfo class.
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
bool isAliasedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to an object that might be pointed to by an LLVM IR v...
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:42
static StringRef getPredicateName(Predicate P)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
MachineJumpTable JumpTableInfo
Constant pool.
bool hasVAStart() const
Returns true if the function calls the llvm.va_start intrinsic.
bool isIntPredicate() const
Definition: InstrTypes.h:978
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Address of a basic block.
uint32_t Offset
virtual ArrayRef< const char * > getRegMaskNames() const =0
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:404
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:880
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:161
void convertStackObjects(yaml::MachineFunction &YMF, const MachineFunction &MF, ModuleSlotTracker &MST)
Definition: MIRPrinter.cpp:286
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
const std::vector< MCCFIInstruction > & getFrameInstructions() const
Returns a reference to a list of cfi instructions in the function's prologue.
This class prints out the machine instructions using the MIR serialization format.
Definition: MIRPrinter.cpp:102
std::vector< MachineStackObject > StackObjects
int64_t getOffset() const
Return the offset from the symbol in this operand.
const PseudoSourceValue * getPseudoValue() const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Serializable representation of MachineFrameInfo.
static void printReg(unsigned Reg, raw_ostream &OS, const TargetRegisterInfo *TRI)
Definition: MIRPrinter.cpp:151
void printMIR(raw_ostream &OS, const Module &M)
Print LLVM IR using the MIR serialization format to the given output stream.
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:720
unsigned getSubReg() const
The Output class is used to generate a yaml document from in-memory structs and vectors.
Definition: YAMLTraits.h:1249
int getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:479
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
TargetIntrinsicInfo - Interface to description of machine instruction set.
SmallBitVector & set()
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:52
bool hasCalls() const
Return true if the current function has any function calls.
OpType getOperation() const
Definition: MCDwarf.h:461
bool memoperands_empty() const
Return true if we don't have any memory operands which described the the memory access done by this i...
Definition: MachineInstr.h:363
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Generic predicate for ISel.
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
Module.h This file contains the declarations for the Module class.
void printIRBlockReference(const BasicBlock &BB)
Definition: MIRPrinter.cpp:642
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:3517
void printLLVMNameWithoutPrefix(raw_ostream &OS, StringRef Name)
Print out a name of an LLVM value without any prefixes.
Definition: AsmWriter.cpp:359
BasicBlock * getBasicBlock() const
Definition: Constants.h:851
livein_iterator livein_begin() const
unsigned getPredicate() const
virtual std::string getName(unsigned IID, Type **Tys=nullptr, unsigned numTys=0) const =0
Return the name of a target intrinsic, e.g.
MCSymbol reference (for debug/eh info)
const ConstantInt * getCImm() const
const Value * getValue() const
Return the base address of the memory access.
Special value supplied for machine level alias analysis.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
A wrapper around std::string which contains a source range that's being set during parsing...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
int getStackProtectorIndex() const
Return the index for the stack protector object.
void print(raw_ostream &OS, AssemblyAnnotationWriter *AAW, bool ShouldPreserveUseListOrder=false, bool IsForDebug=false) const
Print the module to an output stream with an optional AssemblyAnnotationWriter.
Definition: AsmWriter.cpp:3311
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineBasicBlock * getSavePoint() const
bool hasSuccessorProbabilities() const
Return true if any of the successors have probabilities attached to them.
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
std::vector< MachineFunctionLiveIn > LiveIns
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
static void output(const Module &Mod, void *Ctxt, raw_ostream &OS)
Definition: MIRPrinter.cpp:139
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This class should be specialized by type that requires custom conversion to/from a YAML literal block...
Definition: YAMLTraits.h:167
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
static bool hasComplexRegisterTies(const MachineInstr &MI)
Return true when an instruction has tied register that can't be determined by the instruction's descr...
Definition: MIRPrinter.cpp:531
std::vector< Entry > Entries
#define I(x, y, z)
Definition: MD5.cpp:54
iterator end()
Definition: DenseMap.h:69
MCSymbol * getMCSymbol() const
iterator find(const KeyT &Val)
Definition: DenseMap.h:127
bool isValid() const
Definition: LowLevelType.h:88
std::vector< MachineConstantPoolValue > Constants
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Abstract Stack Frame Index.
void printMBBReference(const MachineBasicBlock &MBB)
Definition: MIRPrinter.cpp:627
JTEntryKind getEntryKind() const
void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Definition: MIRPrinter.cpp:208
This file defines passes to print out IR in various granularities.
unsigned getReg() const
getReg - Returns the register number.
void printOffset(int64_t Offset)
Definition: MIRPrinter.cpp:695
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Function * getFunction() const
Definition: Constants.h:850
std::vector< FixedMachineStackObject > FixedStackObjects
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
const MDNode * getRanges() const
Return the range tag for the memory reference.
virtual const TargetInstrInfo * getInstrInfo() const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:537
LLVM Value Representation.
Definition: Value.h:71
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Floating-point immediate operand.
static LLVM_ATTRIBUTE_UNUSED Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
Definition: LaneBitmask.h:82
void printIRValueReference(const Value &V)
Definition: MIRPrinter.cpp:661
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
void printStackObjectReference(int FrameIndex)
Definition: MIRPrinter.cpp:681
bool isDebug() const
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
uint64_t getSize() const
Return the size in bytes of the memory reference.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
const std::vector< MachineConstantPoolEntry > & getConstants() const
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
const BlockAddress * getBlockAddress() const
Address of indexed Constant in Constant Pool.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineJumpTableInfo::JTEntryKind Kind
MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST, const DenseMap< const uint32_t *, unsigned > &RegisterMaskIds, const DenseMap< int, FrameIndexOperand > &StackObjectOperandMapping)
Definition: MIRPrinter.cpp:109
MCSymbol * getLabel() const
Definition: MCDwarf.h:462
const AllocaInst * getObjectAllocation(int ObjectIdx) const
Return the underlying Alloca of the specified stack object if it exists.
const Function * getCurrentFunction() const
void print(const MachineFunction &MF)
Definition: MIRPrinter.cpp:170
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:122
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
bool isInternalRead() const
Metadata reference (for debug info)
uint64_t getBaseAlignment() const
Return the minimum known alignment in bytes of the base address, without the offset.
unsigned getAlignment() const
Return alignment of the basic block.