10 #define DEBUG_TYPE "hexagon-disassembler"
36 using namespace Hexagon;
45 std::unique_ptr<MCInstrInfo const>
const MCII;
46 std::unique_ptr<MCInst *> CurrentBundle;
55 bool &Complete)
const;
61 void adjustExtendedInstructions(
MCInst &MCI,
MCInst const &MCB)
const;
62 void addSubinstOperands(
MCInst *
MI,
unsigned opcode,
unsigned inst)
const;
103 void const *Decoder);
111 uint64_t
Address,
const void *Decoder);
113 const void *Decoder);
115 const void *Decoder);
117 const void *Decoder);
119 const void *Decoder);
121 const void *Decoder);
123 const void *Decoder);
125 const void *Decoder);
127 const void *Decoder);
129 const void *Decoder);
131 const void *Decoder);
133 const void *Decoder);
135 const void *Decoder);
137 const void *Decoder);
139 const void *Decoder);
141 const void *Decoder);
143 const void *Decoder);
145 #include "HexagonGenDisassemblerTables.inc"
164 bool Complete =
false;
167 *CurrentBundle = &
MI;
169 while (Result ==
Success && !Complete) {
173 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
180 HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo());
187 return *
static_cast<HexagonDisassembler
const *
>(Decoder);
200 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
207 else if (BundleSize == 1)
214 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
217 unsigned duplexIClass, IClassLow, IClassHigh;
219 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
220 switch (duplexIClass) {
290 unsigned instLow = Instruction & 0x1fff;
291 unsigned instHigh = (Instruction >> 16) & 0x1fff;
304 addSubinstOperands(MILow, opLow, instLow);
305 addSubinstOperands(MIHigh, opHigh, instHigh);
316 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
338 unsigned reg =
i->getReg() - Hexagon::R0;
347 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
348 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
349 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
350 case Hexagon::J4_cmpeqn1_fp0_jump_t:
351 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
352 case Hexagon::J4_cmpeqn1_fp1_jump_t:
353 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
354 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
355 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
356 case Hexagon::J4_cmpeqn1_tp0_jump_t:
357 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
358 case Hexagon::J4_cmpeqn1_tp1_jump_t:
359 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
360 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
361 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
362 case Hexagon::J4_cmpgtn1_fp0_jump_t:
363 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
364 case Hexagon::J4_cmpgtn1_fp1_jump_t:
365 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
366 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
367 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
368 case Hexagon::J4_cmpgtn1_tp0_jump_t:
369 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
370 case Hexagon::J4_cmpgtn1_tp1_jump_t:
380 assert(MCO.
isReg() &&
"New value consumers must be registers");
382 getContext().getRegisterInfo()->getEncodingValue(MCO.
getReg());
383 if ((Register & 0x6) == 0)
386 unsigned Lookback = (Register & 0x6) >> 1;
390 auto i = Instructions.end() - 1;
391 for (
auto n = Instructions.begin() - 1;; --
i, ++
Offset) {
400 if (Offset == Lookback)
403 auto const &Inst = *
i->getInst();
404 bool SubregBit = (Register & 0x1) != 0;
409 assert(Producer != Hexagon::NoRegister);
414 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
415 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
420 assert(Producer != Hexagon::NoRegister);
426 adjustExtendedInstructions(MI, MCB);
430 if(Extender !=
nullptr) {
440 void HexagonDisassembler::adjustExtendedInstructions(
MCInst &MCI,
441 MCInst const &MCB)
const {
453 case Hexagon::PS_storerbabs:
454 opcode = Hexagon::S2_storerbgp;
456 case Hexagon::PS_storerhabs:
457 opcode = Hexagon::S2_storerhgp;
459 case Hexagon::PS_storerfabs:
460 opcode = Hexagon::S2_storerfgp;
462 case Hexagon::PS_storeriabs:
463 opcode = Hexagon::S2_storerigp;
465 case Hexagon::PS_storerbnewabs:
466 opcode = Hexagon::S2_storerbnewgp;
468 case Hexagon::PS_storerhnewabs:
469 opcode = Hexagon::S2_storerhnewgp;
471 case Hexagon::PS_storerinewabs:
472 opcode = Hexagon::S2_storerinewgp;
474 case Hexagon::PS_storerdabs:
475 opcode = Hexagon::S2_storerdgp;
477 case Hexagon::PS_loadrbabs:
478 opcode = Hexagon::L2_loadrbgp;
480 case Hexagon::PS_loadrubabs:
481 opcode = Hexagon::L2_loadrubgp;
483 case Hexagon::PS_loadrhabs:
484 opcode = Hexagon::L2_loadrhgp;
486 case Hexagon::PS_loadruhabs:
487 opcode = Hexagon::L2_loadruhgp;
489 case Hexagon::PS_loadriabs:
490 opcode = Hexagon::L2_loadrigp;
492 case Hexagon::PS_loadrdabs:
493 opcode = Hexagon::L2_loadrdgp;
504 if (RegNo < Table.
size()) {
514 const void *Decoder) {
520 const void *Decoder) {
523 Hexagon::R5,
Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
524 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
525 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
526 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
527 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
528 Hexagon::R30, Hexagon::R31};
535 const void *Decoder) {
536 static const MCPhysReg VecRegDecoderTable[] = {
538 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
539 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
540 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
541 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
542 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
543 Hexagon::V30, Hexagon::V31};
550 const void *Decoder) {
551 static const MCPhysReg DoubleRegDecoderTable[] = {
552 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
553 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
554 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
555 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
562 const void *Decoder) {
563 static const MCPhysReg VecDblRegDecoderTable[] = {
564 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
565 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
566 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
567 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
574 const void *Decoder) {
575 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
576 Hexagon::P2, Hexagon::P3};
583 const void *Decoder) {
584 static const MCPhysReg VecPredRegDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
585 Hexagon::Q2, Hexagon::Q3};
592 const void *Decoder) {
593 static const MCPhysReg CtrlRegDecoderTable[] = {
594 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
595 Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7,
596 Hexagon::USR,
Hexagon::PC, Hexagon::UGP, Hexagon::GP,
597 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC
603 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
606 unsigned Register = CtrlRegDecoderTable[RegNo];
613 const void *Decoder) {
614 static const MCPhysReg CtrlReg64DecoderTable[] = {
615 Hexagon::C1_0, Hexagon::NoRegister,
616 Hexagon::C3_2, Hexagon::NoRegister,
617 Hexagon::C7_6, Hexagon::NoRegister,
618 Hexagon::C9_8, Hexagon::NoRegister,
619 Hexagon::C11_10, Hexagon::NoRegister,
620 Hexagon::CS, Hexagon::NoRegister,
621 Hexagon::UPC, Hexagon::NoRegister
627 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
630 unsigned Register = CtrlReg64DecoderTable[RegNo];
637 const void *Decoder) {
638 unsigned Register = 0;
641 Register = Hexagon::M0;
644 Register = Hexagon::M1;
663 assert(Success);(void)Success;
665 uint32_t Operand = Upper26 | Lower6;
671 HexagonDisassembler
const &Disassembler =
disassembler(Decoder);
672 int64_t FullValue =
fullValue(*Disassembler.MCII,
673 **Disassembler.CurrentBundle,
674 MI, SignExtend64<T>(tmp));
675 int64_t Extended = SignExtend64<32>(FullValue);
677 Disassembler.getContext());
682 const void *Decoder) {
683 HexagonDisassembler
const &Disassembler =
disassembler(Decoder);
684 int64_t FullValue =
fullValue(*Disassembler.MCII,
685 **Disassembler.CurrentBundle,
687 assert(FullValue >= 0 &&
"Negative in unsigned decoder");
693 uint64_t ,
const void *Decoder) {
694 signedDecoder<16>(
MI, tmp, Decoder);
699 uint64_t ,
const void *Decoder) {
700 signedDecoder<12>(
MI, tmp, Decoder);
705 uint64_t ,
const void *Decoder) {
706 signedDecoder<11>(
MI, tmp, Decoder);
711 uint64_t ,
const void *Decoder) {
717 uint64_t ,
const void *Decoder) {
718 signedDecoder<13>(
MI, tmp, Decoder);
723 uint64_t ,
const void *Decoder) {
724 signedDecoder<14>(
MI, tmp, Decoder);
729 uint64_t ,
const void *Decoder) {
730 signedDecoder<10>(
MI, tmp, Decoder);
735 const void *Decoder) {
736 signedDecoder<8>(
MI, tmp, Decoder);
741 uint64_t ,
const void *Decoder) {
742 signedDecoder<6>(
MI, tmp, Decoder);
747 uint64_t ,
const void *Decoder) {
748 signedDecoder<4>(
MI, tmp, Decoder);
753 uint64_t ,
const void *Decoder) {
754 signedDecoder<5>(
MI, tmp, Decoder);
759 uint64_t ,
const void *Decoder) {
760 signedDecoder<6>(
MI, tmp, Decoder);
765 uint64_t ,
const void *Decoder) {
766 signedDecoder<7>(
MI, tmp, Decoder);
771 uint64_t ,
const void *Decoder) {
772 signedDecoder<10>(
MI, tmp, Decoder);
777 uint64_t ,
const void *Decoder) {
778 signedDecoder<19>(
MI, tmp, Decoder);
784 const void *Decoder) {
785 HexagonDisassembler
const &Disassembler =
disassembler(Decoder);
791 **Disassembler.CurrentBundle,
793 int64_t Extended = SignExtend64<32>(FullValue) + Address;
794 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address,
true,
809 {S4_pstorerdfnew_abs, 0xafc02084},
810 {S4_pstorerdtnew_abs, 0xafc02080},
811 {S4_pstorerdf_abs, 0xafc00084},
812 {S4_pstorerdt_abs, 0xafc00080},
813 {S4_pstorerinewfnew_abs, 0xafa03084},
814 {S4_pstorerinewtnew_abs, 0xafa03080},
815 {S4_pstorerhnewfnew_abs, 0xafa02884},
816 {S4_pstorerhnewtnew_abs, 0xafa02880},
817 {S4_pstorerbnewfnew_abs, 0xafa02084},
818 {S4_pstorerbnewtnew_abs, 0xafa02080},
819 {S4_pstorerinewf_abs, 0xafa01084},
820 {S4_pstorerinewt_abs, 0xafa01080},
821 {S4_pstorerhnewf_abs, 0xafa00884},
822 {S4_pstorerhnewt_abs, 0xafa00880},
823 {S4_pstorerbnewf_abs, 0xafa00084},
824 {S4_pstorerbnewt_abs, 0xafa00080},
825 {S4_pstorerifnew_abs, 0xaf802084},
826 {S4_pstoreritnew_abs, 0xaf802080},
827 {S4_pstorerif_abs, 0xaf800084},
828 {S4_pstorerit_abs, 0xaf800080},
829 {S4_pstorerhfnew_abs, 0xaf402084},
830 {S4_pstorerhtnew_abs, 0xaf402080},
831 {S4_pstorerhf_abs, 0xaf400084},
832 {S4_pstorerht_abs, 0xaf400080},
833 {S4_pstorerbfnew_abs, 0xaf002084},
834 {S4_pstorerbtnew_abs, 0xaf002080},
835 {S4_pstorerbf_abs, 0xaf000084},
836 {S4_pstorerbt_abs, 0xaf000080}};
841 {PS_loadriabs, 0x49800000},
842 {PS_loadruhabs, 0x49600000},
843 {PS_loadrhabs, 0x49400000},
844 {PS_loadrubabs, 0x49200000},
845 {PS_loadrbabs, 0x49000000},
846 {PS_storerdabs, 0x48c00000},
847 {PS_storerinewabs, 0x48a01000},
848 {PS_storerhnewabs, 0x48a00800},
849 {PS_storerbnewabs, 0x48a00000},
850 {PS_storeriabs, 0x48800000},
851 {PS_storerfabs, 0x48600000},
852 {PS_storerhabs, 0x48400000},
853 {PS_storerbabs, 0x48000000}};
858 unsigned MachineOpcode = 0;
872 for (
size_t i = 0;
i <
NumLS; ++
i) {
888 switch (LLVMOpcode) {
893 case Hexagon::S4_pstorerdf_abs:
894 case Hexagon::S4_pstorerdt_abs:
895 case Hexagon::S4_pstorerdfnew_abs:
896 case Hexagon::S4_pstorerdtnew_abs:
898 Value = insn & UINT64_C(3);
901 Value = (insn >> 12) & UINT64_C(48);
902 Value |= (insn >> 3) & UINT64_C(15);
905 Value = (insn >> 8) & UINT64_C(31);
909 case Hexagon::S4_pstorerbnewf_abs:
910 case Hexagon::S4_pstorerbnewt_abs:
911 case Hexagon::S4_pstorerbnewfnew_abs:
912 case Hexagon::S4_pstorerbnewtnew_abs:
913 case Hexagon::S4_pstorerhnewf_abs:
914 case Hexagon::S4_pstorerhnewt_abs:
915 case Hexagon::S4_pstorerhnewfnew_abs:
916 case Hexagon::S4_pstorerhnewtnew_abs:
917 case Hexagon::S4_pstorerinewf_abs:
918 case Hexagon::S4_pstorerinewt_abs:
919 case Hexagon::S4_pstorerinewfnew_abs:
920 case Hexagon::S4_pstorerinewtnew_abs:
922 Value = insn & UINT64_C(3);
925 Value = (insn >> 12) & UINT64_C(48);
926 Value |= (insn >> 3) & UINT64_C(15);
929 Value = (insn >> 8) & UINT64_C(7);
933 case Hexagon::S4_pstorerbf_abs:
934 case Hexagon::S4_pstorerbt_abs:
935 case Hexagon::S4_pstorerbfnew_abs:
936 case Hexagon::S4_pstorerbtnew_abs:
937 case Hexagon::S4_pstorerhf_abs:
938 case Hexagon::S4_pstorerht_abs:
939 case Hexagon::S4_pstorerhfnew_abs:
940 case Hexagon::S4_pstorerhtnew_abs:
941 case Hexagon::S4_pstorerif_abs:
942 case Hexagon::S4_pstorerit_abs:
943 case Hexagon::S4_pstorerifnew_abs:
944 case Hexagon::S4_pstoreritnew_abs:
946 Value = insn & UINT64_C(3);
949 Value = (insn >> 12) & UINT64_C(48);
950 Value |= (insn >> 3) & UINT64_C(15);
953 Value = (insn >> 8) & UINT64_C(31);
957 case Hexagon::L4_ploadrdf_abs:
958 case Hexagon::L4_ploadrdt_abs:
959 case Hexagon::L4_ploadrdfnew_abs:
960 case Hexagon::L4_ploadrdtnew_abs:
962 Value = insn & UINT64_C(31);
965 Value = ((insn >> 9) & UINT64_C(3));
968 Value = ((insn >> 15) & UINT64_C(62));
969 Value |= ((insn >> 8) & UINT64_C(1));
973 case Hexagon::L4_ploadrbf_abs:
974 case Hexagon::L4_ploadrbt_abs:
975 case Hexagon::L4_ploadrbfnew_abs:
976 case Hexagon::L4_ploadrbtnew_abs:
977 case Hexagon::L4_ploadrhf_abs:
978 case Hexagon::L4_ploadrht_abs:
979 case Hexagon::L4_ploadrhfnew_abs:
980 case Hexagon::L4_ploadrhtnew_abs:
981 case Hexagon::L4_ploadrubf_abs:
982 case Hexagon::L4_ploadrubt_abs:
983 case Hexagon::L4_ploadrubfnew_abs:
984 case Hexagon::L4_ploadrubtnew_abs:
985 case Hexagon::L4_ploadruhf_abs:
986 case Hexagon::L4_ploadruht_abs:
987 case Hexagon::L4_ploadruhfnew_abs:
988 case Hexagon::L4_ploadruhtnew_abs:
989 case Hexagon::L4_ploadrif_abs:
990 case Hexagon::L4_ploadrit_abs:
991 case Hexagon::L4_ploadrifnew_abs:
992 case Hexagon::L4_ploadritnew_abs:
994 Value = insn & UINT64_C(31);
997 Value = (insn >> 9) & UINT64_C(3);
1000 Value = (insn >> 15) & UINT64_C(62);
1001 Value |= (insn >> 8) & UINT64_C(1);
1006 case (Hexagon::PS_loadriabs):
1009 case Hexagon::PS_loadrhabs:
1010 case Hexagon::PS_loadruhabs:
1013 case Hexagon::PS_loadrbabs:
1014 case Hexagon::PS_loadrubabs:
1016 Value |= insn & UINT64_C(31);
1018 Value = (insn >> 11) & UINT64_C(49152);
1019 Value |= (insn >> 7) & UINT64_C(15872);
1020 Value |= (insn >> 5) & UINT64_C(511);
1024 case Hexagon::PS_loadrdabs:
1025 Value = insn & UINT64_C(31);
1027 Value = (insn >> 11) & UINT64_C(49152);
1028 Value |= (insn >> 7) & UINT64_C(15872);
1029 Value |= (insn >> 5) & UINT64_C(511);
1033 case Hexagon::PS_storerdabs:
1035 Value = (insn >> 11) & UINT64_C(49152);
1036 Value |= (insn >> 7) & UINT64_C(15872);
1037 Value |= (insn >> 5) & UINT64_C(256);
1038 Value |= insn & UINT64_C(255);
1041 Value = (insn >> 8) & UINT64_C(31);
1046 case Hexagon::PS_storerinewabs:
1049 case Hexagon::PS_storerhnewabs:
1052 case Hexagon::PS_storerbnewabs:
1053 Value = (insn >> 11) & UINT64_C(49152);
1054 Value |= (insn >> 7) & UINT64_C(15872);
1055 Value |= (insn >> 5) & UINT64_C(256);
1056 Value |= insn & UINT64_C(255);
1059 Value = (insn >> 8) & UINT64_C(7);
1064 case Hexagon::PS_storeriabs:
1067 case Hexagon::PS_storerhabs:
1068 case Hexagon::PS_storerfabs:
1071 case Hexagon::PS_storerbabs:
1072 Value = (insn >> 11) & UINT64_C(49152);
1073 Value |= (insn >> 7) & UINT64_C(15872);
1074 Value |= (insn >> 5) & UINT64_C(256);
1075 Value |= insn & UINT64_C(255);
1078 Value = (insn >> 8) & UINT64_C(31);
1088 void const *Decoder) {
1090 if ((~insn & 0xf0000000) == 0xf0000000) {
1093 Value = (insn & 0x0fff0000) << 4;
1095 Value |= ((insn & 0x3fff) << 6);
1216 op = Hexagon::SL1_loadri_io;
1218 op = Hexagon::SL1_loadrub_io;
1220 os <<
"<unknown subinstruction>";
1226 op = Hexagon::SL2_deallocframe;
1228 op = Hexagon::SL2_jumpr31;
1230 op = Hexagon::SL2_jumpr31_f;
1232 op = Hexagon::SL2_jumpr31_fnew;
1234 op = Hexagon::SL2_jumpr31_t;
1236 op = Hexagon::SL2_jumpr31_tnew;
1238 op = Hexagon::SL2_loadrb_io;
1240 op = Hexagon::SL2_loadrd_sp;
1242 op = Hexagon::SL2_loadrh_io;
1244 op = Hexagon::SL2_loadri_sp;
1246 op = Hexagon::SL2_loadruh_io;
1248 op = Hexagon::SL2_return;
1250 op = Hexagon::SL2_return_f;
1252 op = Hexagon::SL2_return_fnew;
1254 op = Hexagon::SL2_return_t;
1256 op = Hexagon::SL2_return_tnew;
1258 os <<
"<unknown subinstruction>";
1264 op = Hexagon::SA1_addi;
1266 op = Hexagon::SA1_addrx;
1268 op = Hexagon::SA1_addsp;
1270 op = Hexagon::SA1_and1;
1272 op = Hexagon::SA1_clrf;
1274 op = Hexagon::SA1_clrfnew;
1276 op = Hexagon::SA1_clrt;
1278 op = Hexagon::SA1_clrtnew;
1280 op = Hexagon::SA1_cmpeqi;
1282 op = Hexagon::SA1_combine0i;
1284 op = Hexagon::SA1_combine1i;
1286 op = Hexagon::SA1_combine2i;
1288 op = Hexagon::SA1_combine3i;
1290 op = Hexagon::SA1_combinerz;
1292 op = Hexagon::SA1_combinezr;
1294 op = Hexagon::SA1_dec;
1296 op = Hexagon::SA1_inc;
1298 op = Hexagon::SA1_seti;
1300 op = Hexagon::SA1_setin1;
1302 op = Hexagon::SA1_sxtb;
1304 op = Hexagon::SA1_sxth;
1306 op = Hexagon::SA1_tfr;
1308 op = Hexagon::SA1_zxtb;
1310 op = Hexagon::SA1_zxth;
1312 os <<
"<unknown subinstruction>";
1318 op = Hexagon::SS1_storeb_io;
1320 op = Hexagon::SS1_storew_io;
1322 os <<
"<unknown subinstruction>";
1328 op = Hexagon::SS2_allocframe;
1330 op = Hexagon::SS2_storebi0;
1332 op = Hexagon::SS2_storebi1;
1334 op = Hexagon::SS2_stored_sp;
1336 op = Hexagon::SS2_storeh_io;
1338 op = Hexagon::SS2_storew_sp;
1340 op = Hexagon::SS2_storewi0;
1342 op = Hexagon::SS2_storewi1;
1344 os <<
"<unknown subinstruction>";
1356 if (encoded_reg < 8)
1357 return Hexagon::R0 + encoded_reg;
1358 else if (encoded_reg < 16)
1359 return Hexagon::R0 + encoded_reg + 8;
1362 return Hexagon::NoRegister;
1366 if (encoded_dreg < 4)
1367 return Hexagon::D0 + encoded_dreg;
1368 else if (encoded_dreg < 8)
1369 return Hexagon::D0 + encoded_dreg + 4;
1372 return Hexagon::NoRegister;
1375 void HexagonDisassembler::addSubinstOperands(
MCInst *MI,
unsigned opcode,
1376 unsigned inst)
const {
1380 case Hexagon::SL2_deallocframe:
1381 case Hexagon::SL2_jumpr31:
1382 case Hexagon::SL2_jumpr31_f:
1383 case Hexagon::SL2_jumpr31_fnew:
1384 case Hexagon::SL2_jumpr31_t:
1385 case Hexagon::SL2_jumpr31_tnew:
1386 case Hexagon::SL2_return:
1387 case Hexagon::SL2_return_f:
1388 case Hexagon::SL2_return_fnew:
1389 case Hexagon::SL2_return_t:
1390 case Hexagon::SL2_return_tnew:
1393 case Hexagon::SS2_allocframe:
1395 operand = ((inst & 0x1f0) >> 4) << 3;
1398 case Hexagon::SL1_loadri_io:
1406 operand = (inst & 0xf00) >> 6;
1409 case Hexagon::SL1_loadrub_io:
1417 operand = (inst & 0xf00) >> 8;
1420 case Hexagon::SL2_loadrb_io:
1428 operand = (inst & 0x700) >> 8;
1431 case Hexagon::SL2_loadrh_io:
1432 case Hexagon::SL2_loadruh_io:
1440 operand = ((inst & 0x700) >> 8) << 1;
1443 case Hexagon::SL2_loadrd_sp:
1448 operand = ((inst & 0x0f8) >> 3) << 3;
1451 case Hexagon::SL2_loadri_sp:
1456 operand = ((inst & 0x1f0) >> 4) << 2;
1459 case Hexagon::SA1_addi:
1465 operand = SignExtend64<7>((inst & 0x7f0) >> 4);
1468 case Hexagon::SA1_addrx:
1478 case Hexagon::SA1_and1:
1479 case Hexagon::SA1_dec:
1480 case Hexagon::SA1_inc:
1481 case Hexagon::SA1_sxtb:
1482 case Hexagon::SA1_sxth:
1483 case Hexagon::SA1_tfr:
1484 case Hexagon::SA1_zxtb:
1485 case Hexagon::SA1_zxth:
1494 case Hexagon::SA1_addsp:
1499 operand = ((inst & 0x3f0) >> 4) << 2;
1502 case Hexagon::SA1_seti:
1507 operand = (inst & 0x3f0) >> 4;
1510 case Hexagon::SA1_clrf:
1511 case Hexagon::SA1_clrfnew:
1512 case Hexagon::SA1_clrt:
1513 case Hexagon::SA1_clrtnew:
1514 case Hexagon::SA1_setin1:
1519 if (opcode == Hexagon::SA1_setin1)
1523 case Hexagon::SA1_cmpeqi:
1528 operand = inst & 0x3;
1531 case Hexagon::SA1_combine0i:
1532 case Hexagon::SA1_combine1i:
1533 case Hexagon::SA1_combine2i:
1534 case Hexagon::SA1_combine3i:
1539 operand = (inst & 0x060) >> 5;
1542 case Hexagon::SA1_combinerz:
1543 case Hexagon::SA1_combinezr:
1552 case Hexagon::SS1_storeb_io:
1557 operand = (inst & 0xf00) >> 8;
1563 case Hexagon::SS1_storew_io:
1568 operand = ((inst & 0xf00) >> 8) << 2;
1574 case Hexagon::SS2_storebi0:
1575 case Hexagon::SS2_storebi1:
1580 operand = inst & 0xf;
1583 case Hexagon::SS2_storewi0:
1584 case Hexagon::SS2_storewi1:
1589 operand = (inst & 0xf) << 2;
1592 case Hexagon::SS2_stored_sp:
1594 operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
1600 case Hexagon::SS2_storeh_io:
1605 operand = ((inst & 0x700) >> 8) << 1;
1611 case Hexagon::SS2_storew_sp:
1613 operand = ((inst & 0x1f0) >> 4) << 2;
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
DecodeStatus
Ternary decode status.
static MCOperand createExpr(const MCExpr *Val)
static const size_t NumLS
Superclass for all disassemblers.
static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static const unsigned int StoreConditionalOpcodeData[][2]
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
void setInnerLoop(MCInst &MCI)
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
bool isImmext(MCInst const &MCI)
static MCOperand createReg(unsigned Reg)
static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static HexagonDisassembler const & disassembler(void const *Decoder)
static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Context object for machine code objects.
static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
unsigned getReg() const
Returns the register number.
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
size_t size() const
size - Get the array size.
iterator insert(iterator I, const MCOperand &Op)
static unsigned getRegFromSubinstEncoding(unsigned encoded_reg)
Instances of this class represent a single low-level machine instruction.
static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg)
const MCExpr * getExpr() const
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, void const *Decoder)
static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
Interface to description of machine instruction set.
static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, raw_ostream &os)
void setOuterLoop(MCInst &MCI)
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, int64_t Value)
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void LLVMInitializeHexagonDisassembler()
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
static const unsigned IntRegDecoderTable[]
static unsigned int LoadStoreOpcodeData[][2]
void setOpcode(unsigned Op)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
static const size_t NumCondS
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Promote Memory to Register
static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
unsigned getOpcode() const
Target - Wrapper for Target specific information.
static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createInst(const MCInst *Val)
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInst * getInst() const
size_t bundleSize(MCInst const &MCI)
static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
void setReg(unsigned Reg)
Set the register number.
static MCContext & contextFromDecoder(void const *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define HEXAGON_INSTR_SIZE
LLVM Value Representation.
Check for a valid bundle.
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
static MCOperand createImm(int64_t Val)
static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
Target & getTheHexagonTarget()
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)