39 #define DEBUG_TYPE "amdgpu-disassembler"
53 uint64_t Addr,
const void *Decoder) {
56 APInt SignedOffset(18, Imm * 4,
true);
57 int64_t
Offset = (SignedOffset.
sext(64) + 4 + Addr).getSExtValue();
59 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr,
true, 2, 2))
64 #define DECODE_OPERAND2(RegClass, DecName) \
65 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
68 const void *Decoder) { \
69 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
70 return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \
73 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass)
95 const void *Decoder) {
97 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
100 #define GET_SUBTARGETINFO_ENUM
101 #include "AMDGPUGenSubtargetInfo.inc"
102 #undef GET_SUBTARGETINFO_ENUM
104 #include "AMDGPUGenDisassemblerTables.inc"
112 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.
data());
113 Bytes = Bytes.
slice(
sizeof(
T));
124 const auto SavedBytes = Bytes;
143 const unsigned MaxInstBytesNum = (
std::min)((
size_t)8, Bytes_.
size());
144 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
153 if (Bytes.
size() >= 8) {
154 const uint64_t QW = eatBytes<uint64_t>(Bytes);
163 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
166 if (Bytes.
size() < 4)
break;
167 const uint32_t DW = eatBytes<uint32_t>(Bytes);
174 if (Bytes.
size() < 4)
break;
175 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
182 Size = Res ? (MaxInstBytesNum - Bytes.
size()) : 0;
193 const Twine& ErrMsg)
const {
208 unsigned Val)
const {
209 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
210 if (Val >= RegCl.getNumRegs())
212 ": unknown register " +
Twine(Val));
218 unsigned Val)
const {
222 switch (SRegClassID) {
223 case AMDGPU::SGPR_32RegClassID:
224 case AMDGPU::TTMP_32RegClassID:
226 case AMDGPU::SGPR_64RegClassID:
227 case AMDGPU::TTMP_64RegClassID:
230 case AMDGPU::SGPR_128RegClassID:
231 case AMDGPU::TTMP_128RegClassID:
234 case AMDGPU::SReg_256RegClassID:
237 case AMDGPU::SReg_512RegClassID:
246 if (Val % (1 << shift)) {
248 <<
": scalar reg isn't aligned " << Val;
295 unsigned Val)
const {
325 if (Bytes.
size() < 4)
326 return errOperand(0,
"cannot read literal, inst bytes left " +
332 using namespace AMDGPU::EncValues;
384 return 0x3fc45f306dc9c882;
433 using namespace AMDGPU;
439 return VGPR_32RegClassID;
440 case OPW64:
return VReg_64RegClassID;
441 case OPW128:
return VReg_128RegClassID;
446 using namespace AMDGPU;
452 return SGPR_32RegClassID;
453 case OPW64:
return SGPR_64RegClassID;
454 case OPW128:
return SGPR_128RegClassID;
459 using namespace AMDGPU;
465 return TTMP_32RegClassID;
466 case OPW64:
return TTMP_64RegClassID;
467 case OPW128:
return TTMP_128RegClassID;
472 using namespace AMDGPU::EncValues;
509 using namespace AMDGPU;
536 using namespace AMDGPU;
555 uint64_t ,
bool IsBranch,
556 uint64_t , uint64_t ) {
557 typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy;
558 typedef std::vector<SymbolInfoTy> SectionSymbolsTy;
564 auto *Symbols =
static_cast<SectionSymbolsTy *
>(DisInfo);
565 auto Result =
std::find_if(Symbols->begin(), Symbols->end(),
566 [Value](
const SymbolInfoTy& Val) {
567 return std::get<0>(Val) == static_cast<uint64_t>(Value)
570 if (Result != Symbols->end()) {
571 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
594 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
static int64_t getInlineImmVal16(unsigned Imm)
Target & getTheGCNTarget()
The target for GCN GPUs.
#define DECODE_OPERAND(RegClass)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
static MCOperand createExpr(const MCExpr *Val)
Superclass for all disassemblers.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
raw_ostream * CommentStream
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MCOperand decodeOperand_VReg_64(unsigned Val) const
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeOperand_VS_64(unsigned Val) const
static MCOperand createReg(unsigned Reg)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
MCOperand decodeOperand_VReg_96(unsigned Val) const
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
TargetRegisterInfo interface that is implemented by all hw codegen targets.
static int64_t getInlineImmVal32(unsigned Imm)
Context object for machine code objects.
const MCSubtargetInfo & STI
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeSpecialReg32(unsigned Val) const
MCContext & getContext() const
size_t size() const
size - Get the array size.
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
Instances of this class represent a single low-level machine instruction.
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
MCOperand decodeOperand_SReg_512(unsigned Val) const
Symbolize and annotate disassembled instructions.
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
MCOperand decodeOperand_SReg_128(unsigned Val) const
APInt sext(unsigned width) const
Sign extend to a new width.
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static int64_t getInlineImmVal64(unsigned Imm)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
llvm::MCDisassembler::DecodeStatus DecodeStatus
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeOperand_VSrc16(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
uint64_t DoubleToBits(double Double)
DoubleToBits - This function takes a double and returns the bit equivalent 64-bit integer...
MCOperand decodeOperand_VReg_128(unsigned Val) const
static MCOperand decodeIntImmed(unsigned Imm)
unsigned getOpcode() const
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
const MCRegisterInfo * getRegisterInfo() const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
void LLVMInitializeAMDGPUDisassembler()
bool isVI(const MCSubtargetInfo &STI)
unsigned getNumOperands() const
This file contains declaration for AMDGPU ISA disassembler.
MCOperand decodeSpecialReg64(unsigned Val) const
MCSubtargetInfo - Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
unsigned getTtmpClassId(const OpWidthTy Width) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getVgprClassId(const OpWidthTy Width) const
LLVM Value Representation.
MCOperand decodeOperand_SReg_64(unsigned Val) const
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
MCOperand decodeLiteralConstant() const
void addOperand(const MCOperand &Op)
MCOperand decodeOperand_SReg_256(unsigned Val) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
auto find_if(R &&Range, UnaryPredicate P) -> decltype(std::begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Instances of this class represent operands of the MCInst class.
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
static MCOperand createImm(int64_t Val)