LLVM  4.0.0
LiveRangeCalc.cpp
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1 //===---- LiveRangeCalc.cpp - Calculate live ranges -----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implementation of the LiveRangeCalc class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "LiveRangeCalc.h"
15 #include "llvm/ADT/SetVector.h"
18 
19 using namespace llvm;
20 
21 #define DEBUG_TYPE "regalloc"
22 
23 void LiveRangeCalc::resetLiveOutMap() {
24  unsigned NumBlocks = MF->getNumBlockIDs();
25  Seen.clear();
26  Seen.resize(NumBlocks);
27  EntryInfoMap.clear();
28  Map.resize(NumBlocks);
29 }
30 
32  SlotIndexes *SI,
34  VNInfo::Allocator *VNIA) {
35  MF = mf;
36  MRI = &MF->getRegInfo();
37  Indexes = SI;
38  DomTree = MDT;
39  Alloc = VNIA;
40  resetLiveOutMap();
41  LiveIn.clear();
42 }
43 
44 
45 static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
46  LiveRange &LR, const MachineOperand &MO) {
47  const MachineInstr &MI = *MO.getParent();
48  SlotIndex DefIdx =
50 
51  // Create the def in LR. This may find an existing def.
52  LR.createDeadDef(DefIdx, Alloc);
53 }
54 
55 void LiveRangeCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
56  assert(MRI && Indexes && "call reset() first");
57 
58  // Step 1: Create minimal live segments for every definition of Reg.
59  // Visit all def operands. If the same instruction has multiple defs of Reg,
60  // createDeadDef() will deduplicate.
61  const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
62  unsigned Reg = LI.reg;
63  for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
64  if (!MO.isDef() && !MO.readsReg())
65  continue;
66 
67  unsigned SubReg = MO.getSubReg();
68  if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
69  LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
70  : MRI->getMaxLaneMaskForVReg(Reg);
71  // If this is the first time we see a subregister def, initialize
72  // subranges by creating a copy of the main range.
73  if (!LI.hasSubRanges() && !LI.empty()) {
74  LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
75  LI.createSubRangeFrom(*Alloc, ClassMask, LI);
76  }
77 
78  LaneBitmask Mask = SubMask;
79  for (LiveInterval::SubRange &S : LI.subranges()) {
80  // A Mask for subregs common to the existing subrange and current def.
81  LaneBitmask Common = S.LaneMask & Mask;
82  if (Common.none())
83  continue;
84  LiveInterval::SubRange *CommonRange;
85  // A Mask for subregs covered by the subrange but not the current def.
86  LaneBitmask RM = S.LaneMask & ~Mask;
87  if (RM.any()) {
88  // Split the subrange S into two parts: one covered by the current
89  // def (CommonRange), and the one not affected by it (updated S).
90  S.LaneMask = RM;
91  CommonRange = LI.createSubRangeFrom(*Alloc, Common, S);
92  } else {
93  assert(Common == S.LaneMask);
94  CommonRange = &S;
95  }
96  if (MO.isDef())
97  createDeadDef(*Indexes, *Alloc, *CommonRange, MO);
98  Mask &= ~Common;
99  }
100  // Create a new SubRange for subregs we did not cover yet.
101  if (Mask.any()) {
102  LiveInterval::SubRange *NewRange = LI.createSubRange(*Alloc, Mask);
103  if (MO.isDef())
104  createDeadDef(*Indexes, *Alloc, *NewRange, MO);
105  }
106  }
107 
108  // Create the def in the main liverange. We do not have to do this if
109  // subranges are tracked as we recreate the main range later in this case.
110  if (MO.isDef() && !LI.hasSubRanges())
111  createDeadDef(*Indexes, *Alloc, LI, MO);
112  }
113 
114  // We may have created empty live ranges for partially undefined uses, we
115  // can't keep them because we won't find defs in them later.
117 
118  // Step 2: Extend live segments to all uses, constructing SSA form as
119  // necessary.
120  if (LI.hasSubRanges()) {
121  for (LiveInterval::SubRange &S : LI.subranges()) {
122  LiveRangeCalc SubLRC;
123  SubLRC.reset(MF, Indexes, DomTree, Alloc);
124  SubLRC.extendToUses(S, Reg, S.LaneMask, &LI);
125  }
126  LI.clear();
128  } else {
129  resetLiveOutMap();
130  extendToUses(LI, Reg, LaneBitmask::getAll());
131  }
132 }
133 
135  // First create dead defs at all defs found in subranges.
136  LiveRange &MainRange = LI;
137  assert(MainRange.segments.empty() && MainRange.valnos.empty() &&
138  "Expect empty main liverange");
139 
140  for (const LiveInterval::SubRange &SR : LI.subranges()) {
141  for (const VNInfo *VNI : SR.valnos) {
142  if (!VNI->isUnused() && !VNI->isPHIDef())
143  MainRange.createDeadDef(VNI->def, *Alloc);
144  }
145  }
146  resetLiveOutMap();
147  extendToUses(MainRange, LI.reg, LaneBitmask::getAll(), &LI);
148 }
149 
151  assert(MRI && Indexes && "call reset() first");
152 
153  // Visit all def operands. If the same instruction has multiple defs of Reg,
154  // LR.createDeadDef() will deduplicate.
155  for (MachineOperand &MO : MRI->def_operands(Reg))
156  createDeadDef(*Indexes, *Alloc, LR, MO);
157 }
158 
159 
160 void LiveRangeCalc::extendToUses(LiveRange &LR, unsigned Reg, LaneBitmask Mask,
161  LiveInterval *LI) {
163  if (LI != nullptr)
164  LI->computeSubRangeUndefs(Undefs, Mask, *MRI, *Indexes);
165 
166  // Visit all operands that read Reg. This may include partial defs.
167  bool IsSubRange = !Mask.all();
168  const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
169  for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
170  // Clear all kill flags. They will be reinserted after register allocation
171  // by LiveIntervalAnalysis::addKillFlags().
172  if (MO.isUse())
173  MO.setIsKill(false);
174  // MO::readsReg returns "true" for subregister defs. This is for keeping
175  // liveness of the entire register (i.e. for the main range of the live
176  // interval). For subranges, definitions of non-overlapping subregisters
177  // do not count as uses.
178  if (!MO.readsReg() || (IsSubRange && MO.isDef()))
179  continue;
180 
181  unsigned SubReg = MO.getSubReg();
182  if (SubReg != 0) {
183  LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
184  if (MO.isDef())
185  SLM = ~SLM;
186  // Ignore uses not reading the current (sub)range.
187  if ((SLM & Mask).none())
188  continue;
189  }
190 
191  // Determine the actual place of the use.
192  const MachineInstr *MI = MO.getParent();
193  unsigned OpNo = (&MO - &MI->getOperand(0));
194  SlotIndex UseIdx;
195  if (MI->isPHI()) {
196  assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
197  // The actual place where a phi operand is used is the end of the pred
198  // MBB. PHI operands are paired: (Reg, PredMBB).
199  UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
200  } else {
201  // Check for early-clobber redefs.
202  bool isEarlyClobber = false;
203  unsigned DefIdx;
204  if (MO.isDef())
205  isEarlyClobber = MO.isEarlyClobber();
206  else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
207  // FIXME: This would be a lot easier if tied early-clobber uses also
208  // had an early-clobber flag.
209  isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
210  }
211  UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
212  }
213 
214  // MI is reading Reg. We may have visited MI before if it happens to be
215  // reading Reg multiple times. That is OK, extend() is idempotent.
216  extend(LR, UseIdx, Reg, Undefs);
217  }
218 }
219 
220 
221 void LiveRangeCalc::updateFromLiveIns() {
222  LiveRangeUpdater Updater;
223  for (const LiveInBlock &I : LiveIn) {
224  if (!I.DomNode)
225  continue;
226  MachineBasicBlock *MBB = I.DomNode->getBlock();
227  assert(I.Value && "No live-in value found");
228  SlotIndex Start, End;
229  std::tie(Start, End) = Indexes->getMBBRange(MBB);
230 
231  if (I.Kill.isValid())
232  // Value is killed inside this block.
233  End = I.Kill;
234  else {
235  // The value is live-through, update LiveOut as well.
236  // Defer the Domtree lookup until it is needed.
237  assert(Seen.test(MBB->getNumber()));
238  Map[MBB] = LiveOutPair(I.Value, nullptr);
239  }
240  Updater.setDest(&I.LR);
241  Updater.add(Start, End, I.Value);
242  }
243  LiveIn.clear();
244 }
245 
246 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
247  ArrayRef<SlotIndex> Undefs) {
248  assert(Use.isValid() && "Invalid SlotIndex");
249  assert(Indexes && "Missing SlotIndexes");
250  assert(DomTree && "Missing dominator tree");
251 
252  MachineBasicBlock *UseMBB = Indexes->getMBBFromIndex(Use.getPrevSlot());
253  assert(UseMBB && "No MBB at Use");
254 
255  // Is there a def in the same MBB we can extend?
256  auto EP = LR.extendInBlock(Undefs, Indexes->getMBBStartIdx(UseMBB), Use);
257  if (EP.first != nullptr || EP.second)
258  return;
259 
260  // Find the single reaching def, or determine if Use is jointly dominated by
261  // multiple values, and we may need to create even more phi-defs to preserve
262  // VNInfo SSA form. Perform a search for all predecessor blocks where we
263  // know the dominating VNInfo.
264  if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs))
265  return;
266 
267  // When there were multiple different values, we may need new PHIs.
268  calculateValues();
269 }
270 
271 
272 // This function is called by a client after using the low-level API to add
273 // live-out and live-in blocks. The unique value optimization is not
274 // available, SplitEditor::transferValues handles that case directly anyway.
276  assert(Indexes && "Missing SlotIndexes");
277  assert(DomTree && "Missing dominator tree");
278  updateSSA();
279  updateFromLiveIns();
280 }
281 
282 
283 bool LiveRangeCalc::isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
284  MachineBasicBlock &MBB, BitVector &DefOnEntry,
285  BitVector &UndefOnEntry) {
286  unsigned BN = MBB.getNumber();
287  if (DefOnEntry[BN])
288  return true;
289  if (UndefOnEntry[BN])
290  return false;
291 
292  auto MarkDefined =
293  [this,BN,&DefOnEntry,&UndefOnEntry] (MachineBasicBlock &B) -> bool {
294  for (MachineBasicBlock *S : B.successors())
295  DefOnEntry[S->getNumber()] = true;
296  DefOnEntry[BN] = true;
297  return true;
298  };
299 
300  SetVector<unsigned> WorkList;
301  // Checking if the entry of MBB is reached by some def: add all predecessors
302  // that are potentially defined-on-exit to the work list.
303  for (MachineBasicBlock *P : MBB.predecessors())
304  WorkList.insert(P->getNumber());
305 
306  for (unsigned i = 0; i != WorkList.size(); ++i) {
307  // Determine if the exit from the block is reached by some def.
308  unsigned N = WorkList[i];
310  if (Seen[N] && Map[&B].first != nullptr)
311  return MarkDefined(B);
312  SlotIndex Begin, End;
313  std::tie(Begin, End) = Indexes->getMBBRange(&B);
314  LiveRange::iterator UB = std::upper_bound(LR.begin(), LR.end(), End);
315  if (UB != LR.begin()) {
316  LiveRange::Segment &Seg = *std::prev(UB);
317  if (Seg.end > Begin) {
318  // There is a segment that overlaps B. If the range is not explicitly
319  // undefined between the end of the segment and the end of the block,
320  // treat the block as defined on exit. If it is, go to the next block
321  // on the work list.
322  if (LR.isUndefIn(Undefs, Seg.end, End))
323  continue;
324  return MarkDefined(B);
325  }
326  }
327 
328  // No segment overlaps with this block. If this block is not defined on
329  // entry, or it undefines the range, do not process its predecessors.
330  if (UndefOnEntry[N] || LR.isUndefIn(Undefs, Begin, End)) {
331  UndefOnEntry[N] = true;
332  continue;
333  }
334  if (DefOnEntry[N])
335  return MarkDefined(B);
336 
337  // Still don't know: add all predecessors to the work list.
338  for (MachineBasicBlock *P : B.predecessors())
339  WorkList.insert(P->getNumber());
340  }
341 
342  UndefOnEntry[BN] = true;
343  return false;
344 }
345 
346 bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
347  SlotIndex Use, unsigned PhysReg,
348  ArrayRef<SlotIndex> Undefs) {
349  unsigned UseMBBNum = UseMBB.getNumber();
350 
351  // Block numbers where LR should be live-in.
352  SmallVector<unsigned, 16> WorkList(1, UseMBBNum);
353 
354  // Remember if we have seen more than one value.
355  bool UniqueVNI = true;
356  VNInfo *TheVNI = nullptr;
357 
358  bool FoundUndef = false;
359 
360  // Using Seen as a visited set, perform a BFS for all reaching defs.
361  for (unsigned i = 0; i != WorkList.size(); ++i) {
362  MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
363 
364 #ifndef NDEBUG
365  if (MBB->pred_empty()) {
366  MBB->getParent()->verify();
367  errs() << "Use of " << PrintReg(PhysReg)
368  << " does not have a corresponding definition on every path:\n";
369  const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);
370  if (MI != nullptr)
371  errs() << Use << " " << *MI;
372  report_fatal_error("Use not jointly dominated by defs.");
373  }
374 
376  !MBB->isLiveIn(PhysReg)) {
377  MBB->getParent()->verify();
378  const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
379  errs() << "The register " << PrintReg(PhysReg, TRI)
380  << " needs to be live in to BB#" << MBB->getNumber()
381  << ", but is missing from the live-in list.\n";
382  report_fatal_error("Invalid global physical register");
383  }
384 #endif
385  FoundUndef |= MBB->pred_empty();
386 
388  PE = MBB->pred_end(); PI != PE; ++PI) {
389  MachineBasicBlock *Pred = *PI;
390 
391  // Is this a known live-out block?
392  if (Seen.test(Pred->getNumber())) {
393  if (VNInfo *VNI = Map[Pred].first) {
394  if (TheVNI && TheVNI != VNI)
395  UniqueVNI = false;
396  TheVNI = VNI;
397  }
398  continue;
399  }
400 
401  SlotIndex Start, End;
402  std::tie(Start, End) = Indexes->getMBBRange(Pred);
403 
404  // First time we see Pred. Try to determine the live-out value, but set
405  // it as null if Pred is live-through with an unknown value.
406  auto EP = LR.extendInBlock(Undefs, Start, End);
407  VNInfo *VNI = EP.first;
408  FoundUndef |= EP.second;
409  setLiveOutValue(Pred, VNI);
410  if (VNI) {
411  if (TheVNI && TheVNI != VNI)
412  UniqueVNI = false;
413  TheVNI = VNI;
414  }
415  if (VNI || EP.second)
416  continue;
417 
418  // No, we need a live-in value for Pred as well
419  if (Pred != &UseMBB)
420  WorkList.push_back(Pred->getNumber());
421  else
422  // Loopback to UseMBB, so value is really live through.
423  Use = SlotIndex();
424  }
425  }
426 
427  LiveIn.clear();
428  FoundUndef |= (TheVNI == nullptr);
429  if (Undefs.size() > 0 && FoundUndef)
430  UniqueVNI = false;
431 
432  // Both updateSSA() and LiveRangeUpdater benefit from ordered blocks, but
433  // neither require it. Skip the sorting overhead for small updates.
434  if (WorkList.size() > 4)
435  array_pod_sort(WorkList.begin(), WorkList.end());
436 
437  // If a unique reaching def was found, blit in the live ranges immediately.
438  if (UniqueVNI) {
439  assert(TheVNI != nullptr);
440  LiveRangeUpdater Updater(&LR);
441  for (unsigned BN : WorkList) {
442  SlotIndex Start, End;
443  std::tie(Start, End) = Indexes->getMBBRange(BN);
444  // Trim the live range in UseMBB.
445  if (BN == UseMBBNum && Use.isValid())
446  End = Use;
447  else
448  Map[MF->getBlockNumbered(BN)] = LiveOutPair(TheVNI, nullptr);
449  Updater.add(Start, End, TheVNI);
450  }
451  return true;
452  }
453 
454  // Prepare the defined/undefined bit vectors.
455  auto EF = EntryInfoMap.find(&LR);
456  if (EF == EntryInfoMap.end()) {
457  unsigned N = MF->getNumBlockIDs();
458  EF = EntryInfoMap.insert({&LR, {BitVector(), BitVector()}}).first;
459  EF->second.first.resize(N);
460  EF->second.second.resize(N);
461  }
462  BitVector &DefOnEntry = EF->second.first;
463  BitVector &UndefOnEntry = EF->second.second;
464 
465  // Multiple values were found, so transfer the work list to the LiveIn array
466  // where UpdateSSA will use it as a work list.
467  LiveIn.reserve(WorkList.size());
468  for (unsigned BN : WorkList) {
469  MachineBasicBlock *MBB = MF->getBlockNumbered(BN);
470  if (Undefs.size() > 0 && !isDefOnEntry(LR, Undefs, *MBB, DefOnEntry, UndefOnEntry))
471  continue;
472  addLiveInBlock(LR, DomTree->getNode(MBB));
473  if (MBB == &UseMBB)
474  LiveIn.back().Kill = Use;
475  }
476 
477  return false;
478 }
479 
480 
481 // This is essentially the same iterative algorithm that SSAUpdater uses,
482 // except we already have a dominator tree, so we don't have to recompute it.
483 void LiveRangeCalc::updateSSA() {
484  assert(Indexes && "Missing SlotIndexes");
485  assert(DomTree && "Missing dominator tree");
486 
487  // Interate until convergence.
488  unsigned Changes;
489  do {
490  Changes = 0;
491  // Propagate live-out values down the dominator tree, inserting phi-defs
492  // when necessary.
493  for (LiveInBlock &I : LiveIn) {
494  MachineDomTreeNode *Node = I.DomNode;
495  // Skip block if the live-in value has already been determined.
496  if (!Node)
497  continue;
498  MachineBasicBlock *MBB = Node->getBlock();
499  MachineDomTreeNode *IDom = Node->getIDom();
500  LiveOutPair IDomValue;
501 
502  // We need a live-in value to a block with no immediate dominator?
503  // This is probably an unreachable block that has survived somehow.
504  bool needPHI = !IDom || !Seen.test(IDom->getBlock()->getNumber());
505 
506  // IDom dominates all of our predecessors, but it may not be their
507  // immediate dominator. Check if any of them have live-out values that are
508  // properly dominated by IDom. If so, we need a phi-def here.
509  if (!needPHI) {
510  IDomValue = Map[IDom->getBlock()];
511 
512  // Cache the DomTree node that defined the value.
513  if (IDomValue.first && !IDomValue.second)
514  Map[IDom->getBlock()].second = IDomValue.second =
515  DomTree->getNode(Indexes->getMBBFromIndex(IDomValue.first->def));
516 
518  PE = MBB->pred_end(); PI != PE; ++PI) {
519  LiveOutPair &Value = Map[*PI];
520  if (!Value.first || Value.first == IDomValue.first)
521  continue;
522 
523  // Cache the DomTree node that defined the value.
524  if (!Value.second)
525  Value.second =
526  DomTree->getNode(Indexes->getMBBFromIndex(Value.first->def));
527 
528  // This predecessor is carrying something other than IDomValue.
529  // It could be because IDomValue hasn't propagated yet, or it could be
530  // because MBB is in the dominance frontier of that value.
531  if (DomTree->dominates(IDom, Value.second)) {
532  needPHI = true;
533  break;
534  }
535  }
536  }
537 
538  // The value may be live-through even if Kill is set, as can happen when
539  // we are called from extendRange. In that case LiveOutSeen is true, and
540  // LiveOut indicates a foreign or missing value.
541  LiveOutPair &LOP = Map[MBB];
542 
543  // Create a phi-def if required.
544  if (needPHI) {
545  ++Changes;
546  assert(Alloc && "Need VNInfo allocator to create PHI-defs");
547  SlotIndex Start, End;
548  std::tie(Start, End) = Indexes->getMBBRange(MBB);
549  LiveRange &LR = I.LR;
550  VNInfo *VNI = LR.getNextValue(Start, *Alloc);
551  I.Value = VNI;
552  // This block is done, we know the final value.
553  I.DomNode = nullptr;
554 
555  // Add liveness since updateFromLiveIns now skips this node.
556  if (I.Kill.isValid()) {
557  if (VNI)
558  LR.addSegment(LiveInterval::Segment(Start, I.Kill, VNI));
559  } else {
560  if (VNI)
561  LR.addSegment(LiveInterval::Segment(Start, End, VNI));
562  LOP = LiveOutPair(VNI, Node);
563  }
564  } else if (IDomValue.first) {
565  // No phi-def here. Remember incoming value.
566  I.Value = IDomValue.first;
567 
568  // If the IDomValue is killed in the block, don't propagate through.
569  if (I.Kill.isValid())
570  continue;
571 
572  // Propagate IDomValue if it isn't killed:
573  // MBB is live-out and doesn't define its own value.
574  if (LOP.first == IDomValue.first)
575  continue;
576  ++Changes;
577  LOP = IDomValue;
578  }
579  }
580  } while (Changes);
581 }
void add(LiveRange::Segment)
Add a segment to LR and coalesce when possible, just like LR.addSegment().
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:193
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const unsigned reg
Definition: LiveInterval.h:656
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:406
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:53
void createDeadDefs(LiveRange &LR, unsigned Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
size_t i
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI)
setLiveOutValue - Indicate that VNI is live out from MBB.
static LaneBitmask getAll()
Definition: LaneBitmask.h:75
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
A live range for subregisters.
Definition: LiveInterval.h:632
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:159
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
SubRange * createSubRangeFrom(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, const LiveRange &CopyFrom)
Like createSubRange() but the new range is filled with a copy of the liveness information in CopyFrom...
Definition: LiveInterval.h:729
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
iterator end()
Get an iterator to the end of the SetVector.
Definition: SetVector.h:93
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:78
bool empty() const
Definition: LiveInterval.h:357
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
DomTreeNodeBase< NodeT > * getIDom() const
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
ExternalFunctions * EF
void clear()
clear - Clear all bits.
Definition: BitVector.h:188
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetRegisterInfo * getTargetRegisterInfo() const
bool isPHI() const
Definition: MachineInstr.h:786
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
iterator end()
Definition: LiveInterval.h:206
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:710
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
constexpr bool any() const
Definition: LaneBitmask.h:51
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:77
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:136
SlotIndexes pass.
Definition: SlotIndexes.h:323
void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill=SlotIndex())
addLiveInBlock - Add a block with an unknown live-in value.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Segments segments
Definition: LiveInterval.h:195
MachineBasicBlock * MBB
iterator begin()
Get an iterator to the beginning of the SetVector.
Definition: SetVector.h:83
Base class for the actual dominator tree node.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
std::vector< MachineBasicBlock * >::iterator pred_iterator
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
NodeT * getBlock() const
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:282
iterator_range< def_iterator > def_operands(unsigned Reg) const
bool isEarlyClobber() const
void reset(const MachineFunction *MF, SlotIndexes *, MachineDominatorTree *, VNInfo::Allocator *)
reset - Prepare caches for a new set of non-overlapping live ranges.
#define P(N)
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
Definition: STLExtras.h:689
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:144
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:720
constexpr bool none() const
Definition: LaneBitmask.h:50
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:138
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Use)
Attempt to extend a value defined after StartIdx to include Use.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
void setDest(LiveRange *lr)
Select a different destination live range.
Definition: LiveInterval.h:861
void resize(typename StorageT::size_type s)
Definition: IndexedMap.h:60
static const unsigned End
iterator_range< pred_iterator > predecessors()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:74
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
Definition: SlotIndexes.h:416
bool isUndefIn(ArrayRef< SlotIndex > Undefs, SlotIndex Begin, SlotIndex End) const
Returns true if there is an explicit "undef" between Begin End.
Definition: LiveInterval.h:582
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool test(unsigned Idx) const
Definition: BitVector.h:323
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
Definition: SlotIndexes.h:521
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:489
VNInfoList valnos
Definition: LiveInterval.h:196
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
constexpr bool all() const
Definition: LaneBitmask.h:52
static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc, LiveRange &LR, const MachineOperand &MO)
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
Definition: SlotIndexes.h:479
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:247
iterator begin()
Definition: LiveInterval.h:205
Helper class for performant LiveRange bulk updates.
Definition: LiveInterval.h:828
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
A vector that has set insertion semantics.
Definition: SetVector.h:41
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
IRTranslator LLVM IR MI
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:738
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
void calculateValues()
calculateValues - Calculate the value that will be live-in to each block added with addLiveInBlock...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.
Definition: SlotIndexes.h:468