27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "MSP430GenInstrInfo.inc"
31 void MSP430InstrInfo::anchor() {}
39 unsigned SrcReg,
bool isKill,
int FrameIdx,
43 if (MI != MBB.
end()) DL = MI->getDebugLoc();
52 if (RC == &MSP430::GR16RegClass)
53 BuildMI(MBB, MI, DL,
get(MSP430::MOV16mr))
56 else if (RC == &MSP430::GR8RegClass)
57 BuildMI(MBB, MI, DL,
get(MSP430::MOV8mr))
66 unsigned DestReg,
int FrameIdx,
70 if (MI != MBB.
end()) DL = MI->getDebugLoc();
79 if (RC == &MSP430::GR16RegClass)
80 BuildMI(MBB, MI, DL,
get(MSP430::MOV16rm))
83 else if (RC == &MSP430::GR8RegClass)
84 BuildMI(MBB, MI, DL,
get(MSP430::MOV8rm))
93 const DebugLoc &DL,
unsigned DestReg,
94 unsigned SrcReg,
bool KillSrc)
const {
96 if (MSP430::GR16RegClass.
contains(DestReg, SrcReg))
97 Opc = MSP430::MOV16rr;
98 else if (MSP430::GR8RegClass.
contains(DestReg, SrcReg))
103 BuildMI(MBB, I, DL,
get(Opc), DestReg)
108 int *BytesRemoved)
const {
109 assert(!BytesRemoved &&
"code size not handled");
114 while (I != MBB.
begin()) {
116 if (I->isDebugValue())
118 if (I->getOpcode() != MSP430::JMP &&
119 I->getOpcode() != MSP430::JCC &&
120 I->getOpcode() != MSP430::Br &&
121 I->getOpcode() != MSP430::Bm)
124 I->eraseFromParent();
134 assert(Cond.
size() == 1 &&
"Invalid Xbranch condition!");
180 bool AllowModify)
const {
184 while (I != MBB.
begin()) {
186 if (I->isDebugValue())
200 if (I->getOpcode() == MSP430::Br ||
201 I->getOpcode() == MSP430::Bm)
205 if (I->getOpcode() == MSP430::JMP) {
207 TBB = I->getOperand(0).getMBB();
212 while (std::next(I) != MBB.
end())
213 std::next(I)->eraseFromParent();
220 I->eraseFromParent();
226 TBB = I->getOperand(0).getMBB();
231 assert(I->getOpcode() == MSP430::JCC &&
"Invalid conditional branch");
240 TBB = I->getOperand(0).getMBB();
252 if (TBB != I->getOperand(0).getMBB())
257 if (OldBranchCode == BranchCode)
271 int *BytesAdded)
const {
273 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
275 "MSP430 branch conditions have one component!");
276 assert(!BytesAdded &&
"code size not handled");
280 assert(!FBB &&
"Unconditional branch with multiple successors!");
308 case TargetOpcode::CFI_INSTRUCTION:
310 case TargetOpcode::IMPLICIT_DEF:
312 case TargetOpcode::DBG_VALUE:
324 case MSP430::SAR8r1c:
325 case MSP430::SAR16r1c:
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const char * getSymbolName() const
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
return AArch64::GPR64RegClass contains(Reg)
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
LLVM_NODISCARD bool empty() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
unsigned getKillRegState(bool B)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool empty() const
empty - Check if the array is empty.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
unsigned getOpcode() const
Return the opcode number for this descriptor.
The memory access writes data.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
const MachineInstrBuilder & addFrameIndex(int Idx) const
MSP430InstrInfo(MSP430Subtarget &STI)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const
Measure the specified inline asm to determine an approximation of its length.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...