LLVM  4.0.0
SystemZMCTargetDesc.h
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1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
12 
13 #include "llvm/Support/DataTypes.h"
14 
15 namespace llvm {
16 
17 class MCAsmBackend;
18 class MCCodeEmitter;
19 class MCContext;
20 class MCInstrInfo;
21 class MCObjectWriter;
22 class MCRegisterInfo;
23 class MCSubtargetInfo;
24 class MCTargetOptions;
25 class StringRef;
26 class Target;
27 class Triple;
28 class raw_pwrite_stream;
29 class raw_ostream;
30 
32 
33 namespace SystemZMC {
34 // How many bytes are in the ABI-defined, caller-allocated part of
35 // a stack frame.
36 const int64_t CallFrameSize = 160;
37 
38 // The offset of the DWARF CFA from the incoming stack pointer.
40 
41 // Maps of asm register numbers to LLVM register numbers, with 0 indicating
42 // an invalid register. In principle we could use 32-bit and 64-bit register
43 // classes directly, provided that we relegated the GPR allocation order
44 // in SystemZRegisterInfo.td to an AltOrder and left the default order
45 // as %r0-%r15. It seems better to provide the same interface for
46 // all classes though.
47 extern const unsigned GR32Regs[16];
48 extern const unsigned GRH32Regs[16];
49 extern const unsigned GR64Regs[16];
50 extern const unsigned GR128Regs[16];
51 extern const unsigned FP32Regs[16];
52 extern const unsigned FP64Regs[16];
53 extern const unsigned FP128Regs[16];
54 extern const unsigned VR32Regs[32];
55 extern const unsigned VR64Regs[32];
56 extern const unsigned VR128Regs[32];
57 extern const unsigned AR32Regs[16];
58 
59 // Return the 0-based number of the first architectural register that
60 // contains the given LLVM register. E.g. R1D -> 1.
61 unsigned getFirstReg(unsigned Reg);
62 
63 // Return the given register as a GR64.
64 inline unsigned getRegAsGR64(unsigned Reg) {
65  return GR64Regs[getFirstReg(Reg)];
66 }
67 
68 // Return the given register as a low GR32.
69 inline unsigned getRegAsGR32(unsigned Reg) {
70  return GR32Regs[getFirstReg(Reg)];
71 }
72 
73 // Return the given register as a high GR32.
74 inline unsigned getRegAsGRH32(unsigned Reg) {
75  return GRH32Regs[getFirstReg(Reg)];
76 }
77 
78 // Return the given register as a VR128.
79 inline unsigned getRegAsVR128(unsigned Reg) {
80  return VR128Regs[getFirstReg(Reg)];
81 }
82 } // end namespace SystemZMC
83 
84 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
85  const MCRegisterInfo &MRI,
86  MCContext &Ctx);
87 
88 MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
89  const MCRegisterInfo &MRI,
90  const Triple &TT, StringRef CPU,
91  const MCTargetOptions &Options);
92 
93 MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
94 } // end namespace llvm
95 
96 // Defines symbolic names for SystemZ registers.
97 // This defines a mapping from register name to register number.
98 #define GET_REGINFO_ENUM
99 #include "SystemZGenRegisterInfo.inc"
100 
101 // Defines symbolic names for the SystemZ instructions.
102 #define GET_INSTRINFO_ENUM
103 #include "SystemZGenInstrInfo.inc"
104 
105 #define GET_SUBTARGETINFO_ENUM
106 #include "SystemZGenSubtargetInfo.inc"
107 
108 #endif
const unsigned GR32Regs[16]
const int64_t CallFrameSize
unsigned getFirstReg(unsigned Reg)
const unsigned FP128Regs[16]
const unsigned FP32Regs[16]
MCAsmBackend * createSystemZMCAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
const unsigned VR64Regs[32]
unsigned getRegAsGRH32(unsigned Reg)
const unsigned AR32Regs[16]
unsigned getRegAsGR32(unsigned Reg)
Reg
All possible values of the reg field in the ModR/M byte.
const unsigned GRH32Regs[16]
unsigned const MachineRegisterInfo * MRI
const int64_t CFAOffsetFromInitialSP
MCObjectWriter * createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI)
const unsigned FP64Regs[16]
static const char * Target
const unsigned GR128Regs[16]
unsigned getRegAsGR64(unsigned Reg)
unsigned getRegAsVR128(unsigned Reg)
const unsigned GR64Regs[16]
MCCodeEmitter * createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Target & getTheSystemZTarget()
const unsigned VR32Regs[32]
const unsigned VR128Regs[32]