LLVM  4.0.0
InstCombineShifts.cpp
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1 //===- InstCombineShifts.cpp ----------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the visitShl, visitLShr, and visitAShr functions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InstCombineInternal.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/IR/PatternMatch.h"
19 using namespace llvm;
20 using namespace PatternMatch;
21 
22 #define DEBUG_TYPE "instcombine"
23 
25  assert(I.getOperand(1)->getType() == I.getOperand(0)->getType());
26  Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
27 
28  // See if we can fold away this shift.
29  if (SimplifyDemandedInstructionBits(I))
30  return &I;
31 
32  // Try to fold constant and into select arguments.
33  if (isa<Constant>(Op0))
34  if (SelectInst *SI = dyn_cast<SelectInst>(Op1))
35  if (Instruction *R = FoldOpIntoSelect(I, SI))
36  return R;
37 
38  if (Constant *CUI = dyn_cast<Constant>(Op1))
39  if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
40  return Res;
41 
42  // (C1 shift (A add C2)) -> (C1 shift C2) shift A)
43  // iff A and C2 are both positive.
44  Value *A;
45  Constant *C;
46  if (match(Op0, m_Constant()) && match(Op1, m_Add(m_Value(A), m_Constant(C))))
47  if (isKnownNonNegative(A, DL) && isKnownNonNegative(C, DL))
49  I.getOpcode(), Builder->CreateBinOp(I.getOpcode(), Op0, C), A);
50 
51  // X shift (A srem B) -> X shift (A and B-1) iff B is a power of 2.
52  // Because shifts by negative values (which could occur if A were negative)
53  // are undefined.
54  const APInt *B;
55  if (Op1->hasOneUse() && match(Op1, m_SRem(m_Value(A), m_Power2(B)))) {
56  // FIXME: Should this get moved into SimplifyDemandedBits by saying we don't
57  // demand the sign bit (and many others) here??
58  Value *Rem = Builder->CreateAnd(A, ConstantInt::get(I.getType(), *B-1),
59  Op1->getName());
60  I.setOperand(1, Rem);
61  return &I;
62  }
63 
64  return nullptr;
65 }
66 
67 /// Return true if we can simplify two logical (either left or right) shifts
68 /// that have constant shift amounts.
69 static bool canEvaluateShiftedShift(unsigned FirstShiftAmt,
70  bool IsFirstShiftLeft,
71  Instruction *SecondShift, InstCombiner &IC,
72  Instruction *CxtI) {
73  assert(SecondShift->isLogicalShift() && "Unexpected instruction type");
74 
75  // We need constant shifts.
76  auto *SecondShiftConst = dyn_cast<ConstantInt>(SecondShift->getOperand(1));
77  if (!SecondShiftConst)
78  return false;
79 
80  unsigned SecondShiftAmt = SecondShiftConst->getZExtValue();
81  bool IsSecondShiftLeft = SecondShift->getOpcode() == Instruction::Shl;
82 
83  // We can always fold shl(c1) + shl(c2) -> shl(c1+c2).
84  // We can always fold lshr(c1) + lshr(c2) -> lshr(c1+c2).
85  if (IsFirstShiftLeft == IsSecondShiftLeft)
86  return true;
87 
88  // We can always fold lshr(c) + shl(c) -> and(c2).
89  // We can always fold shl(c) + lshr(c) -> and(c2).
90  if (FirstShiftAmt == SecondShiftAmt)
91  return true;
92 
93  unsigned TypeWidth = SecondShift->getType()->getScalarSizeInBits();
94 
95  // If the 2nd shift is bigger than the 1st, we can fold:
96  // lshr(c1) + shl(c2) -> shl(c3) + and(c4) or
97  // shl(c1) + lshr(c2) -> lshr(c3) + and(c4),
98  // but it isn't profitable unless we know the and'd out bits are already zero.
99  // Also check that the 2nd shift is valid (less than the type width) or we'll
100  // crash trying to produce the bit mask for the 'and'.
101  if (SecondShiftAmt > FirstShiftAmt && SecondShiftAmt < TypeWidth) {
102  unsigned MaskShift = IsSecondShiftLeft ? TypeWidth - SecondShiftAmt
103  : SecondShiftAmt - FirstShiftAmt;
104  APInt Mask = APInt::getLowBitsSet(TypeWidth, FirstShiftAmt) << MaskShift;
105  if (IC.MaskedValueIsZero(SecondShift->getOperand(0), Mask, 0, CxtI))
106  return true;
107  }
108 
109  return false;
110 }
111 
112 /// See if we can compute the specified value, but shifted
113 /// logically to the left or right by some number of bits. This should return
114 /// true if the expression can be computed for the same cost as the current
115 /// expression tree. This is used to eliminate extraneous shifting from things
116 /// like:
117 /// %C = shl i128 %A, 64
118 /// %D = shl i128 %B, 96
119 /// %E = or i128 %C, %D
120 /// %F = lshr i128 %E, 64
121 /// where the client will ask if E can be computed shifted right by 64-bits. If
122 /// this succeeds, the GetShiftedValue function will be called to produce the
123 /// value.
124 static bool CanEvaluateShifted(Value *V, unsigned NumBits, bool IsLeftShift,
125  InstCombiner &IC, Instruction *CxtI) {
126  // We can always evaluate constants shifted.
127  if (isa<Constant>(V))
128  return true;
129 
131  if (!I) return false;
132 
133  // If this is the opposite shift, we can directly reuse the input of the shift
134  // if the needed bits are already zero in the input. This allows us to reuse
135  // the value which means that we don't care if the shift has multiple uses.
136  // TODO: Handle opposite shift by exact value.
137  ConstantInt *CI = nullptr;
138  if ((IsLeftShift && match(I, m_LShr(m_Value(), m_ConstantInt(CI)))) ||
139  (!IsLeftShift && match(I, m_Shl(m_Value(), m_ConstantInt(CI))))) {
140  if (CI->getZExtValue() == NumBits) {
141  // TODO: Check that the input bits are already zero with MaskedValueIsZero
142 #if 0
143  // If this is a truncate of a logical shr, we can truncate it to a smaller
144  // lshr iff we know that the bits we would otherwise be shifting in are
145  // already zeros.
146  uint32_t OrigBitWidth = OrigTy->getScalarSizeInBits();
147  uint32_t BitWidth = Ty->getScalarSizeInBits();
148  if (MaskedValueIsZero(I->getOperand(0),
149  APInt::getHighBitsSet(OrigBitWidth, OrigBitWidth-BitWidth)) &&
150  CI->getLimitedValue(BitWidth) < BitWidth) {
151  return CanEvaluateTruncated(I->getOperand(0), Ty);
152  }
153 #endif
154 
155  }
156  }
157 
158  // We can't mutate something that has multiple uses: doing so would
159  // require duplicating the instruction in general, which isn't profitable.
160  if (!I->hasOneUse()) return false;
161 
162  switch (I->getOpcode()) {
163  default: return false;
164  case Instruction::And:
165  case Instruction::Or:
166  case Instruction::Xor:
167  // Bitwise operators can all arbitrarily be arbitrarily evaluated shifted.
168  return CanEvaluateShifted(I->getOperand(0), NumBits, IsLeftShift, IC, I) &&
169  CanEvaluateShifted(I->getOperand(1), NumBits, IsLeftShift, IC, I);
170 
171  case Instruction::Shl:
172  case Instruction::LShr:
173  return canEvaluateShiftedShift(NumBits, IsLeftShift, I, IC, CxtI);
174 
175  case Instruction::Select: {
176  SelectInst *SI = cast<SelectInst>(I);
177  Value *TrueVal = SI->getTrueValue();
178  Value *FalseVal = SI->getFalseValue();
179  return CanEvaluateShifted(TrueVal, NumBits, IsLeftShift, IC, SI) &&
180  CanEvaluateShifted(FalseVal, NumBits, IsLeftShift, IC, SI);
181  }
182  case Instruction::PHI: {
183  // We can change a phi if we can change all operands. Note that we never
184  // get into trouble with cyclic PHIs here because we only consider
185  // instructions with a single use.
186  PHINode *PN = cast<PHINode>(I);
187  for (Value *IncValue : PN->incoming_values())
188  if (!CanEvaluateShifted(IncValue, NumBits, IsLeftShift, IC, PN))
189  return false;
190  return true;
191  }
192  }
193 }
194 
195 /// When CanEvaluateShifted returned true for an expression,
196 /// this value inserts the new computation that produces the shifted value.
197 static Value *GetShiftedValue(Value *V, unsigned NumBits, bool isLeftShift,
198  InstCombiner &IC, const DataLayout &DL) {
199  // We can always evaluate constants shifted.
200  if (Constant *C = dyn_cast<Constant>(V)) {
201  if (isLeftShift)
202  V = IC.Builder->CreateShl(C, NumBits);
203  else
204  V = IC.Builder->CreateLShr(C, NumBits);
205  // If we got a constantexpr back, try to simplify it with TD info.
206  if (auto *C = dyn_cast<Constant>(V))
207  if (auto *FoldedC =
209  V = FoldedC;
210  return V;
211  }
212 
213  Instruction *I = cast<Instruction>(V);
214  IC.Worklist.Add(I);
215 
216  switch (I->getOpcode()) {
217  default: llvm_unreachable("Inconsistency with CanEvaluateShifted");
218  case Instruction::And:
219  case Instruction::Or:
220  case Instruction::Xor:
221  // Bitwise operators can all arbitrarily be arbitrarily evaluated shifted.
222  I->setOperand(
223  0, GetShiftedValue(I->getOperand(0), NumBits, isLeftShift, IC, DL));
224  I->setOperand(
225  1, GetShiftedValue(I->getOperand(1), NumBits, isLeftShift, IC, DL));
226  return I;
227 
228  case Instruction::Shl: {
229  BinaryOperator *BO = cast<BinaryOperator>(I);
230  unsigned TypeWidth = BO->getType()->getScalarSizeInBits();
231 
232  // We only accept shifts-by-a-constant in CanEvaluateShifted.
233  ConstantInt *CI = cast<ConstantInt>(BO->getOperand(1));
234 
235  // We can always fold shl(c1)+shl(c2) -> shl(c1+c2).
236  if (isLeftShift) {
237  // If this is oversized composite shift, then unsigned shifts get 0.
238  unsigned NewShAmt = NumBits+CI->getZExtValue();
239  if (NewShAmt >= TypeWidth)
240  return Constant::getNullValue(I->getType());
241 
242  BO->setOperand(1, ConstantInt::get(BO->getType(), NewShAmt));
243  BO->setHasNoUnsignedWrap(false);
244  BO->setHasNoSignedWrap(false);
245  return I;
246  }
247 
248  // We turn shl(c)+lshr(c) -> and(c2) if the input doesn't already have
249  // zeros.
250  if (CI->getValue() == NumBits) {
251  APInt Mask(APInt::getLowBitsSet(TypeWidth, TypeWidth - NumBits));
252  V = IC.Builder->CreateAnd(BO->getOperand(0),
254  if (Instruction *VI = dyn_cast<Instruction>(V)) {
255  VI->moveBefore(BO);
256  VI->takeName(BO);
257  }
258  return V;
259  }
260 
261  // We turn shl(c1)+shr(c2) -> shl(c3)+and(c4), but only when we know that
262  // the and won't be needed.
263  assert(CI->getZExtValue() > NumBits);
264  BO->setOperand(1, ConstantInt::get(BO->getType(),
265  CI->getZExtValue() - NumBits));
266  BO->setHasNoUnsignedWrap(false);
267  BO->setHasNoSignedWrap(false);
268  return BO;
269  }
270  // FIXME: This is almost identical to the SHL case. Refactor both cases into
271  // a helper function.
272  case Instruction::LShr: {
273  BinaryOperator *BO = cast<BinaryOperator>(I);
274  unsigned TypeWidth = BO->getType()->getScalarSizeInBits();
275  // We only accept shifts-by-a-constant in CanEvaluateShifted.
276  ConstantInt *CI = cast<ConstantInt>(BO->getOperand(1));
277 
278  // We can always fold lshr(c1)+lshr(c2) -> lshr(c1+c2).
279  if (!isLeftShift) {
280  // If this is oversized composite shift, then unsigned shifts get 0.
281  unsigned NewShAmt = NumBits+CI->getZExtValue();
282  if (NewShAmt >= TypeWidth)
283  return Constant::getNullValue(BO->getType());
284 
285  BO->setOperand(1, ConstantInt::get(BO->getType(), NewShAmt));
286  BO->setIsExact(false);
287  return I;
288  }
289 
290  // We turn lshr(c)+shl(c) -> and(c2) if the input doesn't already have
291  // zeros.
292  if (CI->getValue() == NumBits) {
293  APInt Mask(APInt::getHighBitsSet(TypeWidth, TypeWidth - NumBits));
294  V = IC.Builder->CreateAnd(I->getOperand(0),
296  if (Instruction *VI = dyn_cast<Instruction>(V)) {
297  VI->moveBefore(I);
298  VI->takeName(I);
299  }
300  return V;
301  }
302 
303  // We turn lshr(c1)+shl(c2) -> lshr(c3)+and(c4), but only when we know that
304  // the and won't be needed.
305  assert(CI->getZExtValue() > NumBits);
306  BO->setOperand(1, ConstantInt::get(BO->getType(),
307  CI->getZExtValue() - NumBits));
308  BO->setIsExact(false);
309  return BO;
310  }
311 
312  case Instruction::Select:
313  I->setOperand(
314  1, GetShiftedValue(I->getOperand(1), NumBits, isLeftShift, IC, DL));
315  I->setOperand(
316  2, GetShiftedValue(I->getOperand(2), NumBits, isLeftShift, IC, DL));
317  return I;
318  case Instruction::PHI: {
319  // We can change a phi if we can change all operands. Note that we never
320  // get into trouble with cyclic PHIs here because we only consider
321  // instructions with a single use.
322  PHINode *PN = cast<PHINode>(I);
323  for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i)
325  isLeftShift, IC, DL));
326  return PN;
327  }
328  }
329 }
330 
331 /// Try to fold (X << C1) << C2, where the shifts are some combination of
332 /// shl/ashr/lshr.
333 static Instruction *
335  InstCombiner::BuilderTy *Builder) {
336  Value *Op0 = I.getOperand(0);
337  uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();
338 
339  // Find out if this is a shift of a shift by a constant.
340  BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0);
341  if (ShiftOp && !ShiftOp->isShift())
342  ShiftOp = nullptr;
343 
344  if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) {
345 
346  // This is a constant shift of a constant shift. Be careful about hiding
347  // shl instructions behind bit masks. They are used to represent multiplies
348  // by a constant, and it is important that simple arithmetic expressions
349  // are still recognizable by scalar evolution.
350  //
351  // The transforms applied to shl are very similar to the transforms applied
352  // to mul by constant. We can be more aggressive about optimizing right
353  // shifts.
354  //
355  // Combinations of right and left shifts will still be optimized in
356  // DAGCombine where scalar evolution no longer applies.
357 
358  ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1));
359  uint32_t ShiftAmt1 = ShiftAmt1C->getLimitedValue(TypeBits);
360  uint32_t ShiftAmt2 = COp1->getLimitedValue(TypeBits);
361  assert(ShiftAmt2 != 0 && "Should have been simplified earlier");
362  if (ShiftAmt1 == 0)
363  return nullptr; // Will be simplified in the future.
364  Value *X = ShiftOp->getOperand(0);
365 
366  IntegerType *Ty = cast<IntegerType>(I.getType());
367 
368  // Check for (X << c1) << c2 and (X >> c1) >> c2
369  if (I.getOpcode() == ShiftOp->getOpcode()) {
370  uint32_t AmtSum = ShiftAmt1 + ShiftAmt2; // Fold into one big shift.
371  // If this is an oversized composite shift, then unsigned shifts become
372  // zero (handled in InstSimplify) and ashr saturates.
373  if (AmtSum >= TypeBits) {
374  if (I.getOpcode() != Instruction::AShr)
375  return nullptr;
376  AmtSum = TypeBits - 1; // Saturate to 31 for i32 ashr.
377  }
378 
379  return BinaryOperator::Create(I.getOpcode(), X,
380  ConstantInt::get(Ty, AmtSum));
381  }
382 
383  if (ShiftAmt1 == ShiftAmt2) {
384  // If we have ((X << C) >>u C), turn this into X & (-1 >>u C).
385  if (I.getOpcode() == Instruction::LShr &&
386  ShiftOp->getOpcode() == Instruction::Shl) {
387  APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt1));
388  return BinaryOperator::CreateAnd(
389  X, ConstantInt::get(I.getContext(), Mask));
390  }
391  } else if (ShiftAmt1 < ShiftAmt2) {
392  uint32_t ShiftDiff = ShiftAmt2 - ShiftAmt1;
393 
394  // (X >>?,exact C1) << C2 --> X << (C2-C1)
395  // The inexact version is deferred to DAGCombine so we don't hide shl
396  // behind a bit mask.
397  if (I.getOpcode() == Instruction::Shl &&
398  ShiftOp->getOpcode() != Instruction::Shl && ShiftOp->isExact()) {
399  assert(ShiftOp->getOpcode() == Instruction::LShr ||
400  ShiftOp->getOpcode() == Instruction::AShr);
401  ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
402  BinaryOperator *NewShl =
403  BinaryOperator::Create(Instruction::Shl, X, ShiftDiffCst);
405  NewShl->setHasNoSignedWrap(I.hasNoSignedWrap());
406  return NewShl;
407  }
408 
409  // (X << C1) >>u C2 --> X >>u (C2-C1) & (-1 >> C2)
410  if (I.getOpcode() == Instruction::LShr &&
411  ShiftOp->getOpcode() == Instruction::Shl) {
412  ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
413  // (X <<nuw C1) >>u C2 --> X >>u (C2-C1)
414  if (ShiftOp->hasNoUnsignedWrap()) {
415  BinaryOperator *NewLShr =
416  BinaryOperator::Create(Instruction::LShr, X, ShiftDiffCst);
417  NewLShr->setIsExact(I.isExact());
418  return NewLShr;
419  }
420  Value *Shift = Builder->CreateLShr(X, ShiftDiffCst);
421 
422  APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt2));
423  return BinaryOperator::CreateAnd(
424  Shift, ConstantInt::get(I.getContext(), Mask));
425  }
426 
427  // We can't handle (X << C1) >>s C2, it shifts arbitrary bits in. However,
428  // we can handle (X <<nsw C1) >>s C2 since it only shifts in sign bits.
429  if (I.getOpcode() == Instruction::AShr &&
430  ShiftOp->getOpcode() == Instruction::Shl) {
431  if (ShiftOp->hasNoSignedWrap()) {
432  // (X <<nsw C1) >>s C2 --> X >>s (C2-C1)
433  ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
434  BinaryOperator *NewAShr =
435  BinaryOperator::Create(Instruction::AShr, X, ShiftDiffCst);
436  NewAShr->setIsExact(I.isExact());
437  return NewAShr;
438  }
439  }
440  } else {
441  assert(ShiftAmt2 < ShiftAmt1);
442  uint32_t ShiftDiff = ShiftAmt1 - ShiftAmt2;
443 
444  // (X >>?exact C1) << C2 --> X >>?exact (C1-C2)
445  // The inexact version is deferred to DAGCombine so we don't hide shl
446  // behind a bit mask.
447  if (I.getOpcode() == Instruction::Shl &&
448  ShiftOp->getOpcode() != Instruction::Shl && ShiftOp->isExact()) {
449  ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
450  BinaryOperator *NewShr =
451  BinaryOperator::Create(ShiftOp->getOpcode(), X, ShiftDiffCst);
452  NewShr->setIsExact(true);
453  return NewShr;
454  }
455 
456  // (X << C1) >>u C2 --> X << (C1-C2) & (-1 >> C2)
457  if (I.getOpcode() == Instruction::LShr &&
458  ShiftOp->getOpcode() == Instruction::Shl) {
459  ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
460  if (ShiftOp->hasNoUnsignedWrap()) {
461  // (X <<nuw C1) >>u C2 --> X <<nuw (C1-C2)
462  BinaryOperator *NewShl =
463  BinaryOperator::Create(Instruction::Shl, X, ShiftDiffCst);
464  NewShl->setHasNoUnsignedWrap(true);
465  return NewShl;
466  }
467  Value *Shift = Builder->CreateShl(X, ShiftDiffCst);
468 
469  APInt Mask(APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt2));
470  return BinaryOperator::CreateAnd(
471  Shift, ConstantInt::get(I.getContext(), Mask));
472  }
473 
474  // We can't handle (X << C1) >>s C2, it shifts arbitrary bits in. However,
475  // we can handle (X <<nsw C1) >>s C2 since it only shifts in sign bits.
476  if (I.getOpcode() == Instruction::AShr &&
477  ShiftOp->getOpcode() == Instruction::Shl) {
478  if (ShiftOp->hasNoSignedWrap()) {
479  // (X <<nsw C1) >>s C2 --> X <<nsw (C1-C2)
480  ConstantInt *ShiftDiffCst = ConstantInt::get(Ty, ShiftDiff);
481  BinaryOperator *NewShl =
482  BinaryOperator::Create(Instruction::Shl, X, ShiftDiffCst);
483  NewShl->setHasNoSignedWrap(true);
484  return NewShl;
485  }
486  }
487  }
488  }
489 
490  return nullptr;
491 }
492 
494  BinaryOperator &I) {
495  bool isLeftShift = I.getOpcode() == Instruction::Shl;
496 
497  ConstantInt *COp1 = nullptr;
498  if (ConstantDataVector *CV = dyn_cast<ConstantDataVector>(Op1))
499  COp1 = dyn_cast_or_null<ConstantInt>(CV->getSplatValue());
500  else if (ConstantVector *CV = dyn_cast<ConstantVector>(Op1))
501  COp1 = dyn_cast_or_null<ConstantInt>(CV->getSplatValue());
502  else
503  COp1 = dyn_cast<ConstantInt>(Op1);
504 
505  if (!COp1)
506  return nullptr;
507 
508  // See if we can propagate this shift into the input, this covers the trivial
509  // cast of lshr(shl(x,c1),c2) as well as other more complex cases.
510  if (I.getOpcode() != Instruction::AShr &&
511  CanEvaluateShifted(Op0, COp1->getZExtValue(), isLeftShift, *this, &I)) {
512  DEBUG(dbgs() << "ICE: GetShiftedValue propagating shift through expression"
513  " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n");
514 
515  return replaceInstUsesWith(
516  I, GetShiftedValue(Op0, COp1->getZExtValue(), isLeftShift, *this, DL));
517  }
518 
519  // See if we can simplify any instructions used by the instruction whose sole
520  // purpose is to compute bits we don't care about.
521  uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();
522 
523  assert(!COp1->uge(TypeBits) &&
524  "Shift over the type width should have been removed already");
525 
526  // ((X*C1) << C2) == (X * (C1 << C2))
527  if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0))
528  if (BO->getOpcode() == Instruction::Mul && isLeftShift)
529  if (Constant *BOOp = dyn_cast<Constant>(BO->getOperand(1)))
530  return BinaryOperator::CreateMul(BO->getOperand(0),
531  ConstantExpr::getShl(BOOp, Op1));
532 
533  if (Instruction *FoldedShift = foldOpWithConstantIntoOperand(I))
534  return FoldedShift;
535 
536  // Fold shift2(trunc(shift1(x,c1)), c2) -> trunc(shift2(shift1(x,c1),c2))
537  if (TruncInst *TI = dyn_cast<TruncInst>(Op0)) {
538  Instruction *TrOp = dyn_cast<Instruction>(TI->getOperand(0));
539  // If 'shift2' is an ashr, we would have to get the sign bit into a funny
540  // place. Don't try to do this transformation in this case. Also, we
541  // require that the input operand is a shift-by-constant so that we have
542  // confidence that the shifts will get folded together. We could do this
543  // xform in more cases, but it is unlikely to be profitable.
544  if (TrOp && I.isLogicalShift() && TrOp->isShift() &&
545  isa<ConstantInt>(TrOp->getOperand(1))) {
546  // Okay, we'll do this xform. Make the shift of shift.
547  Constant *ShAmt = ConstantExpr::getZExt(COp1, TrOp->getType());
548  // (shift2 (shift1 & 0x00FF), c2)
549  Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
550 
551  // For logical shifts, the truncation has the effect of making the high
552  // part of the register be zeros. Emulate this by inserting an AND to
553  // clear the top bits as needed. This 'and' will usually be zapped by
554  // other xforms later if dead.
555  unsigned SrcSize = TrOp->getType()->getScalarSizeInBits();
556  unsigned DstSize = TI->getType()->getScalarSizeInBits();
557  APInt MaskV(APInt::getLowBitsSet(SrcSize, DstSize));
558 
559  // The mask we constructed says what the trunc would do if occurring
560  // between the shifts. We want to know the effect *after* the second
561  // shift. We know that it is a logical shift by a constant, so adjust the
562  // mask as appropriate.
563  if (I.getOpcode() == Instruction::Shl)
564  MaskV <<= COp1->getZExtValue();
565  else {
566  assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift");
567  MaskV = MaskV.lshr(COp1->getZExtValue());
568  }
569 
570  // shift1 & 0x00FF
571  Value *And = Builder->CreateAnd(NSh,
572  ConstantInt::get(I.getContext(), MaskV),
573  TI->getName());
574 
575  // Return the value truncated to the interesting size.
576  return new TruncInst(And, I.getType());
577  }
578  }
579 
580  if (Op0->hasOneUse()) {
581  if (BinaryOperator *Op0BO = dyn_cast<BinaryOperator>(Op0)) {
582  // Turn ((X >> C) + Y) << C -> (X + (Y << C)) & (~0 << C)
583  Value *V1, *V2;
584  ConstantInt *CC;
585  switch (Op0BO->getOpcode()) {
586  default: break;
587  case Instruction::Add:
588  case Instruction::And:
589  case Instruction::Or:
590  case Instruction::Xor: {
591  // These operators commute.
592  // Turn (Y + (X >> C)) << C -> (X + (Y << C)) & (~0 << C)
593  if (isLeftShift && Op0BO->getOperand(1)->hasOneUse() &&
594  match(Op0BO->getOperand(1), m_Shr(m_Value(V1),
595  m_Specific(Op1)))) {
596  Value *YS = // (Y << C)
597  Builder->CreateShl(Op0BO->getOperand(0), Op1, Op0BO->getName());
598  // (X + (Y << C))
599  Value *X = Builder->CreateBinOp(Op0BO->getOpcode(), YS, V1,
600  Op0BO->getOperand(1)->getName());
601  uint32_t Op1Val = COp1->getLimitedValue(TypeBits);
602 
603  APInt Bits = APInt::getHighBitsSet(TypeBits, TypeBits - Op1Val);
605  if (VectorType *VT = dyn_cast<VectorType>(X->getType()))
606  Mask = ConstantVector::getSplat(VT->getNumElements(), Mask);
607  return BinaryOperator::CreateAnd(X, Mask);
608  }
609 
610  // Turn (Y + ((X >> C) & CC)) << C -> ((X & (CC << C)) + (Y << C))
611  Value *Op0BOOp1 = Op0BO->getOperand(1);
612  if (isLeftShift && Op0BOOp1->hasOneUse() &&
613  match(Op0BOOp1,
614  m_And(m_OneUse(m_Shr(m_Value(V1), m_Specific(Op1))),
615  m_ConstantInt(CC)))) {
616  Value *YS = // (Y << C)
617  Builder->CreateShl(Op0BO->getOperand(0), Op1,
618  Op0BO->getName());
619  // X & (CC << C)
620  Value *XM = Builder->CreateAnd(V1, ConstantExpr::getShl(CC, Op1),
621  V1->getName()+".mask");
622  return BinaryOperator::Create(Op0BO->getOpcode(), YS, XM);
623  }
625  }
626 
627  case Instruction::Sub: {
628  // Turn ((X >> C) + Y) << C -> (X + (Y << C)) & (~0 << C)
629  if (isLeftShift && Op0BO->getOperand(0)->hasOneUse() &&
630  match(Op0BO->getOperand(0), m_Shr(m_Value(V1),
631  m_Specific(Op1)))) {
632  Value *YS = // (Y << C)
633  Builder->CreateShl(Op0BO->getOperand(1), Op1, Op0BO->getName());
634  // (X + (Y << C))
635  Value *X = Builder->CreateBinOp(Op0BO->getOpcode(), V1, YS,
636  Op0BO->getOperand(0)->getName());
637  uint32_t Op1Val = COp1->getLimitedValue(TypeBits);
638 
639  APInt Bits = APInt::getHighBitsSet(TypeBits, TypeBits - Op1Val);
641  if (VectorType *VT = dyn_cast<VectorType>(X->getType()))
642  Mask = ConstantVector::getSplat(VT->getNumElements(), Mask);
643  return BinaryOperator::CreateAnd(X, Mask);
644  }
645 
646  // Turn (((X >> C)&CC) + Y) << C -> (X + (Y << C)) & (CC << C)
647  if (isLeftShift && Op0BO->getOperand(0)->hasOneUse() &&
648  match(Op0BO->getOperand(0),
649  m_And(m_OneUse(m_Shr(m_Value(V1), m_Value(V2))),
650  m_ConstantInt(CC))) && V2 == Op1) {
651  Value *YS = // (Y << C)
652  Builder->CreateShl(Op0BO->getOperand(1), Op1, Op0BO->getName());
653  // X & (CC << C)
654  Value *XM = Builder->CreateAnd(V1, ConstantExpr::getShl(CC, Op1),
655  V1->getName()+".mask");
656 
657  return BinaryOperator::Create(Op0BO->getOpcode(), XM, YS);
658  }
659 
660  break;
661  }
662  }
663 
664 
665  // If the operand is a bitwise operator with a constant RHS, and the
666  // shift is the only use, we can pull it out of the shift.
667  if (ConstantInt *Op0C = dyn_cast<ConstantInt>(Op0BO->getOperand(1))) {
668  bool isValid = true; // Valid only for And, Or, Xor
669  bool highBitSet = false; // Transform if high bit of constant set?
670 
671  switch (Op0BO->getOpcode()) {
672  default: isValid = false; break; // Do not perform transform!
673  case Instruction::Add:
674  isValid = isLeftShift;
675  break;
676  case Instruction::Or:
677  case Instruction::Xor:
678  highBitSet = false;
679  break;
680  case Instruction::And:
681  highBitSet = true;
682  break;
683  }
684 
685  // If this is a signed shift right, and the high bit is modified
686  // by the logical operation, do not perform the transformation.
687  // The highBitSet boolean indicates the value of the high bit of
688  // the constant which would cause it to be modified for this
689  // operation.
690  //
691  if (isValid && I.getOpcode() == Instruction::AShr)
692  isValid = Op0C->getValue()[TypeBits-1] == highBitSet;
693 
694  if (isValid) {
695  Constant *NewRHS = ConstantExpr::get(I.getOpcode(), Op0C, Op1);
696 
697  Value *NewShift =
698  Builder->CreateBinOp(I.getOpcode(), Op0BO->getOperand(0), Op1);
699  NewShift->takeName(Op0BO);
700 
701  return BinaryOperator::Create(Op0BO->getOpcode(), NewShift,
702  NewRHS);
703  }
704  }
705  }
706  }
707 
708  if (Instruction *Folded = foldShiftByConstOfShiftByConst(I, COp1, Builder))
709  return Folded;
710 
711  return nullptr;
712 }
713 
715  if (Value *V = SimplifyVectorOp(I))
716  return replaceInstUsesWith(I, V);
717 
718  if (Value *V =
720  I.hasNoUnsignedWrap(), DL, &TLI, &DT, &AC))
721  return replaceInstUsesWith(I, V);
722 
723  if (Instruction *V = commonShiftTransforms(I))
724  return V;
725 
726  if (ConstantInt *Op1C = dyn_cast<ConstantInt>(I.getOperand(1))) {
727  unsigned ShAmt = Op1C->getZExtValue();
728 
729  // Turn:
730  // %zext = zext i32 %V to i64
731  // %res = shl i64 %V, 8
732  //
733  // Into:
734  // %shl = shl i32 %V, 8
735  // %res = zext i32 %shl to i64
736  //
737  // This is only valid if %V would have zeros shifted out.
738  if (auto *ZI = dyn_cast<ZExtInst>(I.getOperand(0))) {
739  unsigned SrcBitWidth = ZI->getSrcTy()->getScalarSizeInBits();
740  if (ShAmt < SrcBitWidth &&
741  MaskedValueIsZero(ZI->getOperand(0),
742  APInt::getHighBitsSet(SrcBitWidth, ShAmt), 0, &I)) {
743  auto *Shl = Builder->CreateShl(ZI->getOperand(0), ShAmt);
744  return new ZExtInst(Shl, I.getType());
745  }
746  }
747 
748  // If the shifted-out value is known-zero, then this is a NUW shift.
749  if (!I.hasNoUnsignedWrap() &&
751  APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt), 0,
752  &I)) {
754  return &I;
755  }
756 
757  // If the shifted out value is all signbits, this is a NSW shift.
758  if (!I.hasNoSignedWrap() &&
759  ComputeNumSignBits(I.getOperand(0), 0, &I) > ShAmt) {
760  I.setHasNoSignedWrap();
761  return &I;
762  }
763  }
764 
765  // (C1 << A) << C2 -> (C1 << C2) << A
766  Constant *C1, *C2;
767  Value *A;
768  if (match(I.getOperand(0), m_OneUse(m_Shl(m_Constant(C1), m_Value(A)))) &&
769  match(I.getOperand(1), m_Constant(C2)))
770  return BinaryOperator::CreateShl(ConstantExpr::getShl(C1, C2), A);
771 
772  return nullptr;
773 }
774 
776  if (Value *V = SimplifyVectorOp(I))
777  return replaceInstUsesWith(I, V);
778 
779  if (Value *V = SimplifyLShrInst(I.getOperand(0), I.getOperand(1), I.isExact(),
780  DL, &TLI, &DT, &AC))
781  return replaceInstUsesWith(I, V);
782 
783  if (Instruction *R = commonShiftTransforms(I))
784  return R;
785 
786  Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
787 
788  if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
789  unsigned ShAmt = Op1C->getZExtValue();
790 
791  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Op0)) {
792  unsigned BitWidth = Op0->getType()->getScalarSizeInBits();
793  // ctlz.i32(x)>>5 --> zext(x == 0)
794  // cttz.i32(x)>>5 --> zext(x == 0)
795  // ctpop.i32(x)>>5 --> zext(x == -1)
796  if ((II->getIntrinsicID() == Intrinsic::ctlz ||
797  II->getIntrinsicID() == Intrinsic::cttz ||
798  II->getIntrinsicID() == Intrinsic::ctpop) &&
799  isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
800  bool isCtPop = II->getIntrinsicID() == Intrinsic::ctpop;
801  Constant *RHS = ConstantInt::getSigned(Op0->getType(), isCtPop ? -1:0);
802  Value *Cmp = Builder->CreateICmpEQ(II->getArgOperand(0), RHS);
803  return new ZExtInst(Cmp, II->getType());
804  }
805  }
806 
807  // If the shifted-out value is known-zero, then this is an exact shift.
808  if (!I.isExact() &&
809  MaskedValueIsZero(Op0, APInt::getLowBitsSet(Op1C->getBitWidth(), ShAmt),
810  0, &I)){
811  I.setIsExact();
812  return &I;
813  }
814  }
815 
816  return nullptr;
817 }
818 
820  if (Value *V = SimplifyVectorOp(I))
821  return replaceInstUsesWith(I, V);
822 
823  if (Value *V = SimplifyAShrInst(I.getOperand(0), I.getOperand(1), I.isExact(),
824  DL, &TLI, &DT, &AC))
825  return replaceInstUsesWith(I, V);
826 
827  if (Instruction *R = commonShiftTransforms(I))
828  return R;
829 
830  Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
831 
832  if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
833  unsigned ShAmt = Op1C->getZExtValue();
834 
835  // If the input is a SHL by the same constant (ashr (shl X, C), C), then we
836  // have a sign-extend idiom.
837  Value *X;
838  if (match(Op0, m_Shl(m_Value(X), m_Specific(Op1)))) {
839  // If the input is an extension from the shifted amount value, e.g.
840  // %x = zext i8 %A to i32
841  // %y = shl i32 %x, 24
842  // %z = ashr %y, 24
843  // then turn this into "z = sext i8 A to i32".
844  if (ZExtInst *ZI = dyn_cast<ZExtInst>(X)) {
845  uint32_t SrcBits = ZI->getOperand(0)->getType()->getScalarSizeInBits();
846  uint32_t DestBits = ZI->getType()->getScalarSizeInBits();
847  if (Op1C->getZExtValue() == DestBits-SrcBits)
848  return new SExtInst(ZI->getOperand(0), ZI->getType());
849  }
850  }
851 
852  // If the shifted-out value is known-zero, then this is an exact shift.
853  if (!I.isExact() &&
854  MaskedValueIsZero(Op0, APInt::getLowBitsSet(Op1C->getBitWidth(), ShAmt),
855  0, &I)) {
856  I.setIsExact();
857  return &I;
858  }
859  }
860 
861  // See if we can turn a signed shr into an unsigned shr.
862  if (MaskedValueIsZero(Op0,
864  0, &I))
865  return BinaryOperator::CreateLShr(Op0, Op1);
866 
867  return nullptr;
868 }
static bool canEvaluateShiftedShift(unsigned FirstShiftAmt, bool IsFirstShiftLeft, Instruction *SecondShift, InstCombiner &IC, Instruction *CxtI)
Return true if we can simplify two logical (either left or right) shifts that have constant shift amo...
A vector constant whose element type is a simple 1/2/4/8-byte integer or float/double, and whose elements are just simple data values (i.e.
Definition: Constants.h:739
BinaryOp_match< LHS, RHS, Instruction::And > m_And(const LHS &L, const RHS &R)
Definition: PatternMatch.h:506
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:64
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:451
size_t i
BinaryOp_match< LHS, RHS, Instruction::SRem > m_SRem(const LHS &L, const RHS &R)
Definition: PatternMatch.h:494
This class represents zero extension of integer types.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:536
class_match< Constant > m_Constant()
Match an arbitrary Constant and ignore it.
Definition: PatternMatch.h:83
static Instruction * foldShiftByConstOfShiftByConst(BinaryOperator &I, ConstantInt *COp1, InstCombiner::BuilderTy *Builder)
Try to fold (X << C1) << C2, where the shifts are some combination of shl/ashr/lshr.
void Add(Instruction *I)
Add - Add the specified instruction to the worklist if it isn't already in it.
This class represents a sign extension of integer types.
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition: Constants.cpp:195
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:191
bool uge(uint64_t Num) const
This function will return true iff this constant represents a value with active bits bigger than 64 b...
Definition: Constants.h:247
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:41
This class represents the LLVM 'select' instruction.
Instruction * commonShiftTransforms(BinaryOperator &I)
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:143
BinOp2_match< LHS, RHS, Instruction::LShr, Instruction::AShr > m_Shr(const LHS &L, const RHS &R)
Matches LShr or AShr.
Definition: PatternMatch.h:658
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1122
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:588
The core instruction combiner logic.
BinaryOp_match< LHS, RHS, Instruction::Add > m_Add(const LHS &L, const RHS &R)
Definition: PatternMatch.h:434
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:154
Constant * ConstantFoldConstant(const Constant *C, const DataLayout &DL, const TargetLibraryInfo *TLI=nullptr)
ConstantFoldConstant - Attempt to fold the constant using the specified DataLayout.
static Constant * get(unsigned Opcode, Constant *C1, Constant *C2, unsigned Flags=0, Type *OnlyIfReducedTy=nullptr)
get - Return a binary or shift operator constant expression, folding if possible. ...
Definition: Constants.cpp:1728
static Constant * getZExt(Constant *C, Type *Ty, bool OnlyIfReduced=false)
Definition: Constants.cpp:1587
void setIsExact(bool b=true)
Set or clear the exact flag on this instruction, which must be an operator which supports this flag...
uint64_t getLimitedValue(uint64_t Limit=~0ULL) const
getLimitedValue - If the value is smaller than the specified limit, return it, otherwise return the l...
Definition: Constants.h:256
TargetLibraryInfo & getTargetLibraryInfo() const
bool isLogicalShift() const
Return true if this is a logical shift left or a logical shift right.
Definition: Instruction.h:136
class_match< ConstantInt > m_ConstantInt()
Match an arbitrary ConstantInt and ignore it.
Definition: PatternMatch.h:75
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
cst_pred_ty< is_power2 > m_Power2()
Match an integer or vector power of 2.
Definition: PatternMatch.h:272
void takeName(Value *V)
Transfer the name from V to this value.
Definition: Value.cpp:263
This class represents a truncation of integer types.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:518
OneUse_match< T > m_OneUse(const T &SubPattern)
Definition: PatternMatch.h:55
BinaryOp_match< LHS, RHS, Instruction::LShr > m_LShr(const LHS &L, const RHS &R)
Definition: PatternMatch.h:530
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:399
bool isExact() const
Determine whether the exact flag is set.
bool isKnownNonNegative(const Value *V, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr)
Returns true if the give value is known to be non-negative.
This is an important base class in LLVM.
Definition: Constant.h:42
bool MaskedValueIsZero(const Value *V, const APInt &Mask, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr)
Return true if 'V & Mask' is known to be zero.
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1947
bool hasNoSignedWrap() const
Determine whether the no signed wrap flag is set.
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1952
Value * SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, const DataLayout &DL, const TargetLibraryInfo *TLI=nullptr, const DominatorTree *DT=nullptr, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr)
Given operands for a Shl, fold the result or return null.
specificval_ty m_Specific(const Value *V)
Match if we have a specific specified value.
Definition: PatternMatch.h:322
BinaryOp_match< LHS, RHS, Instruction::Shl > m_Shl(const LHS &L, const RHS &R)
Definition: PatternMatch.h:524
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Value * getOperand(unsigned i) const
Definition: User.h:145
Class to represent integer types.
Definition: DerivedTypes.h:39
Constant Vector Declarations.
Definition: Constants.h:490
Instruction * visitLShr(BinaryOperator &I)
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:654
const Value * getTrueValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
InstCombineWorklist & Worklist
A worklist of the instructions that need to be simplified.
BinaryOps getOpcode() const
Definition: InstrTypes.h:541
static Constant * getSplat(unsigned NumElts, Constant *Elt)
Return a ConstantVector with the specified constant in each element.
Definition: Constants.cpp:1034
void setHasNoSignedWrap(bool b=true)
Set or clear the nsw flag on this instruction, which must be an operator which supports this flag...
This is the shared class of boolean and integer constants.
Definition: Constants.h:88
unsigned ComputeNumSignBits(const Value *Op, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr)
Return the number of times the sign bit of the register is replicated into the other bits...
bool hasNoUnsignedWrap() const
Determine whether the no unsigned wrap flag is set.
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type...
Definition: Type.cpp:123
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:230
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:558
static ConstantInt * getSigned(IntegerType *Ty, int64_t V)
Return a ConstantInt with the specified value for the specified type.
Definition: Constants.cpp:572
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
void setOperand(unsigned i, Value *Val)
Definition: User.h:150
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:513
Class to represent vector types.
Definition: DerivedTypes.h:369
Class for arbitrary precision integers.
Definition: APInt.h:77
static BinaryOperator * Create(BinaryOps Op, Value *S1, Value *S2, const Twine &Name=Twine(), Instruction *InsertBefore=nullptr)
Construct a binary instruction, given the opcode and the two operands.
Value * CreateShl(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
Definition: IRBuilder.h:932
static bool CanEvaluateShifted(Value *V, unsigned NumBits, bool IsLeftShift, InstCombiner &IC, Instruction *CxtI)
See if we can compute the specified value, but shifted logically to the left or right by some number ...
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1942
static Value * GetShiftedValue(Value *V, unsigned NumBits, bool isLeftShift, InstCombiner &IC, const DataLayout &DL)
When CanEvaluateShifted returned true for an expression, this value inserts the new computation that ...
#define I(x, y, z)
Definition: MD5.cpp:54
bool hasOneUse() const
Return true if there is exactly one user of this value.
Definition: Value.h:383
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
static Constant * getShl(Constant *C1, Constant *C2, bool HasNUW=false, bool HasNSW=false)
Definition: Constants.cpp:2203
bool MaskedValueIsZero(Value *V, const APInt &Mask, unsigned Depth=0, Instruction *CxtI=nullptr) const
Value * SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout &DL, const TargetLibraryInfo *TLI=nullptr, const DominatorTree *DT=nullptr, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr)
Given operands for a LShr, fold the result or return null.
void setHasNoUnsignedWrap(bool b=true)
Set or clear the nsw flag on this instruction, which must be an operator which supports this flag...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
Value * SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact, const DataLayout &DL, const TargetLibraryInfo *TLI=nullptr, const DominatorTree *DT=nullptr, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr)
Given operands for a AShr, fold the result or return nulll.
This file provides internal interfaces used to implement the InstCombine.
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:111
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
Value * CreateLShr(Value *LHS, Value *RHS, const Twine &Name="", bool isExact=false)
Definition: IRBuilder.h:951
#define DEBUG(X)
Definition: Debug.h:100
const Value * getFalseValue() const
Instruction * visitAShr(BinaryOperator &I)
void setIncomingValue(unsigned i, Value *V)
Instruction * visitShl(BinaryOperator &I)
static BinaryOperator * CreateMul(Value *S1, Value *S2, const Twine &Name, Instruction *InsertBefore, Value *FlagsOp)
op_range incoming_values()
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
Instruction * FoldShiftByConstant(Value *Op0, Constant *Op1, BinaryOperator &I)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44