28 #define DEBUG_TYPE "mccodeemitter"
31 using namespace Hexagon;
33 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
37 : MCT(aMCT), MCII(aMII), Addend(new
unsigned(0)),
44 if (Instruction == 0) {
47 assert(Instruction != Last);
51 if (Instruction == 1) {
54 assert(Instruction != Last);
59 assert(Instruction == Last);
62 if(Instruction == Last)
81 verifyInstructionPredicates(HMI,
96 if (Consumer == Producer)
98 if (Consumer == Producer2)
101 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
102 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
103 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
117 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10,
118 Hexagon::R11, Hexagon::R12, Hexagon::R13,
119 Hexagon::R14, Hexagon::R15};
124 "pseudo-instruction found");
134 if ((Reg <= 23) && (Reg >= 16))
143 unsigned SOffset = 0;
144 unsigned VOffset = 0;
149 auto i = Instructions.begin() + Index - 1;
151 assert(
i != Instructions.begin() - 1 &&
"Couldn't find producer");
152 MCInst const &Inst = *
i->getInst();
162 :
static_cast<unsigned>(Hexagon::NoRegister);
166 :
static_cast<unsigned>(Hexagon::NoRegister);
174 "Unpredicated consumer depending on predicated producer");
186 MCO.
setReg(Offset + Hexagon::R0);
204 if (HMB.
getOpcode() >= Hexagon::DuplexIClass0 &&
205 HMB.
getOpcode() <= Hexagon::DuplexIClassF) {
207 "Emitting duplex without duplex parse bits");
210 case Hexagon::DuplexIClass0:
213 case Hexagon::DuplexIClass1:
216 case Hexagon::DuplexIClass2:
219 case Hexagon::DuplexIClass3:
222 case Hexagon::DuplexIClass4:
225 case Hexagon::DuplexIClass5:
228 case Hexagon::DuplexIClass6:
231 case Hexagon::DuplexIClass7:
234 case Hexagon::DuplexIClass8:
237 case Hexagon::DuplexIClass9:
240 case Hexagon::DuplexIClassA:
243 case Hexagon::DuplexIClassB:
246 case Hexagon::DuplexIClassC:
249 case Hexagon::DuplexIClassD:
252 case Hexagon::DuplexIClassE:
255 case Hexagon::DuplexIClassF:
265 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
275 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
282 void raise_relocation_error(
unsigned bits,
unsigned kind) {
286 Stream <<
"Unrecognized relocation combination bits: " << bits
287 <<
" kind: " << kind;
328 raise_relocation_error(0, kind);
335 case Hexagon::A2_tfrih:
356 raise_relocation_error(0, kind);
360 case Hexagon::A2_tfril:
381 raise_relocation_error(0, kind);
389 if (*ImpUses != Hexagon::GP)
401 raise_relocation_error(0, kind);
405 raise_relocation_error(0, kind);
416 bool isPCRel (
unsigned Kind) {
441 unsigned HexagonMCCodeEmitter::getExprOpValue(
const MCInst &MI,
448 if (isa<HexagonMCExpr>(ME))
451 if (ME->evaluateAsAbsolute(Value))
468 DEBUG(
dbgs() <<
"----------------------------------------\n");
472 DEBUG(
dbgs() <<
"Relocation bits: " << bits <<
"\n");
473 DEBUG(
dbgs() <<
"Addend: " << *Addend <<
"\n");
474 DEBUG(
dbgs() <<
"----------------------------------------\n");
478 raise_relocation_error(bits, kind);
521 raise_relocation_error(bits, kind);
541 raise_relocation_error(bits, kind);
576 raise_relocation_error(bits, kind);
584 raise_relocation_error(bits, kind);
618 raise_relocation_error(bits, kind);
629 raise_relocation_error(bits, kind);
639 raise_relocation_error(bits, kind);
657 raise_relocation_error(bits, kind);
660 raise_relocation_error(bits, kind);
691 raise_relocation_error(bits, kind);
699 raise_relocation_error(bits, kind);
711 raise_relocation_error(bits, kind);
714 raise_relocation_error(bits, kind);
725 raise_relocation_error(bits, kind);
732 raise_relocation_error(bits, kind);
743 raise_relocation_error(bits, kind);
770 raise_relocation_error(bits, kind);
773 raise_relocation_error(bits, kind);
777 FixupKind = getFixupNoBits(MCII, MI, MO, kind);
781 MCExpr const *FixupExpression =
782 (*Addend > 0 && isPCRel(FixupKind))
804 case Hexagon::A2_tfrrcr:
805 case Hexagon::A2_tfrcrr:
806 if(Reg == Hexagon::M0)
808 if(Reg == Hexagon::M1)
823 #define ENABLE_INSTR_PREDICATE_VERIFIER
824 #include "HexagonGenMCCodeEmitter.inc"
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
void push_back(const T &Elt)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
STATISTIC(NumFunctions,"Total number of functions")
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool mayStore() const
Return true if this instruction could possibly modify memory.
Describe properties that are true of each instruction in the target description file.
bool isBundle(MCInst const &MCI)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
bool isSubInstruction(MCInst const &MCI)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
uint32_t parseBits(size_t Instruction, size_t Last, MCInst const &MCB, MCInst const &MCI) const
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
bool isImmext(MCInst const &MCI)
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const
EncodeSingleInstruction - Emit a single.
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
const MCInstrDesc HexagonInsts[]
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Function Alias Analysis false
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
bool s23_2_reloc(MCExpr const &Expr)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
const MCExpr * getExpr() const
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Lanai::Fixups FixupKind(const MCExpr *Expr)
MCExpr const & getExpr(MCExpr const &Expr)
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
Definition for classes that emit Hexagon machine code from MCInsts.
Binary assembler expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getOpcode() const
Return the opcode number for this descriptor.
void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts a value to fix up the immediate of an LDI Rd, K instruction.
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Promote Memory to Register
bool mayLoad() const
Return true if this instruction could possibly read memory.
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT)
const MCRegisterInfo * getRegisterInfo() const
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
unsigned getNumOperands() const
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInst * getInst() const
References to labels and assigned expressions.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
size_t bundleSize(MCInst const &MCI)
void setReg(unsigned Reg)
Set the register number.
VariantKind getKind() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
A raw_ostream that writes to an std::string.
#define HEXAGON_INSTR_SIZE
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2)
This class implements an extremely fast bulk output stream that can only output to a stream...
unsigned getDuplexRegisterNumbering(unsigned Reg)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
const MCOperand & getOperand(unsigned i) const
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)