LLVM  4.0.0
BPFISelLowering.cpp
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1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that BPF uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "BPFISelLowering.h"
16 #include "BPF.h"
17 #include "BPFSubtarget.h"
18 #include "BPFTargetMachine.h"
27 #include "llvm/IR/DiagnosticInfo.h"
29 #include "llvm/Support/Debug.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "bpf-lower"
35 
36 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg) {
38  DAG.getContext()->diagnose(
40 }
41 
42 static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg,
43  SDValue Val) {
45  std::string Str;
46  raw_string_ostream OS(Str);
47  OS << Msg;
48  Val->print(OS);
49  OS.flush();
50  DAG.getContext()->diagnose(
52 }
53 
55  const BPFSubtarget &STI)
56  : TargetLowering(TM) {
57 
58  // Set up the register classes.
59  addRegisterClass(MVT::i64, &BPF::GPRRegClass);
60 
61  // Compute derived properties from the register classes
63 
65 
73 
75 
79 
84 
89 
94 
100 
106 
111 
112  // Extended load operations for i1 types must be promoted
113  for (MVT VT : MVT::integer_valuetypes()) {
117 
121  }
122 
124 
125  // Function alignments (log2)
128 
129  // inline memcpy() for kernel to see explicit copy
133 }
134 
136  switch (Op.getOpcode()) {
137  case ISD::BR_CC:
138  return LowerBR_CC(Op, DAG);
139  case ISD::GlobalAddress:
140  return LowerGlobalAddress(Op, DAG);
141  case ISD::SELECT_CC:
142  return LowerSELECT_CC(Op, DAG);
143  default:
144  llvm_unreachable("unimplemented operand");
145  }
146 }
147 
148 // Calling Convention Implementation
149 #include "BPFGenCallingConv.inc"
150 
151 SDValue BPFTargetLowering::LowerFormalArguments(
152  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
153  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
154  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
155  switch (CallConv) {
156  default:
157  llvm_unreachable("Unsupported calling convention");
158  case CallingConv::C:
159  case CallingConv::Fast:
160  break;
161  }
162 
164  MachineRegisterInfo &RegInfo = MF.getRegInfo();
165 
166  // Assign locations to all of the incoming arguments.
168  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
169  CCInfo.AnalyzeFormalArguments(Ins, CC_BPF64);
170 
171  for (auto &VA : ArgLocs) {
172  if (VA.isRegLoc()) {
173  // Arguments passed in registers
174  EVT RegVT = VA.getLocVT();
175  switch (RegVT.getSimpleVT().SimpleTy) {
176  default: {
177  errs() << "LowerFormalArguments Unhandled argument type: "
178  << RegVT.getEVTString() << '\n';
179  llvm_unreachable(0);
180  }
181  case MVT::i64:
182  unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
183  RegInfo.addLiveIn(VA.getLocReg(), VReg);
184  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
185 
186  // If this is an 8/16/32-bit value, it is really passed promoted to 64
187  // bits. Insert an assert[sz]ext to capture this, then truncate to the
188  // right size.
189  if (VA.getLocInfo() == CCValAssign::SExt)
190  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
191  DAG.getValueType(VA.getValVT()));
192  else if (VA.getLocInfo() == CCValAssign::ZExt)
193  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
194  DAG.getValueType(VA.getValVT()));
195 
196  if (VA.getLocInfo() != CCValAssign::Full)
197  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
198 
199  InVals.push_back(ArgValue);
200  }
201  } else {
202  fail(DL, DAG, "defined with too many args");
203  InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT()));
204  }
205  }
206 
207  if (IsVarArg || MF.getFunction()->hasStructRetAttr()) {
208  fail(DL, DAG, "functions with VarArgs or StructRet are not supported");
209  }
210 
211  return Chain;
212 }
213 
214 const unsigned BPFTargetLowering::MaxArgs = 5;
215 
216 SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
217  SmallVectorImpl<SDValue> &InVals) const {
218  SelectionDAG &DAG = CLI.DAG;
219  auto &Outs = CLI.Outs;
220  auto &OutVals = CLI.OutVals;
221  auto &Ins = CLI.Ins;
222  SDValue Chain = CLI.Chain;
223  SDValue Callee = CLI.Callee;
224  bool &IsTailCall = CLI.IsTailCall;
225  CallingConv::ID CallConv = CLI.CallConv;
226  bool IsVarArg = CLI.IsVarArg;
228 
229  // BPF target does not support tail call optimization.
230  IsTailCall = false;
231 
232  switch (CallConv) {
233  default:
234  report_fatal_error("Unsupported calling convention");
235  case CallingConv::Fast:
236  case CallingConv::C:
237  break;
238  }
239 
240  // Analyze operands of the call, assigning locations to each operand.
242  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
243 
244  CCInfo.AnalyzeCallOperands(Outs, CC_BPF64);
245 
246  unsigned NumBytes = CCInfo.getNextStackOffset();
247 
248  if (Outs.size() > MaxArgs)
249  fail(CLI.DL, DAG, "too many args to ", Callee);
250 
251  for (auto &Arg : Outs) {
252  ISD::ArgFlagsTy Flags = Arg.Flags;
253  if (!Flags.isByVal())
254  continue;
255 
256  fail(CLI.DL, DAG, "pass by value not supported ", Callee);
257  }
258 
259  auto PtrVT = getPointerTy(MF.getDataLayout());
260  Chain = DAG.getCALLSEQ_START(
261  Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL);
262 
263  SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass;
264 
265  // Walk arg assignments
266  for (unsigned i = 0,
267  e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs);
268  i != e; ++i) {
269  CCValAssign &VA = ArgLocs[i];
270  SDValue Arg = OutVals[i];
271 
272  // Promote the value if needed.
273  switch (VA.getLocInfo()) {
274  default:
275  llvm_unreachable("Unknown loc info");
276  case CCValAssign::Full:
277  break;
278  case CCValAssign::SExt:
279  Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
280  break;
281  case CCValAssign::ZExt:
282  Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
283  break;
284  case CCValAssign::AExt:
285  Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
286  break;
287  }
288 
289  // Push arguments into RegsToPass vector
290  if (VA.isRegLoc())
291  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
292  else
293  llvm_unreachable("call arg pass bug");
294  }
295 
296  SDValue InFlag;
297 
298  // Build a sequence of copy-to-reg nodes chained together with token chain and
299  // flag operands which copy the outgoing args into registers. The InFlag in
300  // necessary since all emitted instructions must be stuck together.
301  for (auto &Reg : RegsToPass) {
302  Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
303  InFlag = Chain.getValue(1);
304  }
305 
306  // If the callee is a GlobalAddress node (quite common, every direct call is)
307  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
308  // Likewise ExternalSymbol -> TargetExternalSymbol.
309  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
310  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT,
311  G->getOffset(), 0);
312  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
313  Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
314 
315  // Returns a chain & a flag for retval copy to use.
316  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
318  Ops.push_back(Chain);
319  Ops.push_back(Callee);
320 
321  // Add argument registers to the end of the list so that they are
322  // known live into the call.
323  for (auto &Reg : RegsToPass)
324  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
325 
326  if (InFlag.getNode())
327  Ops.push_back(InFlag);
328 
329  Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
330  InFlag = Chain.getValue(1);
331 
332  // Create the CALLSEQ_END node.
333  Chain = DAG.getCALLSEQ_END(
334  Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true),
335  DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL);
336  InFlag = Chain.getValue(1);
337 
338  // Handle result values, copying them out of physregs into vregs that we
339  // return.
340  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
341  InVals);
342 }
343 
344 SDValue
345 BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
346  bool IsVarArg,
348  const SmallVectorImpl<SDValue> &OutVals,
349  const SDLoc &DL, SelectionDAG &DAG) const {
350  unsigned Opc = BPFISD::RET_FLAG;
351 
352  // CCValAssign - represent the assignment of the return value to a location
355 
356  // CCState - Info about the registers and stack slot.
357  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
358 
359  if (MF.getFunction()->getReturnType()->isAggregateType()) {
360  fail(DL, DAG, "only integer returns supported");
361  return DAG.getNode(Opc, DL, MVT::Other, Chain);
362  }
363 
364  // Analize return values.
365  CCInfo.AnalyzeReturn(Outs, RetCC_BPF64);
366 
367  SDValue Flag;
368  SmallVector<SDValue, 4> RetOps(1, Chain);
369 
370  // Copy the result values into the output registers.
371  for (unsigned i = 0; i != RVLocs.size(); ++i) {
372  CCValAssign &VA = RVLocs[i];
373  assert(VA.isRegLoc() && "Can only return in registers!");
374 
375  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
376 
377  // Guarantee that all emitted copies are stuck together,
378  // avoiding something bad.
379  Flag = Chain.getValue(1);
380  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
381  }
382 
383  RetOps[0] = Chain; // Update chain.
384 
385  // Add the flag if we have it.
386  if (Flag.getNode())
387  RetOps.push_back(Flag);
388 
389  return DAG.getNode(Opc, DL, MVT::Other, RetOps);
390 }
391 
392 SDValue BPFTargetLowering::LowerCallResult(
393  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
394  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
395  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
396 
398  // Assign locations to each value returned by this call.
400  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
401 
402  if (Ins.size() >= 2) {
403  fail(DL, DAG, "only small returns supported");
404  for (unsigned i = 0, e = Ins.size(); i != e; ++i)
405  InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT));
406  return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1);
407  }
408 
409  CCInfo.AnalyzeCallResult(Ins, RetCC_BPF64);
410 
411  // Copy all of the result registers out of their specified physreg.
412  for (auto &Val : RVLocs) {
413  Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
414  Val.getValVT(), InFlag).getValue(1);
415  InFlag = Chain.getValue(2);
416  InVals.push_back(Chain.getValue(0));
417  }
418 
419  return Chain;
420 }
421 
422 static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
423  switch (CC) {
424  default:
425  break;
426  case ISD::SETULT:
427  case ISD::SETULE:
428  case ISD::SETLT:
429  case ISD::SETLE:
431  std::swap(LHS, RHS);
432  break;
433  }
434 }
435 
436 SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
437  SDValue Chain = Op.getOperand(0);
438  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
439  SDValue LHS = Op.getOperand(2);
440  SDValue RHS = Op.getOperand(3);
441  SDValue Dest = Op.getOperand(4);
442  SDLoc DL(Op);
443 
444  NegateCC(LHS, RHS, CC);
445 
446  return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
447  DAG.getConstant(CC, DL, MVT::i64), Dest);
448 }
449 
450 SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
451  SDValue LHS = Op.getOperand(0);
452  SDValue RHS = Op.getOperand(1);
453  SDValue TrueV = Op.getOperand(2);
454  SDValue FalseV = Op.getOperand(3);
455  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
456  SDLoc DL(Op);
457 
458  NegateCC(LHS, RHS, CC);
459 
460  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64);
461 
462  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
463  SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
464 
465  return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
466 }
467 
468 const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
469  switch ((BPFISD::NodeType)Opcode) {
471  break;
472  case BPFISD::RET_FLAG:
473  return "BPFISD::RET_FLAG";
474  case BPFISD::CALL:
475  return "BPFISD::CALL";
476  case BPFISD::SELECT_CC:
477  return "BPFISD::SELECT_CC";
478  case BPFISD::BR_CC:
479  return "BPFISD::BR_CC";
480  case BPFISD::Wrapper:
481  return "BPFISD::Wrapper";
482  }
483  return nullptr;
484 }
485 
486 SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
487  SelectionDAG &DAG) const {
488  SDLoc DL(Op);
489  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
490  SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
491 
492  return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
493 }
494 
497  MachineBasicBlock *BB) const {
499  DebugLoc DL = MI.getDebugLoc();
500 
501  assert(MI.getOpcode() == BPF::Select && "Unexpected instr type to insert");
502 
503  // To "insert" a SELECT instruction, we actually have to insert the diamond
504  // control-flow pattern. The incoming instruction knows the destination vreg
505  // to set, the condition code register to branch on, the true/false values to
506  // select between, and a branch opcode to use.
507  const BasicBlock *LLVM_BB = BB->getBasicBlock();
509 
510  // ThisMBB:
511  // ...
512  // TrueVal = ...
513  // jmp_XX r1, r2 goto Copy1MBB
514  // fallthrough --> Copy0MBB
515  MachineBasicBlock *ThisMBB = BB;
516  MachineFunction *F = BB->getParent();
517  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
518  MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
519 
520  F->insert(I, Copy0MBB);
521  F->insert(I, Copy1MBB);
522  // Update machine-CFG edges by transferring all successors of the current
523  // block to the new block which will contain the Phi node for the select.
524  Copy1MBB->splice(Copy1MBB->begin(), BB,
525  std::next(MachineBasicBlock::iterator(MI)), BB->end());
526  Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
527  // Next, add the true and fallthrough blocks as its successors.
528  BB->addSuccessor(Copy0MBB);
529  BB->addSuccessor(Copy1MBB);
530 
531  // Insert Branch if Flag
532  unsigned LHS = MI.getOperand(1).getReg();
533  unsigned RHS = MI.getOperand(2).getReg();
534  int CC = MI.getOperand(3).getImm();
535  switch (CC) {
536  case ISD::SETGT:
537  BuildMI(BB, DL, TII.get(BPF::JSGT_rr))
538  .addReg(LHS)
539  .addReg(RHS)
540  .addMBB(Copy1MBB);
541  break;
542  case ISD::SETUGT:
543  BuildMI(BB, DL, TII.get(BPF::JUGT_rr))
544  .addReg(LHS)
545  .addReg(RHS)
546  .addMBB(Copy1MBB);
547  break;
548  case ISD::SETGE:
549  BuildMI(BB, DL, TII.get(BPF::JSGE_rr))
550  .addReg(LHS)
551  .addReg(RHS)
552  .addMBB(Copy1MBB);
553  break;
554  case ISD::SETUGE:
555  BuildMI(BB, DL, TII.get(BPF::JUGE_rr))
556  .addReg(LHS)
557  .addReg(RHS)
558  .addMBB(Copy1MBB);
559  break;
560  case ISD::SETEQ:
561  BuildMI(BB, DL, TII.get(BPF::JEQ_rr))
562  .addReg(LHS)
563  .addReg(RHS)
564  .addMBB(Copy1MBB);
565  break;
566  case ISD::SETNE:
567  BuildMI(BB, DL, TII.get(BPF::JNE_rr))
568  .addReg(LHS)
569  .addReg(RHS)
570  .addMBB(Copy1MBB);
571  break;
572  default:
573  report_fatal_error("unimplemented select CondCode " + Twine(CC));
574  }
575 
576  // Copy0MBB:
577  // %FalseValue = ...
578  // # fallthrough to Copy1MBB
579  BB = Copy0MBB;
580 
581  // Update machine-CFG edges
582  BB->addSuccessor(Copy1MBB);
583 
584  // Copy1MBB:
585  // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
586  // ...
587  BB = Copy1MBB;
588  BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
589  .addReg(MI.getOperand(5).getReg())
590  .addMBB(Copy0MBB)
591  .addReg(MI.getOperand(4).getReg())
592  .addMBB(ThisMBB);
593 
594  MI.eraseFromParent(); // The pseudo instruction is gone now.
595  return BB;
596 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVMContext * getContext() const
Definition: SelectionDAG.h:333
static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC)
Diagnostic information for unsupported feature in backend.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:724
size_t i
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:572
LocInfo getLocInfo() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:219
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:615
static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg)
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.cpp:238
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:369
bool isRegLoc() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:388
std::string getEVTString() const
getEVTString - This function returns value type as a string, e.g.
Definition: ValueTypes.cpp:120
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
struct fuzzer::@269 Flags
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:327
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:611
unsigned getLocReg() const
#define F(x, y, z)
Definition: MD5.cpp:51
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:421
SmallVector< ISD::OutputArg, 32 > Outs
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
int64_t getImm() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
TargetInstrInfo - Interface to description of machine instruction set.
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
const SDValue & getOperand(unsigned i) const
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
MVT getLocVT() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:228
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
self_iterator getIterator()
Definition: ilist_node.h:81
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y)...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:350
EVT - Extended Value Type.
Definition: ValueTypes.h:31
This structure contains all information that is necessary for lowering calls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const TargetRegisterInfo * getRegisterInfo() const override
Definition: BPFSubtarget.h:58
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const DebugLoc & getDebugLoc() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:566
const DataFlowGraph & G
Definition: RDFGraph.cpp:206
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:584
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:715
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:354
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:400
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:403
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:560
Representation of each machine instruction.
Definition: MachineInstr.h:52
SmallVector< SDValue, 32 > OutVals
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:247
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:610
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:418
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual const TargetInstrInfo * getInstrInfo() const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:377
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
Conversion operators.
Definition: ISDOpcodes.h:397
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:406
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:226
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:529
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:326
BRIND - Indirect branch.
Definition: ISDOpcodes.h:556
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:545