LLVM  4.0.0
RDFLiveness.cpp
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1 //===--- RDFLiveness.cpp --------------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Computation of the liveness information from the data-flow graph.
11 //
12 // The main functionality of this code is to compute block live-in
13 // information. With the live-in information in place, the placement
14 // of kill flags can also be recalculated.
15 //
16 // The block live-in calculation is based on the ideas from the following
17 // publication:
18 //
19 // Dibyendu Das, Ramakrishna Upadrasta, Benoit Dupont de Dinechin.
20 // "Efficient Liveness Computation Using Merge Sets and DJ-Graphs."
21 // ACM Transactions on Architecture and Code Optimization, Association for
22 // Computing Machinery, 2012, ACM TACO Special Issue on "High-Performance
23 // and Embedded Architectures and Compilers", 8 (4),
24 // <10.1145/2086696.2086706>. <hal-00647369>
25 //
26 #include "RDFGraph.h"
27 #include "RDFLiveness.h"
28 #include "llvm/ADT/SetVector.h"
35 
36 using namespace llvm;
37 using namespace rdf;
38 
39 namespace llvm {
40 namespace rdf {
41  template<>
42  raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) {
43  OS << '{';
44  for (auto &I : P.Obj) {
45  OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{';
46  for (auto J = I.second.begin(), E = I.second.end(); J != E; ) {
47  OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second);
48  if (++J != E)
49  OS << ',';
50  }
51  OS << '}';
52  }
53  OS << " }";
54  return OS;
55  }
56 } // namespace rdf
57 } // namespace llvm
58 
59 // The order in the returned sequence is the order of reaching defs in the
60 // upward traversal: the first def is the closest to the given reference RefA,
61 // the next one is further up, and so on.
62 // The list ends at a reaching phi def, or when the reference from RefA is
63 // covered by the defs in the list (see FullChain).
64 // This function provides two modes of operation:
65 // (1) Returning the sequence of reaching defs for a particular reference
66 // node. This sequence will terminate at the first phi node [1].
67 // (2) Returning a partial sequence of reaching defs, where the final goal
68 // is to traverse past phi nodes to the actual defs arising from the code
69 // itself.
70 // In mode (2), the register reference for which the search was started
71 // may be different from the reference node RefA, for which this call was
72 // made, hence the argument RefRR, which holds the original register.
73 // Also, some definitions may have already been encountered in a previous
74 // call that will influence register covering. The register references
75 // already defined are passed in through DefRRs.
76 // In mode (1), the "continuation" considerations do not apply, and the
77 // RefRR is the same as the register in RefA, and the set DefRRs is empty.
78 //
79 // [1] It is possible for multiple phi nodes to be included in the returned
80 // sequence:
81 // SubA = phi ...
82 // SubB = phi ...
83 // ... = SuperAB(rdef:SubA), SuperAB"(rdef:SubB)
84 // However, these phi nodes are independent from one another in terms of
85 // the data-flow.
86 
88  NodeAddr<RefNode*> RefA, bool FullChain, const RegisterAggr &DefRRs) {
89  NodeList RDefs; // Return value.
90  SetVector<NodeId> DefQ;
91  SetVector<NodeId> Owners;
92 
93  // Dead defs will be treated as if they were live, since they are actually
94  // on the data-flow path. They cannot be ignored because even though they
95  // do not generate meaningful values, they still modify registers.
96 
97  // If the reference is undefined, there is nothing to do.
98  if (RefA.Addr->getFlags() & NodeAttrs::Undef)
99  return RDefs;
100 
101  // The initial queue should not have reaching defs for shadows. The
102  // whole point of a shadow is that it will have a reaching def that
103  // is not aliased to the reaching defs of the related shadows.
104  NodeId Start = RefA.Id;
105  auto SNA = DFG.addr<RefNode*>(Start);
106  if (NodeId RD = SNA.Addr->getReachingDef())
107  DefQ.insert(RD);
108 
109  // Collect all the reaching defs, going up until a phi node is encountered,
110  // or there are no more reaching defs. From this set, the actual set of
111  // reaching defs will be selected.
112  // The traversal upwards must go on until a covering def is encountered.
113  // It is possible that a collection of non-covering (individually) defs
114  // will be sufficient, but keep going until a covering one is found.
115  for (unsigned i = 0; i < DefQ.size(); ++i) {
116  auto TA = DFG.addr<DefNode*>(DefQ[i]);
117  if (TA.Addr->getFlags() & NodeAttrs::PhiRef)
118  continue;
119  // Stop at the covering/overwriting def of the initial register reference.
120  RegisterRef RR = TA.Addr->getRegRef(DFG);
121  if (!DFG.IsPreservingDef(TA))
122  if (RegisterAggr::isCoverOf(RR, RefRR, TRI))
123  continue;
124  // Get the next level of reaching defs. This will include multiple
125  // reaching defs for shadows.
126  for (auto S : DFG.getRelatedRefs(TA.Addr->getOwner(DFG), TA))
127  if (NodeId RD = NodeAddr<RefNode*>(S).Addr->getReachingDef())
128  DefQ.insert(RD);
129  }
130 
131  // Remove all non-phi defs that are not aliased to RefRR, and collect
132  // the owners of the remaining defs.
133  SetVector<NodeId> Defs;
134  for (NodeId N : DefQ) {
135  auto TA = DFG.addr<DefNode*>(N);
136  bool IsPhi = TA.Addr->getFlags() & NodeAttrs::PhiRef;
137  if (!IsPhi && !DFG.alias(RefRR, TA.Addr->getRegRef(DFG)))
138  continue;
139  Defs.insert(TA.Id);
140  Owners.insert(TA.Addr->getOwner(DFG).Id);
141  }
142 
143  // Return the MachineBasicBlock containing a given instruction.
144  auto Block = [this] (NodeAddr<InstrNode*> IA) -> MachineBasicBlock* {
145  if (IA.Addr->getKind() == NodeAttrs::Stmt)
146  return NodeAddr<StmtNode*>(IA).Addr->getCode()->getParent();
147  assert(IA.Addr->getKind() == NodeAttrs::Phi);
148  NodeAddr<PhiNode*> PA = IA;
149  NodeAddr<BlockNode*> BA = PA.Addr->getOwner(DFG);
150  return BA.Addr->getCode();
151  };
152  // Less(A,B) iff instruction A is further down in the dominator tree than B.
153  auto Less = [&Block,this] (NodeId A, NodeId B) -> bool {
154  if (A == B)
155  return false;
156  auto OA = DFG.addr<InstrNode*>(A), OB = DFG.addr<InstrNode*>(B);
157  MachineBasicBlock *BA = Block(OA), *BB = Block(OB);
158  if (BA != BB)
159  return MDT.dominates(BB, BA);
160  // They are in the same block.
161  bool StmtA = OA.Addr->getKind() == NodeAttrs::Stmt;
162  bool StmtB = OB.Addr->getKind() == NodeAttrs::Stmt;
163  if (StmtA) {
164  if (!StmtB) // OB is a phi and phis dominate statements.
165  return true;
166  MachineInstr *CA = NodeAddr<StmtNode*>(OA).Addr->getCode();
167  MachineInstr *CB = NodeAddr<StmtNode*>(OB).Addr->getCode();
168  // The order must be linear, so tie-break such equalities.
169  if (CA == CB)
170  return A < B;
171  return MDT.dominates(CB, CA);
172  } else {
173  // OA is a phi.
174  if (StmtB)
175  return false;
176  // Both are phis. There is no ordering between phis (in terms of
177  // the data-flow), so tie-break this via node id comparison.
178  return A < B;
179  }
180  };
181 
182  std::vector<NodeId> Tmp(Owners.begin(), Owners.end());
183  std::sort(Tmp.begin(), Tmp.end(), Less);
184 
185  // The vector is a list of instructions, so that defs coming from
186  // the same instruction don't need to be artificially ordered.
187  // Then, when computing the initial segment, and iterating over an
188  // instruction, pick the defs that contribute to the covering (i.e. is
189  // not covered by previously added defs). Check the defs individually,
190  // i.e. first check each def if is covered or not (without adding them
191  // to the tracking set), and then add all the selected ones.
192 
193  // The reason for this is this example:
194  // *d1<A>, *d2<B>, ... Assume A and B are aliased (can happen in phi nodes).
195  // *d3<C> If A \incl BuC, and B \incl AuC, then *d2 would be
196  // covered if we added A first, and A would be covered
197  // if we added B first.
198 
199  RegisterAggr RRs(DefRRs);
200 
201  auto DefInSet = [&Defs] (NodeAddr<RefNode*> TA) -> bool {
202  return TA.Addr->getKind() == NodeAttrs::Def &&
203  Defs.count(TA.Id);
204  };
205  for (NodeId T : Tmp) {
206  if (!FullChain && RRs.hasCoverOf(RefRR))
207  break;
208  auto TA = DFG.addr<InstrNode*>(T);
209  bool IsPhi = DFG.IsCode<NodeAttrs::Phi>(TA);
210  NodeList Ds;
211  for (NodeAddr<DefNode*> DA : TA.Addr->members_if(DefInSet, DFG)) {
212  RegisterRef QR = DA.Addr->getRegRef(DFG);
213  // Add phi defs even if they are covered by subsequent defs. This is
214  // for cases where the reached use is not covered by any of the defs
215  // encountered so far: the phi def is needed to expose the liveness
216  // of that use to the entry of the block.
217  // Example:
218  // phi d1<R3>(,d2,), ... Phi def d1 is covered by d2.
219  // d2<R3>(d1,,u3), ...
220  // ..., u3<D1>(d2) This use needs to be live on entry.
221  if (FullChain || IsPhi || !RRs.hasCoverOf(QR))
222  Ds.push_back(DA);
223  }
224  RDefs.insert(RDefs.end(), Ds.begin(), Ds.end());
225  for (NodeAddr<DefNode*> DA : Ds) {
226  // When collecting a full chain of definitions, do not consider phi
227  // defs to actually define a register.
228  uint16_t Flags = DA.Addr->getFlags();
229  if (!FullChain || !(Flags & NodeAttrs::PhiRef))
230  if (!(Flags & NodeAttrs::Preserving)) // Don't care about Undef here.
231  RRs.insert(DA.Addr->getRegRef(DFG));
232  }
233  }
234 
235  auto DeadP = [](const NodeAddr<DefNode*> DA) -> bool {
236  return DA.Addr->getFlags() & NodeAttrs::Dead;
237  };
238  RDefs.resize(std::distance(RDefs.begin(), remove_if(RDefs, DeadP)));
239 
240  return RDefs;
241 }
242 
243 
245  NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) {
246  // Collect all defined registers. Do not consider phis to be defining
247  // anything, only collect "real" definitions.
248  RegisterAggr DefRRs(TRI);
249  for (NodeId D : Defs) {
250  const auto DA = DFG.addr<const DefNode*>(D);
251  if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
252  DefRRs.insert(DA.Addr->getRegRef(DFG));
253  }
254 
255  NodeList RDs = getAllReachingDefs(RefRR, RefA, true, DefRRs);
256  if (RDs.empty())
257  return Defs;
258 
259  // Make a copy of the preexisting definitions and add the newly found ones.
260  NodeSet TmpDefs = Defs;
261  for (NodeAddr<NodeBase*> R : RDs)
262  TmpDefs.insert(R.Id);
263 
264  NodeSet Result = Defs;
265 
266  for (NodeAddr<DefNode*> DA : RDs) {
267  Result.insert(DA.Id);
268  if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef))
269  continue;
270  NodeAddr<PhiNode*> PA = DA.Addr->getOwner(DFG);
271  if (Visited.count(PA.Id))
272  continue;
273  Visited.insert(PA.Id);
274  // Go over all phi uses and get the reaching defs for each use.
275  for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
276  const auto &T = getAllReachingDefsRec(RefRR, U, Visited, TmpDefs);
277  Result.insert(T.begin(), T.end());
278  }
279  }
280 
281  return Result;
282 }
283 
284 
286  NodeAddr<DefNode*> DefA, const RegisterAggr &DefRRs) {
287  NodeSet Uses;
288 
289  // If the original register is already covered by all the intervening
290  // defs, no more uses can be reached.
291  if (DefRRs.hasCoverOf(RefRR))
292  return Uses;
293 
294  // Add all directly reached uses.
295  // If the def is dead, it does not provide a value for any use.
296  bool IsDead = DefA.Addr->getFlags() & NodeAttrs::Dead;
297  NodeId U = !IsDead ? DefA.Addr->getReachedUse() : 0;
298  while (U != 0) {
299  auto UA = DFG.addr<UseNode*>(U);
300  if (!(UA.Addr->getFlags() & NodeAttrs::Undef)) {
301  RegisterRef UR = UA.Addr->getRegRef(DFG);
302  if (DFG.alias(RefRR, UR) && !DefRRs.hasCoverOf(UR))
303  Uses.insert(U);
304  }
305  U = UA.Addr->getSibling();
306  }
307 
308  // Traverse all reached defs. This time dead defs cannot be ignored.
309  for (NodeId D = DefA.Addr->getReachedDef(), NextD; D != 0; D = NextD) {
310  auto DA = DFG.addr<DefNode*>(D);
311  NextD = DA.Addr->getSibling();
312  RegisterRef DR = DA.Addr->getRegRef(DFG);
313  // If this def is already covered, it cannot reach anything new.
314  // Similarly, skip it if it is not aliased to the interesting register.
315  if (DefRRs.hasCoverOf(DR) || !DFG.alias(RefRR, DR))
316  continue;
317  NodeSet T;
318  if (DFG.IsPreservingDef(DA)) {
319  // If it is a preserving def, do not update the set of intervening defs.
320  T = getAllReachedUses(RefRR, DA, DefRRs);
321  } else {
322  RegisterAggr NewDefRRs = DefRRs;
323  NewDefRRs.insert(DR);
324  T = getAllReachedUses(RefRR, DA, NewDefRRs);
325  }
326  Uses.insert(T.begin(), T.end());
327  }
328  return Uses;
329 }
330 
331 
333  RealUseMap.clear();
334 
335  NodeList Phis;
336  NodeAddr<FuncNode*> FA = DFG.getFunc();
337  NodeList Blocks = FA.Addr->members(DFG);
338  for (NodeAddr<BlockNode*> BA : Blocks) {
339  auto Ps = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG);
340  Phis.insert(Phis.end(), Ps.begin(), Ps.end());
341  }
342 
343  // phi use -> (map: reaching phi -> set of registers defined in between)
344  std::map<NodeId,std::map<NodeId,RegisterAggr>> PhiUp;
345  std::vector<NodeId> PhiUQ; // Work list of phis for upward propagation.
346 
347  // Go over all phis.
348  for (NodeAddr<PhiNode*> PhiA : Phis) {
349  // Go over all defs and collect the reached uses that are non-phi uses
350  // (i.e. the "real uses").
351  RefMap &RealUses = RealUseMap[PhiA.Id];
352  NodeList PhiRefs = PhiA.Addr->members(DFG);
353 
354  // Have a work queue of defs whose reached uses need to be found.
355  // For each def, add to the queue all reached (non-phi) defs.
356  SetVector<NodeId> DefQ;
357  NodeSet PhiDefs;
358  for (NodeAddr<RefNode*> R : PhiRefs) {
359  if (!DFG.IsRef<NodeAttrs::Def>(R))
360  continue;
361  DefQ.insert(R.Id);
362  PhiDefs.insert(R.Id);
363  }
364 
365  // Collect the super-set of all possible reached uses. This set will
366  // contain all uses reached from this phi, either directly from the
367  // phi defs, or (recursively) via non-phi defs reached by the phi defs.
368  // This set of uses will later be trimmed to only contain these uses that
369  // are actually reached by the phi defs.
370  for (unsigned i = 0; i < DefQ.size(); ++i) {
371  NodeAddr<DefNode*> DA = DFG.addr<DefNode*>(DefQ[i]);
372  // Visit all reached uses. Phi defs should not really have the "dead"
373  // flag set, but check it anyway for consistency.
374  bool IsDead = DA.Addr->getFlags() & NodeAttrs::Dead;
375  NodeId UN = !IsDead ? DA.Addr->getReachedUse() : 0;
376  while (UN != 0) {
377  NodeAddr<UseNode*> A = DFG.addr<UseNode*>(UN);
378  uint16_t F = A.Addr->getFlags();
379  if ((F & (NodeAttrs::Undef | NodeAttrs::PhiRef)) == 0) {
380  RegisterRef R = DFG.normalizeRef(getRestrictedRegRef(A));
381  RealUses[R.Reg].insert({A.Id,R.Mask});
382  }
383  UN = A.Addr->getSibling();
384  }
385  // Visit all reached defs, and add them to the queue. These defs may
386  // override some of the uses collected here, but that will be handled
387  // later.
388  NodeId DN = DA.Addr->getReachedDef();
389  while (DN != 0) {
390  NodeAddr<DefNode*> A = DFG.addr<DefNode*>(DN);
391  for (auto T : DFG.getRelatedRefs(A.Addr->getOwner(DFG), A)) {
392  uint16_t Flags = NodeAddr<DefNode*>(T).Addr->getFlags();
393  // Must traverse the reached-def chain. Consider:
394  // def(D0) -> def(R0) -> def(R0) -> use(D0)
395  // The reachable use of D0 passes through a def of R0.
396  if (!(Flags & NodeAttrs::PhiRef))
397  DefQ.insert(T.Id);
398  }
399  DN = A.Addr->getSibling();
400  }
401  }
402  // Filter out these uses that appear to be reachable, but really
403  // are not. For example:
404  //
405  // R1:0 = d1
406  // = R1:0 u2 Reached by d1.
407  // R0 = d3
408  // = R1:0 u4 Still reached by d1: indirectly through
409  // the def d3.
410  // R1 = d5
411  // = R1:0 u6 Not reached by d1 (covered collectively
412  // by d3 and d5), but following reached
413  // defs and uses from d1 will lead here.
414  auto InPhiDefs = [&PhiDefs] (NodeAddr<DefNode*> DA) -> bool {
415  return PhiDefs.count(DA.Id);
416  };
417  for (auto UI = RealUses.begin(), UE = RealUses.end(); UI != UE; ) {
418  // For each reached register UI->first, there is a set UI->second, of
419  // uses of it. For each such use, check if it is reached by this phi,
420  // i.e. check if the set of its reaching uses intersects the set of
421  // this phi's defs.
422  NodeRefSet &Uses = UI->second;
423  for (auto I = Uses.begin(), E = Uses.end(); I != E; ) {
424  auto UA = DFG.addr<UseNode*>(I->first);
425  // Undef flag is checked above.
426  assert((UA.Addr->getFlags() & NodeAttrs::Undef) == 0);
427  RegisterRef R(UI->first, I->second);
428  NodeList RDs = getAllReachingDefs(R, UA);
429  if (any_of(RDs, InPhiDefs))
430  ++I;
431  else
432  I = Uses.erase(I);
433  }
434  if (Uses.empty())
435  UI = RealUses.erase(UI);
436  else
437  ++UI;
438  }
439 
440  // If this phi reaches some "real" uses, add it to the queue for upward
441  // propagation.
442  if (!RealUses.empty())
443  PhiUQ.push_back(PhiA.Id);
444 
445  // Go over all phi uses and check if the reaching def is another phi.
446  // Collect the phis that are among the reaching defs of these uses.
447  // While traversing the list of reaching defs for each phi use, accumulate
448  // the set of registers defined between this phi (PhiA) and the owner phi
449  // of the reaching def.
450  NodeSet SeenUses;
451 
452  for (auto I : PhiRefs) {
453  if (!DFG.IsRef<NodeAttrs::Use>(I) || SeenUses.count(I.Id))
454  continue;
455  NodeAddr<UseNode*> UA = I;
456 
457  // Given a phi use UA, traverse all related phi uses (including UA).
458  // The related phi uses may reach different phi nodes or may reach the
459  // same phi node. If multiple uses reach the same phi P, the intervening
460  // defs must be accumulated for all such uses. To group all such uses
461  // into one set, map their node ids to the first use id that reaches P.
462  std::map<NodeId,NodeId> FirstUse; // Phi reached up -> first phi use.
463 
464  for (NodeAddr<UseNode*> VA : DFG.getRelatedRefs(PhiA, UA)) {
465  SeenUses.insert(VA.Id);
466  RegisterAggr DefRRs(TRI);
467  for (NodeAddr<DefNode*> DA : getAllReachingDefs(VA)) {
468  if (DA.Addr->getFlags() & NodeAttrs::PhiRef) {
469  NodeId RP = DA.Addr->getOwner(DFG).Id;
470  NodeId FU = FirstUse.insert({RP,VA.Id}).first->second;
471  std::map<NodeId,RegisterAggr> &M = PhiUp[FU];
472  auto F = M.find(RP);
473  if (F == M.end())
474  M.insert(std::make_pair(RP, DefRRs));
475  else
476  F->second.insert(DefRRs);
477  }
478  DefRRs.insert(DA.Addr->getRegRef(DFG));
479  }
480  }
481  }
482  }
483 
484  if (Trace) {
485  dbgs() << "Phi-up-to-phi map with intervening defs:\n";
486  for (auto I : PhiUp) {
487  dbgs() << "phi " << Print<NodeId>(I.first, DFG) << " -> {";
488  for (auto R : I.second)
489  dbgs() << ' ' << Print<NodeId>(R.first, DFG)
490  << Print<RegisterAggr>(R.second, DFG);
491  dbgs() << " }\n";
492  }
493  }
494 
495  // Propagate the reached registers up in the phi chain.
496  //
497  // The following type of situation needs careful handling:
498  //
499  // phi d1<R1:0> (1)
500  // |
501  // ... d2<R1>
502  // |
503  // phi u3<R1:0> (2)
504  // |
505  // ... u4<R1>
506  //
507  // The phi node (2) defines a register pair R1:0, and reaches a "real"
508  // use u4 of just R1. The same phi node is also known to reach (upwards)
509  // the phi node (1). However, the use u4 is not reached by phi (1),
510  // because of the intervening definition d2 of R1. The data flow between
511  // phis (1) and (2) is restricted to R1:0 minus R1, i.e. R0.
512  //
513  // When propagating uses up the phi chains, get the all reaching defs
514  // for a given phi use, and traverse the list until the propagated ref
515  // is covered, or until reaching the final phi. Only assume that the
516  // reference reaches the phi in the latter case.
517 
518  for (unsigned i = 0; i < PhiUQ.size(); ++i) {
519  auto PA = DFG.addr<PhiNode*>(PhiUQ[i]);
520  NodeList PUs = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG);
521  RefMap &RUM = RealUseMap[PA.Id];
522 
523  for (NodeAddr<UseNode*> UA : PUs) {
524  std::map<NodeId,RegisterAggr> &PUM = PhiUp[UA.Id];
525  RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(UA));
526  for (const std::pair<NodeId,RegisterAggr> &P : PUM) {
527  bool Changed = false;
528  const RegisterAggr &MidDefs = P.second;
529 
530  // Collect the set PropUp of uses that are reached by the current
531  // phi PA, and are not covered by any intervening def between the
532  // currently visited use UA and the the upward phi P.
533 
534  if (MidDefs.hasCoverOf(UR))
535  continue;
536 
537  // General algorithm:
538  // for each (R,U) : U is use node of R, U is reached by PA
539  // if MidDefs does not cover (R,U)
540  // then add (R-MidDefs,U) to RealUseMap[P]
541  //
542  for (const std::pair<RegisterId,NodeRefSet> &T : RUM) {
543  RegisterRef R = DFG.restrictRef(RegisterRef(T.first), UR);
544  if (!R)
545  continue;
546  for (std::pair<NodeId,LaneBitmask> V : T.second) {
547  RegisterRef S = DFG.restrictRef(RegisterRef(R.Reg, V.second), R);
548  if (!S)
549  continue;
550  if (RegisterRef SS = MidDefs.clearIn(S)) {
551  NodeRefSet &RS = RealUseMap[P.first][SS.Reg];
552  Changed |= RS.insert({V.first,SS.Mask}).second;
553  }
554  }
555  }
556 
557  if (Changed)
558  PhiUQ.push_back(P.first);
559  }
560  }
561  }
562 
563  if (Trace) {
564  dbgs() << "Real use map:\n";
565  for (auto I : RealUseMap) {
566  dbgs() << "phi " << Print<NodeId>(I.first, DFG);
567  NodeAddr<PhiNode*> PA = DFG.addr<PhiNode*>(I.first);
568  NodeList Ds = PA.Addr->members_if(DFG.IsRef<NodeAttrs::Def>, DFG);
569  if (!Ds.empty()) {
570  RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(DFG);
571  dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>';
572  } else {
573  dbgs() << "<noreg>";
574  }
575  dbgs() << " -> " << Print<RefMap>(I.second, DFG) << '\n';
576  }
577  }
578 }
579 
580 
582  // Populate the node-to-block map. This speeds up the calculations
583  // significantly.
584  NBMap.clear();
585  for (NodeAddr<BlockNode*> BA : DFG.getFunc().Addr->members(DFG)) {
586  MachineBasicBlock *BB = BA.Addr->getCode();
587  for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) {
588  for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG))
589  NBMap.insert(std::make_pair(RA.Id, BB));
590  NBMap.insert(std::make_pair(IA.Id, BB));
591  }
592  }
593 
594  MachineFunction &MF = DFG.getMF();
595 
596  // Compute IDF first, then the inverse.
597  decltype(IIDF) IDF;
598  for (MachineBasicBlock &B : MF) {
599  auto F1 = MDF.find(&B);
600  if (F1 == MDF.end())
601  continue;
602  SetVector<MachineBasicBlock*> IDFB(F1->second.begin(), F1->second.end());
603  for (unsigned i = 0; i < IDFB.size(); ++i) {
604  auto F2 = MDF.find(IDFB[i]);
605  if (F2 != MDF.end())
606  IDFB.insert(F2->second.begin(), F2->second.end());
607  }
608  // Add B to the IDF(B). This will put B in the IIDF(B).
609  IDFB.insert(&B);
610  IDF[&B].insert(IDFB.begin(), IDFB.end());
611  }
612 
613  for (auto I : IDF)
614  for (auto S : I.second)
615  IIDF[S].insert(I.first);
616 
617  computePhiInfo();
618 
619  NodeAddr<FuncNode*> FA = DFG.getFunc();
620  NodeList Blocks = FA.Addr->members(DFG);
621 
622  // Build the phi live-on-entry map.
623  for (NodeAddr<BlockNode*> BA : Blocks) {
624  MachineBasicBlock *MB = BA.Addr->getCode();
625  RefMap &LON = PhiLON[MB];
626  for (auto P : BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG))
627  for (const RefMap::value_type &S : RealUseMap[P.Id])
628  LON[S.first].insert(S.second.begin(), S.second.end());
629  }
630 
631  if (Trace) {
632  dbgs() << "Phi live-on-entry map:\n";
633  for (auto &I : PhiLON)
634  dbgs() << "block #" << I.first->getNumber() << " -> "
635  << Print<RefMap>(I.second, DFG) << '\n';
636  }
637 
638  // Build the phi live-on-exit map. Each phi node has some set of reached
639  // "real" uses. Propagate this set backwards into the block predecessors
640  // through the reaching defs of the corresponding phi uses.
641  for (NodeAddr<BlockNode*> BA : Blocks) {
642  NodeList Phis = BA.Addr->members_if(DFG.IsCode<NodeAttrs::Phi>, DFG);
643  for (NodeAddr<PhiNode*> PA : Phis) {
644  RefMap &RUs = RealUseMap[PA.Id];
645  if (RUs.empty())
646  continue;
647 
648  for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) {
649  NodeAddr<PhiUseNode*> PUA = U;
650  if (PUA.Addr->getReachingDef() == 0)
651  continue;
652 
653  // Mark all reached "real" uses of P as live on exit in the
654  // predecessor.
655  // Remap all the RUs so that they have a correct reaching def.
656  auto PrA = DFG.addr<BlockNode*>(PUA.Addr->getPredecessor());
657  RefMap &LOX = PhiLOX[PrA.Addr->getCode()];
658 
659  RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(PUA));
660  for (const std::pair<RegisterId,NodeRefSet> &T : RUs) {
661  // Check if T.first aliases UR?
662  LaneBitmask M;
663  for (std::pair<NodeId,LaneBitmask> P : T.second)
664  M |= P.second;
665 
666  RegisterRef S = DFG.restrictRef(RegisterRef(T.first, M), UR);
667  if (!S)
668  continue;
669  for (NodeAddr<DefNode*> D : getAllReachingDefs(S, PUA))
670  LOX[S.Reg].insert({D.Id, S.Mask});
671  }
672  } // for U : phi uses
673  } // for P : Phis
674  } // for B : Blocks
675 
676  if (Trace) {
677  dbgs() << "Phi live-on-exit map:\n";
678  for (auto &I : PhiLOX)
679  dbgs() << "block #" << I.first->getNumber() << " -> "
680  << Print<RefMap>(I.second, DFG) << '\n';
681  }
682 
683  RefMap LiveIn;
684  traverse(&MF.front(), LiveIn);
685 
686  // Add function live-ins to the live-in set of the function entry block.
687  auto &EntryIn = LiveMap[&MF.front()];
688  for (auto I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I)
689  EntryIn.insert(RegisterRef(I->first));
690 
691  if (Trace) {
692  // Dump the liveness map
693  for (MachineBasicBlock &B : MF) {
694  std::vector<RegisterRef> LV;
695  for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
696  LV.push_back(RegisterRef(I->PhysReg, I->LaneMask));
697  std::sort(LV.begin(), LV.end());
698  dbgs() << "BB#" << B.getNumber() << "\t rec = {";
699  for (auto I : LV)
700  dbgs() << ' ' << Print<RegisterRef>(I, DFG);
701  dbgs() << " }\n";
702  //dbgs() << "\tcomp = " << Print<RegisterAggr>(LiveMap[&B], DFG) << '\n';
703 
704  LV.clear();
705  for (std::pair<RegisterId,LaneBitmask> P : LiveMap[&B]) {
706  MCSubRegIndexIterator S(P.first, &TRI);
707  if (!S.isValid()) {
708  LV.push_back(RegisterRef(P.first));
709  continue;
710  }
711  do {
713  if ((M & P.second).any())
714  LV.push_back(RegisterRef(S.getSubReg()));
715  ++S;
716  } while (S.isValid());
717  }
718  std::sort(LV.begin(), LV.end());
719  dbgs() << "\tcomp = {";
720  for (auto I : LV)
721  dbgs() << ' ' << Print<RegisterRef>(I, DFG);
722  dbgs() << " }\n";
723 
724  }
725  }
726 }
727 
728 
730  for (auto &B : DFG.getMF()) {
731  // Remove all live-ins.
732  std::vector<unsigned> T;
733  for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
734  T.push_back(I->PhysReg);
735  for (auto I : T)
736  B.removeLiveIn(I);
737  // Add the newly computed live-ins.
738  auto &LiveIns = LiveMap[&B];
739  for (auto I : LiveIns) {
740  B.addLiveIn({MCPhysReg(I.first), I.second});
741  }
742  }
743 }
744 
745 
747  for (auto &B : DFG.getMF())
748  resetKills(&B);
749 }
750 
751 
753  auto CopyLiveIns = [this] (MachineBasicBlock *B, BitVector &LV) -> void {
754  for (auto I : B->liveins()) {
755  MCSubRegIndexIterator S(I.PhysReg, &TRI);
756  if (!S.isValid()) {
757  LV.set(I.PhysReg);
758  continue;
759  }
760  do {
762  if ((M & I.LaneMask).any())
763  LV.set(S.getSubReg());
764  ++S;
765  } while (S.isValid());
766  }
767  };
768 
769  BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());
770  CopyLiveIns(B, LiveIn);
771  for (auto SI : B->successors())
772  CopyLiveIns(SI, Live);
773 
774  for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
775  MachineInstr *MI = &*I;
776  if (MI->isDebugValue())
777  continue;
778 
779  MI->clearKillInfo();
780  for (auto &Op : MI->operands()) {
781  // An implicit def of a super-register may not necessarily start a
782  // live range of it, since an implicit use could be used to keep parts
783  // of it live. Instead of analyzing the implicit operands, ignore
784  // implicit defs.
785  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
786  continue;
787  unsigned R = Op.getReg();
789  continue;
790  for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
791  Live.reset(*SR);
792  }
793  for (auto &Op : MI->operands()) {
794  if (!Op.isReg() || !Op.isUse())
795  continue;
796  unsigned R = Op.getReg();
798  continue;
799  bool IsLive = false;
800  for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
801  if (!Live[*AR])
802  continue;
803  IsLive = true;
804  break;
805  }
806  if (IsLive)
807  continue;
808  Op.setIsKill(true);
809  for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
810  Live.set(*SR);
811  }
812  }
813 }
814 
815 
816 RegisterRef Liveness::getRestrictedRegRef(NodeAddr<RefNode*> RA) const {
817  assert(DFG.IsRef<NodeAttrs::Use>(RA));
818  if (RA.Addr->getFlags() & NodeAttrs::Shadow) {
819  NodeId RD = RA.Addr->getReachingDef();
820  assert(RD);
821  RA = DFG.addr<DefNode*>(RD);
822  }
823  return RA.Addr->getRegRef(DFG);
824 }
825 
826 
827 // Helper function to obtain the basic block containing the reaching def
828 // of the given use.
829 MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const {
830  auto F = NBMap.find(RN);
831  if (F != NBMap.end())
832  return F->second;
833  llvm_unreachable("Node id not in map");
834 }
835 
836 
837 void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
838  // The LiveIn map, for each (physical) register, contains the set of live
839  // reaching defs of that register that are live on entry to the associated
840  // block.
841 
842  // The summary of the traversal algorithm:
843  //
844  // R is live-in in B, if there exists a U(R), such that rdef(R) dom B
845  // and (U \in IDF(B) or B dom U).
846  //
847  // for (C : children) {
848  // LU = {}
849  // traverse(C, LU)
850  // LiveUses += LU
851  // }
852  //
853  // LiveUses -= Defs(B);
854  // LiveUses += UpwardExposedUses(B);
855  // for (C : IIDF[B])
856  // for (U : LiveUses)
857  // if (Rdef(U) dom C)
858  // C.addLiveIn(U)
859  //
860 
861  // Go up the dominator tree (depth-first).
862  MachineDomTreeNode *N = MDT.getNode(B);
863  for (auto I : *N) {
864  RefMap L;
865  MachineBasicBlock *SB = I->getBlock();
866  traverse(SB, L);
867 
868  for (auto S : L)
869  LiveIn[S.first].insert(S.second.begin(), S.second.end());
870  }
871 
872  if (Trace) {
873  dbgs() << "\n-- BB#" << B->getNumber() << ": " << __func__
874  << " after recursion into: {";
875  for (auto I : *N)
876  dbgs() << ' ' << I->getBlock()->getNumber();
877  dbgs() << " }\n";
878  dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
879  dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
880  }
881 
882  // Add reaching defs of phi uses that are live on exit from this block.
883  RefMap &PUs = PhiLOX[B];
884  for (auto &S : PUs)
885  LiveIn[S.first].insert(S.second.begin(), S.second.end());
886 
887  if (Trace) {
888  dbgs() << "after LOX\n";
889  dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
890  dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
891  }
892 
893  // The LiveIn map at this point has all defs that are live-on-exit from B,
894  // as if they were live-on-entry to B. First, we need to filter out all
895  // defs that are present in this block. Then we will add reaching defs of
896  // all upward-exposed uses.
897 
898  // To filter out the defs, first make a copy of LiveIn, and then re-populate
899  // LiveIn with the defs that should remain.
900  RefMap LiveInCopy = LiveIn;
901  LiveIn.clear();
902 
903  for (const std::pair<RegisterId,NodeRefSet> &LE : LiveInCopy) {
904  RegisterRef LRef(LE.first);
905  NodeRefSet &NewDefs = LiveIn[LRef.Reg]; // To be filled.
906  const NodeRefSet &OldDefs = LE.second;
907  for (NodeRef OR : OldDefs) {
908  // R is a def node that was live-on-exit
909  auto DA = DFG.addr<DefNode*>(OR.first);
910  NodeAddr<InstrNode*> IA = DA.Addr->getOwner(DFG);
911  NodeAddr<BlockNode*> BA = IA.Addr->getOwner(DFG);
912  if (B != BA.Addr->getCode()) {
913  // Defs from a different block need to be preserved. Defs from this
914  // block will need to be processed further, except for phi defs, the
915  // liveness of which is handled through the PhiLON/PhiLOX maps.
916  NewDefs.insert(OR);
917  continue;
918  }
919 
920  // Defs from this block need to stop the liveness from being
921  // propagated upwards. This only applies to non-preserving defs,
922  // and to the parts of the register actually covered by those defs.
923  // (Note that phi defs should always be preserving.)
924  RegisterAggr RRs(TRI);
925  LRef.Mask = OR.second;
926 
927  if (!DFG.IsPreservingDef(DA)) {
928  assert(!(IA.Addr->getFlags() & NodeAttrs::Phi));
929  // DA is a non-phi def that is live-on-exit from this block, and
930  // that is also located in this block. LRef is a register ref
931  // whose use this def reaches. If DA covers LRef, then no part
932  // of LRef is exposed upwards.A
933  if (RRs.insert(DA.Addr->getRegRef(DFG)).hasCoverOf(LRef))
934  continue;
935  }
936 
937  // DA itself was not sufficient to cover LRef. In general, it is
938  // the last in a chain of aliased defs before the exit from this block.
939  // There could be other defs in this block that are a part of that
940  // chain. Check that now: accumulate the registers from these defs,
941  // and if they all together cover LRef, it is not live-on-entry.
943  // DefNode -> InstrNode -> BlockNode.
944  NodeAddr<InstrNode*> ITA = TA.Addr->getOwner(DFG);
945  NodeAddr<BlockNode*> BTA = ITA.Addr->getOwner(DFG);
946  // Reaching defs are ordered in the upward direction.
947  if (BTA.Addr->getCode() != B) {
948  // We have reached past the beginning of B, and the accumulated
949  // registers are not covering LRef. The first def from the
950  // upward chain will be live.
951  // Subtract all accumulated defs (RRs) from LRef.
952  RegisterAggr L(TRI);
953  L.insert(LRef).clear(RRs);
954  assert(!L.empty());
955  NewDefs.insert({TA.Id,L.begin()->second});
956  break;
957  }
958 
959  // TA is in B. Only add this def to the accumulated cover if it is
960  // not preserving.
961  if (!(TA.Addr->getFlags() & NodeAttrs::Preserving))
962  RRs.insert(TA.Addr->getRegRef(DFG));
963  // If this is enough to cover LRef, then stop.
964  if (RRs.hasCoverOf(LRef))
965  break;
966  }
967  }
968  }
969 
970  emptify(LiveIn);
971 
972  if (Trace) {
973  dbgs() << "after defs in block\n";
974  dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
975  dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
976  }
977 
978  // Scan the block for upward-exposed uses and add them to the tracking set.
979  for (auto I : DFG.getFunc().Addr->findBlock(B, DFG).Addr->members(DFG)) {
980  NodeAddr<InstrNode*> IA = I;
981  if (IA.Addr->getKind() != NodeAttrs::Stmt)
982  continue;
983  for (NodeAddr<UseNode*> UA : IA.Addr->members_if(DFG.IsUse, DFG)) {
984  if (UA.Addr->getFlags() & NodeAttrs::Undef)
985  continue;
986  RegisterRef RR = DFG.normalizeRef(UA.Addr->getRegRef(DFG));
988  if (getBlockWithRef(D.Id) != B)
989  LiveIn[RR.Reg].insert({D.Id,RR.Mask});
990  }
991  }
992 
993  if (Trace) {
994  dbgs() << "after uses in block\n";
995  dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
996  dbgs() << " Local: " << Print<RegisterAggr>(LiveMap[B], DFG) << '\n';
997  }
998 
999  // Phi uses should not be propagated up the dominator tree, since they
1000  // are not dominated by their corresponding reaching defs.
1001  RegisterAggr &Local = LiveMap[B];
1002  RefMap &LON = PhiLON[B];
1003  for (auto &R : LON) {
1004  LaneBitmask M;
1005  for (auto P : R.second)
1006  M |= P.second;
1007  Local.insert(RegisterRef(R.first,M));
1008  }
1009 
1010  if (Trace) {
1011  dbgs() << "after phi uses in block\n";
1012  dbgs() << " LiveIn: " << Print<RefMap>(LiveIn, DFG) << '\n';
1013  dbgs() << " Local: " << Print<RegisterAggr>(Local, DFG) << '\n';
1014  }
1015 
1016  for (auto C : IIDF[B]) {
1017  RegisterAggr &LiveC = LiveMap[C];
1018  for (const std::pair<RegisterId,NodeRefSet> &S : LiveIn)
1019  for (auto R : S.second)
1020  if (MDT.properlyDominates(getBlockWithRef(R.first), C))
1021  LiveC.insert(RegisterRef(S.first, R.second));
1022  }
1023 }
1024 
1025 
1026 void Liveness::emptify(RefMap &M) {
1027  for (auto I = M.begin(), E = M.end(); I != E; )
1028  I = I->second.empty() ? M.erase(I) : std::next(I);
1029 }
1030 
MachineLoop * L
NodeList members(const DataFlowGraph &G) const
Definition: RDFGraph.cpp:541
MachineFunction & getMF() const
Definition: RDFGraph.h:761
RegisterRef restrictRef(RegisterRef AR, RegisterRef BR) const
Definition: RDFGraph.cpp:1097
bool alias(RegisterRef RA, RegisterRef RB) const
Definition: RDFGraph.cpp:1207
iterator_range< livein_iterator > liveins() const
size_t i
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
NodeId getReachedDef() const
Definition: RDFGraph.h:659
livein_iterator livein_end() const
uint16_t getFlags() const
Definition: RDFGraph.h:558
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
auto remove_if(R &&Range, UnaryPredicate P) -> decltype(std::begin(Range))
Provide wrappers to std::remove_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:776
std::set< NodeRef > NodeRefSet
Definition: RDFLiveness.h:47
static bool IsPreservingDef(const NodeAddr< DefNode * > DA)
Definition: RDFGraph.h:896
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isValid() const
Returns true if this iterator is not yet at the end.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
iterator end()
Get an iterator to the end of the SetVector.
Definition: SetVector.h:93
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const TargetRegisterInfo &TRI)
Definition: RDFGraph.h:521
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:78
iterator_range< succ_iterator > successors()
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:172
void clearKillInfo()
Clears kill flags on all operands.
struct fuzzer::@269 Flags
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
Definition: RDFGraph.cpp:1193
NodeId getReachedUse() const
Definition: RDFGraph.h:665
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
std::vector< NodeAddr< NodeBase * > > NodeList
Definition: RDFGraph.h:610
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
#define F(x, y, z)
Definition: MD5.cpp:51
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:136
#define T
std::map< RegisterId, NodeRefSet > RefMap
Definition: RDFLiveness.h:49
iterator begin()
Get an iterator to the beginning of the SetVector.
Definition: SetVector.h:83
Base class for the actual dominator tree node.
NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr< RefNode * > RefA, bool FullChain, const RegisterAggr &DefRRs)
Definition: RDFLiveness.cpp:87
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
reverse_iterator rend()
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
Definition: RDFGraph.cpp:547
reverse_iterator rbegin()
NodeList members_if(Predicate P, const DataFlowGraph &G) const
Definition: RDFGraph.h:1002
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isDebugValue() const
Definition: MachineInstr.h:777
INITIALIZE_PASS(HexagonEarlyIfConversion,"hexagon-eif","Hexagon early if conversion", false, false) bool HexagonEarlyIfConversion MachineBasicBlock * SB
#define P(N)
static bool IsRef(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:870
bool hasCoverOf(RegisterRef RR) const
Definition: RDFGraph.cpp:688
uint16_t getKind() const
Definition: RDFGraph.h:557
LaneBitmask Mask
Definition: RDFGraph.h:417
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
MCRegAliasIterator enumerates all registers aliasing Reg.
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:743
static bool IsCode(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:876
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint32_t NodeId
Definition: RDFGraph.h:262
NodeId getPredecessor() const
Definition: RDFGraph.h:680
iterator find(MachineBasicBlock *B)
std::pair< NodeId, LaneBitmask > NodeRef
Definition: RDFLiveness.h:46
NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr< DefNode * > DefA, const RegisterAggr &DefRRs)
unsigned getSubReg() const
Returns current sub-register.
RegisterAggr & insert(RegisterRef RR)
Definition: RDFGraph.cpp:699
NodeId getSibling() const
Definition: RDFGraph.h:635
NodeSet getAllReachingDefsRec(RegisterRef RefRR, NodeAddr< RefNode * > RefA, NodeSet &Visited, const NodeSet &Defs)
livein_iterator livein_begin() const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
std::set< NodeId > NodeSet
Definition: RDFGraph.h:613
NodeAddr< FuncNode * > getFunc() const
Definition: RDFGraph.h:760
RegisterRef getRegRef(const DataFlowGraph &G) const
Definition: RDFGraph.cpp:422
static bool IsUse(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:886
unsigned getSubRegIndex() const
Returns sub-register index of the current sub-register.
Representation of each machine instruction.
Definition: MachineInstr.h:52
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
Definition: RDFGraph.cpp:448
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
RegisterRef clearIn(RegisterRef RR) const
Definition: RDFGraph.cpp:745
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
Definition: SetVector.h:205
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
iterator end()
Definition: DenseMap.h:69
iterator find(const KeyT &Val)
Definition: DenseMap.h:127
MachineBasicBlock * getCode() const
Definition: RDFGraph.h:727
RegisterRef normalizeRef(RegisterRef RR) const
Definition: RDFGraph.cpp:1080
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A vector that has set insertion semantics.
Definition: SetVector.h:41
NodeAddr< T > addr(NodeId N) const
Definition: RDFGraph.h:756
NodeId getReachingDef() const
Definition: RDFGraph.h:628
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")