27 #define DEBUG_TYPE "asm-printer"
29 #define GET_INSTRUCTION_NAME
30 #define PRINT_ALIAS_INSTR
31 #include "AArch64GenAsmWriter.inc"
32 #define GET_INSTRUCTION_NAME
33 #define PRINT_ALIAS_INSTR
34 #include "AArch64GenAsmWriter1.inc"
58 if (Opcode == AArch64::SYSxt)
65 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
66 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
72 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
73 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
75 const char *AsmMnemonic =
nullptr;
94 if (Is64Bit && IsSigned)
111 const char *AsmMnemonic =
nullptr;
113 int64_t immr = Op2.
getImm();
114 int64_t imms = Op3.
getImm();
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
118 }
else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
119 ((imms + 1 == immr))) {
122 }
else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
125 }
else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
128 }
else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
131 }
else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
145 O <<
'\t' << (IsSigned ?
"sbfiz" :
"ubfiz") <<
'\t'
147 <<
", #" << (Is64Bit ? 64 : 32) - Op2.
getImm() <<
", #" << Op3.
getImm() + 1;
153 O <<
'\t' << (IsSigned ?
"sbfx" :
"ubfx") <<
'\t'
160 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
166 if ((Op2.
getReg() == AArch64::WZR || Op2.
getReg() == AArch64::XZR) &&
167 (ImmR == 0 || ImmS < ImmR)) {
169 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
170 int LSB = (BitWidth - ImmR) % BitWidth;
171 int Width = ImmS + 1;
174 <<
", #" << LSB <<
", #" << Width;
177 }
else if (ImmS < ImmR) {
179 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
180 int LSB = (BitWidth - ImmR) % BitWidth;
181 int Width = ImmS + 1;
190 int Width = ImmS - ImmR + 1;
194 <<
", #" << LSB <<
", #" << Width;
202 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
203 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
205 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
215 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
227 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
229 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
234 Opcode == AArch64::MOVZXi ? 64 : 32)) {
241 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
243 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
247 Value = Value & 0xffffffff;
256 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
260 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
279 case AArch64::TBXv8i8One:
280 case AArch64::TBXv8i8Two:
281 case AArch64::TBXv8i8Three:
282 case AArch64::TBXv8i8Four:
286 case AArch64::TBLv8i8One:
287 case AArch64::TBLv8i8Two:
288 case AArch64::TBLv8i8Three:
289 case AArch64::TBLv8i8Four:
293 case AArch64::TBXv16i8One:
294 case AArch64::TBXv16i8Two:
295 case AArch64::TBXv16i8Three:
296 case AArch64::TBXv16i8Four:
300 case AArch64::TBLv16i8One:
301 case AArch64::TBLv16i8Two:
302 case AArch64::TBLv16i8Three:
303 case AArch64::TBLv16i8Four:
322 { AArch64::LD1i8,
"ld1",
".b", 1,
true, 0 },
323 { AArch64::LD1i16,
"ld1",
".h", 1,
true, 0 },
324 { AArch64::LD1i32,
"ld1",
".s", 1,
true, 0 },
325 { AArch64::LD1i64,
"ld1",
".d", 1,
true, 0 },
326 { AArch64::LD1i8_POST,
"ld1",
".b", 2,
true, 1 },
327 { AArch64::LD1i16_POST,
"ld1",
".h", 2,
true, 2 },
328 { AArch64::LD1i32_POST,
"ld1",
".s", 2,
true, 4 },
329 { AArch64::LD1i64_POST,
"ld1",
".d", 2,
true, 8 },
330 { AArch64::LD1Rv16b,
"ld1r",
".16b", 0,
false, 0 },
331 { AArch64::LD1Rv8h,
"ld1r",
".8h", 0,
false, 0 },
332 { AArch64::LD1Rv4s,
"ld1r",
".4s", 0,
false, 0 },
333 { AArch64::LD1Rv2d,
"ld1r",
".2d", 0,
false, 0 },
334 { AArch64::LD1Rv8b,
"ld1r",
".8b", 0,
false, 0 },
335 { AArch64::LD1Rv4h,
"ld1r",
".4h", 0,
false, 0 },
336 { AArch64::LD1Rv2s,
"ld1r",
".2s", 0,
false, 0 },
337 { AArch64::LD1Rv1d,
"ld1r",
".1d", 0,
false, 0 },
338 { AArch64::LD1Rv16b_POST,
"ld1r",
".16b", 1,
false, 1 },
339 { AArch64::LD1Rv8h_POST,
"ld1r",
".8h", 1,
false, 2 },
340 { AArch64::LD1Rv4s_POST,
"ld1r",
".4s", 1,
false, 4 },
341 { AArch64::LD1Rv2d_POST,
"ld1r",
".2d", 1,
false, 8 },
342 { AArch64::LD1Rv8b_POST,
"ld1r",
".8b", 1,
false, 1 },
343 { AArch64::LD1Rv4h_POST,
"ld1r",
".4h", 1,
false, 2 },
344 { AArch64::LD1Rv2s_POST,
"ld1r",
".2s", 1,
false, 4 },
345 { AArch64::LD1Rv1d_POST,
"ld1r",
".1d", 1,
false, 8 },
346 { AArch64::LD1Onev16b,
"ld1",
".16b", 0,
false, 0 },
347 { AArch64::LD1Onev8h,
"ld1",
".8h", 0,
false, 0 },
348 { AArch64::LD1Onev4s,
"ld1",
".4s", 0,
false, 0 },
349 { AArch64::LD1Onev2d,
"ld1",
".2d", 0,
false, 0 },
350 { AArch64::LD1Onev8b,
"ld1",
".8b", 0,
false, 0 },
351 { AArch64::LD1Onev4h,
"ld1",
".4h", 0,
false, 0 },
352 { AArch64::LD1Onev2s,
"ld1",
".2s", 0,
false, 0 },
353 { AArch64::LD1Onev1d,
"ld1",
".1d", 0,
false, 0 },
354 { AArch64::LD1Onev16b_POST,
"ld1",
".16b", 1,
false, 16 },
355 { AArch64::LD1Onev8h_POST,
"ld1",
".8h", 1,
false, 16 },
356 { AArch64::LD1Onev4s_POST,
"ld1",
".4s", 1,
false, 16 },
357 { AArch64::LD1Onev2d_POST,
"ld1",
".2d", 1,
false, 16 },
358 { AArch64::LD1Onev8b_POST,
"ld1",
".8b", 1,
false, 8 },
359 { AArch64::LD1Onev4h_POST,
"ld1",
".4h", 1,
false, 8 },
360 { AArch64::LD1Onev2s_POST,
"ld1",
".2s", 1,
false, 8 },
361 { AArch64::LD1Onev1d_POST,
"ld1",
".1d", 1,
false, 8 },
362 { AArch64::LD1Twov16b,
"ld1",
".16b", 0,
false, 0 },
363 { AArch64::LD1Twov8h,
"ld1",
".8h", 0,
false, 0 },
364 { AArch64::LD1Twov4s,
"ld1",
".4s", 0,
false, 0 },
365 { AArch64::LD1Twov2d,
"ld1",
".2d", 0,
false, 0 },
366 { AArch64::LD1Twov8b,
"ld1",
".8b", 0,
false, 0 },
367 { AArch64::LD1Twov4h,
"ld1",
".4h", 0,
false, 0 },
368 { AArch64::LD1Twov2s,
"ld1",
".2s", 0,
false, 0 },
369 { AArch64::LD1Twov1d,
"ld1",
".1d", 0,
false, 0 },
370 { AArch64::LD1Twov16b_POST,
"ld1",
".16b", 1,
false, 32 },
371 { AArch64::LD1Twov8h_POST,
"ld1",
".8h", 1,
false, 32 },
372 { AArch64::LD1Twov4s_POST,
"ld1",
".4s", 1,
false, 32 },
373 { AArch64::LD1Twov2d_POST,
"ld1",
".2d", 1,
false, 32 },
374 { AArch64::LD1Twov8b_POST,
"ld1",
".8b", 1,
false, 16 },
375 { AArch64::LD1Twov4h_POST,
"ld1",
".4h", 1,
false, 16 },
376 { AArch64::LD1Twov2s_POST,
"ld1",
".2s", 1,
false, 16 },
377 { AArch64::LD1Twov1d_POST,
"ld1",
".1d", 1,
false, 16 },
378 { AArch64::LD1Threev16b,
"ld1",
".16b", 0,
false, 0 },
379 { AArch64::LD1Threev8h,
"ld1",
".8h", 0,
false, 0 },
380 { AArch64::LD1Threev4s,
"ld1",
".4s", 0,
false, 0 },
381 { AArch64::LD1Threev2d,
"ld1",
".2d", 0,
false, 0 },
382 { AArch64::LD1Threev8b,
"ld1",
".8b", 0,
false, 0 },
383 { AArch64::LD1Threev4h,
"ld1",
".4h", 0,
false, 0 },
384 { AArch64::LD1Threev2s,
"ld1",
".2s", 0,
false, 0 },
385 { AArch64::LD1Threev1d,
"ld1",
".1d", 0,
false, 0 },
386 { AArch64::LD1Threev16b_POST,
"ld1",
".16b", 1,
false, 48 },
387 { AArch64::LD1Threev8h_POST,
"ld1",
".8h", 1,
false, 48 },
388 { AArch64::LD1Threev4s_POST,
"ld1",
".4s", 1,
false, 48 },
389 { AArch64::LD1Threev2d_POST,
"ld1",
".2d", 1,
false, 48 },
390 { AArch64::LD1Threev8b_POST,
"ld1",
".8b", 1,
false, 24 },
391 { AArch64::LD1Threev4h_POST,
"ld1",
".4h", 1,
false, 24 },
392 { AArch64::LD1Threev2s_POST,
"ld1",
".2s", 1,
false, 24 },
393 { AArch64::LD1Threev1d_POST,
"ld1",
".1d", 1,
false, 24 },
394 { AArch64::LD1Fourv16b,
"ld1",
".16b", 0,
false, 0 },
395 { AArch64::LD1Fourv8h,
"ld1",
".8h", 0,
false, 0 },
396 { AArch64::LD1Fourv4s,
"ld1",
".4s", 0,
false, 0 },
397 { AArch64::LD1Fourv2d,
"ld1",
".2d", 0,
false, 0 },
398 { AArch64::LD1Fourv8b,
"ld1",
".8b", 0,
false, 0 },
399 { AArch64::LD1Fourv4h,
"ld1",
".4h", 0,
false, 0 },
400 { AArch64::LD1Fourv2s,
"ld1",
".2s", 0,
false, 0 },
401 { AArch64::LD1Fourv1d,
"ld1",
".1d", 0,
false, 0 },
402 { AArch64::LD1Fourv16b_POST,
"ld1",
".16b", 1,
false, 64 },
403 { AArch64::LD1Fourv8h_POST,
"ld1",
".8h", 1,
false, 64 },
404 { AArch64::LD1Fourv4s_POST,
"ld1",
".4s", 1,
false, 64 },
405 { AArch64::LD1Fourv2d_POST,
"ld1",
".2d", 1,
false, 64 },
406 { AArch64::LD1Fourv8b_POST,
"ld1",
".8b", 1,
false, 32 },
407 { AArch64::LD1Fourv4h_POST,
"ld1",
".4h", 1,
false, 32 },
408 { AArch64::LD1Fourv2s_POST,
"ld1",
".2s", 1,
false, 32 },
409 { AArch64::LD1Fourv1d_POST,
"ld1",
".1d", 1,
false, 32 },
410 { AArch64::LD2i8,
"ld2",
".b", 1,
true, 0 },
411 { AArch64::LD2i16,
"ld2",
".h", 1,
true, 0 },
412 { AArch64::LD2i32,
"ld2",
".s", 1,
true, 0 },
413 { AArch64::LD2i64,
"ld2",
".d", 1,
true, 0 },
414 { AArch64::LD2i8_POST,
"ld2",
".b", 2,
true, 2 },
415 { AArch64::LD2i16_POST,
"ld2",
".h", 2,
true, 4 },
416 { AArch64::LD2i32_POST,
"ld2",
".s", 2,
true, 8 },
417 { AArch64::LD2i64_POST,
"ld2",
".d", 2,
true, 16 },
418 { AArch64::LD2Rv16b,
"ld2r",
".16b", 0,
false, 0 },
419 { AArch64::LD2Rv8h,
"ld2r",
".8h", 0,
false, 0 },
420 { AArch64::LD2Rv4s,
"ld2r",
".4s", 0,
false, 0 },
421 { AArch64::LD2Rv2d,
"ld2r",
".2d", 0,
false, 0 },
422 { AArch64::LD2Rv8b,
"ld2r",
".8b", 0,
false, 0 },
423 { AArch64::LD2Rv4h,
"ld2r",
".4h", 0,
false, 0 },
424 { AArch64::LD2Rv2s,
"ld2r",
".2s", 0,
false, 0 },
425 { AArch64::LD2Rv1d,
"ld2r",
".1d", 0,
false, 0 },
426 { AArch64::LD2Rv16b_POST,
"ld2r",
".16b", 1,
false, 2 },
427 { AArch64::LD2Rv8h_POST,
"ld2r",
".8h", 1,
false, 4 },
428 { AArch64::LD2Rv4s_POST,
"ld2r",
".4s", 1,
false, 8 },
429 { AArch64::LD2Rv2d_POST,
"ld2r",
".2d", 1,
false, 16 },
430 { AArch64::LD2Rv8b_POST,
"ld2r",
".8b", 1,
false, 2 },
431 { AArch64::LD2Rv4h_POST,
"ld2r",
".4h", 1,
false, 4 },
432 { AArch64::LD2Rv2s_POST,
"ld2r",
".2s", 1,
false, 8 },
433 { AArch64::LD2Rv1d_POST,
"ld2r",
".1d", 1,
false, 16 },
434 { AArch64::LD2Twov16b,
"ld2",
".16b", 0,
false, 0 },
435 { AArch64::LD2Twov8h,
"ld2",
".8h", 0,
false, 0 },
436 { AArch64::LD2Twov4s,
"ld2",
".4s", 0,
false, 0 },
437 { AArch64::LD2Twov2d,
"ld2",
".2d", 0,
false, 0 },
438 { AArch64::LD2Twov8b,
"ld2",
".8b", 0,
false, 0 },
439 { AArch64::LD2Twov4h,
"ld2",
".4h", 0,
false, 0 },
440 { AArch64::LD2Twov2s,
"ld2",
".2s", 0,
false, 0 },
441 { AArch64::LD2Twov16b_POST,
"ld2",
".16b", 1,
false, 32 },
442 { AArch64::LD2Twov8h_POST,
"ld2",
".8h", 1,
false, 32 },
443 { AArch64::LD2Twov4s_POST,
"ld2",
".4s", 1,
false, 32 },
444 { AArch64::LD2Twov2d_POST,
"ld2",
".2d", 1,
false, 32 },
445 { AArch64::LD2Twov8b_POST,
"ld2",
".8b", 1,
false, 16 },
446 { AArch64::LD2Twov4h_POST,
"ld2",
".4h", 1,
false, 16 },
447 { AArch64::LD2Twov2s_POST,
"ld2",
".2s", 1,
false, 16 },
448 { AArch64::LD3i8,
"ld3",
".b", 1,
true, 0 },
449 { AArch64::LD3i16,
"ld3",
".h", 1,
true, 0 },
450 { AArch64::LD3i32,
"ld3",
".s", 1,
true, 0 },
451 { AArch64::LD3i64,
"ld3",
".d", 1,
true, 0 },
452 { AArch64::LD3i8_POST,
"ld3",
".b", 2,
true, 3 },
453 { AArch64::LD3i16_POST,
"ld3",
".h", 2,
true, 6 },
454 { AArch64::LD3i32_POST,
"ld3",
".s", 2,
true, 12 },
455 { AArch64::LD3i64_POST,
"ld3",
".d", 2,
true, 24 },
456 { AArch64::LD3Rv16b,
"ld3r",
".16b", 0,
false, 0 },
457 { AArch64::LD3Rv8h,
"ld3r",
".8h", 0,
false, 0 },
458 { AArch64::LD3Rv4s,
"ld3r",
".4s", 0,
false, 0 },
459 { AArch64::LD3Rv2d,
"ld3r",
".2d", 0,
false, 0 },
460 { AArch64::LD3Rv8b,
"ld3r",
".8b", 0,
false, 0 },
461 { AArch64::LD3Rv4h,
"ld3r",
".4h", 0,
false, 0 },
462 { AArch64::LD3Rv2s,
"ld3r",
".2s", 0,
false, 0 },
463 { AArch64::LD3Rv1d,
"ld3r",
".1d", 0,
false, 0 },
464 { AArch64::LD3Rv16b_POST,
"ld3r",
".16b", 1,
false, 3 },
465 { AArch64::LD3Rv8h_POST,
"ld3r",
".8h", 1,
false, 6 },
466 { AArch64::LD3Rv4s_POST,
"ld3r",
".4s", 1,
false, 12 },
467 { AArch64::LD3Rv2d_POST,
"ld3r",
".2d", 1,
false, 24 },
468 { AArch64::LD3Rv8b_POST,
"ld3r",
".8b", 1,
false, 3 },
469 { AArch64::LD3Rv4h_POST,
"ld3r",
".4h", 1,
false, 6 },
470 { AArch64::LD3Rv2s_POST,
"ld3r",
".2s", 1,
false, 12 },
471 { AArch64::LD3Rv1d_POST,
"ld3r",
".1d", 1,
false, 24 },
472 { AArch64::LD3Threev16b,
"ld3",
".16b", 0,
false, 0 },
473 { AArch64::LD3Threev8h,
"ld3",
".8h", 0,
false, 0 },
474 { AArch64::LD3Threev4s,
"ld3",
".4s", 0,
false, 0 },
475 { AArch64::LD3Threev2d,
"ld3",
".2d", 0,
false, 0 },
476 { AArch64::LD3Threev8b,
"ld3",
".8b", 0,
false, 0 },
477 { AArch64::LD3Threev4h,
"ld3",
".4h", 0,
false, 0 },
478 { AArch64::LD3Threev2s,
"ld3",
".2s", 0,
false, 0 },
479 { AArch64::LD3Threev16b_POST,
"ld3",
".16b", 1,
false, 48 },
480 { AArch64::LD3Threev8h_POST,
"ld3",
".8h", 1,
false, 48 },
481 { AArch64::LD3Threev4s_POST,
"ld3",
".4s", 1,
false, 48 },
482 { AArch64::LD3Threev2d_POST,
"ld3",
".2d", 1,
false, 48 },
483 { AArch64::LD3Threev8b_POST,
"ld3",
".8b", 1,
false, 24 },
484 { AArch64::LD3Threev4h_POST,
"ld3",
".4h", 1,
false, 24 },
485 { AArch64::LD3Threev2s_POST,
"ld3",
".2s", 1,
false, 24 },
486 { AArch64::LD4i8,
"ld4",
".b", 1,
true, 0 },
487 { AArch64::LD4i16,
"ld4",
".h", 1,
true, 0 },
488 { AArch64::LD4i32,
"ld4",
".s", 1,
true, 0 },
489 { AArch64::LD4i64,
"ld4",
".d", 1,
true, 0 },
490 { AArch64::LD4i8_POST,
"ld4",
".b", 2,
true, 4 },
491 { AArch64::LD4i16_POST,
"ld4",
".h", 2,
true, 8 },
492 { AArch64::LD4i32_POST,
"ld4",
".s", 2,
true, 16 },
493 { AArch64::LD4i64_POST,
"ld4",
".d", 2,
true, 32 },
494 { AArch64::LD4Rv16b,
"ld4r",
".16b", 0,
false, 0 },
495 { AArch64::LD4Rv8h,
"ld4r",
".8h", 0,
false, 0 },
496 { AArch64::LD4Rv4s,
"ld4r",
".4s", 0,
false, 0 },
497 { AArch64::LD4Rv2d,
"ld4r",
".2d", 0,
false, 0 },
498 { AArch64::LD4Rv8b,
"ld4r",
".8b", 0,
false, 0 },
499 { AArch64::LD4Rv4h,
"ld4r",
".4h", 0,
false, 0 },
500 { AArch64::LD4Rv2s,
"ld4r",
".2s", 0,
false, 0 },
501 { AArch64::LD4Rv1d,
"ld4r",
".1d", 0,
false, 0 },
502 { AArch64::LD4Rv16b_POST,
"ld4r",
".16b", 1,
false, 4 },
503 { AArch64::LD4Rv8h_POST,
"ld4r",
".8h", 1,
false, 8 },
504 { AArch64::LD4Rv4s_POST,
"ld4r",
".4s", 1,
false, 16 },
505 { AArch64::LD4Rv2d_POST,
"ld4r",
".2d", 1,
false, 32 },
506 { AArch64::LD4Rv8b_POST,
"ld4r",
".8b", 1,
false, 4 },
507 { AArch64::LD4Rv4h_POST,
"ld4r",
".4h", 1,
false, 8 },
508 { AArch64::LD4Rv2s_POST,
"ld4r",
".2s", 1,
false, 16 },
509 { AArch64::LD4Rv1d_POST,
"ld4r",
".1d", 1,
false, 32 },
510 { AArch64::LD4Fourv16b,
"ld4",
".16b", 0,
false, 0 },
511 { AArch64::LD4Fourv8h,
"ld4",
".8h", 0,
false, 0 },
512 { AArch64::LD4Fourv4s,
"ld4",
".4s", 0,
false, 0 },
513 { AArch64::LD4Fourv2d,
"ld4",
".2d", 0,
false, 0 },
514 { AArch64::LD4Fourv8b,
"ld4",
".8b", 0,
false, 0 },
515 { AArch64::LD4Fourv4h,
"ld4",
".4h", 0,
false, 0 },
516 { AArch64::LD4Fourv2s,
"ld4",
".2s", 0,
false, 0 },
517 { AArch64::LD4Fourv16b_POST,
"ld4",
".16b", 1,
false, 64 },
518 { AArch64::LD4Fourv8h_POST,
"ld4",
".8h", 1,
false, 64 },
519 { AArch64::LD4Fourv4s_POST,
"ld4",
".4s", 1,
false, 64 },
520 { AArch64::LD4Fourv2d_POST,
"ld4",
".2d", 1,
false, 64 },
521 { AArch64::LD4Fourv8b_POST,
"ld4",
".8b", 1,
false, 32 },
522 { AArch64::LD4Fourv4h_POST,
"ld4",
".4h", 1,
false, 32 },
523 { AArch64::LD4Fourv2s_POST,
"ld4",
".2s", 1,
false, 32 },
524 { AArch64::ST1i8,
"st1",
".b", 0,
true, 0 },
525 { AArch64::ST1i16,
"st1",
".h", 0,
true, 0 },
526 { AArch64::ST1i32,
"st1",
".s", 0,
true, 0 },
527 { AArch64::ST1i64,
"st1",
".d", 0,
true, 0 },
528 { AArch64::ST1i8_POST,
"st1",
".b", 1,
true, 1 },
529 { AArch64::ST1i16_POST,
"st1",
".h", 1,
true, 2 },
530 { AArch64::ST1i32_POST,
"st1",
".s", 1,
true, 4 },
531 { AArch64::ST1i64_POST,
"st1",
".d", 1,
true, 8 },
532 { AArch64::ST1Onev16b,
"st1",
".16b", 0,
false, 0 },
533 { AArch64::ST1Onev8h,
"st1",
".8h", 0,
false, 0 },
534 { AArch64::ST1Onev4s,
"st1",
".4s", 0,
false, 0 },
535 { AArch64::ST1Onev2d,
"st1",
".2d", 0,
false, 0 },
536 { AArch64::ST1Onev8b,
"st1",
".8b", 0,
false, 0 },
537 { AArch64::ST1Onev4h,
"st1",
".4h", 0,
false, 0 },
538 { AArch64::ST1Onev2s,
"st1",
".2s", 0,
false, 0 },
539 { AArch64::ST1Onev1d,
"st1",
".1d", 0,
false, 0 },
540 { AArch64::ST1Onev16b_POST,
"st1",
".16b", 1,
false, 16 },
541 { AArch64::ST1Onev8h_POST,
"st1",
".8h", 1,
false, 16 },
542 { AArch64::ST1Onev4s_POST,
"st1",
".4s", 1,
false, 16 },
543 { AArch64::ST1Onev2d_POST,
"st1",
".2d", 1,
false, 16 },
544 { AArch64::ST1Onev8b_POST,
"st1",
".8b", 1,
false, 8 },
545 { AArch64::ST1Onev4h_POST,
"st1",
".4h", 1,
false, 8 },
546 { AArch64::ST1Onev2s_POST,
"st1",
".2s", 1,
false, 8 },
547 { AArch64::ST1Onev1d_POST,
"st1",
".1d", 1,
false, 8 },
548 { AArch64::ST1Twov16b,
"st1",
".16b", 0,
false, 0 },
549 { AArch64::ST1Twov8h,
"st1",
".8h", 0,
false, 0 },
550 { AArch64::ST1Twov4s,
"st1",
".4s", 0,
false, 0 },
551 { AArch64::ST1Twov2d,
"st1",
".2d", 0,
false, 0 },
552 { AArch64::ST1Twov8b,
"st1",
".8b", 0,
false, 0 },
553 { AArch64::ST1Twov4h,
"st1",
".4h", 0,
false, 0 },
554 { AArch64::ST1Twov2s,
"st1",
".2s", 0,
false, 0 },
555 { AArch64::ST1Twov1d,
"st1",
".1d", 0,
false, 0 },
556 { AArch64::ST1Twov16b_POST,
"st1",
".16b", 1,
false, 32 },
557 { AArch64::ST1Twov8h_POST,
"st1",
".8h", 1,
false, 32 },
558 { AArch64::ST1Twov4s_POST,
"st1",
".4s", 1,
false, 32 },
559 { AArch64::ST1Twov2d_POST,
"st1",
".2d", 1,
false, 32 },
560 { AArch64::ST1Twov8b_POST,
"st1",
".8b", 1,
false, 16 },
561 { AArch64::ST1Twov4h_POST,
"st1",
".4h", 1,
false, 16 },
562 { AArch64::ST1Twov2s_POST,
"st1",
".2s", 1,
false, 16 },
563 { AArch64::ST1Twov1d_POST,
"st1",
".1d", 1,
false, 16 },
564 { AArch64::ST1Threev16b,
"st1",
".16b", 0,
false, 0 },
565 { AArch64::ST1Threev8h,
"st1",
".8h", 0,
false, 0 },
566 { AArch64::ST1Threev4s,
"st1",
".4s", 0,
false, 0 },
567 { AArch64::ST1Threev2d,
"st1",
".2d", 0,
false, 0 },
568 { AArch64::ST1Threev8b,
"st1",
".8b", 0,
false, 0 },
569 { AArch64::ST1Threev4h,
"st1",
".4h", 0,
false, 0 },
570 { AArch64::ST1Threev2s,
"st1",
".2s", 0,
false, 0 },
571 { AArch64::ST1Threev1d,
"st1",
".1d", 0,
false, 0 },
572 { AArch64::ST1Threev16b_POST,
"st1",
".16b", 1,
false, 48 },
573 { AArch64::ST1Threev8h_POST,
"st1",
".8h", 1,
false, 48 },
574 { AArch64::ST1Threev4s_POST,
"st1",
".4s", 1,
false, 48 },
575 { AArch64::ST1Threev2d_POST,
"st1",
".2d", 1,
false, 48 },
576 { AArch64::ST1Threev8b_POST,
"st1",
".8b", 1,
false, 24 },
577 { AArch64::ST1Threev4h_POST,
"st1",
".4h", 1,
false, 24 },
578 { AArch64::ST1Threev2s_POST,
"st1",
".2s", 1,
false, 24 },
579 { AArch64::ST1Threev1d_POST,
"st1",
".1d", 1,
false, 24 },
580 { AArch64::ST1Fourv16b,
"st1",
".16b", 0,
false, 0 },
581 { AArch64::ST1Fourv8h,
"st1",
".8h", 0,
false, 0 },
582 { AArch64::ST1Fourv4s,
"st1",
".4s", 0,
false, 0 },
583 { AArch64::ST1Fourv2d,
"st1",
".2d", 0,
false, 0 },
584 { AArch64::ST1Fourv8b,
"st1",
".8b", 0,
false, 0 },
585 { AArch64::ST1Fourv4h,
"st1",
".4h", 0,
false, 0 },
586 { AArch64::ST1Fourv2s,
"st1",
".2s", 0,
false, 0 },
587 { AArch64::ST1Fourv1d,
"st1",
".1d", 0,
false, 0 },
588 { AArch64::ST1Fourv16b_POST,
"st1",
".16b", 1,
false, 64 },
589 { AArch64::ST1Fourv8h_POST,
"st1",
".8h", 1,
false, 64 },
590 { AArch64::ST1Fourv4s_POST,
"st1",
".4s", 1,
false, 64 },
591 { AArch64::ST1Fourv2d_POST,
"st1",
".2d", 1,
false, 64 },
592 { AArch64::ST1Fourv8b_POST,
"st1",
".8b", 1,
false, 32 },
593 { AArch64::ST1Fourv4h_POST,
"st1",
".4h", 1,
false, 32 },
594 { AArch64::ST1Fourv2s_POST,
"st1",
".2s", 1,
false, 32 },
595 { AArch64::ST1Fourv1d_POST,
"st1",
".1d", 1,
false, 32 },
596 { AArch64::ST2i8,
"st2",
".b", 0,
true, 0 },
597 { AArch64::ST2i16,
"st2",
".h", 0,
true, 0 },
598 { AArch64::ST2i32,
"st2",
".s", 0,
true, 0 },
599 { AArch64::ST2i64,
"st2",
".d", 0,
true, 0 },
600 { AArch64::ST2i8_POST,
"st2",
".b", 1,
true, 2 },
601 { AArch64::ST2i16_POST,
"st2",
".h", 1,
true, 4 },
602 { AArch64::ST2i32_POST,
"st2",
".s", 1,
true, 8 },
603 { AArch64::ST2i64_POST,
"st2",
".d", 1,
true, 16 },
604 { AArch64::ST2Twov16b,
"st2",
".16b", 0,
false, 0 },
605 { AArch64::ST2Twov8h,
"st2",
".8h", 0,
false, 0 },
606 { AArch64::ST2Twov4s,
"st2",
".4s", 0,
false, 0 },
607 { AArch64::ST2Twov2d,
"st2",
".2d", 0,
false, 0 },
608 { AArch64::ST2Twov8b,
"st2",
".8b", 0,
false, 0 },
609 { AArch64::ST2Twov4h,
"st2",
".4h", 0,
false, 0 },
610 { AArch64::ST2Twov2s,
"st2",
".2s", 0,
false, 0 },
611 { AArch64::ST2Twov16b_POST,
"st2",
".16b", 1,
false, 32 },
612 { AArch64::ST2Twov8h_POST,
"st2",
".8h", 1,
false, 32 },
613 { AArch64::ST2Twov4s_POST,
"st2",
".4s", 1,
false, 32 },
614 { AArch64::ST2Twov2d_POST,
"st2",
".2d", 1,
false, 32 },
615 { AArch64::ST2Twov8b_POST,
"st2",
".8b", 1,
false, 16 },
616 { AArch64::ST2Twov4h_POST,
"st2",
".4h", 1,
false, 16 },
617 { AArch64::ST2Twov2s_POST,
"st2",
".2s", 1,
false, 16 },
618 { AArch64::ST3i8,
"st3",
".b", 0,
true, 0 },
619 { AArch64::ST3i16,
"st3",
".h", 0,
true, 0 },
620 { AArch64::ST3i32,
"st3",
".s", 0,
true, 0 },
621 { AArch64::ST3i64,
"st3",
".d", 0,
true, 0 },
622 { AArch64::ST3i8_POST,
"st3",
".b", 1,
true, 3 },
623 { AArch64::ST3i16_POST,
"st3",
".h", 1,
true, 6 },
624 { AArch64::ST3i32_POST,
"st3",
".s", 1,
true, 12 },
625 { AArch64::ST3i64_POST,
"st3",
".d", 1,
true, 24 },
626 { AArch64::ST3Threev16b,
"st3",
".16b", 0,
false, 0 },
627 { AArch64::ST3Threev8h,
"st3",
".8h", 0,
false, 0 },
628 { AArch64::ST3Threev4s,
"st3",
".4s", 0,
false, 0 },
629 { AArch64::ST3Threev2d,
"st3",
".2d", 0,
false, 0 },
630 { AArch64::ST3Threev8b,
"st3",
".8b", 0,
false, 0 },
631 { AArch64::ST3Threev4h,
"st3",
".4h", 0,
false, 0 },
632 { AArch64::ST3Threev2s,
"st3",
".2s", 0,
false, 0 },
633 { AArch64::ST3Threev16b_POST,
"st3",
".16b", 1,
false, 48 },
634 { AArch64::ST3Threev8h_POST,
"st3",
".8h", 1,
false, 48 },
635 { AArch64::ST3Threev4s_POST,
"st3",
".4s", 1,
false, 48 },
636 { AArch64::ST3Threev2d_POST,
"st3",
".2d", 1,
false, 48 },
637 { AArch64::ST3Threev8b_POST,
"st3",
".8b", 1,
false, 24 },
638 { AArch64::ST3Threev4h_POST,
"st3",
".4h", 1,
false, 24 },
639 { AArch64::ST3Threev2s_POST,
"st3",
".2s", 1,
false, 24 },
640 { AArch64::ST4i8,
"st4",
".b", 0,
true, 0 },
641 { AArch64::ST4i16,
"st4",
".h", 0,
true, 0 },
642 { AArch64::ST4i32,
"st4",
".s", 0,
true, 0 },
643 { AArch64::ST4i64,
"st4",
".d", 0,
true, 0 },
644 { AArch64::ST4i8_POST,
"st4",
".b", 1,
true, 4 },
645 { AArch64::ST4i16_POST,
"st4",
".h", 1,
true, 8 },
646 { AArch64::ST4i32_POST,
"st4",
".s", 1,
true, 16 },
647 { AArch64::ST4i64_POST,
"st4",
".d", 1,
true, 32 },
648 { AArch64::ST4Fourv16b,
"st4",
".16b", 0,
false, 0 },
649 { AArch64::ST4Fourv8h,
"st4",
".8h", 0,
false, 0 },
650 { AArch64::ST4Fourv4s,
"st4",
".4s", 0,
false, 0 },
651 { AArch64::ST4Fourv2d,
"st4",
".2d", 0,
false, 0 },
652 { AArch64::ST4Fourv8b,
"st4",
".8b", 0,
false, 0 },
653 { AArch64::ST4Fourv4h,
"st4",
".4h", 0,
false, 0 },
654 { AArch64::ST4Fourv2s,
"st4",
".2s", 0,
false, 0 },
655 { AArch64::ST4Fourv16b_POST,
"st4",
".16b", 1,
false, 64 },
656 { AArch64::ST4Fourv8h_POST,
"st4",
".8h", 1,
false, 64 },
657 { AArch64::ST4Fourv4s_POST,
"st4",
".4s", 1,
false, 64 },
658 { AArch64::ST4Fourv2d_POST,
"st4",
".2d", 1,
false, 64 },
659 { AArch64::ST4Fourv8b_POST,
"st4",
".8b", 1,
false, 32 },
660 { AArch64::ST4Fourv4h_POST,
"st4",
".4h", 1,
false, 32 },
661 { AArch64::ST4Fourv2s_POST,
"st4",
".2s", 1,
false, 32 },
681 O <<
"\t" << (IsTbx ?
"tbx" :
"tbl") << Layout <<
'\t'
684 unsigned ListOpNum = IsTbx ? 2 : 1;
694 O <<
"\t" << LdStDesc->Mnemonic << LdStDesc->Layout <<
'\t';
698 int OpNum = LdStDesc->ListOperand;
701 if (LdStDesc->HasLane)
709 if (LdStDesc->NaturalOffset != 0) {
711 if (Reg != AArch64::XZR)
714 assert(LdStDesc->NaturalOffset &&
"no offset on post-inc instruction?");
715 O <<
", #" << LdStDesc->NaturalOffset;
731 assert(Opcode == AArch64::SYSxt &&
"Invalid opcode for SYS alias!");
734 const char *
Asm =
nullptr;
740 unsigned Op1Val = Op1.
getImm();
741 unsigned CnVal = Cn.
getImm();
742 unsigned CmVal = Cm.
getImm();
743 unsigned Op2Val = Op2.
getImm();
752 if (Op1Val == 0 && Op2Val == 0)
756 if (Op1Val == 0 && Op2Val == 0)
758 else if (Op1Val == 3 && Op2Val == 1)
764 if (Op1Val == 3 && Op2Val == 1)
768 if (Op1Val == 0 && Op2Val == 1)
770 if (Op1Val == 0 && Op2Val == 2)
774 if (Op1Val == 3 && Op2Val == 1)
776 else if (Op1Val == 0 && Op2Val == 2)
780 if (Op1Val == 3 && Op2Val == 1)
784 if (Op1Val == 3 && Op2Val == 1 &&
789 if (Op1Val == 3 && Op2Val == 1)
791 else if (Op1Val == 0 && Op2Val == 2)
804 case 0: Asm =
"at\ts1e1r";
break;
805 case 1: Asm =
"at\ts1e1w";
break;
806 case 2: Asm =
"at\ts1e0r";
break;
807 case 3: Asm =
"at\ts1e0w";
break;
814 case 0: Asm =
"at\ts1e2r";
break;
815 case 1: Asm =
"at\ts1e2w";
break;
816 case 4: Asm =
"at\ts12e1r";
break;
817 case 5: Asm =
"at\ts12e1w";
break;
818 case 6: Asm =
"at\ts12e0r";
break;
819 case 7: Asm =
"at\ts12e0w";
break;
826 case 0: Asm =
"at\ts1e3r";
break;
827 case 1: Asm =
"at\ts1e3w";
break;
841 case 0: Asm =
"at\ts1e1rp";
break;
842 case 1: Asm =
"at\ts1e1wp";
break;
848 }
else if (CnVal == 8) {
861 case 0: Asm =
"tlbi\tvmalle1is";
break;
862 case 1: Asm =
"tlbi\tvae1is";
break;
863 case 2: Asm =
"tlbi\taside1is";
break;
864 case 3: Asm =
"tlbi\tvaae1is";
break;
865 case 5: Asm =
"tlbi\tvale1is";
break;
866 case 7: Asm =
"tlbi\tvaale1is";
break;
873 case 0: Asm =
"tlbi\talle2is";
break;
874 case 1: Asm =
"tlbi\tvae2is";
break;
875 case 4: Asm =
"tlbi\talle1is";
break;
876 case 5: Asm =
"tlbi\tvale2is";
break;
877 case 6: Asm =
"tlbi\tvmalls12e1is";
break;
884 case 0: Asm =
"tlbi\talle3is";
break;
885 case 1: Asm =
"tlbi\tvae3is";
break;
886 case 5: Asm =
"tlbi\tvale3is";
break;
899 case 1: Asm =
"tlbi\tipas2e1is";
break;
900 case 5: Asm =
"tlbi\tipas2le1is";
break;
913 case 1: Asm =
"tlbi\tipas2e1";
break;
914 case 5: Asm =
"tlbi\tipas2le1";
break;
927 case 0: Asm =
"tlbi\tvmalle1";
break;
928 case 1: Asm =
"tlbi\tvae1";
break;
929 case 2: Asm =
"tlbi\taside1";
break;
930 case 3: Asm =
"tlbi\tvaae1";
break;
931 case 5: Asm =
"tlbi\tvale1";
break;
932 case 7: Asm =
"tlbi\tvaale1";
break;
939 case 0: Asm =
"tlbi\talle2";
break;
940 case 1: Asm =
"tlbi\tvae2";
break;
941 case 4: Asm =
"tlbi\talle1";
break;
942 case 5: Asm =
"tlbi\tvale2";
break;
943 case 6: Asm =
"tlbi\tvmalls12e1";
break;
950 case 0: Asm =
"tlbi\talle3";
break;
951 case 1: Asm =
"tlbi\tvae3";
break;
952 case 5: Asm =
"tlbi\tvale3";
break;
968 return Asm !=
nullptr;
978 }
else if (Op.
isImm()) {
981 assert(Op.
isExpr() &&
"unknown operand kind in printOperand");
1005 if (Reg == AArch64::XZR)
1017 assert(Op.
isReg() &&
"Non-register vreg operand!");
1026 assert(Op.
isImm() &&
"System instruction C[nm] operands must be immediates!");
1035 unsigned Val = (MO.
getImm() & 0xfff);
1036 assert(Val == MO.
getImm() &&
"Add/sub immediate out of range!");
1107 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1109 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1112 O <<
", lsl #" << ShiftVal;
1118 O <<
" #" << ShiftVal;
1128 bool IsLSL = !SignExtend && SrcRegKind ==
'x';
1132 O << (SignExtend ?
's' :
'u') <<
"xt" << SrcRegKind;
1134 if (DoShift || IsLSL)
1135 O <<
" #" <<
Log2_32(Width / 8);
1194 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1205 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1220 O <<
format(
"#%.8f", FPImm);
1228 case AArch64::Q0: Reg = AArch64::Q1;
break;
1229 case AArch64::Q1: Reg = AArch64::Q2;
break;
1230 case AArch64::Q2: Reg = AArch64::Q3;
break;
1231 case AArch64::Q3: Reg = AArch64::Q4;
break;
1232 case AArch64::Q4: Reg = AArch64::Q5;
break;
1233 case AArch64::Q5: Reg = AArch64::Q6;
break;
1234 case AArch64::Q6: Reg = AArch64::Q7;
break;
1235 case AArch64::Q7: Reg = AArch64::Q8;
break;
1236 case AArch64::Q8: Reg = AArch64::Q9;
break;
1237 case AArch64::Q9: Reg = AArch64::Q10;
break;
1238 case AArch64::Q10: Reg = AArch64::Q11;
break;
1239 case AArch64::Q11: Reg = AArch64::Q12;
break;
1240 case AArch64::Q12: Reg = AArch64::Q13;
break;
1241 case AArch64::Q13: Reg = AArch64::Q14;
break;
1242 case AArch64::Q14: Reg = AArch64::Q15;
break;
1243 case AArch64::Q15: Reg = AArch64::Q16;
break;
1244 case AArch64::Q16: Reg = AArch64::Q17;
break;
1245 case AArch64::Q17: Reg = AArch64::Q18;
break;
1246 case AArch64::Q18: Reg = AArch64::Q19;
break;
1247 case AArch64::Q19: Reg = AArch64::Q20;
break;
1248 case AArch64::Q20: Reg = AArch64::Q21;
break;
1249 case AArch64::Q21: Reg = AArch64::Q22;
break;
1250 case AArch64::Q22: Reg = AArch64::Q23;
break;
1251 case AArch64::Q23: Reg = AArch64::Q24;
break;
1252 case AArch64::Q24: Reg = AArch64::Q25;
break;
1253 case AArch64::Q25: Reg = AArch64::Q26;
break;
1254 case AArch64::Q26: Reg = AArch64::Q27;
break;
1255 case AArch64::Q27: Reg = AArch64::Q28;
break;
1256 case AArch64::Q28: Reg = AArch64::Q29;
break;
1257 case AArch64::Q29: Reg = AArch64::Q30;
break;
1258 case AArch64::Q30: Reg = AArch64::Q31;
break;
1268 template<
unsigned size>
1273 static_assert(size == 64 || size == 32,
1274 "Template parameter must be either 32 or 64");
1277 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1278 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1295 unsigned NumRegs = 1;
1307 if (
unsigned FirstReg =
MRI.
getSubReg(Reg, AArch64::dsub0))
1309 else if (
unsigned FirstReg =
MRI.
getSubReg(Reg, AArch64::qsub0))
1322 if (
i + 1 != NumRegs)
1337 template <
unsigned NumLanes,
char LaneKind>
1341 std::string Suffix(
".");
1343 Suffix +=
itostr(NumLanes) + LaneKind;
1404 if (Opcode == AArch64::ISB) {
1405 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1406 Name = ISB ? ISB->Name :
"";
1408 auto DB = AArch64DB::lookupDBByEncoding(Val);
1409 Name = DB ? DB->Name :
"";
1425 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1426 O <<
"DBGDTRRX_EL0";
1445 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1446 O <<
"DBGDTRTX_EL0";
1462 auto PState = AArch64PState::lookupPStateByEncoding(Val);
1474 O <<
format(
"#%#016llx", Val);
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
static float getFPImmFloat(unsigned Imm)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const LdStNInstrDesc LdStNInstInfo[]
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static CondCode getInvertedCondCode(CondCode Code)
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printLogicalImm32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
void printLogicalImm64(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
Reg
All possible values of the reg field in the ModR/M byte.
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getCondCodeName(CondCode Code)
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride=1)
unsigned getReg() const
Returns the register number.
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
void printAlignedLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
MCRegisterClass - Base class of TargetRegisterClass.
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
Instances of this class represent a single low-level machine instruction.
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
static unsigned getWRegFromXReg(unsigned Reg)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
This class is intended to be used as a base class for asm properties and features specific to the tar...
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
Interface to description of machine instruction set.
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static std::string itostr(int64_t X)
void printAdrpLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
bool haveFeatures(FeatureBitset ActiveFeatures) const
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
unsigned getOpcode() const
std::string genericRegisterString(uint32_t Bits)
virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
MCSubtargetInfo - Generic base class for all target subtargets.
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const SysReg * lookupSysRegByEncoding(uint16_t)
This class implements an extremely fast bulk output stream that can only output to a stream...
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
StringRef - Represent a constant reference to a string, i.e.
Instances of this class represent operands of the MCInst class.
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
const MCRegisterInfo & MRI
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)