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LLVM
4.0.0
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Define some predicates that are used for node matching. More...
Functions | |
| Predicate | InvertPredicate (Predicate Opcode) |
| Invert the specified predicate. != -> ==, < -> >=. More... | |
| Predicate | getSwappedPredicate (Predicate Opcode) |
| Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a). More... | |
| int | getNonRecordFormOpcode (uint16_t) |
| bool | isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction. More... | |
| bool | isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction. More... | |
| bool | isVPKUDUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction. More... | |
| bool | isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes). More... | |
| bool | isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes). More... | |
| bool | isVMRGEOShuffleMask (ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction More... | |
| int | isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) |
| isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1. More... | |
| bool | isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize) |
| isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW. More... | |
| bool | isXXINSERTWMask (ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE) |
| isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0. More... | |
| unsigned | getVSPLTImmediate (SDNode *N, unsigned EltSize, SelectionDAG &DAG) |
| getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask. More... | |
| SDValue | get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG) |
| get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted. More... | |
| int | isQVALIGNIShuffleMask (SDNode *N) |
| If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1. More... | |
| FastISel * | createFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) |
| int | getAltVSXFMAOpcode (uint16_t Opcode) |
Define some predicates that are used for node matching.
| anonymous enum |
Definition at line 38 of file PPCSubtarget.h.
| Enumerator | |
|---|---|
| BR_NO_HINT | |
| BR_NONTAKEN_HINT | |
| BR_TAKEN_HINT | |
| BR_HINT_MASK | |
Definition at line 60 of file PPCPredicates.h.
| enum llvm::PPC::Fixups |
Definition at line 19 of file PPCFixupKinds.h.
| enum llvm::PPC::Predicate |
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition at line 27 of file PPCPredicates.h.
| FastISel * llvm::PPC::createFastISel | ( | FunctionLoweringInfo & | FuncInfo, |
| const TargetLibraryInfo * | LibInfo | ||
| ) |
Definition at line 2366 of file PPCFastISel.cpp.
References llvm::MachineFunction::getSubtarget(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isSVR4ABI(), and llvm::FunctionLoweringInfo::MF.
Referenced by llvm::PPCTargetLowering::createFastISel().
| SDValue llvm::PPC::get_VSPLTI_elt | ( | SDNode * | N, |
| unsigned | ByteSize, | ||
| SelectionDAG & | DAG | ||
| ) |
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted.
The ByteSize field indicates the number of bytes of each element [124] -> [bhw].
Definition at line 1627 of file PPCISelLowering.cpp.
References assert(), llvm::MVT::f32, llvm::FloatToBits(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), i, llvm::MVT::i32, llvm::isAllOnesConstant(), llvm::isNullConstant(), isSplat(), llvm::SDValue::isUndef(), and llvm::SignExtend32().
| int llvm::PPC::getAltVSXFMAOpcode | ( | uint16_t | Opcode | ) |
Referenced by llvm::PPCInstrInfo::findCommutedOpIndices().
| int llvm::PPC::getNonRecordFormOpcode | ( | uint16_t | ) |
Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a).
Referenced by llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::ICmpInst::swapOperands().
| unsigned llvm::PPC::getVSPLTImmediate | ( | SDNode * | N, |
| unsigned | EltSize, | ||
| SelectionDAG & | DAG | ||
| ) |
getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask.
Definition at line 1613 of file PPCISelLowering.cpp.
References assert(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::DataLayout::isLittleEndian(), isSplatShuffleMask(), and N.
Invert the specified predicate. != -> ==, < -> >=.
Referenced by llvm::PPCInstrInfo::reverseBranchCondition().
| int llvm::PPC::isQVALIGNIShuffleMask | ( | SDNode * | N | ) |
If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1.
isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1.
Definition at line 1730 of file PPCISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), i, isConstantOrUndef(), N, llvm::MVT::v4f32, llvm::MVT::v4f64, and llvm::MVT::v4i1.
| bool llvm::PPC::isSplatShuffleMask | ( | ShuffleVectorSDNode * | N, |
| unsigned | EltSize | ||
| ) |
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.
Definition at line 1494 of file PPCISelLowering.cpp.
References assert(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), i, and llvm::MVT::v16i8.
Referenced by getVSPLTImmediate().
| bool llvm::PPC::isVMRGEOShuffleMask | ( | ShuffleVectorSDNode * | N, |
| bool | CheckEven, | ||
| unsigned | ShuffleKind, | ||
| SelectionDAG & | DAG | ||
| ) |
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instruction
Determine if the specified shuffle mask is suitable for the vmrgew or vmrgow instructions.
| [in] | N | The shuffle vector SD Node to analyze |
| [in] | CheckEven | Check for an even merge (true) or an odd merge (false) |
| [in] | ShuffleKind | Identify the type of merge:
|
| [in] | DAG | The current SelectionDAG |
Definition at line 1421 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().
| bool llvm::PPC::isVMRGHShuffleMask | ( | ShuffleVectorSDNode * | N, |
| unsigned | UnitSize, | ||
| unsigned | ShuffleKind, | ||
| SelectionDAG & | DAG | ||
| ) |
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1331 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().
| bool llvm::PPC::isVMRGLShuffleMask | ( | ShuffleVectorSDNode * | N, |
| unsigned | UnitSize, | ||
| unsigned | ShuffleKind, | ||
| SelectionDAG & | DAG | ||
| ) |
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1306 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::isLittleEndian(), and isVMerge().
| bool llvm::PPC::isVPKUDUMShuffleMask | ( | ShuffleVectorSDNode * | N, |
| unsigned | ShuffleKind, | ||
| SelectionDAG & | DAG | ||
| ) |
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction, AND the VPKUDUM instruction exists for the current subtarget.
The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1238 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getSubtarget(), llvm::PPCSubtarget::hasP8Vector(), i, isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().
| bool llvm::PPC::isVPKUHUMShuffleMask | ( | ShuffleVectorSDNode * | N, |
| unsigned | ShuffleKind, | ||
| SelectionDAG & | DAG | ||
| ) |
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1170 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), i, isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().
| bool llvm::PPC::isVPKUWUMShuffleMask | ( | ShuffleVectorSDNode * | N, |
| unsigned | ShuffleKind, | ||
| SelectionDAG & | DAG | ||
| ) |
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1201 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), i, isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().
| int llvm::PPC::isVSLDOIShuffleMask | ( | SDNode * | N, |
| unsigned | ShuffleKind, | ||
| SelectionDAG & | DAG | ||
| ) |
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).
Definition at line 1450 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), i, isConstantOrUndef(), llvm::DataLayout::isLittleEndian(), N, and llvm::MVT::v16i8.
| bool llvm::PPC::isXXINSERTWMask | ( | ShuffleVectorSDNode * | N, |
| unsigned & | ShiftElts, | ||
| unsigned & | InsertAtByte, | ||
| bool & | Swap, | ||
| bool | IsLE | ||
| ) |
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction introduced in ISA 3.0.
This is essentially any shuffle of v4f32/v4i32 vectors that just inserts one element from one vector into the other. This function will also set a couple of output parameters for how much the source vector needs to be shifted and what byte number needs to be specified for the instruction to put the element in the desired location of the target vector.
Definition at line 1526 of file PPCISelLowering.cpp.
References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getOperand(), i, and llvm::SDValue::isUndef().
1.8.6