LLVM  4.0.0
MachineInstr.cpp
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1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Methods common to all machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/InlineAsm.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/IR/Metadata.h"
32 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/IR/Value.h"
36 #include "llvm/MC/MCInstrDesc.h"
37 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/Debug.h"
48 using namespace llvm;
49 
51  "print-whole-regmask",
52  cl::desc("Print the full contents of regmask operands in IR dumps"),
53  cl::init(true), cl::Hidden);
54 
55 //===----------------------------------------------------------------------===//
56 // MachineOperand Implementation
57 //===----------------------------------------------------------------------===//
58 
59 void MachineOperand::setReg(unsigned Reg) {
60  if (getReg() == Reg) return; // No change.
61 
62  // Otherwise, we have to change the register. If this operand is embedded
63  // into a machine function, we need to update the old and new register's
64  // use/def lists.
65  if (MachineInstr *MI = getParent())
66  if (MachineBasicBlock *MBB = MI->getParent())
67  if (MachineFunction *MF = MBB->getParent()) {
68  MachineRegisterInfo &MRI = MF->getRegInfo();
70  SmallContents.RegNo = Reg;
71  MRI.addRegOperandToUseList(this);
72  return;
73  }
74 
75  // Otherwise, just change the register, no problem. :)
76  SmallContents.RegNo = Reg;
77 }
78 
79 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
80  const TargetRegisterInfo &TRI) {
82  if (SubIdx && getSubReg())
83  SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
84  setReg(Reg);
85  if (SubIdx)
86  setSubReg(SubIdx);
87 }
88 
91  if (getSubReg()) {
92  Reg = TRI.getSubReg(Reg, getSubReg());
93  // Note that getSubReg() may return 0 if the sub-register doesn't exist.
94  // That won't happen in legal code.
95  setSubReg(0);
96  if (isDef())
97  setIsUndef(false);
98  }
99  setReg(Reg);
100 }
101 
102 /// Change a def to a use, or a use to a def.
103 void MachineOperand::setIsDef(bool Val) {
104  assert(isReg() && "Wrong MachineOperand accessor");
105  assert((!Val || !isDebug()) && "Marking a debug operation as def");
106  if (IsDef == Val)
107  return;
108  // MRI may keep uses and defs in different list positions.
109  if (MachineInstr *MI = getParent())
110  if (MachineBasicBlock *MBB = MI->getParent())
111  if (MachineFunction *MF = MBB->getParent()) {
112  MachineRegisterInfo &MRI = MF->getRegInfo();
113  MRI.removeRegOperandFromUseList(this);
114  IsDef = Val;
115  MRI.addRegOperandToUseList(this);
116  return;
117  }
118  IsDef = Val;
119 }
120 
121 // If this operand is currently a register operand, and if this is in a
122 // function, deregister the operand from the register's use/def list.
123 void MachineOperand::removeRegFromUses() {
124  if (!isReg() || !isOnRegUseList())
125  return;
126 
127  if (MachineInstr *MI = getParent()) {
128  if (MachineBasicBlock *MBB = MI->getParent()) {
129  if (MachineFunction *MF = MBB->getParent())
130  MF->getRegInfo().removeRegOperandFromUseList(this);
131  }
132  }
133 }
134 
135 /// ChangeToImmediate - Replace this operand with a new immediate operand of
136 /// the specified value. If an operand is known to be an immediate already,
137 /// the setImm method should be used.
138 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
139  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
140 
141  removeRegFromUses();
142 
143  OpKind = MO_Immediate;
144  Contents.ImmVal = ImmVal;
145 }
146 
148  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
149 
150  removeRegFromUses();
151 
152  OpKind = MO_FPImmediate;
153  Contents.CFP = FPImm;
154 }
155 
156 void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
157  assert((!isReg() || !isTied()) &&
158  "Cannot change a tied operand into an external symbol");
159 
160  removeRegFromUses();
161 
162  OpKind = MO_ExternalSymbol;
163  Contents.OffsetedInfo.Val.SymbolName = SymName;
164  setOffset(0); // Offset is always 0.
165  setTargetFlags(TargetFlags);
166 }
167 
169  assert((!isReg() || !isTied()) &&
170  "Cannot change a tied operand into an MCSymbol");
171 
172  removeRegFromUses();
173 
174  OpKind = MO_MCSymbol;
175  Contents.Sym = Sym;
176 }
177 
179  assert((!isReg() || !isTied()) &&
180  "Cannot change a tied operand into a FrameIndex");
181 
182  removeRegFromUses();
183 
184  OpKind = MO_FrameIndex;
185  setIndex(Idx);
186 }
187 
188 /// ChangeToRegister - Replace this operand with a new register operand of
189 /// the specified value. If an operand is known to be an register already,
190 /// the setReg method should be used.
191 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
192  bool isKill, bool isDead, bool isUndef,
193  bool isDebug) {
194  MachineRegisterInfo *RegInfo = nullptr;
195  if (MachineInstr *MI = getParent())
196  if (MachineBasicBlock *MBB = MI->getParent())
197  if (MachineFunction *MF = MBB->getParent())
198  RegInfo = &MF->getRegInfo();
199  // If this operand is already a register operand, remove it from the
200  // register's use/def lists.
201  bool WasReg = isReg();
202  if (RegInfo && WasReg)
203  RegInfo->removeRegOperandFromUseList(this);
204 
205  // Change this to a register and set the reg#.
206  OpKind = MO_Register;
207  SmallContents.RegNo = Reg;
208  SubReg_TargetFlags = 0;
209  IsDef = isDef;
210  IsImp = isImp;
211  IsKill = isKill;
212  IsDead = isDead;
213  IsUndef = isUndef;
214  IsInternalRead = false;
215  IsEarlyClobber = false;
216  IsDebug = isDebug;
217  // Ensure isOnRegUseList() returns false.
218  Contents.Reg.Prev = nullptr;
219  // Preserve the tie when the operand was already a register.
220  if (!WasReg)
221  TiedTo = 0;
222 
223  // If this operand is embedded in a function, add the operand to the
224  // register's use/def list.
225  if (RegInfo)
226  RegInfo->addRegOperandToUseList(this);
227 }
228 
229 /// isIdenticalTo - Return true if this operand is identical to the specified
230 /// operand. Note that this should stay in sync with the hash_value overload
231 /// below.
233  if (getType() != Other.getType() ||
234  getTargetFlags() != Other.getTargetFlags())
235  return false;
236 
237  switch (getType()) {
239  return getReg() == Other.getReg() && isDef() == Other.isDef() &&
240  getSubReg() == Other.getSubReg();
242  return getImm() == Other.getImm();
244  return getCImm() == Other.getCImm();
246  return getFPImm() == Other.getFPImm();
248  return getMBB() == Other.getMBB();
250  return getIndex() == Other.getIndex();
253  return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
255  return getIndex() == Other.getIndex();
257  return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
259  return !strcmp(getSymbolName(), Other.getSymbolName()) &&
260  getOffset() == Other.getOffset();
262  return getBlockAddress() == Other.getBlockAddress() &&
263  getOffset() == Other.getOffset();
266  return getRegMask() == Other.getRegMask();
268  return getMCSymbol() == Other.getMCSymbol();
270  return getCFIIndex() == Other.getCFIIndex();
272  return getMetadata() == Other.getMetadata();
274  return getIntrinsicID() == Other.getIntrinsicID();
276  return getPredicate() == Other.getPredicate();
277  }
278  llvm_unreachable("Invalid machine operand type");
279 }
280 
281 // Note: this must stay exactly in sync with isIdenticalTo above.
283  switch (MO.getType()) {
285  // Register operands don't have target flags.
286  return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
288  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
290  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
292  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
294  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
296  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
299  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
300  MO.getOffset());
302  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
304  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
305  MO.getSymbolName());
307  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
308  MO.getOffset());
310  return hash_combine(MO.getType(), MO.getTargetFlags(),
311  MO.getBlockAddress(), MO.getOffset());
314  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
316  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
318  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
320  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
322  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
324  return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
325  }
326  llvm_unreachable("Invalid machine operand type");
327 }
328 
330  const TargetIntrinsicInfo *IntrinsicInfo) const {
331  ModuleSlotTracker DummyMST(nullptr);
332  print(OS, DummyMST, TRI, IntrinsicInfo);
333 }
334 
336  const TargetRegisterInfo *TRI,
337  const TargetIntrinsicInfo *IntrinsicInfo) const {
338  switch (getType()) {
340  OS << PrintReg(getReg(), TRI, getSubReg());
341 
342  if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
343  isInternalRead() || isEarlyClobber() || isTied()) {
344  OS << '<';
345  bool NeedComma = false;
346  if (isDef()) {
347  if (NeedComma) OS << ',';
348  if (isEarlyClobber())
349  OS << "earlyclobber,";
350  if (isImplicit())
351  OS << "imp-";
352  OS << "def";
353  NeedComma = true;
354  // <def,read-undef> only makes sense when getSubReg() is set.
355  // Don't clutter the output otherwise.
356  if (isUndef() && getSubReg())
357  OS << ",read-undef";
358  } else if (isImplicit()) {
359  OS << "imp-use";
360  NeedComma = true;
361  }
362 
363  if (isKill()) {
364  if (NeedComma) OS << ',';
365  OS << "kill";
366  NeedComma = true;
367  }
368  if (isDead()) {
369  if (NeedComma) OS << ',';
370  OS << "dead";
371  NeedComma = true;
372  }
373  if (isUndef() && isUse()) {
374  if (NeedComma) OS << ',';
375  OS << "undef";
376  NeedComma = true;
377  }
378  if (isInternalRead()) {
379  if (NeedComma) OS << ',';
380  OS << "internal";
381  NeedComma = true;
382  }
383  if (isTied()) {
384  if (NeedComma) OS << ',';
385  OS << "tied";
386  if (TiedTo != 15)
387  OS << unsigned(TiedTo - 1);
388  }
389  OS << '>';
390  }
391  break;
392  case MachineOperand::MO_Immediate:
393  OS << getImm();
394  break;
395  case MachineOperand::MO_CImmediate:
396  getCImm()->getValue().print(OS, false);
397  break;
398  case MachineOperand::MO_FPImmediate:
399  if (getFPImm()->getType()->isFloatTy()) {
400  OS << getFPImm()->getValueAPF().convertToFloat();
401  } else if (getFPImm()->getType()->isHalfTy()) {
402  APFloat APF = getFPImm()->getValueAPF();
403  bool Unused;
404  APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
405  OS << "half " << APF.convertToFloat();
406  } else {
407  OS << getFPImm()->getValueAPF().convertToDouble();
408  }
409  break;
410  case MachineOperand::MO_MachineBasicBlock:
411  OS << "<BB#" << getMBB()->getNumber() << ">";
412  break;
413  case MachineOperand::MO_FrameIndex:
414  OS << "<fi#" << getIndex() << '>';
415  break;
416  case MachineOperand::MO_ConstantPoolIndex:
417  OS << "<cp#" << getIndex();
418  if (getOffset()) OS << "+" << getOffset();
419  OS << '>';
420  break;
421  case MachineOperand::MO_TargetIndex:
422  OS << "<ti#" << getIndex();
423  if (getOffset()) OS << "+" << getOffset();
424  OS << '>';
425  break;
426  case MachineOperand::MO_JumpTableIndex:
427  OS << "<jt#" << getIndex() << '>';
428  break;
429  case MachineOperand::MO_GlobalAddress:
430  OS << "<ga:";
431  getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
432  if (getOffset()) OS << "+" << getOffset();
433  OS << '>';
434  break;
435  case MachineOperand::MO_ExternalSymbol:
436  OS << "<es:" << getSymbolName();
437  if (getOffset()) OS << "+" << getOffset();
438  OS << '>';
439  break;
440  case MachineOperand::MO_BlockAddress:
441  OS << '<';
442  getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
443  if (getOffset()) OS << "+" << getOffset();
444  OS << '>';
445  break;
446  case MachineOperand::MO_RegisterMask: {
447  unsigned NumRegsInMask = 0;
448  unsigned NumRegsEmitted = 0;
449  OS << "<regmask";
450  for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
451  unsigned MaskWord = i / 32;
452  unsigned MaskBit = i % 32;
453  if (getRegMask()[MaskWord] & (1 << MaskBit)) {
454  if (PrintWholeRegMask || NumRegsEmitted <= 10) {
455  OS << " " << PrintReg(i, TRI);
456  NumRegsEmitted++;
457  }
458  NumRegsInMask++;
459  }
460  }
461  if (NumRegsEmitted != NumRegsInMask)
462  OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
463  OS << ">";
464  break;
465  }
466  case MachineOperand::MO_RegisterLiveOut:
467  OS << "<regliveout>";
468  break;
469  case MachineOperand::MO_Metadata:
470  OS << '<';
471  getMetadata()->printAsOperand(OS, MST);
472  OS << '>';
473  break;
474  case MachineOperand::MO_MCSymbol:
475  OS << "<MCSym=" << *getMCSymbol() << '>';
476  break;
477  case MachineOperand::MO_CFIIndex:
478  OS << "<call frame instruction>";
479  break;
480  case MachineOperand::MO_IntrinsicID: {
481  Intrinsic::ID ID = getIntrinsicID();
482  if (ID < Intrinsic::num_intrinsics)
483  OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>';
484  else if (IntrinsicInfo)
485  OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>';
486  else
487  OS << "<intrinsic:" << ID << '>';
488  break;
489  }
490  case MachineOperand::MO_Predicate: {
491  auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
492  OS << '<' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
493  << CmpInst::getPredicateName(Pred) << '>';
494  }
495  }
496  if (unsigned TF = getTargetFlags())
497  OS << "[TF=" << TF << ']';
498 }
499 
500 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
501 LLVM_DUMP_METHOD void MachineOperand::dump() const {
502  dbgs() << *this << '\n';
503 }
504 #endif
505 
506 //===----------------------------------------------------------------------===//
507 // MachineMemOperand Implementation
508 //===----------------------------------------------------------------------===//
509 
510 /// getAddrSpace - Return the LLVM IR address space number that this pointer
511 /// points into.
512 unsigned MachinePointerInfo::getAddrSpace() const {
513  if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
514  return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
515 }
516 
517 /// getConstantPool - Return a MachinePointerInfo record that refers to the
518 /// constant pool.
519 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
520  return MachinePointerInfo(MF.getPSVManager().getConstantPool());
521 }
522 
523 /// getFixedStack - Return a MachinePointerInfo record that refers to the
524 /// the specified FrameIndex.
525 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
526  int FI, int64_t Offset) {
527  return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
528 }
529 
530 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
531  return MachinePointerInfo(MF.getPSVManager().getJumpTable());
532 }
533 
534 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
535  return MachinePointerInfo(MF.getPSVManager().getGOT());
536 }
537 
538 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
539  int64_t Offset) {
540  return MachinePointerInfo(MF.getPSVManager().getStack(), Offset);
541 }
542 
543 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
544  uint64_t s, unsigned int a,
545  const AAMDNodes &AAInfo,
546  const MDNode *Ranges,
547  SynchronizationScope SynchScope,
548  AtomicOrdering Ordering,
549  AtomicOrdering FailureOrdering)
550  : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
551  AAInfo(AAInfo), Ranges(Ranges) {
552  assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
553  isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
554  "invalid pointer value");
555  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
556  assert((isLoad() || isStore()) && "Not a load/store!");
557 
558  AtomicInfo.SynchScope = static_cast<unsigned>(SynchScope);
559  assert(getSynchScope() == SynchScope && "Value truncated");
560  AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
561  assert(getOrdering() == Ordering && "Value truncated");
562  AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
563  assert(getFailureOrdering() == FailureOrdering && "Value truncated");
564 }
565 
566 /// Profile - Gather unique data for the object.
567 ///
568 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
569  ID.AddInteger(getOffset());
570  ID.AddInteger(Size);
571  ID.AddPointer(getOpaqueValue());
572  ID.AddInteger(getFlags());
573  ID.AddInteger(getBaseAlignment());
574 }
575 
576 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
577  // The Value and Offset may differ due to CSE. But the flags and size
578  // should be the same.
579  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
580  assert(MMO->getSize() == getSize() && "Size mismatch!");
581 
582  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
583  // Update the alignment value.
584  BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
585  // Also update the base and offset, because the new alignment may
586  // not be applicable with the old ones.
587  PtrInfo = MMO->PtrInfo;
588  }
589 }
590 
591 /// getAlignment - Return the minimum known alignment in bytes of the
592 /// actual memory reference.
593 uint64_t MachineMemOperand::getAlignment() const {
594  return MinAlign(getBaseAlignment(), getOffset());
595 }
596 
597 void MachineMemOperand::print(raw_ostream &OS) const {
598  ModuleSlotTracker DummyMST(nullptr);
599  print(OS, DummyMST);
600 }
601 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
602  assert((isLoad() || isStore()) &&
603  "SV has to be a load, store or both.");
604 
605  if (isVolatile())
606  OS << "Volatile ";
607 
608  if (isLoad())
609  OS << "LD";
610  if (isStore())
611  OS << "ST";
612  OS << getSize();
613 
614  // Print the address information.
615  OS << "[";
616  if (const Value *V = getValue())
617  V->printAsOperand(OS, /*PrintType=*/false, MST);
618  else if (const PseudoSourceValue *PSV = getPseudoValue())
619  PSV->printCustom(OS);
620  else
621  OS << "<unknown>";
622 
623  unsigned AS = getAddrSpace();
624  if (AS != 0)
625  OS << "(addrspace=" << AS << ')';
626 
627  // If the alignment of the memory reference itself differs from the alignment
628  // of the base pointer, print the base alignment explicitly, next to the base
629  // pointer.
630  if (getBaseAlignment() != getAlignment())
631  OS << "(align=" << getBaseAlignment() << ")";
632 
633  if (getOffset() != 0)
634  OS << "+" << getOffset();
635  OS << "]";
636 
637  // Print the alignment of the reference.
638  if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
639  OS << "(align=" << getAlignment() << ")";
640 
641  // Print TBAA info.
642  if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
643  OS << "(tbaa=";
644  if (TBAAInfo->getNumOperands() > 0)
645  TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
646  else
647  OS << "<unknown>";
648  OS << ")";
649  }
650 
651  // Print AA scope info.
652  if (const MDNode *ScopeInfo = getAAInfo().Scope) {
653  OS << "(alias.scope=";
654  if (ScopeInfo->getNumOperands() > 0)
655  for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
656  ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
657  if (i != ie-1)
658  OS << ",";
659  }
660  else
661  OS << "<unknown>";
662  OS << ")";
663  }
664 
665  // Print AA noalias scope info.
666  if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
667  OS << "(noalias=";
668  if (NoAliasInfo->getNumOperands() > 0)
669  for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
670  NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
671  if (i != ie-1)
672  OS << ",";
673  }
674  else
675  OS << "<unknown>";
676  OS << ")";
677  }
678 
679  if (isNonTemporal())
680  OS << "(nontemporal)";
681  if (isDereferenceable())
682  OS << "(dereferenceable)";
683  if (isInvariant())
684  OS << "(invariant)";
685 }
686 
687 //===----------------------------------------------------------------------===//
688 // MachineInstr Implementation
689 //===----------------------------------------------------------------------===//
690 
691 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
692  if (MCID->ImplicitDefs)
693  for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
694  ++ImpDefs)
695  addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
696  if (MCID->ImplicitUses)
697  for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
698  ++ImpUses)
699  addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
700 }
701 
702 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
703 /// implicit operands. It reserves space for the number of operands specified by
704 /// the MCInstrDesc.
705 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
706  DebugLoc dl, bool NoImp)
707  : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
708  AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
709  debugLoc(std::move(dl)) {
710  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
711 
712  // Reserve space for the expected number of operands.
713  if (unsigned NumOps = MCID->getNumOperands() +
714  MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
715  CapOperands = OperandCapacity::get(NumOps);
716  Operands = MF.allocateOperandArray(CapOperands);
717  }
718 
719  if (!NoImp)
720  addImplicitDefUseOperands(MF);
721 }
722 
723 /// MachineInstr ctor - Copies MachineInstr arg exactly
724 ///
725 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
726  : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
727  Flags(0), AsmPrinterFlags(0), NumMemRefs(MI.NumMemRefs),
728  MemRefs(MI.MemRefs), debugLoc(MI.getDebugLoc()) {
729  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
730 
731  CapOperands = OperandCapacity::get(MI.getNumOperands());
732  Operands = MF.allocateOperandArray(CapOperands);
733 
734  // Copy operands.
735  for (const MachineOperand &MO : MI.operands())
736  addOperand(MF, MO);
737 
738  // Copy all the sensible flags.
739  setFlags(MI.Flags);
740 }
741 
742 /// getRegInfo - If this instruction is embedded into a MachineFunction,
743 /// return the MachineRegisterInfo object for the current function, otherwise
744 /// return null.
745 MachineRegisterInfo *MachineInstr::getRegInfo() {
746  if (MachineBasicBlock *MBB = getParent())
747  return &MBB->getParent()->getRegInfo();
748  return nullptr;
749 }
750 
751 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
752 /// this instruction from their respective use lists. This requires that the
753 /// operands already be on their use lists.
754 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
755  for (MachineOperand &MO : operands())
756  if (MO.isReg())
757  MRI.removeRegOperandFromUseList(&MO);
758 }
759 
760 /// AddRegOperandsToUseLists - Add all of the register operands in
761 /// this instruction from their respective use lists. This requires that the
762 /// operands not be on their use lists yet.
763 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
764  for (MachineOperand &MO : operands())
765  if (MO.isReg())
766  MRI.addRegOperandToUseList(&MO);
767 }
768 
769 void MachineInstr::addOperand(const MachineOperand &Op) {
770  MachineBasicBlock *MBB = getParent();
771  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
772  MachineFunction *MF = MBB->getParent();
773  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
774  addOperand(*MF, Op);
775 }
776 
777 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
778 /// ranges. If MRI is non-null also update use-def chains.
779 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
780  unsigned NumOps, MachineRegisterInfo *MRI) {
781  if (MRI)
782  return MRI->moveOperands(Dst, Src, NumOps);
783 
784  // MachineOperand is a trivially copyable type so we can just use memmove.
785  std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
786 }
787 
788 /// addOperand - Add the specified operand to the instruction. If it is an
789 /// implicit operand, it is added to the end of the operand list. If it is
790 /// an explicit operand it is added at the end of the explicit operand list
791 /// (before the first implicit operand).
792 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
793  assert(MCID && "Cannot add operands before providing an instr descriptor");
794 
795  // Check if we're adding one of our existing operands.
796  if (&Op >= Operands && &Op < Operands + NumOperands) {
797  // This is unusual: MI->addOperand(MI->getOperand(i)).
798  // If adding Op requires reallocating or moving existing operands around,
799  // the Op reference could go stale. Support it by copying Op.
800  MachineOperand CopyOp(Op);
801  return addOperand(MF, CopyOp);
802  }
803 
804  // Find the insert location for the new operand. Implicit registers go at
805  // the end, everything else goes before the implicit regs.
806  //
807  // FIXME: Allow mixed explicit and implicit operands on inline asm.
808  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
809  // implicit-defs, but they must not be moved around. See the FIXME in
810  // InstrEmitter.cpp.
811  unsigned OpNo = getNumOperands();
812  bool isImpReg = Op.isReg() && Op.isImplicit();
813  if (!isImpReg && !isInlineAsm()) {
814  while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
815  --OpNo;
816  assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
817  }
818  }
819 
820 #ifndef NDEBUG
821  bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
822  // OpNo now points as the desired insertion point. Unless this is a variadic
823  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
824  // RegMask operands go between the explicit and implicit operands.
825  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
826  OpNo < MCID->getNumOperands() || isMetaDataOp) &&
827  "Trying to add an operand to a machine instr that is already done!");
828 #endif
829 
830  MachineRegisterInfo *MRI = getRegInfo();
831 
832  // Determine if the Operands array needs to be reallocated.
833  // Save the old capacity and operand array.
834  OperandCapacity OldCap = CapOperands;
835  MachineOperand *OldOperands = Operands;
836  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
837  CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
838  Operands = MF.allocateOperandArray(CapOperands);
839  // Move the operands before the insertion point.
840  if (OpNo)
841  moveOperands(Operands, OldOperands, OpNo, MRI);
842  }
843 
844  // Move the operands following the insertion point.
845  if (OpNo != NumOperands)
846  moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
847  MRI);
848  ++NumOperands;
849 
850  // Deallocate the old operand array.
851  if (OldOperands != Operands && OldOperands)
852  MF.deallocateOperandArray(OldCap, OldOperands);
853 
854  // Copy Op into place. It still needs to be inserted into the MRI use lists.
855  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
856  NewMO->ParentMI = this;
857 
858  // When adding a register operand, tell MRI about it.
859  if (NewMO->isReg()) {
860  // Ensure isOnRegUseList() returns false, regardless of Op's status.
861  NewMO->Contents.Reg.Prev = nullptr;
862  // Ignore existing ties. This is not a property that can be copied.
863  NewMO->TiedTo = 0;
864  // Add the new operand to MRI, but only for instructions in an MBB.
865  if (MRI)
866  MRI->addRegOperandToUseList(NewMO);
867  // The MCID operand information isn't accurate until we start adding
868  // explicit operands. The implicit operands are added first, then the
869  // explicits are inserted before them.
870  if (!isImpReg) {
871  // Tie uses to defs as indicated in MCInstrDesc.
872  if (NewMO->isUse()) {
873  int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
874  if (DefIdx != -1)
875  tieOperands(DefIdx, OpNo);
876  }
877  // If the register operand is flagged as early, mark the operand as such.
878  if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
879  NewMO->setIsEarlyClobber(true);
880  }
881  }
882 }
883 
884 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
885 /// fewer operand than it started with.
886 ///
887 void MachineInstr::RemoveOperand(unsigned OpNo) {
888  assert(OpNo < getNumOperands() && "Invalid operand number");
889  untieRegOperand(OpNo);
890 
891 #ifndef NDEBUG
892  // Moving tied operands would break the ties.
893  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
894  if (Operands[i].isReg())
895  assert(!Operands[i].isTied() && "Cannot move tied operands");
896 #endif
897 
898  MachineRegisterInfo *MRI = getRegInfo();
899  if (MRI && Operands[OpNo].isReg())
900  MRI->removeRegOperandFromUseList(Operands + OpNo);
901 
902  // Don't call the MachineOperand destructor. A lot of this code depends on
903  // MachineOperand having a trivial destructor anyway, and adding a call here
904  // wouldn't make it 'destructor-correct'.
905 
906  if (unsigned N = NumOperands - 1 - OpNo)
907  moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
908  --NumOperands;
909 }
910 
911 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
912 /// This function should be used only occasionally. The setMemRefs function
913 /// is the primary method for setting up a MachineInstr's MemRefs list.
915  MachineMemOperand *MO) {
916  mmo_iterator OldMemRefs = MemRefs;
917  unsigned OldNumMemRefs = NumMemRefs;
918 
919  unsigned NewNum = NumMemRefs + 1;
920  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
921 
922  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
923  NewMemRefs[NewNum - 1] = MO;
924  setMemRefs(NewMemRefs, NewMemRefs + NewNum);
925 }
926 
927 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
928 /// identical.
929 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
930  auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
931  auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
932  if ((E1 - I1) != (E2 - I2))
933  return false;
934  for (; I1 != E1; ++I1, ++I2) {
935  if (**I1 != **I2)
936  return false;
937  }
938  return true;
939 }
940 
941 std::pair<MachineInstr::mmo_iterator, unsigned>
943 
944  // If either of the incoming memrefs are empty, we must be conservative and
945  // treat this as if we've exhausted our space for memrefs and dropped them.
946  if (memoperands_empty() || Other.memoperands_empty())
947  return std::make_pair(nullptr, 0);
948 
949  // If both instructions have identical memrefs, we don't need to merge them.
950  // Since many instructions have a single memref, and we tend to merge things
951  // like pairs of loads from the same location, this catches a large number of
952  // cases in practice.
953  if (hasIdenticalMMOs(*this, Other))
954  return std::make_pair(MemRefs, NumMemRefs);
955 
956  // TODO: consider uniquing elements within the operand lists to reduce
957  // space usage and fall back to conservative information less often.
958  size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
959 
960  // If we don't have enough room to store this many memrefs, be conservative
961  // and drop them. Otherwise, we'd fail asserts when trying to add them to
962  // the new instruction.
963  if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
964  return std::make_pair(nullptr, 0);
965 
967  mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
968  mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
969  MemBegin);
970  MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
971  MemEnd);
972  assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
973  "missing memrefs");
974 
975  return std::make_pair(MemBegin, CombinedNumMemRefs);
976 }
977 
978 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
979  assert(!isBundledWithPred() && "Must be called on bundle header");
980  for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
981  if (MII->getDesc().getFlags() & Mask) {
982  if (Type == AnyInBundle)
983  return true;
984  } else {
985  if (Type == AllInBundle && !MII->isBundle())
986  return false;
987  }
988  // This was the last instruction in the bundle.
989  if (!MII->isBundledWithSucc())
990  return Type == AllInBundle;
991  }
992 }
993 
995  MICheckType Check) const {
996  // If opcodes or number of operands are not the same then the two
997  // instructions are obviously not identical.
998  if (Other.getOpcode() != getOpcode() ||
999  Other.getNumOperands() != getNumOperands())
1000  return false;
1001 
1002  if (isBundle()) {
1003  // We have passed the test above that both instructions have the same
1004  // opcode, so we know that both instructions are bundles here. Let's compare
1005  // MIs inside the bundle.
1006  assert(Other.isBundle() && "Expected that both instructions are bundles.");
1007  MachineBasicBlock::const_instr_iterator I1 = getIterator();
1009  // Loop until we analysed the last intruction inside at least one of the
1010  // bundles.
1011  while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
1012  ++I1;
1013  ++I2;
1014  if (!I1->isIdenticalTo(*I2, Check))
1015  return false;
1016  }
1017  // If we've reached the end of just one of the two bundles, but not both,
1018  // the instructions are not identical.
1019  if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
1020  return false;
1021  }
1022 
1023  // Check operands to make sure they match.
1024  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1025  const MachineOperand &MO = getOperand(i);
1026  const MachineOperand &OMO = Other.getOperand(i);
1027  if (!MO.isReg()) {
1028  if (!MO.isIdenticalTo(OMO))
1029  return false;
1030  continue;
1031  }
1032 
1033  // Clients may or may not want to ignore defs when testing for equality.
1034  // For example, machine CSE pass only cares about finding common
1035  // subexpressions, so it's safe to ignore virtual register defs.
1036  if (MO.isDef()) {
1037  if (Check == IgnoreDefs)
1038  continue;
1039  else if (Check == IgnoreVRegDefs) {
1042  if (MO.getReg() != OMO.getReg())
1043  return false;
1044  } else {
1045  if (!MO.isIdenticalTo(OMO))
1046  return false;
1047  if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
1048  return false;
1049  }
1050  } else {
1051  if (!MO.isIdenticalTo(OMO))
1052  return false;
1053  if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
1054  return false;
1055  }
1056  }
1057  // If DebugLoc does not match then two dbg.values are not identical.
1058  if (isDebugValue())
1059  if (getDebugLoc() && Other.getDebugLoc() &&
1060  getDebugLoc() != Other.getDebugLoc())
1061  return false;
1062  return true;
1063 }
1064 
1066  assert(getParent() && "Not embedded in a basic block!");
1067  return getParent()->remove(this);
1068 }
1069 
1071  assert(getParent() && "Not embedded in a basic block!");
1072  return getParent()->remove_instr(this);
1073 }
1074 
1076  assert(getParent() && "Not embedded in a basic block!");
1077  getParent()->erase(this);
1078 }
1079 
1081  assert(getParent() && "Not embedded in a basic block!");
1083  MachineFunction *MF = MBB->getParent();
1084  assert(MF && "Not embedded in a function!");
1085 
1086  MachineInstr *MI = (MachineInstr *)this;
1087  MachineRegisterInfo &MRI = MF->getRegInfo();
1088 
1089  for (const MachineOperand &MO : MI->operands()) {
1090  if (!MO.isReg() || !MO.isDef())
1091  continue;
1092  unsigned Reg = MO.getReg();
1094  continue;
1095  MRI.markUsesInDebugValueAsUndef(Reg);
1096  }
1097  MI->eraseFromParent();
1098 }
1099 
1101  assert(getParent() && "Not embedded in a basic block!");
1102  getParent()->erase_instr(this);
1103 }
1104 
1105 /// getNumExplicitOperands - Returns the number of non-implicit operands.
1106 ///
1108  unsigned NumOperands = MCID->getNumOperands();
1109  if (!MCID->isVariadic())
1110  return NumOperands;
1111 
1112  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
1113  const MachineOperand &MO = getOperand(i);
1114  if (!MO.isReg() || !MO.isImplicit())
1115  NumOperands++;
1116  }
1117  return NumOperands;
1118 }
1119 
1121  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
1122  setFlag(BundledPred);
1123  MachineBasicBlock::instr_iterator Pred = getIterator();
1124  --Pred;
1125  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1126  Pred->setFlag(BundledSucc);
1127 }
1128 
1130  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
1131  setFlag(BundledSucc);
1132  MachineBasicBlock::instr_iterator Succ = getIterator();
1133  ++Succ;
1134  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
1135  Succ->setFlag(BundledPred);
1136 }
1137 
1139  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
1140  clearFlag(BundledPred);
1141  MachineBasicBlock::instr_iterator Pred = getIterator();
1142  --Pred;
1143  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1144  Pred->clearFlag(BundledSucc);
1145 }
1146 
1148  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
1149  clearFlag(BundledSucc);
1150  MachineBasicBlock::instr_iterator Succ = getIterator();
1151  ++Succ;
1152  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
1153  Succ->clearFlag(BundledPred);
1154 }
1155 
1157  if (isInlineAsm()) {
1158  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1159  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1160  return true;
1161  }
1162  return false;
1163 }
1164 
1166  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1167  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1168  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
1169 }
1170 
1172  unsigned *GroupNo) const {
1173  assert(isInlineAsm() && "Expected an inline asm instruction");
1174  assert(OpIdx < getNumOperands() && "OpIdx out of range");
1175 
1176  // Ignore queries about the initial operands.
1177  if (OpIdx < InlineAsm::MIOp_FirstOperand)
1178  return -1;
1179 
1180  unsigned Group = 0;
1181  unsigned NumOps;
1182  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1183  i += NumOps) {
1184  const MachineOperand &FlagMO = getOperand(i);
1185  // If we reach the implicit register operands, stop looking.
1186  if (!FlagMO.isImm())
1187  return -1;
1188  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1189  if (i + NumOps > OpIdx) {
1190  if (GroupNo)
1191  *GroupNo = Group;
1192  return i;
1193  }
1194  ++Group;
1195  }
1196  return -1;
1197 }
1198 
1200  assert(isDebugValue() && "not a DBG_VALUE");
1201  return cast<DILocalVariable>(getOperand(2).getMetadata());
1202 }
1203 
1205  assert(isDebugValue() && "not a DBG_VALUE");
1206  return cast<DIExpression>(getOperand(3).getMetadata());
1207 }
1208 
1209 const TargetRegisterClass*
1211  const TargetInstrInfo *TII,
1212  const TargetRegisterInfo *TRI) const {
1213  assert(getParent() && "Can't have an MBB reference here!");
1214  assert(getParent()->getParent() && "Can't have an MF reference here!");
1215  const MachineFunction &MF = *getParent()->getParent();
1216 
1217  // Most opcodes have fixed constraints in their MCInstrDesc.
1218  if (!isInlineAsm())
1219  return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1220 
1221  if (!getOperand(OpIdx).isReg())
1222  return nullptr;
1223 
1224  // For tied uses on inline asm, get the constraint from the def.
1225  unsigned DefIdx;
1226  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1227  OpIdx = DefIdx;
1228 
1229  // Inline asm stores register class constraints in the flag word.
1230  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1231  if (FlagIdx < 0)
1232  return nullptr;
1233 
1234  unsigned Flag = getOperand(FlagIdx).getImm();
1235  unsigned RCID;
1240  return TRI->getRegClass(RCID);
1241 
1242  // Assume that all registers in a memory operand are pointers.
1244  return TRI->getPointerRegClass(MF);
1245 
1246  return nullptr;
1247 }
1248 
1250  unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1251  const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1252  // Check every operands inside the bundle if we have
1253  // been asked to.
1254  if (ExploreBundle)
1255  for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
1256  ++OpndIt)
1257  CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1258  OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1259  else
1260  // Otherwise, just check the current operands.
1261  for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1262  CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1263  return CurRC;
1264 }
1265 
1266 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1267  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1268  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1269  assert(CurRC && "Invalid initial register class");
1270  // Check if Reg is constrained by some of its use/def from MI.
1271  const MachineOperand &MO = getOperand(OpIdx);
1272  if (!MO.isReg() || MO.getReg() != Reg)
1273  return CurRC;
1274  // If yes, accumulate the constraints through the operand.
1275  return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1276 }
1277 
1279  unsigned OpIdx, const TargetRegisterClass *CurRC,
1280  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1281  const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1282  const MachineOperand &MO = getOperand(OpIdx);
1283  assert(MO.isReg() &&
1284  "Cannot get register constraints for non-register operand");
1285  assert(CurRC && "Invalid initial register class");
1286  if (unsigned SubIdx = MO.getSubReg()) {
1287  if (OpRC)
1288  CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1289  else
1290  CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1291  } else if (OpRC)
1292  CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1293  return CurRC;
1294 }
1295 
1296 /// Return the number of instructions inside the MI bundle, not counting the
1297 /// header instruction.
1300  unsigned Size = 0;
1301  while (I->isBundledWithSucc()) {
1302  ++Size;
1303  ++I;
1304  }
1305  return Size;
1306 }
1307 
1308 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1309 /// the given register (not considering sub/super-registers).
1311  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1312  const MachineOperand &MO = getOperand(i);
1313  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
1314  return true;
1315  }
1316  return false;
1317 }
1318 
1319 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1320 /// the specific register or -1 if it is not found. It further tightens
1321 /// the search criteria to a use that kills the register if isKill is true.
1323  unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
1324  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1325  const MachineOperand &MO = getOperand(i);
1326  if (!MO.isReg() || !MO.isUse())
1327  continue;
1328  unsigned MOReg = MO.getReg();
1329  if (!MOReg)
1330  continue;
1331  if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1333  TRI->isSubRegister(MOReg, Reg)))
1334  if (!isKill || MO.isKill())
1335  return i;
1336  }
1337  return -1;
1338 }
1339 
1340 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1341 /// indicating if this instruction reads or writes Reg. This also considers
1342 /// partial defines.
1343 std::pair<bool,bool>
1345  SmallVectorImpl<unsigned> *Ops) const {
1346  bool PartDef = false; // Partial redefine.
1347  bool FullDef = false; // Full define.
1348  bool Use = false;
1349 
1350  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1351  const MachineOperand &MO = getOperand(i);
1352  if (!MO.isReg() || MO.getReg() != Reg)
1353  continue;
1354  if (Ops)
1355  Ops->push_back(i);
1356  if (MO.isUse())
1357  Use |= !MO.isUndef();
1358  else if (MO.getSubReg() && !MO.isUndef())
1359  // A partial <def,undef> doesn't count as reading the register.
1360  PartDef = true;
1361  else
1362  FullDef = true;
1363  }
1364  // A partial redefine uses Reg unless there is also a full define.
1365  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1366 }
1367 
1368 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1369 /// the specified register or -1 if it is not found. If isDead is true, defs
1370 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1371 /// also checks if there is a def of a super-register.
1372 int
1373 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1374  const TargetRegisterInfo *TRI) const {
1375  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1376  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1377  const MachineOperand &MO = getOperand(i);
1378  // Accept regmask operands when Overlap is set.
1379  // Ignore them when looking for a specific def operand (Overlap == false).
1380  if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1381  return i;
1382  if (!MO.isReg() || !MO.isDef())
1383  continue;
1384  unsigned MOReg = MO.getReg();
1385  bool Found = (MOReg == Reg);
1386  if (!Found && TRI && isPhys &&
1388  if (Overlap)
1389  Found = TRI->regsOverlap(MOReg, Reg);
1390  else
1391  Found = TRI->isSubRegister(MOReg, Reg);
1392  }
1393  if (Found && (!isDead || MO.isDead()))
1394  return i;
1395  }
1396  return -1;
1397 }
1398 
1399 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1400 /// operand list that is used to represent the predicate. It returns -1 if
1401 /// none is found.
1403  // Don't call MCID.findFirstPredOperandIdx() because this variant
1404  // is sometimes called on an instruction that's not yet complete, and
1405  // so the number of operands is less than the MCID indicates. In
1406  // particular, the PTX target does this.
1407  const MCInstrDesc &MCID = getDesc();
1408  if (MCID.isPredicable()) {
1409  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1410  if (MCID.OpInfo[i].isPredicate())
1411  return i;
1412  }
1413 
1414  return -1;
1415 }
1416 
1417 // MachineOperand::TiedTo is 4 bits wide.
1418 const unsigned TiedMax = 15;
1419 
1420 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1421 ///
1422 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1423 /// field. TiedTo can have these values:
1424 ///
1425 /// 0: Operand is not tied to anything.
1426 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1427 /// TiedMax: Tied to an operand >= TiedMax-1.
1428 ///
1429 /// The tied def must be one of the first TiedMax operands on a normal
1430 /// instruction. INLINEASM instructions allow more tied defs.
1431 ///
1432 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1433  MachineOperand &DefMO = getOperand(DefIdx);
1434  MachineOperand &UseMO = getOperand(UseIdx);
1435  assert(DefMO.isDef() && "DefIdx must be a def operand");
1436  assert(UseMO.isUse() && "UseIdx must be a use operand");
1437  assert(!DefMO.isTied() && "Def is already tied to another use");
1438  assert(!UseMO.isTied() && "Use is already tied to another def");
1439 
1440  if (DefIdx < TiedMax)
1441  UseMO.TiedTo = DefIdx + 1;
1442  else {
1443  // Inline asm can use the group descriptors to find tied operands, but on
1444  // normal instruction, the tied def must be within the first TiedMax
1445  // operands.
1446  assert(isInlineAsm() && "DefIdx out of range");
1447  UseMO.TiedTo = TiedMax;
1448  }
1449 
1450  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1451  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1452 }
1453 
1454 /// Given the index of a tied register operand, find the operand it is tied to.
1455 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1456 /// which must exist.
1457 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1458  const MachineOperand &MO = getOperand(OpIdx);
1459  assert(MO.isTied() && "Operand isn't tied");
1460 
1461  // Normally TiedTo is in range.
1462  if (MO.TiedTo < TiedMax)
1463  return MO.TiedTo - 1;
1464 
1465  // Uses on normal instructions can be out of range.
1466  if (!isInlineAsm()) {
1467  // Normal tied defs must be in the 0..TiedMax-1 range.
1468  if (MO.isUse())
1469  return TiedMax - 1;
1470  // MO is a def. Search for the tied use.
1471  for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1472  const MachineOperand &UseMO = getOperand(i);
1473  if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1474  return i;
1475  }
1476  llvm_unreachable("Can't find tied use");
1477  }
1478 
1479  // Now deal with inline asm by parsing the operand group descriptor flags.
1480  // Find the beginning of each operand group.
1481  SmallVector<unsigned, 8> GroupIdx;
1482  unsigned OpIdxGroup = ~0u;
1483  unsigned NumOps;
1484  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1485  i += NumOps) {
1486  const MachineOperand &FlagMO = getOperand(i);
1487  assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1488  unsigned CurGroup = GroupIdx.size();
1489  GroupIdx.push_back(i);
1490  NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1491  // OpIdx belongs to this operand group.
1492  if (OpIdx > i && OpIdx < i + NumOps)
1493  OpIdxGroup = CurGroup;
1494  unsigned TiedGroup;
1495  if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1496  continue;
1497  // Operands in this group are tied to operands in TiedGroup which must be
1498  // earlier. Find the number of operands between the two groups.
1499  unsigned Delta = i - GroupIdx[TiedGroup];
1500 
1501  // OpIdx is a use tied to TiedGroup.
1502  if (OpIdxGroup == CurGroup)
1503  return OpIdx - Delta;
1504 
1505  // OpIdx is a def tied to this use group.
1506  if (OpIdxGroup == TiedGroup)
1507  return OpIdx + Delta;
1508  }
1509  llvm_unreachable("Invalid tied operand on inline asm");
1510 }
1511 
1512 /// clearKillInfo - Clears kill flags on all operands.
1513 ///
1515  for (MachineOperand &MO : operands()) {
1516  if (MO.isReg() && MO.isUse())
1517  MO.setIsKill(false);
1518  }
1519 }
1520 
1521 void MachineInstr::substituteRegister(unsigned FromReg,
1522  unsigned ToReg,
1523  unsigned SubIdx,
1524  const TargetRegisterInfo &RegInfo) {
1526  if (SubIdx)
1527  ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1528  for (MachineOperand &MO : operands()) {
1529  if (!MO.isReg() || MO.getReg() != FromReg)
1530  continue;
1531  MO.substPhysReg(ToReg, RegInfo);
1532  }
1533  } else {
1534  for (MachineOperand &MO : operands()) {
1535  if (!MO.isReg() || MO.getReg() != FromReg)
1536  continue;
1537  MO.substVirtReg(ToReg, SubIdx, RegInfo);
1538  }
1539  }
1540 }
1541 
1542 /// isSafeToMove - Return true if it is safe to move this instruction. If
1543 /// SawStore is set to true, it means that there is a store (or call) between
1544 /// the instruction's location and its intended destination.
1546  // Ignore stuff that we obviously can't move.
1547  //
1548  // Treat volatile loads as stores. This is not strictly necessary for
1549  // volatiles, but it is required for atomic loads. It is not allowed to move
1550  // a load across an atomic load with Ordering > Monotonic.
1551  if (mayStore() || isCall() ||
1552  (mayLoad() && hasOrderedMemoryRef())) {
1553  SawStore = true;
1554  return false;
1555  }
1556 
1557  if (isPosition() || isDebugValue() || isTerminator() ||
1558  hasUnmodeledSideEffects())
1559  return false;
1560 
1561  // See if this instruction does a load. If so, we have to guarantee that the
1562  // loaded value doesn't change between the load and the its intended
1563  // destination. The check for isInvariantLoad gives the targe the chance to
1564  // classify the load as always returning a constant, e.g. a constant pool
1565  // load.
1566  if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1567  // Otherwise, this is a real load. If there is a store between the load and
1568  // end of block, we can't move it.
1569  return !SawStore;
1570 
1571  return true;
1572 }
1573 
1574 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1575 /// or volatile memory reference, or if the information describing the memory
1576 /// reference is not available. Return false if it is known to have no ordered
1577 /// memory references.
1579  // An instruction known never to access memory won't have a volatile access.
1580  if (!mayStore() &&
1581  !mayLoad() &&
1582  !isCall() &&
1583  !hasUnmodeledSideEffects())
1584  return false;
1585 
1586  // Otherwise, if the instruction has no memory reference information,
1587  // conservatively assume it wasn't preserved.
1588  if (memoperands_empty())
1589  return true;
1590 
1591  // Check if any of our memory operands are ordered.
1592  return any_of(memoperands(), [](const MachineMemOperand *MMO) {
1593  return !MMO->isUnordered();
1594  });
1595 }
1596 
1597 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1598 /// trap and is loading from a location whose value is invariant across a run of
1599 /// this function.
1601  // If the instruction doesn't load at all, it isn't an invariant load.
1602  if (!mayLoad())
1603  return false;
1604 
1605  // If the instruction has lost its memoperands, conservatively assume that
1606  // it may not be an invariant load.
1607  if (memoperands_empty())
1608  return false;
1609 
1610  const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1611 
1612  for (MachineMemOperand *MMO : memoperands()) {
1613  if (MMO->isVolatile()) return false;
1614  if (MMO->isStore()) return false;
1615  if (MMO->isInvariant() && MMO->isDereferenceable())
1616  continue;
1617 
1618  // A load from a constant PseudoSourceValue is invariant.
1619  if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1620  if (PSV->isConstant(&MFI))
1621  continue;
1622 
1623  if (const Value *V = MMO->getValue()) {
1624  // If we have an AliasAnalysis, ask it whether the memory is constant.
1625  if (AA &&
1627  MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1628  continue;
1629  }
1630 
1631  // Otherwise assume conservatively.
1632  return false;
1633  }
1634 
1635  // Everything checks out.
1636  return true;
1637 }
1638 
1639 /// isConstantValuePHI - If the specified instruction is a PHI that always
1640 /// merges together the same virtual register, return the register, otherwise
1641 /// return 0.
1643  if (!isPHI())
1644  return 0;
1645  assert(getNumOperands() >= 3 &&
1646  "It's illegal to have a PHI without source operands");
1647 
1648  unsigned Reg = getOperand(1).getReg();
1649  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1650  if (getOperand(i).getReg() != Reg)
1651  return 0;
1652  return Reg;
1653 }
1654 
1656  if (hasProperty(MCID::UnmodeledSideEffects))
1657  return true;
1658  if (isInlineAsm()) {
1659  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1660  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1661  return true;
1662  }
1663 
1664  return false;
1665 }
1666 
1668  return mayStore() || isCall() || hasUnmodeledSideEffects();
1669 }
1670 
1671 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1672 ///
1674  for (const MachineOperand &MO : operands()) {
1675  if (!MO.isReg() || MO.isUse())
1676  continue;
1677  if (!MO.isDead())
1678  return false;
1679  }
1680  return true;
1681 }
1682 
1683 /// copyImplicitOps - Copy implicit register operands from specified
1684 /// instruction to this instruction.
1686  const MachineInstr &MI) {
1687  for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1688  i != e; ++i) {
1689  const MachineOperand &MO = MI.getOperand(i);
1690  if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1691  addOperand(MF, MO);
1692  }
1693 }
1694 
1696 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1697  dbgs() << " ";
1698  print(dbgs(), false /* SkipOpers */, TII);
1699 #endif
1700 }
1701 
1702 void MachineInstr::print(raw_ostream &OS, bool SkipOpers,
1703  const TargetInstrInfo *TII) const {
1704  const Module *M = nullptr;
1705  if (const MachineBasicBlock *MBB = getParent())
1706  if (const MachineFunction *MF = MBB->getParent())
1707  M = MF->getFunction()->getParent();
1708 
1709  ModuleSlotTracker MST(M);
1710  print(OS, MST, SkipOpers, TII);
1711 }
1712 
1714  bool SkipOpers, const TargetInstrInfo *TII) const {
1715  // We can be a bit tidier if we know the MachineFunction.
1716  const MachineFunction *MF = nullptr;
1717  const TargetRegisterInfo *TRI = nullptr;
1718  const MachineRegisterInfo *MRI = nullptr;
1719  const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1720 
1721  if (const MachineBasicBlock *MBB = getParent()) {
1722  MF = MBB->getParent();
1723  if (MF) {
1724  MRI = &MF->getRegInfo();
1725  TRI = MF->getSubtarget().getRegisterInfo();
1726  if (!TII)
1727  TII = MF->getSubtarget().getInstrInfo();
1728  IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
1729  }
1730  }
1731 
1732  // Save a list of virtual registers.
1733  SmallVector<unsigned, 8> VirtRegs;
1734 
1735  // Print explicitly defined operands on the left of an assignment syntax.
1736  unsigned StartOp = 0, e = getNumOperands();
1737  for (; StartOp < e && getOperand(StartOp).isReg() &&
1738  getOperand(StartOp).isDef() &&
1739  !getOperand(StartOp).isImplicit();
1740  ++StartOp) {
1741  if (StartOp != 0) OS << ", ";
1742  getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo);
1743  unsigned Reg = getOperand(StartOp).getReg();
1745  VirtRegs.push_back(Reg);
1746  LLT Ty = MRI ? MRI->getType(Reg) : LLT{};
1747  if (Ty.isValid())
1748  OS << '(' << Ty << ')';
1749  }
1750  }
1751 
1752  if (StartOp != 0)
1753  OS << " = ";
1754 
1755  // Print the opcode name.
1756  if (TII)
1757  OS << TII->getName(getOpcode());
1758  else
1759  OS << "UNKNOWN";
1760 
1761  if (SkipOpers)
1762  return;
1763 
1764  // Print the rest of the operands.
1765  bool OmittedAnyCallClobbers = false;
1766  bool FirstOp = true;
1767  unsigned AsmDescOp = ~0u;
1768  unsigned AsmOpCount = 0;
1769 
1770  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1771  // Print asm string.
1772  OS << " ";
1773  getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
1774 
1775  // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1776  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1777  if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1778  OS << " [sideeffect]";
1779  if (ExtraInfo & InlineAsm::Extra_MayLoad)
1780  OS << " [mayload]";
1781  if (ExtraInfo & InlineAsm::Extra_MayStore)
1782  OS << " [maystore]";
1783  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1784  OS << " [isconvergent]";
1785  if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1786  OS << " [alignstack]";
1787  if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1788  OS << " [attdialect]";
1789  if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1790  OS << " [inteldialect]";
1791 
1792  StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1793  FirstOp = false;
1794  }
1795 
1796  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1797  const MachineOperand &MO = getOperand(i);
1798 
1800  VirtRegs.push_back(MO.getReg());
1801 
1802  // Omit call-clobbered registers which aren't used anywhere. This makes
1803  // call instructions much less noisy on targets where calls clobber lots
1804  // of registers. Don't rely on MO.isDead() because we may be called before
1805  // LiveVariables is run, or we may be looking at a non-allocatable reg.
1806  if (MRI && isCall() &&
1807  MO.isReg() && MO.isImplicit() && MO.isDef()) {
1808  unsigned Reg = MO.getReg();
1810  if (MRI->use_empty(Reg)) {
1811  bool HasAliasLive = false;
1812  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
1813  unsigned AliasReg = *AI;
1814  if (!MRI->use_empty(AliasReg)) {
1815  HasAliasLive = true;
1816  break;
1817  }
1818  }
1819  if (!HasAliasLive) {
1820  OmittedAnyCallClobbers = true;
1821  continue;
1822  }
1823  }
1824  }
1825  }
1826 
1827  if (FirstOp) FirstOp = false; else OS << ",";
1828  OS << " ";
1829  if (i < getDesc().NumOperands) {
1830  const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1831  if (MCOI.isPredicate())
1832  OS << "pred:";
1833  if (MCOI.isOptionalDef())
1834  OS << "opt:";
1835  }
1836  if (isDebugValue() && MO.isMetadata()) {
1837  // Pretty print DBG_VALUE instructions.
1838  auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1839  if (DIV && !DIV->getName().empty())
1840  OS << "!\"" << DIV->getName() << '\"';
1841  else
1842  MO.print(OS, MST, TRI);
1843  } else if (TRI && (isInsertSubreg() || isRegSequence() ||
1844  (isSubregToReg() && i == 3)) && MO.isImm()) {
1845  OS << TRI->getSubRegIndexName(MO.getImm());
1846  } else if (i == AsmDescOp && MO.isImm()) {
1847  // Pretty print the inline asm operand descriptor.
1848  OS << '$' << AsmOpCount++;
1849  unsigned Flag = MO.getImm();
1850  switch (InlineAsm::getKind(Flag)) {
1851  case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1852  case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1853  case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1854  case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1855  case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1856  case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1857  default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1858  }
1859 
1860  unsigned RCID = 0;
1861  if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1862  InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1863  if (TRI) {
1864  OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1865  } else
1866  OS << ":RC" << RCID;
1867  }
1868 
1869  if (InlineAsm::isMemKind(Flag)) {
1870  unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1871  switch (MCID) {
1872  case InlineAsm::Constraint_es: OS << ":es"; break;
1873  case InlineAsm::Constraint_i: OS << ":i"; break;
1874  case InlineAsm::Constraint_m: OS << ":m"; break;
1875  case InlineAsm::Constraint_o: OS << ":o"; break;
1876  case InlineAsm::Constraint_v: OS << ":v"; break;
1877  case InlineAsm::Constraint_Q: OS << ":Q"; break;
1878  case InlineAsm::Constraint_R: OS << ":R"; break;
1879  case InlineAsm::Constraint_S: OS << ":S"; break;
1880  case InlineAsm::Constraint_T: OS << ":T"; break;
1881  case InlineAsm::Constraint_Um: OS << ":Um"; break;
1882  case InlineAsm::Constraint_Un: OS << ":Un"; break;
1883  case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1884  case InlineAsm::Constraint_Us: OS << ":Us"; break;
1885  case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1886  case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1887  case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1888  case InlineAsm::Constraint_X: OS << ":X"; break;
1889  case InlineAsm::Constraint_Z: OS << ":Z"; break;
1890  case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1891  case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1892  default: OS << ":?"; break;
1893  }
1894  }
1895 
1896  unsigned TiedTo = 0;
1897  if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1898  OS << " tiedto:$" << TiedTo;
1899 
1900  OS << ']';
1901 
1902  // Compute the index of the next operand descriptor.
1903  AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1904  } else
1905  MO.print(OS, MST, TRI);
1906  }
1907 
1908  // Briefly indicate whether any call clobbers were omitted.
1909  if (OmittedAnyCallClobbers) {
1910  if (!FirstOp) OS << ",";
1911  OS << " ...";
1912  }
1913 
1914  bool HaveSemi = false;
1915  const unsigned PrintableFlags = FrameSetup | FrameDestroy;
1916  if (Flags & PrintableFlags) {
1917  if (!HaveSemi) {
1918  OS << ";";
1919  HaveSemi = true;
1920  }
1921  OS << " flags: ";
1922 
1923  if (Flags & FrameSetup)
1924  OS << "FrameSetup";
1925 
1926  if (Flags & FrameDestroy)
1927  OS << "FrameDestroy";
1928  }
1929 
1930  if (!memoperands_empty()) {
1931  if (!HaveSemi) {
1932  OS << ";";
1933  HaveSemi = true;
1934  }
1935 
1936  OS << " mem:";
1937  for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1938  i != e; ++i) {
1939  (*i)->print(OS, MST);
1940  if (std::next(i) != e)
1941  OS << " ";
1942  }
1943  }
1944 
1945  // Print the regclass of any virtual registers encountered.
1946  if (MRI && !VirtRegs.empty()) {
1947  if (!HaveSemi) {
1948  OS << ";";
1949  HaveSemi = true;
1950  }
1951  for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1952  const RegClassOrRegBank &RC = MRI->getRegClassOrRegBank(VirtRegs[i]);
1953  if (!RC)
1954  continue;
1955  // Generic virtual registers do not have register classes.
1956  if (RC.is<const RegisterBank *>())
1957  OS << " " << RC.get<const RegisterBank *>()->getName();
1958  else
1959  OS << " "
1960  << TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
1961  OS << ':' << PrintReg(VirtRegs[i]);
1962  for (unsigned j = i+1; j != VirtRegs.size();) {
1963  if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
1964  ++j;
1965  continue;
1966  }
1967  if (VirtRegs[i] != VirtRegs[j])
1968  OS << "," << PrintReg(VirtRegs[j]);
1969  VirtRegs.erase(VirtRegs.begin()+j);
1970  }
1971  }
1972  }
1973 
1974  // Print debug location information.
1975  if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1976  if (!HaveSemi)
1977  OS << ";";
1978  auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1979  OS << " line no:" << DV->getLine();
1980  if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1981  DebugLoc InlinedAtDL(InlinedAt);
1982  if (InlinedAtDL && MF) {
1983  OS << " inlined @[ ";
1984  InlinedAtDL.print(OS);
1985  OS << " ]";
1986  }
1987  }
1988  if (isIndirectDebugValue())
1989  OS << " indirect";
1990  } else if (debugLoc && MF) {
1991  if (!HaveSemi)
1992  OS << ";";
1993  OS << " dbg:";
1994  debugLoc.print(OS);
1995  }
1996 
1997  OS << '\n';
1998 }
1999 
2000 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
2001  const TargetRegisterInfo *RegInfo,
2002  bool AddIfNotFound) {
2003  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
2004  bool hasAliases = isPhysReg &&
2005  MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
2006  bool Found = false;
2007  SmallVector<unsigned,4> DeadOps;
2008  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2009  MachineOperand &MO = getOperand(i);
2010  if (!MO.isReg() || !MO.isUse() || MO.isUndef())
2011  continue;
2012 
2013  // DEBUG_VALUE nodes do not contribute to code generation and should
2014  // always be ignored. Failure to do so may result in trying to modify
2015  // KILL flags on DEBUG_VALUE nodes.
2016  if (MO.isDebug())
2017  continue;
2018 
2019  unsigned Reg = MO.getReg();
2020  if (!Reg)
2021  continue;
2022 
2023  if (Reg == IncomingReg) {
2024  if (!Found) {
2025  if (MO.isKill())
2026  // The register is already marked kill.
2027  return true;
2028  if (isPhysReg && isRegTiedToDefOperand(i))
2029  // Two-address uses of physregs must not be marked kill.
2030  return true;
2031  MO.setIsKill();
2032  Found = true;
2033  }
2034  } else if (hasAliases && MO.isKill() &&
2036  // A super-register kill already exists.
2037  if (RegInfo->isSuperRegister(IncomingReg, Reg))
2038  return true;
2039  if (RegInfo->isSubRegister(IncomingReg, Reg))
2040  DeadOps.push_back(i);
2041  }
2042  }
2043 
2044  // Trim unneeded kill operands.
2045  while (!DeadOps.empty()) {
2046  unsigned OpIdx = DeadOps.back();
2047  if (getOperand(OpIdx).isImplicit())
2048  RemoveOperand(OpIdx);
2049  else
2050  getOperand(OpIdx).setIsKill(false);
2051  DeadOps.pop_back();
2052  }
2053 
2054  // If not found, this means an alias of one of the operands is killed. Add a
2055  // new implicit operand if required.
2056  if (!Found && AddIfNotFound) {
2058  false /*IsDef*/,
2059  true /*IsImp*/,
2060  true /*IsKill*/));
2061  return true;
2062  }
2063  return Found;
2064 }
2065 
2067  const TargetRegisterInfo *RegInfo) {
2069  RegInfo = nullptr;
2070  for (MachineOperand &MO : operands()) {
2071  if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2072  continue;
2073  unsigned OpReg = MO.getReg();
2074  if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
2075  MO.setIsKill(false);
2076  }
2077 }
2078 
2080  const TargetRegisterInfo *RegInfo,
2081  bool AddIfNotFound) {
2082  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
2083  bool hasAliases = isPhysReg &&
2084  MCRegAliasIterator(Reg, RegInfo, false).isValid();
2085  bool Found = false;
2086  SmallVector<unsigned,4> DeadOps;
2087  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2088  MachineOperand &MO = getOperand(i);
2089  if (!MO.isReg() || !MO.isDef())
2090  continue;
2091  unsigned MOReg = MO.getReg();
2092  if (!MOReg)
2093  continue;
2094 
2095  if (MOReg == Reg) {
2096  MO.setIsDead();
2097  Found = true;
2098  } else if (hasAliases && MO.isDead() &&
2100  // There exists a super-register that's marked dead.
2101  if (RegInfo->isSuperRegister(Reg, MOReg))
2102  return true;
2103  if (RegInfo->isSubRegister(Reg, MOReg))
2104  DeadOps.push_back(i);
2105  }
2106  }
2107 
2108  // Trim unneeded dead operands.
2109  while (!DeadOps.empty()) {
2110  unsigned OpIdx = DeadOps.back();
2111  if (getOperand(OpIdx).isImplicit())
2112  RemoveOperand(OpIdx);
2113  else
2114  getOperand(OpIdx).setIsDead(false);
2115  DeadOps.pop_back();
2116  }
2117 
2118  // If not found, this means an alias of one of the operands is dead. Add a
2119  // new implicit operand if required.
2120  if (Found || !AddIfNotFound)
2121  return Found;
2122 
2124  true /*IsDef*/,
2125  true /*IsImp*/,
2126  false /*IsKill*/,
2127  true /*IsDead*/));
2128  return true;
2129 }
2130 
2132  for (MachineOperand &MO : operands()) {
2133  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2134  continue;
2135  MO.setIsDead(false);
2136  }
2137 }
2138 
2139 void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
2140  for (MachineOperand &MO : operands()) {
2141  if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2142  continue;
2143  MO.setIsUndef(IsUndef);
2144  }
2145 }
2146 
2148  const TargetRegisterInfo *RegInfo) {
2150  MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
2151  if (MO)
2152  return;
2153  } else {
2154  for (const MachineOperand &MO : operands()) {
2155  if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2156  MO.getSubReg() == 0)
2157  return;
2158  }
2159  }
2161  true /*IsDef*/,
2162  true /*IsImp*/));
2163 }
2164 
2166  const TargetRegisterInfo &TRI) {
2167  bool HasRegMask = false;
2168  for (MachineOperand &MO : operands()) {
2169  if (MO.isRegMask()) {
2170  HasRegMask = true;
2171  continue;
2172  }
2173  if (!MO.isReg() || !MO.isDef()) continue;
2174  unsigned Reg = MO.getReg();
2175  if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
2176  // If there are no uses, including partial uses, the def is dead.
2177  if (none_of(UsedRegs,
2178  [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
2179  MO.setIsDead();
2180  }
2181 
2182  // This is a call with a register mask operand.
2183  // Mask clobbers are always dead, so add defs for the non-dead defines.
2184  if (HasRegMask)
2185  for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
2186  I != E; ++I)
2187  addRegisterDefined(*I, &TRI);
2188 }
2189 
2190 unsigned
2192  // Build up a buffer of hash code components.
2193  SmallVector<size_t, 8> HashComponents;
2194  HashComponents.reserve(MI->getNumOperands() + 1);
2195  HashComponents.push_back(MI->getOpcode());
2196  for (const MachineOperand &MO : MI->operands()) {
2197  if (MO.isReg() && MO.isDef() &&
2199  continue; // Skip virtual register defs.
2200 
2201  HashComponents.push_back(hash_value(MO));
2202  }
2203  return hash_combine_range(HashComponents.begin(), HashComponents.end());
2204 }
2205 
2207  // Find the source location cookie.
2208  unsigned LocCookie = 0;
2209  const MDNode *LocMD = nullptr;
2210  for (unsigned i = getNumOperands(); i != 0; --i) {
2211  if (getOperand(i-1).isMetadata() &&
2212  (LocMD = getOperand(i-1).getMetadata()) &&
2213  LocMD->getNumOperands() != 0) {
2214  if (const ConstantInt *CI =
2215  mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2216  LocCookie = CI->getZExtValue();
2217  break;
2218  }
2219  }
2220  }
2221 
2222  if (const MachineBasicBlock *MBB = getParent())
2223  if (const MachineFunction *MF = MBB->getParent())
2224  return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2225  report_fatal_error(Msg);
2226 }
2227 
2229  const MCInstrDesc &MCID, bool IsIndirect,
2230  unsigned Reg, unsigned Offset,
2231  const MDNode *Variable, const MDNode *Expr) {
2232  assert(isa<DILocalVariable>(Variable) && "not a variable");
2233  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2234  assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2235  "Expected inlined-at fields to agree");
2236  if (IsIndirect)
2237  return BuildMI(MF, DL, MCID)
2238  .addReg(Reg, RegState::Debug)
2239  .addImm(Offset)
2240  .addMetadata(Variable)
2241  .addMetadata(Expr);
2242  else {
2243  assert(Offset == 0 && "A direct address cannot have an offset.");
2244  return BuildMI(MF, DL, MCID)
2245  .addReg(Reg, RegState::Debug)
2246  .addReg(0U, RegState::Debug)
2247  .addMetadata(Variable)
2248  .addMetadata(Expr);
2249  }
2250 }
2251 
2254  const DebugLoc &DL, const MCInstrDesc &MCID,
2255  bool IsIndirect, unsigned Reg,
2256  unsigned Offset, const MDNode *Variable,
2257  const MDNode *Expr) {
2258  assert(isa<DILocalVariable>(Variable) && "not a variable");
2259  assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2260  MachineFunction &MF = *BB.getParent();
2261  MachineInstr *MI =
2262  BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, Variable, Expr);
2263  BB.insert(I, MI);
2264  return MachineInstrBuilder(MF, MI);
2265 }
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isImplicit() const
void bundleWithPred()
Bundle this instruction with its predecessor.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void print(raw_ostream &OS, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const
void push_back(const T &Elt)
Definition: SmallVector.h:211
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
Definition: MCInstrDesc.h:96
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
size_t i
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:450
void setTargetFlags(unsigned F)
const ConstantFP * getFPImm() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
static bool isDebug()
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1040
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void setIsUndef(bool Val=true)
iterator end() const
Definition: ArrayRef.h:130
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
This file contains the declarations for metadata subclasses.
bool isTied() const
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isBundle(MCInst const &MCI)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
MachineBasicBlock reference.
const char * getSymbolName() const
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:830
void setIsDead(bool Val=true)
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
Manage lifetime of a slot tracker for printing IR.
const MDNode * getMetadata() const
void reserve(size_type N)
Definition: SmallVector.h:377
Mask of live-out registers.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with strcmp
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isImmKind(unsigned Flag)
Definition: InlineAsm.h:275
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Mask of preserved registers.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void clearKillInfo()
Clears kill flags on all operands.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
unsigned getCFIIndex() const
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
MCCFIInstruction index.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
Name of external global symbol.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:750
Reg
All possible values of the reg field in the ModR/M byte.
static StringRef getName(Value *V)
void setIndex(int Idx)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isUndef() const
void bundleWithSucc()
Bundle this instruction with its successor.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
Definition: DebugLoc.cpp:85
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:292
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:154
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool isKill() const
Immediate >64bit operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
Definition: APFloat.cpp:4132
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
int64_t getImm() const
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
struct llvm::MachineOperand::@38::@39 Reg
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
unsigned short NumOperands
Definition: MCInstrDesc.h:166
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
Definition: Module.cpp:196
TargetInstrInfo - Interface to description of machine instruction set.
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:359
bool isBundle() const
Definition: MachineInstr.h:804
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
Intrinsic::ID getIntrinsicID() const
unsigned getTargetFlags() const
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:99
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:269
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
MCRegAliasIterator enumerates all registers aliasing Reg.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:743
uint32_t Offset
static unsigned getMemoryConstraintID(unsigned Flag)
Definition: InlineAsm.h:328
Address of a basic block.
iterator begin() const
Definition: ArrayRef.h:129
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:324
int64_t getOffset() const
Return the offset from the symbol in this operand.
self_iterator getIterator()
Definition: ilist_node.h:81
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
void setOffset(int64_t Offset)
unsigned getSubReg() const
static unsigned getHashValue(const MachineInstr *const &MI)
static bool isMemKind(unsigned Flag)
Definition: InlineAsm.h:276
iterator erase(const_iterator CI)
Definition: SmallVector.h:431
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
TargetIntrinsicInfo - Interface to description of machine instruction set.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Representation for a specific memory location.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
const ConstantInt * CI
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1034
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
bool memoperands_empty() const
Return true if we don't have any memory operands which described the the memory access done by this i...
Definition: MachineInstr.h:363
Iterator for intrusive lists based on ilist_node.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
Definition: Constants.h:88
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Generic predicate for ISel.
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:135
MachineBasicBlock * MBB
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
unsigned getPredicate() const
void dump(const TargetInstrInfo *TII=nullptr) const
This class implements the register bank concept.
Definition: RegisterBank.h:29
DWARF expression.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
MCSymbol reference (for debug/eh info)
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const ConstantInt * getCImm() const
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:602
Special value supplied for machine level alias analysis.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:480
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
An opaque object representing a hash code.
Definition: Hashing.h:72
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
const unsigned TiedMax
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:350
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
union llvm::MachineOperand::@38::@40::@41 Val
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
std::pair< mmo_iterator, unsigned > mergeMemRefsWith(const MachineInstr &Other)
Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of b...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void setSubReg(unsigned subReg)
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
MCSymbol * getMCSymbol() const
bool isValid() const
Definition: LowLevelType.h:88
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Abstract Stack Frame Index.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void unbundleFromSucc()
Break bundle below this instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
virtual const TargetInstrInfo * getInstrInfo() const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:537
LLVM Value Representation.
Definition: Value.h:71
Floating-point immediate operand.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
bool isDebug() const
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
const BlockAddress * getBlockAddress() const
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Address of indexed Constant in Constant Pool.
bool isStackAligningInlineAsm() const
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
int is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:123
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool isInternalRead() const
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
Definition: PointerUnion.h:87
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Metadata reference (for debug info)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:358
static cl::opt< bool > PrintWholeRegMask("print-whole-regmask", cl::desc("Print the full contents of regmask operands in IR dumps"), cl::init(true), cl::Hidden)
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.