64 #define DEBUG_TYPE "hexagon-lowering"
68 cl::desc(
"Control jump table emission on Hexagon target"));
72 cl::desc(
"Enable Hexagon SDNode scheduling"));
76 cl::desc(
"Enable Fast Math processing"));
80 cl::desc(
"Set minimum jump tables"));
84 cl::desc(
"Max #stores to inline memcpy"));
88 cl::desc(
"Max #stores to inline memcpy"));
92 cl::desc(
"Max #stores to inline memmove"));
96 cl::desc(
"Max #stores to inline memmove"));
100 cl::desc(
"Max #stores to inline memset"));
104 cl::desc(
"Max #stores to inline memset"));
109 class HexagonCCState :
public CCState {
110 unsigned NumNamedVarArgParams;
115 int NumNamedVarArgParams)
116 :
CCState(CC, isVarArg, MF, locs, C),
117 NumNamedVarArgParams(NumNamedVarArgParams) {}
119 unsigned getNumNamedVarArgParams()
const {
return NumNamedVarArgParams; }
178 HexagonCCState &HState =
static_cast<HexagonCCState &
>(State);
180 if (ValNo < HState.getNumNamedVarArgParams()) {
182 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
200 else if (ArgFlags.
isZExt())
264 else if (ArgFlags.
isZExt())
277 if (!
CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
282 if (!
CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
327 Hexagon::D1, Hexagon::D2
330 Hexagon::R1, Hexagon::R3
347 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
348 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
352 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
353 Hexagon::W5, Hexagon::W6, Hexagon::W7
358 bool UseHVXDbl = HST.useHVXDblOps();
360 if ((UseHVX && !UseHVXDbl) &&
371 if ((UseHVX && !UseHVXDbl) &&
383 if ((UseHVX && UseHVXDbl) &&
394 if ((UseHVX && UseHVXDbl) &&
414 bool UseHVXDbl = HST.useHVXDblOps();
426 else if (ArgFlags.
isZExt())
477 static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
512 bool UseHVXDbl = HST.useHVXDblOps();
514 unsigned OffSiz = 64;
521 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
540 void HexagonTargetLowering::promoteLdStType(
MVT VT,
MVT PromotedLdStVT) {
541 if (VT != PromotedLdStVT) {
616 for (
unsigned i = 0;
i != RVLocs.
size(); ++
i) {
639 if (!CI->
isTailCall() || Attr.getValueAsString() ==
"true")
664 for (
unsigned i = 0;
i != RVLocs.
size(); ++
i) {
666 if (RVLocs[
i].getValVT() ==
MVT::i1) {
676 unsigned PredR =
MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
684 RVLocs[
i].getValVT(), InFlag);
711 bool IsStructRet = (Outs.
empty()) ?
false : Outs[0].
Flags.isSRet();
716 unsigned NumNamedVarArgParams = -1U;
720 if (
const Function*
F = dyn_cast<Function>(GV)) {
724 if (
F->isVarArg() &&
F->getFunctionType()->getNumParams() != 0)
725 NumNamedVarArgParams =
F->getFunctionType()->getNumParams();
740 if (Attr.getValueAsString() ==
"true")
746 IsVarArg, IsStructRet,
748 Outs, OutVals, Ins, DAG);
749 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
756 DEBUG(
dbgs() << (IsTailCall ?
"Eligible for Tail Call\n"
757 :
"Argument must be passed on stack. "
758 "Not eligible for Tail Call\n"));
761 unsigned NumBytes = CCInfo.getNextStackOffset();
769 bool NeedsArgAlign =
false;
770 unsigned LargestAlignSeen = 0;
772 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
805 LargestAlignSeen = std::max(LargestAlignSeen,
827 if (NeedsArgAlign && Subtarget.
hasV60TOps()) {
828 DEBUG(
dbgs() <<
"Function needs byte stack align due to call args\n");
834 const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
835 LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
840 if (!MemOpChains.
empty())
854 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i) {
856 RegsToPass[
i].second, Glue);
871 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i) {
873 RegsToPass[
i].second, Glue);
888 dyn_cast<ExternalSymbolSDNode>(Callee)) {
900 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i) {
902 RegsToPass[i].second.getValueType()));
914 Chain = DAG.
getNode(OpCode, dl, NodeTys, Ops);
925 InVals, OutVals, Callee);
936 bool UseHVXDbl = HST.useHVXDblOps();
938 bool ValidHVXDblType =
945 if (ValidHVXDblType || ValidHVXType ||
951 return isa<ConstantSDNode>(
Offset);
970 VT =
LD->getMemoryVT();
972 VT =
ST->getMemoryVT();
973 if (
ST->getValue().getValueType() ==
MVT::i64 &&
ST->isTruncatingStore())
983 int32_t OffsetVal = cast<ConstantSDNode>(Offset.
getNode())->getSExtValue();
984 if (HII.isValidAutoIncImm(VT, OffsetVal)) {
1005 if (FuncInfo.hasClobberLR())
1008 cast<ConstantSDNode>(Node->
getOperand(
i))->getZExtValue();
1019 for (; NumVals; --NumVals, ++
i) {}
1023 for (; NumVals; --NumVals, ++
i) {
1030 FuncInfo.setHasClobberLR(
true);
1060 unsigned IntNo = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
1062 if (IntNo == Intrinsic::hexagon_prefetch) {
1080 assert(AlignConst &&
"Non-constant Align in LowerDYNAMIC_STACKALLOC");
1086 A = HFI.getStackAlignment();
1089 dbgs () << __func__ <<
" Align: " << A <<
" Size: ";
1128 for (
unsigned i = 0, e = ArgLocs.size();
i != e; ++
i) {
1132 unsigned StackLocation;
1160 }
else if (UseHVX && UseHVXDbl &&
1175 }
else if (UseHVX && UseHVXDbl &&
1183 assert(0 &&
"need to support VecPred regs");
1192 assert (0 &&
"ByValSize must be bigger than 8 bytes");
1225 if (!MemOps.
empty())
1232 CCInfo.getNextStackOffset(),
1234 FuncInfo.setVarArgsFrameIndex(FrameIndex);
1278 if (isa<ConstantSDNode>(InpVal)) {
1279 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
1371 if (Alignment == 2) {
1406 Loads[0].getValue(1), Loads[1].getValue(1),
1407 Loads[2].getValue(1), Loads[3].getValue(1));
1421 SDValue Ops[] = { Result, LoadChain };
1443 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1444 "Inconsistent target flag encountered");
1446 if (IsPositionIndependent)
1454 int Idx = cast<JumpTableSDNode>(
Op)->getIndex();
1476 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1498 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1516 auto *GAN = cast<GlobalAddressSDNode>(
Op);
1518 auto *GV = GAN->getGlobal();
1519 int64_t
Offset = GAN->getOffset();
1527 if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
1549 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
1630 if (IsPositionIndependent) {
1901 for (
unsigned IntExpOp :
1910 for (
unsigned FPExpOp :
1958 static const unsigned VectExpOps[] = {
1984 for (
unsigned VectExpOp : VectExpOps)
2045 }
else if (UseHVXDbl) {
2102 for (
unsigned FPExpOpV4 :
2129 }
else if (UseHVXDbl) {
2324 unsigned DefinedValues)
const {
2328 if ((EltBits != 8) && (EltBits != 16))
2335 int even_start = -2;
2337 size_t mask_len = Mask.
size();
2338 for (
auto idx : Mask) {
2339 if ((idx - even_start) == 2)
2344 if (even_start == (
int)(mask_len * 2) - 2)
2345 return StridedLoadKind::Even;
2346 for (
auto idx : Mask) {
2347 if ((idx - odd_start) == 2)
2352 if (odd_start == (
int)(mask_len * 2) - 1)
2353 return StridedLoadKind::Odd;
2355 return StridedLoadKind::NoPattern;
2382 if (Lane == -1) Lane = 0;
2386 return createSplat(DAG, dl, VT, V1.getOperand(0));
2392 !isa<ConstantSDNode>(V1.getOperand(0))) {
2393 bool IsScalarToVector =
true;
2394 for (
unsigned i = 1, e = V1.getNumOperands();
i != e; ++
i) {
2395 if (!V1.getOperand(
i).isUndef()) {
2396 IsScalarToVector =
false;
2400 if (IsScalarToVector)
2401 return createSplat(DAG, dl, VT, V1.getOperand(0));
2408 size_t MaskLen = Mask.
size();
2410 if ((Subtarget.
useHVXSglOps() && (ElemSizeInBits * MaskLen) == 64 * 8) ||
2411 (Subtarget.
useHVXDblOps() && (ElemSizeInBits * MaskLen) == 128 * 8)) {
2415 if (Pattern == StridedLoadKind::NoPattern)
2421 SDValue Ops[] = { Vec1, Vec0, StridePattern };
2445 for (
unsigned i = 1, e = NElts;
i != e; ++
i) {
2464 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.
getNode())) &&
2467 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.
getNode())) &&
2523 APInt APSplatBits, APSplatUndef;
2524 unsigned SplatBitSize;
2531 HasAnyUndefs, 0,
true) && SplatBitSize <= 16)) {
2533 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
2534 (32 - SplatBitSize));
2564 for (
unsigned i = 0, e = NElts;
i != e; ++
i) {
2583 unsigned EltSize = Size / NElts;
2585 uint64_t
Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2586 bool HasNonConstantElements =
false;
2588 for (
unsigned i = 0, e = NElts;
i != e; ++
i) {
2591 unsigned OpIdx = NElts -
i - 1;
2598 Val = Cst->getSExtValue();
2600 HasNonConstantElements =
true;
2603 Res = (Res << EltSize) | Val;
2616 if (HasNonConstantElements) {
2622 for (
unsigned i = 0, e = NElts;
i != e; ++
i) {
2625 unsigned OpIdx = NElts -
i - 1;
2627 if (isa<ConstantSDNode>(Operand))
2640 const SDValue Ops[] = {ConstVal, Operand, Combined};
2693 for (
unsigned i = 0, e = NElts;
i != e; ++
i) {
2694 unsigned N = NElts-
i-1;
2716 HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(
SDValue Op,
2729 unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);
2734 if (!(ResVT.
isByteSized() && ResSize == VectorSizeInBits) ||
2735 !(VT.
isByteSized() && OpSize == 2 * VectorSizeInBits))
2775 EltSize : VTN * EltSize, dl,
MVT::i64);
2779 uint64_t
X = CI->getZExtValue();
2781 const SDValue Ops[] = {Vec, Width, Offset};
2784 assert(CW &&
"Non constant width in LowerEXTRACT_VECTOR");
2792 unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
2795 Subreg = Hexagon::isub_lo;
2797 Subreg = Hexagon::isub_hi;
2799 Subreg = Hexagon::isub_hi;
2801 Subreg = Hexagon::isub_hi;
2825 const SDValue Ops[] = {Vec, Combined};
2851 EltSize : VTN * EltSize, dl,
MVT::i64);
2855 const SDValue Ops[] = {Vec, Val, Width, Offset};
2880 const SDValue Ops[] = {Vec, Val, Combined};
2919 unsigned OffsetReg = Hexagon::R28;
2925 Chain = DAG.
getCopyToReg(Chain, dl, OffsetReg, Offset);
2941 errs() <<
"Check for a non-legal type in this operation\n";
2983 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2995 if (Constraint.
size() == 1) {
2996 switch (Constraint[0]) {
3007 std::pair<unsigned, const TargetRegisterClass*>
3012 if (Constraint.
size() == 1) {
3013 switch (Constraint[0]) {
3023 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
3026 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
3038 return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
3048 return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
3053 if (Subtarget.
hasV60TOps() && UseHVX && UseHVXDbl)
3054 return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
3055 return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
3060 return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
3082 unsigned AS)
const {
3104 int Scale = AM.
Scale;
3128 return Imm >= -512 && Imm <= 511;
3138 bool isCalleeStructRet,
3139 bool isCallerStructRet,
3146 bool CCMatch = CallerCC == CalleeCC;
3154 if (!isa<GlobalAddressSDNode>(Callee) &&
3155 !isa<ExternalSymbolSDNode>(Callee)) {
3175 if (isCalleeStructRet || isCallerStructRet)
3197 unsigned DstAlign,
unsigned SrcAlign,
bool IsMemset,
bool ZeroMemset,
3200 auto Aligned = [](
unsigned GivenA,
unsigned MinA) ->
bool {
3201 return (GivenA % MinA) == 0;
3204 if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3206 if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3208 if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3215 unsigned AS,
unsigned Align,
bool *
Fast)
const {
3239 std::pair<const TargetRegisterClass*, uint8_t>
3252 RRC = &Hexagon::VectorRegsRegClass;
3260 RRC = &Hexagon::VectorRegs128BRegClass;
3262 RRC = &Hexagon::VecDblRegsRegClass;
3268 RRC = &Hexagon::VecDblRegs128BRegClass;
3271 return std::make_pair(RRC, Cost);
3278 Type *Ty = cast<PointerType>(Addr->
getType())->getElementType();
3280 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic loads supported");
3281 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3282 : Intrinsic::hexagon_L4_loadd_locked;
3295 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic stores supported");
3296 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3297 : Intrinsic::hexagon_S4_stored_locked;
3322 return Size >= 4 && Size <= 8;
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
Value * getValueOperand()
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
A parsed version of the target data layout string in and methods for querying it. ...
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Flags getFlags() const
Return the raw flags of the source value,.
LLVMContext * getContext() const
uint64_t getZExtValue() const
Get zero extended value.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
BR_CC - Conditional branch.
LocInfo getLocInfo() const
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
void setHasEHReturn(bool H=true)
A Module instance is used to store all the information related to an LLVM module. ...
const TargetMachine & getTargetMachine() const
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
HexagonTargetObjectFile * getObjFileLowering() const override
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
int getSplatIndex() const
Carry-setting nodes for multiple precision addition and subtraction.
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Y = RRC X, rotate right via carry.
const TargetSubtargetInfo & getSubtarget() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
This class represents a function call, abstracting a target machine's calling convention.
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
const GlobalValue * getGlobal() const
unsigned getRARegister() const
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
constexpr bool isInt< 8 >(int64_t x)
unsigned getSizeInBits() const
unsigned getByValSize() const
static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Hexagon target-specific information for each MachineFunction.
unsigned getNumOperands() const
Return the number of values used by this operation.
const Function * getParent() const
Return the enclosing method, or null if none.
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned Num) const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
An instruction for reading from memory.
const HexagonFrameLowering * getFrameLowering() const override
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
const SDValue & getBasePtr() const
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
void dumpr() const
Dump (recursively) this node and its use-def subgraph.
SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
bool isNegative() const
Determine sign of this APInt.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
bool useHVXDblOps() const
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
struct fuzzer::@269 Flags
int64_t getOffset() const
Shift and rotation operations.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
MachineFunction & getMachineFunction() const
const HexagonRegisterInfo * getRegisterInfo() const override
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void addLoc(const CCValAssign &V)
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Reg
All possible values of the reg field in the ModR/M byte.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
#define Hexagon_PointerSize
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool isPositionIndependent() const
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
INLINEASM - Represents an inline asm block.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_NODISCARD bool empty() const
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM's memory model.
STACKSAVE - STACKSAVE has one operand, an input chain.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
MachineFunction & getMachineFunction() const
static SDValue createSplat(SelectionDAG &DAG, const SDLoc &dl, EVT VT, SDValue Val)
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
bool useHVXSglOps() const
Simple integer binary arithmetic operators.
static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
MachineConstantPoolValue * getMachineCPVal() const
An instruction for storing to memory.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
Value * CreateZExt(Value *V, Type *DestTy, const Twine &Name="")
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
size_t size() const
size - Get the array size.
const DataLayout & getDataLayout() const
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset)
Stack pointer relative access.
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
This class is used to represent ISD::STORE nodes.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getScalarSizeInBits() const
initializer< Ty > init(const Ty &Val)
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
unsigned const MachineRegisterInfo * MRI
bool isMachineConstantPoolEntry() const
MVT - Machine Value Type.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Simple binary floating point operators.
C - The default llvm calling convention, compatible with C.
static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, SDValue &Base, SDValue &Offset, bool &IsInc, SelectionDAG &DAG)
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Value * getCompareOperand()
static bool CC_Hexagon(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const Constant * getConstVal() const
Carry-using nodes for multiple precision addition and subtraction.
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
static mvt_range fp_valuetypes()
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
static unsigned getKind(unsigned Flags)
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
static mvt_range vector_valuetypes()
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
Value * CreateICmpEQ(Value *LHS, Value *RHS, const Twine &Name="")
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
This structure contains all information that is necessary for lowering calls.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
static bool isSExtFree(SDValue N)
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
static bool CC_HexagonVector(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
const MachinePointerInfo & getPointerInfo() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
unsigned getByValAlign() const
bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
ArrayRef< int > getMask() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
#define HEXAGON_LRFP_SIZE
CCState - This class holds information needed while lowering arguments and return values...
unsigned countPopulation(T Value)
Count the number of set bits in a value.
void dump() const
Dump this node, for debugging.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
#define HEXAGON_GOT_SYM_NAME
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
static bool isHvxVectorType(MVT ty)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
const SDValue & getChain() const
Byte Swap and Counting operators.
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
CHAIN = SC CHAIN, Imm128 - System call.
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
ConstantInt * getInt32(uint32_t C)
Get a constant 32-bit value.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
BasicBlock * GetInsertBlock() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
void setAdjustsStack(bool V)
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static mvt_range integer_valuetypes()
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Class for arbitrary precision integers.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
bool isIntegerTy() const
True if this is an instance of IntegerType.
static StridedLoadKind isStridedLoad(const ArrayRef< int > &Mask)
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
void setPrefLoopAlignment(unsigned Align)
Set the target's preferred loop alignment.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
const GlobalObject * getBaseObject() const
ANY_EXTEND - Used for integer types. The high bits are undefined.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
static cl::opt< int > MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::ZeroOrMore, cl::init(8), cl::desc("Max #stores to inline memset"))
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
BR_JT - Jumptable branch.
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
SmallVector< SDValue, 32 > OutVals
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
void ensureMaxAlignment(unsigned Align)
Make sure the function is at least Align bytes aligned.
Bitwise operators - logical and, logical or, logical xor.
MO_GOT - Indicates a GOT-relative relocation.
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
int getVarArgsFrameIndex()
unsigned getStoreSizeInBits() const
getStoreSizeInBits - Return the number of bits overwritten by a store of the specified value type...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static cl::opt< int > MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memcpy"))
CallInst * CreateCall(Value *Callee, ArrayRef< Value * > Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
static bool CC_Hexagon_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
FSINCOS - Compute both fsin and fcos as a single operation.
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
getEVT - Return the value type corresponding to the specified type.
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
unsigned getAlignment() const
static cl::opt< int > MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::ZeroOrMore, cl::init(6), cl::desc("Max #stores to inline memcpy"))
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
const HexagonInstrInfo * getInstrInfo() const override
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
PREFETCH - This corresponds to a prefetch intrinsic.
static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
Primary interface to the complete machine description for the target machine.
static bool isCommonSplatElement(BuildVectorSDNode *BVN)
StringRef - Represent a constant reference to a string, i.e.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame)...
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
unsigned getLocMemOffset() const
MVT getVectorElementType() const
SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
static cl::opt< int > MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::ZeroOrMore, cl::init(6), cl::desc("Max #stores to inline memmove"))
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
static cl::opt< int > MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memset"))
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
static cl::opt< bool > EnableFastMath("ffast-math", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Fast Math processing"))
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
const BasicBlock * getParent() const
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
LLVMContext & getContext() const
Get the global data context.
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
uint64_t getZExtValue() const
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...