LLVM  4.0.0
Macros | Functions
AArch64RegisterBankInfo.cpp File Reference

This file implements the targeting of the RegisterBankInfo class for AArch64. More...

#include "AArch64RegisterBankInfo.h"
#include "AArch64InstrInfo.h"
#include "llvm/CodeGen/LowLevelType.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include "AArch64GenRegisterBankInfo.def"
Include dependency graph for AArch64RegisterBankInfo.cpp:

Go to the source code of this file.

Macros

#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB)
 
#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset)
 
#define CHECK_VALUEMAP(RBName, Size)   CHECK_VALUEMAP_IMPL(RBName, Size, 0)
 
#define CHECK_VALUEMAP_3OPS(RBName, Size)
 
#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size)
 

Functions

static bool isPreISelGenericFloatingPointOpcode (unsigned Opc)
 Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point operands. More...
 

Detailed Description

This file implements the targeting of the RegisterBankInfo class for AArch64.

Todo:
This should be generated by TableGen.

Definition in file AArch64RegisterBankInfo.cpp.

Macro Definition Documentation

#define CHECK_PARTIALMAP (   Idx,
  ValStartIdx,
  ValLength,
  RB 
)
Value:
do { \
AArch64::PartMappings[AArch64::PartialMappingIdx::Idx - \
AArch64::PartialMappingIdx::PMI_Min]; \
(void)Map; \
assert(Map.StartIdx == ValStartIdx && Map.Length == ValLength && \
Map.RegBank == &RB && #Idx " is incorrectly initialized"); \
} while (0)
Helper struct that represents how a value is partially mapped into a register.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo().

#define CHECK_VALUEMAP (   RBName,
  Size 
)    CHECK_VALUEMAP_IMPL(RBName, Size, 0)
#define CHECK_VALUEMAP_3OPS (   RBName,
  Size 
)
Value:
do { \
CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
} while (0)
#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset)

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo().

#define CHECK_VALUEMAP_CROSSREGCPY (   RBNameDst,
  RBNameSrc,
  Size 
)
Value:
do { \
unsigned PartialMapDstIdx = \
AArch64::PMI_##RBNameDst##Size - AArch64::PMI_Min; \
unsigned PartialMapSrcIdx = \
AArch64::PMI_##RBNameSrc##Size - AArch64::PMI_Min; \
(void) PartialMapDstIdx; \
(void) PartialMapSrcIdx; \
const ValueMapping *Map = AArch64::getCopyMapping( \
AArch64::PMI_First##RBNameDst == AArch64::PMI_FirstGPR, \
AArch64::PMI_First##RBNameSrc == AArch64::PMI_FirstGPR, Size); \
(void) Map; \
assert(Map[0].BreakDown == &AArch64::PartMappings[PartialMapDstIdx] && \
Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
" Dst is incorrectly initialized"); \
assert(Map[1].BreakDown == &AArch64::PartMappings[PartialMapSrcIdx] && \
Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
" Src is incorrectly initialized"); \
\
} while (0)
Helper struct that represents how a value is mapped through different register banks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo().

#define CHECK_VALUEMAP_IMPL (   RBName,
  Size,
  Offset 
)
Value:
do { \
unsigned PartialMapBaseIdx = \
AArch64::PartialMappingIdx::PMI_##RBName##Size - \
AArch64::PartialMappingIdx::PMI_Min; \
(void)PartialMapBaseIdx; \
AArch64::PartialMappingIdx::PMI_First##RBName, Size)[Offset]; \
(void)Map; \
assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] && \
Map.NumBreakDowns == 1 && #RBName #Size \
" " #Offset " is incorrectly initialized"); \
} while (0)
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Methods to get a uniquely generated ValueMapping.
uint32_t Offset
Helper struct that represents how a value is mapped through different register banks.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const

Function Documentation

static bool isPreISelGenericFloatingPointOpcode ( unsigned  Opc)
static

Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point operands.

Definition at line 386 of file AArch64RegisterBankInfo.cpp.

Referenced by llvm::AArch64RegisterBankInfo::getInstrMapping().