23 #ifndef LLVM_BUILD_GLOBAL_ISEL
24 #error "You shouldn't build this"
34 (1u << ARM::GPRRegClassID) | (1u << ARM::GPRwithAPSRRegClassID) |
35 (1u << ARM::GPRnopcRegClassID) | (1u << ARM::rGPRRegClassID) |
36 (1u << ARM::hGPRRegClassID) | (1u << ARM::tGPRRegClassID) |
37 (1u << ARM::GPRnopc_and_hGPRRegClassID) |
38 (1u << ARM::hGPR_and_rGPRRegClassID) | (1u << ARM::tcGPRRegClassID) |
39 (1u << ARM::tGPR_and_tcGPRRegClassID) | (1u << ARM::GPRspRegClassID) |
40 (1u << ARM::hGPR_and_tcGPRRegClassID),
70 static bool AlreadyInit =
false;
86 "Subclass not added?");
88 "Subclass not added?");
90 "Subclass not added?");
92 "Subclass not added?");
94 "Subclass not added?");
96 "Subclass not added?");
98 "Subclass not added?");
99 assert(RBGPR.
getSize() == 32 &&
"GPRs should hold up to 32-bit");
106 switch (RC.
getID()) {
108 case tGPR_and_tcGPRRegClassID:
129 using namespace TargetOpcode;
RegisterBank ** RegBanks
Hold the set of supported register banks.
RegisterBankInfo::PartialMapping GPRPartialMapping
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getID() const
Return the register class ID number.
setjmp/longjmp based exceptions
const uint32_t GPRCoverageData[]
Holds all the information related to register banks.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Methods to get a uniquely generated array of ValueMapping.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
This file declares the targeting of the RegisterBankInfo class for ARM.
RegisterBankInfo::ValueMapping ValueMappings[]
Helper struct that represents how a value is partially mapped into a register.
Conditional register: NZCV.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
RegisterBank GPRRegBank(ARM::GPRRegBankID,"GPRB", 32, ARM::GPRCoverageData)
This class implements the register bank concept.
Helper struct that represents how a value is mapped through different register banks.
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
bool isValid() const
Check whether this object is valid.
Representation of each machine instruction.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const override
Get a register bank that covers RC.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
InstructionMapping getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
RegisterBank * RegBanks[]