LLVM  4.0.0
SystemZISelLowering.h
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1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17 
18 #include "SystemZ.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
27 
28  // Return with a flag operand. Operand 0 is the chain operand.
30 
31  // Calls a function. Operand 0 is the chain operand and operand 1
32  // is the target address. The arguments start at operand 2.
33  // There is an optional glue operand at the end.
36 
37  // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38  // (The call target is implicitly __tls_get_offset.)
41 
42  // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43  // accesses (LARL). Operand 0 is the address.
45 
46  // Used in cases where an offset is applied to a TargetGlobalAddress.
47  // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48  // PCREL_WRAPPER for an anchor point. This is used so that we can
49  // cheaply refer to either the full address or the anchor point
50  // as a register base.
52 
53  // Integer absolute.
55 
56  // Integer comparisons. There are three operands: the two values
57  // to compare, and an integer of type SystemZICMP.
59 
60  // Floating-point comparisons. The two operands are the values to compare.
62 
63  // Test under mask. The first operand is ANDed with the second operand
64  // and the condition codes are set on the result. The third operand is
65  // a boolean that is true if the condition codes need to distinguish
66  // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67  // register forms do but the memory forms don't).
68  TM,
69 
70  // Branches if a condition is true. Operand 0 is the chain operand;
71  // operand 1 is the 4-bit condition-code mask, with bit N in
72  // big-endian order meaning "branch if CC=N"; operand 2 is the
73  // target block and operand 3 is the flag operand.
75 
76  // Selects between operand 0 and operand 1. Operand 2 is the
77  // mask of condition-code values for which operand 0 should be
78  // chosen over operand 1; it has the same form as BR_CCMASK.
79  // Operand 3 is the flag operand.
81 
82  // Evaluates to the gap between the stack pointer and the
83  // base of the dynamically-allocatable area.
85 
86  // Count number of bits set in operand 0 per byte.
88 
89  // Wrappers around the ISD opcodes of the same name. The output and
90  // first input operands are GR128s. The trailing numbers are the
91  // widths of the second operand in bits.
97 
98  // Use a series of MVCs to copy bytes from one memory location to another.
99  // The operands are:
100  // - the target address
101  // - the source address
102  // - the constant length
103  //
104  // This isn't a memory opcode because we'd need to attach two
105  // MachineMemOperands rather than one.
107 
108  // Like MVC, but implemented as a loop that handles X*256 bytes
109  // followed by straight-line code to handle the rest (if any).
110  // The value of X is passed as an additional operand.
112 
113  // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
114  NC,
116  OC,
118  XC,
120 
121  // Use CLC to compare two blocks of memory, with the same comments
122  // as for MVC and MVC_LOOP.
125 
126  // Use an MVST-based sequence to implement stpcpy().
128 
129  // Use a CLST-based sequence to implement strcmp(). The two input operands
130  // are the addresses of the strings to compare.
132 
133  // Use an SRST-based sequence to search a block of memory. The first
134  // operand is the end address, the second is the start, and the third
135  // is the character to search for. CC is set to 1 on success and 2
136  // on failure.
138 
139  // Store the CC value in bits 29 and 28 of an integer.
141 
142  // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
144 
145  // Compiler barrier only; generate a no-op.
147 
148  // Transaction begin. The first operand is the chain, the second
149  // the TDB pointer, and the third the immediate control field.
150  // Returns chain and glue.
153 
154  // Transaction end. Just the chain operand. Returns chain and glue.
156 
157  // Create a vector constant by filling byte N of the result with bit
158  // 15-N of the single operand.
160 
161  // Create a vector constant by replicating an element-sized RISBG-style mask.
162  // The first operand specifies the starting set bit and the second operand
163  // specifies the ending set bit. Both operands count from the MSB of the
164  // element.
166 
167  // Replicate a GPR scalar value into all elements of a vector.
169 
170  // Create a vector from two i64 GPRs.
172 
173  // Replicate one element of a vector into all elements. The first operand
174  // is the vector and the second is the index of the element to replicate.
176 
177  // Interleave elements from the high half of operand 0 and the high half
178  // of operand 1.
180 
181  // Likewise for the low halves.
183 
184  // Concatenate the vectors in the first two operands, shift them left
185  // by the third operand, and take the first half of the result.
187 
188  // Take one element of the first v2i64 operand and the one element of
189  // the second v2i64 operand and concatenate them to form a v2i64 result.
190  // The third operand is a 4-bit value of the form 0A0B, where A and B
191  // are the element selectors for the first operand and second operands
192  // respectively.
194 
195  // Perform a general vector permute on vector operands 0 and 1.
196  // Each byte of operand 2 controls the corresponding byte of the result,
197  // in the same way as a byte-level VECTOR_SHUFFLE mask.
199 
200  // Pack vector operands 0 and 1 into a single vector with half-sized elements.
202 
203  // Likewise, but saturate the result and set CC. PACKS_CC does signed
204  // saturation and PACKLS_CC does unsigned saturation.
207 
208  // Unpack the first half of vector operand 0 into double-sized elements.
209  // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
212 
213  // Likewise for the second half.
216 
217  // Shift each element of vector operand 0 by the number of bits specified
218  // by scalar operand 1.
222 
223  // For each element of the output type, sum across all sub-elements of
224  // operand 0 belonging to the corresponding element, and add in the
225  // rightmost sub-element of the corresponding element of operand 1.
227 
228  // Compare integer vector operands 0 and 1 to produce the usual 0/-1
229  // vector result. VICMPE is for equality, VICMPH for "signed greater than"
230  // and VICMPHL for "unsigned greater than".
234 
235  // Likewise, but also set the condition codes on the result.
239 
240  // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
241  // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
242  // greater than" and VFCMPHE for "ordered and greater than or equal to".
246 
247  // Likewise, but also set the condition codes on the result.
251 
252  // Test floating-point data class for vectors.
254 
255  // Extend the even f32 elements of vector operand 0 to produce a vector
256  // of f64 elements.
258 
259  // Round the f64 elements of vector operand 0 to f32s and store them in the
260  // even elements of the result.
262 
263  // AND the two vector operands together and set CC based on the result.
265 
266  // String operations that set CC as a side-effect.
276 
277  // Test Data Class.
278  //
279  // Operand 0: the value to test
280  // Operand 1: the bit mask
282 
283  // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
284  // ATOMIC_LOAD_<op>.
285  //
286  // Operand 0: the address of the containing 32-bit-aligned field
287  // Operand 1: the second operand of <op>, in the high bits of an i32
288  // for everything except ATOMIC_SWAPW
289  // Operand 2: how many bits to rotate the i32 left to bring the first
290  // operand into the high bits
291  // Operand 3: the negative of operand 2, for rotating the other way
292  // Operand 4: the width of the field in bits (8 or 16)
304 
305  // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
306  //
307  // Operand 0: the address of the containing 32-bit-aligned field
308  // Operand 1: the compare value, in the low bits of an i32
309  // Operand 2: the swap value, in the low bits of an i32
310  // Operand 3: how many bits to rotate the i32 left to bring the first
311  // operand into the high bits
312  // Operand 4: the negative of operand 2, for rotating the other way
313  // Operand 5: the width of the field in bits (8 or 16)
315 
316  // Byte swapping load.
317  //
318  // Operand 0: the address to load from
319  // Operand 1: the type of load (i16, i32, i64)
321 
322  // Byte swapping store.
323  //
324  // Operand 0: the value to store
325  // Operand 1: the address to store to
326  // Operand 2: the type of store (i16, i32, i64)
328 
329  // Prefetch from the second operand using the 4-bit control code in
330  // the first operand. The code is 1 for a load prefetch and 2 for
331  // a store prefetch.
333 };
334 
335 // Return true if OPCODE is some kind of PC-relative address.
336 inline bool isPCREL(unsigned Opcode) {
337  return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
338 }
339 } // end namespace SystemZISD
340 
341 namespace SystemZICMP {
342 // Describes whether an integer comparison needs to be signed or unsigned,
343 // or whether either type is OK.
344 enum {
348 };
349 } // end namespace SystemZICMP
350 
351 class SystemZSubtarget;
352 class SystemZTargetMachine;
353 
355 public:
356  explicit SystemZTargetLowering(const TargetMachine &TM,
357  const SystemZSubtarget &STI);
358 
359  // Override TargetLowering.
360  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
361  return MVT::i32;
362  }
363  MVT getVectorIdxTy(const DataLayout &DL) const override {
364  // Only the lower 12 bits of an element index are used, so we don't
365  // want to clobber the upper 32 bits of a GPR unnecessarily.
366  return MVT::i32;
367  }
369  const override {
370  // Widen subvectors to the full width rather than promoting integer
371  // elements. This is better because:
372  //
373  // (a) it means that we can handle the ABI for passing and returning
374  // sub-128 vectors without having to handle them as legal types.
375  //
376  // (b) we don't have instructions to extend on load and truncate on store,
377  // so promoting the integers is less efficient.
378  //
379  // (c) there are no multiplication instructions for the widest integer
380  // type (v2i64).
381  if (VT.getScalarSizeInBits() % 8 == 0)
382  return TypeWidenVector;
384  }
386  EVT) const override;
387  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
388  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
389  bool isLegalICmpImmediate(int64_t Imm) const override;
390  bool isLegalAddImmediate(int64_t Imm) const override;
391  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
392  unsigned AS) const override;
393  bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const override;
394  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
395  unsigned Align,
396  bool *Fast) const override;
397  bool isTruncateFree(Type *, Type *) const override;
398  bool isTruncateFree(EVT, EVT) const override;
399  const char *getTargetNodeName(unsigned Opcode) const override;
400  std::pair<unsigned, const TargetRegisterClass *>
402  StringRef Constraint, MVT VT) const override;
404  getConstraintType(StringRef Constraint) const override;
406  getSingleConstraintMatchWeight(AsmOperandInfo &info,
407  const char *constraint) const override;
409  std::string &Constraint,
410  std::vector<SDValue> &Ops,
411  SelectionDAG &DAG) const override;
412 
413  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
414  if (ConstraintCode.size() == 1) {
415  switch(ConstraintCode[0]) {
416  default:
417  break;
418  case 'Q':
420  case 'R':
422  case 'S':
424  case 'T':
426  }
427  }
428  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
429  }
430 
431  /// If a physical register, this returns the register that receives the
432  /// exception address on entry to an EH pad.
433  unsigned
434  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
435  return SystemZ::R6D;
436  }
437 
438  /// If a physical register, this returns the register that receives the
439  /// exception typeid on entry to a landing pad.
440  unsigned
441  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
442  return SystemZ::R7D;
443  }
444 
445  /// Override to support customized stack guard loading.
446  bool useLoadStackGuardNode() const override {
447  return true;
448  }
449  void insertSSPDeclarations(Module &M) const override {
450  }
451 
454  MachineBasicBlock *BB) const override;
455  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
456  bool allowTruncateForTailCall(Type *, Type *) const override;
457  bool mayBeEmittedAsTailCall(CallInst *CI) const override;
459  bool isVarArg,
461  const SDLoc &DL, SelectionDAG &DAG,
462  SmallVectorImpl<SDValue> &InVals) const override;
463  SDValue LowerCall(CallLoweringInfo &CLI,
464  SmallVectorImpl<SDValue> &InVals) const override;
465 
467  bool isVarArg,
469  LLVMContext &Context) const override;
470  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
472  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
473  SelectionDAG &DAG) const override;
475  SelectionDAG &DAG) const override;
476  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
477 
479  return ISD::ANY_EXTEND;
480  }
481 
482  bool supportSwiftError() const override {
483  return true;
484  }
485 
486 private:
487  const SystemZSubtarget &Subtarget;
488 
489  // Implement LowerOperation for individual opcodes.
490  SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
491  SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
492  SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
493  SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
494  SelectionDAG &DAG) const;
495  SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
496  SelectionDAG &DAG, unsigned Opcode,
497  SDValue GOTOffset) const;
498  SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
499  SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
500  SelectionDAG &DAG) const;
501  SDValue lowerBlockAddress(BlockAddressSDNode *Node,
502  SelectionDAG &DAG) const;
503  SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
504  SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
505  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
506  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
507  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
508  SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
509  SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
510  SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
511  SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
512  SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
513  SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
514  SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
515  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
516  SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
517  SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
518  SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
519  SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
520  SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
521  SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
522  unsigned Opcode) const;
523  SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
524  SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
525  SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
526  SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
527  SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
528  SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
529  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
530  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
531  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
532  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
533  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
534  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
535  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
536  SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
537  unsigned UnpackHigh) const;
538  SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
539 
540  SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
541  unsigned Index, DAGCombinerInfo &DCI,
542  bool Force) const;
543  SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
544  DAGCombinerInfo &DCI) const;
545  SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
546  SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
547  SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
548  SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
549  SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
550  SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
551  SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
552  SDValue combineSHIFTROT(SDNode *N, DAGCombinerInfo &DCI) const;
553 
554  // If the last instruction before MBBI in MBB was some form of COMPARE,
555  // try to replace it with a COMPARE AND BRANCH just before MBBI.
556  // CCMask and Target are the BRC-like operands for the branch.
557  // Return true if the change was made.
558  bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
560  unsigned CCMask,
561  MachineBasicBlock *Target) const;
562 
563  // Implement EmitInstrWithCustomInserter for individual operation types.
565  unsigned LOCROpcode) const;
566  MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
567  unsigned StoreOpcode, unsigned STOCOpcode,
568  bool Invert) const;
570  bool ClearEven, unsigned SubReg) const;
571  MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
572  MachineBasicBlock *BB,
573  unsigned BinOpcode, unsigned BitSize,
574  bool Invert = false) const;
575  MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
577  unsigned CompareOpcode,
578  unsigned KeepOldMask,
579  unsigned BitSize) const;
580  MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
581  MachineBasicBlock *BB) const;
582  MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
583  unsigned Opcode) const;
584  MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
585  unsigned Opcode) const;
586  MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
588  unsigned Opcode, bool NoFloat) const;
589  MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
591  unsigned Opcode) const;
592 };
593 } // end namespace llvm
594 
595 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
LLVMContext & Context
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
This class represents a function call, abstracting a target machine's calling convention.
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
MVT getVectorIdxTy(const DataLayout &DL) const override
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
lazy value info
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
unsigned SubReg
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MachineBasicBlock * MBB
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const override
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:262
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
This is an important base class in LLVM.
Definition: Constant.h:42
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
uint32_t Offset
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isPCREL(unsigned Opcode)
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:769
Represents one node in the SelectionDAG.
Target - Wrapper for Target specific information.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:403
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Representation of each machine instruction.
Definition: MachineInstr.h:52
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const override
This callback is used to prepare for a volatile or atomic load.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
This file describes how to lower LLVM code to machine code.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.