LLVM  4.0.0
TargetSubtargetInfo.h
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1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the subtarget options of a Target machine.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
24 #include "llvm/Support/CodeGen.h"
25 #include <memory>
26 #include <vector>
27 
28 namespace llvm {
29 
30 class CallLowering;
31 class InstructionSelector;
32 class LegalizerInfo;
33 class MachineInstr;
34 class RegisterBankInfo;
35 class SDep;
36 class SelectionDAGTargetInfo;
37 class SUnit;
38 class TargetFrameLowering;
39 class TargetInstrInfo;
40 class TargetLowering;
41 class TargetRegisterClass;
42 class TargetRegisterInfo;
43 class TargetSchedModel;
44 struct MachineSchedPolicy;
45 
46 //===----------------------------------------------------------------------===//
47 ///
48 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
49 /// Target-specific options that control code generation and printing should
50 /// be exposed through a TargetSubtargetInfo-derived class.
51 ///
53 protected: // Can only create subclasses...
54  TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
57  const SubtargetInfoKV *ProcSched,
58  const MCWriteProcResEntry *WPR,
59  const MCWriteLatencyEntry *WL,
60  const MCReadAdvanceEntry *RA, const InstrStage *IS,
61  const unsigned *OC, const unsigned *FP);
62 
63 public:
64  // AntiDepBreakMode - Type of anti-dependence breaking that should
65  // be performed before post-RA scheduling.
68 
69  TargetSubtargetInfo() = delete;
70  TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
71  void operator=(const TargetSubtargetInfo &) = delete;
72  virtual ~TargetSubtargetInfo();
73 
74  virtual bool isXRaySupported() const { return false; }
75 
76  // Interfaces to the major aspects of target machine information:
77  //
78  // -- Instruction opcode and operand information
79  // -- Pipelines and scheduling information
80  // -- Stack frame information
81  // -- Selection DAG lowering information
82  // -- Call lowering information
83  //
84  // N.B. These objects may change during compilation. It's not safe to cache
85  // them between functions.
86  virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
87  virtual const TargetFrameLowering *getFrameLowering() const {
88  return nullptr;
89  }
90  virtual const TargetLowering *getTargetLowering() const { return nullptr; }
92  return nullptr;
93  }
94  virtual const CallLowering *getCallLowering() const { return nullptr; }
95 
96  // FIXME: This lets targets specialize the selector by subtarget (which lets
97  // us do things like a dedicated avx512 selector). However, we might want
98  // to also specialize selectors by MachineFunction, which would let us be
99  // aware of optsize/optnone and such.
101  return nullptr;
102  }
103 
104  /// Target can subclass this hook to select a different DAG scheduler.
107  return nullptr;
108  }
109 
110  virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
111 
112  /// getRegisterInfo - If register information is available, return it. If
113  /// not, return null.
114  ///
115  virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
116 
117  /// If the information for the register banks is available, return it.
118  /// Otherwise return nullptr.
119  virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
120 
121  /// getInstrItineraryData - Returns instruction itinerary data for the target
122  /// or specific subtarget.
123  ///
124  virtual const InstrItineraryData *getInstrItineraryData() const {
125  return nullptr;
126  }
127 
128  /// Resolve a SchedClass at runtime, where SchedClass identifies an
129  /// MCSchedClassDesc with the isVariant property. This may return the ID of
130  /// another variant SchedClass, but repeated invocation must quickly terminate
131  /// in a nonvariant SchedClass.
132  virtual unsigned resolveSchedClass(unsigned SchedClass,
133  const MachineInstr *MI,
134  const TargetSchedModel *SchedModel) const {
135  return 0;
136  }
137 
138  /// \brief True if the subtarget should run MachineScheduler after aggressive
139  /// coalescing.
140  ///
141  /// This currently replaces the SelectionDAG scheduler with the "source" order
142  /// scheduler (though see below for an option to turn this off and use the
143  /// TargetLowering preference). It does not yet disable the postRA scheduler.
144  virtual bool enableMachineScheduler() const;
145 
146  /// \brief True if the machine scheduler should disable the TLI preference
147  /// for preRA scheduling with the source level scheduler.
148  virtual bool enableMachineSchedDefaultSched() const { return true; }
149 
150  /// \brief True if the subtarget should enable joining global copies.
151  ///
152  /// By default this is enabled if the machine scheduler is enabled, but
153  /// can be overridden.
154  virtual bool enableJoinGlobalCopies() const;
155 
156  /// True if the subtarget should run a scheduler after register allocation.
157  ///
158  /// By default this queries the PostRAScheduling bit in the scheduling model
159  /// which is the preferred way to influence this.
160  virtual bool enablePostRAScheduler() const;
161 
162  /// \brief True if the subtarget should run the atomic expansion pass.
163  virtual bool enableAtomicExpand() const;
164 
165  /// \brief Override generic scheduling policy within a region.
166  ///
167  /// This is a convenient way for targets that don't provide any custom
168  /// scheduling heuristics (no custom MachineSchedStrategy) to make
169  /// changes to the generic scheduling policy.
171  unsigned NumRegionInstrs) const {}
172 
173  // \brief Perform target specific adjustments to the latency of a schedule
174  // dependency.
175  virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
176 
177  // For use with PostRAScheduling: get the anti-dependence breaking that should
178  // be performed before post-RA scheduling.
180 
181  // For use with PostRAScheduling: in CriticalPathRCs, return any register
182  // classes that should only be considered for anti-dependence breaking if they
183  // are on the critical path.
184  virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
185  return CriticalPathRCs.clear();
186  }
187 
188  // \brief Provide an ordered list of schedule DAG mutations for the post-RA
189  // scheduler.
190  virtual void getPostRAMutations(
191  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
192  }
193 
194  // \brief Provide an ordered list of schedule DAG mutations for the machine
195  // pipeliner.
196  virtual void getSMSMutations(
197  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
198  }
199 
200  // For use with PostRAScheduling: get the minimum optimization level needed
201  // to enable post-RA scheduling.
203  return CodeGenOpt::Default;
204  }
205 
206  /// \brief True if the subtarget should run the local reassignment
207  /// heuristic of the register allocator.
208  /// This heuristic may be compile time intensive, \p OptLevel provides
209  /// a finer grain to tune the register allocator.
210  virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
211 
212  /// \brief Enable use of alias analysis during code generation (during MI
213  /// scheduling, DAGCombine, etc.).
214  virtual bool useAA() const;
215 
216  /// \brief Enable the use of the early if conversion pass.
217  virtual bool enableEarlyIfConversion() const { return false; }
218 
219  /// \brief Return PBQPConstraint(s) for the target.
220  ///
221  /// Override to provide custom PBQP constraints.
222  virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
223  return nullptr;
224  }
225 
226  /// Enable tracking of subregister liveness in register allocator.
227  /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
228  /// possible.
229  virtual bool enableSubRegLiveness() const { return false; }
230 };
231 
232 } // end namespace llvm
233 
234 #endif // LLVM_TARGET_TARGETSUBTARGETINFO_H
virtual bool enableMachineScheduler() const
True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool enableAtomicExpand() const
True if the subtarget should run the atomic expansion pass.
ScheduleDAGSDNodes *(* FunctionPassCtor)(SelectionDAGISel *, CodeGenOpt::Level)
virtual bool enableSubRegLiveness() const
Enable tracking of subregister liveness in register allocator.
virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
Override generic scheduling policy within a region.
virtual bool enablePostRAScheduler() const
True if the subtarget should run a scheduler after register allocation.
virtual const CallLowering * getCallLowering() const
SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary pointers. ...
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const
virtual AntiDepBreakMode getAntiDepBreakMode() const
Holds all the information related to register banks.
Provide an instruction scheduling machine model to CodeGen passes.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
Itinerary data supplied by a subtarget to be used by a target.
virtual bool isXRaySupported() const
virtual void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual const InstructionSelector * getInstructionSelector() const
TargetInstrInfo - Interface to description of machine instruction set.
SDep - Scheduling dependency.
Definition: ScheduleDAG.h:45
void operator=(const TargetSubtargetInfo &)=delete
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:55
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool enableMachineSchedDefaultSched() const
True if the machine scheduler should disable the TLI preference for preRA scheduling with the source ...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
virtual const TargetFrameLowering * getFrameLowering() const
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
virtual const TargetLowering * getTargetLowering() const
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
Information about stack frame layout on the target.
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accomodate up to NumRegBanks RegisterBank instances.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
Definition: MCSchedule.h:86
TargetSubtargetInfo - Generic base class for all target subtargets.
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Representation of each machine instruction.
Definition: MachineInstr.h:52
These values represent a non-pipelined step in the execution of an instruction.
MCSubtargetInfo - Generic base class for all target subtargets.
pgo instr use
virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const
True if the subtarget should run the local reassignment heuristic of the register allocator...
virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const
virtual const TargetInstrInfo * getInstrInfo() const
virtual void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
virtual const LegalizerInfo * getLegalizerInfo() const
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
virtual RegisterScheduler::FunctionPassCtor getDAGScheduler(CodeGenOpt::Level) const
Target can subclass this hook to select a different DAG scheduler.
SmallVectorImpl< const TargetRegisterClass * > RegClassVector
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:244
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).