37 #define DEBUG_TYPE "mccodeemitter"
39 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted.");
40 STATISTIC(MCNumFixups,
"Number of MC fixups created.");
50 : Ctx(ctx), MCII(mcii) {}
51 AArch64MCCodeEmitter(
const AArch64MCCodeEmitter &) =
delete;
52 void operator=(
const AArch64MCCodeEmitter &) =
delete;
53 ~AArch64MCCodeEmitter()
override =
default;
57 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
70 template <u
int32_t FixupKind>
166 unsigned fixMOVZ(
const MCInst &
MI,
unsigned EncodedValue,
173 unsigned fixMulHigh(
const MCInst &
MI,
unsigned EncodedValue,
176 template<
int hasRs,
int hasRt2>
unsigned
177 fixLoadStoreExclusive(
const MCInst &
MI,
unsigned EncodedValue,
180 unsigned fixOneOperandFPComparison(
const MCInst &
MI,
unsigned EncodedValue,
184 uint64_t computeAvailableFeatures(
const FeatureBitset &FB)
const;
185 void verifyInstructionPredicates(
const MCInst &
MI,
186 uint64_t AvailableFeatures)
const;
198 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
200 assert(MO.
isImm() &&
"did not expect relocated expression");
201 return static_cast<unsigned>(MO.
getImm());
204 template<
unsigned FixupKind>
uint32_t
205 AArch64MCCodeEmitter::getLdStUImm12OpValue(
const MCInst &MI,
unsigned OpIdx,
212 ImmVal = static_cast<uint32_t>(MO.
getImm());
214 assert(MO.
isExpr() &&
"unable to encode load/store imm operand");
226 AArch64MCCodeEmitter::getAdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
252 AArch64MCCodeEmitter::getAddSubImmOpValue(
const MCInst &MI,
unsigned OpIdx,
259 "unexpected shift type for add/sub immediate");
261 assert((ShiftVal == 0 || ShiftVal == 12) &&
262 "unexpected shift value for add/sub immediate");
264 return MO.
getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal));
276 if (
const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) {
282 return ShiftVal == 0 ? 0 : (1 << ShiftVal);
287 uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue(
309 AArch64MCCodeEmitter::getLoadLiteralOpValue(
const MCInst &MI,
unsigned OpIdx,
329 AArch64MCCodeEmitter::getMemExtendOpValue(
const MCInst &MI,
unsigned OpIdx,
334 return (SignExtend << 1) | DoShift;
338 AArch64MCCodeEmitter::getMoveWideImmOpValue(
const MCInst &MI,
unsigned OpIdx,
345 assert(MO.
isExpr() &&
"Unexpected movz/movk immediate");
357 uint32_t AArch64MCCodeEmitter::getTestBranchTargetOpValue(
389 MCFixupKind Kind = MI.
getOpcode() == AArch64::BL
407 AArch64MCCodeEmitter::getVecShifterOpValue(
const MCInst &MI,
unsigned OpIdx,
411 assert(MO.
isImm() &&
"Expected an immediate value for the shift amount!");
431 uint32_t AArch64MCCodeEmitter::getFixedPointScaleOpValue(
435 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
440 AArch64MCCodeEmitter::getVecShiftR64OpValue(
const MCInst &MI,
unsigned OpIdx,
444 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
449 AArch64MCCodeEmitter::getVecShiftR32OpValue(
const MCInst &MI,
unsigned OpIdx,
453 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
458 AArch64MCCodeEmitter::getVecShiftR16OpValue(
const MCInst &MI,
unsigned OpIdx,
462 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
467 AArch64MCCodeEmitter::getVecShiftR8OpValue(
const MCInst &MI,
unsigned OpIdx,
471 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
476 AArch64MCCodeEmitter::getVecShiftL64OpValue(
const MCInst &MI,
unsigned OpIdx,
480 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
485 AArch64MCCodeEmitter::getVecShiftL32OpValue(
const MCInst &MI,
unsigned OpIdx,
489 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
494 AArch64MCCodeEmitter::getVecShiftL16OpValue(
const MCInst &MI,
unsigned OpIdx,
498 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
503 AArch64MCCodeEmitter::getVecShiftL8OpValue(
const MCInst &MI,
unsigned OpIdx,
507 assert(MO.
isImm() &&
"Expected an immediate value for the scale amount!");
513 uint32_t AArch64MCCodeEmitter::getMoveVecShifterOpValue(
518 "Expected an immediate value for the move shift amount!");
520 assert((ShiftVal == 8 || ShiftVal == 16) &&
"Invalid shift amount!");
521 return ShiftVal == 8 ? 0 : 1;
524 unsigned AArch64MCCodeEmitter::fixMOVZ(
const MCInst &MI,
unsigned EncodedValue,
533 if (UImm16MO.
isImm())
545 return EncodedValue & ~(1u << 30);
552 return EncodedValue & ~(1u << 30);
558 verifyInstructionPredicates(MI,
561 if (MI.
getOpcode() == AArch64::TLSDESCCALL) {
570 uint64_t
Binary = getBinaryCodeForInstr(MI, Fixups, STI);
576 AArch64MCCodeEmitter::fixMulHigh(
const MCInst &MI,
577 unsigned EncodedValue,
581 EncodedValue |= 0x1f << 10;
585 template<
int hasRs,
int hasRt2>
unsigned
586 AArch64MCCodeEmitter::fixLoadStoreExclusive(
const MCInst &MI,
587 unsigned EncodedValue,
589 if (!hasRs) EncodedValue |= 0x001F0000;
590 if (!hasRt2) EncodedValue |= 0x00007C00;
595 unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(
599 EncodedValue &= ~(0x1f << 16);
603 #define ENABLE_INSTR_PREDICATE_VERIFIER
604 #include "AArch64GenMCCodeEmitter.inc"
609 return new AArch64MCCodeEmitter(MCII, Ctx);
void push_back(const T &Elt)
STATISTIC(NumFunctions,"Total number of functions")
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
VariantKind getKind() const
Get the kind of this expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Lanai::Fixups FixupKind(const MCExpr *Expr)
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
PowerPC TLS Dynamic Call Fixup
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
MCSubtargetInfo - Generic base class for all target subtargets.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const