LLVM  4.0.0
MipsSEInstrInfo.h
Go to the documentation of this file.
1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
16 
17 #include "MipsInstrInfo.h"
18 #include "MipsSERegisterInfo.h"
19 
20 namespace llvm {
21 
23  const MipsSERegisterInfo RI;
24 
25 public:
26  explicit MipsSEInstrInfo(const MipsSubtarget &STI);
27 
28  const MipsRegisterInfo &getRegisterInfo() const override;
29 
30  /// isLoadFromStackSlot - If the specified machine instruction is a direct
31  /// load from a stack slot, return the virtual or physical register number of
32  /// the destination along with the FrameIndex of the loaded stack slot. If
33  /// not, return 0. This predicate must return 0 if the instruction has
34  /// any side effects other than loading from the stack slot.
35  unsigned isLoadFromStackSlot(const MachineInstr &MI,
36  int &FrameIndex) const override;
37 
38  /// isStoreToStackSlot - If the specified machine instruction is a direct
39  /// store to a stack slot, return the virtual or physical register number of
40  /// the source reg along with the FrameIndex of the loaded stack slot. If
41  /// not, return 0. This predicate must return 0 if the instruction has
42  /// any side effects other than storing to the stack slot.
43  unsigned isStoreToStackSlot(const MachineInstr &MI,
44  int &FrameIndex) const override;
45 
47  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
48  bool KillSrc) const override;
49 
52  unsigned SrcReg, bool isKill, int FrameIndex,
53  const TargetRegisterClass *RC,
54  const TargetRegisterInfo *TRI,
55  int64_t Offset) const override;
56 
59  unsigned DestReg, int FrameIndex,
60  const TargetRegisterClass *RC,
61  const TargetRegisterInfo *TRI,
62  int64_t Offset) const override;
63 
64  bool expandPostRAPseudo(MachineInstr &MI) const override;
65 
66  unsigned getOppositeBranchOpc(unsigned Opc) const override;
67 
68  /// Adjust SP by Amount bytes.
69  void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
70  MachineBasicBlock::iterator I) const override;
71 
72  /// Emit a series of instructions to load an immediate. If NewImm is a
73  /// non-NULL parameter, the last instruction is not emitted, but instead
74  /// its immediate operand is returned in NewImm.
75  unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
77  unsigned *NewImm) const;
78 
79 private:
80  unsigned getAnalyzableBrOpc(unsigned Opc) const override;
81 
82  void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
83 
84  void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
85 
86  std::pair<bool, bool> compareOpndSize(unsigned Opc,
87  const MachineFunction &MF) const;
88 
89  void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
90  unsigned NewOpc) const;
91 
92  void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
93  unsigned LoOpc, unsigned HiOpc,
94  bool HasExplicitDef) const;
95 
96  /// Expand pseudo Int-to-FP conversion instructions.
97  ///
98  /// For example, the following pseudo instruction
99  /// PseudoCVT_D32_W D2, A5
100  /// gets expanded into these two instructions:
101  /// MTC1 F4, A5
102  /// CVT_D32_W D2, F4
103  ///
104  /// We do this expansion post-RA to avoid inserting a floating point copy
105  /// instruction between MTC1 and CVT_D32_W.
106  void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
107  unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
108 
109  void expandExtractElementF64(MachineBasicBlock &MBB,
110  MachineBasicBlock::iterator I, bool FP64) const;
111  void expandBuildPairF64(MachineBasicBlock &MBB,
112  MachineBasicBlock::iterator I, bool FP64) const;
113  void expandEhReturn(MachineBasicBlock &MBB,
115 };
116 
117 }
118 
119 #endif
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
A debug info location.
Definition: DebugLoc.h:34
MipsSEInstrInfo(const MipsSubtarget &STI)
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
MachineBasicBlock * MBB
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
uint32_t Offset
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool expandPostRAPseudo(MachineInstr &MI) const override
Representation of each machine instruction.
Definition: MachineInstr.h:52
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
IRTranslator LLVM IR MI
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.