47 "disable-ppc-vsx-fma-mutation",
51 #define DEBUG_TYPE "ppc-vsx-fma-mutate"
53 namespace llvm {
namespace PPC {
109 SlotIndex FMAIdx = LIS->getInstructionIndex(MI);
118 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->
def);
161 bool OtherUsers =
false, KillsAddendSrc =
false;
168 if (J->modifiesRegister(AddendSrcReg, TRI) ||
169 J->killsRegister(AddendSrcReg, TRI)) {
170 KillsAddendSrc =
true;
175 if (OtherUsers || KillsAddendSrc)
189 unsigned KilledProdOp = 0, OtherProdOp = 0;
192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill()
193 && Reg2 != OldFMAReg) {
196 }
else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill()
197 && Reg3 != OldFMAReg) {
213 !LIS->getInterval(AddendSrcReg).liveAt(FMAIdx))
242 "Addend copy not tied to old FMA output!");
244 DEBUG(
dbgs() <<
"VSX FMA Mutation:\n " << MI);
290 if (UseMI == AddendMI)
293 UseMO.
substVirtReg(KilledProdReg, KilledProdSubReg, *TRI);
299 LiveInterval &NewFMAInt = LIS->getInterval(KilledProdReg);
303 if (AI->valno == AddendValNo)
308 LIS->getVNInfoAllocator());
310 NewFMAInt.
addSegment(LiveInterval::Segment(AI->start, AI->end,
313 DEBUG(
dbgs() <<
" extended: " << NewFMAInt <<
'\n');
321 unsigned Unit = *Units;
323 LiveRange &AddendSrcRange = LIS->getRegUnit(Unit);
326 DEBUG(
dbgs() <<
" extended: " << AddendSrcRange <<
'\n');
330 DEBUG(
dbgs() <<
" trimmed: " << FMAInt <<
'\n');
334 DEBUG(
dbgs() <<
" removing: " << *AddendMI <<
'\n');
335 LIS->RemoveMachineInstrFromMaps(*AddendMI);
355 LIS = &getAnalysis<LiveIntervals>();
359 bool Changed =
false;
386 "PowerPC VSX FMA Mutation",
false,
false)
395 char PPCVSXFMAMutate::ID = 0;
397 return new PPCVSXFMAMutate();
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Segments::iterator iterator
SlotIndex def
The index of the defining instruction.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
FunctionPass * createPPCVSXFMAMutatePass()
LiveInterval - This class represents the liveness of a register, or stack slot.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
MachineInstrBundleIterator< MachineInstr > iterator
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
VNInfo - Value Number Information.
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
return AArch64::GPR64RegClass contains(Reg)
This class represents the liveness of a register, stack slot, etc.
static const MachineInstrBuilder & AddSubReg(const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
initializer< Ty > init(const Ty &Val)
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
int getAltVSXFMAOpcode(uint16_t Opcode)
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Use)
Attempt to extend a value defined after StartIdx to include Use.
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
void initializePPCVSXFMAMutatePass(PassRegistry &)
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
FunctionPass class - This class is used to implement most global optimizations.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void setIsKill(bool Val=true)
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
const PPCInstrInfo * getInstrInfo() const override
MachineOperand class - Representation of each machine instruction operand.
static cl::opt< bool > DisableVSXFMAMutate("disable-ppc-vsx-fma-mutation", cl::desc("Disable VSX FMA instruction mutation"), cl::init(true), cl::Hidden)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
INITIALIZE_PASS_BEGIN(PPCVSXFMAMutate, DEBUG_TYPE,"PowerPC VSX FMA Mutation", false, false) INITIALIZE_PASS_END(PPCVSXFMAMutate
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setSubReg(unsigned subReg)
static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read, bool &Write, bool &Effects, bool &StackPointer)
static reg_nodbg_iterator reg_nodbg_end()
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
std::vector< uint8_t > Unit
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FMA - Perform a * b + c with no intermediate rounding step.
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const
SlotIndex - An opaque wrapper around machine indexes.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...