43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
51 cl::desc(
"Disable analysis for CTR loops"));
57 cl::desc(
"Causes the backend to crash instead of generating a nop VSX copy"),
62 cl::desc(
"Use the old (incorrect) instruction latency calculation"));
65 void PPCInstrInfo::anchor() {}
69 Subtarget(STI), RI(STI.getTargetMachine()) {}
77 static_cast<const PPCSubtarget *
>(STI)->getDarwinDirective();
81 static_cast<const PPCSubtarget *
>(STI)->getInstrItineraryData();
113 unsigned *PredCost)
const {
115 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
135 Latency = std::max(Latency, (
unsigned) Cycle);
144 unsigned UseIdx)
const {
145 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
161 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
162 PPC::CRBITRCRegClass.contains(Reg);
250 unsigned &SrcReg,
unsigned &DstReg,
251 unsigned &SubIdx)
const {
253 default:
return false;
255 case PPC::EXTSW_32_64:
258 SubIdx = PPC::sub_32;
272 case PPC::RESTORE_CR:
273 case PPC::RESTORE_CRBIT:
280 case PPC::RESTORE_VRSAVE:
303 case PPC::SPILL_CRBIT:
310 case PPC::SPILL_VRSAVE:
325 unsigned OpIdx2)
const {
348 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
349 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
357 bool ChangeReg0 =
false;
363 "Expecting a two-address instruction!");
375 if (MB == 0 && ME == 31)
386 .addImm((ME + 1) & 31)
387 .addImm((MB - 1) & 31);
408 unsigned &SrcOpIdx2)
const {
419 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
429 default: Opcode = PPC::NOP;
break;
438 BuildMI(MBB, MI, DL,
get(Opcode));
453 bool AllowModify)
const {
454 bool isPPC64 = Subtarget.
isPPC64();
474 }
else if (LastInst.
getOpcode() == PPC::BCC) {
482 }
else if (LastInst.
getOpcode() == PPC::BC) {
490 }
else if (LastInst.
getOpcode() == PPC::BCn) {
498 }
else if (LastInst.
getOpcode() == PPC::BDNZ8 ||
509 }
else if (LastInst.
getOpcode() == PPC::BDZ8 ||
534 if (SecondLastInst.
getOpcode() == PPC::BCC &&
544 }
else if (SecondLastInst.
getOpcode() == PPC::BC &&
554 }
else if (SecondLastInst.
getOpcode() == PPC::BCn &&
564 }
else if ((SecondLastInst.
getOpcode() == PPC::BDNZ8 ||
578 }
else if ((SecondLastInst.
getOpcode() == PPC::BDZ8 ||
602 I->eraseFromParent();
611 int *BytesRemoved)
const {
612 assert(!BytesRemoved &&
"code size not handled");
618 if (I->getOpcode() !=
PPC::B && I->getOpcode() != PPC::BCC &&
619 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
620 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() !=
PPC::BDNZ &&
621 I->getOpcode() != PPC::BDZ8 && I->getOpcode() !=
PPC::BDZ)
625 I->eraseFromParent();
629 if (I == MBB.
begin())
return 1;
631 if (I->getOpcode() != PPC::BCC &&
632 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
633 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() !=
PPC::BDNZ &&
634 I->getOpcode() != PPC::BDZ8 && I->getOpcode() !=
PPC::BDZ)
638 I->eraseFromParent();
647 int *BytesAdded)
const {
649 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
651 "PPC branch conditions have two components!");
652 assert(!BytesAdded &&
"code size not handled");
654 bool isPPC64 = Subtarget.
isPPC64();
660 else if (Cond[1].
getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
661 BuildMI(&MBB, DL,
get(Cond[0].getImm() ?
663 (isPPC64 ? PPC::BDZ8 :
PPC::BDZ))).addMBB(TBB);
669 BuildMI(&MBB, DL,
get(PPC::BCC))
675 if (Cond[1].
getReg() == PPC::CTR || Cond[1].
getReg() == PPC::CTR8)
676 BuildMI(&MBB, DL,
get(Cond[0].getImm() ?
684 BuildMI(&MBB, DL,
get(PPC::BCC))
693 unsigned TrueReg,
unsigned FalseReg,
694 int &CondCycles,
int &TrueCycles,
int &FalseCycles)
const {
698 if (Cond.
size() != 2)
703 if (Cond[1].
getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
714 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
715 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
716 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
717 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
733 const DebugLoc &dl,
unsigned DestReg,
735 unsigned FalseReg)
const {
737 "PPC branch conditions have two components!");
740 "Cannot insert select on target without ISEL support");
745 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
746 assert(RC &&
"TrueReg and FalseReg must have overlapping register classes");
748 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
749 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
751 PPC::GPRCRegClass.hasSubClassEq(RC) ||
752 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
753 "isel is for regular integer GPRs only");
755 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
759 bool SwapOps =
false;
760 switch (SelectPred) {
764 SubIdx = PPC::sub_eq; SwapOps =
false;
break;
768 SubIdx = PPC::sub_eq; SwapOps =
true;
break;
772 SubIdx = PPC::sub_lt; SwapOps =
false;
break;
776 SubIdx = PPC::sub_lt; SwapOps =
true;
break;
780 SubIdx = PPC::sub_gt; SwapOps =
false;
break;
784 SubIdx = PPC::sub_gt; SwapOps =
true;
break;
788 SubIdx = PPC::sub_un; SwapOps =
false;
break;
792 SubIdx = PPC::sub_un; SwapOps =
true;
break;
797 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
798 SecondReg = SwapOps ? TrueReg : FalseReg;
803 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
804 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
806 MRI.getRegClass(FirstReg)->
contains(PPC::X0) ?
807 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
808 unsigned OldFirstReg = FirstReg;
809 FirstReg = MRI.createVirtualRegister(FirstRC);
810 BuildMI(MBB, MI, dl,
get(TargetOpcode::COPY), FirstReg)
814 BuildMI(MBB, MI, dl,
get(OpCode), DestReg)
821 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
822 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
823 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
824 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
826 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
827 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
828 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
829 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
831 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
832 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
833 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
834 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
836 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
837 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
838 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
839 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
842 assert(Ret != 4 &&
"Invalid CR bit register");
848 const DebugLoc &DL,
unsigned DestReg,
849 unsigned SrcReg,
bool KillSrc)
const {
853 if (PPC::F8RCRegClass.
contains(DestReg) &&
854 PPC::VSRCRegClass.
contains(SrcReg)) {
862 }
else if (PPC::F8RCRegClass.
contains(SrcReg) &&
863 PPC::VSRCRegClass.
contains(DestReg)) {
874 if (PPC::CRBITRCRegClass.
contains(SrcReg) &&
875 PPC::GPRCRegClass.
contains(DestReg)) {
881 BuildMI(MBB, I, DL,
get(PPC::RLWINM), DestReg)
887 }
else if (PPC::CRRCRegClass.
contains(SrcReg) &&
888 PPC::G8RCRegClass.
contains(DestReg)) {
889 BuildMI(MBB, I, DL,
get(PPC::MFOCRF8), DestReg).
addReg(SrcReg);
892 }
else if (PPC::CRRCRegClass.
contains(SrcReg) &&
893 PPC::GPRCRegClass.
contains(DestReg)) {
900 if (PPC::GPRCRegClass.
contains(DestReg, SrcReg))
902 else if (PPC::G8RCRegClass.
contains(DestReg, SrcReg))
904 else if (PPC::F4RCRegClass.
contains(DestReg, SrcReg))
906 else if (PPC::CRRCRegClass.
contains(DestReg, SrcReg))
908 else if (PPC::VRRCRegClass.
contains(DestReg, SrcReg))
910 else if (PPC::VSRCRegClass.
contains(DestReg, SrcReg))
920 else if (PPC::VSFRCRegClass.
contains(DestReg, SrcReg) ||
921 PPC::VSSRCRegClass.
contains(DestReg, SrcReg))
923 else if (PPC::QFRCRegClass.
contains(DestReg, SrcReg))
925 else if (PPC::QSRCRegClass.
contains(DestReg, SrcReg))
927 else if (PPC::QBRCRegClass.
contains(DestReg, SrcReg))
929 else if (PPC::CRBITRCRegClass.
contains(DestReg, SrcReg))
936 BuildMI(MBB, I, DL, MCID, DestReg)
945 unsigned SrcReg,
bool isKill,
949 bool &NonRI,
bool &SpillsVRS)
const{
954 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
955 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
960 }
else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
961 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
966 }
else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
971 }
else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
976 }
else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
982 }
else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
988 }
else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
994 }
else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1001 }
else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1002 unsigned Opc = Subtarget.
hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
1008 }
else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1009 unsigned Opc = Subtarget.
hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX;
1015 }
else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1017 "VRSAVE only needs spill/restore on Darwin");
1023 }
else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1029 }
else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1035 }
else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1051 unsigned SrcReg,
bool isKill,
int FrameIdx,
1069 bool NonRI =
false, SpillsVRS =
false;
1070 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1080 for (
unsigned i = 0, e = NewMIs.
size();
i != e; ++
i)
1092 unsigned DestReg,
int FrameIdx,
1095 bool &NonRI,
bool &SpillsVRS)
const {
1099 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1100 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1102 DestReg), FrameIdx));
1103 }
else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1104 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1107 }
else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1110 }
else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1113 }
else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1115 get(PPC::RESTORE_CR), DestReg),
1118 }
else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1120 get(PPC::RESTORE_CRBIT), DestReg),
1123 }
else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1127 }
else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1132 }
else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1133 unsigned Opc = Subtarget.
hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX;
1135 DestReg), FrameIdx));
1137 }
else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1138 unsigned Opc = Subtarget.
hasP9Vector() ? PPC::DFLOADf32 : PPC::LXSSPX;
1140 DestReg), FrameIdx));
1142 }
else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1144 "VRSAVE only needs spill/restore on Darwin");
1146 get(PPC::RESTORE_VRSAVE),
1150 }
else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1154 }
else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1158 }
else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1172 unsigned DestReg,
int FrameIdx,
1178 if (MI != MBB.
end()) DL = MI->getDebugLoc();
1190 if (Subtarget.
hasVSX() && RC == &PPC::VRRCRegClass)
1191 RC = &PPC::VSRCRegClass;
1193 bool NonRI =
false, SpillsVRS =
false;
1194 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1204 for (
unsigned i = 0, e = NewMIs.
size();
i != e; ++
i)
1217 assert(Cond.
size() == 2 &&
"Invalid PPC branch opcode!");
1218 if (Cond[1].
getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1219 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1231 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1261 if (UseInfo->isLookupPtrRegClass()) {
1262 if (UseInfo->RegClass != 1)
1265 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1266 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1273 if (UseInfo->Constraints != 0)
1277 if (UseInfo->isLookupPtrRegClass()) {
1278 bool isPPC64 = Subtarget.
isPPC64();
1279 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1281 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1282 PPC::ZERO8 : PPC::ZERO;
1297 if (
I->definesRegister(PPC::CTR) ||
I->definesRegister(PPC::CTR8))
1309 unsigned NumT,
unsigned ExtraT,
1311 unsigned NumF,
unsigned ExtraF,
1342 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1343 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR) {
1344 bool isPPC64 = Subtarget.
isPPC64();
1345 MI.
setDesc(
get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1346 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1350 .addReg(Pred[1].
getReg());
1354 .addReg(Pred[1].
getReg());
1358 .addImm(Pred[0].getImm())
1359 .addReg(Pred[1].
getReg());
1363 }
else if (OpC ==
PPC::B) {
1364 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1365 bool isPPC64 = Subtarget.
isPPC64();
1367 : (isPPC64 ? PPC::BDZ8 :
PPC::BDZ)));
1374 .addReg(Pred[1].
getReg())
1382 .addReg(Pred[1].
getReg())
1390 .addImm(Pred[0].getImm())
1391 .addReg(Pred[1].
getReg())
1396 }
else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1398 if (Pred[1].
getReg() == PPC::CTR8 || Pred[1].
getReg() == PPC::CTR)
1401 bool setLR = OpC ==
PPC::BCTRL || OpC == PPC::BCTRL8;
1402 bool isPPC64 = Subtarget.
isPPC64();
1405 MI.
setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1406 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1408 .addReg(Pred[1].
getReg());
1411 MI.
setDesc(
get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1412 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1414 .addReg(Pred[1].
getReg());
1418 MI.
setDesc(
get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1419 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1421 .addImm(Pred[0].getImm())
1422 .addReg(Pred[1].
getReg());
1431 assert(Pred1.
size() == 2 &&
"Invalid PPC first predicate");
1432 assert(Pred2.
size() == 2 &&
"Invalid PPC second predicate");
1434 if (Pred1[1].
getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1436 if (Pred2[1].
getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1440 if (Pred1[1].
getReg() != Pred2[1].getReg())
1461 std::vector<MachineOperand> &Pred)
const {
1469 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1470 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1513 unsigned &SrcReg2,
int &
Mask,
1518 default:
return false;
1551 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1562 bool isPPC64 = Subtarget.
isPPC64();
1563 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1564 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1565 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1569 if (!MI)
return false;
1572 bool equalityOnly =
false;
1575 if (is32BitSignedCompare) {
1577 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1578 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1579 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1580 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1581 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1585 }
else if (is32BitUnsignedCompare) {
1587 bool isZeroExtendingRotate =
1588 (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo ||
1589 MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo)
1594 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1595 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1596 MIOpC == PPC::SRW || MIOpC == PPC::SRWo ||
1597 isZeroExtendingRotate) {
1599 equalityOnly =
true;
1603 equalityOnly = is64BitUnsignedCompare;
1605 equalityOnly = is32BitUnsignedCompare;
1617 }
else if (UseMI->
getOpcode() == PPC::ISEL ||
1620 if (SubIdx != PPC::sub_eq)
1632 bool FoundUse =
false;
1667 for (; I != E && !noSub; --
I) {
1681 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1682 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1683 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1706 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1709 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1730 bool ShouldSwap =
false;
1737 ShouldSwap = !ShouldSwap;
1749 "Invalid predicate for equality-only optimization");
1752 }
else if (UseMI->
getOpcode() == PPC::ISEL ||
1755 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1756 "Invalid CR bit for equality-only optimization");
1758 if (NewSubReg == PPC::sub_lt)
1759 NewSubReg = PPC::sub_gt;
1760 else if (NewSubReg == PPC::sub_gt)
1761 NewSubReg = PPC::sub_lt;
1776 get(TargetOpcode::COPY), CRReg)
1783 if (MIOpC != NewOpC) {
1796 *ImpDefs; ++ImpDefs)
1802 *ImpUses; ++ImpUses)
1808 "Record-form instruction does not define cr0?");
1813 for (
unsigned i = 0, e = PredsToUpdate.
size();
i < e;
i++)
1814 PredsToUpdate[
i].first->setImm(PredsToUpdate[
i].second);
1816 for (
unsigned i = 0, e = SubRegsToUpdate.
size(); i < e; i++)
1817 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1832 }
else if (Opcode == TargetOpcode::STACKMAP) {
1835 }
else if (Opcode == TargetOpcode::PATCHPOINT) {
1844 std::pair<unsigned, unsigned>
1847 return std::make_pair(TF & Mask, TF & ~Mask);
1852 using namespace PPCII;
1853 static const std::pair<unsigned, const char *>
TargetFlags[] = {
1867 using namespace PPCII;
1868 static const std::pair<unsigned, const char *>
TargetFlags[] = {
1878 case TargetOpcode::LOAD_STACK_GUARD: {
1880 "Only Linux target is expected to contain LOAD_STACK_GUARD");
1881 const int64_t
Offset = Subtarget.
isPPC64() ? -0x7010 : -0x7008;
1889 case PPC::DFLOADf32:
1890 case PPC::DFLOADf64:
1891 case PPC::DFSTOREf32:
1892 case PPC::DFSTOREf64: {
1894 "Invalid D-Form Pseudo-ops on non-P9 target.");
1895 unsigned UpperOpcode, LowerOpcode;
1897 case PPC::DFLOADf32:
1898 UpperOpcode = PPC::LXSSP;
1899 LowerOpcode = PPC::LFS;
1901 case PPC::DFLOADf64:
1902 UpperOpcode = PPC::LXSD;
1903 LowerOpcode = PPC::LFD;
1905 case PPC::DFSTOREf32:
1906 UpperOpcode = PPC::STXSSP;
1907 LowerOpcode = PPC::STFS;
1909 case PPC::DFSTOREf64:
1910 UpperOpcode = PPC::STXSD;
1911 LowerOpcode = PPC::STFD;
1916 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
1917 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
1918 Opcode = LowerOpcode;
1920 Opcode = UpperOpcode;
1930 if (Subtarget.
hasVSX() && RC == &PPC::VRRCRegClass)
1931 return &PPC::VSRCRegClass;
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
int getNonRecordFormOpcode(uint16_t)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
MachineBasicBlock * getMBB() const
const PPCTargetMachine & getTargetMachine() const
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isDarwin() const
isDarwin - True if this is any darwin platform.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const char * getSymbolName() const
bool isPredicable(MachineInstr &MI) const override
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
const MCPhysReg * iterator
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
use_instr_iterator use_instr_begin(unsigned RegNo) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
PPCInstrInfo(PPCSubtarget &STI)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
size_t size() const
size - Get the array size.
Instances of this class represent a single low-level machine instruction.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
const MachineOperand & getOperand(unsigned i) const
static ManagedStatic< OptionRegistry > OR
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
const MCPhysReg * ImplicitDefs
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
MI-level patchpoint operands.
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool empty() const
empty - Check if the array is empty.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
bool isTargetLinux() const
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
The next are not flags but distinct values.
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
void setOpcode(unsigned Op)
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
On a symbol operand, this represents the lo part.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void setSubReg(unsigned subReg)
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
const TargetInstrInfo * TII
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static use_instr_iterator use_instr_end()
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
This holds information about one operand of a machine instruction, indicating the register class for ...
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function's picbase...
bool expandPostRAPseudo(MachineInstr &MI) const override
const MCPhysReg * ImplicitUses
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...