LLVM  4.0.0
BPFAsmBackend.cpp
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1 //===-- BPFAsmBackend.cpp - BPF Assembler Backend -------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "llvm/ADT/StringRef.h"
12 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCFixup.h"
14 #include "llvm/MC/MCObjectWriter.h"
15 #include <cassert>
16 #include <cstdint>
17 
18 using namespace llvm;
19 
20 namespace {
21 
22 class BPFAsmBackend : public MCAsmBackend {
23 public:
24  bool IsLittleEndian;
25 
26  BPFAsmBackend(bool IsLittleEndian)
27  : MCAsmBackend(), IsLittleEndian(IsLittleEndian) {}
28  ~BPFAsmBackend() override = default;
29 
30  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
31  uint64_t Value, bool IsPCRel) const override;
32 
33  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
34 
35  // No instruction requires relaxation
36  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
37  const MCRelaxableFragment *DF,
38  const MCAsmLayout &Layout) const override {
39  return false;
40  }
41 
42  unsigned getNumFixupKinds() const override { return 1; }
43 
44  bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
45 
46  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
47  MCInst &Res) const override {}
48 
49  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
50 };
51 
52 } // end anonymous namespace
53 
54 bool BPFAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
55  if ((Count % 8) != 0)
56  return false;
57 
58  for (uint64_t i = 0; i < Count; i += 8)
59  OW->write64(0x15000000);
60 
61  return true;
62 }
63 
64 void BPFAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
65  unsigned DataSize, uint64_t Value,
66  bool IsPCRel) const {
67  if (Fixup.getKind() == FK_SecRel_4 || Fixup.getKind() == FK_SecRel_8) {
68  assert(Value == 0);
69  } else if (Fixup.getKind() == FK_Data_4 || Fixup.getKind() == FK_Data_8) {
70  unsigned Size = Fixup.getKind() == FK_Data_4 ? 4 : 8;
71 
72  for (unsigned i = 0; i != Size; ++i) {
73  unsigned Idx = IsLittleEndian ? i : Size - i;
74  Data[Fixup.getOffset() + Idx] = uint8_t(Value >> (i * 8));
75  }
76  } else {
77  assert(Fixup.getKind() == FK_PCRel_2);
78  Value = (uint16_t)((Value - 8) / 8);
79  if (IsLittleEndian) {
80  Data[Fixup.getOffset() + 2] = Value & 0xFF;
81  Data[Fixup.getOffset() + 3] = Value >> 8;
82  } else {
83  Data[Fixup.getOffset() + 2] = Value >> 8;
84  Data[Fixup.getOffset() + 3] = Value & 0xFF;
85  }
86  }
87 }
88 
89 MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
90  return createBPFELFObjectWriter(OS, 0, IsLittleEndian);
91 }
92 
94  const MCRegisterInfo &MRI,
95  const Triple &TT, StringRef CPU,
96  const MCTargetOptions&) {
97  return new BPFAsmBackend(/*IsLittleEndian=*/true);
98 }
99 
101  const MCRegisterInfo &MRI,
102  const Triple &TT, StringRef CPU,
103  const MCTargetOptions&) {
104  return new BPFAsmBackend(/*IsLittleEndian=*/false);
105 }
size_t i
void write64(uint64_t Value)
MCObjectWriter * createBPFELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian)
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:66
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
MCAsmBackend * createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
A four-byte section relative fixup.
Definition: MCFixup.h:42
A four-byte fixup.
Definition: MCFixup.h:26
const MCSubtargetInfo * STI
uint32_t getOffset() const
Definition: MCFixup.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:249
unsigned const MachineRegisterInfo * MRI
MCFixupKind getKind() const
Definition: MCFixup.h:93
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAsmBackend * createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
A two-byte pc relative fixup.
Definition: MCFixup.h:29
Target - Wrapper for Target specific information.
A eight-byte section relative fixup.
Definition: MCFixup.h:43
MCSubtargetInfo - Generic base class for all target subtargets.
A eight-byte fixup.
Definition: MCFixup.h:27
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:333
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47