46 return R == Hexagon::R0 || R == Hexagon::R1 || R ==
Hexagon::R2 ||
47 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
51 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
58 using namespace Hexagon;
61 R0, R1,
R2, R3,
R4, R5,
R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
64 D0, D1, D2, D3, D4, D5, D6, D7, 0
70 V0, V1,
V2, V3,
V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
71 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
75 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
78 switch (RC->
getID()) {
79 case IntRegsRegClassID:
81 case DoubleRegsRegClassID:
83 case PredRegsRegClassID:
85 case VectorRegsRegClassID:
86 case VectorRegs128BRegClassID:
88 case VecDblRegsRegClassID:
89 case VecDblRegs128BRegClassID:
97 dbgs() <<
"Register class: " << getRegClassName(RC) <<
"\n";
106 static const MCPhysReg CalleeSavedRegsV3[] = {
107 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
108 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
114 static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
115 Hexagon::R0, Hexagon::R1,
Hexagon::R2, Hexagon::R3,
116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
117 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
118 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
128 return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
131 llvm_unreachable(
"Callee saved registers requested for unknown architecture "
139 Reserved.
set(Hexagon::R29);
140 Reserved.
set(Hexagon::R30);
141 Reserved.
set(Hexagon::R31);
143 Reserved.
set(Hexagon::D14);
144 Reserved.
set(Hexagon::D15);
145 Reserved.
set(Hexagon::LC0);
146 Reserved.
set(Hexagon::LC1);
147 Reserved.
set(Hexagon::SA0);
148 Reserved.
set(Hexagon::SA1);
149 Reserved.
set(Hexagon::UGP);
150 Reserved.
set(Hexagon::GP);
151 Reserved.
set(Hexagon::CS0);
152 Reserved.
set(Hexagon::CS1);
153 Reserved.
set(Hexagon::CS);
154 Reserved.
set(Hexagon::USR);
160 int SPAdj,
unsigned FIOp,
164 assert(SPAdj == 0 &&
"Unexpected");
171 auto &HFI = *HST.getFrameLowering();
177 int Offset = HFI.getFrameIndexReference(MF, FI, BP);
184 case Hexagon::PS_fia:
185 MI.
setDesc(HII.get(Hexagon::A2_addi));
191 MI.
setDesc(HII.get(Hexagon::A2_addi));
195 if (!HII.isValidOffset(Opc, RealOffset)) {
199 unsigned TmpR =
MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
201 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
242 static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
243 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
245 switch (RC->
getID()) {
246 case Hexagon::CtrRegs64RegClassID:
247 case Hexagon::DoubleRegsRegClassID:
249 case Hexagon::VecDblRegsRegClassID:
250 case Hexagon::VecDblRegs128BRegClassID:
271 #define GET_REGINFO_TARGET_DESC
272 #include "HexagonGenRegisterInfo.inc"
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
const HexagonArchEnum & getHexagonArchVersion() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned getRARegister() const
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Hexagon target-specific information for each MachineFunction.
unsigned getHexagonSubRegIndex(const TargetRegisterClass *RC, unsigned GenIdx) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned getFrameRegister() const
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
unsigned getFirstCallerSavedNonParamReg() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
bool isEHReturnCalleeSaveReg(unsigned Reg) const
const MachineOperand & getOperand(unsigned i) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getStackRegister() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool isCalleeSaveReg(unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...