14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
43 virtual void anchor();
52 Delegate *TheDelegate;
55 const bool TracksSubRegLiveness;
76 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
83 return PhysRegUseDefLists[RegNo];
86 MachineOperand *getRegUseDefListHead(
unsigned RegNo)
const {
88 return VRegInfo[RegNo].second;
89 return PhysRegUseDefLists[RegNo];
93 static MachineOperand *getNextOperandForReg(
const MachineOperand *MO) {
94 assert(MO && MO->isReg() &&
"This is not a register operand!");
95 return MO->Contents.Reg.Next;
100 BitVector UsedPhysRegMask;
106 BitVector ReservedRegs;
108 typedef DenseMap<unsigned, LLT> VRegToTypeMap;
110 mutable std::unique_ptr<VRegToTypeMap> VRegToType;
116 std::vector<std::pair<unsigned, unsigned> > LiveIns;
118 MachineRegisterInfo(
const MachineRegisterInfo&) =
delete;
119 void operator=(
const MachineRegisterInfo&) =
delete;
121 explicit MachineRegisterInfo(MachineFunction *MF);
131 assert(TheDelegate == delegate &&
132 "Only the current delegate can perform reset!");
133 TheDelegate =
nullptr;
137 assert(delegate && !TheDelegate &&
138 "Attempted to set delegate to null, or to change it without "
139 "first resetting it!");
141 TheDelegate = delegate;
192 return TracksSubRegLiveness;
217 template<
bool Uses,
bool Defs,
bool SkipDebug,
218 bool ByOperand,
bool ByInstr,
bool ByBundle>
220 template<
bool Uses,
bool Defs,
bool SkipDebug,
221 bool ByOperand,
bool ByInstr,
bool ByBundle>
225 template<
bool,
bool,
bool,
bool,
bool,
bool>
227 template<
bool,
bool,
bool,
bool,
bool,
bool>
247 typedef defusechain_instr_iterator<true,true,false,false,true,false>
263 typedef defusechain_instr_iterator<true,true,false,false,false,true>
282 typedef defusechain_iterator<true,true,true,true,false,false>
299 typedef defusechain_instr_iterator<true,true,true,false,true,false>
316 typedef defusechain_instr_iterator<true,true,true,false,false,true>
337 typedef defusechain_iterator<false,true,false,true,false,false>
350 typedef defusechain_instr_iterator<false,true,false,false,true,false>
366 typedef defusechain_instr_iterator<false,true,false,false,false,true>
393 typedef defusechain_iterator<true,false,false,true,false,false>
406 typedef defusechain_instr_iterator<true,false,false,false,true,false>
422 typedef defusechain_instr_iterator<true,false,false,false,false,true>
450 typedef defusechain_iterator<true,false,true,true,false,false>
467 typedef defusechain_instr_iterator<true,false,true,false,true,false>
484 typedef defusechain_instr_iterator<true,false,true,false,false,true>
542 void dumpUses(
unsigned RegNo)
const;
564 "Register class not set, wrong accessor");
619 unsigned MinNumRegs = 0);
641 return *VRegToType.get();
677 RegAllocHints[VReg].first =
Type;
678 RegAllocHints[VReg].second = PrefReg;
689 std::pair<unsigned, unsigned>
692 return RegAllocHints[VReg];
700 return Hint.first ? 0 : Hint.second;
751 return !ReservedRegs.
empty();
766 "Reserved registers haven't been frozen yet. "
767 "Use TRI::getReservedRegs().");
798 LiveIns.push_back(std::make_pair(Reg, vreg));
803 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
835 template<
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
836 bool ByOperand,
bool ByInstr,
bool ByBundle>
838 :
public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
844 if ((!ReturnUses && op->
isUse()) ||
845 (!ReturnDefs && op->
isDef()) ||
853 assert(
Op &&
"Cannot increment end iterator!");
854 Op = getNextOperandForReg(
Op);
862 assert(!
Op->isDebug() &&
"Can't have debug defs");
866 while (
Op && ((!ReturnDefs &&
Op->isDef()) ||
867 (SkipDebug &&
Op->isDebug())))
868 Op = getNextOperandForReg(
Op);
872 typedef std::iterator<std::forward_iterator_tag,
874 typedef std::iterator<std::forward_iterator_tag,
891 assert(
Op &&
"Cannot increment end iterator!");
898 }
while (
Op &&
Op->getParent() ==
P);
899 }
else if (ByBundle) {
916 assert(
Op &&
"Cannot dereference end iterator!");
917 return Op - &
Op->getParent()->getOperand(0);
922 assert(
Op &&
"Cannot dereference end iterator!");
927 assert(
Op &&
"Cannot dereference end iterator!");
938 template<
bool ReturnUses,
bool ReturnDefs,
bool SkipDebug,
939 bool ByOperand,
bool ByInstr,
bool ByBundle>
941 :
public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
947 if ((!ReturnUses && op->
isUse()) ||
948 (!ReturnDefs && op->
isDef()) ||
956 assert(
Op &&
"Cannot increment end iterator!");
957 Op = getNextOperandForReg(
Op);
965 assert(!
Op->isDebug() &&
"Can't have debug defs");
969 while (
Op && ((!ReturnDefs &&
Op->isDef()) ||
970 (SkipDebug &&
Op->isDebug())))
971 Op = getNextOperandForReg(
Op);
975 typedef std::iterator<std::forward_iterator_tag,
977 typedef std::iterator<std::forward_iterator_tag,
994 assert(
Op &&
"Cannot increment end iterator!");
1001 }
while (
Op &&
Op->getParent() ==
P);
1002 }
else if (ByBundle) {
1018 assert(
Op &&
"Cannot dereference end iterator!");
1021 return *
Op->getParent();
iterator_range< reg_bundle_iterator > reg_bundles(unsigned Reg) const
defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator
use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register...
defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator
use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...
defusechain_iterator & operator++()
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
MachineFunctionProperties & reset(Property P)
livein_iterator livein_end() const
bool hasProperty(Property P) const
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
iterator_range< use_iterator > use_operands(unsigned Reg) const
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
defusechain_instr_iterator operator++(int)
const BitVector & getUsedPhysRegsMask() const
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(unsigned Reg) const
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
bool shouldTrackSubRegLiveness(unsigned VReg) const
defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator
reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
static use_nodbg_iterator use_nodbg_end()
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
MachineInstr & operator*() const
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
static use_iterator use_end()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
use_instr_iterator use_instr_begin(unsigned RegNo) const
iterator_range< use_bundle_iterator > use_bundles(unsigned Reg) const
static void advance(T &it, size_t Val)
void setUsedPhysRegMask(BitVector &Mask)
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
const MachineFunctionProperties & getProperties() const
Get the function properties.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
defusechain_iterator< true, true, false, true, false, false > reg_iterator
reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.
iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(unsigned Reg) const
def_bundle_iterator def_bundle_begin(unsigned RegNo) const
defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator
use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...
static reg_instr_iterator reg_instr_end()
defusechain_iterator - This class provides iterator support for machine operands in the function that...
reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const
MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)
Returns an iterator to the first instruction in the bundle containing I.
bool isLiveIn(unsigned Reg) const
static def_instr_iterator def_instr_end()
defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator
def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register...
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI)
defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator
def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register...
friend class defusechain_iterator
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator
reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator
use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register...
TargetInstrInfo - Interface to description of machine instruction set.
iterator_range< def_iterator > def_operands(unsigned Reg) const
bool reservedRegsFrozen() const
reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
MachineOperand * operator->() const
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
iterator_range< reg_instr_iterator > reg_instructions(unsigned Reg) const
unsigned const MachineRegisterInfo * MRI
bool operator!=(const defusechain_iterator &x) const
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
use_bundle_iterator use_bundle_begin(unsigned RegNo) const
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::reference reference
The instances of the Type class are immutable: once they are created, they are never changed...
defusechain_iterator< false, true, false, true, false, false > def_iterator
def_iterator/def_begin/def_end - Walk all defs of the specified register.
std::iterator< std::forward_iterator_tag, MachineInstr, ptrdiff_t >::pointer pointer
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
defusechain_instr_iterator & operator++()
bool empty() const
empty - Tests whether there are no bits in this bitvector.
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(unsigned Reg) const
iterator_range< def_bundle_iterator > def_bundles(unsigned Reg) const
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
bool tracksLiveness() const
tracksLiveness - Returns true when tracking register liveness accurately.
unsigned createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet...
defusechain_iterator operator++(int)
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
friend class defusechain_instr_iterator
defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator
reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register...
use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const
bool subRegLivenessEnabled() const
reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
static use_bundle_nodbg_iterator use_bundle_nodbg_end()
Iterator for intrusive lists based on ilist_node.
defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator
reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...
MachineOperand class - Representation of each machine instruction operand.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register...
bool test(unsigned Idx) const
static reg_bundle_iterator reg_bundle_end()
MachineOperand & operator*() const
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
unsigned getWeight() const
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
livein_iterator livein_begin() const
void invalidateLiveness()
invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.
This class implements the register bank concept.
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
void resetDelegate(Delegate *delegate)
static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()
A range adaptor for a pair of iterators.
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
unsigned operator*() const
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
def_iterator def_begin(unsigned RegNo) const
bool operator==(const defusechain_instr_iterator &x) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
Representation of each machine instruction.
bool hasOneDef(unsigned RegNo) const
Return true if there is exactly one operand defining the specified register.
defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator
reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register...
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
static use_bundle_iterator use_bundle_end()
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
def_instr_iterator def_instr_begin(unsigned RegNo) const
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(unsigned Reg) const
Iterate over the pressure sets affected by the given physical or virtual register.
use_iterator use_begin(unsigned RegNo) const
bool operator==(const defusechain_iterator &x) const
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
PSetIterator getPressureSets(unsigned RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)
addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void setSimpleHint(unsigned VReg, unsigned PrefReg)
Specify the preferred register allocation hint for the specified virtual register.
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
static reg_nodbg_iterator reg_nodbg_end()
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
static use_instr_nodbg_iterator use_instr_nodbg_end()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void dumpUses(unsigned RegNo) const
static def_iterator def_end()
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
bool livein_empty() const
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MachineInstr * operator->() const
void setDelegate(Delegate *delegate)
reg_iterator reg_begin(unsigned RegNo) const
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
void verifyUseLists() const
Verify the use list of all registers.
reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const
static reg_iterator reg_end()
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
defusechain_instr_iterator()
bool operator!=(const defusechain_instr_iterator &x) const
PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank
Convenient type to represent either a register class or a register bank.
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
static def_bundle_iterator def_bundle_end()
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.