33 #define DEBUG_TYPE "mccodeemitter"
35 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted.");
36 STATISTIC(MCNumCPRelocations,
"Number of constant pool relocations created.");
40 ARMMCCodeEmitter(
const ARMMCCodeEmitter &) =
delete;
41 void operator=(
const ARMMCCodeEmitter &) =
delete;
48 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
51 ~ARMMCCodeEmitter()
override {}
64 unsigned getMachineSoImmOpValue(
unsigned SoImm)
const;
68 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
85 bool EncodeAddrModeOpValues(
const MCInst &
MI,
unsigned OpIdx,
86 unsigned &
Reg,
unsigned &Imm,
218 uint32_t getAddrMode2OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
228 uint32_t getAddrMode3OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
239 uint32_t getAddrModeThumbSPOpValue(
const MCInst &MI,
unsigned OpIdx,
259 uint32_t getAddrMode5FP16OpValue(
const MCInst &MI,
unsigned OpIdx,
264 unsigned getCCOutOpValue(
const MCInst &MI,
unsigned Op,
273 unsigned getSOImmOpValue(
const MCInst &MI,
unsigned Op,
294 unsigned SoImm = MO.
getImm();
296 assert(SoImmVal != -1 &&
"Not a valid so_imm value!");
307 unsigned getModImmOpValue(
const MCInst &MI,
unsigned Op,
326 unsigned getT2SOImmOpValue(
const MCInst &MI,
unsigned Op,
331 assert(Encoded != ~0U &&
"Not a Thumb2 so_imm value?");
335 unsigned getT2AddrModeSORegOpValue(
const MCInst &MI,
unsigned OpNum,
338 unsigned getT2AddrModeImm8OpValue(
const MCInst &MI,
unsigned OpNum,
341 unsigned getT2AddrModeImm8OffsetOpValue(
const MCInst &MI,
unsigned OpNum,
346 unsigned getSORegRegOpValue(
const MCInst &MI,
unsigned Op,
349 unsigned getSORegImmOpValue(
const MCInst &MI,
unsigned Op,
352 unsigned getT2SORegOpValue(
const MCInst &MI,
unsigned Op,
356 unsigned getNEONVcvtImm32OpValue(
const MCInst &MI,
unsigned Op,
362 unsigned getBitfieldInvertedMaskOpValue(
const MCInst &MI,
unsigned Op,
366 unsigned getRegisterListOpValue(
const MCInst &MI,
unsigned Op,
369 unsigned getAddrMode6AddressOpValue(
const MCInst &MI,
unsigned Op,
372 unsigned getAddrMode6OneLane32AddressOpValue(
const MCInst &MI,
unsigned Op,
375 unsigned getAddrMode6DupAddressOpValue(
const MCInst &MI,
unsigned Op,
378 unsigned getAddrMode6OffsetOpValue(
const MCInst &MI,
unsigned Op,
382 unsigned getShiftRight8Imm(
const MCInst &MI,
unsigned Op,
385 unsigned getShiftRight16Imm(
const MCInst &MI,
unsigned Op,
388 unsigned getShiftRight32Imm(
const MCInst &MI,
unsigned Op,
391 unsigned getShiftRight64Imm(
const MCInst &MI,
unsigned Op,
395 unsigned getThumbSRImmOpValue(
const MCInst &MI,
unsigned Op,
399 unsigned NEONThumb2DataIPostEncoder(
const MCInst &MI,
400 unsigned EncodedValue,
402 unsigned NEONThumb2LoadStorePostEncoder(
const MCInst &MI,
403 unsigned EncodedValue,
405 unsigned NEONThumb2DupPostEncoder(
const MCInst &MI,
406 unsigned EncodedValue,
408 unsigned NEONThumb2V8PostEncoder(
const MCInst &MI,
409 unsigned EncodedValue,
412 unsigned VFPThumb2PostEncoder(
const MCInst &MI,
413 unsigned EncodedValue,
420 void EmitConstant(uint64_t Val,
unsigned Size,
raw_ostream &OS)
const {
422 for (
unsigned i = 0;
i != Size; ++
i) {
423 unsigned Shift = IsLittleEndian ?
i * 8 : (Size - 1 -
i) * 8;
424 EmitByte((Val >> Shift) & 0xff, OS);
438 return new ARMMCCodeEmitter(MCII, Ctx,
true);
444 return new ARMMCCodeEmitter(MCII, Ctx,
false);
450 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(
const MCInst &MI,
451 unsigned EncodedValue,
457 unsigned Bit24 = EncodedValue & 0x01000000;
458 unsigned Bit28 = Bit24 << 4;
459 EncodedValue &= 0xEFFFFFFF;
460 EncodedValue |= Bit28;
461 EncodedValue |= 0x0F000000;
470 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(
const MCInst &MI,
471 unsigned EncodedValue,
474 EncodedValue &= 0xF0FFFFFF;
475 EncodedValue |= 0x09000000;
484 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(
const MCInst &MI,
485 unsigned EncodedValue,
488 EncodedValue &= 0x00FFFFFF;
489 EncodedValue |= 0xEE000000;
497 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(
const MCInst &MI,
498 unsigned EncodedValue,
501 EncodedValue |= 0xC000000;
509 unsigned ARMMCCodeEmitter::
510 VFPThumb2PostEncoder(
const MCInst &MI,
unsigned EncodedValue,
513 EncodedValue &= 0x0FFFFFFF;
514 EncodedValue |= 0xE0000000;
521 unsigned ARMMCCodeEmitter::
527 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
533 case ARM::Q0:
case ARM::Q1:
case ARM::Q2:
case ARM::Q3:
534 case ARM::Q4:
case ARM::Q5:
case ARM::Q6:
case ARM::Q7:
535 case ARM::Q8:
case ARM::Q9:
case ARM::Q10:
case ARM::Q11:
536 case ARM::Q12:
case ARM::Q13:
case ARM::Q14:
case ARM::Q15:
539 }
else if (MO.
isImm()) {
540 return static_cast<unsigned>(MO.
getImm());
543 .bitcastToAPInt().getHiBits(32).getLimitedValue());
550 bool ARMMCCodeEmitter::
551 EncodeAddrModeOpValues(
const MCInst &MI,
unsigned OpIdx,
unsigned &Reg,
557 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
559 int32_t SImm = MO1.
getImm();
563 if (SImm == INT32_MIN) {
588 assert(MO.
isExpr() &&
"Unexpected branch target type!");
601 uint32_t S = (offset & 0x800000) >> 23;
602 uint32_t J1 = (offset & 0x400000) >> 22;
603 uint32_t J2 = (offset & 0x200000) >> 21;
618 getThumbBLTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
631 getThumbBLXTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
643 getThumbBRTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
650 return (MO.
getImm() >> 1);
655 getThumbBCCTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
662 return (MO.
getImm() >> 1);
667 getThumbCBTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
673 return (MO.
getImm() >> 1);
680 for (
int i = 0;
i < NumOp-1; ++
i) {
704 return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
710 getARMBranchTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
726 getARMBLTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
741 getARMBLXTargetOpValue(
const MCInst &MI,
unsigned OpIdx,
753 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
764 bool I = (Val & 0x800000);
765 bool J1 = (Val & 0x400000);
766 bool J2 = (Val & 0x200000);
783 getAdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
790 int64_t offset = MO.
getImm();
794 if (offset == INT32_MIN) {
797 }
else if (offset < 0) {
815 assert(SoImmVal != -1 &&
"Not a valid so_imm value!");
824 getT2AdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
831 int32_t Val = MO.
getImm();
832 if (Val == INT32_MIN)
844 getThumbAdrLabelOpValue(
const MCInst &MI,
unsigned OpIdx,
857 getThumbAddrModeRegRegOpValue(
const MCInst &MI,
unsigned OpIdx,
865 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
866 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.
getReg());
867 return (Rm << 3) | Rn;
872 getAddrModeImm12OpValue(
const MCInst &MI,
unsigned OpIdx,
883 Reg = CTX.getRegisterInfo()->getEncodingValue(
ARM::PC);
897 ++MCNumCPRelocations;
901 if (Offset == INT32_MIN) {
904 }
else if (Offset < 0) {
911 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
917 Binary |= (Reg << 13);
924 getT2Imm8s4OpValue(
const MCInst &MI,
unsigned OpIdx,
937 bool isAdd = Imm8 >= 0;
956 getT2AddrModeImm8s4OpValue(
const MCInst &MI,
unsigned OpIdx,
967 Reg = CTX.getRegisterInfo()->getEncodingValue(
ARM::PC);
971 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
976 ++MCNumCPRelocations;
978 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
986 uint32_t Binary = (Imm8 >> 2) & 0xff;
990 Binary |= (Reg << 9);
997 getT2AddrModeImm0_1020s4OpValue(
const MCInst &MI,
unsigned OpIdx,
1004 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1005 unsigned Imm8 = MO1.
getImm();
1006 return (Reg << 8) |
Imm8;
1010 ARMMCCodeEmitter::getHiLo16ImmOpValue(
const MCInst &MI,
unsigned OpIdx,
1018 return static_cast<unsigned>(MO.
getImm());
1024 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(
E);
1028 const int64_t
Value = MCE->getValue();
1029 if (Value > UINT32_MAX)
1032 switch (ARM16Expr->
getKind()) {
1034 return (int32_t(Value) & 0xffff0000) >> 16;
1036 return (int32_t(Value) & 0x0000ffff);
1041 switch (ARM16Expr->
getKind()) {
1066 getLdStSORegOpValue(
const MCInst &MI,
unsigned OpIdx,
1072 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1073 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1077 unsigned SBits = getShiftOp(ShOp);
1081 assert((ShImm & ~0x1f) == 0 &&
"Out of range shift amount");
1092 Binary |= SBits << 5;
1093 Binary |= ShImm << 7;
1100 getAddrMode2OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
1108 unsigned Imm = MO1.
getImm();
1116 Binary |= getShiftOp(ShOp) << 5;
1117 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1119 return Binary | (isAdd << 12) | (isReg << 13);
1123 getPostIdxRegOpValue(
const MCInst &MI,
unsigned OpIdx,
1130 bool isAdd = MO1.
getImm() != 0;
1131 return CTX.getRegisterInfo()->getEncodingValue(MO.
getReg()) | (isAdd << 4);
1135 getAddrMode3OffsetOpValue(
const MCInst &MI,
unsigned OpIdx,
1144 unsigned Imm = MO1.
getImm();
1146 bool isImm = MO.
getReg() == 0;
1150 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1151 return Imm8 | (isAdd << 8) | (isImm << 9);
1155 getAddrMode3OpValue(
const MCInst &MI,
unsigned OpIdx,
1169 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(
ARM::PC);
1171 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1176 ++MCNumCPRelocations;
1177 return (Rn << 9) | (1 << 13);
1179 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1180 unsigned Imm = MO2.
getImm();
1182 bool isImm = MO1.
getReg() == 0;
1186 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1187 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1192 getAddrModeThumbSPOpValue(
const MCInst &MI,
unsigned OpIdx,
1199 "Unexpected base register!");
1203 return MO1.
getImm() & 0xff;
1208 getAddrModeISOpValue(
const MCInst &MI,
unsigned OpIdx,
1216 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1217 unsigned Imm5 = MO1.
getImm();
1218 return ((Imm5 & 0x1f) << 3) | Rn;
1223 getAddrModePCOpValue(
const MCInst &MI,
unsigned OpIdx,
1229 return (MO.
getImm() >> 2);
1234 getAddrMode5OpValue(
const MCInst &MI,
unsigned OpIdx,
1245 Reg = CTX.getRegisterInfo()->getEncodingValue(
ARM::PC);
1249 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1258 ++MCNumCPRelocations;
1260 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1268 Binary |= (Reg << 9);
1274 getAddrMode5FP16OpValue(
const MCInst &MI,
unsigned OpIdx,
1285 Reg = CTX.getRegisterInfo()->getEncodingValue(
ARM::PC);
1289 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1298 ++MCNumCPRelocations;
1300 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1308 Binary |= (Reg << 9);
1312 unsigned ARMMCCodeEmitter::
1313 getSORegRegOpValue(
const MCInst &MI,
unsigned OpIdx,
1332 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1336 unsigned Rs = MO1.
getReg();
1352 Binary |= SBits << 4;
1357 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) <<
ARMII::RegRsShift);
1360 unsigned ARMMCCodeEmitter::
1361 getSORegImmOpValue(
const MCInst &MI,
unsigned OpIdx,
1377 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1400 Binary |= SBits << 4;
1402 assert(Offset < 32 &&
"Offset must be in range 0-31!");
1403 return Binary | (Offset << 7);
1407 unsigned ARMMCCodeEmitter::
1408 getT2AddrModeSORegOpValue(
const MCInst &MI,
unsigned OpNum,
1417 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1419 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.
getReg());
1426 unsigned ARMMCCodeEmitter::
1427 getT2AddrModeImm8OpValue(
const MCInst &MI,
unsigned OpNum,
1434 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.
getReg());
1439 int32_t tmp = (int32_t)MO2.
getImm();
1448 unsigned ARMMCCodeEmitter::
1449 getT2AddrModeImm8OffsetOpValue(
const MCInst &MI,
unsigned OpNum,
1456 int32_t tmp = (int32_t)MO1.
getImm();
1465 unsigned ARMMCCodeEmitter::
1466 getT2SORegOpValue(
const MCInst &MI,
unsigned OpIdx,
1482 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1500 Binary |= SBits << 4;
1508 unsigned ARMMCCodeEmitter::
1509 getBitfieldInvertedMaskOpValue(
const MCInst &MI,
unsigned Op,
1518 assert (v != 0 && lsb < 32 && msb < 32 &&
"Illegal bitfield mask!");
1519 return lsb | (msb << 5);
1522 unsigned ARMMCCodeEmitter::
1523 getRegisterListOpValue(
const MCInst &MI,
unsigned Op,
1533 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1534 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1536 unsigned Binary = 0;
1538 if (SPRRegs || DPRRegs) {
1540 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1542 Binary |= (RegNo & 0x1f) << 8;
1546 Binary |= NumRegs * 2;
1557 Binary |= 1 << RegNo;
1566 unsigned ARMMCCodeEmitter::
1567 getAddrMode6AddressOpValue(
const MCInst &MI,
unsigned Op,
1573 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.
getReg());
1580 case 8: Align = 0x01;
break;
1581 case 16: Align = 0x02;
break;
1582 case 32: Align = 0x03;
break;
1585 return RegNo | (Align << 4);
1590 unsigned ARMMCCodeEmitter::
1591 getAddrMode6OneLane32AddressOpValue(
const MCInst &MI,
unsigned Op,
1597 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.
getReg());
1605 case 2: Align = 0x00;
break;
1606 case 4: Align = 0x03;
break;
1609 return RegNo | (Align << 4);
1617 unsigned ARMMCCodeEmitter::
1618 getAddrMode6DupAddressOpValue(
const MCInst &MI,
unsigned Op,
1624 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.
getReg());
1631 case 8: Align = 0x01;
break;
1632 case 16: Align = 0x03;
break;
1635 return RegNo | (Align << 4);
1638 unsigned ARMMCCodeEmitter::
1639 getAddrMode6OffsetOpValue(
const MCInst &MI,
unsigned Op,
1643 if (MO.
getReg() == 0)
return 0x0D;
1644 return CTX.getRegisterInfo()->getEncodingValue(MO.
getReg());
1647 unsigned ARMMCCodeEmitter::
1648 getShiftRight8Imm(
const MCInst &MI,
unsigned Op,
1654 unsigned ARMMCCodeEmitter::
1655 getShiftRight16Imm(
const MCInst &MI,
unsigned Op,
1661 unsigned ARMMCCodeEmitter::
1662 getShiftRight32Imm(
const MCInst &MI,
unsigned Op,
1668 unsigned ARMMCCodeEmitter::
1669 getShiftRight64Imm(
const MCInst &MI,
unsigned Op,
1675 void ARMMCCodeEmitter::
1681 uint64_t TSFlags = Desc.
TSFlags;
1691 uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1694 if (
isThumb(STI) && Size == 4) {
1695 EmitConstant(Binary >> 16, 2, OS);
1696 EmitConstant(Binary & 0xffff, 2, OS);
1698 EmitConstant(Binary, Size, OS);
1702 #include "ARMGenMCCodeEmitter.inc"
static bool isReg(const MCInst &MI, unsigned OpNo)
void push_back(const T &Elt)
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
static unsigned char getAM3Offset(unsigned AM3Opc)
STATISTIC(NumFunctions,"Total number of functions")
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
VariantKind getKind() const
getOpcode - Get the kind of this expression.
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1...
static bool isThumb(const MCSubtargetInfo &STI)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
static int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
Function Alias Analysis false
Instances of this class represent a single low-level machine instruction.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
static unsigned getSOImmValRot(unsigned Imm)
getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount...
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
static unsigned char getAM5Offset(unsigned AM5Opc)
MCCodeEmitter - Generic instruction encoding interface.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
static unsigned getSOImmValImm(unsigned Imm)
getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value...
Lanai::Fixups FixupKind(const MCExpr *Expr)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
static int32_t encodeThumbBLOffset(int32_t offset)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
static AddrOpc getAM2Op(unsigned AM2Opc)
static unsigned getAM2Offset(unsigned AM2Opc)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned getOpcode() const
static AddrOpc getAM3Op(unsigned AM3Opc)
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getNumOperands() const
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCSubtargetInfo - Generic base class for all target subtargets.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
static AddrOpc getAM5Op(unsigned AM5Opc)
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
static unsigned getSORegOffset(unsigned Op)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This class implements an extremely fast bulk output stream that can only output to a stream...
Target specific expression.
Instances of this class represent operands of the MCInst class.
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
static ShiftOpc getSORegShOp(unsigned Op)