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LLVM
4.0.0
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#include "SelectionDAGBuilder.h"#include "SDNodeDbgValue.h"#include "llvm/ADT/BitVector.h"#include "llvm/ADT/Optional.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/Statistic.h"#include "llvm/Analysis/AliasAnalysis.h"#include "llvm/Analysis/BranchProbabilityInfo.h"#include "llvm/Analysis/ConstantFolding.h"#include "llvm/Analysis/Loads.h"#include "llvm/Analysis/TargetLibraryInfo.h"#include "llvm/Analysis/ValueTracking.h"#include "llvm/Analysis/VectorUtils.h"#include "llvm/CodeGen/Analysis.h"#include "llvm/CodeGen/FastISel.h"#include "llvm/CodeGen/FunctionLoweringInfo.h"#include "llvm/CodeGen/GCMetadata.h"#include "llvm/CodeGen/GCStrategy.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineModuleInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/SelectionDAGTargetInfo.h"#include "llvm/CodeGen/StackMaps.h"#include "llvm/CodeGen/WinEHFuncInfo.h"#include "llvm/IR/CallingConv.h"#include "llvm/IR/ConstantRange.h"#include "llvm/IR/Constants.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/DebugInfo.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/GetElementPtrTypeIterator.h"#include "llvm/IR/GlobalVariable.h"#include "llvm/IR/InlineAsm.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/IntrinsicInst.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/LLVMContext.h"#include "llvm/IR/Module.h"#include "llvm/IR/Statepoint.h"#include "llvm/MC/MCSymbol.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetFrameLowering.h"#include "llvm/Target/TargetInstrInfo.h"#include "llvm/Target/TargetIntrinsicInfo.h"#include "llvm/Target/TargetLowering.h"#include "llvm/Target/TargetOptions.h"#include "llvm/Target/TargetSubtargetInfo.h"#include <algorithm>#include <utility>#include "llvm/IR/Instruction.def"#include "llvm/CodeGen/SelectionDAGISel.h"Go to the source code of this file.
Classes | |
| class | ExtraFlags |
Macros | |
| #define | DEBUG_TYPE "isel" |
| #define | HANDLE_INST(NUM, OPCODE, CLASS) case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; |
Functions | |
| static SDValue | getCopyFromPartsVector (SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V) |
| getCopyFromPartsVector - Create a value that contains the specified legal parts combined into the value they represent. More... | |
| static SDValue | getCopyFromParts (SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, Optional< ISD::NodeType > AssertOp=None) |
| getCopyFromParts - Create a value that contains the specified legal parts combined into the value they represent. More... | |
| static void | diagnosePossiblyInvalidConstraint (LLVMContext &Ctx, const Value *V, const Twine &ErrMsg) |
| static void | getCopyToPartsVector (SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V) |
| getCopyToPartsVector - Create a series of nodes that contain the specified value split into legal parts. More... | |
| static void | getCopyToParts (SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind=ISD::ANY_EXTEND) |
| getCopyToParts - Create a series of nodes that contain the specified value split into legal parts. More... | |
| static void | findUnwindDestinations (FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, BranchProbability Prob, SmallVectorImpl< std::pair< MachineBasicBlock *, BranchProbability >> &UnwindDests) |
| When an invoke or a cleanupret unwinds to the next EH pad, there are many places it could ultimately go. More... | |
| static bool | InBlock (const Value *V, const BasicBlock *BB) |
| static SDValue | getLoadStackGuard (SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain) |
| Create a LOAD_STACK_GUARD node, and let it carry the target specific global variable if there exists one. More... | |
| static bool | isVectorReductionOp (const User *I) |
| Checks if the given instruction performs a vector reduction, in which case we have the freedom to alter the elements in the result as long as the reduction of them stays unchanged. More... | |
| static bool | hasOnlySelectUsers (const Value *Cond) |
| static bool | getUniformBase (const Value *&Ptr, SDValue &Base, SDValue &Index, SelectionDAGBuilder *SDB) |
| static SDValue | GetSignificand (SelectionDAG &DAG, SDValue Op, const SDLoc &dl) |
| GetSignificand - Get the significand and build it into a floating-point number with exponent of 1: More... | |
| static SDValue | GetExponent (SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, const SDLoc &dl) |
| GetExponent - Get the exponent: More... | |
| static SDValue | getF32Constant (SelectionDAG &DAG, unsigned Flt, const SDLoc &dl) |
| getF32Constant - Get 32-bit floating point constant. More... | |
| static SDValue | getLimitedPrecisionExp2 (SDValue t0, const SDLoc &dl, SelectionDAG &DAG) |
| static SDValue | expandExp (const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) |
| expandExp - Lower an exp intrinsic. More... | |
| static SDValue | expandLog (const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) |
| expandLog - Lower a log intrinsic. More... | |
| static SDValue | expandLog2 (const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) |
| expandLog2 - Lower a log2 intrinsic. More... | |
| static SDValue | expandLog10 (const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) |
| expandLog10 - Lower a log10 intrinsic. More... | |
| static SDValue | expandExp2 (const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) |
| expandExp2 - Lower an exp2 intrinsic. More... | |
| static SDValue | expandPow (const SDLoc &dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI) |
| visitPow - Lower a pow intrinsic. More... | |
| static SDValue | ExpandPowI (const SDLoc &DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG) |
| ExpandPowI - Expand a llvm.powi intrinsic. More... | |
| static unsigned | getUnderlyingArgReg (const SDValue &N) |
| static bool | IsOnlyUsedInZeroEqualityComparison (const Value *V) |
| IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the value is equal or not-equal to zero. More... | |
| static SDValue | getMemCmpLoad (const Value *PtrVal, MVT LoadVT, Type *LoadTy, SelectionDAGBuilder &Builder) |
| static void | patchMatchingInput (const SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &MatchingOpInfo, SelectionDAG &DAG) |
Make sure that the output operand OpInfo and its corresponding input operand MatchingOpInfo have compatible constraint types (otherwise error out). More... | |
| static SDValue | getAddressForMemoryInput (SDValue Chain, const SDLoc &Location, SDISelAsmOperandInfo &OpInfo, SelectionDAG &DAG) |
| Get a direct memory input to behave well as an indirect operand. More... | |
| static void | GetRegistersForValue (SelectionDAG &DAG, const TargetLowering &TLI, const SDLoc &DL, SDISelAsmOperandInfo &OpInfo) |
| GetRegistersForValue - Assign registers (virtual or physical) for the specified operand. More... | |
| static unsigned | findMatchingInlineAsmOperand (unsigned OperandNo, const std::vector< SDValue > &AsmNodeOperands) |
| static bool | createVirtualRegs (SmallVector< unsigned, 4 > &Regs, unsigned NumRegs, MVT RegVT, SelectionDAG &DAG) |
Fill Regs with NumRegs new virtual registers of type RegVT. More... | |
| static void | addStackMapLiveVars (ImmutableCallSite CS, unsigned StartIdx, const SDLoc &DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder) |
| Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's operand list. More... | |
| static AttributeSet | getReturnAttrs (TargetLowering::CallLoweringInfo &CLI) |
| Returns an AttributeSet representing the attributes applied to the return value of the given call. More... | |
| static bool | isOnlyUsedInEntryBlock (const Argument *A, bool FastISel) |
| isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block, return true. More... | |
| static bool | areJTsAllowed (const TargetLowering &TLI, const SwitchInst *SI) |
Variables | |
| static unsigned | LimitFloatPrecision |
| LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6, 8 or 12 bits). More... | |
| static cl::opt< unsigned, true > | LimitFPPrecision ("limit-float-precision", cl::desc("Generate low-precision inline sequences ""for some float libcalls"), cl::location(LimitFloatPrecision), cl::init(0)) |
| static cl::opt< bool > | EnableFMFInDAG ("enable-fmf-dag", cl::init(true), cl::Hidden, cl::desc("Enable fast-math-flags for DAG nodes")) |
| static cl::opt< unsigned > | JumpTableDensity ("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in ""a normal function")) |
| Minimum jump table density for normal functions. More... | |
| static cl::opt< unsigned > | OptsizeJumpTableDensity ("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in ""an optsize function")) |
| Minimum jump table density for -Os or -Oz functions. More... | |
| static const unsigned | MaxParallelChains = 64 |
| #define DEBUG_TYPE "isel" |
Definition at line 74 of file SelectionDAGBuilder.cpp.
| #define HANDLE_INST | ( | NUM, | |
| OPCODE, | |||
| CLASS | |||
| ) | case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break; |
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Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's operand list.
Constants are converted to TargetConstants purely as an optimization to avoid constant materialization and register allocation.
FrameIndex operands are converted to TargetFrameIndex so that ISEL does not generate addess computation nodes, and so ExpandISelPseudo can convert the TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids address materialization and register allocation, but may also be required for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an alloca in the entry block, then the runtime may assume that the alloca's StackMap location can be read immediately after compilation and that the location is valid at any point during execution (this is similar to the assumption made by the llvm.gcroot intrinsic). If the alloca's location were only available in a register, then the runtime would need to trap when execution reaches the StackMap in order to read the alloca's location.
Definition at line 7401 of file SelectionDAGBuilder.cpp.
References llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::arg_size(), C, llvm::StackMaps::ConstantOp, llvm::SelectionDAGBuilder::DAG, llvm::CallSiteBase< FunTy, BBTy, ValTy, UserTy, UseTy, InstrTy, CallTy, InvokeTy, IterTy >::getArgument(), llvm::SelectionDAG::getDataLayout(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAGBuilder::getValue(), i, llvm::MVT::i64, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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Definition at line 8432 of file SelectionDAGBuilder.cpp.
References llvm::ISD::BR_JT, llvm::ISD::BRIND, llvm::Function::getFnAttribute(), llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), llvm::Attribute::getValueAsString(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), and llvm::MVT::Other.
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Fill Regs with NumRegs new virtual registers of type RegVT.
Definition at line 6787 of file SelectionDAGBuilder.cpp.
References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getTargetLoweringInfo(), i, and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().
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Definition at line 258 of file SelectionDAGBuilder.cpp.
References llvm::LLVMContext::emitError(), and I.
Referenced by getCopyFromPartsVector(), and getCopyToParts().
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expandExp - Lower an exp intrinsic.
Handles the special sequences for limited-precision mode.
Definition at line 4272 of file SelectionDAGBuilder.cpp.
References llvm::MVT::f32, llvm::ISD::FEXP, llvm::ISD::FMUL, getF32Constant(), getLimitedPrecisionExp2(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), LimitFloatPrecision, and t0.
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expandExp2 - Lower an exp2 intrinsic.
Handles the special sequences for limited-precision mode.
Definition at line 4583 of file SelectionDAGBuilder.cpp.
References llvm::MVT::f32, llvm::ISD::FEXP2, getLimitedPrecisionExp2(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), and LimitFloatPrecision.
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expandLog - Lower a log intrinsic.
Handles the special sequences for limited-precision mode.
Definition at line 4295 of file SelectionDAGBuilder.cpp.
References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FLOG, llvm::ISD::FMUL, llvm::ISD::FSUB, GetExponent(), getF32Constant(), llvm::SelectionDAG::getNode(), GetSignificand(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, t0, and X.
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expandLog10 - Lower a log10 intrinsic.
Handles the special sequences for limited-precision mode.
Definition at line 4492 of file SelectionDAGBuilder.cpp.
References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FLOG10, llvm::ISD::FMUL, llvm::ISD::FSUB, GetExponent(), getF32Constant(), llvm::SelectionDAG::getNode(), GetSignificand(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, t0, and X.
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expandLog2 - Lower a log2 intrinsic.
Handles the special sequences for limited-precision mode.
Definition at line 4394 of file SelectionDAGBuilder.cpp.
References llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FLOG2, llvm::ISD::FMUL, llvm::ISD::FSUB, GetExponent(), getF32Constant(), llvm::SelectionDAG::getNode(), GetSignificand(), llvm::SDValue::getValueType(), llvm::MVT::i32, LimitFloatPrecision, t0, and X.
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visitPow - Lower a pow intrinsic.
Handles the special sequences for limited-precision mode with x == 10.0f.
Definition at line 4595 of file SelectionDAGBuilder.cpp.
References llvm::MVT::f32, llvm::ISD::FMUL, llvm::ISD::FPOW, getF32Constant(), getLimitedPrecisionExp2(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), LimitFloatPrecision, and t0.
ExpandPowI - Expand a llvm.powi intrinsic.
Definition at line 4624 of file SelectionDAGBuilder.cpp.
References llvm::countPopulation(), llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FPOWI, llvm::SelectionDAG::getConstantFP(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::Log2_32(), and llvm::Function::optForSize().
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Definition at line 6768 of file SelectionDAGBuilder.cpp.
References assert(), llvm::InlineAsm::getNumOperandRegisters(), llvm::InlineAsm::isMemKind(), llvm::InlineAsm::isRegDefEarlyClobberKind(), llvm::InlineAsm::isRegDefKind(), and llvm::InlineAsm::Op_FirstOperand.
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When an invoke or a cleanupret unwinds to the next EH pad, there are many places it could ultimately go.
In the IR, we have a single unwind destination, but in the machine CFG, we enumerate all the possible blocks. This function skips over imaginary basic blocks that hold catchswitch instructions, and finds all the "real" machine basic block destinations. As those destinations may not be successors of EHPadBB, here we also calculate the edge probability to those destinations. The passed-in Prob is the edge probability to EHPadBB.
Definition at line 1268 of file SelectionDAGBuilder.cpp.
References llvm::BasicBlock::back(), llvm::FunctionLoweringInfo::BPI, llvm::classifyEHPersonality(), llvm::CoreCLR, llvm::FunctionLoweringInfo::Fn, llvm::BranchProbabilityInfo::getEdgeProbability(), llvm::BasicBlock::getFirstNonPHI(), llvm::Function::getPersonalityFn(), llvm::FunctionLoweringInfo::MBBMap, and llvm::MSVC_CXX.
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Get a direct memory input to behave well as an indirect operand.
This may introduce stores, hence the need for a Chain.
Definition at line 6622 of file SelectionDAGBuilder.cpp.
References llvm::MachineFrameInfo::CreateStackObject(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getDataLayout(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::DataLayout::getPrefTypeAlignment(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::Value::getType(), and llvm::DataLayout::getTypeAllocSize().
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getCopyFromParts - Create a value that contains the specified legal parts combined into the value they represent.
If the parts combine to a type larger than ValueVT then AssertOp can be used to specify whether the extra bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT (ISD::AssertSext).
Definition at line 129 of file SelectionDAGBuilder.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::EVT::bitsLT(), llvm::ISD::BUILD_PAIR, llvm::MVT::f64, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getCopyFromPartsVector(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::TargetLoweringBase::hasBigEndianPartOrdering(), llvm::MipsISD::Hi, llvm::DataLayout::isBigEndian(), llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::MVT::isInteger(), llvm::EVT::isVector(), llvm::MVT::isVector(), llvm_unreachable, llvm::MipsISD::Lo, llvm::Log2_32(), llvm::ISD::OR, llvm::MVT::ppcf128, llvm::ISD::SHL, std::swap(), llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by getCopyFromPartsVector(), llvm::RegsForValue::getCopyFromRegs(), and llvm::TargetLowering::LowerCallTo().
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getCopyFromPartsVector - Create a value that contains the specified legal parts combined into the value they represent.
If the parts combine to a type larger than ValueVT then AssertOp can be used to specify whether the extra bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT (ISD::AssertSext).
Definition at line 277 of file SelectionDAGBuilder.cpp.
References assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, diagnosePossiblyInvalidConstraint(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getCopyFromParts(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SDValue::getSimpleValueType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::getVectorIdxTy(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), i, llvm::TargetLoweringBase::isTypeLegal(), and llvm::EVT::isVector().
Referenced by getCopyFromParts().
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getCopyToParts - Create a series of nodes that contain the specified value split into legal parts.
If the parts contain more bits than Val, then, for integers, ExtendKind can be used to specify how to generate the extra bits.
Definition at line 383 of file SelectionDAGBuilder.cpp.
References assert(), llvm::ISD::BITCAST, diagnosePossiblyInvalidConstraint(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getContext(), getCopyToPartsVector(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), i, llvm::DataLayout::isBigEndian(), llvm::EVT::isFloatingPoint(), llvm::MVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::MVT::isInteger(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::Log2_32(), llvm::reverse(), llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::MVT::x86mmx.
Referenced by getCopyToPartsVector(), llvm::RegsForValue::getCopyToRegs(), and llvm::TargetLowering::LowerCallTo().
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getCopyToPartsVector - Create a series of nodes that contain the specified value split into legal parts.
Definition at line 514 of file SelectionDAGBuilder.cpp.
References assert(), llvm::ISD::BITCAST, llvm::EVT::bitsGE(), llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), getCopyToParts(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), i, llvm::EVT::isVector(), llvm::MVT::isVector(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by getCopyToParts().
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GetExponent - Get the exponent:
(float)(int)(((Op & 0x7f800000) >> 23) - 127);
where Op is the hexadecimal representation of floating point value.
Definition at line 4161 of file SelectionDAGBuilder.cpp.
References llvm::ISD::AND, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::MVT::i32, llvm::ISD::SINT_TO_FP, llvm::ISD::SRL, llvm::ISD::SUB, and t0.
Referenced by expandLog(), expandLog10(), and expandLog2().
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getF32Constant - Get 32-bit floating point constant.
Definition at line 4174 of file SelectionDAGBuilder.cpp.
References llvm::lltok::APFloat, llvm::MVT::f32, llvm::SelectionDAG::getConstantFP(), and llvm::APFloatBase::IEEEsingle().
Referenced by expandExp(), expandLog(), expandLog10(), expandLog2(), expandPow(), and getLimitedPrecisionExp2().
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Definition at line 4180 of file SelectionDAGBuilder.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::MVT::f32, llvm::ISD::FADD, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), getF32Constant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::i32, LimitFloatPrecision, llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, and X.
Referenced by expandExp(), expandExp2(), and expandPow().
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Create a LOAD_STACK_GUARD node, and let it carry the target specific global variable if there exists one.
Definition at line 1968 of file SelectionDAGBuilder.cpp.
References llvm::MachineFunction::allocateMemRefsArray(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEVTAlignment(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMachineNode(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::TargetLoweringBase::getSDagStackGuard(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), AMDGPU::RuntimeMD::KernelArg::Global, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, and llvm::MachineSDNode::setMemRefs().
Referenced by llvm::SelectionDAGBuilder::visitSPDescriptorParent().
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Definition at line 5930 of file SelectionDAGBuilder.cpp.
References llvm::SelectionDAGBuilder::AA, llvm::ConstantFoldLoadFromConstPtr(), llvm::SelectionDAGBuilder::DAG, llvm::SelectionDAGBuilder::DL, llvm::ConstantExpr::getBitCast(), llvm::SelectionDAGBuilder::getCurSDLoc(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getRoot(), llvm::PointerType::getUnqual(), llvm::SDValue::getValue(), llvm::SelectionDAGBuilder::getValue(), llvm::SelectionDAGBuilder::PendingLoads, llvm::AAResults::pointsToConstantMemory(), and Ptr.
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GetRegistersForValue - Assign registers (virtual or physical) for the specified operand.
We prefer to assign virtual registers, to allow the register allocator to handle the assignment process. However, if the asm uses features that we can't model on machineinstrs, we have SDISel do the allocation. This produces generally horrible, but correct, code.
OpInfo describes the operand.
Definition at line 6667 of file SelectionDAGBuilder.cpp.
References assert(), llvm::TargetRegisterClass::begin(), llvm::ISD::BITCAST, llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetRegisterClass::end(), llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MVT::getSizeInBits(), llvm::MachineFunction::getSubtarget(), I, llvm::InlineAsm::isInput, llvm::MVT::isInteger(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), Regs, and llvm::TargetRegisterClass::vt_begin().
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Returns an AttributeSet representing the attributes applied to the return value of the given call.
Definition at line 7636 of file SelectionDAGBuilder.cpp.
References llvm::Type::getContext(), llvm::TargetLowering::CallLoweringInfo::IsInReg, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::TargetLowering::CallLoweringInfo::RetSExt, llvm::TargetLowering::CallLoweringInfo::RetTy, llvm::AttributeSet::ReturnIndex, and llvm::TargetLowering::CallLoweringInfo::RetZExt.
Referenced by llvm::TargetLowering::LowerCallTo().
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GetSignificand - Get the significand and build it into a floating-point number with exponent of 1:
Op = (Op & 0x007fffff) | 0x3f800000;
where Op is the hexadecimal representation of floating point value.
Definition at line 4148 of file SelectionDAGBuilder.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::MVT::f32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, and llvm::ISD::OR.
Referenced by expandLog(), expandLog10(), and expandLog2().
Definition at line 4679 of file SelectionDAGBuilder.cpp.
References llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::BITCAST, llvm::ISD::CopyFromReg, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getReg(), and llvm::ISD::TRUNCATE.
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Definition at line 3737 of file SelectionDAGBuilder.cpp.
References assert(), llvm::SelectionDAGBuilder::DAG, llvm::dyn_cast(), llvm::SelectionDAGBuilder::findValue(), GEP, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::Value::getType(), llvm::SelectionDAGBuilder::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorVT(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), and Ptr.
Definition at line 2697 of file SelectionDAGBuilder.cpp.
References llvm::all_of(), and llvm::Value::users().
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Definition at line 1568 of file SelectionDAGBuilder.cpp.
References llvm::Instruction::getParent().
Referenced by llvm::SelectionDAGBuilder::FindMergedConditions().
isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block, return true.
This includes arguments used by switches, since the switch may expand into multiple basic blocks.
Definition at line 7999 of file SelectionDAGBuilder.cpp.
References llvm::Function::front(), llvm::Argument::getParent(), llvm::Value::use_empty(), and llvm::Value::users().
IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the value is equal or not-equal to zero.
Definition at line 5917 of file SelectionDAGBuilder.cpp.
References C, and llvm::Value::users().
Checks if the given instruction performs a vector reduction, in which case we have the freedom to alter the elements in the result as long as the reduction of them stays unchanged.
Definition at line 2433 of file SelectionDAGBuilder.cpp.
References llvm::MCID::Add, llvm::APIntOps::And(), llvm::dyn_cast(), llvm::Instruction::getOpcode(), llvm::Value::getType(), llvm::Type::getVectorNumElements(), llvm::ConstantInt::getZExtValue(), I, i, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::Type::isVectorTy(), LLVM_FALLTHROUGH, llvm::APIntOps::Or(), llvm::Value::users(), and llvm::APIntOps::Xor().
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Make sure that the output operand OpInfo and its corresponding input operand MatchingOpInfo have compatible constraint types (otherwise error out).
Definition at line 6593 of file SelectionDAGBuilder.cpp.
References llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::report_fatal_error().
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Minimum jump table density for normal functions.
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LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6, 8 or 12 bits).
Definition at line 78 of file SelectionDAGBuilder.cpp.
Referenced by expandExp(), expandExp2(), expandLog(), expandLog10(), expandLog2(), expandPow(), and getLimitedPrecisionExp2().
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Definition at line 118 of file SelectionDAGBuilder.cpp.
1.8.6