LLVM  4.0.0
Disassembler.cpp
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1 //===-- lib/MC/Disassembler.cpp - Disassembler Public C Interface ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "Disassembler.h"
11 #include "llvm-c/Disassembler.h"
12 #include "llvm/ADT/ArrayRef.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstPrinter.h"
22 #include "llvm/MC/MCInstrDesc.h"
23 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSchedule.h"
32 #include <cassert>
33 #include <cstddef>
34 #include <cstring>
35 
36 using namespace llvm;
37 
38 // LLVMCreateDisasm() creates a disassembler for the TripleName. Symbolic
39 // disassembly is supported by passing a block of information in the DisInfo
40 // parameter and specifying the TagType and callback functions as described in
41 // the header llvm-c/Disassembler.h . The pointer to the block and the
42 // functions can all be passed as NULL. If successful, this returns a
43 // disassembler context. If not, it returns NULL.
44 //
46 LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU,
47  const char *Features, void *DisInfo, int TagType,
48  LLVMOpInfoCallback GetOpInfo,
49  LLVMSymbolLookupCallback SymbolLookUp) {
50  // Get the target.
51  std::string Error;
52  const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
53  if (!TheTarget)
54  return nullptr;
55 
56  const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TT);
57  if (!MRI)
58  return nullptr;
59 
60  // Get the assembler info needed to setup the MCContext.
61  const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, TT);
62  if (!MAI)
63  return nullptr;
64 
65  const MCInstrInfo *MII = TheTarget->createMCInstrInfo();
66  if (!MII)
67  return nullptr;
68 
69  const MCSubtargetInfo *STI =
70  TheTarget->createMCSubtargetInfo(TT, CPU, Features);
71  if (!STI)
72  return nullptr;
73 
74  // Set up the MCContext for creating symbols and MCExpr's.
75  MCContext *Ctx = new MCContext(MAI, MRI, nullptr);
76  if (!Ctx)
77  return nullptr;
78 
79  // Set up disassembler.
80  MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
81  if (!DisAsm)
82  return nullptr;
83 
84  std::unique_ptr<MCRelocationInfo> RelInfo(
85  TheTarget->createMCRelocationInfo(TT, *Ctx));
86  if (!RelInfo)
87  return nullptr;
88 
89  std::unique_ptr<MCSymbolizer> Symbolizer(TheTarget->createMCSymbolizer(
90  TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo)));
91  DisAsm->setSymbolizer(std::move(Symbolizer));
92 
93  // Set up the instruction printer.
94  int AsmPrinterVariant = MAI->getAssemblerDialect();
95  MCInstPrinter *IP = TheTarget->createMCInstPrinter(
96  Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI);
97  if (!IP)
98  return nullptr;
99 
100  LLVMDisasmContext *DC =
101  new LLVMDisasmContext(TT, DisInfo, TagType, GetOpInfo, SymbolLookUp,
102  TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
103  if (!DC)
104  return nullptr;
105 
106  DC->setCPU(CPU);
107  return DC;
108 }
109 
111 LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType,
112  LLVMOpInfoCallback GetOpInfo,
113  LLVMSymbolLookupCallback SymbolLookUp) {
114  return LLVMCreateDisasmCPUFeatures(TT, CPU, "", DisInfo, TagType, GetOpInfo,
115  SymbolLookUp);
116 }
117 
118 LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo,
119  int TagType, LLVMOpInfoCallback GetOpInfo,
120  LLVMSymbolLookupCallback SymbolLookUp) {
121  return LLVMCreateDisasmCPUFeatures(TT, "", "", DisInfo, TagType, GetOpInfo,
122  SymbolLookUp);
123 }
124 
125 //
126 // LLVMDisasmDispose() disposes of the disassembler specified by the context.
127 //
129  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
130  delete DC;
131 }
132 
133 /// \brief Emits the comments that are stored in \p DC comment stream.
134 /// Each comment in the comment stream must end with a newline.
136  formatted_raw_ostream &FormattedOS) {
137  // Flush the stream before taking its content.
138  StringRef Comments = DC->CommentsToEmit.str();
139  // Get the default information for printing a comment.
140  const MCAsmInfo *MAI = DC->getAsmInfo();
141  StringRef CommentBegin = MAI->getCommentString();
142  unsigned CommentColumn = MAI->getCommentColumn();
143  bool IsFirst = true;
144  while (!Comments.empty()) {
145  if (!IsFirst)
146  FormattedOS << '\n';
147  // Emit a line of comments.
148  FormattedOS.PadToColumn(CommentColumn);
149  size_t Position = Comments.find('\n');
150  FormattedOS << CommentBegin << ' ' << Comments.substr(0, Position);
151  // Move after the newline character.
152  Comments = Comments.substr(Position+1);
153  IsFirst = false;
154  }
155  FormattedOS.flush();
156 
157  // Tell the comment stream that the vector changed underneath it.
158  DC->CommentsToEmit.clear();
159 }
160 
161 /// \brief Gets latency information for \p Inst from the itinerary
162 /// scheduling model, based on \p DC information.
163 /// \return The maximum expected latency over all the operands or -1
164 /// if no information is available.
165 static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
166  const int NoInformationAvailable = -1;
167 
168  // Check if we have a CPU to get the itinerary information.
169  if (DC->getCPU().empty())
170  return NoInformationAvailable;
171 
172  // Get itinerary information.
173  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
175  // Get the scheduling class of the requested instruction.
176  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
177  unsigned SCClass = Desc.getSchedClass();
178 
179  int Latency = 0;
180  for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
181  ++OpIdx)
182  Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
183 
184  return Latency;
185 }
186 
187 /// \brief Gets latency information for \p Inst, based on \p DC information.
188 /// \return The maximum expected latency over all the definitions or -1
189 /// if no information is available.
190 static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
191  // Try to compute scheduling information.
192  const MCSubtargetInfo *STI = DC->getSubtargetInfo();
193  const MCSchedModel SCModel = STI->getSchedModel();
194  const int NoInformationAvailable = -1;
195 
196  // Check if we have a scheduling model for instructions.
197  if (!SCModel.hasInstrSchedModel())
198  // Try to fall back to the itinerary model if the scheduling model doesn't
199  // have a scheduling table. Note the default does not have a table.
200  return getItineraryLatency(DC, Inst);
201 
202  // Get the scheduling class of the requested instruction.
203  const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
204  unsigned SCClass = Desc.getSchedClass();
205  const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass);
206  // Resolving the variant SchedClass requires an MI to pass to
207  // SubTargetInfo::resolveSchedClass.
208  if (!SCDesc || !SCDesc->isValid() || SCDesc->isVariant())
209  return NoInformationAvailable;
210 
211  // Compute output latency.
212  int Latency = 0;
213  for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
214  DefIdx != DefEnd; ++DefIdx) {
215  // Lookup the definition's write latency in SubtargetInfo.
216  const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
217  DefIdx);
218  Latency = std::max(Latency, WLEntry->Cycles);
219  }
220 
221  return Latency;
222 }
223 
224 /// \brief Emits latency information in DC->CommentStream for \p Inst, based
225 /// on the information available in \p DC.
226 static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst) {
227  int Latency = getLatency(DC, Inst);
228 
229  // Report only interesting latencies.
230  if (Latency < 2)
231  return;
232 
233  DC->CommentStream << "Latency: " << Latency << '\n';
234 }
235 
236 //
237 // LLVMDisasmInstruction() disassembles a single instruction using the
238 // disassembler context specified in the parameter DC. The bytes of the
239 // instruction are specified in the parameter Bytes, and contains at least
240 // BytesSize number of bytes. The instruction is at the address specified by
241 // the PC parameter. If a valid instruction can be disassembled its string is
242 // returned indirectly in OutString which whos size is specified in the
243 // parameter OutStringSize. This function returns the number of bytes in the
244 // instruction or zero if there was no valid instruction. If this function
245 // returns zero the caller will have to pick how many bytes they want to step
246 // over by printing a .byte, .long etc. to continue.
247 //
248 size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes,
249  uint64_t BytesSize, uint64_t PC, char *OutString,
250  size_t OutStringSize){
251  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
252  // Wrap the pointer to the Bytes, BytesSize and PC in a MemoryObject.
253  ArrayRef<uint8_t> Data(Bytes, BytesSize);
254 
255  uint64_t Size;
256  MCInst Inst;
257  const MCDisassembler *DisAsm = DC->getDisAsm();
258  MCInstPrinter *IP = DC->getIP();
260  SmallVector<char, 64> InsnStr;
261  raw_svector_ostream Annotations(InsnStr);
262  S = DisAsm->getInstruction(Inst, Size, Data, PC,
263  /*REMOVE*/ nulls(), Annotations);
264  switch (S) {
267  // FIXME: Do something different for soft failure modes?
268  return 0;
269 
271  StringRef AnnotationsStr = Annotations.str();
272 
273  SmallVector<char, 64> InsnStr;
274  raw_svector_ostream OS(InsnStr);
275  formatted_raw_ostream FormattedOS(OS);
276  IP->printInst(&Inst, FormattedOS, AnnotationsStr, *DC->getSubtargetInfo());
277 
279  emitLatency(DC, Inst);
280 
281  emitComments(DC, FormattedOS);
282 
283  assert(OutStringSize != 0 && "Output buffer cannot be zero size");
284  size_t OutputSize = std::min(OutStringSize-1, InsnStr.size());
285  std::memcpy(OutString, InsnStr.data(), OutputSize);
286  OutString[OutputSize] = '\0'; // Terminate string.
287 
288  return Size;
289  }
290  }
291  llvm_unreachable("Invalid DecodeStatus!");
292 }
293 
294 //
295 // LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
296 // can set all the Options and 0 otherwise.
297 //
298 int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
299  if (Options & LLVMDisassembler_Option_UseMarkup){
300  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
301  MCInstPrinter *IP = DC->getIP();
302  IP->setUseMarkup(true);
303  DC->addOptions(LLVMDisassembler_Option_UseMarkup);
304  Options &= ~LLVMDisassembler_Option_UseMarkup;
305  }
307  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
308  MCInstPrinter *IP = DC->getIP();
309  IP->setPrintImmHex(true);
310  DC->addOptions(LLVMDisassembler_Option_PrintImmHex);
311  Options &= ~LLVMDisassembler_Option_PrintImmHex;
312  }
314  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
315  // Try to set up the new instruction printer.
316  const MCAsmInfo *MAI = DC->getAsmInfo();
317  const MCInstrInfo *MII = DC->getInstrInfo();
318  const MCRegisterInfo *MRI = DC->getRegisterInfo();
319  int AsmPrinterVariant = MAI->getAssemblerDialect();
320  AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0;
322  Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI);
323  if (IP) {
324  DC->setIP(IP);
325  DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant);
326  Options &= ~LLVMDisassembler_Option_AsmPrinterVariant;
327  }
328  }
330  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
331  MCInstPrinter *IP = DC->getIP();
333  DC->addOptions(LLVMDisassembler_Option_SetInstrComments);
334  Options &= ~LLVMDisassembler_Option_SetInstrComments;
335  }
336  if (Options & LLVMDisassembler_Option_PrintLatency) {
337  LLVMDisasmContext *DC = static_cast<LLVMDisasmContext *>(DCR);
338  DC->addOptions(LLVMDisassembler_Option_PrintLatency);
339  Options &= ~LLVMDisassembler_Option_PrintLatency;
340  }
341  return (Options == 0);
342 }
MCDisassembler * createMCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) const
unsigned getAssemblerDialect() const
Definition: MCAsmInfo.h:491
#define LLVMDisassembler_Option_SetInstrComments
const MCRegisterInfo * getRegisterInfo() const
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI)=0
Print the specified MCInst to the specified raw_ostream.
LLVMDisasmContextRef LLVMCreateDisasm(const char *TT, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName.
DecodeStatus
Ternary decode status.
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Superclass for all disassemblers.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
MCRegisterInfo * createMCRegInfo(StringRef TT) const
createMCRegInfo - Create a MCRegisterInfo implementation.
static void emitComments(LLVMDisasmContext *DC, formatted_raw_ostream &FormattedOS)
Emits the comments that are stored in DC comment stream.
void setPrintImmHex(bool Value)
Definition: MCInstPrinter.h:93
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:490
const std::string & getTripleName() const
void setSymbolizer(std::unique_ptr< MCSymbolizer > Symzer)
Set Symzer as the current symbolizer.
#define LLVMDisassembler_Option_UseMarkup
static const Target * lookupTarget(const std::string &Triple, std::string &Error)
lookupTarget - Lookup a target based on a target triple.
LLVMDisasmContextRef LLVMCreateDisasmCPU(const char *TT, const char *CPU, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName and a specific CPU.
StringRef getCommentString() const
Definition: MCAsmInfo.h:471
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
const MCDisassembler * getDisAsm() const
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
const MCSubtargetInfo * getSubtargetInfo() const
unsigned getCommentColumn() const
This indicates the column (zero-based) at which asm comments should be printed.
Definition: MCAsmInfo.h:469
static void emitLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Emits latency information in DC->CommentStream for Inst, based on the information available in DC...
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Context object for machine code objects.
Definition: MCContext.h:51
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
void * LLVMDisasmContextRef
An opaque reference to a disassembler context.
Itinerary data supplied by a subtarget to be used by a target.
bool isValid() const
Definition: MCSchedule.h:118
static int getLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst, based on DC information.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
MCAsmInfo * createMCAsmInfo(const MCRegisterInfo &MRI, StringRef TheTriple) const
createMCAsmInfo - Create a MCAsmInfo implementation for the specified target triple.
unsigned const MachineRegisterInfo * MRI
unsigned NumWriteLatencyEntries
Definition: MCSchedule.h:114
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:295
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
void setCommentStream(raw_ostream &OS)
Specify a stream to emit comments to.
Definition: MCInstPrinter.h:72
#define LLVMDisassembler_Option_PrintImmHex
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:199
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:587
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCRelocationInfo * createMCRelocationInfo(StringRef TT, MCContext &Ctx) const
createMCRelocationInfo - Create a target specific MCRelocationInfo.
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:219
MCInstPrinter * createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) const
static int getItineraryLatency(LLVMDisasmContext *DC, const MCInst &Inst)
Gets latency information for Inst from the itinerary scheduling model, based on DC information...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool isVariant() const
Definition: MCSchedule.h:121
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:69
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
StringRef str()
Return a StringRef for the vector contents.
Definition: raw_ostream.h:515
MCSymbolizer * createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo) const
createMCSymbolizer - Create a target specific MCSymbolizer.
const MCInstrInfo * getInstrInfo() const
LLVMDisasmContextRef LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp)
Create a disassembler for the TripleName, a specific CPU and specific feature string.
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
StringRef str() const
Explicit conversion to StringRef.
Definition: SmallString.h:267
void setUseMarkup(bool Value)
Definition: MCInstPrinter.h:86
size_t LLVMDisasmInstruction(LLVMDisasmContextRef DCR, uint8_t *Bytes, uint64_t BytesSize, uint64_t PC, char *OutString, size_t OutStringSize)
Disassemble a single instruction using the disassembler context specified in the parameter DC...
int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options)
Set the disassembler's options.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:130
#define LLVMDisassembler_Option_AsmPrinterVariant
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:556
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:41
pointer data()
Return a pointer to the vector's buffer, even if empty().
Definition: SmallVector.h:142
unsigned getNumOperands() const
Definition: MCInst.h:166
void LLVMDisasmDispose(LLVMDisasmContextRef DCR)
Dispose of a disassembler context.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
MCSubtargetInfo - Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
const FeatureBitset Features
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
const MCSchedClassDesc * SCDesc
#define LLVMDisassembler_Option_PrintLatency
char * PC