39 cl::desc(
"Disable hazard detection during preRA scheduling"));
81 bool atInsnStart =
true;
82 unsigned InstCount = 0;
94 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
127 bool NewMI,
unsigned Idx1,
128 unsigned Idx2)
const {
135 unsigned CommutableOpIdx1 = Idx1; (void)CommutableOpIdx1;
136 unsigned CommutableOpIdx2 = Idx2; (void)CommutableOpIdx2;
138 CommutableOpIdx1 == Idx1 && CommutableOpIdx2 == Idx2 &&
139 "TargetInstrInfo::CommuteInstructionImpl(): not commutable operands.");
141 "This only knows how to commute register operands so far");
157 if (HasDef && Reg0 == Reg1 &&
162 }
else if (HasDef && Reg0 == Reg2 &&
197 unsigned OpIdx2)
const {
204 "Precondition violation: MI must be commutable.");
211 unsigned &ResultIdx2,
212 unsigned CommutableOpIdx1,
213 unsigned CommutableOpIdx2) {
216 ResultIdx1 = CommutableOpIdx1;
217 ResultIdx2 = CommutableOpIdx2;
219 if (ResultIdx2 == CommutableOpIdx1)
220 ResultIdx1 = CommutableOpIdx2;
221 else if (ResultIdx2 == CommutableOpIdx2)
222 ResultIdx1 = CommutableOpIdx1;
226 if (ResultIdx1 == CommutableOpIdx1)
227 ResultIdx2 = CommutableOpIdx2;
228 else if (ResultIdx1 == CommutableOpIdx2)
229 ResultIdx2 = CommutableOpIdx1;
235 return (ResultIdx1 == CommutableOpIdx1 && ResultIdx2 == CommutableOpIdx2) ||
236 (ResultIdx1 == CommutableOpIdx2 && ResultIdx2 == CommutableOpIdx1);
243 unsigned &SrcOpIdx2)
const {
245 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
248 if (!MCID.isCommutable())
253 unsigned CommutableOpIdx1 = MCID.
getNumDefs();
254 unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
256 CommutableOpIdx1, CommutableOpIdx2))
278 bool MadeChange =
false;
281 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
288 if (MCID.OpInfo[
i].isPredicate()) {
293 }
else if (MO.
isImm()) {
294 MO.
setImm(Pred[j].getImm());
296 }
else if (MO.
isMBB()) {
297 MO.
setMBB(Pred[j].getMBB());
312 if ((*o)->isLoad()) {
314 dyn_cast_or_null<FixedStackPseudoSourceValue>(
315 (*o)->getPseudoValue())) {
316 FrameIndex =
Value->getFrameIndex();
331 if ((*o)->isStore()) {
333 dyn_cast_or_null<FixedStackPseudoSourceValue>(
334 (*o)->getPseudoValue())) {
335 FrameIndex =
Value->getFrameIndex();
345 unsigned SubIdx,
unsigned &Size,
361 if (BitOffset < 0 || BitOffset % 8)
367 assert(RC->
getSize() >= (Offset + Size) &&
"bad subregister range");
370 Offset = RC->
getSize() - (Offset + Size);
377 unsigned DestReg,
unsigned SubIdx,
404 assert(FoldIdx<2 &&
"FoldIdx refers no nonexistent operand");
412 unsigned FoldReg = FoldOp.
getReg();
413 unsigned LiveReg = LiveOp.
getReg();
416 "Cannot fold physregs");
438 unsigned StartIdx = 0;
440 case TargetOpcode::STACKMAP: {
445 case TargetOpcode::PATCHPOINT: {
451 case TargetOpcode::STATEPOINT: {
462 for (
unsigned Op : Ops) {
472 for (
unsigned i = 0;
i < StartIdx; ++
i)
479 unsigned SpillOffset;
508 for (
unsigned i = 0, e = Ops.
size();
i != e; ++
i)
515 assert(MBB &&
"foldMemoryOperand needs an inserted instruction");
528 for (
unsigned Idx : Ops) {
533 if (SubRegSize > 0 && !(SubRegSize % 8))
534 OpSize = SubRegSize / 8;
537 MemSize = std::max(MemSize, OpSize);
541 assert(MemSize &&
"Did not expect a zero-sized stack slot");
545 if (MI.
getOpcode() == TargetOpcode::STACKMAP ||
546 MI.
getOpcode() == TargetOpcode::PATCHPOINT ||
547 MI.
getOpcode() == TargetOpcode::STATEPOINT) {
562 "Folded a def to a non-store!");
565 "Folded a use to a non-load!");
586 if (
Flags == MachineMemOperand::MOStore)
613 bool &Commuted)
const {
630 return MI1->
getOpcode() == AssocOpcode &&
640 bool &Commuted)
const {
710 unsigned OpIdx[4][4] = {
732 unsigned RegA = OpA.
getReg();
733 unsigned RegB = OpB.
getReg();
734 unsigned RegX = OpX.
getReg();
735 unsigned RegY = OpY.
getReg();
736 unsigned RegC = OpC.
getReg();
753 InstrIdxForVirtReg.
insert(std::make_pair(NewVR, 0));
756 bool KillA = OpA.
isKill();
757 bool KillX = OpX.
isKill();
758 bool KillY = OpY.
isKill();
801 assert(Prev &&
"Unknown pattern for machine combiner");
803 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
815 for (
unsigned i = 0, e = Ops.
size();
i != e; ++
i)
825 if ((MI.
getOpcode() == TargetOpcode::STACKMAP ||
826 MI.
getOpcode() == TargetOpcode::PATCHPOINT ||
827 MI.
getOpcode() == TargetOpcode::STATEPOINT) &&
832 NewMI = &*MBB.
insert(MI, NewMI);
838 if (!NewMI)
return nullptr;
856 bool TargetInstrInfo::isReallyTriviallyReMaterializableGeneric(
899 if (!MO.
isReg())
continue;
921 if (MO.
isDef() && Reg != DefReg)
938 bool StackGrowsDown =
944 if (MI.
getOpcode() != FrameSetupOpcode &&
951 if ((!StackGrowsDown && MI.
getOpcode() == FrameSetupOpcode) ||
952 (StackGrowsDown && MI.
getOpcode() == FrameDestroyOpcode))
1014 SDNode *DefNode,
unsigned DefIdx,
1015 SDNode *UseNode,
unsigned UseIdx)
const {
1016 if (!ItinData || ItinData->
isEmpty())
1031 if (!ItinData || ItinData->
isEmpty())
1046 if (!ItinData || ItinData->
isEmpty())
1077 unsigned *PredCost)
const {
1088 unsigned DefIdx)
const {
1090 if (!ItinData || ItinData->
isEmpty())
1095 return (DefCycle != -1 && DefCycle <= 1);
1104 unsigned UseIdx)
const {
1137 assert(DefIdx == 0 &&
"REG_SEQUENCE only has one def");
1138 for (
unsigned OpIdx = 1, EndOpIdx = MI.
getNumOperands(); OpIdx != EndOpIdx;
1143 "One of the subindex of the reg_sequence is not an immediate");
1162 assert(DefIdx == 0 &&
"EXTRACT_SUBREG only has one def");
1166 "The subindex of the extract_subreg is not an immediate");
1185 assert(DefIdx == 0 &&
"INSERT_SUBREG only has one def");
1190 "One of the subindex of the reg_sequence is not an immediate");
1194 InsertedReg.
Reg = MOInsertedReg.
getReg();
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
virtual MachineInstr * duplicate(MachineInstr &Orig, MachineFunction &MF) const
Create a duplicate of the Orig instruction in MF.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate Root and Prev according to Pattern to reduce critical path length...
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
static MachineInstr * foldPatchpoint(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, const TargetInstrInfo &TII)
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
static cl::opt< bool > DisableHazardRecognizer("disable-sched-hazard", cl::Hidden, cl::init(false), cl::desc("Disable hazard detection during preRA scheduling"))
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
bool isExtractSubreg() const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
int NumMicroOps
of micro-ops, -1 means it's variable
StringRef getCommentString() const
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
A description of a memory reference used in the backend.
unsigned getCallFrameDestroyOpcode() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
struct fuzzer::@269 Flags
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const InstrItinerary * Itineraries
Array of itineraries selected.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, LiveIntervals *LIS=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
bool isLittleEndian() const
Layout endianness...
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Itinerary data supplied by a subtarget to be used by a target.
bool isImmutableObjectIndex(int ObjectIdx) const
isImmutableObjectIndex - Returns true if the specified index corresponds to an immutable object...
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
size_t size() const
size - Get the array size.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Instances of this class represent a single low-level machine instruction.
unsigned getKillRegState(bool B)
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
This class is intended to be used as a base class for asm properties and features specific to the tar...
mmo_iterator memoperands_end() const
bool isInsertSubreg() const
static const unsigned CommuteAnyOperandIndex
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
initializer< Ty > init(const Ty &Val)
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const InstrItineraryData * getInstrItineraries() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
void setMBB(MachineBasicBlock *MBB)
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment. ...
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
void setImm(int64_t immVal)
void setIsInternalRead(bool Val=true)
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when Inst has reassociable sibling.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
MI-level patchpoint operands.
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when Inst is both associative and commutative.
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
succ_iterator succ_begin()
unsigned getSubReg() const
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void setIsKill(bool Val=true)
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
The memory access writes data.
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
virtual const TargetFrameLowering * getFrameLowering() const
virtual unsigned getPredicationCost(const MachineInstr &MI) const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the the memory access done by this i...
Iterator for intrusive lists based on ilist_node.
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociatio...
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
virtual ~TargetInstrInfo()
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
A pair composed of a register and a sub-register index.
virtual const TargetLowering * getTargetLowering() const
Information about stack frame layout on the target.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Represents one node in the SelectionDAG.
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when Inst has reassociable operands in the same MBB.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
StackDirection getStackGrowthDirection() const
getStackGrowthDirection - Return the direction the stack grows
unsigned getSchedClass() const
Return the scheduling class for this instruction.
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1...
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const
Measure the specified inline asm to determine an approximation of its length.
MCSchedModel SchedModel
Basic machine properties.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
const char * getSeparatorString() const
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setSubReg(unsigned subReg)
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
MI-level Statepoint operands.
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
virtual void getNoopForMachoTarget(MCInst &NopInst) const
Return the noop instruction to use for a noop.
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
bool isLookupPtrRegClass() const
Set if this operand is a pointer value and it requires a callback to look up its register class...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
unsigned getMaxInstLength() const
virtual bool hasStoreToStackSlot(const MachineInstr &MI, const MachineMemOperand *&MMO, int &FrameIndex) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getVarIdx() const
Get starting index of non call related arguments (calling convention, statepoint flags, vm state and gc state).
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index...
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
bool isRegSequence() const
static const TargetRegisterClass * canFoldCopy(const MachineInstr &MI, unsigned FoldIdx)
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Machine model for scheduling, bundling, and heuristics.
bool isEmpty() const
Returns true if there are no itineraries.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
bool isInternalRead() const
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
This file describes how to lower LLVM code to machine code.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
A pair composed of a pair of a register and a sub-register index, and another sub-register index...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.