LLVM  4.0.0
X86Disassembler.cpp
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1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the X86 Disassembler.
11 // It contains code to translate the data produced by the decoder into
12 // MCInsts.
13 //
14 //
15 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
16 // 64-bit X86 instruction sets. The main decode sequence for an assembly
17 // instruction in this disassembler is:
18 //
19 // 1. Read the prefix bytes and determine the attributes of the instruction.
20 // These attributes, recorded in enum attributeBits
21 // (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM
22 // provides a mapping from bitmasks to contexts, which are represented by
23 // enum InstructionContext (ibid.).
24 //
25 // 2. Read the opcode, and determine what kind of opcode it is. The
26 // disassembler distinguishes four kinds of opcodes, which are enumerated in
27 // OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte
28 // (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a
29 // (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context.
30 //
31 // 3. Depending on the opcode type, look in one of four ClassDecision structures
32 // (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
33 // OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
34 // a ModRMDecision (ibid.).
35 //
36 // 4. Some instructions, such as escape opcodes or extended opcodes, or even
37 // instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the
38 // ModR/M byte to complete decode. The ModRMDecision's type is an entry from
39 // ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the
40 // ModR/M byte is required and how to interpret it.
41 //
42 // 5. After resolving the ModRMDecision, the disassembler has a unique ID
43 // of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in
44 // INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
45 // meanings of its operands.
46 //
47 // 6. For each operand, its encoding is an entry from OperandEncoding
48 // (X86DisassemblerDecoderCommon.h) and its type is an entry from
49 // OperandType (ibid.). The encoding indicates how to read it from the
50 // instruction; the type indicates how to interpret the value once it has
51 // been read. For example, a register operand could be stored in the R/M
52 // field of the ModR/M byte, the REG field of the ModR/M byte, or added to
53 // the main opcode. This is orthogonal from its meaning (an GPR or an XMM
54 // register, for instance). Given this information, the operands can be
55 // extracted and interpreted.
56 //
57 // 7. As the last step, the disassembler translates the instruction information
58 // and operands into a format understandable by the client - in this case, an
59 // MCInst for use by the MC infrastructure.
60 //
61 // The disassembler is broken broadly into two parts: the table emitter that
62 // emits the instruction decode tables discussed above during compilation, and
63 // the disassembler itself. The table emitter is documented in more detail in
64 // utils/TableGen/X86DisassemblerEmitter.h.
65 //
66 // X86Disassembler.cpp contains the code responsible for step 7, and for
67 // invoking the decoder to execute steps 1-6.
68 // X86DisassemblerDecoderCommon.h contains the definitions needed by both the
69 // table emitter and the disassembler.
70 // X86DisassemblerDecoder.h contains the public interface of the decoder,
71 // factored out into C for possible use by other projects.
72 // X86DisassemblerDecoder.c contains the source code of the decoder, which is
73 // responsible for steps 1-6.
74 //
75 //===----------------------------------------------------------------------===//
76 
77 #include "X86DisassemblerDecoder.h"
79 #include "llvm/MC/MCContext.h"
81 #include "llvm/MC/MCExpr.h"
82 #include "llvm/MC/MCInst.h"
83 #include "llvm/MC/MCInstrInfo.h"
85 #include "llvm/Support/Debug.h"
88 
89 using namespace llvm;
90 using namespace llvm::X86Disassembler;
91 
92 #define DEBUG_TYPE "x86-disassembler"
93 
94 void llvm::X86Disassembler::Debug(const char *file, unsigned line,
95  const char *s) {
96  dbgs() << file << ":" << line << ": " << s;
97 }
98 
100  const void *mii) {
101  const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
102  return MII->getName(Opcode);
103 }
104 
105 #define debug(s) DEBUG(Debug(__FILE__, __LINE__, s));
106 
107 namespace llvm {
108 
109 // Fill-ins to make the compiler happy. These constants are never actually
110 // assigned; they are just filler to make an automatically-generated switch
111 // statement work.
112 namespace X86 {
113  enum {
114  BX_SI = 500,
115  BX_DI = 501,
116  BP_SI = 502,
117  BP_DI = 503,
118  sib = 504,
119  sib64 = 505
120  };
121 }
122 
123 }
124 
125 static bool translateInstruction(MCInst &target,
126  InternalInstruction &source,
127  const MCDisassembler *Dis);
128 
129 namespace {
130 
131 /// Generic disassembler for all X86 platforms. All each platform class should
132 /// have to do is subclass the constructor, and provide a different
133 /// disassemblerMode value.
134 class X86GenericDisassembler : public MCDisassembler {
135  std::unique_ptr<const MCInstrInfo> MII;
136 public:
137  X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
138  std::unique_ptr<const MCInstrInfo> MII);
139 public:
140  DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
141  ArrayRef<uint8_t> Bytes, uint64_t Address,
142  raw_ostream &vStream,
143  raw_ostream &cStream) const override;
144 
145 private:
146  DisassemblerMode fMode;
147 };
148 
149 }
150 
151 X86GenericDisassembler::X86GenericDisassembler(
152  const MCSubtargetInfo &STI,
153  MCContext &Ctx,
154  std::unique_ptr<const MCInstrInfo> MII)
155  : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
156  const FeatureBitset &FB = STI.getFeatureBits();
157  if (FB[X86::Mode16Bit]) {
158  fMode = MODE_16BIT;
159  return;
160  } else if (FB[X86::Mode32Bit]) {
161  fMode = MODE_32BIT;
162  return;
163  } else if (FB[X86::Mode64Bit]) {
164  fMode = MODE_64BIT;
165  return;
166  }
167 
168  llvm_unreachable("Invalid CPU mode");
169 }
170 
171 namespace {
172 struct Region {
173  ArrayRef<uint8_t> Bytes;
174  uint64_t Base;
175  Region(ArrayRef<uint8_t> Bytes, uint64_t Base) : Bytes(Bytes), Base(Base) {}
176 };
177 } // end anonymous namespace
178 
179 /// A callback function that wraps the readByte method from Region.
180 ///
181 /// @param Arg - The generic callback parameter. In this case, this should
182 /// be a pointer to a Region.
183 /// @param Byte - A pointer to the byte to be read.
184 /// @param Address - The address to be read.
185 static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) {
186  auto *R = static_cast<const Region *>(Arg);
187  ArrayRef<uint8_t> Bytes = R->Bytes;
188  unsigned Index = Address - R->Base;
189  if (Bytes.size() <= Index)
190  return -1;
191  *Byte = Bytes[Index];
192  return 0;
193 }
194 
195 /// logger - a callback function that wraps the operator<< method from
196 /// raw_ostream.
197 ///
198 /// @param arg - The generic callback parameter. This should be a pointe
199 /// to a raw_ostream.
200 /// @param log - A string to be logged. logger() adds a newline.
201 static void logger(void* arg, const char* log) {
202  if (!arg)
203  return;
204 
205  raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
206  vStream << log << "\n";
207 }
208 
209 //
210 // Public interface for the disassembler
211 //
212 
213 MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction(
214  MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address,
215  raw_ostream &VStream, raw_ostream &CStream) const {
216  CommentStream = &CStream;
217 
218  InternalInstruction InternalInstr;
219 
220  dlog_t LoggerFn = logger;
221  if (&VStream == &nulls())
222  LoggerFn = nullptr; // Disable logging completely if it's going to nulls().
223 
224  Region R(Bytes, Address);
225 
226  int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R,
227  LoggerFn, (void *)&VStream,
228  (const void *)MII.get(), Address, fMode);
229 
230  if (Ret) {
231  Size = InternalInstr.readerCursor - Address;
232  return Fail;
233  } else {
234  Size = InternalInstr.length;
235  return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail;
236  }
237 }
238 
239 //
240 // Private code that translates from struct InternalInstructions to MCInsts.
241 //
242 
243 /// translateRegister - Translates an internal register to the appropriate LLVM
244 /// register, and appends it as an operand to an MCInst.
245 ///
246 /// @param mcInst - The MCInst to append to.
247 /// @param reg - The Reg to append.
248 static void translateRegister(MCInst &mcInst, Reg reg) {
249 #define ENTRY(x) X86::x,
250  uint8_t llvmRegnums[] = {
251  ALL_REGS
252  0
253  };
254 #undef ENTRY
255 
256  uint8_t llvmRegnum = llvmRegnums[reg];
257  mcInst.addOperand(MCOperand::createReg(llvmRegnum));
258 }
259 
260 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
261 /// immediate Value in the MCInst.
262 ///
263 /// @param Value - The immediate Value, has had any PC adjustment made by
264 /// the caller.
265 /// @param isBranch - If the instruction is a branch instruction
266 /// @param Address - The starting address of the instruction
267 /// @param Offset - The byte offset to this immediate in the instruction
268 /// @param Width - The byte width of this immediate in the instruction
269 ///
270 /// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
271 /// called then that function is called to get any symbolic information for the
272 /// immediate in the instruction using the Address, Offset and Width. If that
273 /// returns non-zero then the symbolic information it returns is used to create
274 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
275 /// returns zero and isBranch is true then a symbol look up for immediate Value
276 /// is done and if a symbol is found an MCExpr is created with that, else
277 /// an MCExpr with the immediate Value is created. This function returns true
278 /// if it adds an operand to the MCInst and false otherwise.
279 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
280  uint64_t Address, uint64_t Offset,
281  uint64_t Width, MCInst &MI,
282  const MCDisassembler *Dis) {
283  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
284  Offset, Width);
285 }
286 
287 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
288 /// referenced by a load instruction with the base register that is the rip.
289 /// These can often be addresses in a literal pool. The Address of the
290 /// instruction and its immediate Value are used to determine the address
291 /// being referenced in the literal pool entry. The SymbolLookUp call back will
292 /// return a pointer to a literal 'C' string if the referenced address is an
293 /// address into a section with 'C' string literals.
294 static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
295  const void *Decoder) {
296  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
297  Dis->tryAddingPcLoadReferenceComment(Value, Address);
298 }
299 
300 static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
301  0, // SEG_OVERRIDE_NONE
302  X86::CS,
303  X86::SS,
304  X86::DS,
305  X86::ES,
306  X86::FS,
307  X86::GS
308 };
309 
310 /// translateSrcIndex - Appends a source index operand to an MCInst.
311 ///
312 /// @param mcInst - The MCInst to append to.
313 /// @param insn - The internal instruction.
314 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
315  unsigned baseRegNo;
316 
317  if (insn.mode == MODE_64BIT)
318  baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
319  else if (insn.mode == MODE_32BIT)
320  baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
321  else {
322  assert(insn.mode == MODE_16BIT);
323  baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
324  }
325  MCOperand baseReg = MCOperand::createReg(baseRegNo);
326  mcInst.addOperand(baseReg);
327 
328  MCOperand segmentReg;
330  mcInst.addOperand(segmentReg);
331  return false;
332 }
333 
334 /// translateDstIndex - Appends a destination index operand to an MCInst.
335 ///
336 /// @param mcInst - The MCInst to append to.
337 /// @param insn - The internal instruction.
338 
339 static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
340  unsigned baseRegNo;
341 
342  if (insn.mode == MODE_64BIT)
343  baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::RDI;
344  else if (insn.mode == MODE_32BIT)
345  baseRegNo = insn.prefixPresent[0x67] ? X86::DI : X86::EDI;
346  else {
347  assert(insn.mode == MODE_16BIT);
348  baseRegNo = insn.prefixPresent[0x67] ? X86::EDI : X86::DI;
349  }
350  MCOperand baseReg = MCOperand::createReg(baseRegNo);
351  mcInst.addOperand(baseReg);
352  return false;
353 }
354 
355 /// translateImmediate - Appends an immediate operand to an MCInst.
356 ///
357 /// @param mcInst - The MCInst to append to.
358 /// @param immediate - The immediate value to append.
359 /// @param operand - The operand, as stored in the descriptor table.
360 /// @param insn - The internal instruction.
361 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
362  const OperandSpecifier &operand,
363  InternalInstruction &insn,
364  const MCDisassembler *Dis) {
365  // Sign-extend the immediate if necessary.
366 
367  OperandType type = (OperandType)operand.type;
368 
369  bool isBranch = false;
370  uint64_t pcrel = 0;
371  if (type == TYPE_RELv) {
372  isBranch = true;
373  pcrel = insn.startLocation +
374  insn.immediateOffset + insn.immediateSize;
375  switch (insn.displacementSize) {
376  default:
377  break;
378  case 1:
379  if(immediate & 0x80)
380  immediate |= ~(0xffull);
381  break;
382  case 2:
383  if(immediate & 0x8000)
384  immediate |= ~(0xffffull);
385  break;
386  case 4:
387  if(immediate & 0x80000000)
388  immediate |= ~(0xffffffffull);
389  break;
390  case 8:
391  break;
392  }
393  }
394  // By default sign-extend all X86 immediates based on their encoding.
395  else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
396  type == TYPE_IMM64 || type == TYPE_IMMv) {
397  switch (operand.encoding) {
398  default:
399  break;
400  case ENCODING_IB:
401  if(immediate & 0x80)
402  immediate |= ~(0xffull);
403  break;
404  case ENCODING_IW:
405  if(immediate & 0x8000)
406  immediate |= ~(0xffffull);
407  break;
408  case ENCODING_ID:
409  if(immediate & 0x80000000)
410  immediate |= ~(0xffffffffull);
411  break;
412  case ENCODING_IO:
413  break;
414  }
415  } else if (type == TYPE_IMM3) {
416  // Check for immediates that printSSECC can't handle.
417  if (immediate >= 8) {
418  unsigned NewOpc;
419  switch (mcInst.getOpcode()) {
420  default: llvm_unreachable("unexpected opcode");
421  case X86::CMPPDrmi: NewOpc = X86::CMPPDrmi_alt; break;
422  case X86::CMPPDrri: NewOpc = X86::CMPPDrri_alt; break;
423  case X86::CMPPSrmi: NewOpc = X86::CMPPSrmi_alt; break;
424  case X86::CMPPSrri: NewOpc = X86::CMPPSrri_alt; break;
425  case X86::CMPSDrm: NewOpc = X86::CMPSDrm_alt; break;
426  case X86::CMPSDrr: NewOpc = X86::CMPSDrr_alt; break;
427  case X86::CMPSSrm: NewOpc = X86::CMPSSrm_alt; break;
428  case X86::CMPSSrr: NewOpc = X86::CMPSSrr_alt; break;
429  case X86::VPCOMBri: NewOpc = X86::VPCOMBri_alt; break;
430  case X86::VPCOMBmi: NewOpc = X86::VPCOMBmi_alt; break;
431  case X86::VPCOMWri: NewOpc = X86::VPCOMWri_alt; break;
432  case X86::VPCOMWmi: NewOpc = X86::VPCOMWmi_alt; break;
433  case X86::VPCOMDri: NewOpc = X86::VPCOMDri_alt; break;
434  case X86::VPCOMDmi: NewOpc = X86::VPCOMDmi_alt; break;
435  case X86::VPCOMQri: NewOpc = X86::VPCOMQri_alt; break;
436  case X86::VPCOMQmi: NewOpc = X86::VPCOMQmi_alt; break;
437  case X86::VPCOMUBri: NewOpc = X86::VPCOMUBri_alt; break;
438  case X86::VPCOMUBmi: NewOpc = X86::VPCOMUBmi_alt; break;
439  case X86::VPCOMUWri: NewOpc = X86::VPCOMUWri_alt; break;
440  case X86::VPCOMUWmi: NewOpc = X86::VPCOMUWmi_alt; break;
441  case X86::VPCOMUDri: NewOpc = X86::VPCOMUDri_alt; break;
442  case X86::VPCOMUDmi: NewOpc = X86::VPCOMUDmi_alt; break;
443  case X86::VPCOMUQri: NewOpc = X86::VPCOMUQri_alt; break;
444  case X86::VPCOMUQmi: NewOpc = X86::VPCOMUQmi_alt; break;
445  }
446  // Switch opcode to the one that doesn't get special printing.
447  mcInst.setOpcode(NewOpc);
448  }
449  } else if (type == TYPE_IMM5) {
450  // Check for immediates that printAVXCC can't handle.
451  if (immediate >= 32) {
452  unsigned NewOpc;
453  switch (mcInst.getOpcode()) {
454  default: llvm_unreachable("unexpected opcode");
455  case X86::VCMPPDrmi: NewOpc = X86::VCMPPDrmi_alt; break;
456  case X86::VCMPPDrri: NewOpc = X86::VCMPPDrri_alt; break;
457  case X86::VCMPPSrmi: NewOpc = X86::VCMPPSrmi_alt; break;
458  case X86::VCMPPSrri: NewOpc = X86::VCMPPSrri_alt; break;
459  case X86::VCMPSDrm: NewOpc = X86::VCMPSDrm_alt; break;
460  case X86::VCMPSDrr: NewOpc = X86::VCMPSDrr_alt; break;
461  case X86::VCMPSSrm: NewOpc = X86::VCMPSSrm_alt; break;
462  case X86::VCMPSSrr: NewOpc = X86::VCMPSSrr_alt; break;
463  case X86::VCMPPDYrmi: NewOpc = X86::VCMPPDYrmi_alt; break;
464  case X86::VCMPPDYrri: NewOpc = X86::VCMPPDYrri_alt; break;
465  case X86::VCMPPSYrmi: NewOpc = X86::VCMPPSYrmi_alt; break;
466  case X86::VCMPPSYrri: NewOpc = X86::VCMPPSYrri_alt; break;
467  case X86::VCMPPDZrmi: NewOpc = X86::VCMPPDZrmi_alt; break;
468  case X86::VCMPPDZrri: NewOpc = X86::VCMPPDZrri_alt; break;
469  case X86::VCMPPDZrrib: NewOpc = X86::VCMPPDZrrib_alt; break;
470  case X86::VCMPPSZrmi: NewOpc = X86::VCMPPSZrmi_alt; break;
471  case X86::VCMPPSZrri: NewOpc = X86::VCMPPSZrri_alt; break;
472  case X86::VCMPPSZrrib: NewOpc = X86::VCMPPSZrrib_alt; break;
473  case X86::VCMPPDZ128rmi: NewOpc = X86::VCMPPDZ128rmi_alt; break;
474  case X86::VCMPPDZ128rri: NewOpc = X86::VCMPPDZ128rri_alt; break;
475  case X86::VCMPPSZ128rmi: NewOpc = X86::VCMPPSZ128rmi_alt; break;
476  case X86::VCMPPSZ128rri: NewOpc = X86::VCMPPSZ128rri_alt; break;
477  case X86::VCMPPDZ256rmi: NewOpc = X86::VCMPPDZ256rmi_alt; break;
478  case X86::VCMPPDZ256rri: NewOpc = X86::VCMPPDZ256rri_alt; break;
479  case X86::VCMPPSZ256rmi: NewOpc = X86::VCMPPSZ256rmi_alt; break;
480  case X86::VCMPPSZ256rri: NewOpc = X86::VCMPPSZ256rri_alt; break;
481  case X86::VCMPSDZrm_Int: NewOpc = X86::VCMPSDZrmi_alt; break;
482  case X86::VCMPSDZrr_Int: NewOpc = X86::VCMPSDZrri_alt; break;
483  case X86::VCMPSDZrrb_Int: NewOpc = X86::VCMPSDZrrb_alt; break;
484  case X86::VCMPSSZrm_Int: NewOpc = X86::VCMPSSZrmi_alt; break;
485  case X86::VCMPSSZrr_Int: NewOpc = X86::VCMPSSZrri_alt; break;
486  case X86::VCMPSSZrrb_Int: NewOpc = X86::VCMPSSZrrb_alt; break;
487  }
488  // Switch opcode to the one that doesn't get special printing.
489  mcInst.setOpcode(NewOpc);
490  }
491  } else if (type == TYPE_AVX512ICC) {
492  if (immediate >= 8 || ((immediate & 0x3) == 3)) {
493  unsigned NewOpc;
494  switch (mcInst.getOpcode()) {
495  default: llvm_unreachable("unexpected opcode");
496  case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPBZ128rmi_alt; break;
497  case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPBZ128rmik_alt; break;
498  case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPBZ128rri_alt; break;
499  case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPBZ128rrik_alt; break;
500  case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPBZ256rmi_alt; break;
501  case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPBZ256rmik_alt; break;
502  case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPBZ256rri_alt; break;
503  case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPBZ256rrik_alt; break;
504  case X86::VPCMPBZrmi: NewOpc = X86::VPCMPBZrmi_alt; break;
505  case X86::VPCMPBZrmik: NewOpc = X86::VPCMPBZrmik_alt; break;
506  case X86::VPCMPBZrri: NewOpc = X86::VPCMPBZrri_alt; break;
507  case X86::VPCMPBZrrik: NewOpc = X86::VPCMPBZrrik_alt; break;
508  case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPDZ128rmi_alt; break;
509  case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPDZ128rmib_alt; break;
510  case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPDZ128rmibk_alt; break;
511  case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPDZ128rmik_alt; break;
512  case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPDZ128rri_alt; break;
513  case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPDZ128rrik_alt; break;
514  case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPDZ256rmi_alt; break;
515  case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPDZ256rmib_alt; break;
516  case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPDZ256rmibk_alt; break;
517  case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPDZ256rmik_alt; break;
518  case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPDZ256rri_alt; break;
519  case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPDZ256rrik_alt; break;
520  case X86::VPCMPDZrmi: NewOpc = X86::VPCMPDZrmi_alt; break;
521  case X86::VPCMPDZrmib: NewOpc = X86::VPCMPDZrmib_alt; break;
522  case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPDZrmibk_alt; break;
523  case X86::VPCMPDZrmik: NewOpc = X86::VPCMPDZrmik_alt; break;
524  case X86::VPCMPDZrri: NewOpc = X86::VPCMPDZrri_alt; break;
525  case X86::VPCMPDZrrik: NewOpc = X86::VPCMPDZrrik_alt; break;
526  case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPQZ128rmi_alt; break;
527  case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPQZ128rmib_alt; break;
528  case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPQZ128rmibk_alt; break;
529  case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPQZ128rmik_alt; break;
530  case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPQZ128rri_alt; break;
531  case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPQZ128rrik_alt; break;
532  case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPQZ256rmi_alt; break;
533  case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPQZ256rmib_alt; break;
534  case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPQZ256rmibk_alt; break;
535  case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPQZ256rmik_alt; break;
536  case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPQZ256rri_alt; break;
537  case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPQZ256rrik_alt; break;
538  case X86::VPCMPQZrmi: NewOpc = X86::VPCMPQZrmi_alt; break;
539  case X86::VPCMPQZrmib: NewOpc = X86::VPCMPQZrmib_alt; break;
540  case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPQZrmibk_alt; break;
541  case X86::VPCMPQZrmik: NewOpc = X86::VPCMPQZrmik_alt; break;
542  case X86::VPCMPQZrri: NewOpc = X86::VPCMPQZrri_alt; break;
543  case X86::VPCMPQZrrik: NewOpc = X86::VPCMPQZrrik_alt; break;
544  case X86::VPCMPUBZ128rmi: NewOpc = X86::VPCMPUBZ128rmi_alt; break;
545  case X86::VPCMPUBZ128rmik: NewOpc = X86::VPCMPUBZ128rmik_alt; break;
546  case X86::VPCMPUBZ128rri: NewOpc = X86::VPCMPUBZ128rri_alt; break;
547  case X86::VPCMPUBZ128rrik: NewOpc = X86::VPCMPUBZ128rrik_alt; break;
548  case X86::VPCMPUBZ256rmi: NewOpc = X86::VPCMPUBZ256rmi_alt; break;
549  case X86::VPCMPUBZ256rmik: NewOpc = X86::VPCMPUBZ256rmik_alt; break;
550  case X86::VPCMPUBZ256rri: NewOpc = X86::VPCMPUBZ256rri_alt; break;
551  case X86::VPCMPUBZ256rrik: NewOpc = X86::VPCMPUBZ256rrik_alt; break;
552  case X86::VPCMPUBZrmi: NewOpc = X86::VPCMPUBZrmi_alt; break;
553  case X86::VPCMPUBZrmik: NewOpc = X86::VPCMPUBZrmik_alt; break;
554  case X86::VPCMPUBZrri: NewOpc = X86::VPCMPUBZrri_alt; break;
555  case X86::VPCMPUBZrrik: NewOpc = X86::VPCMPUBZrrik_alt; break;
556  case X86::VPCMPUDZ128rmi: NewOpc = X86::VPCMPUDZ128rmi_alt; break;
557  case X86::VPCMPUDZ128rmib: NewOpc = X86::VPCMPUDZ128rmib_alt; break;
558  case X86::VPCMPUDZ128rmibk: NewOpc = X86::VPCMPUDZ128rmibk_alt; break;
559  case X86::VPCMPUDZ128rmik: NewOpc = X86::VPCMPUDZ128rmik_alt; break;
560  case X86::VPCMPUDZ128rri: NewOpc = X86::VPCMPUDZ128rri_alt; break;
561  case X86::VPCMPUDZ128rrik: NewOpc = X86::VPCMPUDZ128rrik_alt; break;
562  case X86::VPCMPUDZ256rmi: NewOpc = X86::VPCMPUDZ256rmi_alt; break;
563  case X86::VPCMPUDZ256rmib: NewOpc = X86::VPCMPUDZ256rmib_alt; break;
564  case X86::VPCMPUDZ256rmibk: NewOpc = X86::VPCMPUDZ256rmibk_alt; break;
565  case X86::VPCMPUDZ256rmik: NewOpc = X86::VPCMPUDZ256rmik_alt; break;
566  case X86::VPCMPUDZ256rri: NewOpc = X86::VPCMPUDZ256rri_alt; break;
567  case X86::VPCMPUDZ256rrik: NewOpc = X86::VPCMPUDZ256rrik_alt; break;
568  case X86::VPCMPUDZrmi: NewOpc = X86::VPCMPUDZrmi_alt; break;
569  case X86::VPCMPUDZrmib: NewOpc = X86::VPCMPUDZrmib_alt; break;
570  case X86::VPCMPUDZrmibk: NewOpc = X86::VPCMPUDZrmibk_alt; break;
571  case X86::VPCMPUDZrmik: NewOpc = X86::VPCMPUDZrmik_alt; break;
572  case X86::VPCMPUDZrri: NewOpc = X86::VPCMPUDZrri_alt; break;
573  case X86::VPCMPUDZrrik: NewOpc = X86::VPCMPUDZrrik_alt; break;
574  case X86::VPCMPUQZ128rmi: NewOpc = X86::VPCMPUQZ128rmi_alt; break;
575  case X86::VPCMPUQZ128rmib: NewOpc = X86::VPCMPUQZ128rmib_alt; break;
576  case X86::VPCMPUQZ128rmibk: NewOpc = X86::VPCMPUQZ128rmibk_alt; break;
577  case X86::VPCMPUQZ128rmik: NewOpc = X86::VPCMPUQZ128rmik_alt; break;
578  case X86::VPCMPUQZ128rri: NewOpc = X86::VPCMPUQZ128rri_alt; break;
579  case X86::VPCMPUQZ128rrik: NewOpc = X86::VPCMPUQZ128rrik_alt; break;
580  case X86::VPCMPUQZ256rmi: NewOpc = X86::VPCMPUQZ256rmi_alt; break;
581  case X86::VPCMPUQZ256rmib: NewOpc = X86::VPCMPUQZ256rmib_alt; break;
582  case X86::VPCMPUQZ256rmibk: NewOpc = X86::VPCMPUQZ256rmibk_alt; break;
583  case X86::VPCMPUQZ256rmik: NewOpc = X86::VPCMPUQZ256rmik_alt; break;
584  case X86::VPCMPUQZ256rri: NewOpc = X86::VPCMPUQZ256rri_alt; break;
585  case X86::VPCMPUQZ256rrik: NewOpc = X86::VPCMPUQZ256rrik_alt; break;
586  case X86::VPCMPUQZrmi: NewOpc = X86::VPCMPUQZrmi_alt; break;
587  case X86::VPCMPUQZrmib: NewOpc = X86::VPCMPUQZrmib_alt; break;
588  case X86::VPCMPUQZrmibk: NewOpc = X86::VPCMPUQZrmibk_alt; break;
589  case X86::VPCMPUQZrmik: NewOpc = X86::VPCMPUQZrmik_alt; break;
590  case X86::VPCMPUQZrri: NewOpc = X86::VPCMPUQZrri_alt; break;
591  case X86::VPCMPUQZrrik: NewOpc = X86::VPCMPUQZrrik_alt; break;
592  case X86::VPCMPUWZ128rmi: NewOpc = X86::VPCMPUWZ128rmi_alt; break;
593  case X86::VPCMPUWZ128rmik: NewOpc = X86::VPCMPUWZ128rmik_alt; break;
594  case X86::VPCMPUWZ128rri: NewOpc = X86::VPCMPUWZ128rri_alt; break;
595  case X86::VPCMPUWZ128rrik: NewOpc = X86::VPCMPUWZ128rrik_alt; break;
596  case X86::VPCMPUWZ256rmi: NewOpc = X86::VPCMPUWZ256rmi_alt; break;
597  case X86::VPCMPUWZ256rmik: NewOpc = X86::VPCMPUWZ256rmik_alt; break;
598  case X86::VPCMPUWZ256rri: NewOpc = X86::VPCMPUWZ256rri_alt; break;
599  case X86::VPCMPUWZ256rrik: NewOpc = X86::VPCMPUWZ256rrik_alt; break;
600  case X86::VPCMPUWZrmi: NewOpc = X86::VPCMPUWZrmi_alt; break;
601  case X86::VPCMPUWZrmik: NewOpc = X86::VPCMPUWZrmik_alt; break;
602  case X86::VPCMPUWZrri: NewOpc = X86::VPCMPUWZrri_alt; break;
603  case X86::VPCMPUWZrrik: NewOpc = X86::VPCMPUWZrrik_alt; break;
604  case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPWZ128rmi_alt; break;
605  case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPWZ128rmik_alt; break;
606  case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPWZ128rri_alt; break;
607  case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPWZ128rrik_alt; break;
608  case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPWZ256rmi_alt; break;
609  case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPWZ256rmik_alt; break;
610  case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPWZ256rri_alt; break;
611  case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPWZ256rrik_alt; break;
612  case X86::VPCMPWZrmi: NewOpc = X86::VPCMPWZrmi_alt; break;
613  case X86::VPCMPWZrmik: NewOpc = X86::VPCMPWZrmik_alt; break;
614  case X86::VPCMPWZrri: NewOpc = X86::VPCMPWZrri_alt; break;
615  case X86::VPCMPWZrrik: NewOpc = X86::VPCMPWZrrik_alt; break;
616  }
617  // Switch opcode to the one that doesn't get special printing.
618  mcInst.setOpcode(NewOpc);
619  }
620  }
621 
622  switch (type) {
623  case TYPE_XMM32:
624  case TYPE_XMM64:
625  case TYPE_XMM128:
626  mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
627  return;
628  case TYPE_XMM256:
629  mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
630  return;
631  case TYPE_XMM512:
632  mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
633  return;
634  case TYPE_BNDR:
635  mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4)));
636  case TYPE_REL8:
637  isBranch = true;
638  pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
639  if (immediate & 0x80)
640  immediate |= ~(0xffull);
641  break;
642  case TYPE_REL16:
643  isBranch = true;
644  pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
645  if (immediate & 0x8000)
646  immediate |= ~(0xffffull);
647  break;
648  case TYPE_REL32:
649  case TYPE_REL64:
650  isBranch = true;
651  pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
652  if(immediate & 0x80000000)
653  immediate |= ~(0xffffffffull);
654  break;
655  default:
656  // operand is 64 bits wide. Do nothing.
657  break;
658  }
659 
660  if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
661  insn.immediateOffset, insn.immediateSize,
662  mcInst, Dis))
663  mcInst.addOperand(MCOperand::createImm(immediate));
664 
665  if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 ||
666  type == TYPE_MOFFS32 || type == TYPE_MOFFS64) {
667  MCOperand segmentReg;
669  mcInst.addOperand(segmentReg);
670  }
671 }
672 
673 /// translateRMRegister - Translates a register stored in the R/M field of the
674 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
675 /// @param mcInst - The MCInst to append to.
676 /// @param insn - The internal instruction to extract the R/M field
677 /// from.
678 /// @return - 0 on success; -1 otherwise
679 static bool translateRMRegister(MCInst &mcInst,
680  InternalInstruction &insn) {
681  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
682  debug("A R/M register operand may not have a SIB byte");
683  return true;
684  }
685 
686  switch (insn.eaBase) {
687  default:
688  debug("Unexpected EA base register");
689  return true;
690  case EA_BASE_NONE:
691  debug("EA_BASE_NONE for ModR/M base");
692  return true;
693 #define ENTRY(x) case EA_BASE_##x:
695 #undef ENTRY
696  debug("A R/M register operand may not have a base; "
697  "the operand must be a register.");
698  return true;
699 #define ENTRY(x) \
700  case EA_REG_##x: \
701  mcInst.addOperand(MCOperand::createReg(X86::x)); break;
702  ALL_REGS
703 #undef ENTRY
704  }
705 
706  return false;
707 }
708 
709 /// translateRMMemory - Translates a memory operand stored in the Mod and R/M
710 /// fields of an internal instruction (and possibly its SIB byte) to a memory
711 /// operand in LLVM's format, and appends it to an MCInst.
712 ///
713 /// @param mcInst - The MCInst to append to.
714 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
715 /// from.
716 /// @return - 0 on success; nonzero otherwise
717 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
718  const MCDisassembler *Dis) {
719  // Addresses in an MCInst are represented as five operands:
720  // 1. basereg (register) The R/M base, or (if there is a SIB) the
721  // SIB base
722  // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
723  // scale amount
724  // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
725  // the index (which is multiplied by the
726  // scale amount)
727  // 4. displacement (immediate) 0, or the displacement if there is one
728  // 5. segmentreg (register) x86_registerNONE for now, but could be set
729  // if we have segment overrides
730 
731  MCOperand baseReg;
732  MCOperand scaleAmount;
733  MCOperand indexReg;
734  MCOperand displacement;
735  MCOperand segmentReg;
736  uint64_t pcrel = 0;
737 
738  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
739  if (insn.sibBase != SIB_BASE_NONE) {
740  switch (insn.sibBase) {
741  default:
742  debug("Unexpected sibBase");
743  return true;
744 #define ENTRY(x) \
745  case SIB_BASE_##x: \
746  baseReg = MCOperand::createReg(X86::x); break;
748 #undef ENTRY
749  }
750  } else {
751  baseReg = MCOperand::createReg(0);
752  }
753 
754  // Check whether we are handling VSIB addressing mode for GATHER.
755  // If sibIndex was set to SIB_INDEX_NONE, index offset is 4 and
756  // we should use SIB_INDEX_XMM4|YMM4 for VSIB.
757  // I don't see a way to get the correct IndexReg in readSIB:
758  // We can tell whether it is VSIB or SIB after instruction ID is decoded,
759  // but instruction ID may not be decoded yet when calling readSIB.
760  uint32_t Opcode = mcInst.getOpcode();
761  bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
762  Opcode == X86::VGATHERDPDYrm ||
763  Opcode == X86::VGATHERQPDrm ||
764  Opcode == X86::VGATHERDPSrm ||
765  Opcode == X86::VGATHERQPSrm ||
766  Opcode == X86::VPGATHERDQrm ||
767  Opcode == X86::VPGATHERDQYrm ||
768  Opcode == X86::VPGATHERQQrm ||
769  Opcode == X86::VPGATHERDDrm ||
770  Opcode == X86::VPGATHERQDrm);
771  bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
772  Opcode == X86::VGATHERDPSYrm ||
773  Opcode == X86::VGATHERQPSYrm ||
774  Opcode == X86::VGATHERDPDZrm ||
775  Opcode == X86::VPGATHERDQZrm ||
776  Opcode == X86::VPGATHERQQYrm ||
777  Opcode == X86::VPGATHERDDYrm ||
778  Opcode == X86::VPGATHERQDYrm);
779  bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm ||
780  Opcode == X86::VGATHERDPSZrm ||
781  Opcode == X86::VGATHERQPSZrm ||
782  Opcode == X86::VPGATHERQQZrm ||
783  Opcode == X86::VPGATHERDDZrm ||
784  Opcode == X86::VPGATHERQDZrm);
785  if (IndexIs128 || IndexIs256 || IndexIs512) {
786  unsigned IndexOffset = insn.sibIndex -
787  (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX);
788  SIBIndex IndexBase = IndexIs512 ? SIB_INDEX_ZMM0 :
789  IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0;
790  insn.sibIndex = (SIBIndex)(IndexBase +
791  (insn.sibIndex == SIB_INDEX_NONE ? 4 : IndexOffset));
792  }
793 
794  if (insn.sibIndex != SIB_INDEX_NONE) {
795  switch (insn.sibIndex) {
796  default:
797  debug("Unexpected sibIndex");
798  return true;
799 #define ENTRY(x) \
800  case SIB_INDEX_##x: \
801  indexReg = MCOperand::createReg(X86::x); break;
804  REGS_XMM
805  REGS_YMM
806  REGS_ZMM
807 #undef ENTRY
808  }
809  } else {
810  indexReg = MCOperand::createReg(0);
811  }
812 
813  scaleAmount = MCOperand::createImm(insn.sibScale);
814  } else {
815  switch (insn.eaBase) {
816  case EA_BASE_NONE:
817  if (insn.eaDisplacement == EA_DISP_NONE) {
818  debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
819  return true;
820  }
821  if (insn.mode == MODE_64BIT){
822  pcrel = insn.startLocation +
825  insn.displacementOffset,
826  insn.displacement + pcrel, Dis);
827  baseReg = MCOperand::createReg(X86::RIP); // Section 2.2.1.6
828  }
829  else
830  baseReg = MCOperand::createReg(0);
831 
832  indexReg = MCOperand::createReg(0);
833  break;
834  case EA_BASE_BX_SI:
835  baseReg = MCOperand::createReg(X86::BX);
836  indexReg = MCOperand::createReg(X86::SI);
837  break;
838  case EA_BASE_BX_DI:
839  baseReg = MCOperand::createReg(X86::BX);
840  indexReg = MCOperand::createReg(X86::DI);
841  break;
842  case EA_BASE_BP_SI:
843  baseReg = MCOperand::createReg(X86::BP);
844  indexReg = MCOperand::createReg(X86::SI);
845  break;
846  case EA_BASE_BP_DI:
847  baseReg = MCOperand::createReg(X86::BP);
848  indexReg = MCOperand::createReg(X86::DI);
849  break;
850  default:
851  indexReg = MCOperand::createReg(0);
852  switch (insn.eaBase) {
853  default:
854  debug("Unexpected eaBase");
855  return true;
856  // Here, we will use the fill-ins defined above. However,
857  // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
858  // sib and sib64 were handled in the top-level if, so they're only
859  // placeholders to keep the compiler happy.
860 #define ENTRY(x) \
861  case EA_BASE_##x: \
862  baseReg = MCOperand::createReg(X86::x); break;
864 #undef ENTRY
865 #define ENTRY(x) case EA_REG_##x:
866  ALL_REGS
867 #undef ENTRY
868  debug("A R/M memory operand may not be a register; "
869  "the base field must be a base.");
870  return true;
871  }
872  }
873 
874  scaleAmount = MCOperand::createImm(1);
875  }
876 
877  displacement = MCOperand::createImm(insn.displacement);
878 
880 
881  mcInst.addOperand(baseReg);
882  mcInst.addOperand(scaleAmount);
883  mcInst.addOperand(indexReg);
884  if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
886  insn.displacementSize, mcInst, Dis))
887  mcInst.addOperand(displacement);
888  mcInst.addOperand(segmentReg);
889  return false;
890 }
891 
892 /// translateRM - Translates an operand stored in the R/M (and possibly SIB)
893 /// byte of an instruction to LLVM form, and appends it to an MCInst.
894 ///
895 /// @param mcInst - The MCInst to append to.
896 /// @param operand - The operand, as stored in the descriptor table.
897 /// @param insn - The instruction to extract Mod, R/M, and SIB fields
898 /// from.
899 /// @return - 0 on success; nonzero otherwise
900 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
901  InternalInstruction &insn, const MCDisassembler *Dis) {
902  switch (operand.type) {
903  default:
904  debug("Unexpected type for a R/M operand");
905  return true;
906  case TYPE_R8:
907  case TYPE_R16:
908  case TYPE_R32:
909  case TYPE_R64:
910  case TYPE_Rv:
911  case TYPE_MM64:
912  case TYPE_XMM32:
913  case TYPE_XMM64:
914  case TYPE_XMM128:
915  case TYPE_XMM256:
916  case TYPE_XMM512:
917  case TYPE_VK1:
918  case TYPE_VK2:
919  case TYPE_VK4:
920  case TYPE_VK8:
921  case TYPE_VK16:
922  case TYPE_VK32:
923  case TYPE_VK64:
924  case TYPE_DEBUGREG:
925  case TYPE_CONTROLREG:
926  case TYPE_BNDR:
927  return translateRMRegister(mcInst, insn);
928  case TYPE_M:
929  case TYPE_M8:
930  case TYPE_M16:
931  case TYPE_M32:
932  case TYPE_M64:
933  case TYPE_M128:
934  case TYPE_M256:
935  case TYPE_M512:
936  case TYPE_Mv:
937  case TYPE_M32FP:
938  case TYPE_M64FP:
939  case TYPE_M80FP:
940  case TYPE_M1616:
941  case TYPE_M1632:
942  case TYPE_M1664:
943  case TYPE_LEA:
944  return translateRMMemory(mcInst, insn, Dis);
945  }
946 }
947 
948 /// translateFPRegister - Translates a stack position on the FPU stack to its
949 /// LLVM form, and appends it to an MCInst.
950 ///
951 /// @param mcInst - The MCInst to append to.
952 /// @param stackPos - The stack position to translate.
953 static void translateFPRegister(MCInst &mcInst,
954  uint8_t stackPos) {
955  mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
956 }
957 
958 /// translateMaskRegister - Translates a 3-bit mask register number to
959 /// LLVM form, and appends it to an MCInst.
960 ///
961 /// @param mcInst - The MCInst to append to.
962 /// @param maskRegNum - Number of mask register from 0 to 7.
963 /// @return - false on success; true otherwise.
964 static bool translateMaskRegister(MCInst &mcInst,
965  uint8_t maskRegNum) {
966  if (maskRegNum >= 8) {
967  debug("Invalid mask register number");
968  return true;
969  }
970 
971  mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
972  return false;
973 }
974 
975 /// translateOperand - Translates an operand stored in an internal instruction
976 /// to LLVM's format and appends it to an MCInst.
977 ///
978 /// @param mcInst - The MCInst to append to.
979 /// @param operand - The operand, as stored in the descriptor table.
980 /// @param insn - The internal instruction.
981 /// @return - false on success; true otherwise.
982 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
983  InternalInstruction &insn,
984  const MCDisassembler *Dis) {
985  switch (operand.encoding) {
986  default:
987  debug("Unhandled operand encoding during translation");
988  return true;
989  case ENCODING_REG:
990  translateRegister(mcInst, insn.reg);
991  return false;
992  case ENCODING_WRITEMASK:
993  return translateMaskRegister(mcInst, insn.writemask);
995  return translateRM(mcInst, operand, insn, Dis);
996  case ENCODING_IB:
997  case ENCODING_IW:
998  case ENCODING_ID:
999  case ENCODING_IO:
1000  case ENCODING_Iv:
1001  case ENCODING_Ia:
1002  translateImmediate(mcInst,
1003  insn.immediates[insn.numImmediatesTranslated++],
1004  operand,
1005  insn,
1006  Dis);
1007  return false;
1008  case ENCODING_SI:
1009  return translateSrcIndex(mcInst, insn);
1010  case ENCODING_DI:
1011  return translateDstIndex(mcInst, insn);
1012  case ENCODING_RB:
1013  case ENCODING_RW:
1014  case ENCODING_RD:
1015  case ENCODING_RO:
1016  case ENCODING_Rv:
1017  translateRegister(mcInst, insn.opcodeRegister);
1018  return false;
1019  case ENCODING_FP:
1020  translateFPRegister(mcInst, insn.modRM & 7);
1021  return false;
1022  case ENCODING_VVVV:
1023  translateRegister(mcInst, insn.vvvv);
1024  return false;
1025  case ENCODING_DUP:
1026  return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
1027  insn, Dis);
1028  }
1029 }
1030 
1031 /// translateInstruction - Translates an internal instruction and all its
1032 /// operands to an MCInst.
1033 ///
1034 /// @param mcInst - The MCInst to populate with the instruction's data.
1035 /// @param insn - The internal instruction.
1036 /// @return - false on success; true otherwise.
1037 static bool translateInstruction(MCInst &mcInst,
1038  InternalInstruction &insn,
1039  const MCDisassembler *Dis) {
1040  if (!insn.spec) {
1041  debug("Instruction has no specification");
1042  return true;
1043  }
1044 
1045  mcInst.clear();
1046  mcInst.setOpcode(insn.instructionID);
1047  // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
1048  // prefix bytes should be disassembled as xrelease and xacquire then set the
1049  // opcode to those instead of the rep and repne opcodes.
1050  if (insn.xAcquireRelease) {
1051  if(mcInst.getOpcode() == X86::REP_PREFIX)
1052  mcInst.setOpcode(X86::XRELEASE_PREFIX);
1053  else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
1054  mcInst.setOpcode(X86::XACQUIRE_PREFIX);
1055  }
1056 
1057  insn.numImmediatesTranslated = 0;
1058 
1059  for (const auto &Op : insn.operands) {
1060  if (Op.encoding != ENCODING_NONE) {
1061  if (translateOperand(mcInst, Op, insn, Dis)) {
1062  return true;
1063  }
1064  }
1065  }
1066 
1067  return false;
1068 }
1069 
1071  const MCSubtargetInfo &STI,
1072  MCContext &Ctx) {
1073  std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
1074  return new X86GenericDisassembler(STI, Ctx, std::move(MII));
1075 }
1076 
1078  // Register the disassembler.
1083 }
void clear()
Definition: MCInst.h:172
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
#define ALL_REGS
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
SIBIndex
All possible values of the SIB index field.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
#define Fail
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
Reg
All possible values of the reg field in the ModR/M byte.
#define ALL_EA_BASES
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst...
#define EA_BASES_64BIT
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form, and appends it to an MCInst.
Context object for machine code objects.
Definition: MCContext.h:51
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register, and appends it as an operand to an MCInst.
static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
Region(BasicBlock *Entry, BasicBlock *Exit, RegionInfo *RI, DominatorTree *DT, Region *Parent=nullptr)
Definition: RegionInfo.cpp:64
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
The specification for how to extract and interpret one operand.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address)
A callback function that wraps the readByte method from Region.
#define ALL_SIB_BASES
#define CASE_ENCODING_RM
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
uint32_t Offset
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
dot regions Print regions of function to dot file(with no function bodies)"
void Debug(const char *file, unsigned line, const char *s)
Print a message to debugs()
The x86 internal instruction, which is produced by the decoder.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
StringRef GetInstrName(unsigned Opcode, const void *mii)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setOpcode(unsigned Op)
Definition: MCInst.h:158
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void(* dlog_t)(void *arg, const char *log)
Type for the logging function that the consumer can provide to get debugging output from the decoder...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void LLVMInitializeX86Disassembler()
#define debug(s)
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
#define Success
#define REGS_ZMM
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
OperandType
Types of operands to CF instructions.
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
MCSubtargetInfo - Generic base class for all target subtargets.
#define REGS_XMM
static void logger(void *arg, const char *log)
logger - a callback function that wraps the operator<< method from raw_ostream.
Target & getTheX86_32Target()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
LLVM Value Representation.
Definition: Value.h:71
raw_ostream & nulls()
This returns a reference to a raw_ostream which simply discards output.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const MCDisassembler *Dis)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
#define REGS_YMM
#define EA_BASES_32BIT
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
Target & getTheX86_64Target()
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
DisassemblerMode
Decoding mode for the Intel disassembler.