LLVM  4.0.0
ScheduleDAG.cpp
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1 //===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
12 //
13 //===----------------------------------------------------------------------===//
14 
19 #include "llvm/Support/Debug.h"
25 #include <climits>
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "pre-RA-sched"
29 
30 #ifndef NDEBUG
32  "stress-sched", cl::Hidden, cl::init(false),
33  cl::desc("Stress test instruction scheduling"));
34 #endif
35 
36 void SchedulingPriorityQueue::anchor() { }
37 
39  : TM(mf.getTarget()), TII(mf.getSubtarget().getInstrInfo()),
40  TRI(mf.getSubtarget().getRegisterInfo()), MF(mf),
41  MRI(mf.getRegInfo()), EntrySU(), ExitSU() {
42 #ifndef NDEBUG
44 #endif
45 }
46 
48 
49 /// Clear the DAG state (e.g. between scheduling regions).
51  SUnits.clear();
52  EntrySU = SUnit();
53  ExitSU = SUnit();
54 }
55 
56 /// getInstrDesc helper to handle SDNodes.
57 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
58  if (!Node || !Node->isMachineOpcode()) return nullptr;
59  return &TII->get(Node->getMachineOpcode());
60 }
61 
62 /// addPred - This adds the specified edge as a pred of the current node if
63 /// not already. It also adds the current node as a successor of the
64 /// specified node.
65 bool SUnit::addPred(const SDep &D, bool Required) {
66  // If this node already has this dependence, don't add a redundant one.
67  for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end();
68  I != E; ++I) {
69  // Zero-latency weak edges may be added purely for heuristic ordering. Don't
70  // add them if another kind of edge already exists.
71  if (!Required && I->getSUnit() == D.getSUnit())
72  return false;
73  if (I->overlaps(D)) {
74  // Extend the latency if needed. Equivalent to removePred(I) + addPred(D).
75  if (I->getLatency() < D.getLatency()) {
76  SUnit *PredSU = I->getSUnit();
77  // Find the corresponding successor in N.
78  SDep ForwardD = *I;
79  ForwardD.setSUnit(this);
80  for (SmallVectorImpl<SDep>::iterator II = PredSU->Succs.begin(),
81  EE = PredSU->Succs.end(); II != EE; ++II) {
82  if (*II == ForwardD) {
83  II->setLatency(D.getLatency());
84  break;
85  }
86  }
87  I->setLatency(D.getLatency());
88  }
89  return false;
90  }
91  }
92  // Now add a corresponding succ to N.
93  SDep P = D;
94  P.setSUnit(this);
95  SUnit *N = D.getSUnit();
96  // Update the bookkeeping.
97  if (D.getKind() == SDep::Data) {
98  assert(NumPreds < UINT_MAX && "NumPreds will overflow!");
99  assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!");
100  ++NumPreds;
101  ++N->NumSuccs;
102  }
103  if (!N->isScheduled) {
104  if (D.isWeak()) {
105  ++WeakPredsLeft;
106  }
107  else {
108  assert(NumPredsLeft < UINT_MAX && "NumPredsLeft will overflow!");
109  ++NumPredsLeft;
110  }
111  }
112  if (!isScheduled) {
113  if (D.isWeak()) {
114  ++N->WeakSuccsLeft;
115  }
116  else {
117  assert(N->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
118  ++N->NumSuccsLeft;
119  }
120  }
121  Preds.push_back(D);
122  N->Succs.push_back(P);
123  if (P.getLatency() != 0) {
124  this->setDepthDirty();
125  N->setHeightDirty();
126  }
127  return true;
128 }
129 
130 /// removePred - This removes the specified edge as a pred of the current
131 /// node if it exists. It also removes the current node as a successor of
132 /// the specified node.
133 void SUnit::removePred(const SDep &D) {
134  // Find the matching predecessor.
135  for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end();
136  I != E; ++I)
137  if (*I == D) {
138  // Find the corresponding successor in N.
139  SDep P = D;
140  P.setSUnit(this);
141  SUnit *N = D.getSUnit();
143  assert(Succ != N->Succs.end() && "Mismatching preds / succs lists!");
144  N->Succs.erase(Succ);
145  Preds.erase(I);
146  // Update the bookkeeping.
147  if (P.getKind() == SDep::Data) {
148  assert(NumPreds > 0 && "NumPreds will underflow!");
149  assert(N->NumSuccs > 0 && "NumSuccs will underflow!");
150  --NumPreds;
151  --N->NumSuccs;
152  }
153  if (!N->isScheduled) {
154  if (D.isWeak())
155  --WeakPredsLeft;
156  else {
157  assert(NumPredsLeft > 0 && "NumPredsLeft will underflow!");
158  --NumPredsLeft;
159  }
160  }
161  if (!isScheduled) {
162  if (D.isWeak())
163  --N->WeakSuccsLeft;
164  else {
165  assert(N->NumSuccsLeft > 0 && "NumSuccsLeft will underflow!");
166  --N->NumSuccsLeft;
167  }
168  }
169  if (P.getLatency() != 0) {
170  this->setDepthDirty();
171  N->setHeightDirty();
172  }
173  return;
174  }
175 }
176 
177 void SUnit::setDepthDirty() {
178  if (!isDepthCurrent) return;
179  SmallVector<SUnit*, 8> WorkList;
180  WorkList.push_back(this);
181  do {
182  SUnit *SU = WorkList.pop_back_val();
183  SU->isDepthCurrent = false;
184  for (SUnit::const_succ_iterator I = SU->Succs.begin(),
185  E = SU->Succs.end(); I != E; ++I) {
186  SUnit *SuccSU = I->getSUnit();
187  if (SuccSU->isDepthCurrent)
188  WorkList.push_back(SuccSU);
189  }
190  } while (!WorkList.empty());
191 }
192 
194  if (!isHeightCurrent) return;
195  SmallVector<SUnit*, 8> WorkList;
196  WorkList.push_back(this);
197  do {
198  SUnit *SU = WorkList.pop_back_val();
199  SU->isHeightCurrent = false;
200  for (SUnit::const_pred_iterator I = SU->Preds.begin(),
201  E = SU->Preds.end(); I != E; ++I) {
202  SUnit *PredSU = I->getSUnit();
203  if (PredSU->isHeightCurrent)
204  WorkList.push_back(PredSU);
205  }
206  } while (!WorkList.empty());
207 }
208 
209 /// setDepthToAtLeast - Update this node's successors to reflect the
210 /// fact that this node's depth just increased.
211 ///
212 void SUnit::setDepthToAtLeast(unsigned NewDepth) {
213  if (NewDepth <= getDepth())
214  return;
215  setDepthDirty();
216  Depth = NewDepth;
217  isDepthCurrent = true;
218 }
219 
220 /// setHeightToAtLeast - Update this node's predecessors to reflect the
221 /// fact that this node's height just increased.
222 ///
223 void SUnit::setHeightToAtLeast(unsigned NewHeight) {
224  if (NewHeight <= getHeight())
225  return;
226  setHeightDirty();
227  Height = NewHeight;
228  isHeightCurrent = true;
229 }
230 
231 /// ComputeDepth - Calculate the maximal path from the node to the exit.
232 ///
233 void SUnit::ComputeDepth() {
234  SmallVector<SUnit*, 8> WorkList;
235  WorkList.push_back(this);
236  do {
237  SUnit *Cur = WorkList.back();
238 
239  bool Done = true;
240  unsigned MaxPredDepth = 0;
241  for (SUnit::const_pred_iterator I = Cur->Preds.begin(),
242  E = Cur->Preds.end(); I != E; ++I) {
243  SUnit *PredSU = I->getSUnit();
244  if (PredSU->isDepthCurrent)
245  MaxPredDepth = std::max(MaxPredDepth,
246  PredSU->Depth + I->getLatency());
247  else {
248  Done = false;
249  WorkList.push_back(PredSU);
250  }
251  }
252 
253  if (Done) {
254  WorkList.pop_back();
255  if (MaxPredDepth != Cur->Depth) {
256  Cur->setDepthDirty();
257  Cur->Depth = MaxPredDepth;
258  }
259  Cur->isDepthCurrent = true;
260  }
261  } while (!WorkList.empty());
262 }
263 
264 /// ComputeHeight - Calculate the maximal path from the node to the entry.
265 ///
266 void SUnit::ComputeHeight() {
267  SmallVector<SUnit*, 8> WorkList;
268  WorkList.push_back(this);
269  do {
270  SUnit *Cur = WorkList.back();
271 
272  bool Done = true;
273  unsigned MaxSuccHeight = 0;
274  for (SUnit::const_succ_iterator I = Cur->Succs.begin(),
275  E = Cur->Succs.end(); I != E; ++I) {
276  SUnit *SuccSU = I->getSUnit();
277  if (SuccSU->isHeightCurrent)
278  MaxSuccHeight = std::max(MaxSuccHeight,
279  SuccSU->Height + I->getLatency());
280  else {
281  Done = false;
282  WorkList.push_back(SuccSU);
283  }
284  }
285 
286  if (Done) {
287  WorkList.pop_back();
288  if (MaxSuccHeight != Cur->Height) {
289  Cur->setHeightDirty();
290  Cur->Height = MaxSuccHeight;
291  }
292  Cur->isHeightCurrent = true;
293  }
294  } while (!WorkList.empty());
295 }
296 
298  if (NumPreds < 2)
299  return;
300 
301  SUnit::pred_iterator BestI = Preds.begin();
302  unsigned MaxDepth = BestI->getSUnit()->getDepth();
303  for (SUnit::pred_iterator I = std::next(BestI), E = Preds.end(); I != E;
304  ++I) {
305  if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth)
306  BestI = I;
307  }
308  if (BestI != Preds.begin())
309  std::swap(*Preds.begin(), *BestI);
310 }
311 
312 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
313 void SUnit::print(raw_ostream &OS, const ScheduleDAG *DAG) const {
314  if (this == &DAG->ExitSU)
315  OS << "ExitSU";
316  else if (this == &DAG->EntrySU)
317  OS << "EntrySU";
318  else
319  OS << "SU(" << NodeNum << ")";
320 }
321 
322 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
323 /// a group of nodes flagged together.
324 void SUnit::dump(const ScheduleDAG *G) const {
325  print(dbgs(), G);
326  dbgs() << ": ";
327  G->dumpNode(this);
328 }
329 
330 void SUnit::dumpAll(const ScheduleDAG *G) const {
331  dump(G);
332 
333  dbgs() << " # preds left : " << NumPredsLeft << "\n";
334  dbgs() << " # succs left : " << NumSuccsLeft << "\n";
335  if (WeakPredsLeft)
336  dbgs() << " # weak preds left : " << WeakPredsLeft << "\n";
337  if (WeakSuccsLeft)
338  dbgs() << " # weak succs left : " << WeakSuccsLeft << "\n";
339  dbgs() << " # rdefs left : " << NumRegDefsLeft << "\n";
340  dbgs() << " Latency : " << Latency << "\n";
341  dbgs() << " Depth : " << getDepth() << "\n";
342  dbgs() << " Height : " << getHeight() << "\n";
343 
344  if (Preds.size() != 0) {
345  dbgs() << " Predecessors:\n";
346  for (SUnit::const_succ_iterator I = Preds.begin(), E = Preds.end();
347  I != E; ++I) {
348  dbgs() << " ";
349  switch (I->getKind()) {
350  case SDep::Data: dbgs() << "data "; break;
351  case SDep::Anti: dbgs() << "anti "; break;
352  case SDep::Output: dbgs() << "out "; break;
353  case SDep::Order: dbgs() << "ord "; break;
354  }
355  I->getSUnit()->print(dbgs(), G);
356  if (I->isArtificial())
357  dbgs() << " *";
358  dbgs() << ": Latency=" << I->getLatency();
359  if (I->isAssignedRegDep())
360  dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
361  dbgs() << "\n";
362  }
363  }
364  if (Succs.size() != 0) {
365  dbgs() << " Successors:\n";
366  for (SUnit::const_succ_iterator I = Succs.begin(), E = Succs.end();
367  I != E; ++I) {
368  dbgs() << " ";
369  switch (I->getKind()) {
370  case SDep::Data: dbgs() << "data "; break;
371  case SDep::Anti: dbgs() << "anti "; break;
372  case SDep::Output: dbgs() << "out "; break;
373  case SDep::Order: dbgs() << "ord "; break;
374  }
375  I->getSUnit()->print(dbgs(), G);
376  if (I->isArtificial())
377  dbgs() << " *";
378  dbgs() << ": Latency=" << I->getLatency();
379  if (I->isAssignedRegDep())
380  dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
381  dbgs() << "\n";
382  }
383  }
384 }
385 #endif
386 
387 #ifndef NDEBUG
388 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
389 /// their state is consistent. Return the number of scheduled nodes.
390 ///
391 unsigned ScheduleDAG::VerifyScheduledDAG(bool isBottomUp) {
392  bool AnyNotSched = false;
393  unsigned DeadNodes = 0;
394  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
395  if (!SUnits[i].isScheduled) {
396  if (SUnits[i].NumPreds == 0 && SUnits[i].NumSuccs == 0) {
397  ++DeadNodes;
398  continue;
399  }
400  if (!AnyNotSched)
401  dbgs() << "*** Scheduling failed! ***\n";
402  SUnits[i].dump(this);
403  dbgs() << "has not been scheduled!\n";
404  AnyNotSched = true;
405  }
406  if (SUnits[i].isScheduled &&
407  (isBottomUp ? SUnits[i].getHeight() : SUnits[i].getDepth()) >
408  unsigned(INT_MAX)) {
409  if (!AnyNotSched)
410  dbgs() << "*** Scheduling failed! ***\n";
411  SUnits[i].dump(this);
412  dbgs() << "has an unexpected "
413  << (isBottomUp ? "Height" : "Depth") << " value!\n";
414  AnyNotSched = true;
415  }
416  if (isBottomUp) {
417  if (SUnits[i].NumSuccsLeft != 0) {
418  if (!AnyNotSched)
419  dbgs() << "*** Scheduling failed! ***\n";
420  SUnits[i].dump(this);
421  dbgs() << "has successors left!\n";
422  AnyNotSched = true;
423  }
424  } else {
425  if (SUnits[i].NumPredsLeft != 0) {
426  if (!AnyNotSched)
427  dbgs() << "*** Scheduling failed! ***\n";
428  SUnits[i].dump(this);
429  dbgs() << "has predecessors left!\n";
430  AnyNotSched = true;
431  }
432  }
433  }
434  assert(!AnyNotSched);
435  return SUnits.size() - DeadNodes;
436 }
437 #endif
438 
439 /// InitDAGTopologicalSorting - create the initial topological
440 /// ordering from the DAG to be scheduled.
441 ///
442 /// The idea of the algorithm is taken from
443 /// "Online algorithms for managing the topological order of
444 /// a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly
445 /// This is the MNR algorithm, which was first introduced by
446 /// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in
447 /// "Maintaining a topological order under edge insertions".
448 ///
449 /// Short description of the algorithm:
450 ///
451 /// Topological ordering, ord, of a DAG maps each node to a topological
452 /// index so that for all edges X->Y it is the case that ord(X) < ord(Y).
453 ///
454 /// This means that if there is a path from the node X to the node Z,
455 /// then ord(X) < ord(Z).
456 ///
457 /// This property can be used to check for reachability of nodes:
458 /// if Z is reachable from X, then an insertion of the edge Z->X would
459 /// create a cycle.
460 ///
461 /// The algorithm first computes a topological ordering for the DAG by
462 /// initializing the Index2Node and Node2Index arrays and then tries to keep
463 /// the ordering up-to-date after edge insertions by reordering the DAG.
464 ///
465 /// On insertion of the edge X->Y, the algorithm first marks by calling DFS
466 /// the nodes reachable from Y, and then shifts them using Shift to lie
467 /// immediately after X in Index2Node.
469  unsigned DAGSize = SUnits.size();
470  std::vector<SUnit*> WorkList;
471  WorkList.reserve(DAGSize);
472 
473  Index2Node.resize(DAGSize);
474  Node2Index.resize(DAGSize);
475 
476  // Initialize the data structures.
477  if (ExitSU)
478  WorkList.push_back(ExitSU);
479  for (unsigned i = 0, e = DAGSize; i != e; ++i) {
480  SUnit *SU = &SUnits[i];
481  int NodeNum = SU->NodeNum;
482  unsigned Degree = SU->Succs.size();
483  // Temporarily use the Node2Index array as scratch space for degree counts.
484  Node2Index[NodeNum] = Degree;
485 
486  // Is it a node without dependencies?
487  if (Degree == 0) {
488  assert(SU->Succs.empty() && "SUnit should have no successors");
489  // Collect leaf nodes.
490  WorkList.push_back(SU);
491  }
492  }
493 
494  int Id = DAGSize;
495  while (!WorkList.empty()) {
496  SUnit *SU = WorkList.back();
497  WorkList.pop_back();
498  if (SU->NodeNum < DAGSize)
499  Allocate(SU->NodeNum, --Id);
500  for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
501  I != E; ++I) {
502  SUnit *SU = I->getSUnit();
503  if (SU->NodeNum < DAGSize && !--Node2Index[SU->NodeNum])
504  // If all dependencies of the node are processed already,
505  // then the node can be computed now.
506  WorkList.push_back(SU);
507  }
508  }
509 
510  Visited.resize(DAGSize);
511 
512 #ifndef NDEBUG
513  // Check correctness of the ordering
514  for (unsigned i = 0, e = DAGSize; i != e; ++i) {
515  SUnit *SU = &SUnits[i];
516  for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
517  I != E; ++I) {
518  assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] &&
519  "Wrong topological sorting");
520  }
521  }
522 #endif
523 }
524 
525 /// AddPred - Updates the topological ordering to accommodate an edge
526 /// to be added from SUnit X to SUnit Y.
528  int UpperBound, LowerBound;
529  LowerBound = Node2Index[Y->NodeNum];
530  UpperBound = Node2Index[X->NodeNum];
531  bool HasLoop = false;
532  // Is Ord(X) < Ord(Y) ?
533  if (LowerBound < UpperBound) {
534  // Update the topological order.
535  Visited.reset();
536  DFS(Y, UpperBound, HasLoop);
537  assert(!HasLoop && "Inserted edge creates a loop!");
538  // Recompute topological indexes.
539  Shift(Visited, LowerBound, UpperBound);
540  }
541 }
542 
543 /// RemovePred - Updates the topological ordering to accommodate an
544 /// an edge to be removed from the specified node N from the predecessors
545 /// of the current node M.
547  // InitDAGTopologicalSorting();
548 }
549 
550 /// DFS - Make a DFS traversal to mark all nodes reachable from SU and mark
551 /// all nodes affected by the edge insertion. These nodes will later get new
552 /// topological indexes by means of the Shift method.
553 void ScheduleDAGTopologicalSort::DFS(const SUnit *SU, int UpperBound,
554  bool &HasLoop) {
555  std::vector<const SUnit*> WorkList;
556  WorkList.reserve(SUnits.size());
557 
558  WorkList.push_back(SU);
559  do {
560  SU = WorkList.back();
561  WorkList.pop_back();
562  Visited.set(SU->NodeNum);
563  for (int I = SU->Succs.size()-1; I >= 0; --I) {
564  unsigned s = SU->Succs[I].getSUnit()->NodeNum;
565  // Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
566  if (s >= Node2Index.size())
567  continue;
568  if (Node2Index[s] == UpperBound) {
569  HasLoop = true;
570  return;
571  }
572  // Visit successors if not already and in affected region.
573  if (!Visited.test(s) && Node2Index[s] < UpperBound) {
574  WorkList.push_back(SU->Succs[I].getSUnit());
575  }
576  }
577  } while (!WorkList.empty());
578 }
579 
580 /// Shift - Renumber the nodes so that the topological ordering is
581 /// preserved.
582 void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
583  int UpperBound) {
584  std::vector<int> L;
585  int shift = 0;
586  int i;
587 
588  for (i = LowerBound; i <= UpperBound; ++i) {
589  // w is node at topological index i.
590  int w = Index2Node[i];
591  if (Visited.test(w)) {
592  // Unmark.
593  Visited.reset(w);
594  L.push_back(w);
595  shift = shift + 1;
596  } else {
597  Allocate(w, i - shift);
598  }
599  }
600 
601  for (unsigned j = 0; j < L.size(); ++j) {
602  Allocate(L[j], i - shift);
603  i = i + 1;
604  }
605 }
606 
607 
608 /// WillCreateCycle - Returns true if adding an edge to TargetSU from SU will
609 /// create a cycle. If so, it is not safe to call AddPred(TargetSU, SU).
611  // Is SU reachable from TargetSU via successor edges?
612  if (IsReachable(SU, TargetSU))
613  return true;
615  I = TargetSU->Preds.begin(), E = TargetSU->Preds.end(); I != E; ++I)
616  if (I->isAssignedRegDep() &&
617  IsReachable(SU, I->getSUnit()))
618  return true;
619  return false;
620 }
621 
622 /// IsReachable - Checks if SU is reachable from TargetSU.
624  const SUnit *TargetSU) {
625  // If insertion of the edge SU->TargetSU would create a cycle
626  // then there is a path from TargetSU to SU.
627  int UpperBound, LowerBound;
628  LowerBound = Node2Index[TargetSU->NodeNum];
629  UpperBound = Node2Index[SU->NodeNum];
630  bool HasLoop = false;
631  // Is Ord(TargetSU) < Ord(SU) ?
632  if (LowerBound < UpperBound) {
633  Visited.reset();
634  // There may be a path from TargetSU to SU. Check for it.
635  DFS(TargetSU, UpperBound, HasLoop);
636  }
637  return HasLoop;
638 }
639 
640 /// Allocate - assign the topological index to the node n.
641 void ScheduleDAGTopologicalSort::Allocate(int n, int index) {
642  Node2Index[n] = index;
643  Index2Node[index] = n;
644 }
645 
647 ScheduleDAGTopologicalSort(std::vector<SUnit> &sunits, SUnit *exitsu)
648  : SUnits(sunits), ExitSU(exitsu) {}
649 
MachineLoop * L
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:193
BitVector & set()
Definition: BitVector.h:219
unsigned NumPreds
Definition: ScheduleDAG.h:268
size_t i
void print(raw_ostream &O, const ScheduleDAG *G) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void setSUnit(SUnit *SU)
Definition: ScheduleDAG.h:506
void removePred(const SDep &D)
removePred - This removes the specified edge as a pred of the current node if it exists.
void reserve(size_type N)
Definition: SmallVector.h:377
SmallVector< SDep, 4 > Preds
Definition: ScheduleDAG.h:258
A register anti-dependedence (aka WAR).
Definition: ScheduleDAG.h:50
void dumpAll(const ScheduleDAG *G) const
bool isScheduled
Definition: ScheduleDAG.h:286
unsigned getHeight() const
getHeight - Return the height of this node, which is the length of the maximum path down to any node ...
Definition: ScheduleDAG.h:425
unsigned NumSuccs
Definition: ScheduleDAG.h:269
unsigned NumSuccsLeft
Definition: ScheduleDAG.h:271
bool isWeak() const
isWeak - Test if this a weak dependence.
Definition: ScheduleDAG.h:193
const HexagonInstrInfo * TII
Kind getKind() const
getKind - Return an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:509
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:49
void InitDAGTopologicalSorting()
InitDAGTopologicalSorting - create the initial topological ordering from the DAG to be scheduled...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:51
static cl::opt< bool > StressSchedOpt("stress-sched", cl::Hidden, cl::init(false), cl::desc("Stress test instruction scheduling"))
unsigned WeakSuccsLeft
Definition: ScheduleDAG.h:273
unsigned NumPredsLeft
Definition: ScheduleDAG.h:270
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
void setDepthToAtLeast(unsigned NewDepth)
setDepthToAtLeast - If NewDepth is greater than this node's depth value, set it to be the new depth v...
SDep - Scheduling dependency.
Definition: ScheduleDAG.h:45
void setHeightToAtLeast(unsigned NewHeight)
setDepthToAtLeast - If NewDepth is greater than this node's depth value, set it to be the new height ...
#define P(N)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
void setDepthDirty()
setDepthDirty - Set a flag in this node to indicate that its stored Depth value will require recomput...
bool WillCreateCycle(SUnit *TargetSU, SUnit *SU)
WillCreateCycle - Return true if addPred(TargetSU, SU) creates a cycle.
unsigned const MachineRegisterInfo * MRI
void clearDAG()
clearDAG - clear the DAG state (between regions).
Definition: ScheduleDAG.cpp:50
unsigned short Latency
Definition: ScheduleDAG.h:275
BitVector & reset()
Definition: BitVector.h:260
unsigned getLatency() const
getLatency - Return the latency value for this edge, which roughly means the minimum number of cycles...
Definition: ScheduleDAG.h:139
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
void RemovePred(SUnit *M, SUnit *N)
RemovePred - Updates the topological ordering to accommodate an an edge to be removed from the specif...
Any other ordering dependency.
Definition: ScheduleDAG.h:52
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
unsigned WeakPredsLeft
Definition: ScheduleDAG.h:272
const unsigned MaxDepth
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:757
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool test(unsigned Idx) const
Definition: BitVector.h:323
const DataFlowGraph & G
Definition: RDFGraph.cpp:206
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:382
Represents one node in the SelectionDAG.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
bool IsReachable(const SUnit *SU, const SUnit *TargetSU)
IsReachable - Checks if SU is reachable from TargetSU.
void biasCriticalPath()
Order this node's predecessor edges such that the critical path edge occurs first.
ScheduleDAG(MachineFunction &mf)
Definition: ScheduleDAG.cpp:38
unsigned getDepth() const
getDepth - Return the depth of this node, which is the length of the maximum path up to any node whic...
Definition: ScheduleDAG.h:417
unsigned VerifyScheduledDAG(bool isBottomUp)
VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent...
const TargetRegisterInfo * TRI
Definition: ScheduleDAG.h:580
SUnit * getSUnit() const
Definition: ScheduleDAG.h:503
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
unsigned short NumRegDefsLeft
Definition: ScheduleDAG.h:274
const TargetInstrInfo * TII
Definition: ScheduleDAG.h:579
unsigned NodeNum
Definition: ScheduleDAG.h:266
void setHeightDirty()
setHeightDirty - Set a flag in this node to indicate that its stored Height value will require recomp...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual void dumpNode(const SUnit *SU) const =0
bool addPred(const SDep &D, bool Required=true)
addPred - This adds the specified edge as a pred of the current node if not already.
Definition: ScheduleDAG.cpp:65
SmallVector< SDep, 4 > Succs
Definition: ScheduleDAG.h:259
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
void AddPred(SUnit *Y, SUnit *X)
AddPred - Updates the topological ordering to accommodate an edge to be added from SUnit X to SUnit Y...
virtual ~ScheduleDAG()
Definition: ScheduleDAG.cpp:47
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
std::vector< SUnit > SUnits
Definition: ScheduleDAG.h:583
ScheduleDAGTopologicalSort(std::vector< SUnit > &SUnits, SUnit *ExitSU)
void dump(const ScheduleDAG *G) const
SUnit - Scheduling unit.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:244
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.