LLVM  4.0.0
PPCRegisterInfo.h
Go to the documentation of this file.
1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
17 
18 #include "PPC.h"
19 #include "llvm/ADT/DenseMap.h"
20 
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
23 
24 namespace llvm {
25 
26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27  unsigned Reg = 0;
28  if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29  SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30  Reg = PPC::CR0;
31  else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32  SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33  Reg = PPC::CR1;
34  else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35  SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36  Reg = PPC::CR2;
37  else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38  SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39  Reg = PPC::CR3;
40  else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41  SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42  Reg = PPC::CR4;
43  else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44  SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45  Reg = PPC::CR5;
46  else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47  SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48  Reg = PPC::CR6;
49  else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50  SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51  Reg = PPC::CR7;
52 
53  assert(Reg != 0 && "Invalid CR bit register");
54  return Reg;
55 }
56 
58  DenseMap<unsigned, unsigned> ImmToIdxMap;
59  const PPCTargetMachine &TM;
60 
61 public:
63 
64  /// getPointerRegClass - Return the register class to use to hold pointers.
65  /// This is used for addressing modes.
66  const TargetRegisterClass *
67  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
68 
69  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
70  MachineFunction &MF) const override;
71 
72  const TargetRegisterClass *
74  const MachineFunction &MF) const override;
75 
76  /// Code Generation virtual methods...
77  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
78  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
80  CallingConv::ID CC) const override;
81  const uint32_t *getNoPreservedMask() const override;
82 
83  void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
84 
85  BitVector getReservedRegs(const MachineFunction &MF) const override;
86 
87  /// We require the register scavenger.
88  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
89  return true;
90  }
91 
92  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
93  return true;
94  }
95 
96  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
97  return true;
98  }
99 
100  bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
101  return true;
102  }
103 
107  unsigned FrameIndex) const;
109  unsigned FrameIndex) const;
111  unsigned FrameIndex) const;
113  unsigned FrameIndex) const;
115  unsigned FrameIndex) const;
117  unsigned FrameIndex) const;
118 
119  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
120  int &FrameIdx) const override;
122  unsigned FIOperandNum,
123  RegScavenger *RS = nullptr) const override;
124 
125  // Support for virtual base registers.
126  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
128  unsigned BaseReg, int FrameIdx,
129  int64_t Offset) const override;
130  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
131  int64_t Offset) const override;
132  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
133  int64_t Offset) const override;
134 
135  // Debug information queries.
136  unsigned getFrameRegister(const MachineFunction &MF) const override;
137 
138  // Base pointer (stack realignment) support.
139  unsigned getBaseRegister(const MachineFunction &MF) const;
140  bool hasBasePointer(const MachineFunction &MF) const;
141 };
142 
143 } // end namespace llvm
144 
145 #endif
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getFrameRegister(const MachineFunction &MF) const override
MachineBasicBlock * MBB
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
unsigned getBaseRegister(const MachineFunction &MF) const
uint32_t Offset
Common code between 32-bit and 64-bit PowerPC targets.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
const uint32_t * getNoPreservedMask() const override
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Representation of each machine instruction.
Definition: MachineInstr.h:52
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
bool hasBasePointer(const MachineFunction &MF) const
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override