59 #define DEBUG_TYPE "hexagon-peephole"
63 cl::desc(
"Disable Peephole Optimization"));
67 cl::desc(
"Disable Optimization of PNotP"));
71 cl::desc(
"Disable Optimization of Sign/Zero Extends"));
75 cl::desc(
"Disable Optimization of extensions to i64."));
97 return "Hexagon optimize redundant zero and size extends";
115 if (skipFunction(*MF.getFunction()))
118 QII =
static_cast<const HexagonInstrInfo *
>(MF.getSubtarget().getInstrInfo());
120 MRI = &MF.getRegInfo();
129 MBBb != MBBe; ++MBBb) {
132 PeepholeDoubleRegsMap.
clear();
142 unsigned DstReg = Dst.getReg();
143 unsigned SrcReg = Src.
getReg();
150 PeepholeMap[DstReg] = SrcReg;
163 unsigned DstReg = Dst.getReg();
164 unsigned SrcReg = Src2.
getReg();
165 PeepholeMap[DstReg] = SrcReg;
173 if (
MI.getOpcode() == Hexagon::S2_lsr_i_p) {
180 unsigned DstReg = Dst.getReg();
181 unsigned SrcReg = Src1.
getReg();
182 PeepholeDoubleRegsMap[DstReg] =
183 std::make_pair(*&SrcReg, Hexagon::isub_hi);
191 unsigned DstReg = Dst.getReg();
192 unsigned SrcReg = Src.
getReg();
199 PeepholeMap[DstReg] = SrcReg;
214 unsigned DstReg = Dst.getReg();
215 unsigned SrcReg = Src.
getReg();
219 if (
unsigned PeepholeSrc = PeepholeMap.
lookup(SrcReg)) {
225 PeepholeDoubleRegsMap.
find(SrcReg);
226 if (DI != PeepholeDoubleRegsMap.
end()) {
227 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
230 PeepholeSrc.first,
false ,
false ,
231 false ,
false ,
false ,
232 false , PeepholeSrc.second));
241 if (QII->isPredicated(
MI)) {
243 unsigned Reg0 = Op0.
getReg();
245 if (RC0->
getID() == Hexagon::PredRegsRegClassID) {
250 if (
unsigned PeepholeSrc = PeepholeMap.
lookup(Reg0)) {
252 MI.getOperand(0).setReg(PeepholeSrc);
253 MRI->clearKillFlags(PeepholeSrc);
254 int NewOp = QII->getInvertedPredicatedOpcode(
MI.getOpcode());
255 MI.setDesc(QII->get(NewOp));
264 unsigned Op =
MI.getOpcode();
266 unsigned PR = 1, S1 = 2, S2 = 3;
269 case Hexagon::C2_mux:
270 case Hexagon::C2_muxii:
273 case Hexagon::C2_muxri:
274 NewOp = Hexagon::C2_muxir;
276 case Hexagon::C2_muxir:
277 NewOp = Hexagon::C2_muxri;
281 unsigned PSrc =
MI.getOperand(PR).getReg();
282 if (
unsigned POrig = PeepholeMap.
lookup(PSrc)) {
283 MI.getOperand(PR).setReg(POrig);
284 MRI->clearKillFlags(POrig);
285 MI.setDesc(QII->get(NewOp));
289 ChangeOpInto(
MI.getOperand(S1), Op2);
290 ChangeOpInto(
MI.getOperand(S2), Op1);
303 assert (&Dst != &Src &&
"Cannot duplicate into itself");
310 }
else if (Src.
isImm()) {
320 }
else if (Src.
isReg()) {
337 return new HexagonPeephole();
INITIALIZE_PASS(HexagonPeephole,"hexagon-peephole","Hexagon Peephole", false, false) bool HexagonPeephole
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
ValueT lookup(const KeyT &Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned getID() const
Return the register class ID number.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static cl::opt< bool > DisablePNotP("disable-hexagon-pnotp", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Optimization of PNotP"))
static cl::opt< bool > DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Disable Optimization of Sign/Zero Extends"))
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
initializer< Ty > init(const Ty &Val)
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Represent the analysis usage information of a pass.
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
unsigned getSubReg() const
void initializeHexagonPeepholePass(PassRegistry &)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
FunctionPass * createHexagonPeephole()
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static cl::opt< bool > DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Peephole Optimization"))
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setSubReg(unsigned subReg)
iterator find(const KeyT &Val)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< bool > DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Disable Optimization of extensions to i64."))
StringRef - Represent a constant reference to a string, i.e.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...