LLVM  4.0.0
Macros | Functions | Variables
HexagonSubtarget.cpp File Reference
#include "HexagonSubtarget.h"
#include "Hexagon.h"
#include "HexagonRegisterInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include <map>
#include "HexagonGenSubtargetInfo.inc"
Include dependency graph for HexagonSubtarget.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "hexagon-subtarget"
 
#define GET_SUBTARGETINFO_CTOR
 
#define GET_SUBTARGETINFO_TARGET_DESC
 

Functions

static SUnitgetZeroLatency (SUnit *N, SmallVector< SDep, 4 > &Deps)
 If the SUnit has a zero latency edge, return the other SUnit. More...
 

Variables

static cl::opt< boolEnableMemOps ("enable-hexagon-memops", cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true), cl::desc("Generate V4 MEMOP in code generation for Hexagon target"))
 
static cl::opt< boolDisableMemOps ("disable-hexagon-memops", cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false), cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"))
 
static cl::opt< boolEnableIEEERndNear ("enable-hexagon-ieee-rnd-near", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Generate non-chopped conversion from fp to int."))
 
static cl::opt< boolEnableBSBSched ("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
 
static cl::opt< boolEnableHexagonHVXDouble ("enable-hexagon-hvx-double", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Double Vector eXtensions"))
 
static cl::opt< boolEnableHexagonHVX ("enable-hexagon-hvx", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector eXtensions"))
 
static cl::opt< boolEnableTCLatencySched ("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false))
 
static cl::opt< boolEnableDotCurSched ("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
 
static cl::opt< boolEnableVecFrwdSched ("enable-evec-frwd-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
 
static cl::opt< boolDisableHexagonMISched ("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling"))
 
static cl::opt< boolEnableSubregLiveness ("hexagon-subreg-liveness", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
 
static cl::opt< boolOverrideLongCalls ("hexagon-long-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("If present, forces/disables the use of long calls"))
 

Macro Definition Documentation

#define DEBUG_TYPE   "hexagon-subtarget"

Definition at line 25 of file HexagonSubtarget.cpp.

#define GET_SUBTARGETINFO_CTOR

Definition at line 27 of file HexagonSubtarget.cpp.

#define GET_SUBTARGETINFO_TARGET_DESC

Definition at line 28 of file HexagonSubtarget.cpp.

Function Documentation

static SUnit* getZeroLatency ( SUnit N,
SmallVector< SDep, 4 > &  Deps 
)
static

If the SUnit has a zero latency edge, return the other SUnit.

Definition at line 235 of file HexagonSubtarget.cpp.

References I.

Variable Documentation

cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling"))
static
cl::opt<bool> DisableMemOps("disable-hexagon-memops", cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false), cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target"))
static
cl::opt<bool> EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
static
cl::opt<bool> EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
static
cl::opt<bool> EnableHexagonHVX("enable-hexagon-hvx", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector eXtensions"))
static
cl::opt<bool> EnableHexagonHVXDouble("enable-hexagon-hvx-double", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Double Vector eXtensions"))
static
cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Generate non-chopped conversion from fp to int."))
static
cl::opt<bool> EnableMemOps("enable-hexagon-memops", cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true), cl::desc("Generate V4 MEMOP in code generation for Hexagon target"))
static
cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
static
cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false))
static
cl::opt<bool> EnableVecFrwdSched("enable-evec-frwd-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
static
cl::opt<bool> OverrideLongCalls("hexagon-long-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("If present, forces/disables the use of long calls"))
static