29 :
MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::
B : Mips::J),
45 if ((Opc == Mips::LW) || (Opc ==
Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
81 const DebugLoc &DL,
unsigned DestReg,
82 unsigned SrcReg,
bool KillSrc)
const {
83 unsigned Opc = 0, ZeroReg = 0;
86 if (Mips::GPR32RegClass.
contains(DestReg)) {
87 if (Mips::GPR32RegClass.
contains(SrcReg)) {
89 Opc = Mips::MOVE16_MM;
91 Opc =
Mips::OR, ZeroReg = Mips::ZERO;
92 }
else if (Mips::CCRRegClass.
contains(SrcReg))
94 else if (Mips::FGR32RegClass.
contains(SrcReg))
96 else if (Mips::HI32RegClass.
contains(SrcReg)) {
97 Opc = isMicroMips ? Mips::MFHI16_MM :
Mips::MFHI;
99 }
else if (Mips::LO32RegClass.
contains(SrcReg)) {
100 Opc = isMicroMips ? Mips::MFLO16_MM :
Mips::MFLO;
102 }
else if (Mips::HI32DSPRegClass.
contains(SrcReg))
103 Opc = Mips::MFHI_DSP;
104 else if (Mips::LO32DSPRegClass.
contains(SrcReg))
105 Opc = Mips::MFLO_DSP;
106 else if (Mips::DSPCCRegClass.
contains(SrcReg)) {
107 BuildMI(MBB, I, DL,
get(Mips::RDDSP), DestReg).
addImm(1 << 4)
111 else if (Mips::MSACtrlRegClass.
contains(SrcReg))
114 else if (Mips::GPR32RegClass.
contains(SrcReg)) {
115 if (Mips::CCRRegClass.
contains(DestReg))
117 else if (Mips::FGR32RegClass.
contains(DestReg))
119 else if (Mips::HI32RegClass.
contains(DestReg))
120 Opc = Mips::MTHI, DestReg = 0;
121 else if (Mips::LO32RegClass.
contains(DestReg))
122 Opc = Mips::MTLO, DestReg = 0;
123 else if (Mips::HI32DSPRegClass.
contains(DestReg))
124 Opc = Mips::MTHI_DSP;
125 else if (Mips::LO32DSPRegClass.
contains(DestReg))
126 Opc = Mips::MTLO_DSP;
127 else if (Mips::DSPCCRegClass.
contains(DestReg)) {
128 BuildMI(MBB, I, DL,
get(Mips::WRDSP))
132 }
else if (Mips::MSACtrlRegClass.
contains(DestReg)) {
133 BuildMI(MBB, I, DL,
get(Mips::CTCMSA))
139 else if (Mips::FGR32RegClass.
contains(DestReg, SrcReg))
141 else if (Mips::AFGR64RegClass.
contains(DestReg, SrcReg))
142 Opc = Mips::FMOV_D32;
143 else if (Mips::FGR64RegClass.
contains(DestReg, SrcReg))
144 Opc = Mips::FMOV_D64;
145 else if (Mips::GPR64RegClass.
contains(DestReg)) {
146 if (Mips::GPR64RegClass.
contains(SrcReg))
147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
148 else if (Mips::HI64RegClass.
contains(SrcReg))
149 Opc = Mips::MFHI64, SrcReg = 0;
150 else if (Mips::LO64RegClass.
contains(SrcReg))
151 Opc = Mips::MFLO64, SrcReg = 0;
152 else if (Mips::FGR64RegClass.
contains(SrcReg))
155 else if (Mips::GPR64RegClass.
contains(SrcReg)) {
156 if (Mips::HI64RegClass.
contains(DestReg))
157 Opc = Mips::MTHI64, DestReg = 0;
158 else if (Mips::LO64RegClass.
contains(DestReg))
159 Opc = Mips::MTLO64, DestReg = 0;
160 else if (Mips::FGR64RegClass.
contains(DestReg))
163 else if (Mips::MSA128BRegClass.
contains(DestReg)) {
164 if (Mips::MSA128BRegClass.
contains(SrcReg))
168 assert(Opc &&
"Cannot copy registers");
184 unsigned SrcReg,
bool isKill,
int FI,
192 if (Mips::GPR32RegClass.hasSubClassEq(RC))
194 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
196 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
197 Opc = Mips::STORE_ACC64;
198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
199 Opc = Mips::STORE_ACC64DSP;
200 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
201 Opc = Mips::STORE_ACC128;
202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
203 Opc = Mips::STORE_CCOND_DSP;
204 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
208 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
218 else if (Mips::LO32RegClass.hasSubClassEq(RC))
220 else if (Mips::LO64RegClass.hasSubClassEq(RC))
222 else if (Mips::HI32RegClass.hasSubClassEq(RC))
224 else if (Mips::HI64RegClass.hasSubClassEq(RC))
231 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
234 }
else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
235 BuildMI(MBB, I, DL,
get(Mips::MFHI64), Mips::K0_64);
236 SrcReg = Mips::K0_64;
237 }
else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
240 }
else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
241 BuildMI(MBB, I, DL,
get(Mips::MFLO64), Mips::K0_64);
242 SrcReg = Mips::K0_64;
246 assert(Opc &&
"Register class not handled!");
256 if (I != MBB.
end()) DL = I->getDebugLoc();
262 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
263 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
265 if (Mips::GPR32RegClass.hasSubClassEq(RC))
267 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
269 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
270 Opc = Mips::LOAD_ACC64;
271 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
272 Opc = Mips::LOAD_ACC64DSP;
273 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
274 Opc = Mips::LOAD_ACC128;
275 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
276 Opc = Mips::LOAD_CCOND_DSP;
277 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
279 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
281 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
291 else if (Mips::HI32RegClass.hasSubClassEq(RC))
293 else if (Mips::HI64RegClass.hasSubClassEq(RC))
295 else if (Mips::LO32RegClass.hasSubClassEq(RC))
297 else if (Mips::LO64RegClass.hasSubClassEq(RC))
300 assert(Opc &&
"Register class not handled!");
302 if (!ReqIndirectLoad)
303 BuildMI(MBB, I, DL,
get(Opc), DestReg)
310 unsigned Reg = Mips::K0;
311 unsigned LdOp = Mips::MTLO;
312 if (DestReg == Mips::HI0)
317 if (DestReg == Mips::HI0_64)
323 BuildMI(MBB, I, DL,
get(Opc), Reg)
340 expandRetRA(MBB, MI);
345 case Mips::PseudoMFHI:
346 Opc = isMicroMips ? Mips::MFHI16_MM :
Mips::MFHI;
347 expandPseudoMFHiLo(MBB, MI, Opc);
349 case Mips::PseudoMFLO:
350 Opc = isMicroMips ? Mips::MFLO16_MM :
Mips::MFLO;
351 expandPseudoMFHiLo(MBB, MI, Opc);
353 case Mips::PseudoMFHI64:
354 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
356 case Mips::PseudoMFLO64:
357 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
359 case Mips::PseudoMTLOHI:
360 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI,
false);
362 case Mips::PseudoMTLOHI64:
363 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64,
false);
365 case Mips::PseudoMTLOHI_DSP:
366 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP,
true);
368 case Mips::PseudoCVT_S_W:
369 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1,
false);
371 case Mips::PseudoCVT_D32_W:
372 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1,
false);
374 case Mips::PseudoCVT_S_L:
375 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1,
true);
377 case Mips::PseudoCVT_D64_W:
378 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1,
true);
380 case Mips::PseudoCVT_D64_L:
381 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1,
true);
384 expandBuildPairF64(MBB, MI,
false);
386 case Mips::BuildPairF64_64:
387 expandBuildPairF64(MBB, MI,
true);
390 expandExtractElementF64(MBB, MI,
false);
392 case Mips::ExtractElementF64_64:
393 expandExtractElementF64(MBB, MI,
true);
395 case Mips::MIPSeh_return32:
396 case Mips::MIPSeh_return64:
397 expandEhReturn(MBB, MI);
410 case Mips::BEQ:
return Mips::BNE;
411 case Mips::BEQ_MM:
return Mips::BNE_MM;
412 case Mips::BNE:
return Mips::BEQ;
413 case Mips::BNE_MM:
return Mips::BEQ_MM;
414 case Mips::BGTZ:
return Mips::BLEZ;
415 case Mips::BGEZ:
return Mips::BLTZ;
416 case Mips::BLTZ:
return Mips::BGEZ;
417 case Mips::BLEZ:
return Mips::BGTZ;
418 case Mips::BEQ64:
return Mips::BNE64;
419 case Mips::BNE64:
return Mips::BEQ64;
420 case Mips::BGTZ64:
return Mips::BLEZ64;
421 case Mips::BGEZ64:
return Mips::BLTZ64;
422 case Mips::BLTZ64:
return Mips::BGEZ64;
423 case Mips::BLEZ64:
return Mips::BGTZ64;
424 case Mips::BC1T:
return Mips::BC1F;
425 case Mips::BC1F:
return Mips::BC1T;
426 case Mips::BEQZC_MM:
return Mips::BNEZC_MM;
427 case Mips::BNEZC_MM:
return Mips::BEQZC_MM;
428 case Mips::BEQZC:
return Mips::BNEZC;
429 case Mips::BNEZC:
return Mips::BEQZC;
430 case Mips::BEQC:
return Mips::BNEC;
431 case Mips::BNEC:
return Mips::BEQC;
432 case Mips::BGTZC:
return Mips::BLEZC;
433 case Mips::BGEZC:
return Mips::BLTZC;
434 case Mips::BLTZC:
return Mips::BGEZC;
435 case Mips::BLEZC:
return Mips::BGTZC;
436 case Mips::BEQZC64:
return Mips::BNEZC64;
437 case Mips::BNEZC64:
return Mips::BEQZC64;
438 case Mips::BEQC64:
return Mips::BNEC64;
439 case Mips::BNEC64:
return Mips::BEQC64;
440 case Mips::BGEC64:
return Mips::BLTC64;
441 case Mips::BGEUC64:
return Mips::BLTUC64;
442 case Mips::BLTC64:
return Mips::BGEC64;
443 case Mips::BLTUC64:
return Mips::BGEUC64;
444 case Mips::BGTZC64:
return Mips::BLEZC64;
445 case Mips::BGEZC64:
return Mips::BLTZC64;
446 case Mips::BLTZC64:
return Mips::BGEZC64;
447 case Mips::BLEZC64:
return Mips::BGTZC64;
483 unsigned *NewImm)
const {
487 unsigned Size = STI.
isABI_N64() ? 64 : 32;
488 unsigned LUi = STI.
isABI_N64() ? Mips::LUi64 : Mips::LUi;
489 unsigned ZEROReg = STI.
isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
491 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
492 bool LastInstrIsADDiu = NewImm;
495 AnalyzeImm.
Analyze(Imm, Size, LastInstrIsADDiu);
505 if (Inst->Opc == LUi)
506 BuildMI(MBB, II, DL,
get(LUi), Reg).
addImm(SignExtend64<16>(Inst->ImmOpnd));
509 .
addImm(SignExtend64<16>(Inst->ImmOpnd));
512 for (++Inst; Inst != Seq.
end() - LastInstrIsADDiu; ++Inst)
514 .
addImm(SignExtend64<16>(Inst->ImmOpnd));
516 if (LastInstrIsADDiu)
517 *NewImm = Inst->ImmOpnd;
522 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(
unsigned Opc)
const {
523 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
524 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
525 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
526 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
527 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
528 Opc == Mips::BC1F || Opc ==
Mips::B || Opc == Mips::J ||
529 Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
530 Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
531 Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
532 Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
533 Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 ||
534 Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
535 Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
536 Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
537 Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
538 Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
544 BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::PseudoReturn64))
547 BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::PseudoReturn)).
addReg(Mips::RA);
552 BuildMI(MBB, I, I->getDebugLoc(),
get(Mips::ERET));
555 std::pair<bool, bool>
556 MipsSEInstrInfo::compareOpndSize(
unsigned Opc,
561 unsigned DstRegSize =
getRegClass(Desc, 0, RI, MF)->getSize();
562 unsigned SrcRegSize =
getRegClass(Desc, 1, RI, MF)->getSize();
564 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
569 unsigned NewOpc)
const {
570 BuildMI(MBB, I, I->getDebugLoc(),
get(NewOpc), I->getOperand(0).getReg());
577 bool HasExplicitDef)
const {
585 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
591 if (HasExplicitDef) {
592 unsigned DstReg = I->getOperand(0).getReg();
605 unsigned CvtOpc,
unsigned MovOpc,
607 const MCInstrDesc &CvtDesc =
get(CvtOpc), &MovDesc =
get(MovOpc);
608 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
609 unsigned DstReg = Dst.
getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
612 bool DstIsLarger, SrcIsLarger;
614 std::tie(DstIsLarger, SrcIsLarger) =
615 compareOpndSize(CvtOpc, *MBB.
getParent());
623 BuildMI(MBB, I, DL, MovDesc, TmpReg).
addReg(SrcReg, KillSrc);
630 unsigned DstReg = I->getOperand(0).getReg();
631 unsigned SrcReg = I->getOperand(1).getReg();
632 unsigned N = I->getOperand(2).getImm();
635 assert(N < 2 &&
"Invalid immediate");
636 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
660 BuildMI(MBB, I, dl,
get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
669 unsigned DstReg = I->getOperand(0).getReg();
670 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
713 BuildMI(MBB, I, dl,
get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
734 unsigned OffsetReg = I->getOperand(0).getReg();
735 unsigned TargetReg = I->getOperand(1).getReg();
742 BuildMI(MBB, I, I->getDebugLoc(),
get(ADDU), T9)
745 BuildMI(MBB, I, I->getDebugLoc(),
get(ADDU), RA)
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
bool isZeroImm(const MachineOperand &op) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool ArePtrs64bit() const
const MipsABIInfo & getABI() const
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
constexpr bool isInt< 16 >(int64_t x)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
MipsSEInstrInfo(const MipsSubtarget &STI)
return AArch64::GPR64RegClass contains(Reg)
A description of a memory reference used in the backend.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Reg
All possible values of the reg field in the ModR/M byte.
const MipsSubtarget & Subtarget
static int getRegClass(RegisterKind Is, unsigned RegWidth)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned short NumOperands
const MachineBasicBlock * getParent() const
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static ManagedStatic< OptionRegistry > OR
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
bool isPositionIndependent() const
bool inMicroMipsMode() const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getOpcode() const
Return the opcode number for this descriptor.
The memory access writes data.
unsigned GetPtrSubuOp() const
MachineOperand class - Representation of each machine instruction operand.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool expandPostRAPseudo(MachineInstr &MI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
Representation of each machine instruction.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
unsigned GetPtrAdduOp() const
Primary interface to the complete machine description for the target machine.
unsigned GetPtrAddiuOp() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.