51 "print-whole-regmask",
52 cl::desc(
"Print the full contents of regmask operands in IR dumps"),
60 if (
getReg() == Reg)
return;
70 SmallContents.RegNo =
Reg;
76 SmallContents.RegNo =
Reg;
104 assert(
isReg() &&
"Wrong MachineOperand accessor");
105 assert((!Val || !
isDebug()) &&
"Marking a debug operation as def");
123 void MachineOperand::removeRegFromUses() {
124 if (!
isReg() || !isOnRegUseList())
130 MF->getRegInfo().removeRegOperandFromUseList(
this);
153 Contents.CFP = FPImm;
158 "Cannot change a tied operand into an external symbol");
163 Contents.OffsetedInfo.Val.SymbolName = SymName;
170 "Cannot change a tied operand into an MCSymbol");
180 "Cannot change a tied operand into a FrameIndex");
192 bool isKill,
bool isDead,
bool isUndef,
198 RegInfo = &MF->getRegInfo();
201 bool WasReg =
isReg();
202 if (RegInfo && WasReg)
207 SmallContents.RegNo =
Reg;
208 SubReg_TargetFlags = 0;
214 IsInternalRead =
false;
215 IsEarlyClobber =
false;
218 Contents.Reg.Prev =
nullptr;
332 print(OS, DummyMST, TRI, IntrinsicInfo);
345 bool NeedComma =
false;
347 if (NeedComma) OS <<
',';
349 OS <<
"earlyclobber,";
364 if (NeedComma) OS <<
',';
369 if (NeedComma) OS <<
',';
374 if (NeedComma) OS <<
',';
379 if (NeedComma) OS <<
',';
384 if (NeedComma) OS <<
',';
392 case MachineOperand::MO_Immediate:
395 case MachineOperand::MO_CImmediate:
396 getCImm()->getValue().print(OS, false);
398 case MachineOperand::MO_FPImmediate:
399 if (getFPImm()->getType()->isFloatTy()) {
400 OS << getFPImm()->getValueAPF().convertToFloat();
401 } else if (getFPImm()->getType()->isHalfTy()) {
402 APFloat APF = getFPImm()->getValueAPF();
404 APF.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &Unused);
405 OS << "half " << APF.convertToFloat();
407 OS << getFPImm()->getValueAPF().convertToDouble();
410 case MachineOperand::MO_MachineBasicBlock:
411 OS << "<BB#" << getMBB()->getNumber() << ">";
413 case MachineOperand::MO_FrameIndex:
414 OS << "<fi#" << getIndex() << '>
';
416 case MachineOperand::MO_ConstantPoolIndex:
417 OS << "<cp#" << getIndex();
418 if (getOffset()) OS << "+" << getOffset();
421 case MachineOperand::MO_TargetIndex:
422 OS << "<ti#" << getIndex();
423 if (getOffset()) OS << "+" << getOffset();
426 case MachineOperand::MO_JumpTableIndex:
427 OS << "<jt#" << getIndex() << '>
';
429 case MachineOperand::MO_GlobalAddress:
431 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
432 if (getOffset()) OS << "+" << getOffset();
435 case MachineOperand::MO_ExternalSymbol:
436 OS << "<es:" << getSymbolName();
437 if (getOffset()) OS << "+" << getOffset();
440 case MachineOperand::MO_BlockAddress:
442 getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
443 if (getOffset()) OS << "+" << getOffset();
446 case MachineOperand::MO_RegisterMask: {
447 unsigned NumRegsInMask = 0;
448 unsigned NumRegsEmitted = 0;
450 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
451 unsigned MaskWord = i / 32;
452 unsigned MaskBit = i % 32;
453 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
454 if (PrintWholeRegMask || NumRegsEmitted <= 10) {
455 OS << " " << PrintReg(i, TRI);
461 if (NumRegsEmitted != NumRegsInMask)
462 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
466 case MachineOperand::MO_RegisterLiveOut:
467 OS << "<regliveout>";
469 case MachineOperand::MO_Metadata:
471 getMetadata()->printAsOperand(OS, MST);
474 case MachineOperand::MO_MCSymbol:
475 OS << "<MCSym=" << *getMCSymbol() << '>
';
477 case MachineOperand::MO_CFIIndex:
478 OS << "<call frame instruction>";
480 case MachineOperand::MO_IntrinsicID: {
481 Intrinsic::ID ID = getIntrinsicID();
482 if (ID < Intrinsic::num_intrinsics)
483 OS << "<intrinsic:@" << Intrinsic::getName(ID, None) << '>
';
484 else if (IntrinsicInfo)
485 OS << "<intrinsic:@" << IntrinsicInfo->getName(ID) << '>
';
487 OS << "<intrinsic:" << ID << '>
';
490 case MachineOperand::MO_Predicate: {
491 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
492 OS << '<
' << (CmpInst::isIntPredicate(Pred) ? "intpred" : "floatpred")
493 << CmpInst::getPredicateName(Pred) << '>
';
496 if (unsigned TF = getTargetFlags())
497 OS << "[TF=" << TF << ']
';
500 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
501 LLVM_DUMP_METHOD void MachineOperand::dump() const {
502 dbgs() << *this << '\n
';
506 //===----------------------------------------------------------------------===//
507 // MachineMemOperand Implementation
508 //===----------------------------------------------------------------------===//
512 unsigned MachinePointerInfo::getAddrSpace() const {
513 if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
514 return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
519 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
520 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
525 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
526 int FI, int64_t Offset) {
527 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
530 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
531 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
534 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
535 return MachinePointerInfo(MF.getPSVManager().getGOT());
538 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
540 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset);
543 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
544 uint64_t s, unsigned int a,
545 const AAMDNodes &AAInfo,
546 const MDNode *Ranges,
547 SynchronizationScope SynchScope,
548 AtomicOrdering Ordering,
549 AtomicOrdering FailureOrdering)
550 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
551 AAInfo(AAInfo), Ranges(Ranges) {
552 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
553 isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
554 "invalid pointer value");
555 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
556 assert((isLoad() || isStore()) && "Not a load/store!");
558 AtomicInfo.SynchScope = static_cast<unsigned>(SynchScope);
559 assert(getSynchScope() == SynchScope && "Value truncated");
560 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
561 assert(getOrdering() == Ordering && "Value truncated");
562 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
563 assert(getFailureOrdering() == FailureOrdering && "Value truncated");
568 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
569 ID.AddInteger(getOffset());
571 ID.AddPointer(getOpaqueValue());
572 ID.AddInteger(getFlags());
573 ID.AddInteger(getBaseAlignment());
576 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
577 // The Value and Offset may differ due to CSE. But the flags and size
578 // should be the same.
579 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
580 assert(MMO->getSize() == getSize() && "Size mismatch!");
582 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
583 // Update the alignment value.
584 BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
585 // Also update the base and offset, because the new alignment may
586 // not be applicable with the old ones.
587 PtrInfo = MMO->PtrInfo;
593 uint64_t MachineMemOperand::getAlignment() const {
594 return MinAlign(getBaseAlignment(), getOffset());
597 void MachineMemOperand::print(raw_ostream &OS) const {
598 ModuleSlotTracker DummyMST(nullptr);
601 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
602 assert((isLoad() || isStore()) &&
603 "SV has to be a load, store or both.");
614 // Print the address information.
616 if (const Value *V = getValue())
617 V->printAsOperand(OS, /*PrintType=*/false, MST);
618 else if (const PseudoSourceValue *PSV = getPseudoValue())
619 PSV->printCustom(OS);
623 unsigned AS = getAddrSpace();
625 OS << "(addrspace=" << AS << ')
';
627 // If the alignment of the memory reference itself differs from the alignment
628 // of the base pointer, print the base alignment explicitly, next to the base
630 if (getBaseAlignment() != getAlignment())
631 OS << "(align=" << getBaseAlignment() << ")";
633 if (getOffset() != 0)
634 OS << "+" << getOffset();
637 // Print the alignment of the reference.
638 if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
639 OS << "(align=" << getAlignment() << ")";
642 if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
644 if (TBAAInfo->getNumOperands() > 0)
645 TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
651 // Print AA scope info.
652 if (const MDNode *ScopeInfo = getAAInfo().Scope) {
653 OS << "(alias.scope=";
654 if (ScopeInfo->getNumOperands() > 0)
655 for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
656 ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
665 // Print AA noalias scope info.
666 if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
668 if (NoAliasInfo->getNumOperands() > 0)
669 for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
670 NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
680 OS << "(nontemporal)";
681 if (isDereferenceable())
682 OS << "(dereferenceable)";
687 //===----------------------------------------------------------------------===//
688 // MachineInstr Implementation
689 //===----------------------------------------------------------------------===//
691 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
692 if (MCID->ImplicitDefs)
693 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
695 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
696 if (MCID->ImplicitUses)
697 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
699 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
705 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
706 DebugLoc dl, bool NoImp)
707 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
708 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
709 debugLoc(std::move(dl)) {
710 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
712 // Reserve space for the expected number of operands.
713 if (unsigned NumOps = MCID->getNumOperands() +
714 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
715 CapOperands = OperandCapacity::get(NumOps);
716 Operands = MF.allocateOperandArray(CapOperands);
720 addImplicitDefUseOperands(MF);
725 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
726 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
727 Flags(0), AsmPrinterFlags(0), NumMemRefs(MI.NumMemRefs),
728 MemRefs(MI.MemRefs), debugLoc(MI.getDebugLoc()) {
729 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
731 CapOperands = OperandCapacity::get(MI.getNumOperands());
732 Operands = MF.allocateOperandArray(CapOperands);
735 for (const MachineOperand &MO : MI.operands())
738 // Copy all the sensible flags.
745 MachineRegisterInfo *MachineInstr::getRegInfo() {
746 if (MachineBasicBlock *MBB = getParent())
747 return &MBB->getParent()->getRegInfo();
754 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
755 for (MachineOperand &MO : operands())
757 MRI.removeRegOperandFromUseList(&MO);
763 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
764 for (MachineOperand &MO : operands())
766 MRI.addRegOperandToUseList(&MO);
769 void MachineInstr::addOperand(const MachineOperand &Op) {
770 MachineBasicBlock *MBB = getParent();
771 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
772 MachineFunction *MF = MBB->getParent();
773 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
779 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
780 unsigned NumOps, MachineRegisterInfo *MRI) {
782 return MRI->moveOperands(Dst, Src, NumOps);
784 // MachineOperand is a trivially copyable type so we can just use memmove.
785 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
792 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
793 assert(MCID && "Cannot add operands before providing an instr descriptor");
795 // Check if we're adding one of our existing operands.
796 if (&
Op >= Operands && &
Op < Operands + NumOperands) {
811 unsigned OpNo = getNumOperands();
812 bool isImpReg =
Op.isReg() &&
Op.isImplicit();
813 if (!isImpReg && !isInlineAsm()) {
814 while (OpNo && Operands[OpNo-1].
isReg() && Operands[OpNo-1].
isImplicit()) {
816 assert(!Operands[OpNo].
isTied() &&
"Cannot move tied operands");
825 assert((isImpReg ||
Op.isRegMask() || MCID->isVariadic() ||
826 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
827 "Trying to add an operand to a machine instr that is already done!");
834 OperandCapacity OldCap = CapOperands;
836 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
837 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
838 Operands = MF.allocateOperandArray(CapOperands);
845 if (OpNo != NumOperands)
846 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
851 if (OldOperands != Operands && OldOperands)
852 MF.deallocateOperandArray(OldCap, OldOperands);
856 NewMO->ParentMI =
this;
859 if (NewMO->
isReg()) {
861 NewMO->Contents.
Reg.Prev =
nullptr;
872 if (NewMO->
isUse()) {
873 int DefIdx = MCID->getOperandConstraint(OpNo,
MCOI::TIED_TO);
875 tieOperands(DefIdx, OpNo);
888 assert(OpNo < getNumOperands() &&
"Invalid operand number");
889 untieRegOperand(OpNo);
893 for (
unsigned i = OpNo + 1, e = getNumOperands();
i != e; ++
i)
895 assert(!Operands[
i].
isTied() &&
"Cannot move tied operands");
899 if (MRI && Operands[OpNo].
isReg())
906 if (
unsigned N = NumOperands - 1 - OpNo)
917 unsigned OldNumMemRefs = NumMemRefs;
919 unsigned NewNum = NumMemRefs + 1;
922 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
923 NewMemRefs[NewNum - 1] = MO;
924 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
932 if ((E1 - I1) != (E2 - I2))
934 for (; I1 != E1; ++I1, ++I2) {
941 std::pair<MachineInstr::mmo_iterator, unsigned>
947 return std::make_pair(
nullptr, 0);
954 return std::make_pair(MemRefs, NumMemRefs);
958 size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
963 if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
964 return std::make_pair(
nullptr, 0);
968 mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
972 assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&
975 return std::make_pair(MemBegin, CombinedNumMemRefs);
978 bool MachineInstr::hasPropertyInBundle(
unsigned Mask, QueryType
Type)
const {
979 assert(!isBundledWithPred() &&
"Must be called on bundle header");
981 if (MII->getDesc().getFlags() &
Mask) {
982 if (Type == AnyInBundle)
985 if (Type == AllInBundle && !MII->isBundle())
989 if (!MII->isBundledWithSucc())
990 return Type == AllInBundle;
1006 assert(Other.
isBundle() &&
"Expected that both instructions are bundles.");
1011 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
1014 if (!I1->isIdenticalTo(*I2, Check))
1019 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
1024 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i) {
1037 if (Check == IgnoreDefs)
1039 else if (Check == IgnoreVRegDefs) {
1047 if (Check == CheckKillDead && MO.
isDead() != OMO.
isDead())
1053 if (Check == CheckKillDead && MO.
isKill() != OMO.
isKill())
1084 assert(MF &&
"Not embedded in a function!");
1090 if (!MO.isReg() || !MO.isDef())
1092 unsigned Reg = MO.getReg();
1108 unsigned NumOperands = MCID->getNumOperands();
1109 if (!MCID->isVariadic())
1112 for (
unsigned i = NumOperands, e = getNumOperands();
i != e; ++
i) {
1121 assert(!isBundledWithPred() &&
"MI is already bundled with its predecessor");
1122 setFlag(BundledPred);
1125 assert(!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
1126 Pred->setFlag(BundledSucc);
1130 assert(!isBundledWithSucc() &&
"MI is already bundled with its successor");
1131 setFlag(BundledSucc);
1134 assert(!Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
1135 Succ->setFlag(BundledPred);
1139 assert(isBundledWithPred() &&
"MI isn't bundled with its predecessor");
1140 clearFlag(BundledPred);
1143 assert(Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
1144 Pred->clearFlag(BundledSucc);
1148 assert(isBundledWithSucc() &&
"MI isn't bundled with its successor");
1149 clearFlag(BundledSucc);
1152 assert(Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
1153 Succ->clearFlag(BundledPred);
1157 if (isInlineAsm()) {
1166 assert(isInlineAsm() &&
"getInlineAsmDialect() only works for inline asms!");
1172 unsigned *GroupNo)
const {
1173 assert(isInlineAsm() &&
"Expected an inline asm instruction");
1174 assert(OpIdx < getNumOperands() &&
"OpIdx out of range");
1186 if (!FlagMO.
isImm())
1189 if (
i + NumOps > OpIdx) {
1200 assert(isDebugValue() &&
"not a DBG_VALUE");
1201 return cast<DILocalVariable>(getOperand(2).getMetadata());
1205 assert(isDebugValue() &&
"not a DBG_VALUE");
1206 return cast<DIExpression>(getOperand(3).getMetadata());
1221 if (!getOperand(OpIdx).
isReg())
1226 if (getOperand(OpIdx).
isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1230 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1234 unsigned Flag = getOperand(FlagIdx).getImm();
1257 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1258 OpndIt.getOperandNo(),
Reg, CurRC,
TII, TRI);
1261 for (
unsigned i = 0, e = NumOperands;
i < e && CurRC; ++
i)
1262 CurRC = getRegClassConstraintEffectForVRegImpl(
i, Reg, CurRC, TII, TRI);
1269 assert(CurRC &&
"Invalid initial register class");
1275 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1284 "Cannot get register constraints for non-register operand");
1285 assert(CurRC &&
"Invalid initial register class");
1301 while (I->isBundledWithSucc()) {
1311 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i) {
1324 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i) {
1328 unsigned MOReg = MO.
getReg();
1334 if (!isKill || MO.
isKill())
1343 std::pair<bool,bool>
1346 bool PartDef =
false;
1347 bool FullDef =
false;
1350 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i) {
1365 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1376 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i) {
1384 unsigned MOReg = MO.
getReg();
1385 bool Found = (MOReg ==
Reg);
1386 if (!Found && TRI && isPhys &&
1393 if (Found && (!isDead || MO.
isDead()))
1409 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i)
1435 assert(DefMO.
isDef() &&
"DefIdx must be a def operand");
1436 assert(UseMO.
isUse() &&
"UseIdx must be a use operand");
1437 assert(!DefMO.
isTied() &&
"Def is already tied to another use");
1438 assert(!UseMO.
isTied() &&
"Use is already tied to another def");
1440 if (DefIdx < TiedMax)
1441 UseMO.TiedTo = DefIdx + 1;
1446 assert(isInlineAsm() &&
"DefIdx out of range");
1451 DefMO.TiedTo =
std::min(UseIdx + 1, TiedMax);
1462 if (MO.TiedTo < TiedMax)
1463 return MO.TiedTo - 1;
1466 if (!isInlineAsm()) {
1471 for (
unsigned i = TiedMax - 1, e = getNumOperands();
i != e; ++
i) {
1473 if (UseMO.
isReg() && UseMO.
isUse() && UseMO.TiedTo == OpIdx + 1)
1482 unsigned OpIdxGroup = ~0u;
1487 assert(FlagMO.
isImm() &&
"Invalid tied operand on inline asm");
1488 unsigned CurGroup = GroupIdx.
size();
1492 if (OpIdx >
i && OpIdx <
i + NumOps)
1493 OpIdxGroup = CurGroup;
1499 unsigned Delta =
i - GroupIdx[TiedGroup];
1502 if (OpIdxGroup == CurGroup)
1503 return OpIdx - Delta;
1506 if (OpIdxGroup == TiedGroup)
1507 return OpIdx + Delta;
1527 ToReg = RegInfo.
getSubReg(ToReg, SubIdx);
1551 if (mayStore() || isCall() ||
1552 (mayLoad() && hasOrderedMemoryRef())) {
1557 if (isPosition() || isDebugValue() || isTerminator() ||
1558 hasUnmodeledSideEffects())
1566 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1583 !hasUnmodeledSideEffects())
1588 if (memoperands_empty())
1607 if (memoperands_empty())
1613 if (MMO->isVolatile())
return false;
1614 if (MMO->isStore())
return false;
1615 if (MMO->isInvariant() && MMO->isDereferenceable())
1620 if (PSV->isConstant(&MFI))
1623 if (
const Value *V = MMO->getValue()) {
1645 assert(getNumOperands() >= 3 &&
1646 "It's illegal to have a PHI without source operands");
1648 unsigned Reg = getOperand(1).getReg();
1649 for (
unsigned i = 3, e = getNumOperands();
i < e;
i += 2)
1650 if (getOperand(
i).
getReg() != Reg)
1658 if (isInlineAsm()) {
1668 return mayStore() || isCall() || hasUnmodeledSideEffects();
1696 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1704 const Module *M =
nullptr;
1710 print(OS, MST, SkipOpers, TII);
1736 unsigned StartOp = 0, e = getNumOperands();
1737 for (; StartOp < e && getOperand(StartOp).isReg() &&
1738 getOperand(StartOp).isDef() &&
1739 !getOperand(StartOp).isImplicit();
1741 if (StartOp != 0) OS <<
", ";
1742 getOperand(StartOp).print(OS, MST, TRI, IntrinsicInfo);
1743 unsigned Reg = getOperand(StartOp).getReg();
1748 OS <<
'(' << Ty <<
')';
1757 OS << TII->
getName(getOpcode());
1765 bool OmittedAnyCallClobbers =
false;
1766 bool FirstOp =
true;
1767 unsigned AsmDescOp = ~0u;
1768 unsigned AsmOpCount = 0;
1778 OS <<
" [sideeffect]";
1782 OS <<
" [maystore]";
1784 OS <<
" [isconvergent]";
1786 OS <<
" [alignstack]";
1788 OS <<
" [attdialect]";
1790 OS <<
" [inteldialect]";
1796 for (
unsigned i = StartOp, e = getNumOperands();
i != e; ++
i) {
1806 if (MRI && isCall() &&
1808 unsigned Reg = MO.
getReg();
1811 bool HasAliasLive =
false;
1813 unsigned AliasReg = *AI;
1815 HasAliasLive =
true;
1819 if (!HasAliasLive) {
1820 OmittedAnyCallClobbers =
true;
1827 if (FirstOp) FirstOp =
false;
else OS <<
",";
1839 if (DIV && !DIV->getName().empty())
1840 OS <<
"!\"" << DIV->getName() <<
'\"';
1842 MO.
print(OS, MST, TRI);
1843 }
else if (TRI && (isInsertSubreg() || isRegSequence() ||
1844 (isSubregToReg() &&
i == 3)) && MO.
isImm()) {
1846 }
else if (
i == AsmDescOp && MO.
isImm()) {
1848 OS <<
'$' << AsmOpCount++;
1866 OS <<
":RC" << RCID;
1892 default: OS <<
":?";
break;
1896 unsigned TiedTo = 0;
1898 OS <<
" tiedto:$" << TiedTo;
1905 MO.
print(OS, MST, TRI);
1909 if (OmittedAnyCallClobbers) {
1910 if (!FirstOp) OS <<
",";
1914 bool HaveSemi =
false;
1915 const unsigned PrintableFlags = FrameSetup | FrameDestroy;
1916 if (
Flags & PrintableFlags) {
1923 if (
Flags & FrameSetup)
1926 if (
Flags & FrameDestroy)
1927 OS <<
"FrameDestroy";
1930 if (!memoperands_empty()) {
1937 for (
mmo_iterator i = memoperands_begin(), e = memoperands_end();
1939 (*i)->print(OS, MST);
1940 if (std::next(
i) != e)
1946 if (MRI && !VirtRegs.
empty()) {
1951 for (
unsigned i = 0;
i != VirtRegs.
size(); ++
i) {
1961 OS <<
':' <<
PrintReg(VirtRegs[i]);
1962 for (
unsigned j = i+1; j != VirtRegs.
size();) {
1967 if (VirtRegs[i] != VirtRegs[j])
1968 OS <<
"," <<
PrintReg(VirtRegs[j]);
1975 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1978 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1979 OS <<
" line no:" << DV->getLine();
1980 if (
auto *InlinedAt = debugLoc->getInlinedAt()) {
1982 if (InlinedAtDL && MF) {
1983 OS <<
" inlined @[ ";
1984 InlinedAtDL.
print(OS);
1988 if (isIndirectDebugValue())
1990 }
else if (debugLoc && MF) {
2002 bool AddIfNotFound) {
2004 bool hasAliases = isPhysReg &&
2008 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i) {
2019 unsigned Reg = MO.
getReg();
2023 if (Reg == IncomingReg) {
2028 if (isPhysReg && isRegTiedToDefOperand(
i))
2034 }
else if (hasAliases && MO.
isKill() &&
2045 while (!DeadOps.
empty()) {
2046 unsigned OpIdx = DeadOps.
back();
2048 RemoveOperand(OpIdx);
2050 getOperand(OpIdx).setIsKill(
false);
2056 if (!Found && AddIfNotFound) {
2073 unsigned OpReg = MO.
getReg();
2074 if ((RegInfo && RegInfo->
regsOverlap(Reg, OpReg)) || Reg == OpReg)
2081 bool AddIfNotFound) {
2083 bool hasAliases = isPhysReg &&
2087 for (
unsigned i = 0, e = getNumOperands();
i != e; ++
i) {
2091 unsigned MOReg = MO.
getReg();
2098 }
else if (hasAliases && MO.
isDead() &&
2109 while (!DeadOps.
empty()) {
2110 unsigned OpIdx = DeadOps.
back();
2112 RemoveOperand(OpIdx);
2114 getOperand(OpIdx).setIsDead(
false);
2120 if (Found || !AddIfNotFound)
2150 MachineOperand *MO = findRegisterDefOperand(Reg,
false, RegInfo);
2167 bool HasRegMask =
false;
2174 unsigned Reg = MO.
getReg();
2187 addRegisterDefined(*
I, &TRI);
2208 unsigned LocCookie = 0;
2209 const MDNode *LocMD =
nullptr;
2210 for (
unsigned i = getNumOperands();
i != 0; --
i) {
2215 mdconst::dyn_extract<ConstantInt>(LocMD->
getOperand(0))) {
2224 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2230 unsigned Reg,
unsigned Offset,
2232 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2233 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2234 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2235 "Expected inlined-at fields to agree");
2243 assert(Offset == 0 &&
"A direct address cannot have an offset.");
2255 bool IsIndirect,
unsigned Reg,
2258 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2259 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2262 BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, Variable, Expr);
static bool Check(DecodeStatus &Out, DecodeStatus In)
void bundleWithPred()
Bundle this instruction with its predecessor.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void print(raw_ostream &OS, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
void setTargetFlags(unsigned F)
const ConstantFP * getFPImm() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
A Module instance is used to store all the information related to an LLVM module. ...
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getNumOperands() const
Return number of MDNode operands.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Describe properties that are true of each instruction in the target description file.
void setIsUndef(bool Val=true)
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Address of indexed Jump Table for switch.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool isBundle(MCInst const &MCI)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
MachineBasicBlock reference.
const char * getSymbolName() const
void setIsDead(bool Val=true)
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
Manage lifetime of a slot tracker for printing IR.
const MDNode * getMetadata() const
void reserve(size_type N)
Mask of live-out registers.
iterator_range< mop_iterator > operands()
void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with strcmp
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
static bool isImmKind(unsigned Flag)
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
Mask of preserved registers.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void ChangeToMCSymbol(MCSymbol *Sym)
ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void clearKillInfo()
Clears kill flags on all operands.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
unsigned getCFIIndex() const
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
A Use represents the edge between a Value definition and its users.
void ChangeToES(const char *SymName, unsigned char TargetFlags=0)
ChangeToES - Replace this operand with a new external symbol operand.
Target-dependent index+offset operand.
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Name of external global symbol.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly...
Reg
All possible values of the reg field in the ModR/M byte.
static StringRef getName(Value *V)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void bundleWithSucc()
Bundle this instruction with its successor.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void print(raw_ostream &OS) const
prints source location /path/to/file.exe:line:col @[inlined at]
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
void setIsEarlyClobber(bool Val=true)
void unbundleFromPred()
Break bundle above this instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Immediate >64bit operand.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
struct llvm::MachineOperand::@38::@39 Reg
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
unsigned short NumOperands
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
TargetInstrInfo - Interface to description of machine instruction set.
mmo_iterator memoperands_end() const
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
bool isEarlyClobber() const
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Address of a global value.
initializer< Ty > init(const Ty &Val)
Intrinsic::ID getIntrinsicID() const
unsigned getTargetFlags() const
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
bool isOptionalDef() const
Set if this operand is a optional def.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
ConstantFP - Floating Point Values [float, double].
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
MCRegAliasIterator enumerates all registers aliasing Reg.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
static unsigned getMemoryConstraintID(unsigned Flag)
Address of a basic block.
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
static unsigned getKind(unsigned Flags)
int64_t getOffset() const
Return the offset from the symbol in this operand.
self_iterator getIterator()
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
void setOffset(int64_t Offset)
unsigned getSubReg() const
static unsigned getHashValue(const MachineInstr *const &MI)
static bool isMemKind(unsigned Flag)
iterator erase(const_iterator CI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
TargetIntrinsicInfo - Interface to description of machine instruction set.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
Representation for a specific memory location.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
const MDOperand & getOperand(unsigned I) const
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
bool memoperands_empty() const
Return true if we don't have any memory operands which described the the memory access done by this i...
Iterator for intrusive lists based on ilist_node.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
Generic predicate for ISel.
T get() const
Returns the value of the specified pointer type.
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
void ChangeToFPImmediate(const ConstantFP *FPImm)
ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value...
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
unsigned getPredicate() const
void dump(const TargetInstrInfo *TII=nullptr) const
This class implements the register bank concept.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
friend hash_code hash_value(const MachineOperand &MO)
MachineOperand hash_value overload.
MCSymbol reference (for debug/eh info)
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const ConstantInt * getCImm() const
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Special value supplied for machine level alias analysis.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
An opaque object representing a hash code.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
union llvm::MachineOperand::@38::@40::@41 Val
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges. ...
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
std::pair< mmo_iterator, unsigned > mergeMemRefsWith(const MachineInstr &Other)
Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of b...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void setSubReg(unsigned subReg)
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
MCSymbol * getMCSymbol() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Abstract Stack Frame Index.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void unbundleFromSucc()
Break bundle below this instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
virtual const TargetInstrInfo * getInstrInfo() const
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
Floating-point immediate operand.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void ChangeToFrameIndex(int Idx)
Replace this operand with a frame index.
This class implements an extremely fast bulk output stream that can only output to a stream...
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
const BlockAddress * getBlockAddress() const
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
Address of indexed Constant in Constant Pool.
bool isStackAligningInlineAsm() const
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
This holds information about one operand of a machine instruction, indicating the register class for ...
int is() const
Test if the Union currently holds the type matching T.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineInstr::mmo_iterator allocateMemRefsArray(unsigned long Num)
allocateMemRefsArray - Allocate an array to hold MachineMemOperand pointers.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool isInternalRead() const
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Metadata reference (for debug info)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
static cl::opt< bool > PrintWholeRegMask("print-whole-regmask", cl::desc("Print the full contents of regmask operands in IR dumps"), cl::init(true), cl::Hidden)
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.