23 #define GET_INSTRINFO_CTOR_DTOR
24 #define GET_INSTRMAP_INFO
25 #include "SystemZGenInstrInfo.inc"
28 static uint64_t
allOnes(
unsigned int Count) {
29 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
35 if (SystemZ::GRH32BitRegClass.
contains(Reg))
42 void SystemZInstrInfo::anchor() {}
52 unsigned NewOpcode)
const {
59 MBB->
insert(MI, EarlierMI);
64 HighRegOp.
setReg(RI.getSubReg(HighRegOp.
getReg(), SystemZ::subreg_h64));
65 LowRegOp.
setReg(RI.getSubReg(LowRegOp.
getReg(), SystemZ::subreg_l64));
81 assert(HighOpcode && LowOpcode &&
"Both offsets should be in range");
83 EarlierMI->
setDesc(
get(HighOpcode));
84 MI->setDesc(
get(LowOpcode));
98 assert(NewOpcode &&
"No support for huge argument lists yet");
99 MI->setDesc(
get(NewOpcode));
109 void SystemZInstrInfo::expandRIPseudo(
MachineInstr &MI,
unsigned LowOpcode,
111 bool ConvertHigh)
const {
114 MI.
setDesc(
get(IsHigh ? HighOpcode : LowOpcode));
115 if (IsHigh && ConvertHigh)
123 void SystemZInstrInfo::expandRIEPseudo(
MachineInstr &MI,
unsigned LowOpcode,
125 unsigned HighOpcode)
const {
130 if (!DestIsHigh && !SrcIsHigh)
135 MI.
setDesc(
get(DestIsHigh ? HighOpcode : LowOpcode));
144 void SystemZInstrInfo::expandRXYPseudo(
MachineInstr &MI,
unsigned LowOpcode,
145 unsigned HighOpcode)
const {
155 void SystemZInstrInfo::expandLOCPseudo(
MachineInstr &MI,
unsigned LowOpcode,
156 unsigned HighOpcode)
const {
158 unsigned Opcode =
isHighReg(Reg) ? HighOpcode : LowOpcode;
165 void SystemZInstrInfo::expandLOCRPseudo(
MachineInstr &MI,
unsigned LowOpcode,
166 unsigned HighOpcode)
const {
172 if (!DestIsHigh && !SrcIsHigh)
174 else if (DestIsHigh && SrcIsHigh)
186 void SystemZInstrInfo::expandZExtPseudo(
MachineInstr &MI,
unsigned LowOpcode,
187 unsigned Size)
const {
194 void SystemZInstrInfo::expandLoadStackGuard(
MachineInstr *MI)
const {
205 Ear1MI->
setDesc(
get(SystemZ::EAR));
211 SllgMI->
setDesc(
get(SystemZ::SLLG));
217 Ear2MI->
setDesc(
get(SystemZ::EAR));
232 const DebugLoc &DL,
unsigned DestReg,
233 unsigned SrcReg,
unsigned LowLowOpcode,
234 unsigned Size,
bool KillSrc)
const {
238 if (DestIsHigh && SrcIsHigh)
239 Opcode = SystemZ::RISBHH;
240 else if (DestIsHigh && !SrcIsHigh)
241 Opcode = SystemZ::RISBHL;
242 else if (!DestIsHigh && SrcIsHigh)
243 Opcode = SystemZ::RISBLH;
245 BuildMI(MBB, MBBI, DL,
get(LowLowOpcode), DestReg)
249 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
250 BuildMI(MBB, MBBI, DL,
get(Opcode), DestReg)
260 unsigned OpIdx2)
const {
268 case SystemZ::LOCRMux:
269 case SystemZ::LOCFHR:
271 case SystemZ::LOCGR: {
272 auto &WorkingMI = cloneIfNew(MI);
274 unsigned CCValid = WorkingMI.getOperand(3).getImm();
275 unsigned CCMask = WorkingMI.getOperand(4).getImm();
276 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
314 int &SrcFrameIndex)
const {
330 DestFrameIndex = FI1;
339 bool AllowModify)
const {
345 while (I != MBB.
begin()) {
347 if (I->isDebugValue())
352 if (!isUnpredicatedTerminator(*I))
377 while (std::next(I) != MBB.
end())
386 I->eraseFromParent();
407 assert(Cond.
size() == 2 && TBB &&
"Should have seen a conditional branch");
415 unsigned OldCCValid = Cond[0].getImm();
416 unsigned OldCCMask = Cond[1].getImm();
417 if (OldCCValid == Branch.
CCValid && OldCCMask == Branch.
CCMask)
428 int *BytesRemoved)
const {
429 assert(!BytesRemoved &&
"code size not handled");
435 while (I != MBB.
begin()) {
437 if (I->isDebugValue())
444 I->eraseFromParent();
454 assert(Cond.
size() == 2 &&
"Invalid condition");
455 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
464 int *BytesAdded)
const {
470 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
472 "SystemZ branch conditions have one component!");
473 assert(!BytesAdded &&
"code size not handled");
477 assert(!FBB &&
"Unconditional branch with multiple successors!");
484 unsigned CCValid = Cond[0].getImm();
485 unsigned CCMask = Cond[1].getImm();
486 BuildMI(&MBB, DL,
get(SystemZ::BRC))
499 unsigned &SrcReg2,
int &
Mask,
501 assert(MI.
isCompare() &&
"Caller should have checked for a comparison");
545 if (RLL && RLL->
getOpcode() == SystemZ::LGFR) {
549 if (!RLL || !
isShift(RLL, SystemZ::RLL, 31))
564 for (++MBBI; MBBI != MBBE; ++MBBI) {
583 assert(!SrcReg2 &&
"Only optimizing constant comparisons so far");
585 return Value == 0 && !IsLogical &&
592 unsigned TrueReg,
unsigned FalseReg,
593 int &CondCycles,
int &TrueCycles,
594 int &FalseCycles)
const {
598 if (Pred.
size() != 2)
610 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
611 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
612 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
625 const DebugLoc &DL,
unsigned DstReg,
628 unsigned FalseReg)
const {
632 assert(Pred.
size() == 2 &&
"Invalid condition");
633 unsigned CCValid = Pred[0].getImm();
634 unsigned CCMask = Pred[1].getImm();
637 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
639 Opc = SystemZ::LOCRMux;
644 }
else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
645 Opc = SystemZ::LOCGR;
649 BuildMI(MBB, I, DL,
get(Opc), DstReg)
658 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
659 DefOpc != SystemZ::LGHI)
670 case SystemZ::LOCRMux:
673 NewUseOpc = SystemZ::LOCHIMux;
677 UseIdx = 2, CommuteIdx = 1;
684 NewUseOpc = SystemZ::LOCGHI;
688 UseIdx = 2, CommuteIdx = 1;
696 if (CommuteIdx != -1)
697 if (!commuteInstruction(UseMI,
false, CommuteIdx, UseIdx))
712 Opcode == SystemZ::Trap ||
713 Opcode == SystemZ::CallJG ||
714 Opcode == SystemZ::CallBR)
721 unsigned NumCycles,
unsigned ExtraPredCycles,
735 return NumCycles == 1;
740 unsigned NumCyclesT,
unsigned ExtraPredCyclesT,
742 unsigned NumCyclesF,
unsigned ExtraPredCyclesF,
752 return NumCycles == 1;
757 assert(Pred.
size() == 2 &&
"Invalid condition");
758 unsigned CCValid = Pred[0].getImm();
759 unsigned CCMask = Pred[1].getImm();
760 assert(CCMask > 0 && CCMask < 15 &&
"Invalid predicate");
762 if (Opcode == SystemZ::Trap) {
763 MI.
setDesc(
get(SystemZ::CondTrap));
765 .addImm(CCValid).
addImm(CCMask)
770 MI.
setDesc(
get(SystemZ::CondReturn));
772 .addImm(CCValid).
addImm(CCMask)
776 if (Opcode == SystemZ::CallJG) {
781 MI.
setDesc(
get(SystemZ::CallBRCL));
783 .addImm(CCValid).
addImm(CCMask)
789 if (Opcode == SystemZ::CallBR) {
792 MI.
setDesc(
get(SystemZ::CallBCR));
794 .addImm(CCValid).
addImm(CCMask)
804 const DebugLoc &DL,
unsigned DestReg,
805 unsigned SrcReg,
bool KillSrc)
const {
807 if (SystemZ::GR128BitRegClass.
contains(DestReg, SrcReg)) {
808 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
809 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
810 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
811 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
815 if (SystemZ::GRX32BitRegClass.
contains(DestReg, SrcReg)) {
816 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
822 if (SystemZ::GR64BitRegClass.
contains(DestReg, SrcReg))
823 Opcode = SystemZ::LGR;
824 else if (SystemZ::FP32BitRegClass.
contains(DestReg, SrcReg))
826 Opcode = STI.
hasVector() ? SystemZ::LDR32 : SystemZ::LER;
827 else if (SystemZ::FP64BitRegClass.
contains(DestReg, SrcReg))
829 else if (SystemZ::FP128BitRegClass.
contains(DestReg, SrcReg))
830 Opcode = SystemZ::LXR;
831 else if (SystemZ::VR32BitRegClass.
contains(DestReg, SrcReg))
832 Opcode = SystemZ::VLR32;
833 else if (SystemZ::VR64BitRegClass.
contains(DestReg, SrcReg))
834 Opcode = SystemZ::VLR64;
835 else if (SystemZ::VR128BitRegClass.
contains(DestReg, SrcReg))
836 Opcode = SystemZ::VLR;
837 else if (SystemZ::AR32BitRegClass.
contains(DestReg, SrcReg))
838 Opcode = SystemZ::CPYA;
839 else if (SystemZ::AR32BitRegClass.
contains(DestReg) &&
840 SystemZ::GR32BitRegClass.
contains(SrcReg))
841 Opcode = SystemZ::SAR;
842 else if (SystemZ::GR32BitRegClass.
contains(DestReg) &&
843 SystemZ::AR32BitRegClass.
contains(SrcReg))
844 Opcode = SystemZ::EAR;
848 BuildMI(MBB, MBBI, DL,
get(Opcode), DestReg)
860 unsigned LoadOpcode, StoreOpcode;
875 unsigned LoadOpcode, StoreOpcode;
885 return ((MCID.
TSFlags & Flag) &&
892 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
893 LogicOp(
unsigned regSize,
unsigned immLSB,
unsigned immSize)
894 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
896 explicit operator bool()
const {
return RegSize; }
898 unsigned RegSize, ImmLSB, ImmSize;
904 case SystemZ::NILMux:
return LogicOp(32, 0, 16);
905 case SystemZ::NIHMux:
return LogicOp(32, 16, 16);
906 case SystemZ::NILL64:
return LogicOp(64, 0, 16);
907 case SystemZ::NILH64:
return LogicOp(64, 16, 16);
908 case SystemZ::NIHL64:
return LogicOp(64, 32, 16);
909 case SystemZ::NIHH64:
return LogicOp(64, 48, 16);
910 case SystemZ::NIFMux:
return LogicOp(32, 0, 32);
911 case SystemZ::NILF64:
return LogicOp(64, 0, 32);
912 case SystemZ::NIHF64:
return LogicOp(64, 32, 32);
913 default:
return LogicOp();
920 if (CCDef !=
nullptr)
932 for (
unsigned I = 1;
I < NumOps; ++
I) {
958 unsigned DestReg = Dest.
getReg();
959 unsigned SrcReg = Src.
getReg();
963 if (Opcode == SystemZ::AHIMux &&
971 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
972 if (ThreeOperandOpcode >= 0) {
983 for (
unsigned I = 2;
I < NumOps; ++
I)
998 if (
And.RegSize == 64) {
999 NewOpcode = SystemZ::RISBG;
1002 NewOpcode = SystemZ::RISBGN;
1004 NewOpcode = SystemZ::RISBMux;
1034 if (Ops.
size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1035 if (LIS !=
nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1046 if (!CCLiveRange.
liveAt(MISlot)) {
1062 if (Ops.
size() != 1)
1065 unsigned OpNum = Ops[0];
1070 "Invalid size combination");
1072 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1075 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1085 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1086 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1087 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1091 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1095 .addFrameIndex(FrameIndex)
1102 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG :
SystemZ::LD;
1105 get(LoadOpcode), Dest)
1137 .addMemOperand(MMO);
1155 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1156 if (MemOpcode >= 0) {
1158 if (OpNum == NumOps - 1) {
1161 assert(AccessBytes != 0 &&
"Size of access should be known");
1162 assert(AccessBytes <= Size &&
"Access outside the frame index");
1163 uint64_t Offset = Size - AccessBytes;
1166 for (
unsigned I = 0;
I < OpNum; ++
I)
1189 splitMove(MI, SystemZ::LG);
1192 case SystemZ::ST128:
1193 splitMove(MI, SystemZ::STG);
1201 splitMove(MI, SystemZ::STD);
1204 case SystemZ::LBMux:
1205 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1208 case SystemZ::LHMux:
1209 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1212 case SystemZ::LLCRMux:
1213 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1216 case SystemZ::LLHRMux:
1217 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1220 case SystemZ::LLCMux:
1221 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1224 case SystemZ::LLHMux:
1225 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1229 expandRXYPseudo(MI,
SystemZ::L, SystemZ::LFH);
1232 case SystemZ::LOCMux:
1233 expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1236 case SystemZ::LOCHIMux:
1237 expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1240 case SystemZ::LOCRMux:
1241 expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1244 case SystemZ::STCMux:
1245 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1248 case SystemZ::STHMux:
1249 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1252 case SystemZ::STMux:
1256 case SystemZ::STOCMux:
1257 expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1260 case SystemZ::LHIMux:
1261 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF,
true);
1264 case SystemZ::IIFMux:
1265 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF,
false);
1268 case SystemZ::IILMux:
1269 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL,
false);
1272 case SystemZ::IIHMux:
1273 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH,
false);
1276 case SystemZ::NIFMux:
1277 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF,
false);
1280 case SystemZ::NILMux:
1281 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL,
false);
1284 case SystemZ::NIHMux:
1285 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH,
false);
1288 case SystemZ::OIFMux:
1289 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF,
false);
1292 case SystemZ::OILMux:
1293 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL,
false);
1296 case SystemZ::OIHMux:
1297 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH,
false);
1300 case SystemZ::XIFMux:
1301 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF,
false);
1304 case SystemZ::TMLMux:
1305 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL,
false);
1308 case SystemZ::TMHMux:
1309 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH,
false);
1312 case SystemZ::AHIMux:
1313 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH,
false);
1316 case SystemZ::AHIMuxK:
1317 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1320 case SystemZ::AFIMux:
1321 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH,
false);
1324 case SystemZ::CHIMux:
1325 expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH,
false);
1328 case SystemZ::CFIMux:
1329 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH,
false);
1332 case SystemZ::CLFIMux:
1333 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH,
false);
1337 expandRXYPseudo(MI,
SystemZ::C, SystemZ::CHF);
1340 case SystemZ::CLMux:
1341 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1344 case SystemZ::RISBMux: {
1347 if (SrcIsHigh == DestIsHigh)
1348 MI.
setDesc(
get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1350 MI.
setDesc(
get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1357 splitAdjDynAlloc(MI);
1360 case TargetOpcode::LOAD_STACK_GUARD:
1361 expandLoadStackGuard(&MI);
1393 case SystemZ::BRCTH:
1397 case SystemZ::BRCTG:
1416 case SystemZ::CLGIJ:
1417 case SystemZ::CLGRJ:
1427 unsigned &LoadOpcode,
1428 unsigned &StoreOpcode)
const {
1429 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1432 }
else if (RC == &SystemZ::GRH32BitRegClass) {
1433 LoadOpcode = SystemZ::LFH;
1434 StoreOpcode = SystemZ::STFH;
1435 }
else if (RC == &SystemZ::GRX32BitRegClass) {
1436 LoadOpcode = SystemZ::LMux;
1437 StoreOpcode = SystemZ::STMux;
1438 }
else if (RC == &SystemZ::GR64BitRegClass ||
1439 RC == &SystemZ::ADDR64BitRegClass) {
1440 LoadOpcode = SystemZ::LG;
1441 StoreOpcode = SystemZ::STG;
1442 }
else if (RC == &SystemZ::GR128BitRegClass ||
1443 RC == &SystemZ::ADDR128BitRegClass) {
1444 LoadOpcode = SystemZ::L128;
1445 StoreOpcode = SystemZ::ST128;
1446 }
else if (RC == &SystemZ::FP32BitRegClass) {
1448 StoreOpcode = SystemZ::STE;
1449 }
else if (RC == &SystemZ::FP64BitRegClass) {
1451 StoreOpcode = SystemZ::STD;
1452 }
else if (RC == &SystemZ::FP128BitRegClass) {
1453 LoadOpcode = SystemZ::LX;
1454 StoreOpcode = SystemZ::STX;
1455 }
else if (RC == &SystemZ::VR32BitRegClass) {
1456 LoadOpcode = SystemZ::VL32;
1457 StoreOpcode = SystemZ::VST32;
1458 }
else if (RC == &SystemZ::VR64BitRegClass) {
1459 LoadOpcode = SystemZ::VL64;
1460 StoreOpcode = SystemZ::VST64;
1461 }
else if (RC == &SystemZ::VF128BitRegClass ||
1462 RC == &SystemZ::VR128BitRegClass) {
1463 LoadOpcode = SystemZ::VL;
1464 StoreOpcode = SystemZ::VST;
1470 int64_t Offset)
const {
1473 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1475 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1476 if (Disp12Opcode >= 0)
1477 return Disp12Opcode;
1483 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1485 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1486 if (Disp20Opcode >= 0)
1487 return Disp20Opcode;
1500 case SystemZ::LG:
return SystemZ::LTG;
1501 case SystemZ::LGF:
return SystemZ::LTGF;
1502 case SystemZ::LR:
return SystemZ::LTR;
1503 case SystemZ::LGFR:
return SystemZ::LTGFR;
1504 case SystemZ::LGR:
return SystemZ::LTGR;
1505 case SystemZ::LER:
return SystemZ::LTEBR;
1507 case SystemZ::LXR:
return SystemZ::LTXBR;
1508 case SystemZ::LCDFR:
return SystemZ::LCDBR;
1509 case SystemZ::LPDFR:
return SystemZ::LPDBR;
1510 case SystemZ::LNDFR:
return SystemZ::LNDBR;
1511 case SystemZ::LCDFR_32:
return SystemZ::LCEBR;
1512 case SystemZ::LPDFR_32:
return SystemZ::LPEBR;
1513 case SystemZ::LNDFR_32:
return SystemZ::LNEBR;
1518 case SystemZ::RISBGN:
return SystemZ::RISBG;
1528 uint64_t Top = (Mask >> First) + 1;
1529 if ((Top & -Top) == Top) {
1538 unsigned &Start,
unsigned &
End)
const {
1546 unsigned LSB, Length;
1548 Start = 63 - (LSB + Length - 1);
1556 assert(LSB > 0 &&
"Bottom bit must be set");
1557 assert(LSB + Length < BitSize &&
"Top bit must be set");
1558 Start = 63 - (LSB - 1);
1559 End = 63 - (LSB + Length);
1576 case SystemZ::CLGFI:
1592 return SystemZ::CRJ;
1594 return SystemZ::CGRJ;
1596 return SystemZ::CIJ;
1598 return SystemZ::CGIJ;
1600 return SystemZ::CLRJ;
1602 return SystemZ::CLGRJ;
1604 return SystemZ::CLIJ;
1605 case SystemZ::CLGFI:
1606 return SystemZ::CLGIJ;
1613 return SystemZ::CRBReturn;
1615 return SystemZ::CGRBReturn;
1617 return SystemZ::CIBReturn;
1619 return SystemZ::CGIBReturn;
1621 return SystemZ::CLRBReturn;
1623 return SystemZ::CLGRBReturn;
1625 return SystemZ::CLIBReturn;
1626 case SystemZ::CLGFI:
1627 return SystemZ::CLGIBReturn;
1634 return SystemZ::CRBCall;
1636 return SystemZ::CGRBCall;
1638 return SystemZ::CIBCall;
1640 return SystemZ::CGIBCall;
1642 return SystemZ::CLRBCall;
1644 return SystemZ::CLGRBCall;
1646 return SystemZ::CLIBCall;
1647 case SystemZ::CLGFI:
1648 return SystemZ::CLGIBCall;
1655 return SystemZ::CRT;
1657 return SystemZ::CGRT;
1659 return SystemZ::CIT;
1661 return SystemZ::CGIT;
1663 return SystemZ::CLRT;
1665 return SystemZ::CLGRT;
1667 return SystemZ::CLFIT;
1668 case SystemZ::CLGFI:
1669 return SystemZ::CLGIT;
1671 return SystemZ::CLT;
1673 return SystemZ::CLGT;
1687 return SystemZ::LAT;
1689 return SystemZ::LGAT;
1691 return SystemZ::LFHAT;
1693 return SystemZ::LLGFAT;
1695 return SystemZ::LLGTAT;
1702 unsigned Reg, uint64_t
Value)
const {
1706 Opcode = SystemZ::LGHI;
1708 Opcode = SystemZ::LLILL;
1710 Opcode = SystemZ::LLILH;
1714 Opcode = SystemZ::LGFI;
1734 bool SameVal = (VALa && VALb && (VALa == VALb));
1738 if (PSVa && PSVb && (PSVa == PSVb))
1744 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1745 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1746 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1747 if (LowOffset + LowWidth <= HighOffset)
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getLoadAndTrap(unsigned Opcode) const
bool expandPostRAPseudo(MachineInstr &MBBI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
const int64_t CallFrameSize
SystemZInstrInfo(SystemZSubtarget &STI)
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
MachineBasicBlock * getMBB() const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI)
constexpr bool isInt< 8 >(int64_t x)
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const char * getSymbolName() const
constexpr bool isInt< 16 >(int64_t x)
void setIsDead(bool Val=true)
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
const unsigned CCMASK_ICMP
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
return AArch64::GPR64RegClass contains(Reg)
static uint64_t allOnes(unsigned int Count)
This class represents the liveness of a register, stack slot, etc.
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned getLoadAndTest(unsigned Opcode) const
static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
bool hasLoadStoreOnCond() const
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool hasLoadStoreOnCond2() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
static LogicOp interpretAndImmediate(unsigned Opcode)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const MachineOperand * Target
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
const unsigned CCMASK_ANY
size_t size() const
size - Get the array size.
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
SlotIndexes * getSlotIndexes() const
Control flow instructions. These all have token chains.
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
constexpr bool isUInt< 8 >(uint64_t x)
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
static unsigned getAccessSize(unsigned int Flags)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
static const unsigned End
void setImm(int64_t immVal)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
self_iterator getIterator()
const PseudoSourceValue * getPseudoValue() const
bool empty() const
empty - Check if the array is empty.
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
unsigned getSubReg() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
static bool isImmLH(uint64_t Val)
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static bool isHighReg(unsigned int Reg)
Iterator for intrusive lists based on ilist_node.
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
constexpr bool isInt< 32 >(int64_t x)
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
MachineOperand class - Representation of each machine instruction operand.
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isPredicable(MachineInstr &MI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const unsigned CCMASK_CMP_NE
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
const Value * getValue() const
Return the base address of the memory access.
Special value supplied for machine level alias analysis.
static MachineInstr * finishConvertToThreeAddress(MachineInstr *OldMI, MachineInstr *NewMI, LiveVariables *LV)
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
bool hasMiscellaneousExtensions() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static MachineInstr * getDef(unsigned Reg, const MachineRegisterInfo *MRI)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
bool hasLoadAndTrap() const
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
bool hasDistinctOps() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
uint64_t getSize() const
Return the size in bytes of the memory reference.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isImmLL(uint64_t Val)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SlotIndex - An opaque wrapper around machine indexes.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.