LLVM  4.0.0
Macros | Functions | Variables
AArch64AdvSIMDScalarPass.cpp File Reference
#include "AArch64.h"
#include "AArch64InstrInfo.h"
#include "AArch64RegisterInfo.h"
#include "AArch64Subtarget.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
Include dependency graph for AArch64AdvSIMDScalarPass.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "aarch64-simd-scalar"
 
#define AARCH64_ADVSIMD_NAME   "AdvSIMD Scalar Operation Optimization"
 

Functions

 STATISTIC (NumScalarInsnsUsed,"Number of scalar instructions used")
 
 STATISTIC (NumCopiesDeleted,"Number of cross-class copies deleted")
 
 STATISTIC (NumCopiesInserted,"Number of cross-class copies inserted")
 
 INITIALIZE_PASS (AArch64AdvSIMDScalar,"aarch64-simd-scalar", AARCH64_ADVSIMD_NAME, false, false) static bool isGPR64(unsigned Reg
 
 if (TargetRegisterInfo::isVirtualRegister(Reg)) return MRI-> getRegClass(Reg) ->hasSuperClassEq(&AArch64::GPR64RegClass)
 
return AArch64::GPR64RegClass contains (Reg)
 
static bool isFPR64 (unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI)
 
static MachineOperandgetSrcFromCopy (MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg)
 
static unsigned getTransformOpcode (unsigned Opc)
 
static bool isTransformable (const MachineInstr &MI)
 
static MachineInstrinsertCopy (const TargetInstrInfo *TII, MachineInstr &MI, unsigned Dst, unsigned Src, bool IsKill)
 

Variables

static cl::opt< boolTransformAll ("aarch64-simd-scalar-force-all", cl::desc("Force use of AdvSIMD scalar instructions everywhere"), cl::init(false), cl::Hidden)
 
unsigned SubReg
 
unsigned const
MachineRegisterInfo
MRI
 

Macro Definition Documentation

#define AARCH64_ADVSIMD_NAME   "AdvSIMD Scalar Operation Optimization"

Definition at line 64 of file AArch64AdvSIMDScalarPass.cpp.

#define DEBUG_TYPE   "aarch64-simd-scalar"

Definition at line 51 of file AArch64AdvSIMDScalarPass.cpp.

Function Documentation

return AArch64::GPR64RegClass contains ( Reg  )

Referenced by llvm::LoopBase< N, M >::addBasicBlockToLoop(), llvm::X86Operand::addGR32orGR64Operands(), llvm::HexagonPacketizerList::addToPacket(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), CheckBaseRegAndIndexReg(), computeCalleeSaveRegisterPairs(), llvm::RegionBase< RegionTr >::contains(), llvm::BPFInstrInfo::copyPhysReg(), llvm::Thumb1InstrInfo::copyPhysReg(), llvm::Thumb2InstrInfo::copyPhysReg(), llvm::Mips16InstrInfo::copyPhysReg(), llvm::MipsSEInstrInfo::copyPhysReg(), llvm::LanaiInstrInfo::copyPhysReg(), llvm::MSP430InstrInfo::copyPhysReg(), llvm::R600InstrInfo::copyPhysReg(), llvm::AVRInstrInfo::copyPhysReg(), llvm::SparcInstrInfo::copyPhysReg(), llvm::SIInstrInfo::copyPhysReg(), llvm::AArch64InstrInfo::copyPhysReg(), llvm::HexagonInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), llvm::PPCInstrInfo::copyPhysReg(), llvm::SystemZInstrInfo::copyPhysReg(), llvm::X86InstrInfo::copyPhysReg(), CopyToFromAsymmetricReg(), llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::SystemZFrameLowering::emitPrologue(), llvm::X86FrameLowering::emitPrologue(), llvm::PPCFrameLowering::emitPrologue(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::fitsConstReadLimitations(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::ARMAsmBackendDarwin::generateCompactUnwindEncoding(), llvm::RegionBase< RegionTr >::getBBNode(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), llvm::RegionBase< RegionTr >::getEnteringBlock(), llvm::LoopBase< N, M >::getExitBlocks(), llvm::LoopBase< N, M >::getExitEdges(), llvm::RegionBase< RegionTr >::getExitingBlock(), llvm::LoopBase< N, M >::getExitingBlocks(), llvm::RegionBase< RegionTr >::getExpandedRegion(), getHexagonRegisterPair(), llvm::LoopBase< N, M >::getLoopLatch(), llvm::LoopBase< N, M >::getLoopPredecessor(), getNextRegister(), llvm::RegionBase< RegionTr >::getNode(), getPairedGPR(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::RegionBase< RegionTr >::getSubRegionNode(), llvm::AArch64TargetLowering::insertCopiesSplitCSR(), llvm::PPCTargetLowering::insertCopiesSplitCSR(), isCSRestore(), llvm::HexagonInstrInfo::isDependent(), isEvenReg(), isFPR64(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::AArch64InstrInfo::isGPRCopy(), isHighReg(), llvm::RegionBase< RegionTr >::outermostLoopInRegion(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::PPCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::X86MachineFunctionInfo::setRestoreBasePointer(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), llvm::AVRRegisterInfo::splitReg(), llvm::SIInstrInfo::usesConstantBus(), and llvm::LoopBase< N, M >::verifyLoop().

static MachineOperand* getSrcFromCopy ( MachineInstr MI,
const MachineRegisterInfo MRI,
unsigned SubReg 
)
static
static unsigned getTransformOpcode ( unsigned  Opc)
static

Definition at line 166 of file AArch64AdvSIMDScalarPass.cpp.

Referenced by isTransformable().

if ( TargetRegisterInfo::  isVirtualRegisterReg) -> getRegClass(Reg) ->hasSuperClassEq(&AArch64::GPR64RegClass)
INITIALIZE_PASS ( AArch64AdvSIMDScalar  ,
"aarch64-simd-scalar"  ,
AARCH64_ADVSIMD_NAME  ,
false  ,
false   
)
static MachineInstr* insertCopy ( const TargetInstrInfo TII,
MachineInstr MI,
unsigned  Dst,
unsigned  Src,
bool  IsKill 
)
static
static bool isFPR64 ( unsigned  Reg,
unsigned  SubReg,
const MachineRegisterInfo MRI 
)
static
static bool isTransformable ( const MachineInstr MI)
static
STATISTIC ( NumScalarInsnsUsed  ,
"Number of scalar instructions used"   
)
STATISTIC ( NumCopiesDeleted  ,
"Number of cross-class copies deleted"   
)
STATISTIC ( NumCopiesInserted  ,
"Number of cross-class copies inserted"   
)

Variable Documentation

Initial value:
{
if (SubReg)
return false
unsigned SubReg

Definition at line 107 of file AArch64AdvSIMDScalarPass.cpp.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineFunction::addLiveIn(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::rdf::DataFlowGraph::build(), llvm::calculateSpillWeightsAndHints(), canCompareBeNewValueJump(), canFoldCopy(), llvm::PPCInstrInfo::canInsertSelect(), llvm::AArch64InstrInfo::canInsertSelect(), llvm::SystemZInstrInfo::canInsertSelect(), llvm::X86InstrInfo::canInsertSelect(), llvm::X86RegisterInfo::canRealignStack(), llvm::ARMBaseRegisterInfo::canRealignStack(), llvm::ModuleSymbolTable::CollectAsmSymbols(), CombineCVTAToLocal(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::HexagonBlockRanges::computeDeadMap(), computeLiveOuts(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::WebAssemblyInstrInfo::copyPhysReg(), llvm::NVPTXInstrInfo::copyPhysReg(), llvm::AMDGPUTargetLowering::CreateLiveInRegister(), llvm::HexagonInstrInfo::createVR(), llvm::XCoreFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), doScavengeFrameVirtualRegs(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), llvm::X86FrameLowering::emitCalleeSavedFrameMoves(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::WebAssemblyFrameLowering::emitEpilogue(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::Mips16FrameLowering::emitPrologue(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::WebAssemblyFrameLowering::emitPrologue(), llvm::SystemZFrameLowering::emitPrologue(), llvm::PPCFrameLowering::emitPrologue(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::findPHICopyInsertPoint(), findScratchNonCalleeSaveRegister(), llvm::ScheduleDAGInstrs::fixupKills(), for(), forceReg(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::FunctionLoweringInfo::getCatchPadExceptionPointerVReg(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::TargetRegisterInfo::getRegAllocationHints(), llvm::SIMachineFunctionInfo::getSpilledReg(), getSrcFromCopy(), IncomingArgHandler::getStackAddress(), OutgoingArgHandler::getStackAddress(), llvm::NVPTXAsmPrinter::getVirtualRegisterName(), llvm::PerFunctionMIParsingState::getVRegInfo(), HandleVRSaveUpdate(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), hasVGPROperands(), INITIALIZE_PASS(), llvm::PPCTargetLowering::insertCopiesSplitCSR(), llvm::SIInstrInfo::insertIndirectBranch(), llvm::PPCInstrInfo::insertSelect(), llvm::AArch64InstrInfo::insertSelect(), llvm::SystemZInstrInfo::insertSelect(), llvm::X86InstrInfo::insertSelect(), isCVTAToLocalCombinationCandidate(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isSourceDefinedByImplicitDef(), isSSA(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOpWithMove(), LLVMCreateDisasmCPUFeatures(), LLVMSetDisasmOptions(), llvm::Thumb2InstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::LegalizerHelper::lower(), llvm::HexagonTargetLowering::LowerCallResult(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::BitTracker::MachineEvaluator::MachineEvaluator(), llvm::SIRegisterInfo::materializeFrameBaseRegister(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), needToReserveScavengingSpillSlots(), llvm::BranchFolder::OptimizeFunction(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::TargetInstrInfo::reassociateOps(), removeIPMBasedCompare(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::SIRegisterInfo::restoreSGPR(), llvm::InstructionSelect::runOnMachineFunction(), llvm::Legalizer::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::VirtRegMap::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::ARMInstructionSelector::select(), llvm::AArch64InstructionSelector::select(), llvm::MachineOperand::setIsDef(), llvm::MachineOperand::setReg(), llvm::CoalescerPair::setRegisters(), llvm::SIInstrInfo::shouldClusterMemOps(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), llvm::SIRegisterInfo::spillSGPR(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::Thumb2InstrInfo::storeRegToStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), unsupportedBinOp(), llvm::LiveIntervals::HMEditor::updateAllRanges(), UpdateOperandRegClass(), llvm::ARMBaseRegisterInfo::updateRegAllocHint(), llvm::SIInstrInfo::verifyInstruction(), and writeSPToMemory().

unsigned SubReg
cl::opt<bool> TransformAll("aarch64-simd-scalar-force-all", cl::desc("Force use of AdvSIMD scalar instructions everywhere"), cl::init(false), cl::Hidden)
static