56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM::LDR_POST_IMM:
59 case ARM::LDR_POST_REG:
64 case ARM::LDRB_PRE_IMM:
65 case ARM::LDRB_PRE_REG:
66 case ARM::LDRB_POST_IMM:
67 case ARM::LDRB_POST_REG:
75 case ARM::STR_PRE_IMM:
76 case ARM::STR_PRE_REG:
77 case ARM::STR_POST_IMM:
78 case ARM::STR_POST_REG:
83 case ARM::STRB_PRE_IMM:
84 case ARM::STRB_PRE_REG:
85 case ARM::STRB_POST_IMM:
86 case ARM::STRB_POST_REG:
99 if (TM.isPositionIndependent())
106 if (!TM.isPositionIndependent()) {
112 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
121 unsigned Reg = MI->getOperand(0).getReg();
124 MIB =
BuildMI(MBB, MI, DL,
get(ARM::MOV_ga_pcrel_ldr), Reg)
132 MIB =
BuildMI(MBB, MI, DL,
get(ARM::LDRi12), Reg);
134 MIB.
setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
ARMInstrInfo(const ARMSubtarget &STI)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
struct fuzzer::@269 Flags
Reg
All possible values of the reg field in the ModR/M byte.
The memory access is dereferenceable (i.e., doesn't trap).
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Instances of this class represent a single low-level machine instruction.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
unsigned getUnindexedOpcode(unsigned Opc) const override
void setOpcode(unsigned Op)
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
The memory access reads data.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
The memory access always returns the same value (or traps).
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool useMovt(const MachineFunction &MF) const
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Primary interface to the complete machine description for the target machine.
void addOperand(const MCOperand &Op)
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static MCOperand createImm(int64_t Val)