LLVM  4.0.0
HexagonBlockRanges.h
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1 //===--- HexagonBlockRanges.h -----------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 #ifndef HEXAGON_BLOCK_RANGES_H
10 #define HEXAGON_BLOCK_RANGES_H
11 
12 #include "llvm/ADT/BitVector.h"
14 #include <cassert>
15 #include <map>
16 #include <set>
17 #include <vector>
18 #include <utility>
19 
20 namespace llvm {
21 
22 class HexagonSubtarget;
23 class MachineBasicBlock;
24 class MachineFunction;
25 class MachineInstr;
26 class raw_ostream;
27 class TargetInstrInfo;
28 class TargetRegisterInfo;
29 
32 
33  struct RegisterRef {
34  unsigned Reg, Sub;
35  bool operator<(RegisterRef R) const {
36  return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
37  }
38  };
39  typedef std::set<RegisterRef> RegisterSet;
40 
41  // This is to represent an "index", which is an abstraction of a position
42  // of an instruction within a basic block.
43  class IndexType {
44  public:
45  enum : unsigned {
46  None = 0,
47  Entry = 1,
48  Exit = 2,
49  First = 11 // 10th + 1st
50  };
51 
52  IndexType() : Index(None) {}
53  IndexType(unsigned Idx) : Index(Idx) {}
54 
55  static bool isInstr(IndexType X) { return X.Index >= First; }
56 
57  operator unsigned() const;
58  bool operator== (unsigned x) const;
59  bool operator== (IndexType Idx) const;
60  bool operator!= (unsigned x) const;
61  bool operator!= (IndexType Idx) const;
63  bool operator< (unsigned Idx) const;
64  bool operator< (IndexType Idx) const;
65  bool operator<= (IndexType Idx) const;
66 
67  private:
68  bool operator> (IndexType Idx) const;
69  bool operator>= (IndexType Idx) const;
70 
71  unsigned Index;
72  };
73 
74  // A range of indices, essentially a representation of a live range.
75  // This is also used to represent "dead ranges", i.e. ranges where a
76  // register is dead.
77  class IndexRange : public std::pair<IndexType,IndexType> {
78  public:
79  IndexRange() = default;
80  IndexRange(IndexType Start, IndexType End, bool F = false, bool T = false)
81  : std::pair<IndexType,IndexType>(Start, End), Fixed(F), TiedEnd(T) {}
82 
83  IndexType start() const { return first; }
84  IndexType end() const { return second; }
85 
86  bool operator< (const IndexRange &A) const {
87  return start() < A.start();
88  }
89 
90  bool overlaps(const IndexRange &A) const;
91  bool contains(const IndexRange &A) const;
92  void merge(const IndexRange &A);
93 
94  bool Fixed = false; // Can be renamed? "Fixed" means "no".
95  bool TiedEnd = false; // The end is not a use, but a dead def tied to a use.
96 
97  private:
98  void setStart(const IndexType &S) { first = S; }
99  void setEnd(const IndexType &E) { second = E; }
100  };
101 
102  // A list of index ranges. This represents liveness of a register
103  // in a basic block.
104  class RangeList : public std::vector<IndexRange> {
105  public:
106  void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd) {
107  push_back(IndexRange(Start, End, Fixed, TiedEnd));
108  }
109  void add(const IndexRange &Range) {
110  push_back(Range);
111  }
112 
113  void include(const RangeList &RL);
114  void unionize(bool MergeAdjacent = false);
115  void subtract(const IndexRange &Range);
116 
117  private:
118  void addsub(const IndexRange &A, const IndexRange &B);
119  };
120 
122  public:
124 
125  MachineInstr *getInstr(IndexType Idx) const;
127  MachineBasicBlock &getBlock() const { return Block; }
128  IndexType getPrevIndex(IndexType Idx) const;
129  IndexType getNextIndex(IndexType Idx) const;
130  void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI);
131 
132  friend raw_ostream &operator<< (raw_ostream &OS, const InstrIndexMap &Map);
133 
135 
136  private:
137  MachineBasicBlock &Block;
138  std::map<IndexType,MachineInstr*> Map;
139  };
140 
141  typedef std::map<RegisterRef,RangeList> RegToRangeMap;
145  const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
146 
147  struct PrintRangeMap {
149  : Map(M), TRI(I) {}
150 
151  friend raw_ostream &operator<< (raw_ostream &OS, const PrintRangeMap &P);
152 
153  private:
154  const RegToRangeMap &Map;
155  const TargetRegisterInfo &TRI;
156  };
157 
158 private:
159  RegisterSet getLiveIns(const MachineBasicBlock &B,
160  const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
161 
162  void computeInitialLiveRanges(InstrIndexMap &IndexMap,
163  RegToRangeMap &LiveMap);
164 
165  MachineFunction &MF;
166  const HexagonSubtarget &HST;
167  const TargetInstrInfo &TII;
168  const TargetRegisterInfo &TRI;
169  BitVector Reserved;
170 };
171 
172 inline HexagonBlockRanges::IndexType::operator unsigned() const {
173  assert(Index >= First);
174  return Index;
175 }
176 
177 inline bool HexagonBlockRanges::IndexType::operator== (unsigned x) const {
178  return Index == x;
179 }
180 
182  return Index == Idx.Index;
183 }
184 
185 inline bool HexagonBlockRanges::IndexType::operator!= (unsigned x) const {
186  return Index != x;
187 }
188 
190  return Index != Idx.Index;
191 }
192 
193 inline
195  assert(Index != None);
196  assert(Index != Exit);
197  if (Index == Entry)
198  Index = First;
199  else
200  ++Index;
201  return *this;
202 }
203 
204 inline bool HexagonBlockRanges::IndexType::operator< (unsigned Idx) const {
205  return operator< (IndexType(Idx));
206 }
207 
209  // !(x < x).
210  if (Index == Idx.Index)
211  return false;
212  // !(None < x) for all x.
213  // !(x < None) for all x.
214  if (Index == None || Idx.Index == None)
215  return false;
216  // !(Exit < x) for all x.
217  // !(x < Entry) for all x.
218  if (Index == Exit || Idx.Index == Entry)
219  return false;
220  // Entry < x for all x != Entry.
221  // x < Exit for all x != Exit.
222  if (Index == Entry || Idx.Index == Exit)
223  return true;
224 
225  return Index < Idx.Index;
226 }
227 
229  return operator==(Idx) || operator<(Idx);
230 }
231 
241 
242 } // end namespace llvm
243 
244 #endif // HEXAGON_BLOCK_RANGES_H
bool operator<(unsigned Idx) const
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
void add(const IndexRange &Range)
bool operator<(RegisterRef R) const
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
std::set< RegisterRef > RegisterSet
bool overlaps(const IndexRange &A) const
MachineBasicBlock & getBlock() const
#define F(x, y, z)
Definition: MD5.cpp:51
IndexType getNextIndex(IndexType Idx) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
TargetInstrInfo - Interface to description of machine instruction set.
#define P(N)
MachineInstr * getInstr(IndexType Idx) const
unsigned const MachineRegisterInfo * MRI
bool operator<(const IndexRange &A) const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
static const unsigned End
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void subtract(const IndexRange &Range)
IndexRange(IndexType Start, IndexType End, bool F=false, bool T=false)
bool operator<=(IndexType Idx) const
HexagonBlockRanges(MachineFunction &MF)
PrintRangeMap(const RegToRangeMap &M, const TargetRegisterInfo &I)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
IndexType getPrevIndex(IndexType Idx) const
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool contains(const IndexRange &A) const
RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap)
std::map< RegisterRef, RangeList > RegToRangeMap
IndexType getIndex(MachineInstr *MI) const
#define I(x, y, z)
Definition: MD5.cpp:54
friend raw_ostream & operator<<(raw_ostream &OS, const InstrIndexMap &Map)
friend raw_ostream & operator<<(raw_ostream &OS, const PrintRangeMap &P)
RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap)
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1726
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:326
void unionize(bool MergeAdjacent=false)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1722
void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI)
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
Statically lint checks LLVM IR
Definition: Lint.cpp:192