LLVM  4.0.0
Mips16InstrInfo.cpp
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1 //===-- Mips16InstrInfo.cpp - Mips16 Instruction Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 #include "Mips16InstrInfo.h"
15 #include "MipsMachineFunction.h"
16 #include "MipsTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/Support/Debug.h"
26 #include <cctype>
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "mips16-instrinfo"
31 
33  : MipsInstrInfo(STI, Mips::Bimm16), RI() {}
34 
36  return RI;
37 }
38 
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
45  int &FrameIndex) const {
46  return 0;
47 }
48 
49 /// isStoreToStackSlot - If the specified machine instruction is a direct
50 /// store to a stack slot, return the virtual or physical register number of
51 /// the source reg along with the FrameIndex of the loaded stack slot. If
52 /// not, return 0. This predicate must return 0 if the instruction has
53 /// any side effects other than storing to the stack slot.
55  int &FrameIndex) const {
56  return 0;
57 }
58 
61  const DebugLoc &DL, unsigned DestReg,
62  unsigned SrcReg, bool KillSrc) const {
63  unsigned Opc = 0;
64 
65  if (Mips::CPU16RegsRegClass.contains(DestReg) &&
66  Mips::GPR32RegClass.contains(SrcReg))
67  Opc = Mips::MoveR3216;
68  else if (Mips::GPR32RegClass.contains(DestReg) &&
69  Mips::CPU16RegsRegClass.contains(SrcReg))
70  Opc = Mips::Move32R16;
71  else if ((SrcReg == Mips::HI0) &&
72  (Mips::CPU16RegsRegClass.contains(DestReg)))
73  Opc = Mips::Mfhi16, SrcReg = 0;
74 
75  else if ((SrcReg == Mips::LO0) &&
76  (Mips::CPU16RegsRegClass.contains(DestReg)))
77  Opc = Mips::Mflo16, SrcReg = 0;
78 
79 
80  assert(Opc && "Cannot copy registers");
81 
82  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
83 
84  if (DestReg)
85  MIB.addReg(DestReg, RegState::Define);
86 
87  if (SrcReg)
88  MIB.addReg(SrcReg, getKillRegState(KillSrc));
89 }
90 
93  unsigned SrcReg, bool isKill, int FI,
94  const TargetRegisterClass *RC,
95  const TargetRegisterInfo *TRI,
96  int64_t Offset) const {
97  DebugLoc DL;
98  if (I != MBB.end()) DL = I->getDebugLoc();
100  unsigned Opc = 0;
101  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
102  Opc = Mips::SwRxSpImmX16;
103  assert(Opc && "Register class not handled!");
104  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
105  addFrameIndex(FI).addImm(Offset)
106  .addMemOperand(MMO);
107 }
108 
111  unsigned DestReg, int FI,
112  const TargetRegisterClass *RC,
113  const TargetRegisterInfo *TRI,
114  int64_t Offset) const {
115  DebugLoc DL;
116  if (I != MBB.end()) DL = I->getDebugLoc();
118  unsigned Opc = 0;
119 
120  if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
121  Opc = Mips::LwRxSpImmX16;
122  assert(Opc && "Register class not handled!");
123  BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
124  .addMemOperand(MMO);
125 }
126 
129  switch (MI.getDesc().getOpcode()) {
130  default:
131  return false;
132  case Mips::RetRA16:
133  ExpandRetRA16(MBB, MI, Mips::JrcRa16);
134  break;
135  }
136 
137  MBB.erase(MI.getIterator());
138  return true;
139 }
140 
141 /// GetOppositeBranchOpc - Return the inverse of the specified
142 /// opcode, e.g. turning BEQ to BNE.
143 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
144  switch (Opc) {
145  case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
146  case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
147  case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
148  case Mips::BnezRxImm16: return Mips::BeqzRxImm16;
149  case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
150  case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
151  case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
152  case Mips::Btnez16: return Mips::Bteqz16;
153  case Mips::BtnezX16: return Mips::BteqzX16;
154  case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
155  case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
156  case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
157  case Mips::Bteqz16: return Mips::Btnez16;
158  case Mips::BteqzX16: return Mips::BtnezX16;
159  case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
160  case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
161  case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
162  case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
163  case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
164  case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
165  }
166  llvm_unreachable("Illegal opcode!");
167 }
168 
170  const std::vector<CalleeSavedInfo> &CSI,
171  unsigned Flags = 0) {
172  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
173  // Add the callee-saved register as live-in. Do not add if the register is
174  // RA and return address is taken, because it has already been added in
175  // method MipsTargetLowering::lowerRETURNADDR.
176  // It's killed at the spill, unless the register is RA and return address
177  // is taken.
178  unsigned Reg = CSI[e-i-1].getReg();
179  switch (Reg) {
180  case Mips::RA:
181  case Mips::S0:
182  case Mips::S1:
183  MIB.addReg(Reg, Flags);
184  break;
185  case Mips::S2:
186  break;
187  default:
188  llvm_unreachable("unexpected mips16 callee saved register");
189 
190  }
191  }
192 }
193 // Adjust SP by FrameSize bytes. Save RA, S0, S1
194 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize,
197  DebugLoc DL;
198  MachineFunction &MF = *MBB.getParent();
199  MachineFrameInfo &MFI = MF.getFrameInfo();
200  const BitVector Reserved = RI.getReservedRegs(MF);
201  bool SaveS2 = Reserved[Mips::S2];
203  unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16;
204  MIB = BuildMI(MBB, I, DL, get(Opc));
205  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
206  addSaveRestoreRegs(MIB, CSI);
207  if (SaveS2)
208  MIB.addReg(Mips::S2);
209  if (isUInt<11>(FrameSize))
210  MIB.addImm(FrameSize);
211  else {
212  int Base = 2040; // should create template function like isUInt that
213  // returns largest possible n bit unsigned integer
214  int64_t Remainder = FrameSize - Base;
215  MIB.addImm(Base);
216  if (isInt<16>(-Remainder))
217  BuildAddiuSpImm(MBB, I, -Remainder);
218  else
219  adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
220  }
221 }
222 
223 // Adjust SP by FrameSize bytes. Restore RA, S0, S1
224 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize,
227  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
228  MachineFunction *MF = MBB.getParent();
229  MachineFrameInfo &MFI = MF->getFrameInfo();
230  const BitVector Reserved = RI.getReservedRegs(*MF);
231  bool SaveS2 = Reserved[Mips::S2];
233  unsigned Opc = ((FrameSize <= 128) && !SaveS2)?
234  Mips::Restore16:Mips::RestoreX16;
235 
236  if (!isUInt<11>(FrameSize)) {
237  unsigned Base = 2040;
238  int64_t Remainder = FrameSize - Base;
239  FrameSize = Base; // should create template function like isUInt that
240  // returns largest possible n bit unsigned integer
241 
242  if (isInt<16>(Remainder))
243  BuildAddiuSpImm(MBB, I, Remainder);
244  else
245  adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1);
246  }
247  MIB = BuildMI(MBB, I, DL, get(Opc));
248  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
250  if (SaveS2)
251  MIB.addReg(Mips::S2, RegState::Define);
252  MIB.addImm(FrameSize);
253 }
254 
255 // Adjust SP by Amount bytes where bytes can be up to 32bit number.
256 // This can only be called at times that we know that there is at least one free
257 // register.
258 // This is clearly safe at prologue and epilogue.
259 //
260 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount,
263  unsigned Reg1, unsigned Reg2) const {
264  DebugLoc DL;
265  //
266  // li reg1, constant
267  // move reg2, sp
268  // add reg1, reg1, reg2
269  // move sp, reg1
270  //
271  //
272  MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
273  MIB1.addImm(Amount).addImm(-1);
274  MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
275  MIB2.addReg(Mips::SP, RegState::Kill);
276  MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
277  MIB3.addReg(Reg1);
278  MIB3.addReg(Reg2, RegState::Kill);
279  MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
280  Mips::SP);
281  MIB4.addReg(Reg1, RegState::Kill);
282 }
283 
284 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
285  unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
286  MachineBasicBlock::iterator I) const {
287  llvm_unreachable("adjust stack pointer amount exceeded");
288 }
289 
290 /// Adjust SP by Amount bytes.
291 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
292  MachineBasicBlock &MBB,
293  MachineBasicBlock::iterator I) const {
294  if (Amount == 0)
295  return;
296 
297  if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
298  BuildAddiuSpImm(MBB, I, Amount);
299  else
300  adjustStackPtrBigUnrestricted(SP, Amount, MBB, I);
301 }
302 
303 /// This function generates the sequence of instructions needed to get the
304 /// result of adding register REG and immediate IMM.
305 unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
306  MachineBasicBlock &MBB,
308  const DebugLoc &DL,
309  unsigned &NewImm) const {
310  //
311  // given original instruction is:
312  // Instr rx, T[offset] where offset is too big.
313  //
314  // lo = offset & 0xFFFF
315  // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF;
316  //
317  // let T = temporary register
318  // li T, hi
319  // shl T, 16
320  // add T, Rx, T
321  //
322  RegScavenger rs;
323  int32_t lo = Imm & 0xFFFF;
324  NewImm = lo;
325  int Reg =0;
326  int SpReg = 0;
327 
328  rs.enterBasicBlock(MBB);
329  rs.forward(II);
330  //
331  // We need to know which registers can be used, in the case where there
332  // are not enough free registers. We exclude all registers that
333  // are used in the instruction that we are helping.
334  // // Consider all allocatable registers in the register class initially
335  BitVector Candidates =
336  RI.getAllocatableSet
337  (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
338  // Exclude all the registers being used by the instruction.
339  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
340  MachineOperand &MO = II->getOperand(i);
341  if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
343  Candidates.reset(MO.getReg());
344  }
345 
346  // If the same register was used and defined in an instruction, then
347  // it will not be in the list of candidates.
348  //
349  // we need to analyze the instruction that we are helping.
350  // we need to know if it defines register x but register x is not
351  // present as an operand of the instruction. this tells
352  // whether the register is live before the instruction. if it's not
353  // then we don't need to save it in case there are no free registers.
354  int DefReg = 0;
355  for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
356  MachineOperand &MO = II->getOperand(i);
357  if (MO.isReg() && MO.isDef()) {
358  DefReg = MO.getReg();
359  break;
360  }
361  }
362 
363  BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass);
364  Available &= Candidates;
365  //
366  // we use T0 for the first register, if we need to save something away.
367  // we use T1 for the second register, if we need to save something away.
368  //
369  unsigned FirstRegSaved =0, SecondRegSaved=0;
370  unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0;
371 
372  Reg = Available.find_first();
373 
374  if (Reg == -1) {
375  Reg = Candidates.find_first();
376  Candidates.reset(Reg);
377  if (DefReg != Reg) {
378  FirstRegSaved = Reg;
379  FirstRegSavedTo = Mips::T0;
380  copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true);
381  }
382  }
383  else
384  Available.reset(Reg);
385  BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
386  NewImm = 0;
387  if (FrameReg == Mips::SP) {
388  SpReg = Available.find_first();
389  if (SpReg == -1) {
390  SpReg = Candidates.find_first();
391  // Candidates.reset(SpReg); // not really needed
392  if (DefReg!= SpReg) {
393  SecondRegSaved = SpReg;
394  SecondRegSavedTo = Mips::T1;
395  }
396  if (SecondRegSaved)
397  copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true);
398  }
399  else
400  Available.reset(SpReg);
401  copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false);
402  BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
403  .addReg(Reg);
404  }
405  else
406  BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
407  .addReg(Reg, RegState::Kill);
408  if (FirstRegSaved || SecondRegSaved) {
409  II = std::next(II);
410  if (FirstRegSaved)
411  copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true);
412  if (SecondRegSaved)
413  copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true);
414  }
415  return Reg;
416 }
417 
418 unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
419  return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
420  Opc == Mips::Bimm16 ||
421  Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 ||
422  Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 ||
423  Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
424  Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
425  Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
426  Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
427  Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
428  Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
429  Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
430  Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
431 }
432 
433 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
435  unsigned Opc) const {
436  BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
437 }
438 
439 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
440  if (validSpImm8(Imm))
441  return get(Mips::AddiuSpImm16);
442  else
443  return get(Mips::AddiuSpImmX16);
444 }
445 
447  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
448  DebugLoc DL;
449  BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
450 }
451 
453  return new Mips16InstrInfo(STI);
454 }
455 
456 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
457  int64_t Amount) {
458  switch (Opcode) {
459  case Mips::LbRxRyOffMemX16:
460  case Mips::LbuRxRyOffMemX16:
461  case Mips::LhRxRyOffMemX16:
462  case Mips::LhuRxRyOffMemX16:
463  case Mips::SbRxRyOffMemX16:
464  case Mips::ShRxRyOffMemX16:
465  case Mips::LwRxRyOffMemX16:
466  case Mips::SwRxRyOffMemX16:
467  case Mips::SwRxSpImmX16:
468  case Mips::LwRxSpImmX16:
469  return isInt<16>(Amount);
470  case Mips::AddiuRxRyOffMemX16:
471  if ((Reg == Mips::PC) || (Reg == Mips::SP))
472  return isInt<16>(Amount);
473  return isInt<15>(Amount);
474  }
475  llvm_unreachable("unexpected Opcode in validImmediate");
476 }
477 
478 /// Measure the specified inline asm to determine an approximation of its
479 /// length.
480 /// Comments (which run till the next SeparatorString or newline) do not
481 /// count as an instruction.
482 /// Any other non-whitespace text is considered an instruction, with
483 /// multiple instructions separated by SeparatorString or newlines.
484 /// Variable-length instructions are not handled here; this function
485 /// may be overloaded in the target code to do that.
486 /// We implement the special case of the .space directive taking only an
487 /// integer argument, which is the size in bytes. This is used for creating
488 /// inline code spacing for testing purposes using inline assembly.
489 ///
490 unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str,
491  const MCAsmInfo &MAI) const {
492 
493  // Count the number of instructions in the asm.
494  bool atInsnStart = true;
495  unsigned Length = 0;
496  for (; *Str; ++Str) {
497  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
498  strlen(MAI.getSeparatorString())) == 0)
499  atInsnStart = true;
500  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
501  if (strncmp(Str, ".space", 6)==0) {
502  char *EStr; int Sz;
503  Sz = strtol(Str+6, &EStr, 10);
504  while (isspace(*EStr)) ++EStr;
505  if (*EStr=='\0') {
506  DEBUG(dbgs() << "parsed .space " << Sz << '\n');
507  return Sz;
508  }
509  }
510  Length += MAI.getMaxInstLength();
511  atInsnStart = false;
512  }
513  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
514  MAI.getCommentString().size()) == 0)
515  atInsnStart = false;
516  }
517 
518  return Length;
519 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:157
size_t i
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
A debug info location.
Definition: DebugLoc.h:34
return AArch64::GPR64RegClass contains(Reg)
static void addSaveRestoreRegs(MachineInstrBuilder &MIB, const std::vector< CalleeSavedInfo > &CSI, unsigned Flags=0)
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
StringRef getCommentString() const
Definition: MCAsmInfo.h:471
A description of a memory reference used in the backend.
struct fuzzer::@269 Flags
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void forward()
Move the internal MBB iterator and update register states.
MachineBasicBlock * MBB
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
BitVector getReservedRegs(const MachineFunction &MF) const override
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
unsigned getKillRegState(bool B)
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
BitVector & reset()
Definition: BitVector.h:260
uint32_t Offset
self_iterator getIterator()
Definition: ilist_node.h:81
bool expandPostRAPseudo(MachineInstr &MI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool validSpImm8(int offset)
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
The memory access writes data.
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
MachineOperand class - Representation of each machine instruction operand.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
The memory access reads data.
Representation of each machine instruction.
Definition: MachineInstr.h:52
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
const char * getSeparatorString() const
Definition: MCAsmInfo.h:465
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
Mips16InstrInfo(const MipsSubtarget &STI)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getMaxInstLength() const
Definition: MCAsmInfo.h:462
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:125
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
#define T1
char * PC