LLVM  4.0.0
TwoAddressInstructionPass.cpp
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1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
12 // from:
13 //
14 // A = B op C
15 //
16 // to:
17 //
18 // A = B
19 // A op= C
20 //
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
23 // virtual registers.
24 //
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
27 //
28 //===----------------------------------------------------------------------===//
29 
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
41 #include "llvm/CodeGen/Passes.h"
42 #include "llvm/IR/Function.h"
45 #include "llvm/Support/Debug.h"
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "twoaddrinstr"
56 
57 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
58 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
59 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
60 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
61 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
62 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
63 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
64 
65 // Temporary flag to disable rescheduling.
66 static cl::opt<bool>
67 EnableRescheduling("twoaddr-reschedule",
68  cl::desc("Coalesce copies by rescheduling (default=true)"),
69  cl::init(true), cl::Hidden);
70 
71 namespace {
72 class TwoAddressInstructionPass : public MachineFunctionPass {
73  MachineFunction *MF;
74  const TargetInstrInfo *TII;
75  const TargetRegisterInfo *TRI;
76  const InstrItineraryData *InstrItins;
78  LiveVariables *LV;
79  LiveIntervals *LIS;
80  AliasAnalysis *AA;
81  CodeGenOpt::Level OptLevel;
82 
83  // The current basic block being processed.
85 
86  // Keep track the distance of a MI from the start of the current basic block.
88 
89  // Set of already processed instructions in the current block.
91 
92  // A map from virtual registers to physical registers which are likely targets
93  // to be coalesced to due to copies from physical registers to virtual
94  // registers. e.g. v1024 = move r0.
96 
97  // A map from virtual registers to physical registers which are likely targets
98  // to be coalesced to due to copies to physical registers from virtual
99  // registers. e.g. r1 = move v1024.
101 
102  bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
104 
105  bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
106 
107  bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
108 
109  bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
110  MachineInstr *MI, unsigned Dist);
111 
112  bool commuteInstruction(MachineInstr *MI, unsigned DstIdx,
113  unsigned RegBIdx, unsigned RegCIdx, unsigned Dist);
114 
115  bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
116 
117  bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
119  unsigned RegA, unsigned RegB, unsigned Dist);
120 
121  bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
122 
123  bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
125  unsigned Reg);
126  bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
128  unsigned Reg);
129 
130  bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
132  unsigned SrcIdx, unsigned DstIdx,
133  unsigned Dist, bool shouldOnlyCommute);
134 
135  bool tryInstructionCommute(MachineInstr *MI,
136  unsigned DstOpIdx,
137  unsigned BaseOpIdx,
138  bool BaseOpKilled,
139  unsigned Dist);
140  void scanUses(unsigned DstReg);
141 
142  void processCopy(MachineInstr *MI);
143 
144  typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
145  typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
146  bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
147  void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
148  void eliminateRegSequence(MachineBasicBlock::iterator&);
149 
150 public:
151  static char ID; // Pass identification, replacement for typeid
152  TwoAddressInstructionPass() : MachineFunctionPass(ID) {
154  }
155 
156  void getAnalysisUsage(AnalysisUsage &AU) const override {
157  AU.setPreservesCFG();
166  }
167 
168  /// Pass entry point.
169  bool runOnMachineFunction(MachineFunction&) override;
170 };
171 } // end anonymous namespace
172 
174 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
175  "Two-Address instruction pass", false, false)
177 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
178  "Two-Address instruction pass", false, false)
179 
180 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
181 
182 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
183 
184 /// A two-address instruction has been converted to a three-address instruction
185 /// to avoid clobbering a register. Try to sink it past the instruction that
186 /// would kill the above mentioned register to reduce register pressure.
187 bool TwoAddressInstructionPass::
188 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
189  MachineBasicBlock::iterator OldPos) {
190  // FIXME: Shouldn't we be trying to do this before we three-addressify the
191  // instruction? After this transformation is done, we no longer need
192  // the instruction to be in three-address form.
193 
194  // Check if it's safe to move this instruction.
195  bool SeenStore = true; // Be conservative.
196  if (!MI->isSafeToMove(AA, SeenStore))
197  return false;
198 
199  unsigned DefReg = 0;
200  SmallSet<unsigned, 4> UseRegs;
201 
202  for (const MachineOperand &MO : MI->operands()) {
203  if (!MO.isReg())
204  continue;
205  unsigned MOReg = MO.getReg();
206  if (!MOReg)
207  continue;
208  if (MO.isUse() && MOReg != SavedReg)
209  UseRegs.insert(MO.getReg());
210  if (!MO.isDef())
211  continue;
212  if (MO.isImplicit())
213  // Don't try to move it if it implicitly defines a register.
214  return false;
215  if (DefReg)
216  // For now, don't move any instructions that define multiple registers.
217  return false;
218  DefReg = MO.getReg();
219  }
220 
221  // Find the instruction that kills SavedReg.
222  MachineInstr *KillMI = nullptr;
223  if (LIS) {
224  LiveInterval &LI = LIS->getInterval(SavedReg);
225  assert(LI.end() != LI.begin() &&
226  "Reg should not have empty live interval.");
227 
228  SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
229  LiveInterval::const_iterator I = LI.find(MBBEndIdx);
230  if (I != LI.end() && I->start < MBBEndIdx)
231  return false;
232 
233  --I;
234  KillMI = LIS->getInstructionFromIndex(I->end);
235  }
236  if (!KillMI) {
237  for (MachineOperand &UseMO : MRI->use_nodbg_operands(SavedReg)) {
238  if (!UseMO.isKill())
239  continue;
240  KillMI = UseMO.getParent();
241  break;
242  }
243  }
244 
245  // If we find the instruction that kills SavedReg, and it is in an
246  // appropriate location, we can try to sink the current instruction
247  // past it.
248  if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
249  MachineBasicBlock::iterator(KillMI) == OldPos || KillMI->isTerminator())
250  return false;
251 
252  // If any of the definitions are used by another instruction between the
253  // position and the kill use, then it's not safe to sink it.
254  //
255  // FIXME: This can be sped up if there is an easy way to query whether an
256  // instruction is before or after another instruction. Then we can use
257  // MachineRegisterInfo def / use instead.
258  MachineOperand *KillMO = nullptr;
259  MachineBasicBlock::iterator KillPos = KillMI;
260  ++KillPos;
261 
262  unsigned NumVisited = 0;
263  for (MachineInstr &OtherMI : llvm::make_range(std::next(OldPos), KillPos)) {
264  // DBG_VALUE cannot be counted against the limit.
265  if (OtherMI.isDebugValue())
266  continue;
267  if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
268  return false;
269  ++NumVisited;
270  for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) {
271  MachineOperand &MO = OtherMI.getOperand(i);
272  if (!MO.isReg())
273  continue;
274  unsigned MOReg = MO.getReg();
275  if (!MOReg)
276  continue;
277  if (DefReg == MOReg)
278  return false;
279 
280  if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) {
281  if (&OtherMI == KillMI && MOReg == SavedReg)
282  // Save the operand that kills the register. We want to unset the kill
283  // marker if we can sink MI past it.
284  KillMO = &MO;
285  else if (UseRegs.count(MOReg))
286  // One of the uses is killed before the destination.
287  return false;
288  }
289  }
290  }
291  assert(KillMO && "Didn't find kill");
292 
293  if (!LIS) {
294  // Update kill and LV information.
295  KillMO->setIsKill(false);
296  KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
297  KillMO->setIsKill(true);
298 
299  if (LV)
300  LV->replaceKillInstruction(SavedReg, *KillMI, *MI);
301  }
302 
303  // Move instruction to its destination.
304  MBB->remove(MI);
305  MBB->insert(KillPos, MI);
306 
307  if (LIS)
308  LIS->handleMove(*MI);
309 
310  ++Num3AddrSunk;
311  return true;
312 }
313 
314 /// Return the MachineInstr* if it is the single def of the Reg in current BB.
316  const MachineRegisterInfo *MRI) {
317  MachineInstr *Ret = nullptr;
318  for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
319  if (DefMI.getParent() != BB || DefMI.isDebugValue())
320  continue;
321  if (!Ret)
322  Ret = &DefMI;
323  else if (Ret != &DefMI)
324  return nullptr;
325  }
326  return Ret;
327 }
328 
329 /// Check if there is a reversed copy chain from FromReg to ToReg:
330 /// %Tmp1 = copy %Tmp2;
331 /// %FromReg = copy %Tmp1;
332 /// %ToReg = add %FromReg ...
333 /// %Tmp2 = copy %ToReg;
334 /// MaxLen specifies the maximum length of the copy chain the func
335 /// can walk through.
336 bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
337  int Maxlen) {
338  unsigned TmpReg = FromReg;
339  for (int i = 0; i < Maxlen; i++) {
340  MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
341  if (!Def || !Def->isCopy())
342  return false;
343 
344  TmpReg = Def->getOperand(1).getReg();
345 
346  if (TmpReg == ToReg)
347  return true;
348  }
349  return false;
350 }
351 
352 /// Return true if there are no intervening uses between the last instruction
353 /// in the MBB that defines the specified register and the two-address
354 /// instruction which is being processed. It also returns the last def location
355 /// by reference.
356 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
357  unsigned &LastDef) {
358  LastDef = 0;
359  unsigned LastUse = Dist;
360  for (MachineOperand &MO : MRI->reg_operands(Reg)) {
361  MachineInstr *MI = MO.getParent();
362  if (MI->getParent() != MBB || MI->isDebugValue())
363  continue;
364  DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
365  if (DI == DistanceMap.end())
366  continue;
367  if (MO.isUse() && DI->second < LastUse)
368  LastUse = DI->second;
369  if (MO.isDef() && DI->second > LastDef)
370  LastDef = DI->second;
371  }
372 
373  return !(LastUse > LastDef && LastUse < Dist);
374 }
375 
376 /// Return true if the specified MI is a copy instruction or an extract_subreg
377 /// instruction. It also returns the source and destination registers and
378 /// whether they are physical registers by reference.
379 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
380  unsigned &SrcReg, unsigned &DstReg,
381  bool &IsSrcPhys, bool &IsDstPhys) {
382  SrcReg = 0;
383  DstReg = 0;
384  if (MI.isCopy()) {
385  DstReg = MI.getOperand(0).getReg();
386  SrcReg = MI.getOperand(1).getReg();
387  } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
388  DstReg = MI.getOperand(0).getReg();
389  SrcReg = MI.getOperand(2).getReg();
390  } else
391  return false;
392 
393  IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
394  IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
395  return true;
396 }
397 
398 /// Test if the given register value, which is used by the
399 /// given instruction, is killed by the given instruction.
400 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
401  LiveIntervals *LIS) {
402  if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
403  !LIS->isNotInMIMap(*MI)) {
404  // FIXME: Sometimes tryInstructionTransform() will add instructions and
405  // test whether they can be folded before keeping them. In this case it
406  // sets a kill before recursively calling tryInstructionTransform() again.
407  // If there is no interval available, we assume that this instruction is
408  // one of those. A kill flag is manually inserted on the operand so the
409  // check below will handle it.
410  LiveInterval &LI = LIS->getInterval(Reg);
411  // This is to match the kill flag version where undefs don't have kill
412  // flags.
413  if (!LI.hasAtLeastOneValue())
414  return false;
415 
416  SlotIndex useIdx = LIS->getInstructionIndex(*MI);
417  LiveInterval::const_iterator I = LI.find(useIdx);
418  assert(I != LI.end() && "Reg must be live-in to use.");
419  return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
420  }
421 
422  return MI->killsRegister(Reg);
423 }
424 
425 /// Test if the given register value, which is used by the given
426 /// instruction, is killed by the given instruction. This looks through
427 /// coalescable copies to see if the original value is potentially not killed.
428 ///
429 /// For example, in this code:
430 ///
431 /// %reg1034 = copy %reg1024
432 /// %reg1035 = copy %reg1025<kill>
433 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
434 ///
435 /// %reg1034 is not considered to be killed, since it is copied from a
436 /// register which is not killed. Treating it as not killed lets the
437 /// normal heuristics commute the (two-address) add, which lets
438 /// coalescing eliminate the extra copy.
439 ///
440 /// If allowFalsePositives is true then likely kills are treated as kills even
441 /// if it can't be proven that they are kills.
442 static bool isKilled(MachineInstr &MI, unsigned Reg,
443  const MachineRegisterInfo *MRI,
444  const TargetInstrInfo *TII,
445  LiveIntervals *LIS,
446  bool allowFalsePositives) {
447  MachineInstr *DefMI = &MI;
448  for (;;) {
449  // All uses of physical registers are likely to be kills.
451  (allowFalsePositives || MRI->hasOneUse(Reg)))
452  return true;
453  if (!isPlainlyKilled(DefMI, Reg, LIS))
454  return false;
456  return true;
458  // If there are multiple defs, we can't do a simple analysis, so just
459  // go with what the kill flag says.
460  if (std::next(Begin) != MRI->def_end())
461  return true;
462  DefMI = Begin->getParent();
463  bool IsSrcPhys, IsDstPhys;
464  unsigned SrcReg, DstReg;
465  // If the def is something other than a copy, then it isn't going to
466  // be coalesced, so follow the kill flag.
467  if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
468  return true;
469  Reg = SrcReg;
470  }
471 }
472 
473 /// Return true if the specified MI uses the specified register as a two-address
474 /// use. If so, return the destination register by reference.
475 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
476  for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
477  const MachineOperand &MO = MI.getOperand(i);
478  if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
479  continue;
480  unsigned ti;
481  if (MI.isRegTiedToDefOperand(i, &ti)) {
482  DstReg = MI.getOperand(ti).getReg();
483  return true;
484  }
485  }
486  return false;
487 }
488 
489 /// Given a register, if has a single in-basic block use, return the use
490 /// instruction if it's a copy or a two-address use.
491 static
494  const TargetInstrInfo *TII,
495  bool &IsCopy,
496  unsigned &DstReg, bool &IsDstPhys) {
497  if (!MRI->hasOneNonDBGUse(Reg))
498  // None or more than one use.
499  return nullptr;
501  if (UseMI.getParent() != MBB)
502  return nullptr;
503  unsigned SrcReg;
504  bool IsSrcPhys;
505  if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
506  IsCopy = true;
507  return &UseMI;
508  }
509  IsDstPhys = false;
510  if (isTwoAddrUse(UseMI, Reg, DstReg)) {
511  IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
512  return &UseMI;
513  }
514  return nullptr;
515 }
516 
517 /// Return the physical register the specified virtual register might be mapped
518 /// to.
519 static unsigned
523  if (SI == RegMap.end())
524  return 0;
525  Reg = SI->second;
526  }
528  return Reg;
529  return 0;
530 }
531 
532 /// Return true if the two registers are equal or aliased.
533 static bool
534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
535  if (RegA == RegB)
536  return true;
537  if (!RegA || !RegB)
538  return false;
539  return TRI->regsOverlap(RegA, RegB);
540 }
541 
542 // Returns true if Reg is equal or aliased to at least one register in Set.
543 static bool regOverlapsSet(const SmallVectorImpl<unsigned> &Set, unsigned Reg,
544  const TargetRegisterInfo *TRI) {
545  for (unsigned R : Set)
546  if (TRI->regsOverlap(R, Reg))
547  return true;
548 
549  return false;
550 }
551 
552 /// Return true if it's potentially profitable to commute the two-address
553 /// instruction that's being processed.
554 bool
555 TwoAddressInstructionPass::
556 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
557  MachineInstr *MI, unsigned Dist) {
558  if (OptLevel == CodeGenOpt::None)
559  return false;
560 
561  // Determine if it's profitable to commute this two address instruction. In
562  // general, we want no uses between this instruction and the definition of
563  // the two-address register.
564  // e.g.
565  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
566  // %reg1029<def> = MOV8rr %reg1028
567  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
568  // insert => %reg1030<def> = MOV8rr %reg1028
569  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
570  // In this case, it might not be possible to coalesce the second MOV8rr
571  // instruction if the first one is coalesced. So it would be profitable to
572  // commute it:
573  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
574  // %reg1029<def> = MOV8rr %reg1028
575  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
576  // insert => %reg1030<def> = MOV8rr %reg1029
577  // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
578 
579  if (!isPlainlyKilled(MI, regC, LIS))
580  return false;
581 
582  // Ok, we have something like:
583  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
584  // let's see if it's worth commuting it.
585 
586  // Look for situations like this:
587  // %reg1024<def> = MOV r1
588  // %reg1025<def> = MOV r0
589  // %reg1026<def> = ADD %reg1024, %reg1025
590  // r0 = MOV %reg1026
591  // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
592  unsigned ToRegA = getMappedReg(regA, DstRegMap);
593  if (ToRegA) {
594  unsigned FromRegB = getMappedReg(regB, SrcRegMap);
595  unsigned FromRegC = getMappedReg(regC, SrcRegMap);
596  bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
597  bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
598 
599  // Compute if any of the following are true:
600  // -RegB is not tied to a register and RegC is compatible with RegA.
601  // -RegB is tied to the wrong physical register, but RegC is.
602  // -RegB is tied to the wrong physical register, and RegC isn't tied.
603  if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
604  return true;
605  // Don't compute if any of the following are true:
606  // -RegC is not tied to a register and RegB is compatible with RegA.
607  // -RegC is tied to the wrong physical register, but RegB is.
608  // -RegC is tied to the wrong physical register, and RegB isn't tied.
609  if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
610  return false;
611  }
612 
613  // If there is a use of regC between its last def (could be livein) and this
614  // instruction, then bail.
615  unsigned LastDefC = 0;
616  if (!noUseAfterLastDef(regC, Dist, LastDefC))
617  return false;
618 
619  // If there is a use of regB between its last def (could be livein) and this
620  // instruction, then go ahead and make this transformation.
621  unsigned LastDefB = 0;
622  if (!noUseAfterLastDef(regB, Dist, LastDefB))
623  return true;
624 
625  // Look for situation like this:
626  // %reg101 = MOV %reg100
627  // %reg102 = ...
628  // %reg103 = ADD %reg102, %reg101
629  // ... = %reg103 ...
630  // %reg100 = MOV %reg103
631  // If there is a reversed copy chain from reg101 to reg103, commute the ADD
632  // to eliminate an otherwise unavoidable copy.
633  // FIXME:
634  // We can extend the logic further: If an pair of operands in an insn has
635  // been merged, the insn could be regarded as a virtual copy, and the virtual
636  // copy could also be used to construct a copy chain.
637  // To more generally minimize register copies, ideally the logic of two addr
638  // instruction pass should be integrated with register allocation pass where
639  // interference graph is available.
640  if (isRevCopyChain(regC, regA, 3))
641  return true;
642 
643  if (isRevCopyChain(regB, regA, 3))
644  return false;
645 
646  // Since there are no intervening uses for both registers, then commute
647  // if the def of regC is closer. Its live interval is shorter.
648  return LastDefB && LastDefC && LastDefC > LastDefB;
649 }
650 
651 /// Commute a two-address instruction and update the basic block, distance map,
652 /// and live variables if needed. Return true if it is successful.
653 bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI,
654  unsigned DstIdx,
655  unsigned RegBIdx,
656  unsigned RegCIdx,
657  unsigned Dist) {
658  unsigned RegC = MI->getOperand(RegCIdx).getReg();
659  DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
660  MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx);
661 
662  if (NewMI == nullptr) {
663  DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
664  return false;
665  }
666 
667  DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
668  assert(NewMI == MI &&
669  "TargetInstrInfo::commuteInstruction() should not return a new "
670  "instruction unless it was requested.");
671 
672  // Update source register map.
673  unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
674  if (FromRegC) {
675  unsigned RegA = MI->getOperand(DstIdx).getReg();
676  SrcRegMap[RegA] = FromRegC;
677  }
678 
679  return true;
680 }
681 
682 /// Return true if it is profitable to convert the given 2-address instruction
683 /// to a 3-address one.
684 bool
685 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
686  // Look for situations like this:
687  // %reg1024<def> = MOV r1
688  // %reg1025<def> = MOV r0
689  // %reg1026<def> = ADD %reg1024, %reg1025
690  // r2 = MOV %reg1026
691  // Turn ADD into a 3-address instruction to avoid a copy.
692  unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
693  if (!FromRegB)
694  return false;
695  unsigned ToRegA = getMappedReg(RegA, DstRegMap);
696  return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
697 }
698 
699 /// Convert the specified two-address instruction into a three address one.
700 /// Return true if this transformation was successful.
701 bool
702 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
704  unsigned RegA, unsigned RegB,
705  unsigned Dist) {
706  // FIXME: Why does convertToThreeAddress() need an iterator reference?
708  MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV);
709  assert(MBB->getIterator() == MFI &&
710  "convertToThreeAddress changed iterator reference");
711  if (!NewMI)
712  return false;
713 
714  DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
715  DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
716  bool Sunk = false;
717 
718  if (LIS)
719  LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
720 
721  if (NewMI->findRegisterUseOperand(RegB, false, TRI))
722  // FIXME: Temporary workaround. If the new instruction doesn't
723  // uses RegB, convertToThreeAddress must have created more
724  // then one instruction.
725  Sunk = sink3AddrInstruction(NewMI, RegB, mi);
726 
727  MBB->erase(mi); // Nuke the old inst.
728 
729  if (!Sunk) {
730  DistanceMap.insert(std::make_pair(NewMI, Dist));
731  mi = NewMI;
732  nmi = std::next(mi);
733  }
734 
735  // Update source and destination register maps.
736  SrcRegMap.erase(RegA);
737  DstRegMap.erase(RegB);
738  return true;
739 }
740 
741 /// Scan forward recursively for only uses, update maps if the use is a copy or
742 /// a two-address instruction.
743 void
744 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
745  SmallVector<unsigned, 4> VirtRegPairs;
746  bool IsDstPhys;
747  bool IsCopy = false;
748  unsigned NewReg = 0;
749  unsigned Reg = DstReg;
750  while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
751  NewReg, IsDstPhys)) {
752  if (IsCopy && !Processed.insert(UseMI).second)
753  break;
754 
756  if (DI != DistanceMap.end())
757  // Earlier in the same MBB.Reached via a back edge.
758  break;
759 
760  if (IsDstPhys) {
761  VirtRegPairs.push_back(NewReg);
762  break;
763  }
764  bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
765  if (!isNew)
766  assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
767  VirtRegPairs.push_back(NewReg);
768  Reg = NewReg;
769  }
770 
771  if (!VirtRegPairs.empty()) {
772  unsigned ToReg = VirtRegPairs.back();
773  VirtRegPairs.pop_back();
774  while (!VirtRegPairs.empty()) {
775  unsigned FromReg = VirtRegPairs.back();
776  VirtRegPairs.pop_back();
777  bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
778  if (!isNew)
779  assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
780  ToReg = FromReg;
781  }
782  bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
783  if (!isNew)
784  assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
785  }
786 }
787 
788 /// If the specified instruction is not yet processed, process it if it's a
789 /// copy. For a copy instruction, we find the physical registers the
790 /// source and destination registers might be mapped to. These are kept in
791 /// point-to maps used to determine future optimizations. e.g.
792 /// v1024 = mov r0
793 /// v1025 = mov r1
794 /// v1026 = add v1024, v1025
795 /// r1 = mov r1026
796 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
797 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
798 /// potentially joined with r1 on the output side. It's worthwhile to commute
799 /// 'add' to eliminate a copy.
800 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
801  if (Processed.count(MI))
802  return;
803 
804  bool IsSrcPhys, IsDstPhys;
805  unsigned SrcReg, DstReg;
806  if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
807  return;
808 
809  if (IsDstPhys && !IsSrcPhys)
810  DstRegMap.insert(std::make_pair(SrcReg, DstReg));
811  else if (!IsDstPhys && IsSrcPhys) {
812  bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
813  if (!isNew)
814  assert(SrcRegMap[DstReg] == SrcReg &&
815  "Can't map to two src physical registers!");
816 
817  scanUses(DstReg);
818  }
819 
820  Processed.insert(MI);
821 }
822 
823 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
824 /// consider moving the instruction below the kill instruction in order to
825 /// eliminate the need for the copy.
826 bool TwoAddressInstructionPass::
827 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
829  unsigned Reg) {
830  // Bail immediately if we don't have LV or LIS available. We use them to find
831  // kills efficiently.
832  if (!LV && !LIS)
833  return false;
834 
835  MachineInstr *MI = &*mi;
837  if (DI == DistanceMap.end())
838  // Must be created from unfolded load. Don't waste time trying this.
839  return false;
840 
841  MachineInstr *KillMI = nullptr;
842  if (LIS) {
843  LiveInterval &LI = LIS->getInterval(Reg);
844  assert(LI.end() != LI.begin() &&
845  "Reg should not have empty live interval.");
846 
847  SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
848  LiveInterval::const_iterator I = LI.find(MBBEndIdx);
849  if (I != LI.end() && I->start < MBBEndIdx)
850  return false;
851 
852  --I;
853  KillMI = LIS->getInstructionFromIndex(I->end);
854  } else {
855  KillMI = LV->getVarInfo(Reg).findKill(MBB);
856  }
857  if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
858  // Don't mess with copies, they may be coalesced later.
859  return false;
860 
861  if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
862  KillMI->isBranch() || KillMI->isTerminator())
863  // Don't move pass calls, etc.
864  return false;
865 
866  unsigned DstReg;
867  if (isTwoAddrUse(*KillMI, Reg, DstReg))
868  return false;
869 
870  bool SeenStore = true;
871  if (!MI->isSafeToMove(AA, SeenStore))
872  return false;
873 
874  if (TII->getInstrLatency(InstrItins, *MI) > 1)
875  // FIXME: Needs more sophisticated heuristics.
876  return false;
877 
881  for (const MachineOperand &MO : MI->operands()) {
882  if (!MO.isReg())
883  continue;
884  unsigned MOReg = MO.getReg();
885  if (!MOReg)
886  continue;
887  if (MO.isDef())
888  Defs.push_back(MOReg);
889  else {
890  Uses.push_back(MOReg);
891  if (MOReg != Reg && (MO.isKill() ||
892  (LIS && isPlainlyKilled(MI, MOReg, LIS))))
893  Kills.push_back(MOReg);
894  }
895  }
896 
897  // Move the copies connected to MI down as well.
899  MachineBasicBlock::iterator AfterMI = std::next(Begin);
900 
902  while (End->isCopy() &&
903  regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) {
904  Defs.push_back(End->getOperand(0).getReg());
905  ++End;
906  }
907 
908  // Check if the reschedule will not break depedencies.
909  unsigned NumVisited = 0;
910  MachineBasicBlock::iterator KillPos = KillMI;
911  ++KillPos;
912  for (MachineInstr &OtherMI : llvm::make_range(End, KillPos)) {
913  // DBG_VALUE cannot be counted against the limit.
914  if (OtherMI.isDebugValue())
915  continue;
916  if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
917  return false;
918  ++NumVisited;
919  if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
920  OtherMI.isBranch() || OtherMI.isTerminator())
921  // Don't move pass calls, etc.
922  return false;
923  for (const MachineOperand &MO : OtherMI.operands()) {
924  if (!MO.isReg())
925  continue;
926  unsigned MOReg = MO.getReg();
927  if (!MOReg)
928  continue;
929  if (MO.isDef()) {
930  if (regOverlapsSet(Uses, MOReg, TRI))
931  // Physical register use would be clobbered.
932  return false;
933  if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
934  // May clobber a physical register def.
935  // FIXME: This may be too conservative. It's ok if the instruction
936  // is sunken completely below the use.
937  return false;
938  } else {
939  if (regOverlapsSet(Defs, MOReg, TRI))
940  return false;
941  bool isKill =
942  MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
943  if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
944  regOverlapsSet(Kills, MOReg, TRI)))
945  // Don't want to extend other live ranges and update kills.
946  return false;
947  if (MOReg == Reg && !isKill)
948  // We can't schedule across a use of the register in question.
949  return false;
950  // Ensure that if this is register in question, its the kill we expect.
951  assert((MOReg != Reg || &OtherMI == KillMI) &&
952  "Found multiple kills of a register in a basic block");
953  }
954  }
955  }
956 
957  // Move debug info as well.
958  while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
959  --Begin;
960 
961  nmi = End;
962  MachineBasicBlock::iterator InsertPos = KillPos;
963  if (LIS) {
964  // We have to move the copies first so that the MBB is still well-formed
965  // when calling handleMove().
966  for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
967  auto CopyMI = MBBI++;
968  MBB->splice(InsertPos, MBB, CopyMI);
969  LIS->handleMove(*CopyMI);
970  InsertPos = CopyMI;
971  }
972  End = std::next(MachineBasicBlock::iterator(MI));
973  }
974 
975  // Copies following MI may have been moved as well.
976  MBB->splice(InsertPos, MBB, Begin, End);
977  DistanceMap.erase(DI);
978 
979  // Update live variables
980  if (LIS) {
981  LIS->handleMove(*MI);
982  } else {
983  LV->removeVirtualRegisterKilled(Reg, *KillMI);
984  LV->addVirtualRegisterKilled(Reg, *MI);
985  }
986 
987  DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
988  return true;
989 }
990 
991 /// Return true if the re-scheduling will put the given instruction too close
992 /// to the defs of its register dependencies.
993 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
994  MachineInstr *MI) {
995  for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
996  if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
997  continue;
998  if (&DefMI == MI)
999  return true; // MI is defining something KillMI uses
1000  DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
1001  if (DDI == DistanceMap.end())
1002  return true; // Below MI
1003  unsigned DefDist = DDI->second;
1004  assert(Dist > DefDist && "Visited def already?");
1005  if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
1006  return true;
1007  }
1008  return false;
1009 }
1010 
1011 /// If there is one more local instruction that reads 'Reg' and it kills 'Reg,
1012 /// consider moving the kill instruction above the current two-address
1013 /// instruction in order to eliminate the need for the copy.
1014 bool TwoAddressInstructionPass::
1015 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
1017  unsigned Reg) {
1018  // Bail immediately if we don't have LV or LIS available. We use them to find
1019  // kills efficiently.
1020  if (!LV && !LIS)
1021  return false;
1022 
1023  MachineInstr *MI = &*mi;
1025  if (DI == DistanceMap.end())
1026  // Must be created from unfolded load. Don't waste time trying this.
1027  return false;
1028 
1029  MachineInstr *KillMI = nullptr;
1030  if (LIS) {
1031  LiveInterval &LI = LIS->getInterval(Reg);
1032  assert(LI.end() != LI.begin() &&
1033  "Reg should not have empty live interval.");
1034 
1035  SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
1036  LiveInterval::const_iterator I = LI.find(MBBEndIdx);
1037  if (I != LI.end() && I->start < MBBEndIdx)
1038  return false;
1039 
1040  --I;
1041  KillMI = LIS->getInstructionFromIndex(I->end);
1042  } else {
1043  KillMI = LV->getVarInfo(Reg).findKill(MBB);
1044  }
1045  if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
1046  // Don't mess with copies, they may be coalesced later.
1047  return false;
1048 
1049  unsigned DstReg;
1050  if (isTwoAddrUse(*KillMI, Reg, DstReg))
1051  return false;
1052 
1053  bool SeenStore = true;
1054  if (!KillMI->isSafeToMove(AA, SeenStore))
1055  return false;
1056 
1057  SmallSet<unsigned, 2> Uses;
1058  SmallSet<unsigned, 2> Kills;
1059  SmallSet<unsigned, 2> Defs;
1060  SmallSet<unsigned, 2> LiveDefs;
1061  for (const MachineOperand &MO : KillMI->operands()) {
1062  if (!MO.isReg())
1063  continue;
1064  unsigned MOReg = MO.getReg();
1065  if (MO.isUse()) {
1066  if (!MOReg)
1067  continue;
1068  if (isDefTooClose(MOReg, DI->second, MI))
1069  return false;
1070  bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
1071  if (MOReg == Reg && !isKill)
1072  return false;
1073  Uses.insert(MOReg);
1074  if (isKill && MOReg != Reg)
1075  Kills.insert(MOReg);
1076  } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1077  Defs.insert(MOReg);
1078  if (!MO.isDead())
1079  LiveDefs.insert(MOReg);
1080  }
1081  }
1082 
1083  // Check if the reschedule will not break depedencies.
1084  unsigned NumVisited = 0;
1085  for (MachineInstr &OtherMI :
1087  // DBG_VALUE cannot be counted against the limit.
1088  if (OtherMI.isDebugValue())
1089  continue;
1090  if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1091  return false;
1092  ++NumVisited;
1093  if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1094  OtherMI.isBranch() || OtherMI.isTerminator())
1095  // Don't move pass calls, etc.
1096  return false;
1097  SmallVector<unsigned, 2> OtherDefs;
1098  for (const MachineOperand &MO : OtherMI.operands()) {
1099  if (!MO.isReg())
1100  continue;
1101  unsigned MOReg = MO.getReg();
1102  if (!MOReg)
1103  continue;
1104  if (MO.isUse()) {
1105  if (Defs.count(MOReg))
1106  // Moving KillMI can clobber the physical register if the def has
1107  // not been seen.
1108  return false;
1109  if (Kills.count(MOReg))
1110  // Don't want to extend other live ranges and update kills.
1111  return false;
1112  if (&OtherMI != MI && MOReg == Reg &&
1113  !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
1114  // We can't schedule across a use of the register in question.
1115  return false;
1116  } else {
1117  OtherDefs.push_back(MOReg);
1118  }
1119  }
1120 
1121  for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1122  unsigned MOReg = OtherDefs[i];
1123  if (Uses.count(MOReg))
1124  return false;
1126  LiveDefs.count(MOReg))
1127  return false;
1128  // Physical register def is seen.
1129  Defs.erase(MOReg);
1130  }
1131  }
1132 
1133  // Move the old kill above MI, don't forget to move debug info as well.
1134  MachineBasicBlock::iterator InsertPos = mi;
1135  while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
1136  --InsertPos;
1137  MachineBasicBlock::iterator From = KillMI;
1138  MachineBasicBlock::iterator To = std::next(From);
1139  while (std::prev(From)->isDebugValue())
1140  --From;
1141  MBB->splice(InsertPos, MBB, From, To);
1142 
1143  nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
1144  DistanceMap.erase(DI);
1145 
1146  // Update live variables
1147  if (LIS) {
1148  LIS->handleMove(*KillMI);
1149  } else {
1150  LV->removeVirtualRegisterKilled(Reg, *KillMI);
1151  LV->addVirtualRegisterKilled(Reg, *MI);
1152  }
1153 
1154  DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1155  return true;
1156 }
1157 
1158 /// Tries to commute the operand 'BaseOpIdx' and some other operand in the
1159 /// given machine instruction to improve opportunities for coalescing and
1160 /// elimination of a register to register copy.
1161 ///
1162 /// 'DstOpIdx' specifies the index of MI def operand.
1163 /// 'BaseOpKilled' specifies if the register associated with 'BaseOpIdx'
1164 /// operand is killed by the given instruction.
1165 /// The 'Dist' arguments provides the distance of MI from the start of the
1166 /// current basic block and it is used to determine if it is profitable
1167 /// to commute operands in the instruction.
1168 ///
1169 /// Returns true if the transformation happened. Otherwise, returns false.
1170 bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI,
1171  unsigned DstOpIdx,
1172  unsigned BaseOpIdx,
1173  bool BaseOpKilled,
1174  unsigned Dist) {
1175  if (!MI->isCommutable())
1176  return false;
1177 
1178  unsigned DstOpReg = MI->getOperand(DstOpIdx).getReg();
1179  unsigned BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1180  unsigned OpsNum = MI->getDesc().getNumOperands();
1181  unsigned OtherOpIdx = MI->getDesc().getNumDefs();
1182  for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1183  // The call of findCommutedOpIndices below only checks if BaseOpIdx
1184  // and OtherOpIdx are commutable, it does not really search for
1185  // other commutable operands and does not change the values of passed
1186  // variables.
1187  if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() ||
1188  !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
1189  continue;
1190 
1191  unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1192  bool AggressiveCommute = false;
1193 
1194  // If OtherOp dies but BaseOp does not, swap the OtherOp and BaseOp
1195  // operands. This makes the live ranges of DstOp and OtherOp joinable.
1196  bool DoCommute =
1197  !BaseOpKilled && isKilled(*MI, OtherOpReg, MRI, TII, LIS, false);
1198 
1199  if (!DoCommute &&
1200  isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
1201  DoCommute = true;
1202  AggressiveCommute = true;
1203  }
1204 
1205  // If it's profitable to commute, try to do so.
1206  if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1207  Dist)) {
1208  ++NumCommuted;
1209  if (AggressiveCommute)
1210  ++NumAggrCommuted;
1211  return true;
1212  }
1213  }
1214  return false;
1215 }
1216 
1217 /// For the case where an instruction has a single pair of tied register
1218 /// operands, attempt some transformations that may either eliminate the tied
1219 /// operands or improve the opportunities for coalescing away the register copy.
1220 /// Returns true if no copy needs to be inserted to untie mi's operands
1221 /// (either because they were untied, or because mi was rescheduled, and will
1222 /// be visited again later). If the shouldOnlyCommute flag is true, only
1223 /// instruction commutation is attempted.
1224 bool TwoAddressInstructionPass::
1225 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1227  unsigned SrcIdx, unsigned DstIdx,
1228  unsigned Dist, bool shouldOnlyCommute) {
1229  if (OptLevel == CodeGenOpt::None)
1230  return false;
1231 
1232  MachineInstr &MI = *mi;
1233  unsigned regA = MI.getOperand(DstIdx).getReg();
1234  unsigned regB = MI.getOperand(SrcIdx).getReg();
1235 
1237  "cannot make instruction into two-address form");
1238  bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1239 
1241  scanUses(regA);
1242 
1243  bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
1244 
1245  // If the instruction is convertible to 3 Addr, instead
1246  // of returning try 3 Addr transformation aggresively and
1247  // use this variable to check later. Because it might be better.
1248  // For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
1249  // instead of the following code.
1250  // addl %esi, %edi
1251  // movl %edi, %eax
1252  // ret
1253  if (Commuted && !MI.isConvertibleTo3Addr())
1254  return false;
1255 
1256  if (shouldOnlyCommute)
1257  return false;
1258 
1259  // If there is one more use of regB later in the same MBB, consider
1260  // re-schedule this MI below it.
1261  if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1262  ++NumReSchedDowns;
1263  return true;
1264  }
1265 
1266  // If we commuted, regB may have changed so we should re-sample it to avoid
1267  // confusing the three address conversion below.
1268  if (Commuted) {
1269  regB = MI.getOperand(SrcIdx).getReg();
1270  regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1271  }
1272 
1273  if (MI.isConvertibleTo3Addr()) {
1274  // This instruction is potentially convertible to a true
1275  // three-address instruction. Check if it is profitable.
1276  if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1277  // Try to convert it.
1278  if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1279  ++NumConvertedTo3Addr;
1280  return true; // Done with this instruction.
1281  }
1282  }
1283  }
1284 
1285  // Return if it is commuted but 3 addr conversion is failed.
1286  if (Commuted)
1287  return false;
1288 
1289  // If there is one more use of regB later in the same MBB, consider
1290  // re-schedule it before this MI if it's legal.
1291  if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1292  ++NumReSchedUps;
1293  return true;
1294  }
1295 
1296  // If this is an instruction with a load folded into it, try unfolding
1297  // the load, e.g. avoid this:
1298  // movq %rdx, %rcx
1299  // addq (%rax), %rcx
1300  // in favor of this:
1301  // movq (%rax), %rcx
1302  // addq %rdx, %rcx
1303  // because it's preferable to schedule a load than a register copy.
1304  if (MI.mayLoad() && !regBKilled) {
1305  // Determine if a load can be unfolded.
1306  unsigned LoadRegIndex;
1307  unsigned NewOpc =
1308  TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1309  /*UnfoldLoad=*/true,
1310  /*UnfoldStore=*/false,
1311  &LoadRegIndex);
1312  if (NewOpc != 0) {
1313  const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1314  if (UnfoldMCID.getNumDefs() == 1) {
1315  // Unfold the load.
1316  DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1317  const TargetRegisterClass *RC =
1318  TRI->getAllocatableClass(
1319  TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1320  unsigned Reg = MRI->createVirtualRegister(RC);
1322  if (!TII->unfoldMemoryOperand(*MF, MI, Reg,
1323  /*UnfoldLoad=*/true,
1324  /*UnfoldStore=*/false, NewMIs)) {
1325  DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1326  return false;
1327  }
1328  assert(NewMIs.size() == 2 &&
1329  "Unfolded a load into multiple instructions!");
1330  // The load was previously folded, so this is the only use.
1331  NewMIs[1]->addRegisterKilled(Reg, TRI);
1332 
1333  // Tentatively insert the instructions into the block so that they
1334  // look "normal" to the transformation logic.
1335  MBB->insert(mi, NewMIs[0]);
1336  MBB->insert(mi, NewMIs[1]);
1337 
1338  DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1339  << "2addr: NEW INST: " << *NewMIs[1]);
1340 
1341  // Transform the instruction, now that it no longer has a load.
1342  unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1343  unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1344  MachineBasicBlock::iterator NewMI = NewMIs[1];
1345  bool TransformResult =
1346  tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1347  (void)TransformResult;
1348  assert(!TransformResult &&
1349  "tryInstructionTransform() should return false.");
1350  if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1351  // Success, or at least we made an improvement. Keep the unfolded
1352  // instructions and discard the original.
1353  if (LV) {
1354  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1355  MachineOperand &MO = MI.getOperand(i);
1356  if (MO.isReg() &&
1358  if (MO.isUse()) {
1359  if (MO.isKill()) {
1360  if (NewMIs[0]->killsRegister(MO.getReg()))
1361  LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
1362  else {
1363  assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1364  "Kill missing after load unfold!");
1365  LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
1366  }
1367  }
1368  } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {
1369  if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1370  LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
1371  else {
1372  assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1373  "Dead flag missing after load unfold!");
1374  LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
1375  }
1376  }
1377  }
1378  }
1379  LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
1380  }
1381 
1382  SmallVector<unsigned, 4> OrigRegs;
1383  if (LIS) {
1384  for (const MachineOperand &MO : MI.operands()) {
1385  if (MO.isReg())
1386  OrigRegs.push_back(MO.getReg());
1387  }
1388  }
1389 
1390  MI.eraseFromParent();
1391 
1392  // Update LiveIntervals.
1393  if (LIS) {
1394  MachineBasicBlock::iterator Begin(NewMIs[0]);
1395  MachineBasicBlock::iterator End(NewMIs[1]);
1396  LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1397  }
1398 
1399  mi = NewMIs[1];
1400  } else {
1401  // Transforming didn't eliminate the tie and didn't lead to an
1402  // improvement. Clean up the unfolded instructions and keep the
1403  // original.
1404  DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1405  NewMIs[0]->eraseFromParent();
1406  NewMIs[1]->eraseFromParent();
1407  }
1408  }
1409  }
1410  }
1411 
1412  return false;
1413 }
1414 
1415 // Collect tied operands of MI that need to be handled.
1416 // Rewrite trivial cases immediately.
1417 // Return true if any tied operands where found, including the trivial ones.
1418 bool TwoAddressInstructionPass::
1419 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1420  const MCInstrDesc &MCID = MI->getDesc();
1421  bool AnyOps = false;
1422  unsigned NumOps = MI->getNumOperands();
1423 
1424  for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1425  unsigned DstIdx = 0;
1426  if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1427  continue;
1428  AnyOps = true;
1429  MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1430  MachineOperand &DstMO = MI->getOperand(DstIdx);
1431  unsigned SrcReg = SrcMO.getReg();
1432  unsigned DstReg = DstMO.getReg();
1433  // Tied constraint already satisfied?
1434  if (SrcReg == DstReg)
1435  continue;
1436 
1437  assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1438 
1439  // Deal with <undef> uses immediately - simply rewrite the src operand.
1440  if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1441  // Constrain the DstReg register class if required.
1443  if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1444  TRI, *MF))
1445  MRI->constrainRegClass(DstReg, RC);
1446  SrcMO.setReg(DstReg);
1447  SrcMO.setSubReg(0);
1448  DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1449  continue;
1450  }
1451  TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1452  }
1453  return AnyOps;
1454 }
1455 
1456 // Process a list of tied MI operands that all use the same source register.
1457 // The tied pairs are of the form (SrcIdx, DstIdx).
1458 void
1459 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1460  TiedPairList &TiedPairs,
1461  unsigned &Dist) {
1462  bool IsEarlyClobber = false;
1463  for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1464  const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1465  IsEarlyClobber |= DstMO.isEarlyClobber();
1466  }
1467 
1468  bool RemovedKillFlag = false;
1469  bool AllUsesCopied = true;
1470  unsigned LastCopiedReg = 0;
1471  SlotIndex LastCopyIdx;
1472  unsigned RegB = 0;
1473  unsigned SubRegB = 0;
1474  for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1475  unsigned SrcIdx = TiedPairs[tpi].first;
1476  unsigned DstIdx = TiedPairs[tpi].second;
1477 
1478  const MachineOperand &DstMO = MI->getOperand(DstIdx);
1479  unsigned RegA = DstMO.getReg();
1480 
1481  // Grab RegB from the instruction because it may have changed if the
1482  // instruction was commuted.
1483  RegB = MI->getOperand(SrcIdx).getReg();
1484  SubRegB = MI->getOperand(SrcIdx).getSubReg();
1485 
1486  if (RegA == RegB) {
1487  // The register is tied to multiple destinations (or else we would
1488  // not have continued this far), but this use of the register
1489  // already matches the tied destination. Leave it.
1490  AllUsesCopied = false;
1491  continue;
1492  }
1493  LastCopiedReg = RegA;
1494 
1496  "cannot make instruction into two-address form");
1497 
1498 #ifndef NDEBUG
1499  // First, verify that we don't have a use of "a" in the instruction
1500  // (a = b + a for example) because our transformation will not
1501  // work. This should never occur because we are in SSA form.
1502  for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1503  assert(i == DstIdx ||
1504  !MI->getOperand(i).isReg() ||
1505  MI->getOperand(i).getReg() != RegA);
1506 #endif
1507 
1508  // Emit a copy.
1509  MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1510  TII->get(TargetOpcode::COPY), RegA);
1511  // If this operand is folding a truncation, the truncation now moves to the
1512  // copy so that the register classes remain valid for the operands.
1513  MIB.addReg(RegB, 0, SubRegB);
1514  const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1515  if (SubRegB) {
1517  assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1518  SubRegB) &&
1519  "tied subregister must be a truncation");
1520  // The superreg class will not be used to constrain the subreg class.
1521  RC = nullptr;
1522  }
1523  else {
1524  assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
1525  && "tied subregister must be a truncation");
1526  }
1527  }
1528 
1529  // Update DistanceMap.
1531  --PrevMI;
1532  DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
1533  DistanceMap[MI] = ++Dist;
1534 
1535  if (LIS) {
1536  LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
1537 
1539  LiveInterval &LI = LIS->getInterval(RegA);
1540  VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1541  SlotIndex endIdx =
1542  LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
1543  LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1544  }
1545  }
1546 
1547  DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1548 
1549  MachineOperand &MO = MI->getOperand(SrcIdx);
1550  assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1551  "inconsistent operand info for 2-reg pass");
1552  if (MO.isKill()) {
1553  MO.setIsKill(false);
1554  RemovedKillFlag = true;
1555  }
1556 
1557  // Make sure regA is a legal regclass for the SrcIdx operand.
1560  MRI->constrainRegClass(RegA, RC);
1561  MO.setReg(RegA);
1562  // The getMatchingSuper asserts guarantee that the register class projected
1563  // by SubRegB is compatible with RegA with no subregister. So regardless of
1564  // whether the dest oper writes a subreg, the source oper should not.
1565  MO.setSubReg(0);
1566 
1567  // Propagate SrcRegMap.
1568  SrcRegMap[RegA] = RegB;
1569  }
1570 
1571  if (AllUsesCopied) {
1572  if (!IsEarlyClobber) {
1573  // Replace other (un-tied) uses of regB with LastCopiedReg.
1574  for (MachineOperand &MO : MI->operands()) {
1575  if (MO.isReg() && MO.getReg() == RegB &&
1576  MO.isUse()) {
1577  if (MO.isKill()) {
1578  MO.setIsKill(false);
1579  RemovedKillFlag = true;
1580  }
1581  MO.setReg(LastCopiedReg);
1582  MO.setSubReg(MO.getSubReg());
1583  }
1584  }
1585  }
1586 
1587  // Update live variables for regB.
1588  if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) {
1590  --PrevMI;
1591  LV->addVirtualRegisterKilled(RegB, *PrevMI);
1592  }
1593 
1594  // Update LiveIntervals.
1595  if (LIS) {
1596  LiveInterval &LI = LIS->getInterval(RegB);
1597  SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
1598  LiveInterval::const_iterator I = LI.find(MIIdx);
1599  assert(I != LI.end() && "RegB must be live-in to use.");
1600 
1601  SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1602  if (I->end == UseIdx)
1603  LI.removeSegment(LastCopyIdx, UseIdx);
1604  }
1605 
1606  } else if (RemovedKillFlag) {
1607  // Some tied uses of regB matched their destination registers, so
1608  // regB is still used in this instruction, but a kill flag was
1609  // removed from a different tied use of regB, so now we need to add
1610  // a kill flag to one of the remaining uses of regB.
1611  for (MachineOperand &MO : MI->operands()) {
1612  if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1613  MO.setIsKill(true);
1614  break;
1615  }
1616  }
1617  }
1618 }
1619 
1620 /// Reduce two-address instructions to two operands.
1621 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1622  MF = &Func;
1623  const TargetMachine &TM = MF->getTarget();
1624  MRI = &MF->getRegInfo();
1625  TII = MF->getSubtarget().getInstrInfo();
1626  TRI = MF->getSubtarget().getRegisterInfo();
1627  InstrItins = MF->getSubtarget().getInstrItineraryData();
1628  LV = getAnalysisIfAvailable<LiveVariables>();
1629  LIS = getAnalysisIfAvailable<LiveIntervals>();
1630  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
1631  OptLevel = TM.getOptLevel();
1632 
1633  bool MadeChange = false;
1634 
1635  DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1636  DEBUG(dbgs() << "********** Function: "
1637  << MF->getName() << '\n');
1638 
1639  // This pass takes the function out of SSA form.
1640  MRI->leaveSSA();
1641 
1642  TiedOperandMap TiedOperands;
1643  for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1644  MBBI != MBBE; ++MBBI) {
1645  MBB = &*MBBI;
1646  unsigned Dist = 0;
1647  DistanceMap.clear();
1648  SrcRegMap.clear();
1649  DstRegMap.clear();
1650  Processed.clear();
1651  for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1652  mi != me; ) {
1653  MachineBasicBlock::iterator nmi = std::next(mi);
1654  if (mi->isDebugValue()) {
1655  mi = nmi;
1656  continue;
1657  }
1658 
1659  // Expand REG_SEQUENCE instructions. This will position mi at the first
1660  // expanded instruction.
1661  if (mi->isRegSequence())
1662  eliminateRegSequence(mi);
1663 
1664  DistanceMap.insert(std::make_pair(&*mi, ++Dist));
1665 
1666  processCopy(&*mi);
1667 
1668  // First scan through all the tied register uses in this instruction
1669  // and record a list of pairs of tied operands for each register.
1670  if (!collectTiedOperands(&*mi, TiedOperands)) {
1671  mi = nmi;
1672  continue;
1673  }
1674 
1675  ++NumTwoAddressInstrs;
1676  MadeChange = true;
1677  DEBUG(dbgs() << '\t' << *mi);
1678 
1679  // If the instruction has a single pair of tied operands, try some
1680  // transformations that may either eliminate the tied operands or
1681  // improve the opportunities for coalescing away the register copy.
1682  if (TiedOperands.size() == 1) {
1684  = TiedOperands.begin()->second;
1685  if (TiedPairs.size() == 1) {
1686  unsigned SrcIdx = TiedPairs[0].first;
1687  unsigned DstIdx = TiedPairs[0].second;
1688  unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1689  unsigned DstReg = mi->getOperand(DstIdx).getReg();
1690  if (SrcReg != DstReg &&
1691  tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1692  // The tied operands have been eliminated or shifted further down
1693  // the block to ease elimination. Continue processing with 'nmi'.
1694  TiedOperands.clear();
1695  mi = nmi;
1696  continue;
1697  }
1698  }
1699  }
1700 
1701  // Now iterate over the information collected above.
1702  for (auto &TO : TiedOperands) {
1703  processTiedPairs(&*mi, TO.second, Dist);
1704  DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1705  }
1706 
1707  // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1708  if (mi->isInsertSubreg()) {
1709  // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1710  // To %reg:subidx = COPY %subreg
1711  unsigned SubIdx = mi->getOperand(3).getImm();
1712  mi->RemoveOperand(3);
1713  assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1714  mi->getOperand(0).setSubReg(SubIdx);
1715  mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1716  mi->RemoveOperand(1);
1717  mi->setDesc(TII->get(TargetOpcode::COPY));
1718  DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1719  }
1720 
1721  // Clear TiedOperands here instead of at the top of the loop
1722  // since most instructions do not have tied operands.
1723  TiedOperands.clear();
1724  mi = nmi;
1725  }
1726  }
1727 
1728  if (LIS)
1729  MF->verify(this, "After two-address instruction pass");
1730 
1731  return MadeChange;
1732 }
1733 
1734 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1735 ///
1736 /// The instruction is turned into a sequence of sub-register copies:
1737 ///
1738 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1739 ///
1740 /// Becomes:
1741 ///
1742 /// %dst:ssub0<def,undef> = COPY %v1
1743 /// %dst:ssub1<def> = COPY %v2
1744 ///
1745 void TwoAddressInstructionPass::
1746 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1747  MachineInstr &MI = *MBBI;
1748  unsigned DstReg = MI.getOperand(0).getReg();
1749  if (MI.getOperand(0).getSubReg() ||
1751  !(MI.getNumOperands() & 1)) {
1752  DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
1753  llvm_unreachable(nullptr);
1754  }
1755 
1756  SmallVector<unsigned, 4> OrigRegs;
1757  if (LIS) {
1758  OrigRegs.push_back(MI.getOperand(0).getReg());
1759  for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
1760  OrigRegs.push_back(MI.getOperand(i).getReg());
1761  }
1762 
1763  bool DefEmitted = false;
1764  for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) {
1765  MachineOperand &UseMO = MI.getOperand(i);
1766  unsigned SrcReg = UseMO.getReg();
1767  unsigned SubIdx = MI.getOperand(i+1).getImm();
1768  // Nothing needs to be inserted for <undef> operands.
1769  if (UseMO.isUndef())
1770  continue;
1771 
1772  // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1773  // might insert a COPY that uses SrcReg after is was killed.
1774  bool isKill = UseMO.isKill();
1775  if (isKill)
1776  for (unsigned j = i + 2; j < e; j += 2)
1777  if (MI.getOperand(j).getReg() == SrcReg) {
1778  MI.getOperand(j).setIsKill();
1779  UseMO.setIsKill(false);
1780  isKill = false;
1781  break;
1782  }
1783 
1784  // Insert the sub-register copy.
1785  MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
1786  TII->get(TargetOpcode::COPY))
1787  .addReg(DstReg, RegState::Define, SubIdx)
1788  .addOperand(UseMO);
1789 
1790  // The first def needs an <undef> flag because there is no live register
1791  // before it.
1792  if (!DefEmitted) {
1793  CopyMI->getOperand(0).setIsUndef(true);
1794  // Return an iterator pointing to the first inserted instr.
1795  MBBI = CopyMI;
1796  }
1797  DefEmitted = true;
1798 
1799  // Update LiveVariables' kill info.
1800  if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1801  LV->replaceKillInstruction(SrcReg, MI, *CopyMI);
1802 
1803  DEBUG(dbgs() << "Inserted: " << *CopyMI);
1804  }
1805 
1806  MachineBasicBlock::iterator EndMBBI =
1807  std::next(MachineBasicBlock::iterator(MI));
1808 
1809  if (!DefEmitted) {
1810  DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
1811  MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1812  for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j)
1813  MI.RemoveOperand(j);
1814  } else {
1815  DEBUG(dbgs() << "Eliminated: " << MI);
1816  MI.eraseFromParent();
1817  }
1818 
1819  // Udpate LiveIntervals.
1820  if (LIS)
1821  LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
1822 }
void push_back(const T &Elt)
Definition: SmallVector.h:211
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:448
STATISTIC(NumFunctions,"Total number of functions")
size_t i
static MachineInstr * getSingleDef(unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI)
Return the MachineInstr* if it is the single def of the Reg in current BB.
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:651
static unsigned getMappedReg(unsigned Reg, DenseMap< unsigned, unsigned > &RegMap)
Return the physical register the specified virtual register might be mapped to.
static bool isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass,"twoaddressinstruction","Two-Address instruction pass", false, false) INITIALIZE_PASS_END(TwoAddressInstructionPass
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:927
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
MachineInstrBundleIterator< MachineInstr > iterator
VNInfo - Value Number Information.
Definition: LiveInterval.h:45
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
bool erase(const T &V)
Definition: SmallSet.h:107
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static bool regOverlapsSet(const SmallVectorImpl< unsigned > &Set, unsigned Reg, const TargetRegisterInfo *TRI)
MCInst const & instruction(MCInst const &MCB, size_t Index)
iterator end()
Definition: LiveInterval.h:206
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
void initializeTwoAddressInstructionPassPass(PassRegistry &)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
static bool regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI)
Return true if the two registers are equal or aliased.
bool isKill() const
SlotIndexes pass.
Definition: SlotIndexes.h:323
Two Address instruction false
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MachineBasicBlock * MBB
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:819
AnalysisUsage & addPreservedID(const void *ID)
Itinerary data supplied by a subtarget to be used by a target.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
int64_t getImm() const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
Definition: SlotIndexes.h:282
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:777
bool isInsertSubreg() const
Definition: MachineInstr.h:795
bool isEarlyClobber() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
bool hasAtLeastOneValue() const
Definition: LiveInterval.h:284
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineInstrBuilder & UseMI
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Two Address instruction pass
bool isCopy() const
Definition: MachineInstr.h:807
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:80
static MachineInstr * findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys)
Given a register, if has a single in-basic block use, return the use instruction if it's a copy or a ...
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setIsKill(bool Val=true)
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:64
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
Segments::const_iterator const_iterator
Definition: LiveInterval.h:208
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:190
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys)
Return true if the specified MI is a copy instruction or an extract_subreg instruction.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
LiveInterval & getInterval(unsigned Reg)
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isSubregToReg() const
Definition: MachineInstr.h:798
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
def_iterator def_begin(unsigned RegNo) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void setSubReg(unsigned subReg)
iterator find(const KeyT &Val)
Definition: DenseMap.h:127
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:247
iterator begin()
Definition: LiveInterval.h:205
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:306
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:633
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:886
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
bool isNotInMIMap(const MachineInstr &Instr) const
isNotInMIMap - returns true if the specified machine instr has been removed or was never entered in t...
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
#define DEBUG(X)
Definition: Debug.h:100
Primary interface to the complete machine description for the target machine.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
IRTranslator LLVM IR MI
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg)
Return true if the specified MI uses the specified register as a two-address use. ...