LLVM  4.0.0
HexagonRegisterInfo.cpp
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1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "HexagonRegisterInfo.h"
16 #include "Hexagon.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
32 #include "llvm/Support/Debug.h"
38 
39 using namespace llvm;
40 
42  : HexagonGenRegisterInfo(Hexagon::R31) {}
43 
44 
46  return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
47  R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
48 }
49 
51  return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
52 }
53 
54 
55 const MCPhysReg *
57  const TargetRegisterClass *RC) const {
58  using namespace Hexagon;
59 
60  static const MCPhysReg Int32[] = {
61  R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
62  };
63  static const MCPhysReg Int64[] = {
64  D0, D1, D2, D3, D4, D5, D6, D7, 0
65  };
66  static const MCPhysReg Pred[] = {
67  P0, P1, P2, P3, 0
68  };
69  static const MCPhysReg VecSgl[] = {
70  V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
71  V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
72  V28, V29, V30, V31, 0
73  };
74  static const MCPhysReg VecDbl[] = {
75  W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
76  };
77 
78  switch (RC->getID()) {
79  case IntRegsRegClassID:
80  return Int32;
81  case DoubleRegsRegClassID:
82  return Int64;
83  case PredRegsRegClassID:
84  return Pred;
85  case VectorRegsRegClassID:
86  case VectorRegs128BRegClassID:
87  return VecSgl;
88  case VecDblRegsRegClassID:
89  case VecDblRegs128BRegClassID:
90  return VecDbl;
91  default:
92  break;
93  }
94 
95  static const MCPhysReg Empty[] = { 0 };
96 #ifndef NDEBUG
97  dbgs() << "Register class: " << getRegClassName(RC) << "\n";
98 #endif
99  llvm_unreachable("Unexpected register class");
100  return Empty;
101 }
102 
103 
104 const MCPhysReg *
106  static const MCPhysReg CalleeSavedRegsV3[] = {
107  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
108  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
109  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
110  };
111 
112  // Functions that contain a call to __builtin_eh_return also save the first 4
113  // parameter registers.
114  static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
115  Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
116  Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
117  Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
118  Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
119  };
120 
121  bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
122 
128  return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
129  }
130 
131  llvm_unreachable("Callee saved registers requested for unknown architecture "
132  "version");
133 }
134 
135 
137  const {
138  BitVector Reserved(getNumRegs());
139  Reserved.set(Hexagon::R29);
140  Reserved.set(Hexagon::R30);
141  Reserved.set(Hexagon::R31);
142  Reserved.set(Hexagon::PC);
143  Reserved.set(Hexagon::D14);
144  Reserved.set(Hexagon::D15);
145  Reserved.set(Hexagon::LC0);
146  Reserved.set(Hexagon::LC1);
147  Reserved.set(Hexagon::SA0);
148  Reserved.set(Hexagon::SA1);
149  Reserved.set(Hexagon::UGP);
150  Reserved.set(Hexagon::GP);
151  Reserved.set(Hexagon::CS0);
152  Reserved.set(Hexagon::CS1);
153  Reserved.set(Hexagon::CS);
154  Reserved.set(Hexagon::USR);
155  return Reserved;
156 }
157 
158 
160  int SPAdj, unsigned FIOp,
161  RegScavenger *RS) const {
162  //
163  // Hexagon_TODO: Do we need to enforce this for Hexagon?
164  assert(SPAdj == 0 && "Unexpected");
165 
166  MachineInstr &MI = *II;
167  MachineBasicBlock &MB = *MI.getParent();
168  MachineFunction &MF = *MB.getParent();
169  auto &HST = MF.getSubtarget<HexagonSubtarget>();
170  auto &HII = *HST.getInstrInfo();
171  auto &HFI = *HST.getFrameLowering();
172 
173  unsigned BP = 0;
174  int FI = MI.getOperand(FIOp).getIndex();
175  // Select the base pointer (BP) and calculate the actual offset from BP
176  // to the beginning of the object at index FI.
177  int Offset = HFI.getFrameIndexReference(MF, FI, BP);
178  // Add the offset from the instruction.
179  int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
180  bool IsKill = false;
181 
182  unsigned Opc = MI.getOpcode();
183  switch (Opc) {
184  case Hexagon::PS_fia:
185  MI.setDesc(HII.get(Hexagon::A2_addi));
186  MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
187  MI.RemoveOperand(FIOp+1);
188  return;
189  case Hexagon::PS_fi:
190  // Set up the instruction for updating below.
191  MI.setDesc(HII.get(Hexagon::A2_addi));
192  break;
193  }
194 
195  if (!HII.isValidOffset(Opc, RealOffset)) {
196  // If the offset is not valid, calculate the address in a temporary
197  // register and use it with offset 0.
198  auto &MRI = MF.getRegInfo();
199  unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
200  const DebugLoc &DL = MI.getDebugLoc();
201  BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
202  .addReg(BP)
203  .addImm(RealOffset);
204  BP = TmpR;
205  RealOffset = 0;
206  IsKill = true;
207  }
208 
209  MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
210  MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
211 }
212 
213 
215  return Hexagon::R31;
216 }
217 
218 
220  &MF) const {
221  const HexagonFrameLowering *TFI = getFrameLowering(MF);
222  if (TFI->hasFP(MF))
223  return getFrameRegister();
224  return getStackRegister();
225 }
226 
227 
229  return Hexagon::R30;
230 }
231 
232 
234  return Hexagon::R29;
235 }
236 
237 
239  const TargetRegisterClass *RC, unsigned GenIdx) const {
240  assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
241 
242  static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
243  static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
244 
245  switch (RC->getID()) {
246  case Hexagon::CtrRegs64RegClassID:
247  case Hexagon::DoubleRegsRegClassID:
248  return ISub[GenIdx];
249  case Hexagon::VecDblRegsRegClassID:
250  case Hexagon::VecDblRegs128BRegClassID:
251  return VSub[GenIdx];
252  }
253 
254  if (const TargetRegisterClass *SuperRC = *RC->getSuperClasses())
255  return getHexagonSubRegIndex(SuperRC, GenIdx);
256 
257  llvm_unreachable("Invalid register class");
258 }
259 
261  const {
262  return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
263 }
264 
265 
267  return Hexagon::R6;
268 }
269 
270 
271 #define GET_REGINFO_TARGET_DESC
272 #include "HexagonGenRegisterInfo.inc"
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MCPhysReg * getCallerSavedRegs(const MachineFunction *MF, const TargetRegisterClass *RC) const
BitVector & set()
Definition: BitVector.h:219
#define R4(n)
const HexagonArchEnum & getHexagonArchVersion() const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Hexagon target-specific information for each MachineFunction.
A debug info location.
Definition: DebugLoc.h:34
#define R2(n)
unsigned getHexagonSubRegIndex(const TargetRegisterClass *RC, unsigned GenIdx) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
unsigned getFirstCallerSavedNonParamReg() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
bool isEHReturnCalleeSaveReg(unsigned Reg) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
uint32_t Offset
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
#define R6(n)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool useFPForScavengingIndex(const MachineFunction &MF) const override
Returns true if the frame pointer is valid.
BitVector getReservedRegs(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const HexagonInstrInfo * getInstrInfo() const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
IRTranslator LLVM IR MI
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool isCalleeSaveReg(unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
char * PC