LLVM  4.0.0
RISCVMCCodeEmitter.cpp
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1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RISCVMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/Statistic.h"
16 #include "llvm/MC/MCCodeEmitter.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/MC/MCAsmInfo.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "mccodeemitter"
29 
30 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
31 
32 namespace {
33 class RISCVMCCodeEmitter : public MCCodeEmitter {
34  RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
35  void operator=(const RISCVMCCodeEmitter &) = delete;
36  MCContext &Ctx;
37 
38 public:
39  RISCVMCCodeEmitter(MCContext &ctx) : Ctx(ctx) {}
40 
41  ~RISCVMCCodeEmitter() override {}
42 
43  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
45  const MCSubtargetInfo &STI) const override;
46 
47  /// TableGen'erated function for getting the binary encoding for an
48  /// instruction.
49  uint64_t getBinaryCodeForInstr(const MCInst &MI,
51  const MCSubtargetInfo &STI) const;
52 
53  /// Return binary encoding of operand. If the machine operand requires
54  /// relocation, record the relocation and return zero.
55  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
57  const MCSubtargetInfo &STI) const;
58 };
59 } // end anonymous namespace
60 
62  const MCRegisterInfo &MRI,
63  MCContext &Ctx) {
64  return new RISCVMCCodeEmitter(Ctx);
65 }
66 
67 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
69  const MCSubtargetInfo &STI) const {
70  // For now, we only support RISC-V instructions with 32-bit length
71  uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
73  ++MCNumEmitted; // Keep track of the # of mi's emitted.
74 }
75 
76 unsigned
77 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
79  const MCSubtargetInfo &STI) const {
80 
81  if (MO.isReg())
82  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
83 
84  if (MO.isImm())
85  return static_cast<unsigned>(MO.getImm());
86 
87  llvm_unreachable("Unhandled expression!");
88  return 0;
89 }
90 
91 #include "RISCVGenMCCodeEmitter.inc"
STATISTIC(NumFunctions,"Total number of functions")
bool isReg() const
Definition: MCInst.h:56
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
MCCodeEmitter * createRISCVMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Context object for machine code objects.
Definition: MCContext.h:51
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
static void write(bool isBE, void *P, T V)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int64_t getImm() const
Definition: MCInst.h:74
MCSubtargetInfo - Generic base class for all target subtargets.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33