LLVM  4.0.0
TargetPassConfig.cpp
Go to the documentation of this file.
1 //===-- TargetPassConfig.cpp - Target independent code generation passes --===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
12 //
13 //===---------------------------------------------------------------------===//
14 
16 
21 #include "llvm/Analysis/Passes.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/Support/Debug.h"
36 #include "llvm/Transforms/Scalar.h"
38 
39 using namespace llvm;
40 
41 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
42  cl::desc("Disable Post Regalloc Scheduler"));
43 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
44  cl::desc("Disable branch folding"));
45 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
46  cl::desc("Disable tail duplication"));
47 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
48  cl::desc("Disable pre-register allocation tail duplication"));
49 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
50  cl::Hidden, cl::desc("Disable probability-driven block placement"));
51 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
52  cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
53 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
54  cl::desc("Disable Stack Slot Coloring"));
55 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
56  cl::desc("Disable Machine Dead Code Elimination"));
57 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
58  cl::desc("Disable Early If-conversion"));
59 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
60  cl::desc("Disable Machine LICM"));
61 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
62  cl::desc("Disable Machine Common Subexpression Elimination"));
64  "optimize-regalloc", cl::Hidden,
65  cl::desc("Enable optimized register allocation compilation path."));
66 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
67  cl::Hidden,
68  cl::desc("Disable Machine LICM"));
69 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70  cl::desc("Disable Machine Sinking"));
71 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72  cl::desc("Disable Loop Strength Reduction Pass"));
73 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
74  cl::Hidden, cl::desc("Disable ConstantHoisting"));
75 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
76  cl::desc("Disable Codegen Prepare"));
77 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
78  cl::desc("Disable Copy Propagation pass"));
79 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
80  cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
82  "enable-implicit-null-checks",
83  cl::desc("Fold null checks into faulting memory operations"),
84  cl::init(false));
85 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
86  cl::desc("Print LLVM IR produced by the loop-reduce pass"));
87 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
88  cl::desc("Print LLVM IR input to isel pass"));
89 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
90  cl::desc("Dump garbage collector data"));
91 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
92  cl::desc("Verify generated machine code"),
93  cl::init(false),
95 
97 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
98  cl::desc("Print machine instrs"),
99  cl::value_desc("pass-name"), cl::init("option-unspecified"));
100 
102  "global-isel-abort", cl::Hidden,
103  cl::desc("Enable abort calls when \"global\" instruction selection "
104  "fails to lower/select an instruction: 0 disable the abort, "
105  "1 enable the abort, and "
106  "2 disable the abort but emit a diagnostic on failure"),
107  cl::init(1));
108 
109 // Temporary option to allow experimenting with MachineScheduler as a post-RA
110 // scheduler. Targets can "properly" enable this with
111 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
112 // Targets can return true in targetSchedulesPostRAScheduling() and
113 // insert a PostRA scheduling pass wherever it wants.
114 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
115  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
116 
117 // Experimental option to run live interval analysis early.
118 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
119  cl::desc("Run live interval analysis earlier in the pipeline"));
120 
121 // Experimental option to use CFL-AA in codegen
124  "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden,
125  cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"),
126  cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"),
128  "Enable unification-based CFL-AA"),
130  "Enable inclusion-based CFL-AA"),
131  clEnumValN(CFLAAType::Both, "both",
132  "Enable both variants of CFL-AA")));
133 
134 /// Allow standard passes to be disabled by command line options. This supports
135 /// simple binary flags that either suppress the pass or do nothing.
136 /// i.e. -disable-mypass=false has no effect.
137 /// These should be converted to boolOrDefault in order to use applyOverride.
139  bool Override) {
140  if (Override)
141  return IdentifyingPassPtr();
142  return PassID;
143 }
144 
145 /// Allow standard passes to be disabled by the command line, regardless of who
146 /// is adding the pass.
147 ///
148 /// StandardID is the pass identified in the standard pass pipeline and provided
149 /// to addPass(). It may be a target-specific ID in the case that the target
150 /// directly adds its own pass, but in that case we harmlessly fall through.
151 ///
152 /// TargetID is the pass that the target has configured to override StandardID.
153 ///
154 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
155 /// pass to run. This allows multiple options to control a single pass depending
156 /// on where in the pipeline that pass is added.
158  IdentifyingPassPtr TargetID) {
159  if (StandardID == &PostRASchedulerID)
160  return applyDisable(TargetID, DisablePostRASched);
161 
162  if (StandardID == &BranchFolderPassID)
163  return applyDisable(TargetID, DisableBranchFold);
164 
165  if (StandardID == &TailDuplicateID)
166  return applyDisable(TargetID, DisableTailDuplicate);
167 
168  if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
169  return applyDisable(TargetID, DisableEarlyTailDup);
170 
171  if (StandardID == &MachineBlockPlacementID)
172  return applyDisable(TargetID, DisableBlockPlacement);
173 
174  if (StandardID == &StackSlotColoringID)
175  return applyDisable(TargetID, DisableSSC);
176 
177  if (StandardID == &DeadMachineInstructionElimID)
178  return applyDisable(TargetID, DisableMachineDCE);
179 
180  if (StandardID == &EarlyIfConverterID)
181  return applyDisable(TargetID, DisableEarlyIfConversion);
182 
183  if (StandardID == &MachineLICMID)
184  return applyDisable(TargetID, DisableMachineLICM);
185 
186  if (StandardID == &MachineCSEID)
187  return applyDisable(TargetID, DisableMachineCSE);
188 
189  if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
190  return applyDisable(TargetID, DisablePostRAMachineLICM);
191 
192  if (StandardID == &MachineSinkingID)
193  return applyDisable(TargetID, DisableMachineSink);
194 
195  if (StandardID == &MachineCopyPropagationID)
196  return applyDisable(TargetID, DisableCopyProp);
197 
198  return TargetID;
199 }
200 
201 //===---------------------------------------------------------------------===//
202 /// TargetPassConfig
203 //===---------------------------------------------------------------------===//
204 
205 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
206  "Target Pass Configuration", false, false)
207 char TargetPassConfig::ID = 0;
208 
209 // Pseudo Pass IDs.
210 char TargetPassConfig::EarlyTailDuplicateID = 0;
211 char TargetPassConfig::PostRAMachineLICMID = 0;
212 
213 namespace {
214 struct InsertedPass {
215  AnalysisID TargetPassID;
216  IdentifyingPassPtr InsertedPassID;
217  bool VerifyAfter;
218  bool PrintAfter;
219 
220  InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
221  bool VerifyAfter, bool PrintAfter)
222  : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
223  VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
224 
225  Pass *getInsertedPass() const {
226  assert(InsertedPassID.isValid() && "Illegal Pass ID!");
227  if (InsertedPassID.isInstance())
228  return InsertedPassID.getInstance();
229  Pass *NP = Pass::createPass(InsertedPassID.getID());
230  assert(NP && "Pass ID not registered");
231  return NP;
232  }
233 };
234 }
235 
236 namespace llvm {
238 public:
239  // List of passes explicitly substituted by this target. Normally this is
240  // empty, but it is a convenient way to suppress or replace specific passes
241  // that are part of a standard pass pipeline without overridding the entire
242  // pipeline. This mechanism allows target options to inherit a standard pass's
243  // user interface. For example, a target may disable a standard pass by
244  // default by substituting a pass ID of zero, and the user may still enable
245  // that standard pass with an explicit command line option.
247 
248  /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
249  /// is inserted after each instance of the first one.
251 };
252 } // namespace llvm
253 
254 // Out of line virtual method.
256  delete Impl;
257 }
258 
259 // Out of line constructor provides default values for pass options and
260 // registers all common codegen passes.
262  : ImmutablePass(ID), PM(&pm), Started(true), Stopped(false),
263  AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
264  DisableVerify(false), EnableTailMerge(true) {
265 
266  Impl = new PassConfigImpl();
267 
268  // Register all target independent codegen passes to activate their PassIDs,
269  // including this pass itself.
271 
272  // Also register alias analysis passes required by codegen passes.
275 
276  // Substitute Pseudo Pass IDs for real ones.
277  substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
278  substitutePass(&PostRAMachineLICMID, &MachineLICMID);
279 
280  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
281  TM->Options.PrintMachineCode = true;
282 }
283 
285  return TM->getOptLevel();
286 }
287 
288 /// Insert InsertedPassID pass after TargetPassID.
290  IdentifyingPassPtr InsertedPassID,
291  bool VerifyAfter, bool PrintAfter) {
292  assert(((!InsertedPassID.isInstance() &&
293  TargetPassID != InsertedPassID.getID()) ||
294  (InsertedPassID.isInstance() &&
295  TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
296  "Insert a pass after itself!");
297  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
298  PrintAfter);
299 }
300 
301 /// createPassConfig - Create a pass configuration object to be used by
302 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
303 ///
304 /// Targets may override this to extend TargetPassConfig.
306  return new TargetPassConfig(this, PM);
307 }
308 
310  : ImmutablePass(ID), PM(nullptr) {
311  llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
312 }
313 
314 // Helper to verify the analysis is really immutable.
315 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
316  assert(!Initialized && "PassConfig is immutable");
317  Opt = Val;
318 }
319 
321  IdentifyingPassPtr TargetID) {
322  Impl->TargetPasses[StandardID] = TargetID;
323 }
324 
327  I = Impl->TargetPasses.find(ID);
328  if (I == Impl->TargetPasses.end())
329  return ID;
330  return I->second;
331 }
332 
335  IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
336  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
337  FinalPtr.getID() != ID;
338 }
339 
340 /// Add a pass to the PassManager if that pass is supposed to be run. If the
341 /// Started/Stopped flags indicate either that the compilation should start at
342 /// a later pass or that it should stop after an earlier pass, then do not add
343 /// the pass. Finally, compare the current pass against the StartAfter
344 /// and StopAfter options and change the Started/Stopped flags accordingly.
345 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
346  assert(!Initialized && "PassConfig is immutable");
347 
348  // Cache the Pass ID here in case the pass manager finds this pass is
349  // redundant with ones already scheduled / available, and deletes it.
350  // Fundamentally, once we add the pass to the manager, we no longer own it
351  // and shouldn't reference it.
352  AnalysisID PassID = P->getPassID();
353 
354  if (StartBefore == PassID)
355  Started = true;
356  if (StopBefore == PassID)
357  Stopped = true;
358  if (Started && !Stopped) {
359  std::string Banner;
360  // Construct banner message before PM->add() as that may delete the pass.
361  if (AddingMachinePasses && (printAfter || verifyAfter))
362  Banner = std::string("After ") + std::string(P->getPassName());
363  PM->add(P);
364  if (AddingMachinePasses) {
365  if (printAfter)
366  addPrintPass(Banner);
367  if (verifyAfter)
368  addVerifyPass(Banner);
369  }
370 
371  // Add the passes after the pass P if there is any.
372  for (auto IP : Impl->InsertedPasses) {
373  if (IP.TargetPassID == PassID)
374  addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
375  }
376  } else {
377  delete P;
378  }
379  if (StopAfter == PassID)
380  Stopped = true;
381  if (StartAfter == PassID)
382  Started = true;
383  if (Stopped && !Started)
384  report_fatal_error("Cannot stop compilation after pass that is not run");
385 }
386 
387 /// Add a CodeGen pass at this point in the pipeline after checking for target
388 /// and command line overrides.
389 ///
390 /// addPass cannot return a pointer to the pass instance because is internal the
391 /// PassManager and the instance we create here may already be freed.
393  bool printAfter) {
394  IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
395  IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
396  if (!FinalPtr.isValid())
397  return nullptr;
398 
399  Pass *P;
400  if (FinalPtr.isInstance())
401  P = FinalPtr.getInstance();
402  else {
403  P = Pass::createPass(FinalPtr.getID());
404  if (!P)
405  llvm_unreachable("Pass ID not registered");
406  }
407  AnalysisID FinalID = P->getPassID();
408  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
409 
410  return FinalID;
411 }
412 
413 void TargetPassConfig::printAndVerify(const std::string &Banner) {
414  addPrintPass(Banner);
415  addVerifyPass(Banner);
416 }
417 
418 void TargetPassConfig::addPrintPass(const std::string &Banner) {
419  if (TM->shouldPrintMachineCode())
420  PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
421 }
422 
423 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
424  if (VerifyMachineCode)
425  PM->add(createMachineVerifierPass(Banner));
426 }
427 
428 /// Add common target configurable passes that perform LLVM IR to IR transforms
429 /// following machine independent optimization.
431  switch (UseCFLAA) {
434  break;
435  case CFLAAType::Andersen:
437  break;
438  case CFLAAType::Both:
441  break;
442  default:
443  break;
444  }
445 
446  // Basic AliasAnalysis support.
447  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
448  // BasicAliasAnalysis wins if they disagree. This is intended to help
449  // support "obvious" type-punning idioms.
453 
454  // Before running any passes, run the verifier to determine if the input
455  // coming from the front-end and/or optimizer is valid.
456  if (!DisableVerify)
458 
459  // Run loop strength reduction before anything else.
460  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
462  if (PrintLSR)
463  addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
464  }
465 
466  // Run GC lowering passes for builtin collectors
467  // TODO: add a pass insertion point here
470 
471  // Make sure that no unreachable blocks are instruction selected.
473 
474  // Prepare expensive constants for SelectionDAG.
477 
480 
481  // Insert calls to mcount-like functions.
483 }
484 
485 /// Turn exception handling constructs into something the code generators can
486 /// handle.
488  const MCAsmInfo *MCAI = TM->getMCAsmInfo();
489  assert(MCAI && "No MCAsmInfo");
490  switch (MCAI->getExceptionHandlingType()) {
492  // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
493  // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
494  // catch info can get misplaced when a selector ends up more than one block
495  // removed from the parent invoke(s). This could happen when a landing
496  // pad is shared by multiple invokes and is also a target of a normal
497  // edge from elsewhere.
503  break;
505  // We support using both GCC-style and MSVC-style exceptions on Windows, so
506  // add both preparation passes. Each pass will only actually run if it
507  // recognizes the personality function.
510  break;
513 
514  // The lower invoke pass may create unreachable code. Remove it.
516  break;
517  }
518 }
519 
520 /// Add pass to prepare the LLVM IR for code generation. This should be done
521 /// before exception handling preparation passes.
526 }
527 
528 /// Add common passes that perform LLVM IR to IR transforms in preparation for
529 /// instruction selection.
531  addPreISel();
532 
533  // Force codegen to run according to the callgraph.
534  if (TM->Options.EnableIPRA)
535  addPass(new DummyCGSCCPass);
536 
537  // Add both the safe stack and the stack protection passes: each of them will
538  // only protect functions that have corresponding attributes.
541 
542  if (PrintISelInput)
544  dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
545 
546  // All passes which modify the LLVM IR are now complete; run the verifier
547  // to ensure that the IR is valid.
548  if (!DisableVerify)
550 }
551 
552 /// Add the complete set of target-independent postISel code generator passes.
553 ///
554 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
555 /// with nontrivial configuration or multiple passes are broken out below in
556 /// add%Stage routines.
557 ///
558 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
559 /// addPre/Post methods with empty header implementations allow injecting
560 /// target-specific fixups just before or after major stages. Additionally,
561 /// targets have the flexibility to change pass order within a stage by
562 /// overriding default implementation of add%Stage routines below. Each
563 /// technique has maintainability tradeoffs because alternate pass orders are
564 /// not well supported. addPre/Post works better if the target pass is easily
565 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
566 /// the target should override the stage instead.
567 ///
568 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
569 /// before/after any target-independent pass. But it's currently overkill.
571  AddingMachinePasses = true;
572 
573  // Insert a machine instr printer pass after the specified pass.
574  if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
575  !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
577  const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
578  const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
579  assert (TPI && IPI && "Pass ID not registered!");
580  const char *TID = (const char *)(TPI->getTypeInfo());
581  const char *IID = (const char *)(IPI->getTypeInfo());
582  insertPass(TID, IID);
583  }
584 
585  // Print the instruction selected machine code...
586  printAndVerify("After Instruction Selection");
587 
588  if (TM->Options.EnableIPRA)
590 
591  // Expand pseudo-instructions emitted by ISel.
593 
594  // Add passes that optimize machine instructions in SSA form.
595  if (getOptLevel() != CodeGenOpt::None) {
597  } else {
598  // If the target requests it, assign local variables to stack slots relative
599  // to one another and simplify frame index references where possible.
601  }
602 
603  // Run pre-ra passes.
604  addPreRegAlloc();
605 
606  // Run register allocation and passes that are tightly coupled with it,
607  // including phi elimination and scheduling.
608  if (getOptimizeRegAlloc())
610  else
612 
613  // Run post-ra passes.
614  addPostRegAlloc();
615 
616  // Insert prolog/epilog code. Eliminate abstract frame index references...
617  if (getOptLevel() != CodeGenOpt::None)
619 
620  // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
621  // do so if it hasn't been disabled, substituted, or overridden.
624 
625  /// Add passes that optimize machine instructions after register allocation.
626  if (getOptLevel() != CodeGenOpt::None)
628 
629  // Expand pseudo instructions before second scheduling pass.
631 
632  // Run pre-sched2 passes.
633  addPreSched2();
634 
637 
638  // Second pass scheduler.
639  // Let Target optionally insert this pass by itself at some other
640  // point.
641  if (getOptLevel() != CodeGenOpt::None &&
643  if (MISchedPostRA)
645  else
647  }
648 
649  // GC
650  if (addGCPasses()) {
651  if (PrintGCInfo)
652  addPass(createGCInfoPrinter(dbgs()), false, false);
653  }
654 
655  // Basic block placement.
656  if (getOptLevel() != CodeGenOpt::None)
658 
659  addPreEmitPass();
660 
661  if (TM->Options.EnableIPRA)
662  // Collect register usage information and produce a register mask of
663  // clobbered registers, to be used to optimize call sites.
665 
666  addPass(&FuncletLayoutID, false);
667 
668  addPass(&StackMapLivenessID, false);
669  addPass(&LiveDebugValuesID, false);
670 
672  addPass(&PatchableFunctionID, false);
673 
674  AddingMachinePasses = false;
675 }
676 
677 /// Add passes that optimize machine instructions in SSA form.
679  // Pre-ra tail duplication.
680  addPass(&EarlyTailDuplicateID);
681 
682  // Optimize PHIs before DCE: removing dead PHI cycles may make more
683  // instructions dead.
684  addPass(&OptimizePHIsID, false);
685 
686  // This pass merges large allocas. StackSlotColoring is a different pass
687  // which merges spill slots.
688  addPass(&StackColoringID, false);
689 
690  // If the target requests it, assign local variables to stack slots relative
691  // to one another and simplify frame index references where possible.
693 
694  // With optimization, dead code should already be eliminated. However
695  // there is one known exception: lowered code for arguments that are only
696  // used by tail calls, where the tail calls reuse the incoming stack
697  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
699 
700  // Allow targets to insert passes that improve instruction level parallelism,
701  // like if-conversion. Such passes will typically need dominator trees and
702  // loop info, just like LICM and CSE below.
703  addILPOpts();
704 
705  addPass(&MachineLICMID, false);
706  addPass(&MachineCSEID, false);
708 
710  // Clean-up the dead code that may have been generated by peephole
711  // rewriting.
713 }
714 
715 //===---------------------------------------------------------------------===//
716 /// Register Allocation Pass Configuration
717 //===---------------------------------------------------------------------===//
718 
720  switch (OptimizeRegAlloc) {
721  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
722  case cl::BOU_TRUE: return true;
723  case cl::BOU_FALSE: return false;
724  }
725  llvm_unreachable("Invalid optimize-regalloc state");
726 }
727 
728 /// RegisterRegAlloc's global Registry tracks allocator registration.
730 
731 /// A dummy default pass factory indicates whether the register allocator is
732 /// overridden on the command line.
733 LLVM_DEFINE_ONCE_FLAG(InitializeDefaultRegisterAllocatorFlag);
734 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
735 static RegisterRegAlloc
736 defaultRegAlloc("default",
737  "pick register allocator based on -O option",
739 
740 /// -regalloc=... command line option.
743 RegAlloc("regalloc",
745  cl::desc("Register allocator to use"));
746 
749 
750  if (!Ctor) {
751  Ctor = RegAlloc;
753  }
754 }
755 
756 
757 /// Instantiate the default register allocator pass for this target for either
758 /// the optimized or unoptimized allocation path. This will be added to the pass
759 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
760 /// in the optimized case.
761 ///
762 /// A target that uses the standard regalloc pass order for fast or optimized
763 /// allocation may still override this for per-target regalloc
764 /// selection. But -regalloc=... always takes precedence.
766  if (Optimized)
768  else
770 }
771 
772 /// Find and instantiate the register allocation pass requested by this target
773 /// at the current optimization level. Different register allocators are
774 /// defined as separate passes because they may require different analysis.
775 ///
776 /// This helper ensures that the regalloc= option is always available,
777 /// even for targets that override the default allocator.
778 ///
779 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
780 /// this can be folded into addPass.
782  // Initialize the global default.
783  llvm::call_once(InitializeDefaultRegisterAllocatorFlag,
785 
787  if (Ctor != useDefaultRegisterAllocator)
788  return Ctor();
789 
790  // With no -regalloc= override, ask the target for a regalloc pass.
791  return createTargetRegisterAllocator(Optimized);
792 }
793 
794 /// Return true if the default global register allocator is in use and
795 /// has not be overriden on the command line with '-regalloc=...'
797  return RegAlloc.getNumOccurrences() == 0;
798 }
799 
800 /// Add the minimum set of target-independent passes that are required for
801 /// register allocation. No coalescing or scheduling.
803  addPass(&PHIEliminationID, false);
805 
806  if (RegAllocPass)
807  addPass(RegAllocPass);
808 }
809 
810 /// Add standard target-independent passes that are tightly coupled with
811 /// optimized register allocation, including coalescing, machine instruction
812 /// scheduling, and register allocation itself.
814  addPass(&DetectDeadLanesID, false);
815 
817 
818  // LiveVariables currently requires pure SSA form.
819  //
820  // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
821  // LiveVariables can be removed completely, and LiveIntervals can be directly
822  // computed. (We still either need to regenerate kill flags after regalloc, or
823  // preferably fix the scavenger to not depend on them).
824  addPass(&LiveVariablesID, false);
825 
826  // Edge splitting is smarter with machine loop info.
827  addPass(&MachineLoopInfoID, false);
828  addPass(&PHIEliminationID, false);
829 
830  // Eventually, we want to run LiveIntervals before PHI elimination.
831  if (EarlyLiveIntervals)
832  addPass(&LiveIntervalsID, false);
833 
836 
837  // The machine scheduler may accidentally create disconnected components
838  // when moving subregister definitions around, avoid this by splitting them to
839  // separate vregs before. Splitting can also improve reg. allocation quality.
841 
842  // PreRA instruction scheduling.
844 
845  if (RegAllocPass) {
846  // Add the selected register allocation pass.
847  addPass(RegAllocPass);
848 
849  // Allow targets to change the register assignments before rewriting.
850  addPreRewrite();
851 
852  // Finally rewrite virtual registers.
854 
855  // Perform stack slot coloring and post-ra machine LICM.
856  //
857  // FIXME: Re-enable coloring with register when it's capable of adding
858  // kill markers.
860 
861  // Run post-ra machine LICM to hoist reloads / remats.
862  //
863  // FIXME: can this move into MachineLateOptimization?
864  addPass(&PostRAMachineLICMID);
865  }
866 }
867 
868 //===---------------------------------------------------------------------===//
869 /// Post RegAlloc Pass Configuration
870 //===---------------------------------------------------------------------===//
871 
872 /// Add passes that optimize machine instructions after register allocation.
874  // Branch folding must be run after regalloc and prolog/epilog insertion.
876 
877  // Tail duplication.
878  // Note that duplicating tail just increases code size and degrades
879  // performance for targets that require Structured Control Flow.
880  // In addition it can also make CFG irreducible. Thus we disable it.
881  if (!TM->requiresStructuredCFG())
883 
884  // Copy propagation.
886 }
887 
888 /// Add standard GC passes.
891  return true;
892 }
893 
894 /// Add standard basic block placement passes.
897  // Run a separate pass to collect block placement statistics.
900  }
901 }
902 
903 //===---------------------------------------------------------------------===//
904 /// GlobalISel Configuration
905 //===---------------------------------------------------------------------===//
907  return EnableGlobalISelAbort == 1;
908 }
909 
911  return EnableGlobalISelAbort == 2;
912 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:81
static cl::opt< bool > EnableBlockPlacementStats("enable-block-placement-stats", cl::Hidden, cl::desc("Collect probability-driven block placement stats"))
FunctionPass * createCodeGenPreparePass(const TargetMachine *TM=nullptr)
createCodeGenPreparePass - Transform the code to expose more pattern matching during instruction sele...
static cl::opt< bool > DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass"))
static cl::opt< bool > DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare"))
unsigned PrintMachineCode
PrintMachineCode - This flag is enabled when the -print-machineinstrs option is specified on the comm...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > DisableMachineLICM("disable-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
static cl::opt< bool > PrintISelInput("print-isel-input", cl::Hidden, cl::desc("Print LLVM IR input to isel pass"))
Pass * createLoopStrengthReducePass()
This is the interface for LLVM's inclusion-based alias analysis implemented with CFL graph reachabili...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
AnalysisID getPassID() const
getPassID - Return the PassID number that corresponds to this pass.
Definition: Pass.h:103
char & MachineLICMID
MachineLICM - This pass performs LICM on machine instructions.
DWARF-like instruction based exceptions.
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
char & FuncletLayoutID
This pass lays out funclets contiguously.
This is the interface for a metadata-based scoped no-alias analysis.
FunctionPass * createPrintFunctionPass(raw_ostream &OS, const std::string &Banner="")
Create and return a pass that prints functions to the specified raw_ostream as they are processed...
FunctionPass * createVerifierPass(bool FatalErrors=true)
Definition: Verifier.cpp:4791
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
static cl::opt< bool > DisablePartialLibcallInlining("disable-partial-libcall-inlining", cl::Hidden, cl::desc("Disable Partial Libcall Inlining"))
FunctionPass *(* FunctionPassCtor)()
static cl::opt< bool > DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass"))
static void setDefault(FunctionPassCtor C)
FunctionPass * createWinEHPass(const TargetMachine *TM)
createWinEHPass - Prepares personality functions used by MSVC on Windows, in addition to the Itanium ...
const void * getTypeInfo() const
getTypeInfo - Return the id object for the pass...
Definition: PassInfo.h:78
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:67
static cl::opt< bool > EarlyLiveIntervals("early-live-intervals", cl::Hidden, cl::desc("Run live interval analysis earlier in the pipeline"))
virtual bool targetSchedulesPostRAScheduling() const
True if subtarget inserts the final scheduling pass on its own.
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
setjmp/longjmp based exceptions
RegisterPassParser class - Handle the addition of new machine passes.
static cl::opt< bool > PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data"))
static MachinePassRegistry Registry
RegisterRegAlloc's global Registry tracks allocator registration.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
static void initializeDefaultRegisterAllocatorOnce()
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
char & MachineBlockPlacementStatsID
MachineBlockPlacementStats - This pass collects statistics about the basic block placement using bran...
ImmutablePass * createScopedNoAliasAAWrapperPass()
FunctionPass * createShadowStackGCLoweringPass()
ShadowStackGCLowering - Implements the custom lowering mechanism used by the shadow stack GC...
virtual TargetPassConfig * createPassConfig(PassManagerBase &PM)
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Pass * getInstance() const
CodeGenOpt::Level getOptLevel() const
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
static FunctionPass * useDefaultRegisterAllocator()
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
FunctionPass * createGCLoweringPass()
GCLowering Pass - Used by gc.root to perform its default lowering operations.
unsigned EnableIPRA
This flag enables InterProcedural Register Allocation (IPRA).
FunctionPass * createLowerInvokePass()
Definition: LowerInvoke.cpp:84
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
void call_once(once_flag &flag, Function &&F, Args &&...ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:91
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
FunctionPass * createRegUsageInfoCollector()
This pass is executed POST-RA to collect which physical registers are preserved by given machine func...
FunctionPass * createCountingFunctionInserterPass()
Insert mcount-like function calls.
Target-Independent Code Generator Pass Configuration Options.
void initializeAAResultsWrapperPassPass(PassRegistry &)
char & XRayInstrumentationID
This pass inserts the XRay instrumentation sleds if they are supported by the target platform...
static cl::opt< bool > DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting"))
FunctionPass * createPartiallyInlineLibCallsPass()
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:110
static IdentifyingPassPtr overridePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow standard passes to be disabled by the command line, regardless of who is adding the pass...
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
Function Alias Analysis false
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
static cl::opt< bool > DisablePostRAMachineLICM("disable-postra-machine-licm", cl::Hidden, cl::desc("Disable Machine LICM"))
char & ExpandISelPseudosID
ExpandISelPseudos - This pass expands pseudo-instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
static cl::opt< bool > DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, cl::desc("Disable tail duplication"))
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
FunctionPass * createUnreachableBlockEliminationPass()
createUnreachableBlockEliminationPass - The LLVM code generator does not work well with unreachable b...
RegisterRegAlloc class - Track the registration of register allocators.
MachinePassRegistry - Track the registration of machine passes.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, bool Override)
Allow standard passes to be disabled by command line options.
FunctionPass * createGCInfoPrinter(raw_ostream &OS)
Creates a pass to print GC metadata.
Definition: GCMetadata.cpp:86
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
DenseMap< AnalysisID, IdentifyingPassPtr > TargetPasses
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
ValuesClass values(OptsTy...Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:615
SmallVector< InsertedPass, 4 > InsertedPasses
Store the pairs of <AnalysisID, AnalysisID> of which the second pass is inserted after each instance ...
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static cl::opt< bool > DisableEarlyTailDup("disable-early-taildup", cl::Hidden, cl::desc("Disable pre-register allocation tail duplication"))
static cl::opt< std::string > PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"), cl::value_desc("pass-name"), cl::init("option-unspecified"))
This is the interface for LLVM's unification-based alias analysis implemented with CFL graph reachabi...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
FunctionPass * createRegUsageInfoPropPass()
Return a MachineFunction pass that identifies call sites and propagates register usage information of...
This pass is required by interprocedural register allocation.
static cl::opt< bool > DisableSSC("disable-ssc", cl::Hidden, cl::desc("Disable Stack Slot Coloring"))
This is the interface for a metadata-based TBAA.
static char PostRAMachineLICMID
PostRAMachineLICM - A clone of the LICM pass that runs during late machine optimization after regallo...
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
static cl::opt< bool > VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(false), cl::ZeroOrMore)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
char & LiveDebugValuesID
LiveDebugValues pass.
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:538
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
FunctionPass * createSafeStackPass(const TargetMachine *TM=nullptr)
This pass splits the stack into a safe stack and an unsafe stack to protect against stack-based overf...
Definition: SafeStack.cpp:799
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
static cl::opt< bool > DisableMachineSink("disable-machine-sink", cl::Hidden, cl::desc("Disable Machine Sinking"))
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void pm(uint64_t &Value)
Adjusts a program memory address.
PassInfo class - An instance of this class exists for every pass known by the system, and can be obtained from a live Pass by calling its getPassInfo() method.
Definition: PassInfo.h:32
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
MachineFunctionPass * createPrologEpilogInserterPass(const TargetMachine *TM)
cl::opt< bool > MISchedPostRA("misched-postra", cl::Hidden, cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"))
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
char & ImplicitNullChecksID
ImplicitNullChecks - This pass folds null pointer checks into nearby memory operations.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< bool > PrintLSR("print-lsr-output", cl::Hidden, cl::desc("Print LLVM IR produced by the loop-reduce pass"))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:36
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > DisableBranchFold("disable-branch-fold", cl::Hidden, cl::desc("Disable branch folding"))
static FunctionPassCtor getDefault()
FunctionPass * createStackProtectorPass(const TargetMachine *TM)
createStackProtectorPass - This pass adds stack protectors to functions.
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:266
LLVM_DEFINE_ONCE_FLAG(InitializeDefaultRegisterAllocatorFlag)
A dummy default pass factory indicates whether the register allocator is overridden on the command li...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
static cl::opt< bool > DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, cl::desc("Disable Early If-conversion"))
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
static cl::opt< cl::boolOrDefault > OptimizeRegAlloc("optimize-regalloc", cl::Hidden, cl::desc("Enable optimized register allocation compilation path."))
static cl::opt< bool > DisableMachineDCE("disable-machine-dce", cl::Hidden, cl::desc("Disable Machine Dead Code Elimination"))
MachineFunctionPass * createMachineFunctionPrinterPass(raw_ostream &OS, const std::string &Banner="")
MachineFunctionPrinter pass - This pass prints out the machine function to the given stream as a debu...
static cl::opt< CFLAAType > UseCFLAA("use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), cl::values(clEnumValN(CFLAAType::None,"none","Disable CFL-AA"), clEnumValN(CFLAAType::Steensgaard,"steens","Enable unification-based CFL-AA"), clEnumValN(CFLAAType::Andersen,"anders","Enable inclusion-based CFL-AA"), clEnumValN(CFLAAType::Both,"both","Enable both variants of CFL-AA")))
ModulePass * createRewriteSymbolsPass()
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
FunctionPass * createBasicAAWrapperPass()
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Discriminated union of Pass ID types.
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:590
Basic Alias true
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
void emplace_back(ArgTypes &&...Args)
Definition: SmallVector.h:635
char & GCMachineCodeAnalysisID
GCMachineCodeAnalysis - Target-independent pass to mark safe points in machine code.
static cl::opt< bool > DisableBlockPlacement("disable-block-placement", cl::Hidden, cl::desc("Disable probability-driven block placement"))
static cl::opt< int > EnableGlobalISelAbort("global-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"global\" instruction selection ""fails to lower/select an instruction: 0 disable the abort, ""1 enable the abort, and ""2 disable the abort but emit a diagnostic on failure"), cl::init(1))
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
static cl::opt< RegisterRegAlloc::FunctionPassCtor, false, RegisterPassParser< RegisterRegAlloc > > RegAlloc("regalloc", cl::init(&useDefaultRegisterAllocator), cl::desc("Register allocator to use"))
-regalloc=... command line option.
FunctionPass * createDwarfEHPass(const TargetMachine *TM)
createDwarfEHPass - This pass mulches exception handling code into a form adapted to code generation...
virtual void addBlockPlacement()
Add standard basic block placement passes.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
AnalysisID getID() const
#define I(x, y, z)
Definition: MD5.cpp:54
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
static RegisterRegAlloc defaultRegAlloc("default","pick register allocator based on -O option", useDefaultRegisterAllocator)
void setOpt(bool &Opt, bool Val)
static cl::opt< bool > DisablePostRASched("disable-post-ra", cl::Hidden, cl::desc("Disable Post Regalloc Scheduler"))
const void * AnalysisID
Definition: Pass.h:46
ImmutablePass * createCFLSteensAAWrapperPass()
ImmutablePass * createTypeBasedAAWrapperPass()
bool shouldPrintMachineCode() const
This pass is required to take advantage of the interprocedural register allocation infrastructure...
const PassInfo * getPassInfo(const void *TI) const
getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' type identifier (&MyPass::...
This file defines passes to print out IR in various granularities.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
FunctionPass * createSjLjEHPreparePass()
createSjLjEHPreparePass - This pass adapts exception handling code to use the GCC-style builtin setjm...
static cl::opt< bool > EnableImplicitNullChecks("enable-implicit-null-checks", cl::desc("Fold null checks into faulting memory operations"), cl::init(false))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static char EarlyTailDuplicateID
Pseudo Pass IDs.
static Pass * createPass(AnalysisID ID)
Definition: Pass.cpp:208
void initializeCodeGen(PassRegistry &)
Initialize all passes linked into the CodeGen library.
Definition: CodeGen.cpp:22
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:185
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
Primary interface to the complete machine description for the target machine.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:211
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
This is the interface for LLVM's primary stateless and local alias analysis.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:40
No exception support.
ImmutablePass * createCFLAndersAAWrapperPass()
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
bool requiresStructuredCFG() const
static cl::opt< bool > DisableMachineCSE("disable-machine-cse", cl::Hidden, cl::desc("Disable Machine Common Subexpression Elimination"))
void initializeBasicAAWrapperPassPass(PassRegistry &)
FunctionPass * createConstantHoistingPass()