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LLVM
4.0.0
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#include "AArch64CallingConvention.h"#include "AArch64MachineFunctionInfo.h"#include "AArch64ISelLowering.h"#include "AArch64PerfectShuffle.h"#include "AArch64RegisterInfo.h"#include "AArch64Subtarget.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "Utils/AArch64BaseInfo.h"#include "llvm/ADT/APFloat.h"#include "llvm/ADT/APInt.h"#include "llvm/ADT/ArrayRef.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/StringRef.h"#include "llvm/ADT/StringSwitch.h"#include "llvm/ADT/Triple.h"#include "llvm/ADT/Twine.h"#include "llvm/CodeGen/CallingConvLower.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/MachineValueType.h"#include "llvm/CodeGen/RuntimeLibcalls.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/CodeGen/ValueTypes.h"#include "llvm/IR/Attributes.h"#include "llvm/IR/Constants.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/DebugLoc.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/GetElementPtrTypeIterator.h"#include "llvm/IR/GlobalValue.h"#include "llvm/IR/Instruction.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/Module.h"#include "llvm/IR/OperandTraits.h"#include "llvm/IR/Type.h"#include "llvm/IR/Use.h"#include "llvm/IR/Value.h"#include "llvm/MC/MCRegisterInfo.h"#include "llvm/Support/Casting.h"#include "llvm/Support/CodeGen.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Compiler.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetCallingConv.h"#include "llvm/Target/TargetInstrInfo.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetOptions.h"#include <algorithm>#include <bitset>#include <cassert>#include <cctype>#include <cstdint>#include <cstdlib>#include <iterator>#include <limits>#include <tuple>#include <utility>#include <vector>#include "AArch64GenCallingConv.inc"Go to the source code of this file.
Classes | |
| struct | GenericSetCCInfo |
| Helper structure to keep track of ISD::SET_CC operands. More... | |
| struct | AArch64SetCCInfo |
| Helper structure to keep track of a SET_CC lowered into AArch64 code. More... | |
| union | SetCCInfo |
| Helper structure to keep track of SetCC information. More... | |
| struct | SetCCInfoAndKind |
| Helper structure to be able to read SetCC information. More... | |
Macros | |
| #define | DEBUG_TYPE "aarch64-lower" |
Functions | |
| STATISTIC (NumTailCalls,"Number of tail calls") | |
| STATISTIC (NumShiftInserts,"Number of vector shift inserts") | |
| static AArch64CC::CondCode | changeIntCCToAArch64CC (ISD::CondCode CC) |
| changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC More... | |
| static void | changeFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2) |
| changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC. More... | |
| static void | changeFPCCToANDAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2) |
| Convert a DAG fp condition code to an AArch64 CC. More... | |
| static void | changeVectorFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert) |
| changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions. More... | |
| static bool | isLegalArithImmed (uint64_t C) |
| static SDValue | emitComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) |
| static SDValue | emitConditionalComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG) |
| Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate. More... | |
| static bool | isConjunctionDisjunctionTree (const SDValue Val, bool &CanNegate, unsigned Depth=0) |
Returns true if Val is a tree of AND/OR/SETCC operations. More... | |
| static SDValue | emitConjunctionDisjunctionTreeRec (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate) |
| Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops. More... | |
| static SDValue | emitConjunctionDisjunctionTree (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC) |
| Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops. More... | |
| static SDValue | getAArch64Cmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl) |
| static std::pair< SDValue, SDValue > | getAArch64XALUOOp (AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerXOR (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerXALUO (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerPREFETCH (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG) |
| static SDValue | LowerBITCAST (SDValue Op, SelectionDAG &DAG) |
| static EVT | getExtensionTo64Bits (const EVT &OrigVT) |
| static SDValue | addRequiredExtensionForVectorMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode) |
| static bool | isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned) |
| static SDValue | skipExtensionForVectorMULL (SDNode *N, SelectionDAG &DAG) |
| static bool | isSignExtended (SDNode *N, SelectionDAG &DAG) |
| static bool | isZeroExtended (SDNode *N, SelectionDAG &DAG) |
| static bool | isAddSubSExt (SDNode *N, SelectionDAG &DAG) |
| static bool | isAddSubZExt (SDNode *N, SelectionDAG &DAG) |
| static SDValue | LowerMUL (SDValue Op, SelectionDAG &DAG) |
| static bool | canGuaranteeTCO (CallingConv::ID CC) |
| Return true if the calling convention is one that we can guarantee TCO for. More... | |
| static bool | mayTailCallThisCC (CallingConv::ID CC) |
| Return true if we might ever do TCO for calls with this calling convention. More... | |
| static SDValue | getEstimate (const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps) |
| static SDValue | WidenVector (SDValue V64Reg, SelectionDAG &DAG) |
| WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class. More... | |
| static unsigned | getExtFactor (SDValue &V) |
| getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction. More... | |
| static SDValue | NarrowVector (SDValue V128Reg, SelectionDAG &DAG) |
| NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class. More... | |
| static bool | isSingletonEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm) |
| static bool | isEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm) |
| static bool | isREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize) |
| isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize. More... | |
| static bool | isZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| static bool | isZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult) |
| isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More... | |
| static bool | isINSMask (ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly) |
| static bool | isConcatMask (ArrayRef< int > Mask, EVT VT, bool SplitLHS) |
| static SDValue | tryFormConcatFromShuffle (SDValue Op, SelectionDAG &DAG) |
| static SDValue | GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) |
| GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More... | |
| static SDValue | GenerateTBL (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG) |
| static unsigned | getDUPLANEOp (EVT EltType) |
| static bool | resolveBuildVector (BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits) |
| static bool | isAllConstantBuildVector (const SDValue &PotentialBVec, uint64_t &ConstVal) |
| static unsigned | getIntrinsicID (const SDNode *N) |
| static SDValue | tryLowerToSLI (SDNode *N, SelectionDAG &DAG) |
| static SDValue | NormalizeBuildVector (SDValue Op, SelectionDAG &DAG) |
| static bool | getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt) |
| getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More... | |
| static bool | isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt) |
| isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More... | |
| static bool | isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) |
| isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More... | |
| static SDValue | EmitVectorComparison (SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG) |
| static Constant * | getSequentialMask (IRBuilder<> &Builder, unsigned Start, unsigned NumElts) |
Get a mask consisting of sequential integers starting from Start. More... | |
| static bool | memOpAlign (unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck) |
| static SDValue | foldVectorXorShiftIntoCmp (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0. More... | |
| static SDValue | performIntegerAbsCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performXorCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performMulCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performVectorCompareAndMaskUnaryOpCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performIntToFpCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performFpToIntCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| Fold a floating-point multiply by power of two into floating-point to fixed-point conversion. More... | |
| static SDValue | performFDivCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| Fold a floating-point divide by power of two into fixed-point to floating-point conversion. More... | |
| static bool | findEXTRHalf (SDValue N, SDValue &Src, uint32_t &ShiftAmount, bool &FromHi) |
| An EXTR instruction is made up of two shifts, ORed together. More... | |
| static SDValue | tryCombineToEXTR (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair. More... | |
| static SDValue | tryCombineToBSL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performSRLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| static SDValue | performBitcastCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performConcatVectorsCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineFixedPointConvert (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryExtendDUPToExtractHigh (SDValue N, SelectionDAG &DAG) |
| static bool | isEssentiallyExtractSubvector (SDValue N) |
| static bool | isSetCC (SDValue Op, SetCCInfoAndKind &SetCCInfo) |
Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one. More... | |
| static bool | isSetCCOrZExtSetCC (const SDValue &Op, SetCCInfoAndKind &Info) |
| static SDValue | performSetccAddFolding (SDNode *Op, SelectionDAG &DAG) |
| static SDValue | performAddSubLongCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineLongOpWithDup (unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | tryCombineShiftImm (unsigned IID, SDNode *N, SelectionDAG &DAG) |
| static SDValue | tryCombineCRC32 (unsigned Mask, SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineAcrossLanesIntrinsic (unsigned Opc, SDNode *N, SelectionDAG &DAG) |
| static SDValue | performIntrinsicCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) |
| static SDValue | performExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | splitStoreSplat (SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts) |
| static SDValue | replaceZeroVectorStore (SelectionDAG &DAG, StoreSDNode &St) |
| Replace a splat of zeros to a vector store by scalar stores of WZR/XZR. More... | |
| static SDValue | replaceSplatVectorStore (SelectionDAG &DAG, StoreSDNode &St) |
| Replace a splat of a scalar to a vector store by scalar stores of the scalar value. More... | |
| static SDValue | splitStores (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | performPostLD1Combine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp) |
| Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R. More... | |
| static bool | performTBISimplification (SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| Simplify given that the top byte of it is ignored by HW during address translation. More... | |
| static SDValue | performSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| static SDValue | tryMatchAcrossLaneShuffleForReduction (SDNode *N, SDValue OpV, unsigned Op, SelectionDAG &DAG) |
| This function handles the log2-shuffle pattern produced by the. More... | |
| static SDValue | performAcrossLaneMinMaxReductionCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| Target-specific DAG combine for the across vector min/max reductions. More... | |
| static SDValue | performAcrossLaneAddReductionCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) |
| Target-specific DAG combine for the across vector add reduction. More... | |
| static SDValue | performNEONPostLDSTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates. More... | |
| static bool | checkValueWidth (SDValue V, unsigned width, ISD::LoadExtType &ExtType) |
| static bool | isEquivalentMaskless (unsigned CC, unsigned width, ISD::LoadExtType ExtType, int AddConstant, int CompConstant) |
| static SDValue | performCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) |
| static SDValue | performBRCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | getTestBitOperand (SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG) |
| static SDValue | performTBZCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) |
| static SDValue | performVSelectCombine (SDNode *N, SelectionDAG &DAG) |
| static SDValue | performSelectCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI) |
| A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar. More... | |
| static SDValue | performNVCASTCombine (SDNode *N) |
| Get rid of unnecessary NVCASTs (that don't change the type). More... | |
| static void | ReplaceBITCASTResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) |
| static void | ReplaceReductionResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp) |
| static std::pair< SDValue, SDValue > | splitInt128 (SDValue N, SelectionDAG &DAG) |
| static void | ReplaceCMP_SWAP_128Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) |
Variables | |
| static cl::opt< bool > | EnableAArch64SlrGeneration ("aarch64-shift-insert-generation", cl::Hidden, cl::desc("Allow AArch64 SLI/SRI formation"), cl::init(false)) |
| cl::opt< bool > | EnableAArch64ELFLocalDynamicTLSGeneration ("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false)) |
| static const MVT | MVT_CC = MVT::i32 |
| Value type used for condition codes. More... | |
| #define DEBUG_TYPE "aarch64-lower" |
Definition at line 89 of file AArch64ISelLowering.cpp.
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Definition at line 2166 of file AArch64ISelLowering.cpp.
References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), and llvm::EVT::is128BitVector().
Referenced by skipExtensionForVectorMULL().
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Return true if the calling convention is one that we can guarantee TCO for.
Definition at line 2827 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::Fast.
Referenced by mayTailCallThisCC().
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changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
Definition at line 1137 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
Referenced by changeFPCCToANDAArch64CC(), and changeVectorFPCCToAArch64CC().
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Convert a DAG fp condition code to an AArch64 CC.
This differs from changeFPCCToAArch64CC in that it returns cond codes that should be AND'ed instead of OR'ed.
Definition at line 1200 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, assert(), changeFPCCToAArch64CC(), llvm::AArch64CC::LE, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETONE, llvm::ISD::SETUEQ, and llvm::AArch64CC::VC.
Referenced by emitConjunctionDisjunctionTreeRec().
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changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC
Definition at line 1109 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
Referenced by emitConjunctionDisjunctionTreeRec(), and getAArch64Cmp().
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changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions.
Fewer operations are available without a real NZCV register, so we have to use less efficient combinations to get the same effect.
Definition at line 1230 of file AArch64ISelLowering.cpp.
References changeFPCCToAArch64CC(), llvm::AArch64CC::GE, llvm::ISD::getSetCCInverse(), LLVM_FALLTHROUGH, llvm::AArch64CC::MI, llvm::ISD::SETO, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.
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Definition at line 9666 of file AArch64ISelLowering.cpp.
References llvm::abs(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::ISD::Constant, llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::VTSDNode::getVT(), llvm::MVT::i16, llvm::MVT::i8, llvm::ISD::LOAD, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::TargetConstant, and llvm::ISD::ZEXTLOAD.
Referenced by performCONDCombine().
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Definition at line 8763 of file AArch64ISelLowering.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getValueType(), and llvm::MVT::i64.
Referenced by performIntrinsicCombine().
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Definition at line 1265 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDS, llvm::ISD::AND, llvm::AArch64ISD::ANDS, assert(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::AArch64ISD::FCMP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::EVT::isFloatingPoint(), llvm::isNullConstant(), llvm::ISD::isUnsignedIntSetCC(), MVT_CC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SUB, and llvm::AArch64ISD::SUBS.
Referenced by emitConjunctionDisjunctionTreeRec(), and getAArch64Cmp().
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Definition at line 6852 of file AArch64ISelLowering.cpp.
References assert(), llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::dyn_cast(), llvm::AArch64CC::EQ, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::AArch64CC::GE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::EVT::isFloatingPoint(), llvm::AArch64CC::LE, LLVM_FALLTHROUGH, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64ISD::NOT, and resolveBuildVector().
An EXTR instruction is made up of two shifts, ORed together.
This helper searches for and classifies those shifts.
Definition at line 8063 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by tryCombineToEXTR().
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Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0.
Definition at line 7626 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CMGEz, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64Subtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::ISD::isBuildVectorAllOnes(), llvm::EVT::isVector(), and llvm::AArch64ISD::VASHR.
Referenced by performXorCombine().
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GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
Definition at line 5581 of file AArch64ISelLowering.cpp.
References assert(), llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EXT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::SelectionDAG::getConstant(), getExtFactor(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm_unreachable, PerfectShuffleTable, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, WidenVector(), llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.
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Definition at line 5683 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorTemplateCommon< T >::data(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::SDNode::isUndef(), llvm::makeArrayRef(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, and llvm::MVT::v8i8.
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Definition at line 1565 of file AArch64ISelLowering.cpp.
References C, changeIntCCToAArch64CC(), emitComparison(), emitConjunctionDisjunctionTree(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasNUsesOfValue(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, isLegalArithImmed(), llvm::ConstantSDNode::isNullValue(), llvm::ConstantSDNode::isOne(), MVT_CC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::ZEXTLOAD.
Referenced by LowerXOR(), and performSetccAddFolding().
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Definition at line 1676 of file AArch64ISelLowering.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::AArch64ISD::ADDS, assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64CC::HS, llvm::MVT::i32, llvm::MVT::i64, llvm_unreachable, llvm::AArch64CC::LO, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::AArch64CC::NE, llvm::ISD::SADDO, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSUBO, llvm::AArch64ISD::SUBS, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::AArch64CC::VS, and llvm::ISD::ZERO_EXTEND.
Referenced by LowerXALUO().
Definition at line 5745 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::MVT::f16, llvm::MVT::f64, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, and llvm_unreachable.
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Definition at line 4679 of file AArch64ISelLowering.cpp.
References llvm::MVT::f64, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::v1f32, llvm::MVT::v1f64, llvm::MVT::v2f32, llvm::MVT::v2f64, and llvm::MVT::v4f32.
Definition at line 2149 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i8, llvm::MVT::v4i16, and llvm::MVT::v4i8.
Referenced by addRequiredExtensionForVectorMULL().
getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction.
Definition at line 5088 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::EVT::getVectorElementType().
Referenced by GeneratePerfectShuffle(), and llvm::AArch64TargetLowering::ReconstructShuffle().
Definition at line 6045 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::Intrinsic::not_intrinsic, and llvm::Intrinsic::num_intrinsics.
Referenced by performExtendCombine(), and performIntrinsicCombine().
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Get a mask consisting of sequential integers starting from Start.
I.e. <Start, Start + 1, ..., Start + NumElts - 1>
Definition at line 7322 of file AArch64ISelLowering.cpp.
References llvm::ConstantVector::get(), llvm::IRBuilderBase::getInt32(), llvm::BitmaskEnumDetail::Mask(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64TargetLowering::lowerInterleavedStore().
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Definition at line 9978 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::tgtok::Bit, llvm::dyn_cast(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::XOR.
Referenced by performTBZCombine().
getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
Definition at line 6764 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().
Referenced by isVShiftLImm(), and isVShiftRImm().
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Definition at line 2249 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isSignExtended(), and llvm::ISD::SUB.
Referenced by LowerMUL().
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Definition at line 2260 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isZeroExtended(), and llvm::ISD::SUB.
Referenced by LowerMUL().
Definition at line 6028 of file AArch64ISelLowering.cpp.
References llvm::dyn_cast(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), and i.
Referenced by tryLowerToSLI().
Definition at line 5530 of file AArch64ISelLowering.cpp.
References E, llvm::EVT::getSizeInBits(), and llvm::EVT::getVectorNumElements().
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal(), and tryFormConcatFromShuffle().
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Definition at line 9769 of file AArch64ISelLowering.cpp.
References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::NV, llvm::AArch64CC::PL, llvm::ISD::SEXTLOAD, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
Referenced by performCONDCombine().
Definition at line 8462 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().
Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().
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Definition at line 2183 of file AArch64ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, C, llvm::SDNode::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::isIntN(), llvm::isUIntN(), and llvm::SDNode::op_values().
Referenced by isSignExtended(), and isZeroExtended().
Definition at line 5335 of file AArch64ISelLowering.cpp.
References llvm::ArrayRef< T >::end(), llvm::find_if(), llvm::EVT::getVectorNumElements(), llvm::APInt::getZExtValue(), and llvm::APInt::logBase2().
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Definition at line 5491 of file AArch64ISelLowering.cpp.
References i, and llvm::ArrayRef< T >::size().
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Definition at line 1260 of file AArch64ISelLowering.cpp.
Referenced by getAArch64Cmp().
isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize.
(The order of the elements within each block of the vector is reversed.)
Definition at line 5376 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and i.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one.
SetCCInfo is filled accordingly.
Definition at line 8503 of file AArch64ISelLowering.cpp.
References SetCCInfo::AArch64, GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, llvm::dyn_cast(), SetCCInfo::Generic, llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, llvm::ConstantSDNode::isOne(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, llvm::ISD::SETCC, and std::swap().
Referenced by isSetCCOrZExtSetCC().
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Definition at line 8546 of file AArch64ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), isSetCC(), and llvm::ISD::ZERO_EXTEND.
Referenced by performSetccAddFolding().
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Definition at line 2233 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), and llvm::ISD::SIGN_EXTEND.
Referenced by isAddSubSExt(), LowerMUL(), and performMulCombine().
Definition at line 5304 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), and i.
isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
Definition at line 5480 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 5430 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
Definition at line 5461 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), and i.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 5417 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), and i.
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.
Definition at line 6784 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
The value must be in the range: 1 <= Value <= ElementBits for a right shift; or
Definition at line 6795 of file AArch64ISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
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Definition at line 2241 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOpcode(), isExtendedBUILD_VECTOR(), and llvm::ISD::ZERO_EXTEND.
Referenced by isAddSubZExt(), LowerMUL(), and performMulCombine().
isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
Definition at line 5444 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
Definition at line 5403 of file AArch64ISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by llvm::AArch64TargetLowering::isShuffleMaskLegal().
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Definition at line 1855 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADCS, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::AArch64ISD::ADDS, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, llvm::AArch64ISD::SBCS, llvm::ISD::SUBC, llvm::ISD::SUBE, and llvm::AArch64ISD::SUBS.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 2134 of file AArch64ISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::MVT::f16, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::i16, and llvm::MVT::i32.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 2271 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isAddSubSExt(), isAddSubZExt(), llvm::EVT::isInteger(), isSignExtended(), isZeroExtended(), skipExtensionForVectorMULL(), llvm::AArch64ISD::SMULL, std::swap(), llvm::AArch64ISD::UMULL, and llvm::MVT::v2i64.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 1922 of file AArch64ISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::MVT::i32, llvm::MVT::Other, and llvm::AArch64ISD::PREFETCH.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 1976 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::MipsISD::Ext, llvm::MVT::f16, llvm::MVT::f32, llvm::ISD::FP_EXTEND, llvm::MVT::getFloatingPointVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), and llvm::ISD::TRUNCATE.
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Definition at line 2042 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::ISD::FP_ROUND, llvm::MVT::getFloatingPointVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::tgtok::In, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, and llvm::ISD::ZERO_EXTEND.
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Definition at line 1891 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CSEL, getAArch64XALUOOp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::TargetLoweringBase::isTypeLegal(), and llvm::ISD::MERGE_VALUES.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Definition at line 1796 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::CSEL, llvm::dyn_cast(), getAArch64Cmp(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::ConstantSDNode::isAllOnesValue(), llvm::ConstantSDNode::isNullValue(), Other, llvm::ISD::SELECT_CC, std::swap(), and llvm::ISD::XOR.
Referenced by llvm::AArch64TargetLowering::LowerOperation().
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Return true if we might ever do TCO for calls with this calling convention.
Definition at line 2832 of file AArch64ISelLowering.cpp.
References llvm::CallingConv::C, canGuaranteeTCO(), llvm::CallingConv::PreserveMost, and llvm::CallingConv::Swift.
Definition at line 7436 of file AArch64ISelLowering.cpp.
Referenced by llvm::AArch64TargetLowering::getOptimalMemOpType().
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NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.
Definition at line 5095 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().
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Definition at line 6227 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::i32, llvm::EVT::isFloatingPoint(), llvm::SDNode::ops(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
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Target-specific DAG combine for the across vector add reduction.
This function specifically handles the final clean-up step of the vector add reduction produced by the LoopVectorizer. It is the log2-shuffle pattern, which adds all elements of a vector together. For example, for a <4 x i32> vector : %1 = vector_shuffle %0, <2,3,u,u> %2 = add %0, %1 %3 = vector_shuffle %2, <1,u,u,u> %4 = add %2, %3 result = extract_vector_elt %4, 0 becomes : %0 = uaddv %0 result = extract_vector_elt %0, 0
Definition at line 9501 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::isNullConstant(), llvm::EVT::isVector(), and tryMatchAcrossLaneShuffleForReduction().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Target-specific DAG combine for the across vector min/max reductions.
This function specifically handles the final clean-up step of the vector min/max reductions produced by the LoopVectorizer. It is the log2-shuffle pattern, which narrows down and finds the final min/max value from all elements of the vector. For example, for a <16 x i8> vector : svn0 = vector_shuffle %0, undef<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> smax0 = smax arr, svn0 svn1 = vector_shuffle smax0, undef<4,5,6,7,u,u,u,u,u,u,u,u,u,u,u,u> smax1 = smax smax0, svn1 svn2 = vector_shuffle smax1, undef<2,3,u,u,u,u,u,u,u,u,u,u,u,u,u,u> smax2 = smax smax1, svn2 svn3 = vector_shuffle smax2, undef<1,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u> sc = setcc smax2, svn3, gt n0 = extract_vector_elt sc, #0 n1 = extract_vector_elt smax2, #0 n2 = extract_vector_elt $smax2, #1 result = select n0, n1, n2 becomes : %1 = smaxv %0 result = extract_vector_elt %1, 0
Definition at line 9402 of file AArch64ISelLowering.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isVector(), llvm::ISD::SETCC, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SMAX, llvm::ISD::SMIN, tryMatchAcrossLaneShuffleForReduction(), llvm::ISD::UMAX, and llvm::ISD::UMIN.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 8609 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::is128BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractSubvector(), performSetccAddFolding(), llvm::ISD::SIGN_EXTEND, tryExtendDUPToExtractHigh(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 8218 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::dbgs(), DEBUG, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i32, llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::SDNode::isMachineOpcode(), llvm::EVT::isVector(), llvm::Sched::Source, and SubReg.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 9919 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::ADDS, assert(), llvm::ISD::BR, llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::AArch64CC::EQ, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasNUsesOfValue(), llvm::MVT::i32, llvm::MVT::i64, llvm::isNullConstant(), llvm::AArch64CC::NE, llvm::MVT::Other, performCONDCombine(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::AArch64ISD::SUBS, and std::swap().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 8284 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::dbgs(), DEBUG, llvm::AArch64ISD::DUPLANE64, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), i, llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::MVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::TRUNCATE, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v8i16, and WidenVector().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 9845 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, checkValueWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), isEquivalentMaskless(), llvm::SelectionDAG::ReplaceAllUsesWith(), and llvm::AArch64ISD::SUBS.
Referenced by performBRCONDCombine(), and llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 8829 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), getIntrinsicID(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::MipsISD::Hi, llvm::MVT::i64, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MipsISD::Lo, tryCombineLongOpWithDup(), and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Fold a floating-point divide by power of two into fixed-point to floating-point conversion.
Definition at line 7994 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i32, llvm::MVT::v4i64, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Fold a floating-point multiply by power of two into floating-point to fixed-point conversion.
Definition at line 7922 of file AArch64ISelLowering.cpp.
References assert(), llvm::tgtok::Bits, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::TRUNCATE, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4i32, and llvm::MVT::v4i64.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 7650 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::AArch64ISD::CSEL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i32, llvm::EVT::isInteger(), llvm::AArch64CC::PL, llvm::ISD::SRA, llvm::ISD::SUB, llvm::AArch64ISD::SUBS, and llvm::ISD::XOR.
Referenced by performXorCombine().
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Definition at line 8773 of file AArch64ISelLowering.cpp.
References combineAcrossLanesIntrinsic(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FMAXNAN, llvm::ISD::FMAXNUM, llvm::ISD::FMINNAN, llvm::ISD::FMINNUM, getIntrinsicID(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::AArch64ISD::SADDV, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMINV, tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryCombineShiftImm(), llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UMAXV, and llvm::AArch64ISD::UMINV.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 7881 of file AArch64ISelLowering.cpp.
References llvm::MVT::f64, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::AArch64Subtarget::hasNEON(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalLoad(), isVolatile(), llvm::SPII::Load, performVectorCompareAndMaskUnaryOpCombine(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SINT_TO_FP, llvm::AArch64ISD::SITOF, and llvm::AArch64ISD::UITOF.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 7735 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::APInt::ashr(), assert(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::APInt::isPowerOf2(), isSignExtended(), isZeroExtended(), llvm::APInt::logBase2(), llvm::ISD::SHL, llvm::ISD::SUB, and llvm::SDNode::use_begin().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates.
Definition at line 9533 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), i, llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::SDNode::isPredecessorOf(), llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm_unreachable, llvm::makeArrayRef(), N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, llvm::AArch64ISD::ST4post, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
Get rid of unnecessary NVCASTs (that don't change the type).
Definition at line 10166 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), and llvm::SDNode::getValueType().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 8172 of file AArch64ISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::isTypeLegal(), tryCombineToBSL(), and tryCombineToEXTR().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R.
Definition at line 9142 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getResNo(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::SDNode::isPredecessorOf(), llvm::ARM_MB::LD, llvm::AArch64ISD::LD1DUPpost, llvm::AArch64ISD::LD1LANEpost, llvm::ISD::LOAD, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SDNode::use_begin(), and llvm::SDNode::use_end().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar.
This replaces any scalar setcc in the above pattern with a vector one followed by a DUP shuffle on the result.
Definition at line 10105 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::EVT::changeVectorElementTypeToInteger(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::i1, llvm::MVT::i32, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::ISD::SETCC.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 8559 of file AArch64ISelLowering.cpp.
References SetCCInfo::AArch64, llvm::ISD::ADD, assert(), GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, SetCCInfo::Generic, getAArch64Cmp(), llvm::SelectionDAG::getConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, isSetCCOrZExtSetCC(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, and std::swap().
Referenced by performAddSubLongCombine().
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Definition at line 8190 of file AArch64ISelLowering.cpp.
References llvm::ISD::BSWAP, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::MaskedValueIsZero(), and llvm::ISD::ROTR.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 9256 of file AArch64ISelLowering.cpp.
References llvm::SDNode::getOperand(), performTBISimplification(), Split(), splitStores(), and llvm::AArch64Subtarget::supportsAddressTopByteIgnored().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Simplify given that the top byte of it is ignored by HW during address translation.
Definition at line 9241 of file AArch64ISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), and llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine(), and performSTORECombine().
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Definition at line 10045 of file AArch64ISelLowering.cpp.
References assert(), llvm::tgtok::Bit, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getTestBitOperand(), llvm::MVT::i64, llvm::MVT::Other, llvm::AArch64ISD::TBNZ, and llvm::AArch64ISD::TBZ.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 7835 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::isVector(), and llvm::ISD::SETCC.
Referenced by performIntToFpCombine().
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Definition at line 10076 of file AArch64ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i1, llvm::ISD::SETCC, and llvm::ISD::VSELECT.
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 7677 of file AArch64ISelLowering.cpp.
References foldVectorXorShiftIntoCmp(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), and performIntegerAbsCombine().
Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().
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Definition at line 10385 of file AArch64ISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::MVT::f16, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::ISD::TRUNCATE.
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Definition at line 10425 of file AArch64ISelLowering.cpp.
References llvm::MachineFunction::allocateMemRefsArray(), assert(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and splitInt128().
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Definition at line 10402 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDNode::getValueType(), llvm::MipsISD::Hi, llvm::MipsISD::Lo, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and llvm::SelectionDAG::SplitVectorOperand().
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Replace a splat of a scalar to a vector store by scalar stores of the scalar value.
The load store optimizer pass will merge them to store pair stores. This has better performance than a splat of the scalar followed by a split vector store. Even if the stores are not merged it is four stores vs a dup, followed by an ext.b and two stores.
Definition at line 9020 of file AArch64ISelLowering.cpp.
References llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), I, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), and splitStoreSplat().
Referenced by splitStores().
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Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.
The load store optimizer pass will merge them to store pair stores. This should be better than a movi to create the vector zero followed by a vector store if the zero constant is not re-used, since one instructions and one register live range will be removed.
For example, the final generated code should be:
stp xzr, xzr, [x0]
instead of:
movi v0.2d, #0 str q0, [x0]
Definition at line 8971 of file AArch64ISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::StoreSDNode::getBasePtr(), llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::EVT::getSizeInBits(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), I, llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isNullConstant(), llvm::isNullFPConstant(), and splitStoreSplat().
Referenced by splitStores().
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Definition at line 5910 of file AArch64ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), i, llvm::BuildVectorSDNode::isConstantSplat(), and llvm::APInt::zextOrTrunc().
Referenced by EmitVectorComparison().
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Definition at line 2209 of file AArch64ISelLowering.cpp.
References addRequiredExtensionForVectorMULL(), assert(), llvm::ISD::BUILD_VECTOR, C, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::MVT::getVectorVT(), i, llvm::MVT::i32, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by LowerMUL().
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Definition at line 10416 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i128, llvm::MVT::i64, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
Referenced by ReplaceCMP_SWAP_128Results().
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Definition at line 9068 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i64, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::AArch64Subtarget::isMisaligned128StoreSlow(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, llvm::Function::optForMinSize(), replaceSplatVectorStore(), replaceZeroVectorStore(), and llvm::MVT::v2i64.
Referenced by performSTORECombine().
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Definition at line 8927 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::MemSDNode::getAlignment(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::i64, and llvm::MinAlign().
Referenced by replaceSplatVectorStore(), and replaceZeroVectorStore().
| STATISTIC | ( | NumTailCalls | , |
| "Number of tail calls" | |||
| ) |
| STATISTIC | ( | NumShiftInserts | , |
| "Number of vector shift inserts" | |||
| ) |
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Definition at line 8750 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::BitmaskEnumDetail::Mask().
Referenced by performIntrinsicCombine().
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Definition at line 8365 of file AArch64ISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm_unreachable, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, and llvm::MVT::v4i32.
Referenced by performIntrinsicCombine().
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Definition at line 8658 of file AArch64ISelLowering.cpp.
References assert(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), isEssentiallyExtractSubvector(), and tryExtendDUPToExtractHigh().
Referenced by performExtendCombine(), and performIntrinsicCombine().
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Definition at line 8687 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::APInt::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::BuildVectorSDNode::isConstantSplat(), llvm_unreachable, llvm::AArch64ISD::SQSHL_I, llvm::AArch64ISD::SQSHLU_I, llvm::AArch64ISD::SRSHR_I, llvm::AArch64ISD::UQSHL_I, and llvm::AArch64ISD::URSHR_I.
Referenced by performIntrinsicCombine().
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Definition at line 8125 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::tgtok::Bits, llvm::AArch64ISD::BSL, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), i, and llvm::EVT::isVector().
Referenced by performORCombine().
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EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair.
This function looks for the pattern: (or (shl VAL1, N), (srl VAL2, #RegWidth-N)) and replaces it with an EXTR. Can't quite be done in TableGen because the two immediates aren't independent.
Definition at line 8085 of file AArch64ISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AArch64ISD::EXTR, findEXTRHalf(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::OR, and std::swap().
Referenced by performORCombine().
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Definition at line 8427 of file AArch64ISelLowering.cpp.
References llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i64, llvm::MVT::is64BitVector(), llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, and llvm::SDNode::ops().
Referenced by performAddSubLongCombine(), and tryCombineLongOpWithDup().
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Definition at line 5550 of file AArch64ISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::i64, and isConcatMask().
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Definition at line 6063 of file AArch64ISelLowering.cpp.
References llvm::ISD::AND, llvm::APIntOps::And(), llvm::dbgs(), DEBUG, llvm::SDNode::dump(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, isAllConstantBuildVector(), llvm::EVT::isVector(), llvm::AArch64ISD::VLSHR, llvm::AArch64ISD::VSHL, X, and Y.
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This function handles the log2-shuffle pattern produced by the.
LoopVectorizer for the across vector reduction. It consists of log2(NumVectorElements) steps and, in each step, 2^(s) elements are reduced, where s is an induction variable from 0 to log2(NumVectorElements).
Definition at line 9275 of file AArch64ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), i, llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::isVector(), llvm_unreachable, llvm::APInt::logBase2(), llvm::ISD::SMAX, llvm::AArch64ISD::SMAXV, llvm::ISD::SMIN, llvm::AArch64ISD::SMINV, llvm::AArch64ISD::UADDV, llvm::ISD::UMAX, llvm::AArch64ISD::UMAXV, llvm::ISD::UMIN, llvm::AArch64ISD::UMINV, and llvm::ISD::VECTOR_SHUFFLE.
Referenced by performAcrossLaneAddReductionCombine(), and performAcrossLaneMinMaxReductionCombine().
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WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class.
Definition at line 5075 of file AArch64ISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::i32, and llvm::ISD::INSERT_SUBVECTOR.
Referenced by GeneratePerfectShuffle(), and performConcatVectorsCombine().
| cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false)) |
Referenced by llvm::AArch64MCInstLower::lowerSymbolOperandELF().
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Value type used for condition codes.
Definition at line 108 of file AArch64ISelLowering.cpp.
Referenced by emitComparison(), emitConditionalComparison(), and getAArch64Cmp().
1.8.6