LLVM  4.0.0
SystemZInstrInfo.cpp
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1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SystemZInstrInfo.h"
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZTargetMachine.h"
20 
21 using namespace llvm;
22 
23 #define GET_INSTRINFO_CTOR_DTOR
24 #define GET_INSTRMAP_INFO
25 #include "SystemZGenInstrInfo.inc"
26 
27 // Return a mask with Count low bits set.
28 static uint64_t allOnes(unsigned int Count) {
29  return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
30 }
31 
32 // Reg should be a 32-bit GPR. Return true if it is a high register rather
33 // than a low register.
34 static bool isHighReg(unsigned int Reg) {
35  if (SystemZ::GRH32BitRegClass.contains(Reg))
36  return true;
37  assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
38  return false;
39 }
40 
41 // Pin the vtable to this file.
42 void SystemZInstrInfo::anchor() {}
43 
45  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
46  RI(), STI(sti) {
47 }
48 
49 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
50 // each having the opcode given by NewOpcode.
51 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
52  unsigned NewOpcode) const {
53  MachineBasicBlock *MBB = MI->getParent();
54  MachineFunction &MF = *MBB->getParent();
55 
56  // Get two load or store instructions. Use the original instruction for one
57  // of them (arbitrarily the second here) and create a clone for the other.
58  MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
59  MBB->insert(MI, EarlierMI);
60 
61  // Set up the two 64-bit registers.
62  MachineOperand &HighRegOp = EarlierMI->getOperand(0);
63  MachineOperand &LowRegOp = MI->getOperand(0);
64  HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
65  LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
66 
67  // The address in the first (high) instruction is already correct.
68  // Adjust the offset in the second (low) instruction.
69  MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
70  MachineOperand &LowOffsetOp = MI->getOperand(2);
71  LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
72 
73  // Clear the kill flags for the base and index registers in the first
74  // instruction.
75  EarlierMI->getOperand(1).setIsKill(false);
76  EarlierMI->getOperand(3).setIsKill(false);
77 
78  // Set the opcodes.
79  unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
80  unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
81  assert(HighOpcode && LowOpcode && "Both offsets should be in range");
82 
83  EarlierMI->setDesc(get(HighOpcode));
84  MI->setDesc(get(LowOpcode));
85 }
86 
87 // Split ADJDYNALLOC instruction MI.
88 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
89  MachineBasicBlock *MBB = MI->getParent();
90  MachineFunction &MF = *MBB->getParent();
91  MachineFrameInfo &MFFrame = MF.getFrameInfo();
92  MachineOperand &OffsetMO = MI->getOperand(2);
93 
94  uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
96  OffsetMO.getImm());
97  unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
98  assert(NewOpcode && "No support for huge argument lists yet");
99  MI->setDesc(get(NewOpcode));
100  OffsetMO.setImm(Offset);
101 }
102 
103 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
104 // if the first operand is a low GR32 and HighOpcode if the first operand
105 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
106 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
107 // MI has the same kind of operand as LowOpcode, so needs to be converted
108 // if HighOpcode is used.
109 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
110  unsigned HighOpcode,
111  bool ConvertHigh) const {
112  unsigned Reg = MI.getOperand(0).getReg();
113  bool IsHigh = isHighReg(Reg);
114  MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
115  if (IsHigh && ConvertHigh)
116  MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
117 }
118 
119 // MI is a three-operand RIE-style pseudo instruction. Replace it with
120 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
121 // followed by HighOpcode or LowOpcode, depending on whether the target
122 // is a high or low GR32.
123 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
124  unsigned LowOpcodeK,
125  unsigned HighOpcode) const {
126  unsigned DestReg = MI.getOperand(0).getReg();
127  unsigned SrcReg = MI.getOperand(1).getReg();
128  bool DestIsHigh = isHighReg(DestReg);
129  bool SrcIsHigh = isHighReg(SrcReg);
130  if (!DestIsHigh && !SrcIsHigh)
131  MI.setDesc(get(LowOpcodeK));
132  else {
133  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
134  SystemZ::LR, 32, MI.getOperand(1).isKill());
135  MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
136  MI.getOperand(1).setReg(DestReg);
137  MI.tieOperands(0, 1);
138  }
139 }
140 
141 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
142 // if the first operand is a low GR32 and HighOpcode if the first operand
143 // is a high GR32.
144 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
145  unsigned HighOpcode) const {
146  unsigned Reg = MI.getOperand(0).getReg();
147  unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
148  MI.getOperand(2).getImm());
149  MI.setDesc(get(Opcode));
150 }
151 
152 // MI is a load-on-condition pseudo instruction with a single register
153 // (source or destination) operand. Replace it with LowOpcode if the
154 // register is a low GR32 and HighOpcode if the register is a high GR32.
155 void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
156  unsigned HighOpcode) const {
157  unsigned Reg = MI.getOperand(0).getReg();
158  unsigned Opcode = isHighReg(Reg) ? HighOpcode : LowOpcode;
159  MI.setDesc(get(Opcode));
160 }
161 
162 // MI is a load-register-on-condition pseudo instruction. Replace it with
163 // LowOpcode if source and destination are both low GR32s and HighOpcode if
164 // source and destination are both high GR32s.
165 void SystemZInstrInfo::expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
166  unsigned HighOpcode) const {
167  unsigned DestReg = MI.getOperand(0).getReg();
168  unsigned SrcReg = MI.getOperand(2).getReg();
169  bool DestIsHigh = isHighReg(DestReg);
170  bool SrcIsHigh = isHighReg(SrcReg);
171 
172  if (!DestIsHigh && !SrcIsHigh)
173  MI.setDesc(get(LowOpcode));
174  else if (DestIsHigh && SrcIsHigh)
175  MI.setDesc(get(HighOpcode));
176 
177  // If we were unable to implement the pseudo with a single instruction, we
178  // need to convert it back into a branch sequence. This cannot be done here
179  // since the caller of expandPostRAPseudo does not handle changes to the CFG
180  // correctly. This change is defered to the SystemZExpandPseudo pass.
181 }
182 
183 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
184 // of one GRX32 into another. Replace it with LowOpcode if both operands
185 // are low registers, otherwise use RISB[LH]G.
186 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
187  unsigned Size) const {
188  emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
189  MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
190  Size, MI.getOperand(1).isKill());
191  MI.eraseFromParent();
192 }
193 
194 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
195  MachineBasicBlock *MBB = MI->getParent();
196  MachineFunction &MF = *MBB->getParent();
197  const unsigned Reg = MI->getOperand(0).getReg();
198 
199  // Conveniently, all 4 instructions are cloned from LOAD_STACK_GUARD,
200  // so they already have operand 0 set to reg.
201 
202  // ear <reg>, %a0
203  MachineInstr *Ear1MI = MF.CloneMachineInstr(MI);
204  MBB->insert(MI, Ear1MI);
205  Ear1MI->setDesc(get(SystemZ::EAR));
206  MachineInstrBuilder(MF, Ear1MI).addReg(SystemZ::A0);
207 
208  // sllg <reg>, <reg>, 32
209  MachineInstr *SllgMI = MF.CloneMachineInstr(MI);
210  MBB->insert(MI, SllgMI);
211  SllgMI->setDesc(get(SystemZ::SLLG));
212  MachineInstrBuilder(MF, SllgMI).addReg(Reg).addReg(0).addImm(32);
213 
214  // ear <reg>, %a1
215  MachineInstr *Ear2MI = MF.CloneMachineInstr(MI);
216  MBB->insert(MI, Ear2MI);
217  Ear2MI->setDesc(get(SystemZ::EAR));
218  MachineInstrBuilder(MF, Ear2MI).addReg(SystemZ::A1);
219 
220  // lg <reg>, 40(<reg>)
221  MI->setDesc(get(SystemZ::LG));
222  MachineInstrBuilder(MF, MI).addReg(Reg).addImm(40).addReg(0);
223 }
224 
225 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
226 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
227 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
228 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
229 // KillSrc is true if this move is the last use of SrcReg.
230 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
232  const DebugLoc &DL, unsigned DestReg,
233  unsigned SrcReg, unsigned LowLowOpcode,
234  unsigned Size, bool KillSrc) const {
235  unsigned Opcode;
236  bool DestIsHigh = isHighReg(DestReg);
237  bool SrcIsHigh = isHighReg(SrcReg);
238  if (DestIsHigh && SrcIsHigh)
239  Opcode = SystemZ::RISBHH;
240  else if (DestIsHigh && !SrcIsHigh)
241  Opcode = SystemZ::RISBHL;
242  else if (!DestIsHigh && SrcIsHigh)
243  Opcode = SystemZ::RISBLH;
244  else {
245  BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
246  .addReg(SrcReg, getKillRegState(KillSrc));
247  return;
248  }
249  unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
250  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
251  .addReg(DestReg, RegState::Undef)
252  .addReg(SrcReg, getKillRegState(KillSrc))
253  .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
254 }
255 
256 
258  bool NewMI,
259  unsigned OpIdx1,
260  unsigned OpIdx2) const {
261  auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
262  if (NewMI)
263  return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
264  return MI;
265  };
266 
267  switch (MI.getOpcode()) {
268  case SystemZ::LOCRMux:
269  case SystemZ::LOCFHR:
270  case SystemZ::LOCR:
271  case SystemZ::LOCGR: {
272  auto &WorkingMI = cloneIfNew(MI);
273  // Invert condition.
274  unsigned CCValid = WorkingMI.getOperand(3).getImm();
275  unsigned CCMask = WorkingMI.getOperand(4).getImm();
276  WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
277  return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
278  OpIdx1, OpIdx2);
279  }
280  default:
281  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
282  }
283 }
284 
285 
286 // If MI is a simple load or store for a frame object, return the register
287 // it loads or stores and set FrameIndex to the index of the frame object.
288 // Return 0 otherwise.
289 //
290 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
291 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
292  unsigned Flag) {
293  const MCInstrDesc &MCID = MI.getDesc();
294  if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
295  MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
296  FrameIndex = MI.getOperand(1).getIndex();
297  return MI.getOperand(0).getReg();
298  }
299  return 0;
300 }
301 
303  int &FrameIndex) const {
304  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
305 }
306 
308  int &FrameIndex) const {
309  return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
310 }
311 
313  int &DestFrameIndex,
314  int &SrcFrameIndex) const {
315  // Check for MVC 0(Length,FI1),0(FI2)
316  const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
317  if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
318  MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
319  MI.getOperand(4).getImm() != 0)
320  return false;
321 
322  // Check that Length covers the full slots.
323  int64_t Length = MI.getOperand(2).getImm();
324  unsigned FI1 = MI.getOperand(0).getIndex();
325  unsigned FI2 = MI.getOperand(3).getIndex();
326  if (MFI.getObjectSize(FI1) != Length ||
327  MFI.getObjectSize(FI2) != Length)
328  return false;
329 
330  DestFrameIndex = FI1;
331  SrcFrameIndex = FI2;
332  return true;
333 }
334 
336  MachineBasicBlock *&TBB,
337  MachineBasicBlock *&FBB,
339  bool AllowModify) const {
340  // Most of the code and comments here are boilerplate.
341 
342  // Start from the bottom of the block and work up, examining the
343  // terminator instructions.
345  while (I != MBB.begin()) {
346  --I;
347  if (I->isDebugValue())
348  continue;
349 
350  // Working from the bottom, when we see a non-terminator instruction, we're
351  // done.
352  if (!isUnpredicatedTerminator(*I))
353  break;
354 
355  // A terminator that isn't a branch can't easily be handled by this
356  // analysis.
357  if (!I->isBranch())
358  return true;
359 
360  // Can't handle indirect branches.
362  if (!Branch.Target->isMBB())
363  return true;
364 
365  // Punt on compound branches.
366  if (Branch.Type != SystemZII::BranchNormal)
367  return true;
368 
369  if (Branch.CCMask == SystemZ::CCMASK_ANY) {
370  // Handle unconditional branches.
371  if (!AllowModify) {
372  TBB = Branch.Target->getMBB();
373  continue;
374  }
375 
376  // If the block has any instructions after a JMP, delete them.
377  while (std::next(I) != MBB.end())
378  std::next(I)->eraseFromParent();
379 
380  Cond.clear();
381  FBB = nullptr;
382 
383  // Delete the JMP if it's equivalent to a fall-through.
384  if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
385  TBB = nullptr;
386  I->eraseFromParent();
387  I = MBB.end();
388  continue;
389  }
390 
391  // TBB is used to indicate the unconditinal destination.
392  TBB = Branch.Target->getMBB();
393  continue;
394  }
395 
396  // Working from the bottom, handle the first conditional branch.
397  if (Cond.empty()) {
398  // FIXME: add X86-style branch swap
399  FBB = TBB;
400  TBB = Branch.Target->getMBB();
403  continue;
404  }
405 
406  // Handle subsequent conditional branches.
407  assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
408 
409  // Only handle the case where all conditional branches branch to the same
410  // destination.
411  if (TBB != Branch.Target->getMBB())
412  return true;
413 
414  // If the conditions are the same, we can leave them alone.
415  unsigned OldCCValid = Cond[0].getImm();
416  unsigned OldCCMask = Cond[1].getImm();
417  if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
418  continue;
419 
420  // FIXME: Try combining conditions like X86 does. Should be easy on Z!
421  return false;
422  }
423 
424  return false;
425 }
426 
428  int *BytesRemoved) const {
429  assert(!BytesRemoved && "code size not handled");
430 
431  // Most of the code and comments here are boilerplate.
433  unsigned Count = 0;
434 
435  while (I != MBB.begin()) {
436  --I;
437  if (I->isDebugValue())
438  continue;
439  if (!I->isBranch())
440  break;
441  if (!getBranchInfo(*I).Target->isMBB())
442  break;
443  // Remove the branch.
444  I->eraseFromParent();
445  I = MBB.end();
446  ++Count;
447  }
448 
449  return Count;
450 }
451 
454  assert(Cond.size() == 2 && "Invalid condition");
455  Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
456  return false;
457 }
458 
460  MachineBasicBlock *TBB,
461  MachineBasicBlock *FBB,
463  const DebugLoc &DL,
464  int *BytesAdded) const {
465  // In this function we output 32-bit branches, which should always
466  // have enough range. They can be shortened and relaxed by later code
467  // in the pipeline, if desired.
468 
469  // Shouldn't be a fall through.
470  assert(TBB && "insertBranch must not be told to insert a fallthrough");
471  assert((Cond.size() == 2 || Cond.size() == 0) &&
472  "SystemZ branch conditions have one component!");
473  assert(!BytesAdded && "code size not handled");
474 
475  if (Cond.empty()) {
476  // Unconditional branch?
477  assert(!FBB && "Unconditional branch with multiple successors!");
478  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
479  return 1;
480  }
481 
482  // Conditional branch.
483  unsigned Count = 0;
484  unsigned CCValid = Cond[0].getImm();
485  unsigned CCMask = Cond[1].getImm();
486  BuildMI(&MBB, DL, get(SystemZ::BRC))
487  .addImm(CCValid).addImm(CCMask).addMBB(TBB);
488  ++Count;
489 
490  if (FBB) {
491  // Two-way Conditional branch. Insert the second branch.
492  BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
493  ++Count;
494  }
495  return Count;
496 }
497 
498 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
499  unsigned &SrcReg2, int &Mask,
500  int &Value) const {
501  assert(MI.isCompare() && "Caller should have checked for a comparison");
502 
503  if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
504  MI.getOperand(1).isImm()) {
505  SrcReg = MI.getOperand(0).getReg();
506  SrcReg2 = 0;
507  Value = MI.getOperand(1).getImm();
508  Mask = ~0;
509  return true;
510  }
511 
512  return false;
513 }
514 
515 // If Reg is a virtual register, return its definition, otherwise return null.
516 static MachineInstr *getDef(unsigned Reg,
517  const MachineRegisterInfo *MRI) {
519  return nullptr;
520  return MRI->getUniqueVRegDef(Reg);
521 }
522 
523 // Return true if MI is a shift of type Opcode by Imm bits.
524 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
525  return (MI->getOpcode() == Opcode &&
526  !MI->getOperand(2).getReg() &&
527  MI->getOperand(3).getImm() == Imm);
528 }
529 
530 // If the destination of MI has no uses, delete it as dead.
532  if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
533  MI->eraseFromParent();
534 }
535 
536 // Compare compares SrcReg against zero. Check whether SrcReg contains
537 // the result of an IPM sequence whose input CC survives until Compare,
538 // and whether Compare is therefore redundant. Delete it and return
539 // true if so.
540 static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg,
541  const MachineRegisterInfo *MRI,
542  const TargetRegisterInfo *TRI) {
543  MachineInstr *LGFR = nullptr;
544  MachineInstr *RLL = getDef(SrcReg, MRI);
545  if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
546  LGFR = RLL;
547  RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
548  }
549  if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
550  return false;
551 
552  MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
553  if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
554  return false;
555 
556  MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
557  if (!IPM || IPM->getOpcode() != SystemZ::IPM)
558  return false;
559 
560  // Check that there are no assignments to CC between the IPM and Compare,
561  if (IPM->getParent() != Compare.getParent())
562  return false;
563  MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare.getIterator();
564  for (++MBBI; MBBI != MBBE; ++MBBI) {
565  MachineInstr &MI = *MBBI;
566  if (MI.modifiesRegister(SystemZ::CC, TRI))
567  return false;
568  }
569 
570  Compare.eraseFromParent();
571  if (LGFR)
572  eraseIfDead(LGFR, MRI);
573  eraseIfDead(RLL, MRI);
574  eraseIfDead(SRL, MRI);
575  eraseIfDead(IPM, MRI);
576 
577  return true;
578 }
579 
581  MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask,
582  int Value, const MachineRegisterInfo *MRI) const {
583  assert(!SrcReg2 && "Only optimizing constant comparisons so far");
584  bool IsLogical = (Compare.getDesc().TSFlags & SystemZII::IsLogical) != 0;
585  return Value == 0 && !IsLogical &&
586  removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
587 }
588 
589 
592  unsigned TrueReg, unsigned FalseReg,
593  int &CondCycles, int &TrueCycles,
594  int &FalseCycles) const {
595  // Not all subtargets have LOCR instructions.
596  if (!STI.hasLoadStoreOnCond())
597  return false;
598  if (Pred.size() != 2)
599  return false;
600 
601  // Check register classes.
602  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
603  const TargetRegisterClass *RC =
604  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
605  if (!RC)
606  return false;
607 
608  // We have LOCR instructions for 32 and 64 bit general purpose registers.
609  if ((STI.hasLoadStoreOnCond2() &&
610  SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
611  SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
612  SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
613  CondCycles = 2;
614  TrueCycles = 2;
615  FalseCycles = 2;
616  return true;
617  }
618 
619  // Can't do anything else.
620  return false;
621 }
622 
625  const DebugLoc &DL, unsigned DstReg,
627  unsigned TrueReg,
628  unsigned FalseReg) const {
630  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
631 
632  assert(Pred.size() == 2 && "Invalid condition");
633  unsigned CCValid = Pred[0].getImm();
634  unsigned CCMask = Pred[1].getImm();
635 
636  unsigned Opc;
637  if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
638  if (STI.hasLoadStoreOnCond2())
639  Opc = SystemZ::LOCRMux;
640  else {
641  Opc = SystemZ::LOCR;
642  MRI.constrainRegClass(DstReg, &SystemZ::GR32BitRegClass);
643  }
644  } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC))
645  Opc = SystemZ::LOCGR;
646  else
647  llvm_unreachable("Invalid register class");
648 
649  BuildMI(MBB, I, DL, get(Opc), DstReg)
650  .addReg(FalseReg).addReg(TrueReg)
651  .addImm(CCValid).addImm(CCMask);
652 }
653 
655  unsigned Reg,
656  MachineRegisterInfo *MRI) const {
657  unsigned DefOpc = DefMI.getOpcode();
658  if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
659  DefOpc != SystemZ::LGHI)
660  return false;
661  if (DefMI.getOperand(0).getReg() != Reg)
662  return false;
663  int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
664 
665  unsigned UseOpc = UseMI.getOpcode();
666  unsigned NewUseOpc;
667  unsigned UseIdx;
668  int CommuteIdx = -1;
669  switch (UseOpc) {
670  case SystemZ::LOCRMux:
671  if (!STI.hasLoadStoreOnCond2())
672  return false;
673  NewUseOpc = SystemZ::LOCHIMux;
674  if (UseMI.getOperand(2).getReg() == Reg)
675  UseIdx = 2;
676  else if (UseMI.getOperand(1).getReg() == Reg)
677  UseIdx = 2, CommuteIdx = 1;
678  else
679  return false;
680  break;
681  case SystemZ::LOCGR:
682  if (!STI.hasLoadStoreOnCond2())
683  return false;
684  NewUseOpc = SystemZ::LOCGHI;
685  if (UseMI.getOperand(2).getReg() == Reg)
686  UseIdx = 2;
687  else if (UseMI.getOperand(1).getReg() == Reg)
688  UseIdx = 2, CommuteIdx = 1;
689  else
690  return false;
691  break;
692  default:
693  return false;
694  }
695 
696  if (CommuteIdx != -1)
697  if (!commuteInstruction(UseMI, false, CommuteIdx, UseIdx))
698  return false;
699 
700  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
701  UseMI.setDesc(get(NewUseOpc));
702  UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
703  if (DeleteDef)
704  DefMI.eraseFromParent();
705 
706  return true;
707 }
708 
710  unsigned Opcode = MI.getOpcode();
711  if (Opcode == SystemZ::Return ||
712  Opcode == SystemZ::Trap ||
713  Opcode == SystemZ::CallJG ||
714  Opcode == SystemZ::CallBR)
715  return true;
716  return false;
717 }
718 
721  unsigned NumCycles, unsigned ExtraPredCycles,
722  BranchProbability Probability) const {
723  // Avoid using conditional returns at the end of a loop (since then
724  // we'd need to emit an unconditional branch to the beginning anyway,
725  // making the loop body longer). This doesn't apply for low-probability
726  // loops (eg. compare-and-swap retry), so just decide based on branch
727  // probability instead of looping structure.
728  // However, since Compare and Trap instructions cost the same as a regular
729  // Compare instruction, we should allow the if conversion to convert this
730  // into a Conditional Compare regardless of the branch probability.
731  if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
732  MBB.succ_empty() && Probability < BranchProbability(1, 8))
733  return false;
734  // For now only convert single instructions.
735  return NumCycles == 1;
736 }
737 
740  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
741  MachineBasicBlock &FMBB,
742  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
743  BranchProbability Probability) const {
744  // For now avoid converting mutually-exclusive cases.
745  return false;
746 }
747 
750  BranchProbability Probability) const {
751  // For now only duplicate single instructions.
752  return NumCycles == 1;
753 }
754 
756  MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
757  assert(Pred.size() == 2 && "Invalid condition");
758  unsigned CCValid = Pred[0].getImm();
759  unsigned CCMask = Pred[1].getImm();
760  assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
761  unsigned Opcode = MI.getOpcode();
762  if (Opcode == SystemZ::Trap) {
763  MI.setDesc(get(SystemZ::CondTrap));
765  .addImm(CCValid).addImm(CCMask)
766  .addReg(SystemZ::CC, RegState::Implicit);
767  return true;
768  }
769  if (Opcode == SystemZ::Return) {
770  MI.setDesc(get(SystemZ::CondReturn));
772  .addImm(CCValid).addImm(CCMask)
773  .addReg(SystemZ::CC, RegState::Implicit);
774  return true;
775  }
776  if (Opcode == SystemZ::CallJG) {
777  MachineOperand FirstOp = MI.getOperand(0);
778  const uint32_t *RegMask = MI.getOperand(1).getRegMask();
779  MI.RemoveOperand(1);
780  MI.RemoveOperand(0);
781  MI.setDesc(get(SystemZ::CallBRCL));
783  .addImm(CCValid).addImm(CCMask)
784  .addOperand(FirstOp)
785  .addRegMask(RegMask)
786  .addReg(SystemZ::CC, RegState::Implicit);
787  return true;
788  }
789  if (Opcode == SystemZ::CallBR) {
790  const uint32_t *RegMask = MI.getOperand(0).getRegMask();
791  MI.RemoveOperand(0);
792  MI.setDesc(get(SystemZ::CallBCR));
794  .addImm(CCValid).addImm(CCMask)
795  .addRegMask(RegMask)
796  .addReg(SystemZ::CC, RegState::Implicit);
797  return true;
798  }
799  return false;
800 }
801 
804  const DebugLoc &DL, unsigned DestReg,
805  unsigned SrcReg, bool KillSrc) const {
806  // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
807  if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
808  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
809  RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
810  copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
811  RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
812  return;
813  }
814 
815  if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
816  emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
817  return;
818  }
819 
820  // Everything else needs only one instruction.
821  unsigned Opcode;
822  if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
823  Opcode = SystemZ::LGR;
824  else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
825  // For z13 we prefer LDR over LER to avoid partial register dependencies.
826  Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
827  else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
828  Opcode = SystemZ::LDR;
829  else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
830  Opcode = SystemZ::LXR;
831  else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
832  Opcode = SystemZ::VLR32;
833  else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
834  Opcode = SystemZ::VLR64;
835  else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
836  Opcode = SystemZ::VLR;
837  else if (SystemZ::AR32BitRegClass.contains(DestReg, SrcReg))
838  Opcode = SystemZ::CPYA;
839  else if (SystemZ::AR32BitRegClass.contains(DestReg) &&
840  SystemZ::GR32BitRegClass.contains(SrcReg))
841  Opcode = SystemZ::SAR;
842  else if (SystemZ::GR32BitRegClass.contains(DestReg) &&
843  SystemZ::AR32BitRegClass.contains(SrcReg))
844  Opcode = SystemZ::EAR;
845  else
846  llvm_unreachable("Impossible reg-to-reg copy");
847 
848  BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
849  .addReg(SrcReg, getKillRegState(KillSrc));
850 }
851 
853  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
854  bool isKill, int FrameIdx, const TargetRegisterClass *RC,
855  const TargetRegisterInfo *TRI) const {
856  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
857 
858  // Callers may expect a single instruction, so keep 128-bit moves
859  // together for now and lower them after register allocation.
860  unsigned LoadOpcode, StoreOpcode;
861  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
862  addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
863  .addReg(SrcReg, getKillRegState(isKill)),
864  FrameIdx);
865 }
866 
868  MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
869  int FrameIdx, const TargetRegisterClass *RC,
870  const TargetRegisterInfo *TRI) const {
871  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
872 
873  // Callers may expect a single instruction, so keep 128-bit moves
874  // together for now and lower them after register allocation.
875  unsigned LoadOpcode, StoreOpcode;
876  getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
877  addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
878  FrameIdx);
879 }
880 
881 // Return true if MI is a simple load or store with a 12-bit displacement
882 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
883 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
884  const MCInstrDesc &MCID = MI->getDesc();
885  return ((MCID.TSFlags & Flag) &&
886  isUInt<12>(MI->getOperand(2).getImm()) &&
887  MI->getOperand(3).getReg() == 0);
888 }
889 
890 namespace {
891 struct LogicOp {
892  LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
893  LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
894  : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
895 
896  explicit operator bool() const { return RegSize; }
897 
898  unsigned RegSize, ImmLSB, ImmSize;
899 };
900 } // end anonymous namespace
901 
902 static LogicOp interpretAndImmediate(unsigned Opcode) {
903  switch (Opcode) {
904  case SystemZ::NILMux: return LogicOp(32, 0, 16);
905  case SystemZ::NIHMux: return LogicOp(32, 16, 16);
906  case SystemZ::NILL64: return LogicOp(64, 0, 16);
907  case SystemZ::NILH64: return LogicOp(64, 16, 16);
908  case SystemZ::NIHL64: return LogicOp(64, 32, 16);
909  case SystemZ::NIHH64: return LogicOp(64, 48, 16);
910  case SystemZ::NIFMux: return LogicOp(32, 0, 32);
911  case SystemZ::NILF64: return LogicOp(64, 0, 32);
912  case SystemZ::NIHF64: return LogicOp(64, 32, 32);
913  default: return LogicOp();
914  }
915 }
916 
917 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
918  if (OldMI->registerDefIsDead(SystemZ::CC)) {
919  MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
920  if (CCDef != nullptr)
921  CCDef->setIsDead(true);
922  }
923 }
924 
925 // Used to return from convertToThreeAddress after replacing two-address
926 // instruction OldMI with three-address instruction NewMI.
928  MachineInstr *NewMI,
929  LiveVariables *LV) {
930  if (LV) {
931  unsigned NumOps = OldMI->getNumOperands();
932  for (unsigned I = 1; I < NumOps; ++I) {
933  MachineOperand &Op = OldMI->getOperand(I);
934  if (Op.isReg() && Op.isKill())
935  LV->replaceKillInstruction(Op.getReg(), *OldMI, *NewMI);
936  }
937  }
938  transferDeadCC(OldMI, NewMI);
939  return NewMI;
940 }
941 
944  MachineBasicBlock *MBB = MI.getParent();
945  MachineFunction *MF = MBB->getParent();
947 
948  unsigned Opcode = MI.getOpcode();
949  unsigned NumOps = MI.getNumOperands();
950 
951  // Try to convert something like SLL into SLLK, if supported.
952  // We prefer to keep the two-operand form where possible both
953  // because it tends to be shorter and because some instructions
954  // have memory forms that can be used during spilling.
955  if (STI.hasDistinctOps()) {
956  MachineOperand &Dest = MI.getOperand(0);
957  MachineOperand &Src = MI.getOperand(1);
958  unsigned DestReg = Dest.getReg();
959  unsigned SrcReg = Src.getReg();
960  // AHIMux is only really a three-operand instruction when both operands
961  // are low registers. Try to constrain both operands to be low if
962  // possible.
963  if (Opcode == SystemZ::AHIMux &&
966  MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
967  MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
968  MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
969  MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
970  }
971  int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
972  if (ThreeOperandOpcode >= 0) {
973  // Create three address instruction without adding the implicit
974  // operands. Those will instead be copied over from the original
975  // instruction by the loop below.
977  *MF, MF->CreateMachineInstr(get(ThreeOperandOpcode), MI.getDebugLoc(),
978  /*NoImplicit=*/true));
979  MIB.addOperand(Dest);
980  // Keep the kill state, but drop the tied flag.
981  MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
982  // Keep the remaining operands as-is.
983  for (unsigned I = 2; I < NumOps; ++I)
984  MIB.addOperand(MI.getOperand(I));
985  MBB->insert(MI, MIB);
986  return finishConvertToThreeAddress(&MI, MIB, LV);
987  }
988  }
989 
990  // Try to convert an AND into an RISBG-type instruction.
991  if (LogicOp And = interpretAndImmediate(Opcode)) {
992  uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
993  // AND IMMEDIATE leaves the other bits of the register unchanged.
994  Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
995  unsigned Start, End;
996  if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
997  unsigned NewOpcode;
998  if (And.RegSize == 64) {
999  NewOpcode = SystemZ::RISBG;
1000  // Prefer RISBGN if available, since it does not clobber CC.
1001  if (STI.hasMiscellaneousExtensions())
1002  NewOpcode = SystemZ::RISBGN;
1003  } else {
1004  NewOpcode = SystemZ::RISBMux;
1005  Start &= 31;
1006  End &= 31;
1007  }
1008  MachineOperand &Dest = MI.getOperand(0);
1009  MachineOperand &Src = MI.getOperand(1);
1010  MachineInstrBuilder MIB =
1011  BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
1012  .addOperand(Dest)
1013  .addReg(0)
1014  .addReg(Src.getReg(), getKillRegState(Src.isKill()),
1015  Src.getSubReg())
1016  .addImm(Start)
1017  .addImm(End + 128)
1018  .addImm(0);
1019  return finishConvertToThreeAddress(&MI, MIB, LV);
1020  }
1021  }
1022  return nullptr;
1023 }
1024 
1028  LiveIntervals *LIS) const {
1029  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1030  const MachineFrameInfo &MFI = MF.getFrameInfo();
1031  unsigned Size = MFI.getObjectSize(FrameIndex);
1032  unsigned Opcode = MI.getOpcode();
1033 
1034  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1035  if (LIS != nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1036  isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1037 
1038  // Check CC liveness, since new instruction introduces a dead
1039  // def of CC.
1040  MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
1041  LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
1042  ++CCUnit;
1043  assert (!CCUnit.isValid() && "CC only has one reg unit.");
1044  SlotIndex MISlot =
1046  if (!CCLiveRange.liveAt(MISlot)) {
1047  // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1048  MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1049  MI.getDebugLoc(), get(SystemZ::AGSI))
1050  .addFrameIndex(FrameIndex)
1051  .addImm(0)
1052  .addImm(MI.getOperand(2).getImm());
1053  BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
1054  CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
1055  return BuiltMI;
1056  }
1057  }
1058  return nullptr;
1059  }
1060 
1061  // All other cases require a single operand.
1062  if (Ops.size() != 1)
1063  return nullptr;
1064 
1065  unsigned OpNum = Ops[0];
1066  assert(Size ==
1067  MF.getRegInfo()
1068  .getRegClass(MI.getOperand(OpNum).getReg())
1069  ->getSize() &&
1070  "Invalid size combination");
1071 
1072  if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1073  isInt<8>(MI.getOperand(2).getImm())) {
1074  // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1075  Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1076  MachineInstr *BuiltMI =
1077  BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1078  .addFrameIndex(FrameIndex)
1079  .addImm(0)
1080  .addImm(MI.getOperand(2).getImm());
1081  transferDeadCC(&MI, BuiltMI);
1082  return BuiltMI;
1083  }
1084 
1085  if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1086  bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1087  bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1088  // If we're spilling the destination of an LDGR or LGDR, store the
1089  // source register instead.
1090  if (OpNum == 0) {
1091  unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1092  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1093  get(StoreOpcode))
1094  .addOperand(MI.getOperand(1))
1095  .addFrameIndex(FrameIndex)
1096  .addImm(0)
1097  .addReg(0);
1098  }
1099  // If we're spilling the source of an LDGR or LGDR, load the
1100  // destination register instead.
1101  if (OpNum == 1) {
1102  unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1103  unsigned Dest = MI.getOperand(0).getReg();
1104  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1105  get(LoadOpcode), Dest)
1106  .addFrameIndex(FrameIndex)
1107  .addImm(0)
1108  .addReg(0);
1109  }
1110  }
1111 
1112  // Look for cases where the source of a simple store or the destination
1113  // of a simple load is being spilled. Try to use MVC instead.
1114  //
1115  // Although MVC is in practice a fast choice in these cases, it is still
1116  // logically a bytewise copy. This means that we cannot use it if the
1117  // load or store is volatile. We also wouldn't be able to use MVC if
1118  // the two memories partially overlap, but that case cannot occur here,
1119  // because we know that one of the memories is a full frame index.
1120  //
1121  // For performance reasons, we also want to avoid using MVC if the addresses
1122  // might be equal. We don't worry about that case here, because spill slot
1123  // coloring happens later, and because we have special code to remove
1124  // MVCs that turn out to be redundant.
1125  if (OpNum == 0 && MI.hasOneMemOperand()) {
1126  MachineMemOperand *MMO = *MI.memoperands_begin();
1127  if (MMO->getSize() == Size && !MMO->isVolatile()) {
1128  // Handle conversion of loads.
1130  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1131  get(SystemZ::MVC))
1132  .addFrameIndex(FrameIndex)
1133  .addImm(0)
1134  .addImm(Size)
1135  .addOperand(MI.getOperand(1))
1136  .addImm(MI.getOperand(2).getImm())
1137  .addMemOperand(MMO);
1138  }
1139  // Handle conversion of stores.
1141  return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1142  get(SystemZ::MVC))
1143  .addOperand(MI.getOperand(1))
1144  .addImm(MI.getOperand(2).getImm())
1145  .addImm(Size)
1146  .addFrameIndex(FrameIndex)
1147  .addImm(0)
1148  .addMemOperand(MMO);
1149  }
1150  }
1151  }
1152 
1153  // If the spilled operand is the final one, try to change <INSN>R
1154  // into <INSN>.
1155  int MemOpcode = SystemZ::getMemOpcode(Opcode);
1156  if (MemOpcode >= 0) {
1157  unsigned NumOps = MI.getNumExplicitOperands();
1158  if (OpNum == NumOps - 1) {
1159  const MCInstrDesc &MemDesc = get(MemOpcode);
1160  uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1161  assert(AccessBytes != 0 && "Size of access should be known");
1162  assert(AccessBytes <= Size && "Access outside the frame index");
1163  uint64_t Offset = Size - AccessBytes;
1164  MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1165  MI.getDebugLoc(), get(MemOpcode));
1166  for (unsigned I = 0; I < OpNum; ++I)
1167  MIB.addOperand(MI.getOperand(I));
1168  MIB.addFrameIndex(FrameIndex).addImm(Offset);
1169  if (MemDesc.TSFlags & SystemZII::HasIndex)
1170  MIB.addReg(0);
1171  transferDeadCC(&MI, MIB);
1172  return MIB;
1173  }
1174  }
1175 
1176  return nullptr;
1177 }
1178 
1181  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1182  LiveIntervals *LIS) const {
1183  return nullptr;
1184 }
1185 
1187  switch (MI.getOpcode()) {
1188  case SystemZ::L128:
1189  splitMove(MI, SystemZ::LG);
1190  return true;
1191 
1192  case SystemZ::ST128:
1193  splitMove(MI, SystemZ::STG);
1194  return true;
1195 
1196  case SystemZ::LX:
1197  splitMove(MI, SystemZ::LD);
1198  return true;
1199 
1200  case SystemZ::STX:
1201  splitMove(MI, SystemZ::STD);
1202  return true;
1203 
1204  case SystemZ::LBMux:
1205  expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1206  return true;
1207 
1208  case SystemZ::LHMux:
1209  expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1210  return true;
1211 
1212  case SystemZ::LLCRMux:
1213  expandZExtPseudo(MI, SystemZ::LLCR, 8);
1214  return true;
1215 
1216  case SystemZ::LLHRMux:
1217  expandZExtPseudo(MI, SystemZ::LLHR, 16);
1218  return true;
1219 
1220  case SystemZ::LLCMux:
1221  expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1222  return true;
1223 
1224  case SystemZ::LLHMux:
1225  expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1226  return true;
1227 
1228  case SystemZ::LMux:
1229  expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1230  return true;
1231 
1232  case SystemZ::LOCMux:
1233  expandLOCPseudo(MI, SystemZ::LOC, SystemZ::LOCFH);
1234  return true;
1235 
1236  case SystemZ::LOCHIMux:
1237  expandLOCPseudo(MI, SystemZ::LOCHI, SystemZ::LOCHHI);
1238  return true;
1239 
1240  case SystemZ::LOCRMux:
1241  expandLOCRPseudo(MI, SystemZ::LOCR, SystemZ::LOCFHR);
1242  return true;
1243 
1244  case SystemZ::STCMux:
1245  expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1246  return true;
1247 
1248  case SystemZ::STHMux:
1249  expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1250  return true;
1251 
1252  case SystemZ::STMux:
1253  expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1254  return true;
1255 
1256  case SystemZ::STOCMux:
1257  expandLOCPseudo(MI, SystemZ::STOC, SystemZ::STOCFH);
1258  return true;
1259 
1260  case SystemZ::LHIMux:
1261  expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1262  return true;
1263 
1264  case SystemZ::IIFMux:
1265  expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1266  return true;
1267 
1268  case SystemZ::IILMux:
1269  expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1270  return true;
1271 
1272  case SystemZ::IIHMux:
1273  expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1274  return true;
1275 
1276  case SystemZ::NIFMux:
1277  expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1278  return true;
1279 
1280  case SystemZ::NILMux:
1281  expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1282  return true;
1283 
1284  case SystemZ::NIHMux:
1285  expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1286  return true;
1287 
1288  case SystemZ::OIFMux:
1289  expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1290  return true;
1291 
1292  case SystemZ::OILMux:
1293  expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1294  return true;
1295 
1296  case SystemZ::OIHMux:
1297  expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1298  return true;
1299 
1300  case SystemZ::XIFMux:
1301  expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1302  return true;
1303 
1304  case SystemZ::TMLMux:
1305  expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1306  return true;
1307 
1308  case SystemZ::TMHMux:
1309  expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1310  return true;
1311 
1312  case SystemZ::AHIMux:
1313  expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1314  return true;
1315 
1316  case SystemZ::AHIMuxK:
1317  expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1318  return true;
1319 
1320  case SystemZ::AFIMux:
1321  expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1322  return true;
1323 
1324  case SystemZ::CHIMux:
1325  expandRIPseudo(MI, SystemZ::CHI, SystemZ::CIH, false);
1326  return true;
1327 
1328  case SystemZ::CFIMux:
1329  expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1330  return true;
1331 
1332  case SystemZ::CLFIMux:
1333  expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1334  return true;
1335 
1336  case SystemZ::CMux:
1337  expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1338  return true;
1339 
1340  case SystemZ::CLMux:
1341  expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1342  return true;
1343 
1344  case SystemZ::RISBMux: {
1345  bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
1346  bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
1347  if (SrcIsHigh == DestIsHigh)
1348  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1349  else {
1350  MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1351  MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1352  }
1353  return true;
1354  }
1355 
1356  case SystemZ::ADJDYNALLOC:
1357  splitAdjDynAlloc(MI);
1358  return true;
1359 
1360  case TargetOpcode::LOAD_STACK_GUARD:
1361  expandLoadStackGuard(&MI);
1362  return true;
1363 
1364  default:
1365  return false;
1366  }
1367 }
1368 
1370  if (MI.getOpcode() == TargetOpcode::INLINEASM) {
1371  const MachineFunction *MF = MI.getParent()->getParent();
1372  const char *AsmStr = MI.getOperand(0).getSymbolName();
1373  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1374  }
1375  return MI.getDesc().getSize();
1376 }
1377 
1380  switch (MI.getOpcode()) {
1381  case SystemZ::BR:
1382  case SystemZ::J:
1383  case SystemZ::JG:
1386 
1387  case SystemZ::BRC:
1388  case SystemZ::BRCL:
1390  MI.getOperand(1).getImm(), &MI.getOperand(2));
1391 
1392  case SystemZ::BRCT:
1393  case SystemZ::BRCTH:
1396 
1397  case SystemZ::BRCTG:
1400 
1401  case SystemZ::CIJ:
1402  case SystemZ::CRJ:
1404  MI.getOperand(2).getImm(), &MI.getOperand(3));
1405 
1406  case SystemZ::CLIJ:
1407  case SystemZ::CLRJ:
1409  MI.getOperand(2).getImm(), &MI.getOperand(3));
1410 
1411  case SystemZ::CGIJ:
1412  case SystemZ::CGRJ:
1414  MI.getOperand(2).getImm(), &MI.getOperand(3));
1415 
1416  case SystemZ::CLGIJ:
1417  case SystemZ::CLGRJ:
1419  MI.getOperand(2).getImm(), &MI.getOperand(3));
1420 
1421  default:
1422  llvm_unreachable("Unrecognized branch opcode");
1423  }
1424 }
1425 
1427  unsigned &LoadOpcode,
1428  unsigned &StoreOpcode) const {
1429  if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1430  LoadOpcode = SystemZ::L;
1431  StoreOpcode = SystemZ::ST;
1432  } else if (RC == &SystemZ::GRH32BitRegClass) {
1433  LoadOpcode = SystemZ::LFH;
1434  StoreOpcode = SystemZ::STFH;
1435  } else if (RC == &SystemZ::GRX32BitRegClass) {
1436  LoadOpcode = SystemZ::LMux;
1437  StoreOpcode = SystemZ::STMux;
1438  } else if (RC == &SystemZ::GR64BitRegClass ||
1439  RC == &SystemZ::ADDR64BitRegClass) {
1440  LoadOpcode = SystemZ::LG;
1441  StoreOpcode = SystemZ::STG;
1442  } else if (RC == &SystemZ::GR128BitRegClass ||
1443  RC == &SystemZ::ADDR128BitRegClass) {
1444  LoadOpcode = SystemZ::L128;
1445  StoreOpcode = SystemZ::ST128;
1446  } else if (RC == &SystemZ::FP32BitRegClass) {
1447  LoadOpcode = SystemZ::LE;
1448  StoreOpcode = SystemZ::STE;
1449  } else if (RC == &SystemZ::FP64BitRegClass) {
1450  LoadOpcode = SystemZ::LD;
1451  StoreOpcode = SystemZ::STD;
1452  } else if (RC == &SystemZ::FP128BitRegClass) {
1453  LoadOpcode = SystemZ::LX;
1454  StoreOpcode = SystemZ::STX;
1455  } else if (RC == &SystemZ::VR32BitRegClass) {
1456  LoadOpcode = SystemZ::VL32;
1457  StoreOpcode = SystemZ::VST32;
1458  } else if (RC == &SystemZ::VR64BitRegClass) {
1459  LoadOpcode = SystemZ::VL64;
1460  StoreOpcode = SystemZ::VST64;
1461  } else if (RC == &SystemZ::VF128BitRegClass ||
1462  RC == &SystemZ::VR128BitRegClass) {
1463  LoadOpcode = SystemZ::VL;
1464  StoreOpcode = SystemZ::VST;
1465  } else
1466  llvm_unreachable("Unsupported regclass to load or store");
1467 }
1468 
1469 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1470  int64_t Offset) const {
1471  const MCInstrDesc &MCID = get(Opcode);
1472  int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1473  if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1474  // Get the instruction to use for unsigned 12-bit displacements.
1475  int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1476  if (Disp12Opcode >= 0)
1477  return Disp12Opcode;
1478 
1479  // All address-related instructions can use unsigned 12-bit
1480  // displacements.
1481  return Opcode;
1482  }
1483  if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1484  // Get the instruction to use for signed 20-bit displacements.
1485  int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1486  if (Disp20Opcode >= 0)
1487  return Disp20Opcode;
1488 
1489  // Check whether Opcode allows signed 20-bit displacements.
1491  return Opcode;
1492  }
1493  return 0;
1494 }
1495 
1496 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1497  switch (Opcode) {
1498  case SystemZ::L: return SystemZ::LT;
1499  case SystemZ::LY: return SystemZ::LT;
1500  case SystemZ::LG: return SystemZ::LTG;
1501  case SystemZ::LGF: return SystemZ::LTGF;
1502  case SystemZ::LR: return SystemZ::LTR;
1503  case SystemZ::LGFR: return SystemZ::LTGFR;
1504  case SystemZ::LGR: return SystemZ::LTGR;
1505  case SystemZ::LER: return SystemZ::LTEBR;
1506  case SystemZ::LDR: return SystemZ::LTDBR;
1507  case SystemZ::LXR: return SystemZ::LTXBR;
1508  case SystemZ::LCDFR: return SystemZ::LCDBR;
1509  case SystemZ::LPDFR: return SystemZ::LPDBR;
1510  case SystemZ::LNDFR: return SystemZ::LNDBR;
1511  case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1512  case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1513  case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1514  // On zEC12 we prefer to use RISBGN. But if there is a chance to
1515  // actually use the condition code, we may turn it back into RISGB.
1516  // Note that RISBG is not really a "load-and-test" instruction,
1517  // but sets the same condition code values, so is OK to use here.
1518  case SystemZ::RISBGN: return SystemZ::RISBG;
1519  default: return 0;
1520  }
1521 }
1522 
1523 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1524 // have already been filtered out. Store the first set bit in LSB and
1525 // the number of set bits in Length if so.
1526 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1527  unsigned First = findFirstSet(Mask);
1528  uint64_t Top = (Mask >> First) + 1;
1529  if ((Top & -Top) == Top) {
1530  LSB = First;
1531  Length = findFirstSet(Top);
1532  return true;
1533  }
1534  return false;
1535 }
1536 
1537 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1538  unsigned &Start, unsigned &End) const {
1539  // Reject trivial all-zero masks.
1540  Mask &= allOnes(BitSize);
1541  if (Mask == 0)
1542  return false;
1543 
1544  // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1545  // the msb and End specifies the index of the lsb.
1546  unsigned LSB, Length;
1547  if (isStringOfOnes(Mask, LSB, Length)) {
1548  Start = 63 - (LSB + Length - 1);
1549  End = 63 - LSB;
1550  return true;
1551  }
1552 
1553  // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1554  // of the low 1s and End specifies the lsb of the high 1s.
1555  if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1556  assert(LSB > 0 && "Bottom bit must be set");
1557  assert(LSB + Length < BitSize && "Top bit must be set");
1558  Start = 63 - (LSB - 1);
1559  End = 63 - (LSB + Length);
1560  return true;
1561  }
1562 
1563  return false;
1564 }
1565 
1566 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1568  const MachineInstr *MI) const {
1569  switch (Opcode) {
1570  case SystemZ::CHI:
1571  case SystemZ::CGHI:
1572  if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1573  return 0;
1574  break;
1575  case SystemZ::CLFI:
1576  case SystemZ::CLGFI:
1577  if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1578  return 0;
1579  break;
1580  case SystemZ::CL:
1581  case SystemZ::CLG:
1582  if (!STI.hasMiscellaneousExtensions())
1583  return 0;
1584  if (!(MI && MI->getOperand(3).getReg() == 0))
1585  return 0;
1586  break;
1587  }
1588  switch (Type) {
1590  switch (Opcode) {
1591  case SystemZ::CR:
1592  return SystemZ::CRJ;
1593  case SystemZ::CGR:
1594  return SystemZ::CGRJ;
1595  case SystemZ::CHI:
1596  return SystemZ::CIJ;
1597  case SystemZ::CGHI:
1598  return SystemZ::CGIJ;
1599  case SystemZ::CLR:
1600  return SystemZ::CLRJ;
1601  case SystemZ::CLGR:
1602  return SystemZ::CLGRJ;
1603  case SystemZ::CLFI:
1604  return SystemZ::CLIJ;
1605  case SystemZ::CLGFI:
1606  return SystemZ::CLGIJ;
1607  default:
1608  return 0;
1609  }
1611  switch (Opcode) {
1612  case SystemZ::CR:
1613  return SystemZ::CRBReturn;
1614  case SystemZ::CGR:
1615  return SystemZ::CGRBReturn;
1616  case SystemZ::CHI:
1617  return SystemZ::CIBReturn;
1618  case SystemZ::CGHI:
1619  return SystemZ::CGIBReturn;
1620  case SystemZ::CLR:
1621  return SystemZ::CLRBReturn;
1622  case SystemZ::CLGR:
1623  return SystemZ::CLGRBReturn;
1624  case SystemZ::CLFI:
1625  return SystemZ::CLIBReturn;
1626  case SystemZ::CLGFI:
1627  return SystemZ::CLGIBReturn;
1628  default:
1629  return 0;
1630  }
1632  switch (Opcode) {
1633  case SystemZ::CR:
1634  return SystemZ::CRBCall;
1635  case SystemZ::CGR:
1636  return SystemZ::CGRBCall;
1637  case SystemZ::CHI:
1638  return SystemZ::CIBCall;
1639  case SystemZ::CGHI:
1640  return SystemZ::CGIBCall;
1641  case SystemZ::CLR:
1642  return SystemZ::CLRBCall;
1643  case SystemZ::CLGR:
1644  return SystemZ::CLGRBCall;
1645  case SystemZ::CLFI:
1646  return SystemZ::CLIBCall;
1647  case SystemZ::CLGFI:
1648  return SystemZ::CLGIBCall;
1649  default:
1650  return 0;
1651  }
1653  switch (Opcode) {
1654  case SystemZ::CR:
1655  return SystemZ::CRT;
1656  case SystemZ::CGR:
1657  return SystemZ::CGRT;
1658  case SystemZ::CHI:
1659  return SystemZ::CIT;
1660  case SystemZ::CGHI:
1661  return SystemZ::CGIT;
1662  case SystemZ::CLR:
1663  return SystemZ::CLRT;
1664  case SystemZ::CLGR:
1665  return SystemZ::CLGRT;
1666  case SystemZ::CLFI:
1667  return SystemZ::CLFIT;
1668  case SystemZ::CLGFI:
1669  return SystemZ::CLGIT;
1670  case SystemZ::CL:
1671  return SystemZ::CLT;
1672  case SystemZ::CLG:
1673  return SystemZ::CLGT;
1674  default:
1675  return 0;
1676  }
1677  }
1678  return 0;
1679 }
1680 
1681 unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
1682  if (!STI.hasLoadAndTrap())
1683  return 0;
1684  switch (Opcode) {
1685  case SystemZ::L:
1686  case SystemZ::LY:
1687  return SystemZ::LAT;
1688  case SystemZ::LG:
1689  return SystemZ::LGAT;
1690  case SystemZ::LFH:
1691  return SystemZ::LFHAT;
1692  case SystemZ::LLGF:
1693  return SystemZ::LLGFAT;
1694  case SystemZ::LLGT:
1695  return SystemZ::LLGTAT;
1696  }
1697  return 0;
1698 }
1699 
1702  unsigned Reg, uint64_t Value) const {
1703  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1704  unsigned Opcode;
1705  if (isInt<16>(Value))
1706  Opcode = SystemZ::LGHI;
1707  else if (SystemZ::isImmLL(Value))
1708  Opcode = SystemZ::LLILL;
1709  else if (SystemZ::isImmLH(Value)) {
1710  Opcode = SystemZ::LLILH;
1711  Value >>= 16;
1712  } else {
1713  assert(isInt<32>(Value) && "Huge values not handled yet");
1714  Opcode = SystemZ::LGFI;
1715  }
1716  BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1717 }
1718 
1719 bool SystemZInstrInfo::
1721  AliasAnalysis *AA) const {
1722 
1723  if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
1724  return false;
1725 
1726  // If mem-operands show that the same address Value is used by both
1727  // instructions, check for non-overlapping offsets and widths. Not
1728  // sure if a register based analysis would be an improvement...
1729 
1730  MachineMemOperand *MMOa = *MIa.memoperands_begin();
1731  MachineMemOperand *MMOb = *MIb.memoperands_begin();
1732  const Value *VALa = MMOa->getValue();
1733  const Value *VALb = MMOb->getValue();
1734  bool SameVal = (VALa && VALb && (VALa == VALb));
1735  if (!SameVal) {
1736  const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1737  const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1738  if (PSVa && PSVb && (PSVa == PSVb))
1739  SameVal = true;
1740  }
1741  if (SameVal) {
1742  int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
1743  int WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
1744  int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
1745  int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
1746  int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
1747  if (LowOffset + LowWidth <= HighOffset)
1748  return true;
1749  }
1750 
1751  return false;
1752 }
MachineLoop * L
SystemZII::Branch getBranchInfo(const MachineInstr &MI) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getLoadAndTrap(unsigned Opcode) const
bool expandPostRAPseudo(MachineInstr &MBBI) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:406
const int64_t CallFrameSize
SystemZInstrInfo(SystemZSubtarget &STI)
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:952
MachineBasicBlock * getMBB() const
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool use_nodbg_empty(unsigned RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register...
static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI)
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:268
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
const char * getSymbolName() const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
A debug info location.
Definition: DebugLoc.h:34
void setIsDead(bool Val=true)
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImp=false)
CreateMachineInstr - Allocate a new MachineInstr.
const unsigned CCMASK_ICMP
Definition: SystemZ.h:47
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
return AArch64::GPR64RegClass contains(Reg)
static uint64_t allOnes(unsigned int Count)
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned getLoadAndTest(unsigned Opcode) const
static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
bool hasLoadStoreOnCond() const
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned Reg, uint64_t Value) const
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool hasLoadStoreOnCond2() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, unsigned &StoreOpcode) const
bool isKill() const
static LogicOp interpretAndImmediate(unsigned Opcode)
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineBasicBlock * MBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const MachineOperand * Target
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
const unsigned CCMASK_ANY
Definition: SystemZ.h:31
int64_t getImm() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI)
SlotIndexes * getSlotIndexes() const
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:551
unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:309
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static unsigned getAccessSize(unsigned int Flags)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:560
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
uint32_t Offset
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
static const unsigned End
void setImm(int64_t immVal)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:373
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:910
self_iterator getIterator()
Definition: ilist_node.h:81
const PseudoSourceValue * getPseudoValue() const
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:136
bool isRxSBGMask(uint64_t Mask, unsigned BitSize, unsigned &Start, unsigned &End) const
unsigned getSubReg() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:376
static bool isImmLH(uint64_t Val)
Definition: SystemZ.h:150
T findFirstSet(T Val, ZeroBehavior ZB=ZB_Max)
Get the index of the first set bit starting from the least significant bit.
Definition: MathExtras.h:194
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
static bool isHighReg(unsigned int Reg)
Iterator for intrusive lists based on ilist_node.
void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:274
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
MachineOperand class - Representation of each machine instruction operand.
static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length)
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isPredicable(MachineInstr &MI) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
const unsigned CCMASK_CMP_NE
Definition: SystemZ.h:38
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:485
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
const Value * getValue() const
Return the base address of the memory access.
Special value supplied for machine level alias analysis.
static MachineInstr * finishConvertToThreeAddress(MachineInstr *OldMI, MachineInstr *NewMI, LiveVariables *LV)
static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, unsigned Flag)
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1942
bool hasMiscellaneousExtensions() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static MachineInstr * getDef(unsigned Reg, const MachineRegisterInfo *MRI)
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
unsigned getFusedCompare(unsigned Opcode, SystemZII::FusedCompareType Type, const MachineInstr *MI=nullptr) const
bool hasLoadAndTrap() const
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
Definition: SlotIndexes.h:247
unsigned getReg() const
getReg - Returns the register number.
bool hasDistinctOps() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
uint64_t getSize() const
Return the size in bytes of the memory reference.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isImmLL(uint64_t Val)
Definition: SystemZ.h:145
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const unsigned IPM_CC
Definition: SystemZ.h:96
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:903
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:358
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.