38 #define DEBUG_TYPE "regalloc"
40 STATISTIC(NumStores,
"Number of stores added");
41 STATISTIC(NumLoads ,
"Number of loads added");
42 STATISTIC(NumCopies,
"Number of copies coalesced");
52 isBulkSpilling(
false) {}
73 unsigned short LastOpNum;
76 explicit LiveReg(
unsigned v)
77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(
false){}
79 unsigned getSparseSetIndex()
const {
88 LiveRegMap LiveVirtRegs;
113 std::vector<unsigned> PhysRegState;
120 UsedInInstrSet UsedInInstr;
123 void markRegUsedInInstr(
unsigned PhysReg) {
125 UsedInInstr.
insert(*Units);
129 bool isRegUsedInInstr(
unsigned PhysReg)
const {
131 if (UsedInInstr.count(*Units))
149 spillImpossible = ~0u
152 StringRef getPassName()
const override {
return "Fast Register Allocator"; }
171 void AllocateBasicBlock();
177 void addKillFlag(
const LiveReg&);
178 void killVirtReg(LiveRegMap::iterator);
179 void killVirtReg(
unsigned VirtReg);
184 void definePhysReg(
MachineInstr &
MI,
unsigned PhysReg, RegState NewState);
185 unsigned calcSpillCost(
unsigned PhysReg)
const;
186 void assignVirtToPhysReg(LiveReg&,
unsigned PhysReg);
187 LiveRegMap::iterator findLiveVirtReg(
unsigned VirtReg) {
190 LiveRegMap::const_iterator findLiveVirtReg(
unsigned VirtReg)
const {
193 LiveRegMap::iterator assignVirtToPhysReg(
unsigned VReg,
unsigned PhysReg);
194 LiveRegMap::iterator allocVirtReg(
MachineInstr &
MI, LiveRegMap::iterator,
196 LiveRegMap::iterator defineVirtReg(
MachineInstr &
MI,
unsigned OpNum,
197 unsigned VirtReg,
unsigned Hint);
198 LiveRegMap::iterator reloadVirtReg(
MachineInstr &
MI,
unsigned OpNum,
199 unsigned VirtReg,
unsigned Hint);
201 bool setPhysReg(
MachineInstr *
MI,
unsigned OpNum,
unsigned PhysReg);
210 int SS = StackSlotForVirtReg[VirtReg];
215 int FrameIdx = MF->getFrameInfo().CreateSpillStackObject(RC->
getSize(),
219 StackSlotForVirtReg[VirtReg] = FrameIdx;
229 if (StackSlotForVirtReg[MO.
getReg()] != -1)
236 return ++I ==
MRI->reg_nodbg_end();
240 void RAFast::addKillFlag(
const LiveReg &LR) {
241 if (!LR.LastUse)
return;
243 if (MO.
isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
244 if (MO.
getReg() == LR.PhysReg)
247 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI,
true);
252 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
254 assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
255 "Broken RegState mapping");
256 PhysRegState[LRI->PhysReg] = regFree;
259 LiveVirtRegs.erase(LRI);
263 void RAFast::killVirtReg(
unsigned VirtReg) {
265 "killVirtReg needs a virtual register");
266 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
267 if (LRI != LiveVirtRegs.end())
275 "Spilling a physical register is illegal!");
276 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
277 assert(LRI != LiveVirtRegs.end() &&
"Spilling unmapped virtual register");
278 spillVirtReg(MI, LRI);
283 LiveRegMap::iterator LRI) {
285 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg &&
"Broken RegState mapping");
293 <<
" in " <<
PrintReg(LR.PhysReg, TRI));
295 int FI = getStackSpaceFor(LRI->VirtReg, RC);
296 DEBUG(
dbgs() <<
" to stack slot #" << FI <<
"\n");
304 LiveDbgValueMap[LRI->VirtReg];
305 for (
unsigned li = 0, le = LRIDbgValues.
size(); li != le; ++li) {
312 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
313 "Expected inlined-at fields to agree");
322 DEBUG(
dbgs() <<
"Inserting debug info due to spill:" <<
"\n" << *NewDV);
327 LRIDbgValues.
clear();
329 LR.LastUse =
nullptr;
336 if (LiveVirtRegs.empty())
return;
337 isBulkSpilling =
true;
340 for (LiveRegMap::iterator
i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
343 LiveVirtRegs.clear();
344 isBulkSpilling =
false;
352 unsigned PhysReg = MO.
getReg();
354 "Bad usePhysReg operand");
360 markRegUsedInInstr(PhysReg);
361 switch (PhysRegState[PhysReg]) {
365 PhysRegState[PhysReg] = regFree;
378 unsigned Alias = *AI;
379 switch (PhysRegState[Alias]) {
392 assert((TRI->isSuperRegister(PhysReg, Alias) ||
393 TRI->isSuperRegister(Alias, PhysReg)) &&
394 "Instruction is not using a subregister of a reserved register");
397 if (TRI->isSuperRegister(PhysReg, Alias)) {
399 PhysRegState[Alias] = regFree;
404 PhysRegState[Alias] = regDisabled;
412 PhysRegState[PhysReg] = regFree;
419 void RAFast::definePhysReg(
MachineInstr &MI,
unsigned PhysReg,
421 markRegUsedInInstr(PhysReg);
422 switch (
unsigned VirtReg = PhysRegState[PhysReg]) {
426 spillVirtReg(MI, VirtReg);
430 PhysRegState[PhysReg] = NewState;
435 PhysRegState[PhysReg] = NewState;
437 unsigned Alias = *AI;
438 switch (
unsigned VirtReg = PhysRegState[Alias]) {
442 spillVirtReg(MI, VirtReg);
446 PhysRegState[Alias] = regDisabled;
447 if (TRI->isSuperRegister(PhysReg, Alias))
460 unsigned RAFast::calcSpillCost(
unsigned PhysReg)
const {
461 if (isRegUsedInInstr(PhysReg)) {
463 return spillImpossible;
465 switch (
unsigned VirtReg = PhysRegState[PhysReg]) {
472 <<
PrintReg(PhysReg, TRI) <<
" is reserved already.\n");
473 return spillImpossible;
475 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
476 assert(I != LiveVirtRegs.end() &&
"Missing VirtReg entry");
477 return I->Dirty ? spillDirty : spillClean;
485 unsigned Alias = *AI;
486 switch (
unsigned VirtReg = PhysRegState[Alias]) {
493 return spillImpossible;
495 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
496 assert(I != LiveVirtRegs.end() &&
"Missing VirtReg entry");
497 Cost += I->Dirty ? spillDirty : spillClean;
510 void RAFast::assignVirtToPhysReg(LiveReg &LR,
unsigned PhysReg) {
513 PhysRegState[PhysReg] = LR.VirtReg;
514 assert(!LR.PhysReg &&
"Already assigned a physreg");
515 LR.PhysReg = PhysReg;
519 RAFast::assignVirtToPhysReg(
unsigned VirtReg,
unsigned PhysReg) {
520 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
521 assert(LRI != LiveVirtRegs.end() &&
"VirtReg disappeared");
522 assignVirtToPhysReg(*LRI, PhysReg);
528 LiveRegMap::iterator LRI,
530 const unsigned VirtReg = LRI->VirtReg;
533 "Can only allocate virtual registers");
545 unsigned Cost = calcSpillCost(Hint);
546 if (Cost < spillDirty) {
548 definePhysReg(MI, Hint, regFree);
551 return assignVirtToPhysReg(VirtReg, Hint);
559 unsigned PhysReg = *
I;
560 if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) {
561 assignVirtToPhysReg(*LRI, PhysReg);
567 << TRI->getRegClassName(RC) <<
"\n");
569 unsigned BestReg = 0, BestCost = spillImpossible;
571 unsigned Cost = calcSpillCost(*I);
573 DEBUG(
dbgs() <<
"\tCost: " << Cost <<
"\n");
574 DEBUG(
dbgs() <<
"\tBestCost: " << BestCost <<
"\n");
577 assignVirtToPhysReg(*LRI, *I);
581 BestReg = *
I, BestCost = Cost;
585 definePhysReg(MI, BestReg, regFree);
588 return assignVirtToPhysReg(VirtReg, BestReg);
593 MI.
emitError(
"inline assembly requires more registers than available");
595 MI.
emitError(
"ran out of registers during register allocation");
596 definePhysReg(MI, *AO.
begin(), regFree);
597 return assignVirtToPhysReg(VirtReg, *AO.
begin());
606 "Not a virtual register");
607 LiveRegMap::iterator LRI;
609 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
613 MRI->hasOneNonDBGUse(VirtReg)) {
619 LRI = allocVirtReg(MI, LRI, Hint);
620 }
else if (LRI->LastUse) {
623 if (LRI->LastUse != &MI || LRI->LastUse->
getOperand(LRI->LastOpNum).
isUse())
626 assert(LRI->PhysReg &&
"Register not assigned");
628 LRI->LastOpNum = OpNum;
630 markRegUsedInInstr(LRI->PhysReg);
640 "Not a virtual register");
641 LiveRegMap::iterator LRI;
643 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
646 LRI = allocVirtReg(MI, LRI, Hint);
648 int FrameIndex = getStackSpaceFor(VirtReg, RC);
650 <<
PrintReg(LRI->PhysReg, TRI) <<
"\n");
653 }
else if (LRI->Dirty) {
654 if (isLastUseOfLocalReg(MO)) {
655 DEBUG(
dbgs() <<
"Killing last use: " << MO <<
"\n");
661 DEBUG(
dbgs() <<
"Clearing dubious kill: " << MO <<
"\n");
664 DEBUG(
dbgs() <<
"Clearing dubious dead: " << MO <<
"\n");
672 DEBUG(
dbgs() <<
"Clearing clean kill: " << MO <<
"\n");
675 DEBUG(
dbgs() <<
"Clearing clean dead: " << MO <<
"\n");
678 assert(LRI->PhysReg &&
"Register not assigned");
680 LRI->LastOpNum = OpNum;
681 markRegUsedInInstr(LRI->PhysReg);
688 bool RAFast::setPhysReg(
MachineInstr *MI,
unsigned OpNum,
unsigned PhysReg) {
719 DEBUG(
dbgs() <<
"Scanning for through registers:");
723 if (!MO.
isReg())
continue;
729 if (ThroughRegs.
insert(Reg).second)
736 DEBUG(
dbgs() <<
"\nChecking for physdef collisions.\n");
740 unsigned Reg = MO.
getReg();
742 markRegUsedInInstr(Reg);
744 if (ThroughRegs.
count(PhysRegState[*AI]))
745 definePhysReg(*MI, *AI, regFree);
750 DEBUG(
dbgs() <<
"Allocating tied uses.\n");
753 if (!MO.
isReg())
continue;
754 unsigned Reg = MO.
getReg();
759 DEBUG(
dbgs() <<
"Operand " <<
i <<
"("<< MO <<
") is tied to operand "
761 LiveRegMap::iterator LRI = reloadVirtReg(*MI,
i, Reg, 0);
762 unsigned PhysReg = LRI->PhysReg;
763 setPhysReg(MI,
i, PhysReg);
767 DEBUG(
dbgs() <<
"Partial redefine: " << MO <<
"\n");
770 LiveRegMap::iterator LRI = reloadVirtReg(*MI,
i, Reg, 0);
775 DEBUG(
dbgs() <<
"Allocating early clobbers.\n");
778 if (!MO.
isReg())
continue;
779 unsigned Reg = MO.
getReg();
784 LiveRegMap::iterator LRI = defineVirtReg(*MI,
i, Reg, 0);
785 unsigned PhysReg = LRI->PhysReg;
786 if (setPhysReg(MI,
i, PhysReg))
795 unsigned Reg = MO.
getReg();
798 <<
" as used in instr\n");
799 markRegUsedInInstr(Reg);
803 for (
unsigned i = 0, e = PartialDefs.
size();
i != e; ++
i)
804 markRegUsedInInstr(PartialDefs[
i]);
807 void RAFast::AllocateBasicBlock() {
810 PhysRegState.assign(TRI->getNumRegs(), regDisabled);
811 assert(LiveVirtRegs.empty() &&
"Mapping not cleared from last block?");
817 if (
MRI->isAllocatable(LI.PhysReg))
818 definePhysReg(*MII, LI.PhysReg, regReserved);
824 while (MII !=
MBB->
end()) {
828 dbgs() <<
"\n>> " << *MI <<
"Regs:";
829 for (
unsigned Reg = 1,
E = TRI->getNumRegs(); Reg !=
E; ++
Reg) {
830 if (PhysRegState[Reg] == regDisabled)
continue;
831 dbgs() <<
" " << TRI->getName(Reg);
832 switch(PhysRegState[Reg]) {
840 LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
841 assert(I != LiveVirtRegs.end() &&
"Missing VirtReg entry");
844 assert(I->PhysReg == Reg &&
"Bad inverse map");
851 for (LiveRegMap::iterator
i = LiveVirtRegs.begin(),
852 e = LiveVirtRegs.end();
i != e; ++
i) {
857 assert(PhysRegState[
i->PhysReg] ==
i->VirtReg &&
"Bad inverse map");
863 bool ScanDbgValue =
true;
864 while (ScanDbgValue) {
865 ScanDbgValue =
false;
868 if (!MO.
isReg())
continue;
869 unsigned Reg = MO.
getReg();
871 LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
872 if (LRI != LiveVirtRegs.end())
873 setPhysReg(MI,
i, LRI->PhysReg);
875 int SS = StackSlotForVirtReg[
Reg];
878 DEBUG(
dbgs() <<
"Unable to allocate vreg used by DBG_VALUE");
890 cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
891 "Expected inlined-at fields to agree");
893 TII->get(TargetOpcode::DBG_VALUE))
898 DEBUG(
dbgs() <<
"Modifying debug info due to spill:"
906 LiveDbgValueMap[
Reg].push_back(MI);
914 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
928 unsigned VirtOpEnd = 0;
929 bool hasTiedOps =
false;
930 bool hasEarlyClobbers =
false;
931 bool hasPartialRedefs =
false;
932 bool hasPhysDefs =
false;
940 if (!MO.
isReg())
continue;
941 unsigned Reg = MO.
getReg();
946 hasTiedOps = hasTiedOps ||
950 hasEarlyClobbers =
true;
952 hasPartialRedefs =
true;
956 if (!
MRI->isAllocatable(Reg))
continue;
960 definePhysReg(*MI, Reg,
962 hasEarlyClobbers =
true;
976 if (MI->
isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
977 (hasTiedOps && (hasPhysDefs || MCID.
getNumDefs() > 1))) {
978 handleThroughOperands(MI, VirtDead);
983 hasEarlyClobbers =
true;
988 for (
unsigned i = 0;
i != VirtOpEnd; ++
i) {
990 if (!MO.
isReg())
continue;
991 unsigned Reg = MO.
getReg();
994 LiveRegMap::iterator LRI = reloadVirtReg(*MI,
i, Reg, CopyDst);
995 unsigned PhysReg = LRI->PhysReg;
996 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
997 if (setPhysReg(MI,
i, PhysReg))
1004 UsedInInstr.clear();
1005 if (hasEarlyClobbers) {
1008 if (!MO.
isReg())
continue;
1009 unsigned Reg = MO.
getReg();
1013 markRegUsedInInstr(Reg);
1026 DEBUG(
dbgs() <<
" Spilling remaining registers before call.\n");
1031 SkippedInstrs.insert(&MCID);
1036 for (
unsigned i = 0;
i != DefOpEnd; ++
i) {
1040 unsigned Reg = MO.
getReg();
1043 if (!
MRI->isAllocatable(Reg))
continue;
1044 definePhysReg(*MI, Reg, MO.
isDead() ? regFree : regReserved);
1047 LiveRegMap::iterator LRI = defineVirtReg(*MI,
i, Reg, CopySrc);
1048 unsigned PhysReg = LRI->PhysReg;
1049 if (setPhysReg(MI,
i, PhysReg)) {
1053 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1060 for (
unsigned i = 0, e = VirtDead.
size();
i != e; ++
i)
1061 killVirtReg(VirtDead[
i]);
1064 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1065 DEBUG(
dbgs() <<
"-- coalescing: " << *MI);
1073 DEBUG(
dbgs() <<
"Spilling live registers at end of block.\n");
1078 for (
unsigned i = 0, e = Coalesced.
size(); i != e; ++
i)
1079 MBB->
erase(Coalesced[i]);
1080 NumCopies += Coalesced.
size();
1088 DEBUG(
dbgs() <<
"********** FAST REGISTER ALLOCATION **********\n"
1089 <<
"********** Function: " << Fn.
getName() <<
'\n');
1091 MRI = &MF->getRegInfo();
1092 TRI = MF->getSubtarget().getRegisterInfo();
1093 TII = MF->getSubtarget().getInstrInfo();
1094 MRI->freezeReservedRegs(Fn);
1095 RegClassInfo.runOnMachineFunction(Fn);
1096 UsedInInstr.clear();
1097 UsedInInstr.setUniverse(TRI->getNumRegUnits());
1101 StackSlotForVirtReg.resize(
MRI->getNumVirtRegs());
1102 LiveVirtRegs.setUniverse(
MRI->getNumVirtRegs());
1106 MBBi != MBBe; ++MBBi) {
1108 AllocateBasicBlock();
1113 MRI->clearVirtRegs();
1115 SkippedInstrs.clear();
1116 StackSlotForVirtReg.clear();
1117 LiveDbgValueMap.clear();
1122 return new RAFast();
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void push_back(const T &Elt)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
iterator_range< livein_iterator > liveins() const
STATISTIC(NumFunctions,"Total number of functions")
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
std::pair< iterator, bool > insert(const ValueT &Val)
insert - Attempts to insert a new element.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
MachineInstrBundleIterator< MachineInstr > iterator
void setIsDead(bool Val=true)
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Function Alias Analysis false
bool isCopyLike() const
Return true if the instruction behaves like a copy.
RegisterRegAlloc class - Track the registration of register allocators.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
bool isEarlyClobber() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
MachineInstrBuilder & UseMI
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
const MachineOperand & getOperand(unsigned i) const
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SparseSet - Fast set implmentation for objects that can be identified by small unsigned keys...
static RegisterRegAlloc fastRegAlloc("fast","fast register allocator", createFastRegisterAllocator)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void setSubReg(unsigned subReg)
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
StringRef - Represent a constant reference to a string, i.e.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Properties which a MachineFunction may have at a given point in time.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.