42 const DebugLoc &DL,
unsigned DestReg,
43 unsigned SrcReg,
bool KillSrc)
const {
49 "Thumb1 can only copy GPR registers");
51 if (st.
hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
52 || !ARM::tGPRRegClass.contains(DestReg))
72 unsigned SrcReg,
bool isKill,
int FI,
75 assert((RC == &ARM::tGPRRegClass ||
79 if (RC == &ARM::tGPRRegClass ||
83 if (I != MBB.
end()) DL = I->getDebugLoc();
92 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
98 unsigned DestReg,
int FI,
101 assert((RC == &ARM::tGPRRegClass ||
105 if (RC == &ARM::tGPRRegClass ||
109 if (I != MBB.
end()) DL = I->getDebugLoc();
117 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
121 void Thumb1InstrInfo::expandLoadStackGuard(
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getUnindexedOpcode(unsigned Opc) const override
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
return AArch64::GPR64RegClass contains(Reg)
A description of a memory reference used in the backend.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Instances of this class represent a single low-level machine instruction.
unsigned getKillRegState(bool B)
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isPositionIndependent() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The memory access writes data.
void setOpcode(unsigned Op)
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Thumb1InstrInfo(const ARMSubtarget &STI)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Primary interface to the complete machine description for the target machine.
void addOperand(const MCOperand &Op)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static MCOperand createImm(int64_t Val)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.