LLVM  4.0.0
PPCFrameLowering.cpp
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1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PPC implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
26 #include "llvm/IR/Function.h"
28 
29 using namespace llvm;
30 
31 /// VRRegNo - Map from a numbered VR register to its enum value.
32 ///
33 static const MCPhysReg VRRegNo[] = {
34  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
38 };
39 
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41  if (STI.isDarwinABI())
42  return STI.isPPC64() ? 16 : 8;
43  // SVR4 ABI:
44  return STI.isPPC64() ? 16 : 4;
45 }
46 
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48  return STI.isELFv2ABI() ? 24 : 40;
49 }
50 
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52  // For the Darwin ABI:
53  // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54  // for saving the frame pointer (if needed.) While the published ABI has
55  // not used this slot since at least MacOSX 10.2, there is older code
56  // around that does use it, and that needs to continue to work.
57  if (STI.isDarwinABI())
58  return STI.isPPC64() ? -8U : -4U;
59 
60  // SVR4 ABI: First slot in the general register save area.
61  return STI.isPPC64() ? -8U : -4U;
62 }
63 
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65  if (STI.isDarwinABI() || STI.isPPC64())
66  return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
67 
68  // SVR4 ABI:
69  return 8;
70 }
71 
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73  if (STI.isDarwinABI())
74  return STI.isPPC64() ? -16U : -8U;
75 
76  // SVR4 ABI: First slot in the general register save area.
77  return STI.isPPC64()
78  ? -16U
79  : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
80 }
81 
83  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
84  STI.getPlatformStackAlignment(), 0),
85  Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
86  TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
87  FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
88  LinkageSize(computeLinkageSize(Subtarget)),
89  BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
90 
91 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
93  unsigned &NumEntries) const {
94  if (Subtarget.isDarwinABI()) {
95  NumEntries = 1;
96  if (Subtarget.isPPC64()) {
97  static const SpillSlot darwin64Offsets = {PPC::X31, -8};
98  return &darwin64Offsets;
99  } else {
100  static const SpillSlot darwinOffsets = {PPC::R31, -4};
101  return &darwinOffsets;
102  }
103  }
104 
105  // Early exit if not using the SVR4 ABI.
106  if (!Subtarget.isSVR4ABI()) {
107  NumEntries = 0;
108  return nullptr;
109  }
110 
111  // Note that the offsets here overlap, but this is fixed up in
112  // processFunctionBeforeFrameFinalized.
113 
114  static const SpillSlot Offsets[] = {
115  // Floating-point register save area offsets.
116  {PPC::F31, -8},
117  {PPC::F30, -16},
118  {PPC::F29, -24},
119  {PPC::F28, -32},
120  {PPC::F27, -40},
121  {PPC::F26, -48},
122  {PPC::F25, -56},
123  {PPC::F24, -64},
124  {PPC::F23, -72},
125  {PPC::F22, -80},
126  {PPC::F21, -88},
127  {PPC::F20, -96},
128  {PPC::F19, -104},
129  {PPC::F18, -112},
130  {PPC::F17, -120},
131  {PPC::F16, -128},
132  {PPC::F15, -136},
133  {PPC::F14, -144},
134 
135  // General register save area offsets.
136  {PPC::R31, -4},
137  {PPC::R30, -8},
138  {PPC::R29, -12},
139  {PPC::R28, -16},
140  {PPC::R27, -20},
141  {PPC::R26, -24},
142  {PPC::R25, -28},
143  {PPC::R24, -32},
144  {PPC::R23, -36},
145  {PPC::R22, -40},
146  {PPC::R21, -44},
147  {PPC::R20, -48},
148  {PPC::R19, -52},
149  {PPC::R18, -56},
150  {PPC::R17, -60},
151  {PPC::R16, -64},
152  {PPC::R15, -68},
153  {PPC::R14, -72},
154 
155  // CR save area offset. We map each of the nonvolatile CR fields
156  // to the slot for CR2, which is the first of the nonvolatile CR
157  // fields to be assigned, so that we only allocate one save slot.
158  // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
159  {PPC::CR2, -4},
160 
161  // VRSAVE save area offset.
162  {PPC::VRSAVE, -4},
163 
164  // Vector register save area
165  {PPC::V31, -16},
166  {PPC::V30, -32},
167  {PPC::V29, -48},
168  {PPC::V28, -64},
169  {PPC::V27, -80},
170  {PPC::V26, -96},
171  {PPC::V25, -112},
172  {PPC::V24, -128},
173  {PPC::V23, -144},
174  {PPC::V22, -160},
175  {PPC::V21, -176},
176  {PPC::V20, -192}};
177 
178  static const SpillSlot Offsets64[] = {
179  // Floating-point register save area offsets.
180  {PPC::F31, -8},
181  {PPC::F30, -16},
182  {PPC::F29, -24},
183  {PPC::F28, -32},
184  {PPC::F27, -40},
185  {PPC::F26, -48},
186  {PPC::F25, -56},
187  {PPC::F24, -64},
188  {PPC::F23, -72},
189  {PPC::F22, -80},
190  {PPC::F21, -88},
191  {PPC::F20, -96},
192  {PPC::F19, -104},
193  {PPC::F18, -112},
194  {PPC::F17, -120},
195  {PPC::F16, -128},
196  {PPC::F15, -136},
197  {PPC::F14, -144},
198 
199  // General register save area offsets.
200  {PPC::X31, -8},
201  {PPC::X30, -16},
202  {PPC::X29, -24},
203  {PPC::X28, -32},
204  {PPC::X27, -40},
205  {PPC::X26, -48},
206  {PPC::X25, -56},
207  {PPC::X24, -64},
208  {PPC::X23, -72},
209  {PPC::X22, -80},
210  {PPC::X21, -88},
211  {PPC::X20, -96},
212  {PPC::X19, -104},
213  {PPC::X18, -112},
214  {PPC::X17, -120},
215  {PPC::X16, -128},
216  {PPC::X15, -136},
217  {PPC::X14, -144},
218 
219  // VRSAVE save area offset.
220  {PPC::VRSAVE, -4},
221 
222  // Vector register save area
223  {PPC::V31, -16},
224  {PPC::V30, -32},
225  {PPC::V29, -48},
226  {PPC::V28, -64},
227  {PPC::V27, -80},
228  {PPC::V26, -96},
229  {PPC::V25, -112},
230  {PPC::V24, -128},
231  {PPC::V23, -144},
232  {PPC::V22, -160},
233  {PPC::V21, -176},
234  {PPC::V20, -192}};
235 
236  if (Subtarget.isPPC64()) {
237  NumEntries = array_lengthof(Offsets64);
238 
239  return Offsets64;
240  } else {
241  NumEntries = array_lengthof(Offsets);
242 
243  return Offsets;
244  }
245 }
246 
247 /// RemoveVRSaveCode - We have found that this function does not need any code
248 /// to manipulate the VRSAVE register, even though it uses vector registers.
249 /// This can happen when the only registers used are known to be live in or out
250 /// of the function. Remove all of the VRSAVE related code from the function.
251 /// FIXME: The removal of the code results in a compile failure at -O0 when the
252 /// function contains a function call, as the GPR containing original VRSAVE
253 /// contents is spilled and reloaded around the call. Without the prolog code,
254 /// the spill instruction refers to an undefined register. This code needs
255 /// to account for all uses of that GPR.
257  MachineBasicBlock *Entry = MI.getParent();
258  MachineFunction *MF = Entry->getParent();
259 
260  // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
262  ++MBBI;
263  assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
264  MBBI->eraseFromParent();
265 
266  bool RemovedAllMTVRSAVEs = true;
267  // See if we can find and remove the MTVRSAVE instruction from all of the
268  // epilog blocks.
269  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
270  // If last instruction is a return instruction, add an epilogue
271  if (I->isReturnBlock()) {
272  bool FoundIt = false;
273  for (MBBI = I->end(); MBBI != I->begin(); ) {
274  --MBBI;
275  if (MBBI->getOpcode() == PPC::MTVRSAVE) {
276  MBBI->eraseFromParent(); // remove it.
277  FoundIt = true;
278  break;
279  }
280  }
281  RemovedAllMTVRSAVEs &= FoundIt;
282  }
283  }
284 
285  // If we found and removed all MTVRSAVE instructions, remove the read of
286  // VRSAVE as well.
287  if (RemovedAllMTVRSAVEs) {
288  MBBI = MI;
289  assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
290  --MBBI;
291  assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
292  MBBI->eraseFromParent();
293  }
294 
295  // Finally, nuke the UPDATE_VRSAVE.
296  MI.eraseFromParent();
297 }
298 
299 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
300 // instruction selector. Based on the vector registers that have been used,
301 // transform this into the appropriate ORI instruction.
303  MachineFunction *MF = MI.getParent()->getParent();
304  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
305  DebugLoc dl = MI.getDebugLoc();
306 
307  const MachineRegisterInfo &MRI = MF->getRegInfo();
308  unsigned UsedRegMask = 0;
309  for (unsigned i = 0; i != 32; ++i)
310  if (MRI.isPhysRegModified(VRRegNo[i]))
311  UsedRegMask |= 1 << (31-i);
312 
313  // Live in and live out values already must be in the mask, so don't bother
314  // marking them.
316  I = MF->getRegInfo().livein_begin(),
317  E = MF->getRegInfo().livein_end(); I != E; ++I) {
318  unsigned RegNo = TRI->getEncodingValue(I->first);
319  if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
320  UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
321  }
322 
323  // Live out registers appear as use operands on return instructions.
324  for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
325  UsedRegMask != 0 && BI != BE; ++BI) {
326  const MachineBasicBlock &MBB = *BI;
327  if (!MBB.isReturnBlock())
328  continue;
329  const MachineInstr &Ret = MBB.back();
330  for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
331  const MachineOperand &MO = Ret.getOperand(I);
332  if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
333  continue;
334  unsigned RegNo = TRI->getEncodingValue(MO.getReg());
335  UsedRegMask &= ~(1 << (31-RegNo));
336  }
337  }
338 
339  // If no registers are used, turn this into a copy.
340  if (UsedRegMask == 0) {
341  // Remove all VRSAVE code.
342  RemoveVRSaveCode(MI);
343  return;
344  }
345 
346  unsigned SrcReg = MI.getOperand(1).getReg();
347  unsigned DstReg = MI.getOperand(0).getReg();
348 
349  if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
350  if (DstReg != SrcReg)
351  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
352  .addReg(SrcReg)
353  .addImm(UsedRegMask);
354  else
355  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
356  .addReg(SrcReg, RegState::Kill)
357  .addImm(UsedRegMask);
358  } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
359  if (DstReg != SrcReg)
360  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
361  .addReg(SrcReg)
362  .addImm(UsedRegMask >> 16);
363  else
364  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
365  .addReg(SrcReg, RegState::Kill)
366  .addImm(UsedRegMask >> 16);
367  } else {
368  if (DstReg != SrcReg)
369  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
370  .addReg(SrcReg)
371  .addImm(UsedRegMask >> 16);
372  else
373  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
374  .addReg(SrcReg, RegState::Kill)
375  .addImm(UsedRegMask >> 16);
376 
377  BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
378  .addReg(DstReg, RegState::Kill)
379  .addImm(UsedRegMask & 0xFFFF);
380  }
381 
382  // Remove the old UPDATE_VRSAVE instruction.
383  MI.eraseFromParent();
384 }
385 
386 static bool spillsCR(const MachineFunction &MF) {
387  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
388  return FuncInfo->isCRSpilled();
389 }
390 
391 static bool spillsVRSAVE(const MachineFunction &MF) {
392  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
393  return FuncInfo->isVRSAVESpilled();
394 }
395 
396 static bool hasSpills(const MachineFunction &MF) {
397  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
398  return FuncInfo->hasSpills();
399 }
400 
401 static bool hasNonRISpills(const MachineFunction &MF) {
402  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
403  return FuncInfo->hasNonRISpills();
404 }
405 
406 /// MustSaveLR - Return true if this function requires that we save the LR
407 /// register onto the stack in the prolog and restore it in the epilog of the
408 /// function.
409 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
410  const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
411 
412  // We need a save/restore of LR if there is any def of LR (which is
413  // defined by calls, including the PIC setup sequence), or if there is
414  // some use of the LR stack slot (e.g. for builtin_return_address).
415  // (LR comes in 32 and 64 bit versions.)
417  return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
418 }
419 
420 /// determineFrameLayout - Determine the size of the frame and maximum call
421 /// frame size.
423  bool UpdateMF,
424  bool UseEstimate) const {
425  MachineFrameInfo &MFI = MF.getFrameInfo();
426 
427  // Get the number of bytes to allocate from the FrameInfo
428  unsigned FrameSize =
429  UseEstimate ? MFI.estimateStackSize(MF) : MFI.getStackSize();
430 
431  // Get stack alignments. The frame must be aligned to the greatest of these:
432  unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
433  unsigned MaxAlign = MFI.getMaxAlignment(); // algmt required by data in frame
434  unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
435 
436  const PPCRegisterInfo *RegInfo =
437  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
438 
439  // If we are a leaf function, and use up to 224 bytes of stack space,
440  // don't have a frame pointer, calls, or dynamic alloca then we do not need
441  // to adjust the stack pointer (we fit in the Red Zone).
442  // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
443  // stackless code if all local vars are reg-allocated.
444  bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
445  unsigned LR = RegInfo->getRARegister();
446  if (!DisableRedZone &&
447  (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
448  !Subtarget.isSVR4ABI() || // allocated locals.
449  FrameSize == 0) &&
450  FrameSize <= 224 && // Fits in red zone.
451  !MFI.hasVarSizedObjects() && // No dynamic alloca.
452  !MFI.adjustsStack() && // No calls.
453  !MustSaveLR(MF, LR) &&
454  !RegInfo->hasBasePointer(MF)) { // No special alignment.
455  // No need for frame
456  if (UpdateMF)
457  MFI.setStackSize(0);
458  return 0;
459  }
460 
461  // Get the maximum call frame size of all the calls.
462  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
463 
464  // Maximum call frame needs to be at least big enough for linkage area.
465  unsigned minCallFrameSize = getLinkageSize();
466  maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
467 
468  // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
469  // that allocations will be aligned.
470  if (MFI.hasVarSizedObjects())
471  maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
472 
473  // Update maximum call frame size.
474  if (UpdateMF)
475  MFI.setMaxCallFrameSize(maxCallFrameSize);
476 
477  // Include call frame size in total.
478  FrameSize += maxCallFrameSize;
479 
480  // Make sure the frame is aligned.
481  FrameSize = (FrameSize + AlignMask) & ~AlignMask;
482 
483  // Update frame info.
484  if (UpdateMF)
485  MFI.setStackSize(FrameSize);
486 
487  return FrameSize;
488 }
489 
490 // hasFP - Return true if the specified function actually has a dedicated frame
491 // pointer register.
493  const MachineFrameInfo &MFI = MF.getFrameInfo();
494  // FIXME: This is pretty much broken by design: hasFP() might be called really
495  // early, before the stack layout was calculated and thus hasFP() might return
496  // true or false here depending on the time of call.
497  return (MFI.getStackSize()) && needsFP(MF);
498 }
499 
500 // needsFP - Return true if the specified function should have a dedicated frame
501 // pointer register. This is true if the function has variable sized allocas or
502 // if frame pointer elimination is disabled.
504  const MachineFrameInfo &MFI = MF.getFrameInfo();
505 
506  // Naked functions have no stack frame pushed, so we don't have a frame
507  // pointer.
508  if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
509  return false;
510 
511  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
512  MFI.hasVarSizedObjects() || MFI.hasStackMap() || MFI.hasPatchPoint() ||
514  MF.getInfo<PPCFunctionInfo>()->hasFastCall());
515 }
516 
518  bool is31 = needsFP(MF);
519  unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
520  unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
521 
522  const PPCRegisterInfo *RegInfo =
523  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
524  bool HasBP = RegInfo->hasBasePointer(MF);
525  unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
526  unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
527 
528  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
529  BI != BE; ++BI)
530  for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
531  --MBBI;
532  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
533  MachineOperand &MO = MBBI->getOperand(I);
534  if (!MO.isReg())
535  continue;
536 
537  switch (MO.getReg()) {
538  case PPC::FP:
539  MO.setReg(FPReg);
540  break;
541  case PPC::FP8:
542  MO.setReg(FP8Reg);
543  break;
544  case PPC::BP:
545  MO.setReg(BPReg);
546  break;
547  case PPC::BP8:
548  MO.setReg(BP8Reg);
549  break;
550 
551  }
552  }
553  }
554 }
555 
556 /* This function will do the following:
557  - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12
558  respectively (defaults recommended by the ABI) and return true
559  - If MBB is not an entry block, initialize the register scavenger and look
560  for available registers.
561  - If the defaults (R0/R12) are available, return true
562  - If TwoUniqueRegsRequired is set to true, it looks for two unique
563  registers. Otherwise, look for a single available register.
564  - If the required registers are found, set SR1 and SR2 and return true.
565  - If the required registers are not found, set SR2 or both SR1 and SR2 to
566  PPC::NoRegister and return false.
567 
568  Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired
569  is not set, this function will attempt to find two different registers, but
570  still return true if only one register is available (and set SR1 == SR2).
571 */
572 bool
573 PPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB,
574  bool UseAtEnd,
575  bool TwoUniqueRegsRequired,
576  unsigned *SR1,
577  unsigned *SR2) const {
578  RegScavenger RS;
579  unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
580  unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12;
581 
582  // Set the defaults for the two scratch registers.
583  if (SR1)
584  *SR1 = R0;
585 
586  if (SR2) {
587  assert (SR1 && "Asking for the second scratch register but not the first?");
588  *SR2 = R12;
589  }
590 
591  // If MBB is an entry or exit block, use R0 and R12 as the scratch registers.
592  if ((UseAtEnd && MBB->isReturnBlock()) ||
593  (!UseAtEnd && (&MBB->getParent()->front() == MBB)))
594  return true;
595 
596  RS.enterBasicBlock(*MBB);
597 
598  if (UseAtEnd && !MBB->empty()) {
599  // The scratch register will be used at the end of the block, so must
600  // consider all registers used within the block
601 
603  // If no terminator, back iterator up to previous instruction.
604  if (MBBI == MBB->end())
605  MBBI = std::prev(MBBI);
606 
607  if (MBBI != MBB->begin())
608  RS.forward(MBBI);
609  }
610 
611  // If the two registers are available, we're all good.
612  // Note that we only return here if both R0 and R12 are available because
613  // although the function may not require two unique registers, it may benefit
614  // from having two so we should try to provide them.
615  if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12))
616  return true;
617 
618  // Get the list of callee-saved registers for the target.
619  const PPCRegisterInfo *RegInfo =
620  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
621  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
622 
623  // Get all the available registers in the block.
624  BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass :
625  &PPC::GPRCRegClass);
626 
627  // We shouldn't use callee-saved registers as scratch registers as they may be
628  // available when looking for a candidate block for shrink wrapping but not
629  // available when the actual prologue/epilogue is being emitted because they
630  // were added as live-in to the prologue block by PrologueEpilogueInserter.
631  for (int i = 0; CSRegs[i]; ++i)
632  BV.reset(CSRegs[i]);
633 
634  // Set the first scratch register to the first available one.
635  if (SR1) {
636  int FirstScratchReg = BV.find_first();
637  *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg;
638  }
639 
640  // If there is another one available, set the second scratch register to that.
641  // Otherwise, set it to either PPC::NoRegister if this function requires two
642  // or to whatever SR1 is set to if this function doesn't require two.
643  if (SR2) {
644  int SecondScratchReg = BV.find_next(*SR1);
645  if (SecondScratchReg != -1)
646  *SR2 = SecondScratchReg;
647  else
648  *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1;
649  }
650 
651  // Now that we've done our best to provide both registers, double check
652  // whether we were unable to provide enough.
653  if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U))
654  return false;
655 
656  return true;
657 }
658 
659 // We need a scratch register for spilling LR and for spilling CR. By default,
660 // we use two scratch registers to hide latency. However, if only one scratch
661 // register is available, we can adjust for that by not overlapping the spill
662 // code. However, if we need to realign the stack (i.e. have a base pointer)
663 // and the stack frame is large, we need two scratch registers.
664 bool
665 PPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const {
666  const PPCRegisterInfo *RegInfo =
667  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
668  MachineFunction &MF = *(MBB->getParent());
669  bool HasBP = RegInfo->hasBasePointer(MF);
670  unsigned FrameSize = determineFrameLayout(MF, false);
671  int NegFrameSize = -FrameSize;
672  bool IsLargeFrame = !isInt<16>(NegFrameSize);
673  MachineFrameInfo &MFI = MF.getFrameInfo();
674  unsigned MaxAlign = MFI.getMaxAlignment();
675  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
676 
677  return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
678 }
679 
681  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
682 
683  return findScratchRegister(TmpMBB, false,
684  twoUniqueScratchRegsRequired(TmpMBB));
685 }
686 
688  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
689 
690  return findScratchRegister(TmpMBB, true);
691 }
692 
694  MachineBasicBlock &MBB) const {
695  MachineBasicBlock::iterator MBBI = MBB.begin();
696  MachineFrameInfo &MFI = MF.getFrameInfo();
697  const PPCInstrInfo &TII =
698  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
699  const PPCRegisterInfo *RegInfo =
700  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
701 
702  MachineModuleInfo &MMI = MF.getMMI();
703  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
704  DebugLoc dl;
705  bool needsCFI = MMI.hasDebugInfo() ||
707 
708  // Get processor type.
709  bool isPPC64 = Subtarget.isPPC64();
710  // Get the ABI.
711  bool isSVR4ABI = Subtarget.isSVR4ABI();
712  bool isELFv2ABI = Subtarget.isELFv2ABI();
713  assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
714  "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
715 
716  // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
717  // process it.
718  if (!isSVR4ABI)
719  for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
720  if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
721  HandleVRSaveUpdate(*MBBI, TII);
722  break;
723  }
724  }
725 
726  // Move MBBI back to the beginning of the prologue block.
727  MBBI = MBB.begin();
728 
729  // Work out frame sizes.
730  unsigned FrameSize = determineFrameLayout(MF);
731  int NegFrameSize = -FrameSize;
732  if (!isInt<32>(NegFrameSize))
733  llvm_unreachable("Unhandled stack size!");
734 
735  if (MFI.isFrameAddressTaken())
737 
738  // Check if the link register (LR) must be saved.
740  bool MustSaveLR = FI->mustSaveLR();
741  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
742  bool MustSaveCR = !MustSaveCRs.empty();
743  // Do we have a frame pointer and/or base pointer for this function?
744  bool HasFP = hasFP(MF);
745  bool HasBP = RegInfo->hasBasePointer(MF);
746  bool HasRedZone = isPPC64 || !isSVR4ABI;
747 
748  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
749  unsigned BPReg = RegInfo->getBaseRegister(MF);
750  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
751  unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
752  unsigned ScratchReg = 0;
753  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
754  // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
755  const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
756  : PPC::MFLR );
757  const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
758  : PPC::STW );
759  const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
760  : PPC::STWU );
761  const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
762  : PPC::STWUX);
763  const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
764  : PPC::LIS );
765  const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
766  : PPC::ORI );
767  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
768  : PPC::OR );
769  const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
770  : PPC::SUBFC);
771  const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
772  : PPC::SUBFIC);
773 
774  // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
775  // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
776  // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
777  // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
778  assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
779  "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
780 
781  // Using the same bool variable as below to suppress compiler warnings.
782  bool SingleScratchReg =
783  findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB),
784  &ScratchReg, &TempReg);
785  assert(SingleScratchReg &&
786  "Required number of registers not available in this block");
787 
788  SingleScratchReg = ScratchReg == TempReg;
789 
790  int LROffset = getReturnSaveOffset();
791 
792  int FPOffset = 0;
793  if (HasFP) {
794  if (isSVR4ABI) {
795  MachineFrameInfo &MFI = MF.getFrameInfo();
796  int FPIndex = FI->getFramePointerSaveIndex();
797  assert(FPIndex && "No Frame Pointer Save Slot!");
798  FPOffset = MFI.getObjectOffset(FPIndex);
799  } else {
800  FPOffset = getFramePointerSaveOffset();
801  }
802  }
803 
804  int BPOffset = 0;
805  if (HasBP) {
806  if (isSVR4ABI) {
807  MachineFrameInfo &MFI = MF.getFrameInfo();
808  int BPIndex = FI->getBasePointerSaveIndex();
809  assert(BPIndex && "No Base Pointer Save Slot!");
810  BPOffset = MFI.getObjectOffset(BPIndex);
811  } else {
812  BPOffset = getBasePointerSaveOffset();
813  }
814  }
815 
816  int PBPOffset = 0;
817  if (FI->usesPICBase()) {
818  MachineFrameInfo &MFI = MF.getFrameInfo();
819  int PBPIndex = FI->getPICBasePointerSaveIndex();
820  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
821  PBPOffset = MFI.getObjectOffset(PBPIndex);
822  }
823 
824  // Get stack alignments.
825  unsigned MaxAlign = MFI.getMaxAlignment();
826  if (HasBP && MaxAlign > 1)
827  assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
828  "Invalid alignment!");
829 
830  // Frames of 32KB & larger require special handling because they cannot be
831  // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
832  bool isLargeFrame = !isInt<16>(NegFrameSize);
833 
834  assert((isPPC64 || !MustSaveCR) &&
835  "Prologue CR saving supported only in 64-bit mode");
836 
837  // If we need to spill the CR and the LR but we don't have two separate
838  // registers available, we must spill them one at a time
839  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
840  // In the ELFv2 ABI, we are not required to save all CR fields.
841  // If only one or two CR fields are clobbered, it is more efficient to use
842  // mfocrf to selectively save just those fields, because mfocrf has short
843  // latency compares to mfcr.
844  unsigned MfcrOpcode = PPC::MFCR8;
845  unsigned CrState = RegState::ImplicitKill;
846  if (isELFv2ABI && MustSaveCRs.size() == 1) {
847  MfcrOpcode = PPC::MFOCRF8;
848  CrState = RegState::Kill;
849  }
850  MachineInstrBuilder MIB =
851  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
852  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
853  MIB.addReg(MustSaveCRs[i], CrState);
854  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
855  .addReg(TempReg, getKillRegState(true))
856  .addImm(8)
857  .addReg(SPReg);
858  }
859 
860  if (MustSaveLR)
861  BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
862 
863  if (MustSaveCR &&
864  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
865  // In the ELFv2 ABI, we are not required to save all CR fields.
866  // If only one or two CR fields are clobbered, it is more efficient to use
867  // mfocrf to selectively save just those fields, because mfocrf has short
868  // latency compares to mfcr.
869  unsigned MfcrOpcode = PPC::MFCR8;
870  unsigned CrState = RegState::ImplicitKill;
871  if (isELFv2ABI && MustSaveCRs.size() == 1) {
872  MfcrOpcode = PPC::MFOCRF8;
873  CrState = RegState::Kill;
874  }
875  MachineInstrBuilder MIB =
876  BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
877  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
878  MIB.addReg(MustSaveCRs[i], CrState);
879  }
880 
881  if (HasRedZone) {
882  if (HasFP)
883  BuildMI(MBB, MBBI, dl, StoreInst)
884  .addReg(FPReg)
885  .addImm(FPOffset)
886  .addReg(SPReg);
887  if (FI->usesPICBase())
888  BuildMI(MBB, MBBI, dl, StoreInst)
889  .addReg(PPC::R30)
890  .addImm(PBPOffset)
891  .addReg(SPReg);
892  if (HasBP)
893  BuildMI(MBB, MBBI, dl, StoreInst)
894  .addReg(BPReg)
895  .addImm(BPOffset)
896  .addReg(SPReg);
897  }
898 
899  if (MustSaveLR)
900  BuildMI(MBB, MBBI, dl, StoreInst)
901  .addReg(ScratchReg, getKillRegState(true))
902  .addImm(LROffset)
903  .addReg(SPReg);
904 
905  if (MustSaveCR &&
906  !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
907  assert(HasRedZone && "A red zone is always available on PPC64");
908  BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
909  .addReg(TempReg, getKillRegState(true))
910  .addImm(8)
911  .addReg(SPReg);
912  }
913 
914  // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
915  if (!FrameSize)
916  return;
917 
918  // Adjust stack pointer: r1 += NegFrameSize.
919  // If there is a preferred stack alignment, align R1 now
920 
921  if (HasBP && HasRedZone) {
922  // Save a copy of r1 as the base pointer.
923  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
924  .addReg(SPReg)
925  .addReg(SPReg);
926  }
927 
928  // Have we generated a STUX instruction to claim stack frame? If so,
929  // the negated frame size will be placed in ScratchReg.
930  bool HasSTUX = false;
931 
932  // This condition must be kept in sync with canUseAsPrologue.
933  if (HasBP && MaxAlign > 1) {
934  if (isPPC64)
935  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
936  .addReg(SPReg)
937  .addImm(0)
938  .addImm(64 - Log2_32(MaxAlign));
939  else // PPC32...
940  BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
941  .addReg(SPReg)
942  .addImm(0)
943  .addImm(32 - Log2_32(MaxAlign))
944  .addImm(31);
945  if (!isLargeFrame) {
946  BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
947  .addReg(ScratchReg, RegState::Kill)
948  .addImm(NegFrameSize);
949  } else {
950  assert(!SingleScratchReg && "Only a single scratch reg available");
951  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
952  .addImm(NegFrameSize >> 16);
953  BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
954  .addReg(TempReg, RegState::Kill)
955  .addImm(NegFrameSize & 0xFFFF);
956  BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
957  .addReg(ScratchReg, RegState::Kill)
958  .addReg(TempReg, RegState::Kill);
959  }
960 
961  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
962  .addReg(SPReg, RegState::Kill)
963  .addReg(SPReg)
964  .addReg(ScratchReg);
965  HasSTUX = true;
966 
967  } else if (!isLargeFrame) {
968  BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
969  .addReg(SPReg)
970  .addImm(NegFrameSize)
971  .addReg(SPReg);
972 
973  } else {
974  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
975  .addImm(NegFrameSize >> 16);
976  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
977  .addReg(ScratchReg, RegState::Kill)
978  .addImm(NegFrameSize & 0xFFFF);
979  BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
980  .addReg(SPReg, RegState::Kill)
981  .addReg(SPReg)
982  .addReg(ScratchReg);
983  HasSTUX = true;
984  }
985 
986  if (!HasRedZone) {
987  assert(!isPPC64 && "A red zone is always available on PPC64");
988  if (HasSTUX) {
989  // The negated frame size is in ScratchReg, and the SPReg has been
990  // decremented by the frame size: SPReg = old SPReg + ScratchReg.
991  // Since FPOffset, PBPOffset, etc. are relative to the beginning of
992  // the stack frame (i.e. the old SP), ideally, we would put the old
993  // SP into a register and use it as the base for the stores. The
994  // problem is that the only available register may be ScratchReg,
995  // which could be R0, and R0 cannot be used as a base address.
996 
997  // First, set ScratchReg to the old SP. This may need to be modified
998  // later.
999  BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
1000  .addReg(ScratchReg, RegState::Kill)
1001  .addReg(SPReg);
1002 
1003  if (ScratchReg == PPC::R0) {
1004  // R0 cannot be used as a base register, but it can be used as an
1005  // index in a store-indexed.
1006  int LastOffset = 0;
1007  if (HasFP) {
1008  // R0 += (FPOffset-LastOffset).
1009  // Need addic, since addi treats R0 as 0.
1010  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1011  .addReg(ScratchReg)
1012  .addImm(FPOffset-LastOffset);
1013  LastOffset = FPOffset;
1014  // Store FP into *R0.
1015  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1016  .addReg(FPReg, RegState::Kill) // Save FP.
1017  .addReg(PPC::ZERO)
1018  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1019  }
1020  if (FI->usesPICBase()) {
1021  // R0 += (PBPOffset-LastOffset).
1022  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1023  .addReg(ScratchReg)
1024  .addImm(PBPOffset-LastOffset);
1025  LastOffset = PBPOffset;
1026  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1027  .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
1028  .addReg(PPC::ZERO)
1029  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1030  }
1031  if (HasBP) {
1032  // R0 += (BPOffset-LastOffset).
1033  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1034  .addReg(ScratchReg)
1035  .addImm(BPOffset-LastOffset);
1036  LastOffset = BPOffset;
1037  BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1038  .addReg(BPReg, RegState::Kill) // Save BP.
1039  .addReg(PPC::ZERO)
1040  .addReg(ScratchReg); // This will be the index (R0 is ok here).
1041  // BP = R0-LastOffset
1042  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1043  .addReg(ScratchReg, RegState::Kill)
1044  .addImm(-LastOffset);
1045  }
1046  } else {
1047  // ScratchReg is not R0, so use it as the base register. It is
1048  // already set to the old SP, so we can use the offsets directly.
1049 
1050  // Now that the stack frame has been allocated, save all the necessary
1051  // registers using ScratchReg as the base address.
1052  if (HasFP)
1053  BuildMI(MBB, MBBI, dl, StoreInst)
1054  .addReg(FPReg)
1055  .addImm(FPOffset)
1056  .addReg(ScratchReg);
1057  if (FI->usesPICBase())
1058  BuildMI(MBB, MBBI, dl, StoreInst)
1059  .addReg(PPC::R30)
1060  .addImm(PBPOffset)
1061  .addReg(ScratchReg);
1062  if (HasBP) {
1063  BuildMI(MBB, MBBI, dl, StoreInst)
1064  .addReg(BPReg)
1065  .addImm(BPOffset)
1066  .addReg(ScratchReg);
1067  BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1068  .addReg(ScratchReg, RegState::Kill)
1069  .addReg(ScratchReg);
1070  }
1071  }
1072  } else {
1073  // The frame size is a known 16-bit constant (fitting in the immediate
1074  // field of STWU). To be here we have to be compiling for PPC32.
1075  // Since the SPReg has been decreased by FrameSize, add it back to each
1076  // offset.
1077  if (HasFP)
1078  BuildMI(MBB, MBBI, dl, StoreInst)
1079  .addReg(FPReg)
1080  .addImm(FrameSize + FPOffset)
1081  .addReg(SPReg);
1082  if (FI->usesPICBase())
1083  BuildMI(MBB, MBBI, dl, StoreInst)
1084  .addReg(PPC::R30)
1085  .addImm(FrameSize + PBPOffset)
1086  .addReg(SPReg);
1087  if (HasBP) {
1088  BuildMI(MBB, MBBI, dl, StoreInst)
1089  .addReg(BPReg)
1090  .addImm(FrameSize + BPOffset)
1091  .addReg(SPReg);
1092  BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1093  .addReg(SPReg)
1094  .addImm(FrameSize);
1095  }
1096  }
1097  }
1098 
1099  // Add Call Frame Information for the instructions we generated above.
1100  if (needsCFI) {
1101  unsigned CFIIndex;
1102 
1103  if (HasBP) {
1104  // Define CFA in terms of BP. Do this in preference to using FP/SP,
1105  // because if the stack needed aligning then CFA won't be at a fixed
1106  // offset from FP/SP.
1107  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1108  CFIIndex = MF.addFrameInst(
1110  } else {
1111  // Adjust the definition of CFA to account for the change in SP.
1112  assert(NegFrameSize);
1113  CFIIndex = MF.addFrameInst(
1114  MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
1115  }
1116  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1117  .addCFIIndex(CFIIndex);
1118 
1119  if (HasFP) {
1120  // Describe where FP was saved, at a fixed offset from CFA.
1121  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1122  CFIIndex = MF.addFrameInst(
1123  MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
1124  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1125  .addCFIIndex(CFIIndex);
1126  }
1127 
1128  if (FI->usesPICBase()) {
1129  // Describe where FP was saved, at a fixed offset from CFA.
1130  unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
1131  CFIIndex = MF.addFrameInst(
1132  MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
1133  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1134  .addCFIIndex(CFIIndex);
1135  }
1136 
1137  if (HasBP) {
1138  // Describe where BP was saved, at a fixed offset from CFA.
1139  unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
1140  CFIIndex = MF.addFrameInst(
1141  MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
1142  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1143  .addCFIIndex(CFIIndex);
1144  }
1145 
1146  if (MustSaveLR) {
1147  // Describe where LR was saved, at a fixed offset from CFA.
1148  unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
1149  CFIIndex = MF.addFrameInst(
1150  MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
1151  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1152  .addCFIIndex(CFIIndex);
1153  }
1154  }
1155 
1156  // If there is a frame pointer, copy R1 into R31
1157  if (HasFP) {
1158  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1159  .addReg(SPReg)
1160  .addReg(SPReg);
1161 
1162  if (!HasBP && needsCFI) {
1163  // Change the definition of CFA from SP+offset to FP+offset, because SP
1164  // will change at every alloca.
1165  unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
1166  unsigned CFIIndex = MF.addFrameInst(
1168 
1169  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1170  .addCFIIndex(CFIIndex);
1171  }
1172  }
1173 
1174  if (needsCFI) {
1175  // Describe where callee saved registers were saved, at fixed offsets from
1176  // CFA.
1177  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1178  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1179  unsigned Reg = CSI[I].getReg();
1180  if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1181 
1182  // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
1183  // subregisters of CR2. We just need to emit a move of CR2.
1184  if (PPC::CRBITRCRegClass.contains(Reg))
1185  continue;
1186 
1187  // For SVR4, don't emit a move for the CR spill slot if we haven't
1188  // spilled CRs.
1189  if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1190  && !MustSaveCR)
1191  continue;
1192 
1193  // For 64-bit SVR4 when we have spilled CRs, the spill location
1194  // is SP+8, not a frame-relative slot.
1195  if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1196  // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
1197  // the whole CR word. In the ELFv2 ABI, every CR that was
1198  // actually saved gets its own CFI record.
1199  unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1200  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1201  nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
1202  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1203  .addCFIIndex(CFIIndex);
1204  continue;
1205  }
1206 
1207  int Offset = MFI.getObjectOffset(CSI[I].getFrameIdx());
1208  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1209  nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
1210  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1211  .addCFIIndex(CFIIndex);
1212  }
1213  }
1214 }
1215 
1217  MachineBasicBlock &MBB) const {
1219  DebugLoc dl;
1220 
1221  if (MBBI != MBB.end())
1222  dl = MBBI->getDebugLoc();
1223 
1224  const PPCInstrInfo &TII =
1225  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1226  const PPCRegisterInfo *RegInfo =
1227  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1228 
1229  // Get alignment info so we know how to restore the SP.
1230  const MachineFrameInfo &MFI = MF.getFrameInfo();
1231 
1232  // Get the number of bytes allocated from the FrameInfo.
1233  int FrameSize = MFI.getStackSize();
1234 
1235  // Get processor type.
1236  bool isPPC64 = Subtarget.isPPC64();
1237  // Get the ABI.
1238  bool isSVR4ABI = Subtarget.isSVR4ABI();
1239 
1240  // Check if the link register (LR) has been saved.
1242  bool MustSaveLR = FI->mustSaveLR();
1243  const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
1244  bool MustSaveCR = !MustSaveCRs.empty();
1245  // Do we have a frame pointer and/or base pointer for this function?
1246  bool HasFP = hasFP(MF);
1247  bool HasBP = RegInfo->hasBasePointer(MF);
1248  bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI();
1249 
1250  unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1251  unsigned BPReg = RegInfo->getBaseRegister(MF);
1252  unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1253  unsigned ScratchReg = 0;
1254  unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1255  const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1256  : PPC::MTLR );
1257  const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1258  : PPC::LWZ );
1259  const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1260  : PPC::LIS );
1261  const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1262  : PPC::OR );
1263  const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1264  : PPC::ORI );
1265  const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1266  : PPC::ADDI );
1267  const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1268  : PPC::ADD4 );
1269 
1270  int LROffset = getReturnSaveOffset();
1271 
1272  int FPOffset = 0;
1273 
1274  // Using the same bool variable as below to suppress compiler warnings.
1275  bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg,
1276  &TempReg);
1277  assert(SingleScratchReg &&
1278  "Could not find an available scratch register");
1279 
1280  SingleScratchReg = ScratchReg == TempReg;
1281 
1282  if (HasFP) {
1283  if (isSVR4ABI) {
1284  int FPIndex = FI->getFramePointerSaveIndex();
1285  assert(FPIndex && "No Frame Pointer Save Slot!");
1286  FPOffset = MFI.getObjectOffset(FPIndex);
1287  } else {
1288  FPOffset = getFramePointerSaveOffset();
1289  }
1290  }
1291 
1292  int BPOffset = 0;
1293  if (HasBP) {
1294  if (isSVR4ABI) {
1295  int BPIndex = FI->getBasePointerSaveIndex();
1296  assert(BPIndex && "No Base Pointer Save Slot!");
1297  BPOffset = MFI.getObjectOffset(BPIndex);
1298  } else {
1299  BPOffset = getBasePointerSaveOffset();
1300  }
1301  }
1302 
1303  int PBPOffset = 0;
1304  if (FI->usesPICBase()) {
1305  int PBPIndex = FI->getPICBasePointerSaveIndex();
1306  assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1307  PBPOffset = MFI.getObjectOffset(PBPIndex);
1308  }
1309 
1310  bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
1311 
1312  if (IsReturnBlock) {
1313  unsigned RetOpcode = MBBI->getOpcode();
1314  bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1315  RetOpcode == PPC::TCRETURNdi ||
1316  RetOpcode == PPC::TCRETURNai ||
1317  RetOpcode == PPC::TCRETURNri8 ||
1318  RetOpcode == PPC::TCRETURNdi8 ||
1319  RetOpcode == PPC::TCRETURNai8;
1320 
1321  if (UsesTCRet) {
1322  int MaxTCRetDelta = FI->getTailCallSPDelta();
1323  MachineOperand &StackAdjust = MBBI->getOperand(1);
1324  assert(StackAdjust.isImm() && "Expecting immediate value.");
1325  // Adjust stack pointer.
1326  int StackAdj = StackAdjust.getImm();
1327  int Delta = StackAdj - MaxTCRetDelta;
1328  assert((Delta >= 0) && "Delta must be positive");
1329  if (MaxTCRetDelta>0)
1330  FrameSize += (StackAdj +Delta);
1331  else
1332  FrameSize += StackAdj;
1333  }
1334  }
1335 
1336  // Frames of 32KB & larger require special handling because they cannot be
1337  // indexed into with a simple LD/LWZ immediate offset operand.
1338  bool isLargeFrame = !isInt<16>(FrameSize);
1339 
1340  // On targets without red zone, the SP needs to be restored last, so that
1341  // all live contents of the stack frame are upwards of the SP. This means
1342  // that we cannot restore SP just now, since there may be more registers
1343  // to restore from the stack frame (e.g. R31). If the frame size is not
1344  // a simple immediate value, we will need a spare register to hold the
1345  // restored SP. If the frame size is known and small, we can simply adjust
1346  // the offsets of the registers to be restored, and still use SP to restore
1347  // them. In such case, the final update of SP will be to add the frame
1348  // size to it.
1349  // To simplify the code, set RBReg to the base register used to restore
1350  // values from the stack, and set SPAdd to the value that needs to be added
1351  // to the SP at the end. The default values are as if red zone was present.
1352  unsigned RBReg = SPReg;
1353  unsigned SPAdd = 0;
1354 
1355  if (FrameSize) {
1356  // In the prologue, the loaded (or persistent) stack pointer value is
1357  // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
1358  // zone add this offset back now.
1359 
1360  // If this function contained a fastcc call and GuaranteedTailCallOpt is
1361  // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1362  // call which invalidates the stack pointer value in SP(0). So we use the
1363  // value of R31 in this case.
1364  if (FI->hasFastCall()) {
1365  assert(HasFP && "Expecting a valid frame pointer.");
1366  if (!HasRedZone)
1367  RBReg = FPReg;
1368  if (!isLargeFrame) {
1369  BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1370  .addReg(FPReg).addImm(FrameSize);
1371  } else {
1372  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1373  .addImm(FrameSize >> 16);
1374  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1375  .addReg(ScratchReg, RegState::Kill)
1376  .addImm(FrameSize & 0xFFFF);
1377  BuildMI(MBB, MBBI, dl, AddInst)
1378  .addReg(RBReg)
1379  .addReg(FPReg)
1380  .addReg(ScratchReg);
1381  }
1382  } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) {
1383  if (HasRedZone) {
1384  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1385  .addReg(SPReg)
1386  .addImm(FrameSize);
1387  } else {
1388  // Make sure that adding FrameSize will not overflow the max offset
1389  // size.
1390  assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1391  "Local offsets should be negative");
1392  SPAdd = FrameSize;
1393  FPOffset += FrameSize;
1394  BPOffset += FrameSize;
1395  PBPOffset += FrameSize;
1396  }
1397  } else {
1398  // We don't want to use ScratchReg as a base register, because it
1399  // could happen to be R0. Use FP instead, but make sure to preserve it.
1400  if (!HasRedZone) {
1401  // If FP is not saved, copy it to ScratchReg.
1402  if (!HasFP)
1403  BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1404  .addReg(FPReg)
1405  .addReg(FPReg);
1406  RBReg = FPReg;
1407  }
1408  BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
1409  .addImm(0)
1410  .addReg(SPReg);
1411  }
1412  }
1413  assert(RBReg != ScratchReg && "Should have avoided ScratchReg");
1414  // If there is no red zone, ScratchReg may be needed for holding a useful
1415  // value (although not the base register). Make sure it is not overwritten
1416  // too early.
1417 
1418  assert((isPPC64 || !MustSaveCR) &&
1419  "Epilogue CR restoring supported only in 64-bit mode");
1420 
1421  // If we need to restore both the LR and the CR and we only have one
1422  // available scratch register, we must do them one at a time.
1423  if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1424  // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
1425  // is live here.
1426  assert(HasRedZone && "Expecting red zone");
1427  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1428  .addImm(8)
1429  .addReg(SPReg);
1430  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1431  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1432  .addReg(TempReg, getKillRegState(i == e-1));
1433  }
1434 
1435  // Delay restoring of the LR if ScratchReg is needed. This is ok, since
1436  // LR is stored in the caller's stack frame. ScratchReg will be needed
1437  // if RBReg is anything other than SP. We shouldn't use ScratchReg as
1438  // a base register anyway, because it may happen to be R0.
1439  bool LoadedLR = false;
1440  if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) {
1441  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1442  .addImm(LROffset+SPAdd)
1443  .addReg(RBReg);
1444  LoadedLR = true;
1445  }
1446 
1447  if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
1448  // This will only occur for PPC64.
1449  assert(isPPC64 && "Expecting 64-bit mode");
1450  assert(RBReg == SPReg && "Should be using SP as a base register");
1451  BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1452  .addImm(8)
1453  .addReg(RBReg);
1454  }
1455 
1456  if (HasFP) {
1457  // If there is red zone, restore FP directly, since SP has already been
1458  // restored. Otherwise, restore the value of FP into ScratchReg.
1459  if (HasRedZone || RBReg == SPReg)
1460  BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1461  .addImm(FPOffset)
1462  .addReg(SPReg);
1463  else
1464  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1465  .addImm(FPOffset)
1466  .addReg(RBReg);
1467  }
1468 
1469  if (FI->usesPICBase())
1470  BuildMI(MBB, MBBI, dl, LoadInst)
1471  .addReg(PPC::R30)
1472  .addImm(PBPOffset)
1473  .addReg(RBReg);
1474 
1475  if (HasBP)
1476  BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1477  .addImm(BPOffset)
1478  .addReg(RBReg);
1479 
1480  // There is nothing more to be loaded from the stack, so now we can
1481  // restore SP: SP = RBReg + SPAdd.
1482  if (RBReg != SPReg || SPAdd != 0) {
1483  assert(!HasRedZone && "This should not happen with red zone");
1484  // If SPAdd is 0, generate a copy.
1485  if (SPAdd == 0)
1486  BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1487  .addReg(RBReg)
1488  .addReg(RBReg);
1489  else
1490  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1491  .addReg(RBReg)
1492  .addImm(SPAdd);
1493 
1494  assert(RBReg != ScratchReg && "Should be using FP or SP as base register");
1495  if (RBReg == FPReg)
1496  BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1497  .addReg(ScratchReg)
1498  .addReg(ScratchReg);
1499 
1500  // Now load the LR from the caller's stack frame.
1501  if (MustSaveLR && !LoadedLR)
1502  BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1503  .addImm(LROffset)
1504  .addReg(SPReg);
1505  }
1506 
1507  if (MustSaveCR &&
1508  !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
1509  for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1510  BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1511  .addReg(TempReg, getKillRegState(i == e-1));
1512 
1513  if (MustSaveLR)
1514  BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1515 
1516  // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1517  // call optimization
1518  if (IsReturnBlock) {
1519  unsigned RetOpcode = MBBI->getOpcode();
1521  (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1524  unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1525 
1526  if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1527  BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1528  .addReg(SPReg).addImm(CallerAllocatedAmt);
1529  } else {
1530  BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1531  .addImm(CallerAllocatedAmt >> 16);
1532  BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1533  .addReg(ScratchReg, RegState::Kill)
1534  .addImm(CallerAllocatedAmt & 0xFFFF);
1535  BuildMI(MBB, MBBI, dl, AddInst)
1536  .addReg(SPReg)
1537  .addReg(FPReg)
1538  .addReg(ScratchReg);
1539  }
1540  } else {
1541  createTailCallBranchInstr(MBB);
1542  }
1543  }
1544 }
1545 
1546 void PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const {
1548  DebugLoc dl;
1549 
1550  if (MBBI != MBB.end())
1551  dl = MBBI->getDebugLoc();
1552 
1553  const PPCInstrInfo &TII =
1554  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1555 
1556  // Create branch instruction for pseudo tail call return instruction
1557  unsigned RetOpcode = MBBI->getOpcode();
1558  if (RetOpcode == PPC::TCRETURNdi) {
1559  MBBI = MBB.getLastNonDebugInstr();
1560  MachineOperand &JumpTarget = MBBI->getOperand(0);
1561  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1562  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1563  } else if (RetOpcode == PPC::TCRETURNri) {
1564  MBBI = MBB.getLastNonDebugInstr();
1565  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1566  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1567  } else if (RetOpcode == PPC::TCRETURNai) {
1568  MBBI = MBB.getLastNonDebugInstr();
1569  MachineOperand &JumpTarget = MBBI->getOperand(0);
1570  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1571  } else if (RetOpcode == PPC::TCRETURNdi8) {
1572  MBBI = MBB.getLastNonDebugInstr();
1573  MachineOperand &JumpTarget = MBBI->getOperand(0);
1574  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1575  addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1576  } else if (RetOpcode == PPC::TCRETURNri8) {
1577  MBBI = MBB.getLastNonDebugInstr();
1578  assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1579  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1580  } else if (RetOpcode == PPC::TCRETURNai8) {
1581  MBBI = MBB.getLastNonDebugInstr();
1582  MachineOperand &JumpTarget = MBBI->getOperand(0);
1583  BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1584  }
1585 }
1586 
1588  BitVector &SavedRegs,
1589  RegScavenger *RS) const {
1590  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1591 
1592  const PPCRegisterInfo *RegInfo =
1593  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1594 
1595  // Save and clear the LR state.
1597  unsigned LR = RegInfo->getRARegister();
1598  FI->setMustSaveLR(MustSaveLR(MF, LR));
1599  SavedRegs.reset(LR);
1600 
1601  // Save R31 if necessary
1602  int FPSI = FI->getFramePointerSaveIndex();
1603  bool isPPC64 = Subtarget.isPPC64();
1604  bool isDarwinABI = Subtarget.isDarwinABI();
1605  MachineFrameInfo &MFI = MF.getFrameInfo();
1606 
1607  // If the frame pointer save index hasn't been defined yet.
1608  if (!FPSI && needsFP(MF)) {
1609  // Find out what the fix offset of the frame pointer save area.
1610  int FPOffset = getFramePointerSaveOffset();
1611  // Allocate the frame index for frame pointer save area.
1612  FPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1613  // Save the result.
1614  FI->setFramePointerSaveIndex(FPSI);
1615  }
1616 
1617  int BPSI = FI->getBasePointerSaveIndex();
1618  if (!BPSI && RegInfo->hasBasePointer(MF)) {
1619  int BPOffset = getBasePointerSaveOffset();
1620  // Allocate the frame index for the base pointer save area.
1621  BPSI = MFI.CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1622  // Save the result.
1623  FI->setBasePointerSaveIndex(BPSI);
1624  }
1625 
1626  // Reserve stack space for the PIC Base register (R30).
1627  // Only used in SVR4 32-bit.
1628  if (FI->usesPICBase()) {
1629  int PBPSI = MFI.CreateFixedObject(4, -8, true);
1630  FI->setPICBasePointerSaveIndex(PBPSI);
1631  }
1632 
1633  // Make sure we don't explicitly spill r31, because, for example, we have
1634  // some inline asm which explicity clobbers it, when we otherwise have a
1635  // frame pointer and are using r31's spill slot for the prologue/epilogue
1636  // code. Same goes for the base pointer and the PIC base register.
1637  if (needsFP(MF))
1638  SavedRegs.reset(isPPC64 ? PPC::X31 : PPC::R31);
1639  if (RegInfo->hasBasePointer(MF))
1640  SavedRegs.reset(RegInfo->getBaseRegister(MF));
1641  if (FI->usesPICBase())
1642  SavedRegs.reset(PPC::R30);
1643 
1644  // Reserve stack space to move the linkage area to in case of a tail call.
1645  int TCSPDelta = 0;
1647  (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1648  MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1649  }
1650 
1651  // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1652  // function uses CR 2, 3, or 4.
1653  if (!isPPC64 && !isDarwinABI &&
1654  (SavedRegs.test(PPC::CR2) ||
1655  SavedRegs.test(PPC::CR3) ||
1656  SavedRegs.test(PPC::CR4))) {
1657  int FrameIdx = MFI.CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1658  FI->setCRSpillFrameIndex(FrameIdx);
1659  }
1660 }
1661 
1663  RegScavenger *RS) const {
1664  // Early exit if not using the SVR4 ABI.
1665  if (!Subtarget.isSVR4ABI()) {
1666  addScavengingSpillSlot(MF, RS);
1667  return;
1668  }
1669 
1670  // Get callee saved register information.
1671  MachineFrameInfo &MFI = MF.getFrameInfo();
1672  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1673 
1674  // If the function is shrink-wrapped, and if the function has a tail call, the
1675  // tail call might not be in the new RestoreBlock, so real branch instruction
1676  // won't be generated by emitEpilogue(), because shrink-wrap has chosen new
1677  // RestoreBlock. So we handle this case here.
1678  if (MFI.getSavePoint() && MFI.hasTailCall()) {
1679  MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
1680  for (MachineBasicBlock &MBB : MF) {
1681  if (MBB.isReturnBlock() && (&MBB) != RestoreBlock)
1682  createTailCallBranchInstr(MBB);
1683  }
1684  }
1685 
1686  // Early exit if no callee saved registers are modified!
1687  if (CSI.empty() && !needsFP(MF)) {
1688  addScavengingSpillSlot(MF, RS);
1689  return;
1690  }
1691 
1692  unsigned MinGPR = PPC::R31;
1693  unsigned MinG8R = PPC::X31;
1694  unsigned MinFPR = PPC::F31;
1695  unsigned MinVR = PPC::V31;
1696 
1697  bool HasGPSaveArea = false;
1698  bool HasG8SaveArea = false;
1699  bool HasFPSaveArea = false;
1700  bool HasVRSAVESaveArea = false;
1701  bool HasVRSaveArea = false;
1702 
1707 
1708  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1709  unsigned Reg = CSI[i].getReg();
1710  if (PPC::GPRCRegClass.contains(Reg)) {
1711  HasGPSaveArea = true;
1712 
1713  GPRegs.push_back(CSI[i]);
1714 
1715  if (Reg < MinGPR) {
1716  MinGPR = Reg;
1717  }
1718  } else if (PPC::G8RCRegClass.contains(Reg)) {
1719  HasG8SaveArea = true;
1720 
1721  G8Regs.push_back(CSI[i]);
1722 
1723  if (Reg < MinG8R) {
1724  MinG8R = Reg;
1725  }
1726  } else if (PPC::F8RCRegClass.contains(Reg)) {
1727  HasFPSaveArea = true;
1728 
1729  FPRegs.push_back(CSI[i]);
1730 
1731  if (Reg < MinFPR) {
1732  MinFPR = Reg;
1733  }
1734  } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1735  PPC::CRRCRegClass.contains(Reg)) {
1736  ; // do nothing, as we already know whether CRs are spilled
1737  } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1738  HasVRSAVESaveArea = true;
1739  } else if (PPC::VRRCRegClass.contains(Reg)) {
1740  HasVRSaveArea = true;
1741 
1742  VRegs.push_back(CSI[i]);
1743 
1744  if (Reg < MinVR) {
1745  MinVR = Reg;
1746  }
1747  } else {
1748  llvm_unreachable("Unknown RegisterClass!");
1749  }
1750  }
1751 
1753  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1754 
1755  int64_t LowerBound = 0;
1756 
1757  // Take into account stack space reserved for tail calls.
1758  int TCSPDelta = 0;
1760  (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1761  LowerBound = TCSPDelta;
1762  }
1763 
1764  // The Floating-point register save area is right below the back chain word
1765  // of the previous stack frame.
1766  if (HasFPSaveArea) {
1767  for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1768  int FI = FPRegs[i].getFrameIdx();
1769 
1770  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1771  }
1772 
1773  LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1774  }
1775 
1776  // Check whether the frame pointer register is allocated. If so, make sure it
1777  // is spilled to the correct offset.
1778  if (needsFP(MF)) {
1779  HasGPSaveArea = true;
1780 
1781  int FI = PFI->getFramePointerSaveIndex();
1782  assert(FI && "No Frame Pointer Save Slot!");
1783 
1784  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1785  }
1786 
1787  if (PFI->usesPICBase()) {
1788  HasGPSaveArea = true;
1789 
1790  int FI = PFI->getPICBasePointerSaveIndex();
1791  assert(FI && "No PIC Base Pointer Save Slot!");
1792 
1793  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1794  }
1795 
1796  const PPCRegisterInfo *RegInfo =
1797  static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1798  if (RegInfo->hasBasePointer(MF)) {
1799  HasGPSaveArea = true;
1800 
1801  int FI = PFI->getBasePointerSaveIndex();
1802  assert(FI && "No Base Pointer Save Slot!");
1803 
1804  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1805  }
1806 
1807  // General register save area starts right below the Floating-point
1808  // register save area.
1809  if (HasGPSaveArea || HasG8SaveArea) {
1810  // Move general register save area spill slots down, taking into account
1811  // the size of the Floating-point register save area.
1812  for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1813  int FI = GPRegs[i].getFrameIdx();
1814 
1815  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1816  }
1817 
1818  // Move general register save area spill slots down, taking into account
1819  // the size of the Floating-point register save area.
1820  for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1821  int FI = G8Regs[i].getFrameIdx();
1822 
1823  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1824  }
1825 
1826  unsigned MinReg =
1827  std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1828  TRI->getEncodingValue(MinG8R));
1829 
1830  if (Subtarget.isPPC64()) {
1831  LowerBound -= (31 - MinReg + 1) * 8;
1832  } else {
1833  LowerBound -= (31 - MinReg + 1) * 4;
1834  }
1835  }
1836 
1837  // For 32-bit only, the CR save area is below the general register
1838  // save area. For 64-bit SVR4, the CR save area is addressed relative
1839  // to the stack pointer and hence does not need an adjustment here.
1840  // Only CR2 (the first nonvolatile spilled) has an associated frame
1841  // index so that we have a single uniform save area.
1842  if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1843  // Adjust the frame index of the CR spill slot.
1844  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1845  unsigned Reg = CSI[i].getReg();
1846 
1847  if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1848  // Leave Darwin logic as-is.
1849  || (!Subtarget.isSVR4ABI() &&
1850  (PPC::CRBITRCRegClass.contains(Reg) ||
1851  PPC::CRRCRegClass.contains(Reg)))) {
1852  int FI = CSI[i].getFrameIdx();
1853 
1854  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1855  }
1856  }
1857 
1858  LowerBound -= 4; // The CR save area is always 4 bytes long.
1859  }
1860 
1861  if (HasVRSAVESaveArea) {
1862  // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1863  // which have the VRSAVE register class?
1864  // Adjust the frame index of the VRSAVE spill slot.
1865  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1866  unsigned Reg = CSI[i].getReg();
1867 
1868  if (PPC::VRSAVERCRegClass.contains(Reg)) {
1869  int FI = CSI[i].getFrameIdx();
1870 
1871  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1872  }
1873  }
1874 
1875  LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1876  }
1877 
1878  if (HasVRSaveArea) {
1879  // Insert alignment padding, we need 16-byte alignment.
1880  LowerBound = (LowerBound - 15) & ~(15);
1881 
1882  for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1883  int FI = VRegs[i].getFrameIdx();
1884 
1885  MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1886  }
1887  }
1888 
1889  addScavengingSpillSlot(MF, RS);
1890 }
1891 
1892 void
1894  RegScavenger *RS) const {
1895  // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1896  // a large stack, which will require scavenging a register to materialize a
1897  // large offset.
1898 
1899  // We need to have a scavenger spill slot for spills if the frame size is
1900  // large. In case there is no free register for large-offset addressing,
1901  // this slot is used for the necessary emergency spill. Also, we need the
1902  // slot for dynamic stack allocations.
1903 
1904  // The scavenger might be invoked if the frame offset does not fit into
1905  // the 16-bit immediate. We don't know the complete frame size here
1906  // because we've not yet computed callee-saved register spills or the
1907  // needed alignment padding.
1908  unsigned StackSize = determineFrameLayout(MF, false, true);
1909  MachineFrameInfo &MFI = MF.getFrameInfo();
1910  if (MFI.hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1911  hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1912  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1913  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1914  const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1916  RC->getAlignment(),
1917  false));
1918 
1919  // Might we have over-aligned allocas?
1920  bool HasAlVars = MFI.hasVarSizedObjects() &&
1922 
1923  // These kinds of spills might need two registers.
1924  if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1926  RC->getAlignment(),
1927  false));
1928 
1929  }
1930 }
1931 
1932 bool
1935  const std::vector<CalleeSavedInfo> &CSI,
1936  const TargetRegisterInfo *TRI) const {
1937 
1938  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1939  // Return false otherwise to maintain pre-existing behavior.
1940  if (!Subtarget.isSVR4ABI())
1941  return false;
1942 
1943  MachineFunction *MF = MBB.getParent();
1944  const PPCInstrInfo &TII =
1945  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1946  DebugLoc DL;
1947  bool CRSpilled = false;
1948  MachineInstrBuilder CRMIB;
1949 
1950  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1951  unsigned Reg = CSI[i].getReg();
1952  // Only Darwin actually uses the VRSAVE register, but it can still appear
1953  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1954  // Darwin, ignore it.
1955  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1956  continue;
1957 
1958  // CR2 through CR4 are the nonvolatile CR fields.
1959  bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1960 
1961  // Add the callee-saved register as live-in; it's killed at the spill.
1962  MBB.addLiveIn(Reg);
1963 
1964  if (CRSpilled && IsCRField) {
1965  CRMIB.addReg(Reg, RegState::ImplicitKill);
1966  continue;
1967  }
1968 
1969  // Insert the spill to the stack frame.
1970  if (IsCRField) {
1971  PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1972  if (Subtarget.isPPC64()) {
1973  // The actual spill will happen at the start of the prologue.
1974  FuncInfo->addMustSaveCR(Reg);
1975  } else {
1976  CRSpilled = true;
1977  FuncInfo->setSpillsCR();
1978 
1979  // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1980  // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1981  CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1982  .addReg(Reg, RegState::ImplicitKill);
1983 
1984  MBB.insert(MI, CRMIB);
1985  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1986  .addReg(PPC::R12,
1987  getKillRegState(true)),
1988  CSI[i].getFrameIdx()));
1989  }
1990  } else {
1991  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1992  TII.storeRegToStackSlot(MBB, MI, Reg, true,
1993  CSI[i].getFrameIdx(), RC, TRI);
1994  }
1995  }
1996  return true;
1997 }
1998 
1999 static void
2000 restoreCRs(bool isPPC64, bool is31,
2001  bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
2003  const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
2004 
2005  MachineFunction *MF = MBB.getParent();
2006  const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
2007  DebugLoc DL;
2008  unsigned RestoreOp, MoveReg;
2009 
2010  if (isPPC64)
2011  // This is handled during epilogue generation.
2012  return;
2013  else {
2014  // 32-bit: FP-relative
2015  MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
2016  PPC::R12),
2017  CSI[CSIIndex].getFrameIdx()));
2018  RestoreOp = PPC::MTOCRF;
2019  MoveReg = PPC::R12;
2020  }
2021 
2022  if (CR2Spilled)
2023  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2024  .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
2025 
2026  if (CR3Spilled)
2027  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2028  .addReg(MoveReg, getKillRegState(!CR4Spilled)));
2029 
2030  if (CR4Spilled)
2031  MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2032  .addReg(MoveReg, getKillRegState(true)));
2033 }
2034 
2038  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2040  I->getOpcode() == PPC::ADJCALLSTACKUP) {
2041  // Add (actually subtract) back the amount the callee popped on return.
2042  if (int CalleeAmt = I->getOperand(1).getImm()) {
2043  bool is64Bit = Subtarget.isPPC64();
2044  CalleeAmt *= -1;
2045  unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
2046  unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
2047  unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
2048  unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
2049  unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
2050  unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
2051  const DebugLoc &dl = I->getDebugLoc();
2052 
2053  if (isInt<16>(CalleeAmt)) {
2054  BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
2055  .addReg(StackReg, RegState::Kill)
2056  .addImm(CalleeAmt);
2057  } else {
2059  BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
2060  .addImm(CalleeAmt >> 16);
2061  BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
2062  .addReg(TmpReg, RegState::Kill)
2063  .addImm(CalleeAmt & 0xFFFF);
2064  BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
2065  .addReg(StackReg, RegState::Kill)
2066  .addReg(TmpReg);
2067  }
2068  }
2069  }
2070  // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
2071  return MBB.erase(I);
2072 }
2073 
2074 bool
2077  const std::vector<CalleeSavedInfo> &CSI,
2078  const TargetRegisterInfo *TRI) const {
2079 
2080  // Currently, this function only handles SVR4 32- and 64-bit ABIs.
2081  // Return false otherwise to maintain pre-existing behavior.
2082  if (!Subtarget.isSVR4ABI())
2083  return false;
2084 
2085  MachineFunction *MF = MBB.getParent();
2086  const PPCInstrInfo &TII =
2087  *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
2088  bool CR2Spilled = false;
2089  bool CR3Spilled = false;
2090  bool CR4Spilled = false;
2091  unsigned CSIIndex = 0;
2092 
2093  // Initialize insertion-point logic; we will be restoring in reverse
2094  // order of spill.
2095  MachineBasicBlock::iterator I = MI, BeforeI = I;
2096  bool AtStart = I == MBB.begin();
2097 
2098  if (!AtStart)
2099  --BeforeI;
2100 
2101  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2102  unsigned Reg = CSI[i].getReg();
2103 
2104  // Only Darwin actually uses the VRSAVE register, but it can still appear
2105  // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
2106  // Darwin, ignore it.
2107  if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
2108  continue;
2109 
2110  if (Reg == PPC::CR2) {
2111  CR2Spilled = true;
2112  // The spill slot is associated only with CR2, which is the
2113  // first nonvolatile spilled. Save it here.
2114  CSIIndex = i;
2115  continue;
2116  } else if (Reg == PPC::CR3) {
2117  CR3Spilled = true;
2118  continue;
2119  } else if (Reg == PPC::CR4) {
2120  CR4Spilled = true;
2121  continue;
2122  } else {
2123  // When we first encounter a non-CR register after seeing at
2124  // least one CR register, restore all spilled CRs together.
2125  if ((CR2Spilled || CR3Spilled || CR4Spilled)
2126  && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
2127  bool is31 = needsFP(*MF);
2128  restoreCRs(Subtarget.isPPC64(), is31,
2129  CR2Spilled, CR3Spilled, CR4Spilled,
2130  MBB, I, CSI, CSIIndex);
2131  CR2Spilled = CR3Spilled = CR4Spilled = false;
2132  }
2133 
2134  // Default behavior for non-CR saves.
2135  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2136  TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
2137  RC, TRI);
2138  assert(I != MBB.begin() &&
2139  "loadRegFromStackSlot didn't insert any code!");
2140  }
2141 
2142  // Insert in reverse order.
2143  if (AtStart)
2144  I = MBB.begin();
2145  else {
2146  I = BeforeI;
2147  ++I;
2148  }
2149  }
2150 
2151  // If we haven't yet spilled the CRs, do so now.
2152  if (CR2Spilled || CR3Spilled || CR4Spilled) {
2153  bool is31 = needsFP(*MF);
2154  restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
2155  MBB, I, CSI, CSIIndex);
2156  }
2157 
2158  return true;
2159 }
2160 
2162  return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
2163  MF.getSubtarget<PPCSubtarget>().isPPC64());
2164 }
void replaceFPWithRealFP(MachineFunction &MF) const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:157
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const GlobalValue * getGlobal() const
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static const unsigned GPRegs[]
size_t i
livein_iterator livein_end() const
bool isDarwinABI() const
Definition: PPCSubtarget.h:297
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:189
void addMustSaveCR(unsigned Reg)
MachineBasicBlock * getRestorePoint() const
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:166
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:396
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
void setFramePointerSaveIndex(int Idx)
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:777
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static const MCPhysReg VRegs[32]
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
An instruction for reading from memory.
Definition: Instructions.h:164
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:383
return AArch64::GPR64RegClass contains(Reg)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getMinReservedArea() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasDebugInfo() const
Returns true if valid debug info is present.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
static bool hasNonRISpills(const MachineFunction &MF)
void forward()
Move the internal MBB iterator and update register states.
const MachineBasicBlock & front() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
MachineBasicBlock * MBB
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
An instruction for storing to memory.
Definition: Instructions.h:300
int64_t getImm() const
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
unsigned getKillRegState(bool B)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
bool isELFv2ABI() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:122
This file declares the machine register scavenger class.
static const unsigned G8Regs[]
unsigned const MachineRegisterInfo * MRI
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:399
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
unsigned getBaseRegister(const MachineFunction &MF) const
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:376
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
BitVector & reset()
Definition: BitVector.h:260
uint32_t Offset
bool isPositionIndependent() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
int64_t getOffset() const
Return the offset from the symbol in this operand.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isSVR4ABI() const
Definition: PPCSubtarget.h:298
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const PPCRegisterInfo * getRegisterInfo() const override
Definition: PPCSubtarget.h:186
Iterator for intrusive lists based on ilist_node.
bool hasTailCall() const
Returns true if the function contains a tail call.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:274
const MCContext & getContext() const
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:179
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool test(unsigned Idx) const
Definition: BitVector.h:323
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Information about stack frame layout on the target.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:415
static bool spillsVRSAVE(const MachineFunction &MF)
livein_iterator livein_begin() const
static bool hasSpills(const MachineFunction &MF)
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:513
static bool spillsCR(const MachineFunction &MF)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
def_iterator def_begin(unsigned RegNo) const
bool needsFP(const MachineFunction &MF) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:245
MachineBasicBlock * getSavePoint() const
void setPICBasePointerSaveIndex(int Idx)
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII)
PPCFrameLowering(const PPCSubtarget &STI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
void setMaxCallFrameSize(unsigned S)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
static void RemoveVRSaveCode(MachineInstr &MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineModuleInfo & getMMI() const
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
static const MCPhysReg VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
bool hasBasePointer(const MachineFunction &MF) const
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
This class contains meta information specific to a module.