15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
23 namespace R600InstrFlags {
30 class AMDGPUTargetMachine;
32 class MachineFunction;
34 class MachineInstrBuilder;
42 std::vector<std::pair<int, unsigned>>
44 unsigned &ConstCount)
const;
48 unsigned ValueReg,
unsigned Address,
50 unsigned AddrChan)
const;
54 unsigned ValueReg,
unsigned Address,
56 unsigned AddrChan)
const;
74 const DebugLoc &DL,
unsigned DestReg,
unsigned SrcReg,
75 bool KillSrc)
const override;
80 bool isCubeOp(
unsigned opcode)
const;
96 bool isExport(
unsigned Opcode)
const;
110 int getSelIdx(
unsigned Opcode,
unsigned SrcIdx)
const;
121 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
122 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
123 const std::vector<std::pair<int, unsigned> > &TransSrcs,
127 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
128 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
129 const std::vector<std::pair<int, unsigned> > &TransSrcs,
143 std::vector<BankSwizzle> &BS,
144 bool isLastAluTrans)
const;
157 bool isMov(
unsigned Opcode)
const;
168 bool AllowModify)
const override;
173 int *BytesAdded =
nullptr)
const override;
176 int *BytesRemvoed =
nullptr)
const override;
186 unsigned ExtraPredCycles,
190 unsigned NumTCycles,
unsigned ExtraTCycles,
192 unsigned NumFCycles,
unsigned ExtraFCycles,
196 std::vector<MachineOperand> &Pred)
const override;
208 unsigned *PredCost =
nullptr)
const override;
243 unsigned ValueReg,
unsigned Address,
244 unsigned OffsetReg)
const;
251 unsigned ValueReg,
unsigned Address,
252 unsigned OffsetReg)
const;
268 unsigned Src1Reg = 0)
const;
273 unsigned DstReg)
const;
282 unsigned DstReg,
unsigned SrcReg)
const;
308 unsigned Flag = 0)
const;
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
int getIndirectIndexEnd(const MachineFunction &MF) const
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
unsigned int getPredicationCost(const MachineInstr &) const override
bool isLDSInstr(unsigned Opcode) const
bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const
Determine if the specified Flag is set on this Operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool isPredicated(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
Interface definition for R600RegisterInfo.
bool isVectorOnly(unsigned Opcode) const
bool isCubeOp(unsigned opcode) const
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
R600InstrInfo(const R600Subtarget &)
int getLDSNoRetOp(uint16_t Opcode)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool hasInstrModifiers(unsigned Opcode) const
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
bool usesVertexCache(unsigned Opcode) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
bool usesTextureCache(unsigned Opcode) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bool isExport(unsigned Opcode) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
const TargetRegisterClass * getIndirectAddrRegClass() const
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
bool readsLDSSrcReg(const MachineInstr &MI) const
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
bool canBeConsideredALU(const MachineInstr &MI) const
bool mustBeLastInClause(unsigned Opcode) const
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF) const
Reserve the registers that may be accesed using indirect addressing.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
bool definesAddressRegister(MachineInstr &MI) const
const R600RegisterInfo & getRegisterInfo() const
bool isPredicable(MachineInstr &MI) const override
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool isRegisterLoad(const MachineInstr &MI) const
bool usesAddressRegister(MachineInstr &MI) const
unsigned getMaxAlusPerClause() const
bool isReductionOp(unsigned opcode) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
bool isMov(unsigned Opcode) const
int getIndirectIndexBegin(const MachineFunction &MF) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, BranchProbability Probability) const override
bool isRegisterStore(const MachineInstr &MI) const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+...
bool isLDSRetInstr(unsigned Opcode) const
bool isALUInstr(unsigned Opcode) const
bool isTransOnly(unsigned Opcode) const
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override