26 #define DEBUG_TYPE "regalloc"
28 STATISTIC(NumAssigned ,
"Number of registers assigned");
29 STATISTIC(NumUnassigned ,
"Number of registers unassigned");
33 "Live Register Matrix",
false,
false)
40 UserTag(0), RegMaskTag(0), RegMaskVirtReg(0) {}
42 void LiveRegMatrix::getAnalysisUsage(
AnalysisUsage &AU)
const {
51 LIS = &getAnalysis<LiveIntervals>();
52 VRM = &getAnalysis<VirtRegMap>();
55 if (NumRegUnits != Matrix.
size())
57 Matrix.
init(LIUAlloc, NumRegUnits);
64 void LiveRegMatrix::releaseMemory() {
65 for (
unsigned i = 0, e = Matrix.
size();
i != e; ++
i) {
73 template <
typename Callable>
79 unsigned Unit = (*Units).first;
82 if ((S.LaneMask & Mask).any()) {
91 if (
Func(*Units, VRegInterval))
100 <<
" to " <<
PrintReg(PhysReg, TRI) <<
':');
101 assert(!VRM->hasPhys(VirtReg.
reg) &&
"Duplicate VirtReg assignment");
102 VRM->assignVirt2Phys(VirtReg.
reg, PhysReg);
107 Matrix[
Unit].unify(VirtReg, Range);
116 unsigned PhysReg = VRM->getPhys(VirtReg.
reg);
118 <<
" from " <<
PrintReg(PhysReg, TRI) <<
':');
119 VRM->clearVirt(VirtReg.
reg);
124 Matrix[
Unit].extract(VirtReg, Range);
134 if (!Matrix[*
Unit].empty())
145 if (RegMaskVirtReg != VirtReg.
reg || RegMaskTag != UserTag) {
146 RegMaskVirtReg = VirtReg.
reg;
147 RegMaskTag = UserTag;
148 RegMaskUsable.
clear();
155 return !RegMaskUsable.
empty() && (!PhysReg || !RegMaskUsable.
test(PhysReg));
175 Q.
init(UserTag, &VirtReg, &Matrix[RegUnit]);
No interference, go ahead and assign.
bool isValid() const
Returns true if this iterator is not yet at the end.
STATISTIC(NumFunctions,"Total number of functions")
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg)
Check for interference before assigning VirtReg to PhysReg.
LiveInterval - This class represents the liveness of a register, or stack slot.
A live range for subregisters.
void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU)
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
This class represents the liveness of a register, stack slot, etc.
#define INITIALIZE_PASS_DEPENDENCY(depName)
void clear()
clear - Clear all bits.
Query interferences between a single live virtual register and a live interval union.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
A helper class for register coalescers.
iterator_range< subrange_iterator > subranges()
Register unit interference.
void assign(LiveInterval &VirtReg, unsigned PhysReg)
Assign VirtReg to PhysReg.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
SlotIndexes * getSlotIndexes() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool empty() const
empty - Tests whether there are no bits in this bitvector.
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
bool isPhysRegUsed(unsigned PhysReg) const
Returns true if the given PhysReg has any live intervals assigned.
void unassign(LiveInterval &VirtReg)
Unassign VirtReg from its PhysReg.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
bool test(unsigned Idx) const
bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg)
Check for regunit interference only.
void init(LiveIntervalUnion::Allocator &, unsigned Size)
Promote Memory to Register
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void setPreservesAll()
Set by analyses that do not transform their input at all.
static bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, unsigned PhysReg, Callable Func)
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
AnalysisUsage & addRequiredTransitive()
LiveIntervalUnion::Query & query(LiveInterval &VirtReg, unsigned RegUnit)
Query a line of the assigned virtual register matrix directly.
std::vector< uint8_t > Unit
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg=0)
Check for regmask interference only.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Virtual register interference.
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
INITIALIZE_PASS_BEGIN(LiveRegMatrix,"liveregmatrix","Live Register Matrix", false, false) INITIALIZE_PASS_END(LiveRegMatrix