LLVM  4.0.0
Macros | Typedefs | Enumerations | Functions | Variables
HexagonDisassembler.cpp File Reference
#include "Hexagon.h"
#include "MCTargetDesc/HexagonBaseInfo.h"
#include "MCTargetDesc/HexagonMCChecker.h"
#include "MCTargetDesc/HexagonMCTargetDesc.h"
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/TargetRegistry.h"
#include <cassert>
#include <cstddef>
#include <cstdint>
#include <memory>
#include "HexagonGenDisassemblerTables.inc"
Include dependency graph for HexagonDisassembler.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "hexagon-disassembler"
 

Typedefs

typedef
MCDisassembler::DecodeStatus 
DecodeStatus
 

Enumerations

enum  subInstBinaryValues {
  SA1_addi_BITS = 0x0000, SA1_addi_MASK = 0x1800, SA1_addrx_BITS = 0x1800, SA1_addrx_MASK = 0x1f00,
  SA1_addsp_BITS = 0x0c00, SA1_addsp_MASK = 0x1c00, SA1_and1_BITS = 0x1200, SA1_and1_MASK = 0x1f00,
  SA1_clrf_BITS = 0x1a70, SA1_clrf_MASK = 0x1e70, SA1_clrfnew_BITS = 0x1a50, SA1_clrfnew_MASK = 0x1e70,
  SA1_clrt_BITS = 0x1a60, SA1_clrt_MASK = 0x1e70, SA1_clrtnew_BITS = 0x1a40, SA1_clrtnew_MASK = 0x1e70,
  SA1_cmpeqi_BITS = 0x1900, SA1_cmpeqi_MASK = 0x1f00, SA1_combine0i_BITS = 0x1c00, SA1_combine0i_MASK = 0x1d18,
  SA1_combine1i_BITS = 0x1c08, SA1_combine1i_MASK = 0x1d18, SA1_combine2i_BITS = 0x1c10, SA1_combine2i_MASK = 0x1d18,
  SA1_combine3i_BITS = 0x1c18, SA1_combine3i_MASK = 0x1d18, SA1_combinerz_BITS = 0x1d08, SA1_combinerz_MASK = 0x1d08,
  SA1_combinezr_BITS = 0x1d00, SA1_combinezr_MASK = 0x1d08, SA1_dec_BITS = 0x1300, SA1_dec_MASK = 0x1f00,
  SA1_inc_BITS = 0x1100, SA1_inc_MASK = 0x1f00, SA1_seti_BITS = 0x0800, SA1_seti_MASK = 0x1c00,
  SA1_setin1_BITS = 0x1a00, SA1_setin1_MASK = 0x1e40, SA1_sxtb_BITS = 0x1500, SA1_sxtb_MASK = 0x1f00,
  SA1_sxth_BITS = 0x1400, SA1_sxth_MASK = 0x1f00, SA1_tfr_BITS = 0x1000, SA1_tfr_MASK = 0x1f00,
  SA1_zxtb_BITS = 0x1700, SA1_zxtb_MASK = 0x1f00, SA1_zxth_BITS = 0x1600, SA1_zxth_MASK = 0x1f00,
  SL1_loadri_io_BITS = 0x0000, SL1_loadri_io_MASK = 0x1000, SL1_loadrub_io_BITS = 0x1000, SL1_loadrub_io_MASK = 0x1000,
  SL2_deallocframe_BITS = 0x1f00, SL2_deallocframe_MASK = 0x1fc0, SL2_jumpr31_BITS = 0x1fc0, SL2_jumpr31_MASK = 0x1fc4,
  SL2_jumpr31_f_BITS = 0x1fc5, SL2_jumpr31_f_MASK = 0x1fc7, SL2_jumpr31_fnew_BITS = 0x1fc7, SL2_jumpr31_fnew_MASK = 0x1fc7,
  SL2_jumpr31_t_BITS = 0x1fc4, SL2_jumpr31_t_MASK = 0x1fc7, SL2_jumpr31_tnew_BITS = 0x1fc6, SL2_jumpr31_tnew_MASK = 0x1fc7,
  SL2_loadrb_io_BITS = 0x1000, SL2_loadrb_io_MASK = 0x1800, SL2_loadrd_sp_BITS = 0x1e00, SL2_loadrd_sp_MASK = 0x1f00,
  SL2_loadrh_io_BITS = 0x0000, SL2_loadrh_io_MASK = 0x1800, SL2_loadri_sp_BITS = 0x1c00, SL2_loadri_sp_MASK = 0x1e00,
  SL2_loadruh_io_BITS = 0x0800, SL2_loadruh_io_MASK = 0x1800, SL2_return_BITS = 0x1f40, SL2_return_MASK = 0x1fc4,
  SL2_return_f_BITS = 0x1f45, SL2_return_f_MASK = 0x1fc7, SL2_return_fnew_BITS = 0x1f47, SL2_return_fnew_MASK = 0x1fc7,
  SL2_return_t_BITS = 0x1f44, SL2_return_t_MASK = 0x1fc7, SL2_return_tnew_BITS = 0x1f46, SL2_return_tnew_MASK = 0x1fc7,
  SS1_storeb_io_BITS = 0x1000, SS1_storeb_io_MASK = 0x1000, SS1_storew_io_BITS = 0x0000, SS1_storew_io_MASK = 0x1000,
  SS2_allocframe_BITS = 0x1c00, SS2_allocframe_MASK = 0x1e00, SS2_storebi0_BITS = 0x1200, SS2_storebi0_MASK = 0x1f00,
  SS2_storebi1_BITS = 0x1300, SS2_storebi1_MASK = 0x1f00, SS2_stored_sp_BITS = 0x0a00, SS2_stored_sp_MASK = 0x1e00,
  SS2_storeh_io_BITS = 0x0000, SS2_storeh_io_MASK = 0x1800, SS2_storew_sp_BITS = 0x0800, SS2_storew_sp_MASK = 0x1e00,
  SS2_storewi0_BITS = 0x1000, SS2_storewi0_MASK = 0x1f00, SS2_storewi1_BITS = 0x1100, SS2_storewi1_MASK = 0x1f00
}
 

Functions

static DecodeStatus DecodeIntRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeIntRegsLow8RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeVectorRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeDoubleRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeVecDblRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodePredRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeVecPredRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeCtrRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeModRegsRegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus DecodeCtrRegs64RegisterClass (MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
 
static DecodeStatus decodeSpecial (MCInst &MI, uint32_t insn)
 
static DecodeStatus decodeImmext (MCInst &MI, uint32_t insn, void const *Decoder)
 
static unsigned GetSubinstOpcode (unsigned IClass, unsigned inst, unsigned &op, raw_ostream &os)
 
static unsigned getRegFromSubinstEncoding (unsigned encoded_reg)
 
static DecodeStatus unsignedImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s16_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s12_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_1ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_2ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s11_3ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s10_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s8_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s6_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_0ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_1ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_2ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_3ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s4_6ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus s3_6ImmDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static DecodeStatus brtargetDecoder (MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder)
 
static MCDisassemblercreateHexagonDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
 
void LLVMInitializeHexagonDisassembler ()
 
static HexagonDisassembler constdisassembler (void const *Decoder)
 
static MCContextcontextFromDecoder (void const *Decoder)
 
static DecodeStatus DecodeRegisterClass (MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
 
static uint32_t fullValue (MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, int64_t Value)
 
template<size_t T>
static void signedDecoder (MCInst &MI, unsigned tmp, const void *Decoder)
 
static unsigned getDRegFromSubinstEncoding (unsigned encoded_dreg)
 

Variables

static const unsigned int StoreConditionalOpcodeData [][2]
 
static unsigned int LoadStoreOpcodeData [][2]
 
static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData)
 
static const size_t NumLS = array_lengthof(LoadStoreOpcodeData)
 

Macro Definition Documentation

#define DEBUG_TYPE   "hexagon-disassembler"

Definition at line 10 of file HexagonDisassembler.cpp.

Typedef Documentation

Definition at line 38 of file HexagonDisassembler.cpp.

Enumeration Type Documentation

Enumerator
SA1_addi_BITS 
SA1_addi_MASK 
SA1_addrx_BITS 
SA1_addrx_MASK 
SA1_addsp_BITS 
SA1_addsp_MASK 
SA1_and1_BITS 
SA1_and1_MASK 
SA1_clrf_BITS 
SA1_clrf_MASK 
SA1_clrfnew_BITS 
SA1_clrfnew_MASK 
SA1_clrt_BITS 
SA1_clrt_MASK 
SA1_clrtnew_BITS 
SA1_clrtnew_MASK 
SA1_cmpeqi_BITS 
SA1_cmpeqi_MASK 
SA1_combine0i_BITS 
SA1_combine0i_MASK 
SA1_combine1i_BITS 
SA1_combine1i_MASK 
SA1_combine2i_BITS 
SA1_combine2i_MASK 
SA1_combine3i_BITS 
SA1_combine3i_MASK 
SA1_combinerz_BITS 
SA1_combinerz_MASK 
SA1_combinezr_BITS 
SA1_combinezr_MASK 
SA1_dec_BITS 
SA1_dec_MASK 
SA1_inc_BITS 
SA1_inc_MASK 
SA1_seti_BITS 
SA1_seti_MASK 
SA1_setin1_BITS 
SA1_setin1_MASK 
SA1_sxtb_BITS 
SA1_sxtb_MASK 
SA1_sxth_BITS 
SA1_sxth_MASK 
SA1_tfr_BITS 
SA1_tfr_MASK 
SA1_zxtb_BITS 
SA1_zxtb_MASK 
SA1_zxth_BITS 
SA1_zxth_MASK 
SL1_loadri_io_BITS 
SL1_loadri_io_MASK 
SL1_loadrub_io_BITS 
SL1_loadrub_io_MASK 
SL2_deallocframe_BITS 
SL2_deallocframe_MASK 
SL2_jumpr31_BITS 
SL2_jumpr31_MASK 
SL2_jumpr31_f_BITS 
SL2_jumpr31_f_MASK 
SL2_jumpr31_fnew_BITS 
SL2_jumpr31_fnew_MASK 
SL2_jumpr31_t_BITS 
SL2_jumpr31_t_MASK 
SL2_jumpr31_tnew_BITS 
SL2_jumpr31_tnew_MASK 
SL2_loadrb_io_BITS 
SL2_loadrb_io_MASK 
SL2_loadrd_sp_BITS 
SL2_loadrd_sp_MASK 
SL2_loadrh_io_BITS 
SL2_loadrh_io_MASK 
SL2_loadri_sp_BITS 
SL2_loadri_sp_MASK 
SL2_loadruh_io_BITS 
SL2_loadruh_io_MASK 
SL2_return_BITS 
SL2_return_MASK 
SL2_return_f_BITS 
SL2_return_f_MASK 
SL2_return_fnew_BITS 
SL2_return_fnew_MASK 
SL2_return_t_BITS 
SL2_return_t_MASK 
SL2_return_tnew_BITS 
SL2_return_tnew_MASK 
SS1_storeb_io_BITS 
SS1_storeb_io_MASK 
SS1_storew_io_BITS 
SS1_storew_io_MASK 
SS2_allocframe_BITS 
SS2_allocframe_MASK 
SS2_storebi0_BITS 
SS2_storebi0_MASK 
SS2_storebi1_BITS 
SS2_storebi1_MASK 
SS2_stored_sp_BITS 
SS2_stored_sp_MASK 
SS2_storeh_io_BITS 
SS2_storeh_io_MASK 
SS2_storew_sp_BITS 
SS2_storew_sp_MASK 
SS2_storewi0_BITS 
SS2_storewi0_MASK 
SS2_storewi1_BITS 
SS2_storewi1_MASK 

Definition at line 1104 of file HexagonDisassembler.cpp.

Function Documentation

static DecodeStatus brtargetDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static MCContext& contextFromDecoder ( void const Decoder)
static

Definition at line 190 of file HexagonDisassembler.cpp.

References disassembler().

Referenced by decodeImmext(), and s11_1ImmDecoder().

static MCDisassembler* createHexagonDisassembler ( const Target T,
const MCSubtargetInfo STI,
MCContext Ctx 
)
static
static DecodeStatus DecodeCtrRegs64RegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus DecodeCtrRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 548 of file HexagonDisassembler.cpp.

References DecodeRegisterClass().

Referenced by decodeSpecial().

static DecodeStatus decodeImmext ( MCInst MI,
uint32_t  insn,
void const Decoder 
)
static
static DecodeStatus DecodeIntRegsLow8RegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 512 of file HexagonDisassembler.cpp.

References DecodeIntRegsRegisterClass().

static DecodeStatus DecodeIntRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus DecodeModRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus DecodePredRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 572 of file HexagonDisassembler.cpp.

References DecodeRegisterClass().

Referenced by decodeSpecial().

static DecodeStatus DecodeRegisterClass ( MCInst Inst,
unsigned  RegNo,
ArrayRef< MCPhysReg Table 
)
static
static DecodeStatus decodeSpecial ( MCInst MI,
uint32_t  insn 
)
static
static DecodeStatus DecodeVecDblRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 560 of file HexagonDisassembler.cpp.

References DecodeRegisterClass().

static DecodeStatus DecodeVecPredRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 581 of file HexagonDisassembler.cpp.

References DecodeRegisterClass().

static DecodeStatus DecodeVectorRegsRegisterClass ( MCInst Inst,
unsigned  RegNo,
uint64_t  Address,
const void *  Decoder 
)
static
static HexagonDisassembler const& disassembler ( void const Decoder)
static
static uint32_t fullValue ( MCInstrInfo const MCII,
MCInst MCB,
MCInst MI,
int64_t  Value 
)
static
static unsigned getDRegFromSubinstEncoding ( unsigned  encoded_dreg)
static

Definition at line 1365 of file HexagonDisassembler.cpp.

static unsigned getRegFromSubinstEncoding ( unsigned  encoded_reg)
static

Definition at line 1355 of file HexagonDisassembler.cpp.

static unsigned GetSubinstOpcode ( unsigned  IClass,
unsigned  inst,
unsigned op,
raw_ostream os 
)
static

Definition at line 1211 of file HexagonDisassembler.cpp.

References llvm::MCDisassembler::Fail, llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, SA1_addi_BITS, SA1_addi_MASK, SA1_addrx_BITS, SA1_addrx_MASK, SA1_addsp_BITS, SA1_addsp_MASK, SA1_and1_BITS, SA1_and1_MASK, SA1_clrf_BITS, SA1_clrf_MASK, SA1_clrfnew_BITS, SA1_clrfnew_MASK, SA1_clrt_BITS, SA1_clrt_MASK, SA1_clrtnew_BITS, SA1_clrtnew_MASK, SA1_cmpeqi_BITS, SA1_cmpeqi_MASK, SA1_combine0i_BITS, SA1_combine0i_MASK, SA1_combine1i_BITS, SA1_combine1i_MASK, SA1_combine2i_BITS, SA1_combine2i_MASK, SA1_combine3i_BITS, SA1_combine3i_MASK, SA1_combinerz_BITS, SA1_combinerz_MASK, SA1_combinezr_BITS, SA1_combinezr_MASK, SA1_dec_BITS, SA1_dec_MASK, SA1_inc_BITS, SA1_inc_MASK, SA1_seti_BITS, SA1_seti_MASK, SA1_setin1_BITS, SA1_setin1_MASK, SA1_sxtb_BITS, SA1_sxtb_MASK, SA1_sxth_BITS, SA1_sxth_MASK, SA1_tfr_BITS, SA1_tfr_MASK, SA1_zxtb_BITS, SA1_zxtb_MASK, SA1_zxth_BITS, SA1_zxth_MASK, SL1_loadri_io_BITS, SL1_loadri_io_MASK, SL1_loadrub_io_BITS, SL1_loadrub_io_MASK, SL2_deallocframe_BITS, SL2_deallocframe_MASK, SL2_jumpr31_BITS, SL2_jumpr31_f_BITS, SL2_jumpr31_f_MASK, SL2_jumpr31_fnew_BITS, SL2_jumpr31_fnew_MASK, SL2_jumpr31_MASK, SL2_jumpr31_t_BITS, SL2_jumpr31_t_MASK, SL2_jumpr31_tnew_BITS, SL2_jumpr31_tnew_MASK, SL2_loadrb_io_BITS, SL2_loadrb_io_MASK, SL2_loadrd_sp_BITS, SL2_loadrd_sp_MASK, SL2_loadrh_io_BITS, SL2_loadrh_io_MASK, SL2_loadri_sp_BITS, SL2_loadri_sp_MASK, SL2_loadruh_io_BITS, SL2_loadruh_io_MASK, SL2_return_BITS, SL2_return_f_BITS, SL2_return_f_MASK, SL2_return_fnew_BITS, SL2_return_fnew_MASK, SL2_return_MASK, SL2_return_t_BITS, SL2_return_t_MASK, SL2_return_tnew_BITS, SL2_return_tnew_MASK, SS1_storeb_io_BITS, SS1_storeb_io_MASK, SS1_storew_io_BITS, SS1_storew_io_MASK, SS2_allocframe_BITS, SS2_allocframe_MASK, SS2_storebi0_BITS, SS2_storebi0_MASK, SS2_storebi1_BITS, SS2_storebi1_MASK, SS2_stored_sp_BITS, SS2_stored_sp_MASK, SS2_storeh_io_BITS, SS2_storeh_io_MASK, SS2_storew_sp_BITS, SS2_storew_sp_MASK, SS2_storewi0_BITS, SS2_storewi0_MASK, SS2_storewi1_BITS, SS2_storewi1_MASK, and llvm::MCDisassembler::Success.

void LLVMInitializeHexagonDisassembler ( )
static DecodeStatus s10_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 728 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s11_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 704 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s11_1ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static
static DecodeStatus s11_2ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 716 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s11_3ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 722 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s12_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 698 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s16_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 692 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s3_6ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 776 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s4_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 746 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s4_1ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 752 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s4_2ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 758 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s4_3ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 764 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s4_6ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 770 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s6_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 740 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

static DecodeStatus s8_0ImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Definition at line 734 of file HexagonDisassembler.cpp.

References MI, and llvm::MCDisassembler::Success.

template<size_t T>
static void signedDecoder ( MCInst MI,
unsigned  tmp,
const void *  Decoder 
)
static
static DecodeStatus unsignedImmDecoder ( MCInst MI,
unsigned  tmp,
uint64_t  Address,
const void *  Decoder 
)
static

Variable Documentation

unsigned int LoadStoreOpcodeData[][2]
static
Initial value:
= {{PS_loadrdabs, 0x49c00000},
{PS_loadriabs, 0x49800000},
{PS_loadruhabs, 0x49600000},
{PS_loadrhabs, 0x49400000},
{PS_loadrubabs, 0x49200000},
{PS_loadrbabs, 0x49000000},
{PS_storerdabs, 0x48c00000},
{PS_storerinewabs, 0x48a01000},
{PS_storerhnewabs, 0x48a00800},
{PS_storerbnewabs, 0x48a00000},
{PS_storeriabs, 0x48800000},
{PS_storerfabs, 0x48600000},
{PS_storerhabs, 0x48400000},
{PS_storerbabs, 0x48000000}}

Definition at line 840 of file HexagonDisassembler.cpp.

Referenced by decodeSpecial().

const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData)
static

Definition at line 854 of file HexagonDisassembler.cpp.

Referenced by decodeSpecial().

const size_t NumLS = array_lengthof(LoadStoreOpcodeData)
static

Definition at line 855 of file HexagonDisassembler.cpp.

Referenced by decodeSpecial().

const unsigned int StoreConditionalOpcodeData[][2]
static
Initial value:
= {
{S4_pstorerdfnew_abs, 0xafc02084},
{S4_pstorerdtnew_abs, 0xafc02080},
{S4_pstorerdf_abs, 0xafc00084},
{S4_pstorerdt_abs, 0xafc00080},
{S4_pstorerinewfnew_abs, 0xafa03084},
{S4_pstorerinewtnew_abs, 0xafa03080},
{S4_pstorerhnewfnew_abs, 0xafa02884},
{S4_pstorerhnewtnew_abs, 0xafa02880},
{S4_pstorerbnewfnew_abs, 0xafa02084},
{S4_pstorerbnewtnew_abs, 0xafa02080},
{S4_pstorerinewf_abs, 0xafa01084},
{S4_pstorerinewt_abs, 0xafa01080},
{S4_pstorerhnewf_abs, 0xafa00884},
{S4_pstorerhnewt_abs, 0xafa00880},
{S4_pstorerbnewf_abs, 0xafa00084},
{S4_pstorerbnewt_abs, 0xafa00080},
{S4_pstorerifnew_abs, 0xaf802084},
{S4_pstoreritnew_abs, 0xaf802080},
{S4_pstorerif_abs, 0xaf800084},
{S4_pstorerit_abs, 0xaf800080},
{S4_pstorerhfnew_abs, 0xaf402084},
{S4_pstorerhtnew_abs, 0xaf402080},
{S4_pstorerhf_abs, 0xaf400084},
{S4_pstorerht_abs, 0xaf400080},
{S4_pstorerbfnew_abs, 0xaf002084},
{S4_pstorerbtnew_abs, 0xaf002080},
{S4_pstorerbf_abs, 0xaf000084},
{S4_pstorerbt_abs, 0xaf000080}}

Definition at line 808 of file HexagonDisassembler.cpp.

Referenced by decodeSpecial().