LLVM  4.0.0
LanaiISelLowering.cpp
Go to the documentation of this file.
1 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LanaiTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Lanai.h"
15 #include "LanaiCondCode.h"
16 #include "LanaiISelLowering.h"
18 #include "LanaiSubtarget.h"
19 #include "LanaiTargetObjectFile.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/StringSwitch.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/Support/Casting.h"
42 #include "llvm/Support/CodeGen.h"
43 #include "llvm/Support/Debug.h"
49 #include <cassert>
50 #include <cmath>
51 #include <cstdint>
52 #include <cstdlib>
53 #include <utility>
54 
55 #define DEBUG_TYPE "lanai-lower"
56 
57 using namespace llvm;
58 
59 // Limit on number of instructions the lowered multiplication may have before a
60 // call to the library function should be generated instead. The threshold is
61 // currently set to 14 as this was the smallest threshold that resulted in all
62 // constant multiplications being lowered. A threshold of 5 covered all cases
63 // except for one multiplication which required 14. mulsi3 requires 16
64 // instructions (including the prologue and epilogue but excluding instructions
65 // at call site). Until we can inline mulsi3, generating at most 14 instructions
66 // will be faster than invoking mulsi3.
68  "lanai-constant-mul-threshold", cl::Hidden,
69  cl::desc("Maximum number of instruction to generate when lowering constant "
70  "multiplication instead of calling library function [default=14]"),
71  cl::init(14));
72 
74  const LanaiSubtarget &STI)
75  : TargetLowering(TM) {
76  // Set up the register classes.
77  addRegisterClass(MVT::i32, &Lanai::GPRRegClass);
78 
79  // Compute derived properties from the register classes
80  TRI = STI.getRegisterInfo();
82 
84 
92 
97 
101 
106 
113 
119 
125 
130 
134 
135  // Extended load operations for i1 types must be promoted
136  for (MVT VT : MVT::integer_valuetypes()) {
140  }
141 
147 
148  // Function alignments (log2)
151 
152  setJumpIsExpensive(true);
153 
154  // TODO: Setting the minimum jump table entries needed before a
155  // switch is transformed to a jump table to 100 to avoid creating jump tables
156  // as this was causing bad performance compared to a large group of if
157  // statements. Re-evaluate this on new benchmarks.
159 
160  // Use fast calling convention for library functions.
161  for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
162  setLibcallCallingConv(static_cast<RTLIB::Libcall>(I), CallingConv::Fast);
163  }
164 
165  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
167  MaxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
169  MaxStoresPerMemmove = 16; // For @llvm.memmove -> sequence of stores
171 
172  // Booleans always contain 0 or 1.
174 }
175 
177  SelectionDAG &DAG) const {
178  switch (Op.getOpcode()) {
179  case ISD::MUL:
180  return LowerMUL(Op, DAG);
181  case ISD::BR_CC:
182  return LowerBR_CC(Op, DAG);
183  case ISD::ConstantPool:
184  return LowerConstantPool(Op, DAG);
185  case ISD::GlobalAddress:
186  return LowerGlobalAddress(Op, DAG);
187  case ISD::BlockAddress:
188  return LowerBlockAddress(Op, DAG);
189  case ISD::JumpTable:
190  return LowerJumpTable(Op, DAG);
191  case ISD::SELECT_CC:
192  return LowerSELECT_CC(Op, DAG);
193  case ISD::SETCC:
194  return LowerSETCC(Op, DAG);
195  case ISD::SETCCE:
196  return LowerSETCCE(Op, DAG);
197  case ISD::SHL_PARTS:
198  return LowerSHL_PARTS(Op, DAG);
199  case ISD::SRL_PARTS:
200  return LowerSRL_PARTS(Op, DAG);
201  case ISD::VASTART:
202  return LowerVASTART(Op, DAG);
204  return LowerDYNAMIC_STACKALLOC(Op, DAG);
205  case ISD::RETURNADDR:
206  return LowerRETURNADDR(Op, DAG);
207  case ISD::FRAMEADDR:
208  return LowerFRAMEADDR(Op, DAG);
209  default:
210  llvm_unreachable("unimplemented operand");
211  }
212 }
213 
214 //===----------------------------------------------------------------------===//
215 // Lanai Inline Assembly Support
216 //===----------------------------------------------------------------------===//
217 
218 unsigned LanaiTargetLowering::getRegisterByName(const char *RegName, EVT /*VT*/,
219  SelectionDAG & /*DAG*/) const {
220  // Only unallocatable registers should be matched here.
221  unsigned Reg = StringSwitch<unsigned>(RegName)
222  .Case("pc", Lanai::PC)
223  .Case("sp", Lanai::SP)
224  .Case("fp", Lanai::FP)
225  .Case("rr1", Lanai::RR1)
226  .Case("r10", Lanai::R10)
227  .Case("rr2", Lanai::RR2)
228  .Case("r11", Lanai::R11)
229  .Case("rca", Lanai::RCA)
230  .Default(0);
231 
232  if (Reg)
233  return Reg;
234  report_fatal_error("Invalid register name global variable");
235 }
236 
237 std::pair<unsigned, const TargetRegisterClass *>
239  StringRef Constraint,
240  MVT VT) const {
241  if (Constraint.size() == 1)
242  // GCC Constraint Letters
243  switch (Constraint[0]) {
244  case 'r': // GENERAL_REGS
245  return std::make_pair(0U, &Lanai::GPRRegClass);
246  default:
247  break;
248  }
249 
250  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
251 }
252 
253 // Examine constraint type and operand type and determine a weight value.
254 // This object must already have been set up with the operand type
255 // and the current alternative constraint selected.
258  AsmOperandInfo &Info, const char *Constraint) const {
259  ConstraintWeight Weight = CW_Invalid;
260  Value *CallOperandVal = Info.CallOperandVal;
261  // If we don't have a value, we can't do a match,
262  // but allow it at the lowest weight.
263  if (CallOperandVal == nullptr)
264  return CW_Default;
265  // Look at the constraint type.
266  switch (*Constraint) {
267  case 'I': // signed 16 bit immediate
268  case 'J': // integer zero
269  case 'K': // unsigned 16 bit immediate
270  case 'L': // immediate in the range 0 to 31
271  case 'M': // signed 32 bit immediate where lower 16 bits are 0
272  case 'N': // signed 26 bit immediate
273  case 'O': // integer zero
274  if (isa<ConstantInt>(CallOperandVal))
275  Weight = CW_Constant;
276  break;
277  default:
278  Weight = TargetLowering::getSingleConstraintMatchWeight(Info, Constraint);
279  break;
280  }
281  return Weight;
282 }
283 
284 // LowerAsmOperandForConstraint - Lower the specified operand into the Ops
285 // vector. If it is invalid, don't add anything to Ops.
287  SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
288  SelectionDAG &DAG) const {
289  SDValue Result(nullptr, 0);
290 
291  // Only support length 1 constraints for now.
292  if (Constraint.length() > 1)
293  return;
294 
295  char ConstraintLetter = Constraint[0];
296  switch (ConstraintLetter) {
297  case 'I': // Signed 16 bit constant
298  // If this fails, the parent routine will give an error
299  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
300  if (isInt<16>(C->getSExtValue())) {
301  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
302  Op.getValueType());
303  break;
304  }
305  }
306  return;
307  case 'J': // integer zero
308  case 'O':
309  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
310  if (C->getZExtValue() == 0) {
311  Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
312  break;
313  }
314  }
315  return;
316  case 'K': // unsigned 16 bit immediate
317  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
318  if (isUInt<16>(C->getZExtValue())) {
319  Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
320  Op.getValueType());
321  break;
322  }
323  }
324  return;
325  case 'L': // immediate in the range 0 to 31
326  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
327  if (C->getZExtValue() <= 31) {
328  Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
329  Op.getValueType());
330  break;
331  }
332  }
333  return;
334  case 'M': // signed 32 bit immediate where lower 16 bits are 0
335  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
336  int64_t Val = C->getSExtValue();
337  if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
338  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
339  break;
340  }
341  }
342  return;
343  case 'N': // signed 26 bit immediate
344  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
345  int64_t Val = C->getSExtValue();
346  if ((Val >= -33554432) && (Val <= 33554431)) {
347  Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
348  break;
349  }
350  }
351  return;
352  default:
353  break; // This will fall through to the generic implementation
354  }
355 
356  if (Result.getNode()) {
357  Ops.push_back(Result);
358  return;
359  }
360 
361  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
362 }
363 
364 //===----------------------------------------------------------------------===//
365 // Calling Convention Implementation
366 //===----------------------------------------------------------------------===//
367 
368 #include "LanaiGenCallingConv.inc"
369 
370 static unsigned NumFixedArgs;
371 static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
372  CCValAssign::LocInfo LocInfo,
373  ISD::ArgFlagsTy ArgFlags, CCState &State) {
374  // Handle fixed arguments with default CC.
375  // Note: Both the default and fast CC handle VarArg the same and hence the
376  // calling convention of the function is not considered here.
377  if (ValNo < NumFixedArgs) {
378  return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
379  }
380 
381  // Promote i8/i16 args to i32
382  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
383  LocVT = MVT::i32;
384  if (ArgFlags.isSExt())
385  LocInfo = CCValAssign::SExt;
386  else if (ArgFlags.isZExt())
387  LocInfo = CCValAssign::ZExt;
388  else
389  LocInfo = CCValAssign::AExt;
390  }
391 
392  // VarArgs get passed on stack
393  unsigned Offset = State.AllocateStack(4, 4);
394  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
395  return false;
396 }
397 
398 SDValue LanaiTargetLowering::LowerFormalArguments(
399  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
400  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
401  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
402  switch (CallConv) {
403  case CallingConv::C:
404  case CallingConv::Fast:
405  return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);
406  default:
407  llvm_unreachable("Unsupported calling convention");
408  }
409 }
410 
411 SDValue LanaiTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
412  SmallVectorImpl<SDValue> &InVals) const {
413  SelectionDAG &DAG = CLI.DAG;
414  SDLoc &DL = CLI.DL;
416  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
418  SDValue Chain = CLI.Chain;
419  SDValue Callee = CLI.Callee;
420  bool &IsTailCall = CLI.IsTailCall;
421  CallingConv::ID CallConv = CLI.CallConv;
422  bool IsVarArg = CLI.IsVarArg;
423 
424  // Lanai target does not yet support tail call optimization.
425  IsTailCall = false;
426 
427  switch (CallConv) {
428  case CallingConv::Fast:
429  case CallingConv::C:
430  return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,
431  OutVals, Ins, DL, DAG, InVals);
432  default:
433  llvm_unreachable("Unsupported calling convention");
434  }
435 }
436 
437 // LowerCCCArguments - transform physical registers into virtual registers and
438 // generate load operations for arguments places on the stack.
439 SDValue LanaiTargetLowering::LowerCCCArguments(
440  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
441  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
442  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
444  MachineFrameInfo &MFI = MF.getFrameInfo();
445  MachineRegisterInfo &RegInfo = MF.getRegInfo();
447 
448  // Assign locations to all of the incoming arguments.
450  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
451  *DAG.getContext());
452  if (CallConv == CallingConv::Fast) {
453  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);
454  } else {
455  CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);
456  }
457 
458  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
459  CCValAssign &VA = ArgLocs[i];
460  if (VA.isRegLoc()) {
461  // Arguments passed in registers
462  EVT RegVT = VA.getLocVT();
463  switch (RegVT.getSimpleVT().SimpleTy) {
464  case MVT::i32: {
465  unsigned VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
466  RegInfo.addLiveIn(VA.getLocReg(), VReg);
467  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
468 
469  // If this is an 8/16-bit value, it is really passed promoted to 32
470  // bits. Insert an assert[sz]ext to capture this, then truncate to the
471  // right size.
472  if (VA.getLocInfo() == CCValAssign::SExt)
473  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
474  DAG.getValueType(VA.getValVT()));
475  else if (VA.getLocInfo() == CCValAssign::ZExt)
476  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
477  DAG.getValueType(VA.getValVT()));
478 
479  if (VA.getLocInfo() != CCValAssign::Full)
480  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
481 
482  InVals.push_back(ArgValue);
483  break;
484  }
485  default:
486  DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "
487  << RegVT.getEVTString() << "\n");
488  llvm_unreachable("unhandled argument type");
489  }
490  } else {
491  // Sanity check
492  assert(VA.isMemLoc());
493  // Load the argument to a virtual register
494  unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
495  // Check that the argument fits in stack slot
496  if (ObjSize > 4) {
497  errs() << "LowerFormalArguments Unhandled argument type: "
498  << EVT(VA.getLocVT()).getEVTString() << "\n";
499  }
500  // Create the frame index object for this incoming parameter...
501  int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
502 
503  // Create the SelectionDAG nodes corresponding to a load
504  // from this parameter
505  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
506  InVals.push_back(DAG.getLoad(
507  VA.getLocVT(), DL, Chain, FIN,
509  }
510  }
511 
512  // The Lanai ABI for returning structs by value requires that we copy
513  // the sret argument into rv for the return. Save the argument into
514  // a virtual register so that we can access it from the return points.
515  if (MF.getFunction()->hasStructRetAttr()) {
516  unsigned Reg = LanaiMFI->getSRetReturnReg();
517  if (!Reg) {
519  LanaiMFI->setSRetReturnReg(Reg);
520  }
521  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
522  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
523  }
524 
525  if (IsVarArg) {
526  // Record the frame index of the first variable argument
527  // which is a value necessary to VASTART.
528  int FI = MFI.CreateFixedObject(4, CCInfo.getNextStackOffset(), true);
529  LanaiMFI->setVarArgsFrameIndex(FI);
530  }
531 
532  return Chain;
533 }
534 
535 SDValue
536 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
537  bool IsVarArg,
539  const SmallVectorImpl<SDValue> &OutVals,
540  const SDLoc &DL, SelectionDAG &DAG) const {
541  // CCValAssign - represent the assignment of the return value to a location
543 
544  // CCState - Info about the registers and stack slot.
545  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
546  *DAG.getContext());
547 
548  // Analize return values.
549  CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);
550 
551  SDValue Flag;
552  SmallVector<SDValue, 4> RetOps(1, Chain);
553 
554  // Copy the result values into the output registers.
555  for (unsigned i = 0; i != RVLocs.size(); ++i) {
556  CCValAssign &VA = RVLocs[i];
557  assert(VA.isRegLoc() && "Can only return in registers!");
558 
559  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
560 
561  // Guarantee that all emitted copies are stuck together with flags.
562  Flag = Chain.getValue(1);
563  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
564  }
565 
566  // The Lanai ABI for returning structs by value requires that we copy
567  // the sret argument into rv for the return. We saved the argument into
568  // a virtual register in the entry block, so now we copy the value out
569  // and into rv.
573  unsigned Reg = LanaiMFI->getSRetReturnReg();
574  assert(Reg &&
575  "SRetReturnReg should have been set in LowerFormalArguments().");
576  SDValue Val =
577  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
578 
579  Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Flag);
580  Flag = Chain.getValue(1);
581  RetOps.push_back(
582  DAG.getRegister(Lanai::RV, getPointerTy(DAG.getDataLayout())));
583  }
584 
585  RetOps[0] = Chain; // Update chain
586 
587  unsigned Opc = LanaiISD::RET_FLAG;
588  if (Flag.getNode())
589  RetOps.push_back(Flag);
590 
591  // Return Void
592  return DAG.getNode(Opc, DL, MVT::Other,
593  ArrayRef<SDValue>(&RetOps[0], RetOps.size()));
594 }
595 
596 // LowerCCCCallTo - functions arguments are copied from virtual regs to
597 // (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
598 SDValue LanaiTargetLowering::LowerCCCCallTo(
599  SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool IsVarArg,
600  bool /*IsTailCall*/, const SmallVectorImpl<ISD::OutputArg> &Outs,
601  const SmallVectorImpl<SDValue> &OutVals,
602  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
603  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
604  // Analyze operands of the call, assigning locations to each operand.
606  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
607  *DAG.getContext());
610 
611  NumFixedArgs = 0;
612  if (IsVarArg && G) {
613  const Function *CalleeFn = dyn_cast<Function>(G->getGlobal());
614  if (CalleeFn)
615  NumFixedArgs = CalleeFn->getFunctionType()->getNumParams();
616  }
617  if (NumFixedArgs)
618  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_VarArg);
619  else {
620  if (CallConv == CallingConv::Fast)
621  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);
622  else
623  CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);
624  }
625 
626  // Get a count of how many bytes are to be pushed on the stack.
627  unsigned NumBytes = CCInfo.getNextStackOffset();
628 
629  // Create local copies for byval args.
630  SmallVector<SDValue, 8> ByValArgs;
631  for (unsigned I = 0, E = Outs.size(); I != E; ++I) {
632  ISD::ArgFlagsTy Flags = Outs[I].Flags;
633  if (!Flags.isByVal())
634  continue;
635 
636  SDValue Arg = OutVals[I];
637  unsigned Size = Flags.getByValSize();
638  unsigned Align = Flags.getByValAlign();
639 
640  int FI = MFI.CreateStackObject(Size, Align, false);
641  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
642  SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32);
643 
644  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
645  /*IsVolatile=*/false,
646  /*AlwaysInline=*/false,
647  /*isTailCall=*/false, MachinePointerInfo(),
649  ByValArgs.push_back(FIPtr);
650  }
651 
652  Chain = DAG.getCALLSEQ_START(
653  Chain,
654  DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
655  DL);
656 
658  SmallVector<SDValue, 12> MemOpChains;
659  SDValue StackPtr;
660 
661  // Walk the register/memloc assignments, inserting copies/loads.
662  for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {
663  CCValAssign &VA = ArgLocs[I];
664  SDValue Arg = OutVals[I];
665  ISD::ArgFlagsTy Flags = Outs[I].Flags;
666 
667  // Promote the value if needed.
668  switch (VA.getLocInfo()) {
669  case CCValAssign::Full:
670  break;
671  case CCValAssign::SExt:
672  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
673  break;
674  case CCValAssign::ZExt:
675  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
676  break;
677  case CCValAssign::AExt:
678  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
679  break;
680  default:
681  llvm_unreachable("Unknown loc info!");
682  }
683 
684  // Use local copy if it is a byval arg.
685  if (Flags.isByVal())
686  Arg = ByValArgs[J++];
687 
688  // Arguments that can be passed on register must be kept at RegsToPass
689  // vector
690  if (VA.isRegLoc()) {
691  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
692  } else {
693  assert(VA.isMemLoc());
694 
695  if (StackPtr.getNode() == nullptr)
696  StackPtr = DAG.getCopyFromReg(Chain, DL, Lanai::SP,
697  getPointerTy(DAG.getDataLayout()));
698 
699  SDValue PtrOff =
700  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
701  DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
702 
703  MemOpChains.push_back(
704  DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
705  }
706  }
707 
708  // Transform all store nodes into one single node because all store nodes are
709  // independent of each other.
710  if (!MemOpChains.empty())
711  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
712  ArrayRef<SDValue>(&MemOpChains[0], MemOpChains.size()));
713 
714  SDValue InFlag;
715 
716  // Build a sequence of copy-to-reg nodes chained together with token chain and
717  // flag operands which copy the outgoing args into registers. The InFlag in
718  // necessary since all emitted instructions must be stuck together.
719  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
720  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
721  RegsToPass[I].second, InFlag);
722  InFlag = Chain.getValue(1);
723  }
724 
725  // If the callee is a GlobalAddress node (quite common, every direct call is)
726  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
727  // Likewise ExternalSymbol -> TargetExternalSymbol.
728  uint8_t OpFlag = LanaiII::MO_NO_FLAG;
729  if (G) {
730  Callee = DAG.getTargetGlobalAddress(
731  G->getGlobal(), DL, getPointerTy(DAG.getDataLayout()), 0, OpFlag);
732  } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
733  Callee = DAG.getTargetExternalSymbol(
734  E->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlag);
735  }
736 
737  // Returns a chain & a flag for retval copy to use.
738  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
740  Ops.push_back(Chain);
741  Ops.push_back(Callee);
742 
743  // Add a register mask operand representing the call-preserved registers.
744  // TODO: Should return-twice functions be handled?
745  const uint32_t *Mask =
746  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
747  assert(Mask && "Missing call preserved mask for calling convention");
748  Ops.push_back(DAG.getRegisterMask(Mask));
749 
750  // Add argument registers to the end of the list so that they are
751  // known live into the call.
752  for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
753  Ops.push_back(DAG.getRegister(RegsToPass[I].first,
754  RegsToPass[I].second.getValueType()));
755 
756  if (InFlag.getNode())
757  Ops.push_back(InFlag);
758 
759  Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,
760  ArrayRef<SDValue>(&Ops[0], Ops.size()));
761  InFlag = Chain.getValue(1);
762 
763  // Create the CALLSEQ_END node.
764  Chain = DAG.getCALLSEQ_END(
765  Chain,
766  DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
767  DAG.getConstant(0, DL, getPointerTy(DAG.getDataLayout()), true), InFlag,
768  DL);
769  InFlag = Chain.getValue(1);
770 
771  // Handle result values, copying them out of physregs into vregs that we
772  // return.
773  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
774  InVals);
775 }
776 
777 // LowerCallResult - Lower the result values of a call into the
778 // appropriate copies out of appropriate physical registers.
779 SDValue LanaiTargetLowering::LowerCallResult(
780  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
781  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
782  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
783  // Assign locations to each value returned by this call.
785  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
786  *DAG.getContext());
787 
788  CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);
789 
790  // Copy all of the result registers out of their specified physreg.
791  for (unsigned I = 0; I != RVLocs.size(); ++I) {
792  Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(),
793  RVLocs[I].getValVT(), InFlag)
794  .getValue(1);
795  InFlag = Chain.getValue(2);
796  InVals.push_back(Chain.getValue(0));
797  }
798 
799  return Chain;
800 }
801 
802 //===----------------------------------------------------------------------===//
803 // Custom Lowerings
804 //===----------------------------------------------------------------------===//
805 
807  SDValue &RHS, SelectionDAG &DAG) {
808  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
809 
810  // For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
811  // SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
812  // and Lanai only supports integer comparisons, so only provide definitions
813  // for them.
814  switch (SetCCOpcode) {
815  case ISD::SETEQ:
816  return LPCC::ICC_EQ;
817  case ISD::SETGT:
818  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
819  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
820  // X > -1 -> X >= 0 -> is_plus(X)
821  RHS = DAG.getConstant(0, DL, RHS.getValueType());
822  return LPCC::ICC_PL;
823  }
824  return LPCC::ICC_GT;
825  case ISD::SETUGT:
826  return LPCC::ICC_UGT;
827  case ISD::SETLT:
828  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
829  if (RHSC->getZExtValue() == 0)
830  // X < 0 -> is_minus(X)
831  return LPCC::ICC_MI;
832  return LPCC::ICC_LT;
833  case ISD::SETULT:
834  return LPCC::ICC_ULT;
835  case ISD::SETLE:
836  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
837  if (RHSC->getZExtValue() == 0xFFFFFFFF) {
838  // X <= -1 -> X < 0 -> is_minus(X)
839  RHS = DAG.getConstant(0, DL, RHS.getValueType());
840  return LPCC::ICC_MI;
841  }
842  return LPCC::ICC_LE;
843  case ISD::SETULE:
844  return LPCC::ICC_ULE;
845  case ISD::SETGE:
846  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
847  if (RHSC->getZExtValue() == 0)
848  // X >= 0 -> is_plus(X)
849  return LPCC::ICC_PL;
850  return LPCC::ICC_GE;
851  case ISD::SETUGE:
852  return LPCC::ICC_UGE;
853  case ISD::SETNE:
854  return LPCC::ICC_NE;
855  case ISD::SETONE:
856  case ISD::SETUNE:
857  case ISD::SETOGE:
858  case ISD::SETOLE:
859  case ISD::SETOLT:
860  case ISD::SETOGT:
861  case ISD::SETOEQ:
862  case ISD::SETUEQ:
863  case ISD::SETO:
864  case ISD::SETUO:
865  llvm_unreachable("Unsupported comparison.");
866  default:
867  llvm_unreachable("Unknown integer condition code!");
868  }
869 }
870 
872  SDValue Chain = Op.getOperand(0);
873  SDValue Cond = Op.getOperand(1);
874  SDValue LHS = Op.getOperand(2);
875  SDValue RHS = Op.getOperand(3);
876  SDValue Dest = Op.getOperand(4);
877  SDLoc DL(Op);
878 
879  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
880  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
881  SDValue Flag =
882  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
883 
884  return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,
885  TargetCC, Flag);
886 }
887 
889  EVT VT = Op->getValueType(0);
890  if (VT != MVT::i32)
891  return SDValue();
892 
894  if (!C)
895  return SDValue();
896 
897  int64_t MulAmt = C->getSExtValue();
898  int32_t HighestOne = -1;
899  uint32_t NonzeroEntries = 0;
900  int SignedDigit[32] = {0};
901 
902  // Convert to non-adjacent form (NAF) signed-digit representation.
903  // NAF is a signed-digit form where no adjacent digits are non-zero. It is the
904  // minimal Hamming weight representation of a number (on average 1/3 of the
905  // digits will be non-zero vs 1/2 for regular binary representation). And as
906  // the non-zero digits will be the only digits contributing to the instruction
907  // count, this is desirable. The next loop converts it to NAF (following the
908  // approach in 'Guide to Elliptic Curve Cryptography' [ISBN: 038795273X]) by
909  // choosing the non-zero coefficients such that the resulting quotient is
910  // divisible by 2 which will cause the next coefficient to be zero.
911  int64_t E = std::abs(MulAmt);
912  int S = (MulAmt < 0 ? -1 : 1);
913  int I = 0;
914  while (E > 0) {
915  int ZI = 0;
916  if (E % 2 == 1) {
917  ZI = 2 - (E % 4);
918  if (ZI != 0)
919  ++NonzeroEntries;
920  }
921  SignedDigit[I] = S * ZI;
922  if (SignedDigit[I] == 1)
923  HighestOne = I;
924  E = (E - ZI) / 2;
925  ++I;
926  }
927 
928  // Compute number of instructions required. Due to differences in lowering
929  // between the different processors this count is not exact.
930  // Start by assuming a shift and a add/sub for every non-zero entry (hence
931  // every non-zero entry requires 1 shift and 1 add/sub except for the first
932  // entry).
933  int32_t InstrRequired = 2 * NonzeroEntries - 1;
934  // Correct possible over-adding due to shift by 0 (which is not emitted).
935  if (std::abs(MulAmt) % 2 == 1)
936  --InstrRequired;
937  // Return if the form generated would exceed the instruction threshold.
938  if (InstrRequired > LanaiLowerConstantMulThreshold)
939  return SDValue();
940 
941  SDValue Res;
942  SDLoc DL(Op);
943  SDValue V = Op->getOperand(0);
944 
945  // Initialize the running sum. Set the running sum to the maximal shifted
946  // positive value (i.e., largest i such that zi == 1 and MulAmt has V<<i as a
947  // term NAF).
948  if (HighestOne == -1)
949  Res = DAG.getConstant(0, DL, MVT::i32);
950  else {
951  Res = DAG.getNode(ISD::SHL, DL, VT, V,
952  DAG.getConstant(HighestOne, DL, MVT::i32));
953  SignedDigit[HighestOne] = 0;
954  }
955 
956  // Assemble multiplication from shift, add, sub using NAF form and running
957  // sum.
958  for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
959  ++I) {
960  if (SignedDigit[I] == 0)
961  continue;
962 
963  // Shifted multiplicand (v<<i).
964  SDValue Op =
965  DAG.getNode(ISD::SHL, DL, VT, V, DAG.getConstant(I, DL, MVT::i32));
966  if (SignedDigit[I] == 1)
967  Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
968  else if (SignedDigit[I] == -1)
969  Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
970  }
971  return Res;
972 }
973 
975  SDValue LHS = Op.getOperand(0);
976  SDValue RHS = Op.getOperand(1);
977  SDValue Carry = Op.getOperand(2);
978  SDValue Cond = Op.getOperand(3);
979  SDLoc DL(Op);
980 
981  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
982  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
983  SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
984  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
985 }
986 
988  SDValue LHS = Op.getOperand(0);
989  SDValue RHS = Op.getOperand(1);
990  SDValue Cond = Op.getOperand(2);
991  SDLoc DL(Op);
992 
993  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
994  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
995  SDValue Flag =
996  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
997 
998  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
999 }
1000 
1002  SelectionDAG &DAG) const {
1003  SDValue LHS = Op.getOperand(0);
1004  SDValue RHS = Op.getOperand(1);
1005  SDValue TrueV = Op.getOperand(2);
1006  SDValue FalseV = Op.getOperand(3);
1007  SDValue Cond = Op.getOperand(4);
1008  SDLoc DL(Op);
1009 
1010  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
1011  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
1012  SDValue Flag =
1013  DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
1014 
1015  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1016  return DAG.getNode(LanaiISD::SELECT_CC, DL, VTs, TrueV, FalseV, TargetCC,
1017  Flag);
1018 }
1019 
1021  MachineFunction &MF = DAG.getMachineFunction();
1023 
1024  SDLoc DL(Op);
1025  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1026  getPointerTy(DAG.getDataLayout()));
1027 
1028  // vastart just stores the address of the VarArgsFrameIndex slot into the
1029  // memory location argument.
1030  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1031  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1032  MachinePointerInfo(SV));
1033 }
1034 
1036  SelectionDAG &DAG) const {
1037  SDValue Chain = Op.getOperand(0);
1038  SDValue Size = Op.getOperand(1);
1039  SDLoc DL(Op);
1040 
1041  unsigned SPReg = getStackPointerRegisterToSaveRestore();
1042 
1043  // Get a reference to the stack pointer.
1044  SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32);
1045 
1046  // Subtract the dynamic size from the actual stack size to
1047  // obtain the new stack size.
1048  SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size);
1049 
1050  // For Lanai, the outgoing memory arguments area should be on top of the
1051  // alloca area on the stack i.e., the outgoing memory arguments should be
1052  // at a lower address than the alloca area. Move the alloca area down the
1053  // stack by adding back the space reserved for outgoing arguments to SP
1054  // here.
1055  //
1056  // We do not know what the size of the outgoing args is at this point.
1057  // So, we add a pseudo instruction ADJDYNALLOC that will adjust the
1058  // stack pointer. We replace this instruction with on that has the correct,
1059  // known offset in emitPrologue().
1060  SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);
1061 
1062  // The Sub result contains the new stack start address, so it
1063  // must be placed in the stack pointer register.
1064  SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub);
1065 
1066  SDValue Ops[2] = {ArgAdjust, CopyChain};
1067  return DAG.getMergeValues(Ops, DL);
1068 }
1069 
1071  SelectionDAG &DAG) const {
1072  MachineFunction &MF = DAG.getMachineFunction();
1073  MachineFrameInfo &MFI = MF.getFrameInfo();
1074  MFI.setReturnAddressIsTaken(true);
1075 
1076  EVT VT = Op.getValueType();
1077  SDLoc DL(Op);
1078  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1079  if (Depth) {
1080  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1081  const unsigned Offset = -4;
1082  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1083  DAG.getIntPtrConstant(Offset, DL));
1084  return DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1085  }
1086 
1087  // Return the link register, which contains the return address.
1088  // Mark it an implicit live-in.
1089  unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
1090  return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
1091 }
1092 
1094  SelectionDAG &DAG) const {
1096  MFI.setFrameAddressIsTaken(true);
1097 
1098  EVT VT = Op.getValueType();
1099  SDLoc DL(Op);
1100  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
1101  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1102  while (Depth--) {
1103  const unsigned Offset = -8;
1104  SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
1105  DAG.getIntPtrConstant(Offset, DL));
1106  FrameAddr =
1107  DAG.getLoad(VT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
1108  }
1109  return FrameAddr;
1110 }
1111 
1112 const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
1113  switch (Opcode) {
1114  case LanaiISD::ADJDYNALLOC:
1115  return "LanaiISD::ADJDYNALLOC";
1116  case LanaiISD::RET_FLAG:
1117  return "LanaiISD::RET_FLAG";
1118  case LanaiISD::CALL:
1119  return "LanaiISD::CALL";
1120  case LanaiISD::SELECT_CC:
1121  return "LanaiISD::SELECT_CC";
1122  case LanaiISD::SETCC:
1123  return "LanaiISD::SETCC";
1124  case LanaiISD::SUBBF:
1125  return "LanaiISD::SUBBF";
1126  case LanaiISD::SET_FLAG:
1127  return "LanaiISD::SET_FLAG";
1128  case LanaiISD::BR_CC:
1129  return "LanaiISD::BR_CC";
1130  case LanaiISD::Wrapper:
1131  return "LanaiISD::Wrapper";
1132  case LanaiISD::HI:
1133  return "LanaiISD::HI";
1134  case LanaiISD::LO:
1135  return "LanaiISD::LO";
1136  case LanaiISD::SMALL:
1137  return "LanaiISD::SMALL";
1138  default:
1139  return nullptr;
1140  }
1141 }
1142 
1144  SelectionDAG &DAG) const {
1145  SDLoc DL(Op);
1146  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1147  const Constant *C = N->getConstVal();
1148  const LanaiTargetObjectFile *TLOF =
1149  static_cast<const LanaiTargetObjectFile *>(
1151 
1152  // If the code model is small or constant will be placed in the small section,
1153  // then assume address will fit in 21-bits.
1155  TLOF->isConstantInSmallSection(DAG.getDataLayout(), C)) {
1158  return DAG.getNode(ISD::OR, DL, MVT::i32,
1159  DAG.getRegister(Lanai::R0, MVT::i32),
1160  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1161  } else {
1162  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1163  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1164 
1166  N->getOffset(), OpFlagHi);
1168  N->getOffset(), OpFlagLo);
1169  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1170  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1171  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1172  return Result;
1173  }
1174 }
1175 
1177  SelectionDAG &DAG) const {
1178  SDLoc DL(Op);
1179  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1180  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
1181 
1182  const LanaiTargetObjectFile *TLOF =
1183  static_cast<const LanaiTargetObjectFile *>(
1185 
1186  // If the code model is small or global variable will be placed in the small
1187  // section, then assume address will fit in 21-bits.
1188  const GlobalObject *GO = GV->getBaseObject();
1189  if (TLOF->isGlobalInSmallSection(GO, getTargetMachine())) {
1191  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, LanaiII::MO_NO_FLAG);
1192  return DAG.getNode(ISD::OR, DL, MVT::i32,
1193  DAG.getRegister(Lanai::R0, MVT::i32),
1194  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1195  } else {
1196  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1197  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1198 
1199  // Create the TargetGlobalAddress node, folding in the constant offset.
1201  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagHi);
1203  GV, DL, getPointerTy(DAG.getDataLayout()), Offset, OpFlagLo);
1204  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1205  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1206  return DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1207  }
1208 }
1209 
1211  SelectionDAG &DAG) const {
1212  SDLoc DL(Op);
1213  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1214 
1215  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1216  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1217 
1218  SDValue Hi = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagHi);
1219  SDValue Lo = DAG.getBlockAddress(BA, MVT::i32, true, OpFlagLo);
1220  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1221  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1222  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1223  return Result;
1224 }
1225 
1227  SelectionDAG &DAG) const {
1228  SDLoc DL(Op);
1229  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1230 
1231  // If the code model is small assume address will fit in 21-bits.
1235  return DAG.getNode(ISD::OR, DL, MVT::i32,
1236  DAG.getRegister(Lanai::R0, MVT::i32),
1237  DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));
1238  } else {
1239  uint8_t OpFlagHi = LanaiII::MO_ABS_HI;
1240  uint8_t OpFlagLo = LanaiII::MO_ABS_LO;
1241 
1243  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagHi);
1245  JT->getIndex(), getPointerTy(DAG.getDataLayout()), OpFlagLo);
1246  Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);
1247  Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);
1248  SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Hi, Lo);
1249  return Result;
1250  }
1251 }
1252 
1254  SelectionDAG &DAG) const {
1255  EVT VT = Op.getValueType();
1256  unsigned VTBits = VT.getSizeInBits();
1257  SDLoc dl(Op);
1258  assert(Op.getNumOperands() == 3 && "Unexpected SHL!");
1259  SDValue ShOpLo = Op.getOperand(0);
1260  SDValue ShOpHi = Op.getOperand(1);
1261  SDValue ShAmt = Op.getOperand(2);
1262 
1263  // Performs the following for (ShOpLo + (ShOpHi << 32)) << ShAmt:
1264  // LoBitsForHi = (ShAmt == 0) ? 0 : (ShOpLo >> (32-ShAmt))
1265  // HiBitsForHi = ShOpHi << ShAmt
1266  // Hi = (ShAmt >= 32) ? (ShOpLo << (ShAmt-32)) : (LoBitsForHi | HiBitsForHi)
1267  // Lo = (ShAmt >= 32) ? 0 : (ShOpLo << ShAmt)
1268  // return (Hi << 32) | Lo;
1269 
1270  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1271  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1272  SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1273 
1274  // If ShAmt == 0, we just calculated "(SRL ShOpLo, 32)" which is "undef". We
1275  // wanted 0, so CSEL it directly.
1276  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1277  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1278  LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);
1279 
1280  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1281  DAG.getConstant(VTBits, dl, MVT::i32));
1282  SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1283  SDValue HiForNormalShift =
1284  DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
1285 
1286  SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1287 
1288  SetCC = DAG.getSetCC(dl, MVT::i32, ExtraShAmt, Zero, ISD::SETGE);
1289  SDValue Hi =
1290  DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);
1291 
1292  // Lanai shifts of larger than register sizes are wrapped rather than
1293  // clamped, so we can't just emit "lo << b" if b is too big.
1294  SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1295  SDValue Lo = DAG.getSelect(
1296  dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);
1297 
1298  SDValue Ops[2] = {Lo, Hi};
1299  return DAG.getMergeValues(Ops, dl);
1300 }
1301 
1303  SelectionDAG &DAG) const {
1304  MVT VT = Op.getSimpleValueType();
1305  unsigned VTBits = VT.getSizeInBits();
1306  SDLoc dl(Op);
1307  SDValue ShOpLo = Op.getOperand(0);
1308  SDValue ShOpHi = Op.getOperand(1);
1309  SDValue ShAmt = Op.getOperand(2);
1310 
1311  // Performs the following for a >> b:
1312  // unsigned r_high = a_high >> b;
1313  // r_high = (32 - b <= 0) ? 0 : r_high;
1314  //
1315  // unsigned r_low = a_low >> b;
1316  // r_low = (32 - b <= 0) ? r_high : r_low;
1317  // r_low = (b == 0) ? r_low : r_low | (a_high << (32 - b));
1318  // return (unsigned long long)r_high << 32 | r_low;
1319  // Note: This takes advantage of Lanai's shift behavior to avoid needing to
1320  // mask the shift amount.
1321 
1322  SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
1323  SDValue NegatedPlus32 = DAG.getNode(
1324  ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
1325  SDValue SetCC = DAG.getSetCC(dl, MVT::i32, NegatedPlus32, Zero, ISD::SETLE);
1326 
1327  SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpHi, ShAmt);
1328  Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);
1329 
1330  SDValue Lo = DAG.getNode(ISD::SRL, dl, MVT::i32, ShOpLo, ShAmt);
1331  Lo = DAG.getSelect(dl, MVT::i32, SetCC, Hi, Lo);
1332  SDValue CarryBits =
1333  DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);
1334  SDValue ShiftIsZero = DAG.getSetCC(dl, MVT::i32, ShAmt, Zero, ISD::SETEQ);
1335  Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,
1336  DAG.getNode(ISD::OR, dl, MVT::i32, Lo, CarryBits));
1337 
1338  SDValue Ops[2] = {Lo, Hi};
1339  return DAG.getMergeValues(Ops, dl);
1340 }
1341 
1342 // Helper function that checks if N is a null or all ones constant.
1343 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
1344  return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
1345 }
1346 
1347 // Return true if N is conditionally 0 or all ones.
1348 // Detects these expressions where cc is an i1 value:
1349 //
1350 // (select cc 0, y) [AllOnes=0]
1351 // (select cc y, 0) [AllOnes=0]
1352 // (zext cc) [AllOnes=0]
1353 // (sext cc) [AllOnes=0/1]
1354 // (select cc -1, y) [AllOnes=1]
1355 // (select cc y, -1) [AllOnes=1]
1356 //
1357 // * AllOnes determines whether to check for an all zero (AllOnes false) or an
1358 // all ones operand (AllOnes true).
1359 // * Invert is set when N is the all zero/ones constant when CC is false.
1360 // * OtherOp is set to the alternative value of N.
1361 //
1362 // For example, for (select cc X, Y) and AllOnes = 0 if:
1363 // * X = 0, Invert = False and OtherOp = Y
1364 // * Y = 0, Invert = True and OtherOp = X
1365 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC,
1366  bool &Invert, SDValue &OtherOp,
1367  SelectionDAG &DAG) {
1368  switch (N->getOpcode()) {
1369  default:
1370  return false;
1371  case ISD::SELECT: {
1372  CC = N->getOperand(0);
1373  SDValue N1 = N->getOperand(1);
1374  SDValue N2 = N->getOperand(2);
1375  if (isZeroOrAllOnes(N1, AllOnes)) {
1376  Invert = false;
1377  OtherOp = N2;
1378  return true;
1379  }
1380  if (isZeroOrAllOnes(N2, AllOnes)) {
1381  Invert = true;
1382  OtherOp = N1;
1383  return true;
1384  }
1385  return false;
1386  }
1387  case ISD::ZERO_EXTEND: {
1388  // (zext cc) can never be the all ones value.
1389  if (AllOnes)
1390  return false;
1391  CC = N->getOperand(0);
1392  if (CC.getValueType() != MVT::i1)
1393  return false;
1394  SDLoc dl(N);
1395  EVT VT = N->getValueType(0);
1396  OtherOp = DAG.getConstant(1, dl, VT);
1397  Invert = true;
1398  return true;
1399  }
1400  case ISD::SIGN_EXTEND: {
1401  CC = N->getOperand(0);
1402  if (CC.getValueType() != MVT::i1)
1403  return false;
1404  SDLoc dl(N);
1405  EVT VT = N->getValueType(0);
1406  Invert = !AllOnes;
1407  if (AllOnes)
1408  // When looking for an AllOnes constant, N is an sext, and the 'other'
1409  // value is 0.
1410  OtherOp = DAG.getConstant(0, dl, VT);
1411  else
1412  OtherOp =
1414  return true;
1415  }
1416  }
1417 }
1418 
1419 // Combine a constant select operand into its use:
1420 //
1421 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1422 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1423 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
1424 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
1425 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
1426 //
1427 // The transform is rejected if the select doesn't have a constant operand that
1428 // is null, or all ones when AllOnes is set.
1429 //
1430 // Also recognize sext/zext from i1:
1431 //
1432 // (add (zext cc), x) -> (select cc (add x, 1), x)
1433 // (add (sext cc), x) -> (select cc (add x, -1), x)
1434 //
1435 // These transformations eventually create predicated instructions.
1438  bool AllOnes) {
1439  SelectionDAG &DAG = DCI.DAG;
1440  EVT VT = N->getValueType(0);
1441  SDValue NonConstantVal;
1442  SDValue CCOp;
1443  bool SwapSelectOps;
1444  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
1445  NonConstantVal, DAG))
1446  return SDValue();
1447 
1448  // Slct is now know to be the desired identity constant when CC is true.
1449  SDValue TrueVal = OtherOp;
1450  SDValue FalseVal =
1451  DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);
1452  // Unless SwapSelectOps says CC should be false.
1453  if (SwapSelectOps)
1454  std::swap(TrueVal, FalseVal);
1455 
1456  return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
1457 }
1458 
1459 // Attempt combineSelectAndUse on each operand of a commutative operator N.
1460 static SDValue
1462  bool AllOnes) {
1463  SDValue N0 = N->getOperand(0);
1464  SDValue N1 = N->getOperand(1);
1465  if (N0.getNode()->hasOneUse())
1466  if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
1467  return Result;
1468  if (N1.getNode()->hasOneUse())
1469  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
1470  return Result;
1471  return SDValue();
1472 }
1473 
1474 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1477  SDValue N0 = N->getOperand(0);
1478  SDValue N1 = N->getOperand(1);
1479 
1480  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1481  if (N1.getNode()->hasOneUse())
1482  if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, /*AllOnes=*/false))
1483  return Result;
1484 
1485  return SDValue();
1486 }
1487 
1489  DAGCombinerInfo &DCI) const {
1490  switch (N->getOpcode()) {
1491  default:
1492  break;
1493  case ISD::ADD:
1494  case ISD::OR:
1495  case ISD::XOR:
1496  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/false);
1497  case ISD::AND:
1498  return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
1499  case ISD::SUB:
1500  return PerformSUBCombine(N, DCI);
1501  }
1502 
1503  return SDValue();
1504 }
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
void setFrameAddressIsTaken(bool T)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
MVT getValVT() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:458
LLVMContext * getContext() const
Definition: SelectionDAG.h:333
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:804
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:724
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
size_t i
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:572
LocInfo getLocInfo() const
bool hasOneUse() const
Return true if there is exactly one use of this node.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:137
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:615
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
unsigned getSizeInBits() const
unsigned getByValSize() const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
unsigned getNumOperands() const
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
Definition: SelectionDAG.h:817
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:369
bool isRegLoc() const
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:388
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
Definition: Constants.h:822
std::string getEVTString() const
getEVTString - This function returns value type as a string, e.g.
Definition: ValueTypes.cpp:120
struct fuzzer::@269 Flags
Shift and rotation operations.
Definition: ISDOpcodes.h:344
static SDValue combineSelectAndUseCommutative(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:327
virtual TargetLoweringObjectFile * getObjFileLowering() const
void addLoc(const CCValAssign &V)
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
Reg
All possible values of the reg field in the ModR/M byte.
SimpleValueType SimpleTy
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:73
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:611
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:74
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:421
unsigned getRARegister() const
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:487
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:328
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
SDNode * getNode() const
get the SDNode which holds the desired result
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
CodeModel::Model getCodeModel() const
Returns the code model.
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
MVT getLocVT() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
Definition: Constant.h:42
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:637
const Constant * getConstVal() const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
uint32_t Offset
static bool isZeroOrAllOnes(SDValue N, bool AllOnes)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:628
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
static unsigned NumFixedArgs
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
This structure contains all information that is necessary for lowering calls.
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant ""multiplication instead of calling library function [default=14]"), cl::init(14))
unsigned getByValAlign() const
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:546
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:540
TokenFactor - This node takes multiple tokens as input and produces a single token result...
Definition: ISDOpcodes.h:50
CCState - This class holds information needed while lowering arguments and return values...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:274
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:566
const DataFlowGraph & G
Definition: RDFGraph.cpp:206
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:347
bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const
Return true if this constant should be placed into small data section.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:584
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Definition: SelectionDAG.h:715
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:354
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:400
const GlobalObject * getBaseObject() const
Definition: GlobalValue.h:517
bool isMemLoc() const
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:403
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned char TargetFlags=0)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:560
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:633
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:333
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:610
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:418
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:256
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
FunctionType * getFunctionType() const
Returns the FunctionType for me.
Definition: Function.cpp:230
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1099
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static volatile int Zero
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:312
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a carry value...
Definition: ISDOpcodes.h:383
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
unsigned getAlignment() const
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
LLVM Value Representation.
Definition: Value.h:71
static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes)
SDValue getRegister(unsigned Reg, EVT VT)
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
#define DEBUG(X)
Definition: Debug.h:100
Primary interface to the complete machine description for the target machine.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:377
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
unsigned getLocMemOffset() const
Conversion operators.
Definition: ISDOpcodes.h:397
int * Ptr
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:381
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:406
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const LanaiRegisterInfo * getRegisterInfo() const override
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:226
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:529
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:326
char * PC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:545