LLVM  4.0.0
ARMMCInstLower.cpp
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1 //===-- ARMMCInstLower.cpp - Convert ARM MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower ARM MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARM.h"
16 #include "ARMAsmPrinter.h"
18 #include "MCTargetDesc/ARMMCExpr.h"
20 #include "llvm/IR/Constants.h"
21 #include "llvm/IR/Mangler.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCInstBuilder.h"
26 #include "llvm/MC/MCStreamer.h"
27 using namespace llvm;
28 
29 
30 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
31  const MCSymbol *Symbol) {
32  const MCExpr *Expr =
34  switch (MO.getTargetFlags() & ARMII::MO_OPTION_MASK) {
35  default:
36  llvm_unreachable("Unknown target flag on symbol operand");
37  case ARMII::MO_NO_FLAG:
38  break;
39  case ARMII::MO_LO16:
40  Expr =
43  break;
44  case ARMII::MO_HI16:
45  Expr =
48  break;
49  }
50 
51  if (!MO.isJTI() && MO.getOffset())
52  Expr = MCBinaryExpr::createAdd(Expr,
54  OutContext),
55  OutContext);
56  return MCOperand::createExpr(Expr);
57 
58 }
59 
61  MCOperand &MCOp) {
62  switch (MO.getType()) {
63  default: llvm_unreachable("unknown operand type");
65  // Ignore all non-CPSR implicit register operands.
66  if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
67  return false;
68  assert(!MO.getSubReg() && "Subregs should be eliminated!");
69  MCOp = MCOperand::createReg(MO.getReg());
70  break;
72  MCOp = MCOperand::createImm(MO.getImm());
73  break;
76  MO.getMBB()->getSymbol(), OutContext));
77  break;
79  MCOp = GetSymbolRef(MO,
80  GetARMGVSymbol(MO.getGlobal(), MO.getTargetFlags()));
81  break;
82  }
84  MCOp = GetSymbolRef(MO,
86  break;
88  MCOp = GetSymbolRef(MO, GetJTISymbol(MO.getIndex()));
89  break;
91  if (Subtarget->genExecuteOnly())
92  llvm_unreachable("execute-only should not generate constant pools");
93  MCOp = GetSymbolRef(MO, GetCPISymbol(MO.getIndex()));
94  break;
96  MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
97  break;
99  APFloat Val = MO.getFPImm()->getValueAPF();
100  bool ignored;
103  break;
104  }
106  // Ignore call clobbers.
107  return false;
108  }
109  return true;
110 }
111 
113  ARMAsmPrinter &AP) {
114  OutMI.setOpcode(MI->getOpcode());
115 
116  // In the MC layer, we keep modified immediates in their encoded form
117  bool EncodeImms = false;
118  switch (MI->getOpcode()) {
119  default: break;
120  case ARM::MOVi:
121  case ARM::MVNi:
122  case ARM::CMPri:
123  case ARM::CMNri:
124  case ARM::TSTri:
125  case ARM::TEQri:
126  case ARM::MSRi:
127  case ARM::ADCri:
128  case ARM::ADDri:
129  case ARM::ADDSri:
130  case ARM::SBCri:
131  case ARM::SUBri:
132  case ARM::SUBSri:
133  case ARM::ANDri:
134  case ARM::ORRri:
135  case ARM::EORri:
136  case ARM::BICri:
137  case ARM::RSBri:
138  case ARM::RSBSri:
139  case ARM::RSCri:
140  EncodeImms = true;
141  break;
142  }
143 
144  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
145  const MachineOperand &MO = MI->getOperand(i);
146 
147  MCOperand MCOp;
148  if (AP.lowerOperand(MO, MCOp)) {
149  if (MCOp.isImm() && EncodeImms) {
150  int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
151  if (Enc != -1)
152  MCOp.setImm(Enc);
153  }
154  OutMI.addOperand(MCOp);
155  }
156  }
157 }
158 
159 void ARMAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
160 {
162  ->isThumbFunction())
163  {
164  MI.emitError("An attempt to perform XRay instrumentation for a"
165  " Thumb function (not supported). Detected when emitting a sled.");
166  return;
167  }
168  static const int8_t NoopsInSledCount = 6;
169  // We want to emit the following pattern:
170  //
171  // .Lxray_sled_N:
172  // ALIGN
173  // B #20
174  // ; 6 NOP instructions (24 bytes)
175  // .tmpN
176  //
177  // We need the 24 bytes (6 instructions) because at runtime, we'd be patching
178  // over the full 28 bytes (7 instructions) with the following pattern:
179  //
180  // PUSH{ r0, lr }
181  // MOVW r0, #<lower 16 bits of function ID>
182  // MOVT r0, #<higher 16 bits of function ID>
183  // MOVW ip, #<lower 16 bits of address of __xray_FunctionEntry/Exit>
184  // MOVT ip, #<higher 16 bits of address of __xray_FunctionEntry/Exit>
185  // BLX ip
186  // POP{ r0, lr }
187  //
188  OutStreamer->EmitCodeAlignment(4);
189  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
190  OutStreamer->EmitLabel(CurSled);
192 
193  // Emit "B #20" instruction, which jumps over the next 24 bytes (because
194  // register pc is 8 bytes ahead of the jump instruction by the moment CPU
195  // is executing it).
196  // By analogy to ARMAsmPrinter::emitPseudoExpansionLowering() |case ARM::B|.
197  // It is not clear why |addReg(0)| is needed (the last operand).
198  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc).addImm(20)
199  .addImm(ARMCC::AL).addReg(0));
200 
201  MCInst Noop;
202  Subtarget->getInstrInfo()->getNoopForElfTarget(Noop);
203  for (int8_t I = 0; I < NoopsInSledCount; I++)
204  {
205  OutStreamer->EmitInstruction(Noop, getSubtargetInfo());
206  }
207 
208  OutStreamer->EmitLabel(Target);
209  recordSled(CurSled, MI, Kind);
210 }
211 
213 {
214  EmitSled(MI, SledKind::FUNCTION_ENTER);
215 }
216 
218 {
219  EmitSled(MI, SledKind::FUNCTION_EXIT);
220 }
221 
223 {
224  EmitSled(MI, SledKind::TAIL_CALL);
225 }
bool isImplicit() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
virtual void getNoopForElfTarget(MCInst &NopInst) const
const GlobalValue * getGlobal() const
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp)
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:84
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:298
size_t i
const ConstantFP * getFPImm() const
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:79
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
Address of indexed Jump Table for switch.
MachineBasicBlock reference.
const char * getSymbolName() const
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:156
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Mask of preserved registers.
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:376
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Name of external global symbol.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:43
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
Definition: APFloat.cpp:4139
int64_t getImm() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:429
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool isImm() const
Definition: MCInst.h:57
Address of a global value.
void setImm(int64_t Val)
Definition: MCInst.h:78
unsigned getTargetFlags() const
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:218
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind)
Address of a basic block.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int64_t getOffset() const
Return the offset from the symbol in this operand.
unsigned getSubReg() const
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:286
bool genExecuteOnly() const
Definition: ARMSubtarget.h:500
void setOpcode(unsigned Op)
Definition: MCInst.h:158
MachineOperand class - Representation of each machine instruction operand.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:161
static MCOperand createFPImm(double Val)
Definition: MCInst.h:123
Target - Wrapper for Target specific information.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
int64_t getImm() const
Definition: MCInst.h:74
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
double convertToDouble() const
Definition: APFloat.h:1013
static const fltSemantics & IEEEdouble()
Definition: APFloat.cpp:103
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
#define I(x, y, z)
Definition: MD5.cpp:54
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:39
MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects just that part of the flag set...
Definition: ARMBaseInfo.h:294
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
const APFloat & getValueAPF() const
Definition: Constants.h:300
const unsigned Kind
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Floating-point immediate operand.
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
const BlockAddress * getBlockAddress() const
Address of indexed Constant in Constant Pool.
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:149
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:290