43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
49 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
52 bool MatchingInlineAsm)
override;
53 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
56 bool ParseDirective(
AsmToken DirectiveID)
override;
59 unsigned Kind)
override;
67 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
77 bool matchRegisterName(
const AsmToken &Tok,
unsigned &RegNo,
80 bool matchSparcAsmModifiers(
const MCExpr *&EVal,
SMLoc &EndLoc);
81 bool parseDirectiveWord(
unsigned Size,
SMLoc L);
96 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
102 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
103 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
104 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
105 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
106 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
107 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
108 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
109 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
112 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
113 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
114 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
115 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
116 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
117 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
118 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
119 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
121 static const MCPhysReg DoubleRegs[32] = {
122 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
123 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
124 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
125 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
126 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
127 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
128 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
129 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
131 static const MCPhysReg QuadFPRegs[32] = {
132 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
133 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
134 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
135 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
138 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
139 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
140 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
141 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
142 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
143 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
144 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
145 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
148 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
149 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
150 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
151 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
153 static const MCPhysReg CoprocRegs[32] = {
154 Sparc::C0, Sparc::C1, Sparc::C2, Sparc::C3,
155 Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,
156 Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,
157 Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
158 Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
159 Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
160 Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
161 Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
163 static const MCPhysReg CoprocPairRegs[] = {
164 Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
165 Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
166 Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
167 Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
194 SMLoc StartLoc, EndLoc;
225 bool isToken()
const override {
return Kind == k_Token; }
226 bool isReg()
const override {
return Kind == k_Register; }
227 bool isImm()
const override {
return Kind == k_Immediate; }
228 bool isMem()
const override {
return isMEMrr() || isMEMri(); }
229 bool isMEMrr()
const {
return Kind == k_MemoryReg; }
230 bool isMEMri()
const {
return Kind == k_MemoryImm; }
233 return (
Kind == k_Register &&
Reg.Kind == rk_IntReg);
236 bool isFloatReg()
const {
237 return (
Kind == k_Register &&
Reg.Kind == rk_FloatReg);
240 bool isFloatOrDoubleReg()
const {
241 return (
Kind == k_Register && (
Reg.Kind == rk_FloatReg
242 ||
Reg.Kind == rk_DoubleReg));
245 bool isCoprocReg()
const {
246 return (
Kind == k_Register &&
Reg.Kind == rk_CoprocReg);
254 unsigned getReg()
const override {
255 assert((
Kind == k_Register) &&
"Invalid access!");
259 const MCExpr *getImm()
const {
260 assert((
Kind == k_Immediate) &&
"Invalid access!");
264 unsigned getMemBase()
const {
265 assert((
Kind == k_MemoryReg ||
Kind == k_MemoryImm) &&
"Invalid access!");
269 unsigned getMemOffsetReg()
const {
270 assert((
Kind == k_MemoryReg) &&
"Invalid access!");
271 return Mem.OffsetReg;
274 const MCExpr *getMemOff()
const {
275 assert((
Kind == k_MemoryImm) &&
"Invalid access!");
280 SMLoc getStartLoc()
const override {
284 SMLoc getEndLoc()
const override {
290 case k_Token: OS <<
"Token: " <<
getToken() <<
"\n";
break;
291 case k_Register: OS <<
"Reg: #" <<
getReg() <<
"\n";
break;
292 case k_Immediate: OS <<
"Imm: " << getImm() <<
"\n";
break;
293 case k_MemoryReg: OS <<
"Mem: " << getMemBase() <<
"+"
294 << getMemOffsetReg() <<
"\n";
break;
295 case k_MemoryImm:
assert(getMemOff() !=
nullptr);
296 OS <<
"Mem: " << getMemBase()
297 <<
"+" << *getMemOff()
302 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
303 assert(N == 1 &&
"Invalid number of operands!");
307 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
308 assert(N == 1 &&
"Invalid number of operands!");
309 const MCExpr *Expr = getImm();
317 else if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
323 void addMEMrrOperands(
MCInst &Inst,
unsigned N)
const {
324 assert(N == 2 &&
"Invalid number of operands!");
328 assert(getMemOffsetReg() != 0 &&
"Invalid offset");
332 void addMEMriOperands(
MCInst &Inst,
unsigned N)
const {
333 assert(N == 2 &&
"Invalid number of operands!");
337 const MCExpr *Expr = getMemOff();
341 static std::unique_ptr<SparcOperand> CreateToken(
StringRef Str,
SMLoc S) {
342 auto Op = make_unique<SparcOperand>(k_Token);
343 Op->Tok.Data = Str.
data();
344 Op->Tok.Length = Str.
size();
350 static std::unique_ptr<SparcOperand> CreateReg(
unsigned RegNum,
unsigned Kind,
352 auto Op = make_unique<SparcOperand>(k_Register);
353 Op->Reg.RegNum = RegNum;
360 static std::unique_ptr<SparcOperand> CreateImm(
const MCExpr *Val,
SMLoc S,
362 auto Op = make_unique<SparcOperand>(k_Immediate);
369 static bool MorphToIntPairReg(SparcOperand &
Op) {
370 unsigned Reg = Op.getReg();
371 assert(Op.Reg.Kind == rk_IntReg);
372 unsigned regIdx = 32;
373 if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
374 regIdx = Reg - Sparc::G0;
375 else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
376 regIdx = Reg - Sparc::O0 + 8;
377 else if (Reg >= Sparc::L0 && Reg <= Sparc::L7)
378 regIdx = Reg - Sparc::L0 + 16;
379 else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
380 regIdx = Reg - Sparc::I0 + 24;
381 if (regIdx % 2 || regIdx > 31)
383 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
384 Op.Reg.Kind = rk_IntPairReg;
388 static bool MorphToDoubleReg(SparcOperand &Op) {
389 unsigned Reg = Op.getReg();
390 assert(Op.Reg.Kind == rk_FloatReg);
391 unsigned regIdx = Reg - Sparc::F0;
392 if (regIdx % 2 || regIdx > 31)
394 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
395 Op.Reg.Kind = rk_DoubleReg;
399 static bool MorphToQuadReg(SparcOperand &Op) {
400 unsigned Reg = Op.getReg();
402 switch (Op.Reg.Kind) {
405 regIdx = Reg - Sparc::F0;
406 if (regIdx % 4 || regIdx > 31)
408 Reg = QuadFPRegs[regIdx / 4];
411 regIdx = Reg - Sparc::D0;
412 if (regIdx % 2 || regIdx > 31)
414 Reg = QuadFPRegs[regIdx / 2];
418 Op.Reg.Kind = rk_QuadReg;
422 static bool MorphToCoprocPairReg(SparcOperand &Op) {
423 unsigned Reg = Op.getReg();
424 assert(Op.Reg.Kind == rk_CoprocReg);
425 unsigned regIdx = 32;
426 if (Reg >= Sparc::C0 && Reg <= Sparc::C31)
427 regIdx = Reg - Sparc::C0;
428 if (regIdx % 2 || regIdx > 31)
430 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
431 Op.Reg.Kind = rk_CoprocPairReg;
435 static std::unique_ptr<SparcOperand>
436 MorphToMEMrr(
unsigned Base, std::unique_ptr<SparcOperand> Op) {
437 unsigned offsetReg = Op->getReg();
438 Op->Kind = k_MemoryReg;
440 Op->Mem.OffsetReg = offsetReg;
441 Op->Mem.Off =
nullptr;
445 static std::unique_ptr<SparcOperand>
447 auto Op = make_unique<SparcOperand>(k_MemoryReg);
449 Op->Mem.OffsetReg = Sparc::G0;
450 Op->Mem.Off =
nullptr;
456 static std::unique_ptr<SparcOperand>
457 MorphToMEMri(
unsigned Base, std::unique_ptr<SparcOperand> Op) {
458 const MCExpr *Imm = Op->getImm();
459 Op->Kind = k_MemoryImm;
461 Op->Mem.OffsetReg = 0;
469 bool SparcAsmParser::expandSET(
MCInst &Inst,
SMLoc IDLoc,
478 int64_t RawImmValue = IsImm ? MCValOp.
getImm() : 0;
481 if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
483 "set: argument must be between -2147483648 and 4294967295");
488 int32_t ImmValue = RawImmValue;
492 bool IsEffectivelyImm13 =
493 IsImm && ((
is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
505 if (!IsEffectivelyImm13) {
526 if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
529 if (IsEffectivelyImm13)
543 bool SparcAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
547 bool MatchingInlineAsm) {
550 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
552 switch (MatchResult) {
553 case Match_Success: {
560 if (expandSET(Inst, IDLoc, Instructions))
565 for (
const MCInst &
I : Instructions) {
571 case Match_MissingFeature:
573 "instruction requires a CPU feature not currently enabled");
575 case Match_InvalidOperand: {
576 SMLoc ErrorLoc = IDLoc;
577 if (ErrorInfo != ~0ULL) {
578 if (ErrorInfo >= Operands.
size())
579 return Error(IDLoc,
"too few operands for instruction");
581 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
582 if (ErrorLoc ==
SMLoc())
586 return Error(ErrorLoc,
"invalid operand for instruction");
588 case Match_MnemonicFail:
589 return Error(IDLoc,
"invalid instruction mnemonic");
594 bool SparcAsmParser::
595 ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
597 const AsmToken &Tok = Parser.getTok();
604 unsigned regKind = SparcOperand::rk_None;
605 if (matchRegisterName(Tok, RegNo, regKind)) {
610 return Error(StartLoc,
"invalid register name");
621 Operands.
push_back(SparcOperand::CreateToken(Name, NameLoc));
630 SMLoc Loc = getLexer().getLoc();
631 return Error(Loc,
"unexpected token");
635 SMLoc Loc = getLexer().getLoc();
636 return Error(Loc,
"unexpected token");
642 Operands.
push_back(SparcOperand::CreateToken(
"+", Parser.getTok().getLoc()));
647 SMLoc Loc = getLexer().getLoc();
648 return Error(Loc,
"unexpected token");
653 SMLoc Loc = getLexer().getLoc();
654 return Error(Loc,
"unexpected token");
660 bool SparcAsmParser::
661 ParseDirective(
AsmToken DirectiveID)
665 if (IDVal ==
".byte")
666 return parseDirectiveWord(1, DirectiveID.
getLoc());
668 if (IDVal ==
".half")
669 return parseDirectiveWord(2, DirectiveID.
getLoc());
671 if (IDVal ==
".word")
672 return parseDirectiveWord(4, DirectiveID.
getLoc());
674 if (IDVal ==
".nword")
675 return parseDirectiveWord(
is64Bit() ? 8 : 4, DirectiveID.
getLoc());
677 if (
is64Bit() && IDVal ==
".xword")
678 return parseDirectiveWord(8, DirectiveID.
getLoc());
680 if (IDVal ==
".register") {
682 Parser.eatToEndOfStatement();
685 if (IDVal ==
".proc") {
688 Parser.eatToEndOfStatement();
696 bool SparcAsmParser:: parseDirectiveWord(
unsigned Size,
SMLoc L) {
700 if (getParser().parseExpression(Value))
703 getParser().getStreamer().EmitValue(Value, Size);
710 return Error(L,
"unexpected token in directive");
722 unsigned BaseReg = 0;
724 if (ParseRegister(BaseReg, S, E)) {
728 switch (getLexer().getKind()) {
734 Operands.
push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
744 std::unique_ptr<SparcOperand>
Offset;
750 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
751 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
769 Operands.
push_back(SparcOperand::CreateToken(
"[",
770 Parser.getTok().getLoc()));
773 if (Mnemonic ==
"cas" || Mnemonic ==
"casx" || Mnemonic ==
"casa") {
774 SMLoc S = Parser.getTok().getLoc();
779 unsigned RegNo, RegKind;
780 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
785 Operands.
push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
788 ResTy = parseMEMOperand(Operands);
797 Operands.
push_back(SparcOperand::CreateToken(
"]",
798 Parser.getTok().getLoc()));
803 std::unique_ptr<SparcOperand>
Op;
804 ResTy = parseSparcAsmOperand(Op,
false);
812 std::unique_ptr<SparcOperand>
Op;
814 ResTy = parseSparcAsmOperand(Op, (Mnemonic ==
"call"));
825 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
828 SMLoc S = Parser.getTok().getLoc();
833 switch (getLexer().getKind()) {
840 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
846 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
849 Op = SparcOperand::CreateToken(
"%psr", S);
852 Op = SparcOperand::CreateToken(
"%fsr", S);
855 Op = SparcOperand::CreateToken(
"%fq", S);
858 Op = SparcOperand::CreateToken(
"%csr", S);
861 Op = SparcOperand::CreateToken(
"%cq", S);
864 Op = SparcOperand::CreateToken(
"%wim", S);
867 Op = SparcOperand::CreateToken(
"%tbr", S);
871 Op = SparcOperand::CreateToken(
"%xcc", S);
873 Op = SparcOperand::CreateToken(
"%icc", S);
878 if (matchSparcAsmModifiers(EVal, E)) {
880 Op = SparcOperand::CreateImm(EVal, S, E);
888 if (!getParser().parseExpression(EVal, E))
889 Op = SparcOperand::CreateImm(EVal, S, E);
894 if (!getParser().parseIdentifier(Identifier)) {
896 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
900 if (isCall && getContext().getObjectFileInfo()->isPositionIndependent())
903 Op = SparcOperand::CreateImm(Res, S, E);
912 SparcAsmParser::parseBranchModifiers(
OperandVector &Operands) {
922 StringRef modName = Parser.getTok().getString();
923 if (modName ==
"a" || modName ==
"pn" || modName ==
"pt") {
924 Operands.
push_back(SparcOperand::CreateToken(modName,
925 Parser.getTok().getLoc()));
932 bool SparcAsmParser::matchRegisterName(
const AsmToken &Tok,
938 RegKind = SparcOperand::rk_None;
945 RegKind = SparcOperand::rk_IntReg;
951 RegKind = SparcOperand::rk_IntReg;
957 RegKind = SparcOperand::rk_Special;
963 && intVal > 0 && intVal < 32) {
964 RegNo = ASRRegs[intVal];
965 RegKind = SparcOperand::rk_Special;
970 if (name.
equals(
"fprs")) {
972 RegKind = SparcOperand::rk_Special;
978 RegKind = SparcOperand::rk_Special;
984 RegKind = SparcOperand::rk_Special;
990 RegKind = SparcOperand::rk_Special;
996 RegKind = SparcOperand::rk_Special;
1000 if (name.
equals(
"csr")) {
1001 RegNo = Sparc::CPSR;
1002 RegKind = SparcOperand::rk_Special;
1008 RegKind = SparcOperand::rk_Special;
1012 if (name.
equals(
"wim")) {
1014 RegKind = SparcOperand::rk_Special;
1018 if (name.
equals(
"tbr")) {
1020 RegKind = SparcOperand::rk_Special;
1024 if (name.
equals(
"xcc")) {
1027 RegKind = SparcOperand::rk_Special;
1036 RegNo = Sparc::FCC0 + intVal;
1037 RegKind = SparcOperand::rk_Special;
1045 RegNo = IntRegs[intVal];
1046 RegKind = SparcOperand::rk_IntReg;
1053 RegNo = IntRegs[8 + intVal];
1054 RegKind = SparcOperand::rk_IntReg;
1060 RegNo = IntRegs[16 + intVal];
1061 RegKind = SparcOperand::rk_IntReg;
1067 RegNo = IntRegs[24 + intVal];
1068 RegKind = SparcOperand::rk_IntReg;
1074 RegNo = FloatRegs[intVal];
1075 RegKind = SparcOperand::rk_FloatReg;
1081 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
1083 RegNo = DoubleRegs[intVal/2];
1084 RegKind = SparcOperand::rk_DoubleReg;
1091 RegNo = IntRegs[intVal];
1092 RegKind = SparcOperand::rk_IntReg;
1100 RegNo = CoprocRegs[intVal];
1101 RegKind = SparcOperand::rk_CoprocReg;
1105 if (name.
equals(
"tpc")) {
1107 RegKind = SparcOperand::rk_Special;
1110 if (name.
equals(
"tnpc")) {
1111 RegNo = Sparc::TNPC;
1112 RegKind = SparcOperand::rk_Special;
1115 if (name.
equals(
"tstate")) {
1116 RegNo = Sparc::TSTATE;
1117 RegKind = SparcOperand::rk_Special;
1122 RegKind = SparcOperand::rk_Special;
1125 if (name.
equals(
"tick")) {
1126 RegNo = Sparc::TICK;
1127 RegKind = SparcOperand::rk_Special;
1130 if (name.
equals(
"tba")) {
1132 RegKind = SparcOperand::rk_Special;
1135 if (name.
equals(
"pstate")) {
1136 RegNo = Sparc::PSTATE;
1137 RegKind = SparcOperand::rk_Special;
1142 RegKind = SparcOperand::rk_Special;
1145 if (name.
equals(
"pil")) {
1147 RegKind = SparcOperand::rk_Special;
1150 if (name.
equals(
"cwp")) {
1152 RegKind = SparcOperand::rk_Special;
1155 if (name.
equals(
"cansave")) {
1156 RegNo = Sparc::CANSAVE;
1157 RegKind = SparcOperand::rk_Special;
1160 if (name.
equals(
"canrestore")) {
1161 RegNo = Sparc::CANRESTORE;
1162 RegKind = SparcOperand::rk_Special;
1165 if (name.
equals(
"cleanwin")) {
1166 RegNo = Sparc::CLEANWIN;
1167 RegKind = SparcOperand::rk_Special;
1170 if (name.
equals(
"otherwin")) {
1171 RegNo = Sparc::OTHERWIN;
1172 RegKind = SparcOperand::rk_Special;
1175 if (name.
equals(
"wstate")) {
1176 RegNo = Sparc::WSTATE;
1177 RegKind = SparcOperand::rk_Special;
1189 if (
const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1221 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1238 bool SparcAsmParser::matchSparcAsmModifiers(
const MCExpr *&EVal,
1258 if (Parser.parseParenExpression(subExpr, EndLoc))
1261 EVal = adjustPICRelocation(VK, subExpr);
1271 #define GET_REGISTER_MATCHER
1272 #define GET_MATCHER_IMPLEMENTATION
1273 #include "SparcGenAsmMatcher.inc"
1277 SparcOperand &Op = (SparcOperand &)GOp;
1278 if (Op.isFloatOrDoubleReg()) {
1282 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1286 if (SparcOperand::MorphToQuadReg(Op))
1291 if (Op.isIntReg() && Kind == MCK_IntPair) {
1292 if (SparcOperand::MorphToIntPairReg(Op))
1295 if (Op.isCoprocReg() && Kind == MCK_CoprocPair) {
1296 if (SparcOperand::MorphToCoprocPairReg(Op))
1299 return Match_InvalidOperand;
static bool isReg(const MCInst &MI, unsigned OpNo)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
void push_back(const T &Elt)
const MCSymbol & getSymbol() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Generic assembler parser interface, for use by target specific assembly parsers.
static MCOperand createExpr(const MCExpr *Val)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID)
static MCOperand createReg(unsigned Reg)
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Reg
All possible values of the reg field in the ModR/M byte.
Target independent representation for an assembler token.
Represent a reference to a symbol from inside an expression.
Windows NT (Windows on ARM)
static bool isMem(const MachineInstr &MI, unsigned Op)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
Target & getTheSparcTarget()
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Instances of this class represent a single low-level machine instruction.
void LLVMInitializeSparcAsmParser()
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MCExpr * getExpr() const
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Streaming machine code generation interface.
static bool is64Bit(const char *name)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Interface to description of machine instruction set.
Target & getTheSparcelTarget()
static VariantKind parseVariantKind(StringRef name)
static bool hasGOTReference(const MCExpr *Expr)
Binary assembler expressions.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setOpcode(unsigned Op)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool is(TokenKind K) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned getOpcode() const
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Target & getTheSparcV9Target()
static SMLoc getFromPointer(const char *Ptr)
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
StringRef getName() const
getName - Get the symbol name.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
static const SparcMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
const FeatureBitset Features
This class implements an extremely fast bulk output stream that can only output to a stream...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
bool isIntReg(unsigned Reg)
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
Target specific expression.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
Represents a location in source code.
Instances of this class represent operands of the MCInst class.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
static MCOperand createImm(int64_t Val)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const