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LLVM
4.0.0
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#include <AMDGPUInstrInfo.h>
Public Member Functions | |
| AMDGPUInstrInfo (const AMDGPUSubtarget &st) | |
| bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override |
| int | pseudoToMCOpcode (int Opcode) const |
| Return a target-specific opcode if Opcode is a pseudo instruction. More... | |
| int | getMaskedMIMGOp (uint16_t Opcode, unsigned Channels) const |
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels. More... | |
Definition at line 33 of file AMDGPUInstrInfo.h.
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explicit |
Definition at line 32 of file AMDGPUInstrInfo.cpp.
| int AMDGPUInstrInfo::getMaskedMIMGOp | ( | uint16_t | Opcode, |
| unsigned | Channels | ||
| ) | const |
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Channels.
Definition at line 57 of file AMDGPUInstrInfo.cpp.
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection().
| int AMDGPUInstrInfo::pseudoToMCOpcode | ( | int | Opcode | ) | const |
Return a target-specific opcode if Opcode is a pseudo instruction.
Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.
Definition at line 102 of file AMDGPUInstrInfo.cpp.
References llvm::AMDGPU::getMCOpcode(), and subtargetEncodingFamily().
Referenced by llvm::SIInstrInfo::commuteOpcode(), llvm::SIInstrInfo::getMCOpcodeFromPseudo(), llvm::SIInstrInfo::hasVALU32BitEncoding(), and llvm::AMDGPUMCInstLower::lower().
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override |
Definition at line 45 of file AMDGPUInstrInfo.cpp.
References assert().
1.8.6