LLVM  4.0.0
R600OptimizeVectorRegisters.cpp
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1 //===--------------------- R600MergeVectorRegisters.cpp -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// This pass merges inputs of swizzeable instructions into vector sharing
12 /// common data and/or have enough undef subreg using swizzle abilities.
13 ///
14 /// For instance let's consider the following pseudo code :
15 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
16 /// ...
17 /// vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3
18 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3
19 ///
20 /// is turned into :
21 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
22 /// ...
23 /// vreg7<def> = INSERT_SUBREG vreg4, sub3
24 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3
25 ///
26 /// This allow regalloc to reduce register pressure for vector registers and
27 /// to reduce MOV count.
28 //===----------------------------------------------------------------------===//
29 
30 #include "AMDGPU.h"
31 #include "AMDGPUSubtarget.h"
32 #include "R600Defines.h"
33 #include "R600InstrInfo.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/ADT/StringRef.h"
46 #include "llvm/IR/DebugLoc.h"
48 #include "llvm/Support/Debug.h"
51 #include <cassert>
52 #include <utility>
53 #include <vector>
54 
55 using namespace llvm;
56 
57 #define DEBUG_TYPE "vec-merger"
58 
59 static bool
62  E = MRI.def_instr_end(); It != E; ++It) {
63  return (*It).isImplicitDef();
64  }
65  if (MRI.isReserved(Reg)) {
66  return false;
67  }
68  llvm_unreachable("Reg without a def");
69  return false;
70 }
71 
72 namespace {
73 
74 class RegSeqInfo {
75 public:
76  MachineInstr *Instr;
78  std::vector<unsigned> UndefReg;
79 
80  RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
81  assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE);
82  for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
83  MachineOperand &MO = Instr->getOperand(i);
84  unsigned Chan = Instr->getOperand(i + 1).getImm();
85  if (isImplicitlyDef(MRI, MO.getReg()))
86  UndefReg.push_back(Chan);
87  else
88  RegToChan[MO.getReg()] = Chan;
89  }
90  }
91 
92  RegSeqInfo() = default;
93 
94  bool operator==(const RegSeqInfo &RSI) const {
95  return RSI.Instr == Instr;
96  }
97 };
98 
99 class R600VectorRegMerger : public MachineFunctionPass {
100 private:
102  const R600InstrInfo *TII;
103 
104  bool canSwizzle(const MachineInstr &MI) const;
105  bool areAllUsesSwizzeable(unsigned Reg) const;
106  void SwizzleInput(MachineInstr &,
107  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
108  bool tryMergeVector(const RegSeqInfo *Untouched, RegSeqInfo *ToMerge,
109  std::vector<std::pair<unsigned, unsigned>> &Remap) const;
110  bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
111  std::vector<std::pair<unsigned, unsigned>> &RemapChan);
112  bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
113  std::vector<std::pair<unsigned, unsigned>> &RemapChan);
114  MachineInstr *RebuildVector(RegSeqInfo *MI, const RegSeqInfo *BaseVec,
115  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const;
116  void RemoveMI(MachineInstr *);
117  void trackRSI(const RegSeqInfo &RSI);
118 
119  typedef DenseMap<unsigned, std::vector<MachineInstr *>> InstructionSetMap;
121  InstructionSetMap PreviousRegSeqByReg;
122  InstructionSetMap PreviousRegSeqByUndefCount;
123 
124 public:
125  static char ID;
126 
127  R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
128  TII(nullptr) { }
129 
130  void getAnalysisUsage(AnalysisUsage &AU) const override {
131  AU.setPreservesCFG();
137  }
138 
139  StringRef getPassName() const override {
140  return "R600 Vector Registers Merge Pass";
141  }
142 
143  bool runOnMachineFunction(MachineFunction &Fn) override;
144 };
145 
146 } // end anonymous namespace.
147 
148 char R600VectorRegMerger::ID = 0;
149 
150 bool R600VectorRegMerger::canSwizzle(const MachineInstr &MI)
151  const {
152  if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
153  return true;
154  switch (MI.getOpcode()) {
155  case AMDGPU::R600_ExportSwz:
156  case AMDGPU::EG_ExportSwz:
157  return true;
158  default:
159  return false;
160  }
161 }
162 
163 bool R600VectorRegMerger::tryMergeVector(const RegSeqInfo *Untouched,
164  RegSeqInfo *ToMerge, std::vector< std::pair<unsigned, unsigned>> &Remap)
165  const {
166  unsigned CurrentUndexIdx = 0;
167  for (DenseMap<unsigned, unsigned>::iterator It = ToMerge->RegToChan.begin(),
168  E = ToMerge->RegToChan.end(); It != E; ++It) {
170  Untouched->RegToChan.find((*It).first);
171  if (PosInUntouched != Untouched->RegToChan.end()) {
172  Remap.push_back(std::pair<unsigned, unsigned>
173  ((*It).second, (*PosInUntouched).second));
174  continue;
175  }
176  if (CurrentUndexIdx >= Untouched->UndefReg.size())
177  return false;
178  Remap.push_back(std::pair<unsigned, unsigned>
179  ((*It).second, Untouched->UndefReg[CurrentUndexIdx++]));
180  }
181 
182  return true;
183 }
184 
185 static
187  const std::vector<std::pair<unsigned, unsigned>> &RemapChan,
188  unsigned Chan) {
189  for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
190  if (RemapChan[j].first == Chan)
191  return RemapChan[j].second;
192  }
193  llvm_unreachable("Chan wasn't reassigned");
194 }
195 
196 MachineInstr *R600VectorRegMerger::RebuildVector(
197  RegSeqInfo *RSI, const RegSeqInfo *BaseRSI,
198  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
199  unsigned Reg = RSI->Instr->getOperand(0).getReg();
200  MachineBasicBlock::iterator Pos = RSI->Instr;
201  MachineBasicBlock &MBB = *Pos->getParent();
202  DebugLoc DL = Pos->getDebugLoc();
203 
204  unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg();
205  DenseMap<unsigned, unsigned> UpdatedRegToChan = BaseRSI->RegToChan;
206  std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
207  for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
208  E = RSI->RegToChan.end(); It != E; ++It) {
209  unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
210  unsigned SubReg = (*It).first;
211  unsigned Swizzle = (*It).second;
212  unsigned Chan = getReassignedChan(RemapChan, Swizzle);
213 
214  MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::INSERT_SUBREG),
215  DstReg)
216  .addReg(SrcVec)
217  .addReg(SubReg)
218  .addImm(Chan);
219  UpdatedRegToChan[SubReg] = Chan;
220  std::vector<unsigned>::iterator ChanPos = llvm::find(UpdatedUndef, Chan);
221  if (ChanPos != UpdatedUndef.end())
222  UpdatedUndef.erase(ChanPos);
223  assert(!is_contained(UpdatedUndef, Chan) &&
224  "UpdatedUndef shouldn't contain Chan more than once!");
225  DEBUG(dbgs() << " ->"; Tmp->dump(););
226  (void)Tmp;
227  SrcVec = DstReg;
228  }
229  MachineInstr *NewMI =
230  BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg).addReg(SrcVec);
231  DEBUG(dbgs() << " ->"; NewMI->dump(););
232 
233  DEBUG(dbgs() << " Updating Swizzle:\n");
235  E = MRI->use_instr_end(); It != E; ++It) {
236  DEBUG(dbgs() << " ";(*It).dump(); dbgs() << " ->");
237  SwizzleInput(*It, RemapChan);
238  DEBUG((*It).dump());
239  }
240  RSI->Instr->eraseFromParent();
241 
242  // Update RSI
243  RSI->Instr = NewMI;
244  RSI->RegToChan = UpdatedRegToChan;
245  RSI->UndefReg = UpdatedUndef;
246 
247  return NewMI;
248 }
249 
250 void R600VectorRegMerger::RemoveMI(MachineInstr *MI) {
251  for (InstructionSetMap::iterator It = PreviousRegSeqByReg.begin(),
252  E = PreviousRegSeqByReg.end(); It != E; ++It) {
253  std::vector<MachineInstr *> &MIs = (*It).second;
254  MIs.erase(llvm::find(MIs, MI), MIs.end());
255  }
256  for (InstructionSetMap::iterator It = PreviousRegSeqByUndefCount.begin(),
257  E = PreviousRegSeqByUndefCount.end(); It != E; ++It) {
258  std::vector<MachineInstr *> &MIs = (*It).second;
259  MIs.erase(llvm::find(MIs, MI), MIs.end());
260  }
261 }
262 
263 void R600VectorRegMerger::SwizzleInput(MachineInstr &MI,
264  const std::vector<std::pair<unsigned, unsigned>> &RemapChan) const {
265  unsigned Offset;
266  if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
267  Offset = 2;
268  else
269  Offset = 3;
270  for (unsigned i = 0; i < 4; i++) {
271  unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
272  for (unsigned j = 0, e = RemapChan.size(); j < e; j++) {
273  if (RemapChan[j].first == Swizzle) {
274  MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
275  break;
276  }
277  }
278  }
279 }
280 
281 bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const {
283  E = MRI->use_instr_end(); It != E; ++It) {
284  if (!canSwizzle(*It))
285  return false;
286  }
287  return true;
288 }
289 
290 bool R600VectorRegMerger::tryMergeUsingCommonSlot(RegSeqInfo &RSI,
291  RegSeqInfo &CompatibleRSI,
292  std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
293  for (MachineInstr::mop_iterator MOp = RSI.Instr->operands_begin(),
294  MOE = RSI.Instr->operands_end(); MOp != MOE; ++MOp) {
295  if (!MOp->isReg())
296  continue;
297  if (PreviousRegSeqByReg[MOp->getReg()].empty())
298  continue;
299  for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) {
300  CompatibleRSI = PreviousRegSeq[MI];
301  if (RSI == CompatibleRSI)
302  continue;
303  if (tryMergeVector(&CompatibleRSI, &RSI, RemapChan))
304  return true;
305  }
306  }
307  return false;
308 }
309 
310 bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
311  RegSeqInfo &CompatibleRSI,
312  std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
313  unsigned NeededUndefs = 4 - RSI.UndefReg.size();
314  if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
315  return false;
316  std::vector<MachineInstr *> &MIs =
317  PreviousRegSeqByUndefCount[NeededUndefs];
318  CompatibleRSI = PreviousRegSeq[MIs.back()];
319  tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
320  return true;
321 }
322 
323 void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
325  It = RSI.RegToChan.begin(), E = RSI.RegToChan.end(); It != E; ++It) {
326  PreviousRegSeqByReg[(*It).first].push_back(RSI.Instr);
327  }
328  PreviousRegSeqByUndefCount[RSI.UndefReg.size()].push_back(RSI.Instr);
329  PreviousRegSeq[RSI.Instr] = RSI;
330 }
331 
332 bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
333  if (skipFunction(*Fn.getFunction()))
334  return false;
335 
337  TII = ST.getInstrInfo();
338  MRI = &Fn.getRegInfo();
339 
340  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
341  MBB != MBBe; ++MBB) {
342  MachineBasicBlock *MB = &*MBB;
343  PreviousRegSeq.clear();
344  PreviousRegSeqByReg.clear();
345  PreviousRegSeqByUndefCount.clear();
346 
347  for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
348  MII != MIIE; ++MII) {
349  MachineInstr &MI = *MII;
350  if (MI.getOpcode() != AMDGPU::REG_SEQUENCE) {
351  if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
352  unsigned Reg = MI.getOperand(1).getReg();
354  It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end();
355  It != E; ++It) {
356  RemoveMI(&(*It));
357  }
358  }
359  continue;
360  }
361 
362  RegSeqInfo RSI(*MRI, &MI);
363 
364  // All uses of MI are swizzeable ?
365  unsigned Reg = MI.getOperand(0).getReg();
366  if (!areAllUsesSwizzeable(Reg))
367  continue;
368 
369  DEBUG({
370  dbgs() << "Trying to optimize ";
371  MI.dump();
372  });
373 
374  RegSeqInfo CandidateRSI;
375  std::vector<std::pair<unsigned, unsigned>> RemapChan;
376  DEBUG(dbgs() << "Using common slots...\n";);
377  if (tryMergeUsingCommonSlot(RSI, CandidateRSI, RemapChan)) {
378  // Remove CandidateRSI mapping
379  RemoveMI(CandidateRSI.Instr);
380  MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
381  trackRSI(RSI);
382  continue;
383  }
384  DEBUG(dbgs() << "Using free slots...\n";);
385  RemapChan.clear();
386  if (tryMergeUsingFreeSlot(RSI, CandidateRSI, RemapChan)) {
387  RemoveMI(CandidateRSI.Instr);
388  MII = RebuildVector(&RSI, &CandidateRSI, RemapChan);
389  trackRSI(RSI);
390  continue;
391  }
392  //Failed to merge
393  trackRSI(RSI);
394  }
395  }
396  return false;
397 }
398 
400  return new R600VectorRegMerger(tm);
401 }
static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
AMDGPU specific subclass of TargetSubtarget.
size_t i
Interface definition for R600InstrInfo.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
AnalysisUsage & addRequired()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
use_instr_iterator use_instr_begin(unsigned RegNo) const
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
FunctionPass * createR600VectorRegMerger(TargetMachine &tm)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineBasicBlock * MBB
static def_instr_iterator def_instr_end()
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Represent the analysis usage information of a pass.
uint32_t Offset
const R600InstrInfo * getInstrInfo() const override
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
static unsigned getReassignedChan(const std::vector< std::pair< unsigned, unsigned >> &RemapChan, unsigned Chan)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:757
MachineOperand class - Representation of each machine instruction operand.
void dump(const TargetInstrInfo *TII=nullptr) const
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
def_instr_iterator def_instr_begin(unsigned RegNo) const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static use_instr_iterator use_instr_end()
#define DEBUG(X)
Definition: Debug.h:100
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1722
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:783