LLVM  4.0.0
VirtRegMap.cpp
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1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the VirtRegMap class.
11 //
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
15 // code as necessary.
16 //
17 //===----------------------------------------------------------------------===//
18 
20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
38 #include <algorithm>
39 using namespace llvm;
40 
41 #define DEBUG_TYPE "regalloc"
42 
43 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
44 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
45 
46 //===----------------------------------------------------------------------===//
47 // VirtRegMap implementation
48 //===----------------------------------------------------------------------===//
49 
50 char VirtRegMap::ID = 0;
51 
52 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
53 
54 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
55  MRI = &mf.getRegInfo();
56  TII = mf.getSubtarget().getInstrInfo();
57  TRI = mf.getSubtarget().getRegisterInfo();
58  MF = &mf;
59 
60  Virt2PhysMap.clear();
61  Virt2StackSlotMap.clear();
62  Virt2SplitMap.clear();
63 
64  grow();
65  return false;
66 }
67 
69  unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
70  Virt2PhysMap.resize(NumRegs);
71  Virt2StackSlotMap.resize(NumRegs);
72  Virt2SplitMap.resize(NumRegs);
73 }
74 
75 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
76  int SS = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
77  RC->getAlignment());
78  ++NumSpillSlots;
79  return SS;
80 }
81 
82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
83  unsigned Hint = MRI->getSimpleHint(VirtReg);
84  if (!Hint)
85  return false;
87  Hint = getPhys(Hint);
88  return getPhys(VirtReg) == Hint;
89 }
90 
91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
92  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
94  return true;
96  return hasPhys(Hint.second);
97  return false;
98 }
99 
100 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
102  assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
103  "attempt to assign stack slot to already spilled register");
104  const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
105  return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
106 }
107 
108 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
110  assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
111  "attempt to assign stack slot to already spilled register");
112  assert((SS >= 0 ||
113  (SS >= MF->getFrameInfo().getObjectIndexBegin())) &&
114  "illegal fixed frame index");
115  Virt2StackSlotMap[virtReg] = SS;
116 }
117 
118 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
119  OS << "********** REGISTER MAP **********\n";
120  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
122  if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
123  OS << '[' << PrintReg(Reg, TRI) << " -> "
124  << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
125  << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
126  }
127  }
128 
129  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
131  if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
132  OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
133  << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
134  }
135  }
136  OS << '\n';
137 }
138 
139 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
141  print(dbgs());
142 }
143 #endif
144 
145 //===----------------------------------------------------------------------===//
146 // VirtRegRewriter
147 //===----------------------------------------------------------------------===//
148 //
149 // The VirtRegRewriter is the last of the register allocator passes.
150 // It rewrites virtual registers to physical registers as specified in the
151 // VirtRegMap analysis. It also updates live-in information on basic blocks
152 // according to LiveIntervals.
153 //
154 namespace {
155 class VirtRegRewriter : public MachineFunctionPass {
156  MachineFunction *MF;
157  const TargetMachine *TM;
158  const TargetRegisterInfo *TRI;
159  const TargetInstrInfo *TII;
161  SlotIndexes *Indexes;
162  LiveIntervals *LIS;
163  VirtRegMap *VRM;
164 
165  void rewrite();
166  void addMBBLiveIns();
167  bool readsUndefSubreg(const MachineOperand &MO) const;
168  void addLiveInsForSubRanges(const LiveInterval &LI, unsigned PhysReg) const;
169  void handleIdentityCopy(MachineInstr &MI) const;
170 
171 public:
172  static char ID;
173  VirtRegRewriter() : MachineFunctionPass(ID) {}
174 
175  void getAnalysisUsage(AnalysisUsage &AU) const override;
176 
177  bool runOnMachineFunction(MachineFunction&) override;
178  MachineFunctionProperties getSetProperties() const override {
181  }
182 };
183 } // end anonymous namespace
184 
186 
187 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
188  "Virtual Register Rewriter", false, false)
195  "Virtual Register Rewriter", false, false)
196 
197 char VirtRegRewriter::ID = 0;
198 
199 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
200  AU.setPreservesCFG();
201  AU.addRequired<LiveIntervals>();
202  AU.addRequired<SlotIndexes>();
203  AU.addPreserved<SlotIndexes>();
204  AU.addRequired<LiveDebugVariables>();
205  AU.addRequired<LiveStacks>();
206  AU.addPreserved<LiveStacks>();
207  AU.addRequired<VirtRegMap>();
209 }
210 
211 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
212  MF = &fn;
213  TM = &MF->getTarget();
214  TRI = MF->getSubtarget().getRegisterInfo();
215  TII = MF->getSubtarget().getInstrInfo();
216  MRI = &MF->getRegInfo();
217  Indexes = &getAnalysis<SlotIndexes>();
218  LIS = &getAnalysis<LiveIntervals>();
219  VRM = &getAnalysis<VirtRegMap>();
220  DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
221  << "********** Function: "
222  << MF->getName() << '\n');
223  DEBUG(VRM->dump());
224 
225  // Add kill flags while we still have virtual registers.
226  LIS->addKillFlags(VRM);
227 
228  // Live-in lists on basic blocks are required for physregs.
229  addMBBLiveIns();
230 
231  // Rewrite virtual registers.
232  rewrite();
233 
234  // Write out new DBG_VALUE instructions.
235  getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
236 
237  // All machine operands and other references to virtual registers have been
238  // replaced. Remove the virtual registers and release all the transient data.
239  VRM->clearAllVirt();
240  MRI->clearVirtRegs();
241  return true;
242 }
243 
244 void VirtRegRewriter::addLiveInsForSubRanges(const LiveInterval &LI,
245  unsigned PhysReg) const {
246  assert(!LI.empty());
247  assert(LI.hasSubRanges());
248 
249  typedef std::pair<const LiveInterval::SubRange *,
250  LiveInterval::const_iterator> SubRangeIteratorPair;
252  SlotIndex First;
253  SlotIndex Last;
254  for (const LiveInterval::SubRange &SR : LI.subranges()) {
255  SubRanges.push_back(std::make_pair(&SR, SR.begin()));
256  if (!First.isValid() || SR.segments.front().start < First)
257  First = SR.segments.front().start;
258  if (!Last.isValid() || SR.segments.back().end > Last)
259  Last = SR.segments.back().end;
260  }
261 
262  // Check all mbb start positions between First and Last while
263  // simulatenously advancing an iterator for each subrange.
264  for (SlotIndexes::MBBIndexIterator MBBI = Indexes->findMBBIndex(First);
265  MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
266  SlotIndex MBBBegin = MBBI->first;
267  // Advance all subrange iterators so that their end position is just
268  // behind MBBBegin (or the iterator is at the end).
269  LaneBitmask LaneMask;
270  for (auto &RangeIterPair : SubRanges) {
271  const LiveInterval::SubRange *SR = RangeIterPair.first;
272  LiveInterval::const_iterator &SRI = RangeIterPair.second;
273  while (SRI != SR->end() && SRI->end <= MBBBegin)
274  ++SRI;
275  if (SRI == SR->end())
276  continue;
277  if (SRI->start <= MBBBegin)
278  LaneMask |= SR->LaneMask;
279  }
280  if (LaneMask.none())
281  continue;
282  MachineBasicBlock *MBB = MBBI->second;
283  MBB->addLiveIn(PhysReg, LaneMask);
284  }
285 }
286 
287 // Compute MBB live-in lists from virtual register live ranges and their
288 // assignments.
289 void VirtRegRewriter::addMBBLiveIns() {
290  for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
291  unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
292  if (MRI->reg_nodbg_empty(VirtReg))
293  continue;
294  LiveInterval &LI = LIS->getInterval(VirtReg);
295  if (LI.empty() || LIS->intervalIsInOneMBB(LI))
296  continue;
297  // This is a virtual register that is live across basic blocks. Its
298  // assigned PhysReg must be marked as live-in to those blocks.
299  unsigned PhysReg = VRM->getPhys(VirtReg);
300  assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
301 
302  if (LI.hasSubRanges()) {
303  addLiveInsForSubRanges(LI, PhysReg);
304  } else {
305  // Go over MBB begin positions and see if we have segments covering them.
306  // The following works because segments and the MBBIndex list are both
307  // sorted by slot indexes.
308  SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin();
309  for (const auto &Seg : LI) {
310  I = Indexes->advanceMBBIndex(I, Seg.start);
311  for (; I != Indexes->MBBIndexEnd() && I->first < Seg.end; ++I) {
312  MachineBasicBlock *MBB = I->second;
313  MBB->addLiveIn(PhysReg);
314  }
315  }
316  }
317  }
318 
319  // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
320  // each MBB's LiveIns set before calling addLiveIn on them.
321  for (MachineBasicBlock &MBB : *MF)
323 }
324 
325 /// Returns true if the given machine operand \p MO only reads undefined lanes.
326 /// The function only works for use operands with a subregister set.
327 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
328  // Shortcut if the operand is already marked undef.
329  if (MO.isUndef())
330  return true;
331 
332  unsigned Reg = MO.getReg();
333  const LiveInterval &LI = LIS->getInterval(Reg);
334  const MachineInstr &MI = *MO.getParent();
335  SlotIndex BaseIndex = LIS->getInstructionIndex(MI);
336  // This code is only meant to handle reading undefined subregisters which
337  // we couldn't properly detect before.
338  assert(LI.liveAt(BaseIndex) &&
339  "Reads of completely dead register should be marked undef already");
340  unsigned SubRegIdx = MO.getSubReg();
341  assert(SubRegIdx != 0 && LI.hasSubRanges());
342  LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
343  // See if any of the relevant subregister liveranges is defined at this point.
344  for (const LiveInterval::SubRange &SR : LI.subranges()) {
345  if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
346  return false;
347  }
348  return true;
349 }
350 
351 void VirtRegRewriter::handleIdentityCopy(MachineInstr &MI) const {
352  if (!MI.isIdentityCopy())
353  return;
354  DEBUG(dbgs() << "Identity copy: " << MI);
355  ++NumIdCopies;
356 
357  // Copies like:
358  // %R0 = COPY %R0<undef>
359  // %AL = COPY %AL, %EAX<imp-def>
360  // give us additional liveness information: The target (super-)register
361  // must not be valid before this point. Replace the COPY with a KILL
362  // instruction to maintain this information.
363  if (MI.getOperand(0).isUndef() || MI.getNumOperands() > 2) {
364  MI.setDesc(TII->get(TargetOpcode::KILL));
365  DEBUG(dbgs() << " replace by: " << MI);
366  return;
367  }
368 
369  if (Indexes)
370  Indexes->removeMachineInstrFromMaps(MI);
371  MI.eraseFromParent();
372  DEBUG(dbgs() << " deleted.\n");
373 }
374 
375 void VirtRegRewriter::rewrite() {
376  bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
377  SmallVector<unsigned, 8> SuperDeads;
378  SmallVector<unsigned, 8> SuperDefs;
379  SmallVector<unsigned, 8> SuperKills;
380 
381  for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
382  MBBI != MBBE; ++MBBI) {
383  DEBUG(MBBI->print(dbgs(), Indexes));
385  MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
386  MachineInstr *MI = &*MII;
387  ++MII;
388 
390  MOE = MI->operands_end(); MOI != MOE; ++MOI) {
391  MachineOperand &MO = *MOI;
392 
393  // Make sure MRI knows about registers clobbered by regmasks.
394  if (MO.isRegMask())
395  MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
396 
398  continue;
399  unsigned VirtReg = MO.getReg();
400  unsigned PhysReg = VRM->getPhys(VirtReg);
401  assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
402  "Instruction uses unmapped VirtReg");
403  assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
404 
405  // Preserve semantics of sub-register operands.
406  unsigned SubReg = MO.getSubReg();
407  if (SubReg != 0) {
408  if (NoSubRegLiveness) {
409  // A virtual register kill refers to the whole register, so we may
410  // have to add <imp-use,kill> operands for the super-register. A
411  // partial redef always kills and redefines the super-register.
412  if (MO.readsReg() && (MO.isDef() || MO.isKill()))
413  SuperKills.push_back(PhysReg);
414 
415  if (MO.isDef()) {
416  // Also add implicit defs for the super-register.
417  if (MO.isDead())
418  SuperDeads.push_back(PhysReg);
419  else
420  SuperDefs.push_back(PhysReg);
421  }
422  } else {
423  if (MO.isUse()) {
424  if (readsUndefSubreg(MO))
425  // We need to add an <undef> flag if the subregister is
426  // completely undefined (and we are not adding super-register
427  // defs).
428  MO.setIsUndef(true);
429  } else if (!MO.isDead()) {
430  assert(MO.isDef());
431  }
432  }
433 
434  // The <def,undef> flag only makes sense for sub-register defs, and
435  // we are substituting a full physreg. An <imp-use,kill> operand
436  // from the SuperKills list will represent the partial read of the
437  // super-register.
438  if (MO.isDef())
439  MO.setIsUndef(false);
440 
441  // PhysReg operands cannot have subregister indexes.
442  PhysReg = TRI->getSubReg(PhysReg, SubReg);
443  assert(PhysReg && "Invalid SubReg for physical register");
444  MO.setSubReg(0);
445  }
446  // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
447  // we need the inlining here.
448  MO.setReg(PhysReg);
449  }
450 
451  // Add any missing super-register kills after rewriting the whole
452  // instruction.
453  while (!SuperKills.empty())
454  MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
455 
456  while (!SuperDeads.empty())
457  MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
458 
459  while (!SuperDefs.empty())
460  MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
461 
462  DEBUG(dbgs() << "> " << *MI);
463 
464  // We can remove identity copies right now.
465  handleIdentityCopy(*MI);
466  }
467  }
468 }
bool hasPhys(unsigned virtReg) const
returns true if the specified virtual register is mapped to a physical register
Definition: VirtRegMap.h:92
mop_iterator operands_end()
Definition: MachineInstr.h:296
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
STATISTIC(NumFunctions,"Total number of functions")
size_t i
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:450
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
void setIsUndef(bool Val=true)
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Definition: VirtRegMap.cpp:118
A live range for subregisters.
Definition: LiveInterval.h:632
bool empty() const
Definition: LiveInterval.h:357
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
iterator end()
Definition: LiveInterval.h:206
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:710
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
unsigned SubReg
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
bool isKill() const
int getObjectIndexBegin() const
Return the minimum frame object index.
SlotIndexes pass.
Definition: SlotIndexes.h:323
MachineBasicBlock * MBB
void dump() const
Definition: VirtRegMap.cpp:140
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
TargetInstrInfo - Interface to description of machine instruction set.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
bool isValid() const
Returns true if this is a valid index.
Definition: SlotIndexes.h:144
unsigned const MachineRegisterInfo * MRI
constexpr bool none() const
Definition: LaneBitmask.h:50
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
bool hasPreferredPhys(unsigned VirtReg)
returns true if VirtReg is assigned to its preferred physreg.
Definition: VirtRegMap.cpp:82
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
bool hasKnownPreference(unsigned VirtReg)
returns true if VirtReg has a known preferred register.
Definition: VirtRegMap.cpp:91
unsigned getSubReg() const
int CreateSpillStackObject(uint64_t Size, unsigned Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:376
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:36
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
Iterator for intrusive lists based on ilist_node.
Segments::const_iterator const_iterator
Definition: LiveInterval.h:208
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
Promote Memory to Register
Definition: Mem2Reg.cpp:100
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:824
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:382
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
virtregrewriter
Definition: VirtRegMap.cpp:194
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Virtual Register Rewriter
Definition: VirtRegMap.cpp:194
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static char ID
Definition: VirtRegMap.h:70
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
void setSubReg(unsigned subReg)
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block) ...
Definition: SlotIndexes.h:500
INITIALIZE_PASS_BEGIN(VirtRegRewriter,"virtregrewriter","Virtual Register Rewriter", false, false) INITIALIZE_PASS_END(VirtRegRewriter
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Virtual Register false
Definition: VirtRegMap.cpp:194
mop_iterator operands_begin()
Definition: MachineInstr.h:295
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:185
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:100
int assignVirt2StackSlot(unsigned virtReg)
create a mapping for the specifed virtual register to the next available stack slot ...
Definition: VirtRegMap.cpp:100
Primary interface to the complete machine description for the target machine.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:98
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:738
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
Properties which a MachineFunction may have at a given point in time.