LLVM  4.0.0
DbgValueHistoryCalculator.cpp
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1 //===-- llvm/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
11 #include "llvm/ADT/BitVector.h"
12 #include "llvm/ADT/SmallVector.h"
15 #include "llvm/IR/DebugInfo.h"
16 #include "llvm/Support/Debug.h"
21 #include <algorithm>
22 #include <map>
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "dwarfdebug"
26 
27 // \brief If @MI is a DBG_VALUE with debug value described by a
28 // defined register, returns the number of this register.
29 // In the other case, returns 0.
30 static unsigned isDescribedByReg(const MachineInstr &MI) {
31  assert(MI.isDebugValue());
32  assert(MI.getNumOperands() == 4);
33  // If location of variable is described using a register (directly or
34  // indirectly), this register is always a first operand.
35  return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
36 }
37 
39  const MachineInstr &MI) {
40  // Instruction range should start with a DBG_VALUE instruction for the
41  // variable.
42  assert(MI.isDebugValue() && "not a DBG_VALUE");
43  auto &Ranges = VarInstrRanges[Var];
44  if (!Ranges.empty() && Ranges.back().second == nullptr &&
45  Ranges.back().first->isIdenticalTo(MI)) {
46  DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
47  << "\t" << Ranges.back().first << "\t" << MI << "\n");
48  return;
49  }
50  Ranges.push_back(std::make_pair(&MI, nullptr));
51 }
52 
54  const MachineInstr &MI) {
55  auto &Ranges = VarInstrRanges[Var];
56  // Verify that the current instruction range is not yet closed.
57  assert(!Ranges.empty() && Ranges.back().second == nullptr);
58  // For now, instruction ranges are not allowed to cross basic block
59  // boundaries.
60  assert(Ranges.back().first->getParent() == MI.getParent());
61  Ranges.back().second = &MI;
62 }
63 
65  const auto &I = VarInstrRanges.find(Var);
66  if (I == VarInstrRanges.end())
67  return 0;
68  const auto &Ranges = I->second;
69  if (Ranges.empty() || Ranges.back().second != nullptr)
70  return 0;
71  return isDescribedByReg(*Ranges.back().first);
72 }
73 
74 namespace {
75 // Maps physreg numbers to the variables they describe.
76 typedef DbgValueHistoryMap::InlinedVariable InlinedVariable;
77 typedef std::map<unsigned, SmallVector<InlinedVariable, 1>> RegDescribedVarsMap;
78 }
79 
80 // \brief Claim that @Var is not described by @RegNo anymore.
81 static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo,
82  InlinedVariable Var) {
83  const auto &I = RegVars.find(RegNo);
84  assert(RegNo != 0U && I != RegVars.end());
85  auto &VarSet = I->second;
86  const auto &VarPos = find(VarSet, Var);
87  assert(VarPos != VarSet.end());
88  VarSet.erase(VarPos);
89  // Don't keep empty sets in a map to keep it as small as possible.
90  if (VarSet.empty())
91  RegVars.erase(I);
92 }
93 
94 // \brief Claim that @Var is now described by @RegNo.
95 static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo,
96  InlinedVariable Var) {
97  assert(RegNo != 0U);
98  auto &VarSet = RegVars[RegNo];
99  assert(!is_contained(VarSet, Var));
100  VarSet.push_back(Var);
101 }
102 
103 // \brief Terminate the location range for variables described by register at
104 // @I by inserting @ClobberingInstr to their history.
105 static void clobberRegisterUses(RegDescribedVarsMap &RegVars,
106  RegDescribedVarsMap::iterator I,
107  DbgValueHistoryMap &HistMap,
108  const MachineInstr &ClobberingInstr) {
109  // Iterate over all variables described by this register and add this
110  // instruction to their history, clobbering it.
111  for (const auto &Var : I->second)
112  HistMap.endInstrRange(Var, ClobberingInstr);
113  RegVars.erase(I);
114 }
115 
116 // \brief Terminate the location range for variables described by register
117 // @RegNo by inserting @ClobberingInstr to their history.
118 static void clobberRegisterUses(RegDescribedVarsMap &RegVars, unsigned RegNo,
119  DbgValueHistoryMap &HistMap,
120  const MachineInstr &ClobberingInstr) {
121  const auto &I = RegVars.find(RegNo);
122  if (I == RegVars.end())
123  return;
124  clobberRegisterUses(RegVars, I, HistMap, ClobberingInstr);
125 }
126 
127 // \brief Returns the first instruction in @MBB which corresponds to
128 // the function epilogue, or nullptr if @MBB doesn't contain an epilogue.
130  auto LastMI = MBB.getLastNonDebugInstr();
131  if (LastMI == MBB.end() || !LastMI->isReturn())
132  return nullptr;
133  // Assume that epilogue starts with instruction having the same debug location
134  // as the return instruction.
135  DebugLoc LastLoc = LastMI->getDebugLoc();
136  auto Res = LastMI;
137  for (MachineBasicBlock::const_reverse_iterator I = LastMI.getReverse(),
138  E = MBB.rend();
139  I != E; ++I) {
140  if (I->getDebugLoc() != LastLoc)
141  return &*Res;
142  Res = &*I;
143  }
144  // If all instructions have the same debug location, assume whole MBB is
145  // an epilogue.
146  return &*MBB.begin();
147 }
148 
149 // \brief Collect registers that are modified in the function body (their
150 // contents is changed outside of the prologue and epilogue).
151 static void collectChangingRegs(const MachineFunction *MF,
152  const TargetRegisterInfo *TRI,
153  BitVector &Regs) {
154  for (const auto &MBB : *MF) {
155  auto FirstEpilogueInst = getFirstEpilogueInst(MBB);
156 
157  for (const auto &MI : MBB) {
158  // Avoid looking at prologue or epilogue instructions.
159  if (&MI == FirstEpilogueInst)
160  break;
161  if (MI.getFlag(MachineInstr::FrameSetup))
162  continue;
163 
164  // Look for register defs and register masks. Register masks are
165  // typically on calls and they clobber everything not in the mask.
166  for (const MachineOperand &MO : MI.operands()) {
167  // Skip virtual registers since they are handled by the parent.
168  if (MO.isReg() && MO.isDef() && MO.getReg() &&
169  !TRI->isVirtualRegister(MO.getReg())) {
170  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
171  ++AI)
172  Regs.set(*AI);
173  } else if (MO.isRegMask()) {
174  Regs.setBitsNotInMask(MO.getRegMask());
175  }
176  }
177  }
178  }
179 }
180 
182  const TargetRegisterInfo *TRI,
183  DbgValueHistoryMap &Result) {
184  BitVector ChangingRegs(TRI->getNumRegs());
185  collectChangingRegs(MF, TRI, ChangingRegs);
186 
187  const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
188  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
189  RegDescribedVarsMap RegVars;
190  for (const auto &MBB : *MF) {
191  for (const auto &MI : MBB) {
192  if (!MI.isDebugValue()) {
193  // Not a DBG_VALUE instruction. It may clobber registers which describe
194  // some variables.
195  for (const MachineOperand &MO : MI.operands()) {
196  if (MO.isReg() && MO.isDef() && MO.getReg()) {
197  // If this is a virtual register, only clobber it since it doesn't
198  // have aliases.
199  if (TRI->isVirtualRegister(MO.getReg()))
200  clobberRegisterUses(RegVars, MO.getReg(), Result, MI);
201  // If this is a register def operand, it may end a debug value
202  // range.
203  else {
204  for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
205  ++AI)
206  if (ChangingRegs.test(*AI))
207  clobberRegisterUses(RegVars, *AI, Result, MI);
208  }
209  } else if (MO.isRegMask()) {
210  // If this is a register mask operand, clobber all debug values in
211  // non-CSRs.
212  for (int I = ChangingRegs.find_first(); I != -1;
213  I = ChangingRegs.find_next(I)) {
214  // Don't consider SP to be clobbered by register masks.
215  if (unsigned(I) != SP && TRI->isPhysicalRegister(I) &&
216  MO.clobbersPhysReg(I)) {
217  clobberRegisterUses(RegVars, I, Result, MI);
218  }
219  }
220  }
221  }
222  continue;
223  }
224 
225  assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");
226  // Use the base variable (without any DW_OP_piece expressions)
227  // as index into History. The full variables including the
228  // piece expressions are attached to the MI.
229  const DILocalVariable *RawVar = MI.getDebugVariable();
230  assert(RawVar->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
231  "Expected inlined-at fields to agree");
232  InlinedVariable Var(RawVar, MI.getDebugLoc()->getInlinedAt());
233 
234  if (unsigned PrevReg = Result.getRegisterForVar(Var))
235  dropRegDescribedVar(RegVars, PrevReg, Var);
236 
237  Result.startInstrRange(Var, MI);
238 
239  if (unsigned NewReg = isDescribedByReg(MI))
240  addRegDescribedVar(RegVars, NewReg, Var);
241  }
242 
243  // Make sure locations for register-described variables are valid only
244  // until the end of the basic block (unless it's the last basic block, in
245  // which case let their liveness run off to the end of the function).
246  if (!MBB.empty() && &MBB != &MF->back()) {
247  for (auto I = RegVars.begin(), E = RegVars.end(); I != E;) {
248  auto CurElem = I++; // CurElem can be erased below.
249  if (TRI->isVirtualRegister(CurElem->first) ||
250  ChangingRegs.test(CurElem->first))
251  clobberRegisterUses(RegVars, CurElem, Result, MBB.back());
252  }
253  }
254  }
255 }
BitVector & set()
Definition: BitVector.h:219
void calculateDbgValueHistory(const MachineFunction *MF, const TargetRegisterInfo *TRI, DbgValueHistoryMap &Result)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static void collectChangingRegs(const MachineFunction *MF, const TargetRegisterInfo *TRI, BitVector &Regs)
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
Definition: BitVector.h:495
A debug info location.
Definition: DebugLoc.h:34
static void clobberRegisterUses(RegDescribedVarsMap &RegVars, RegDescribedVarsMap::iterator I, DbgValueHistoryMap &HistMap, const MachineInstr &ClobberingInstr)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedVariable Var)
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
MachineBasicBlock * MBB
const RegList & Regs
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
iterator find(const KeyT &Key)
Definition: MapVector.h:131
reverse_iterator rend()
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool isDebugValue() const
Definition: MachineInstr.h:777
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
void startInstrRange(InlinedVariable Var, const MachineInstr &MI)
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned isDescribedByReg(const MachineInstr &MI)
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:757
MachineOperand class - Representation of each machine instruction operand.
static const MachineInstr * getFirstEpilogueInst(const MachineBasicBlock &MBB)
virtual const TargetLowering * getTargetLowering() const
static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedVariable Var)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
#define I(x, y, z)
Definition: MD5.cpp:54
void endInstrRange(InlinedVariable Var, const MachineInstr &MI)
unsigned getReg() const
getReg - Returns the register number.
iterator end()
Definition: MapVector.h:55
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getRegisterForVar(InlinedVariable Var) const
std::pair< const DILocalVariable *, const DILocation * > InlinedVariable
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
This file describes how to lower LLVM code to machine code.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:783