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LLVM
4.0.0
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#include <HexagonSubtarget.h>
Classes | |
| class | HexagonDAGMutation |
Public Types | |
| enum | HexagonArchEnum { V4, V5, V55, V60 } |
Public Attributes | |
| HexagonArchEnum | HexagonArchVersion |
| bool | UseBSBScheduling |
| True if the target should use Back-Skip-Back scheduling. More... | |
Definition at line 33 of file HexagonSubtarget.h.
| Enumerator | |
|---|---|
| V4 | |
| V5 | |
| V55 | |
| V60 | |
Definition at line 41 of file HexagonSubtarget.h.
| HexagonSubtarget::HexagonSubtarget | ( | const Triple & | TT, |
| StringRef | CPU, | ||
| StringRef | FS, | ||
| const TargetMachine & | TM | ||
| ) |
Definition at line 114 of file HexagonSubtarget.cpp.
References DisableMemOps, EnableBSBSched, EnableIEEERndNear, EnableMemOps, hasV60TOps(), and UseBSBScheduling.
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Perform target specific adjustments to the latency of a schedule dependency.
Definition at line 328 of file HexagonSubtarget.cpp.
References llvm::SDep::Anti, llvm::HexagonInstrInfo::canExecuteInBundle(), EnableDotCurSched, llvm::SUnit::getInstr(), getInstrInfo(), llvm::SDep::getKind(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::SDep::getReg(), llvm::MachineOperand::getReg(), hasV60TOps(), llvm::SDep::isAssignedRegDep(), llvm::SUnit::isInstr(), llvm::MachineInstr::isPHI(), llvm::HexagonInstrInfo::isPostIncrement(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegSequence(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), llvm::MachineInstr::mayStore(), llvm::SUnit::NumSuccs, llvm::SDep::setLatency(), llvm::SUnit::Succs, and useBSBScheduling().
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Definition at line 112 of file HexagonSubtarget.h.
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Definition at line 200 of file HexagonSubtarget.cpp.
References DisableHexagonMISched.
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Definition at line 115 of file HexagonSubtarget.h.
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Definition at line 206 of file HexagonSubtarget.cpp.
References EnableSubregLiveness.
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Definition at line 114 of file HexagonSubtarget.h.
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Definition at line 119 of file HexagonSubtarget.h.
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Definition at line 80 of file HexagonSubtarget.h.
Referenced by llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC().
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Definition at line 125 of file HexagonSubtarget.h.
References HexagonArchVersion.
Referenced by llvm::HexagonRegisterInfo::getCalleeSavedRegs(), hasV55TOps(), hasV55TOpsOnly(), hasV5TOps(), hasV5TOpsOnly(), hasV60TOps(), and hasV60TOpsOnly().
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Definition at line 73 of file HexagonSubtarget.h.
Referenced by adjustSchedDependency(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::HexagonAsmPrinter::EmitInstruction(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), llvm::ConvergingVLIWScheduler::pickNodeFromQueue(), and llvm::ConvergingVLIWScheduler::SchedulingCost().
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getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition at line 70 of file HexagonSubtarget.h.
| unsigned HexagonSubtarget::getL1CacheLineSize | ( | ) | const |
Definition at line 386 of file HexagonSubtarget.cpp.
Referenced by llvm::HexagonTTIImpl::getCacheLineSize().
| unsigned HexagonSubtarget::getL1PrefetchDistance | ( | ) | const |
Definition at line 390 of file HexagonSubtarget.cpp.
Referenced by llvm::HexagonTTIImpl::getPrefetchDistance().
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Definition at line 186 of file HexagonSubtarget.cpp.
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Definition at line 74 of file HexagonSubtarget.h.
References llvm::HexagonInstrInfo::getRegisterInfo().
Referenced by llvm::HexagonFrameLowering::emitPrologue(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::HexagonTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerINLINEASM(), and llvm::HexagonTargetLowering::LowerRETURNADDR().
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Definition at line 83 of file HexagonSubtarget.h.
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Definition at line 122 of file HexagonSubtarget.h.
References Hexagon_SMALL_DATA_THRESHOLD.
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Definition at line 191 of file HexagonSubtarget.cpp.
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Definition at line 77 of file HexagonSubtarget.h.
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Definition at line 97 of file HexagonSubtarget.h.
References getHexagonArchVersion(), and V55.
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Definition at line 98 of file HexagonSubtarget.h.
References getHexagonArchVersion(), and V55.
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Definition at line 95 of file HexagonSubtarget.h.
References getHexagonArchVersion(), and V5.
Referenced by llvm::HexagonTargetLowering::HexagonTargetLowering(), and llvm::HexagonTargetLowering::isFPImmLegal().
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Definition at line 96 of file HexagonSubtarget.h.
References getHexagonArchVersion(), and V5.
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Definition at line 99 of file HexagonSubtarget.h.
References getHexagonArchVersion(), and V60.
Referenced by adjustSchedDependency(), llvm::HexagonTargetLowering::findRepresentativeClass(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), HexagonSubtarget(), llvm::HexagonTargetLowering::HexagonTargetLowering(), and llvm::HexagonTargetLowering::LowerCall().
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Definition at line 100 of file HexagonSubtarget.h.
References getHexagonArchVersion(), and V60.
Referenced by cannotCoexistAsymm().
| HexagonSubtarget & HexagonSubtarget::initializeSubtargetDependencies | ( | StringRef | CPU, |
| StringRef | FS | ||
| ) |
Definition at line 83 of file HexagonSubtarget.cpp.
References EnableHexagonHVX, EnableHexagonHVXDouble, HexagonArchVersion, llvm_unreachable, OverrideLongCalls, ParseSubtargetFeatures(), llvm::Hexagon_MC::selectHexagonCPU(), V4, V5, V55, and V60.
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Definition at line 101 of file HexagonSubtarget.h.
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Definition of function is auto generated by tblgen.
Referenced by initializeSubtargetDependencies().
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Definition at line 107 of file HexagonSubtarget.h.
References UseBSBScheduling.
Referenced by adjustSchedDependency(), and llvm::HexagonPacketizerList::producesStall().
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Definition at line 103 of file HexagonSubtarget.h.
Referenced by llvm::HexagonTargetLowering::findRepresentativeClass(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::HexagonTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerFormalArguments(), and llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE().
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Definition at line 102 of file HexagonSubtarget.h.
Referenced by CC_HexagonVector(), llvm::HexagonTargetLowering::findRepresentativeClass(), llvm::HexagonTargetLowering::getConstraintType(), getIndexedAddressParts(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::HexagonTargetLowering::isShuffleMaskLegal(), llvm::HexagonTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), RetCC_Hexagon(), and RetCC_HexagonVector().
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Definition at line 105 of file HexagonSubtarget.h.
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Definition at line 94 of file HexagonSubtarget.h.
| HexagonArchEnum llvm::HexagonSubtarget::HexagonArchVersion |
Definition at line 45 of file HexagonSubtarget.h.
Referenced by getHexagonArchVersion(), and initializeSubtargetDependencies().
| bool llvm::HexagonSubtarget::UseBSBScheduling |
True if the target should use Back-Skip-Back scheduling.
This is the default for V60.
Definition at line 48 of file HexagonSubtarget.h.
Referenced by HexagonSubtarget(), and useBSBScheduling().
1.8.6