LLVM  4.0.0
PPCAsmParser.cpp
Go to the documentation of this file.
1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSymbolELF.h"
28 #include "llvm/Support/SourceMgr.h"
31 
32 using namespace llvm;
33 
34 static const MCPhysReg RRegs[32] = {
35  PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42  PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 };
44 static const MCPhysReg RRegsNoR0[32] = {
45  PPC::ZERO,
46  PPC::R1, PPC::R2, PPC::R3,
47  PPC::R4, PPC::R5, PPC::R6, PPC::R7,
48  PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53  PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 };
55 static const MCPhysReg XRegs[32] = {
56  PPC::X0, PPC::X1, PPC::X2, PPC::X3,
57  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
58  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
59  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63  PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 };
65 static const MCPhysReg XRegsNoX0[32] = {
66  PPC::ZERO8,
67  PPC::X1, PPC::X2, PPC::X3,
68  PPC::X4, PPC::X5, PPC::X6, PPC::X7,
69  PPC::X8, PPC::X9, PPC::X10, PPC::X11,
70  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74  PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 };
76 static const MCPhysReg FRegs[32] = {
77  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84  PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 };
86 static const MCPhysReg VFRegs[32] = {
87  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
88  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
89  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
90  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
91  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
92  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
93  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
94  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
95 };
96 static const MCPhysReg VRegs[32] = {
97  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
98  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
99  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
100  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
101  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
102  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
103  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
104  PPC::V28, PPC::V29, PPC::V30, PPC::V31
105 };
106 static const MCPhysReg VSRegs[64] = {
107  PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
108  PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
109  PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
110  PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
111  PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
112  PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
113  PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
114  PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
115 
116  PPC::V0, PPC::V1, PPC::V2, PPC::V3,
117  PPC::V4, PPC::V5, PPC::V6, PPC::V7,
118  PPC::V8, PPC::V9, PPC::V10, PPC::V11,
119  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
120  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
121  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
122  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
123  PPC::V28, PPC::V29, PPC::V30, PPC::V31
124 };
125 static const MCPhysReg VSFRegs[64] = {
126  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
127  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
128  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
129  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
130  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
131  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
132  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
133  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
134 
135  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
136  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
137  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
138  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
139  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
140  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
141  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
142  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
143 };
144 static const MCPhysReg VSSRegs[64] = {
145  PPC::F0, PPC::F1, PPC::F2, PPC::F3,
146  PPC::F4, PPC::F5, PPC::F6, PPC::F7,
147  PPC::F8, PPC::F9, PPC::F10, PPC::F11,
148  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
149  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
150  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
151  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
152  PPC::F28, PPC::F29, PPC::F30, PPC::F31,
153 
154  PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
155  PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
156  PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
157  PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
158  PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
159  PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
160  PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
161  PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
162 };
163 static unsigned QFRegs[32] = {
164  PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
165  PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
166  PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
167  PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
168  PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
169  PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
170  PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
171  PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
172 };
173 static const MCPhysReg CRBITRegs[32] = {
174  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
175  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
176  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
177  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
178  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
179  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
180  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
181  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
182 };
183 static const MCPhysReg CRRegs[8] = {
184  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
185  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
186 };
187 
188 // Evaluate an expression containing condition register
189 // or condition register field symbols. Returns positive
190 // value on success, or -1 on error.
191 static int64_t
193  switch (E->getKind()) {
194  case MCExpr::Target:
195  return -1;
196 
197  case MCExpr::Constant: {
198  int64_t Res = cast<MCConstantExpr>(E)->getValue();
199  return Res < 0 ? -1 : Res;
200  }
201 
202  case MCExpr::SymbolRef: {
203  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
204  StringRef Name = SRE->getSymbol().getName();
205 
206  if (Name == "lt") return 0;
207  if (Name == "gt") return 1;
208  if (Name == "eq") return 2;
209  if (Name == "so") return 3;
210  if (Name == "un") return 3;
211 
212  if (Name == "cr0") return 0;
213  if (Name == "cr1") return 1;
214  if (Name == "cr2") return 2;
215  if (Name == "cr3") return 3;
216  if (Name == "cr4") return 4;
217  if (Name == "cr5") return 5;
218  if (Name == "cr6") return 6;
219  if (Name == "cr7") return 7;
220 
221  return -1;
222  }
223 
224  case MCExpr::Unary:
225  return -1;
226 
227  case MCExpr::Binary: {
228  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
229  int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
230  int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
231  int64_t Res;
232 
233  if (LHSVal < 0 || RHSVal < 0)
234  return -1;
235 
236  switch (BE->getOpcode()) {
237  default: return -1;
238  case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
239  case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
240  }
241 
242  return Res < 0 ? -1 : Res;
243  }
244  }
245 
246  llvm_unreachable("Invalid expression kind!");
247 }
248 
249 namespace {
250 
251 struct PPCOperand;
252 
253 class PPCAsmParser : public MCTargetAsmParser {
254  const MCInstrInfo &MII;
255  bool IsPPC64;
256  bool IsDarwin;
257 
258  void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
259 
260  bool isPPC64() const { return IsPPC64; }
261  bool isDarwin() const { return IsDarwin; }
262 
263  bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
264 
265  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
266 
267  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
268  PPCMCExpr::VariantKind &Variant);
269  const MCExpr *FixupVariantKind(const MCExpr *E);
270  bool ParseExpression(const MCExpr *&EVal);
271  bool ParseDarwinExpression(const MCExpr *&EVal);
272 
273  bool ParseOperand(OperandVector &Operands);
274 
275  bool ParseDirectiveWord(unsigned Size, AsmToken ID);
276  bool ParseDirectiveTC(unsigned Size, AsmToken ID);
277  bool ParseDirectiveMachine(SMLoc L);
278  bool ParseDarwinDirectiveMachine(SMLoc L);
279  bool ParseDirectiveAbiVersion(SMLoc L);
280  bool ParseDirectiveLocalEntry(SMLoc L);
281 
282  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
283  OperandVector &Operands, MCStreamer &Out,
284  uint64_t &ErrorInfo,
285  bool MatchingInlineAsm) override;
286 
287  void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
288 
289  /// @name Auto-generated Match Functions
290  /// {
291 
292 #define GET_ASSEMBLER_HEADER
293 #include "PPCGenAsmMatcher.inc"
294 
295  /// }
296 
297 
298 public:
299  PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
300  const MCInstrInfo &MII, const MCTargetOptions &Options)
301  : MCTargetAsmParser(Options, STI), MII(MII) {
302  // Check for 64-bit vs. 32-bit pointer mode.
303  const Triple &TheTriple = STI.getTargetTriple();
304  IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
305  TheTriple.getArch() == Triple::ppc64le);
306  IsDarwin = TheTriple.isMacOSX();
307  // Initialize the set of available features.
308  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
309  }
310 
311  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
312  SMLoc NameLoc, OperandVector &Operands) override;
313 
314  bool ParseDirective(AsmToken DirectiveID) override;
315 
316  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
317  unsigned Kind) override;
318 
319  const MCExpr *applyModifierToExpr(const MCExpr *E,
321  MCContext &Ctx) override;
322 };
323 
324 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
325 /// instruction.
326 struct PPCOperand : public MCParsedAsmOperand {
327  enum KindTy {
328  Token,
329  Immediate,
330  ContextImmediate,
331  Expression,
332  TLSRegister
333  } Kind;
334 
335  SMLoc StartLoc, EndLoc;
336  bool IsPPC64;
337 
338  struct TokOp {
339  const char *Data;
340  unsigned Length;
341  };
342 
343  struct ImmOp {
344  int64_t Val;
345  };
346 
347  struct ExprOp {
348  const MCExpr *Val;
349  int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
350  };
351 
352  struct TLSRegOp {
353  const MCSymbolRefExpr *Sym;
354  };
355 
356  union {
357  struct TokOp Tok;
358  struct ImmOp Imm;
359  struct ExprOp Expr;
360  struct TLSRegOp TLSReg;
361  };
362 
363  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
364 public:
365  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
366  Kind = o.Kind;
367  StartLoc = o.StartLoc;
368  EndLoc = o.EndLoc;
369  IsPPC64 = o.IsPPC64;
370  switch (Kind) {
371  case Token:
372  Tok = o.Tok;
373  break;
374  case Immediate:
375  case ContextImmediate:
376  Imm = o.Imm;
377  break;
378  case Expression:
379  Expr = o.Expr;
380  break;
381  case TLSRegister:
382  TLSReg = o.TLSReg;
383  break;
384  }
385  }
386 
387  // Disable use of sized deallocation due to overallocation of PPCOperand
388  // objects in CreateTokenWithStringCopy.
389  void operator delete(void *p) { ::operator delete(p); }
390 
391  /// getStartLoc - Get the location of the first token of this operand.
392  SMLoc getStartLoc() const override { return StartLoc; }
393 
394  /// getEndLoc - Get the location of the last token of this operand.
395  SMLoc getEndLoc() const override { return EndLoc; }
396 
397  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
398  bool isPPC64() const { return IsPPC64; }
399 
400  int64_t getImm() const {
401  assert(Kind == Immediate && "Invalid access!");
402  return Imm.Val;
403  }
404  int64_t getImmS16Context() const {
405  assert((Kind == Immediate || Kind == ContextImmediate) &&
406  "Invalid access!");
407  if (Kind == Immediate)
408  return Imm.Val;
409  return static_cast<int16_t>(Imm.Val);
410  }
411  int64_t getImmU16Context() const {
412  assert((Kind == Immediate || Kind == ContextImmediate) &&
413  "Invalid access!");
414  return Imm.Val;
415  }
416 
417  const MCExpr *getExpr() const {
418  assert(Kind == Expression && "Invalid access!");
419  return Expr.Val;
420  }
421 
422  int64_t getExprCRVal() const {
423  assert(Kind == Expression && "Invalid access!");
424  return Expr.CRVal;
425  }
426 
427  const MCExpr *getTLSReg() const {
428  assert(Kind == TLSRegister && "Invalid access!");
429  return TLSReg.Sym;
430  }
431 
432  unsigned getReg() const override {
433  assert(isRegNumber() && "Invalid access!");
434  return (unsigned) Imm.Val;
435  }
436 
437  unsigned getVSReg() const {
438  assert(isVSRegNumber() && "Invalid access!");
439  return (unsigned) Imm.Val;
440  }
441 
442  unsigned getCCReg() const {
443  assert(isCCRegNumber() && "Invalid access!");
444  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
445  }
446 
447  unsigned getCRBit() const {
448  assert(isCRBitNumber() && "Invalid access!");
449  return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
450  }
451 
452  unsigned getCRBitMask() const {
453  assert(isCRBitMask() && "Invalid access!");
454  return 7 - countTrailingZeros<uint64_t>(Imm.Val);
455  }
456 
457  bool isToken() const override { return Kind == Token; }
458  bool isImm() const override {
459  return Kind == Immediate || Kind == Expression;
460  }
461  bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
462  bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
463  bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
464  bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
465  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
466  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
467  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
468  bool isU6ImmX2() const { return Kind == Immediate &&
469  isUInt<6>(getImm()) &&
470  (getImm() & 1) == 0; }
471  bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
472  bool isU7ImmX4() const { return Kind == Immediate &&
473  isUInt<7>(getImm()) &&
474  (getImm() & 3) == 0; }
475  bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
476  bool isU8ImmX8() const { return Kind == Immediate &&
477  isUInt<8>(getImm()) &&
478  (getImm() & 7) == 0; }
479 
480  bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
481  bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
482  bool isU16Imm() const {
483  switch (Kind) {
484  case Expression:
485  return true;
486  case Immediate:
487  case ContextImmediate:
488  return isUInt<16>(getImmU16Context());
489  default:
490  return false;
491  }
492  }
493  bool isS16Imm() const {
494  switch (Kind) {
495  case Expression:
496  return true;
497  case Immediate:
498  case ContextImmediate:
499  return isInt<16>(getImmS16Context());
500  default:
501  return false;
502  }
503  }
504  bool isS16ImmX4() const { return Kind == Expression ||
505  (Kind == Immediate && isInt<16>(getImm()) &&
506  (getImm() & 3) == 0); }
507  bool isS16ImmX16() const { return Kind == Expression ||
508  (Kind == Immediate && isInt<16>(getImm()) &&
509  (getImm() & 15) == 0); }
510  bool isS17Imm() const {
511  switch (Kind) {
512  case Expression:
513  return true;
514  case Immediate:
515  case ContextImmediate:
516  return isInt<17>(getImmS16Context());
517  default:
518  return false;
519  }
520  }
521  bool isTLSReg() const { return Kind == TLSRegister; }
522  bool isDirectBr() const {
523  if (Kind == Expression)
524  return true;
525  if (Kind != Immediate)
526  return false;
527  // Operand must be 64-bit aligned, signed 27-bit immediate.
528  if ((getImm() & 3) != 0)
529  return false;
530  if (isInt<26>(getImm()))
531  return true;
532  if (!IsPPC64) {
533  // In 32-bit mode, large 32-bit quantities wrap around.
534  if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
535  return true;
536  }
537  return false;
538  }
539  bool isCondBr() const { return Kind == Expression ||
540  (Kind == Immediate && isInt<16>(getImm()) &&
541  (getImm() & 3) == 0); }
542  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
543  bool isVSRegNumber() const {
544  return Kind == Immediate && isUInt<6>(getImm());
545  }
546  bool isCCRegNumber() const { return (Kind == Expression
547  && isUInt<3>(getExprCRVal())) ||
548  (Kind == Immediate
549  && isUInt<3>(getImm())); }
550  bool isCRBitNumber() const { return (Kind == Expression
551  && isUInt<5>(getExprCRVal())) ||
552  (Kind == Immediate
553  && isUInt<5>(getImm())); }
554  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
555  isPowerOf2_32(getImm()); }
556  bool isATBitsAsHint() const { return false; }
557  bool isMem() const override { return false; }
558  bool isReg() const override { return false; }
559 
560  void addRegOperands(MCInst &Inst, unsigned N) const {
561  llvm_unreachable("addRegOperands");
562  }
563 
564  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
565  assert(N == 1 && "Invalid number of operands!");
567  }
568 
569  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
570  assert(N == 1 && "Invalid number of operands!");
572  }
573 
574  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
575  assert(N == 1 && "Invalid number of operands!");
577  }
578 
579  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
580  assert(N == 1 && "Invalid number of operands!");
582  }
583 
584  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
585  if (isPPC64())
586  addRegG8RCOperands(Inst, N);
587  else
588  addRegGPRCOperands(Inst, N);
589  }
590 
591  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
592  if (isPPC64())
593  addRegG8RCNoX0Operands(Inst, N);
594  else
595  addRegGPRCNoR0Operands(Inst, N);
596  }
597 
598  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
599  assert(N == 1 && "Invalid number of operands!");
601  }
602 
603  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
604  assert(N == 1 && "Invalid number of operands!");
606  }
607 
608  void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
609  assert(N == 1 && "Invalid number of operands!");
611  }
612 
613  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
614  assert(N == 1 && "Invalid number of operands!");
616  }
617 
618  void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
619  assert(N == 1 && "Invalid number of operands!");
620  Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
621  }
622 
623  void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
624  assert(N == 1 && "Invalid number of operands!");
625  Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
626  }
627 
628  void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
629  assert(N == 1 && "Invalid number of operands!");
630  Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
631  }
632 
633  void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
634  assert(N == 1 && "Invalid number of operands!");
636  }
637 
638  void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
639  assert(N == 1 && "Invalid number of operands!");
641  }
642 
643  void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
644  assert(N == 1 && "Invalid number of operands!");
646  }
647 
648  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
649  assert(N == 1 && "Invalid number of operands!");
650  Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
651  }
652 
653  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
654  assert(N == 1 && "Invalid number of operands!");
655  Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
656  }
657 
658  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
659  assert(N == 1 && "Invalid number of operands!");
660  Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
661  }
662 
663  void addImmOperands(MCInst &Inst, unsigned N) const {
664  assert(N == 1 && "Invalid number of operands!");
665  if (Kind == Immediate)
666  Inst.addOperand(MCOperand::createImm(getImm()));
667  else
669  }
670 
671  void addS16ImmOperands(MCInst &Inst, unsigned N) const {
672  assert(N == 1 && "Invalid number of operands!");
673  switch (Kind) {
674  case Immediate:
675  Inst.addOperand(MCOperand::createImm(getImm()));
676  break;
677  case ContextImmediate:
678  Inst.addOperand(MCOperand::createImm(getImmS16Context()));
679  break;
680  default:
682  break;
683  }
684  }
685 
686  void addU16ImmOperands(MCInst &Inst, unsigned N) const {
687  assert(N == 1 && "Invalid number of operands!");
688  switch (Kind) {
689  case Immediate:
690  Inst.addOperand(MCOperand::createImm(getImm()));
691  break;
692  case ContextImmediate:
693  Inst.addOperand(MCOperand::createImm(getImmU16Context()));
694  break;
695  default:
697  break;
698  }
699  }
700 
701  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
702  assert(N == 1 && "Invalid number of operands!");
703  if (Kind == Immediate)
704  Inst.addOperand(MCOperand::createImm(getImm() / 4));
705  else
707  }
708 
709  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
710  assert(N == 1 && "Invalid number of operands!");
711  Inst.addOperand(MCOperand::createExpr(getTLSReg()));
712  }
713 
714  StringRef getToken() const {
715  assert(Kind == Token && "Invalid access!");
716  return StringRef(Tok.Data, Tok.Length);
717  }
718 
719  void print(raw_ostream &OS) const override;
720 
721  static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
722  bool IsPPC64) {
723  auto Op = make_unique<PPCOperand>(Token);
724  Op->Tok.Data = Str.data();
725  Op->Tok.Length = Str.size();
726  Op->StartLoc = S;
727  Op->EndLoc = S;
728  Op->IsPPC64 = IsPPC64;
729  return Op;
730  }
731 
732  static std::unique_ptr<PPCOperand>
733  CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
734  // Allocate extra memory for the string and copy it.
735  // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
736  // deleter which will destroy them by simply using "delete", not correctly
737  // calling operator delete on this extra memory after calling the dtor
738  // explicitly.
739  void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
740  std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
741  Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
742  Op->Tok.Length = Str.size();
743  std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
744  Op->StartLoc = S;
745  Op->EndLoc = S;
746  Op->IsPPC64 = IsPPC64;
747  return Op;
748  }
749 
750  static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
751  bool IsPPC64) {
752  auto Op = make_unique<PPCOperand>(Immediate);
753  Op->Imm.Val = Val;
754  Op->StartLoc = S;
755  Op->EndLoc = E;
756  Op->IsPPC64 = IsPPC64;
757  return Op;
758  }
759 
760  static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
761  SMLoc E, bool IsPPC64) {
762  auto Op = make_unique<PPCOperand>(Expression);
763  Op->Expr.Val = Val;
764  Op->Expr.CRVal = EvaluateCRExpr(Val);
765  Op->StartLoc = S;
766  Op->EndLoc = E;
767  Op->IsPPC64 = IsPPC64;
768  return Op;
769  }
770 
771  static std::unique_ptr<PPCOperand>
772  CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
773  auto Op = make_unique<PPCOperand>(TLSRegister);
774  Op->TLSReg.Sym = Sym;
775  Op->StartLoc = S;
776  Op->EndLoc = E;
777  Op->IsPPC64 = IsPPC64;
778  return Op;
779  }
780 
781  static std::unique_ptr<PPCOperand>
782  CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
783  auto Op = make_unique<PPCOperand>(ContextImmediate);
784  Op->Imm.Val = Val;
785  Op->StartLoc = S;
786  Op->EndLoc = E;
787  Op->IsPPC64 = IsPPC64;
788  return Op;
789  }
790 
791  static std::unique_ptr<PPCOperand>
792  CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
793  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
794  return CreateImm(CE->getValue(), S, E, IsPPC64);
795 
796  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
797  if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
798  return CreateTLSReg(SRE, S, E, IsPPC64);
799 
800  if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
801  int64_t Res;
802  if (TE->evaluateAsConstant(Res))
803  return CreateContextImm(Res, S, E, IsPPC64);
804  }
805 
806  return CreateExpr(Val, S, E, IsPPC64);
807  }
808 };
809 
810 } // end anonymous namespace.
811 
812 void PPCOperand::print(raw_ostream &OS) const {
813  switch (Kind) {
814  case Token:
815  OS << "'" << getToken() << "'";
816  break;
817  case Immediate:
818  case ContextImmediate:
819  OS << getImm();
820  break;
821  case Expression:
822  OS << *getExpr();
823  break;
824  case TLSRegister:
825  OS << *getTLSReg();
826  break;
827  }
828 }
829 
830 static void
832  if (Op.isImm()) {
834  return;
835  }
836  const MCExpr *Expr = Op.getExpr();
837  if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
838  if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
839  Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
840  return;
841  }
842  } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
843  if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
844  const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
845  BinExpr->getLHS(), Ctx);
847  return;
848  }
849  }
851 }
852 
853 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
854  const OperandVector &Operands) {
855  int Opcode = Inst.getOpcode();
856  switch (Opcode) {
857  case PPC::DCBTx:
858  case PPC::DCBTT:
859  case PPC::DCBTSTx:
860  case PPC::DCBTSTT: {
861  MCInst TmpInst;
862  TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
863  PPC::DCBT : PPC::DCBTST);
865  (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
866  TmpInst.addOperand(Inst.getOperand(0));
867  TmpInst.addOperand(Inst.getOperand(1));
868  Inst = TmpInst;
869  break;
870  }
871  case PPC::DCBTCT:
872  case PPC::DCBTDS: {
873  MCInst TmpInst;
874  TmpInst.setOpcode(PPC::DCBT);
875  TmpInst.addOperand(Inst.getOperand(2));
876  TmpInst.addOperand(Inst.getOperand(0));
877  TmpInst.addOperand(Inst.getOperand(1));
878  Inst = TmpInst;
879  break;
880  }
881  case PPC::DCBTSTCT:
882  case PPC::DCBTSTDS: {
883  MCInst TmpInst;
884  TmpInst.setOpcode(PPC::DCBTST);
885  TmpInst.addOperand(Inst.getOperand(2));
886  TmpInst.addOperand(Inst.getOperand(0));
887  TmpInst.addOperand(Inst.getOperand(1));
888  Inst = TmpInst;
889  break;
890  }
891  case PPC::DCBFx:
892  case PPC::DCBFL:
893  case PPC::DCBFLP: {
894  int L = 0;
895  if (Opcode == PPC::DCBFL)
896  L = 1;
897  else if (Opcode == PPC::DCBFLP)
898  L = 3;
899 
900  MCInst TmpInst;
901  TmpInst.setOpcode(PPC::DCBF);
902  TmpInst.addOperand(MCOperand::createImm(L));
903  TmpInst.addOperand(Inst.getOperand(0));
904  TmpInst.addOperand(Inst.getOperand(1));
905  Inst = TmpInst;
906  break;
907  }
908  case PPC::LAx: {
909  MCInst TmpInst;
910  TmpInst.setOpcode(PPC::LA);
911  TmpInst.addOperand(Inst.getOperand(0));
912  TmpInst.addOperand(Inst.getOperand(2));
913  TmpInst.addOperand(Inst.getOperand(1));
914  Inst = TmpInst;
915  break;
916  }
917  case PPC::SUBI: {
918  MCInst TmpInst;
919  TmpInst.setOpcode(PPC::ADDI);
920  TmpInst.addOperand(Inst.getOperand(0));
921  TmpInst.addOperand(Inst.getOperand(1));
922  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
923  Inst = TmpInst;
924  break;
925  }
926  case PPC::SUBIS: {
927  MCInst TmpInst;
928  TmpInst.setOpcode(PPC::ADDIS);
929  TmpInst.addOperand(Inst.getOperand(0));
930  TmpInst.addOperand(Inst.getOperand(1));
931  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
932  Inst = TmpInst;
933  break;
934  }
935  case PPC::SUBIC: {
936  MCInst TmpInst;
937  TmpInst.setOpcode(PPC::ADDIC);
938  TmpInst.addOperand(Inst.getOperand(0));
939  TmpInst.addOperand(Inst.getOperand(1));
940  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
941  Inst = TmpInst;
942  break;
943  }
944  case PPC::SUBICo: {
945  MCInst TmpInst;
946  TmpInst.setOpcode(PPC::ADDICo);
947  TmpInst.addOperand(Inst.getOperand(0));
948  TmpInst.addOperand(Inst.getOperand(1));
949  addNegOperand(TmpInst, Inst.getOperand(2), getContext());
950  Inst = TmpInst;
951  break;
952  }
953  case PPC::EXTLWI:
954  case PPC::EXTLWIo: {
955  MCInst TmpInst;
956  int64_t N = Inst.getOperand(2).getImm();
957  int64_t B = Inst.getOperand(3).getImm();
958  TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
959  TmpInst.addOperand(Inst.getOperand(0));
960  TmpInst.addOperand(Inst.getOperand(1));
961  TmpInst.addOperand(MCOperand::createImm(B));
962  TmpInst.addOperand(MCOperand::createImm(0));
963  TmpInst.addOperand(MCOperand::createImm(N - 1));
964  Inst = TmpInst;
965  break;
966  }
967  case PPC::EXTRWI:
968  case PPC::EXTRWIo: {
969  MCInst TmpInst;
970  int64_t N = Inst.getOperand(2).getImm();
971  int64_t B = Inst.getOperand(3).getImm();
972  TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
973  TmpInst.addOperand(Inst.getOperand(0));
974  TmpInst.addOperand(Inst.getOperand(1));
975  TmpInst.addOperand(MCOperand::createImm(B + N));
976  TmpInst.addOperand(MCOperand::createImm(32 - N));
977  TmpInst.addOperand(MCOperand::createImm(31));
978  Inst = TmpInst;
979  break;
980  }
981  case PPC::INSLWI:
982  case PPC::INSLWIo: {
983  MCInst TmpInst;
984  int64_t N = Inst.getOperand(2).getImm();
985  int64_t B = Inst.getOperand(3).getImm();
986  TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
987  TmpInst.addOperand(Inst.getOperand(0));
988  TmpInst.addOperand(Inst.getOperand(0));
989  TmpInst.addOperand(Inst.getOperand(1));
990  TmpInst.addOperand(MCOperand::createImm(32 - B));
991  TmpInst.addOperand(MCOperand::createImm(B));
992  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
993  Inst = TmpInst;
994  break;
995  }
996  case PPC::INSRWI:
997  case PPC::INSRWIo: {
998  MCInst TmpInst;
999  int64_t N = Inst.getOperand(2).getImm();
1000  int64_t B = Inst.getOperand(3).getImm();
1001  TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
1002  TmpInst.addOperand(Inst.getOperand(0));
1003  TmpInst.addOperand(Inst.getOperand(0));
1004  TmpInst.addOperand(Inst.getOperand(1));
1005  TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
1006  TmpInst.addOperand(MCOperand::createImm(B));
1007  TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
1008  Inst = TmpInst;
1009  break;
1010  }
1011  case PPC::ROTRWI:
1012  case PPC::ROTRWIo: {
1013  MCInst TmpInst;
1014  int64_t N = Inst.getOperand(2).getImm();
1015  TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
1016  TmpInst.addOperand(Inst.getOperand(0));
1017  TmpInst.addOperand(Inst.getOperand(1));
1018  TmpInst.addOperand(MCOperand::createImm(32 - N));
1019  TmpInst.addOperand(MCOperand::createImm(0));
1020  TmpInst.addOperand(MCOperand::createImm(31));
1021  Inst = TmpInst;
1022  break;
1023  }
1024  case PPC::SLWI:
1025  case PPC::SLWIo: {
1026  MCInst TmpInst;
1027  int64_t N = Inst.getOperand(2).getImm();
1028  TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
1029  TmpInst.addOperand(Inst.getOperand(0));
1030  TmpInst.addOperand(Inst.getOperand(1));
1031  TmpInst.addOperand(MCOperand::createImm(N));
1032  TmpInst.addOperand(MCOperand::createImm(0));
1033  TmpInst.addOperand(MCOperand::createImm(31 - N));
1034  Inst = TmpInst;
1035  break;
1036  }
1037  case PPC::SRWI:
1038  case PPC::SRWIo: {
1039  MCInst TmpInst;
1040  int64_t N = Inst.getOperand(2).getImm();
1041  TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1042  TmpInst.addOperand(Inst.getOperand(0));
1043  TmpInst.addOperand(Inst.getOperand(1));
1044  TmpInst.addOperand(MCOperand::createImm(32 - N));
1045  TmpInst.addOperand(MCOperand::createImm(N));
1046  TmpInst.addOperand(MCOperand::createImm(31));
1047  Inst = TmpInst;
1048  break;
1049  }
1050  case PPC::CLRRWI:
1051  case PPC::CLRRWIo: {
1052  MCInst TmpInst;
1053  int64_t N = Inst.getOperand(2).getImm();
1054  TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1055  TmpInst.addOperand(Inst.getOperand(0));
1056  TmpInst.addOperand(Inst.getOperand(1));
1057  TmpInst.addOperand(MCOperand::createImm(0));
1058  TmpInst.addOperand(MCOperand::createImm(0));
1059  TmpInst.addOperand(MCOperand::createImm(31 - N));
1060  Inst = TmpInst;
1061  break;
1062  }
1063  case PPC::CLRLSLWI:
1064  case PPC::CLRLSLWIo: {
1065  MCInst TmpInst;
1066  int64_t B = Inst.getOperand(2).getImm();
1067  int64_t N = Inst.getOperand(3).getImm();
1068  TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1069  TmpInst.addOperand(Inst.getOperand(0));
1070  TmpInst.addOperand(Inst.getOperand(1));
1071  TmpInst.addOperand(MCOperand::createImm(N));
1072  TmpInst.addOperand(MCOperand::createImm(B - N));
1073  TmpInst.addOperand(MCOperand::createImm(31 - N));
1074  Inst = TmpInst;
1075  break;
1076  }
1077  case PPC::EXTLDI:
1078  case PPC::EXTLDIo: {
1079  MCInst TmpInst;
1080  int64_t N = Inst.getOperand(2).getImm();
1081  int64_t B = Inst.getOperand(3).getImm();
1082  TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1083  TmpInst.addOperand(Inst.getOperand(0));
1084  TmpInst.addOperand(Inst.getOperand(1));
1085  TmpInst.addOperand(MCOperand::createImm(B));
1086  TmpInst.addOperand(MCOperand::createImm(N - 1));
1087  Inst = TmpInst;
1088  break;
1089  }
1090  case PPC::EXTRDI:
1091  case PPC::EXTRDIo: {
1092  MCInst TmpInst;
1093  int64_t N = Inst.getOperand(2).getImm();
1094  int64_t B = Inst.getOperand(3).getImm();
1095  TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1096  TmpInst.addOperand(Inst.getOperand(0));
1097  TmpInst.addOperand(Inst.getOperand(1));
1098  TmpInst.addOperand(MCOperand::createImm(B + N));
1099  TmpInst.addOperand(MCOperand::createImm(64 - N));
1100  Inst = TmpInst;
1101  break;
1102  }
1103  case PPC::INSRDI:
1104  case PPC::INSRDIo: {
1105  MCInst TmpInst;
1106  int64_t N = Inst.getOperand(2).getImm();
1107  int64_t B = Inst.getOperand(3).getImm();
1108  TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1109  TmpInst.addOperand(Inst.getOperand(0));
1110  TmpInst.addOperand(Inst.getOperand(0));
1111  TmpInst.addOperand(Inst.getOperand(1));
1112  TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1113  TmpInst.addOperand(MCOperand::createImm(B));
1114  Inst = TmpInst;
1115  break;
1116  }
1117  case PPC::ROTRDI:
1118  case PPC::ROTRDIo: {
1119  MCInst TmpInst;
1120  int64_t N = Inst.getOperand(2).getImm();
1121  TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1122  TmpInst.addOperand(Inst.getOperand(0));
1123  TmpInst.addOperand(Inst.getOperand(1));
1124  TmpInst.addOperand(MCOperand::createImm(64 - N));
1125  TmpInst.addOperand(MCOperand::createImm(0));
1126  Inst = TmpInst;
1127  break;
1128  }
1129  case PPC::SLDI:
1130  case PPC::SLDIo: {
1131  MCInst TmpInst;
1132  int64_t N = Inst.getOperand(2).getImm();
1133  TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1134  TmpInst.addOperand(Inst.getOperand(0));
1135  TmpInst.addOperand(Inst.getOperand(1));
1136  TmpInst.addOperand(MCOperand::createImm(N));
1137  TmpInst.addOperand(MCOperand::createImm(63 - N));
1138  Inst = TmpInst;
1139  break;
1140  }
1141  case PPC::SRDI:
1142  case PPC::SRDIo: {
1143  MCInst TmpInst;
1144  int64_t N = Inst.getOperand(2).getImm();
1145  TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1146  TmpInst.addOperand(Inst.getOperand(0));
1147  TmpInst.addOperand(Inst.getOperand(1));
1148  TmpInst.addOperand(MCOperand::createImm(64 - N));
1149  TmpInst.addOperand(MCOperand::createImm(N));
1150  Inst = TmpInst;
1151  break;
1152  }
1153  case PPC::CLRRDI:
1154  case PPC::CLRRDIo: {
1155  MCInst TmpInst;
1156  int64_t N = Inst.getOperand(2).getImm();
1157  TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1158  TmpInst.addOperand(Inst.getOperand(0));
1159  TmpInst.addOperand(Inst.getOperand(1));
1160  TmpInst.addOperand(MCOperand::createImm(0));
1161  TmpInst.addOperand(MCOperand::createImm(63 - N));
1162  Inst = TmpInst;
1163  break;
1164  }
1165  case PPC::CLRLSLDI:
1166  case PPC::CLRLSLDIo: {
1167  MCInst TmpInst;
1168  int64_t B = Inst.getOperand(2).getImm();
1169  int64_t N = Inst.getOperand(3).getImm();
1170  TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1171  TmpInst.addOperand(Inst.getOperand(0));
1172  TmpInst.addOperand(Inst.getOperand(1));
1173  TmpInst.addOperand(MCOperand::createImm(N));
1174  TmpInst.addOperand(MCOperand::createImm(B - N));
1175  Inst = TmpInst;
1176  break;
1177  }
1178  case PPC::RLWINMbm:
1179  case PPC::RLWINMobm: {
1180  unsigned MB, ME;
1181  int64_t BM = Inst.getOperand(3).getImm();
1182  if (!isRunOfOnes(BM, MB, ME))
1183  break;
1184 
1185  MCInst TmpInst;
1186  TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1187  TmpInst.addOperand(Inst.getOperand(0));
1188  TmpInst.addOperand(Inst.getOperand(1));
1189  TmpInst.addOperand(Inst.getOperand(2));
1190  TmpInst.addOperand(MCOperand::createImm(MB));
1191  TmpInst.addOperand(MCOperand::createImm(ME));
1192  Inst = TmpInst;
1193  break;
1194  }
1195  case PPC::RLWIMIbm:
1196  case PPC::RLWIMIobm: {
1197  unsigned MB, ME;
1198  int64_t BM = Inst.getOperand(3).getImm();
1199  if (!isRunOfOnes(BM, MB, ME))
1200  break;
1201 
1202  MCInst TmpInst;
1203  TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1204  TmpInst.addOperand(Inst.getOperand(0));
1205  TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1206  TmpInst.addOperand(Inst.getOperand(1));
1207  TmpInst.addOperand(Inst.getOperand(2));
1208  TmpInst.addOperand(MCOperand::createImm(MB));
1209  TmpInst.addOperand(MCOperand::createImm(ME));
1210  Inst = TmpInst;
1211  break;
1212  }
1213  case PPC::RLWNMbm:
1214  case PPC::RLWNMobm: {
1215  unsigned MB, ME;
1216  int64_t BM = Inst.getOperand(3).getImm();
1217  if (!isRunOfOnes(BM, MB, ME))
1218  break;
1219 
1220  MCInst TmpInst;
1221  TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1222  TmpInst.addOperand(Inst.getOperand(0));
1223  TmpInst.addOperand(Inst.getOperand(1));
1224  TmpInst.addOperand(Inst.getOperand(2));
1225  TmpInst.addOperand(MCOperand::createImm(MB));
1226  TmpInst.addOperand(MCOperand::createImm(ME));
1227  Inst = TmpInst;
1228  break;
1229  }
1230  case PPC::MFTB: {
1231  if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1232  assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1233  Inst.setOpcode(PPC::MFSPR);
1234  }
1235  break;
1236  }
1237  case PPC::CP_COPYx:
1238  case PPC::CP_COPY_FIRST: {
1239  MCInst TmpInst;
1240  TmpInst.setOpcode(PPC::CP_COPY);
1241  TmpInst.addOperand(Inst.getOperand(0));
1242  TmpInst.addOperand(Inst.getOperand(1));
1243  TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1244 
1245  Inst = TmpInst;
1246  break;
1247  }
1248  case PPC::CP_PASTEx :
1249  case PPC::CP_PASTE_LAST: {
1250  MCInst TmpInst;
1251  TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1252  PPC::CP_PASTE : PPC::CP_PASTEo);
1253  TmpInst.addOperand(Inst.getOperand(0));
1254  TmpInst.addOperand(Inst.getOperand(1));
1255  TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1256 
1257  Inst = TmpInst;
1258  break;
1259  }
1260  }
1261 }
1262 
1263 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1264  OperandVector &Operands,
1265  MCStreamer &Out, uint64_t &ErrorInfo,
1266  bool MatchingInlineAsm) {
1267  MCInst Inst;
1268 
1269  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1270  case Match_Success:
1271  // Post-process instructions (typically extended mnemonics)
1272  ProcessInstruction(Inst, Operands);
1273  Inst.setLoc(IDLoc);
1274  Out.EmitInstruction(Inst, getSTI());
1275  return false;
1276  case Match_MissingFeature:
1277  return Error(IDLoc, "instruction use requires an option to be enabled");
1278  case Match_MnemonicFail:
1279  return Error(IDLoc, "unrecognized instruction mnemonic");
1280  case Match_InvalidOperand: {
1281  SMLoc ErrorLoc = IDLoc;
1282  if (ErrorInfo != ~0ULL) {
1283  if (ErrorInfo >= Operands.size())
1284  return Error(IDLoc, "too few operands for instruction");
1285 
1286  ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1287  if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1288  }
1289 
1290  return Error(ErrorLoc, "invalid operand for instruction");
1291  }
1292  }
1293 
1294  llvm_unreachable("Implement any new match types added!");
1295 }
1296 
1297 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1298  if (getParser().getTok().is(AsmToken::Identifier)) {
1299  StringRef Name = getParser().getTok().getString();
1300  if (Name.equals_lower("lr")) {
1301  RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1302  IntVal = 8;
1303  } else if (Name.equals_lower("ctr")) {
1304  RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1305  IntVal = 9;
1306  } else if (Name.equals_lower("vrsave")) {
1307  RegNo = PPC::VRSAVE;
1308  IntVal = 256;
1309  } else if (Name.startswith_lower("r") &&
1310  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1311  RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1312  } else if (Name.startswith_lower("f") &&
1313  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1314  RegNo = FRegs[IntVal];
1315  } else if (Name.startswith_lower("vs") &&
1316  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1317  RegNo = VSRegs[IntVal];
1318  } else if (Name.startswith_lower("v") &&
1319  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1320  RegNo = VRegs[IntVal];
1321  } else if (Name.startswith_lower("q") &&
1322  !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1323  RegNo = QFRegs[IntVal];
1324  } else if (Name.startswith_lower("cr") &&
1325  !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1326  RegNo = CRRegs[IntVal];
1327  } else
1328  return true;
1329  getParser().Lex();
1330  return false;
1331  }
1332  return true;
1333 }
1334 
1335 bool PPCAsmParser::
1336 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1337  const AsmToken &Tok = getParser().getTok();
1338  StartLoc = Tok.getLoc();
1339  EndLoc = Tok.getEndLoc();
1340  RegNo = 0;
1341  int64_t IntVal;
1342  if (MatchRegisterName(RegNo, IntVal))
1343  return TokError("invalid register name");
1344  return false;
1345 }
1346 
1347 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1348 /// the expression and check for VK_PPC_LO/HI/HA
1349 /// symbol variants. If all symbols with modifier use the same
1350 /// variant, return the corresponding PPCMCExpr::VariantKind,
1351 /// and a modified expression using the default symbol variant.
1352 /// Otherwise, return NULL.
1353 const MCExpr *PPCAsmParser::
1354 ExtractModifierFromExpr(const MCExpr *E,
1355  PPCMCExpr::VariantKind &Variant) {
1356  MCContext &Context = getParser().getContext();
1357  Variant = PPCMCExpr::VK_PPC_None;
1358 
1359  switch (E->getKind()) {
1360  case MCExpr::Target:
1361  case MCExpr::Constant:
1362  return nullptr;
1363 
1364  case MCExpr::SymbolRef: {
1365  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1366 
1367  switch (SRE->getKind()) {
1369  Variant = PPCMCExpr::VK_PPC_LO;
1370  break;
1372  Variant = PPCMCExpr::VK_PPC_HI;
1373  break;
1375  Variant = PPCMCExpr::VK_PPC_HA;
1376  break;
1378  Variant = PPCMCExpr::VK_PPC_HIGHER;
1379  break;
1381  Variant = PPCMCExpr::VK_PPC_HIGHERA;
1382  break;
1384  Variant = PPCMCExpr::VK_PPC_HIGHEST;
1385  break;
1387  Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1388  break;
1389  default:
1390  return nullptr;
1391  }
1392 
1393  return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1394  }
1395 
1396  case MCExpr::Unary: {
1397  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1398  const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1399  if (!Sub)
1400  return nullptr;
1401  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1402  }
1403 
1404  case MCExpr::Binary: {
1405  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1406  PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1407  const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1408  const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1409 
1410  if (!LHS && !RHS)
1411  return nullptr;
1412 
1413  if (!LHS) LHS = BE->getLHS();
1414  if (!RHS) RHS = BE->getRHS();
1415 
1416  if (LHSVariant == PPCMCExpr::VK_PPC_None)
1417  Variant = RHSVariant;
1418  else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1419  Variant = LHSVariant;
1420  else if (LHSVariant == RHSVariant)
1421  Variant = LHSVariant;
1422  else
1423  return nullptr;
1424 
1425  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1426  }
1427  }
1428 
1429  llvm_unreachable("Invalid expression kind!");
1430 }
1431 
1432 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1433 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1434 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1435 /// FIXME: This is a hack.
1436 const MCExpr *PPCAsmParser::
1437 FixupVariantKind(const MCExpr *E) {
1438  MCContext &Context = getParser().getContext();
1439 
1440  switch (E->getKind()) {
1441  case MCExpr::Target:
1442  case MCExpr::Constant:
1443  return E;
1444 
1445  case MCExpr::SymbolRef: {
1446  const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1448 
1449  switch (SRE->getKind()) {
1452  break;
1455  break;
1456  default:
1457  return E;
1458  }
1459  return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1460  }
1461 
1462  case MCExpr::Unary: {
1463  const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1464  const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1465  if (Sub == UE->getSubExpr())
1466  return E;
1467  return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1468  }
1469 
1470  case MCExpr::Binary: {
1471  const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1472  const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1473  const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1474  if (LHS == BE->getLHS() && RHS == BE->getRHS())
1475  return E;
1476  return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1477  }
1478  }
1479 
1480  llvm_unreachable("Invalid expression kind!");
1481 }
1482 
1483 /// ParseExpression. This differs from the default "parseExpression" in that
1484 /// it handles modifiers.
1485 bool PPCAsmParser::
1486 ParseExpression(const MCExpr *&EVal) {
1487 
1488  if (isDarwin())
1489  return ParseDarwinExpression(EVal);
1490 
1491  // (ELF Platforms)
1492  // Handle \code @l/@ha \endcode
1493  if (getParser().parseExpression(EVal))
1494  return true;
1495 
1496  EVal = FixupVariantKind(EVal);
1497 
1498  PPCMCExpr::VariantKind Variant;
1499  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1500  if (E)
1501  EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1502 
1503  return false;
1504 }
1505 
1506 /// ParseDarwinExpression. (MachO Platforms)
1507 /// This differs from the default "parseExpression" in that it handles detection
1508 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1509 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1510 /// syntax form so it is done here. TODO: Determine if there is merit in
1511 /// arranging for this to be done at a higher level.
1512 bool PPCAsmParser::
1513 ParseDarwinExpression(const MCExpr *&EVal) {
1514  MCAsmParser &Parser = getParser();
1516  switch (getLexer().getKind()) {
1517  default:
1518  break;
1519  case AsmToken::Identifier:
1520  // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1521  // something starting with any other char should be part of the
1522  // asm syntax. If handwritten asm includes an identifier like lo16,
1523  // then all bets are off - but no-one would do that, right?
1524  StringRef poss = Parser.getTok().getString();
1525  if (poss.equals_lower("lo16")) {
1526  Variant = PPCMCExpr::VK_PPC_LO;
1527  } else if (poss.equals_lower("hi16")) {
1528  Variant = PPCMCExpr::VK_PPC_HI;
1529  } else if (poss.equals_lower("ha16")) {
1530  Variant = PPCMCExpr::VK_PPC_HA;
1531  }
1532  if (Variant != PPCMCExpr::VK_PPC_None) {
1533  Parser.Lex(); // Eat the xx16
1534  if (getLexer().isNot(AsmToken::LParen))
1535  return Error(Parser.getTok().getLoc(), "expected '('");
1536  Parser.Lex(); // Eat the '('
1537  }
1538  break;
1539  }
1540 
1541  if (getParser().parseExpression(EVal))
1542  return true;
1543 
1544  if (Variant != PPCMCExpr::VK_PPC_None) {
1545  if (getLexer().isNot(AsmToken::RParen))
1546  return Error(Parser.getTok().getLoc(), "expected ')'");
1547  Parser.Lex(); // Eat the ')'
1548  EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1549  }
1550  return false;
1551 }
1552 
1553 /// ParseOperand
1554 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1555 /// rNN for MachO.
1556 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1557  MCAsmParser &Parser = getParser();
1558  SMLoc S = Parser.getTok().getLoc();
1559  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1560  const MCExpr *EVal;
1561 
1562  // Attempt to parse the next token as an immediate
1563  switch (getLexer().getKind()) {
1564  // Special handling for register names. These are interpreted
1565  // as immediates corresponding to the register number.
1566  case AsmToken::Percent:
1567  Parser.Lex(); // Eat the '%'.
1568  unsigned RegNo;
1569  int64_t IntVal;
1570  if (MatchRegisterName(RegNo, IntVal))
1571  return Error(S, "invalid register name");
1572 
1573  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1574  return false;
1575 
1576  case AsmToken::Identifier:
1577  case AsmToken::LParen:
1578  case AsmToken::Plus:
1579  case AsmToken::Minus:
1580  case AsmToken::Integer:
1581  case AsmToken::Dot:
1582  case AsmToken::Dollar:
1583  case AsmToken::Exclaim:
1584  case AsmToken::Tilde:
1585  // Note that non-register-name identifiers from the compiler will begin
1586  // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1587  // identifiers like r31foo - so we fall through in the event that parsing
1588  // a register name fails.
1589  if (isDarwin()) {
1590  unsigned RegNo;
1591  int64_t IntVal;
1592  if (!MatchRegisterName(RegNo, IntVal)) {
1593  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1594  return false;
1595  }
1596  }
1597  // All other expressions
1598 
1599  if (!ParseExpression(EVal))
1600  break;
1601  // Fall-through
1603  default:
1604  return Error(S, "unknown operand");
1605  }
1606 
1607  // Push the parsed operand into the list of operands
1608  Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1609 
1610  // Check whether this is a TLS call expression
1611  bool TLSCall = false;
1612  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1613  TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1614 
1615  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1616  const MCExpr *TLSSym;
1617 
1618  Parser.Lex(); // Eat the '('.
1619  S = Parser.getTok().getLoc();
1620  if (ParseExpression(TLSSym))
1621  return Error(S, "invalid TLS call expression");
1622  if (getLexer().isNot(AsmToken::RParen))
1623  return Error(Parser.getTok().getLoc(), "missing ')'");
1624  E = Parser.getTok().getLoc();
1625  Parser.Lex(); // Eat the ')'.
1626 
1627  Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1628  }
1629 
1630  // Otherwise, check for D-form memory operands
1631  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1632  Parser.Lex(); // Eat the '('.
1633  S = Parser.getTok().getLoc();
1634 
1635  int64_t IntVal;
1636  switch (getLexer().getKind()) {
1637  case AsmToken::Percent:
1638  Parser.Lex(); // Eat the '%'.
1639  unsigned RegNo;
1640  if (MatchRegisterName(RegNo, IntVal))
1641  return Error(S, "invalid register name");
1642  break;
1643 
1644  case AsmToken::Integer:
1645  if (isDarwin())
1646  return Error(S, "unexpected integer value");
1647  else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1648  IntVal > 31)
1649  return Error(S, "invalid register number");
1650  break;
1651  case AsmToken::Identifier:
1652  if (isDarwin()) {
1653  unsigned RegNo;
1654  if (!MatchRegisterName(RegNo, IntVal)) {
1655  break;
1656  }
1657  }
1659 
1660  default:
1661  return Error(S, "invalid memory operand");
1662  }
1663 
1664  E = Parser.getTok().getLoc();
1665  if (parseToken(AsmToken::RParen, "missing ')'"))
1666  return true;
1667  Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1668  }
1669 
1670  return false;
1671 }
1672 
1673 /// Parse an instruction mnemonic followed by its operands.
1674 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1675  SMLoc NameLoc, OperandVector &Operands) {
1676  // The first operand is the token for the instruction name.
1677  // If the next character is a '+' or '-', we need to add it to the
1678  // instruction name, to match what TableGen is doing.
1679  std::string NewOpcode;
1680  if (parseOptionalToken(AsmToken::Plus)) {
1681  NewOpcode = Name;
1682  NewOpcode += '+';
1683  Name = NewOpcode;
1684  }
1685  if (parseOptionalToken(AsmToken::Minus)) {
1686  NewOpcode = Name;
1687  NewOpcode += '-';
1688  Name = NewOpcode;
1689  }
1690  // If the instruction ends in a '.', we need to create a separate
1691  // token for it, to match what TableGen is doing.
1692  size_t Dot = Name.find('.');
1693  StringRef Mnemonic = Name.slice(0, Dot);
1694  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1695  Operands.push_back(
1696  PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1697  else
1698  Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1699  if (Dot != StringRef::npos) {
1700  SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1701  StringRef DotStr = Name.slice(Dot, StringRef::npos);
1702  if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1703  Operands.push_back(
1704  PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1705  else
1706  Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1707  }
1708 
1709  // If there are no more operands then finish
1710  if (parseOptionalToken(AsmToken::EndOfStatement))
1711  return false;
1712 
1713  // Parse the first operand
1714  if (ParseOperand(Operands))
1715  return true;
1716 
1717  while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1718  if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1719  return true;
1720  }
1721 
1722  // We'll now deal with an unfortunate special case: the syntax for the dcbt
1723  // and dcbtst instructions differs for server vs. embedded cores.
1724  // The syntax for dcbt is:
1725  // dcbt ra, rb, th [server]
1726  // dcbt th, ra, rb [embedded]
1727  // where th can be omitted when it is 0. dcbtst is the same. We take the
1728  // server form to be the default, so swap the operands if we're parsing for
1729  // an embedded core (they'll be swapped again upon printing).
1730  if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1731  Operands.size() == 4 &&
1732  (Name == "dcbt" || Name == "dcbtst")) {
1733  std::swap(Operands[1], Operands[3]);
1734  std::swap(Operands[2], Operands[1]);
1735  }
1736 
1737  return false;
1738 }
1739 
1740 /// ParseDirective parses the PPC specific directives
1741 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1742  StringRef IDVal = DirectiveID.getIdentifier();
1743  if (isDarwin()) {
1744  if (IDVal == ".machine")
1745  ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1746  else
1747  return true;
1748  } else if (IDVal == ".word")
1749  ParseDirectiveWord(2, DirectiveID);
1750  else if (IDVal == ".llong")
1751  ParseDirectiveWord(8, DirectiveID);
1752  else if (IDVal == ".tc")
1753  ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1754  else if (IDVal == ".machine")
1755  ParseDirectiveMachine(DirectiveID.getLoc());
1756  else if (IDVal == ".abiversion")
1757  ParseDirectiveAbiVersion(DirectiveID.getLoc());
1758  else if (IDVal == ".localentry")
1759  ParseDirectiveLocalEntry(DirectiveID.getLoc());
1760  else
1761  return true;
1762  return false;
1763 }
1764 
1765 /// ParseDirectiveWord
1766 /// ::= .word [ expression (, expression)* ]
1767 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1768  auto parseOp = [&]() -> bool {
1769  const MCExpr *Value;
1770  SMLoc ExprLoc = getParser().getTok().getLoc();
1771  if (getParser().parseExpression(Value))
1772  return true;
1773  if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1774  assert(Size <= 8 && "Invalid size");
1775  uint64_t IntValue = MCE->getValue();
1776  if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1777  return Error(ExprLoc, "literal value out of range for '" +
1778  ID.getIdentifier() + "' directive");
1779  getStreamer().EmitIntValue(IntValue, Size);
1780  } else
1781  getStreamer().EmitValue(Value, Size, ExprLoc);
1782  return false;
1783  };
1784 
1785  if (parseMany(parseOp))
1786  return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1787  return false;
1788 }
1789 
1790 /// ParseDirectiveTC
1791 /// ::= .tc [ symbol (, expression)* ]
1792 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1793  MCAsmParser &Parser = getParser();
1794  // Skip TC symbol, which is only used with XCOFF.
1795  while (getLexer().isNot(AsmToken::EndOfStatement)
1796  && getLexer().isNot(AsmToken::Comma))
1797  Parser.Lex();
1798  if (parseToken(AsmToken::Comma))
1799  return addErrorSuffix(" in '.tc' directive");
1800 
1801  // Align to word size.
1802  getParser().getStreamer().EmitValueToAlignment(Size);
1803 
1804  // Emit expressions.
1805  return ParseDirectiveWord(Size, ID);
1806 }
1807 
1808 /// ParseDirectiveMachine (ELF platforms)
1809 /// ::= .machine [ cpu | "push" | "pop" ]
1810 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1811  MCAsmParser &Parser = getParser();
1812  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1813  Parser.getTok().isNot(AsmToken::String))
1814  return Error(L, "unexpected token in '.machine' directive");
1815 
1816  StringRef CPU = Parser.getTok().getIdentifier();
1817 
1818  // FIXME: Right now, the parser always allows any available
1819  // instruction, so the .machine directive is not useful.
1820  // Implement ".machine any" (by doing nothing) for the benefit
1821  // of existing assembler code. Likewise, we can then implement
1822  // ".machine push" and ".machine pop" as no-op.
1823  if (CPU != "any" && CPU != "push" && CPU != "pop")
1824  return TokError("unrecognized machine type");
1825 
1826  Parser.Lex();
1827 
1828  if (parseToken(AsmToken::EndOfStatement))
1829  return addErrorSuffix(" in '.machine' directive");
1830 
1831  PPCTargetStreamer &TStreamer =
1832  *static_cast<PPCTargetStreamer *>(
1833  getParser().getStreamer().getTargetStreamer());
1834  TStreamer.emitMachine(CPU);
1835 
1836  return false;
1837 }
1838 
1839 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1840 /// ::= .machine cpu-identifier
1841 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1842  MCAsmParser &Parser = getParser();
1843  if (Parser.getTok().isNot(AsmToken::Identifier) &&
1844  Parser.getTok().isNot(AsmToken::String))
1845  return Error(L, "unexpected token in directive");
1846 
1847  StringRef CPU = Parser.getTok().getIdentifier();
1848  Parser.Lex();
1849 
1850  // FIXME: this is only the 'default' set of cpu variants.
1851  // However we don't act on this information at present, this is simply
1852  // allowing parsing to proceed with minimal sanity checking.
1853  if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L,
1854  "unrecognized cpu type") ||
1855  check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L,
1856  "wrong cpu type specified for 64bit") ||
1857  check(!isPPC64() && CPU == "ppc64", L,
1858  "wrong cpu type specified for 32bit") ||
1859  parseToken(AsmToken::EndOfStatement))
1860  return addErrorSuffix(" in '.machine' directive");
1861  return false;
1862 }
1863 
1864 /// ParseDirectiveAbiVersion
1865 /// ::= .abiversion constant-expression
1866 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1867  int64_t AbiVersion;
1868  if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1869  "expected constant expression") ||
1870  parseToken(AsmToken::EndOfStatement))
1871  return addErrorSuffix(" in '.abiversion' directive");
1872 
1873  PPCTargetStreamer &TStreamer =
1874  *static_cast<PPCTargetStreamer *>(
1875  getParser().getStreamer().getTargetStreamer());
1876  TStreamer.emitAbiVersion(AbiVersion);
1877 
1878  return false;
1879 }
1880 
1881 /// ParseDirectiveLocalEntry
1882 /// ::= .localentry symbol, expression
1883 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1884  StringRef Name;
1885  if (getParser().parseIdentifier(Name))
1886  return Error(L, "expected identifier in '.localentry' directive");
1887 
1888  MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1889  const MCExpr *Expr;
1890 
1891  if (parseToken(AsmToken::Comma) ||
1892  check(getParser().parseExpression(Expr), L, "expected expression") ||
1893  parseToken(AsmToken::EndOfStatement))
1894  return addErrorSuffix(" in '.localentry' directive");
1895 
1896  PPCTargetStreamer &TStreamer =
1897  *static_cast<PPCTargetStreamer *>(
1898  getParser().getStreamer().getTargetStreamer());
1899  TStreamer.emitLocalEntry(Sym, Expr);
1900 
1901  return false;
1902 }
1903 
1904 
1905 
1906 /// Force static initialization.
1911 }
1912 
1913 #define GET_REGISTER_MATCHER
1914 #define GET_MATCHER_IMPLEMENTATION
1915 #include "PPCGenAsmMatcher.inc"
1916 
1917 // Define this matcher function after the auto-generated include so we
1918 // have the match class enum definitions.
1919 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1920  unsigned Kind) {
1921  // If the kind is a token for a literal immediate, check if our asm
1922  // operand matches. This is for InstAliases which have a fixed-value
1923  // immediate in the syntax.
1924  int64_t ImmVal;
1925  switch (Kind) {
1926  case MCK_0: ImmVal = 0; break;
1927  case MCK_1: ImmVal = 1; break;
1928  case MCK_2: ImmVal = 2; break;
1929  case MCK_3: ImmVal = 3; break;
1930  case MCK_4: ImmVal = 4; break;
1931  case MCK_5: ImmVal = 5; break;
1932  case MCK_6: ImmVal = 6; break;
1933  case MCK_7: ImmVal = 7; break;
1934  default: return Match_InvalidOperand;
1935  }
1936 
1937  PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1938  if (Op.isImm() && Op.getImm() == ImmVal)
1939  return Match_Success;
1940 
1941  return Match_InvalidOperand;
1942 }
1943 
1944 const MCExpr *
1945 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1947  MCContext &Ctx) {
1948  switch (Variant) {
1950  return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1952  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1954  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1956  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1958  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1960  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1962  return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1963  default:
1964  return nullptr;
1965  }
1966 }
MachineLoop * L
static bool isReg(const MCInst &MI, unsigned OpNo)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:494
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:315
static const MCPhysReg XRegsNoX0[32]
void push_back(const T &Elt)
Definition: SmallVector.h:211
static int64_t EvaluateCRExpr(const MCExpr *E)
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx)
Definition: MCExpr.cpp:144
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx)
Definition: MCExpr.h:360
#define R4(n)
LLVMContext & Context
uint64_t Token
const MCSymbol & getSymbol() const
Definition: MCExpr.h:311
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:298
const char * getPointer() const
Definition: SMLoc.h:35
static unsigned MatchRegisterName(StringRef Name)
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:66
static const MCPhysReg VFRegs[32]
static const PPCMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isDarwin, MCContext &Ctx)
Definition: PPCMCExpr.cpp:22
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
MCTargetAsmParser - Generic interface to target specific assembly parsers.
Multiplication.
Definition: MCExpr.h:406
ExprKind getKind() const
Definition: MCExpr.h:70
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:173
Target & getThePPC32Target()
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmLexer.h:114
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static const MCPhysReg VRegs[32]
static const MCPhysReg CRBITRegs[32]
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
bool isNot(TokenKind K) const
Definition: MCAsmLexer.h:87
static const MCPhysReg FRegs[32]
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
#define R2(n)
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:765
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:427
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.cpp:139
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
static const MCPhysReg VSSRegs[64]
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Target independent representation for an assembler token.
Definition: MCAsmLexer.h:25
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:161
Windows NT (Windows on ARM)
static const MCPhysReg CRRegs[8]
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:135
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static const MCPhysReg XRegs[32]
Context object for machine code objects.
Definition: MCContext.h:51
static unsigned QFRegs[32]
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:497
Unary assembler expressions.
Definition: MCExpr.h:335
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)=0
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: StringRef.h:699
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:270
Target & getThePPC64Target()
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
Unary expressions.
Definition: MCExpr.h:40
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isImm() const
Definition: MCInst.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:514
Streaming machine code generation interface.
Definition: MCStreamer.h:161
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:309
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:295
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:399
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:28
virtual void emitAbiVersion(int AbiVersion)=0
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:587
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
void LLVMInitializePowerPCAsmParser()
Force static initialization.
MCExpr const & getExpr(MCExpr const &Expr)
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:366
Binary assembler expressions.
Definition: MCExpr.h:388
void setLoc(SMLoc loc)
Definition: MCInst.h:161
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void setOpcode(unsigned Op)
Definition: MCInst.h:158
#define R6(n)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
unsigned getOpcode() const
Definition: MCInst.h:159
Target & getThePPC64LETarget()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
int64_t getImm() const
Definition: MCInst.h:74
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:37
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:517
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmLexer.h:103
static const MCPhysReg VSRegs[64]
const MCExpr * getSubExpr() const
Get the child of this unary expression.
Definition: MCExpr.h:378
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:199
static const size_t npos
Definition: StringRef.h:51
unsigned getNumOperands() const
Definition: MCInst.h:166
#define N
Opcode getOpcode() const
Get the kind of this binary expression.
Definition: MCExpr.h:511
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:39
Unary minus.
Definition: MCExpr.h:339
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:312
static const MCPhysReg RRegs[32]
const unsigned Kind
VariantKind getKind() const
Definition: MCExpr.h:313
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side...
LLVM Value Representation.
Definition: Value.h:71
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:32
static const MCPhysReg VSFRegs[64]
Constant expressions.
Definition: MCExpr.h:38
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
Binary expressions.
Definition: MCExpr.h:37
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:125
Subtraction.
Definition: MCExpr.h:412
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
Target specific expression.
Definition: MCExpr.h:41
virtual void emitMachine(StringRef CPU)=0
Represents a location in source code.
Definition: SMLoc.h:24
LLVM_NODISCARD bool startswith_lower(StringRef Prefix) const
Check if this string starts with the given Prefix, ignoring case.
Definition: StringRef.cpp:61
bool isUIntN(unsigned N, uint64_t x)
isUIntN - Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:360
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
static const MCPhysReg RRegsNoR0[32]
Opcode getOpcode() const
Get the kind of this unary expression.
Definition: MCExpr.h:375