LLVM  4.0.0
AMDGPUBaseInfo.h
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1 //===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12 
13 #include "AMDKernelCodeT.h"
14 #include "llvm/IR/CallingConv.h"
15 
16 #include "SIDefines.h"
17 
18 #define GET_INSTRINFO_OPERAND_ENUM
19 #include "AMDGPUGenInstrInfo.inc"
20 #undef GET_INSTRINFO_OPERAND_ENUM
21 
22 namespace llvm {
23 
24 class FeatureBitset;
25 class Function;
26 class GlobalValue;
27 class MCContext;
28 class MCInstrDesc;
29 class MCRegisterClass;
30 class MCRegisterInfo;
31 class MCSection;
32 class MCSubtargetInfo;
33 
34 namespace AMDGPU {
35 
37 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
38 
39 struct IsaVersion {
40  unsigned Major;
41  unsigned Minor;
42  unsigned Stepping;
43 };
44 
47  const FeatureBitset &Features);
49 
51 
53 
55 
56 bool isGroupSegment(const GlobalValue *GV);
57 bool isGlobalSegment(const GlobalValue *GV);
58 bool isReadOnlySegment(const GlobalValue *GV);
59 
60 /// \returns True if constants should be emitted to .text section for given
61 /// target triple \p TT, false otherwise.
63 
64 /// \returns Integer value requested using \p F's \p Name attribute.
65 ///
66 /// \returns \p Default if attribute is not present.
67 ///
68 /// \returns \p Default and emits error if requested value cannot be converted
69 /// to integer.
70 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
71 
72 /// \returns A pair of integer values requested using \p F's \p Name attribute
73 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
74 /// is false).
75 ///
76 /// \returns \p Default if attribute is not present.
77 ///
78 /// \returns \p Default and emits error if one of the requested values cannot be
79 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
80 /// not present.
81 std::pair<int, int> getIntegerPairAttribute(const Function &F,
83  std::pair<int, int> Default,
84  bool OnlyFirstRequired = false);
85 
86 /// \returns Waitcnt bit mask for given isa \p Version.
88 
89 /// \returns Vmcnt bit mask for given isa \p Version.
91 
92 /// \returns Expcnt bit mask for given isa \p Version.
94 
95 /// \returns Lgkmcnt bit mask for given isa \p Version.
97 
98 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
99 unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt);
100 
101 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
102 unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt);
103 
104 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
105 unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt);
106 
107 /// \brief Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
108 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
109 /// \p Lgkmcnt respectively.
110 ///
111 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
112 /// \p Vmcnt = \p Waitcnt[3:0]
113 /// \p Expcnt = \p Waitcnt[6:4]
114 /// \p Lgkmcnt = \p Waitcnt[11:8]
115 void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt,
116  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
117 
118 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
119 unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt);
120 
121 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
122 unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt);
123 
124 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
125 unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt);
126 
127 /// \brief Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
128 /// \p Version.
129 ///
130 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
131 /// Waitcnt[3:0] = \p Vmcnt
132 /// Waitcnt[6:4] = \p Expcnt
133 /// Waitcnt[11:8] = \p Lgkmcnt
134 ///
135 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
136 /// isa \p Version.
138  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
139 
140 unsigned getInitialPSInputAddr(const Function &F);
141 
142 bool isShader(CallingConv::ID cc);
143 bool isCompute(CallingConv::ID cc);
144 
145 bool isSI(const MCSubtargetInfo &STI);
146 bool isCI(const MCSubtargetInfo &STI);
147 bool isVI(const MCSubtargetInfo &STI);
148 
149 /// If \p Reg is a pseudo reg, return the correct hardware register given
150 /// \p STI otherwise return \p Reg.
151 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
152 
153 /// \brief Can this operand also contain immediate values?
154 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
155 
156 /// \brief Is this floating-point operand?
157 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
158 
159 /// \brief Does this opearnd support only inlinable literals?
160 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
161 
162 /// \brief Get the size in bits of a register from the register class \p RC.
163 unsigned getRegBitWidth(unsigned RCID);
164 
165 /// \brief Get the size in bits of a register from the register class \p RC.
166 unsigned getRegBitWidth(const MCRegisterClass &RC);
167 
168 /// \brief Get size of register operand
169 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
170  unsigned OpNo);
171 
173 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
174  switch (OpInfo.OperandType) {
179  return 4;
180 
185  return 8;
186 
191  return 2;
192 
193  default:
194  llvm_unreachable("unhandled operand type");
195  }
196 }
197 
199 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
200  return getOperandSize(Desc.OpInfo[OpNo]);
201 }
202 
203 /// \brief Is this literal inlinable
205 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
206 
208 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
209 
211 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
212 
213 } // end namespace AMDGPU
214 } // end namespace llvm
215 
216 #endif
unsigned getExpcntBitMask(IsaVersion Version)
Instances of this class represent a uniqued identifier for a section in the current translation unit...
Definition: MCSection.h:40
unsigned decodeVmcnt(IsaVersion Version, unsigned Waitcnt)
unsigned getVmcntBitMask(IsaVersion Version)
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
MCSection * getHSATextSection(MCContext &Ctx)
MCSection * getHSARodataReadonlyAgentSection(MCContext &Ctx)
unsigned getWaitcntBitMask(IsaVersion Version)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
bool isGlobalSegment(const GlobalValue *GV)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
AMD Kernel Code Object (amd_kernel_code_t).
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned encodeWaitcnt(IsaVersion Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
unsigned encodeExpcnt(IsaVersion Version, unsigned Waitcnt, unsigned Expcnt)
Context object for machine code objects.
Definition: MCContext.h:51
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:82
#define F(x, y, z)
Definition: MD5.cpp:51
bool isGroupSegment(const GlobalValue *GV)
bool isReadOnlySegment(const GlobalValue *GV)
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
MCSection * getHSADataGlobalAgentSection(MCContext &Ctx)
MCSection * getHSADataGlobalProgramSection(MCContext &Ctx)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
bool isSI(const MCSubtargetInfo &STI)
unsigned const MachineRegisterInfo * MRI
IsaVersion getIsaVersion(const FeatureBitset &Features)
bool isShader(CallingConv::ID cc)
bool isCompute(CallingConv::ID cc)
unsigned encodeLgkmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this opearnd support only inlinable literals?
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const FeatureBitset &Features)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Operands with register or inline constant.
Definition: SIDefines.h:99
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned decodeExpcnt(IsaVersion Version, unsigned Waitcnt)
unsigned getLgkmcntBitMask(IsaVersion Version)
void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
unsigned encodeVmcnt(IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeLgkmcnt(IsaVersion Version, unsigned Waitcnt)
bool isCI(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
bool isVI(const MCSubtargetInfo &STI)
#define LLVM_READNONE
Definition: Compiler.h:167
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
MCSubtargetInfo - Generic base class for all target subtargets.
bool shouldEmitConstantsToTextSection(const Triple &TT)
#define LLVM_READONLY
Definition: Compiler.h:174
Operands with register or 32-bit immediate.
Definition: SIDefines.h:91
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
const FeatureBitset Features
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
const uint64_t Version
Definition: InstrProf.h:799