15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H
28 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
29 AArch64::X3, AArch64::X4, AArch64::X5,
30 AArch64::X6, AArch64::X7};
31 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
32 AArch64::H3, AArch64::H4, AArch64::H5,
33 AArch64::H6, AArch64::H7};
35 AArch64::S3, AArch64::S4, AArch64::S5,
36 AArch64::S6, AArch64::S7};
38 AArch64::D3, AArch64::D4, AArch64::D5,
39 AArch64::D6, AArch64::D7};
41 AArch64::Q3, AArch64::Q4, AArch64::Q5,
42 AArch64::Q6, AArch64::Q7};
46 CCState &State,
unsigned SlotAlign) {
52 for (
auto &It : PendingMembers) {
53 It.convertToMem(State.
AllocateStack(Size, std::max(Align, SlotAlign)));
59 PendingMembers.clear();
65 static bool CC_AArch64_Custom_Stack_Block(
78 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8);
84 static bool CC_AArch64_Custom_Block(
unsigned &ValNo,
MVT &ValVT,
MVT &LocVT,
117 for (
auto &It : PendingMembers) {
118 It.convertToReg(RegResult);
122 PendingMembers.clear();
127 for (
auto Reg : RegList)
134 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
void push_back(const T &Elt)
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
unsigned getStackAlignment() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
bool is32BitVector() const
is32BitVector - Return true if this is a 32-bit vector type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
SmallVectorImpl< llvm::CCValAssign > & getPendingLocs()
MachineFunction & getMachineFunction() const
bool isInConsecutiveRegsLast() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
MVT - Machine Value Type.
CCState - This class holds information needed while lowering arguments and return values...
unsigned AllocateRegBlock(ArrayRef< MCPhysReg > Regs, unsigned RegsRequired)
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers.
bool is64BitVector() const
is64BitVector - Return true if this is a 64-bit vector type.
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
bool isTargetDarwin() const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static const MCPhysReg QRegList[]
static const MCPhysReg DRegList[]
unsigned getOrigAlign() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
static const MCPhysReg SRegList[]