LLVM  4.0.0
SIRegisterInfo.h
Go to the documentation of this file.
1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition for SIRegisterInfo
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
17 
18 #include "AMDGPURegisterInfo.h"
19 #include "SIDefines.h"
21 
22 namespace llvm {
23 
24 class SISubtarget;
25 class MachineRegisterInfo;
26 class SIMachineFunctionInfo;
27 
28 class SIRegisterInfo final : public AMDGPURegisterInfo {
29 private:
30  unsigned SGPRSetID;
31  unsigned VGPRSetID;
32  BitVector SGPRPressureSets;
33  BitVector VGPRPressureSets;
34 
35  void reserveRegisterTuples(BitVector &, unsigned Reg) const;
36  void classifyPressureSet(unsigned PSetID, unsigned Reg,
37  BitVector &PressureSets) const;
38 
39 public:
41 
42  /// Return the end register initially reserved for the scratch buffer in case
43  /// spilling is needed.
44  unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
45 
46  /// Return the end register initially reserved for the scratch wave offset in
47  /// case spilling is needed.
49  const MachineFunction &MF) const;
50 
51  BitVector getReservedRegs(const MachineFunction &MF) const override;
52 
53  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
54 
55  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
57  const MachineFunction &MF) const override;
58  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
59  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
60 
61  int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
62 
63  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
64  int Idx) const override;
65 
66  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
67 
69  unsigned BaseReg, int FrameIdx,
70  int64_t Offset) const override;
71 
72  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
73  int64_t Offset) const override;
74 
75  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
76  int64_t Offset) const override;
77 
79  const MachineFunction &MF, unsigned Kind = 0) const override;
80 
82  int FI, RegScavenger *RS) const;
83 
85  int FI, RegScavenger *RS) const;
86 
88  unsigned FIOperandNum,
89  RegScavenger *RS) const override;
90 
91  unsigned getHWRegIndex(unsigned Reg) const {
92  return getEncodingValue(Reg) & 0xff;
93  }
94 
95  /// \brief Return the 'base' register class for this register.
96  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
97  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
98 
99  /// \returns true if this class contains only SGPR registers
100  bool isSGPRClass(const TargetRegisterClass *RC) const {
101  return !hasVGPRs(RC);
102  }
103 
104  /// \returns true if this class ID contains only SGPR registers
105  bool isSGPRClassID(unsigned RCID) const {
106  return isSGPRClass(getRegClass(RCID));
107  }
108 
109  bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
110  const TargetRegisterClass *RC;
112  RC = MRI.getRegClass(Reg);
113  else
114  RC = getPhysRegClass(Reg);
115  return isSGPRClass(RC);
116  }
117 
118  /// \returns true if this class contains VGPR registers.
119  bool hasVGPRs(const TargetRegisterClass *RC) const;
120 
121  /// \returns A VGPR reg class with the same width as \p SRC
123  const TargetRegisterClass *SRC) const;
124 
125  /// \returns A SGPR reg class with the same width as \p SRC
127  const TargetRegisterClass *VRC) const;
128 
129  /// \returns The register class that is used for a sub-register of \p RC for
130  /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
131  /// be returned.
133  unsigned SubIdx) const;
134 
135  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
136  unsigned DefSubReg,
137  const TargetRegisterClass *SrcRC,
138  unsigned SrcSubReg) const override;
139 
140  /// \returns True if operands defined with this operand type can accept
141  /// a literal constant (i.e. any 32-bit immediate).
142  bool opCanUseLiteralConstant(unsigned OpType) const {
143  // TODO: 64-bit operands have extending behavior from 32-bit literal.
144  return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
146  }
147 
148  /// \returns True if operands defined with this operand type can accept
149  /// an inline constant. i.e. An integer value in the range (-16, 64) or
150  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
151  bool opCanUseInlineConstant(unsigned OpType) const {
152  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
153  OpType <= AMDGPU::OPERAND_SRC_LAST;
154  }
155 
157  // SGPRS:
168 
169  // VGPRS:
174  };
175 
176  /// \brief Returns the physical register that \p Value is stored in.
177  unsigned getPreloadedValue(const MachineFunction &MF,
178  enum PreloadedValue Value) const;
179 
181  const TargetRegisterClass *RC,
182  const MachineFunction &MF) const;
183 
184  unsigned getSGPRPressureSet() const { return SGPRSetID; };
185  unsigned getVGPRPressureSet() const { return VGPRSetID; };
186 
188  unsigned Reg) const;
189  bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
190 
191  bool isSGPRPressureSet(unsigned SetID) const {
192  return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
193  }
194  bool isVGPRPressureSet(unsigned SetID) const {
195  return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
196  }
197 
198  /// \returns SGPR allocation granularity supported by the subtarget.
199  unsigned getSGPRAllocGranule() const {
200  return 8;
201  }
202 
203  /// \returns Total number of SGPRs supported by the subtarget.
204  unsigned getTotalNumSGPRs(const SISubtarget &ST) const;
205 
206  /// \returns Number of addressable SGPRs supported by the subtarget.
207  unsigned getNumAddressableSGPRs(const SISubtarget &ST) const;
208 
209  /// \returns Number of reserved SGPRs supported by the subtarget.
210  unsigned getNumReservedSGPRs(const SISubtarget &ST,
211  const SIMachineFunctionInfo &MFI) const;
212 
213  /// \returns Minimum number of SGPRs that meets given number of waves per
214  /// execution unit requirement for given subtarget.
215  unsigned getMinNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU) const;
216 
217  /// \returns Maximum number of SGPRs that meets given number of waves per
218  /// execution unit requirement for given subtarget.
219  unsigned getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU,
220  bool Addressable) const;
221 
222  /// \returns Maximum number of SGPRs that meets number of waves per execution
223  /// unit requirement for function \p MF, or number of SGPRs explicitly
224  /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
225  ///
226  /// \returns Value that meets number of waves per execution unit requirement
227  /// if explicitly requested value cannot be converted to integer, violates
228  /// subtarget's specifications, or does not meet number of waves per execution
229  /// unit requirement.
230  unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
231 
232  /// \returns VGPR allocation granularity supported by the subtarget.
233  unsigned getVGPRAllocGranule() const {
234  return 4;
235  }
236 
237  /// \returns Total number of VGPRs supported by the subtarget.
238  unsigned getTotalNumVGPRs() const {
239  return 256;
240  }
241 
242  /// \returns Number of reserved VGPRs for debugger use supported by the
243  /// subtarget.
244  unsigned getNumDebuggerReservedVGPRs(const SISubtarget &ST) const;
245 
246  /// \returns Minimum number of SGPRs that meets given number of waves per
247  /// execution unit requirement.
248  unsigned getMinNumVGPRs(unsigned WavesPerEU) const;
249 
250  /// \returns Maximum number of VGPRs that meets given number of waves per
251  /// execution unit requirement.
252  unsigned getMaxNumVGPRs(unsigned WavesPerEU) const;
253 
254  /// \returns Maximum number of VGPRs that meets number of waves per execution
255  /// unit requirement for function \p MF, or number of VGPRs explicitly
256  /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
257  ///
258  /// \returns Value that meets number of waves per execution unit requirement
259  /// if explicitly requested value cannot be converted to integer, violates
260  /// subtarget's specifications, or does not meet number of waves per execution
261  /// unit requirement.
262  unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
263 
265  unsigned EltSize) const;
266 
267 private:
268  void buildSpillLoadStore(MachineBasicBlock::iterator MI,
269  unsigned LoadStoreOp,
270  int Index,
271  unsigned ValueReg,
272  bool ValueIsKill,
273  unsigned ScratchRsrcReg,
274  unsigned ScratchOffsetReg,
275  int64_t InstrOffset,
276  MachineMemOperand *MMO,
277  RegScavenger *RS) const;
278 };
279 
280 } // End namespace llvm
281 
282 #endif
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
bool opCanUseInlineConstant(unsigned OpType) const
bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
bool isSGPRPressureSet(unsigned SetID) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
bool isSGPRClass(const TargetRegisterClass *RC) const
unsigned getNumReservedSGPRs(const SISubtarget &ST, const SIMachineFunctionInfo &MFI) const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
unsigned getHWRegIndex(unsigned Reg) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
A description of a memory reference used in the backend.
unsigned getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU, bool Addressable) const
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
static int getRegClass(RegisterKind Is, unsigned RegWidth)
unsigned getVGPRAllocGranule() const
bool opCanUseLiteralConstant(unsigned OpType) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
int64_t getMUBUFInstrOffset(const MachineInstr *MI) const
MachineBasicBlock * MBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
unsigned getVGPRPressureSet() const
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
unsigned const MachineRegisterInfo * MRI
bool hasVGPRs(const TargetRegisterClass *RC) const
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
uint32_t Offset
bool isSGPRClassID(unsigned RCID) const
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getSGPRAllocGranule() const
unsigned getNumAddressableSGPRs(const SISubtarget &ST) const
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
unsigned getNumDebuggerReservedVGPRs(const SISubtarget &ST) const
bool test(unsigned Idx) const
Definition: BitVector.h:323
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
void spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the 'base' register class for this register.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
Returns a register that is not used at any point in the function.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
unsigned getTotalNumSGPRs(const SISubtarget &ST) const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
unsigned getSGPRPressureSet() const
unsigned getMinNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU) const
const unsigned Kind
bool isVGPRPressureSet(unsigned SetID) const
LLVM Value Representation.
Definition: Value.h:71
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
IRTranslator LLVM IR MI
unsigned getTotalNumVGPRs() const