55 unsigned FlatScratchInitReg
63 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
64 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
67 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
74 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
75 .addReg(FlatScrInitLo)
76 .
addReg(ScratchWaveOffsetReg);
79 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
84 unsigned SIFrameLowering::getReservedPrivateSegmentBufferReg(
93 if (ScratchRsrcReg == AMDGPU::NoRegister)
94 return AMDGPU::NoRegister;
98 return ScratchRsrcReg;
115 AllSGPR128s = AllSGPR128s.
slice(
std::min(static_cast<unsigned>(AllSGPR128s.
size()), NumPreloaded));
130 return ScratchRsrcReg;
133 unsigned SIFrameLowering::getReservedPrivateSegmentWaveByteOffsetReg(
142 return ScratchWaveOffsetReg;
150 if (NumPreloaded > AllSGPRs.
size())
151 return ScratchWaveOffsetReg;
153 AllSGPRs = AllSGPRs.
slice(NumPreloaded);
168 if (AllSGPRs.
size() < 13)
169 return ScratchWaveOffsetReg;
176 TRI->isSubRegisterEq(ScratchRsrcReg,
Reg))
185 return ScratchWaveOffsetReg;
194 emitDebuggerPrologue(MF, MBB);
196 assert(&MF.
front() == &MBB &&
"Shrink-wrapping not yet supported");
210 unsigned ScratchRsrcReg
211 = getReservedPrivateSegmentBufferReg(ST, TII, TRI, MFI, MF);
212 unsigned ScratchWaveOffsetReg
213 = getReservedPrivateSegmentWaveByteOffsetReg(ST, TII, TRI, MFI, MF);
215 if (ScratchRsrcReg == AMDGPU::NoRegister) {
216 assert(ScratchWaveOffsetReg == AMDGPU::NoRegister);
220 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg));
232 emitFlatScratchInit(TII, TRI, MF, MBB);
239 unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister;
245 bool OffsetRegUsed = !MRI.
use_empty(ScratchWaveOffsetReg);
246 bool ResourceRegUsed = !MRI.
use_empty(ScratchRsrcReg);
251 assert(PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister &&
252 "scratch wave offset input is required");
253 MRI.
addLiveIn(PreloadedScratchWaveOffsetReg);
254 MBB.
addLiveIn(PreloadedScratchWaveOffsetReg);
257 if (ResourceRegUsed && PreloadedPrivateBufferReg != AMDGPU::NoRegister) {
259 MRI.
addLiveIn(PreloadedPrivateBufferReg);
260 MBB.
addLiveIn(PreloadedPrivateBufferReg);
265 if (&OtherBB == &MBB)
269 OtherBB.addLiveIn(ScratchWaveOffsetReg);
272 OtherBB.addLiveIn(ScratchRsrcReg);
281 bool CopyBuffer = ResourceRegUsed &&
282 PreloadedPrivateBufferReg != AMDGPU::NoRegister &&
284 ScratchRsrcReg != PreloadedPrivateBufferReg;
289 bool CopyBufferFirst = TRI->isSubRegisterEq(PreloadedPrivateBufferReg,
290 ScratchWaveOffsetReg);
291 if (CopyBuffer && CopyBufferFirst) {
292 BuildMI(MBB, I, DL, TII->
get(AMDGPU::COPY), ScratchRsrcReg)
297 PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg) {
298 BuildMI(MBB, I, DL, TII->
get(AMDGPU::COPY), ScratchWaveOffsetReg)
302 if (CopyBuffer && !CopyBufferFirst) {
303 BuildMI(MBB, I, DL, TII->
get(AMDGPU::COPY), ScratchRsrcReg)
307 if (ResourceRegUsed && (ST.
isMesaGfxShader(MF) || (PreloadedPrivateBufferReg == AMDGPU::NoRegister))) {
309 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
311 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
312 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
315 uint64_t Rsrc23 = TII->getScratchRsrcWords23();
317 if (MFI->hasPrivateMemoryInputPtr()) {
318 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
321 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);
323 BuildMI(MBB, I, DL, Mov64, Rsrc01)
324 .
addReg(PreloadedPrivateBufferReg)
327 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
333 auto MMO = MF.getMachineMemOperand(PtrInfo,
338 BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01)
339 .
addReg(PreloadedPrivateBufferReg)
346 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
347 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
349 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
353 BuildMI(MBB, I, DL, SMovB32, Rsrc1)
359 BuildMI(MBB, I, DL, SMovB32, Rsrc2)
360 .
addImm(Rsrc23 & 0xffffffff)
363 BuildMI(MBB, I, DL, SMovB32, Rsrc3)
384 assert((RS || !MayNeedScavengingEmergencySlot) &&
385 "RegScavenger required if spilling");
387 if (MayNeedScavengingEmergencySlot) {
389 AMDGPU::SGPR_32RegClass.getSize(),
406 for (
unsigned i = 0;
i < 3; ++
i) {
414 unsigned WorkGroupIDVGPR =
416 BuildMI(MBB, I, DL, TII->
get(AMDGPU::V_MOV_B32_e32), WorkGroupIDVGPR)
417 .addReg(WorkGroupIDSGPR);
421 TII->storeRegToStackSlot(MBB, I, WorkGroupIDVGPR,
false,
422 WorkGroupIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);
431 TII->storeRegToStackSlot(MBB, I, WorkItemIDVGPR,
false,
432 WorkItemIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);
Interface definition for SIRegisterInfo.
int getDebuggerWorkGroupIDStackObjectIndex(unsigned Dim) const
AMDGPU specific subclass of TargetSubtarget.
unsigned getNumPreloadedSGPRs() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
static ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF, const SIRegisterInfo *TRI)
Describe properties that are true of each instruction in the target description file.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
const SIInstrInfo * getInstrInfo() const override
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space...
static ArrayRef< MCPhysReg > getAllSGPRs(const MachineFunction &MF, const SIRegisterInfo *TRI)
unsigned getScratchWaveOffsetReg() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const_iterator begin(StringRef path)
Get begin iterator over path.
static IntegerType * getInt64Ty(LLVMContext &C)
bool isAmdCodeObjectV2(const MachineFunction &MF) const
unsigned getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses...
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
void setScratchRSrcReg(unsigned Reg)
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
unsigned getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU, bool Addressable) const
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Reg
All possible values of the reg field in the ModR/M byte.
The memory access is dereferenceable (i.e., doesn't trap).
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool isMesaGfxShader(const MachineFunction &MF) const
unsigned getWorkItemIDVGPR(unsigned Dim) const
const MachineBasicBlock & front() const
static unsigned getAlignment(GlobalVariable *GV)
bool hasStackObjects() const
Return true if there are any stack objects in this function.
int getDebuggerWorkItemIDStackObjectIndex(unsigned Dim) const
unsigned getWorkGroupIDSGPR(unsigned Dim) const
size_t size() const
size - Get the array size.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
Class to represent pointers.
bool hasSGPRInitBug() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
Address space for constant memory (VTX2)
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
ArrayRef< T > drop_back(size_t N=1) const
Drop the last N elements of the array.
bool isCompute(CallingConv::ID cc)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
void setScratchWaveOffsetReg(unsigned Reg)
This class contains a discriminated union of information about pointers in memory operands...
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
The memory access always returns the same value (or traps).
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool debuggerEmitPrologue() const
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.