55 class X86MCInstLower {
89 CurrentShadowSize += Code.
size();
90 if (CurrentShadowSize >= RequiredShadowSize)
95 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
97 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
99 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
104 void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
111 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
137 Suffix =
"$non_lazy_ptr";
149 }
else if (MO.
isMBB()) {
156 Sym = Ctx.getOrCreateSymbol(Name);
184 const MCExpr *Expr =
nullptr;
197 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
199 Expr = MCBinaryExpr::createSub(Expr,
200 MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
215 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT;
break;
217 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT;
break;
220 Expr = MCSymbolRefExpr::create(Sym, Ctx);
222 Expr = MCBinaryExpr::createSub(Expr,
223 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
226 assert(MAI.doesSetDirectiveSuppressReloc());
233 Expr = MCSymbolRefExpr::create(Label, Ctx);
239 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
242 Expr = MCBinaryExpr::createAdd(Expr,
243 MCConstantExpr::create(MO.
getOffset(), Ctx),
245 return MCOperand::createExpr(Expr);
261 if (Reg !=
X86::AL && Reg != X86::AX && Reg !=
X86::EAX && Reg != X86::RAX)
274 unsigned NewOpcode = 0;
279 case X86::MOVSX16rr8:
280 if (Op0 == X86::AX && Op1 ==
X86::AL)
281 NewOpcode = X86::CBW;
283 case X86::MOVSX32rr16:
284 if (Op0 ==
X86::EAX && Op1 == X86::AX)
285 NewOpcode = X86::CWDE;
287 case X86::MOVSX64rr32:
288 if (Op0 == X86::RAX && Op1 ==
X86::EAX)
289 NewOpcode = X86::CDQE;
293 if (NewOpcode != 0) {
308 unsigned AddrBase = IsStore;
309 unsigned RegOp = IsStore ? 0 : 5;
310 unsigned AddrOp = AddrBase + 3;
318 "Unexpected instruction!");
322 if (Reg !=
X86::AL && Reg != X86::AX && Reg !=
X86::EAX && Reg != X86::RAX)
332 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
352 return Subtarget.
is64Bit() ? X86::RETQ : X86::RETL;
362 case MachineOperand::MO_Register:
366 return MCOperand::createReg(MO.
getReg());
367 case MachineOperand::MO_Immediate:
368 return MCOperand::createImm(MO.
getImm());
369 case MachineOperand::MO_MachineBasicBlock:
370 case MachineOperand::MO_GlobalAddress:
371 case MachineOperand::MO_ExternalSymbol:
373 case MachineOperand::MO_MCSymbol:
375 case MachineOperand::MO_JumpTableIndex:
377 case MachineOperand::MO_ConstantPoolIndex:
379 case MachineOperand::MO_BlockAddress:
382 case MachineOperand::MO_RegisterMask:
392 if (
auto MaybeMCOp = LowerMachineOperand(MI, MO))
404 "Unexpected # of LEA operands");
406 "LEA has segment specified!");
411 case X86::VMOVZPQILo2PQIrr:
413 case X86::VMOVAPDYrr:
415 case X86::VMOVAPSYrr:
417 case X86::VMOVDQAYrr:
419 case X86::VMOVDQUYrr:
421 case X86::VMOVUPDYrr:
423 case X86::VMOVUPSYrr: {
429 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr;
break;
430 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV;
break;
431 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV;
break;
432 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV;
break;
433 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV;
break;
434 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV;
break;
435 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV;
break;
436 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV;
break;
437 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV;
break;
438 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV;
break;
439 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV;
break;
440 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV;
break;
441 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV;
break;
448 case X86::VMOVSSrr: {
454 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV;
break;
455 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV;
break;
465 case X86::TAILJMPr64:
466 case X86::TAILJMPr64_REX:
468 case X86::CALL64pcrel32: {
478 case X86::EH_RETURN64: {
497 OutMI.
addOperand(MCOperand::createReg(ReturnReg));
503 case X86::TAILJMPr: Opcode = X86::JMP32r;
goto SetTailJmpOpcode;
505 case X86::TAILJMPd64: Opcode = X86::JMP_1;
goto SetTailJmpOpcode;
524 case X86::DEC16r: Opcode = X86::DEC16r_alt;
break;
525 case X86::DEC32r: Opcode = X86::DEC32r_alt;
break;
526 case X86::INC16r: Opcode = X86::INC16r_alt;
break;
527 case X86::INC32r: Opcode = X86::INC32r_alt;
break;
536 case X86::ADD16rr_DB: OutMI.
setOpcode(X86::OR16rr);
goto ReSimplify;
537 case X86::ADD32rr_DB: OutMI.
setOpcode(X86::OR32rr);
goto ReSimplify;
538 case X86::ADD64rr_DB: OutMI.
setOpcode(X86::OR64rr);
goto ReSimplify;
539 case X86::ADD16ri_DB: OutMI.
setOpcode(X86::OR16ri);
goto ReSimplify;
540 case X86::ADD32ri_DB: OutMI.
setOpcode(X86::OR32ri);
goto ReSimplify;
541 case X86::ADD64ri32_DB: OutMI.
setOpcode(X86::OR64ri32);
goto ReSimplify;
542 case X86::ADD16ri8_DB: OutMI.
setOpcode(X86::OR16ri8);
goto ReSimplify;
543 case X86::ADD32ri8_DB: OutMI.
setOpcode(X86::OR32ri8);
goto ReSimplify;
544 case X86::ADD64ri8_DB: OutMI.
setOpcode(X86::OR64ri8);
goto ReSimplify;
549 case X86::ACQUIRE_MOV8rm: OutMI.
setOpcode(X86::MOV8rm);
goto ReSimplify;
550 case X86::ACQUIRE_MOV16rm: OutMI.
setOpcode(X86::MOV16rm);
goto ReSimplify;
551 case X86::ACQUIRE_MOV32rm: OutMI.
setOpcode(X86::MOV32rm);
goto ReSimplify;
552 case X86::ACQUIRE_MOV64rm: OutMI.
setOpcode(X86::MOV64rm);
goto ReSimplify;
553 case X86::RELEASE_MOV8mr: OutMI.
setOpcode(X86::MOV8mr);
goto ReSimplify;
554 case X86::RELEASE_MOV16mr: OutMI.
setOpcode(X86::MOV16mr);
goto ReSimplify;
555 case X86::RELEASE_MOV32mr: OutMI.
setOpcode(X86::MOV32mr);
goto ReSimplify;
556 case X86::RELEASE_MOV64mr: OutMI.
setOpcode(X86::MOV64mr);
goto ReSimplify;
557 case X86::RELEASE_MOV8mi: OutMI.
setOpcode(X86::MOV8mi);
goto ReSimplify;
558 case X86::RELEASE_MOV16mi: OutMI.
setOpcode(X86::MOV16mi);
goto ReSimplify;
559 case X86::RELEASE_MOV32mi: OutMI.
setOpcode(X86::MOV32mi);
goto ReSimplify;
560 case X86::RELEASE_MOV64mi32: OutMI.
setOpcode(X86::MOV64mi32);
goto ReSimplify;
561 case X86::RELEASE_ADD8mi: OutMI.
setOpcode(X86::ADD8mi);
goto ReSimplify;
562 case X86::RELEASE_ADD8mr: OutMI.
setOpcode(X86::ADD8mr);
goto ReSimplify;
563 case X86::RELEASE_ADD32mi: OutMI.
setOpcode(X86::ADD32mi);
goto ReSimplify;
564 case X86::RELEASE_ADD32mr: OutMI.
setOpcode(X86::ADD32mr);
goto ReSimplify;
565 case X86::RELEASE_ADD64mi32: OutMI.
setOpcode(X86::ADD64mi32);
goto ReSimplify;
566 case X86::RELEASE_ADD64mr: OutMI.
setOpcode(X86::ADD64mr);
goto ReSimplify;
567 case X86::RELEASE_AND8mi: OutMI.
setOpcode(X86::AND8mi);
goto ReSimplify;
568 case X86::RELEASE_AND8mr: OutMI.
setOpcode(X86::AND8mr);
goto ReSimplify;
569 case X86::RELEASE_AND32mi: OutMI.
setOpcode(X86::AND32mi);
goto ReSimplify;
570 case X86::RELEASE_AND32mr: OutMI.
setOpcode(X86::AND32mr);
goto ReSimplify;
571 case X86::RELEASE_AND64mi32: OutMI.
setOpcode(X86::AND64mi32);
goto ReSimplify;
572 case X86::RELEASE_AND64mr: OutMI.
setOpcode(X86::AND64mr);
goto ReSimplify;
573 case X86::RELEASE_OR8mi: OutMI.
setOpcode(X86::OR8mi);
goto ReSimplify;
574 case X86::RELEASE_OR8mr: OutMI.
setOpcode(X86::OR8mr);
goto ReSimplify;
575 case X86::RELEASE_OR32mi: OutMI.
setOpcode(X86::OR32mi);
goto ReSimplify;
576 case X86::RELEASE_OR32mr: OutMI.
setOpcode(X86::OR32mr);
goto ReSimplify;
577 case X86::RELEASE_OR64mi32: OutMI.
setOpcode(X86::OR64mi32);
goto ReSimplify;
578 case X86::RELEASE_OR64mr: OutMI.
setOpcode(X86::OR64mr);
goto ReSimplify;
579 case X86::RELEASE_XOR8mi: OutMI.
setOpcode(X86::XOR8mi);
goto ReSimplify;
580 case X86::RELEASE_XOR8mr: OutMI.
setOpcode(X86::XOR8mr);
goto ReSimplify;
581 case X86::RELEASE_XOR32mi: OutMI.
setOpcode(X86::XOR32mi);
goto ReSimplify;
582 case X86::RELEASE_XOR32mr: OutMI.
setOpcode(X86::XOR32mr);
goto ReSimplify;
583 case X86::RELEASE_XOR64mi32: OutMI.
setOpcode(X86::XOR64mi32);
goto ReSimplify;
584 case X86::RELEASE_XOR64mr: OutMI.
setOpcode(X86::XOR64mr);
goto ReSimplify;
585 case X86::RELEASE_INC8m: OutMI.
setOpcode(X86::INC8m);
goto ReSimplify;
586 case X86::RELEASE_INC16m: OutMI.
setOpcode(X86::INC16m);
goto ReSimplify;
587 case X86::RELEASE_INC32m: OutMI.
setOpcode(X86::INC32m);
goto ReSimplify;
588 case X86::RELEASE_INC64m: OutMI.
setOpcode(X86::INC64m);
goto ReSimplify;
589 case X86::RELEASE_DEC8m: OutMI.
setOpcode(X86::DEC8m);
goto ReSimplify;
590 case X86::RELEASE_DEC16m: OutMI.
setOpcode(X86::DEC16m);
goto ReSimplify;
591 case X86::RELEASE_DEC32m: OutMI.
setOpcode(X86::DEC32m);
goto ReSimplify;
592 case X86::RELEASE_DEC64m: OutMI.
setOpcode(X86::DEC64m);
goto ReSimplify;
601 case X86::MOV8mr_NOREX:
603 case X86::MOV8rm_NOREX:
612 case X86::MOV8mr_NOREX:
613 case X86::MOV8mr: NewOpc = X86::MOV8o32a;
break;
614 case X86::MOV8rm_NOREX:
615 case X86::MOV8rm: NewOpc = X86::MOV8ao32;
break;
616 case X86::MOV16mr: NewOpc = X86::MOV16o32a;
break;
617 case X86::MOV16rm: NewOpc = X86::MOV16ao32;
break;
618 case X86::MOV32mr: NewOpc = X86::MOV32o32a;
break;
619 case X86::MOV32rm: NewOpc = X86::MOV32ao32;
break;
625 case X86::ADC8ri:
case X86::ADC16ri:
case X86::ADC32ri:
case X86::ADC64ri32:
626 case X86::ADD8ri:
case X86::ADD16ri:
case X86::ADD32ri:
case X86::ADD64ri32:
627 case X86::AND8ri:
case X86::AND16ri:
case X86::AND32ri:
case X86::AND64ri32:
628 case X86::CMP8ri:
case X86::CMP16ri:
case X86::CMP32ri:
case X86::CMP64ri32:
629 case X86::OR8ri:
case X86::OR16ri:
case X86::OR32ri:
case X86::OR64ri32:
630 case X86::SBB8ri:
case X86::SBB16ri:
case X86::SBB32ri:
case X86::SBB64ri32:
631 case X86::SUB8ri:
case X86::SUB16ri:
case X86::SUB32ri:
case X86::SUB64ri32:
632 case X86::TEST8ri:
case X86::TEST16ri:
case X86::TEST32ri:
case X86::TEST64ri32:
633 case X86::XOR8ri:
case X86::XOR16ri:
case X86::XOR32ri:
case X86::XOR64ri32: {
637 case X86::ADC8ri: NewOpc = X86::ADC8i8;
break;
638 case X86::ADC16ri: NewOpc = X86::ADC16i16;
break;
639 case X86::ADC32ri: NewOpc = X86::ADC32i32;
break;
640 case X86::ADC64ri32: NewOpc = X86::ADC64i32;
break;
641 case X86::ADD8ri: NewOpc = X86::ADD8i8;
break;
642 case X86::ADD16ri: NewOpc = X86::ADD16i16;
break;
643 case X86::ADD32ri: NewOpc = X86::ADD32i32;
break;
644 case X86::ADD64ri32: NewOpc = X86::ADD64i32;
break;
645 case X86::AND8ri: NewOpc = X86::AND8i8;
break;
646 case X86::AND16ri: NewOpc = X86::AND16i16;
break;
647 case X86::AND32ri: NewOpc = X86::AND32i32;
break;
648 case X86::AND64ri32: NewOpc = X86::AND64i32;
break;
649 case X86::CMP8ri: NewOpc = X86::CMP8i8;
break;
650 case X86::CMP16ri: NewOpc = X86::CMP16i16;
break;
651 case X86::CMP32ri: NewOpc = X86::CMP32i32;
break;
652 case X86::CMP64ri32: NewOpc = X86::CMP64i32;
break;
653 case X86::OR8ri: NewOpc = X86::OR8i8;
break;
654 case X86::OR16ri: NewOpc = X86::OR16i16;
break;
655 case X86::OR32ri: NewOpc = X86::OR32i32;
break;
656 case X86::OR64ri32: NewOpc = X86::OR64i32;
break;
657 case X86::SBB8ri: NewOpc = X86::SBB8i8;
break;
658 case X86::SBB16ri: NewOpc = X86::SBB16i16;
break;
659 case X86::SBB32ri: NewOpc = X86::SBB32i32;
break;
660 case X86::SBB64ri32: NewOpc = X86::SBB64i32;
break;
661 case X86::SUB8ri: NewOpc = X86::SUB8i8;
break;
662 case X86::SUB16ri: NewOpc = X86::SUB16i16;
break;
663 case X86::SUB32ri: NewOpc = X86::SUB32i32;
break;
664 case X86::SUB64ri32: NewOpc = X86::SUB64i32;
break;
665 case X86::TEST8ri: NewOpc = X86::TEST8i8;
break;
666 case X86::TEST16ri: NewOpc = X86::TEST16i16;
break;
667 case X86::TEST32ri: NewOpc = X86::TEST32i32;
break;
668 case X86::TEST64ri32: NewOpc = X86::TEST64i32;
break;
669 case X86::XOR8ri: NewOpc = X86::XOR8i8;
break;
670 case X86::XOR16ri: NewOpc = X86::XOR16i16;
break;
671 case X86::XOR32ri: NewOpc = X86::XOR32i32;
break;
672 case X86::XOR64ri32: NewOpc = X86::XOR64i32;
break;
679 case X86::MOVSX16rr8:
680 case X86::MOVSX32rr16:
681 case X86::MOVSX64rr32:
687 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
690 bool is64Bits = MI.
getOpcode() == X86::TLS_addr64 ||
693 bool needsPadding = MI.
getOpcode() == X86::TLS_addr64;
702 case X86::TLS_addr32:
703 case X86::TLS_addr64:
706 case X86::TLS_base_addr32:
709 case X86::TLS_base_addr64:
745 EmitAndCountInstruction(LEA);
753 StringRef name = is64Bits ?
"__tls_get_addr" :
"___tls_get_addr";
760 EmitAndCountInstruction(
MCInstBuilder(is64Bits ? X86::CALL64pcrel32
771 assert(Is64Bit &&
"EmitNops only supports X86-64");
774 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
775 Opc = IndexReg = Displacement = SegmentReg = 0;
780 case 1: NopSize = 1; Opc = X86::NOOP;
break;
781 case 2: NopSize = 2; Opc = X86::XCHG16ar;
break;
782 case 3: NopSize = 3; Opc = X86::NOOPL;
break;
783 case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8;
break;
784 case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8;
785 IndexReg = X86::RAX;
break;
786 case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8;
787 IndexReg = X86::RAX;
break;
788 case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512;
break;
789 case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512;
790 IndexReg = X86::RAX;
break;
791 case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512;
792 IndexReg = X86::RAX;
break;
793 default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512;
794 IndexReg = X86::RAX; SegmentReg = X86::CS;
break;
797 unsigned NumPrefixes =
std::min(NumBytes - NopSize, 5U);
798 NopSize += NumPrefixes;
799 for (
unsigned i = 0;
i != NumPrefixes; ++
i)
818 .addImm(Displacement)
823 assert(NopSize <= NumBytes &&
"We overemitted?");
830 unsigned NopsToEmit = NumBytes;
833 NumBytes -=
EmitNop(OS, NumBytes, Is64Bit, STI);
834 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
838 void X86AsmPrinter::LowerSTATEPOINT(
const MachineInstr &MI,
839 X86MCInstLower &MCIL) {
840 assert(Subtarget->
is64Bit() &&
"Statepoint currently only supports X86-64");
843 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
851 switch (CallTarget.
getType()) {
854 CallTargetMCOp = MCIL.LowerSymbolOperand(
855 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
856 CallOpcode = X86::CALL64pcrel32;
864 CallOpcode = X86::CALL64pcrel32;
872 CallOpcode = X86::CALL64r;
891 void X86AsmPrinter::LowerFAULTING_LOAD_OP(
const MachineInstr &MI,
892 X86MCInstLower &MCIL) {
898 unsigned LoadOperandsBeginIdx = 3;
905 if (LoadDefRegister != X86::NoRegister)
911 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *
I))
917 void X86AsmPrinter::LowerPATCHABLE_OP(
const MachineInstr &MI,
918 X86MCInstLower &MCIL) {
927 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
935 if (Code.
size() < MinSize) {
936 if (MinSize == 2 && Opcode == X86::PUSH64r) {
944 unsigned NopSize =
EmitNop(*OutStreamer, MinSize, Subtarget->
is64Bit(),
946 assert(NopSize == MinSize &&
"Could not implement MinSize!");
956 void X86AsmPrinter::LowerSTACKMAP(
const MachineInstr &MI) {
960 SMShadowTracker.reset(NumShadowBytes);
965 void X86AsmPrinter::LowerPATCHPOINT(
const MachineInstr &MI,
966 X86MCInstLower &MCIL) {
967 assert(Subtarget->
is64Bit() &&
"Patchpoint currently only supports X86-64");
974 unsigned ScratchIdx = opers.getNextScratchIdx();
975 unsigned EncodedBytes = 0;
993 MCIL.LowerSymbolOperand(CalleeMO,
994 MCIL.GetSymbolFromOperand(CalleeMO));
1006 EmitAndCountInstruction(
1008 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1012 unsigned NumBytes = opers.getNumPatchBytes();
1013 assert(NumBytes >= EncodedBytes &&
1014 "Patchpoint can't request size less than the length of a call.");
1020 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &MI,
1021 X86MCInstLower &MCIL) {
1050 void X86AsmPrinter::LowerPATCHABLE_RET(
const MachineInstr &MI,
1051 X86MCInstLower &MCIL) {
1073 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1080 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &MI, X86MCInstLower &MCIL) {
1108 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1118 while (MBBI == MBB->
begin()) {
1144 "Expected a constant of the same type!");
1152 std::string Comment;
1159 auto GetRegisterName = [](
unsigned RegNum) ->
StringRef {
1169 SrcOp1.
isReg() ? GetRegisterName(SrcOp1.
getReg()) :
"mem";
1171 SrcOp2.
isReg() ? GetRegisterName(SrcOp2.
getReg()) :
"mem";
1175 if (Src1Name == Src2Name)
1176 for (
int i = 0, e = ShuffleMask.size();
i != e; ++
i)
1177 if (ShuffleMask[
i] >= e)
1178 ShuffleMask[
i] -= e;
1186 if (SrcOp1Idx > 1) {
1187 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) &&
"Unexpected writemask");
1190 if (WriteMaskOp.
isReg()) {
1191 CS <<
" {%" << GetRegisterName(WriteMaskOp.
getReg()) <<
"}";
1193 if (SrcOp1Idx == 2) {
1201 for (
int i = 0, e = ShuffleMask.size();
i != e; ++
i) {
1211 bool isSrc1 = ShuffleMask[
i] < (int)e;
1212 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1214 bool IsFirst =
true;
1216 (ShuffleMask[
i] < (
int)e) == isSrc1) {
1224 CS << ShuffleMask[
i] % (int)e;
1236 X86MCInstLower MCInstLowering(*
MF, *
this);
1243 OutStreamer->
AddComment(
"EVEX TO VEX Compression ",
false);
1247 case TargetOpcode::DBG_VALUE:
1251 case X86::Int_MemBarrier:
1257 case X86::EH_RETURN64: {
1279 case X86::TAILJMPr64:
1280 case X86::TAILJMPm64:
1281 case X86::TAILJMPd64:
1282 case X86::TAILJMPr64_REX:
1283 case X86::TAILJMPm64_REX:
1288 case X86::TLS_addr32:
1289 case X86::TLS_addr64:
1290 case X86::TLS_base_addr32:
1291 case X86::TLS_base_addr64:
1292 return LowerTlsAddr(MCInstLowering, *MI);
1294 case X86::MOVPC32r: {
1310 bool hasFP = FrameLowering->
hasFP(*
MF);
1318 if (HasActiveDwarfFrame && !hasFP) {
1329 if (HasActiveDwarfFrame && !hasFP) {
1335 case X86::ADD32ri: {
1367 case TargetOpcode::STATEPOINT:
1368 return LowerSTATEPOINT(*MI, MCInstLowering);
1370 case TargetOpcode::FAULTING_LOAD_OP:
1371 return LowerFAULTING_LOAD_OP(*MI, MCInstLowering);
1373 case TargetOpcode::PATCHABLE_OP:
1374 return LowerPATCHABLE_OP(*MI, MCInstLowering);
1376 case TargetOpcode::STACKMAP:
1377 return LowerSTACKMAP(*MI);
1379 case TargetOpcode::PATCHPOINT:
1380 return LowerPATCHPOINT(*MI, MCInstLowering);
1382 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1383 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1385 case TargetOpcode::PATCHABLE_RET:
1386 return LowerPATCHABLE_RET(*MI, MCInstLowering);
1388 case TargetOpcode::PATCHABLE_TAIL_CALL:
1389 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1391 case X86::MORESTACK_RET:
1395 case X86::MORESTACK_RET_RESTORE_R10:
1403 case X86::SEH_PushReg:
1408 case X86::SEH_SaveReg:
1414 case X86::SEH_SaveXMM:
1420 case X86::SEH_StackAlloc:
1425 case X86::SEH_SetFrame:
1431 case X86::SEH_PushFrame:
1436 case X86::SEH_EndPrologue:
1441 case X86::SEH_Epilogue: {
1450 if (!MBBI->isPseudo()) {
1463 case X86::VPSHUFBrm:
1464 case X86::VPSHUFBYrm:
1465 case X86::VPSHUFBZ128rm:
1466 case X86::VPSHUFBZ128rmk:
1467 case X86::VPSHUFBZ128rmkz:
1468 case X86::VPSHUFBZ256rm:
1469 case X86::VPSHUFBZ256rmk:
1470 case X86::VPSHUFBZ256rmkz:
1471 case X86::VPSHUFBZrm:
1472 case X86::VPSHUFBZrmk:
1473 case X86::VPSHUFBZrmkz: {
1476 unsigned SrcIdx, MaskIdx;
1480 case X86::VPSHUFBrm:
1481 case X86::VPSHUFBYrm:
1482 case X86::VPSHUFBZ128rm:
1483 case X86::VPSHUFBZ256rm:
1484 case X86::VPSHUFBZrm:
1485 SrcIdx = 1; MaskIdx = 5;
break;
1486 case X86::VPSHUFBZ128rmkz:
1487 case X86::VPSHUFBZ256rmkz:
1488 case X86::VPSHUFBZrmkz:
1489 SrcIdx = 2; MaskIdx = 6;
break;
1490 case X86::VPSHUFBZ128rmk:
1491 case X86::VPSHUFBZ256rmk:
1492 case X86::VPSHUFBZrmk:
1493 SrcIdx = 3; MaskIdx = 7;
break;
1497 "We should always have at least 6 operands!");
1509 case X86::VPERMILPSrm:
1510 case X86::VPERMILPSYrm:
1511 case X86::VPERMILPSZ128rm:
1512 case X86::VPERMILPSZ128rmk:
1513 case X86::VPERMILPSZ128rmkz:
1514 case X86::VPERMILPSZ256rm:
1515 case X86::VPERMILPSZ256rmk:
1516 case X86::VPERMILPSZ256rmkz:
1517 case X86::VPERMILPSZrm:
1518 case X86::VPERMILPSZrmk:
1519 case X86::VPERMILPSZrmkz:
1520 case X86::VPERMILPDrm:
1521 case X86::VPERMILPDYrm:
1522 case X86::VPERMILPDZ128rm:
1523 case X86::VPERMILPDZ128rmk:
1524 case X86::VPERMILPDZ128rmkz:
1525 case X86::VPERMILPDZ256rm:
1526 case X86::VPERMILPDZ256rmk:
1527 case X86::VPERMILPDZ256rmkz:
1528 case X86::VPERMILPDZrm:
1529 case X86::VPERMILPDZrmk:
1530 case X86::VPERMILPDZrmkz: {
1533 unsigned SrcIdx, MaskIdx;
1537 case X86::VPERMILPSrm:
1538 case X86::VPERMILPSYrm:
1539 case X86::VPERMILPSZ128rm:
1540 case X86::VPERMILPSZ256rm:
1541 case X86::VPERMILPSZrm:
1542 SrcIdx = 1; MaskIdx = 5; ElSize = 32;
break;
1543 case X86::VPERMILPSZ128rmkz:
1544 case X86::VPERMILPSZ256rmkz:
1545 case X86::VPERMILPSZrmkz:
1546 SrcIdx = 2; MaskIdx = 6; ElSize = 32;
break;
1547 case X86::VPERMILPSZ128rmk:
1548 case X86::VPERMILPSZ256rmk:
1549 case X86::VPERMILPSZrmk:
1550 SrcIdx = 3; MaskIdx = 7; ElSize = 32;
break;
1551 case X86::VPERMILPDrm:
1552 case X86::VPERMILPDYrm:
1553 case X86::VPERMILPDZ128rm:
1554 case X86::VPERMILPDZ256rm:
1555 case X86::VPERMILPDZrm:
1556 SrcIdx = 1; MaskIdx = 5; ElSize = 64;
break;
1557 case X86::VPERMILPDZ128rmkz:
1558 case X86::VPERMILPDZ256rmkz:
1559 case X86::VPERMILPDZrmkz:
1560 SrcIdx = 2; MaskIdx = 6; ElSize = 64;
break;
1561 case X86::VPERMILPDZ128rmk:
1562 case X86::VPERMILPDZ256rmk:
1563 case X86::VPERMILPDZrmk:
1564 SrcIdx = 3; MaskIdx = 7; ElSize = 64;
break;
1568 "We should always have at least 6 operands!");
1580 case X86::VPERMIL2PDrm:
1581 case X86::VPERMIL2PSrm:
1582 case X86::VPERMIL2PDrmY:
1583 case X86::VPERMIL2PSrmY: {
1587 "We should always have at least 8 operands!");
1590 if (!CtrlOp.isImm())
1596 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSrmY: ElSize = 32;
break;
1597 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDrmY: ElSize = 64;
break;
1610 case X86::VPPERMrrm: {
1614 "We should always have at least 7 operands!");
1626 #define MOV_CASE(Prefix, Suffix) \
1627 case X86::Prefix##MOVAPD##Suffix##rm: \
1628 case X86::Prefix##MOVAPS##Suffix##rm: \
1629 case X86::Prefix##MOVUPD##Suffix##rm: \
1630 case X86::Prefix##MOVUPS##Suffix##rm: \
1631 case X86::Prefix##MOVDQA##Suffix##rm: \
1632 case X86::Prefix##MOVDQU##Suffix##rm:
1634 #define MOV_AVX512_CASE(Suffix) \
1635 case X86::VMOVDQA64##Suffix##rm: \
1636 case X86::VMOVDQA32##Suffix##rm: \
1637 case X86::VMOVDQU64##Suffix##rm: \
1638 case X86::VMOVDQU32##Suffix##rm: \
1639 case X86::VMOVDQU16##Suffix##rm: \
1640 case X86::VMOVDQU8##Suffix##rm: \
1641 case X86::VMOVAPS##Suffix##rm: \
1642 case X86::VMOVAPD##Suffix##rm: \
1643 case X86::VMOVUPS##Suffix##rm: \
1644 case X86::VMOVUPD##Suffix##rm:
1646 #define CASE_ALL_MOV_RM() \
1650 MOV_AVX512_CASE(Z) \
1651 MOV_AVX512_CASE(Z256) \
1652 MOV_AVX512_CASE(Z128)
1662 std::string Comment;
1666 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
1668 for (
int i = 0, NumElements = CDS->getNumElements();
i < NumElements; ++
i) {
1671 if (CDS->getElementType()->isIntegerTy())
1672 CS << CDS->getElementAsInteger(
i);
1673 else if (CDS->getElementType()->isFloatTy())
1674 CS << CDS->getElementAsFloat(
i);
1675 else if (CDS->getElementType()->isDoubleTy())
1676 CS << CDS->getElementAsDouble(
i);
1682 }
else if (
auto *CV = dyn_cast<ConstantVector>(
C)) {
1684 for (
int i = 0, NumOperands = CV->getNumOperands();
i < NumOperands; ++
i) {
1688 if (isa<UndefValue>(COp)) {
1690 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
1691 if (CI->getBitWidth() <= 64) {
1692 CS << CI->getZExtValue();
1695 const auto &Val = CI->getValue();
1697 for (
int i = 0,
N = Val.getNumWords();
i <
N; ++
i) {
1700 CS << Val.getRawData()[
i];
1704 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
1706 CF->getValueAPF().toString(Str);
1720 MCInstLowering.Lower(MI, TmpInst);
1737 EmitAndCountInstruction(TmpInst);
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void DecodeVPERMILPMask(MVT VT, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
A parsed version of the target data layout string in and methods for querying it. ...
mop_iterator operands_end()
StringRef getPrivateGlobalPrefix() const
const GlobalValue * getGlobal() const
static const char * getRegisterName(unsigned RegNo)
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol * getSymbol(const GlobalValue *GV) const
virtual void EmitWinCFIEndProlog()
MCTargetOptions MCOptions
Machine level options.
MO_TLSLDM - Represents the offset into the global offset table at which.
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
MCContext & OutContext
This is the context for the output file that we are streaming.
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
MO_TLSGD - Represents the offset into the global offset table at which.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
This class represents a function call, abstracting a target machine's calling convention.
const MachineFunction * MF
The current machine function.
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
A raw_ostream that writes to an SmallVector or SmallString.
const char * getSymbolName() const
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
ArrayRef< MCDwarfFrameInfo > getDwarfFrameInfos() const
iterator_range< mop_iterator > operands()
print alias Alias Set Printer
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
AddrSegmentReg - The operand # of the segment in the memory operand.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
CLEANUPRET - Represents a return from a cleanup block funclet.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool hasInternalLinkage() const
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Base class for the full range of assembler expressions which are needed for parsing.
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
Represent a reference to a symbol from inside an expression.
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
#define CASE_ALL_MOV_RM()
MCContext & getContext() const
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Context object for machine code objects.
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
const MachineBasicBlock & front() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
PointerTy getPointer() const
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
unsigned getReg() const
Returns the register number.
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
This class is a data container for one entry in a MachineConstantPool.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(std::begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
const MachineBasicBlock * getParent() const
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
const Constant * ConstVal
This class is intended to be used as a base class for asm properties and features specific to the tar...
const MCExpr * getExpr() const
Address of a global value.
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
unsigned getTargetFlags() const
Streaming machine code generation interface.
AddrNumOperands - Total number of operands in a memory reference.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
PointerIntPair - This class implements a pair of a pointer and small integer.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
virtual void EmitWinCFIPushReg(unsigned Register)
This is an important base class in LLVM.
const MachineOperand & getOperand(unsigned i) const
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind)
MCCodeEmitter - Generic instruction encoding interface.
TargetMachine & TM
Target machine description.
This class is intended to be used as a driving class for all asm writers.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
Value * getOperand(unsigned i) const
int64_t getOffset() const
Return the offset from the symbol in this operand.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
MI-level patchpoint operands.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
void DecodeVPERMIL2PMask(MVT VT, unsigned M2Z, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset)
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
int getSEHRegNum(unsigned i) const
const X86Subtarget & getSubtarget() const
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void dump(const TargetInstrInfo *TII=nullptr) const
virtual void EmitWinCFIAllocStack(unsigned Size)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned getOpcode() const
Target - Wrapper for Target specific information.
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
CATCHRET - Represents a return from a catch block funclet.
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
unsigned getNumFrameInfos()
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
unsigned getNumOperands() const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isCall(QueryType Type=AnyInBundle) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
MCSymbol * getMCSymbol() const
MCSubtargetInfo - Generic base class for all target subtargets.
MI-level Statepoint operands.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
unsigned getSlotSize() const
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
mop_iterator operands_begin()
MachineInstrBundleIterator< const MachineInstr > const_iterator
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Primary interface to the complete machine description for the target machine.
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset)
virtual void EmitWinCFIPushFrame(bool Code)
const std::vector< MachineConstantPoolEntry > & getConstants() const
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
const BlockAddress * getBlockAddress() const
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
union llvm::MachineConstantPoolEntry::@35 Val
The constant itself.
Instances of this class represent operands of the MCInst class.
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
static MCOperand createImm(int64_t Val)
static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment)
const MCOperand & getOperand(unsigned i) const
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
virtual void EmitWinCFISetFrame(unsigned Register, unsigned Offset)