LLVM  4.0.0
Namespaces | Classes | Enumerations | Functions | Variables
llvm::AMDGPU Namespace Reference

Namespaces

 EncValues
 
 Hwreg
 
 SDWA
 
 SendMsg
 

Classes

struct  IsaVersion
 

Enumerations

enum  TargetIndex {
  TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum  Fixups { fixup_si_sopp_br = FirstTargetFixupKind, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
 
enum  OperandType {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_FP32,
  OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_FP16, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32,
  OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64,
  OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_FP16, OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_C_FP64,
  OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, OPERAND_INPUT_MODS, OPERAND_KIMM32,
  OPERAND_KIMM16
}
 
enum  TargetFlags { TF_LONG_BRANCH_FORWARD = 1 << 0, TF_LONG_BRANCH_BACKWARD = 1 << 1 }
 

Functions

static int getMCOpcode (uint16_t Opcode, unsigned Gen)
 
int getLDSNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getVOPe64 (uint16_t Opcode)
 
LLVM_READONLY int getVOPe32 (uint16_t Opcode)
 
LLVM_READONLY int getCommuteRev (uint16_t Opcode)
 
LLVM_READONLY int getCommuteOrig (uint16_t Opcode)
 
LLVM_READONLY int getAddr64Inst (uint16_t Opcode)
 
LLVM_READONLY int getAtomicRetOp (uint16_t Opcode)
 
LLVM_READONLY int getAtomicNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getSOPKOp (uint16_t Opcode)
 
IsaVersion getIsaVersion (const FeatureBitset &Features)
 
void initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const FeatureBitset &Features)
 
MCSectiongetHSATextSection (MCContext &Ctx)
 
MCSectiongetHSADataGlobalAgentSection (MCContext &Ctx)
 
MCSectiongetHSADataGlobalProgramSection (MCContext &Ctx)
 
MCSectiongetHSARodataReadonlyAgentSection (MCContext &Ctx)
 
bool isGroupSegment (const GlobalValue *GV)
 
bool isGlobalSegment (const GlobalValue *GV)
 
bool isReadOnlySegment (const GlobalValue *GV)
 
bool shouldEmitConstantsToTextSection (const Triple &TT)
 
int getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned getWaitcntBitMask (IsaVersion Version)
 
unsigned getVmcntBitMask (IsaVersion Version)
 
unsigned getExpcntBitMask (IsaVersion Version)
 
unsigned getLgkmcntBitMask (IsaVersion Version)
 
unsigned decodeVmcnt (IsaVersion Version, unsigned Waitcnt)
 
unsigned decodeExpcnt (IsaVersion Version, unsigned Waitcnt)
 
unsigned decodeLgkmcnt (IsaVersion Version, unsigned Waitcnt)
 
void decodeWaitcnt (IsaVersion Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
unsigned encodeVmcnt (IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned encodeExpcnt (IsaVersion Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned encodeLgkmcnt (IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned encodeWaitcnt (IsaVersion Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned getInitialPSInputAddr (const Function &F)
 
bool isShader (CallingConv::ID cc)
 
bool isCompute (CallingConv::ID cc)
 
bool isSI (const MCSubtargetInfo &STI)
 
bool isCI (const MCSubtargetInfo &STI)
 
bool isVI (const MCSubtargetInfo &STI)
 
unsigned getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
bool isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
LLVM_READONLY int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
LLVM_READNONE unsigned getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 

Variables

const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
 
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
 
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
 

Enumeration Type Documentation

Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 17 of file AMDGPUFixupKinds.h.

Enumerator
OPERAND_REG_IMM_INT32 

Operands with register or 32-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_FP16 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_INPUT_MODS 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 

Definition at line 89 of file SIDefines.h.

Enumerator
TF_LONG_BRANCH_FORWARD 
TF_LONG_BRANCH_BACKWARD 

Definition at line 767 of file SIInstrInfo.h.

Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 119 of file AMDGPU.h.

Function Documentation

unsigned llvm::AMDGPU::decodeExpcnt ( IsaVersion  Version,
unsigned  Waitcnt 
)
Returns
Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 243 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt().

unsigned llvm::AMDGPU::decodeLgkmcnt ( IsaVersion  Version,
unsigned  Waitcnt 
)
Returns
Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 247 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt().

unsigned llvm::AMDGPU::decodeVmcnt ( IsaVersion  Version,
unsigned  Waitcnt 
)
Returns
Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 239 of file AMDGPUBaseInfo.cpp.

Referenced by decodeWaitcnt().

void llvm::AMDGPU::decodeWaitcnt ( IsaVersion  Version,
unsigned  Waitcnt,
unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt 
)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] Expcnt = Waitcnt[6:4] Lgkmcnt = Waitcnt[11:8]

Definition at line 251 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), and decodeVmcnt().

unsigned llvm::AMDGPU::encodeExpcnt ( IsaVersion  Version,
unsigned  Waitcnt,
unsigned  Expcnt 
)
Returns
Waitcnt with encoded Expcnt for given isa Version.

Definition at line 262 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

unsigned llvm::AMDGPU::encodeLgkmcnt ( IsaVersion  Version,
unsigned  Waitcnt,
unsigned  Lgkmcnt 
)
Returns
Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 266 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

unsigned llvm::AMDGPU::encodeVmcnt ( IsaVersion  Version,
unsigned  Waitcnt,
unsigned  Vmcnt 
)
Returns
Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 258 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

unsigned llvm::AMDGPU::encodeWaitcnt ( IsaVersion  Version,
unsigned  Vmcnt,
unsigned  Expcnt,
unsigned  Lgkmcnt 
)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[3:0] = Vmcnt Waitcnt[6:4] = Expcnt Waitcnt[11:8] = Lgkmcnt

Returns
Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 270 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), and getWaitcntBitMask().

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst ( uint16_t  Opcode)
LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp ( uint16_t  Opcode)
LLVM_READONLY int llvm::AMDGPU::getAtomicRetOp ( uint16_t  Opcode)
LLVM_READONLY int llvm::AMDGPU::getCommuteOrig ( uint16_t  Opcode)
LLVM_READONLY int llvm::AMDGPU::getCommuteRev ( uint16_t  Opcode)
unsigned llvm::AMDGPU::getExpcntBitMask ( IsaVersion  Version)
Returns
Expcnt bit mask for given isa Version.

Definition at line 231 of file AMDGPUBaseInfo.cpp.

MCSection * llvm::AMDGPU::getHSADataGlobalAgentSection ( MCContext &  Ctx)
MCSection * llvm::AMDGPU::getHSADataGlobalProgramSection ( MCContext &  Ctx)
MCSection * llvm::AMDGPU::getHSARodataReadonlyAgentSection ( MCContext &  Ctx)
MCSection * llvm::AMDGPU::getHSATextSection ( MCContext &  Ctx)
unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function &  F)

Definition at line 279 of file AMDGPUBaseInfo.cpp.

References getIntegerAttribute().

Referenced by PrivateMemoryInputPtr().

int llvm::AMDGPU::getIntegerAttribute ( const Function &  F,
StringRef  Name,
int  Default 
)
Returns
Integer value requested using F's Name attribute.
Default if attribute is not present.
Default and emits error if requested value cannot be converted to integer.

Definition at line 180 of file AMDGPUBaseInfo.cpp.

References A, llvm::LLVMContext::emitError(), llvm::StringRef::getAsInteger(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), and llvm::Attribute::isStringAttribute().

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), getInitialPSInputAddr(), llvm::SIRegisterInfo::getMaxNumSGPRs(), and llvm::SIRegisterInfo::getMaxNumVGPRs().

std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute ( const Function &  F,
StringRef  Name,
std::pair< int, int >  Default,
bool  OnlyFirstRequired = false 
)
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 195 of file AMDGPUBaseInfo.cpp.

References A, llvm::LLVMContext::emitError(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), llvm::Attribute::isStringAttribute(), and llvm::StringRef::split().

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

IsaVersion llvm::AMDGPU::getIsaVersion ( const FeatureBitset &  Features)
int llvm::AMDGPU::getLDSNoRetOp ( uint16_t  Opcode)
unsigned llvm::AMDGPU::getLgkmcntBitMask ( IsaVersion  Version)
Returns
Lgkmcnt bit mask for given isa Version.

Definition at line 235 of file AMDGPUBaseInfo.cpp.

static int llvm::AMDGPU::getMCOpcode ( uint16_t  Opcode,
unsigned  Gen 
)
static

Definition at line 77 of file AMDGPUInstrInfo.cpp.

Referenced by llvm::AMDGPUInstrInfo::pseudoToMCOpcode().

unsigned llvm::AMDGPU::getMCReg ( unsigned  Reg,
const MCSubtargetInfo &  STI 
)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 311 of file AMDGPUBaseInfo.cpp.

References assert(), isCI(), and isSI().

Referenced by llvm::AMDGPUDisassembler::decodeSpecialReg32(), llvm::AMDGPUDisassembler::decodeSpecialReg64(), and llvm::AMDGPUMCInstLower::lowerOperand().

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIdx 
)
LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo &  OpInfo)
inline
LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)
inline

Definition at line 199 of file AMDGPUBaseInfo.h.

References getOperandSize(), and llvm::MCInstrDesc::OpInfo.

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned  RCID)

Get the size in bits of a register from the register class RC.

Definition at line 359 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

Referenced by getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass &  RC)

Get the size in bits of a register from the register class RC.

Definition at line 389 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

unsigned llvm::AMDGPU::getRegOperandSize ( const MCRegisterInfo *  MRI,
const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Get size of register operand.

Definition at line 393 of file AMDGPUBaseInfo.cpp.

References getRegBitWidth(), llvm::MCRegisterInfo::getRegClass(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

LLVM_READONLY int llvm::AMDGPU::getSOPKOp ( uint16_t  Opcode)

Referenced by shrinkScalarCompare().

unsigned llvm::AMDGPU::getVmcntBitMask ( IsaVersion  Version)
Returns
Vmcnt bit mask for given isa Version.

Definition at line 227 of file AMDGPUBaseInfo.cpp.

LLVM_READONLY int llvm::AMDGPU::getVOPe32 ( uint16_t  Opcode)
LLVM_READONLY int llvm::AMDGPU::getVOPe64 ( uint16_t  Opcode)
unsigned llvm::AMDGPU::getWaitcntBitMask ( IsaVersion  Version)
Returns
Waitcnt bit mask for given isa Version.

Definition at line 220 of file AMDGPUBaseInfo.cpp.

Referenced by encodeWaitcnt().

void llvm::AMDGPU::initDefaultAMDKernelCodeT ( amd_kernel_code_t Header,
const FeatureBitset &  Features 
)
bool llvm::AMDGPU::isCI ( const MCSubtargetInfo &  STI)

Definition at line 303 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by getMCReg().

bool llvm::AMDGPU::isCompute ( CallingConv::ID  cc)
bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue *  GV)
bool llvm::AMDGPU::isGroupSegment ( const GlobalValue *  GV)
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 ( int16_t  Literal,
bool  HasInv2Pi 
)

Definition at line 442 of file AMDGPUBaseInfo.cpp.

References assert().

Referenced by llvm::SIInstrInfo::isInlineConstant().

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 416 of file AMDGPUBaseInfo.cpp.

References llvm::FloatToBits().

Referenced by llvm::SIInstrInfo::isInlineConstant().

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 ( int64_t  Literal,
bool  HasInv2Pi 
)

Is this literal inlinable.

Definition at line 399 of file AMDGPUBaseInfo.cpp.

References llvm::DoubleToBits().

Referenced by llvm::SIInstrInfo::isInlineConstant().

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue *  GV)
bool llvm::AMDGPU::isShader ( CallingConv::ID  cc)
bool llvm::AMDGPU::isSI ( const MCSubtargetInfo &  STI)

Definition at line 299 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by getMCReg().

bool llvm::AMDGPU::isSISrcFPOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)
bool llvm::AMDGPU::isSISrcInlinableOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Does this opearnd support only inlinable literals?

Definition at line 351 of file AMDGPUBaseInfo.cpp.

References OPERAND_REG_INLINE_C_FIRST, OPERAND_REG_INLINE_C_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

bool llvm::AMDGPU::isSISrcOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Can this operand also contain immediate values?

Definition at line 330 of file AMDGPUBaseInfo.cpp.

References OPERAND_SRC_FIRST, OPERAND_SRC_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo &  STI)
bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple &  TT)
Returns
True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 176 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, and llvm::Triple::getOS().

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

Variable Documentation

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL
const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 762 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 763 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 764 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().