LLVM  4.0.0
HexagonMCCodeEmitter.cpp
Go to the documentation of this file.
1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "Hexagon.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
27 
28 #define DEBUG_TYPE "mccodeemitter"
29 
30 using namespace llvm;
31 using namespace Hexagon;
32 
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
34 
36  MCContext &aMCT)
37  : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
38  Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
39 
41  MCInst const &MCB,
42  MCInst const &MCI) const {
43  bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
44  if (Instruction == 0) {
46  assert(!Duplex);
47  assert(Instruction != Last);
49  }
50  }
51  if (Instruction == 1) {
53  assert(!Duplex);
54  assert(Instruction != Last);
56  }
57  }
58  if (Duplex) {
59  assert(Instruction == Last);
61  }
62  if(Instruction == Last)
65 }
66 
69  MCSubtargetInfo const &STI) const {
70  MCInst &HMB = const_cast<MCInst &>(MI);
71 
73  DEBUG(dbgs() << "Encoding bundle\n";);
74  *Addend = 0;
75  *Extended = false;
76  *CurrentBundle = &MI;
77  size_t Instruction = 0;
78  size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
79  for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
80  MCInst &HMI = const_cast<MCInst &>(*I.getInst());
81  verifyInstructionPredicates(HMI,
82  computeAvailableFeatures(STI.getFeatureBits()));
83 
84  EncodeSingleInstruction(HMI, OS, Fixups, STI,
85  parseBits(Instruction, Last, HMB, HMI),
86  Instruction);
87  *Extended = HexagonMCInstrInfo::isImmext(HMI);
88  *Addend += HEXAGON_INSTR_SIZE;
89  ++Instruction;
90  }
91  return;
92 }
93 
94 static bool RegisterMatches(unsigned Consumer, unsigned Producer,
95  unsigned Producer2) {
96  if (Consumer == Producer)
97  return true;
98  if (Consumer == Producer2)
99  return true;
100  // Calculate if we're a single vector consumer referencing a double producer
101  if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
102  if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
103  return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
104  return false;
105 }
106 
107 /// EncodeSingleInstruction - Emit a single
110  const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
111  MCInst HMB = MI;
113  uint64_t Binary;
114 
115  // Compound instructions are limited to using registers 0-7 and 16-23
116  // and here we make a map 16-23 to 8-15 so they can be correctly encoded.
117  static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10,
118  Hexagon::R11, Hexagon::R12, Hexagon::R13,
119  Hexagon::R14, Hexagon::R15};
120 
121  // Pseudo instructions don't get encoded and shouldn't be here
122  // in the first place!
123  assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
124  "pseudo-instruction found");
125  DEBUG(dbgs() << "Encoding insn"
126  " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
127  "\n");
128 
130  for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
131  if (HMB.getOperand(i).isReg()) {
132  unsigned Reg =
134  if ((Reg <= 23) && (Reg >= 16))
135  HMB.getOperand(i).setReg(RegMap[Reg - 16]);
136  }
137  }
138 
139  if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
140  // Calculate the new value distance to the associated producer
141  MCOperand &MCO =
143  unsigned SOffset = 0;
144  unsigned VOffset = 0;
145  unsigned Register = MCO.getReg();
146  unsigned Register1;
147  unsigned Register2;
148  auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
149  auto i = Instructions.begin() + Index - 1;
150  for (;; --i) {
151  assert(i != Instructions.begin() - 1 && "Couldn't find producer");
152  MCInst const &Inst = *i->getInst();
154  continue;
155  ++SOffset;
156  if (HexagonMCInstrInfo::isVector(MCII, Inst))
157  // Vector instructions don't count scalars
158  ++VOffset;
159  Register1 =
162  : static_cast<unsigned>(Hexagon::NoRegister);
163  Register2 =
166  : static_cast<unsigned>(Hexagon::NoRegister);
167  if (!RegisterMatches(Register, Register1, Register2))
168  // This isn't the register we're looking for
169  continue;
170  if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
171  // Producer is unpredicated
172  break;
174  "Unpredicated consumer depending on predicated producer");
175  if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
177  // Producer predicate sense matched ours
178  break;
179  }
180  // Hexagon PRM 10.11 Construct Nt from distance
181  unsigned Offset =
182  HexagonMCInstrInfo::isVector(MCII, HMB) ? VOffset : SOffset;
183  Offset <<= 1;
184  Offset |=
185  HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2);
186  MCO.setReg(Offset + Hexagon::R0);
187  }
188 
189  Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
190  // Check for unimplemented instructions. Immediate extenders
191  // are encoded as zero, so they need to be accounted for.
192  if ((!Binary) &&
193  ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
194  (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
195  (HMB.getOpcode() != A4_ext_g))) {
196  DEBUG(dbgs() << "Unimplemented inst: "
197  " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
198  "\n");
199  llvm_unreachable("Unimplemented Instruction");
200  }
201  Binary |= Parse;
202 
203  // if we need to emit a duplexed instruction
204  if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
205  HMB.getOpcode() <= Hexagon::DuplexIClassF) {
207  "Emitting duplex without duplex parse bits");
208  unsigned dupIClass;
209  switch (HMB.getOpcode()) {
210  case Hexagon::DuplexIClass0:
211  dupIClass = 0;
212  break;
213  case Hexagon::DuplexIClass1:
214  dupIClass = 1;
215  break;
216  case Hexagon::DuplexIClass2:
217  dupIClass = 2;
218  break;
219  case Hexagon::DuplexIClass3:
220  dupIClass = 3;
221  break;
222  case Hexagon::DuplexIClass4:
223  dupIClass = 4;
224  break;
225  case Hexagon::DuplexIClass5:
226  dupIClass = 5;
227  break;
228  case Hexagon::DuplexIClass6:
229  dupIClass = 6;
230  break;
231  case Hexagon::DuplexIClass7:
232  dupIClass = 7;
233  break;
234  case Hexagon::DuplexIClass8:
235  dupIClass = 8;
236  break;
237  case Hexagon::DuplexIClass9:
238  dupIClass = 9;
239  break;
240  case Hexagon::DuplexIClassA:
241  dupIClass = 10;
242  break;
243  case Hexagon::DuplexIClassB:
244  dupIClass = 11;
245  break;
246  case Hexagon::DuplexIClassC:
247  dupIClass = 12;
248  break;
249  case Hexagon::DuplexIClassD:
250  dupIClass = 13;
251  break;
252  case Hexagon::DuplexIClassE:
253  dupIClass = 14;
254  break;
255  case Hexagon::DuplexIClassF:
256  dupIClass = 15;
257  break;
258  default:
259  llvm_unreachable("Unimplemented DuplexIClass");
260  break;
261  }
262  // 29 is the bit position.
263  // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
264  // Last bit is moved to bit position 13
265  Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
266 
267  const MCInst *subInst0 = HMB.getOperand(0).getInst();
268  const MCInst *subInst1 = HMB.getOperand(1).getInst();
269 
270  // get subinstruction slot 0
271  unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
272  // get subinstruction slot 1
273  unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
274 
275  Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
276  }
277  support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
278  ++MCNumEmitted;
279 }
280 
281 namespace {
282 void raise_relocation_error(unsigned bits, unsigned kind) {
283  std::string Text;
284  {
285  llvm::raw_string_ostream Stream(Text);
286  Stream << "Unrecognized relocation combination bits: " << bits
287  << " kind: " << kind;
288  }
289  report_fatal_error(Text);
290 }
291 }
292 
293 /// getFixupNoBits - Some insns are not extended and thus have no
294 /// bits. These cases require a more brute force method for determining
295 /// the correct relocation.
296 namespace {
297 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
298  const MCOperand &MO,
299  const MCSymbolRefExpr::VariantKind kind) {
300  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
301  unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
302 
303  if (insnType == HexagonII::TypePREFIX) {
304  switch (kind) {
323  if (MCID.isBranch())
325  else
327  default:
328  raise_relocation_error(0, kind);
329  }
330  } else if (MCID.isBranch())
332 
333  switch (MCID.getOpcode()) {
334  case Hexagon::HI:
335  case Hexagon::A2_tfrih:
336  switch (kind) {
355  default:
356  raise_relocation_error(0, kind);
357  }
358 
359  case Hexagon::LO:
360  case Hexagon::A2_tfril:
361  switch (kind) {
380  default:
381  raise_relocation_error(0, kind);
382  }
383 
384  // The only relocs left should be GP relative:
385  default:
386  if (MCID.mayStore() || MCID.mayLoad()) {
387  for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
388  ++ImpUses) {
389  if (*ImpUses != Hexagon::GP)
390  continue;
391  switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
400  default:
401  raise_relocation_error(0, kind);
402  }
403  }
404  }
405  raise_relocation_error(0, kind);
406  }
407  llvm_unreachable("Relocation exit not taken");
408 }
409 }
410 
411 namespace llvm {
412 extern const MCInstrDesc HexagonInsts[];
413 }
414 
415 namespace {
416  bool isPCRel (unsigned Kind) {
417  switch(Kind){
434  return true;
435  default:
436  return false;
437  }
438  }
439 }
440 
441 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
442  const MCOperand &MO,
443  const MCExpr *ME,
445  const MCSubtargetInfo &STI) const
446 
447 {
448  if (isa<HexagonMCExpr>(ME))
449  ME = &HexagonMCInstrInfo::getExpr(*ME);
450  int64_t Value;
451  if (ME->evaluateAsAbsolute(Value))
452  return Value;
453  assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() == MCExpr::Binary);
454  if (ME->getKind() == MCExpr::Binary) {
455  MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
456  getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
457  getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
458  return 0;
459  }
462  const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
463  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
464  unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
466  const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
467 
468  DEBUG(dbgs() << "----------------------------------------\n");
469  DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
470  << "\n");
471  DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
472  DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
473  DEBUG(dbgs() << "Addend: " << *Addend << "\n");
474  DEBUG(dbgs() << "----------------------------------------\n");
475 
476  switch (bits) {
477  default:
478  raise_relocation_error(bits, kind);
479  case 32:
480  switch (kind) {
482  FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
484  break;
486  FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
488  break;
490  FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
492  break;
494  FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
496  break;
498  FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
500  break;
502  FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
504  break;
506  FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
508  break;
511  break;
513  FixupKind =
515  break;
517  FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
519  break;
520  default:
521  raise_relocation_error(bits, kind);
522  }
523  break;
524 
525  case 22:
526  switch (kind) {
529  break;
532  break;
534  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
536  break;
539  break;
540  default:
541  raise_relocation_error(bits, kind);
542  }
543  break;
544 
545  case 16:
546  if (*Extended) {
547  switch (kind) {
550  break;
553  break;
556  break;
559  break;
561  FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
562  break;
565  break;
568  break;
570  FixupKind = Hexagon::fixup_Hexagon_16_X;
571  break;
574  break;
575  default:
576  raise_relocation_error(bits, kind);
577  }
578  } else
579  switch (kind) {
582  FixupKind = Hexagon::fixup_Hexagon_23_REG;
583  else
584  raise_relocation_error(bits, kind);
585  break;
586  }
589  break;
591  if (MCID.getOpcode() == Hexagon::HI)
593  else
595  break;
598  break;
601  break;
603  FixupKind = Hexagon::fixup_Hexagon_HI16;
604  break;
607  break;
610  break;
612  FixupKind = Hexagon::fixup_Hexagon_LO16;
613  break;
616  break;
617  default:
618  raise_relocation_error(bits, kind);
619  }
620  break;
621 
622  case 15:
623  switch (kind) {
625  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
627  break;
628  default:
629  raise_relocation_error(bits, kind);
630  }
631  break;
632 
633  case 13:
634  switch (kind) {
637  break;
638  default:
639  raise_relocation_error(bits, kind);
640  }
641  break;
642 
643  case 12:
644  if (*Extended)
645  switch (kind) {
646  // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
649  break;
652  break;
654  FixupKind = Hexagon::fixup_Hexagon_12_X;
655  break;
656  default:
657  raise_relocation_error(bits, kind);
658  }
659  else
660  raise_relocation_error(bits, kind);
661  break;
662 
663  case 11:
664  if (*Extended)
665  switch (kind) {
668  break;
671  break;
674  break;
677  break;
680  break;
683  break;
685  FixupKind = Hexagon::fixup_Hexagon_11_X;
686  break;
689  break;
690  default:
691  raise_relocation_error(bits, kind);
692  }
693  else {
694  switch (kind) {
697  break;
698  default:
699  raise_relocation_error(bits, kind);
700  }
701  }
702  break;
703 
704  case 10:
705  if (*Extended) {
706  switch (kind) {
708  FixupKind = Hexagon::fixup_Hexagon_10_X;
709  break;
710  default:
711  raise_relocation_error(bits, kind);
712  }
713  } else
714  raise_relocation_error(bits, kind);
715  break;
716 
717  case 9:
718  if (MCID.isBranch() ||
720  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
722  else if (*Extended)
723  FixupKind = Hexagon::fixup_Hexagon_9_X;
724  else
725  raise_relocation_error(bits, kind);
726  break;
727 
728  case 8:
729  if (*Extended)
730  FixupKind = Hexagon::fixup_Hexagon_8_X;
731  else
732  raise_relocation_error(bits, kind);
733  break;
734 
735  case 7:
736  if (MCID.isBranch() ||
738  FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
740  else if (*Extended)
741  FixupKind = Hexagon::fixup_Hexagon_7_X;
742  else
743  raise_relocation_error(bits, kind);
744  break;
745 
746  case 6:
747  if (*Extended) {
748  switch (kind) {
751  break;
752  // This is part of an extender, GOT_11 is a
753  // Word32_U6 unsigned/truncated reloc.
756  break;
759  break;
762  break;
765  break;
767  FixupKind = Hexagon::fixup_Hexagon_6_X;
768  break;
769  default:
770  raise_relocation_error(bits, kind);
771  }
772  } else
773  raise_relocation_error(bits, kind);
774  break;
775 
776  case 0:
777  FixupKind = getFixupNoBits(MCII, MI, MO, kind);
778  break;
779  }
780 
781  MCExpr const *FixupExpression =
782  (*Addend > 0 && isPCRel(FixupKind))
784  MCConstantExpr::create(*Addend, MCT), MCT)
785  : MO.getExpr();
786 
787  MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
788  MCFixupKind(FixupKind), MI.getLoc());
789  Fixups.push_back(fixup);
790  // All of the information is in the fixup.
791  return 0;
792 }
793 
794 unsigned
796  SmallVectorImpl<MCFixup> &Fixups,
797  MCSubtargetInfo const &STI) const {
798  assert(!MO.isImm());
799  if (MO.isReg()) {
800  unsigned Reg = MO.getReg();
803  switch(MI.getOpcode()){
804  case Hexagon::A2_tfrrcr:
805  case Hexagon::A2_tfrcrr:
806  if(Reg == Hexagon::M0)
807  Reg = Hexagon::C6;
808  if(Reg == Hexagon::M1)
809  Reg = Hexagon::C7;
810  }
811  return MCT.getRegisterInfo()->getEncodingValue(Reg);
812  }
813 
814  return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
815 }
816 
818  MCRegisterInfo const &MRI,
819  MCContext &MCT) {
820  return new HexagonMCCodeEmitter(MII, MCT);
821 }
822 
823 #define ENABLE_INSTR_PREDICATE_VERIFIER
824 #include "HexagonGenMCCodeEmitter.inc"
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
STATISTIC(NumFunctions,"Total number of functions")
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
size_t i
bool isReg() const
Definition: MCInst.h:56
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:384
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
ExprKind getKind() const
Definition: MCExpr.h:70
bool isBundle(MCInst const &MCI)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
uint64_t getBinaryCodeForInstr(MCInst const &MI, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
demanded bits
bool isSubInstruction(MCInst const &MCI)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:66
uint32_t parseBits(size_t Instruction, size_t Last, MCInst const &MCB, MCInst const &MCI) const
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
bool isImmext(MCInst const &MCI)
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const
EncodeSingleInstruction - Emit a single.
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:261
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
const MCInstrDesc HexagonInsts[]
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:161
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
Context object for machine code objects.
Definition: MCContext.h:51
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
Function Alias Analysis false
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
bool s23_2_reloc(MCExpr const &Expr)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:429
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const override
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
const MCExpr * getExpr() const
Definition: MCInst.h:93
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:514
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
Lanai::Fixups FixupKind(const MCExpr *Expr)
uint32_t Offset
MCExpr const & getExpr(MCExpr const &Expr)
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
SMLoc getLoc() const
Definition: MCInst.h:162
Definition for classes that emit Hexagon machine code from MCInsts.
Binary assembler expressions.
Definition: MCExpr.h:388
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:82
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts a value to fix up the immediate of an LDI Rd, K instruction.
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Promote Memory to Register
Definition: Mem2Reg.cpp:100
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:378
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getOpcode() const
Definition: MCInst.h:159
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT)
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:245
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:517
unsigned getNumOperands() const
Definition: MCInst.h:166
#define I(x, y, z)
Definition: MD5.cpp:54
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInst * getInst() const
Definition: MCInst.h:102
References to labels and assigned expressions.
Definition: MCExpr.h:39
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:503
size_t bundleSize(MCInst const &MCI)
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:69
const unsigned Kind
VariantKind getKind() const
Definition: MCExpr.h:313
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
#define HEXAGON_INSTR_SIZE
Definition: Hexagon.h:30
aarch64 promote const
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
Definition: Value.h:71
static bool RegisterMatches(unsigned Consumer, unsigned Producer, unsigned Producer2)
Binary expressions.
Definition: MCExpr.h:37
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:100
unsigned getDuplexRegisterNumbering(unsigned Reg)
IRTranslator LLVM IR MI
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:149
unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl< MCFixup > &Fixups, MCSubtargetInfo const &STI) const
Return binary encoding of operand.
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)