41 #define DEBUG_TYPE "regalloc"
46 "Live Interval Analysis",
false,
false)
56 cl::desc(
"Eagerly compute live intervals for all physreg units."));
65 "Use segment set for the computation of the live ranges of physregs."));
82 DomTree(nullptr), LRCalc(nullptr) {
92 for (
unsigned i = 0, e = VirtRegIntervals.size();
i != e; ++
i)
94 VirtRegIntervals.clear();
97 RegMaskBlocks.
clear();
99 for (
unsigned i = 0, e = RegUnitRanges.size();
i != e; ++
i)
100 delete RegUnitRanges[
i];
101 RegUnitRanges.clear();
104 VNInfoAllocator.
Reset();
114 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
115 Indexes = &getAnalysis<SlotIndexes>();
116 DomTree = &getAnalysis<MachineDominatorTree>();
126 computeLiveInRegUnits();
140 OS <<
"********** INTERVALS **********\n";
143 for (
unsigned i = 0, e = RegUnitRanges.size();
i != e; ++
i)
155 for (
unsigned i = 0, e = RegMaskSlots.size(); i != e; ++
i)
156 OS <<
' ' << RegMaskSlots[i];
162 void LiveIntervals::printInstrs(
raw_ostream &OS)
const {
163 OS <<
"********** MACHINEINSTRS **********\n";
164 MF->
print(OS, Indexes);
167 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
168 void LiveIntervals::dumpInstrs()
const {
173 LiveInterval* LiveIntervals::createInterval(
unsigned reg) {
182 void LiveIntervals::computeVirtRegInterval(
LiveInterval &LI) {
183 assert(LRCalc &&
"LRCalc not initialized.");
184 assert(LI.
empty() &&
"Should only compute empty intervals.");
187 computeDeadValues(LI,
nullptr);
190 void LiveIntervals::computeVirtRegs() {
199 void LiveIntervals::computeRegMasks() {
204 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[
MBB.
getNumber()];
205 RMB.first = RegMaskSlots.size();
225 if (
const uint32_t *
Mask = MBB.getEndClobberMask(TRI)) {
226 assert(!MBB.empty() &&
"empty return block?");
227 RegMaskSlots.push_back(
233 RMB.second = RegMaskSlots.size() - RMB.first;
251 void LiveIntervals::computeRegUnitRange(
LiveRange &LR,
unsigned Unit) {
252 assert(LRCalc &&
"LRCalc not initialized.");
273 unsigned Reg = *Supers;
275 LRCalc->extendToUses(LR, Reg);
289 void LiveIntervals::computeLiveInRegUnits() {
291 DEBUG(
dbgs() <<
"Computing live-in reg-units in ABI blocks.\n");
308 for (
const auto &LI : MBB->
liveins()) {
310 unsigned Unit = *Units;
324 DEBUG(
dbgs() <<
"Created " << NewRanges.
size() <<
" new intervals.\n");
327 for (
unsigned i = 0, e = NewRanges.
size();
i != e; ++
i) {
328 unsigned Unit = NewRanges[
i];
329 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
336 for (
auto VNI : VNIs) {
355 while (!WorkList.
empty()) {
364 assert(ExtVNI == VNI &&
"Unexpected existing value number");
368 !UsedPHIs.
insert(VNI).second)
372 if (!LiveOut.
insert(Pred).second)
377 WorkList.
push_back(std::make_pair(Stop, PVNI));
383 DEBUG(
dbgs() <<
" live-in at " << BlockStart <<
'\n');
388 if (!LiveOut.
insert(Pred).second)
392 "Wrong value out of predecessor");
393 WorkList.
push_back(std::make_pair(Stop, VNI));
400 DEBUG(
dbgs() <<
"Shrink: " << *li <<
'\n');
402 &&
"Can only shrink virtual registers");
405 bool NeedsCleanup =
false;
432 <<
"Warning: Instr claims to read non-existent value in "
441 WorkList.
push_back(std::make_pair(Idx, VNI));
453 bool CanSeparate = computeDeadValues(*li, dead);
454 DEBUG(
dbgs() <<
"Shrunk: " << *li <<
'\n');
460 bool MayHaveSplitComponents =
false;
461 for (
auto VNI : LI.
valnos) {
466 assert(I != LI.
end() &&
"Missing segment for VNI");
470 unsigned VReg = LI.
reg;
484 DEBUG(
dbgs() <<
"Dead PHI at " << Def <<
" may separate interval\n");
485 MayHaveSplitComponents =
true;
489 assert(MI &&
"No instruction defining live value");
492 DEBUG(
dbgs() <<
"All defs dead: " << Def <<
'\t' << *MI);
497 return MayHaveSplitComponents;
501 DEBUG(
dbgs() <<
"Shrink: " << SR <<
'\n');
503 &&
"Can only shrink virtual registers");
514 unsigned SubReg = MO.getSubReg();
517 if ((LaneMask & SR.
LaneMask).none())
539 WorkList.
push_back(std::make_pair(Idx, VNI));
551 for (
auto VNI : SR.
valnos) {
555 assert(Segment !=
nullptr &&
"Missing segment for VNI");
560 DEBUG(
dbgs() <<
"Dead PHI at " << VNI->
def <<
" may separate interval\n");
566 DEBUG(
dbgs() <<
"Shrunk: " << SR <<
'\n');
572 assert(LRCalc &&
"LRCalc not initialized.");
574 for (
unsigned i = 0, e = Indices.
size();
i != e; ++
i)
575 LRCalc->
extend(LR, Indices[
i], 0, Undefs);
597 if (EndPoints) EndPoints->
push_back(MBBEnd);
606 SuccI != SuccE; ++SuccI) {
614 std::tie(MBBStart, MBBEnd) = Indexes->
getMBBRange(MBB);
632 if (EndPoints) EndPoints->
push_back(MBBEnd);
670 for (
const LiveInterval::SubRange &SR : LI.
subranges()) {
671 SRs.push_back(std::make_pair(&SR, SR.find(LI.
begin()->end)));
680 if (RI->end.isBlock())
694 for (
auto &RUP : RU) {
696 LiveRange::const_iterator &I = RUP.second;
697 if (I == RURange.
end())
700 if (I == RURange.
end() || I->start >= RI->end)
722 for (
auto &SRP : SRs) {
723 const LiveInterval::SubRange &SR = *SRP.first;
724 LiveRange::const_iterator &I = SRP.second;
728 if (I == SR.
end() || I->start >= RI->end)
736 bool IsFullWrite =
false;
738 if (!MO.isReg() || MO.getReg() !=
Reg)
743 if ((UseMask & ~DefinedLanesMask).any())
745 }
else if (MO.getSubReg() == 0) {
758 LiveRange::const_iterator
N = std::next(RI);
759 if (N != LI.
end() && N->start == RI->end)
793 return MBB1 == MBB2 ? MBB1 :
nullptr;
859 std::lower_bound(Slots.
begin(), Slots.
end(), LiveI->start);
868 assert(*SlotI >= LiveI->start);
870 while (*SlotI < LiveI->
end) {
880 if (++SlotI == SlotE)
888 while (*SlotI < LiveI->start)
889 if (++SlotI == SlotE)
913 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
914 UpdateFlags(UpdateFlags) {}
922 return &LIS.getRegUnit(Unit);
923 return LIS.getCachedRegUnit(Unit);
929 DEBUG(
dbgs() <<
"handleMove " << OldIdx <<
" -> " << NewIdx <<
": " << *MI);
930 bool hasRegMask =
false;
944 unsigned Reg = MO.getReg();
950 unsigned SubReg = MO.getSubReg();
951 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg)
952 :
MRI.getMaxLaneMaskForVReg(Reg);
954 if ((S.LaneMask & LaneMask).none())
956 updateRange(S, Reg, S.LaneMask);
970 updateRegMaskSlots();
977 if (!Updated.insert(&LR).second)
988 dbgs() <<
":\t" << LR <<
'\n';
993 handleMoveUp(LR, Reg, LaneMask);
1018 if (
MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end))
1020 if (MO->isReg() && MO->isUse())
1021 MO->setIsKill(
false);
1030 LR.
advanceTo(Next, NewIdx.getBaseIndex());
1032 if (NewIdxIn == E ||
1035 Prev->end = NewIdx.getRegSlot();
1038 OldIdxIn->end = Next->start;
1045 OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());
1055 OldIdxOut = OldIdxIn;
1062 VNInfo *OldIdxVNI = OldIdxOut->valno;
1063 assert(OldIdxVNI->
def == OldIdxOut->start &&
"Inconsistent def");
1069 OldIdxVNI->
def = NewIdxDef;
1070 OldIdxOut->start = OldIdxVNI->
def;
1079 = LR.
advanceTo(OldIdxOut, NewIdx.getRegSlot());
1080 bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1081 if (!OldIdxDefIsDead &&
1085 if (OldIdxOut != LR.
begin() &&
1087 OldIdxOut->start)) {
1092 IPrev->end = OldIdxOut->end;
1096 assert(INext != E &&
"Must have following segment");
1102 INext->start = OldIdxOut->end;
1103 INext->valno->def = INext->start;
1106 if (AfterNewIdx == E) {
1111 std::copy(std::next(OldIdxOut), E, OldIdxOut);
1116 DefVNI->
def = NewIdxDef;
1119 Prev->end = NewIdxDef;
1125 std::copy(std::next(OldIdxOut), std::next(AfterNewIdx), OldIdxOut);
1133 Prev->valno->def = NewIdxDef;
1136 DefVNI->
def = Prev->start;
1141 DefVNI->
def = NewIdxDef;
1142 assert(DefVNI != AfterNewIdx->valno);
1148 if (AfterNewIdx != E &&
1152 assert(AfterNewIdx->valno != OldIdxVNI &&
"Multiple defs of value?");
1160 assert(AfterNewIdx != OldIdxOut &&
"Inconsistent iterators");
1161 std::copy(std::next(OldIdxOut), AfterNewIdx, OldIdxOut);
1164 VNInfo *NewSegmentVNI = OldIdxVNI;
1165 NewSegmentVNI->
def = NewIdxDef;
1195 = std::max(OldIdxIn->start.getDeadSlot(),
1196 NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));
1197 OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, Reg, LaneMask);
1200 OldIdxOut = std::next(OldIdxIn);
1204 OldIdxOut = OldIdxIn;
1205 OldIdxIn = OldIdxOut != LR.
begin() ? std::prev(OldIdxOut) : E;
1212 VNInfo *OldIdxVNI = OldIdxOut->valno;
1213 assert(OldIdxVNI->
def == OldIdxOut->start &&
"Inconsistent def");
1214 bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1220 assert(NewIdxOut->valno != OldIdxVNI &&
1221 "Same value defined more than once?");
1223 if (!OldIdxDefIsDead) {
1226 OldIdxVNI->
def = NewIdxDef;
1227 OldIdxOut->start = NewIdxDef;
1236 if (!OldIdxDefIsDead) {
1238 if (OldIdxIn != E &&
1242 assert(NewIdxIn == LR.
find(NewIdx.getBaseIndex()));
1252 std::copy_backward(NewIdxIn, OldIdxIn, OldIdxOut);
1262 Next->valno->def = SplitPos;
1267 NewSegment->valno->def = SplitPos;
1271 OldIdxOut->start = NewIdxDef;
1272 OldIdxVNI->
def = NewIdxDef;
1274 OldIdxIn->end = NewIdx.getRegSlot();
1282 std::copy_backward(NewIdxOut, OldIdxOut, std::next(OldIdxOut));
1285 VNInfo *NewSegmentVNI = OldIdxVNI;
1288 NewSegmentVNI->
def = NewIdxDef;
1293 void updateRegMaskSlots() {
1295 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1297 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1298 "No RegMask at OldIdx.");
1299 *RI = NewIdx.getRegSlot();
1300 assert((RI == LIS.RegMaskSlots.begin() ||
1302 "Cannot move regmask instruction above another call");
1303 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1305 "Cannot move regmask instruction below another call");
1316 unsigned SubReg = MO.getSubReg();
1317 if (SubReg != 0 && LaneMask.
any()
1318 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())
1322 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1323 if (InstSlot > LastUse && InstSlot < OldIdx)
1331 assert(Before < OldIdx &&
"Expected upwards move");
1344 while (MII != Begin) {
1345 if ((--MII)->isDebugValue())
1355 if (MO->isReg() && !MO->isUndef() &&
1357 TRI.hasRegUnit(MO->getReg(),
Reg))
1372 "Cannot handle moves across basic block boundaries.");
1374 HMEditor HME(*
this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1383 HMEditor HME(*
this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1394 if (LII == LR.
begin()) {
1399 if (LII != LR.
end() && LII->start < endIdx)
1400 lastUseIdx = LII->end;
1425 if ((Mask & LaneMask).none())
1429 if (!isStartValid) {
1430 if (LII->end.isDead()) {
1432 if (LII != LR.
begin())
1433 prevStart = std::prev(LII)->start;
1439 LII = LR.
find(prevStart);
1458 }
else if (LII->start != instrIdx.
getRegSlot()) {
1468 }
else if (MO.
isUse()) {
1472 if (!isEndValid && !LII->end.isBlock())
1490 while (End != MBB->
end() && !Indexes->
hasIndex(*End))
1494 if (End == MBB->
end())
1508 MOI != MOE; ++MOI) {
1517 for (
unsigned i = 0, e = OrigRegs.
size();
i != e; ++
i) {
1518 unsigned Reg = OrigRegs[
i];
1528 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1530 repairOldRegInRange(Begin, End, endIdx, LI, Reg);
1546 if (VNI !=
nullptr) {
1553 if (
VNInfo *SVNI = S.getVNInfoAt(Pos))
1555 S.removeValNo(SVNI);
1563 unsigned NumComp = ConEQ.
Classify(LI);
1566 DEBUG(
dbgs() <<
" Split " << NumComp <<
" components: " << LI <<
'\n');
1567 unsigned Reg = LI.
reg;
1569 for (
unsigned I = 1; I < NumComp; ++
I) {
1578 assert(LRCalc &&
"LRCalc not initialized.");
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void push_back(const T &Elt)
bool isEHPad() const
Returns true if the block is a landing pad.
const_iterator end(StringRef path)
Get end iterator over path.
mop_iterator operands_end()
bool isValid() const
Check if the iterator is at the end of the list.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ArrayRef< SlotIndex > getRegMaskSlots() const
getRegMaskSlots - Returns a sorted array of slot indices of all instructions with register mask opera...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SlotIndex getInstructionIndex(const MachineInstr &MI) const
Returns the base index for the given instruction.
iterator_range< livein_iterator > liveins() const
cl::opt< bool > UseSegmentSetForPhysRegs
SlotIndex def
The index of the defining instruction.
void createDeadDefs(LiveRange &LR, unsigned Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
void updateAllRanges(MachineInstr *MI)
Update all live ranges touched by MI, assuming a move from OldIdx to NewIdx.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
A Module instance is used to store all the information related to an LLVM module. ...
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool runOnMachineFunction(MachineFunction &) override
runOnMachineFunction - pass entry point
Interval Class - An Interval is a set of nodes defined such that every node in the interval has all o...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static LaneBitmask getAll()
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
MIBundleOperands - Iterate over all operands in a bundle of machine instructions. ...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void removeMachineInstrFromMaps(MachineInstr &MI)
Remove the given machine instruction from the mapping.
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
INITIALIZE_PASS_BEGIN(LiveIntervals,"liveintervals","Live Interval Analysis", false, false) INITIALIZE_PASS_END(LiveIntervals
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
A live range for subregisters.
This represents a simple continuous liveness interval for a value.
SlotIndex endPoint() const
Return the end point of the last live range segment to interact with the instruction, if any.
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
void markUnused()
Mark this value as unused.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
VNInfo - Value Number Information.
void print(raw_ostream &O, const Module *=nullptr) const override
print - Implement the dump method.
iterator_range< mop_iterator > operands()
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
void flushSegmentSet()
Flush segment set into the regular segment vector.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
void Distribute(LiveInterval &LI, LiveInterval *LIV[], MachineRegisterInfo &MRI)
Distribute values in LI into a separate LiveIntervals for each connected component.
LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst)
Given a register and an instruction, adds a live segment from that instruction to the end of its MBB...
This class represents the liveness of a register, stack slot, etc.
static bool isEarlierInstr(SlotIndex A, SlotIndex B)
isEarlierInstr - Return true if A refers to an instruction earlier than B.
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill...
uint64_t getEntryFreq() const
void clear()
clear - Clear all bits.
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
intervalIsInOneMBB - If LI is confined to a single basic block, return a pointer to that block...
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
ArrayRef< SlotIndex > getRegMaskSlotsInBlock(unsigned MBBNum) const
getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all instructions with register mas...
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it...
ArrayRef< const uint32_t * > getRegMaskBits() const
getRegMaskBits() - Returns an array of register mask pointers corresponding to getRegMaskSlots().
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
VNInfo::Allocator & getVNInfoAllocator()
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
Result of a LiveRange query.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SmallVector< std::pair< SlotIndex, VNInfo * >, 16 > ShrinkToUsesWorkList
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
constexpr bool any() const
LLVM_NODISCARD bool empty() const
bool isUnused() const
Returns true if this value is unused.
static reg_instr_iterator reg_instr_end()
SlotIndex getNextNonNullIndex(SlotIndex Index)
Returns the next non-null index, if one exists.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range...
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isBundled() const
Return true if this instruction part of a bundle.
VNInfo * valueOutOrDead() const
Returns the value alive at the end of the instruction, if any.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses...
static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes, ShrinkToUsesWorkList &WorkList, const LiveRange &OldRange)
bool livein_empty() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
AnalysisUsage & addPreservedID(const void *ID)
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
const float huge_valf
Use this rather than HUGE_VALF; the latter causes warnings on MSVC.
const uint32_t * getBeginClobberMask(const TargetRegisterInfo *TRI) const
Get the clobber mask for the start of this basic block.
char & LiveIntervalsID
LiveIntervals - This analysis keeps track of the live ranges of virtual and physical registers...
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
size_t size() const
size - Get the array size.
LiveRange * getCachedRegUnit(unsigned Unit)
getCachedRegUnit - Return the live range for Unit if it has already been computed, or NULL if it hasn't been computed yet.
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const MachineBasicBlock * getParent() const
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
bool isDebugValue() const
void reset(const MachineFunction *MF, SlotIndexes *, MachineDominatorTree *, VNInfo::Allocator *)
reset - Prepare caches for a new set of non-overlapping live ranges.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
initializer< Ty > init(const Ty &Val)
bool hasAtLeastOneValue() const
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
SlotIndexes * getSlotIndexes() const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
bool isValid() const
Returns true if this is a valid index.
unsigned const MachineRegisterInfo * MRI
iterator_range< use_nodbg_iterator > use_nodbg_operands(unsigned Reg) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void swap(SmallVectorImpl &RHS)
std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Use)
Attempt to extend a value defined after StartIdx to include Use.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
MachineInstrBuilder & UseMI
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Live Interval static false cl::opt< bool > EnablePrecomputePhysRegs("precompute-phys-liveness", cl::Hidden, cl::desc("Eagerly compute live intervals for all physreg units."))
Represent the analysis usage information of a pass.
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
void initializeLiveIntervalsPass(PassRegistry &)
reg_instr_iterator reg_instr_begin(unsigned RegNo) const
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
VNInfo * valueDefined() const
Return the value defined by this instruction, if any.
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
HMEditor(LiveIntervals &LIS, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
iterator_range< pred_iterator > predecessors()
void verify() const
Walk the range and assert if any invariants fail to hold.
bool subRegLivenessEnabled() const
succ_iterator succ_begin()
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< unsigned > OrigRegs)
repairIntervalsInRange - Update live intervals for instructions in a range of iterators.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
pred_iterator pred_begin()
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
unsigned id
The ID number of this value.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
ArrayRef< const uint32_t * > getRegMaskBitsInBlock(unsigned MBBNum) const
getRegMaskBitsInBlock - Returns an array of mask pointers corresponding to getRegMaskSlotsInBlock(MBB...
Iterator for intrusive lists based on ilist_node.
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
static LaneBitmask getNone()
LiveRange * getRegUnitLI(unsigned Unit)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
LiveInterval & getInterval(unsigned Reg)
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &Instr)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
A range adaptor for a pair of iterators.
void repairIndexesInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End)
Repair indexes after adding and removing instructions.
LiveInterval & createEmptyInterval(unsigned Reg)
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
SlotIndex beginIndex() const
beginIndex - Return the lowest numbered slot covered.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B)
Return true if A refers to the same instruction as B or an earlier one.
pointer data()
Return a pointer to the vector's buffer, even if empty().
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void addKillFlags(const VirtRegMap *)
addKillFlags - Add kill flags to any instruction that kills a virtual register.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
AnalysisUsage & addRequiredTransitiveID(char &ID)
AnalysisUsage & addRequiredTransitive()
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasInterval(unsigned Reg) const
bool reg_empty(unsigned RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
~LiveIntervals() override
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
std::vector< uint8_t > Unit
unsigned getReg() const
getReg - Returns the register number.
bool isValid() const
isValid - Returns true until all the operands have been visited.
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
mop_iterator operands_begin()
static LLVM_ATTRIBUTE_UNUSED Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart, bool UpdateFlags=false)
moveIntoBundle - Update intervals for operands of MI so that they begin/end on the SlotIndex for Bund...
This class implements an extremely fast bulk output stream that can only output to a stream...
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
iterator FindSegmentContaining(SlotIndex Idx)
Return an iterator to the segment that contains the specified index, or end() if there is none...
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
SlotIndex - An opaque wrapper around machine indexes.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
unsigned pred_size() const
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx...
bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const
Returns true if liveness for register class RC should be tracked at the subregister level...
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
handleMove - call this method to notify LiveIntervals that instruction 'mi' has been moved within a b...
LiveInterval & createAndComputeVirtRegInterval(unsigned Reg)
static void createSegmentsForValues(LiveRange &LR, iterator_range< LiveInterval::vni_iterator > VNIs)
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.