50 cl::desc(
"Enable the CCMP formation pass"),
54 cl::desc(
"Enable the machine combiner pass"),
58 cl::desc(
"Suppress STP for AArch64"),
62 "aarch64-enable-simd-scalar",
63 cl::desc(
"Enable use of AdvSIMD scalar integer instructions"),
68 cl::desc(
"Enable the promote constant pass"),
72 "aarch64-enable-collect-loh",
73 cl::desc(
"Enable the pass that emits the linker optimization hints (LOH)"),
78 cl::desc(
"Enable the pass that removes dead"
79 " definitons and replaces stores to"
80 " them with stores to the zero"
85 "aarch64-enable-copyelim",
90 cl::desc(
"Enable the load/store pair"
91 " optimization pass"),
96 cl::desc(
"Run SimplifyCFG after expanding atomic operations"
97 " to make use of cmpxchg flow-based information"),
102 cl::desc(
"Run early if-conversion"),
107 cl::desc(
"Enable the condition optimizer pass"),
112 cl::desc(
"Work around Cortex-A53 erratum 835769"),
117 cl::desc(
"Enable the type promotion pass"),
122 cl::desc(
"Enable optimizations on complex GEPs"),
127 cl::desc(
"Relax out of range conditional branches"));
132 cl::desc(
"Enable the global merge pass"));
136 cl::desc(
"Enable the loop data prefetch pass"),
168 return llvm::make_unique<AArch64_MachoTargetObjectFile>();
170 return llvm::make_unique<AArch64_ELFTargetObjectFile>();
178 return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
180 return "e-m:o-i64:64-i128:128-n32:64-S128";
182 return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
183 return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
209 TT, CPU, FS, Options,
212 isLittle(LittleEndian) {
218 #ifdef LLVM_BUILD_GLOBAL_ISEL
222 std::unique_ptr<CallLowering> CallLoweringInfo;
223 std::unique_ptr<InstructionSelector> InstSelector;
224 std::unique_ptr<LegalizerInfo>
Legalizer;
225 std::unique_ptr<RegisterBankInfo> RegBankInfo;
228 return CallLoweringInfo.get();
232 return InstSelector.get();
240 return RegBankInfo.get();
265 I = llvm::make_unique<AArch64Subtarget>(
TargetTriple, CPU, FS, *
this,
267 #ifndef LLVM_BUILD_GLOBAL_ISEL
270 AArch64GISelActualAccessor *GISel =
271 new AArch64GISelActualAccessor();
272 GISel->CallLoweringInfo.reset(
283 GISel->RegBankInfo.reset(RBI);
285 I->setGISelAccessor(*GISel);
290 void AArch64leTargetMachine::anchor() { }
298 void AArch64beTargetMachine::anchor() { }
318 return getTM<AArch64TargetMachine>();
330 void addIRPasses()
override;
331 bool addPreISel()
override;
332 bool addInstSelector()
override;
333 #ifdef LLVM_BUILD_GLOBAL_ISEL
334 bool addIRTranslator()
override;
335 bool addLegalizeMachineIR()
override;
336 bool addRegBankSelect()
override;
337 bool addGlobalInstructionSelect()
override;
339 bool addILPOpts()
override;
340 void addPreRegAlloc()
override;
341 void addPostRegAlloc()
override;
342 void addPreSched2()
override;
343 void addPreEmitPass()
override;
355 return new AArch64PassConfig(
this, PM);
358 void AArch64PassConfig::addIRPasses() {
397 bool AArch64PassConfig::addPreISel() {
419 bool AArch64PassConfig::addInstSelector() {
431 #ifdef LLVM_BUILD_GLOBAL_ISEL
432 bool AArch64PassConfig::addIRTranslator() {
437 bool AArch64PassConfig::addLegalizeMachineIR() {
442 bool AArch64PassConfig::addRegBankSelect() {
447 bool AArch64PassConfig::addGlobalInstructionSelect() {
453 bool AArch64PassConfig::addILPOpts() {
468 void AArch64PassConfig::addPreRegAlloc() {
482 void AArch64PassConfig::addPostRegAlloc() {
492 void AArch64PassConfig::addPreSched2() {
500 void AArch64PassConfig::addPreEmitPass() {
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
Target & getTheAArch64beTarget()
static cl::opt< bool > EnableAddressTypePromotion("aarch64-enable-type-promotion", cl::Hidden, cl::desc("Enable the type promotion pass"), cl::init(true))
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
void initializeAArch64A53Fix835769Pass(PassRegistry &)
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
const AArch64Subtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
void initializeAArch64LoadStoreOptPass(PassRegistry &)
Target & getTheAArch64leTarget()
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
Analysis pass providing the TargetTransformInfo.
This class provides the information for the target register banks.
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
FunctionPass * createAArch64ConditionalCompares()
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool IsLittleEndian)
Create an AArch64 architecture model.
ModulePass * createAArch64PromoteConstantPass()
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
FunctionPass * createAArch64AddressTypePromotionPass()
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createLoopDataPrefetchPass()
const Triple & getTargetTriple() const
This file declares the targeting of the RegisterBankInfo class for AArch64.
FunctionPass * createAArch64CollectLOHPass()
Holds all the information related to register banks.
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
FunctionPass * createAArch64VectorByElementOptPass()
createAArch64VectorByElementOptPass - returns an instance of the vector by element optimization pass...
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
void initializeGlobalISel(PassRegistry &Registry)
Initialize all passes linked into the GlobalISel library.
void initializeLDTLSCleanupPass(PassRegistry &)
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
FunctionPass * createAArch64RedundantCopyEliminationPass()
Target & getTheARM64Target()
void initializeAArch64CollectLOHPass(PassRegistry &)
Target-Independent Code Generator Pass Configuration Options.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createAArch64A57FPLoadBalancing()
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
This file declares the targeting of the Machinelegalizer class for AArch64.
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
Function Alias Analysis false
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead"" definitons and replaces stores to"" them with stores to the zero"" register"), cl::init(true))
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
std::unique_ptr< ScheduleDAGMutation > createMacroFusionDAGMutation(const TargetInstrInfo *TII)
FunctionPass * createInterleavedAccessPass(const TargetMachine *TM)
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
void initializeAArch64PromoteConstantPass(PassRegistry &)
FunctionPass * createSeparateConstOffsetFromGEPPass(const TargetMachine *TM=nullptr, bool LowerGEP=false)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
void LLVMInitializeAArch64Target()
void initializeAArch64VectorByElementOptPass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(int Threshold=-1, std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createAArch64AdvSIMDScalar()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
~AArch64TargetMachine() override
This file declares the targeting of the InstructionSelector class for AArch64.
Triple - Helper class for working with autoconf configuration names.
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden, cl::desc("Work around Cortex-A53 erratum 835769"), cl::init(false))
void initializeAArch64AddressTypePromotionPass(PassRegistry &)
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
FunctionPass * createAArch64A53Fix835769()
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
This pass is responsible for selecting generic machine instructions to target-specific instructions...
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Target - Wrapper for Target specific information.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
FunctionPass * createAArch64ConditionOptimizerPass()
TargetIRAnalysis getTargetIRAnalysis() override
Get the TargetIRAnalysis for this target.
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG...
Provides the logic to select generic machine instructions.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations"" to make use of cmpxchg flow-based information"), cl::init(true))
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
This class provides the information for the target register banks.
const TargetRegisterInfo * TRI
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
FunctionPass * createAArch64StorePairSuppressPass()
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
This file describes how to lower LLVM calls to machine code calls.
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
const TargetInstrInfo * TII
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair"" optimization pass"), cl::init(true), cl::Hidden)
StringRef getValueAsString() const
Return the attribute's value as a string.
This file declares the IRTranslator pass.
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
FunctionPass * createAArch64DeadRegisterDefinitions()
StringRef - Represent a constant reference to a string, i.e.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
void initializeAArch64StorePairSuppressPass(PassRegistry &)