34 #define DEBUG_TYPE "instr-emitter"
62 unsigned &NumImpUses) {
70 NumImpUses = N - NumExpUses;
71 for (
unsigned I = N;
I > NumExpUses; --
I) {
72 if (isa<RegisterMaskSDNode>(Node->
getOperand(
I - 1)))
87 EmitCopyFromReg(
SDNode *Node,
unsigned ResNo,
bool IsClone,
bool IsCloned,
95 bool isNew = VRBaseMap.
insert(std::make_pair(
Op, SrcReg)).second;
97 assert(isNew &&
"Node emitted out of order - early");
103 bool MatchReg =
true;
111 if (!IsClone && !IsCloned)
121 }
else if (DestReg != SrcReg)
132 if (
User->isMachineOpcode()) {
164 assert(UseRC->
hasType(VT) &&
"Incompatible phys register def and uses!");
178 VRBase).addReg(SrcReg);
184 bool isNew = VRBaseMap.
insert(std::make_pair(Op, VRBase)).second;
186 assert(isNew &&
"Node emitted out of order - early");
191 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(
SDNode *Node,
192 unsigned ResNo)
const {
207 void InstrEmitter::CreateVirtualRegisters(
SDNode *Node,
210 bool IsClone,
bool IsCloned,
213 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
244 if (!VRBase && !IsClone && !IsCloned)
264 assert(RC &&
"Isn't a register operand!");
271 if (
i < NumResults) {
275 bool isNew = VRBaseMap.
insert(std::make_pair(Op, VRBase)).second;
277 assert(isNew &&
"Node emitted out of order - early");
284 unsigned InstrEmitter::getVR(
SDValue Op,
298 TII->
get(TargetOpcode::IMPLICIT_DEF), VReg);
303 assert(I != VRBaseMap.
end() &&
"Node emitted out of order - late");
317 bool IsDebug,
bool IsClone,
bool IsCloned) {
320 "Chain and glue operands should occur at end of operand list!");
322 unsigned VReg = getVR(Op, VRBaseMap);
334 if (IIOpNum < II->getNumOperands())
340 if (!ConstrainedRC) {
342 assert(OpRC &&
"Constraints cannot be fulfilled for allocation");
345 TII->
get(TargetOpcode::COPY), NewVReg).addReg(VReg);
349 "Constraining an allocatable VReg produced an unallocatable class?");
364 !(IsClone || IsCloned);
388 bool IsDebug,
bool IsClone,
bool IsCloned) {
390 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
391 IsDebug, IsClone, IsCloned);
406 TGA->getTargetFlags());
408 MIB.
addMBB(BBNode->getBasicBlock());
415 unsigned Align =
CP->getAlignment();
428 if (
CP->isMachineConstantPoolEntry())
435 }
else if (
auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
436 MIB.
addSym(SymNode->getMCSymbol());
440 BA->getTargetFlags());
442 MIB.
addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
446 "Chain and glue operands should occur at end of operand list!");
447 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
448 IsDebug, IsClone, IsCloned);
452 unsigned InstrEmitter::ConstrainForSubReg(
unsigned VReg,
unsigned SubIdx,
469 assert(RC &&
"No legal register class for VT supports that SubIdx");
471 BuildMI(*MBB, InsertPos, DL, TII->
get(TargetOpcode::COPY), NewReg)
478 void InstrEmitter::EmitSubregNode(
SDNode *Node,
480 bool IsClone,
bool IsCloned) {
497 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
501 unsigned SubIdx = cast<ConstantSDNode>(Node->
getOperand(1))->getZExtValue();
516 unsigned SrcReg, DstReg, DefSubIdx;
519 SubIdx == DefSubIdx &&
528 TII->
get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
535 Reg = ConstrainForSubReg(Reg, SubIdx,
546 TII->
get(TargetOpcode::COPY), VRBase);
548 CopyMI.
addReg(Reg, 0, SubIdx);
552 }
else if (Opc == TargetOpcode::INSERT_SUBREG ||
553 Opc == TargetOpcode::SUBREG_TO_REG) {
557 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
575 assert(SRC &&
"No register class supports VT and SubIdx for INSERT_SUBREG");
586 if (Opc == TargetOpcode::SUBREG_TO_REG) {
590 AddOperand(MIB, N0, 0,
nullptr, VRBaseMap,
false,
593 AddOperand(MIB, N1, 0,
nullptr, VRBaseMap,
false,
596 MBB->
insert(InsertPos, MIB);
598 llvm_unreachable(
"Node is not insert_subreg, extract_subreg, or subreg_to_reg");
601 bool isNew = VRBaseMap.
insert(std::make_pair(Op, VRBase)).second;
603 assert(isNew &&
"Node emitted out of order - early");
611 InstrEmitter::EmitCopyToRegClassNode(
SDNode *Node,
613 unsigned VReg = getVR(Node->
getOperand(0), VRBaseMap);
616 unsigned DstRCIdx = cast<ConstantSDNode>(Node->
getOperand(1))->getZExtValue();
621 NewVReg).addReg(VReg);
624 bool isNew = VRBaseMap.
insert(std::make_pair(Op, NewVReg)).second;
626 assert(isNew &&
"Node emitted out of order - early");
631 void InstrEmitter::EmitRegSequence(
SDNode *Node,
633 bool IsClone,
bool IsCloned) {
634 unsigned DstRCIdx = cast<ConstantSDNode>(Node->
getOperand(0))->getZExtValue();
640 assert((NumOps & 1) == 1 &&
641 "REG_SEQUENCE must have an odd number of operands!");
642 for (
unsigned i = 1;
i != NumOps; ++
i) {
649 unsigned SubIdx = cast<ConstantSDNode>(
Op)->getZExtValue();
654 if (SRC && SRC != RC) {
660 AddOperand(MIB, Op,
i+1, &II, VRBaseMap,
false,
664 MBB->
insert(InsertPos, MIB);
666 bool isNew = VRBaseMap.
insert(std::make_pair(Op, NewVReg)).second;
668 assert(isNew &&
"Node emitted out of order - early");
680 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
681 "Expected inlined-at fields to agree");
686 return BuildMI(*MF, DL, TII->
get(TargetOpcode::DBG_VALUE))
704 if (I==VRBaseMap.
end())
711 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
712 if (CI->getBitWidth() > 64)
715 MIB.
addImm(CI->getSExtValue());
716 }
else if (
const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
732 assert(Offset == 0 &&
"direct value cannot have an offset");
746 EmitMachineNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
751 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
752 Opc == TargetOpcode::INSERT_SUBREG ||
753 Opc == TargetOpcode::SUBREG_TO_REG) {
754 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
759 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
760 EmitCopyToRegClassNode(Node, VRBaseMap);
765 if (Opc == TargetOpcode::REG_SEQUENCE) {
766 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
770 if (Opc == TargetOpcode::IMPLICIT_DEF)
780 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
785 if (Opc == TargetOpcode::PATCHPOINT) {
787 NumDefs = NumResults;
792 unsigned NumImpUses = 0;
793 unsigned NodeOperands =
795 bool HasPhysRegOuts = NumResults > NumDefs && II.
getImplicitDefs()!=
nullptr;
797 unsigned NumMIOperands = NodeOperands + NumResults;
800 "Too few operands for a variadic node!");
805 "#operands for dag node doesn't match .td file!");
814 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
818 bool HasOptPRefs = NumDefs > NumResults;
819 assert((!HasOptPRefs || !HasPhysRegOuts) &&
820 "Unable to cope with optional defs and phys regs defs!");
821 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
822 for (
unsigned i = NumSkip;
i != NodeOperands; ++
i)
823 AddOperand(MIB, Node->
getOperand(
i),
i-NumSkip+NumDefs, &II,
824 VRBaseMap,
false, IsClone, IsCloned);
828 for (
unsigned i = 0; ScratchRegs[
i]; ++
i)
833 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
834 cast<MachineSDNode>(Node)->memoperands_end());
839 MBB->
insert(InsertPos, MIB);
859 if (HasPhysRegOuts) {
860 for (
unsigned i = NumDefs; i < NumResults; ++
i) {
861 unsigned Reg = II.getImplicitDefs()[i - NumDefs];
866 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
886 for (
unsigned i = 0, e =
F->getNumOperands(); i != e; ++
i)
888 unsigned Reg = R->
getReg();
896 if (!UsedRegs.
empty() || II.getImplicitDefs())
897 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
900 if (II.hasPostISelHook())
907 EmitSpecialNode(
SDNode *Node,
bool IsClone,
bool IsCloned,
914 llvm_unreachable(
"This target-independent node should have been selected!");
916 llvm_unreachable(
"EntryToken should have been excluded from the schedule!");
926 SrcReg = getVR(SrcVal, VRBaseMap);
929 if (SrcReg == DestReg)
933 DestReg).addReg(SrcReg);
938 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
942 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
970 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->
getSymbol();
989 cast<ConstantSDNode>(Node->
getOperand(i))->getZExtValue();
999 for (
unsigned j = 0; j != NumVals; ++j, ++
i) {
1010 for (
unsigned j = 0; j != NumVals; ++j, ++
i) {
1022 for (
unsigned j = 0; j != NumVals; ++j, ++
i)
1023 AddOperand(MIB, Node->
getOperand(i), 0,
nullptr, VRBaseMap,
1024 false, IsClone, IsCloned);
1028 unsigned DefGroup = 0;
1030 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1031 unsigned UseIdx = GroupIdx.
back() + 1;
1032 for (
unsigned j = 0; j != NumVals; ++j)
1045 for (
unsigned Reg : ECRegs) {
1048 assert(MO &&
"No def operand for clobbered register?");
1055 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1059 MBB->
insert(InsertPos, MIB);
1070 TII(MF->getSubtarget().getInstrInfo()),
1071 TRI(MF->getSubtarget().getRegisterInfo()),
1072 TLI(MF->getSubtarget().getTargetLowering()),
MBB(mbb),
1073 InsertPos(insertpos) {}
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void push_back(const T &Elt)
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getNumImplicitUses() const
Return the number of implicit uses this instruction has.
const DebugLoc & getDebugLoc() const
InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos)
InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the g...
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool hasOneUse() const
Return true if there is exactly one use of this node.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getNumOperands() const
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
unsigned getPrefTypeAlignment(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
Describe properties that are true of each instruction in the target description file.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Completely target-dependent object reference.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getNumOperands() const
Return the number of values used by this operation.
unsigned getNumOperands() const
const SDValue & getOperand(unsigned Num) const
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
EntryToken - This is the marker used to indicate the start of a region.
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
unsigned getResNo() const
get the index which selects a specific result in the SDNode
const unsigned MinRCSize
MinRCSize - Smallest register class we allow when constraining virtual registers. ...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
CopyToReg - This node has three operands: a chain, a register number to set to this value...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getMachineOpcode() const
MDNode * getExpression() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void setIsEarlyClobber(bool Val=true)
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
DbgValueKind getKind() const
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag...
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
virtual const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getKillRegState(bool B)
unsigned getDebugRegState(bool B)
This corresponds to the llvm.lifetime.
unsigned getDefRegState(bool B)
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool erase(const KeyT &Val)
unsigned const MachineRegisterInfo * MRI
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
bool isOptionalDef() const
Set if this operand is a optional def.
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
ConstantFP - Floating Point Values [float, double].
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
const MachineInstrBuilder & addTargetIndex(unsigned Idx, int64_t Offset=0, unsigned char TargetFlags=0) const
unsigned getFrameIx() const
static unsigned getKind(unsigned Flags)
Value * getOperand(unsigned i) const
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
This is the shared class of boolean and integer constants.
void dump() const
Dump this node, for debugging.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned char TargetFlags=0) const
MachineOperand class - Representation of each machine instruction operand.
SDNode * getSDNode() const
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
SDNode * getGluedUser() const
If this node has a glue value with a user, return the user (there is at most one).
bool isMachineOpcode() const
Represents one node in the SelectionDAG.
const MachineInstrBuilder & addFrameIndex(int Idx) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
iterator_range< use_iterator > uses()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
static unsigned countOperands(SDNode *Node, unsigned NumExpUses, unsigned &NumImpUses)
countOperands - The inputs to target nodes have any actual inputs first, followed by an optional chai...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
unsigned getImplRegState(bool B)
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
iterator find(const KeyT &Val)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
DebugLoc getDebugLoc() const
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
EVT getValueType() const
Return the ValueType of the referenced return value.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const DebugLoc & getDebugLoc() const
Return the source location info.
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const Value * getConst() const
MachineInstr * EmitDbgValue(SDDbgValue *SD, DenseMap< SDValue, unsigned > &VRBaseMap)
EmitDbgValue - Generate machine instruction for a dbg_value node.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
uint64_t getOffset() const
LLVM Value Representation.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
static const Function * getParent(const Value *V)
unsigned getResNo() const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
MDNode * getVariable() const
const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
SDDbgValue - Holds the information from a dbg_value node through SDISel.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
This file describes how to lower LLVM code to machine code.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
uint64_t getZExtValue() const
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.