LLVM  4.0.0
HexagonVLIWPacketizer.h
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1 #ifndef HEXAGONVLIWPACKETIZER_H
2 #define HEXAGONVLIWPACKETIZER_H
3 
8 
9 namespace llvm {
11  // Vector of instructions assigned to the packet that has just been created.
12  std::vector<MachineInstr*> OldPacketMIs;
13 
14  // Has the instruction been promoted to a dot-new instruction.
15  bool PromotedToDotNew;
16 
17  // Has the instruction been glued to allocframe.
18  bool GlueAllocframeStore;
19 
20  // Has the feeder instruction been glued to new value jump.
21  bool GlueToNewValueJump;
22 
23  // Check if there is a dependence between some instruction already in this
24  // packet and this instruction.
25  bool Dependence;
26 
27  // Only check for dependence if there are resources available to
28  // schedule this instruction.
29  bool FoundSequentialDependence;
30 
31  // Track MIs with ignored dependence.
32  std::vector<MachineInstr*> IgnoreDepMIs;
33 
34 protected:
35  /// \brief A handle to the branch probability pass.
38 
39 private:
40  const HexagonInstrInfo *HII;
41  const HexagonRegisterInfo *HRI;
42 
43 public:
44  // Ctor.
48 
49  // initPacketizerState - initialize some internal flags.
50  void initPacketizerState() override;
51 
52  // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
54  const MachineBasicBlock *MBB) override;
55 
56  // isSoloInstruction - return true if instruction MI can not be packetized
57  // with any other instruction, which means that MI itself is a packet.
58  bool isSoloInstruction(const MachineInstr &MI) override;
59 
60  // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
61  // together.
62  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
63 
64  // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
65  // and SUJ.
66  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
67 
71  bool shouldAddToPacket(const MachineInstr &MI) override;
72 
74 
75 protected:
76  bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
77  unsigned DepReg);
80  const TargetRegisterClass *RC);
81  bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
82  unsigned DepReg, MachineBasicBlock::iterator &MII,
83  const TargetRegisterClass *RC);
84  void cleanUpDotCur();
85 
88  const TargetRegisterClass *RC);
89  bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
90  unsigned DepReg, MachineBasicBlock::iterator &MII,
91  const TargetRegisterClass *RC);
92  bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
93  unsigned DepReg, MachineBasicBlock::iterator &MII);
95  const MachineInstr &PacketMI, unsigned DepReg);
100  bool restrictingDepExistInPacket(MachineInstr&, unsigned);
101  bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
103  bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
104  inline bool isPromotedToDotNew() const {
105  return PromotedToDotNew;
106  }
107  bool tryAllocateResourcesForConstExt(bool Reserve);
110  bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
111  bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
112  bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J);
113  bool producesStall(const MachineInstr &MI);
114 };
115 } // namespace llvm
116 #endif // HEXAGONVLIWPACKETIZER_H
117 
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
const MachineLoopInfo * MLI
bool demoteToDotOld(MachineInstr &MI)
bool isCurifiable(MachineInstr &MI)
Kind
Kind - These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:48
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
bool shouldAddToPacket(const MachineInstr &MI) override
MachineFunction & MF
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
const MachineBranchProbabilityInfo * MBPI
A handle to the branch probability pass.
MachineBasicBlock * MBB
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, const MachineBranchProbabilityInfo *MBPI)
bool isSoloInstruction(const MachineInstr &MI) override
bool tryAllocateResourcesForConstExt(bool Reserve)
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
#define I(x, y, z)
Definition: MD5.cpp:54
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
bool useCallersSP(MachineInstr &MI)
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
void useCalleesSP(MachineInstr &MI)
IRTranslator LLVM IR MI
void unpacketizeSoloInstrs(MachineFunction &MF)
Dependence - This class represents a dependence between two memory memory references in a function...
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
bool producesStall(const MachineInstr &MI)
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:244
bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J)