33 AArch64ELFObjectWriter(uint8_t OSABI,
bool IsLittleEndian,
bool IsILP32);
35 ~AArch64ELFObjectWriter()
override =
default;
39 const MCFixup &Fixup,
bool IsPCRel)
const override;
45 AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI,
52 #define R_CLS(rtype) \
53 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
54 #define BAD_ILP32_MOV(lp64rtype) "ILP32 absolute MOV relocation not "\
55 "supported (LP64 eqv: " #lp64rtype ")"
72 return ELF::R_AARCH64_NONE;
75 return ELF::R_AARCH64_NONE;
78 return ELF::R_AARCH64_NONE;
81 return ELF::R_AARCH64_NONE;
84 return ELF::R_AARCH64_NONE;
87 return ELF::R_AARCH64_NONE;
90 return ELF::R_AARCH64_NONE;
93 return ELF::R_AARCH64_NONE;
96 return ELF::R_AARCH64_NONE;
99 return ELF::R_AARCH64_NONE;
100 default:
return false;
108 bool IsPCRel)
const {
116 "Should only be expression-level modifiers here");
120 "Should only be expression-level modifiers here");
123 switch ((
unsigned)Fixup.
getKind()) {
126 return ELF::R_AARCH64_NONE;
128 return R_CLS(PREL16);
130 return R_CLS(PREL32);
134 "relocation not supported (LP64 eqv: PREL64)");
135 return ELF::R_AARCH64_NONE;
137 return ELF::R_AARCH64_PREL64;
140 return R_CLS(ADR_PREL_LO21);
143 return R_CLS(ADR_PREL_PG_HI21);
145 return R_CLS(ADR_GOT_PAGE);
147 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
149 return R_CLS(TLSDESC_ADR_PAGE21);
151 "invalid symbol kind for ADRP relocation");
152 return ELF::R_AARCH64_NONE;
154 return R_CLS(JUMP26);
156 return R_CLS(CALL26);
159 return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
160 return R_CLS(LD_PREL_LO19);
162 return R_CLS(TSTBR14);
164 return R_CLS(CONDBR19);
167 return ELF::R_AARCH64_NONE;
171 return ELF::R_AARCH64_NONE;
172 switch ((
unsigned)Fixup.
getKind()) {
175 return ELF::R_AARCH64_NONE;
183 return ELF::R_AARCH64_NONE;
185 return ELF::R_AARCH64_ABS64;
188 return R_CLS(TLSLD_ADD_DTPREL_HI12);
190 return R_CLS(TLSLE_ADD_TPREL_HI12);
192 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
194 return R_CLS(TLSLD_ADD_DTPREL_LO12);
196 return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
198 return R_CLS(TLSLE_ADD_TPREL_LO12);
200 return R_CLS(TLSDESC_ADD_LO12_NC);
202 return R_CLS(ADD_ABS_LO12_NC);
205 "invalid fixup for add (uimm12) instruction");
206 return ELF::R_AARCH64_NONE;
209 return R_CLS(LDST8_ABS_LO12_NC);
211 return R_CLS(TLSLD_LDST8_DTPREL_LO12);
213 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
215 return R_CLS(TLSLE_LDST8_TPREL_LO12);
217 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
220 "invalid fixup for 8-bit load/store instruction");
221 return ELF::R_AARCH64_NONE;
224 return R_CLS(LDST16_ABS_LO12_NC);
226 return R_CLS(TLSLD_LDST16_DTPREL_LO12);
228 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
230 return R_CLS(TLSLE_LDST16_TPREL_LO12);
232 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
235 "invalid fixup for 16-bit load/store instruction");
236 return ELF::R_AARCH64_NONE;
239 return R_CLS(LDST32_ABS_LO12_NC);
241 return R_CLS(TLSLD_LDST32_DTPREL_LO12);
243 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
245 return R_CLS(TLSLE_LDST32_TPREL_LO12);
247 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
250 "invalid fixup for 32-bit load/store instruction");
251 return ELF::R_AARCH64_NONE;
254 return R_CLS(LDST64_ABS_LO12_NC);
256 return R_CLS(LD64_GOT_LO12_NC);
258 return R_CLS(TLSLD_LDST64_DTPREL_LO12);
260 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
262 return R_CLS(TLSLE_LDST64_TPREL_LO12);
264 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
266 return IsILP32 ? ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC
267 : ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
269 return IsILP32 ? ELF::R_AARCH64_P32_TLSDESC_LD32_LO12_NC
270 : ELF::R_AARCH64_TLSDESC_LD64_LO12_NC;
273 "invalid fixup for 64-bit load/store instruction");
274 return ELF::R_AARCH64_NONE;
277 return R_CLS(LDST128_ABS_LO12_NC);
280 "invalid fixup for 128-bit load/store instruction");
281 return ELF::R_AARCH64_NONE;
285 return ELF::R_AARCH64_MOVW_UABS_G3;
287 return ELF::R_AARCH64_MOVW_UABS_G2;
289 return ELF::R_AARCH64_MOVW_SABS_G2;
291 return ELF::R_AARCH64_MOVW_UABS_G2_NC;
293 return R_CLS(MOVW_UABS_G1);
295 return ELF::R_AARCH64_MOVW_SABS_G1;
297 return ELF::R_AARCH64_MOVW_UABS_G1_NC;
299 return R_CLS(MOVW_UABS_G0);
301 return R_CLS(MOVW_SABS_G0);
303 return R_CLS(MOVW_UABS_G0_NC);
305 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
307 return R_CLS(TLSLD_MOVW_DTPREL_G1);
309 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
311 return R_CLS(TLSLD_MOVW_DTPREL_G0);
313 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
315 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
317 return R_CLS(TLSLE_MOVW_TPREL_G1);
319 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
321 return R_CLS(TLSLE_MOVW_TPREL_G0);
323 return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
325 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
327 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
329 "invalid fixup for movz/movk instruction");
330 return ELF::R_AARCH64_NONE;
332 return R_CLS(TLSDESC_CALL);
335 return ELF::R_AARCH64_NONE;
347 new AArch64ELFObjectWriter(OSABI, IsLittleEndian, IsILP32);
This represents an "assembler immediate".
#define BAD_ILP32_MOV(lp64rtype)
Defines the object file and target independent interfaces used by the assembler backend to write nati...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
static unsigned getRelocType(const MCValue &Target, const MCFixupKind FixupKind, const bool IsPCRel)
Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
Context object for machine code objects.
void reportError(SMLoc L, const Twine &Msg)
static bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::VariantKind RefKind, MCContext &Ctx)
MCFixupKind getKind() const
const MCSymbolRefExpr * getSymB() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCObjectWriter * createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool IsILP32)
const MCSymbolRefExpr * getSymA() const
uint32_t getRefKind() const
Target - Wrapper for Target specific information.
MCObjectWriter * createELFObjectWriter(MCELFObjectTargetWriter *MOTW, raw_pwrite_stream &OS, bool IsLittleEndian)
Construct a new ELF writer instance.
static bool isNotChecked(VariantKind Kind)
An abstract base class for streams implementations that also support a pwrite operation.
static VariantKind getSymbolLoc(VariantKind Kind)
VariantKind getKind() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())