|
| enum | Type {
TypePSEUDO = 0,
TypeALU32 = 1,
TypeCR = 2,
TypeJR = 3,
TypeJ = 4,
TypeLD = 5,
TypeST = 6,
TypeSYSTEM = 7,
TypeXTYPE = 8,
TypeV4LDST = 9,
TypeNV = 10,
TypeDUPLEX = 11,
TypeCOMPOUND = 12,
TypeCVI_FIRST = 13,
TypeCVI_VA = TypeCVI_FIRST,
TypeCVI_VA_DV = 14,
TypeCVI_VX = 15,
TypeCVI_VX_DV = 16,
TypeCVI_VP = 17,
TypeCVI_VP_VS = 18,
TypeCVI_VS = 19,
TypeCVI_VINLANESAT = 20,
TypeCVI_VM_LD = 21,
TypeCVI_VM_TMP_LD = 22,
TypeCVI_VM_CUR_LD = 23,
TypeCVI_VM_VP_LDU = 24,
TypeCVI_VM_ST = 25,
TypeCVI_VM_NEW_ST = 26,
TypeCVI_VM_STU = 27,
TypeCVI_HIST = 28,
TypeCVI_LAST = TypeCVI_HIST,
TypePREFIX = 30,
TypeENDLOOP = 31
} |
| |
| enum | SubTarget {
HasV2SubT = 0xf,
HasV2SubTOnly = 0x1,
NoV2SubT = 0x0,
HasV3SubT = 0xe,
HasV3SubTOnly = 0x2,
NoV3SubT = 0x1,
HasV4SubT = 0xc,
NoV4SubT = 0x3,
HasV5SubT = 0x8,
NoV5SubT = 0x7
} |
| |
| enum | AddrMode {
NoAddrMode = 0,
Absolute = 1,
AbsoluteSet = 2,
BaseImmOffset = 3,
BaseLongOffset = 4,
BaseRegOffset = 5,
PostInc = 6
} |
| |
| enum | MemAccessSize {
MemAccessSize::NoMemAccess = 0,
MemAccessSize::ByteAccess = 1,
MemAccessSize::HalfWordAccess = 2,
MemAccessSize::WordAccess = 3,
MemAccessSize::DoubleWordAccess = 4,
MemAccessSize::Vector64Access = 7,
MemAccessSize::Vector128Access = 8
} |
| |
| enum | {
TypePos = 0,
TypeMask = 0x1f,
SoloPos = 5,
SoloMask = 0x1,
SoloAXPos = 6,
SoloAXMask = 0x1,
SoloAin1Pos = 7,
SoloAin1Mask = 0x1,
PredicatedPos = 8,
PredicatedMask = 0x1,
PredicatedFalsePos = 9,
PredicatedFalseMask = 0x1,
PredicatedNewPos = 10,
PredicatedNewMask = 0x1,
PredicateLatePos = 11,
PredicateLateMask = 0x1,
NewValuePos = 12,
NewValueMask = 0x1,
hasNewValuePos = 13,
hasNewValueMask = 0x1,
NewValueOpPos = 14,
NewValueOpMask = 0x7,
mayNVStorePos = 17,
mayNVStoreMask = 0x1,
NVStorePos = 18,
NVStoreMask = 0x1,
mayCVLoadPos = 19,
mayCVLoadMask = 0x1,
CVLoadPos = 20,
CVLoadMask = 0x1,
ExtendablePos = 21,
ExtendableMask = 0x1,
ExtendedPos = 22,
ExtendedMask = 0x1,
ExtendableOpPos = 23,
ExtendableOpMask = 0x7,
ExtentSignedPos = 26,
ExtentSignedMask = 0x1,
ExtentBitsPos = 27,
ExtentBitsMask = 0x1f,
ExtentAlignPos = 32,
ExtentAlignMask = 0x3,
validSubTargetPos = 34,
validSubTargetMask = 0xf,
AddrModePos = 40,
AddrModeMask = 0x7,
MemAccessSizePos = 43,
MemAccesSizeMask = 0xf,
TakenPos = 47,
TakenMask = 0x1,
FPPos = 48,
FPMask = 0x1,
hasNewValuePos2 = 50,
hasNewValueMask2 = 0x1,
NewValueOpPos2 = 51,
NewValueOpMask2 = 0x7,
AccumulatorPos = 54,
AccumulatorMask = 0x1,
PrefersSlot3Pos = 55,
PrefersSlot3Mask = 0x1,
CofMax1Pos = 60,
CofMax1Mask = 0x1
} |
| |
| enum | HexagonMOTargetFlagVal {
MO_NO_FLAG,
HMOTF_ConstExtended = 1,
MO_PCREL,
MO_GOT,
MO_LO16,
MO_HI16,
MO_GPREL,
MO_GDGOT,
MO_GDPLT,
MO_IE,
MO_IEGOT,
MO_TPREL
} |
| |
| enum | SubInstructionGroup {
HSIG_None = 0,
HSIG_L1,
HSIG_L2,
HSIG_S1,
HSIG_S2,
HSIG_A,
HSIG_Compound
} |
| |
| enum | CompoundGroup { HCG_None = 0,
HCG_A,
HCG_B,
HCG_C
} |
| |
| enum | InstParseBits {
INST_PARSE_MASK = 0x0000c000,
INST_PARSE_PACKET_END = 0x0000c000,
INST_PARSE_LOOP_END = 0x00008000,
INST_PARSE_NOT_END = 0x00004000,
INST_PARSE_DUPLEX = 0x00000000,
INST_PARSE_EXTENDER = 0x00000000
} |
| |
| enum | InstIClassBits : unsigned {
INST_ICLASS_MASK = 0xf0000000,
INST_ICLASS_EXTENDER = 0x00000000,
INST_ICLASS_J_1 = 0x10000000,
INST_ICLASS_J_2 = 0x20000000,
INST_ICLASS_LD_ST_1 = 0x30000000,
INST_ICLASS_LD_ST_2 = 0x40000000,
INST_ICLASS_J_3 = 0x50000000,
INST_ICLASS_CR = 0x60000000,
INST_ICLASS_ALU32_1 = 0x70000000,
INST_ICLASS_XTYPE_1 = 0x80000000,
INST_ICLASS_LD = 0x90000000,
INST_ICLASS_ST = 0xa0000000,
INST_ICLASS_ALU32_2 = 0xb0000000,
INST_ICLASS_XTYPE_2 = 0xc0000000,
INST_ICLASS_XTYPE_3 = 0xd0000000,
INST_ICLASS_XTYPE_4 = 0xe0000000,
INST_ICLASS_ALU32_3 = 0xf0000000
} |
| |
HexagonII - This namespace holds all of the target specific flags that instruction info tracks.