LLVM  4.0.0
TargetRegisterInfo.cpp
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1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TargetRegisterInfo interface.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/BitVector.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/Format.h"
25 
26 #define DEBUG_TYPE "target-reg-info"
27 
28 using namespace llvm;
29 
32  const char *const *SRINames,
33  const LaneBitmask *SRILaneMasks,
34  LaneBitmask SRICoveringLanes)
35  : InfoDesc(ID), SubRegIndexNames(SRINames),
36  SubRegIndexLaneMasks(SRILaneMasks),
37  RegClassBegin(RCB), RegClassEnd(RCE),
38  CoveringLanes(SRICoveringLanes) {
39 }
40 
42 
44  const {
45  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
46  RegisterSet.set(*AI);
47 }
48 
50  ArrayRef<MCPhysReg> Exceptions) const {
51  // Check that all super registers of reserved regs are reserved as well.
52  BitVector Checked(getNumRegs());
53  for (int Reg = RegisterSet.find_first(); Reg>=0;
54  Reg = RegisterSet.find_next(Reg)) {
55  if (Checked[Reg])
56  continue;
57  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
58  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
59  dbgs() << "Error: Super register " << PrintReg(*SR, this)
60  << " of reserved register " << PrintReg(Reg, this)
61  << " is not reserved.\n";
62  return false;
63  }
64 
65  // We transitively check superregs. So we can remember this for later
66  // to avoid compiletime explosion in deep register hierarchies.
67  Checked.set(*SR);
68  }
69  }
70  return true;
71 }
72 
73 namespace llvm {
74 
76  unsigned SubIdx) {
77  return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
78  if (!Reg)
79  OS << "%noreg";
80  else if (TargetRegisterInfo::isStackSlot(Reg))
81  OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
83  OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
84  else if (TRI && Reg < TRI->getNumRegs())
85  OS << '%' << TRI->getName(Reg);
86  else
87  OS << "%physreg" << Reg;
88  if (SubIdx) {
89  if (TRI)
90  OS << ':' << TRI->getSubRegIndexName(SubIdx);
91  else
92  OS << ":sub(" << SubIdx << ')';
93  }
94  });
95 }
96 
98  return Printable([Unit, TRI](raw_ostream &OS) {
99  // Generic printout when TRI is missing.
100  if (!TRI) {
101  OS << "Unit~" << Unit;
102  return;
103  }
104 
105  // Check for invalid register units.
106  if (Unit >= TRI->getNumRegUnits()) {
107  OS << "BadUnit~" << Unit;
108  return;
109  }
110 
111  // Normal units have at least one root.
112  MCRegUnitRootIterator Roots(Unit, TRI);
113  assert(Roots.isValid() && "Unit has no roots.");
114  OS << TRI->getName(*Roots);
115  for (++Roots; Roots.isValid(); ++Roots)
116  OS << '~' << TRI->getName(*Roots);
117  });
118 }
119 
121  return Printable([Unit, TRI](raw_ostream &OS) {
122  if (TRI && TRI->isVirtualRegister(Unit)) {
123  OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
124  } else {
125  OS << PrintRegUnit(Unit, TRI);
126  }
127  });
128 }
129 
130 } // End of llvm namespace
131 
132 /// getAllocatableClass - Return the maximal subclass of the given register
133 /// class that is alloctable, or NULL.
134 const TargetRegisterClass *
136  if (!RC || RC->isAllocatable())
137  return RC;
138 
139  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
140  ++It) {
141  const TargetRegisterClass *SubRC = getRegClass(It.getID());
142  if (SubRC->isAllocatable())
143  return SubRC;
144  }
145  return nullptr;
146 }
147 
148 /// getMinimalPhysRegClass - Returns the Register Class of a physical
149 /// register of the given type, picking the most sub register class of
150 /// the right type that contains this physreg.
151 const TargetRegisterClass *
153  assert(isPhysicalRegister(reg) && "reg must be a physical register");
154 
155  // Pick the most sub register class of the right type that contains
156  // this physreg.
157  const TargetRegisterClass* BestRC = nullptr;
158  for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
159  const TargetRegisterClass* RC = *I;
160  if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
161  (!BestRC || BestRC->hasSubClass(RC)))
162  BestRC = RC;
163  }
164 
165  assert(BestRC && "Couldn't find the register class");
166  return BestRC;
167 }
168 
169 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
170 /// registers for the specific register class.
172  const TargetRegisterClass *RC, BitVector &R){
173  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
175  for (unsigned i = 0; i != Order.size(); ++i)
176  R.set(Order[i]);
177 }
178 
180  const TargetRegisterClass *RC) const {
181  BitVector Allocatable(getNumRegs());
182  if (RC) {
183  // A register class with no allocatable subclass returns an empty set.
184  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
185  if (SubClass)
186  getAllocatableSetForRC(MF, SubClass, Allocatable);
187  } else {
189  E = regclass_end(); I != E; ++I)
190  if ((*I)->isAllocatable())
191  getAllocatableSetForRC(MF, *I, Allocatable);
192  }
193 
194  // Mask out the reserved registers
195  BitVector Reserved = getReservedRegs(MF);
196  Allocatable &= Reserved.flip();
197 
198  return Allocatable;
199 }
200 
201 static inline
203  const uint32_t *B,
204  const TargetRegisterInfo *TRI,
205  const MVT::SimpleValueType SVT =
207  const MVT VT(SVT);
208  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
209  if (unsigned Common = *A++ & *B++) {
210  const TargetRegisterClass *RC =
211  TRI->getRegClass(I + countTrailingZeros(Common));
212  if (SVT == MVT::SimpleValueType::Any || RC->hasType(VT))
213  return RC;
214  }
215  return nullptr;
216 }
217 
218 const TargetRegisterClass *
220  const TargetRegisterClass *B,
221  const MVT::SimpleValueType SVT) const {
222  // First take care of the trivial cases.
223  if (A == B)
224  return A;
225  if (!A || !B)
226  return nullptr;
227 
228  // Register classes are ordered topologically, so the largest common
229  // sub-class it the common sub-class with the smallest ID.
230  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT);
231 }
232 
233 const TargetRegisterClass *
235  const TargetRegisterClass *B,
236  unsigned Idx) const {
237  assert(A && B && "Missing register class");
238  assert(Idx && "Bad sub-register index");
239 
240  // Find Idx in the list of super-register indices.
241  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
242  if (RCI.getSubReg() == Idx)
243  // The bit mask contains all register classes that are projected into B
244  // by Idx. Find a class that is also a sub-class of A.
245  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
246  return nullptr;
247 }
248 
250 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
251  const TargetRegisterClass *RCB, unsigned SubB,
252  unsigned &PreA, unsigned &PreB) const {
253  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
254 
255  // Search all pairs of sub-register indices that project into RCA and RCB
256  // respectively. This is quadratic, but usually the sets are very small. On
257  // most targets like X86, there will only be a single sub-register index
258  // (e.g., sub_16bit projecting into GR16).
259  //
260  // The worst case is a register class like DPR on ARM.
261  // We have indices dsub_0..dsub_7 projecting into that class.
262  //
263  // It is very common that one register class is a sub-register of the other.
264  // Arrange for RCA to be the larger register so the answer will be found in
265  // the first iteration. This makes the search linear for the most common
266  // case.
267  const TargetRegisterClass *BestRC = nullptr;
268  unsigned *BestPreA = &PreA;
269  unsigned *BestPreB = &PreB;
270  if (RCA->getSize() < RCB->getSize()) {
271  std::swap(RCA, RCB);
272  std::swap(SubA, SubB);
273  std::swap(BestPreA, BestPreB);
274  }
275 
276  // Also terminate the search one we have found a register class as small as
277  // RCA.
278  unsigned MinSize = RCA->getSize();
279 
280  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
281  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
282  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
283  // Check if a common super-register class exists for this index pair.
284  const TargetRegisterClass *RC =
285  firstCommonClass(IA.getMask(), IB.getMask(), this);
286  if (!RC || RC->getSize() < MinSize)
287  continue;
288 
289  // The indexes must compose identically: PreA+SubA == PreB+SubB.
290  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
291  if (FinalA != FinalB)
292  continue;
293 
294  // Is RC a better candidate than BestRC?
295  if (BestRC && RC->getSize() >= BestRC->getSize())
296  continue;
297 
298  // Yes, RC is the smallest super-register seen so far.
299  BestRC = RC;
300  *BestPreA = IA.getSubReg();
301  *BestPreB = IB.getSubReg();
302 
303  // Bail early if we reached MinSize. We won't find a better candidate.
304  if (BestRC->getSize() == MinSize)
305  return BestRC;
306  }
307  }
308  return BestRC;
309 }
310 
311 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
312 /// share the same register file.
314  const TargetRegisterClass *DefRC,
315  unsigned DefSubReg,
316  const TargetRegisterClass *SrcRC,
317  unsigned SrcSubReg) {
318  // Same register class.
319  if (DefRC == SrcRC)
320  return true;
321 
322  // Both operands are sub registers. Check if they share a register class.
323  unsigned SrcIdx, DefIdx;
324  if (SrcSubReg && DefSubReg) {
325  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
326  SrcIdx, DefIdx) != nullptr;
327  }
328 
329  // At most one of the register is a sub register, make it Src to avoid
330  // duplicating the test.
331  if (!SrcSubReg) {
332  std::swap(DefSubReg, SrcSubReg);
333  std::swap(DefRC, SrcRC);
334  }
335 
336  // One of the register is a sub register, check if we can get a superclass.
337  if (SrcSubReg)
338  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
339 
340  // Plain copy.
341  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
342 }
343 
345  unsigned DefSubReg,
346  const TargetRegisterClass *SrcRC,
347  unsigned SrcSubReg) const {
348  // If this source does not incur a cross register bank copy, use it.
349  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
350 }
351 
352 // Compute target-independent register allocator hints to help eliminate copies.
353 void
355  ArrayRef<MCPhysReg> Order,
357  const MachineFunction &MF,
358  const VirtRegMap *VRM,
359  const LiveRegMatrix *Matrix) const {
360  const MachineRegisterInfo &MRI = MF.getRegInfo();
361  std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
362 
363  // Hints with HintType != 0 were set by target-dependent code.
364  // Such targets must provide their own implementation of
365  // TRI::getRegAllocationHints to interpret those hint types.
366  assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints");
367 
368  // Target-independent hints are either a physical or a virtual register.
369  unsigned Phys = Hint.second;
370  if (VRM && isVirtualRegister(Phys))
371  Phys = VRM->getPhys(Phys);
372 
373  // Check that Phys is a valid hint in VirtReg's register class.
374  if (!isPhysicalRegister(Phys))
375  return;
376  if (MRI.isReserved(Phys))
377  return;
378  // Check that Phys is in the allocation order. We shouldn't heed hints
379  // from VirtReg's register class if they aren't in the allocation order. The
380  // target probably has a reason for removing the register.
381  if (!is_contained(Order, Phys))
382  return;
383 
384  // All clear, tell the register allocator to prefer this register.
385  Hints.push_back(Phys);
386 }
387 
389  return !MF.getFunction()->hasFnAttribute("no-realign-stack");
390 }
391 
393  const MachineFunction &MF) const {
394  const MachineFrameInfo &MFI = MF.getFrameInfo();
396  const Function *F = MF.getFunction();
397  unsigned StackAlign = TFI->getStackAlignment();
398  bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
399  F->hasFnAttribute(Attribute::StackAlignment));
400  if (MF.getFunction()->hasFnAttribute("stackrealign") || requiresRealignment) {
401  if (canRealignStack(MF))
402  return true;
403  DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n");
404  }
405  return false;
406 }
407 
409  const uint32_t *mask1) const {
410  unsigned N = (getNumRegs()+31) / 32;
411  for (unsigned I = 0; I < N; ++I)
412  if ((mask0[I] & mask1[I]) != mask0[I])
413  return false;
414  return true;
415 }
416 
417 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
418 void
419 TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
420  const TargetRegisterInfo *TRI) {
421  dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n";
422 }
423 #endif
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
Definition: SmallVector.h:211
BitVector & set()
Definition: BitVector.h:219
bool isValid() const
Check if the iterator is at the end of the list.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
Definition: BitVector.h:157
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
size_t i
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const
Mark a register and all its aliases as reserved in the given set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
Definition: BitVector.h:166
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
regclass_iterator regclass_end() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Live Register Matrix
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:191
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
unsigned getNumRegClasses() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Reg
All possible values of the reg field in the ModR/M byte.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
#define F(x, y, z)
Definition: MD5.cpp:51
MCRegUnitRootIterator enumerates the root registers of a register unit.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
MCRegisterClass - Base class of TargetRegisterClass.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any)
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:111
regclass_iterator regclass_begin() const
Register class iterators.
MVT - Machine Value Type.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well...
Extra information, not in MCRegisterDesc, about registers.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
virtual const TargetFrameLowering * getFrameLowering() const
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file...
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Information about stack frame layout on the target.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
BitVector & flip()
Definition: BitVector.h:299
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes)
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
std::vector< uint8_t > Unit
Definition: FuzzerDefs.h:71
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:100
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:98
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
std::set< RegisterRef > RegisterSet
Definition: RDFGraph.h:434
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
const TargetRegisterClass *const * regclass_iterator
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:783
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.