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LLVM
4.0.0
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#include <SIMachineScheduler.h>
Public Member Functions | |
| SIScheduleDAGMI (MachineSchedContext *C) | |
| ~SIScheduleDAGMI () override | |
| void | schedule () override |
| Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions. More... | |
| void | initRPTracker (RegPressureTracker &RPTracker) |
| MachineBasicBlock * | getBB () |
| MachineBasicBlock::iterator | getCurrentTop () |
| MachineBasicBlock::iterator | getCurrentBottom () |
| LiveIntervals * | getLIS () |
| MachineRegisterInfo * | getMRI () |
| const TargetRegisterInfo * | getTRI () |
| SUnit & | getEntrySU () |
| SUnit & | getExitSU () |
| void | restoreSULinksLeft () |
| template<typename _Iterator > | |
| void | fillVgprSgprCost (_Iterator First, _Iterator End, unsigned &VgprUsage, unsigned &SgprUsage) |
| std::set< unsigned > | getInRegs () |
| unsigned | getVGPRSetID () const |
| unsigned | getSGPRSetID () const |
Public Member Functions inherited from llvm::ScheduleDAGMILive | |
| ScheduleDAGMILive (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S) | |
| ~ScheduleDAGMILive () override | |
| bool | hasVRegLiveness () const override |
| Return true if this DAG supports VReg liveness and RegPressure. More... | |
| bool | isTrackingPressure () const |
| Return true if register pressure tracking is enabled. More... | |
| const IntervalPressure & | getTopPressure () const |
| Get current register pressure for the top scheduled instructions. More... | |
| const RegPressureTracker & | getTopRPTracker () const |
| const IntervalPressure & | getBotPressure () const |
| Get current register pressure for the bottom scheduled instructions. More... | |
| const RegPressureTracker & | getBotRPTracker () const |
| const IntervalPressure & | getRegPressure () const |
| Get register pressure for the entire scheduling region before scheduling. More... | |
| const std::vector < PressureChange > & | getRegionCriticalPSets () const |
| PressureDiff & | getPressureDiff (const SUnit *SU) |
| void | computeDFSResult () |
| Compute a DFSResult after DAG building is complete, and before any queue comparisons. More... | |
| const SchedDFSResult * | getDFSResult () const |
| Return a non-null DFS result if the scheduling strategy initialized it. More... | |
| BitVector & | getScheduledTrees () |
| void | enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override |
| Implement the ScheduleDAGInstrs interface for handling the next scheduling region. More... | |
| unsigned | computeCyclicCriticalPath () |
| Compute the cyclic critical path through the DAG. More... | |
Public Member Functions inherited from llvm::ScheduleDAGMI | |
| ScheduleDAGMI (MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags) | |
| ~ScheduleDAGMI () override | |
| LiveIntervals * | getLIS () const |
| void | addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation) |
| Add a postprocessing step to the DAG builder. More... | |
| bool | canAddEdge (SUnit *SuccSU, SUnit *PredSU) |
| True if an edge can be added from PredSU to SuccSU without creating a cycle. More... | |
| bool | addEdge (SUnit *SuccSU, const SDep &PredDep) |
| Add a DAG edge to the given SU with the given predecessor dependence data. More... | |
| MachineBasicBlock::iterator | top () const |
| MachineBasicBlock::iterator | bottom () const |
| void | moveInstruction (MachineInstr *MI, MachineBasicBlock::iterator InsertPos) |
| Change the position of an instruction within the basic block and update live ranges and region boundary iterators. More... | |
| const SUnit * | getNextClusterPred () const |
| const SUnit * | getNextClusterSucc () const |
| void | viewGraph (const Twine &Name, const Twine &Title) override |
| viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'. More... | |
| void | viewGraph () override |
| Out-of-line implementation with no arguments is handy for gdb. More... | |
Public Member Functions inherited from llvm::ScheduleDAGInstrs | |
| ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false) | |
| ~ScheduleDAGInstrs () override | |
| const TargetSchedModel * | getSchedModel () const |
| Get the machine model for instruction scheduling. More... | |
| const MCSchedClassDesc * | getSchedClass (SUnit *SU) const |
| Resolve and cache a resolved scheduling class for an SUnit. More... | |
| MachineBasicBlock::iterator | begin () const |
| begin - Return an iterator to the top of the current scheduling region. More... | |
| MachineBasicBlock::iterator | end () const |
| end - Return an iterator to the bottom of the current scheduling region. More... | |
| SUnit * | newSUnit (MachineInstr *MI) |
| newSUnit - Creates a new SUnit and return a ptr to it. More... | |
| SUnit * | getSUnit (MachineInstr *MI) const |
| getSUnit - Return an existing SUnit for this MI, or NULL. More... | |
| virtual void | startBlock (MachineBasicBlock *BB) |
| startBlock - Prepare to perform scheduling in the given block. More... | |
| virtual void | finishBlock () |
| finishBlock - Clean up after scheduling in the given block. More... | |
| virtual void | exitRegion () |
| Notify that the scheduler has finished scheduling the current region. More... | |
| void | buildSchedGraph (AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false) |
| buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input. More... | |
| void | addSchedBarrierDeps () |
| addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. More... | |
| virtual void | finalizeSchedule () |
| finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. More... | |
| void | dumpNode (const SUnit *SU) const override |
| std::string | getGraphNodeLabel (const SUnit *SU) const override |
| Return a label for a DAG node that points to an instruction. More... | |
| std::string | getDAGName () const override |
| Return a label for the region of code covered by the DAG. More... | |
| void | fixupKills (MachineBasicBlock *MBB) |
| Fix register kill flags that scheduling has made invalid. More... | |
Public Member Functions inherited from llvm::ScheduleDAG | |
| ScheduleDAG (MachineFunction &mf) | |
| virtual | ~ScheduleDAG () |
| void | clearDAG () |
| clearDAG - clear the DAG state (between regions). More... | |
| const MCInstrDesc * | getInstrDesc (const SUnit *SU) const |
| getInstrDesc - Return the MCInstrDesc of this SUnit. More... | |
| virtual void | addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const |
| addCustomGraphFeatures - Add custom features for a visualization of the ScheduleDAG. More... | |
| unsigned | VerifyScheduledDAG (bool isBottomUp) |
| VerifyScheduledDAG - Verify that all SUnits were scheduled and that their state is consistent. More... | |
Public Attributes | |
| std::vector< unsigned > | IsLowLatencySU |
| std::vector< unsigned > | LowLatencyOffset |
| std::vector< unsigned > | IsHighLatencySU |
| std::vector< int > | TopDownIndex2SU |
| std::vector< int > | BottomUpIndex2SU |
Public Attributes inherited from llvm::ScheduleDAG | |
| const TargetMachine & | TM |
| const TargetInstrInfo * | TII |
| const TargetRegisterInfo * | TRI |
| MachineFunction & | MF |
| MachineRegisterInfo & | MRI |
| std::vector< SUnit > | SUnits |
| SUnit | EntrySU |
| SUnit | ExitSU |
| bool | StressSched |
Additional Inherited Members | |
Public Types inherited from llvm::ScheduleDAGInstrs | |
| typedef std::list< SUnit * > | SUList |
| A list of SUnits, used in Value2SUsMap, during DAG construction. More... | |
Protected Types inherited from llvm::ScheduleDAGInstrs | |
| typedef std::vector< std::pair < MachineInstr *, MachineInstr * > > | DbgValueVector |
| DbgValues - Remember instruction that precedes DBG_VALUE. More... | |
Protected Member Functions inherited from llvm::ScheduleDAGMILive | |
| void | buildDAGWithRegPressure () |
| Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled. More... | |
| void | initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots) |
| Release ExitSU predecessors and setup scheduler queues. More... | |
| void | scheduleMI (SUnit *SU, bool IsTopNode) |
| Move an instruction and update register pressure. More... | |
| void | initRegPressure () |
| void | updatePressureDiffs (ArrayRef< RegisterMaskPair > LiveUses) |
| Update the PressureDiff array for liveness after scheduling this instruction. More... | |
| void | updateScheduledPressure (const SUnit *SU, const std::vector< unsigned > &NewMaxPressure) |
| void | collectVRegUses (SUnit &SU) |
Protected Member Functions inherited from llvm::ScheduleDAGMI | |
| void | postprocessDAG () |
| Apply each ScheduleDAGMutation step in order. More... | |
| void | initQueues (ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots) |
| Release ExitSU predecessors and setup scheduler queues. More... | |
| void | updateQueues (SUnit *SU, bool IsTopNode) |
| Update scheduler DAG and queues after scheduling an instruction. More... | |
| void | placeDebugValues () |
| Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues. More... | |
| void | dumpSchedule () const |
| dump the scheduled Sequence. More... | |
| bool | checkSchedLimit () |
| void | findRootsAndBiasEdges (SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots) |
| void | releaseSucc (SUnit *SU, SDep *SuccEdge) |
| ReleaseSucc - Decrement the NumPredsLeft count of a successor. More... | |
| void | releaseSuccessors (SUnit *SU) |
| releaseSuccessors - Call releaseSucc on each of SU's successors. More... | |
| void | releasePred (SUnit *SU, SDep *PredEdge) |
| ReleasePred - Decrement the NumSuccsLeft count of a predecessor. More... | |
| void | releasePredecessors (SUnit *SU) |
| releasePredecessors - Call releasePred on each of SU's predecessors. More... | |
Protected Member Functions inherited from llvm::ScheduleDAGInstrs | |
| void | reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N) |
| Remove in FIFO order some SUs from huge maps. More... | |
| void | addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0) |
| Add a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the dependency. More... | |
| void | addChainDependencies (SUnit *SU, SUList &sus, unsigned Latency) |
| Add dependencies as needed from all SUs in list to SU. More... | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap) |
| Add dependencies as needed from all SUs in map, to SU. More... | |
| void | addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) |
| Add dependencies as needed to SU, from all SUs mapped to V. More... | |
| void | addBarrierChain (Value2SUsMap &map) |
| Add barrier chain edges from all SUs in map, and then clear the map. More... | |
| void | insertBarrierChain (Value2SUsMap &map) |
| Insert a barrier chain in a huge region, far below current SU. More... | |
| void | initSUnits () |
| Create an SUnit for each real instruction, numbered in top-down topological order. More... | |
| void | addPhysRegDataDeps (SUnit *SU, unsigned OperIdx) |
| MO is an operand of SU's instruction that defines a physical register. More... | |
| void | addPhysRegDeps (SUnit *SU, unsigned OperIdx) |
| addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx. More... | |
| void | addVRegDefDeps (SUnit *SU, unsigned OperIdx) |
| addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx. More... | |
| void | addVRegUseDeps (SUnit *SU, unsigned OperIdx) |
| addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. More... | |
| void | startBlockForKills (MachineBasicBlock *BB) |
| PostRA helper for rewriting kill flags. More... | |
| bool | toggleKillFlag (MachineInstr *MI, MachineOperand &MO) |
| Toggle a register operand kill flag. More... | |
| LaneBitmask | getLaneMaskForMO (const MachineOperand &MO) const |
| Returns a mask for which lanes get read/written by the given (register) machine operand. More... | |
Protected Attributes inherited from llvm::ScheduleDAGMILive | |
| RegisterClassInfo * | RegClassInfo |
| SchedDFSResult * | DFSResult |
| Information about DAG subtrees. More... | |
| BitVector | ScheduledTrees |
| MachineBasicBlock::iterator | LiveRegionEnd |
| VReg2SUnitMultiMap | VRegUses |
| Maps vregs to the SUnits of their uses in the current scheduling region. More... | |
| PressureDiffs | SUPressureDiffs |
| bool | ShouldTrackPressure |
| Register pressure in this region computed by initRegPressure. More... | |
| bool | ShouldTrackLaneMasks |
| IntervalPressure | RegPressure |
| RegPressureTracker | RPTracker |
| std::vector< PressureChange > | RegionCriticalPSets |
| List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing set ID order. More... | |
| IntervalPressure | TopPressure |
| The top of the unscheduled zone. More... | |
| RegPressureTracker | TopRPTracker |
| IntervalPressure | BotPressure |
| The bottom of the unscheduled zone. More... | |
| RegPressureTracker | BotRPTracker |
| bool | DisconnectedComponentsRenamed |
| True if disconnected subregister components are already renamed. More... | |
Protected Attributes inherited from llvm::ScheduleDAGMI | |
| AliasAnalysis * | AA |
| LiveIntervals * | LIS |
| std::unique_ptr < MachineSchedStrategy > | SchedImpl |
| ScheduleDAGTopologicalSort | Topo |
| Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries. More... | |
| std::vector< std::unique_ptr < ScheduleDAGMutation > > | Mutations |
| Ordered list of DAG postprocessing steps. More... | |
| MachineBasicBlock::iterator | CurrentTop |
| The top of the unscheduled zone. More... | |
| MachineBasicBlock::iterator | CurrentBottom |
| The bottom of the unscheduled zone. More... | |
| const SUnit * | NextClusterPred |
| Record the next node in a scheduled cluster. More... | |
| const SUnit * | NextClusterSucc |
| unsigned | NumInstrsScheduled |
| The number of instructions scheduled so far. More... | |
Protected Attributes inherited from llvm::ScheduleDAGInstrs | |
| const MachineLoopInfo * | MLI |
| const MachineFrameInfo & | MFI |
| TargetSchedModel | SchedModel |
| TargetSchedModel provides an interface to the machine model. More... | |
| bool | RemoveKillFlags |
| True if the DAG builder should remove kill flags (in preparation for rescheduling). More... | |
| bool | CanHandleTerminators |
| The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. More... | |
| bool | TrackLaneMasks |
| Whether lane masks should get tracked. More... | |
| MachineBasicBlock * | BB |
| State specific to the current scheduling region. More... | |
| MachineBasicBlock::iterator | RegionBegin |
| The beginning of the range to be scheduled. More... | |
| MachineBasicBlock::iterator | RegionEnd |
| The end of the range to be scheduled. More... | |
| unsigned | NumRegionInstrs |
| Instructions in this region (distance(RegionBegin, RegionEnd)). More... | |
| DenseMap< MachineInstr *, SUnit * > | MISUnitMap |
| After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit. More... | |
| Reg2SUnitsMap | Defs |
| State internal to DAG building. More... | |
| Reg2SUnitsMap | Uses |
| VReg2SUnitMultiMap | CurrentVRegDefs |
| Tracks the last instruction(s) in this region defining each virtual register. More... | |
| VReg2SUnitOperIdxMultiMap | CurrentVRegUses |
| Tracks the last instructions in this region using each virtual register. More... | |
| AliasAnalysis * | AAForDep |
| SUnit * | BarrierChain |
| Remember a generic side-effecting instruction as we proceed. More... | |
| UndefValue * | UnknownValue |
| For an unanalyzable memory access, this Value is used in maps. More... | |
| DbgValueVector | DbgValues |
| MachineInstr * | FirstDbgValue |
| BitVector | LiveRegs |
| Set of live physical registers for updating kill flags. More... | |
Definition at line 422 of file SIMachineScheduler.h.
| SIScheduleDAGMI::SIScheduleDAGMI | ( | MachineSchedContext * | C | ) |
Definition at line 1653 of file SIMachineScheduler.cpp.
References llvm::SIRegisterInfo::getSGPRPressureSet(), llvm::SIRegisterInfo::getVGPRPressureSet(), llvm::ScheduleDAG::TII, and llvm::ScheduleDAG::TRI.
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overridedefault |
| void SIScheduleDAGMI::fillVgprSgprCost | ( | _Iterator | First, |
| _Iterator | End, | ||
| unsigned & | VgprUsage, | ||
| unsigned & | SgprUsage | ||
| ) |
Definition at line 1757 of file SIMachineScheduler.cpp.
References llvm::WebAssembly::End, llvm::MachineRegisterInfo::getPressureSets(), llvm::PSetIterator::getWeight(), llvm::PSetIterator::isValid(), and llvm::TargetRegisterInfo::isVirtualRegister().
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Definition at line 448 of file SIMachineScheduler.h.
References llvm::ScheduleDAGInstrs::BB.
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Definition at line 450 of file SIMachineScheduler.h.
References llvm::ScheduleDAGMI::CurrentBottom.
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Definition at line 449 of file SIMachineScheduler.h.
References llvm::ScheduleDAGMI::CurrentTop.
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Definition at line 454 of file SIMachineScheduler.h.
References llvm::ScheduleDAG::EntrySU.
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Definition at line 455 of file SIMachineScheduler.h.
References llvm::ScheduleDAG::ExitSU.
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Definition at line 464 of file SIMachineScheduler.h.
References llvm::RegPressureTracker::getPressure(), llvm::RegisterPressure::LiveInRegs, and llvm::ScheduleDAGMILive::RPTracker.
Referenced by llvm::SIScheduleBlockScheduler::SIScheduleBlockScheduler().
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Definition at line 451 of file SIMachineScheduler.h.
References llvm::ScheduleDAGMI::LIS.
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Definition at line 452 of file SIMachineScheduler.h.
References llvm::ScheduleDAG::MRI.
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Definition at line 473 of file SIMachineScheduler.h.
Referenced by llvm::SIScheduleBlock::printDebug().
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Definition at line 453 of file SIMachineScheduler.h.
References llvm::ScheduleDAG::TRI.
Referenced by llvm::SIScheduleBlock::printDebug().
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Definition at line 472 of file SIMachineScheduler.h.
Referenced by llvm::SIScheduleBlock::printDebug().
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Definition at line 444 of file SIMachineScheduler.h.
References llvm::ScheduleDAGInstrs::BB, llvm::RegPressureTracker::init(), llvm::ScheduleDAGMI::LIS, llvm::ScheduleDAG::MF, llvm::ScheduleDAGMILive::RegClassInfo, and llvm::ScheduleDAGInstrs::RegionBegin.
| void SIScheduleDAGMI::restoreSULinksLeft | ( | ) |
Definition at line 1745 of file SIMachineScheduler.cpp.
References i.
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overridevirtual |
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
schedule - Called back from MachineScheduler::runOnMachineFunction after setting up the current scheduling region.
[RegionBegin, RegionEnd) only includes instructions that have DAG nodes, not scheduling boundaries.
This is a skeletal driver, with all the functionality pushed into helpers, so that it can be easily extended by experimental schedulers. Generally, implementing MachineSchedStrategy should be sufficient to implement a new scheduling algorithm. However, if a scheduler further subclasses ScheduleDAGMILive then it will want to override this virtual method in order to update any specialized state.
Reimplemented from llvm::ScheduleDAGMILive.
Definition at line 1776 of file SIMachineScheduler.cpp.
References assert(), llvm::ScheduleDAGInstrs::begin(), llvm::BlockLatencyRegUsage, llvm::BlockRegUsage, llvm::BlockRegUsageLatency, llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), llvm::ScheduleDAGMI::CurrentBottom, llvm::ScheduleDAGMI::CurrentTop, llvm::dbgs(), DEBUG, llvm::SUnit::dumpAll(), llvm::ScheduleDAGMI::dumpSchedule(), E, llvm::ScheduleDAGMI::findRootsAndBiasEdges(), llvm::SUnit::getInstr(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::RegPressureTracker::getPos(), I, i, llvm::ScheduleDAGMILive::initQueues(), llvm::SIInstrInfo::isHighLatencyInstruction(), IsHighLatencySU, llvm::SIInstrInfo::isLowLatencyInstruction(), IsLowLatencySU, llvm::LatenciesAlone, llvm::LatenciesAlonePlusConsecutive, llvm::LatenciesGrouped, LowLatencyOffset, llvm::SIScheduleBlockResult::MaxVGPRUsage, llvm::SUnit::NodeNum, llvm::ScheduleDAGMI::placeDebugValues(), llvm::ScheduleDAGInstrs::RegionBegin, llvm::ScheduleDAGMI::SchedImpl, llvm::ScheduleDAGMILive::scheduleMI(), Scheduler, llvm::SIScheduler::scheduleVariant(), llvm::RegPressureTracker::setPos(), llvm::ScheduleDAG::SUnits, llvm::SIScheduleBlockResult::SUs, llvm::ScheduleDAGMILive::TopRPTracker, and llvm::ScheduleDAG::TRI.
| std::vector<int> llvm::SIScheduleDAGMI::BottomUpIndex2SU |
Definition at line 488 of file SIMachineScheduler.h.
| std::vector<unsigned> llvm::SIScheduleDAGMI::IsHighLatencySU |
Definition at line 484 of file SIMachineScheduler.h.
Referenced by llvm::SIScheduleBlock::finalizeUnits(), and schedule().
| std::vector<unsigned> llvm::SIScheduleDAGMI::IsLowLatencySU |
Definition at line 482 of file SIMachineScheduler.h.
Referenced by schedule().
| std::vector<unsigned> llvm::SIScheduleDAGMI::LowLatencyOffset |
Definition at line 483 of file SIMachineScheduler.h.
Referenced by schedule().
| std::vector<int> llvm::SIScheduleDAGMI::TopDownIndex2SU |
Definition at line 487 of file SIMachineScheduler.h.
1.8.6