27 #define DEBUG_TYPE "legalize-types"
49 bool DAGTypeLegalizer::SoftenFloatResult(
SDNode *
N,
unsigned ResNo) {
50 DEBUG(
dbgs() <<
"Soften float result " << ResNo <<
": "; N->
dump(&DAG);
57 dbgs() <<
"SoftenFloatResult #" << ResNo <<
": ";
66 "Unsupported SoftenFloatRes opcode!");
71 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N, ResNo);
break;
75 R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N);
break;
76 case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo);
break;
79 case ISD::FADD: R = SoftenFloatRes_FADD(N);
break;
80 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N);
break;
81 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N, ResNo);
break;
82 case ISD::FCOS: R = SoftenFloatRes_FCOS(N);
break;
83 case ISD::FDIV: R = SoftenFloatRes_FDIV(N);
break;
84 case ISD::FEXP: R = SoftenFloatRes_FEXP(N);
break;
85 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N);
break;
86 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N);
break;
87 case ISD::FLOG: R = SoftenFloatRes_FLOG(N);
break;
88 case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N);
break;
89 case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N);
break;
90 case ISD::FMA: R = SoftenFloatRes_FMA(N);
break;
91 case ISD::FMUL: R = SoftenFloatRes_FMUL(N);
break;
93 case ISD::FNEG: R = SoftenFloatRes_FNEG(N, ResNo);
break;
97 case ISD::FPOW: R = SoftenFloatRes_FPOW(N);
break;
98 case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N);
break;
99 case ISD::FREM: R = SoftenFloatRes_FREM(N);
break;
100 case ISD::FRINT: R = SoftenFloatRes_FRINT(N);
break;
101 case ISD::FROUND: R = SoftenFloatRes_FROUND(N);
break;
102 case ISD::FSIN: R = SoftenFloatRes_FSIN(N);
break;
103 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N);
break;
104 case ISD::FSUB: R = SoftenFloatRes_FSUB(N);
break;
105 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N);
break;
106 case ISD::LOAD: R = SoftenFloatRes_LOAD(N, ResNo);
break;
107 case ISD::SELECT: R = SoftenFloatRes_SELECT(N, ResNo);
break;
108 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N, ResNo);
break;
111 case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N);
break;
112 case ISD::VAARG: R = SoftenFloatRes_VAARG(N);
break;
117 SetSoftenedFloat(
SDValue(N, ResNo), R);
118 ReplaceSoftenFloatResult(N, ResNo, R);
123 return R.getNode() && R.getNode() !=
N;
126 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(
SDNode *N,
unsigned ResNo) {
132 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(
SDNode *N,
134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
135 return BitConvertToInteger(Op);
138 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(
SDNode *N) {
147 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(
SDNode *N,
unsigned ResNo) {
163 APInt Val(128, words);
174 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(
SDNode *N) {
181 SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(
SDNode *N,
unsigned ResNo) {
196 SDValue DAGTypeLegalizer::SoftenFloatRes_FMINNUM(
SDNode *N) {
206 NVT, Ops,
false,
SDLoc(N)).first;
209 SDValue DAGTypeLegalizer::SoftenFloatRes_FMAXNUM(
SDNode *N) {
219 NVT, Ops,
false,
SDLoc(N)).first;
232 NVT, Ops,
false,
SDLoc(N)).first;
244 NVT, Op,
false,
SDLoc(N)).first;
247 SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(
SDNode *N,
unsigned ResNo) {
256 EVT RVT = RHS.getValueType();
277 }
else if (SizeDiff < 0) {
307 NVT, Op,
false,
SDLoc(N)).first;
320 NVT, Ops,
false,
SDLoc(N)).first;
332 NVT, Op,
false,
SDLoc(N)).first;
344 NVT, Op,
false,
SDLoc(N)).first;
356 NVT, Op,
false,
SDLoc(N)).first;
368 NVT, Op,
false,
SDLoc(N)).first;
380 NVT, Op,
false,
SDLoc(N)).first;
392 NVT, Op,
false,
SDLoc(N)).first;
406 NVT, Ops,
false,
SDLoc(N)).first;
419 NVT, Ops,
false,
SDLoc(N)).first;
422 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(
SDNode *N) {
431 NVT, Op,
false,
SDLoc(N)).first;
434 SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(
SDNode *N,
unsigned ResNo) {
449 NVT, Ops,
false, dl).first;
452 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(
SDNode *N) {
462 SoftenFloatResult(Op.
getNode(), 0);
466 Op = GetPromotedFloat(Op);
470 return BitConvertToInteger(Op);
476 Op = GetSoftenedFloat(Op);
483 SDValue DAGTypeLegalizer::SoftenFloatRes_FP16_TO_FP(
SDNode *N) {
487 false,
SDLoc(N)).first;
497 SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(
SDNode *N) {
521 NVT, Ops,
false,
SDLoc(N)).first;
526 "Unsupported power type!");
535 NVT, Ops,
false,
SDLoc(N)).first;
548 NVT, Ops,
false,
SDLoc(N)).first;
560 NVT, Op,
false,
SDLoc(N)).first;
572 NVT, Op,
false,
SDLoc(N)).first;
584 NVT, Op,
false,
SDLoc(N)).first;
596 NVT, Op,
false,
SDLoc(N)).first;
609 NVT, Ops,
false,
SDLoc(N)).first;
624 NVT, Op,
false,
SDLoc(N)).first;
627 SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(
SDNode *N,
unsigned ResNo) {
628 bool LegalInHWReg = isLegalInHWReg(N->
getValueType(ResNo));
635 L->getMemOperand()->getFlags() &
639 NewL = DAG.
getLoad(L->getAddressingMode(), L->getExtensionType(), NVT, dl,
640 L->getChain(), L->getBasePtr(), L->getOffset(),
641 L->getPointerInfo(), NVT, L->getAlignment(), MMOFlags,
652 dl, L->getChain(), L->getBasePtr(), L->getOffset(),
653 L->getPointerInfo(), L->getMemoryVT(), L->getAlignment(),
654 MMOFlags, L->getAAInfo());
661 return BitConvertToInteger(ExtendNode);
664 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT(
SDNode *N,
unsigned ResNo) {
673 SDValue DAGTypeLegalizer::SoftenFloatRes_SELECT_CC(
SDNode *N,
unsigned ResNo) {
706 SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(
SDNode *N) {
731 Op, Signed, dl).first;
739 bool DAGTypeLegalizer::SoftenFloatOperand(
SDNode *N,
unsigned OpNo) {
740 DEBUG(
dbgs() <<
"Soften float operand " << OpNo <<
": "; N->
dump(&DAG);
746 if (CanSkipSoftenFloatOperand(N, OpNo))
749 dbgs() <<
"SoftenFloatOperand Op #" << OpNo <<
": ";
754 case ISD::BITCAST: Res = SoftenFloatOp_BITCAST(N);
break;
755 case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N);
break;
762 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N);
break;
764 Res = SoftenFloatOp_STORE(N, OpNo);
768 if (Res.getNode() == N &&
776 if (!Res.getNode())
return false;
780 if (Res.getNode() ==
N)
784 "Invalid operand expansion");
786 ReplaceValueWith(
SDValue(N, 0), Res);
790 bool DAGTypeLegalizer::CanSkipSoftenFloatOperand(
SDNode *N,
unsigned OpNo) {
831 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_EXTEND(
SDNode *N) {
847 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(
SDNode *N) {
868 NewLHS = GetSoftenedFloat(NewLHS);
869 NewRHS = GetSoftenedFloat(NewRHS);
874 if (!NewRHS.getNode()) {
886 SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_XINT(
SDNode *N) {
915 SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(
SDNode *N) {
920 NewLHS = GetSoftenedFloat(NewLHS);
921 NewRHS = GetSoftenedFloat(NewRHS);
926 if (!NewRHS.getNode()) {
943 NewLHS = GetSoftenedFloat(NewLHS);
944 NewRHS = GetSoftenedFloat(NewRHS);
948 if (!NewRHS.getNode()) {
950 "Unexpected setcc expansion!");
960 SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(
SDNode *N,
unsigned OpNo) {
962 assert(OpNo == 1 &&
"Can only soften the stored value!");
972 Val = GetSoftenedFloat(Val);
987 void DAGTypeLegalizer::ExpandFloatResult(
SDNode *N,
unsigned ResNo) {
999 dbgs() <<
"ExpandFloatResult #" << ResNo <<
": ";
1002 llvm_unreachable(
"Do not know how to expand the result of this operator!");
1004 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi);
break;
1005 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi);
break;
1009 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi);
break;
1013 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi);
break;
1016 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi);
break;
1017 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi);
break;
1018 case ISD::FMAXNUM: ExpandFloatRes_FMAXNUM(N, Lo, Hi);
break;
1019 case ISD::FADD: ExpandFloatRes_FADD(N, Lo, Hi);
break;
1020 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi);
break;
1022 case ISD::FCOS: ExpandFloatRes_FCOS(N, Lo, Hi);
break;
1023 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi);
break;
1024 case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi);
break;
1025 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi);
break;
1026 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi);
break;
1027 case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi);
break;
1028 case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi);
break;
1029 case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi);
break;
1030 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi);
break;
1031 case ISD::FMUL: ExpandFloatRes_FMUL(N, Lo, Hi);
break;
1033 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi);
break;
1035 case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi);
break;
1036 case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi);
break;
1037 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi);
break;
1038 case ISD::FROUND: ExpandFloatRes_FROUND(N, Lo, Hi);
break;
1039 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi);
break;
1040 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi);
break;
1041 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi);
break;
1042 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi);
break;
1043 case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi);
break;
1046 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi);
break;
1054 void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(
SDNode *N,
SDValue &Lo,
1058 "Do not know how to expand this float constant!");
1059 APInt C = cast<ConstantFPSDNode>(
N)->getValueAPF().bitcastToAPInt();
1069 void DAGTypeLegalizer::ExpandFloatRes_FABS(
SDNode *N,
SDValue &Lo,
1072 "Logic only correct for ppcf128!");
1083 void DAGTypeLegalizer::ExpandFloatRes_FMINNUM(
SDNode *N,
SDValue &Lo,
1090 GetPairElements(Call, Lo, Hi);
1093 void DAGTypeLegalizer::ExpandFloatRes_FMAXNUM(
SDNode *N,
SDValue &Lo,
1100 GetPairElements(Call, Lo, Hi);
1103 void DAGTypeLegalizer::ExpandFloatRes_FADD(
SDNode *N,
SDValue &Lo,
1110 GetPairElements(Call, Lo, Hi);
1113 void DAGTypeLegalizer::ExpandFloatRes_FCEIL(
SDNode *N,
1120 GetPairElements(Call, Lo, Hi);
1123 void DAGTypeLegalizer::ExpandFloatRes_FCOPYSIGN(
SDNode *N,
1132 GetPairElements(Call, Lo, Hi);
1135 void DAGTypeLegalizer::ExpandFloatRes_FCOS(
SDNode *N,
1142 GetPairElements(Call, Lo, Hi);
1145 void DAGTypeLegalizer::ExpandFloatRes_FDIV(
SDNode *N,
SDValue &Lo,
1156 GetPairElements(Call, Lo, Hi);
1159 void DAGTypeLegalizer::ExpandFloatRes_FEXP(
SDNode *N,
1166 GetPairElements(Call, Lo, Hi);
1169 void DAGTypeLegalizer::ExpandFloatRes_FEXP2(
SDNode *N,
1176 GetPairElements(Call, Lo, Hi);
1179 void DAGTypeLegalizer::ExpandFloatRes_FFLOOR(
SDNode *N,
1186 GetPairElements(Call, Lo, Hi);
1189 void DAGTypeLegalizer::ExpandFloatRes_FLOG(
SDNode *N,
1196 GetPairElements(Call, Lo, Hi);
1199 void DAGTypeLegalizer::ExpandFloatRes_FLOG2(
SDNode *N,
1206 GetPairElements(Call, Lo, Hi);
1209 void DAGTypeLegalizer::ExpandFloatRes_FLOG10(
SDNode *N,
1216 GetPairElements(Call, Lo, Hi);
1219 void DAGTypeLegalizer::ExpandFloatRes_FMA(
SDNode *N,
SDValue &Lo,
1230 GetPairElements(Call, Lo, Hi);
1233 void DAGTypeLegalizer::ExpandFloatRes_FMUL(
SDNode *N,
SDValue &Lo,
1244 GetPairElements(Call, Lo, Hi);
1247 void DAGTypeLegalizer::ExpandFloatRes_FNEARBYINT(
SDNode *N,
1256 GetPairElements(Call, Lo, Hi);
1259 void DAGTypeLegalizer::ExpandFloatRes_FNEG(
SDNode *N,
SDValue &Lo,
1267 void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(
SDNode *N,
SDValue &Lo,
1276 void DAGTypeLegalizer::ExpandFloatRes_FPOW(
SDNode *N,
1283 GetPairElements(Call, Lo, Hi);
1286 void DAGTypeLegalizer::ExpandFloatRes_FPOWI(
SDNode *N,
1293 GetPairElements(Call, Lo, Hi);
1296 void DAGTypeLegalizer::ExpandFloatRes_FREM(
SDNode *N,
1303 GetPairElements(Call, Lo, Hi);
1306 void DAGTypeLegalizer::ExpandFloatRes_FRINT(
SDNode *N,
1313 GetPairElements(Call, Lo, Hi);
1316 void DAGTypeLegalizer::ExpandFloatRes_FROUND(
SDNode *N,
1325 GetPairElements(Call, Lo, Hi);
1328 void DAGTypeLegalizer::ExpandFloatRes_FSIN(
SDNode *N,
1335 GetPairElements(Call, Lo, Hi);
1338 void DAGTypeLegalizer::ExpandFloatRes_FSQRT(
SDNode *N,
1345 GetPairElements(Call, Lo, Hi);
1348 void DAGTypeLegalizer::ExpandFloatRes_FSUB(
SDNode *N,
SDValue &Lo,
1359 GetPairElements(Call, Lo, Hi);
1362 void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(
SDNode *N,
1369 GetPairElements(Call, Lo, Hi);
1372 void DAGTypeLegalizer::ExpandFloatRes_LOAD(
SDNode *N,
SDValue &Lo,
1375 ExpandRes_NormalLoad(N, Lo, Hi);
1397 APInt(NVT.getSizeInBits(), 0)), dl, NVT);
1401 ReplaceValueWith(
SDValue(LD, 1), Chain);
1404 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(
SDNode *N,
SDValue &Lo,
1436 Hi = TLI.
makeLibCall(DAG, LC, VT, Src,
true, dl).first;
1437 GetPairElements(Hi, Lo, Hi);
1448 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
1449 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
1450 static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
1474 GetPairElements(Lo, Lo, Hi);
1486 bool DAGTypeLegalizer::ExpandFloatOperand(
SDNode *N,
unsigned OpNo) {
1497 dbgs() <<
"ExpandFloatOperand Op #" << OpNo <<
": ";
1506 case ISD::BR_CC: Res = ExpandFloatOp_BR_CC(N);
break;
1512 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N);
break;
1513 case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
1518 if (!Res.getNode())
return false;
1522 if (Res.getNode() ==
N)
1526 "Invalid operand expansion");
1528 ReplaceValueWith(
SDValue(N, 0), Res);
1534 void DAGTypeLegalizer::FloatExpandSetCCOperands(
SDValue &NewLHS,
1538 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1539 GetExpandedFloat(NewLHS, LHSLo, LHSHi);
1540 GetExpandedFloat(NewRHS, RHSLo, RHSHi);
1553 LHSLo, RHSLo, CCCode);
1558 LHSHi, RHSHi, CCCode);
1560 NewLHS = DAG.
getNode(
ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
1567 FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
1582 SDValue DAGTypeLegalizer::ExpandFloatOp_FCOPYSIGN(
SDNode *N) {
1584 "Logic only correct for ppcf128!");
1593 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(
SDNode *N) {
1595 "Logic only correct for ppcf128!");
1603 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(
SDNode *N) {
1611 "Logic only correct for ppcf128!");
1624 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(
SDNode *N) {
1632 "Logic only correct for ppcf128!");
1633 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
1659 SDValue DAGTypeLegalizer::ExpandFloatOp_SELECT_CC(
SDNode *N) {
1662 FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
1680 FloatExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
1685 "Unexpected setcc expansion!");
1694 SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(
SDNode *N,
unsigned OpNo) {
1696 return ExpandOp_NormalStore(N, OpNo);
1699 assert(OpNo == 1 &&
"Can only expand the stored value so far");
1733 bool DAGTypeLegalizer::PromoteFloatOperand(
SDNode *N,
unsigned OpNo) {
1745 case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo);
break;
1746 case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo);
break;
1749 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo);
break;
1750 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo);
break;
1751 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo);
break;
1752 case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo);
break;
1756 ReplaceValueWith(
SDValue(N, 0), R);
1760 SDValue DAGTypeLegalizer::PromoteFloatOp_BITCAST(
SDNode *N,
unsigned OpNo) {
1768 EVT PromotedVT = Promoted->getValueType(0);
1777 SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(
SDNode *N,
unsigned OpNo) {
1778 assert (OpNo == 1 &&
"Only Operand 1 must need promotion here");
1786 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT(
SDNode *N,
unsigned OpNo) {
1791 SDValue DAGTypeLegalizer::PromoteFloatOp_FP_EXTEND(
SDNode *N,
unsigned OpNo) {
1806 SDValue DAGTypeLegalizer::PromoteFloatOp_SELECT_CC(
SDNode *N,
unsigned OpNo) {
1817 SDValue DAGTypeLegalizer::PromoteFloatOp_SETCC(
SDNode *N,
unsigned OpNo) {
1830 SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(
SDNode *N,
unsigned OpNo) {
1835 SDValue Promoted = GetPromotedFloat(Val);
1851 void DAGTypeLegalizer::PromoteFloatResult(
SDNode *N,
unsigned ResNo) {
1862 case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N);
break;
1865 R = PromoteFloatRes_EXTRACT_VECTOR_ELT(N);
break;
1884 case ISD::FTRUNC: R = PromoteFloatRes_UnaryOp(N);
break;
1896 case ISD::FSUB: R = PromoteFloatRes_BinOp(N);
break;
1899 case ISD::FMAD: R = PromoteFloatRes_FMAD(N);
break;
1901 case ISD::FPOWI: R = PromoteFloatRes_FPOWI(N);
break;
1904 case ISD::LOAD: R = PromoteFloatRes_LOAD(N);
break;
1905 case ISD::SELECT: R = PromoteFloatRes_SELECT(N);
break;
1910 case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N);
break;
1915 SetPromotedFloat(
SDValue(N, ResNo), R);
1923 SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(
SDNode *N) {
1930 SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(
SDNode *N) {
1951 SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(
SDNode *N) {
1962 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1964 switch (getTypeAction(VecVT)) {
1968 ReplaceValueWith(
SDValue(N, 0), Res);
1972 Vec = GetWidenedVector(Vec);
1974 ReplaceValueWith(
SDValue(N, 0), Res);
1979 GetSplitVector(Vec, Lo, Hi);
1983 if (IdxVal < LoElts)
1989 ReplaceValueWith(
SDValue(N, 0), Res);
2013 SDValue DAGTypeLegalizer::PromoteFloatRes_FCOPYSIGN(
SDNode *N) {
2026 SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryOp(
SDNode *N) {
2037 SDValue DAGTypeLegalizer::PromoteFloatRes_BinOp(
SDNode *N) {
2056 SDValue DAGTypeLegalizer::PromoteFloatRes_FPOWI(
SDNode *N) {
2067 SDValue DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(
SDNode *N) {
2105 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT(
SDNode *N) {
2115 SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT_CC(
SDNode *N) {
2126 SDValue DAGTypeLegalizer::PromoteFloatRes_XINT_TO_FP(
SDNode *N) {
2137 SDValue DAGTypeLegalizer::PromoteFloatRes_UNDEF(
SDNode *N) {
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
SDValue getValue(unsigned R) const
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Flags getFlags() const
Return the raw flags of the source value,.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
LLVMContext * getContext() const
DiagnosticInfoOptimizationBase::Argument NV
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
const SDValue & getOperand(unsigned Num) const
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
const SDValue & getBasePtr() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Shift and rotation operations.
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
CopyToReg - This node has three operands: a chain, a register number to set to this value...
APInt bitcastToAPInt() const
The memory access is dereferenceable (i.e., doesn't trap).
bool bitsGE(EVT VT) const
bitsGE - Return true if this has no less bits than VT.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
bool isUNINDEXEDStore(const SDNode *N)
Returns true if the specified node is an unindexed store.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Simple integer binary arithmetic operators.
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
static RTLIB::Libcall GetFPLibCall(EVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128, RTLIB::Libcall Call_PPCF128)
GetFPLibCall - Return the right libcall for the given floating point type.
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const
Soften the operands of a comparison.
SDNode * getNode() const
get the SDNode which holds the desired result
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Simple binary floating point operators.
const unsigned int integerPartWidth
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
unsigned getOpcode() const
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
const SDValue & getValue() const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
EVT - Extended Value Type.
const APFloat & getValueAPF() const
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc, or post-dec.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
const MachinePointerInfo & getPointerInfo() const
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
const SDValue & getOffset() const
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
void dump() const
Dump this node, for debugging.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and rounds it to a floating point val...
const SDValue & getChain() const
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
Select(COND, TRUEVAL, FALSEVAL).
ZERO_EXTEND - Used for integer types, zeroing the new bits.
ANY_EXTEND - Used for integer types. The high bits are undefined.
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
Bitwise operators - logical and, logical or, logical xor.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void clearBit(unsigned bitPosition)
Set a given bit to 0.
The memory access always returns the same value (or traps).
static const fltSemantics & PPCDoubleDouble()
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getCondCode(ISD::CondCode Cond)
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input...
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
FMA - Perform a * b + c with no intermediate rounding step.
bool isTruncatingStore() const
Return true if the op does a truncation before store.
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
SetCC operator - This evaluates to a true value iff the condition is true.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
TRUNCATE - Completely drop the high bits.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
const SDNodeFlags * getFlags() const
This could be defined as a virtual function and implemented more simply and directly, but it is not to avoid creating a vtable for this class.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.