LLVM  4.0.0
Mips16InstrInfo.h
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1 //===-- Mips16InstrInfo.h - Mips16 Instruction Information ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips16 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
15 #define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H
16 
17 #include "Mips16RegisterInfo.h"
18 #include "MipsInstrInfo.h"
19 
20 namespace llvm {
21 class MipsSubtarget;
23  const Mips16RegisterInfo RI;
24 
25 public:
26  explicit Mips16InstrInfo(const MipsSubtarget &STI);
27 
28  const MipsRegisterInfo &getRegisterInfo() const override;
29 
30  /// isLoadFromStackSlot - If the specified machine instruction is a direct
31  /// load from a stack slot, return the virtual or physical register number of
32  /// the destination along with the FrameIndex of the loaded stack slot. If
33  /// not, return 0. This predicate must return 0 if the instruction has
34  /// any side effects other than loading from the stack slot.
35  unsigned isLoadFromStackSlot(const MachineInstr &MI,
36  int &FrameIndex) const override;
37 
38  /// isStoreToStackSlot - If the specified machine instruction is a direct
39  /// store to a stack slot, return the virtual or physical register number of
40  /// the source reg along with the FrameIndex of the loaded stack slot. If
41  /// not, return 0. This predicate must return 0 if the instruction has
42  /// any side effects other than storing to the stack slot.
43  unsigned isStoreToStackSlot(const MachineInstr &MI,
44  int &FrameIndex) const override;
45 
47  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
48  bool KillSrc) const override;
49 
52  unsigned SrcReg, bool isKill, int FrameIndex,
53  const TargetRegisterClass *RC,
54  const TargetRegisterInfo *TRI,
55  int64_t Offset) const override;
56 
59  unsigned DestReg, int FrameIndex,
60  const TargetRegisterClass *RC,
61  const TargetRegisterInfo *TRI,
62  int64_t Offset) const override;
63 
64  bool expandPostRAPseudo(MachineInstr &MI) const override;
65 
66  unsigned getOppositeBranchOpc(unsigned Opc) const override;
67 
68  // Adjust SP by FrameSize bytes. Save RA, S0, S1
69  void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
71 
72  // Adjust SP by FrameSize bytes. Restore RA, S0, S1
73  void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB,
75 
76 
77  /// Adjust SP by Amount bytes.
78  void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
79  MachineBasicBlock::iterator I) const override;
80 
81  /// Emit a series of instructions to load an immediate.
82  // This is to adjust some FrameReg. We return the new register to be used
83  // in place of FrameReg and the adjusted immediate field (&NewImm)
84  //
85  unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB,
87  unsigned &NewImm) const;
88 
89  static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount);
90 
91  static bool validSpImm8(int offset) {
92  return ((offset & 7) == 0) && isInt<11>(offset);
93  }
94 
95  //
96  // build the proper one based on the Imm field
97  //
98 
99  const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
100 
101  void BuildAddiuSpImm
102  (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
103 
104  unsigned getInlineAsmLength(const char *Str,
105  const MCAsmInfo &MAI) const override;
106 private:
107  unsigned getAnalyzableBrOpc(unsigned Opc) const override;
108 
109  void ExpandRetRA16(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
110  unsigned Opc) const;
111 
112  // Adjust SP by Amount bytes where bytes can be up to 32bit number.
113  void adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
115  unsigned Reg1, unsigned Reg2) const;
116 
117  // Adjust SP by Amount bytes where bytes can be up to 32bit number.
118  void adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount,
119  MachineBasicBlock &MBB,
121 
122 };
123 
124 }
125 
126 #endif
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
void makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
const MCInstrDesc & AddiuSpImm(int64_t Imm) const
A debug info location.
Definition: DebugLoc.h:34
Reg
All possible values of the reg field in the ModR/M byte.
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
MachineBasicBlock * MBB
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
void BuildAddiuSpImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
void restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
uint32_t Offset
bool expandPostRAPseudo(MachineInstr &MI) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool validSpImm8(int offset)
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
Representation of each machine instruction.
Definition: MachineInstr.h:52
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
Mips16InstrInfo(const MipsSubtarget &STI)
IRTranslator LLVM IR MI
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned getOppositeBranchOpc(unsigned Opc) const override
GetOppositeBranchOpc - Return the inverse of the specified opcode, e.g.