29 #define DEBUG_TYPE "arm-disassembler"
47 void advanceITState() {
52 bool instrInITBlock() {
53 return !ITStates.empty();
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
64 void setITState(
char Firstcond,
char Mask) {
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = countTrailingZeros<uint8_t>(
Mask);
68 unsigned char CCBits =
static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 &&
"Invalid IT mask!");
71 for (
unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
94 ~ARMDisassembler()
override {}
109 ~ThumbDisassembler()
override {}
117 mutable ITStatus ITBlock;
119 void UpdateThumbVFPPredicate(
MCInst&)
const;
142 uint64_t
Address,
const void *Decoder);
144 unsigned RegNo, uint64_t
Address,
145 const void *Decoder);
147 unsigned RegNo, uint64_t
Address,
148 const void *Decoder);
150 uint64_t
Address,
const void *Decoder);
152 uint64_t
Address,
const void *Decoder);
154 uint64_t
Address,
const void *Decoder);
156 uint64_t
Address,
const void *Decoder);
158 uint64_t
Address,
const void *Decoder);
160 uint64_t
Address,
const void *Decoder);
162 uint64_t
Address,
const void *Decoder);
166 const void *Decoder);
168 uint64_t
Address,
const void *Decoder);
170 uint64_t
Address,
const void *Decoder);
172 unsigned RegNo, uint64_t
Address,
173 const void *Decoder);
176 uint64_t
Address,
const void *Decoder);
178 uint64_t
Address,
const void *Decoder);
180 uint64_t
Address,
const void *Decoder);
182 uint64_t
Address,
const void *Decoder);
184 uint64_t
Address,
const void *Decoder);
187 uint64_t
Address,
const void *Decoder);
189 uint64_t
Address,
const void *Decoder);
193 const void *Decoder);
195 uint64_t
Address,
const void *Decoder);
197 uint64_t
Address,
const void *Decoder);
199 uint64_t
Address,
const void *Decoder);
201 uint64_t
Address,
const void *Decoder);
206 const void *Decoder);
208 uint64_t
Address,
const void *Decoder);
210 uint64_t
Address,
const void *Decoder);
212 uint64_t
Address,
const void *Decoder);
214 uint64_t
Address,
const void *Decoder);
216 uint64_t
Address,
const void *Decoder);
218 uint64_t
Address,
const void *Decoder);
220 uint64_t
Address,
const void *Decoder);
222 uint64_t
Address,
const void *Decoder);
224 uint64_t
Address,
const void *Decoder);
226 uint64_t
Address,
const void *Decoder);
228 uint64_t
Address,
const void *Decoder);
230 uint64_t
Address,
const void *Decoder);
232 uint64_t
Address,
const void *Decoder);
234 uint64_t
Address,
const void *Decoder);
236 uint64_t
Address,
const void *Decoder);
238 uint64_t
Address,
const void *Decoder);
240 uint64_t
Address,
const void *Decoder);
242 uint64_t
Address,
const void *Decoder);
244 uint64_t
Address,
const void *Decoder);
246 uint64_t
Address,
const void *Decoder);
248 uint64_t
Address,
const void *Decoder);
250 uint64_t
Address,
const void *Decoder);
252 uint64_t
Address,
const void *Decoder);
254 uint64_t
Address,
const void *Decoder);
256 uint64_t
Address,
const void *Decoder);
258 uint64_t
Address,
const void *Decoder);
260 uint64_t
Address,
const void *Decoder);
262 uint64_t
Address,
const void *Decoder);
264 uint64_t
Address,
const void *Decoder);
266 uint64_t
Address,
const void *Decoder);
268 uint64_t
Address,
const void *Decoder);
270 uint64_t
Address,
const void *Decoder);
272 uint64_t
Address,
const void *Decoder);
274 uint64_t
Address,
const void *Decoder);
276 uint64_t
Address,
const void *Decoder);
278 uint64_t
Address,
const void *Decoder);
280 uint64_t
Address,
const void *Decoder);
282 uint64_t
Address,
const void *Decoder);
284 uint64_t
Address,
const void *Decoder);
286 uint64_t
Address,
const void *Decoder);
288 uint64_t
Address,
const void *Decoder);
290 uint64_t
Address,
const void *Decoder);
292 uint64_t
Address,
const void *Decoder);
294 uint64_t
Address,
const void *Decoder);
296 uint64_t
Address,
const void *Decoder);
298 uint64_t
Address,
const void *Decoder);
300 uint64_t
Address,
const void *Decoder);
302 uint64_t
Address,
const void *Decoder);
304 uint64_t
Address,
const void *Decoder);
306 uint64_t
Address,
const void *Decoder);
308 uint64_t
Address,
const void *Decoder);
310 uint64_t
Address,
const void *Decoder);
312 uint64_t
Address,
const void *Decoder);
314 uint64_t
Address,
const void *Decoder);
316 uint64_t
Address,
const void *Decoder);
318 uint64_t
Address,
const void *Decoder);
320 uint64_t
Address,
const void *Decoder);
324 uint64_t
Address,
const void *Decoder);
326 uint64_t
Address,
const void *Decoder);
328 uint64_t
Address,
const void *Decoder);
330 uint64_t
Address,
const void *Decoder);
332 uint64_t
Address,
const void *Decoder);
334 uint64_t
Address,
const void *Decoder);
336 uint64_t
Address,
const void *Decoder);
338 uint64_t
Address,
const void *Decoder);
340 uint64_t
Address,
const void *Decoder);
342 uint64_t
Address,
const void *Decoder);
344 uint64_t
Address,
const void* Decoder);
346 uint64_t
Address,
const void* Decoder);
348 uint64_t
Address,
const void* Decoder);
350 uint64_t
Address,
const void* Decoder);
352 uint64_t
Address,
const void *Decoder);
354 uint64_t
Address,
const void *Decoder);
356 uint64_t
Address,
const void *Decoder);
358 uint64_t
Address,
const void *Decoder);
360 uint64_t
Address,
const void *Decoder);
362 uint64_t
Address,
const void *Decoder);
364 uint64_t
Address,
const void *Decoder);
366 uint64_t
Address,
const void *Decoder);
368 uint64_t
Address,
const void *Decoder);
370 uint64_t
Address,
const void *Decoder);
372 uint64_t
Address,
const void *Decoder);
374 uint64_t
Address,
const void *Decoder);
376 uint64_t
Address,
const void *Decoder);
378 uint64_t
Address,
const void *Decoder);
380 uint64_t
Address,
const void *Decoder);
382 uint64_t
Address,
const void *Decoder);
384 uint64_t
Address,
const void *Decoder);
386 uint64_t
Address,
const void *Decoder);
388 uint64_t
Address,
const void *Decoder);
390 uint64_t
Address,
const void *Decoder);
392 uint64_t
Address,
const void *Decoder);
394 uint64_t
Address,
const void *Decoder);
397 uint64_t
Address,
const void *Decoder);
399 uint64_t
Address,
const void *Decoder);
400 #include "ARMGenDisassemblerTables.inc"
405 return new ARMDisassembler(STI, Ctx);
411 return new ThumbDisassembler(STI, Ctx);
432 default:
return Result;
442 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
443 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
447 if (Bytes.
size() < 4) {
454 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
547 MCInst &MI,
const void *Decoder) {
564 const void *Decoder) {
577 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
578 if (I == MI.
end())
break;
579 if (OpInfo[
i].isOptionalDef() && OpInfo[
i].
RegClass == ARM::CCRRegClassID) {
580 if (
i > 0 && OpInfo[
i-1].isPredicate())
continue;
594 ThumbDisassembler::AddThumbPredicate(
MCInst &MI)
const {
597 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
614 if (ITBlock.instrInITBlock())
620 if (MI.
getOperand(0).
getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
629 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
639 CC = ITBlock.getITCC();
642 if (ITBlock.instrInITBlock())
643 ITBlock.advanceITState();
648 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
649 if (I == MI.
end())
break;
650 if (OpInfo[
i].isPredicate()) {
676 void ThumbDisassembler::UpdateThumbVFPPredicate(
MCInst &MI)
const {
678 CC = ITBlock.getITCC();
679 if (ITBlock.instrInITBlock())
680 ITBlock.advanceITState();
685 for (
unsigned i = 0;
i < NumOps; ++
i, ++
I) {
686 if (OpInfo[
i].isPredicate() ) {
692 I->setReg(ARM::CPSR);
705 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
706 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
709 if (Bytes.
size() < 2) {
714 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
719 Check(Result, AddThumbPredicate(MI));
727 bool InITBlock = ITBlock.instrInITBlock();
728 Check(Result, AddThumbPredicate(MI));
740 if (MI.
getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
743 Check(Result, AddThumbPredicate(MI));
752 ITBlock.setITState(Firstcond, Mask);
759 if (Bytes.
size() < 4) {
765 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
770 bool InITBlock = ITBlock.instrInITBlock();
771 Check(Result, AddThumbPredicate(MI));
780 Check(Result, AddThumbPredicate(MI));
784 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
789 UpdateThumbVFPPredicate(MI);
801 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
806 Check(Result, AddThumbPredicate(MI));
811 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
813 NEONLdStInsn &= 0xF0FFFFFF;
814 NEONLdStInsn |= 0x04000000;
819 Check(Result, AddThumbPredicate(MI));
824 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
826 NEONDataInsn &= 0xF0FFFFFF;
827 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4;
828 NEONDataInsn |= 0x12000000;
833 Check(Result, AddThumbPredicate(MI));
838 NEONCryptoInsn &= 0xF0FFFFFF;
839 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4;
840 NEONCryptoInsn |= 0x12000000;
849 NEONv8Insn &= 0xF3FFFFFF;
875 ARM::R0, ARM::R1,
ARM::R2, ARM::R3,
877 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
878 ARM::R12, ARM::SP, ARM::LR,
ARM::PC
882 uint64_t Address,
const void *Decoder) {
893 uint64_t Address,
const void *Decoder) {
906 uint64_t Address,
const void *Decoder) {
920 uint64_t Address,
const void *Decoder) {
927 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
928 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
932 uint64_t Address,
const void *Decoder) {
938 if ((RegNo & 1) || RegNo == 0xe)
947 uint64_t Address,
const void *Decoder) {
977 uint64_t Address,
const void *Decoder) {
981 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
983 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
991 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
992 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
993 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
994 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
995 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
996 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
997 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
998 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1002 uint64_t Address,
const void *Decoder) {
1012 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1013 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1014 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1015 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1016 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1017 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1018 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1019 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1023 uint64_t Address,
const void *Decoder) {
1025 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1027 bool hasD16 = featureBits[ARM::FeatureD16];
1029 if (RegNo > 31 || (hasD16 && RegNo > 15))
1038 uint64_t Address,
const void *Decoder) {
1046 uint64_t Address,
const void *Decoder) {
1053 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1054 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1055 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1056 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1061 uint64_t Address,
const void *Decoder) {
1062 if (RegNo > 31 || (RegNo & 1) != 0)
1072 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1073 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1074 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1075 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1076 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1081 uint64_t Address,
const void *Decoder) {
1091 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1092 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1093 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1094 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1095 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1096 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1097 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1098 ARM::D28_D30, ARM::D29_D31
1104 const void *Decoder) {
1114 uint64_t Address,
const void *Decoder) {
1117 if (Inst.
getOpcode() == ARM::tBcc && Val == 0xE)
1128 uint64_t Address,
const void *Decoder) {
1137 uint64_t Address,
const void *Decoder) {
1140 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1141 unsigned type = fieldFromInstruction(Val, 5, 2);
1142 unsigned imm = fieldFromInstruction(Val, 7, 5);
1167 unsigned Op = Shift | (imm << 3);
1174 uint64_t Address,
const void *Decoder) {
1177 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1178 unsigned type = fieldFromInstruction(Val, 5, 2);
1179 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1209 uint64_t Address,
const void *Decoder) {
1212 bool NeedDisjointWriteback =
false;
1213 unsigned WritebackReg = 0;
1217 case ARM::LDMIA_UPD:
1218 case ARM::LDMDB_UPD:
1219 case ARM::LDMIB_UPD:
1220 case ARM::LDMDA_UPD:
1221 case ARM::t2LDMIA_UPD:
1222 case ARM::t2LDMDB_UPD:
1223 case ARM::t2STMIA_UPD:
1224 case ARM::t2STMDB_UPD:
1225 NeedDisjointWriteback =
true;
1232 for (
unsigned i = 0;
i < 16; ++
i) {
1233 if (Val & (1 <<
i)) {
1237 if (NeedDisjointWriteback && WritebackReg == Inst.
end()[-1].getReg())
1246 uint64_t Address,
const void *Decoder) {
1249 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1250 unsigned regs = fieldFromInstruction(Val, 0, 8);
1253 if (regs == 0 || (Vd + regs) > 32) {
1254 regs = Vd + regs > 32 ? 32 - Vd : regs;
1255 regs = std::max( 1u, regs);
1261 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1270 uint64_t Address,
const void *Decoder) {
1273 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1274 unsigned regs = fieldFromInstruction(Val, 1, 7);
1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1278 regs = Vd + regs > 32 ? 32 - Vd : regs;
1279 regs = std::max( 1u, regs);
1286 for (
unsigned i = 0;
i < (regs - 1); ++
i) {
1295 uint64_t Address,
const void *Decoder) {
1301 unsigned msb = fieldFromInstruction(Val, 5, 5);
1302 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1314 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1315 uint32_t lsb_mask = (1U << lsb) - 1;
1322 uint64_t Address,
const void *Decoder) {
1325 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1326 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1327 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1328 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1329 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1330 unsigned U = fieldFromInstruction(Insn, 23, 1);
1333 case ARM::LDC_OFFSET:
1336 case ARM::LDC_OPTION:
1337 case ARM::LDCL_OFFSET:
1339 case ARM::LDCL_POST:
1340 case ARM::LDCL_OPTION:
1341 case ARM::STC_OFFSET:
1344 case ARM::STC_OPTION:
1345 case ARM::STCL_OFFSET:
1347 case ARM::STCL_POST:
1348 case ARM::STCL_OPTION:
1349 case ARM::t2LDC_OFFSET:
1350 case ARM::t2LDC_PRE:
1351 case ARM::t2LDC_POST:
1352 case ARM::t2LDC_OPTION:
1353 case ARM::t2LDCL_OFFSET:
1354 case ARM::t2LDCL_PRE:
1355 case ARM::t2LDCL_POST:
1356 case ARM::t2LDCL_OPTION:
1357 case ARM::t2STC_OFFSET:
1358 case ARM::t2STC_PRE:
1359 case ARM::t2STC_POST:
1360 case ARM::t2STC_OPTION:
1361 case ARM::t2STCL_OFFSET:
1362 case ARM::t2STCL_PRE:
1363 case ARM::t2STCL_POST:
1364 case ARM::t2STCL_OPTION:
1365 if (coproc == 0xA || coproc == 0xB)
1373 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1374 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1383 case ARM::t2LDC2_OFFSET:
1384 case ARM::t2LDC2L_OFFSET:
1385 case ARM::t2LDC2_PRE:
1386 case ARM::t2LDC2L_PRE:
1387 case ARM::t2STC2_OFFSET:
1388 case ARM::t2STC2L_OFFSET:
1389 case ARM::t2STC2_PRE:
1390 case ARM::t2STC2L_PRE:
1391 case ARM::LDC2_OFFSET:
1392 case ARM::LDC2L_OFFSET:
1394 case ARM::LDC2L_PRE:
1395 case ARM::STC2_OFFSET:
1396 case ARM::STC2L_OFFSET:
1398 case ARM::STC2L_PRE:
1399 case ARM::t2LDC_OFFSET:
1400 case ARM::t2LDCL_OFFSET:
1401 case ARM::t2LDC_PRE:
1402 case ARM::t2LDCL_PRE:
1403 case ARM::t2STC_OFFSET:
1404 case ARM::t2STCL_OFFSET:
1405 case ARM::t2STC_PRE:
1406 case ARM::t2STCL_PRE:
1407 case ARM::LDC_OFFSET:
1408 case ARM::LDCL_OFFSET:
1411 case ARM::STC_OFFSET:
1412 case ARM::STCL_OFFSET:
1418 case ARM::t2LDC2_POST:
1419 case ARM::t2LDC2L_POST:
1420 case ARM::t2STC2_POST:
1421 case ARM::t2STC2L_POST:
1422 case ARM::LDC2_POST:
1423 case ARM::LDC2L_POST:
1424 case ARM::STC2_POST:
1425 case ARM::STC2L_POST:
1426 case ARM::t2LDC_POST:
1427 case ARM::t2LDCL_POST:
1428 case ARM::t2STC_POST:
1429 case ARM::t2STCL_POST:
1431 case ARM::LDCL_POST:
1433 case ARM::STCL_POST:
1444 case ARM::LDC_OFFSET:
1447 case ARM::LDC_OPTION:
1448 case ARM::LDCL_OFFSET:
1450 case ARM::LDCL_POST:
1451 case ARM::LDCL_OPTION:
1452 case ARM::STC_OFFSET:
1455 case ARM::STC_OPTION:
1456 case ARM::STCL_OFFSET:
1458 case ARM::STCL_POST:
1459 case ARM::STCL_OPTION:
1472 uint64_t Address,
const void *Decoder) {
1475 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1477 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1478 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1479 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1480 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1481 unsigned P = fieldFromInstruction(Insn, 24, 1);
1482 unsigned W = fieldFromInstruction(Insn, 21, 1);
1486 case ARM::STR_POST_IMM:
1487 case ARM::STR_POST_REG:
1488 case ARM::STRB_POST_IMM:
1489 case ARM::STRB_POST_REG:
1490 case ARM::STRT_POST_REG:
1491 case ARM::STRT_POST_IMM:
1492 case ARM::STRBT_POST_REG:
1493 case ARM::STRBT_POST_IMM:
1506 case ARM::LDR_POST_IMM:
1507 case ARM::LDR_POST_REG:
1508 case ARM::LDRB_POST_IMM:
1509 case ARM::LDRB_POST_REG:
1510 case ARM::LDRBT_POST_REG:
1511 case ARM::LDRBT_POST_IMM:
1512 case ARM::LDRT_POST_REG:
1513 case ARM::LDRT_POST_IMM:
1525 if (!fieldFromInstruction(Insn, 23, 1))
1528 bool writeback = (P == 0) || (W == 1);
1529 unsigned idx_mode = 0;
1532 else if (!P && writeback)
1535 if (writeback && (Rn == 15 || Rn == Rt))
1542 switch( fieldFromInstruction(Insn, 5, 2)) {
1558 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1577 uint64_t Address,
const void *Decoder) {
1580 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1581 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1582 unsigned type = fieldFromInstruction(Val, 5, 2);
1583 unsigned imm = fieldFromInstruction(Val, 7, 5);
1584 unsigned U = fieldFromInstruction(Val, 12, 1);
1621 uint64_t Address,
const void *Decoder) {
1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1625 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1626 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1627 unsigned type = fieldFromInstruction(Insn, 22, 1);
1628 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1629 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1630 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1631 unsigned W = fieldFromInstruction(Insn, 21, 1);
1632 unsigned P = fieldFromInstruction(Insn, 24, 1);
1633 unsigned Rt2 = Rt + 1;
1635 bool writeback = (W == 1) | (P == 0);
1641 case ARM::STRD_POST:
1644 case ARM::LDRD_POST:
1653 case ARM::STRD_POST:
1654 if (P == 0 && W == 1)
1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1659 if (type && Rm == 15)
1663 if (!type && fieldFromInstruction(Insn, 8, 4))
1668 case ARM::STRH_POST:
1671 if (writeback && (Rn == 15 || Rn == Rt))
1673 if (!type && Rm == 15)
1678 case ARM::LDRD_POST:
1679 if (type && Rn == 15){
1684 if (P == 0 && W == 1)
1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1688 if (!type && writeback && Rn == 15)
1690 if (writeback && (Rn == Rt || Rn == Rt2))
1695 case ARM::LDRH_POST:
1696 if (type && Rn == 15){
1703 if (!type && Rm == 15)
1705 if (!type && writeback && (Rn == 15 || Rn == Rt))
1709 case ARM::LDRSH_PRE:
1710 case ARM::LDRSH_POST:
1712 case ARM::LDRSB_PRE:
1713 case ARM::LDRSB_POST:
1714 if (type && Rn == 15){
1719 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1721 if (!type && (Rt == 15 || Rm == 15))
1723 if (!type && writeback && (Rn == 15 || Rn == Rt))
1740 case ARM::STRD_POST:
1743 case ARM::STRH_POST:
1757 case ARM::STRD_POST:
1760 case ARM::LDRD_POST:
1773 case ARM::LDRD_POST:
1776 case ARM::LDRH_POST:
1778 case ARM::LDRSH_PRE:
1779 case ARM::LDRSH_POST:
1781 case ARM::LDRSB_PRE:
1782 case ARM::LDRSB_POST:
1812 uint64_t Address,
const void *Decoder) {
1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1816 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1841 uint64_t Address,
const void *Decoder) {
1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1845 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1846 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1847 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1865 uint64_t Address,
const void *Decoder) {
1868 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1869 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1878 case ARM::LDMDA_UPD:
1884 case ARM::LDMDB_UPD:
1890 case ARM::LDMIA_UPD:
1896 case ARM::LDMIB_UPD:
1902 case ARM::STMDA_UPD:
1908 case ARM::STMDB_UPD:
1914 case ARM::STMIA_UPD:
1920 case ARM::STMIB_UPD:
1928 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1930 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1931 fieldFromInstruction(Insn, 20, 1) == 0))
1956 uint64_t Address,
const void *Decoder) {
1957 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1958 unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
1971 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
1978 uint64_t Address,
const void *Decoder) {
1979 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1980 unsigned M = fieldFromInstruction(Insn, 17, 1);
1981 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1982 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1988 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1989 fieldFromInstruction(Insn, 16, 1) != 0 ||
1990 fieldFromInstruction(Insn, 20, 8) != 0x10)
2005 }
else if (imod && !M) {
2010 }
else if (!imod && M) {
2025 uint64_t Address,
const void *Decoder) {
2026 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2027 unsigned M = fieldFromInstruction(Insn, 8, 1);
2028 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2029 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2045 }
else if (imod && !M) {
2050 }
else if (!imod && M) {
2056 int imm = fieldFromInstruction(Insn, 0, 8);
2067 uint64_t Address,
const void *Decoder) {
2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2073 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2074 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2075 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2076 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2091 uint64_t Address,
const void *Decoder) {
2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2095 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2098 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2099 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2118 uint64_t Address,
const void *Decoder) {
2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2122 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2123 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2124 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2125 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2146 uint64_t Address,
const void *Decoder) {
2149 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2150 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2151 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2167 uint64_t Address,
const void *Decoder) {
2170 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2175 if (!FeatureBits[ARM::HasV8_1aOps] ||
2176 !FeatureBits[ARM::HasV8Ops])
2181 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2182 fieldFromInstruction(Insn, 4,4) != 0)
2184 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2185 fieldFromInstruction(Insn, 0,4) != 0)
2195 uint64_t Address,
const void *Decoder) {
2198 unsigned add = fieldFromInstruction(Val, 12, 1);
2199 unsigned imm = fieldFromInstruction(Val, 0, 12);
2200 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2205 if (!add) imm *= -1;
2206 if (imm == 0 && !add) imm = INT32_MIN;
2215 uint64_t Address,
const void *Decoder) {
2218 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2220 unsigned U = fieldFromInstruction(Val, 8, 1);
2221 unsigned imm = fieldFromInstruction(Val, 0, 8);
2235 uint64_t Address,
const void *Decoder) {
2238 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2240 unsigned U = fieldFromInstruction(Val, 8, 1);
2241 unsigned imm = fieldFromInstruction(Val, 0, 8);
2255 uint64_t Address,
const void *Decoder) {
2261 uint64_t Address,
const void *Decoder) {
2270 unsigned S = fieldFromInstruction(Insn, 26, 1);
2271 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2272 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2273 unsigned I1 = !(J1 ^ S);
2274 unsigned I2 = !(J2 ^ S);
2275 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2276 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2277 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2278 int imm32 = SignExtend32<25>(tmp << 1);
2280 true, 4, Inst, Decoder))
2288 uint64_t Address,
const void *Decoder) {
2291 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2292 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2296 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2298 true, 4, Inst, Decoder))
2304 true, 4, Inst, Decoder))
2314 uint64_t Address,
const void *Decoder) {
2317 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2318 unsigned align = fieldFromInstruction(Val, 4, 2);
2331 uint64_t Address,
const void *Decoder) {
2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2335 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2336 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2337 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2338 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2339 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2343 case ARM::VLD1q16:
case ARM::VLD1q32:
case ARM::VLD1q64:
case ARM::VLD1q8:
2344 case ARM::VLD1q16wb_fixed:
case ARM::VLD1q16wb_register:
2345 case ARM::VLD1q32wb_fixed:
case ARM::VLD1q32wb_register:
2346 case ARM::VLD1q64wb_fixed:
case ARM::VLD1q64wb_register:
2347 case ARM::VLD1q8wb_fixed:
case ARM::VLD1q8wb_register:
2348 case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d8:
2349 case ARM::VLD2d16wb_fixed:
case ARM::VLD2d16wb_register:
2350 case ARM::VLD2d32wb_fixed:
case ARM::VLD2d32wb_register:
2351 case ARM::VLD2d8wb_fixed:
case ARM::VLD2d8wb_register:
2358 case ARM::VLD2b16wb_fixed:
2359 case ARM::VLD2b16wb_register:
2360 case ARM::VLD2b32wb_fixed:
2361 case ARM::VLD2b32wb_register:
2362 case ARM::VLD2b8wb_fixed:
2363 case ARM::VLD2b8wb_register:
2377 case ARM::VLD3d8_UPD:
2378 case ARM::VLD3d16_UPD:
2379 case ARM::VLD3d32_UPD:
2383 case ARM::VLD4d8_UPD:
2384 case ARM::VLD4d16_UPD:
2385 case ARM::VLD4d32_UPD:
2392 case ARM::VLD3q8_UPD:
2393 case ARM::VLD3q16_UPD:
2394 case ARM::VLD3q32_UPD:
2398 case ARM::VLD4q8_UPD:
2399 case ARM::VLD4q16_UPD:
2400 case ARM::VLD4q32_UPD:
2412 case ARM::VLD3d8_UPD:
2413 case ARM::VLD3d16_UPD:
2414 case ARM::VLD3d32_UPD:
2418 case ARM::VLD4d8_UPD:
2419 case ARM::VLD4d16_UPD:
2420 case ARM::VLD4d32_UPD:
2427 case ARM::VLD3q8_UPD:
2428 case ARM::VLD3q16_UPD:
2429 case ARM::VLD3q32_UPD:
2433 case ARM::VLD4q8_UPD:
2434 case ARM::VLD4q16_UPD:
2435 case ARM::VLD4q32_UPD:
2448 case ARM::VLD4d8_UPD:
2449 case ARM::VLD4d16_UPD:
2450 case ARM::VLD4d32_UPD:
2457 case ARM::VLD4q8_UPD:
2458 case ARM::VLD4q16_UPD:
2459 case ARM::VLD4q32_UPD:
2469 case ARM::VLD1d8wb_fixed:
2470 case ARM::VLD1d16wb_fixed:
2471 case ARM::VLD1d32wb_fixed:
2472 case ARM::VLD1d64wb_fixed:
2473 case ARM::VLD1d8wb_register:
2474 case ARM::VLD1d16wb_register:
2475 case ARM::VLD1d32wb_register:
2476 case ARM::VLD1d64wb_register:
2477 case ARM::VLD1q8wb_fixed:
2478 case ARM::VLD1q16wb_fixed:
2479 case ARM::VLD1q32wb_fixed:
2480 case ARM::VLD1q64wb_fixed:
2481 case ARM::VLD1q8wb_register:
2482 case ARM::VLD1q16wb_register:
2483 case ARM::VLD1q32wb_register:
2484 case ARM::VLD1q64wb_register:
2485 case ARM::VLD1d8Twb_fixed:
2486 case ARM::VLD1d8Twb_register:
2487 case ARM::VLD1d16Twb_fixed:
2488 case ARM::VLD1d16Twb_register:
2489 case ARM::VLD1d32Twb_fixed:
2490 case ARM::VLD1d32Twb_register:
2491 case ARM::VLD1d64Twb_fixed:
2492 case ARM::VLD1d64Twb_register:
2493 case ARM::VLD1d8Qwb_fixed:
2494 case ARM::VLD1d8Qwb_register:
2495 case ARM::VLD1d16Qwb_fixed:
2496 case ARM::VLD1d16Qwb_register:
2497 case ARM::VLD1d32Qwb_fixed:
2498 case ARM::VLD1d32Qwb_register:
2499 case ARM::VLD1d64Qwb_fixed:
2500 case ARM::VLD1d64Qwb_register:
2501 case ARM::VLD2d8wb_fixed:
2502 case ARM::VLD2d16wb_fixed:
2503 case ARM::VLD2d32wb_fixed:
2504 case ARM::VLD2q8wb_fixed:
2505 case ARM::VLD2q16wb_fixed:
2506 case ARM::VLD2q32wb_fixed:
2507 case ARM::VLD2d8wb_register:
2508 case ARM::VLD2d16wb_register:
2509 case ARM::VLD2d32wb_register:
2510 case ARM::VLD2q8wb_register:
2511 case ARM::VLD2q16wb_register:
2512 case ARM::VLD2q32wb_register:
2513 case ARM::VLD2b8wb_fixed:
2514 case ARM::VLD2b16wb_fixed:
2515 case ARM::VLD2b32wb_fixed:
2516 case ARM::VLD2b8wb_register:
2517 case ARM::VLD2b16wb_register:
2518 case ARM::VLD2b32wb_register:
2521 case ARM::VLD3d8_UPD:
2522 case ARM::VLD3d16_UPD:
2523 case ARM::VLD3d32_UPD:
2524 case ARM::VLD3q8_UPD:
2525 case ARM::VLD3q16_UPD:
2526 case ARM::VLD3q32_UPD:
2527 case ARM::VLD4d8_UPD:
2528 case ARM::VLD4d16_UPD:
2529 case ARM::VLD4d32_UPD:
2530 case ARM::VLD4q8_UPD:
2531 case ARM::VLD4q16_UPD:
2532 case ARM::VLD4q32_UPD:
2559 case ARM::VLD1d8wb_fixed:
2560 case ARM::VLD1d16wb_fixed:
2561 case ARM::VLD1d32wb_fixed:
2562 case ARM::VLD1d64wb_fixed:
2563 case ARM::VLD1d8Twb_fixed:
2564 case ARM::VLD1d16Twb_fixed:
2565 case ARM::VLD1d32Twb_fixed:
2566 case ARM::VLD1d64Twb_fixed:
2567 case ARM::VLD1d8Qwb_fixed:
2568 case ARM::VLD1d16Qwb_fixed:
2569 case ARM::VLD1d32Qwb_fixed:
2570 case ARM::VLD1d64Qwb_fixed:
2571 case ARM::VLD1d8wb_register:
2572 case ARM::VLD1d16wb_register:
2573 case ARM::VLD1d32wb_register:
2574 case ARM::VLD1d64wb_register:
2575 case ARM::VLD1q8wb_fixed:
2576 case ARM::VLD1q16wb_fixed:
2577 case ARM::VLD1q32wb_fixed:
2578 case ARM::VLD1q64wb_fixed:
2579 case ARM::VLD1q8wb_register:
2580 case ARM::VLD1q16wb_register:
2581 case ARM::VLD1q32wb_register:
2582 case ARM::VLD1q64wb_register:
2586 if (Rm != 0xD && Rm != 0xF &&
2590 case ARM::VLD2d8wb_fixed:
2591 case ARM::VLD2d16wb_fixed:
2592 case ARM::VLD2d32wb_fixed:
2593 case ARM::VLD2b8wb_fixed:
2594 case ARM::VLD2b16wb_fixed:
2595 case ARM::VLD2b32wb_fixed:
2596 case ARM::VLD2q8wb_fixed:
2597 case ARM::VLD2q16wb_fixed:
2598 case ARM::VLD2q32wb_fixed:
2606 uint64_t Address,
const void *Decoder) {
2607 unsigned type = fieldFromInstruction(Insn, 8, 4);
2608 unsigned align = fieldFromInstruction(Insn, 4, 2);
2613 unsigned load = fieldFromInstruction(Insn, 21, 1);
2619 uint64_t Address,
const void *Decoder) {
2620 unsigned size = fieldFromInstruction(Insn, 6, 2);
2623 unsigned type = fieldFromInstruction(Insn, 8, 4);
2624 unsigned align = fieldFromInstruction(Insn, 4, 2);
2628 unsigned load = fieldFromInstruction(Insn, 21, 1);
2634 uint64_t Address,
const void *Decoder) {
2635 unsigned size = fieldFromInstruction(Insn, 6, 2);
2638 unsigned align = fieldFromInstruction(Insn, 4, 2);
2641 unsigned load = fieldFromInstruction(Insn, 21, 1);
2647 uint64_t Address,
const void *Decoder) {
2648 unsigned size = fieldFromInstruction(Insn, 6, 2);
2651 unsigned load = fieldFromInstruction(Insn, 21, 1);
2657 uint64_t Address,
const void *Decoder) {
2660 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2661 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2662 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2663 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2664 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2665 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2669 case ARM::VST1d8wb_fixed:
2670 case ARM::VST1d16wb_fixed:
2671 case ARM::VST1d32wb_fixed:
2672 case ARM::VST1d64wb_fixed:
2673 case ARM::VST1d8wb_register:
2674 case ARM::VST1d16wb_register:
2675 case ARM::VST1d32wb_register:
2676 case ARM::VST1d64wb_register:
2677 case ARM::VST1q8wb_fixed:
2678 case ARM::VST1q16wb_fixed:
2679 case ARM::VST1q32wb_fixed:
2680 case ARM::VST1q64wb_fixed:
2681 case ARM::VST1q8wb_register:
2682 case ARM::VST1q16wb_register:
2683 case ARM::VST1q32wb_register:
2684 case ARM::VST1q64wb_register:
2685 case ARM::VST1d8Twb_fixed:
2686 case ARM::VST1d16Twb_fixed:
2687 case ARM::VST1d32Twb_fixed:
2688 case ARM::VST1d64Twb_fixed:
2689 case ARM::VST1d8Twb_register:
2690 case ARM::VST1d16Twb_register:
2691 case ARM::VST1d32Twb_register:
2692 case ARM::VST1d64Twb_register:
2693 case ARM::VST1d8Qwb_fixed:
2694 case ARM::VST1d16Qwb_fixed:
2695 case ARM::VST1d32Qwb_fixed:
2696 case ARM::VST1d64Qwb_fixed:
2697 case ARM::VST1d8Qwb_register:
2698 case ARM::VST1d16Qwb_register:
2699 case ARM::VST1d32Qwb_register:
2700 case ARM::VST1d64Qwb_register:
2701 case ARM::VST2d8wb_fixed:
2702 case ARM::VST2d16wb_fixed:
2703 case ARM::VST2d32wb_fixed:
2704 case ARM::VST2d8wb_register:
2705 case ARM::VST2d16wb_register:
2706 case ARM::VST2d32wb_register:
2707 case ARM::VST2q8wb_fixed:
2708 case ARM::VST2q16wb_fixed:
2709 case ARM::VST2q32wb_fixed:
2710 case ARM::VST2q8wb_register:
2711 case ARM::VST2q16wb_register:
2712 case ARM::VST2q32wb_register:
2713 case ARM::VST2b8wb_fixed:
2714 case ARM::VST2b16wb_fixed:
2715 case ARM::VST2b32wb_fixed:
2716 case ARM::VST2b8wb_register:
2717 case ARM::VST2b16wb_register:
2718 case ARM::VST2b32wb_register:
2723 case ARM::VST3d8_UPD:
2724 case ARM::VST3d16_UPD:
2725 case ARM::VST3d32_UPD:
2726 case ARM::VST3q8_UPD:
2727 case ARM::VST3q16_UPD:
2728 case ARM::VST3q32_UPD:
2729 case ARM::VST4d8_UPD:
2730 case ARM::VST4d16_UPD:
2731 case ARM::VST4d32_UPD:
2732 case ARM::VST4q8_UPD:
2733 case ARM::VST4q16_UPD:
2734 case ARM::VST4q32_UPD:
2751 else if (Rm != 0xF) {
2756 case ARM::VST1d8wb_fixed:
2757 case ARM::VST1d16wb_fixed:
2758 case ARM::VST1d32wb_fixed:
2759 case ARM::VST1d64wb_fixed:
2760 case ARM::VST1q8wb_fixed:
2761 case ARM::VST1q16wb_fixed:
2762 case ARM::VST1q32wb_fixed:
2763 case ARM::VST1q64wb_fixed:
2764 case ARM::VST1d8Twb_fixed:
2765 case ARM::VST1d16Twb_fixed:
2766 case ARM::VST1d32Twb_fixed:
2767 case ARM::VST1d64Twb_fixed:
2768 case ARM::VST1d8Qwb_fixed:
2769 case ARM::VST1d16Qwb_fixed:
2770 case ARM::VST1d32Qwb_fixed:
2771 case ARM::VST1d64Qwb_fixed:
2772 case ARM::VST2d8wb_fixed:
2773 case ARM::VST2d16wb_fixed:
2774 case ARM::VST2d32wb_fixed:
2775 case ARM::VST2q8wb_fixed:
2776 case ARM::VST2q16wb_fixed:
2777 case ARM::VST2q32wb_fixed:
2778 case ARM::VST2b8wb_fixed:
2779 case ARM::VST2b16wb_fixed:
2780 case ARM::VST2b32wb_fixed:
2791 case ARM::VST1q16wb_fixed:
2792 case ARM::VST1q16wb_register:
2793 case ARM::VST1q32wb_fixed:
2794 case ARM::VST1q32wb_register:
2795 case ARM::VST1q64wb_fixed:
2796 case ARM::VST1q64wb_register:
2797 case ARM::VST1q8wb_fixed:
2798 case ARM::VST1q8wb_register:
2802 case ARM::VST2d16wb_fixed:
2803 case ARM::VST2d16wb_register:
2804 case ARM::VST2d32wb_fixed:
2805 case ARM::VST2d32wb_register:
2806 case ARM::VST2d8wb_fixed:
2807 case ARM::VST2d8wb_register:
2814 case ARM::VST2b16wb_fixed:
2815 case ARM::VST2b16wb_register:
2816 case ARM::VST2b32wb_fixed:
2817 case ARM::VST2b32wb_register:
2818 case ARM::VST2b8wb_fixed:
2819 case ARM::VST2b8wb_register:
2833 case ARM::VST3d8_UPD:
2834 case ARM::VST3d16_UPD:
2835 case ARM::VST3d32_UPD:
2839 case ARM::VST4d8_UPD:
2840 case ARM::VST4d16_UPD:
2841 case ARM::VST4d32_UPD:
2848 case ARM::VST3q8_UPD:
2849 case ARM::VST3q16_UPD:
2850 case ARM::VST3q32_UPD:
2854 case ARM::VST4q8_UPD:
2855 case ARM::VST4q16_UPD:
2856 case ARM::VST4q32_UPD:
2869 case ARM::VST3d8_UPD:
2870 case ARM::VST3d16_UPD:
2871 case ARM::VST3d32_UPD:
2875 case ARM::VST4d8_UPD:
2876 case ARM::VST4d16_UPD:
2877 case ARM::VST4d32_UPD:
2884 case ARM::VST3q8_UPD:
2885 case ARM::VST3q16_UPD:
2886 case ARM::VST3q32_UPD:
2890 case ARM::VST4q8_UPD:
2891 case ARM::VST4q16_UPD:
2892 case ARM::VST4q32_UPD:
2905 case ARM::VST4d8_UPD:
2906 case ARM::VST4d16_UPD:
2907 case ARM::VST4d32_UPD:
2914 case ARM::VST4q8_UPD:
2915 case ARM::VST4q16_UPD:
2916 case ARM::VST4q32_UPD:
2928 uint64_t Address,
const void *Decoder) {
2931 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2932 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2933 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2934 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2935 unsigned align = fieldFromInstruction(Insn, 4, 1);
2936 unsigned size = fieldFromInstruction(Insn, 6, 2);
2938 if (size == 0 && align == 1)
2940 align *= (1 << size);
2943 case ARM::VLD1DUPq16:
case ARM::VLD1DUPq32:
case ARM::VLD1DUPq8:
2944 case ARM::VLD1DUPq16wb_fixed:
case ARM::VLD1DUPq16wb_register:
2945 case ARM::VLD1DUPq32wb_fixed:
case ARM::VLD1DUPq32wb_register:
2946 case ARM::VLD1DUPq8wb_fixed:
case ARM::VLD1DUPq8wb_register:
2967 if (Rm != 0xD && Rm != 0xF &&
2975 uint64_t Address,
const void *Decoder) {
2978 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2979 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2980 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2981 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2982 unsigned align = fieldFromInstruction(Insn, 4, 1);
2983 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2987 case ARM::VLD2DUPd16:
case ARM::VLD2DUPd32:
case ARM::VLD2DUPd8:
2988 case ARM::VLD2DUPd16wb_fixed:
case ARM::VLD2DUPd16wb_register:
2989 case ARM::VLD2DUPd32wb_fixed:
case ARM::VLD2DUPd32wb_register:
2990 case ARM::VLD2DUPd8wb_fixed:
case ARM::VLD2DUPd8wb_register:
2994 case ARM::VLD2DUPd16x2:
case ARM::VLD2DUPd32x2:
case ARM::VLD2DUPd8x2:
2995 case ARM::VLD2DUPd16x2wb_fixed:
case ARM::VLD2DUPd16x2wb_register:
2996 case ARM::VLD2DUPd32x2wb_fixed:
case ARM::VLD2DUPd32x2wb_register:
2997 case ARM::VLD2DUPd8x2wb_fixed:
case ARM::VLD2DUPd8x2wb_register:
3014 if (Rm != 0xD && Rm != 0xF) {
3023 uint64_t Address,
const void *Decoder) {
3026 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3027 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3028 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3029 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3030 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3049 else if (Rm != 0xF) {
3058 uint64_t Address,
const void *Decoder) {
3061 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3062 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3063 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3064 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3065 unsigned size = fieldFromInstruction(Insn, 6, 2);
3066 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3067 unsigned align = fieldFromInstruction(Insn, 4, 1);
3101 else if (Rm != 0xF) {
3111 uint64_t Address,
const void *Decoder) {
3114 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3116 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3117 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3118 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3119 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3120 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3121 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3134 case ARM::VORRiv4i16:
3135 case ARM::VORRiv2i32:
3136 case ARM::VBICiv4i16:
3137 case ARM::VBICiv2i32:
3141 case ARM::VORRiv8i16:
3142 case ARM::VORRiv4i32:
3143 case ARM::VBICiv8i16:
3144 case ARM::VBICiv4i32:
3156 uint64_t Address,
const void *Decoder) {
3159 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3160 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3161 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3162 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3163 unsigned size = fieldFromInstruction(Insn, 18, 2);
3175 uint64_t Address,
const void *Decoder) {
3181 uint64_t Address,
const void *Decoder) {
3187 uint64_t Address,
const void *Decoder) {
3193 uint64_t Address,
const void *Decoder) {
3199 uint64_t Address,
const void *Decoder) {
3202 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3203 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3204 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3205 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3206 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3207 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3208 unsigned op = fieldFromInstruction(Insn, 6, 1);
3235 uint64_t Address,
const void *Decoder) {
3238 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3239 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3259 uint64_t Address,
const void *Decoder) {
3261 true, 2, Inst, Decoder))
3267 uint64_t Address,
const void *Decoder) {
3269 true, 4, Inst, Decoder))
3275 uint64_t Address,
const void *Decoder) {
3277 true, 2, Inst, Decoder))
3283 uint64_t Address,
const void *Decoder) {
3286 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3287 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3298 uint64_t Address,
const void *Decoder) {
3301 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3302 unsigned imm = fieldFromInstruction(Val, 3, 5);
3312 uint64_t Address,
const void *Decoder) {
3313 unsigned imm = Val << 2;
3322 uint64_t Address,
const void *Decoder) {
3330 uint64_t Address,
const void *Decoder) {
3333 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3334 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3335 unsigned imm = fieldFromInstruction(Val, 0, 2);
3358 uint64_t Address,
const void *Decoder) {
3361 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3362 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3365 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3367 bool hasMP = featureBits[ARM::FeatureMP];
3368 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3422 if (!hasV7Ops || !hasMP)
3430 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3431 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3432 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3440 uint64_t Address,
const void* Decoder) {
3443 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3444 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3445 unsigned U = fieldFromInstruction(Insn, 9, 1);
3446 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3449 unsigned add = fieldFromInstruction(Insn, 9, 1);
3452 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3454 bool hasMP = featureBits[ARM::FeatureMP];
3455 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3465 case ARM::t2LDRSBi8:
3471 case ARM::t2LDRSHi8:
3488 case ARM::t2LDRSHi8:
3494 case ARM::t2LDRSBi8:
3510 if (!hasV7Ops || !hasMP)
3524 uint64_t Address,
const void* Decoder) {
3527 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3528 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3529 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3533 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3535 bool hasMP = featureBits[ARM::FeatureMP];
3536 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3543 case ARM::t2LDRHi12:
3546 case ARM::t2LDRSHi12:
3549 case ARM::t2LDRBi12:
3552 case ARM::t2LDRSBi12:
3569 case ARM::t2LDRSHi12:
3571 case ARM::t2LDRHi12:
3574 case ARM::t2LDRSBi12:
3589 case ARM::t2PLDWi12:
3590 if (!hasV7Ops || !hasMP)
3604 uint64_t Address,
const void* Decoder) {
3607 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3608 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3609 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3643 uint64_t Address,
const void* Decoder) {
3646 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3647 unsigned U = fieldFromInstruction(Insn, 23, 1);
3648 int imm = fieldFromInstruction(Insn, 0, 12);
3651 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3653 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3657 case ARM::t2LDRBpci:
3658 case ARM::t2LDRHpci:
3661 case ARM::t2LDRSBpci:
3664 case ARM::t2LDRSHpci:
3696 uint64_t Address,
const void *Decoder) {
3700 int imm = Val & 0xFF;
3702 if (!(Val & 0x100)) imm *= -1;
3710 uint64_t Address,
const void *Decoder) {
3713 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3714 unsigned imm = fieldFromInstruction(Val, 0, 9);
3725 uint64_t Address,
const void *Decoder) {
3728 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3729 unsigned imm = fieldFromInstruction(Val, 0, 8);
3740 uint64_t Address,
const void *Decoder) {
3741 int imm = Val & 0xFF;
3744 else if (!(Val & 0x100))
3753 uint64_t Address,
const void *Decoder) {
3756 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3757 unsigned imm = fieldFromInstruction(Val, 0, 9);
3799 uint64_t Address,
const void *Decoder) {
3802 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3803 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3804 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3805 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3807 unsigned load = fieldFromInstruction(Insn, 20, 1);
3811 case ARM::t2LDR_PRE:
3812 case ARM::t2LDR_POST:
3815 case ARM::t2LDRB_PRE:
3816 case ARM::t2LDRB_POST:
3819 case ARM::t2LDRH_PRE:
3820 case ARM::t2LDRH_POST:
3823 case ARM::t2LDRSB_PRE:
3824 case ARM::t2LDRSB_POST:
3830 case ARM::t2LDRSH_PRE:
3831 case ARM::t2LDRSH_POST:
3860 uint64_t Address,
const void *Decoder) {
3863 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3864 unsigned imm = fieldFromInstruction(Val, 0, 12);
3869 case ARM::t2STRBi12:
3870 case ARM::t2STRHi12:
3886 uint64_t Address,
const void *Decoder) {
3887 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3897 uint64_t Address,
const void *Decoder) {
3901 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3902 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3909 }
else if (Inst.
getOpcode() == ARM::tADDspr) {
3910 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3922 uint64_t Address,
const void *Decoder) {
3923 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3924 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3933 uint64_t Address,
const void *Decoder) {
3935 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3936 unsigned add = fieldFromInstruction(Insn, 4, 1);
3946 uint64_t Address,
const void *Decoder) {
3954 unsigned S = (Val >> 23) & 1;
3955 unsigned J1 = (Val >> 22) & 1;
3956 unsigned J2 = (Val >> 21) & 1;
3957 unsigned I1 = !(J1 ^ S);
3958 unsigned I2 = !(J2 ^ S);
3959 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3960 int imm32 = SignExtend32<25>(tmp << 1);
3963 (Address & ~2u) + imm32 + 4,
3964 true, 4, Inst, Decoder))
3970 uint64_t Address,
const void *Decoder) {
3971 if (Val == 0xA || Val == 0xB)
3975 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3977 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3986 uint64_t Address,
const void *Decoder) {
3989 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3990 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4002 uint64_t Address,
const void *Decoder) {
4005 unsigned pred = fieldFromInstruction(Insn, 22, 4);
4006 if (pred == 0xE || pred == 0xF) {
4007 unsigned opc = fieldFromInstruction(Insn, 4, 28);
4022 unsigned imm = fieldFromInstruction(Insn, 0, 4);
4026 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
4027 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
4028 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
4029 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
4030 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4044 uint64_t Address,
const void *Decoder) {
4045 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4047 unsigned byte = fieldFromInstruction(Val, 8, 2);
4048 unsigned imm = fieldFromInstruction(Val, 0, 8);
4065 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4066 unsigned rot = fieldFromInstruction(Val, 7, 5);
4067 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4076 uint64_t Address,
const void *Decoder){
4078 true, 2, Inst, Decoder))
4084 uint64_t Address,
const void *Decoder){
4092 unsigned S = (Val >> 23) & 1;
4093 unsigned J1 = (Val >> 22) & 1;
4094 unsigned J2 = (Val >> 21) & 1;
4095 unsigned I1 = !(J1 ^ S);
4096 unsigned I2 = !(J2 ^ S);
4097 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4098 int imm32 = SignExtend32<25>(tmp << 1);
4101 true, 4, Inst, Decoder))
4107 uint64_t Address,
const void *Decoder) {
4116 uint64_t Address,
const void *Decoder) {
4125 uint64_t Address,
const void *Decoder) {
4128 ((
const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4130 if (FeatureBits[ARM::FeatureMClass]) {
4131 unsigned ValLow = Val & 0xff;
4150 if (!(FeatureBits[ARM::HasV7Ops]))
4159 if (!(FeatureBits[ARM::HasV8MMainlineOps]))
4169 if (!(FeatureBits[ARM::Feature8MSecExt]))
4177 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4178 if (!(FeatureBits[ARM::HasV7Ops])) {
4191 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4192 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4206 uint64_t Address,
const void *Decoder) {
4208 unsigned R = fieldFromInstruction(Val, 5, 1);
4209 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4215 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4216 SysM == 0x1a || SysM == 0x1b)
4219 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4220 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4229 uint64_t Address,
const void *Decoder) {
4232 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4233 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4234 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4250 uint64_t Address,
const void *Decoder){
4253 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4254 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4255 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4256 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4261 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4275 uint64_t Address,
const void *Decoder) {
4278 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4279 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4280 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4281 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4282 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4283 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4300 uint64_t Address,
const void *Decoder) {
4303 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4304 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4305 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4306 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4307 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4308 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4309 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4328 uint64_t Address,
const void *Decoder) {
4331 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4332 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4333 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4334 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4335 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4336 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4353 uint64_t Address,
const void *Decoder) {
4356 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4357 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4358 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4359 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4360 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4361 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4378 uint64_t Address,
const void *Decoder) {
4381 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4382 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4383 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4384 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4385 unsigned size = fieldFromInstruction(Insn, 10, 2);
4393 if (fieldFromInstruction(Insn, 4, 1))
4395 index = fieldFromInstruction(Insn, 5, 3);
4398 if (fieldFromInstruction(Insn, 5, 1))
4400 index = fieldFromInstruction(Insn, 6, 2);
4401 if (fieldFromInstruction(Insn, 4, 1))
4405 if (fieldFromInstruction(Insn, 6, 1))
4407 index = fieldFromInstruction(Insn, 7, 1);
4409 switch (fieldFromInstruction(Insn, 4, 2)) {
4445 uint64_t Address,
const void *Decoder) {
4448 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4449 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4450 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4451 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4452 unsigned size = fieldFromInstruction(Insn, 10, 2);
4460 if (fieldFromInstruction(Insn, 4, 1))
4462 index = fieldFromInstruction(Insn, 5, 3);
4465 if (fieldFromInstruction(Insn, 5, 1))
4467 index = fieldFromInstruction(Insn, 6, 2);
4468 if (fieldFromInstruction(Insn, 4, 1))
4472 if (fieldFromInstruction(Insn, 6, 1))
4474 index = fieldFromInstruction(Insn, 7, 1);
4476 switch (fieldFromInstruction(Insn, 4, 2)) {
4511 uint64_t Address,
const void *Decoder) {
4514 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4515 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4516 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4517 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4518 unsigned size = fieldFromInstruction(Insn, 10, 2);
4527 index = fieldFromInstruction(Insn, 5, 3);
4528 if (fieldFromInstruction(Insn, 4, 1))
4532 index = fieldFromInstruction(Insn, 6, 2);
4533 if (fieldFromInstruction(Insn, 4, 1))
4535 if (fieldFromInstruction(Insn, 5, 1))
4539 if (fieldFromInstruction(Insn, 5, 1))
4541 index = fieldFromInstruction(Insn, 7, 1);
4542 if (fieldFromInstruction(Insn, 4, 1) != 0)
4544 if (fieldFromInstruction(Insn, 6, 1))
4578 uint64_t Address,
const void *Decoder) {
4581 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4582 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4583 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4584 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4585 unsigned size = fieldFromInstruction(Insn, 10, 2);
4594 index = fieldFromInstruction(Insn, 5, 3);
4595 if (fieldFromInstruction(Insn, 4, 1))
4599 index = fieldFromInstruction(Insn, 6, 2);
4600 if (fieldFromInstruction(Insn, 4, 1))
4602 if (fieldFromInstruction(Insn, 5, 1))
4606 if (fieldFromInstruction(Insn, 5, 1))
4608 index = fieldFromInstruction(Insn, 7, 1);
4609 if (fieldFromInstruction(Insn, 4, 1) != 0)
4611 if (fieldFromInstruction(Insn, 6, 1))
4642 uint64_t Address,
const void *Decoder) {
4645 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4646 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4647 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4648 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4649 unsigned size = fieldFromInstruction(Insn, 10, 2);
4658 if (fieldFromInstruction(Insn, 4, 1))
4660 index = fieldFromInstruction(Insn, 5, 3);
4663 if (fieldFromInstruction(Insn, 4, 1))
4665 index = fieldFromInstruction(Insn, 6, 2);
4666 if (fieldFromInstruction(Insn, 5, 1))
4670 if (fieldFromInstruction(Insn, 4, 2))
4672 index = fieldFromInstruction(Insn, 7, 1);
4673 if (fieldFromInstruction(Insn, 6, 1))
4712 uint64_t Address,
const void *Decoder) {
4715 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4716 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4717 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4718 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4719 unsigned size = fieldFromInstruction(Insn, 10, 2);
4728 if (fieldFromInstruction(Insn, 4, 1))
4730 index = fieldFromInstruction(Insn, 5, 3);
4733 if (fieldFromInstruction(Insn, 4, 1))
4735 index = fieldFromInstruction(Insn, 6, 2);
4736 if (fieldFromInstruction(Insn, 5, 1))
4740 if (fieldFromInstruction(Insn, 4, 2))
4742 index = fieldFromInstruction(Insn, 7, 1);
4743 if (fieldFromInstruction(Insn, 6, 1))
4776 uint64_t Address,
const void *Decoder) {
4779 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4780 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4781 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4782 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4783 unsigned size = fieldFromInstruction(Insn, 10, 2);
4792 if (fieldFromInstruction(Insn, 4, 1))
4794 index = fieldFromInstruction(Insn, 5, 3);
4797 if (fieldFromInstruction(Insn, 4, 1))
4799 index = fieldFromInstruction(Insn, 6, 2);
4800 if (fieldFromInstruction(Insn, 5, 1))
4804 switch (fieldFromInstruction(Insn, 4, 2)) {
4810 align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
4813 index = fieldFromInstruction(Insn, 7, 1);
4814 if (fieldFromInstruction(Insn, 6, 1))
4857 uint64_t Address,
const void *Decoder) {
4860 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4861 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4862 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4863 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4864 unsigned size = fieldFromInstruction(Insn, 10, 2);
4873 if (fieldFromInstruction(Insn, 4, 1))
4875 index = fieldFromInstruction(Insn, 5, 3);
4878 if (fieldFromInstruction(Insn, 4, 1))
4880 index = fieldFromInstruction(Insn, 6, 2);
4881 if (fieldFromInstruction(Insn, 5, 1))
4885 switch (fieldFromInstruction(Insn, 4, 2)) {
4891 align = 4 << fieldFromInstruction(Insn, 4, 2);
break;
4894 index = fieldFromInstruction(Insn, 7, 1);
4895 if (fieldFromInstruction(Insn, 6, 1))
4929 uint64_t Address,
const void *Decoder) {
4931 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4932 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4933 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4934 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4935 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4937 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4955 uint64_t Address,
const void *Decoder) {
4957 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4958 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4959 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4960 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4961 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4963 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4981 uint64_t Address,
const void *Decoder) {
4983 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4984 unsigned mask = fieldFromInstruction(Insn, 0, 4);
5001 uint64_t Address,
const void *Decoder) {
5004 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5005 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5006 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5007 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5008 unsigned W = fieldFromInstruction(Insn, 21, 1);
5009 unsigned U = fieldFromInstruction(Insn, 23, 1);
5010 unsigned P = fieldFromInstruction(Insn, 24, 1);
5011 bool writeback = (W == 1) | (P == 0);
5013 addr |= (U << 8) | (Rn << 9);
5015 if (writeback && (Rn == Rt || Rn == Rt2))
5038 uint64_t Address,
const void *Decoder) {
5041 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5042 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
5043 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5044 unsigned addr = fieldFromInstruction(Insn, 0, 8);
5045 unsigned W = fieldFromInstruction(Insn, 21, 1);
5046 unsigned U = fieldFromInstruction(Insn, 23, 1);
5047 unsigned P = fieldFromInstruction(Insn, 24, 1);
5048 bool writeback = (W == 1) | (P == 0);
5050 addr |= (U << 8) | (Rn << 9);
5052 if (writeback && (Rn == Rt || Rn == Rt2))
5072 uint64_t Address,
const void *Decoder) {
5073 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5074 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5077 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5078 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5079 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5088 const void *Decoder) {
5098 uint64_t Address,
const void *Decoder) {
5099 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5100 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5101 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5102 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5109 if (Rt == Rn || Rn == Rt2)
5125 uint64_t Address,
const void *Decoder) {
5127 ((
const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5128 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5130 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5131 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5132 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5133 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5134 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5135 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5136 unsigned op = fieldFromInstruction(Insn, 5, 1);
5141 if (!(imm & 0x38)) {
5184 uint64_t Address,
const void *Decoder) {
5186 ((
const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5187 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5189 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5190 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5191 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5192 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5193 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5194 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5195 unsigned op = fieldFromInstruction(Insn, 5, 1);
5200 if (!(imm & 0x38)) {
5243 uint64_t Address,
const void *Decoder) {
5246 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5247 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5248 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5249 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5250 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5252 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5270 uint64_t Address,
const void *Decoder) {
5274 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5275 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5276 unsigned cop = fieldFromInstruction(Val, 8, 4);
5277 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5278 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5280 if ((cop & ~0x1) == 0xa)
static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCDisassembler * createARMDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static const uint16_t GPRPairDecoderTable[]
static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCDisassembler * createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
DecodeStatus
Ternary decode status.
static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Superclass for all disassemblers.
static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Describe properties that are true of each instruction in the target description file.
static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
getAM5Opc - This function encodes the addrmode5 opc field.
static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t GPRDecoderTable[]
static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
opt Optimize addressing mode
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
MCDisassembler::DecodeStatus DecodeStatus
Target & getTheThumbLETarget()
static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCOperand createReg(unsigned Reg)
static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static bool Check(DecodeStatus &Out, DecodeStatus In)
static const uint16_t DPairSpacedDecoderTable[]
const MCInstrDesc ARMInsts[]
static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Target & getTheARMBETarget()
Context object for machine code objects.
static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
unsigned getReg() const
Returns the register number.
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
Target & getTheThumbBETarget()
static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static bool add(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
This function adds the integer array x to the integer array Y and places the result in dest...
static const uint16_t SPRDecoderTable[]
static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
size_t size() const
size - Get the array size.
iterator insert(iterator I, const MCOperand &Op)
static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
Instances of this class represent a single low-level machine instruction.
static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
unsigned short NumOperands
static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCSubtargetInfo & getSubtargetInfo() const
static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t DPRDecoderTable[]
static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static const uint16_t DPairDecoderTable[]
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static const uint16_t QPRDecoderTable[]
static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, uint64_t Address, raw_ostream &OS, raw_ostream &CS, uint32_t Insn, DecodeStatus Result)
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setOpcode(unsigned Op)
static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Promote Memory to Register
static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Adddress, const void *Decoder)
static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static void AddThumb1SBit(MCInst &MI, bool InITBlock)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
void LLVMInitializeARMDisassembler()
static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
unsigned getOpcode() const
Target - Wrapper for Target specific information.
static unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset)
getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
MCSubtargetInfo - Generic base class for all target subtargets.
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, uint64_t Address, const void *Decoder)
LLVM Value Representation.
static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
const MCOperandInfo * OpInfo
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
This class implements an extremely fast bulk output stream that can only output to a stream...
static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
void addOperand(const MCOperand &Op)
static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, const void *Decoder)
tryAddingPcLoadReferenceComment - trys to add a comment as to what is being referenced by a load inst...
static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
Target & getTheARMLETarget()
This holds information about one operand of a machine instruction, indicating the register class for ...
static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder)
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static MCOperand createImm(int64_t Val)
static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)
static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder)
const MCOperand & getOperand(unsigned i) const
static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, bool isBranch, uint64_t InstSize, MCInst &MI, const void *Decoder)
tryAddingSymbolicOperand - trys to add a symbolic operand in place of the immediate Value in the MCIn...
static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder)