LLVM  4.0.0
InstructionSelector.cpp
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1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the InstructionSelector class.
11 //===----------------------------------------------------------------------===//
12 
19 
20 #define DEBUG_TYPE "instructionselector"
21 
22 using namespace llvm;
23 
25 
28  const RegisterBankInfo &RBI) const {
30  MachineFunction &MF = *MBB.getParent();
32 
33  for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
34  MachineOperand &MO = I.getOperand(OpI);
35 
36  // There's nothing to be done on non-register operands.
37  if (!MO.isReg())
38  continue;
39 
40  DEBUG(dbgs() << "Converting operand: " << MO << '\n');
41  assert(MO.isReg() && "Unsupported non-reg operand");
42 
43  unsigned Reg = MO.getReg();
44  // Physical registers don't need to be constrained.
45  if (TRI.isPhysicalRegister(Reg))
46  continue;
47 
48  // Register operands with a value of 0 (e.g. predicate operands) don't need
49  // to be constrained.
50  if (Reg == 0)
51  continue;
52 
53  // If the operand is a vreg, we should constrain its regclass, and only
54  // insert COPYs if that's impossible.
55  // constrainOperandRegClass does that for us.
56  MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
57  Reg, OpI));
58  }
59  return true;
60 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
Holds all the information related to register banks.
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
MachineBasicBlock * MBB
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:100