25 #define GET_INSTRINFO_CTOR_DTOR
26 #define GET_INSTRMAP_INFO
27 #include "AMDGPUGenInstrInfo.inc"
30 void AMDGPUInstrInfo::anchor() {}
46 int64_t Offset0, int64_t Offset1,
47 unsigned NumLoads)
const {
48 assert(Offset1 > Offset0 &&
49 "Second offset should be larger than first offset!");
54 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
59 default:
return Opcode;
60 case 1:
return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
61 case 2:
return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
62 case 3:
return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
78 return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
111 if (MCOp == (uint16_t)-1)
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Cha...
static SIEncodingFamily subtargetEncodingFamily(const AMDGPUSubtarget &ST)
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
AMDGPUInstrInfo(const AMDGPUSubtarget &st)
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
static int getMCOpcode(uint16_t Opcode, unsigned Gen)
TargetRegisterInfo interface that is implemented by all hw codegen targets.
Generation getGeneration() const
The AMDGPU TargetMachine interface definition for hw codgen targets.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Represents one node in the SelectionDAG.
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())