LLVM  4.0.0
HexagonAsmBackend.cpp
Go to the documentation of this file.
1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "Hexagon.h"
11 #include "HexagonFixupKinds.h"
12 #include "HexagonMCTargetDesc.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAsmLayout.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectWriter.h"
26 #include "llvm/Support/Debug.h"
28 
29 #include <sstream>
30 
31 using namespace llvm;
32 using namespace Hexagon;
33 
34 #define DEBUG_TYPE "hexagon-asm-backend"
35 
37  ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
38 
39 namespace {
40 
41 class HexagonAsmBackend : public MCAsmBackend {
42  uint8_t OSABI;
43  StringRef CPU;
44  mutable uint64_t relaxedCnt;
45  std::unique_ptr <MCInstrInfo> MCII;
46  std::unique_ptr <MCInst *> RelaxTarget;
47  MCInst * Extender;
48 
49  void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
50  MCInst &HMB) const {
52  SmallString<256> Code;
53  raw_svector_ostream VecOS(Code);
54  E.encodeInstruction(HMB, VecOS, Fixups, RF.getSubtargetInfo());
55 
56  // Update the fragment.
57  RF.setInst(HMB);
58  RF.getContents() = Code;
59  RF.getFixups() = Fixups;
60  }
61 public:
62  HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) :
63  OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *),
64  Extender(nullptr) {}
65 
66  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
67  return createHexagonELFObjectWriter(OS, OSABI, CPU);
68  }
69 
70  void setExtender(MCContext &Context) const {
71  if (Extender == nullptr)
72  const_cast<HexagonAsmBackend *>(this)->Extender = new (Context) MCInst;
73  }
74 
75  MCInst *takeExtender() const {
76  assert(Extender != nullptr);
77  MCInst * Result = Extender;
78  const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
79  return Result;
80  }
81 
82  unsigned getNumFixupKinds() const override {
84  }
85 
86  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
87  const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
88  // This table *must* be in same the order of fixup_* kinds in
89  // HexagonFixupKinds.h.
90  //
91  // namei offset bits flags
92  { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
93  { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
94  { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
95  { "fixup_Hexagon_LO16", 0, 32, 0 },
96  { "fixup_Hexagon_HI16", 0, 32, 0 },
97  { "fixup_Hexagon_32", 0, 32, 0 },
98  { "fixup_Hexagon_16", 0, 32, 0 },
99  { "fixup_Hexagon_8", 0, 32, 0 },
100  { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
101  { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
102  { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
103  { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
104  { "fixup_Hexagon_HL16", 0, 32, 0 },
105  { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
106  { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
107  { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
108  { "fixup_Hexagon_32_6_X", 0, 32, 0 },
109  { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110  { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
111  { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
112  { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113  { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
114  { "fixup_Hexagon_16_X", 0, 32, 0 },
115  { "fixup_Hexagon_12_X", 0, 32, 0 },
116  { "fixup_Hexagon_11_X", 0, 32, 0 },
117  { "fixup_Hexagon_10_X", 0, 32, 0 },
118  { "fixup_Hexagon_9_X", 0, 32, 0 },
119  { "fixup_Hexagon_8_X", 0, 32, 0 },
120  { "fixup_Hexagon_7_X", 0, 32, 0 },
121  { "fixup_Hexagon_6_X", 0, 32, 0 },
122  { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
123  { "fixup_Hexagon_COPY", 0, 32, 0 },
124  { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
125  { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
126  { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
127  { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
128  { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
129  { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
130  { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
131  { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
132  { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
133  { "fixup_Hexagon_GOT_32", 0, 32, 0 },
134  { "fixup_Hexagon_GOT_16", 0, 32, 0 },
135  { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
136  { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
137  { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
138  { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
139  { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
140  { "fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
141  { "fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
142  { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
143  { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
144  { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
145  { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
146  { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
147  { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
148  { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
149  { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
150  { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
151  { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
152  { "fixup_Hexagon_IE_32", 0, 32, 0 },
153  { "fixup_Hexagon_IE_16", 0, 32, 0 },
154  { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
155  { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
156  { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
157  { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
158  { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
159  { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
160  { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
161  { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
162  { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
163  { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
164  { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
165  { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
166  { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
167  { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
168  { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
169  { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
170  { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
171  { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
172  { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
173  { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
174  { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
175  { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
176  { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
177  { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
178  { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
179  { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
180  { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
181  { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
182  { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
183  { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
184  { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
185  { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }
186  };
187 
188  if (Kind < FirstTargetFixupKind)
189  return MCAsmBackend::getFixupKindInfo(Kind);
190 
191  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
192  "Invalid kind!");
193  return Infos[Kind - FirstTargetFixupKind];
194  }
195 
196  /// processFixupValue - Target hook to adjust the literal value of a fixup
197  /// if necessary. IsResolved signals whether the caller believes a relocation
198  /// is needed; the target can modify the value. The default does nothing.
199  void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
200  const MCFixup &Fixup, const MCFragment *DF,
201  const MCValue &Target, uint64_t &Value,
202  bool &IsResolved) override {
203  MCFixupKind Kind = Fixup.getKind();
204 
205  switch((unsigned)Kind) {
206  default:
207  llvm_unreachable("Unknown Fixup Kind!");
208 
209  case fixup_Hexagon_LO16:
210  case fixup_Hexagon_HI16:
211  case fixup_Hexagon_16:
212  case fixup_Hexagon_8:
217  case fixup_Hexagon_HL16:
219  case fixup_Hexagon_16_X:
220  case fixup_Hexagon_12_X:
221  case fixup_Hexagon_11_X:
222  case fixup_Hexagon_10_X:
223  case fixup_Hexagon_9_X:
224  case fixup_Hexagon_8_X:
225  case fixup_Hexagon_7_X:
226  case fixup_Hexagon_6_X:
227  case fixup_Hexagon_COPY:
256  case fixup_Hexagon_IE_32:
257  case fixup_Hexagon_IE_16:
292  // These relocations should always have a relocation recorded
293  IsResolved = false;
294  return;
295 
297  //IsResolved = false;
298  break;
299 
310  if (DisableFixup)
311  IsResolved = false;
312  break;
313 
314  case FK_Data_1:
315  case FK_Data_2:
316  case FK_Data_4:
317  case FK_PCRel_4:
318  case fixup_Hexagon_32:
319  // Leave these relocations alone as they are used for EH.
320  return;
321  }
322  }
323 
324  /// getFixupKindNumBytes - The number of bytes the fixup may change.
325  static unsigned getFixupKindNumBytes(unsigned Kind) {
326  switch (Kind) {
327  default:
328  return 0;
329 
330  case FK_Data_1:
331  return 1;
332  case FK_Data_2:
333  return 2;
334  case FK_Data_4: // this later gets mapped to R_HEX_32
335  case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
336  case fixup_Hexagon_32:
348  return 4;
349  }
350  }
351 
352  // Make up for left shift when encoding the operand.
353  static uint64_t adjustFixupValue(MCFixupKind Kind, uint64_t Value) {
354  switch((unsigned)Kind) {
355  default:
356  break;
357 
363  Value >>= 2;
364  break;
365 
371  Value &= 0x3f;
372  break;
373 
375  Value >>= 6;
376  break;
377  }
378  return (Value);
379  }
380 
381  void HandleFixupError(const int bits, const int align_bits,
382  const int64_t FixupValue, const char *fixupStr) const {
383  // Error: value 1124 out of range: -1024-1023 when resolving
384  // symbol in file xprtsock.S
385  const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
386  const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
387  std::stringstream errStr;
388  errStr << "\nError: value " <<
389  FixupValue <<
390  " out of range: " <<
391  IntMin.getSExtValue() <<
392  "-" <<
393  IntMax.getSExtValue() <<
394  " when resolving " <<
395  fixupStr <<
396  " fixup\n";
397  llvm_unreachable(errStr.str().c_str());
398  }
399 
400  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
401  /// data fragment, at the offset specified by the fixup and following the
402  /// fixup kind as appropriate.
403  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
404  uint64_t FixupValue, bool IsPCRel) const override {
405 
406  // When FixupValue is 0 the relocation is external and there
407  // is nothing for us to do.
408  if (!FixupValue) return;
409 
410  MCFixupKind Kind = Fixup.getKind();
411  uint64_t Value;
412  uint32_t InstMask;
413  uint32_t Reloc;
414 
415  // LLVM gives us an encoded value, we have to convert it back
416  // to a real offset before we can use it.
417  uint32_t Offset = Fixup.getOffset();
418  unsigned NumBytes = getFixupKindNumBytes(Kind);
419  assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
420  char *InstAddr = Data + Offset;
421 
422  Value = adjustFixupValue(Kind, FixupValue);
423  if(!Value)
424  return;
425  int sValue = (int)Value;
426 
427  switch((unsigned)Kind) {
428  default:
429  return;
430 
432  if (!(isIntN(7, sValue)))
433  HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
435  InstMask = 0x00001f18; // Word32_B7
436  Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
437  ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
438  break;
439 
441  if (!(isIntN(9, sValue)))
442  HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
444  InstMask = 0x003000fe; // Word32_B9
445  Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
446  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
447  break;
448 
449  // Since the existing branches that use this relocation cannot be
450  // extended, they should only be fixed up if the target is within range.
452  if (!(isIntN(13, sValue)))
453  HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
455  InstMask = 0x00202ffe; // Word32_B13
456  Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
457  (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
458  ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
459  break;
460 
462  if (!(isIntN(15, sValue)))
463  HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
465  InstMask = 0x00df20fe; // Word32_B15
466  Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
467  (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
468  (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
469  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
470  break;
471 
473  if (!(isIntN(22, sValue)))
474  HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
476  InstMask = 0x01ff3ffe; // Word32_B22
477  Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
478  ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
479  break;
480 
482  InstMask = 0x0fff3fff; // Word32_X26
483  Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
484  (Value & 0x3fff); // Value 13-0 = Target 13-0
485  break;
486 
487  case FK_Data_1:
488  case FK_Data_2:
489  case FK_Data_4:
490  case fixup_Hexagon_32:
491  InstMask = 0xffffffff; // Word32
492  Reloc = Value;
493  break;
494  }
495 
496  DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "(" <<
497  (unsigned)Kind << ")\n");
498  DEBUG(uint32_t OldData = 0;
499  for (unsigned i = 0; i < NumBytes; i++)
500  OldData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
501  dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) <<
502  ": AValue=0x"; dbgs().write_hex(FixupValue) <<
503  ": Offset=" << Offset <<
504  ": Size=" << DataSize <<
505  ": OInst=0x"; dbgs().write_hex(OldData) <<
506  ": Reloc=0x"; dbgs().write_hex(Reloc););
507 
508  // For each byte of the fragment that the fixup touches, mask in the
509  // bits from the fixup value. The Value has been "split up" into the
510  // appropriate bitfields above.
511  for (unsigned i = 0; i < NumBytes; i++){
512  InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
513  InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
514  }
515 
516  DEBUG(uint32_t NewData = 0;
517  for (unsigned i = 0; i < NumBytes; i++)
518  NewData |= (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
519  dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
520  }
521 
522  bool isInstRelaxable(MCInst const &HMI) const {
523  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
524  bool Relaxable = false;
525  // Branches and loop-setup insns are handled as necessary by relaxation.
527  (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
529  MCID.isBranch()) ||
531  MCID.isBranch()) ||
533  HMI.getOpcode() != Hexagon::C4_addipc))
534  if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
535  Relaxable = true;
536  MCOperand const &Operand =
539  Relaxable = false;
540  }
541 
542  return Relaxable;
543  }
544 
545  /// MayNeedRelaxation - Check whether the given instruction may need
546  /// relaxation.
547  ///
548  /// \param Inst - The instruction to test.
549  bool mayNeedRelaxation(MCInst const &Inst) const override {
550  return true;
551  }
552 
553  /// fixupNeedsRelaxation - Target specific predicate for whether a given
554  /// fixup requires the associated instruction to be relaxed.
555  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
556  uint64_t Value,
557  const MCRelaxableFragment *DF,
558  const MCAsmLayout &Layout) const override {
559  MCInst const &MCB = DF->getInst();
561 
562  *RelaxTarget = nullptr;
563  MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
564  MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
565  bool Relaxable = isInstRelaxable(MCI);
566  if (Relaxable == false)
567  return false;
568  // If we cannot resolve the fixup value, it requires relaxation.
569  if (!Resolved) {
570  switch ((unsigned)Fixup.getKind()) {
572  // GetFixupCount assumes B22 won't relax
574  default:
575  return false;
576  break;
580  case fixup_Hexagon_B7_PCREL: {
582  ++relaxedCnt;
583  *RelaxTarget = &MCI;
584  setExtender(Layout.getAssembler().getContext());
585  return true;
586  } else {
587  return false;
588  }
589  break;
590  }
591  }
592  }
593 
594  MCFixupKind Kind = Fixup.getKind();
595  int64_t sValue = Value;
596  int64_t maxValue;
597 
598  switch ((unsigned)Kind) {
600  maxValue = 1 << 8;
601  break;
603  maxValue = 1 << 10;
604  break;
606  maxValue = 1 << 16;
607  break;
609  maxValue = 1 << 23;
610  break;
611  default:
612  maxValue = INT64_MAX;
613  break;
614  }
615 
616  bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
617 
618  if (isFarAway) {
620  ++relaxedCnt;
621  *RelaxTarget = &MCI;
622  setExtender(Layout.getAssembler().getContext());
623  return true;
624  }
625  }
626 
627  return false;
628  }
629 
630  /// Simple predicate for targets where !Resolved implies requiring relaxation
631  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
632  const MCRelaxableFragment *DF,
633  const MCAsmLayout &Layout) const override {
634  llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
635  }
636 
637  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
638  MCInst &Res) const override {
640  "Hexagon relaxInstruction only works on bundles");
641 
643  // Copy the results into the bundle.
644  bool Update = false;
645  for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
646  MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
647 
648  // if immediate extender needed, add it in
649  if (*RelaxTarget == &CrntHMI) {
650  Update = true;
652  "No room to insert extender for relaxation");
653 
654  MCInst *HMIx = takeExtender();
656  *MCII, CrntHMI,
659  *RelaxTarget = nullptr;
660  }
661  // now copy over the original instruction(the one we may have extended)
662  Res.addOperand(MCOperand::createInst(I.getInst()));
663  }
664  (void)Update;
665  assert(Update && "Didn't find relaxation target");
666  }
667 
668  bool writeNopData(uint64_t Count,
669  MCObjectWriter * OW) const override {
670  static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
671  ParseIn = 0x00004000, // In packet parse-bits.
672  ParseEnd = 0x0000c000; // End of packet parse-bits.
673 
674  while(Count % HEXAGON_INSTR_SIZE) {
675  DEBUG(dbgs() << "Alignment not a multiple of the instruction size:" <<
676  Count % HEXAGON_INSTR_SIZE << "/" << HEXAGON_INSTR_SIZE << "\n");
677  --Count;
678  OW->write8(0);
679  }
680 
681  while(Count) {
682  Count -= HEXAGON_INSTR_SIZE;
683  // Close the packet whenever a multiple of the maximum packet size remains
684  uint32_t ParseBits = (Count % (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE))?
685  ParseIn: ParseEnd;
686  OW->write32(Nopcode | ParseBits);
687  }
688  return true;
689  }
690 
691  void finishLayout(MCAssembler const &Asm,
692  MCAsmLayout &Layout) const override {
693  for (auto I : Layout.getSectionOrder()) {
694  auto &Fragments = I->getFragmentList();
695  for (auto &J : Fragments) {
696  switch (J.getKind()) {
697  default:
698  break;
699  case MCFragment::FT_Align: {
700  auto Size = Asm.computeFragmentSize(Layout, J);
701  for (auto K = J.getIterator();
702  K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
703  --K;
704  switch (K->getKind()) {
705  default:
706  break;
707  case MCFragment::FT_Align: {
708  // Don't pad before other alignments
709  Size = 0;
710  break;
711  }
713  auto &RF = cast<MCRelaxableFragment>(*K);
714  auto &Inst = const_cast<MCInst &>(RF.getInst());
715  while (Size > 0 && HexagonMCInstrInfo::bundleSize(Inst) < 4) {
716  MCInst *Nop = new (Asm.getContext()) MCInst;
717  Nop->setOpcode(Hexagon::A2_nop);
719  Size -= 4;
720  if (!HexagonMCChecker(
721  *MCII, RF.getSubtargetInfo(), Inst, Inst,
722  *Asm.getContext().getRegisterInfo()).check()) {
723  Inst.erase(Inst.end() - 1);
724  Size = 0;
725  }
726  }
727  bool Error = HexagonMCShuffle(*MCII, RF.getSubtargetInfo(), Inst);
728  //assert(!Error);
729  (void)Error;
730  ReplaceInstruction(Asm.getEmitter(), RF, Inst);
731  Layout.invalidateFragmentsFrom(&RF);
732  Size = 0; // Only look back one instruction
733  break;
734  }
735  }
736  }
737  }
738  }
739  }
740  }
741  }
742 };
743 } // end anonymous namespace
744 
745 namespace llvm {
747  MCRegisterInfo const & /*MRI*/,
748  const Triple &TT, StringRef CPU,
749  const MCTargetOptions &Options) {
750  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
751  return new HexagonAsmBackend(T, OSABI, CPU);
752 }
753 }
static MCInstrInfo * createMCInstrInfo()
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:279
LLVMContext & Context
size_t i
This represents an "assembler immediate".
Definition: MCValue.h:40
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isBundle(MCInst const &MCI)
MCCodeEmitter & getEmitter() const
Definition: MCAssembler.h:262
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:490
demanded bits
const MCSubtargetInfo & getSubtargetInfo()
Definition: MCFragment.h:266
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
MCContext & getContext() const
Definition: MCAssembler.h:258
Defines the object file and target independent interfaces used by the assembler backend to write nati...
void write8(uint8_t Value)
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:431
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:66
const MCInst & getInst() const
Definition: MCFragment.h:263
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
MCInst const & instruction(MCInst const &MCB, size_t Index)
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:29
#define HEXAGON_PACKET_SIZE
Definition: Hexagon.h:33
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:261
A four-byte fixup.
Definition: MCFixup.h:26
Context object for machine code objects.
Definition: MCContext.h:51
static cl::opt< bool > DisableFixup("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"))
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
SmallVectorImpl< char > & getContents()
Definition: MCFragment.h:175
uint32_t getOffset() const
Definition: MCFixup.h:95
MCObjectWriter * createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:249
const MCExpr * getExpr() const
Definition: MCInst.h:93
void write32(uint32_t Value)
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
uint64_t computeFragmentSize(const MCAsmLayout &Layout, const MCFragment &F) const
Compute the effective fragment size assuming it is laid out at the given SectionAddress and FragmentO...
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1321
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
Definition: MCFragment.cpp:52
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
SmallVectorImpl< MCFixup > & getFixups()
Definition: MCFragment.h:200
uint32_t Offset
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
Definition: MCAsmLayout.h:66
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
Definition for classes that emit Hexagon machine code from MCInsts.
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:366
MCFixupKind getKind() const
Definition: MCFixup.h:93
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:24
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void setOpcode(unsigned Op)
Definition: MCInst.h:158
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
A four-byte pc relative fixup.
Definition: MCFixup.h:30
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:77
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:135
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:245
#define I(x, y, z)
Definition: MD5.cpp:54
MCSubtargetInfo - Generic base class for all target subtargets.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
Target independent information on a fixup kind.
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:333
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:441
#define HEXAGON_INSTR_SIZE
Definition: Hexagon.h:30
LLVM Value Representation.
Definition: Value.h:71
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
Lightweight error class with error context and mandatory checking.
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:51
Check for a valid bundle.
#define DEBUG(X)
Definition: Debug.h:100
MCAsmBackend * createHexagonAsmBackend(Target const &T, MCRegisterInfo const &, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
bool mustNotExtend(MCExpr const &Expr)
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
A two-byte fixup.
Definition: MCFixup.h:25
void setInst(const MCInst &Value)
Definition: MCFragment.h:264
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164