LLVM  4.0.0
HexagonVLIWPacketizer.cpp
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1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
17 //
18 //===----------------------------------------------------------------------===//
19 #include "HexagonRegisterInfo.h"
20 #include "HexagonSubtarget.h"
21 #include "HexagonTargetMachine.h"
22 #include "HexagonVLIWPacketizer.h"
28 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/Support/Debug.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "packets"
35 
36 static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
37  cl::ZeroOrMore, cl::init(false),
38  cl::desc("Disable Hexagon packetizer pass"));
39 
40 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
42  cl::desc("Allow non-solo packetization of volatile memory references"));
43 
44 static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false),
45  cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"));
46 
47 static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores",
49  cl::desc("Disable vector double new-value-stores"));
50 
52 
53 namespace llvm {
56 }
57 
58 
59 namespace {
60  class HexagonPacketizer : public MachineFunctionPass {
61  public:
62  static char ID;
63  HexagonPacketizer() : MachineFunctionPass(ID) {
65  }
66 
67  void getAnalysisUsage(AnalysisUsage &AU) const override {
68  AU.setPreservesCFG();
76  }
77  StringRef getPassName() const override { return "Hexagon Packetizer"; }
78  bool runOnMachineFunction(MachineFunction &Fn) override;
79  MachineFunctionProperties getRequiredProperties() const override {
82  }
83 
84  private:
85  const HexagonInstrInfo *HII;
86  const HexagonRegisterInfo *HRI;
87  };
88 
89  char HexagonPacketizer::ID = 0;
90 }
91 
92 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
93  false, false)
98 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
99  false, false)
100 
102  MachineLoopInfo &MLI, AliasAnalysis *AA,
104  : VLIWPacketizerList(MF, MLI, AA), MBPI(MBPI), MLI(&MLI) {
105  HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
106  HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
107 
108  addMutation(make_unique<HexagonSubtarget::HexagonDAGMutation>());
109 }
110 
111 // Check if FirstI modifies a register that SecondI reads.
112 static bool hasWriteToReadDep(const MachineInstr &FirstI,
113  const MachineInstr &SecondI,
114  const TargetRegisterInfo *TRI) {
115  for (auto &MO : FirstI.operands()) {
116  if (!MO.isReg() || !MO.isDef())
117  continue;
118  unsigned R = MO.getReg();
119  if (SecondI.readsRegister(R, TRI))
120  return true;
121  }
122  return false;
123 }
124 
125 
127  MachineBasicBlock::iterator BundleIt, bool Before) {
129  if (Before)
130  InsertPt = BundleIt.getInstrIterator();
131  else
132  InsertPt = std::next(BundleIt).getInstrIterator();
133 
134  MachineBasicBlock &B = *MI.getParent();
135  // The instruction should at least be bundled with the preceding instruction
136  // (there will always be one, i.e. BUNDLE, if nothing else).
138  if (MI.isBundledWithSucc()) {
141  } else {
142  // If it's not bundled with the successor (i.e. it is the last one
143  // in the bundle), then we can simply unbundle it from the predecessor,
144  // which will take care of updating the predecessor's flag.
145  MI.unbundleFromPred();
146  }
147  B.splice(InsertPt, &B, MI.getIterator());
148 
149  // Get the size of the bundle without asserting.
152  unsigned Size = 0;
153  for (++I; I != E && I->isBundledWithPred(); ++I)
154  ++Size;
155 
156  // If there are still two or more instructions, then there is nothing
157  // else to be done.
158  if (Size > 1)
159  return BundleIt;
160 
161  // Otherwise, extract the single instruction out and delete the bundle.
162  MachineBasicBlock::iterator NextIt = std::next(BundleIt);
163  MachineInstr &SingleI = *BundleIt->getNextNode();
164  SingleI.unbundleFromPred();
165  assert(!SingleI.isBundledWithSucc());
166  BundleIt->eraseFromParent();
167  return NextIt;
168 }
169 
170 
171 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) {
172  if (DisablePacketizer || skipFunction(*MF.getFunction()))
173  return false;
174 
175  HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
176  HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
177  auto &MLI = getAnalysis<MachineLoopInfo>();
178  auto *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
179  auto *MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
180 
182  HII->genAllInsnTimingClasses(MF);
183 
184  // Instantiate the packetizer.
185  HexagonPacketizerList Packetizer(MF, MLI, AA, MBPI);
186 
187  // DFA state table should not be empty.
188  assert(Packetizer.getResourceTracker() && "Empty DFA table!");
189 
190  //
191  // Loop over all basic blocks and remove KILL pseudo-instructions
192  // These instructions confuse the dependence analysis. Consider:
193  // D0 = ... (Insn 0)
194  // R0 = KILL R0, D0 (Insn 1)
195  // R0 = ... (Insn 2)
196  // Here, Insn 1 will result in the dependence graph not emitting an output
197  // dependence between Insn 0 and Insn 2. This can lead to incorrect
198  // packetization
199  //
200  for (auto &MB : MF) {
201  auto End = MB.end();
202  auto MI = MB.begin();
203  while (MI != End) {
204  auto NextI = std::next(MI);
205  if (MI->isKill()) {
206  MB.erase(MI);
207  End = MB.end();
208  }
209  MI = NextI;
210  }
211  }
212 
213  // Loop over all of the basic blocks.
214  for (auto &MB : MF) {
215  auto Begin = MB.begin(), End = MB.end();
216  while (Begin != End) {
217  // First the first non-boundary starting from the end of the last
218  // scheduling region.
219  MachineBasicBlock::iterator RB = Begin;
220  while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
221  ++RB;
222  // First the first boundary starting from the beginning of the new
223  // region.
225  while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
226  ++RE;
227  // Add the scheduling boundary if it's not block end.
228  if (RE != End)
229  ++RE;
230  // If RB == End, then RE == End.
231  if (RB != End)
232  Packetizer.PacketizeMIs(&MB, RB, RE);
233 
234  Begin = RE;
235  }
236  }
237 
238  Packetizer.unpacketizeSoloInstrs(MF);
239  return true;
240 }
241 
242 
243 // Reserve resources for a constant extender. Trigger an assertion if the
244 // reservation fails.
247  llvm_unreachable("Resources not available");
248 }
249 
251  return tryAllocateResourcesForConstExt(false);
252 }
253 
254 // Allocate resources (i.e. 4 bytes) for constant extender. If succeeded,
255 // return true, otherwise, return false.
257  auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
258  bool Avail = ResourceTracker->canReserveResources(*ExtMI);
259  if (Reserve && Avail)
261  MF.DeleteMachineInstr(ExtMI);
262  return Avail;
263 }
264 
265 
267  SDep::Kind DepType, unsigned DepReg) {
268  // Check for LR dependence.
269  if (DepReg == HRI->getRARegister())
270  return true;
271 
272  if (HII->isDeallocRet(MI))
273  if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
274  return true;
275 
276  // Check if this is a predicate dependence.
277  const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg);
278  if (RC == &Hexagon::PredRegsRegClass)
279  return true;
280 
281  // Assumes that the first operand of the CALLr is the function address.
282  if (HII->isIndirectCall(MI) && (DepType == SDep::Data)) {
283  const MachineOperand MO = MI.getOperand(0);
284  if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg))
285  return true;
286  }
287 
288  if (HII->isJumpR(MI)) {
289  const MachineOperand &MO = HII->isPredicated(MI) ? MI.getOperand(1)
290  : MI.getOperand(0);
291  assert(MO.isReg() && MO.isUse());
292  if (MO.getReg() == DepReg)
293  return true;
294  }
295  return false;
296 }
297 
298 static bool isRegDependence(const SDep::Kind DepType) {
299  return DepType == SDep::Data || DepType == SDep::Anti ||
300  DepType == SDep::Output;
301 }
302 
303 static bool isDirectJump(const MachineInstr &MI) {
304  return MI.getOpcode() == Hexagon::J2_jump;
305 }
306 
307 static bool isSchedBarrier(const MachineInstr &MI) {
308  switch (MI.getOpcode()) {
309  case Hexagon::Y2_barrier:
310  return true;
311  }
312  return false;
313 }
314 
315 static bool isControlFlow(const MachineInstr &MI) {
316  return MI.getDesc().isTerminator() || MI.getDesc().isCall();
317 }
318 
319 
320 /// Returns true if the instruction modifies a callee-saved register.
322  const TargetRegisterInfo *TRI) {
323  const MachineFunction &MF = *MI.getParent()->getParent();
324  for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
325  if (MI.modifiesRegister(*CSR, TRI))
326  return true;
327  return false;
328 }
329 
330 // Returns true if an instruction can be promoted to .new predicate or
331 // new-value store.
333  const TargetRegisterClass *NewRC) {
334  // Vector stores can be predicated, and can be new-value stores, but
335  // they cannot be predicated on a .new predicate value.
336  if (NewRC == &Hexagon::PredRegsRegClass)
337  if (HII->isV60VectorInstruction(MI) && MI.mayStore())
338  return false;
339  return HII->isCondInst(MI) || HII->isJumpR(MI) || MI.isReturn() ||
340  HII->mayBeNewStore(MI);
341 }
342 
343 // Promote an instructiont to its .cur form.
344 // At this time, we have already made a call to canPromoteToDotCur and made
345 // sure that it can *indeed* be promoted.
348  const TargetRegisterClass* RC) {
349  assert(DepType == SDep::Data);
350  int CurOpcode = HII->getDotCurOp(MI);
351  MI.setDesc(HII->get(CurOpcode));
352  return true;
353 }
354 
356  MachineInstr *MI = nullptr;
357  for (auto BI : CurrentPacketMIs) {
358  DEBUG(dbgs() << "Cleanup packet has "; BI->dump(););
359  if (BI->getOpcode() == Hexagon::V6_vL32b_cur_ai) {
360  MI = BI;
361  continue;
362  }
363  if (MI) {
364  for (auto &MO : BI->operands())
365  if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
366  return;
367  }
368  }
369  if (!MI)
370  return;
371  // We did not find a use of the CUR, so de-cur it.
372  MI->setDesc(HII->get(Hexagon::V6_vL32b_ai));
373  DEBUG(dbgs() << "Demoted CUR "; MI->dump(););
374 }
375 
376 // Check to see if an instruction can be dot cur.
378  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
379  const TargetRegisterClass *RC) {
380  if (!HII->isV60VectorInstruction(MI))
381  return false;
382  if (!HII->isV60VectorInstruction(*MII))
383  return false;
384 
385  // Already a dot new instruction.
386  if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
387  return false;
388 
389  if (!HII->mayBeCurLoad(MI))
390  return false;
391 
392  // The "cur value" cannot come from inline asm.
393  if (PacketSU->getInstr()->isInlineAsm())
394  return false;
395 
396  // Make sure candidate instruction uses cur.
397  DEBUG(dbgs() << "Can we DOT Cur Vector MI\n";
398  MI.dump();
399  dbgs() << "in packet\n";);
400  MachineInstr &MJ = *MII;
401  DEBUG({
402  dbgs() << "Checking CUR against ";
403  MJ.dump();
404  });
405  unsigned DestReg = MI.getOperand(0).getReg();
406  bool FoundMatch = false;
407  for (auto &MO : MJ.operands())
408  if (MO.isReg() && MO.getReg() == DestReg)
409  FoundMatch = true;
410  if (!FoundMatch)
411  return false;
412 
413  // Check for existing uses of a vector register within the packet which
414  // would be affected by converting a vector load into .cur formt.
415  for (auto BI : CurrentPacketMIs) {
416  DEBUG(dbgs() << "packet has "; BI->dump(););
417  if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
418  return false;
419  }
420 
421  DEBUG(dbgs() << "Can Dot CUR MI\n"; MI.dump(););
422  // We can convert the opcode into a .cur.
423  return true;
424 }
425 
426 // Promote an instruction to its .new form. At this time, we have already
427 // made a call to canPromoteToDotNew and made sure that it can *indeed* be
428 // promoted.
431  const TargetRegisterClass* RC) {
432  assert (DepType == SDep::Data);
433  int NewOpcode;
434  if (RC == &Hexagon::PredRegsRegClass)
435  NewOpcode = HII->getDotNewPredOp(MI, MBPI);
436  else
437  NewOpcode = HII->getDotNewOp(MI);
438  MI.setDesc(HII->get(NewOpcode));
439  return true;
440 }
441 
443  int NewOpcode = HII->getDotOldOp(MI.getOpcode());
444  MI.setDesc(HII->get(NewOpcode));
445  return true;
446 }
447 
449  unsigned Opc = MI.getOpcode();
450  switch (Opc) {
451  case Hexagon::S2_storerd_io:
452  case Hexagon::S2_storeri_io:
453  case Hexagon::S2_storerh_io:
454  case Hexagon::S2_storerb_io:
455  break;
456  default:
457  llvm_unreachable("Unexpected instruction");
458  }
459  unsigned FrameSize = MF.getFrameInfo().getStackSize();
460  MachineOperand &Off = MI.getOperand(1);
461  int64_t NewOff = Off.getImm() - (FrameSize + HEXAGON_LRFP_SIZE);
462  if (HII->isValidOffset(Opc, NewOff)) {
463  Off.setImm(NewOff);
464  return true;
465  }
466  return false;
467 }
468 
470  unsigned Opc = MI.getOpcode();
471  switch (Opc) {
472  case Hexagon::S2_storerd_io:
473  case Hexagon::S2_storeri_io:
474  case Hexagon::S2_storerh_io:
475  case Hexagon::S2_storerb_io:
476  break;
477  default:
478  llvm_unreachable("Unexpected instruction");
479  }
480  unsigned FrameSize = MF.getFrameInfo().getStackSize();
481  MachineOperand &Off = MI.getOperand(1);
482  Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
483 }
484 
489 };
490 
491 /// Returns true if an instruction is predicated on p0 and false if it's
492 /// predicated on !p0.
494  const HexagonInstrInfo *HII) {
495  if (!HII->isPredicated(MI))
496  return PK_Unknown;
497  if (HII->isPredicatedTrue(MI))
498  return PK_True;
499  return PK_False;
500 }
501 
503  const HexagonInstrInfo *HII) {
504  assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
505 #ifndef NDEBUG
506  // Post Increment means duplicates. Use dense map to find duplicates in the
507  // list. Caution: Densemap initializes with the minimum of 64 buckets,
508  // whereas there are at most 5 operands in the post increment.
509  DenseSet<unsigned> DefRegsSet;
510  for (auto &MO : MI.operands())
511  if (MO.isReg() && MO.isDef())
512  DefRegsSet.insert(MO.getReg());
513 
514  for (auto &MO : MI.operands())
515  if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
516  return MO;
517 #else
518  if (MI.mayLoad()) {
519  const MachineOperand &Op1 = MI.getOperand(1);
520  // The 2nd operand is always the post increment operand in load.
521  assert(Op1.isReg() && "Post increment operand has be to a register.");
522  return Op1;
523  }
524  if (MI.getDesc().mayStore()) {
525  const MachineOperand &Op0 = MI.getOperand(0);
526  // The 1st operand is always the post increment operand in store.
527  assert(Op0.isReg() && "Post increment operand has be to a register.");
528  return Op0;
529  }
530 #endif
531  // we should never come here.
532  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
533 }
534 
535 // Get the value being stored.
537  // value being stored is always the last operand.
538  return MI.getOperand(MI.getNumOperands()-1);
539 }
540 
541 static bool isLoadAbsSet(const MachineInstr &MI) {
542  unsigned Opc = MI.getOpcode();
543  switch (Opc) {
544  case Hexagon::L4_loadrd_ap:
545  case Hexagon::L4_loadrb_ap:
546  case Hexagon::L4_loadrh_ap:
547  case Hexagon::L4_loadrub_ap:
548  case Hexagon::L4_loadruh_ap:
549  case Hexagon::L4_loadri_ap:
550  return true;
551  }
552  return false;
553 }
554 
556  assert(isLoadAbsSet(MI));
557  return MI.getOperand(1);
558 }
559 
560 
561 // Can be new value store?
562 // Following restrictions are to be respected in convert a store into
563 // a new value store.
564 // 1. If an instruction uses auto-increment, its address register cannot
565 // be a new-value register. Arch Spec 5.4.2.1
566 // 2. If an instruction uses absolute-set addressing mode, its address
567 // register cannot be a new-value register. Arch Spec 5.4.2.1.
568 // 3. If an instruction produces a 64-bit result, its registers cannot be used
569 // as new-value registers. Arch Spec 5.4.2.2.
570 // 4. If the instruction that sets the new-value register is conditional, then
571 // the instruction that uses the new-value register must also be conditional,
572 // and both must always have their predicates evaluate identically.
573 // Arch Spec 5.4.2.3.
574 // 5. There is an implied restriction that a packet cannot have another store,
575 // if there is a new value store in the packet. Corollary: if there is
576 // already a store in a packet, there can not be a new value store.
577 // Arch Spec: 3.4.4.2
579  const MachineInstr &PacketMI, unsigned DepReg) {
580  // Make sure we are looking at the store, that can be promoted.
581  if (!HII->mayBeNewStore(MI))
582  return false;
583 
584  // Make sure there is dependency and can be new value'd.
585  const MachineOperand &Val = getStoreValueOperand(MI);
586  if (Val.isReg() && Val.getReg() != DepReg)
587  return false;
588 
589  const MCInstrDesc& MCID = PacketMI.getDesc();
590 
591  // First operand is always the result.
592  const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
593  // Double regs can not feed into new value store: PRM section: 5.4.2.2.
594  if (PacketRC == &Hexagon::DoubleRegsRegClass)
595  return false;
596 
597  // New-value stores are of class NV (slot 0), dual stores require class ST
598  // in slot 0 (PRM 5.5).
599  for (auto I : CurrentPacketMIs) {
600  SUnit *PacketSU = MIToSUnit.find(I)->second;
601  if (PacketSU->getInstr()->mayStore())
602  return false;
603  }
604 
605  // Make sure it's NOT the post increment register that we are going to
606  // new value.
607  if (HII->isPostIncrement(MI) &&
608  getPostIncrementOperand(MI, HII).getReg() == DepReg) {
609  return false;
610  }
611 
612  if (HII->isPostIncrement(PacketMI) && PacketMI.mayLoad() &&
613  getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
614  // If source is post_inc, or absolute-set addressing, it can not feed
615  // into new value store
616  // r3 = memw(r2++#4)
617  // memw(r30 + #-1404) = r2.new -> can not be new value store
618  // arch spec section: 5.4.2.1.
619  return false;
620  }
621 
622  if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
623  return false;
624 
625  // If the source that feeds the store is predicated, new value store must
626  // also be predicated.
627  if (HII->isPredicated(PacketMI)) {
628  if (!HII->isPredicated(MI))
629  return false;
630 
631  // Check to make sure that they both will have their predicates
632  // evaluate identically.
633  unsigned predRegNumSrc = 0;
634  unsigned predRegNumDst = 0;
635  const TargetRegisterClass* predRegClass = nullptr;
636 
637  // Get predicate register used in the source instruction.
638  for (auto &MO : PacketMI.operands()) {
639  if (!MO.isReg())
640  continue;
641  predRegNumSrc = MO.getReg();
642  predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
643  if (predRegClass == &Hexagon::PredRegsRegClass)
644  break;
645  }
646  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
647  "predicate register not found in a predicated PacketMI instruction");
648 
649  // Get predicate register used in new-value store instruction.
650  for (auto &MO : MI.operands()) {
651  if (!MO.isReg())
652  continue;
653  predRegNumDst = MO.getReg();
654  predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst);
655  if (predRegClass == &Hexagon::PredRegsRegClass)
656  break;
657  }
658  assert((predRegClass == &Hexagon::PredRegsRegClass) &&
659  "predicate register not found in a predicated MI instruction");
660 
661  // New-value register producer and user (store) need to satisfy these
662  // constraints:
663  // 1) Both instructions should be predicated on the same register.
664  // 2) If producer of the new-value register is .new predicated then store
665  // should also be .new predicated and if producer is not .new predicated
666  // then store should not be .new predicated.
667  // 3) Both new-value register producer and user should have same predicate
668  // sense, i.e, either both should be negated or both should be non-negated.
669  if (predRegNumDst != predRegNumSrc ||
670  HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
671  getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
672  return false;
673  }
674 
675  // Make sure that other than the new-value register no other store instruction
676  // register has been modified in the same packet. Predicate registers can be
677  // modified by they should not be modified between the producer and the store
678  // instruction as it will make them both conditional on different values.
679  // We already know this to be true for all the instructions before and
680  // including PacketMI. Howerver, we need to perform the check for the
681  // remaining instructions in the packet.
682 
683  unsigned StartCheck = 0;
684 
685  for (auto I : CurrentPacketMIs) {
686  SUnit *TempSU = MIToSUnit.find(I)->second;
687  MachineInstr &TempMI = *TempSU->getInstr();
688 
689  // Following condition is true for all the instructions until PacketMI is
690  // reached (StartCheck is set to 0 before the for loop).
691  // StartCheck flag is 1 for all the instructions after PacketMI.
692  if (&TempMI != &PacketMI && !StartCheck) // Start processing only after
693  continue; // encountering PacketMI.
694 
695  StartCheck = 1;
696  if (&TempMI == &PacketMI) // We don't want to check PacketMI for dependence.
697  continue;
698 
699  for (auto &MO : MI.operands())
700  if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
701  return false;
702  }
703 
704  // Make sure that for non-POST_INC stores:
705  // 1. The only use of reg is DepReg and no other registers.
706  // This handles V4 base+index registers.
707  // The following store can not be dot new.
708  // Eg. r0 = add(r0, #3)
709  // memw(r1+r0<<#2) = r0
710  if (!HII->isPostIncrement(MI)) {
711  for (unsigned opNum = 0; opNum < MI.getNumOperands()-1; opNum++) {
712  const MachineOperand &MO = MI.getOperand(opNum);
713  if (MO.isReg() && MO.getReg() == DepReg)
714  return false;
715  }
716  }
717 
718  // If data definition is because of implicit definition of the register,
719  // do not newify the store. Eg.
720  // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
721  // S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
722  for (auto &MO : PacketMI.operands()) {
723  if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
724  continue;
725  unsigned R = MO.getReg();
726  if (R == DepReg || HRI->isSuperRegister(DepReg, R))
727  return false;
728  }
729 
730  // Handle imp-use of super reg case. There is a target independent side
731  // change that should prevent this situation but I am handling it for
732  // just-in-case. For example, we cannot newify R2 in the following case:
733  // %R3<def> = A2_tfrsi 0;
734  // S2_storeri_io %R0<kill>, 0, %R2<kill>, %D1<imp-use,kill>;
735  for (auto &MO : MI.operands()) {
736  if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
737  return false;
738  }
739 
740  // Can be dot new store.
741  return true;
742 }
743 
744 // Can this MI to promoted to either new value store or new value jump.
746  const SUnit *PacketSU, unsigned DepReg,
748  if (!HII->mayBeNewStore(MI))
749  return false;
750 
751  // Check to see the store can be new value'ed.
752  MachineInstr &PacketMI = *PacketSU->getInstr();
753  if (canPromoteToNewValueStore(MI, PacketMI, DepReg))
754  return true;
755 
756  // Check to see the compare/jump can be new value'ed.
757  // This is done as a pass on its own. Don't need to check it here.
758  return false;
759 }
760 
761 static bool isImplicitDependency(const MachineInstr &I, unsigned DepReg) {
762  for (auto &MO : I.operands())
763  if (MO.isReg() && MO.isDef() && (MO.getReg() == DepReg) && MO.isImplicit())
764  return true;
765  return false;
766 }
767 
768 // Check to see if an instruction can be dot new
769 // There are three kinds.
770 // 1. dot new on predicate - V2/V3/V4
771 // 2. dot new on stores NV/ST - V4
772 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
774  const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
775  const TargetRegisterClass* RC) {
776  // Already a dot new instruction.
777  if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
778  return false;
779 
780  if (!isNewifiable(MI, RC))
781  return false;
782 
783  const MachineInstr &PI = *PacketSU->getInstr();
784 
785  // The "new value" cannot come from inline asm.
786  if (PI.isInlineAsm())
787  return false;
788 
789  // IMPLICIT_DEFs won't materialize as real instructions, so .new makes no
790  // sense.
791  if (PI.isImplicitDef())
792  return false;
793 
794  // If dependency is trough an implicitly defined register, we should not
795  // newify the use.
796  if (isImplicitDependency(PI, DepReg))
797  return false;
798 
799  const MCInstrDesc& MCID = PI.getDesc();
800  const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
801  if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass)
802  return false;
803 
804  // predicate .new
805  if (RC == &Hexagon::PredRegsRegClass)
806  if (HII->isCondInst(MI) || HII->isJumpR(MI) || MI.isReturn())
807  return HII->predCanBeUsedAsDotNew(PI, DepReg);
808 
809  if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
810  return false;
811 
812  // Create a dot new machine instruction to see if resources can be
813  // allocated. If not, bail out now.
814  int NewOpcode = HII->getDotNewOp(MI);
815  const MCInstrDesc &D = HII->get(NewOpcode);
816  MachineInstr *NewMI = MF.CreateMachineInstr(D, DebugLoc());
817  bool ResourcesAvailable = ResourceTracker->canReserveResources(*NewMI);
818  MF.DeleteMachineInstr(NewMI);
819  if (!ResourcesAvailable)
820  return false;
821 
822  // New Value Store only. New Value Jump generated as a separate pass.
823  if (!canPromoteToNewValue(MI, PacketSU, DepReg, MII))
824  return false;
825 
826  return true;
827 }
828 
829 // Go through the packet instructions and search for an anti dependency between
830 // them and DepReg from MI. Consider this case:
831 // Trying to add
832 // a) %R1<def> = TFRI_cdNotPt %P3, 2
833 // to this packet:
834 // {
835 // b) %P0<def> = C2_or %P3<kill>, %P0<kill>
836 // c) %P3<def> = C2_tfrrp %R23
837 // d) %R1<def> = C2_cmovenewit %P3, 4
838 // }
839 // The P3 from a) and d) will be complements after
840 // a)'s P3 is converted to .new form
841 // Anti-dep between c) and b) is irrelevant for this case
843  unsigned DepReg) {
844  SUnit *PacketSUDep = MIToSUnit.find(&MI)->second;
845 
846  for (auto I : CurrentPacketMIs) {
847  // We only care for dependencies to predicated instructions
848  if (!HII->isPredicated(*I))
849  continue;
850 
851  // Scheduling Unit for current insn in the packet
852  SUnit *PacketSU = MIToSUnit.find(I)->second;
853 
854  // Look at dependencies between current members of the packet and
855  // predicate defining instruction MI. Make sure that dependency is
856  // on the exact register we care about.
857  if (PacketSU->isSucc(PacketSUDep)) {
858  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
859  auto &Dep = PacketSU->Succs[i];
860  if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
861  Dep.getReg() == DepReg)
862  return true;
863  }
864  }
865  }
866 
867  return false;
868 }
869 
870 
871 /// Gets the predicate register of a predicated instruction.
873  const HexagonInstrInfo *QII) {
874  /// We use the following rule: The first predicate register that is a use is
875  /// the predicate register of a predicated instruction.
876  assert(QII->isPredicated(MI) && "Must be predicated instruction");
877 
878  for (auto &Op : MI.operands()) {
879  if (Op.isReg() && Op.getReg() && Op.isUse() &&
880  Hexagon::PredRegsRegClass.contains(Op.getReg()))
881  return Op.getReg();
882  }
883 
884  llvm_unreachable("Unknown instruction operand layout");
885  return 0;
886 }
887 
888 // Given two predicated instructions, this function detects whether
889 // the predicates are complements.
891  MachineInstr &MI2) {
892  // If we don't know the predicate sense of the instructions bail out early, we
893  // need it later.
894  if (getPredicateSense(MI1, HII) == PK_Unknown ||
895  getPredicateSense(MI2, HII) == PK_Unknown)
896  return false;
897 
898  // Scheduling unit for candidate.
899  SUnit *SU = MIToSUnit[&MI1];
900 
901  // One corner case deals with the following scenario:
902  // Trying to add
903  // a) %R24<def> = A2_tfrt %P0, %R25
904  // to this packet:
905  // {
906  // b) %R25<def> = A2_tfrf %P0, %R24
907  // c) %P0<def> = C2_cmpeqi %R26, 1
908  // }
909  //
910  // On general check a) and b) are complements, but presence of c) will
911  // convert a) to .new form, and then it is not a complement.
912  // We attempt to detect it by analyzing existing dependencies in the packet.
913 
914  // Analyze relationships between all existing members of the packet.
915  // Look for Anti dependecy on the same predicate reg as used in the
916  // candidate.
917  for (auto I : CurrentPacketMIs) {
918  // Scheduling Unit for current insn in the packet.
919  SUnit *PacketSU = MIToSUnit.find(I)->second;
920 
921  // If this instruction in the packet is succeeded by the candidate...
922  if (PacketSU->isSucc(SU)) {
923  for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
924  auto Dep = PacketSU->Succs[i];
925  // The corner case exist when there is true data dependency between
926  // candidate and one of current packet members, this dep is on
927  // predicate reg, and there already exist anti dep on the same pred in
928  // the packet.
929  if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
930  Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
931  // Here I know that I is predicate setting instruction with true
932  // data dep to candidate on the register we care about - c) in the
933  // above example. Now I need to see if there is an anti dependency
934  // from c) to any other instruction in the same packet on the pred
935  // reg of interest.
936  if (restrictingDepExistInPacket(*I, Dep.getReg()))
937  return false;
938  }
939  }
940  }
941  }
942 
943  // If the above case does not apply, check regular complement condition.
944  // Check that the predicate register is the same and that the predicate
945  // sense is different We also need to differentiate .old vs. .new: !p0
946  // is not complementary to p0.new.
947  unsigned PReg1 = getPredicatedRegister(MI1, HII);
948  unsigned PReg2 = getPredicatedRegister(MI2, HII);
949  return PReg1 == PReg2 &&
950  Hexagon::PredRegsRegClass.contains(PReg1) &&
951  Hexagon::PredRegsRegClass.contains(PReg2) &&
952  getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
953  HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
954 }
955 
956 // Initialize packetizer flags.
958  Dependence = false;
959  PromotedToDotNew = false;
960  GlueToNewValueJump = false;
961  GlueAllocframeStore = false;
962  FoundSequentialDependence = false;
963 }
964 
965 // Ignore bundling of pseudo instructions.
967  const MachineBasicBlock *) {
968  if (MI.isDebugValue())
969  return true;
970 
971  if (MI.isCFIInstruction())
972  return false;
973 
974  // We must print out inline assembly.
975  if (MI.isInlineAsm())
976  return false;
977 
978  if (MI.isImplicitDef())
979  return false;
980 
981  // We check if MI has any functional units mapped to it. If it doesn't,
982  // we ignore the instruction.
983  const MCInstrDesc& TID = MI.getDesc();
985  unsigned FuncUnits = IS->getUnits();
986  return !FuncUnits;
987 }
988 
990  if (MI.isEHLabel() || MI.isCFIInstruction())
991  return true;
992 
993  // Consider inline asm to not be a solo instruction by default.
994  // Inline asm will be put in a packet temporarily, but then it will be
995  // removed, and placed outside of the packet (before or after, depending
996  // on dependencies). This is to reduce the impact of inline asm as a
997  // "packet splitting" instruction.
998  if (MI.isInlineAsm() && !ScheduleInlineAsm)
999  return true;
1000 
1001  // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
1002  // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
1003  // They must not be grouped with other instructions in a packet.
1004  if (isSchedBarrier(MI))
1005  return true;
1006 
1007  if (HII->isSolo(MI))
1008  return true;
1009 
1010  if (MI.getOpcode() == Hexagon::A2_nop)
1011  return true;
1012 
1013  return false;
1014 }
1015 
1016 
1017 // Quick check if instructions MI and MJ cannot coexist in the same packet.
1018 // Limit the tests to be "one-way", e.g. "if MI->isBranch and MJ->isInlineAsm",
1019 // but not the symmetric case: "if MJ->isBranch and MI->isInlineAsm".
1020 // For full test call this function twice:
1021 // cannotCoexistAsymm(MI, MJ) || cannotCoexistAsymm(MJ, MI)
1022 // Doing the test only one way saves the amount of code in this function,
1023 // since every test would need to be repeated with the MI and MJ reversed.
1024 static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ,
1025  const HexagonInstrInfo &HII) {
1026  const MachineFunction *MF = MI.getParent()->getParent();
1028  HII.isHVXMemWithAIndirect(MI, MJ))
1029  return true;
1030 
1031  // An inline asm cannot be together with a branch, because we may not be
1032  // able to remove the asm out after packetizing (i.e. if the asm must be
1033  // moved past the bundle). Similarly, two asms cannot be together to avoid
1034  // complications when determining their relative order outside of a bundle.
1035  if (MI.isInlineAsm())
1036  return MJ.isInlineAsm() || MJ.isBranch() || MJ.isBarrier() ||
1037  MJ.isCall() || MJ.isTerminator();
1038 
1039  switch (MI.getOpcode()) {
1040  case (Hexagon::S2_storew_locked):
1041  case (Hexagon::S4_stored_locked):
1042  case (Hexagon::L2_loadw_locked):
1043  case (Hexagon::L4_loadd_locked):
1044  case (Hexagon::Y4_l2fetch): {
1045  // These instructions can only be grouped with ALU32 or non-floating-point
1046  // XTYPE instructions. Since there is no convenient way of identifying fp
1047  // XTYPE instructions, only allow grouping with ALU32 for now.
1048  unsigned TJ = HII.getType(MJ);
1049  if (TJ != HexagonII::TypeALU32)
1050  return true;
1051  break;
1052  }
1053  default:
1054  break;
1055  }
1056 
1057  // "False" really means that the quick check failed to determine if
1058  // I and J cannot coexist.
1059  return false;
1060 }
1061 
1062 
1063 // Full, symmetric check.
1065  const MachineInstr &MJ) {
1066  return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1067 }
1068 
1070  for (auto &B : MF) {
1071  MachineBasicBlock::iterator BundleIt;
1073  for (auto I = B.instr_begin(), E = B.instr_end(); I != E; I = NextI) {
1074  NextI = std::next(I);
1075  MachineInstr &MI = *I;
1076  if (MI.isBundle())
1077  BundleIt = I;
1078  if (!MI.isInsideBundle())
1079  continue;
1080 
1081  // Decide on where to insert the instruction that we are pulling out.
1082  // Debug instructions always go before the bundle, but the placement of
1083  // INLINE_ASM depends on potential dependencies. By default, try to
1084  // put it before the bundle, but if the asm writes to a register that
1085  // other instructions in the bundle read, then we need to place it
1086  // after the bundle (to preserve the bundle semantics).
1087  bool InsertBeforeBundle;
1088  if (MI.isInlineAsm())
1089  InsertBeforeBundle = !hasWriteToReadDep(MI, *BundleIt, HRI);
1090  else if (MI.isDebugValue())
1091  InsertBeforeBundle = true;
1092  else
1093  continue;
1094 
1095  BundleIt = moveInstrOut(MI, BundleIt, InsertBeforeBundle);
1096  }
1097  }
1098 }
1099 
1100 // Check if a given instruction is of class "system".
1101 static bool isSystemInstr(const MachineInstr &MI) {
1102  unsigned Opc = MI.getOpcode();
1103  switch (Opc) {
1104  case Hexagon::Y2_barrier:
1105  case Hexagon::Y2_dcfetchbo:
1106  return true;
1107  }
1108  return false;
1109 }
1110 
1112  const MachineInstr &J) {
1113  // The dependence graph may not include edges between dead definitions,
1114  // so without extra checks, we could end up packetizing two instruction
1115  // defining the same (dead) register.
1116  if (I.isCall() || J.isCall())
1117  return false;
1118  if (HII->isPredicated(I) || HII->isPredicated(J))
1119  return false;
1120 
1121  BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
1122  for (auto &MO : I.operands()) {
1123  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1124  continue;
1125  DeadDefs[MO.getReg()] = true;
1126  }
1127 
1128  for (auto &MO : J.operands()) {
1129  if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1130  continue;
1131  unsigned R = MO.getReg();
1132  if (R != Hexagon::USR_OVF && DeadDefs[R])
1133  return true;
1134  }
1135  return false;
1136 }
1137 
1139  const MachineInstr &J) {
1140  // A save callee-save register function call can only be in a packet
1141  // with instructions that don't write to the callee-save registers.
1142  if ((HII->isSaveCalleeSavedRegsCall(I) &&
1143  doesModifyCalleeSavedReg(J, HRI)) ||
1144  (HII->isSaveCalleeSavedRegsCall(J) &&
1145  doesModifyCalleeSavedReg(I, HRI)))
1146  return true;
1147 
1148  // Two control flow instructions cannot go in the same packet.
1149  if (isControlFlow(I) && isControlFlow(J))
1150  return true;
1151 
1152  // \ref-manual (7.3.4) A loop setup packet in loopN or spNloop0 cannot
1153  // contain a speculative indirect jump,
1154  // a new-value compare jump or a dealloc_return.
1155  auto isBadForLoopN = [this] (const MachineInstr &MI) -> bool {
1156  if (MI.isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1157  return true;
1158  if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
1159  return true;
1160  return false;
1161  };
1162 
1163  if (HII->isLoopN(I) && isBadForLoopN(J))
1164  return true;
1165  if (HII->isLoopN(J) && isBadForLoopN(I))
1166  return true;
1167 
1168  // dealloc_return cannot appear in the same packet as a conditional or
1169  // unconditional jump.
1170  return HII->isDeallocRet(I) &&
1171  (J.isBranch() || J.isCall() || J.isBarrier());
1172 }
1173 
1175  const MachineInstr &J) {
1176  bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J);
1177  bool StoreI = I.mayStore(), StoreJ = J.mayStore();
1178  if ((SysI && StoreJ) || (SysJ && StoreI))
1179  return true;
1180 
1181  if (StoreI && StoreJ) {
1182  if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1183  return true;
1184  } else {
1185  // A memop cannot be in the same packet with another memop or a store.
1186  // Two stores can be together, but here I and J cannot both be stores.
1187  bool MopStI = HII->isMemOp(I) || StoreI;
1188  bool MopStJ = HII->isMemOp(J) || StoreJ;
1189  if (MopStI && MopStJ)
1190  return true;
1191  }
1192 
1193  return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1194 }
1195 
1196 // SUI is the current instruction that is out side of the current packet.
1197 // SUJ is the current instruction inside the current packet against which that
1198 // SUI will be packetized.
1200  assert(SUI->getInstr() && SUJ->getInstr());
1201  MachineInstr &I = *SUI->getInstr();
1202  MachineInstr &J = *SUJ->getInstr();
1203 
1204  // Clear IgnoreDepMIs when Packet starts.
1205  if (CurrentPacketMIs.size() == 1)
1206  IgnoreDepMIs.clear();
1207 
1208  MachineBasicBlock::iterator II = I.getIterator();
1209 
1210  // Solo instructions cannot go in the packet.
1211  assert(!isSoloInstruction(I) && "Unexpected solo instr!");
1212 
1213  if (cannotCoexist(I, J))
1214  return false;
1215 
1217  if (Dependence)
1218  return false;
1219 
1220  // V4 allows dual stores. It does not allow second store, if the first
1221  // store is not in SLOT0. New value store, new value jump, dealloc_return
1222  // and memop always take SLOT0. Arch spec 3.4.4.2.
1224  if (Dependence)
1225  return false;
1226 
1227  // If an instruction feeds new value jump, glue it.
1228  MachineBasicBlock::iterator NextMII = I.getIterator();
1229  ++NextMII;
1230  if (NextMII != I.getParent()->end() && HII->isNewValueJump(*NextMII)) {
1231  MachineInstr &NextMI = *NextMII;
1232 
1233  bool secondRegMatch = false;
1234  const MachineOperand &NOp0 = NextMI.getOperand(0);
1235  const MachineOperand &NOp1 = NextMI.getOperand(1);
1236 
1237  if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1238  secondRegMatch = true;
1239 
1240  for (auto T : CurrentPacketMIs) {
1241  SUnit *PacketSU = MIToSUnit.find(T)->second;
1242  MachineInstr &PI = *PacketSU->getInstr();
1243  // NVJ can not be part of the dual jump - Arch Spec: section 7.8.
1244  if (PI.isCall()) {
1245  Dependence = true;
1246  break;
1247  }
1248  // Validate:
1249  // 1. Packet does not have a store in it.
1250  // 2. If the first operand of the nvj is newified, and the second
1251  // operand is also a reg, it (second reg) is not defined in
1252  // the same packet.
1253  // 3. If the second operand of the nvj is newified, (which means
1254  // first operand is also a reg), first reg is not defined in
1255  // the same packet.
1256  if (PI.getOpcode() == Hexagon::S2_allocframe || PI.mayStore() ||
1257  HII->isLoopN(PI)) {
1258  Dependence = true;
1259  break;
1260  }
1261  // Check #2/#3.
1262  const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1263  if (OpR.isReg() && PI.modifiesRegister(OpR.getReg(), HRI)) {
1264  Dependence = true;
1265  break;
1266  }
1267  }
1268 
1269  if (Dependence)
1270  return false;
1271  GlueToNewValueJump = true;
1272  }
1273 
1274  // There no dependency between a prolog instruction and its successor.
1275  if (!SUJ->isSucc(SUI))
1276  return true;
1277 
1278  for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1279  if (FoundSequentialDependence)
1280  break;
1281 
1282  if (SUJ->Succs[i].getSUnit() != SUI)
1283  continue;
1284 
1285  SDep::Kind DepType = SUJ->Succs[i].getKind();
1286  // For direct calls:
1287  // Ignore register dependences for call instructions for packetization
1288  // purposes except for those due to r31 and predicate registers.
1289  //
1290  // For indirect calls:
1291  // Same as direct calls + check for true dependences to the register
1292  // used in the indirect call.
1293  //
1294  // We completely ignore Order dependences for call instructions.
1295  //
1296  // For returns:
1297  // Ignore register dependences for return instructions like jumpr,
1298  // dealloc return unless we have dependencies on the explicit uses
1299  // of the registers used by jumpr (like r31) or dealloc return
1300  // (like r29 or r30).
1301  unsigned DepReg = 0;
1302  const TargetRegisterClass *RC = nullptr;
1303  if (DepType == SDep::Data) {
1304  DepReg = SUJ->Succs[i].getReg();
1305  RC = HRI->getMinimalPhysRegClass(DepReg);
1306  }
1307 
1308  if (I.isCall() || HII->isJumpR(I) || I.isReturn() || HII->isTailCall(I)) {
1309  if (!isRegDependence(DepType))
1310  continue;
1311  if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))
1312  continue;
1313  }
1314 
1315  if (DepType == SDep::Data) {
1316  if (canPromoteToDotCur(J, SUJ, DepReg, II, RC))
1317  if (promoteToDotCur(J, DepType, II, RC))
1318  continue;
1319  }
1320 
1321  // Data dpendence ok if we have load.cur.
1322  if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1323  if (HII->isV60VectorInstruction(I))
1324  continue;
1325  }
1326 
1327  // For instructions that can be promoted to dot-new, try to promote.
1328  if (DepType == SDep::Data) {
1329  if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
1330  if (promoteToDotNew(I, DepType, II, RC)) {
1331  PromotedToDotNew = true;
1332  continue;
1333  }
1334  }
1335  if (HII->isNewValueJump(I))
1336  continue;
1337  }
1338 
1339  // For predicated instructions, if the predicates are complements then
1340  // there can be no dependence.
1341  if (HII->isPredicated(I) && HII->isPredicated(J) &&
1342  arePredicatesComplements(I, J)) {
1343  // Not always safe to do this translation.
1344  // DAG Builder attempts to reduce dependence edges using transitive
1345  // nature of dependencies. Here is an example:
1346  //
1347  // r0 = tfr_pt ... (1)
1348  // r0 = tfr_pf ... (2)
1349  // r0 = tfr_pt ... (3)
1350  //
1351  // There will be an output dependence between (1)->(2) and (2)->(3).
1352  // However, there is no dependence edge between (1)->(3). This results
1353  // in all 3 instructions going in the same packet. We ignore dependce
1354  // only once to avoid this situation.
1355  auto Itr = find(IgnoreDepMIs, &J);
1356  if (Itr != IgnoreDepMIs.end()) {
1357  Dependence = true;
1358  return false;
1359  }
1360  IgnoreDepMIs.push_back(&I);
1361  continue;
1362  }
1363 
1364  // Ignore Order dependences between unconditional direct branches
1365  // and non-control-flow instructions.
1366  if (isDirectJump(I) && !J.isBranch() && !J.isCall() &&
1367  DepType == SDep::Order)
1368  continue;
1369 
1370  // Ignore all dependences for jumps except for true and output
1371  // dependences.
1372  if (I.isConditionalBranch() && DepType != SDep::Data &&
1373  DepType != SDep::Output)
1374  continue;
1375 
1376  // Ignore output dependences due to superregs. We can write to two
1377  // different subregisters of R1:0 for instance in the same cycle.
1378 
1379  // If neither I nor J defines DepReg, then this is a superfluous output
1380  // dependence. The dependence must be of the form:
1381  // R0 = ...
1382  // R1 = ...
1383  // and there is an output dependence between the two instructions with
1384  // DepReg = D0.
1385  // We want to ignore these dependences. Ideally, the dependence
1386  // constructor should annotate such dependences. We can then avoid this
1387  // relatively expensive check.
1388  //
1389  if (DepType == SDep::Output) {
1390  // DepReg is the register that's responsible for the dependence.
1391  unsigned DepReg = SUJ->Succs[i].getReg();
1392 
1393  // Check if I and J really defines DepReg.
1394  if (!I.definesRegister(DepReg) && !J.definesRegister(DepReg))
1395  continue;
1396  FoundSequentialDependence = true;
1397  break;
1398  }
1399 
1400  // For Order dependences:
1401  // 1. On V4 or later, volatile loads/stores can be packetized together,
1402  // unless other rules prevent is.
1403  // 2. Store followed by a load is not allowed.
1404  // 3. Store followed by a store is only valid on V4 or later.
1405  // 4. Load followed by any memory operation is allowed.
1406  if (DepType == SDep::Order) {
1407  if (!PacketizeVolatiles) {
1408  bool OrdRefs = I.hasOrderedMemoryRef() || J.hasOrderedMemoryRef();
1409  if (OrdRefs) {
1410  FoundSequentialDependence = true;
1411  break;
1412  }
1413  }
1414  // J is first, I is second.
1415  bool LoadJ = J.mayLoad(), StoreJ = J.mayStore();
1416  bool LoadI = I.mayLoad(), StoreI = I.mayStore();
1417  if (StoreJ) {
1418  // Two stores are only allowed on V4+. Load following store is never
1419  // allowed.
1420  if (LoadI) {
1421  FoundSequentialDependence = true;
1422  break;
1423  }
1424  } else if (!LoadJ || (!LoadI && !StoreI)) {
1425  // If J is neither load nor store, assume a dependency.
1426  // If J is a load, but I is neither, also assume a dependency.
1427  FoundSequentialDependence = true;
1428  break;
1429  }
1430  // Store followed by store: not OK on V2.
1431  // Store followed by load: not OK on all.
1432  // Load followed by store: OK on all.
1433  // Load followed by load: OK on all.
1434  continue;
1435  }
1436 
1437  // For V4, special case ALLOCFRAME. Even though there is dependency
1438  // between ALLOCFRAME and subsequent store, allow it to be packetized
1439  // in a same packet. This implies that the store is using the caller's
1440  // SP. Hence, offset needs to be updated accordingly.
1441  if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {
1442  unsigned Opc = I.getOpcode();
1443  switch (Opc) {
1444  case Hexagon::S2_storerd_io:
1445  case Hexagon::S2_storeri_io:
1446  case Hexagon::S2_storerh_io:
1447  case Hexagon::S2_storerb_io:
1448  if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1449  // Since this store is to be glued with allocframe in the same
1450  // packet, it will use SP of the previous stack frame, i.e.
1451  // caller's SP. Therefore, we need to recalculate offset
1452  // according to this change.
1453  GlueAllocframeStore = useCallersSP(I);
1454  if (GlueAllocframeStore)
1455  continue;
1456  }
1457  default:
1458  break;
1459  }
1460  }
1461 
1462  // There are certain anti-dependencies that cannot be ignored.
1463  // Specifically:
1464  // J2_call ... %R0<imp-def> ; SUJ
1465  // R0 = ... ; SUI
1466  // Those cannot be packetized together, since the call will observe
1467  // the effect of the assignment to R0.
1468  if (DepType == SDep::Anti && J.isCall()) {
1469  // Check if I defines any volatile register. We should also check
1470  // registers that the call may read, but these happen to be a
1471  // subset of the volatile register set.
1472  for (const MCPhysReg *P = J.getDesc().ImplicitDefs; P && *P; ++P) {
1473  if (!I.modifiesRegister(*P, HRI))
1474  continue;
1475  FoundSequentialDependence = true;
1476  break;
1477  }
1478  }
1479 
1480  // Skip over remaining anti-dependences. Two instructions that are
1481  // anti-dependent can share a packet, since in most such cases all
1482  // operands are read before any modifications take place.
1483  // The exceptions are branch and call instructions, since they are
1484  // executed after all other instructions have completed (at least
1485  // conceptually).
1486  if (DepType != SDep::Anti) {
1487  FoundSequentialDependence = true;
1488  break;
1489  }
1490  }
1491 
1492  if (FoundSequentialDependence) {
1493  Dependence = true;
1494  return false;
1495  }
1496 
1497  return true;
1498 }
1499 
1501  assert(SUI->getInstr() && SUJ->getInstr());
1502  MachineInstr &I = *SUI->getInstr();
1503  MachineInstr &J = *SUJ->getInstr();
1504 
1505  if (cannotCoexist(I, J))
1506  return false;
1507 
1508  if (!Dependence)
1509  return true;
1510 
1511  // Check if the instruction was promoted to a dot-new. If so, demote it
1512  // back into a dot-old.
1513  if (PromotedToDotNew)
1514  demoteToDotOld(I);
1515 
1516  cleanUpDotCur();
1517  // Check if the instruction (must be a store) was glued with an allocframe
1518  // instruction. If so, restore its offset to its original value, i.e. use
1519  // current SP instead of caller's SP.
1520  if (GlueAllocframeStore) {
1521  useCalleesSP(I);
1522  GlueAllocframeStore = false;
1523  }
1524  return false;
1525 }
1526 
1531  if (MI.isImplicitDef()) {
1532  unsigned R = MI.getOperand(0).getReg();
1533  if (Hexagon::IntRegsRegClass.contains(R)) {
1534  MCSuperRegIterator S(R, HRI, false);
1535  MI.addOperand(MachineOperand::CreateReg(*S, true, true));
1536  }
1537  return MII;
1538  }
1540 
1541  bool ExtMI = HII->isExtended(MI) || HII->isConstExtended(MI);
1542  bool Good = true;
1543 
1544  if (GlueToNewValueJump) {
1545  MachineInstr &NvjMI = *++MII;
1546  // We need to put both instructions in the same packet: MI and NvjMI.
1547  // Either of them can require a constant extender. Try to add both to
1548  // the current packet, and if that fails, end the packet and start a
1549  // new one.
1551  if (ExtMI)
1552  Good = tryAllocateResourcesForConstExt(true);
1553 
1554  bool ExtNvjMI = HII->isExtended(NvjMI) || HII->isConstExtended(NvjMI);
1555  if (Good) {
1558  else
1559  Good = false;
1560  }
1561  if (Good && ExtNvjMI)
1562  Good = tryAllocateResourcesForConstExt(true);
1563 
1564  if (!Good) {
1565  endPacket(MBB, MI);
1568  if (ExtMI) {
1571  }
1574  if (ExtNvjMI) {
1577  }
1578  }
1579  CurrentPacketMIs.push_back(&MI);
1580  CurrentPacketMIs.push_back(&NvjMI);
1581  return MII;
1582  }
1583 
1585  if (ExtMI && !tryAllocateResourcesForConstExt(true)) {
1586  endPacket(MBB, MI);
1587  if (PromotedToDotNew)
1588  demoteToDotOld(MI);
1589  if (GlueAllocframeStore) {
1590  useCalleesSP(MI);
1591  GlueAllocframeStore = false;
1592  }
1595  }
1596 
1597  CurrentPacketMIs.push_back(&MI);
1598  return MII;
1599 }
1600 
1603  OldPacketMIs = CurrentPacketMIs;
1605 }
1606 
1608  return !producesStall(MI);
1609 }
1610 
1611 
1612 // Return true when ConsMI uses a register defined by ProdMI.
1613 static bool isDependent(const MachineInstr &ProdMI,
1614  const MachineInstr &ConsMI) {
1615  if (!ProdMI.getOperand(0).isReg())
1616  return false;
1617  unsigned DstReg = ProdMI.getOperand(0).getReg();
1618 
1619  for (auto &Op : ConsMI.operands())
1620  if (Op.isReg() && Op.isUse() && Op.getReg() == DstReg)
1621  // The MIs depend on each other.
1622  return true;
1623 
1624  return false;
1625 }
1626 
1627 // V60 forward scheduling.
1629  // Check whether the previous packet is in a different loop. If this is the
1630  // case, there is little point in trying to avoid a stall because that would
1631  // favor the rare case (loop entry) over the common case (loop iteration).
1632  //
1633  // TODO: We should really be able to check all the incoming edges if this is
1634  // the first packet in a basic block, so we can avoid stalls from the loop
1635  // backedge.
1636  if (!OldPacketMIs.empty()) {
1637  auto *OldBB = OldPacketMIs.front()->getParent();
1638  auto *ThisBB = I.getParent();
1639  if (MLI->getLoopFor(OldBB) != MLI->getLoopFor(ThisBB))
1640  return false;
1641  }
1642 
1643  // Check for stall between two vector instructions.
1644  if (HII->isV60VectorInstruction(I)) {
1645  for (auto J : OldPacketMIs) {
1646  if (!HII->isV60VectorInstruction(*J))
1647  continue;
1648  if (isDependent(*J, I) && !HII->isVecUsableNextPacket(*J, I))
1649  return true;
1650  }
1651  return false;
1652  }
1653 
1654  // Check for stall between two scalar instructions. First, check that
1655  // there is no definition of a use in the current packet, because it
1656  // may be a candidate for .new.
1657  for (auto J : CurrentPacketMIs)
1658  if (!HII->isV60VectorInstruction(*J) && isDependent(*J, I))
1659  return false;
1660 
1661  // Check for stall between I and instructions in the previous packet.
1662  if (MF.getSubtarget<HexagonSubtarget>().useBSBScheduling()) {
1663  for (auto J : OldPacketMIs) {
1664  if (HII->isV60VectorInstruction(*J))
1665  continue;
1666  if (!HII->isLateInstrFeedsEarlyInstr(*J, I))
1667  continue;
1668  if (isDependent(*J, I) && !HII->canExecuteInBundle(*J, I))
1669  return true;
1670  }
1671  }
1672 
1673  return false;
1674 }
1675 
1676 
1677 //===----------------------------------------------------------------------===//
1678 // Public Constructor Functions
1679 //===----------------------------------------------------------------------===//
1680 
1682  return new HexagonPacketizer();
1683 }
bool canReserveResources(const llvm::MCInstrDesc *MID)
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:217
std::vector< MachineInstr * > CurrentPacketMIs
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool canPromoteToNewValueStore(const MachineInstr &MI, const MachineInstr &PacketMI, unsigned DepReg)
bool isIndirectCall(const MachineInstr &MI) const
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static bool hasWriteToReadDep(const MachineInstr &FirstI, const MachineInstr &SecondI, const TargetRegisterInfo *TRI)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_end()
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:448
bool isSucc(SUnit *N)
isSucc - Test if node N is a successor of this node.
Definition: ScheduleDAG.h:460
size_t i
bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, const HexagonInstrInfo &HII)
bool isNewValueInst(const MachineInstr &MI) const
Hexagon Packetizer
Implements a dense probed hash-table based set.
Definition: DenseSet.h:202
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:384
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isPredicatedTrue(const MachineInstr &MI) const
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:389
const MachineLoopInfo * MLI
bool demoteToDotOld(MachineInstr &MI)
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static cl::opt< bool > PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references"))
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
bool isMemOp(const MachineInstr &MI) const
static cl::opt< bool > DisablePacketizer("disable-packetizer", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon packetizer pass"))
bool isTailCall(const MachineInstr &MI) const override
bool isCFIInstruction() const
Definition: MachineInstr.h:770
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Kind
Kind - These are the different kinds of scheduling dependencies.
Definition: ScheduleDAG.h:48
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
return AArch64::GPR64RegClass contains(Reg)
A register anti-dependedence (aka WAR).
Definition: ScheduleDAG.h:50
bool restrictingDepExistInPacket(MachineInstr &, unsigned)
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
static cl::opt< bool > EnableGenAllInsnClass("enable-gen-insn", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC"))
std::map< MachineInstr *, SUnit * > MIToSUnit
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
bool shouldAddToPacket(const MachineInstr &MI) override
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:242
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
Regular data dependence (aka true-dependence).
Definition: ScheduleDAG.h:49
virtual void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI)
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
unsigned getUnits() const
Returns the choice of FUs.
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
Definition: MCInstrDesc.h:255
const InstrItineraryData * getInstrItins() const
bool isCondInst(const MachineInstr &MI) const
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isLoopN(const MachineInstr &MI) const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI) override
Hexagon false
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2)
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:233
static bool doesModifyCalleeSavedReg(const MachineInstr &MI, const TargetRegisterInfo *TRI)
Returns true if the instruction modifies a callee-saved register.
void unbundleFromPred()
Break bundle above this instruction.
const MachineBranchProbabilityInfo * MBPI
A handle to the branch probability pass.
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:51
static bool isControlFlow(const MachineInstr &MI)
DFAPacketizer * ResourceTracker
MachineBasicBlock * MBB
void initializeHexagonPacketizerPass(PassRegistry &)
static bool isImplicitDependency(const MachineInstr &I, unsigned DepReg)
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
int64_t getImm() const
void reserveResources(const llvm::MCInstrDesc *MID)
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
bool isJumpR(const MachineInstr &MI) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, MachineBasicBlock::iterator BundleIt, bool Before)
bool hasV60TOpsOnly() const
static unsigned getPredicatedRegister(MachineInstr &MI, const HexagonInstrInfo *QII)
Gets the predicate register of a predicated instruction.
bool isDebugValue() const
Definition: MachineInstr.h:777
bool isImplicitDef() const
Definition: MachineInstr.h:788
int getDotOldOp(const int opc) const
static const MachineOperand & getAbsSetOperand(const MachineInstr &MI)
bool isBundle() const
Definition: MachineInstr.h:804
bool isSoloInstruction(const MachineInstr &MI) override
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
#define P(N)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:420
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
static bool isSystemInstr(const MachineInstr &MI)
FunctionPass * createHexagonPacketizer()
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:168
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
Represent the analysis usage information of a pass.
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:177
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
self_iterator getIterator()
Definition: ilist_node.h:81
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:229
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
static bool isRegDependence(const SDep::Kind DepType)
bool tryAllocateResourcesForConstExt(bool Reserve)
bool isDotCurInst(const MachineInstr &MI) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isExtended(const MachineInstr &MI) const
Any other ordering dependency.
Definition: ScheduleDAG.h:52
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:895
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:865
static const MachineOperand & getPostIncrementOperand(const MachineInstr &MI, const HexagonInstrInfo *HII)
bool useBSBScheduling() const
#define HEXAGON_LRFP_SIZE
Definition: Hexagon.h:27
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:757
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:789
INITIALIZE_PASS_BEGIN(HexagonPacketizer,"packets","Hexagon Packetizer", false, false) INITIALIZE_PASS_END(HexagonPacketizer
static cl::opt< bool > DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable vector double new-value-stores"))
void dump(const TargetInstrInfo *TII=nullptr) const
bool isV60VectorInstruction(const MachineInstr &MI) const
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override
bool isPredicatedNew(const MachineInstr &MI) const
static const MachineOperand & getStoreValueOperand(const MachineInstr &MI)
bool isDeallocRet(const MachineInstr &MI) const
static bool isLoadAbsSet(const MachineInstr &MI)
static PredicateKind getPredicateSense(const MachineInstr &MI, const HexagonInstrInfo *HII)
Returns true if an instruction is predicated on p0 and false if it's predicated on !p0...
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:556
bool isDotNewInst(const MachineInstr &MI) const
static bool isSchedBarrier(const MachineInstr &MI)
bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType, unsigned DepReg)
bool ignorePseudoInstruction(const MachineInstr &MI, const MachineBasicBlock *MBB) override
bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC)
int getDotNewOp(const MachineInstr &MI) const
static bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI)
cl::opt< bool > ScheduleInlineAsm
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
bool isEHLabel() const
Definition: MachineInstr.h:765
int getDotCurOp(const MachineInstr &MI) const
bool hasControlDependence(const MachineInstr &I, const MachineInstr &J)
bool useCallersSP(MachineInstr &MI)
bool mayBeNewStore(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType, MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J)
aarch64 promote const
bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ)
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override
bool mayBeCurLoad(const MachineInstr &MI) const
SmallVector< SDep, 4 > Succs
Definition: ScheduleDAG.h:259
#define DEBUG(X)
Definition: Debug.h:100
void useCalleesSP(MachineInstr &MI)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:40
void unpacketizeSoloInstrs(MachineFunction &MF)
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
Dependence - This class represents a dependence between two memory memory references in a function...
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
bool isConstExtended(const MachineInstr &MI) const
bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
static bool isDirectJump(const MachineInstr &MI)
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:431
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:903
uint64_t getType(const MachineInstr &MI) const
bool producesStall(const MachineInstr &MI)
Properties which a MachineFunction may have at a given point in time.
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:244
bool isNewValueJump(const MachineInstr &MI) const
bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J)