39 #define DEBUG_TYPE "msp430-lower"
49 cl::desc(
"Hardware multiplier use mode"),
53 "Do not use hardware multiplier"),
55 "Assume hardware multiplier can be used inside interrupts"),
57 "Assume hardware multiplier cannot be used inside interrupts")));
208 if (Constraint.
size() == 1) {
209 switch (Constraint[0]) {
219 std::pair<unsigned, const TargetRegisterClass *>
222 if (Constraint.
size() == 1) {
224 switch (Constraint[0]) {
228 return std::make_pair(0U, &MSP430::GR8RegClass);
230 return std::make_pair(0U, &MSP430::GR16RegClass);
241 #include "MSP430GenCallingConv.inc"
245 template<
typename ArgT>
248 unsigned CurrentArgIndex = ~0U;
249 for (
unsigned i = 0, e = Args.
size();
i != e;
i++) {
250 if (CurrentArgIndex == Args[
i].OrigArgIndex) {
273 template<
typename ArgT>
278 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
290 unsigned RegsLeft = NbRegs;
291 bool UseStack =
false;
294 for (
unsigned i = 0, e = ArgsParts.
size();
i != e;
i++) {
295 MVT ArgVT = Args[ValNo].VT;
305 else if (ArgFlags.
isZExt())
313 State.
HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
317 unsigned Parts = ArgsParts[
i];
319 if (!UseStack && Parts <= RegsLeft) {
320 unsigned FirstVal = ValNo;
321 for (
unsigned j = 0; j < Parts; j++) {
333 for (
unsigned j = 0; j < Parts; j++)
334 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
349 template<
typename ArgT>
360 SDValue MSP430TargetLowering::LowerFormalArguments(
370 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
400 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
401 Outs, OutVals, Ins, dl, DAG, InVals);
410 SDValue MSP430TargetLowering::LowerCCCArguments(
427 unsigned Offset = CCInfo.getNextStackOffset();
431 for (
unsigned i = 0, e = ArgLocs.size();
i != e; ++
i) {
440 errs() <<
"LowerFormalArguments Unhandled argument type: "
480 errs() <<
"LowerFormalArguments Unhandled argument type: "
527 for (
unsigned i = 0;
i != RVLocs.
size(); ++
i) {
547 RetOps.push_back(Flag);
555 SDValue MSP430TargetLowering::LowerCCCCallTo(
568 unsigned NumBytes = CCInfo.getNextStackOffset();
579 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
618 MemOp = DAG.
getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
635 if (!MemOpChains.
empty())
642 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i) {
644 RegsToPass[
i].second, InFlag);
664 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i)
666 RegsToPass[i].second.getValueType()));
681 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
688 SDValue MSP430TargetLowering::LowerCallResult(
701 for (
unsigned i = 0; i != RVLocs.
size(); ++
i) {
703 RVLocs[i].getValVT(), InFlag).
getValue(1);
733 uint64_t ShiftAmount = cast<ConstantSDNode>(N->
getOperand(1))->getZExtValue();
740 if (Opc ==
ISD::SRL && ShiftAmount) {
747 while (ShiftAmount--)
756 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
757 int64_t Offset = cast<GlobalAddressSDNode>(
Op)->
getOffset();
768 const char *Sym = cast<ExternalSymbolSDNode>(
Op)->
getSymbol();
779 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
816 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
830 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
844 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
858 RHS = DAG.
getConstant(
C->getSExtValue() + 1, dl,
C->getValueType(0));
883 Chain, Dest, TargetCC,
Flag);
898 if (RHSC->isNullValue() && LHS.
hasOneUse() &&
916 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
975 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1000 if (ReturnAddrIndex == 0) {
1019 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1045 unsigned Depth = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
1081 bool MSP430TargetLowering::getPostIndexedAddressParts(
SDNode *
N,
SDNode *
Op,
1099 uint64_t RHSC = RHS->getZExtValue();
1100 if ((VT ==
MVT::i16 && RHSC != 2) ||
1181 Opc = MSP430::SHL8r1;
1182 RC = &MSP430::GR8RegClass;
1185 Opc = MSP430::SHL16r1;
1186 RC = &MSP430::GR16RegClass;
1189 Opc = MSP430::SAR8r1;
1190 RC = &MSP430::GR8RegClass;
1193 Opc = MSP430::SAR16r1;
1194 RC = &MSP430::GR16RegClass;
1197 Opc = MSP430::SAR8r1c;
1198 RC = &MSP430::GR8RegClass;
1201 Opc = MSP430::SAR16r1c;
1202 RC = &MSP430::GR16RegClass;
1240 .addReg(ShiftAmtSrcReg).
addImm(0);
1250 BuildMI(LoopBB, dl, TII.
get(MSP430::PHI), ShiftReg)
1251 .addReg(SrcReg).
addMBB(BB)
1253 BuildMI(LoopBB, dl, TII.
get(MSP430::PHI), ShiftAmtReg)
1254 .addReg(ShiftAmtSrcReg).
addMBB(BB)
1258 BuildMI(LoopBB, dl, TII.
get(MSP430::SUB8ri), ShiftAmtReg2)
1259 .addReg(ShiftAmtReg).
addImm(1);
1267 .addReg(SrcReg).
addMBB(BB)
1279 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1280 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1281 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1287 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1288 "Unexpected instr type to insert");
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void setRAIndex(int Index)
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Return with a flag operand. Operand 0 is the chain operand.
MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...
LLVMContext * getContext() const
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
LocInfo getLocInfo() const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
MSP430_INTR - Calling convention used for MSP430 interrupt routines.
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Y = RRC X, rotate right via carry.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
unsigned getByValSize() const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
const SDValue & getOperand(unsigned Num) const
static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
The address of a basic block.
std::string getEVTString() const
getEVTString - This function returns value type as a string, e.g.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterInfo * getRegisterInfo() const override
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
Shift and rotation operations.
MachineFunction & getMachineFunction() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
LLVM_NODISCARD bool empty() const
SmallVector< ISD::InputArg, 32 > Ins
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Same as RET_FLAG, but used for returning from ISRs.
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
void setVarArgsFrameIndex(int Index)
Simple integer binary arithmetic operators.
SmallVector< ISD::OutputArg, 32 > Outs
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
ValuesClass values(OptsTy...Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MVT - Machine Value Type.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
C - The default llvm calling convention, compatible with C.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
const MachineOperand & getOperand(unsigned i) const
int getVarArgsFrameIndex() const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
void setPrefFunctionAlignment(unsigned Align)
Set the target's preferred function alignment.
self_iterator getIterator()
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
This class contains a discriminated union of information about pointers in memory operands...
void HandleByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags)
Allocate space on the stack large enough to pass an argument by value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
unsigned getByValAlign() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
BRCOND - Conditional branch.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
bool isIntegerTy() const
True if this is an instance of IntegerType.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)
Analyze incoming and outgoing function arguments.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
static cl::opt< HWMultUseMode > HWMultMode("msp430-hwmult-mode", cl::Hidden, cl::desc("Hardware multiplier use mode"), cl::init(HWMultNoIntr), cl::values(clEnumValN(NoHWMult,"no","Do not use hardware multiplier"), clEnumValN(HWMultIntr,"interrupts","Assume hardware multiplier can be used inside interrupts"), clEnumValN(HWMultNoIntr,"use","Assume hardware multiplier cannot be used inside interrupts")))
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
unsigned getReg() const
getReg - Returns the register number.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Y = R{R,L}A X, rotate right (left) arithmetically.
void setReturnAddressIsTaken(bool s)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
SDValue getValueType(EVT)
Primary interface to the complete machine description for the target machine.
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SHL, SRA, SRL - Non-constant shifts.
TRUNCATE - Completely drop the high bits.
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...