34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
42 assert(MF &&
"Invalid MachineFunction pointer.");
46 return CSR_AArch64_NoRegs_SaveList;
48 return CSR_AArch64_AllRegs_SaveList;
51 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
52 CSR_AArch64_CXX_TLS_Darwin_SaveList;
56 Attribute::SwiftError))
57 return CSR_AArch64_AAPCS_SwiftError_SaveList;
59 return CSR_AArch64_RT_MostRegs_SaveList;
61 return CSR_AArch64_AAPCS_SaveList;
66 assert(MF &&
"Invalid MachineFunction pointer.");
69 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
78 return CSR_AArch64_NoRegs_RegMask;
80 return CSR_AArch64_AllRegs_RegMask;
82 return CSR_AArch64_CXX_TLS_Darwin_RegMask;
86 return CSR_AArch64_AAPCS_SwiftError_RegMask;
88 return CSR_AArch64_RT_MostRegs_RegMask;
90 return CSR_AArch64_AAPCS_RegMask;
95 return CSR_AArch64_TLS_Darwin_RegMask;
98 return CSR_AArch64_TLS_ELF_RegMask;
112 return CSR_AArch64_AAPCS_ThisReturn_RegMask;
121 markSuperRegs(Reserved, AArch64::SP);
122 markSuperRegs(Reserved, AArch64::XZR);
123 markSuperRegs(Reserved, AArch64::WSP);
124 markSuperRegs(Reserved, AArch64::WZR);
127 markSuperRegs(Reserved, AArch64::FP);
128 markSuperRegs(Reserved, AArch64::W29);
132 markSuperRegs(Reserved, AArch64::X18);
133 markSuperRegs(Reserved, AArch64::W18);
137 markSuperRegs(Reserved, AArch64::X19);
138 markSuperRegs(Reserved, AArch64::W19);
141 assert(checkAllSuperRegsMarked(Reserved));
146 unsigned Reg)
const {
172 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
177 unsigned Kind)
const {
178 return &AArch64::GPR64RegClass;
183 if (RC == &AArch64::CCRRegClass)
184 return &AArch64::GPR64RegClass;
201 if (needsStackRealignment(MF))
219 return TFI->
hasFP(MF) ? AArch64::FP : AArch64::SP;
261 assert(i < MI->getNumOperands() &&
262 "Instr doesn't have FrameIndex operand!");
288 int64_t FPOffset = Offset - 16 * 20;
321 assert(Offset <= INT_MAX &&
"Offset too big to fit in int.");
322 assert(MI &&
"Unable to get the legal offset for nil instruction.");
335 if (Ins != MBB->
end())
336 DL = Ins->getDebugLoc();
340 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
345 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
364 assert(Done &&
"Unable to resolve frame index!");
369 int SPAdj,
unsigned FIOperandNum,
371 assert(SPAdj == 0 &&
"Unexpected");
386 MI.
getOpcode() == TargetOpcode::PATCHPOINT) {
401 "Emergency spill slot is out of reach");
406 unsigned ScratchReg =
416 switch (RC->
getID()) {
419 case AArch64::GPR32RegClassID:
420 case AArch64::GPR32spRegClassID:
421 case AArch64::GPR32allRegClassID:
422 case AArch64::GPR64spRegClassID:
423 case AArch64::GPR64allRegClassID:
424 case AArch64::GPR64RegClassID:
425 case AArch64::GPR32commonRegClassID:
426 case AArch64::GPR64commonRegClassID:
432 case AArch64::FPR8RegClassID:
433 case AArch64::FPR16RegClassID:
434 case AArch64::FPR32RegClassID:
435 case AArch64::FPR64RegClassID:
436 case AArch64::FPR128RegClassID:
439 case AArch64::DDRegClassID:
440 case AArch64::DDDRegClassID:
441 case AArch64::DDDDRegClassID:
442 case AArch64::QQRegClassID:
443 case AArch64::QQQRegClassID:
444 case AArch64::QQQQRegClassID:
447 case AArch64::FPR128_loRegClassID:
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
bool cannotEliminateFrame(const MachineFunction &MF) const
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const uint32_t * getTLSCallPreservedMask() const
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getFrameRegister(const MachineFunction &MF) const override
int64_t getLocalFrameSize() const
Get the size of the local object blob.
unsigned getBaseRegister() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
bool isX18Reserved() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
AArch64RegisterInfo(const Triple &TT)
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
bool isDebugValue() const
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Triple - Helper class for working with autoconf configuration names.
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
AttributeSet getAttributes() const
Return the attribute list for this Function.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
BitVector getReservedRegs(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
bool useFPForScavengingIndex(const MachineFunction &MF) const override
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isConstantPhysReg(unsigned PhysReg) const override
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
bool hasBasePointer(const MachineFunction &MF) const