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LLVM
4.0.0
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#include "AArch64InstrInfo.h"#include "AArch64Subtarget.h"#include "MCTargetDesc/AArch64AddressingModes.h"#include "Utils/AArch64BaseInfo.h"#include "llvm/ADT/ArrayRef.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/STLExtras.h"#include "llvm/CodeGen/MachineBasicBlock.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstr.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineOperand.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/StackMaps.h"#include "llvm/IR/DebugLoc.h"#include "llvm/IR/GlobalValue.h"#include "llvm/MC/MCInst.h"#include "llvm/MC/MCInstrDesc.h"#include "llvm/Support/Casting.h"#include "llvm/Support/CodeGen.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Compiler.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetOptions.h"#include "llvm/Target/TargetRegisterInfo.h"#include "llvm/Target/TargetSubtargetInfo.h"#include <cassert>#include <cstdint>#include <iterator>#include <utility>#include "AArch64GenInstrInfo.inc"Go to the source code of this file.
Macros | |
| #define | GET_INSTRINFO_CTOR_DTOR |
Enumerations | |
| enum | AccessKind { AK_Write = 0x01, AK_Read = 0x10, AK_All = 0x11 } |
| enum | FMAInstKind { FMAInstKind::Default, FMAInstKind::Indexed, FMAInstKind::Accumulator } |
Variables | |
| static const MachineMemOperand::Flags | MOSuppressPair |
| static cl::opt< unsigned > | TBZDisplacementBits ("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)")) |
| static cl::opt< unsigned > | CBZDisplacementBits ("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)")) |
| static cl::opt< unsigned > | BCCDisplacementBits ("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)")) |
| #define GET_INSTRINFO_CTOR_DTOR |
Definition at line 51 of file AArch64InstrInfo.cpp.
| enum AccessKind |
| Enumerator | |
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| AK_Write | |
| AK_Read | |
| AK_All | |
Definition at line 961 of file AArch64InstrInfo.cpp.
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| Enumerator | |
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| Default | |
| Indexed | |
| Accumulator | |
Definition at line 3561 of file AArch64InstrInfo.cpp.
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Definition at line 2000 of file AArch64InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MCRegisterInfo::getSubReg(), and llvm::TargetRegisterInfo::isPhysicalRegister().
Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple().
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True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.
Note: If From and To are from different blocks it's assumed CC are accessed on the path.
Definition at line 972 of file AArch64InstrInfo.cpp.
References AK_Read, AK_Write, assert(), llvm::find_if(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), MI, llvm::MachineInstr::modifiesRegister(), and llvm::MachineInstr::readsRegister().
Referenced by canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().
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Check if AArch64::NZCV should be alive in successors of MBB.
Definition at line 1088 of file AArch64InstrInfo.cpp.
References llvm::MachineBasicBlock::successors().
Referenced by canInstrSubstituteCmpInstr().
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Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.
Definition at line 666 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::processLogicalImmediate().
Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().
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Definition at line 3145 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineOperand::isReg(), and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by canCombineWithFMUL(), and canCombineWithMUL().
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Definition at line 3181 of file AArch64InstrInfo.cpp.
References canCombine().
Referenced by getFMAPatterns().
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Definition at line 3174 of file AArch64InstrInfo.cpp.
References canCombine().
Referenced by getMaddPatterns().
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Definition at line 424 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineOperand::isImm(), llvm::TargetRegisterInfo::isVirtualRegister(), LLVM_FALLTHROUGH, and removeCopies().
Referenced by llvm::AArch64InstrInfo::canInsertSelect(), and llvm::AArch64InstrInfo::insertSelect().
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Check if CmpInstr can be substituted by MI.
CmpInstr can be substituted:
Definition at line 1208 of file AArch64InstrInfo.cpp.
References AK_All, AK_Write, areCFlagsAccessedBetweenInstrs(), areCFlagsAliveInSuccessors(), assert(), E, findCondCodeUsedByInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), getUsedNZCV(), I, llvm::MachineBasicBlock::instr_end(), llvm::AArch64CC::Invalid, isADDSRegImm(), isSUBSRegImm(), llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), and sForm().
Definition at line 1845 of file AArch64InstrInfo.cpp.
Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().
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Return the opcode that does not set flags when possible - otherwise return the original opcode.
The caller is responsible to do the actual substitution and legality checking.
Definition at line 916 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::definesRegister(), and llvm::MachineInstr::getOpcode().
Referenced by getMaddPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().
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Find a condition code used by the instruction.
Returns AArch64CC::Invalid if either the instruction does not use condition codes or we don't optimize CmpInstr in the presence of such instructions.
Definition at line 1119 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64CC::Invalid.
Referenced by canInstrSubstituteCmpInstr().
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Definition at line 2012 of file AArch64InstrInfo.cpp.
Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple().
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genFusedMultiply - Generate fused multiply instructions.
This function supports both integer and floating point instructions. A typical example: F|MUL I=A,B,0 F|ADD R,I,C ==> F|MADD R,A,B,C
| Root | is the F|ADD instruction | |
| [out] | InsInstrs | is a vector of machine instructions and will contain the generated madd instruction |
| IdxMulOpd | is index of operand in Root that is the result of the F|MUL. In the example above IdxMulOpd is 1. | |
| MaddOpc | the opcode fo the f|madd instruction |
Definition at line 3575 of file AArch64InstrInfo.cpp.
References Accumulator, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), Default, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), Indexed, llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().
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genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V
| Root | is the ADD instruction | |
| [out] | InsInstrs | is a vector of machine instructions and will contain the generated madd instruction |
| IdxMulOpd | is index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1. | |
| MaddOpc | the opcode fo the madd instruction | |
| VR | is a virtual register that holds the value of an ADD operand (V in the example above). |
Definition at line 3640 of file AArch64InstrInfo.cpp.
References assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().
Definition at line 148 of file AArch64InstrInfo.cpp.
References B, BCCDisplacementBits, CBZDisplacementBits, llvm_unreachable, and TBZDisplacementBits.
Referenced by llvm::AArch64InstrInfo::isBranchOffsetInRange().
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Floating-Point Support.
Find instructions that can be turned into madd.
Definition at line 3322 of file AArch64InstrInfo.cpp.
References assert(), canCombineWithFMUL(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidateFP(), llvm::MachineOperand::isReg(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().
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Find instructions that can be turned into madd.
Definition at line 3214 of file AArch64InstrInfo.cpp.
References assert(), canCombineWithMUL(), convertFlagSettingOpcode(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), isCombineInstrCandidate(), isCombineInstrSettingFlag(), llvm::MachineOperand::isReg(), llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::getMachineCombinerPatterns().
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Definition at line 1147 of file AArch64InstrInfo.cpp.
References assert(), llvm::AArch64CC::EQ, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::AArch64CC::Invalid, llvm::AArch64CC::LE, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.
Referenced by canInstrSubstituteCmpInstr().
Definition at line 1189 of file AArch64InstrInfo.cpp.
Referenced by canInstrSubstituteCmpInstr().
Definition at line 3138 of file AArch64InstrInfo.cpp.
References isCombineInstrCandidate32(), and isCombineInstrCandidate64().
Referenced by getMaddPatterns().
Definition at line 3078 of file AArch64InstrInfo.cpp.
Referenced by isCombineInstrCandidate().
Definition at line 3097 of file AArch64InstrInfo.cpp.
Referenced by isCombineInstrCandidate().
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Definition at line 3116 of file AArch64InstrInfo.cpp.
References llvm::TargetOptions::AllowFPOpFusion, llvm::FPOpFusion::Fast, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
Referenced by getFMAPatterns().
Definition at line 3059 of file AArch64InstrInfo.cpp.
Referenced by getMaddPatterns().
Definition at line 1193 of file AArch64InstrInfo.cpp.
Referenced by canInstrSubstituteCmpInstr().
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Definition at line 117 of file AArch64InstrInfo.cpp.
References llvm::MachineOperand::CreateImm(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm_unreachable, and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
Referenced by llvm::AArch64InstrInfo::analyzeBranch().
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Definition at line 411 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isFullCopy(), and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by canFoldIntoCSel().
Definition at line 1811 of file AArch64InstrInfo.cpp.
Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().
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Get opcode of S version of Instr.
If Instr is S version its opcode is returned. AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version or we are not interested in it.
Definition at line 1055 of file AArch64InstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
Referenced by canInstrSubstituteCmpInstr().
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Definition at line 875 of file AArch64InstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::TargetRegisterClass::contains(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineInstr::getRegClassConstraint(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::TargetRegisterClass::hasSubClassEq(), llvm::MachineOperand::isFI(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), MRI, and TII.
Referenced by llvm::AArch64InstrInfo::optimizeCompareInstr().
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Referenced by getBranchDisplacementBits().
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Referenced by getBranchDisplacementBits().
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Definition at line 54 of file AArch64InstrInfo.cpp.
Referenced by llvm::AArch64InstrInfo::isLdStPairSuppressed(), and llvm::AArch64InstrInfo::suppressLdStPair().
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Referenced by getBranchDisplacementBits().
1.8.6