LLVM  4.0.0
SparcMCCodeEmitter.cpp
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1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SparcMCCodeEmitter class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcMCExpr.h"
16 #include "SparcMCTargetDesc.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCAsmInfo.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "mccodeemitter"
32 
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
34 
35 namespace {
36 class SparcMCCodeEmitter : public MCCodeEmitter {
37  SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
38  void operator=(const SparcMCCodeEmitter &) = delete;
39  const MCInstrInfo &MCII;
40  MCContext &Ctx;
41 
42 public:
43  SparcMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
44  : MCII(mcii), Ctx(ctx) {}
45 
46  ~SparcMCCodeEmitter() override {}
47 
48  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
50  const MCSubtargetInfo &STI) const override;
51 
52  // getBinaryCodeForInstr - TableGen'erated function for getting the
53  // binary encoding for an instruction.
54  uint64_t getBinaryCodeForInstr(const MCInst &MI,
56  const MCSubtargetInfo &STI) const;
57 
58  /// getMachineOpValue - Return binary encoding of operand. If the machine
59  /// operand requires relocation, record the relocation and return zero.
60  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
62  const MCSubtargetInfo &STI) const;
63 
64  unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
66  const MCSubtargetInfo &STI) const;
67  unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
69  const MCSubtargetInfo &STI) const;
70  unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
72  const MCSubtargetInfo &STI) const;
73  unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
75  const MCSubtargetInfo &STI) const;
76 
77 private:
78  uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
79  void verifyInstructionPredicates(const MCInst &MI,
80  uint64_t AvailableFeatures) const;
81 };
82 } // end anonymous namespace
83 
85  const MCRegisterInfo &MRI,
86  MCContext &Ctx) {
87  return new SparcMCCodeEmitter(MCII, Ctx);
88 }
89 
90 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
92  const MCSubtargetInfo &STI) const {
93  verifyInstructionPredicates(MI,
94  computeAvailableFeatures(STI.getFeatureBits()));
95 
96  unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
97 
98  if (Ctx.getAsmInfo()->isLittleEndian()) {
99  // Output the bits in little-endian byte order.
100  support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
101  } else {
102  // Output the bits in big-endian byte order.
103  support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
104  }
105  unsigned tlsOpNo = 0;
106  switch (MI.getOpcode()) {
107  default: break;
108  case SP::TLS_CALL: tlsOpNo = 1; break;
109  case SP::TLS_ADDrr:
110  case SP::TLS_ADDXrr:
111  case SP::TLS_LDrr:
112  case SP::TLS_LDXrr: tlsOpNo = 3; break;
113  }
114  if (tlsOpNo != 0) {
115  const MCOperand &MO = MI.getOperand(tlsOpNo);
116  uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
117  assert(op == 0 && "Unexpected operand value!");
118  (void)op; // suppress warning.
119  }
120 
121  ++MCNumEmitted; // Keep track of the # of mi's emitted.
122 }
123 
124 
125 unsigned SparcMCCodeEmitter::
126 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
127  SmallVectorImpl<MCFixup> &Fixups,
128  const MCSubtargetInfo &STI) const {
129 
130  if (MO.isReg())
131  return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
132 
133  if (MO.isImm())
134  return MO.getImm();
135 
136  assert(MO.isExpr());
137  const MCExpr *Expr = MO.getExpr();
138  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
139  MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
140  Fixups.push_back(MCFixup::create(0, Expr, Kind));
141  return 0;
142  }
143 
144  int64_t Res;
145  if (Expr->evaluateAsAbsolute(Res))
146  return Res;
147 
148  llvm_unreachable("Unhandled expression!");
149  return 0;
150 }
151 
152 unsigned SparcMCCodeEmitter::
153 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
154  SmallVectorImpl<MCFixup> &Fixups,
155  const MCSubtargetInfo &STI) const {
156  const MCOperand &MO = MI.getOperand(OpNo);
157  if (MO.isReg() || MO.isImm())
158  return getMachineOpValue(MI, MO, Fixups, STI);
159 
160  if (MI.getOpcode() == SP::TLS_CALL) {
161  // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
162  // encodeInstruction.
163 #ifndef NDEBUG
164  // Verify that the callee is actually __tls_get_addr.
165  const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
166  assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
167  "Unexpected expression in TLS_CALL");
168  const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
169  assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
170  "Unexpected function for TLS_CALL");
171 #endif
172  return 0;
173  }
174 
176 
177  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
178  if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
180  }
181 
182  Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind));
183 
184  return 0;
185 }
186 
187 unsigned SparcMCCodeEmitter::
188 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
189  SmallVectorImpl<MCFixup> &Fixups,
190  const MCSubtargetInfo &STI) const {
191  const MCOperand &MO = MI.getOperand(OpNo);
192  if (MO.isReg() || MO.isImm())
193  return getMachineOpValue(MI, MO, Fixups, STI);
194 
195  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
197  return 0;
198 }
199 
200 unsigned SparcMCCodeEmitter::
201 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
202  SmallVectorImpl<MCFixup> &Fixups,
203  const MCSubtargetInfo &STI) const {
204  const MCOperand &MO = MI.getOperand(OpNo);
205  if (MO.isReg() || MO.isImm())
206  return getMachineOpValue(MI, MO, Fixups, STI);
207 
208  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
210  return 0;
211 }
212 unsigned SparcMCCodeEmitter::
213 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
214  SmallVectorImpl<MCFixup> &Fixups,
215  const MCSubtargetInfo &STI) const {
216  const MCOperand &MO = MI.getOperand(OpNo);
217  if (MO.isReg() || MO.isImm())
218  return getMachineOpValue(MI, MO, Fixups, STI);
219 
220  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
222  Fixups.push_back(MCFixup::create(0, MO.getExpr(),
224 
225  return 0;
226 }
227 
228 #define ENABLE_INSTR_PREDICATE_VERIFIER
229 #include "SparcGenMCCodeEmitter.inc"
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
STATISTIC(NumFunctions,"Total number of functions")
bool isReg() const
Definition: MCInst.h:56
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: SparcMCExpr.h:82
ExprKind getKind() const
Definition: MCExpr.h:70
#define op(i)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:161
Context object for machine code objects.
Definition: MCContext.h:51
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
bool isImm() const
Definition: MCInst.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:23
bool isExpr() const
Definition: MCInst.h:59
VariantKind getKind() const
getOpcode - Get the kind of this expression.
Definition: SparcMCExpr.h:79
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:82
fixup_sparc_bpr - 16-bit fixup for bpr
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
Definition: MCInst.h:159
int64_t getImm() const
Definition: MCInst.h:74
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
Definition: MCExpr.h:39
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
fixup_sparc_br22 - 22-bit PC relative relocation for branches
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164