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X86ISelLowering.h
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1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
16 #define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
17 
22 
23 namespace llvm {
24  class X86Subtarget;
25  class X86TargetMachine;
26 
27  namespace X86ISD {
28  // X86 Specific DAG Nodes
29  enum NodeType : unsigned {
30  // Start the numbering where the builtin ops leave off.
32 
33  /// Bit scan forward.
34  BSF,
35  /// Bit scan reverse.
36  BSR,
37 
38  /// Double shift instructions. These correspond to
39  /// X86::SHLDxx and X86::SHRDxx instructions.
42 
43  /// Bitwise logical AND of floating point values. This corresponds
44  /// to X86::ANDPS or X86::ANDPD.
46 
47  /// Bitwise logical OR of floating point values. This corresponds
48  /// to X86::ORPS or X86::ORPD.
49  FOR,
50 
51  /// Bitwise logical XOR of floating point values. This corresponds
52  /// to X86::XORPS or X86::XORPD.
54 
55  /// Bitwise logical ANDNOT of floating point values. This
56  /// corresponds to X86::ANDNPS or X86::ANDNPD.
58 
59  /// These operations represent an abstract X86 call
60  /// instruction, which includes a bunch of information. In particular the
61  /// operands of these node are:
62  ///
63  /// #0 - The incoming token chain
64  /// #1 - The callee
65  /// #2 - The number of arg bytes the caller pushes on the stack.
66  /// #3 - The number of arg bytes the callee pops off the stack.
67  /// #4 - The value to pass in AL/AX/EAX (optional)
68  /// #5 - The value to pass in DL/DX/EDX (optional)
69  ///
70  /// The result values of these nodes are:
71  ///
72  /// #0 - The outgoing token chain
73  /// #1 - The first register result value (optional)
74  /// #2 - The second register result value (optional)
75  ///
77 
78  /// This operation implements the lowering for readcyclecounter.
80 
81  /// X86 Read Time-Stamp Counter and Processor ID.
83 
84  /// X86 Read Performance Monitoring Counters.
86 
87  /// X86 compare and logical compare instructions.
89 
90  /// X86 bit-test instructions.
91  BT,
92 
93  /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
94  /// operand, usually produced by a CMP instruction.
96 
97  /// X86 Select
99 
100  // Same as SETCC except it's materialized with a sbb and the value is all
101  // one's or all zero's.
102  SETCC_CARRY, // R = carry_bit ? ~0 : 0
103 
104  /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
105  /// Operands are two FP values to compare; result is a mask of
106  /// 0s or 1s. Generally DTRT for C/C++ with NaNs.
108 
109  /// X86 FP SETCC, similar to above, but with output as an i1 mask and
110  /// with optional rounding mode.
112 
113  /// X86 conditional moves. Operand 0 and operand 1 are the two values
114  /// to select from. Operand 2 is the condition code, and operand 3 is the
115  /// flag operand produced by a CMP or TEST instruction. It also writes a
116  /// flag result.
118 
119  /// X86 conditional branches. Operand 0 is the chain operand, operand 1
120  /// is the block to branch if condition is true, operand 2 is the
121  /// condition code, and operand 3 is the flag operand produced by a CMP
122  /// or TEST instruction.
124 
125  /// Return with a flag operand. Operand 0 is the chain operand, operand
126  /// 1 is the number of bytes of stack to pop.
128 
129  /// Return from interrupt. Operand 0 is the number of bytes to pop.
131 
132  /// Repeat fill, corresponds to X86::REP_STOSx.
134 
135  /// Repeat move, corresponds to X86::REP_MOVSx.
137 
138  /// On Darwin, this node represents the result of the popl
139  /// at function entry, used for PIC code.
141 
142  /// A wrapper node for TargetConstantPool, TargetJumpTable,
143  /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress,
144  /// MCSymbol and TargetBlockAddress.
146 
147  /// Special wrapper used under X86-64 PIC mode for RIP
148  /// relative displacements.
150 
151  /// Copies a 64-bit value from the low word of an XMM vector
152  /// to an MMX vector. If you think this is too close to the previous
153  /// mnemonic, so do I; blame Intel.
155 
156  /// Copies a 32-bit value from the low word of a MMX
157  /// vector to a GPR.
159 
160  /// Copies a GPR into the low 32-bit word of a MMX vector
161  /// and zero out the high word.
163 
164  /// Extract an 8-bit value from a vector and zero extend it to
165  /// i32, corresponds to X86::PEXTRB.
167 
168  /// Extract a 16-bit value from a vector and zero extend it to
169  /// i32, corresponds to X86::PEXTRW.
171 
172  /// Insert any element of a 4 x float vector into any element
173  /// of a destination 4 x floatvector.
175 
176  /// Insert the lower 8-bits of a 32-bit value to a vector,
177  /// corresponds to X86::PINSRB.
179 
180  /// Insert the lower 16-bits of a 32-bit value to a vector,
181  /// corresponds to X86::PINSRW.
183 
184  /// Shuffle 16 8-bit values within a vector.
186 
187  /// Compute Sum of Absolute Differences.
189  /// Compute Double Block Packed Sum-Absolute-Differences
191 
192  /// Bitwise Logical AND NOT of Packed FP values.
194 
195  /// Blend where the selector is an immediate.
197 
198  /// Blend where the condition has been shrunk.
199  /// This is used to emphasize that the condition mask is
200  /// no more valid for generic VSELECT optimizations.
202 
203  /// Combined add and sub on an FP vector.
205 
206  // FP vector ops with rounding mode.
214 
215  // FP vector get exponent.
217  // Extract Normalized Mantissas.
219  // FP Scale.
222 
223  // Integer add/sub with unsigned saturation.
226 
227  // Integer add/sub with signed saturation.
230 
231  // Unsigned Integer average.
233 
234  /// Integer horizontal add/sub.
237 
238  /// Floating point horizontal add/sub.
241 
242  // Integer absolute value
244 
245  // Detect Conflicts Within a Vector
247 
248  /// Floating point max and min.
250 
251  /// Commutative FMIN and FMAX.
253 
254  /// Floating point reciprocal-sqrt and reciprocal approximation.
255  /// Note that these typically require refinement
256  /// in order to obtain suitable precision.
259 
260  // Thread Local Storage.
262 
263  // Thread Local Storage. A call to get the start address
264  // of the TLS block for the current module.
266 
267  // Thread Local Storage. When calling to an OS provided
268  // thunk at the address from an earlier relocation.
270 
271  // Exception Handling helpers.
273 
274  // SjLj exception handling setjmp.
276 
277  // SjLj exception handling longjmp.
279 
280  // SjLj exception handling dispatch.
282 
283  /// Tail call return. See X86TargetLowering::LowerCall for
284  /// the list of operands.
286 
287  // Vector move to low scalar and zero higher vector elements.
289 
290  // Vector integer zero-extend.
292  // Vector integer signed-extend.
294 
295  // Vector integer truncate.
297  // Vector integer truncate with unsigned/signed saturation.
299 
300  // Vector FP extend.
302 
303  // Vector FP round.
305 
306  // Convert a vector to mask, set bits base on MSB.
308 
309  // 128-bit vector logical left / right shift
311 
312  // Vector shift elements
314 
315  // Vector variable shift right arithmetic.
316  // Unlike ISD::SRA, in case shift count greater then element size
317  // use sign bit to fill destination data element.
319 
320  // Vector shift elements by immediate
322 
323  // Bit rotate by immediate
325 
326  // Vector packed double/float comparison.
328 
329  // Vector integer comparisons.
331  // Vector integer comparisons, the result is in a mask vector.
333 
335 
336  /// Vector comparison generating mask bits for fp and
337  /// integer signed and unsigned data types.
340  // Vector comparison with rounding mode for FP values
342 
343  // Arithmetic operations with FLAGS results.
345  INC, DEC, OR, XOR, AND,
346 
347  // Bit field extract.
349 
350  // LOW, HI, FLAGS = umul LHS, RHS.
352 
353  // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS.
355 
356  // 8-bit divrem that zero-extend the high result (AH).
359 
360  // X86-specific multiply by immediate.
362 
363  // Vector sign bit extraction.
365 
366  // Vector bitwise comparisons.
368 
369  // Vector packed fp sign bitwise comparisons.
371 
372  // Vector "test" in AVX-512, the result is in a mask vector.
375 
376  // OR/AND test for masks.
379 
380  // Several flavors of instructions with vector shuffle behaviors.
381  // Saturated signed/unnsigned packing.
384  // Intra-lane alignr.
386  // AVX512 inter-lane alignr.
392  //Shuffle Packed Values at 128-bit granularity.
410 
411  // Variable Permute (VPERM).
412  // Res = VPERMV MaskV, V0
414 
415  // 3-op Variable Permute (VPERMT2).
416  // Res = VPERMV3 V0, MaskV, V1
418 
419  // 3-op Variable Permute overwriting the index (VPERMI2).
420  // Res = VPERMIV3 V0, MaskV, V1
422 
423  // Bitwise ternary logic.
425  // Fix Up Special Packed Float32/64 values.
428  // Range Restriction Calculation For Packed Pairs of Float32/64 values.
430  // Reduce - Perform Reduction Transformation on scalar\packed FP.
432  // RndScale - Round FP Values To Include A Given Number Of Fraction Bits.
434  // Tests Types Of a FP Values for packed types.
436  // Tests Types Of a FP Values for scalar types.
438 
439  // Broadcast scalar to vector.
441  // Broadcast mask to vector.
443  // Broadcast subvector to vector.
445 
446  // Insert/Extract vector element.
449 
450  /// SSE4A Extraction and Insertion.
452 
453  // XOP variable/immediate rotations.
455  // XOP arithmetic/logical shifts.
457  // XOP signed/unsigned integer comparisons.
459  // XOP packed permute bytes.
461  // XOP two source permutation.
463 
464  // Vector multiply packed unsigned doubleword integers.
466  // Vector multiply packed signed doubleword integers.
468  // Vector Multiply Packed UnsignedIntegers with Round and Scale.
470 
471  // Multiply and Add Packed Integers.
474 
475  // FMA nodes.
482 
483  // FMA with rounding mode.
490 
491  // Scalar intrinsic FMA with rounding mode.
492  // Two versions, passthru bits on op1 or op3.
497 
498  // Compress and expand.
501 
502  // Convert Unsigned/Integer to Floating-Point Value with rounding mode.
505 
506  // Vector float/double to signed/unsigned integer.
508  // Scalar float/double to signed/unsigned integer.
510 
511  // Vector float/double to signed/unsigned integer with truncation.
513  // Scalar float/double to signed/unsigned integer with truncation.
515 
516  // Vector signed/unsigned integer to float/double.
518 
519  // Save xmm argument registers to the stack, according to %al. An operator
520  // is needed so that this can be expanded with control flow.
522 
523  // Windows's _chkstk call to do stack probing.
525 
526  // For allocating variable amounts of stack space when using
527  // segmented stacks. Check if the current stacklet has enough space, and
528  // falls back to heap allocation if not.
530 
531  // Memory barriers.
534 
535  // Store FP status word into i16 register.
537 
538  // Store contents of %ah into %eflags.
540 
541  // Get a random integer and indicate whether it is valid in CF.
543 
544  // Get a NIST SP800-90B & C compliant random integer and
545  // indicate whether it is valid in CF.
547 
548  // SSE42 string comparisons.
551 
552  // Test if in transactional execution.
554 
555  // ERI instructions.
557 
558  // Conversions between float and half-float.
560 
561  // Compare and swap.
567 
568  /// LOCK-prefixed arithmetic read-modify-write instructions.
569  /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS)
571 
572  // Load, scalar_to_vector, and zero extend.
574 
575  // Store FP control world into i16 memory.
577 
578  /// This instruction implements FP_TO_SINT with the
579  /// integer destination in memory and a FP reg source. This corresponds
580  /// to the X86::FIST*m instructions and the rounding mode change stuff. It
581  /// has two inputs (token chain and address) and two outputs (int value
582  /// and token chain).
586 
587  /// This instruction implements SINT_TO_FP with the
588  /// integer source in memory and FP reg result. This corresponds to the
589  /// X86::FILD*m instructions. It has three inputs (token chain, address,
590  /// and source type) and two outputs (FP value and token chain). FILD_FLAG
591  /// also produces a flag).
594 
595  /// This instruction implements an extending load to FP stack slots.
596  /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
597  /// operand, ptr to load from, and a ValueType node indicating the type
598  /// to load to.
600 
601  /// This instruction implements a truncating store to FP stack
602  /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
603  /// chain operand, value to store, address, and a ValueType to store it
604  /// as.
606 
607  /// This instruction grabs the address of the next argument
608  /// from a va_list. (reads and modifies the va_list in memory)
610 
611  // Vector truncating store with unsigned/signed saturation
613  // Vector truncating masked store with unsigned/signed saturation
615 
616  // WARNING: Do not add anything in the end unless you want the node to
617  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
618  // opcodes will be thought as target memory ops!
619  };
620  } // end namespace X86ISD
621 
622  /// Define some predicates that are used for node matching.
623  namespace X86 {
624  /// Return true if the specified
625  /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
626  /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions.
627  bool isVEXTRACT128Index(SDNode *N);
628 
629  /// Return true if the specified
630  /// INSERT_SUBVECTOR operand specifies a subvector insert that is
631  /// suitable for input to VINSERTF128, VINSERTI128 instructions.
632  bool isVINSERT128Index(SDNode *N);
633 
634  /// Return true if the specified
635  /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
636  /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions.
637  bool isVEXTRACT256Index(SDNode *N);
638 
639  /// Return true if the specified
640  /// INSERT_SUBVECTOR operand specifies a subvector insert that is
641  /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions.
642  bool isVINSERT256Index(SDNode *N);
643 
644  /// Return the appropriate
645  /// immediate to extract the specified EXTRACT_SUBVECTOR index
646  /// with VEXTRACTF128, VEXTRACTI128 instructions.
647  unsigned getExtractVEXTRACT128Immediate(SDNode *N);
648 
649  /// Return the appropriate
650  /// immediate to insert at the specified INSERT_SUBVECTOR index
651  /// with VINSERTF128, VINSERT128 instructions.
652  unsigned getInsertVINSERT128Immediate(SDNode *N);
653 
654  /// Return the appropriate
655  /// immediate to extract the specified EXTRACT_SUBVECTOR index
656  /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions.
657  unsigned getExtractVEXTRACT256Immediate(SDNode *N);
658 
659  /// Return the appropriate
660  /// immediate to insert at the specified INSERT_SUBVECTOR index
661  /// with VINSERTF64x4, VINSERTI64x4 instructions.
662  unsigned getInsertVINSERT256Immediate(SDNode *N);
663 
664  /// Returns true if Elt is a constant zero or floating point constant +0.0.
665  bool isZeroNode(SDValue Elt);
666 
667  /// Returns true of the given offset can be
668  /// fit into displacement field of the instruction.
670  bool hasSymbolicDisplacement = true);
671 
672  /// Determines whether the callee is required to pop its
673  /// own arguments. Callee pop is necessary to support tail calls.
674  bool isCalleePop(CallingConv::ID CallingConv,
675  bool is64Bit, bool IsVarArg, bool GuaranteeTCO);
676 
677  } // end namespace X86
678 
679  //===--------------------------------------------------------------------===//
680  // X86 Implementation of the TargetLowering interface
681  class X86TargetLowering final : public TargetLowering {
682  public:
683  explicit X86TargetLowering(const X86TargetMachine &TM,
684  const X86Subtarget &STI);
685 
686  unsigned getJumpTableEncoding() const override;
687  bool useSoftFloat() const override;
688 
689  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
690  return MVT::i8;
691  }
692 
693  const MCExpr *
695  const MachineBasicBlock *MBB, unsigned uid,
696  MCContext &Ctx) const override;
697 
698  /// Returns relocation base for the given PIC jumptable.
700  SelectionDAG &DAG) const override;
701  const MCExpr *
703  unsigned JTI, MCContext &Ctx) const override;
704 
705  /// Return the desired alignment for ByVal aggregate
706  /// function arguments in the caller parameter area. For X86, aggregates
707  /// that contains are placed at 16-byte boundaries while the rest are at
708  /// 4-byte boundaries.
709  unsigned getByValTypeAlignment(Type *Ty,
710  const DataLayout &DL) const override;
711 
712  /// Returns the target specific optimal type for load
713  /// and store operations as a result of memset, memcpy, and memmove
714  /// lowering. If DstAlign is zero that means it's safe to destination
715  /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
716  /// means there isn't a need to check it against alignment requirement,
717  /// probably because the source does not need to be loaded. If 'IsMemset' is
718  /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
719  /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
720  /// source is constant so it does not need to be loaded.
721  /// It returns EVT::Other if the type should be determined using generic
722  /// target-independent logic.
723  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
724  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
725  MachineFunction &MF) const override;
726 
727  /// Returns true if it's safe to use load / store of the
728  /// specified type to expand memcpy / memset inline. This is mostly true
729  /// for all types except for some special cases. For example, on X86
730  /// targets without SSE2 f64 load / store are done with fldl / fstpl which
731  /// also does type conversion. Note the specified type doesn't have to be
732  /// legal as the hook is used before type legalization.
733  bool isSafeMemOpType(MVT VT) const override;
734 
735  /// Returns true if the target allows unaligned memory accesses of the
736  /// specified type. Returns whether it is "fast" in the last argument.
737  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align,
738  bool *Fast) const override;
739 
740  /// Provide custom lowering hooks for some operations.
741  ///
742  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
743 
744  /// Places new result values for the node in Results (their number
745  /// and types must exactly match those of the original return values of
746  /// the node), or leaves Results empty, which indicates that the node is not
747  /// to be custom lowered after all.
750  SelectionDAG &DAG) const override;
751 
752  /// Replace the results of node with an illegal result
753  /// type with new values built out of custom code.
754  ///
756  SelectionDAG &DAG) const override;
757 
758  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
759 
760  /// Return true if the target has native support for
761  /// the specified value type and it is 'desirable' to use the type for the
762  /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
763  /// instruction encodings are longer and some i16 instructions are slow.
764  bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
765 
766  /// Return true if the target has native support for the
767  /// specified value type and it is 'desirable' to use the type. e.g. On x86
768  /// i16 is legal, but undesirable since i16 instruction encodings are longer
769  /// and some i16 instructions are slow.
770  bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
771 
772  /// Return true if the MachineFunction contains a COPY which would imply
773  /// HasOpaqueSPAdjustment.
774  bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const override;
775 
778  MachineBasicBlock *MBB) const override;
779 
780  /// This method returns the name of a target specific DAG node.
781  const char *getTargetNodeName(unsigned Opcode) const override;
782 
783  bool isCheapToSpeculateCttz() const override;
784 
785  bool isCheapToSpeculateCtlz() const override;
786 
787  bool isCtlzFast() const override;
788 
789  bool hasBitPreservingFPLogic(EVT VT) const override {
790  return VT == MVT::f32 || VT == MVT::f64 || VT.isVector();
791  }
792 
793  bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
794  // If the pair to store is a mixture of float and int values, we will
795  // save two bitwise instructions and one float-to-int instruction and
796  // increase one store instruction. There is potentially a more
797  // significant benefit because it avoids the float->int domain switch
798  // for input value. So It is more likely a win.
799  if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
800  (LTy.isInteger() && HTy.isFloatingPoint()))
801  return true;
802  // If the pair only contains int values, we will save two bitwise
803  // instructions and increase one store instruction (costing one more
804  // store buffer). Since the benefit is more blurred so we leave
805  // such pair out until we get testcase to prove it is a win.
806  return false;
807  }
808 
809  bool hasAndNotCompare(SDValue Y) const override;
810 
811  /// Return the value type to use for ISD::SETCC.
813  EVT VT) const override;
814 
815  /// Determine which of the bits specified in Mask are known to be either
816  /// zero or one and return them in the KnownZero/KnownOne bitsets.
818  APInt &KnownZero,
819  APInt &KnownOne,
820  const SelectionDAG &DAG,
821  unsigned Depth = 0) const override;
822 
823  /// Determine the number of bits in the operation that are sign bits.
825  const SelectionDAG &DAG,
826  unsigned Depth) const override;
827 
828  bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
829  int64_t &Offset) const override;
830 
832 
833  bool ExpandInlineAsm(CallInst *CI) const override;
834 
835  ConstraintType getConstraintType(StringRef Constraint) const override;
836 
837  /// Examine constraint string and operand type and determine a weight value.
838  /// The operand object must already have been set up with the operand type.
840  getSingleConstraintMatchWeight(AsmOperandInfo &info,
841  const char *constraint) const override;
842 
843  const char *LowerXConstraint(EVT ConstraintVT) const override;
844 
845  /// Lower the specified operand into the Ops vector. If it is invalid, don't
846  /// add anything to Ops. If hasMemory is true it means one of the asm
847  /// constraint of the inline asm instruction being processed is 'm'.
849  std::string &Constraint,
850  std::vector<SDValue> &Ops,
851  SelectionDAG &DAG) const override;
852 
853  unsigned
854  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
855  if (ConstraintCode == "i")
857  else if (ConstraintCode == "o")
859  else if (ConstraintCode == "v")
861  else if (ConstraintCode == "X")
863  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
864  }
865 
866  /// Given a physical register constraint
867  /// (e.g. {edx}), return the register number and the register class for the
868  /// register. This should only be used for C_Register constraints. On
869  /// error, this returns a register number of 0.
870  std::pair<unsigned, const TargetRegisterClass *>
872  StringRef Constraint, MVT VT) const override;
873 
874  /// Return true if the addressing mode represented
875  /// by AM is legal for this target, for a load/store of the specified type.
876  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
877  Type *Ty, unsigned AS) const override;
878 
879  /// Return true if the specified immediate is legal
880  /// icmp immediate, that is the target has icmp instructions which can
881  /// compare a register against the immediate without having to materialize
882  /// the immediate into a register.
883  bool isLegalICmpImmediate(int64_t Imm) const override;
884 
885  /// Return true if the specified immediate is legal
886  /// add immediate, that is the target has add instructions which can
887  /// add a register and the immediate without having to materialize
888  /// the immediate into a register.
889  bool isLegalAddImmediate(int64_t Imm) const override;
890 
891  /// \brief Return the cost of the scaling factor used in the addressing
892  /// mode represented by AM for this target, for a load/store
893  /// of the specified type.
894  /// If the AM is supported, the return value must be >= 0.
895  /// If the AM is not supported, it returns a negative value.
896  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
897  unsigned AS) const override;
898 
899  bool isVectorShiftByScalarCheap(Type *Ty) const override;
900 
901  /// Return true if it's free to truncate a value of
902  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
903  /// register EAX to i16 by referencing its sub-register AX.
904  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
905  bool isTruncateFree(EVT VT1, EVT VT2) const override;
906 
907  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
908 
909  /// Return true if any actual instruction that defines a
910  /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
911  /// register. This does not necessarily include registers defined in
912  /// unknown ways, such as incoming arguments, or copies from unknown
913  /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
914  /// does not necessarily apply to truncate instructions. e.g. on x86-64,
915  /// all instructions that define 32-bit values implicit zero-extend the
916  /// result out to 64 bits.
917  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
918  bool isZExtFree(EVT VT1, EVT VT2) const override;
919  bool isZExtFree(SDValue Val, EVT VT2) const override;
920 
921  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
922  /// extend node) is profitable.
923  bool isVectorLoadExtDesirable(SDValue) const override;
924 
925  /// Return true if an FMA operation is faster than a pair of fmul and fadd
926  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
927  /// method returns true, otherwise fmuladd is expanded to fmul + fadd.
928  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
929 
930  /// Return true if it's profitable to narrow
931  /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
932  /// from i32 to i8 but not from i32 to i16.
933  bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
934 
935  /// Given an intrinsic, checks if on the target the intrinsic will need to map
936  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
937  /// true and stores the intrinsic information into the IntrinsicInfo that was
938  /// passed to the function.
939  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
940  unsigned Intrinsic) const override;
941 
942  /// Returns true if the target can instruction select the
943  /// specified FP immediate natively. If false, the legalizer will
944  /// materialize the FP immediate as a load from a constant pool.
945  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
946 
947  /// Targets can use this to indicate that they only support *some*
948  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
949  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
950  /// be legal.
952  EVT VT) const override;
953 
954  /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
955  /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to
956  /// replace a VAND with a constant pool entry.
958  EVT VT) const override;
959 
960  /// If true, then instruction selection should
961  /// seek to shrink the FP constant of the specified type to a smaller type
962  /// in order to save space and / or reduce runtime.
963  bool ShouldShrinkFPConstant(EVT VT) const override {
964  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
965  // expensive than a straight movsd. On the other hand, it's important to
966  // shrink long double fp constant since fldt is very slow.
967  return !X86ScalarSSEf64 || VT == MVT::f80;
968  }
969 
970  /// Return true if we believe it is correct and profitable to reduce the
971  /// load node to a smaller type.
973  EVT NewVT) const override;
974 
975  /// Return true if the specified scalar FP type is computed in an SSE
976  /// register, not on the X87 floating point stack.
977  bool isScalarFPTypeInSSEReg(EVT VT) const {
978  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
979  (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
980  }
981 
982  /// \brief Returns true if it is beneficial to convert a load of a constant
983  /// to just the constant itself.
985  Type *Ty) const override;
986 
987  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
988  /// with this index.
989  bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override;
990 
991  /// Intel processors have a unified instruction and data cache
992  const char * getClearCacheBuiltinName() const override {
993  return nullptr; // nothing to do, move along.
994  }
995 
996  unsigned getRegisterByName(const char* RegName, EVT VT,
997  SelectionDAG &DAG) const override;
998 
999  /// If a physical register, this returns the register that receives the
1000  /// exception address on entry to an EH pad.
1001  unsigned
1002  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
1003 
1004  /// If a physical register, this returns the register that receives the
1005  /// exception typeid on entry to a landing pad.
1006  unsigned
1007  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
1008 
1009  virtual bool needsFixedCatchObjects() const override;
1010 
1011  /// This method returns a target specific FastISel object,
1012  /// or null if the target does not support "fast" ISel.
1014  const TargetLibraryInfo *libInfo) const override;
1015 
1016  /// If the target has a standard location for the stack protector cookie,
1017  /// returns the address of that location. Otherwise, returns nullptr.
1018  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
1019 
1020  bool useLoadStackGuardNode() const override;
1021  void insertSSPDeclarations(Module &M) const override;
1022  Value *getSDagStackGuard(const Module &M) const override;
1023  Value *getSSPStackGuardCheck(const Module &M) const override;
1024 
1025  /// Return true if the target stores SafeStack pointer at a fixed offset in
1026  /// some non-standard address space, and populates the address space and
1027  /// offset as appropriate.
1028  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
1029 
1030  SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
1031  SelectionDAG &DAG) const;
1032 
1033  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
1034 
1035  /// \brief Customize the preferred legalization strategy for certain types.
1036  LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
1037 
1038  bool isIntDivCheap(EVT VT, AttributeSet Attr) const override;
1039 
1040  bool supportSwiftError() const override;
1041 
1042  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
1043 
1044  /// \brief Lower interleaved load(s) into target specific
1045  /// instructions/intrinsics.
1046  bool lowerInterleavedLoad(LoadInst *LI,
1048  ArrayRef<unsigned> Indices,
1049  unsigned Factor) const override;
1050  protected:
1051  std::pair<const TargetRegisterClass *, uint8_t>
1053  MVT VT) const override;
1054 
1055  private:
1056  /// Keep a reference to the X86Subtarget around so that we can
1057  /// make the right decision when generating code for different targets.
1058  const X86Subtarget &Subtarget;
1059 
1060  /// Select between SSE or x87 floating point ops.
1061  /// When SSE is available, use it for f32 operations.
1062  /// When SSE2 is available, use it for f64 operations.
1063  bool X86ScalarSSEf32;
1064  bool X86ScalarSSEf64;
1065 
1066  /// A list of legal FP immediates.
1067  std::vector<APFloat> LegalFPImmediates;
1068 
1069  /// Indicate that this x86 target can instruction
1070  /// select the specified FP immediate natively.
1071  void addLegalFPImmediate(const APFloat& Imm) {
1072  LegalFPImmediates.push_back(Imm);
1073  }
1074 
1075  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1076  CallingConv::ID CallConv, bool isVarArg,
1077  const SmallVectorImpl<ISD::InputArg> &Ins,
1078  const SDLoc &dl, SelectionDAG &DAG,
1079  SmallVectorImpl<SDValue> &InVals) const;
1080  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1081  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
1082  const SDLoc &dl, SelectionDAG &DAG,
1083  const CCValAssign &VA, MachineFrameInfo &MFI,
1084  unsigned i) const;
1085  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
1086  const SDLoc &dl, SelectionDAG &DAG,
1087  const CCValAssign &VA,
1088  ISD::ArgFlagsTy Flags) const;
1089 
1090  // Call lowering helpers.
1091 
1092  /// Check whether the call is eligible for tail call optimization. Targets
1093  /// that want to do tail call optimization should implement this function.
1094  bool IsEligibleForTailCallOptimization(SDValue Callee,
1095  CallingConv::ID CalleeCC,
1096  bool isVarArg,
1097  bool isCalleeStructRet,
1098  bool isCallerStructRet,
1099  Type *RetTy,
1100  const SmallVectorImpl<ISD::OutputArg> &Outs,
1101  const SmallVectorImpl<SDValue> &OutVals,
1102  const SmallVectorImpl<ISD::InputArg> &Ins,
1103  SelectionDAG& DAG) const;
1104  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
1105  SDValue Chain, bool IsTailCall,
1106  bool Is64Bit, int FPDiff,
1107  const SDLoc &dl) const;
1108 
1109  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
1110  SelectionDAG &DAG) const;
1111 
1112  unsigned getAddressSpace(void) const;
1113 
1114  std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
1115  bool isSigned,
1116  bool isReplace) const;
1117 
1118  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1119  SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const;
1120  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
1121  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1122  SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const;
1123  SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const;
1124  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1125 
1126  unsigned getGlobalWrapperKind(const GlobalValue *GV = nullptr) const;
1127  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
1128  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
1129  SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &dl,
1130  int64_t Offset, SelectionDAG &DAG) const;
1131  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
1132  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
1133  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
1134 
1135  SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1136  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1137  SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
1138  SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
1139  SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
1140  SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1141  SDValue LowerFP_TO_INT(SDValue Op, const X86Subtarget &Subtarget,
1142  SelectionDAG &DAG) const;
1143  SDValue LowerToBT(SDValue And, ISD::CondCode CC, const SDLoc &dl,
1144  SelectionDAG &DAG) const;
1145  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
1146  SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
1147  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
1148  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
1149  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1150  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
1151  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
1152  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
1153  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1154  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
1155  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
1156  SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
1157  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
1158  SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1159  SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1160  SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
1161  SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
1162  SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1163  SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const;
1164  SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const;
1165  SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const;
1166 
1167  SDValue
1168  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1169  const SmallVectorImpl<ISD::InputArg> &Ins,
1170  const SDLoc &dl, SelectionDAG &DAG,
1171  SmallVectorImpl<SDValue> &InVals) const override;
1172  SDValue LowerCall(CallLoweringInfo &CLI,
1173  SmallVectorImpl<SDValue> &InVals) const override;
1174 
1175  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1176  const SmallVectorImpl<ISD::OutputArg> &Outs,
1177  const SmallVectorImpl<SDValue> &OutVals,
1178  const SDLoc &dl, SelectionDAG &DAG) const override;
1179 
1180  bool supportSplitCSR(MachineFunction *MF) const override {
1181  return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
1182  MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
1183  }
1184  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
1185  void insertCopiesSplitCSR(
1186  MachineBasicBlock *Entry,
1187  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
1188 
1189  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
1190 
1191  bool mayBeEmittedAsTailCall(CallInst *CI) const override;
1192 
1193  EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
1194  ISD::NodeType ExtendKind) const override;
1195 
1196  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1197  bool isVarArg,
1198  const SmallVectorImpl<ISD::OutputArg> &Outs,
1199  LLVMContext &Context) const override;
1200 
1201  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
1202 
1204  shouldExpandAtomicLoadInIR(LoadInst *SI) const override;
1205  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
1207  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
1208 
1209  LoadInst *
1210  lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override;
1211 
1212  bool needsCmpXchgNb(Type *MemType) const;
1213 
1214  void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
1215  MachineBasicBlock *DispatchBB, int FI) const;
1216 
1217  // Utility function to emit the low-level va_arg code for X86-64.
1218  MachineBasicBlock *
1219  EmitVAARG64WithCustomInserter(MachineInstr &MI,
1220  MachineBasicBlock *MBB) const;
1221 
1222  /// Utility function to emit the xmm reg save portion of va_start.
1223  MachineBasicBlock *
1224  EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr &BInstr,
1225  MachineBasicBlock *BB) const;
1226 
1227  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
1228  MachineBasicBlock *BB) const;
1229 
1230  MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr &I,
1231  MachineBasicBlock *BB) const;
1232 
1233  MachineBasicBlock *EmitLoweredCatchRet(MachineInstr &MI,
1234  MachineBasicBlock *BB) const;
1235 
1236  MachineBasicBlock *EmitLoweredCatchPad(MachineInstr &MI,
1237  MachineBasicBlock *BB) const;
1238 
1239  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
1240  MachineBasicBlock *BB) const;
1241 
1242  MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr &MI,
1243  MachineBasicBlock *BB) const;
1244 
1245  MachineBasicBlock *EmitLoweredTLSCall(MachineInstr &MI,
1246  MachineBasicBlock *BB) const;
1247 
1248  MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
1249  MachineBasicBlock *MBB) const;
1250 
1251  MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
1252  MachineBasicBlock *MBB) const;
1253 
1254  MachineBasicBlock *emitFMA3Instr(MachineInstr &MI,
1255  MachineBasicBlock *MBB) const;
1256 
1257  MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr &MI,
1258  MachineBasicBlock *MBB) const;
1259 
1260  /// Emit nodes that will be selected as "test Op0,Op0", or something
1261  /// equivalent, for use with the given x86 condition code.
1262  SDValue EmitTest(SDValue Op0, unsigned X86CC, const SDLoc &dl,
1263  SelectionDAG &DAG) const;
1264 
1265  /// Emit nodes that will be selected as "cmp Op0,Op1", or something
1266  /// equivalent, for use with the given x86 condition code.
1267  SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl,
1268  SelectionDAG &DAG) const;
1269 
1270  /// Convert a comparison if required by the subtarget.
1271  SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
1272 
1273  /// Check if replacement of SQRT with RSQRT should be disabled.
1274  bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override;
1275 
1276  /// Use rsqrt* to speed up sqrt calculations.
1277  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1278  int &RefinementSteps, bool &UseOneConstNR,
1279  bool Reciprocal) const override;
1280 
1281  /// Use rcp* to speed up fdiv calculations.
1282  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1283  int &RefinementSteps) const override;
1284 
1285  /// Reassociate floating point divisions into multiply by reciprocal.
1286  unsigned combineRepeatedFPDivisors() const override;
1287  };
1288 
1289  namespace X86 {
1290  FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
1291  const TargetLibraryInfo *libInfo);
1292  } // end namespace X86
1293 
1294  // Base class for all X86 non-masked store operations.
1295  class X86StoreSDNode : public MemSDNode {
1296  public:
1297  X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1298  SDVTList VTs, EVT MemVT,
1300  :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1301  const SDValue &getValue() const { return getOperand(1); }
1302  const SDValue &getBasePtr() const { return getOperand(2); }
1303 
1304  static bool classof(const SDNode *N) {
1305  return N->getOpcode() == X86ISD::VTRUNCSTORES ||
1307  }
1308  };
1309 
1310  // Base class for all X86 masked store operations.
1311  // The class has the same order of operands as MaskedStoreSDNode for
1312  // convenience.
1314  public:
1315  X86MaskedStoreSDNode(unsigned Opcode, unsigned Order,
1316  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1318  : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {}
1319 
1320  const SDValue &getBasePtr() const { return getOperand(1); }
1321  const SDValue &getMask() const { return getOperand(2); }
1322  const SDValue &getValue() const { return getOperand(3); }
1323 
1324  static bool classof(const SDNode *N) {
1325  return N->getOpcode() == X86ISD::VMTRUNCSTORES ||
1327  }
1328  };
1329 
1330  // X86 Truncating Store with Signed saturation.
1332  public:
1333  TruncSStoreSDNode(unsigned Order, const DebugLoc &dl,
1334  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1335  : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1336 
1337  static bool classof(const SDNode *N) {
1338  return N->getOpcode() == X86ISD::VTRUNCSTORES;
1339  }
1340  };
1341 
1342  // X86 Truncating Store with Unsigned saturation.
1344  public:
1345  TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl,
1346  SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
1347  : X86StoreSDNode(X86ISD::VTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1348 
1349  static bool classof(const SDNode *N) {
1350  return N->getOpcode() == X86ISD::VTRUNCSTOREUS;
1351  }
1352  };
1353 
1354  // X86 Truncating Masked Store with Signed saturation.
1356  public:
1357  MaskedTruncSStoreSDNode(unsigned Order,
1358  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1360  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {}
1361 
1362  static bool classof(const SDNode *N) {
1363  return N->getOpcode() == X86ISD::VMTRUNCSTORES;
1364  }
1365  };
1366 
1367  // X86 Truncating Masked Store with Unsigned saturation.
1369  public:
1371  const DebugLoc &dl, SDVTList VTs, EVT MemVT,
1373  : X86MaskedStoreSDNode(X86ISD::VMTRUNCSTOREUS, Order, dl, VTs, MemVT, MMO) {}
1374 
1375  static bool classof(const SDNode *N) {
1376  return N->getOpcode() == X86ISD::VMTRUNCSTOREUS;
1377  }
1378  };
1379 
1380 } // end namespace llvm
1381 
1382 #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) !=...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isVINSERT128Index(SDNode *N)
Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable f...
Double shift instructions.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
Vector comparison generating mask bits for fp and integer signed and unsigned data types...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool isVectorLoadExtDesirable(SDValue) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
Repeat move, corresponds to X86::REP_MOVSx.
LLVMContext & Context
static bool classof(const SDNode *N)
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
X86TargetLowering(const X86TargetMachine &TM, const X86Subtarget &STI)
Return with a flag operand.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
size_t i
bool isVectorClearMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Similar to isShuffleMaskLegal.
Tail call return.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Compute Double Block Packed Sum-Absolute-Differences.
bool isVEXTRACT128Index(SDNode *N)
Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable fo...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
static bool classof(const SDNode *N)
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
X86 conditional moves.
const SDValue & getValue() const
This class represents a function call, abstracting a target machine's calling convention.
bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
unsigned getInsertVINSERT128Immediate(SDNode *N)
Return the appropriate immediate to insert at the specified INSERT_SUBVECTOR index with VINSERTF128...
A debug info location.
Definition: DebugLoc.h:34
const SDValue & getOperand(unsigned Num) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
static bool classof(const SDNode *N)
SSE4A Extraction and Insertion.
static bool classof(const SDNode *N)
An instruction for reading from memory.
Definition: Instructions.h:164
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Bitwise logical ANDNOT of floating point values.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
This operation implements the lowering for readcyclecounter.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:39
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
X86 compare and logical compare instructions.
MaskedTruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:133
lazy value info
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB.
A description of a memory reference used in the backend.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
struct fuzzer::@269 Flags
Bitwise Logical AND NOT of Packed FP values.
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if we believe it is correct and profitable to reduce the load node to a smaller type...
bool isVINSERT256Index(SDNode *N)
Return true if the specified INSERT_SUBVECTOR operand specifies a subvector insert that is suitable f...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:588
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result...
unsigned getExtractVEXTRACT128Immediate(SDNode *N)
Return the appropriate immediate to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:123
Integer horizontal add/sub.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Copies a 64-bit value from the low word of an XMM vector to an MMX vector.
Context object for machine code objects.
Definition: MCContext.h:51
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const SDValue & getBasePtr() const
Copies a 32-bit value from the low word of a MMX vector to a GPR.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Definition: FastISel.h:31
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
X86 FP SETCC, similar to above, but with output as an i1 mask and with optional rounding mode...
bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const override
Return true if the MachineFunction contains a COPY which would imply HasOpaqueSPAdjustment.
Return from interrupt. Operand 0 is the number of bytes to pop.
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isSafeMemOpType(MVT VT) const override
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline...
MachineBasicBlock * MBB
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
static bool classof(const SDNode *N)
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
Floating point horizontal add/sub.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override
Returns true if the target allows unaligned memory accesses of the specified type.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
Bitwise logical XOR of floating point values.
static bool classof(const SDNode *N)
const SDValue & getBasePtr() const
const SDValue & getMask() const
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type Ty1 to type Ty2.
This instruction implements an extending load to FP stack slots.
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint letter, return the type of constraint for this target.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector.
This is an important base class in LLVM.
Definition: Constant.h:42
Repeat fill, corresponds to X86::REP_STOSx.
static bool is64Bit(const char *name)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:818
X86 conditional branches.
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW.
uint32_t Offset
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Commutative FMIN and FMAX.
On Darwin, this node represents the result of the popl at function entry, used for PIC code...
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
Value * getSDagStackGuard(const Module &M) const override
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
Windows x64, Windows Itanium (IA-64)
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower interleaved load(s) into target specific instructions/intrinsics.
MachineMemOperand * MMO
Memory reference information.
bool isVEXTRACT256Index(SDNode *N)
Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector extract that is suitable fo...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
These operations represent an abstract X86 call instruction, which includes a bunch of information...
Floating point max and min.
bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word. ...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Provides information about what library functions are available for the current target.
X86 Read Time-Stamp Counter and Processor ID.
bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const override
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
bool isNarrowingProfitable(EVT VT1, EVT VT2) const override
Return true if it's profitable to narrow operations of type VT1 to VT2.
This is an abstract virtual class for memory operations.
Bit scan reverse.
unsigned getExtractVEXTRACT256Immediate(SDNode *N)
Return the appropriate immediate to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64X4...
Floating point reciprocal-sqrt and reciprocal approximation.
bool useSoftFloat() const override
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:769
Represents one node in the SelectionDAG.
X86 bit-test instructions.
virtual bool needsFixedCatchObjects() const override
const SDValue & getValue() const
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
MaskedTruncSStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
Class for arbitrary precision integers.
Definition: APInt.h:77
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source...
Bit scan forward.
const char * getClearCacheBuiltinName() const override
Intel processors have a unified instruction and data cache.
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1942
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Places new result values for the node in Results (their number and types must exactly match those of ...
Representation of each machine instruction.
Definition: MachineInstr.h:52
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace the results of node with an illegal result type with new values built out of custom code...
Value * getIRStackGuard(IRBuilder<> &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB.
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress.
Bitwise logical AND of floating point values.
Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const override
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address spa...
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Customize the preferred legalization strategy for certain types.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Value * getSSPStackGuardCheck(const Module &M) const override
If the target has a standard stack protection check function that performs validation and error handl...
X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT MemVT, MachineMemOperand *MMO)
LOCK-prefixed arithmetic read-modify-write instructions.
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getInsertVINSERT256Immediate(SDNode *N)
Return the appropriate immediate to insert at the specified INSERT_SUBVECTOR index with VINSERTF64x4...
Blend where the selector is an immediate.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:118
This instruction implements a truncating store to FP stack slots.
Combined add and sub on an FP vector.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
This instruction grabs the address of the next argument from a va_list.
LLVM Value Representation.
Definition: Value.h:71
Bitwise logical OR of floating point values.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the valu...
Blend where the condition has been shrunk.
X86 Read Performance Monitoring Counters.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
IRTranslator LLVM IR MI
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
bool isZeroNode(SDValue Elt)
Returns true if Elt is a constant zero or floating point constant +0.0.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Returns true of the given offset can be fit into displacement field of the instruction.
bool isVectorShiftByScalarCheap(Type *Ty) const override
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Compute Sum of Absolute Differences.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isScalarFPTypeInSSEReg(EVT VT) const
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating p...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
bool isIntDivCheap(EVT VT, AttributeSet Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
Shuffle 16 8-bit values within a vector.
This file describes how to lower LLVM code to machine code.
Special wrapper used under X86-64 PIC mode for RIP relative displacements.