LLVM  4.0.0
ARMBaseInstrInfo.cpp
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1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
39 #include "llvm/Support/Debug.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "arm-instrinfo"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "ARMGenInstrInfo.inc"
49 
50 static cl::opt<bool>
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52  cl::desc("Enable ARM 2-addr to 3-addr conv"));
53 
54 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
55 struct ARM_MLxEntry {
56  uint16_t MLxOpc; // MLA / MLS opcode
57  uint16_t MulOpc; // Expanded multiplication opcode
58  uint16_t AddSubOpc; // Expanded add / sub opcode
59  bool NegAcc; // True if the acc is negated before the add / sub.
60  bool HasLane; // True if instruction has an extra "lane" operand.
61 };
62 
63 static const ARM_MLxEntry ARM_MLxTable[] = {
64  // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
65  // fp scalar ops
66  { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67  { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
68  { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
69  { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
70  { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
71  { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
72  { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
73  { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 
75  // fp SIMD ops
76  { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
77  { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
78  { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
79  { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
80  { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
81  { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
82  { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
83  { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 };
85 
87  : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
88  Subtarget(STI) {
89  for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
90  if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
91  llvm_unreachable("Duplicated entries?");
92  MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
93  MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
94  }
95 }
96 
97 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
98 // currently defaults to no prepass hazard recognizer.
101  const ScheduleDAG *DAG) const {
102  if (usePreRAHazardRecognizer()) {
103  const InstrItineraryData *II =
104  static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
105  return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
106  }
108 }
109 
112  const ScheduleDAG *DAG) const {
113  if (Subtarget.isThumb2() || Subtarget.hasVFP2())
114  return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
116 }
117 
120  // FIXME: Thumb2 support.
121 
122  if (!EnableARM3Addr)
123  return nullptr;
124 
125  MachineFunction &MF = *MI.getParent()->getParent();
126  uint64_t TSFlags = MI.getDesc().TSFlags;
127  bool isPre = false;
128  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
129  default: return nullptr;
130  case ARMII::IndexModePre:
131  isPre = true;
132  break;
134  break;
135  }
136 
137  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
138  // operation.
139  unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
140  if (MemOpc == 0)
141  return nullptr;
142 
143  MachineInstr *UpdateMI = nullptr;
144  MachineInstr *MemMI = nullptr;
145  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
146  const MCInstrDesc &MCID = MI.getDesc();
147  unsigned NumOps = MCID.getNumOperands();
148  bool isLoad = !MI.mayStore();
149  const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
150  const MachineOperand &Base = MI.getOperand(2);
151  const MachineOperand &Offset = MI.getOperand(NumOps - 3);
152  unsigned WBReg = WB.getReg();
153  unsigned BaseReg = Base.getReg();
154  unsigned OffReg = Offset.getReg();
155  unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
156  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
157  switch (AddrMode) {
158  default: llvm_unreachable("Unknown indexed op!");
159  case ARMII::AddrMode2: {
160  bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
161  unsigned Amt = ARM_AM::getAM2Offset(OffImm);
162  if (OffReg == 0) {
163  if (ARM_AM::getSOImmVal(Amt) == -1)
164  // Can't encode it in a so_imm operand. This transformation will
165  // add more than 1 instruction. Abandon!
166  return nullptr;
167  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
168  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
169  .addReg(BaseReg)
170  .addImm(Amt)
171  .addImm(Pred)
172  .addReg(0)
173  .addReg(0);
174  } else if (Amt != 0) {
176  unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
177  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
178  get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
179  .addReg(BaseReg)
180  .addReg(OffReg)
181  .addReg(0)
182  .addImm(SOOpc)
183  .addImm(Pred)
184  .addReg(0)
185  .addReg(0);
186  } else
187  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
188  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
189  .addReg(BaseReg)
190  .addReg(OffReg)
191  .addImm(Pred)
192  .addReg(0)
193  .addReg(0);
194  break;
195  }
196  case ARMII::AddrMode3 : {
197  bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
198  unsigned Amt = ARM_AM::getAM3Offset(OffImm);
199  if (OffReg == 0)
200  // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
201  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
202  get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
203  .addReg(BaseReg)
204  .addImm(Amt)
205  .addImm(Pred)
206  .addReg(0)
207  .addReg(0);
208  else
209  UpdateMI = BuildMI(MF, MI.getDebugLoc(),
210  get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
211  .addReg(BaseReg)
212  .addReg(OffReg)
213  .addImm(Pred)
214  .addReg(0)
215  .addReg(0);
216  break;
217  }
218  }
219 
220  std::vector<MachineInstr*> NewMIs;
221  if (isPre) {
222  if (isLoad)
223  MemMI =
224  BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
225  .addReg(WBReg)
226  .addImm(0)
227  .addImm(Pred);
228  else
229  MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
230  .addReg(MI.getOperand(1).getReg())
231  .addReg(WBReg)
232  .addReg(0)
233  .addImm(0)
234  .addImm(Pred);
235  NewMIs.push_back(MemMI);
236  NewMIs.push_back(UpdateMI);
237  } else {
238  if (isLoad)
239  MemMI =
240  BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
241  .addReg(BaseReg)
242  .addImm(0)
243  .addImm(Pred);
244  else
245  MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
246  .addReg(MI.getOperand(1).getReg())
247  .addReg(BaseReg)
248  .addReg(0)
249  .addImm(0)
250  .addImm(Pred);
251  if (WB.isDead())
252  UpdateMI->getOperand(0).setIsDead();
253  NewMIs.push_back(UpdateMI);
254  NewMIs.push_back(MemMI);
255  }
256 
257  // Transfer LiveVariables states, kill / dead info.
258  if (LV) {
259  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
260  MachineOperand &MO = MI.getOperand(i);
262  unsigned Reg = MO.getReg();
263 
265  if (MO.isDef()) {
266  MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
267  if (MO.isDead())
268  LV->addVirtualRegisterDead(Reg, *NewMI);
269  }
270  if (MO.isUse() && MO.isKill()) {
271  for (unsigned j = 0; j < 2; ++j) {
272  // Look at the two new MI's in reverse order.
273  MachineInstr *NewMI = NewMIs[j];
274  if (!NewMI->readsRegister(Reg))
275  continue;
276  LV->addVirtualRegisterKilled(Reg, *NewMI);
277  if (VI.removeKill(MI))
278  VI.Kills.push_back(NewMI);
279  break;
280  }
281  }
282  }
283  }
284  }
285 
287  MFI->insert(MBBI, NewMIs[1]);
288  MFI->insert(MBBI, NewMIs[0]);
289  return NewMIs[0];
290 }
291 
292 // Branch analysis.
294  MachineBasicBlock *&TBB,
295  MachineBasicBlock *&FBB,
297  bool AllowModify) const {
298  TBB = nullptr;
299  FBB = nullptr;
300 
302  if (I == MBB.begin())
303  return false; // Empty blocks are easy.
304  --I;
305 
306  // Walk backwards from the end of the basic block until the branch is
307  // analyzed or we give up.
308  while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
309 
310  // Flag to be raised on unanalyzeable instructions. This is useful in cases
311  // where we want to clean up on the end of the basic block before we bail
312  // out.
313  bool CantAnalyze = false;
314 
315  // Skip over DEBUG values and predicated nonterminators.
316  while (I->isDebugValue() || !I->isTerminator()) {
317  if (I == MBB.begin())
318  return false;
319  --I;
320  }
321 
322  if (isIndirectBranchOpcode(I->getOpcode()) ||
323  isJumpTableBranchOpcode(I->getOpcode())) {
324  // Indirect branches and jump tables can't be analyzed, but we still want
325  // to clean up any instructions at the tail of the basic block.
326  CantAnalyze = true;
327  } else if (isUncondBranchOpcode(I->getOpcode())) {
328  TBB = I->getOperand(0).getMBB();
329  } else if (isCondBranchOpcode(I->getOpcode())) {
330  // Bail out if we encounter multiple conditional branches.
331  if (!Cond.empty())
332  return true;
333 
334  assert(!FBB && "FBB should have been null.");
335  FBB = TBB;
336  TBB = I->getOperand(0).getMBB();
337  Cond.push_back(I->getOperand(1));
338  Cond.push_back(I->getOperand(2));
339  } else if (I->isReturn()) {
340  // Returns can't be analyzed, but we should run cleanup.
341  CantAnalyze = !isPredicated(*I);
342  } else {
343  // We encountered other unrecognized terminator. Bail out immediately.
344  return true;
345  }
346 
347  // Cleanup code - to be run for unpredicated unconditional branches and
348  // returns.
349  if (!isPredicated(*I) &&
350  (isUncondBranchOpcode(I->getOpcode()) ||
351  isIndirectBranchOpcode(I->getOpcode()) ||
352  isJumpTableBranchOpcode(I->getOpcode()) ||
353  I->isReturn())) {
354  // Forget any previous condition branch information - it no longer applies.
355  Cond.clear();
356  FBB = nullptr;
357 
358  // If we can modify the function, delete everything below this
359  // unconditional branch.
360  if (AllowModify) {
361  MachineBasicBlock::iterator DI = std::next(I);
362  while (DI != MBB.end()) {
363  MachineInstr &InstToDelete = *DI;
364  ++DI;
365  InstToDelete.eraseFromParent();
366  }
367  }
368  }
369 
370  if (CantAnalyze)
371  return true;
372 
373  if (I == MBB.begin())
374  return false;
375 
376  --I;
377  }
378 
379  // We made it past the terminators without bailing out - we must have
380  // analyzed this branch successfully.
381  return false;
382 }
383 
384 
386  int *BytesRemoved) const {
387  assert(!BytesRemoved && "code size not handled");
388 
390  if (I == MBB.end())
391  return 0;
392 
393  if (!isUncondBranchOpcode(I->getOpcode()) &&
394  !isCondBranchOpcode(I->getOpcode()))
395  return 0;
396 
397  // Remove the branch.
398  I->eraseFromParent();
399 
400  I = MBB.end();
401 
402  if (I == MBB.begin()) return 1;
403  --I;
404  if (!isCondBranchOpcode(I->getOpcode()))
405  return 1;
406 
407  // Remove the branch.
408  I->eraseFromParent();
409  return 2;
410 }
411 
413  MachineBasicBlock *TBB,
414  MachineBasicBlock *FBB,
416  const DebugLoc &DL,
417  int *BytesAdded) const {
418  assert(!BytesAdded && "code size not handled");
420  int BOpc = !AFI->isThumbFunction()
421  ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
422  int BccOpc = !AFI->isThumbFunction()
423  ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
424  bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
425 
426  // Shouldn't be a fall through.
427  assert(TBB && "insertBranch must not be told to insert a fallthrough");
428  assert((Cond.size() == 2 || Cond.size() == 0) &&
429  "ARM branch conditions have two components!");
430 
431  // For conditional branches, we use addOperand to preserve CPSR flags.
432 
433  if (!FBB) {
434  if (Cond.empty()) { // Unconditional branch?
435  if (isThumb)
436  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
437  else
438  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
439  } else
440  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
441  .addImm(Cond[0].getImm()).addOperand(Cond[1]);
442  return 1;
443  }
444 
445  // Two-way conditional branch.
446  BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
447  .addImm(Cond[0].getImm()).addOperand(Cond[1]);
448  if (isThumb)
449  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
450  else
451  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
452  return 2;
453 }
454 
457  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
458  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
459  return false;
460 }
461 
463  if (MI.isBundle()) {
466  while (++I != E && I->isInsideBundle()) {
467  int PIdx = I->findFirstPredOperandIdx();
468  if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
469  return true;
470  }
471  return false;
472  }
473 
474  int PIdx = MI.findFirstPredOperandIdx();
475  return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
476 }
477 
480  unsigned Opc = MI.getOpcode();
481  if (isUncondBranchOpcode(Opc)) {
482  MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
484  .addImm(Pred[0].getImm())
485  .addReg(Pred[1].getReg());
486  return true;
487  }
488 
489  int PIdx = MI.findFirstPredOperandIdx();
490  if (PIdx != -1) {
491  MachineOperand &PMO = MI.getOperand(PIdx);
492  PMO.setImm(Pred[0].getImm());
493  MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
494  return true;
495  }
496  return false;
497 }
498 
500  ArrayRef<MachineOperand> Pred2) const {
501  if (Pred1.size() > 2 || Pred2.size() > 2)
502  return false;
503 
504  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
505  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
506  if (CC1 == CC2)
507  return true;
508 
509  switch (CC1) {
510  default:
511  return false;
512  case ARMCC::AL:
513  return true;
514  case ARMCC::HS:
515  return CC2 == ARMCC::HI;
516  case ARMCC::LS:
517  return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
518  case ARMCC::GE:
519  return CC2 == ARMCC::GT;
520  case ARMCC::LE:
521  return CC2 == ARMCC::LT;
522  }
523 }
524 
526  MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
527  bool Found = false;
528  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
529  const MachineOperand &MO = MI.getOperand(i);
530  if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
531  (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
532  Pred.push_back(MO);
533  Found = true;
534  }
535  }
536 
537  return Found;
538 }
539 
540 static bool isCPSRDefined(const MachineInstr *MI) {
541  for (const auto &MO : MI->operands())
542  if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
543  return true;
544  return false;
545 }
546 
547 static bool isEligibleForITBlock(const MachineInstr *MI) {
548  switch (MI->getOpcode()) {
549  default: return true;
550  case ARM::tADC: // ADC (register) T1
551  case ARM::tADDi3: // ADD (immediate) T1
552  case ARM::tADDi8: // ADD (immediate) T2
553  case ARM::tADDrr: // ADD (register) T1
554  case ARM::tAND: // AND (register) T1
555  case ARM::tASRri: // ASR (immediate) T1
556  case ARM::tASRrr: // ASR (register) T1
557  case ARM::tBIC: // BIC (register) T1
558  case ARM::tEOR: // EOR (register) T1
559  case ARM::tLSLri: // LSL (immediate) T1
560  case ARM::tLSLrr: // LSL (register) T1
561  case ARM::tLSRri: // LSR (immediate) T1
562  case ARM::tLSRrr: // LSR (register) T1
563  case ARM::tMUL: // MUL T1
564  case ARM::tMVN: // MVN (register) T1
565  case ARM::tORR: // ORR (register) T1
566  case ARM::tROR: // ROR (register) T1
567  case ARM::tRSB: // RSB (immediate) T1
568  case ARM::tSBC: // SBC (register) T1
569  case ARM::tSUBi3: // SUB (immediate) T1
570  case ARM::tSUBi8: // SUB (immediate) T2
571  case ARM::tSUBrr: // SUB (register) T1
572  return !isCPSRDefined(MI);
573  }
574 }
575 
576 /// isPredicable - Return true if the specified instruction can be predicated.
577 /// By default, this returns true for every instruction with a
578 /// PredicateOperand.
580  if (!MI.isPredicable())
581  return false;
582 
583  if (MI.isBundle())
584  return false;
585 
586  if (!isEligibleForITBlock(&MI))
587  return false;
588 
589  ARMFunctionInfo *AFI =
591 
592  if (AFI->isThumb2Function()) {
593  if (getSubtarget().restrictIT())
594  return isV8EligibleForIT(&MI);
595  } else { // non-Thumb
597  return false;
598  }
599 
600  return true;
601 }
602 
603 namespace llvm {
605  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
606  const MachineOperand &MO = MI->getOperand(i);
607  if (!MO.isReg() || MO.isUndef() || MO.isUse())
608  continue;
609  if (MO.getReg() != ARM::CPSR)
610  continue;
611  if (!MO.isDead())
612  return false;
613  }
614  // all definitions of CPSR are dead
615  return true;
616 }
617 }
618 
619 /// GetInstSize - Return the size of the specified MachineInstr.
620 ///
622  const MachineBasicBlock &MBB = *MI.getParent();
623  const MachineFunction *MF = MBB.getParent();
624  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
625 
626  const MCInstrDesc &MCID = MI.getDesc();
627  if (MCID.getSize())
628  return MCID.getSize();
629 
630  // If this machine instr is an inline asm, measure it.
631  if (MI.getOpcode() == ARM::INLINEASM)
632  return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
633  unsigned Opc = MI.getOpcode();
634  switch (Opc) {
635  default:
636  // pseudo-instruction sizes are zero.
637  return 0;
638  case TargetOpcode::BUNDLE:
639  return getInstBundleLength(MI);
640  case ARM::MOVi16_ga_pcrel:
641  case ARM::MOVTi16_ga_pcrel:
642  case ARM::t2MOVi16_ga_pcrel:
643  case ARM::t2MOVTi16_ga_pcrel:
644  return 4;
645  case ARM::MOVi32imm:
646  case ARM::t2MOVi32imm:
647  return 8;
648  case ARM::CONSTPOOL_ENTRY:
649  case ARM::JUMPTABLE_INSTS:
650  case ARM::JUMPTABLE_ADDRS:
651  case ARM::JUMPTABLE_TBB:
652  case ARM::JUMPTABLE_TBH:
653  // If this machine instr is a constant pool entry, its size is recorded as
654  // operand #2.
655  return MI.getOperand(2).getImm();
656  case ARM::Int_eh_sjlj_longjmp:
657  return 16;
658  case ARM::tInt_eh_sjlj_longjmp:
659  return 10;
660  case ARM::tInt_WIN_eh_sjlj_longjmp:
661  return 12;
662  case ARM::Int_eh_sjlj_setjmp:
663  case ARM::Int_eh_sjlj_setjmp_nofp:
664  return 20;
665  case ARM::tInt_eh_sjlj_setjmp:
666  case ARM::t2Int_eh_sjlj_setjmp:
667  case ARM::t2Int_eh_sjlj_setjmp_nofp:
668  return 12;
669  case ARM::SPACE:
670  return MI.getOperand(1).getImm();
671  }
672 }
673 
674 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
675  unsigned Size = 0;
678  while (++I != E && I->isInsideBundle()) {
679  assert(!I->isBundle() && "No nested bundle!");
680  Size += getInstSizeInBytes(*I);
681  }
682  return Size;
683 }
684 
687  unsigned DestReg, bool KillSrc,
688  const ARMSubtarget &Subtarget) const {
689  unsigned Opc = Subtarget.isThumb()
690  ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
691  : ARM::MRS;
692 
693  MachineInstrBuilder MIB =
694  BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
695 
696  // There is only 1 A/R class MRS instruction, and it always refers to
697  // APSR. However, there are lots of other possibilities on M-class cores.
698  if (Subtarget.isMClass())
699  MIB.addImm(0x800);
700 
701  AddDefaultPred(MIB);
702 
703  MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
704 }
705 
708  unsigned SrcReg, bool KillSrc,
709  const ARMSubtarget &Subtarget) const {
710  unsigned Opc = Subtarget.isThumb()
711  ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
712  : ARM::MSR;
713 
714  MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
715 
716  if (Subtarget.isMClass())
717  MIB.addImm(0x800);
718  else
719  MIB.addImm(8);
720 
721  MIB.addReg(SrcReg, getKillRegState(KillSrc));
722 
723  AddDefaultPred(MIB);
724 
725  MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
726 }
727 
730  const DebugLoc &DL, unsigned DestReg,
731  unsigned SrcReg, bool KillSrc) const {
732  bool GPRDest = ARM::GPRRegClass.contains(DestReg);
733  bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
734 
735  if (GPRDest && GPRSrc) {
736  AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
737  .addReg(SrcReg, getKillRegState(KillSrc))));
738  return;
739  }
740 
741  bool SPRDest = ARM::SPRRegClass.contains(DestReg);
742  bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
743 
744  unsigned Opc = 0;
745  if (SPRDest && SPRSrc)
746  Opc = ARM::VMOVS;
747  else if (GPRDest && SPRSrc)
748  Opc = ARM::VMOVRS;
749  else if (SPRDest && GPRSrc)
750  Opc = ARM::VMOVSR;
751  else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
752  Opc = ARM::VMOVD;
753  else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
754  Opc = ARM::VORRq;
755 
756  if (Opc) {
757  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
758  MIB.addReg(SrcReg, getKillRegState(KillSrc));
759  if (Opc == ARM::VORRq)
760  MIB.addReg(SrcReg, getKillRegState(KillSrc));
761  AddDefaultPred(MIB);
762  return;
763  }
764 
765  // Handle register classes that require multiple instructions.
766  unsigned BeginIdx = 0;
767  unsigned SubRegs = 0;
768  int Spacing = 1;
769 
770  // Use VORRq when possible.
771  if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
772  Opc = ARM::VORRq;
773  BeginIdx = ARM::qsub_0;
774  SubRegs = 2;
775  } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
776  Opc = ARM::VORRq;
777  BeginIdx = ARM::qsub_0;
778  SubRegs = 4;
779  // Fall back to VMOVD.
780  } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
781  Opc = ARM::VMOVD;
782  BeginIdx = ARM::dsub_0;
783  SubRegs = 2;
784  } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
785  Opc = ARM::VMOVD;
786  BeginIdx = ARM::dsub_0;
787  SubRegs = 3;
788  } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
789  Opc = ARM::VMOVD;
790  BeginIdx = ARM::dsub_0;
791  SubRegs = 4;
792  } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
793  Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
794  BeginIdx = ARM::gsub_0;
795  SubRegs = 2;
796  } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
797  Opc = ARM::VMOVD;
798  BeginIdx = ARM::dsub_0;
799  SubRegs = 2;
800  Spacing = 2;
801  } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
802  Opc = ARM::VMOVD;
803  BeginIdx = ARM::dsub_0;
804  SubRegs = 3;
805  Spacing = 2;
806  } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
807  Opc = ARM::VMOVD;
808  BeginIdx = ARM::dsub_0;
809  SubRegs = 4;
810  Spacing = 2;
811  } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
812  Opc = ARM::VMOVS;
813  BeginIdx = ARM::ssub_0;
814  SubRegs = 2;
815  } else if (SrcReg == ARM::CPSR) {
816  copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
817  return;
818  } else if (DestReg == ARM::CPSR) {
819  copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
820  return;
821  }
822 
823  assert(Opc && "Impossible reg-to-reg copy");
824 
825  const TargetRegisterInfo *TRI = &getRegisterInfo();
827 
828  // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
829  if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
830  BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
831  Spacing = -Spacing;
832  }
833 #ifndef NDEBUG
834  SmallSet<unsigned, 4> DstRegs;
835 #endif
836  for (unsigned i = 0; i != SubRegs; ++i) {
837  unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
838  unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
839  assert(Dst && Src && "Bad sub-register");
840 #ifndef NDEBUG
841  assert(!DstRegs.count(Src) && "destructive vector copy");
842  DstRegs.insert(Dst);
843 #endif
844  Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
845  // VORR takes two source operands.
846  if (Opc == ARM::VORRq)
847  Mov.addReg(Src);
848  Mov = AddDefaultPred(Mov);
849  // MOVr can set CC.
850  if (Opc == ARM::MOVr)
851  Mov = AddDefaultCC(Mov);
852  }
853  // Add implicit super-register defs and kills to the last instruction.
854  Mov->addRegisterDefined(DestReg, TRI);
855  if (KillSrc)
856  Mov->addRegisterKilled(SrcReg, TRI);
857 }
858 
859 const MachineInstrBuilder &
861  unsigned SubIdx, unsigned State,
862  const TargetRegisterInfo *TRI) const {
863  if (!SubIdx)
864  return MIB.addReg(Reg, State);
865 
867  return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
868  return MIB.addReg(Reg, State, SubIdx);
869 }
870 
873  unsigned SrcReg, bool isKill, int FI,
874  const TargetRegisterClass *RC,
875  const TargetRegisterInfo *TRI) const {
876  DebugLoc DL;
877  if (I != MBB.end()) DL = I->getDebugLoc();
878  MachineFunction &MF = *MBB.getParent();
879  MachineFrameInfo &MFI = MF.getFrameInfo();
880  unsigned Align = MFI.getObjectAlignment(FI);
881 
884  MFI.getObjectSize(FI), Align);
885 
886  switch (RC->getSize()) {
887  case 4:
888  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
889  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
890  .addReg(SrcReg, getKillRegState(isKill))
891  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
892  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
893  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
894  .addReg(SrcReg, getKillRegState(isKill))
895  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
896  } else
897  llvm_unreachable("Unknown reg class!");
898  break;
899  case 8:
900  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
901  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
902  .addReg(SrcReg, getKillRegState(isKill))
903  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
904  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
905  if (Subtarget.hasV5TEOps()) {
906  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
907  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
908  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
909  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
910 
911  AddDefaultPred(MIB);
912  } else {
913  // Fallback to STM instruction, which has existed since the dawn of
914  // time.
915  MachineInstrBuilder MIB =
916  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
917  .addFrameIndex(FI).addMemOperand(MMO));
918  AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
919  AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
920  }
921  } else
922  llvm_unreachable("Unknown reg class!");
923  break;
924  case 16:
925  if (ARM::DPairRegClass.hasSubClassEq(RC)) {
926  // Use aligned spills if the stack can be realigned.
927  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
928  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
929  .addFrameIndex(FI).addImm(16)
930  .addReg(SrcReg, getKillRegState(isKill))
931  .addMemOperand(MMO));
932  } else {
933  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
934  .addReg(SrcReg, getKillRegState(isKill))
935  .addFrameIndex(FI)
936  .addMemOperand(MMO));
937  }
938  } else
939  llvm_unreachable("Unknown reg class!");
940  break;
941  case 24:
942  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
943  // Use aligned spills if the stack can be realigned.
944  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
945  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
946  .addFrameIndex(FI).addImm(16)
947  .addReg(SrcReg, getKillRegState(isKill))
948  .addMemOperand(MMO));
949  } else {
950  MachineInstrBuilder MIB =
951  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
952  .addFrameIndex(FI))
953  .addMemOperand(MMO);
954  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
955  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
956  AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
957  }
958  } else
959  llvm_unreachable("Unknown reg class!");
960  break;
961  case 32:
962  if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
963  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
964  // FIXME: It's possible to only store part of the QQ register if the
965  // spilled def has a sub-register index.
966  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
967  .addFrameIndex(FI).addImm(16)
968  .addReg(SrcReg, getKillRegState(isKill))
969  .addMemOperand(MMO));
970  } else {
971  MachineInstrBuilder MIB =
972  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
973  .addFrameIndex(FI))
974  .addMemOperand(MMO);
975  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
976  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
977  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
978  AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
979  }
980  } else
981  llvm_unreachable("Unknown reg class!");
982  break;
983  case 64:
984  if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
985  MachineInstrBuilder MIB =
986  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
987  .addFrameIndex(FI))
988  .addMemOperand(MMO);
989  MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
990  MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
991  MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
992  MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
993  MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
994  MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
995  MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
996  AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
997  } else
998  llvm_unreachable("Unknown reg class!");
999  break;
1000  default:
1001  llvm_unreachable("Unknown reg class!");
1002  }
1003 }
1004 
1006  int &FrameIndex) const {
1007  switch (MI.getOpcode()) {
1008  default: break;
1009  case ARM::STRrs:
1010  case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1011  if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1012  MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1013  MI.getOperand(3).getImm() == 0) {
1014  FrameIndex = MI.getOperand(1).getIndex();
1015  return MI.getOperand(0).getReg();
1016  }
1017  break;
1018  case ARM::STRi12:
1019  case ARM::t2STRi12:
1020  case ARM::tSTRspi:
1021  case ARM::VSTRD:
1022  case ARM::VSTRS:
1023  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1024  MI.getOperand(2).getImm() == 0) {
1025  FrameIndex = MI.getOperand(1).getIndex();
1026  return MI.getOperand(0).getReg();
1027  }
1028  break;
1029  case ARM::VST1q64:
1030  case ARM::VST1d64TPseudo:
1031  case ARM::VST1d64QPseudo:
1032  if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1033  FrameIndex = MI.getOperand(0).getIndex();
1034  return MI.getOperand(2).getReg();
1035  }
1036  break;
1037  case ARM::VSTMQIA:
1038  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1039  FrameIndex = MI.getOperand(1).getIndex();
1040  return MI.getOperand(0).getReg();
1041  }
1042  break;
1043  }
1044 
1045  return 0;
1046 }
1047 
1049  int &FrameIndex) const {
1050  const MachineMemOperand *Dummy;
1051  return MI.mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1052 }
1053 
1054 void ARMBaseInstrInfo::
1056  unsigned DestReg, int FI,
1057  const TargetRegisterClass *RC,
1058  const TargetRegisterInfo *TRI) const {
1059  DebugLoc DL;
1060  if (I != MBB.end()) DL = I->getDebugLoc();
1061  MachineFunction &MF = *MBB.getParent();
1062  MachineFrameInfo &MFI = MF.getFrameInfo();
1063  unsigned Align = MFI.getObjectAlignment(FI);
1066  MFI.getObjectSize(FI), Align);
1067 
1068  switch (RC->getSize()) {
1069  case 4:
1070  if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1071  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1072  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1073 
1074  } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1075  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1076  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1077  } else
1078  llvm_unreachable("Unknown reg class!");
1079  break;
1080  case 8:
1081  if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1082  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1083  .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1084  } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1085  MachineInstrBuilder MIB;
1086 
1087  if (Subtarget.hasV5TEOps()) {
1088  MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1089  AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1090  AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1091  MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1092 
1093  AddDefaultPred(MIB);
1094  } else {
1095  // Fallback to LDM instruction, which has existed since the dawn of
1096  // time.
1097  MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1098  .addFrameIndex(FI).addMemOperand(MMO));
1099  MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1100  MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1101  }
1102 
1104  MIB.addReg(DestReg, RegState::ImplicitDefine);
1105  } else
1106  llvm_unreachable("Unknown reg class!");
1107  break;
1108  case 16:
1109  if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1110  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1111  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1112  .addFrameIndex(FI).addImm(16)
1113  .addMemOperand(MMO));
1114  } else {
1115  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1116  .addFrameIndex(FI)
1117  .addMemOperand(MMO));
1118  }
1119  } else
1120  llvm_unreachable("Unknown reg class!");
1121  break;
1122  case 24:
1123  if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1124  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1125  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1126  .addFrameIndex(FI).addImm(16)
1127  .addMemOperand(MMO));
1128  } else {
1129  MachineInstrBuilder MIB =
1130  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1131  .addFrameIndex(FI)
1132  .addMemOperand(MMO));
1133  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1134  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1135  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1137  MIB.addReg(DestReg, RegState::ImplicitDefine);
1138  }
1139  } else
1140  llvm_unreachable("Unknown reg class!");
1141  break;
1142  case 32:
1143  if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1144  if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1145  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1146  .addFrameIndex(FI).addImm(16)
1147  .addMemOperand(MMO));
1148  } else {
1149  MachineInstrBuilder MIB =
1150  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1151  .addFrameIndex(FI))
1152  .addMemOperand(MMO);
1153  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1154  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1155  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1156  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1158  MIB.addReg(DestReg, RegState::ImplicitDefine);
1159  }
1160  } else
1161  llvm_unreachable("Unknown reg class!");
1162  break;
1163  case 64:
1164  if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1165  MachineInstrBuilder MIB =
1166  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1167  .addFrameIndex(FI))
1168  .addMemOperand(MMO);
1169  MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1170  MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1171  MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1172  MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1173  MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1174  MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1175  MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1176  MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1178  MIB.addReg(DestReg, RegState::ImplicitDefine);
1179  } else
1180  llvm_unreachable("Unknown reg class!");
1181  break;
1182  default:
1183  llvm_unreachable("Unknown regclass!");
1184  }
1185 }
1186 
1188  int &FrameIndex) const {
1189  switch (MI.getOpcode()) {
1190  default: break;
1191  case ARM::LDRrs:
1192  case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1193  if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1194  MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1195  MI.getOperand(3).getImm() == 0) {
1196  FrameIndex = MI.getOperand(1).getIndex();
1197  return MI.getOperand(0).getReg();
1198  }
1199  break;
1200  case ARM::LDRi12:
1201  case ARM::t2LDRi12:
1202  case ARM::tLDRspi:
1203  case ARM::VLDRD:
1204  case ARM::VLDRS:
1205  if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1206  MI.getOperand(2).getImm() == 0) {
1207  FrameIndex = MI.getOperand(1).getIndex();
1208  return MI.getOperand(0).getReg();
1209  }
1210  break;
1211  case ARM::VLD1q64:
1212  case ARM::VLD1d64TPseudo:
1213  case ARM::VLD1d64QPseudo:
1214  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1215  FrameIndex = MI.getOperand(1).getIndex();
1216  return MI.getOperand(0).getReg();
1217  }
1218  break;
1219  case ARM::VLDMQIA:
1220  if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1221  FrameIndex = MI.getOperand(1).getIndex();
1222  return MI.getOperand(0).getReg();
1223  }
1224  break;
1225  }
1226 
1227  return 0;
1228 }
1229 
1231  int &FrameIndex) const {
1232  const MachineMemOperand *Dummy;
1233  return MI.mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1234 }
1235 
1236 /// \brief Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1237 /// depending on whether the result is used.
1238 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1239  bool isThumb1 = Subtarget.isThumb1Only();
1240  bool isThumb2 = Subtarget.isThumb2();
1241  const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1242 
1243  DebugLoc dl = MI->getDebugLoc();
1244  MachineBasicBlock *BB = MI->getParent();
1245 
1246  MachineInstrBuilder LDM, STM;
1247  if (isThumb1 || !MI->getOperand(1).isDead()) {
1248  LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1249  : isThumb1 ? ARM::tLDMIA_UPD
1250  : ARM::LDMIA_UPD))
1251  .addOperand(MI->getOperand(1));
1252  } else {
1253  LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1254  }
1255 
1256  if (isThumb1 || !MI->getOperand(0).isDead()) {
1257  STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1258  : isThumb1 ? ARM::tSTMIA_UPD
1259  : ARM::STMIA_UPD))
1260  .addOperand(MI->getOperand(0));
1261  } else {
1262  STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1263  }
1264 
1265  AddDefaultPred(LDM.addOperand(MI->getOperand(3)));
1266  AddDefaultPred(STM.addOperand(MI->getOperand(2)));
1267 
1268  // Sort the scratch registers into ascending order.
1269  const TargetRegisterInfo &TRI = getRegisterInfo();
1270  llvm::SmallVector<unsigned, 6> ScratchRegs;
1271  for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1272  ScratchRegs.push_back(MI->getOperand(I).getReg());
1273  std::sort(ScratchRegs.begin(), ScratchRegs.end(),
1274  [&TRI](const unsigned &Reg1,
1275  const unsigned &Reg2) -> bool {
1276  return TRI.getEncodingValue(Reg1) <
1277  TRI.getEncodingValue(Reg2);
1278  });
1279 
1280  for (const auto &Reg : ScratchRegs) {
1281  LDM.addReg(Reg, RegState::Define);
1282  STM.addReg(Reg, RegState::Kill);
1283  }
1284 
1285  BB->erase(MI);
1286 }
1287 
1288 
1290  if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1291  assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1292  "LOAD_STACK_GUARD currently supported only for MachO.");
1293  expandLoadStackGuard(MI);
1294  MI.getParent()->erase(MI);
1295  return true;
1296  }
1297 
1298  if (MI.getOpcode() == ARM::MEMCPY) {
1299  expandMEMCPY(MI);
1300  return true;
1301  }
1302 
1303  // This hook gets to expand COPY instructions before they become
1304  // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1305  // widened to VMOVD. We prefer the VMOVD when possible because it may be
1306  // changed into a VORR that can go down the NEON pipeline.
1307  if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || Subtarget.isFPOnlySP())
1308  return false;
1309 
1310  // Look for a copy between even S-registers. That is where we keep floats
1311  // when using NEON v2f32 instructions for f32 arithmetic.
1312  unsigned DstRegS = MI.getOperand(0).getReg();
1313  unsigned SrcRegS = MI.getOperand(1).getReg();
1314  if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1315  return false;
1316 
1317  const TargetRegisterInfo *TRI = &getRegisterInfo();
1318  unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1319  &ARM::DPRRegClass);
1320  unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1321  &ARM::DPRRegClass);
1322  if (!DstRegD || !SrcRegD)
1323  return false;
1324 
1325  // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1326  // legal if the COPY already defines the full DstRegD, and it isn't a
1327  // sub-register insertion.
1328  if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
1329  return false;
1330 
1331  // A dead copy shouldn't show up here, but reject it just in case.
1332  if (MI.getOperand(0).isDead())
1333  return false;
1334 
1335  // All clear, widen the COPY.
1336  DEBUG(dbgs() << "widening: " << MI);
1337  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1338 
1339  // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1340  // or some other super-register.
1341  int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
1342  if (ImpDefIdx != -1)
1343  MI.RemoveOperand(ImpDefIdx);
1344 
1345  // Change the opcode and operands.
1346  MI.setDesc(get(ARM::VMOVD));
1347  MI.getOperand(0).setReg(DstRegD);
1348  MI.getOperand(1).setReg(SrcRegD);
1349  AddDefaultPred(MIB);
1350 
1351  // We are now reading SrcRegD instead of SrcRegS. This may upset the
1352  // register scavenger and machine verifier, so we need to indicate that we
1353  // are reading an undefined value from SrcRegD, but a proper value from
1354  // SrcRegS.
1355  MI.getOperand(1).setIsUndef();
1356  MIB.addReg(SrcRegS, RegState::Implicit);
1357 
1358  // SrcRegD may actually contain an unrelated value in the ssub_1
1359  // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1360  if (MI.getOperand(1).isKill()) {
1361  MI.getOperand(1).setIsKill(false);
1362  MI.addRegisterKilled(SrcRegS, TRI, true);
1363  }
1364 
1365  DEBUG(dbgs() << "replaced by: " << MI);
1366  return true;
1367 }
1368 
1369 /// Create a copy of a const pool value. Update CPI to the new index and return
1370 /// the label UID.
1371 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1374 
1375  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1376  assert(MCPE.isMachineConstantPoolEntry() &&
1377  "Expecting a machine constantpool entry!");
1378  ARMConstantPoolValue *ACPV =
1379  static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1380 
1381  unsigned PCLabelId = AFI->createPICLabelUId();
1382  ARMConstantPoolValue *NewCPV = nullptr;
1383 
1384  // FIXME: The below assumes PIC relocation model and that the function
1385  // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1386  // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1387  // instructions, so that's probably OK, but is PIC always correct when
1388  // we get here?
1389  if (ACPV->isGlobalValue())
1391  cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1392  4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1393  else if (ACPV->isExtSymbol())
1394  NewCPV = ARMConstantPoolSymbol::
1395  Create(MF.getFunction()->getContext(),
1396  cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1397  else if (ACPV->isBlockAddress())
1398  NewCPV = ARMConstantPoolConstant::
1399  Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1401  else if (ACPV->isLSDA())
1402  NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1403  ARMCP::CPLSDA, 4);
1404  else if (ACPV->isMachineBasicBlock())
1405  NewCPV = ARMConstantPoolMBB::
1406  Create(MF.getFunction()->getContext(),
1407  cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1408  else
1409  llvm_unreachable("Unexpected ARM constantpool value type!!");
1410  CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1411  return PCLabelId;
1412 }
1413 
1416  unsigned DestReg, unsigned SubIdx,
1417  const MachineInstr &Orig,
1418  const TargetRegisterInfo &TRI) const {
1419  unsigned Opcode = Orig.getOpcode();
1420  switch (Opcode) {
1421  default: {
1422  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1423  MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1424  MBB.insert(I, MI);
1425  break;
1426  }
1427  case ARM::tLDRpci_pic:
1428  case ARM::t2LDRpci_pic: {
1429  MachineFunction &MF = *MBB.getParent();
1430  unsigned CPI = Orig.getOperand(1).getIndex();
1431  unsigned PCLabelId = duplicateCPV(MF, CPI);
1432  MachineInstrBuilder MIB =
1433  BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
1434  .addConstantPoolIndex(CPI)
1435  .addImm(PCLabelId);
1436  MIB->setMemRefs(Orig.memoperands_begin(), Orig.memoperands_end());
1437  break;
1438  }
1439  }
1440 }
1441 
1443  MachineFunction &MF) const {
1444  MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1445  switch (Orig.getOpcode()) {
1446  case ARM::tLDRpci_pic:
1447  case ARM::t2LDRpci_pic: {
1448  unsigned CPI = Orig.getOperand(1).getIndex();
1449  unsigned PCLabelId = duplicateCPV(MF, CPI);
1450  Orig.getOperand(1).setIndex(CPI);
1451  Orig.getOperand(2).setImm(PCLabelId);
1452  break;
1453  }
1454  }
1455  return MI;
1456 }
1457 
1459  const MachineInstr &MI1,
1460  const MachineRegisterInfo *MRI) const {
1461  unsigned Opcode = MI0.getOpcode();
1462  if (Opcode == ARM::t2LDRpci ||
1463  Opcode == ARM::t2LDRpci_pic ||
1464  Opcode == ARM::tLDRpci ||
1465  Opcode == ARM::tLDRpci_pic ||
1466  Opcode == ARM::LDRLIT_ga_pcrel ||
1467  Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1468  Opcode == ARM::tLDRLIT_ga_pcrel ||
1469  Opcode == ARM::MOV_ga_pcrel ||
1470  Opcode == ARM::MOV_ga_pcrel_ldr ||
1471  Opcode == ARM::t2MOV_ga_pcrel) {
1472  if (MI1.getOpcode() != Opcode)
1473  return false;
1474  if (MI0.getNumOperands() != MI1.getNumOperands())
1475  return false;
1476 
1477  const MachineOperand &MO0 = MI0.getOperand(1);
1478  const MachineOperand &MO1 = MI1.getOperand(1);
1479  if (MO0.getOffset() != MO1.getOffset())
1480  return false;
1481 
1482  if (Opcode == ARM::LDRLIT_ga_pcrel ||
1483  Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1484  Opcode == ARM::tLDRLIT_ga_pcrel ||
1485  Opcode == ARM::MOV_ga_pcrel ||
1486  Opcode == ARM::MOV_ga_pcrel_ldr ||
1487  Opcode == ARM::t2MOV_ga_pcrel)
1488  // Ignore the PC labels.
1489  return MO0.getGlobal() == MO1.getGlobal();
1490 
1491  const MachineFunction *MF = MI0.getParent()->getParent();
1492  const MachineConstantPool *MCP = MF->getConstantPool();
1493  int CPI0 = MO0.getIndex();
1494  int CPI1 = MO1.getIndex();
1495  const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1496  const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1497  bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1498  bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1499  if (isARMCP0 && isARMCP1) {
1500  ARMConstantPoolValue *ACPV0 =
1501  static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1502  ARMConstantPoolValue *ACPV1 =
1503  static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1504  return ACPV0->hasSameValue(ACPV1);
1505  } else if (!isARMCP0 && !isARMCP1) {
1506  return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1507  }
1508  return false;
1509  } else if (Opcode == ARM::PICLDR) {
1510  if (MI1.getOpcode() != Opcode)
1511  return false;
1512  if (MI0.getNumOperands() != MI1.getNumOperands())
1513  return false;
1514 
1515  unsigned Addr0 = MI0.getOperand(1).getReg();
1516  unsigned Addr1 = MI1.getOperand(1).getReg();
1517  if (Addr0 != Addr1) {
1518  if (!MRI ||
1521  return false;
1522 
1523  // This assumes SSA form.
1524  MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1525  MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1526  // Check if the loaded value, e.g. a constantpool of a global address, are
1527  // the same.
1528  if (!produceSameValue(*Def0, *Def1, MRI))
1529  return false;
1530  }
1531 
1532  for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
1533  // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1534  const MachineOperand &MO0 = MI0.getOperand(i);
1535  const MachineOperand &MO1 = MI1.getOperand(i);
1536  if (!MO0.isIdenticalTo(MO1))
1537  return false;
1538  }
1539  return true;
1540  }
1541 
1543 }
1544 
1545 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1546 /// determine if two loads are loading from the same base address. It should
1547 /// only return true if the base pointers are the same and the only differences
1548 /// between the two addresses is the offset. It also returns the offsets by
1549 /// reference.
1550 ///
1551 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1552 /// is permanently disabled.
1554  int64_t &Offset1,
1555  int64_t &Offset2) const {
1556  // Don't worry about Thumb: just ARM and Thumb2.
1557  if (Subtarget.isThumb1Only()) return false;
1558 
1559  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1560  return false;
1561 
1562  switch (Load1->getMachineOpcode()) {
1563  default:
1564  return false;
1565  case ARM::LDRi12:
1566  case ARM::LDRBi12:
1567  case ARM::LDRD:
1568  case ARM::LDRH:
1569  case ARM::LDRSB:
1570  case ARM::LDRSH:
1571  case ARM::VLDRD:
1572  case ARM::VLDRS:
1573  case ARM::t2LDRi8:
1574  case ARM::t2LDRBi8:
1575  case ARM::t2LDRDi8:
1576  case ARM::t2LDRSHi8:
1577  case ARM::t2LDRi12:
1578  case ARM::t2LDRBi12:
1579  case ARM::t2LDRSHi12:
1580  break;
1581  }
1582 
1583  switch (Load2->getMachineOpcode()) {
1584  default:
1585  return false;
1586  case ARM::LDRi12:
1587  case ARM::LDRBi12:
1588  case ARM::LDRD:
1589  case ARM::LDRH:
1590  case ARM::LDRSB:
1591  case ARM::LDRSH:
1592  case ARM::VLDRD:
1593  case ARM::VLDRS:
1594  case ARM::t2LDRi8:
1595  case ARM::t2LDRBi8:
1596  case ARM::t2LDRSHi8:
1597  case ARM::t2LDRi12:
1598  case ARM::t2LDRBi12:
1599  case ARM::t2LDRSHi12:
1600  break;
1601  }
1602 
1603  // Check if base addresses and chain operands match.
1604  if (Load1->getOperand(0) != Load2->getOperand(0) ||
1605  Load1->getOperand(4) != Load2->getOperand(4))
1606  return false;
1607 
1608  // Index should be Reg0.
1609  if (Load1->getOperand(3) != Load2->getOperand(3))
1610  return false;
1611 
1612  // Determine the offsets.
1613  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1614  isa<ConstantSDNode>(Load2->getOperand(1))) {
1615  Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1616  Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1617  return true;
1618  }
1619 
1620  return false;
1621 }
1622 
1623 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1624 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1625 /// be scheduled togther. On some targets if two loads are loading from
1626 /// addresses in the same cache line, it's better if they are scheduled
1627 /// together. This function takes two integers that represent the load offsets
1628 /// from the common base address. It returns true if it decides it's desirable
1629 /// to schedule the two loads together. "NumLoads" is the number of loads that
1630 /// have already been scheduled after Load1.
1631 ///
1632 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1633 /// is permanently disabled.
1635  int64_t Offset1, int64_t Offset2,
1636  unsigned NumLoads) const {
1637  // Don't worry about Thumb: just ARM and Thumb2.
1638  if (Subtarget.isThumb1Only()) return false;
1639 
1640  assert(Offset2 > Offset1);
1641 
1642  if ((Offset2 - Offset1) / 8 > 64)
1643  return false;
1644 
1645  // Check if the machine opcodes are different. If they are different
1646  // then we consider them to not be of the same base address,
1647  // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1648  // In this case, they are considered to be the same because they are different
1649  // encoding forms of the same basic instruction.
1650  if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1651  !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1652  Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1653  (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1654  Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1655  return false; // FIXME: overly conservative?
1656 
1657  // Four loads in a row should be sufficient.
1658  if (NumLoads >= 3)
1659  return false;
1660 
1661  return true;
1662 }
1663 
1665  const MachineBasicBlock *MBB,
1666  const MachineFunction &MF) const {
1667  // Debug info is never a scheduling boundary. It's necessary to be explicit
1668  // due to the special treatment of IT instructions below, otherwise a
1669  // dbg_value followed by an IT will result in the IT instruction being
1670  // considered a scheduling hazard, which is wrong. It should be the actual
1671  // instruction preceding the dbg_value instruction(s), just like it is
1672  // when debug info is not present.
1673  if (MI.isDebugValue())
1674  return false;
1675 
1676  // Terminators and labels can't be scheduled around.
1677  if (MI.isTerminator() || MI.isPosition())
1678  return true;
1679 
1680  // Treat the start of the IT block as a scheduling boundary, but schedule
1681  // t2IT along with all instructions following it.
1682  // FIXME: This is a big hammer. But the alternative is to add all potential
1683  // true and anti dependencies to IT block instructions as implicit operands
1684  // to the t2IT instruction. The added compile time and complexity does not
1685  // seem worth it.
1687  // Make sure to skip any dbg_value instructions
1688  while (++I != MBB->end() && I->isDebugValue())
1689  ;
1690  if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1691  return true;
1692 
1693  // Don't attempt to schedule around any instruction that defines
1694  // a stack-oriented pointer, as it's unlikely to be profitable. This
1695  // saves compile time, because it doesn't require every single
1696  // stack slot reference to depend on the instruction that does the
1697  // modification.
1698  // Calls don't actually change the stack pointer, even if they have imp-defs.
1699  // No ARM calling conventions change the stack pointer. (X86 calling
1700  // conventions sometimes do).
1701  if (!MI.isCall() && MI.definesRegister(ARM::SP))
1702  return true;
1703 
1704  return false;
1705 }
1706 
1707 bool ARMBaseInstrInfo::
1709  unsigned NumCycles, unsigned ExtraPredCycles,
1710  BranchProbability Probability) const {
1711  if (!NumCycles)
1712  return false;
1713 
1714  // If we are optimizing for size, see if the branch in the predecessor can be
1715  // lowered to cbn?z by the constant island lowering pass, and return false if
1716  // so. This results in a shorter instruction sequence.
1717  if (MBB.getParent()->getFunction()->optForSize()) {
1718  MachineBasicBlock *Pred = *MBB.pred_begin();
1719  if (!Pred->empty()) {
1720  MachineInstr *LastMI = &*Pred->rbegin();
1721  if (LastMI->getOpcode() == ARM::t2Bcc) {
1722  MachineBasicBlock::iterator CmpMI = LastMI;
1723  if (CmpMI != Pred->begin()) {
1724  --CmpMI;
1725  if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1726  CmpMI->getOpcode() == ARM::t2CMPri) {
1727  unsigned Reg = CmpMI->getOperand(0).getReg();
1728  unsigned PredReg = 0;
1729  ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg);
1730  if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1731  isARMLowRegister(Reg))
1732  return false;
1733  }
1734  }
1735  }
1736  }
1737  }
1738 
1739  // Attempt to estimate the relative costs of predication versus branching.
1740  // Here we scale up each component of UnpredCost to avoid precision issue when
1741  // scaling NumCycles by Probability.
1742  const unsigned ScalingUpFactor = 1024;
1743  unsigned UnpredCost = Probability.scale(NumCycles * ScalingUpFactor);
1744  UnpredCost += ScalingUpFactor; // The branch itself
1745  UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1746 
1747  return (NumCycles + ExtraPredCycles) * ScalingUpFactor <= UnpredCost;
1748 }
1749 
1750 bool ARMBaseInstrInfo::
1752  unsigned TCycles, unsigned TExtra,
1753  MachineBasicBlock &FMBB,
1754  unsigned FCycles, unsigned FExtra,
1755  BranchProbability Probability) const {
1756  if (!TCycles || !FCycles)
1757  return false;
1758 
1759  // Attempt to estimate the relative costs of predication versus branching.
1760  // Here we scale up each component of UnpredCost to avoid precision issue when
1761  // scaling TCycles/FCycles by Probability.
1762  const unsigned ScalingUpFactor = 1024;
1763  unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
1764  unsigned FUnpredCost =
1765  Probability.getCompl().scale(FCycles * ScalingUpFactor);
1766  unsigned UnpredCost = TUnpredCost + FUnpredCost;
1767  UnpredCost += 1 * ScalingUpFactor; // The branch itself
1768  UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1769 
1770  return (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor <= UnpredCost;
1771 }
1772 
1773 bool
1775  MachineBasicBlock &FMBB) const {
1776  // Reduce false anti-dependencies to let the target's out-of-order execution
1777  // engine do its thing.
1778  return Subtarget.isProfitableToUnpredicate();
1779 }
1780 
1781 /// getInstrPredicate - If instruction is predicated, returns its predicate
1782 /// condition, otherwise returns AL. It also returns the condition code
1783 /// register by reference.
1785  unsigned &PredReg) {
1786  int PIdx = MI.findFirstPredOperandIdx();
1787  if (PIdx == -1) {
1788  PredReg = 0;
1789  return ARMCC::AL;
1790  }
1791 
1792  PredReg = MI.getOperand(PIdx+1).getReg();
1793  return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1794 }
1795 
1796 
1797 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1798  if (Opc == ARM::B)
1799  return ARM::Bcc;
1800  if (Opc == ARM::tB)
1801  return ARM::tBcc;
1802  if (Opc == ARM::t2B)
1803  return ARM::t2Bcc;
1804 
1805  llvm_unreachable("Unknown unconditional branch opcode!");
1806 }
1807 
1809  bool NewMI,
1810  unsigned OpIdx1,
1811  unsigned OpIdx2) const {
1812  switch (MI.getOpcode()) {
1813  case ARM::MOVCCr:
1814  case ARM::t2MOVCCr: {
1815  // MOVCC can be commuted by inverting the condition.
1816  unsigned PredReg = 0;
1817  ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1818  // MOVCC AL can't be inverted. Shouldn't happen.
1819  if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1820  return nullptr;
1821  MachineInstr *CommutedMI =
1822  TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1823  if (!CommutedMI)
1824  return nullptr;
1825  // After swapping the MOVCC operands, also invert the condition.
1826  CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
1827  .setImm(ARMCC::getOppositeCondition(CC));
1828  return CommutedMI;
1829  }
1830  }
1831  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1832 }
1833 
1834 /// Identify instructions that can be folded into a MOVCC instruction, and
1835 /// return the defining instruction.
1837  const MachineRegisterInfo &MRI,
1838  const TargetInstrInfo *TII) {
1840  return nullptr;
1841  if (!MRI.hasOneNonDBGUse(Reg))
1842  return nullptr;
1843  MachineInstr *MI = MRI.getVRegDef(Reg);
1844  if (!MI)
1845  return nullptr;
1846  // MI is folded into the MOVCC by predicating it.
1847  if (!MI->isPredicable())
1848  return nullptr;
1849  // Check if MI has any non-dead defs or physreg uses. This also detects
1850  // predicated instructions which will be reading CPSR.
1851  for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1852  const MachineOperand &MO = MI->getOperand(i);
1853  // Reject frame index operands, PEI can't handle the predicated pseudos.
1854  if (MO.isFI() || MO.isCPI() || MO.isJTI())
1855  return nullptr;
1856  if (!MO.isReg())
1857  continue;
1858  // MI can't have any tied operands, that would conflict with predication.
1859  if (MO.isTied())
1860  return nullptr;
1862  return nullptr;
1863  if (MO.isDef() && !MO.isDead())
1864  return nullptr;
1865  }
1866  bool DontMoveAcrossStores = true;
1867  if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1868  return nullptr;
1869  return MI;
1870 }
1871 
1874  unsigned &TrueOp, unsigned &FalseOp,
1875  bool &Optimizable) const {
1876  assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
1877  "Unknown select instruction");
1878  // MOVCC operands:
1879  // 0: Def.
1880  // 1: True use.
1881  // 2: False use.
1882  // 3: Condition code.
1883  // 4: CPSR use.
1884  TrueOp = 1;
1885  FalseOp = 2;
1886  Cond.push_back(MI.getOperand(3));
1887  Cond.push_back(MI.getOperand(4));
1888  // We can always fold a def.
1889  Optimizable = true;
1890  return false;
1891 }
1892 
1893 MachineInstr *
1896  bool PreferFalse) const {
1897  assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
1898  "Unknown select instruction");
1900  MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
1901  bool Invert = !DefMI;
1902  if (!DefMI)
1903  DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
1904  if (!DefMI)
1905  return nullptr;
1906 
1907  // Find new register class to use.
1908  MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
1909  unsigned DestReg = MI.getOperand(0).getReg();
1910  const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1911  if (!MRI.constrainRegClass(DestReg, PreviousClass))
1912  return nullptr;
1913 
1914  // Create a new predicated version of DefMI.
1915  // Rfalse is the first use.
1916  MachineInstrBuilder NewMI =
1917  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
1918 
1919  // Copy all the DefMI operands, excluding its (null) predicate.
1920  const MCInstrDesc &DefDesc = DefMI->getDesc();
1921  for (unsigned i = 1, e = DefDesc.getNumOperands();
1922  i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1923  NewMI.addOperand(DefMI->getOperand(i));
1924 
1925  unsigned CondCode = MI.getOperand(3).getImm();
1926  if (Invert)
1928  else
1929  NewMI.addImm(CondCode);
1930  NewMI.addOperand(MI.getOperand(4));
1931 
1932  // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1933  if (NewMI->hasOptionalDef())
1934  AddDefaultCC(NewMI);
1935 
1936  // The output register value when the predicate is false is an implicit
1937  // register operand tied to the first def.
1938  // The tie makes the register allocator ensure the FalseReg is allocated the
1939  // same register as operand 0.
1940  FalseReg.setImplicit();
1941  NewMI.addOperand(FalseReg);
1942  NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1943 
1944  // Update SeenMIs set: register newly created MI and erase removed DefMI.
1945  SeenMIs.insert(NewMI);
1946  SeenMIs.erase(DefMI);
1947 
1948  // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1949  // DefMI would be invalid when tranferred inside the loop. Checking for a
1950  // loop is expensive, but at least remove kill flags if they are in different
1951  // BBs.
1952  if (DefMI->getParent() != MI.getParent())
1953  NewMI->clearKillInfo();
1954 
1955  // The caller will erase MI, but not DefMI.
1956  DefMI->eraseFromParent();
1957  return NewMI;
1958 }
1959 
1960 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1961 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1962 /// def operand.
1963 ///
1964 /// This will go away once we can teach tblgen how to set the optional CPSR def
1965 /// operand itself.
1967  uint16_t PseudoOpc;
1968  uint16_t MachineOpc;
1969 };
1970 
1972  {ARM::ADDSri, ARM::ADDri},
1973  {ARM::ADDSrr, ARM::ADDrr},
1974  {ARM::ADDSrsi, ARM::ADDrsi},
1975  {ARM::ADDSrsr, ARM::ADDrsr},
1976 
1977  {ARM::SUBSri, ARM::SUBri},
1978  {ARM::SUBSrr, ARM::SUBrr},
1979  {ARM::SUBSrsi, ARM::SUBrsi},
1980  {ARM::SUBSrsr, ARM::SUBrsr},
1981 
1982  {ARM::RSBSri, ARM::RSBri},
1983  {ARM::RSBSrsi, ARM::RSBrsi},
1984  {ARM::RSBSrsr, ARM::RSBrsr},
1985 
1986  {ARM::t2ADDSri, ARM::t2ADDri},
1987  {ARM::t2ADDSrr, ARM::t2ADDrr},
1988  {ARM::t2ADDSrs, ARM::t2ADDrs},
1989 
1990  {ARM::t2SUBSri, ARM::t2SUBri},
1991  {ARM::t2SUBSrr, ARM::t2SUBrr},
1992  {ARM::t2SUBSrs, ARM::t2SUBrs},
1993 
1994  {ARM::t2RSBSri, ARM::t2RSBri},
1995  {ARM::t2RSBSrs, ARM::t2RSBrs},
1996 };
1997 
1998 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1999  for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
2000  if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
2002  return 0;
2003 }
2004 
2007  const DebugLoc &dl, unsigned DestReg,
2008  unsigned BaseReg, int NumBytes,
2009  ARMCC::CondCodes Pred, unsigned PredReg,
2010  const ARMBaseInstrInfo &TII,
2011  unsigned MIFlags) {
2012  if (NumBytes == 0 && DestReg != BaseReg) {
2013  BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2014  .addReg(BaseReg, RegState::Kill)
2015  .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
2016  .setMIFlags(MIFlags);
2017  return;
2018  }
2019 
2020  bool isSub = NumBytes < 0;
2021  if (isSub) NumBytes = -NumBytes;
2022 
2023  while (NumBytes) {
2024  unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2025  unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2026  assert(ThisVal && "Didn't extract field correctly");
2027 
2028  // We will handle these bits from offset, clear them.
2029  NumBytes &= ~ThisVal;
2030 
2031  assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2032 
2033  // Build the new ADD / SUB.
2034  unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2035  BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2036  .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
2037  .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
2038  .setMIFlags(MIFlags);
2039  BaseReg = DestReg;
2040  }
2041 }
2042 
2044  MachineFunction &MF, MachineInstr *MI,
2045  unsigned NumBytes) {
2046  // This optimisation potentially adds lots of load and store
2047  // micro-operations, it's only really a great benefit to code-size.
2048  if (!MF.getFunction()->optForMinSize())
2049  return false;
2050 
2051  // If only one register is pushed/popped, LLVM can use an LDR/STR
2052  // instead. We can't modify those so make sure we're dealing with an
2053  // instruction we understand.
2054  bool IsPop = isPopOpcode(MI->getOpcode());
2055  bool IsPush = isPushOpcode(MI->getOpcode());
2056  if (!IsPush && !IsPop)
2057  return false;
2058 
2059  bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2060  MI->getOpcode() == ARM::VLDMDIA_UPD;
2061  bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2062  MI->getOpcode() == ARM::tPOP ||
2063  MI->getOpcode() == ARM::tPOP_RET;
2064 
2065  assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2066  MI->getOperand(1).getReg() == ARM::SP)) &&
2067  "trying to fold sp update into non-sp-updating push/pop");
2068 
2069  // The VFP push & pop act on D-registers, so we can only fold an adjustment
2070  // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2071  // if this is violated.
2072  if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2073  return false;
2074 
2075  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2076  // pred) so the list starts at 4. Thumb1 starts after the predicate.
2077  int RegListIdx = IsT1PushPop ? 2 : 4;
2078 
2079  // Calculate the space we'll need in terms of registers.
2080  unsigned RegsNeeded;
2081  const TargetRegisterClass *RegClass;
2082  if (IsVFPPushPop) {
2083  RegsNeeded = NumBytes / 8;
2084  RegClass = &ARM::DPRRegClass;
2085  } else {
2086  RegsNeeded = NumBytes / 4;
2087  RegClass = &ARM::GPRRegClass;
2088  }
2089 
2090  // We're going to have to strip all list operands off before
2091  // re-adding them since the order matters, so save the existing ones
2092  // for later.
2094 
2095  // We're also going to need the first register transferred by this
2096  // instruction, which won't necessarily be the first register in the list.
2097  unsigned FirstRegEnc = -1;
2098 
2100  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) {
2101  MachineOperand &MO = MI->getOperand(i);
2102  RegList.push_back(MO);
2103 
2104  if (MO.isReg() && TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2105  FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2106  }
2107 
2108  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2109 
2110  // Now try to find enough space in the reglist to allocate NumBytes.
2111  for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
2112  --CurRegEnc) {
2113  unsigned CurReg = RegClass->getRegister(CurRegEnc);
2114  if (!IsPop) {
2115  // Pushing any register is completely harmless, mark the
2116  // register involved as undef since we don't care about it in
2117  // the slightest.
2118  RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2119  false, false, true));
2120  --RegsNeeded;
2121  continue;
2122  }
2123 
2124  // However, we can only pop an extra register if it's not live. For
2125  // registers live within the function we might clobber a return value
2126  // register; the other way a register can be live here is if it's
2127  // callee-saved.
2128  if (isCalleeSavedRegister(CurReg, CSRegs) ||
2129  MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2131  // VFP pops don't allow holes in the register list, so any skip is fatal
2132  // for our transformation. GPR pops do, so we should just keep looking.
2133  if (IsVFPPushPop)
2134  return false;
2135  else
2136  continue;
2137  }
2138 
2139  // Mark the unimportant registers as <def,dead> in the POP.
2140  RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2141  true));
2142  --RegsNeeded;
2143  }
2144 
2145  if (RegsNeeded > 0)
2146  return false;
2147 
2148  // Finally we know we can profitably perform the optimisation so go
2149  // ahead: strip all existing registers off and add them back again
2150  // in the right order.
2151  for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2152  MI->RemoveOperand(i);
2153 
2154  // Add the complete list back in.
2155  MachineInstrBuilder MIB(MF, &*MI);
2156  for (int i = RegList.size() - 1; i >= 0; --i)
2157  MIB.addOperand(RegList[i]);
2158 
2159  return true;
2160 }
2161 
2162 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2163  unsigned FrameReg, int &Offset,
2164  const ARMBaseInstrInfo &TII) {
2165  unsigned Opcode = MI.getOpcode();
2166  const MCInstrDesc &Desc = MI.getDesc();
2167  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2168  bool isSub = false;
2169 
2170  // Memory operands in inline assembly always use AddrMode2.
2171  if (Opcode == ARM::INLINEASM)
2172  AddrMode = ARMII::AddrMode2;
2173 
2174  if (Opcode == ARM::ADDri) {
2175  Offset += MI.getOperand(FrameRegIdx+1).getImm();
2176  if (Offset == 0) {
2177  // Turn it into a move.
2178  MI.setDesc(TII.get(ARM::MOVr));
2179  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2180  MI.RemoveOperand(FrameRegIdx+1);
2181  Offset = 0;
2182  return true;
2183  } else if (Offset < 0) {
2184  Offset = -Offset;
2185  isSub = true;
2186  MI.setDesc(TII.get(ARM::SUBri));
2187  }
2188 
2189  // Common case: small offset, fits into instruction.
2190  if (ARM_AM::getSOImmVal(Offset) != -1) {
2191  // Replace the FrameIndex with sp / fp
2192  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2193  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2194  Offset = 0;
2195  return true;
2196  }
2197 
2198  // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2199  // as possible.
2200  unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2201  unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2202 
2203  // We will handle these bits from offset, clear them.
2204  Offset &= ~ThisImmVal;
2205 
2206  // Get the properly encoded SOImmVal field.
2207  assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2208  "Bit extraction didn't work?");
2209  MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2210  } else {
2211  unsigned ImmIdx = 0;
2212  int InstrOffs = 0;
2213  unsigned NumBits = 0;
2214  unsigned Scale = 1;
2215  switch (AddrMode) {
2216  case ARMII::AddrMode_i12: {
2217  ImmIdx = FrameRegIdx + 1;
2218  InstrOffs = MI.getOperand(ImmIdx).getImm();
2219  NumBits = 12;
2220  break;
2221  }
2222  case ARMII::AddrMode2: {
2223  ImmIdx = FrameRegIdx+2;
2224  InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2225  if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2226  InstrOffs *= -1;
2227  NumBits = 12;
2228  break;
2229  }
2230  case ARMII::AddrMode3: {
2231  ImmIdx = FrameRegIdx+2;
2232  InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2233  if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2234  InstrOffs *= -1;
2235  NumBits = 8;
2236  break;
2237  }
2238  case ARMII::AddrMode4:
2239  case ARMII::AddrMode6:
2240  // Can't fold any offset even if it's zero.
2241  return false;
2242  case ARMII::AddrMode5: {
2243  ImmIdx = FrameRegIdx+1;
2244  InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2245  if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2246  InstrOffs *= -1;
2247  NumBits = 8;
2248  Scale = 4;
2249  break;
2250  }
2251  default:
2252  llvm_unreachable("Unsupported addressing mode!");
2253  }
2254 
2255  Offset += InstrOffs * Scale;
2256  assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2257  if (Offset < 0) {
2258  Offset = -Offset;
2259  isSub = true;
2260  }
2261 
2262  // Attempt to fold address comp. if opcode has offset bits
2263  if (NumBits > 0) {
2264  // Common case: small offset, fits into instruction.
2265  MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2266  int ImmedOffset = Offset / Scale;
2267  unsigned Mask = (1 << NumBits) - 1;
2268  if ((unsigned)Offset <= Mask * Scale) {
2269  // Replace the FrameIndex with sp
2270  MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2271  // FIXME: When addrmode2 goes away, this will simplify (like the
2272  // T2 version), as the LDR.i12 versions don't need the encoding
2273  // tricks for the offset value.
2274  if (isSub) {
2275  if (AddrMode == ARMII::AddrMode_i12)
2276  ImmedOffset = -ImmedOffset;
2277  else
2278  ImmedOffset |= 1 << NumBits;
2279  }
2280  ImmOp.ChangeToImmediate(ImmedOffset);
2281  Offset = 0;
2282  return true;
2283  }
2284 
2285  // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2286  ImmedOffset = ImmedOffset & Mask;
2287  if (isSub) {
2288  if (AddrMode == ARMII::AddrMode_i12)
2289  ImmedOffset = -ImmedOffset;
2290  else
2291  ImmedOffset |= 1 << NumBits;
2292  }
2293  ImmOp.ChangeToImmediate(ImmedOffset);
2294  Offset &= ~(Mask*Scale);
2295  }
2296  }
2297 
2298  Offset = (isSub) ? -Offset : Offset;
2299  return Offset == 0;
2300 }
2301 
2302 /// analyzeCompare - For a comparison instruction, return the source registers
2303 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2304 /// compares against in CmpValue. Return true if the comparison instruction
2305 /// can be analyzed.
2306 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
2307  unsigned &SrcReg2, int &CmpMask,
2308  int &CmpValue) const {
2309  switch (MI.getOpcode()) {
2310  default: break;
2311  case ARM::CMPri:
2312  case ARM::t2CMPri:
2313  case ARM::tCMPi8:
2314  SrcReg = MI.getOperand(0).getReg();
2315  SrcReg2 = 0;
2316  CmpMask = ~0;
2317  CmpValue = MI.getOperand(1).getImm();
2318  return true;
2319  case ARM::CMPrr:
2320  case ARM::t2CMPrr:
2321  SrcReg = MI.getOperand(0).getReg();
2322  SrcReg2 = MI.getOperand(1).getReg();
2323  CmpMask = ~0;
2324  CmpValue = 0;
2325  return true;
2326  case ARM::TSTri:
2327  case ARM::t2TSTri:
2328  SrcReg = MI.getOperand(0).getReg();
2329  SrcReg2 = 0;
2330  CmpMask = MI.getOperand(1).getImm();
2331  CmpValue = 0;
2332  return true;
2333  }
2334 
2335  return false;
2336 }
2337 
2338 /// isSuitableForMask - Identify a suitable 'and' instruction that
2339 /// operates on the given source register and applies the same mask
2340 /// as a 'tst' instruction. Provide a limited look-through for copies.
2341 /// When successful, MI will hold the found instruction.
2342 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2343  int CmpMask, bool CommonUse) {
2344  switch (MI->getOpcode()) {
2345  case ARM::ANDri:
2346  case ARM::t2ANDri:
2347  if (CmpMask != MI->getOperand(2).getImm())
2348  return false;
2349  if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2350  return true;
2351  break;
2352  }
2353 
2354  return false;
2355 }
2356 
2357 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2358 /// the condition code if we modify the instructions such that flags are
2359 /// set by MI(b,a).
2361  switch (CC) {
2362  default: return ARMCC::AL;
2363  case ARMCC::EQ: return ARMCC::EQ;
2364  case ARMCC::NE: return ARMCC::NE;
2365  case ARMCC::HS: return ARMCC::LS;
2366  case ARMCC::LO: return ARMCC::HI;
2367  case ARMCC::HI: return ARMCC::LO;
2368  case ARMCC::LS: return ARMCC::HS;
2369  case ARMCC::GE: return ARMCC::LE;
2370  case ARMCC::LT: return ARMCC::GT;
2371  case ARMCC::GT: return ARMCC::LT;
2372  case ARMCC::LE: return ARMCC::GE;
2373  }
2374 }
2375 
2376 /// isRedundantFlagInstr - check whether the first instruction, whose only
2377 /// purpose is to update flags, can be made redundant.
2378 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2379 /// CMPri can be made redundant by SUBri if the operands are the same.
2380 /// This function can be extended later on.
2381 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2382  unsigned SrcReg2, int ImmValue,
2383  MachineInstr *OI) {
2384  if ((CmpI->getOpcode() == ARM::CMPrr ||
2385  CmpI->getOpcode() == ARM::t2CMPrr) &&
2386  (OI->getOpcode() == ARM::SUBrr ||
2387  OI->getOpcode() == ARM::t2SUBrr) &&
2388  ((OI->getOperand(1).getReg() == SrcReg &&
2389  OI->getOperand(2).getReg() == SrcReg2) ||
2390  (OI->getOperand(1).getReg() == SrcReg2 &&
2391  OI->getOperand(2).getReg() == SrcReg)))
2392  return true;
2393 
2394  if ((CmpI->getOpcode() == ARM::CMPri ||
2395  CmpI->getOpcode() == ARM::t2CMPri) &&
2396  (OI->getOpcode() == ARM::SUBri ||
2397  OI->getOpcode() == ARM::t2SUBri) &&
2398  OI->getOperand(1).getReg() == SrcReg &&
2399  OI->getOperand(2).getImm() == ImmValue)
2400  return true;
2401  return false;
2402 }
2403 
2404 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2405 /// comparison into one that sets the zero bit in the flags register;
2406 /// Remove a redundant Compare instruction if an earlier instruction can set the
2407 /// flags in the same way as Compare.
2408 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2409 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2410 /// condition code of instructions which use the flags.
2412  MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
2413  int CmpValue, const MachineRegisterInfo *MRI) const {
2414  // Get the unique definition of SrcReg.
2415  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2416  if (!MI) return false;
2417 
2418  // Masked compares sometimes use the same register as the corresponding 'and'.
2419  if (CmpMask != ~0) {
2420  if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2421  MI = nullptr;
2423  UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2424  UI != UE; ++UI) {
2425  if (UI->getParent() != CmpInstr.getParent())
2426  continue;
2427  MachineInstr *PotentialAND = &*UI;
2428  if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2429  isPredicated(*PotentialAND))
2430  continue;
2431  MI = PotentialAND;
2432  break;
2433  }
2434  if (!MI) return false;
2435  }
2436  }
2437 
2438  // Get ready to iterate backward from CmpInstr.
2439  MachineBasicBlock::iterator I = CmpInstr, E = MI,
2440  B = CmpInstr.getParent()->begin();
2441 
2442  // Early exit if CmpInstr is at the beginning of the BB.
2443  if (I == B) return false;
2444 
2445  // There are two possible candidates which can be changed to set CPSR:
2446  // One is MI, the other is a SUB instruction.
2447  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2448  // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2449  MachineInstr *Sub = nullptr;
2450  if (SrcReg2 != 0)
2451  // MI is not a candidate for CMPrr.
2452  MI = nullptr;
2453  else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
2454  // Conservatively refuse to convert an instruction which isn't in the same
2455  // BB as the comparison.
2456  // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2457  // Thus we cannot return here.
2458  if (CmpInstr.getOpcode() == ARM::CMPri ||
2459  CmpInstr.getOpcode() == ARM::t2CMPri)
2460  MI = nullptr;
2461  else
2462  return false;
2463  }
2464 
2465  // Check that CPSR isn't set between the comparison instruction and the one we
2466  // want to change. At the same time, search for Sub.
2467  const TargetRegisterInfo *TRI = &getRegisterInfo();
2468  --I;
2469  for (; I != E; --I) {
2470  const MachineInstr &Instr = *I;
2471 
2472  if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2473  Instr.readsRegister(ARM::CPSR, TRI))
2474  // This instruction modifies or uses CPSR after the one we want to
2475  // change. We can't do this transformation.
2476  return false;
2477 
2478  // Check whether CmpInstr can be made redundant by the current instruction.
2479  if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2480  Sub = &*I;
2481  break;
2482  }
2483 
2484  if (I == B)
2485  // The 'and' is below the comparison instruction.
2486  return false;
2487  }
2488 
2489  // Return false if no candidates exist.
2490  if (!MI && !Sub)
2491  return false;
2492 
2493  // The single candidate is called MI.
2494  if (!MI) MI = Sub;
2495 
2496  // We can't use a predicated instruction - it doesn't always write the flags.
2497  if (isPredicated(*MI))
2498  return false;
2499 
2500  bool IsThumb1 = false;
2501  switch (MI->getOpcode()) {
2502  default: break;
2503  case ARM::tLSLri:
2504  case ARM::tLSRri:
2505  case ARM::tLSLrr:
2506  case ARM::tLSRrr:
2507  case ARM::tSUBrr:
2508  case ARM::tADDrr:
2509  case ARM::tADDi3:
2510  case ARM::tADDi8:
2511  case ARM::tSUBi3:
2512  case ARM::tSUBi8:
2513  IsThumb1 = true;
2515  case ARM::RSBrr:
2516  case ARM::RSBri:
2517  case ARM::RSCrr:
2518  case ARM::RSCri:
2519  case ARM::ADDrr:
2520  case ARM::ADDri:
2521  case ARM::ADCrr:
2522  case ARM::ADCri:
2523  case ARM::SUBrr:
2524  case ARM::SUBri:
2525  case ARM::SBCrr:
2526  case ARM::SBCri:
2527  case ARM::t2RSBri:
2528  case ARM::t2ADDrr:
2529  case ARM::t2ADDri:
2530  case ARM::t2ADCrr:
2531  case ARM::t2ADCri:
2532  case ARM::t2SUBrr:
2533  case ARM::t2SUBri:
2534  case ARM::t2SBCrr:
2535  case ARM::t2SBCri:
2536  case ARM::ANDrr:
2537  case ARM::ANDri:
2538  case ARM::t2ANDrr:
2539  case ARM::t2ANDri:
2540  case ARM::ORRrr:
2541  case ARM::ORRri:
2542  case ARM::t2ORRrr:
2543  case ARM::t2ORRri:
2544  case ARM::EORrr:
2545  case ARM::EORri:
2546  case ARM::t2EORrr:
2547  case ARM::t2EORri:
2548  case ARM::t2LSRri:
2549  case ARM::t2LSRrr:
2550  case ARM::t2LSLri:
2551  case ARM::t2LSLrr: {
2552  // Scan forward for the use of CPSR
2553  // When checking against MI: if it's a conditional code that requires
2554  // checking of the V bit or C bit, then this is not safe to do.
2555  // It is safe to remove CmpInstr if CPSR is redefined or killed.
2556  // If we are done with the basic block, we need to check whether CPSR is
2557  // live-out.
2559  OperandsToUpdate;
2560  bool isSafe = false;
2561  I = CmpInstr;
2562  E = CmpInstr.getParent()->end();
2563  while (!isSafe && ++I != E) {
2564  const MachineInstr &Instr = *I;
2565  for (unsigned IO = 0, EO = Instr.getNumOperands();
2566  !isSafe && IO != EO; ++IO) {
2567  const MachineOperand &MO = Instr.getOperand(IO);
2568  if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2569  isSafe = true;
2570  break;
2571  }
2572  if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2573  continue;
2574  if (MO.isDef()) {
2575  isSafe = true;
2576  break;
2577  }
2578  // Condition code is after the operand before CPSR except for VSELs.
2579  ARMCC::CondCodes CC;
2580  bool IsInstrVSel = true;
2581  switch (Instr.getOpcode()) {
2582  default:
2583  IsInstrVSel = false;
2584  CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2585  break;
2586  case ARM::VSELEQD:
2587  case ARM::VSELEQS:
2588  CC = ARMCC::EQ;
2589  break;
2590  case ARM::VSELGTD:
2591  case ARM::VSELGTS:
2592  CC = ARMCC::GT;
2593  break;
2594  case ARM::VSELGED:
2595  case ARM::VSELGES:
2596  CC = ARMCC::GE;
2597  break;
2598  case ARM::VSELVSS:
2599  case ARM::VSELVSD:
2600  CC = ARMCC::VS;
2601  break;
2602  }
2603 
2604  if (Sub) {
2606  if (NewCC == ARMCC::AL)
2607  return false;
2608  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2609  // on CMP needs to be updated to be based on SUB.
2610  // Push the condition code operands to OperandsToUpdate.
2611  // If it is safe to remove CmpInstr, the condition code of these
2612  // operands will be modified.
2613  if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2614  Sub->getOperand(2).getReg() == SrcReg) {
2615  // VSel doesn't support condition code update.
2616  if (IsInstrVSel)
2617  return false;
2618  OperandsToUpdate.push_back(
2619  std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2620  }
2621  } else {
2622  // No Sub, so this is x = <op> y, z; cmp x, 0.
2623  switch (CC) {
2624  case ARMCC::EQ: // Z
2625  case ARMCC::NE: // Z
2626  case ARMCC::MI: // N
2627  case ARMCC::PL: // N
2628  case ARMCC::AL: // none
2629  // CPSR can be used multiple times, we should continue.
2630  break;
2631  case ARMCC::HS: // C
2632  case ARMCC::LO: // C
2633  case ARMCC::VS: // V
2634  case ARMCC::VC: // V
2635  case ARMCC::HI: // C Z
2636  case ARMCC::LS: // C Z
2637  case ARMCC::GE: // N V
2638  case ARMCC::LT: // N V
2639  case ARMCC::GT: // Z N V
2640  case ARMCC::LE: // Z N V
2641  // The instruction uses the V bit or C bit which is not safe.
2642  return false;
2643  }
2644  }
2645  }
2646  }
2647 
2648  // If CPSR is not killed nor re-defined, we should check whether it is
2649  // live-out. If it is live-out, do not optimize.
2650  if (!isSafe) {
2651  MachineBasicBlock *MBB = CmpInstr.getParent();
2653  SE = MBB->succ_end(); SI != SE; ++SI)
2654  if ((*SI)->isLiveIn(ARM::CPSR))
2655  return false;
2656  }
2657 
2658  // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
2659  // set CPSR so this is represented as an explicit output)
2660  if (!IsThumb1) {
2661  MI->getOperand(5).setReg(ARM::CPSR);
2662  MI->getOperand(5).setIsDef(true);
2663  }
2664  assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
2665  CmpInstr.eraseFromParent();
2666 
2667  // Modify the condition code of operands in OperandsToUpdate.
2668  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2669  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2670  for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2671  OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2672  return true;
2673  }
2674  }
2675 
2676  return false;
2677 }
2678 
2680  unsigned Reg,
2681  MachineRegisterInfo *MRI) const {
2682  // Fold large immediates into add, sub, or, xor.
2683  unsigned DefOpc = DefMI.getOpcode();
2684  if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2685  return false;
2686  if (!DefMI.getOperand(1).isImm())
2687  // Could be t2MOVi32imm <ga:xx>
2688  return false;
2689 
2690  if (!MRI->hasOneNonDBGUse(Reg))
2691  return false;
2692 
2693  const MCInstrDesc &DefMCID = DefMI.getDesc();
2694  if (DefMCID.hasOptionalDef()) {
2695  unsigned NumOps = DefMCID.getNumOperands();
2696  const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
2697  if (MO.getReg() == ARM::CPSR && !MO.isDead())
2698  // If DefMI defines CPSR and it is not dead, it's obviously not safe
2699  // to delete DefMI.
2700  return false;
2701  }
2702 
2703  const MCInstrDesc &UseMCID = UseMI.getDesc();
2704  if (UseMCID.hasOptionalDef()) {
2705  unsigned NumOps = UseMCID.getNumOperands();
2706  if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
2707  // If the instruction sets the flag, do not attempt this optimization
2708  // since it may change the semantics of the code.
2709  return false;
2710  }
2711 
2712  unsigned UseOpc = UseMI.getOpcode();
2713  unsigned NewUseOpc = 0;
2714  uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
2715  uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2716  bool Commute = false;
2717  switch (UseOpc) {
2718  default: return false;
2719  case ARM::SUBrr:
2720  case ARM::ADDrr:
2721  case ARM::ORRrr:
2722  case ARM::EORrr:
2723  case ARM::t2SUBrr:
2724  case ARM::t2ADDrr:
2725  case ARM::t2ORRrr:
2726  case ARM::t2EORrr: {
2727  Commute = UseMI.getOperand(2).getReg() != Reg;
2728  switch (UseOpc) {
2729  default: break;
2730  case ARM::ADDrr:
2731  case ARM::SUBrr: {
2732  if (UseOpc == ARM::SUBrr && Commute)
2733  return false;
2734 
2735  // ADD/SUB are special because they're essentially the same operation, so
2736  // we can handle a larger range of immediates.
2737  if (ARM_AM::isSOImmTwoPartVal(ImmVal))
2738  NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
2739  else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
2740  ImmVal = -ImmVal;
2741  NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
2742  } else
2743  return false;
2744  SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2745  SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2746  break;
2747  }
2748  case ARM::ORRrr:
2749  case ARM::EORrr: {
2750  if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2751  return false;
2752  SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2753  SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2754  switch (UseOpc) {
2755  default: break;
2756  case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2757  case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2758  }
2759  break;
2760  }
2761  case ARM::t2ADDrr:
2762  case ARM::t2SUBrr: {
2763  if (UseOpc == ARM::t2SUBrr && Commute)
2764  return false;
2765 
2766  // ADD/SUB are special because they're essentially the same operation, so
2767  // we can handle a larger range of immediates.
2768  if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2769  NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
2770  else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
2771  ImmVal = -ImmVal;
2772  NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
2773  } else
2774  return false;
2775  SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2776  SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2777  break;
2778  }
2779  case ARM::t2ORRrr:
2780  case ARM::t2EORrr: {
2781  if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2782  return false;
2783  SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2784  SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2785  switch (UseOpc) {
2786  default: break;
2787  case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2788  case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2789  }
2790  break;
2791  }
2792  }
2793  }
2794  }
2795 
2796  unsigned OpIdx = Commute ? 2 : 1;
2797  unsigned Reg1 = UseMI.getOperand(OpIdx).getReg();
2798  bool isKill = UseMI.getOperand(OpIdx).isKill();
2799  unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2800  AddDefaultCC(
2801  AddDefaultPred(BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
2802  get(NewUseOpc), NewReg)
2803  .addReg(Reg1, getKillRegState(isKill))
2804  .addImm(SOImmValV1)));
2805  UseMI.setDesc(get(NewUseOpc));
2806  UseMI.getOperand(1).setReg(NewReg);
2807  UseMI.getOperand(1).setIsKill();
2808  UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
2809  DefMI.eraseFromParent();
2810  return true;
2811 }
2812 
2813 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2814  const MachineInstr &MI) {
2815  switch (MI.getOpcode()) {
2816  default: {
2817  const MCInstrDesc &Desc = MI.getDesc();
2818  int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2819  assert(UOps >= 0 && "bad # UOps");
2820  return UOps;
2821  }
2822 
2823  case ARM::LDRrs:
2824  case ARM::LDRBrs:
2825  case ARM::STRrs:
2826  case ARM::STRBrs: {
2827  unsigned ShOpVal = MI.getOperand(3).getImm();
2828  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2829  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2830  if (!isSub &&
2831  (ShImm == 0 ||
2832  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2833  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2834  return 1;
2835  return 2;
2836  }
2837 
2838  case ARM::LDRH:
2839  case ARM::STRH: {
2840  if (!MI.getOperand(2).getReg())
2841  return 1;
2842 
2843  unsigned ShOpVal = MI.getOperand(3).getImm();
2844  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2845  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2846  if (!isSub &&
2847  (ShImm == 0 ||
2848  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2849  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2850  return 1;
2851  return 2;
2852  }
2853 
2854  case ARM::LDRSB:
2855  case ARM::LDRSH:
2856  return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
2857 
2858  case ARM::LDRSB_POST:
2859  case ARM::LDRSH_POST: {
2860  unsigned Rt = MI.getOperand(0).getReg();
2861  unsigned Rm = MI.getOperand(3).getReg();
2862  return (Rt == Rm) ? 4 : 3;
2863  }
2864 
2865  case ARM::LDR_PRE_REG:
2866  case ARM::LDRB_PRE_REG: {
2867  unsigned Rt = MI.getOperand(0).getReg();
2868  unsigned Rm = MI.getOperand(3).getReg();
2869  if (Rt == Rm)
2870  return 3;
2871  unsigned ShOpVal = MI.getOperand(4).getImm();
2872  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2873  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2874  if (!isSub &&
2875  (ShImm == 0 ||
2876  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2877  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2878  return 2;
2879  return 3;
2880  }
2881 
2882  case ARM::STR_PRE_REG:
2883  case ARM::STRB_PRE_REG: {
2884  unsigned ShOpVal = MI.getOperand(4).getImm();
2885  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2886  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2887  if (!isSub &&
2888  (ShImm == 0 ||
2889  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2890  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2891  return 2;
2892  return 3;
2893  }
2894 
2895  case ARM::LDRH_PRE:
2896  case ARM::STRH_PRE: {
2897  unsigned Rt = MI.getOperand(0).getReg();
2898  unsigned Rm = MI.getOperand(3).getReg();
2899  if (!Rm)
2900  return 2;
2901  if (Rt == Rm)
2902  return 3;
2903  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
2904  }
2905 
2906  case ARM::LDR_POST_REG:
2907  case ARM::LDRB_POST_REG:
2908  case ARM::LDRH_POST: {
2909  unsigned Rt = MI.getOperand(0).getReg();
2910  unsigned Rm = MI.getOperand(3).getReg();
2911  return (Rt == Rm) ? 3 : 2;
2912  }
2913 
2914  case ARM::LDR_PRE_IMM:
2915  case ARM::LDRB_PRE_IMM:
2916  case ARM::LDR_POST_IMM:
2917  case ARM::LDRB_POST_IMM:
2918  case ARM::STRB_POST_IMM:
2919  case ARM::STRB_POST_REG:
2920  case ARM::STRB_PRE_IMM:
2921  case ARM::STRH_POST:
2922  case ARM::STR_POST_IMM:
2923  case ARM::STR_POST_REG:
2924  case ARM::STR_PRE_IMM:
2925  return 2;
2926 
2927  case ARM::LDRSB_PRE:
2928  case ARM::LDRSH_PRE: {
2929  unsigned Rm = MI.getOperand(3).getReg();
2930  if (Rm == 0)
2931  return 3;
2932  unsigned Rt = MI.getOperand(0).getReg();
2933  if (Rt == Rm)
2934  return 4;
2935  unsigned ShOpVal = MI.getOperand(4).getImm();
2936  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2937  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2938  if (!isSub &&
2939  (ShImm == 0 ||
2940  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2941  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2942  return 3;
2943  return 4;
2944  }
2945 
2946  case ARM::LDRD: {
2947  unsigned Rt = MI.getOperand(0).getReg();
2948  unsigned Rn = MI.getOperand(2).getReg();
2949  unsigned Rm = MI.getOperand(3).getReg();
2950  if (Rm)
2951  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
2952  : 3;
2953  return (Rt == Rn) ? 3 : 2;
2954  }
2955 
2956  case ARM::STRD: {
2957  unsigned Rm = MI.getOperand(3).getReg();
2958  if (Rm)
2959  return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
2960  : 3;
2961  return 2;
2962  }
2963 
2964  case ARM::LDRD_POST:
2965  case ARM::t2LDRD_POST:
2966  return 3;
2967 
2968  case ARM::STRD_POST:
2969  case ARM::t2STRD_POST:
2970  return 4;
2971 
2972  case ARM::LDRD_PRE: {
2973  unsigned Rt = MI.getOperand(0).getReg();
2974  unsigned Rn = MI.getOperand(3).getReg();
2975  unsigned Rm = MI.getOperand(4).getReg();
2976  if (Rm)
2977  return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
2978  : 4;
2979  return (Rt == Rn) ? 4 : 3;
2980  }
2981 
2982  case ARM::t2LDRD_PRE: {
2983  unsigned Rt = MI.getOperand(0).getReg();
2984  unsigned Rn = MI.getOperand(3).getReg();
2985  return (Rt == Rn) ? 4 : 3;
2986  }
2987 
2988  case ARM::STRD_PRE: {
2989  unsigned Rm = MI.getOperand(4).getReg();
2990  if (Rm)
2991  return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
2992  : 4;
2993  return 3;
2994  }
2995 
2996  case ARM::t2STRD_PRE:
2997  return 3;
2998 
2999  case ARM::t2LDR_POST:
3000  case ARM::t2LDRB_POST:
3001  case ARM::t2LDRB_PRE:
3002  case ARM::t2LDRSBi12:
3003  case ARM::t2LDRSBi8:
3004  case ARM::t2LDRSBpci:
3005  case ARM::t2LDRSBs:
3006  case ARM::t2LDRH_POST:
3007  case ARM::t2LDRH_PRE:
3008  case ARM::t2LDRSBT:
3009  case ARM::t2LDRSB_POST:
3010  case ARM::t2LDRSB_PRE:
3011  case ARM::t2LDRSH_POST:
3012  case ARM::t2LDRSH_PRE:
3013  case ARM::t2LDRSHi12:
3014  case ARM::t2LDRSHi8:
3015  case ARM::t2LDRSHpci:
3016  case ARM::t2LDRSHs:
3017  return 2;
3018 
3019  case ARM::t2LDRDi8: {
3020  unsigned Rt = MI.getOperand(0).getReg();
3021  unsigned Rn = MI.getOperand(2).getReg();
3022  return (Rt == Rn) ? 3 : 2;
3023  }
3024 
3025  case ARM::t2STRB_POST:
3026  case ARM::t2STRB_PRE:
3027  case ARM::t2STRBs:
3028  case ARM::t2STRDi8:
3029  case ARM::t2STRH_POST:
3030  case ARM::t2STRH_PRE:
3031  case ARM::t2STRHs:
3032  case ARM::t2STR_POST:
3033  case ARM::t2STR_PRE:
3034  case ARM::t2STRs:
3035  return 2;
3036  }
3037 }
3038 
3039 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
3040 // can't be easily determined return 0 (missing MachineMemOperand).
3041 //
3042 // FIXME: The current MachineInstr design does not support relying on machine
3043 // mem operands to determine the width of a memory access. Instead, we expect
3044 // the target to provide this information based on the instruction opcode and
3045 // operands. However, using MachineMemOperand is the best solution now for
3046 // two reasons:
3047 //
3048 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3049 // operands. This is much more dangerous than using the MachineMemOperand
3050 // sizes because CodeGen passes can insert/remove optional machine operands. In
3051 // fact, it's totally incorrect for preRA passes and appears to be wrong for
3052 // postRA passes as well.
3053 //
3054 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
3055 // machine model that calls this should handle the unknown (zero size) case.
3056 //
3057 // Long term, we should require a target hook that verifies MachineMemOperand
3058 // sizes during MC lowering. That target hook should be local to MC lowering
3059 // because we can't ensure that it is aware of other MI forms. Doing this will
3060 // ensure that MachineMemOperands are correctly propagated through all passes.
3062  unsigned Size = 0;
3064  E = MI.memoperands_end();
3065  I != E; ++I) {
3066  Size += (*I)->getSize();
3067  }
3068  return Size / 4;
3069 }
3070 
3071 static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,
3072  unsigned NumRegs) {
3073  unsigned UOps = 1 + NumRegs; // 1 for address computation.
3074  switch (Opc) {
3075  default:
3076  break;
3077  case ARM::VLDMDIA_UPD:
3078  case ARM::VLDMDDB_UPD:
3079  case ARM::VLDMSIA_UPD:
3080  case ARM::VLDMSDB_UPD:
3081  case ARM::VSTMDIA_UPD:
3082  case ARM::VSTMDDB_UPD:
3083  case ARM::VSTMSIA_UPD:
3084  case ARM::VSTMSDB_UPD:
3085  case ARM::LDMIA_UPD:
3086  case ARM::LDMDA_UPD:
3087  case ARM::LDMDB_UPD:
3088  case ARM::LDMIB_UPD:
3089  case ARM::STMIA_UPD:
3090  case ARM::STMDA_UPD:
3091  case ARM::STMDB_UPD:
3092  case ARM::STMIB_UPD:
3093  case ARM::tLDMIA_UPD:
3094  case ARM::tSTMIA_UPD:
3095  case ARM::t2LDMIA_UPD:
3096  case ARM::t2LDMDB_UPD:
3097  case ARM::t2STMIA_UPD:
3098  case ARM::t2STMDB_UPD:
3099  ++UOps; // One for base register writeback.
3100  break;
3101  case ARM::LDMIA_RET:
3102  case ARM::tPOP_RET:
3103  case ARM::t2LDMIA_RET:
3104  UOps += 2; // One for base reg wb, one for write to pc.
3105  break;
3106  }
3107  return UOps;
3108 }
3109 
3111  const MachineInstr &MI) const {
3112  if (!ItinData || ItinData->isEmpty())
3113  return 1;
3114 
3115  const MCInstrDesc &Desc = MI.getDesc();
3116  unsigned Class = Desc.getSchedClass();
3117  int ItinUOps = ItinData->getNumMicroOps(Class);
3118  if (ItinUOps >= 0) {
3119  if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3120  return getNumMicroOpsSwiftLdSt(ItinData, MI);
3121 
3122  return ItinUOps;
3123  }
3124 
3125  unsigned Opc = MI.getOpcode();
3126  switch (Opc) {
3127  default:
3128  llvm_unreachable("Unexpected multi-uops instruction!");
3129  case ARM::VLDMQIA:
3130  case ARM::VSTMQIA:
3131  return 2;
3132 
3133  // The number of uOps for load / store multiple are determined by the number
3134  // registers.
3135  //
3136  // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3137  // same cycle. The scheduling for the first load / store must be done
3138  // separately by assuming the address is not 64-bit aligned.
3139  //
3140  // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3141  // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3142  // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3143  case ARM::VLDMDIA:
3144  case ARM::VLDMDIA_UPD:
3145  case ARM::VLDMDDB_UPD:
3146  case ARM::VLDMSIA:
3147  case ARM::VLDMSIA_UPD:
3148  case ARM::VLDMSDB_UPD:
3149  case ARM::VSTMDIA:
3150  case ARM::VSTMDIA_UPD:
3151  case ARM::VSTMDDB_UPD:
3152  case ARM::VSTMSIA:
3153  case ARM::VSTMSIA_UPD:
3154  case ARM::VSTMSDB_UPD: {
3155  unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands();
3156  return (NumRegs / 2) + (NumRegs % 2) + 1;
3157  }
3158 
3159  case ARM::LDMIA_RET:
3160  case ARM::LDMIA:
3161  case ARM::LDMDA:
3162  case ARM::LDMDB:
3163  case ARM::LDMIB:
3164  case ARM::LDMIA_UPD:
3165  case ARM::LDMDA_UPD:
3166  case ARM::LDMDB_UPD:
3167  case ARM::LDMIB_UPD:
3168  case ARM::STMIA:
3169  case ARM::STMDA:
3170  case ARM::STMDB:
3171  case ARM::STMIB:
3172  case ARM::STMIA_UPD:
3173  case ARM::STMDA_UPD:
3174  case ARM::STMDB_UPD:
3175  case ARM::STMIB_UPD:
3176  case ARM::tLDMIA:
3177  case ARM::tLDMIA_UPD:
3178  case ARM::tSTMIA_UPD:
3179  case ARM::tPOP_RET:
3180  case ARM::tPOP:
3181  case ARM::tPUSH:
3182  case ARM::t2LDMIA_RET:
3183  case ARM::t2LDMIA:
3184  case ARM::t2LDMDB:
3185  case ARM::t2LDMIA_UPD:
3186  case ARM::t2LDMDB_UPD:
3187  case ARM::t2STMIA:
3188  case ARM::t2STMDB:
3189  case ARM::t2STMIA_UPD:
3190  case ARM::t2STMDB_UPD: {
3191  unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1;
3192  switch (Subtarget.getLdStMultipleTiming()) {
3194  return getNumMicroOpsSingleIssuePlusExtras(Opc, NumRegs);
3196  // Assume the worst.
3197  return NumRegs;
3199  if (NumRegs < 4)
3200  return 2;
3201  // 4 registers would be issued: 2, 2.
3202  // 5 registers would be issued: 2, 2, 1.
3203  unsigned UOps = (NumRegs / 2);
3204  if (NumRegs % 2)
3205  ++UOps;
3206  return UOps;
3207  }
3209  unsigned UOps = (NumRegs / 2);
3210  // If there are odd number of registers or if it's not 64-bit aligned,
3211  // then it takes an extra AGU (Address Generation Unit) cycle.
3212  if ((NumRegs % 2) || !MI.hasOneMemOperand() ||
3213  (*MI.memoperands_begin())->getAlignment() < 8)
3214  ++UOps;
3215  return UOps;
3216  }
3217  }
3218  }
3219  }
3220  llvm_unreachable("Didn't find the number of microops");
3221 }
3222 
3223 int
3224 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3225  const MCInstrDesc &DefMCID,
3226  unsigned DefClass,
3227  unsigned DefIdx, unsigned DefAlign) const {
3228  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3229  if (RegNo <= 0)
3230  // Def is the address writeback.
3231  return ItinData->getOperandCycle(DefClass, DefIdx);
3232 
3233  int DefCycle;
3234  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3235  // (regno / 2) + (regno % 2) + 1
3236  DefCycle = RegNo / 2 + 1;
3237  if (RegNo % 2)
3238  ++DefCycle;
3239  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3240  DefCycle = RegNo;
3241  bool isSLoad = false;
3242 
3243  switch (DefMCID.getOpcode()) {
3244  default: break;
3245  case ARM::VLDMSIA:
3246  case ARM::VLDMSIA_UPD:
3247  case ARM::VLDMSDB_UPD:
3248  isSLoad = true;
3249  break;
3250  }
3251 
3252  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3253  // then it takes an extra cycle.
3254  if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3255  ++DefCycle;
3256  } else {
3257  // Assume the worst.
3258  DefCycle = RegNo + 2;
3259  }
3260 
3261  return DefCycle;
3262 }
3263 
3264 int
3265 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3266  const MCInstrDesc &DefMCID,
3267  unsigned DefClass,
3268  unsigned DefIdx, unsigned DefAlign) const {
3269  int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3270  if (RegNo <= 0)
3271  // Def is the address writeback.
3272  return ItinData->getOperandCycle(DefClass, DefIdx);
3273 
3274  int DefCycle;
3275  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3276  // 4 registers would be issued: 1, 2, 1.
3277  // 5 registers would be issued: 1, 2, 2.
3278  DefCycle = RegNo / 2;
3279  if (DefCycle < 1)
3280  DefCycle = 1;
3281  // Result latency is issue cycle + 2: E2.
3282  DefCycle += 2;
3283  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3284  DefCycle = (RegNo / 2);
3285  // If there are odd number of registers or if it's not 64-bit aligned,
3286  // then it takes an extra AGU (Address Generation Unit) cycle.
3287  if ((RegNo % 2) || DefAlign < 8)
3288  ++DefCycle;
3289  // Result latency is AGU cycles + 2.
3290  DefCycle += 2;
3291  } else {
3292  // Assume the worst.
3293  DefCycle = RegNo + 2;
3294  }
3295 
3296  return DefCycle;
3297 }
3298 
3299 int
3300 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3301  const MCInstrDesc &UseMCID,
3302  unsigned UseClass,
3303  unsigned UseIdx, unsigned UseAlign) const {
3304  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3305  if (RegNo <= 0)
3306  return ItinData->getOperandCycle(UseClass, UseIdx);
3307 
3308  int UseCycle;
3309  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3310  // (regno / 2) + (regno % 2) + 1
3311  UseCycle = RegNo / 2 + 1;
3312  if (RegNo % 2)
3313  ++UseCycle;
3314  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3315  UseCycle = RegNo;
3316  bool isSStore = false;
3317 
3318  switch (UseMCID.getOpcode()) {
3319  default: break;
3320  case ARM::VSTMSIA:
3321  case ARM::VSTMSIA_UPD:
3322  case ARM::VSTMSDB_UPD:
3323  isSStore = true;
3324  break;
3325  }
3326 
3327  // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3328  // then it takes an extra cycle.
3329  if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3330  ++UseCycle;
3331  } else {
3332  // Assume the worst.
3333  UseCycle = RegNo + 2;
3334  }
3335 
3336  return UseCycle;
3337 }
3338 
3339 int
3340 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3341  const MCInstrDesc &UseMCID,
3342  unsigned UseClass,
3343  unsigned UseIdx, unsigned UseAlign) const {
3344  int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3345  if (RegNo <= 0)
3346  return ItinData->getOperandCycle(UseClass, UseIdx);
3347 
3348  int UseCycle;
3349  if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3350  UseCycle = RegNo / 2;
3351  if (UseCycle < 2)
3352  UseCycle = 2;
3353  // Read in E3.
3354  UseCycle += 2;
3355  } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3356  UseCycle = (RegNo / 2);
3357  // If there are odd number of registers or if it's not 64-bit aligned,
3358  // then it takes an extra AGU (Address Generation Unit) cycle.
3359  if ((RegNo % 2) || UseAlign < 8)
3360  ++UseCycle;
3361  } else {
3362  // Assume the worst.
3363  UseCycle = 1;
3364  }
3365  return UseCycle;
3366 }
3367 
3368 int
3370  const MCInstrDesc &DefMCID,
3371  unsigned DefIdx, unsigned DefAlign,
3372  const MCInstrDesc &UseMCID,
3373  unsigned UseIdx, unsigned UseAlign) const {
3374  unsigned DefClass = DefMCID.getSchedClass();
3375  unsigned UseClass = UseMCID.getSchedClass();
3376 
3377  if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3378  return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3379 
3380  // This may be a def / use of a variable_ops instruction, the operand
3381  // latency might be determinable dynamically. Let the target try to
3382  // figure it out.
3383  int DefCycle = -1;
3384  bool LdmBypass = false;
3385  switch (DefMCID.getOpcode()) {
3386  default:
3387  DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3388  break;
3389 
3390  case ARM::VLDMDIA:
3391  case ARM::VLDMDIA_UPD:
3392  case ARM::VLDMDDB_UPD:
3393  case ARM::VLDMSIA:
3394  case ARM::VLDMSIA_UPD:
3395  case ARM::VLDMSDB_UPD:
3396  DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3397  break;
3398 
3399  case ARM::LDMIA_RET:
3400  case ARM::LDMIA:
3401  case ARM::LDMDA:
3402  case ARM::LDMDB:
3403  case ARM::LDMIB:
3404  case ARM::LDMIA_UPD:
3405  case ARM::LDMDA_UPD:
3406  case ARM::LDMDB_UPD:
3407  case ARM::LDMIB_UPD:
3408  case ARM::tLDMIA:
3409  case ARM::tLDMIA_UPD:
3410  case ARM::tPUSH:
3411  case ARM::t2LDMIA_RET:
3412  case ARM::t2LDMIA:
3413  case ARM::t2LDMDB:
3414  case ARM::t2LDMIA_UPD:
3415  case ARM::t2LDMDB_UPD:
3416  LdmBypass = 1;
3417  DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3418  break;
3419  }
3420 
3421  if (DefCycle == -1)
3422  // We can't seem to determine the result latency of the def, assume it's 2.
3423  DefCycle = 2;
3424 
3425  int UseCycle = -1;
3426  switch (UseMCID.getOpcode()) {
3427  default:
3428  UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3429  break;
3430 
3431  case ARM::VSTMDIA:
3432  case ARM::VSTMDIA_UPD:
3433  case ARM::VSTMDDB_UPD:
3434  case ARM::VSTMSIA:
3435  case ARM::VSTMSIA_UPD:
3436  case ARM::VSTMSDB_UPD:
3437  UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3438  break;
3439 
3440  case ARM::STMIA:
3441  case ARM::STMDA:
3442  case ARM::STMDB:
3443  case ARM::STMIB:
3444  case ARM::STMIA_UPD:
3445  case ARM::STMDA_UPD:
3446  case ARM::STMDB_UPD:
3447  case ARM::STMIB_UPD:
3448  case ARM::tSTMIA_UPD:
3449  case ARM::tPOP_RET:
3450  case ARM::tPOP:
3451  case ARM::t2STMIA:
3452  case ARM::t2STMDB:
3453  case ARM::t2STMIA_UPD:
3454  case ARM::t2STMDB_UPD:
3455  UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3456  break;
3457  }
3458 
3459  if (UseCycle == -1)
3460  // Assume it's read in the first stage.
3461  UseCycle = 1;
3462 
3463  UseCycle = DefCycle - UseCycle + 1;
3464  if (UseCycle > 0) {
3465  if (LdmBypass) {
3466  // It's a variable_ops instruction so we can't use DefIdx here. Just use
3467  // first def operand.
3468  if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3469  UseClass, UseIdx))
3470  --UseCycle;
3471  } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3472  UseClass, UseIdx)) {
3473  --UseCycle;
3474  }
3475  }
3476 
3477  return UseCycle;
3478 }
3479 
3481  const MachineInstr *MI, unsigned Reg,
3482  unsigned &DefIdx, unsigned &Dist) {
3483  Dist = 0;
3484 
3487  assert(II->isInsideBundle() && "Empty bundle?");
3488 
3489  int Idx = -1;
3490  while (II->isInsideBundle()) {
3491  Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3492  if (Idx != -1)
3493  break;
3494  --II;
3495  ++Dist;
3496  }
3497 
3498  assert(Idx != -1 && "Cannot find bundled definition!");
3499  DefIdx = Idx;
3500  return &*II;
3501 }
3502 
3504  const MachineInstr &MI, unsigned Reg,
3505  unsigned &UseIdx, unsigned &Dist) {
3506  Dist = 0;
3507 
3509  assert(II->isInsideBundle() && "Empty bundle?");
3511 
3512  // FIXME: This doesn't properly handle multiple uses.
3513  int Idx = -1;
3514  while (II != E && II->isInsideBundle()) {
3515  Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3516  if (Idx != -1)
3517  break;
3518  if (II->getOpcode() != ARM::t2IT)
3519  ++Dist;
3520  ++II;
3521  }
3522 
3523  if (Idx == -1) {
3524  Dist = 0;
3525  return nullptr;
3526  }
3527 
3528  UseIdx = Idx;
3529  return &*II;
3530 }
3531 
3532 /// Return the number of cycles to add to (or subtract from) the static
3533 /// itinerary based on the def opcode and alignment. The caller will ensure that
3534 /// adjusted latency is at least one cycle.
3535 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3536  const MachineInstr &DefMI,
3537  const MCInstrDesc &DefMCID, unsigned DefAlign) {
3538  int Adjust = 0;
3539  if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3540  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3541  // variants are one cycle cheaper.
3542  switch (DefMCID.getOpcode()) {
3543  default: break;
3544  case ARM::LDRrs:
3545  case ARM::LDRBrs: {
3546  unsigned ShOpVal = DefMI.getOperand(3).getImm();
3547  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3548  if (ShImm == 0 ||
3549  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3550  --Adjust;
3551  break;
3552  }
3553  case ARM::t2LDRs:
3554  case ARM::t2LDRBs:
3555  case ARM::t2LDRHs:
3556  case ARM::t2LDRSHs: {
3557  // Thumb2 mode: lsl only.
3558  unsigned ShAmt = DefMI.getOperand(3).getImm();
3559  if (ShAmt == 0 || ShAmt == 2)
3560  --Adjust;
3561  break;
3562  }
3563  }
3564  } else if (Subtarget.isSwift()) {
3565  // FIXME: Properly handle all of the latency adjustments for address
3566  // writeback.
3567  switch (DefMCID.getOpcode()) {
3568  default: break;
3569  case ARM::LDRrs:
3570  case ARM::LDRBrs: {
3571  unsigned ShOpVal = DefMI.getOperand(3).getImm();
3572  bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3573  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3574  if (!isSub &&
3575  (ShImm == 0 ||
3576  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3577  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3578  Adjust -= 2;
3579  else if (!isSub &&
3580  ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3581  --Adjust;
3582  break;
3583  }
3584  case ARM::t2LDRs:
3585  case ARM::t2LDRBs:
3586  case ARM::t2LDRHs:
3587  case ARM::t2LDRSHs: {
3588  // Thumb2 mode: lsl only.
3589  unsigned ShAmt = DefMI.getOperand(3).getImm();
3590  if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3591  Adjust -= 2;
3592  break;
3593  }
3594  }
3595  }
3596 
3597  if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) {
3598  switch (DefMCID.getOpcode()) {
3599  default: break;
3600  case ARM::VLD1q8:
3601  case ARM::VLD1q16:
3602  case ARM::VLD1q32:
3603  case ARM::VLD1q64:
3604  case ARM::VLD1q8wb_fixed:
3605  case ARM::VLD1q16wb_fixed:
3606  case ARM::VLD1q32wb_fixed:
3607  case ARM::VLD1q64wb_fixed:
3608  case ARM::VLD1q8wb_register:
3609  case ARM::VLD1q16wb_register:
3610  case ARM::VLD1q32wb_register:
3611  case ARM::VLD1q64wb_register:
3612  case ARM::VLD2d8:
3613  case ARM::VLD2d16:
3614  case ARM::VLD2d32:
3615  case ARM::VLD2q8:
3616  case ARM::VLD2q16:
3617  case ARM::VLD2q32:
3618  case ARM::VLD2d8wb_fixed:
3619  case ARM::VLD2d16wb_fixed:
3620  case ARM::VLD2d32wb_fixed:
3621  case ARM::VLD2q8wb_fixed:
3622  case ARM::VLD2q16wb_fixed:
3623  case ARM::VLD2q32wb_fixed:
3624  case ARM::VLD2d8wb_register:
3625  case ARM::VLD2d16wb_register:
3626  case ARM::VLD2d32wb_register:
3627  case ARM::VLD2q8wb_register:
3628  case ARM::VLD2q16wb_register:
3629  case ARM::VLD2q32wb_register:
3630  case ARM::VLD3d8:
3631  case ARM::VLD3d16:
3632  case ARM::VLD3d32:
3633  case ARM::VLD1d64T:
3634  case ARM::VLD3d8_UPD:
3635  case ARM::VLD3d16_UPD:
3636  case ARM::VLD3d32_UPD:
3637  case ARM::VLD1d64Twb_fixed:
3638  case ARM::VLD1d64Twb_register:
3639  case ARM::VLD3q8_UPD:
3640  case ARM::VLD3q16_UPD:
3641  case ARM::VLD3q32_UPD:
3642  case ARM::VLD4d8:
3643  case ARM::VLD4d16:
3644  case ARM::VLD4d32:
3645  case ARM::VLD1d64Q:
3646  case ARM::VLD4d8_UPD:
3647  case ARM::VLD4d16_UPD:
3648  case ARM::VLD4d32_UPD:
3649  case ARM::VLD1d64Qwb_fixed:
3650  case ARM::VLD1d64Qwb_register:
3651  case ARM::VLD4q8_UPD:
3652  case ARM::VLD4q16_UPD:
3653  case ARM::VLD4q32_UPD:
3654  case ARM::VLD1DUPq8:
3655  case ARM::VLD1DUPq16:
3656  case ARM::VLD1DUPq32:
3657  case ARM::VLD1DUPq8wb_fixed:
3658  case ARM::VLD1DUPq16wb_fixed:
3659  case ARM::VLD1DUPq32wb_fixed:
3660  case ARM::VLD1DUPq8wb_register:
3661  case ARM::VLD1DUPq16wb_register:
3662  case ARM::VLD1DUPq32wb_register:
3663  case ARM::VLD2DUPd8:
3664  case ARM::VLD2DUPd16:
3665  case ARM::VLD2DUPd32:
3666  case ARM::VLD2DUPd8wb_fixed:
3667  case ARM::VLD2DUPd16wb_fixed:
3668  case ARM::VLD2DUPd32wb_fixed:
3669  case ARM::VLD2DUPd8wb_register:
3670  case ARM::VLD2DUPd16wb_register:
3671  case ARM::VLD2DUPd32wb_register:
3672  case ARM::VLD4DUPd8:
3673  case ARM::VLD4DUPd16:
3674  case ARM::VLD4DUPd32:
3675  case ARM::VLD4DUPd8_UPD:
3676  case ARM::VLD4DUPd16_UPD:
3677  case ARM::VLD4DUPd32_UPD:
3678  case ARM::VLD1LNd8:
3679  case ARM::VLD1LNd16:
3680  case ARM::VLD1LNd32:
3681  case ARM::VLD1LNd8_UPD:
3682  case ARM::VLD1LNd16_UPD:
3683  case ARM::VLD1LNd32_UPD:
3684  case ARM::VLD2LNd8:
3685  case ARM::VLD2LNd16:
3686  case ARM::VLD2LNd32:
3687  case ARM::VLD2LNq16:
3688  case ARM::VLD2LNq32:
3689  case ARM::VLD2LNd8_UPD:
3690  case ARM::VLD2LNd16_UPD:
3691  case ARM::VLD2LNd32_UPD:
3692  case ARM::VLD2LNq16_UPD:
3693  case ARM::VLD2LNq32_UPD:
3694  case ARM::VLD4LNd8:
3695  case ARM::VLD4LNd16:
3696  case ARM::VLD4LNd32:
3697  case ARM::VLD4LNq16:
3698  case ARM::VLD4LNq32:
3699  case ARM::VLD4LNd8_UPD:
3700  case ARM::VLD4LNd16_UPD:
3701  case ARM::VLD4LNd32_UPD:
3702  case ARM::VLD4LNq16_UPD:
3703  case ARM::VLD4LNq32_UPD:
3704  // If the address is not 64-bit aligned, the latencies of these
3705  // instructions increases by one.
3706  ++Adjust;
3707  break;
3708  }
3709  }
3710  return Adjust;
3711 }
3712 
3714  const MachineInstr &DefMI,
3715  unsigned DefIdx,
3716  const MachineInstr &UseMI,
3717  unsigned UseIdx) const {
3718  // No operand latency. The caller may fall back to getInstrLatency.
3719  if (!ItinData || ItinData->isEmpty())
3720  return -1;
3721 
3722  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
3723  unsigned Reg = DefMO.getReg();
3724 
3725  const MachineInstr *ResolvedDefMI = &DefMI;
3726  unsigned DefAdj = 0;
3727  if (DefMI.isBundle())
3728  ResolvedDefMI =
3729  getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
3730  if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() ||
3731  ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) {
3732  return 1;
3733  }
3734 
3735  const MachineInstr *ResolvedUseMI = &UseMI;
3736  unsigned UseAdj = 0;
3737  if (UseMI.isBundle()) {
3738  ResolvedUseMI =
3739  getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
3740  if (!ResolvedUseMI)
3741  return -1;
3742  }
3743 
3744  return getOperandLatencyImpl(
3745  ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
3746  Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
3747 }
3748 
3749 int ARMBaseInstrInfo::getOperandLatencyImpl(
3750  const InstrItineraryData *ItinData, const MachineInstr &DefMI,
3751  unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
3752  const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
3753  unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
3754  if (Reg == ARM::CPSR) {
3755  if (DefMI.getOpcode() == ARM::FMSTAT) {
3756  // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3757  return Subtarget.isLikeA9() ? 1 : 20;
3758  }
3759 
3760  // CPSR set and branch can be paired in the same cycle.
3761  if (UseMI.isBranch())
3762  return 0;
3763 
3764  // Otherwise it takes the instruction latency (generally one).
3765  unsigned Latency = getInstrLatency(ItinData, DefMI);
3766 
3767  // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3768  // its uses. Instructions which are otherwise scheduled between them may
3769  // incur a code size penalty (not able to use the CPSR setting 16-bit
3770  // instructions).
3771  if (Latency > 0 && Subtarget.isThumb2()) {
3772  const MachineFunction *MF = DefMI.getParent()->getParent();
3773  // FIXME: Use Function::optForSize().
3774  if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3775  --Latency;
3776  }
3777  return Latency;
3778  }
3779 
3780  if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
3781  return -1;
3782 
3783  unsigned DefAlign = DefMI.hasOneMemOperand()
3784  ? (*DefMI.memoperands_begin())->getAlignment()
3785  : 0;
3786  unsigned UseAlign = UseMI.hasOneMemOperand()
3787  ? (*UseMI.memoperands_begin())->getAlignment()
3788  : 0;
3789 
3790  // Get the itinerary's latency if possible, and handle variable_ops.
3791  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,
3792  UseIdx, UseAlign);
3793  // Unable to find operand latency. The caller may resort to getInstrLatency.
3794  if (Latency < 0)
3795  return Latency;
3796 
3797  // Adjust for IT block position.
3798  int Adj = DefAdj + UseAdj;
3799 
3800  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3801  Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3802  if (Adj >= 0 || (int)Latency > -Adj) {
3803  return Latency + Adj;
3804  }
3805  // Return the itinerary latency, which may be zero but not less than zero.
3806  return Latency;
3807 }
3808 
3809 int
3811  SDNode *DefNode, unsigned DefIdx,
3812  SDNode *UseNode, unsigned UseIdx) const {
3813  if (!DefNode->isMachineOpcode())
3814  return 1;
3815 
3816  const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3817 
3818  if (isZeroCost(DefMCID.Opcode))
3819  return 0;
3820 
3821  if (!ItinData || ItinData->isEmpty())
3822  return DefMCID.mayLoad() ? 3 : 1;
3823 
3824  if (!UseNode->isMachineOpcode()) {
3825  int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3826  int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
3827  int Threshold = 1 + Adj;
3828  return Latency <= Threshold ? 1 : Latency - Adj;
3829  }
3830 
3831  const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3832  const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3833  unsigned DefAlign = !DefMN->memoperands_empty()
3834  ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3835  const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3836  unsigned UseAlign = !UseMN->memoperands_empty()
3837  ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3838  int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3839  UseMCID, UseIdx, UseAlign);
3840 
3841  if (Latency > 1 &&
3842  (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3843  Subtarget.isCortexA7())) {
3844  // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3845  // variants are one cycle cheaper.
3846  switch (DefMCID.getOpcode()) {
3847  default: break;
3848  case ARM::LDRrs:
3849  case ARM::LDRBrs: {
3850  unsigned ShOpVal =
3851  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3852  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3853  if (ShImm == 0 ||
3854  (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3855  --Latency;
3856  break;
3857  }
3858  case ARM::t2LDRs:
3859  case ARM::t2LDRBs:
3860  case ARM::t2LDRHs:
3861  case ARM::t2LDRSHs: {
3862  // Thumb2 mode: lsl only.
3863  unsigned ShAmt =
3864  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3865  if (ShAmt == 0 || ShAmt == 2)
3866  --Latency;
3867  break;
3868  }
3869  }
3870  } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3871  // FIXME: Properly handle all of the latency adjustments for address
3872  // writeback.
3873  switch (DefMCID.getOpcode()) {
3874  default: break;
3875  case ARM::LDRrs:
3876  case ARM::LDRBrs: {
3877  unsigned ShOpVal =
3878  cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3879  unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3880  if (ShImm == 0 ||
3881  ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3882  ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3883  Latency -= 2;
3884  else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3885  --Latency;
3886  break;
3887  }
3888  case ARM::t2LDRs:
3889  case ARM::t2LDRBs:
3890  case ARM::t2LDRHs:
3891  case ARM::t2LDRSHs: {
3892  // Thumb2 mode: lsl 0-3 only.
3893  Latency -= 2;
3894  break;
3895  }
3896  }
3897  }
3898 
3899  if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment())
3900  switch (DefMCID.getOpcode()) {
3901  default: break;
3902  case ARM::VLD1q8:
3903  case ARM::VLD1q16:
3904  case ARM::VLD1q32:
3905  case ARM::VLD1q64:
3906  case ARM::VLD1q8wb_register:
3907  case ARM::VLD1q16wb_register:
3908  case ARM::VLD1q32wb_register:
3909  case ARM::VLD1q64wb_register:
3910  case ARM::VLD1q8wb_fixed:
3911  case ARM::VLD1q16wb_fixed:
3912  case ARM::VLD1q32wb_fixed:
3913  case ARM::VLD1q64wb_fixed:
3914  case ARM::VLD2d8:
3915  case ARM::VLD2d16:
3916  case ARM::VLD2d32:
3917  case ARM::VLD2q8Pseudo:
3918  case ARM::VLD2q16Pseudo:
3919  case ARM::VLD2q32Pseudo:
3920  case ARM::VLD2d8wb_fixed:
3921  case ARM::VLD2d16wb_fixed:
3922  case ARM::VLD2d32wb_fixed:
3923  case ARM::VLD2q8PseudoWB_fixed:
3924  case ARM::VLD2q16PseudoWB_fixed:
3925  case ARM::VLD2q32PseudoWB_fixed:
3926  case ARM::VLD2d8wb_register:
3927  case ARM::VLD2d16wb_register:
3928  case ARM::VLD2d32wb_register:
3929  case ARM::VLD2q8PseudoWB_register:
3930  case ARM::VLD2q16PseudoWB_register:
3931  case ARM::VLD2q32PseudoWB_register:
3932  case ARM::VLD3d8Pseudo:
3933  case ARM::VLD3d16Pseudo:
3934  case ARM::VLD3d32Pseudo:
3935  case ARM::VLD1d64TPseudo:
3936  case ARM::VLD1d64TPseudoWB_fixed:
3937  case ARM::VLD3d8Pseudo_UPD:
3938  case ARM::VLD3d16Pseudo_UPD:
3939  case ARM::VLD3d32Pseudo_UPD:
3940  case ARM::VLD3q8Pseudo_UPD:
3941  case ARM::VLD3q16Pseudo_UPD:
3942  case ARM::VLD3q32Pseudo_UPD:
3943  case ARM::VLD3q8oddPseudo:
3944  case ARM::VLD3q16oddPseudo:
3945  case ARM::VLD3q32oddPseudo:
3946  case ARM::VLD3q8oddPseudo_UPD:
3947  case ARM::VLD3q16oddPseudo_UPD:
3948  case ARM::VLD3q32oddPseudo_UPD:
3949  case ARM::VLD4d8Pseudo:
3950  case ARM::VLD4d16Pseudo:
3951  case ARM::VLD4d32Pseudo:
3952  case ARM::VLD1d64QPseudo:
3953  case ARM::VLD1d64QPseudoWB_fixed:
3954  case ARM::VLD4d8Pseudo_UPD:
3955  case ARM::VLD4d16Pseudo_UPD:
3956  case ARM::VLD4d32Pseudo_UPD:
3957  case ARM::VLD4q8Pseudo_UPD:
3958  case ARM::VLD4q16Pseudo_UPD:
3959  case ARM::VLD4q32Pseudo_UPD:
3960  case ARM::VLD4q8oddPseudo:
3961  case ARM::VLD4q16oddPseudo:
3962  case ARM::VLD4q32oddPseudo:
3963  case ARM::VLD4q8oddPseudo_UPD:
3964  case ARM::VLD4q16oddPseudo_UPD:
3965  case ARM::VLD4q32oddPseudo_UPD:
3966  case ARM::VLD1DUPq8:
3967  case ARM::VLD1DUPq16:
3968  case ARM::VLD1DUPq32:
3969  case ARM::VLD1DUPq8wb_fixed:
3970  case ARM::VLD1DUPq16wb_fixed:
3971  case ARM::VLD1DUPq32wb_fixed:
3972  case ARM::VLD1DUPq8wb_register:
3973  case ARM::VLD1DUPq16wb_register:
3974  case ARM::VLD1DUPq32wb_register:
3975  case ARM::VLD2DUPd8:
3976  case ARM::VLD2DUPd16:
3977  case ARM::VLD2DUPd32:
3978  case ARM::VLD2DUPd8wb_fixed:
3979  case ARM::VLD2DUPd16wb_fixed:
3980  case ARM::VLD2DUPd32wb_fixed:
3981  case ARM::VLD2DUPd8wb_register:
3982  case ARM::VLD2DUPd16wb_register:
3983  case ARM::VLD2DUPd32wb_register:
3984  case ARM::VLD4DUPd8Pseudo:
3985  case ARM::VLD4DUPd16Pseudo:
3986  case ARM::VLD4DUPd32Pseudo:
3987  case ARM::VLD4DUPd8Pseudo_UPD:
3988  case ARM::VLD4DUPd16Pseudo_UPD:
3989  case ARM::VLD4DUPd32Pseudo_UPD:
3990  case ARM::VLD1LNq8Pseudo:
3991  case ARM::VLD1LNq16Pseudo:
3992  case ARM::VLD1LNq32Pseudo:
3993  case ARM::VLD1LNq8Pseudo_UPD:
3994  case ARM::VLD1LNq16Pseudo_UPD:
3995  case ARM::VLD1LNq32Pseudo_UPD:
3996  case ARM::VLD2LNd8Pseudo:
3997  case ARM::VLD2LNd16Pseudo:
3998  case ARM::VLD2LNd32Pseudo:
3999  case ARM::VLD2LNq16Pseudo:
4000  case ARM::VLD2LNq32Pseudo:
4001  case ARM::VLD2LNd8Pseudo_UPD:
4002  case ARM::VLD2LNd16Pseudo_UPD:
4003  case ARM::VLD2LNd32Pseudo_UPD:
4004  case ARM::VLD2LNq16Pseudo_UPD:
4005  case ARM::VLD2LNq32Pseudo_UPD:
4006  case ARM::VLD4LNd8Pseudo:
4007  case ARM::VLD4LNd16Pseudo:
4008  case ARM::VLD4LNd32Pseudo:
4009  case ARM::VLD4LNq16Pseudo:
4010  case ARM::VLD4LNq32Pseudo:
4011  case ARM::VLD4LNd8Pseudo_UPD:
4012  case ARM::VLD4LNd16Pseudo_UPD:
4013  case ARM::VLD4LNd32Pseudo_UPD:
4014  case ARM::VLD4LNq16Pseudo_UPD:
4015  case ARM::VLD4LNq32Pseudo_UPD:
4016  // If the address is not 64-bit aligned, the latencies of these
4017  // instructions increases by one.
4018  ++Latency;
4019  break;
4020  }
4021 
4022  return Latency;
4023 }
4024 
4025 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4026  if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4027  MI.isImplicitDef())
4028  return 0;
4029 
4030  if (MI.isBundle())
4031  return 0;
4032 
4033  const MCInstrDesc &MCID = MI.getDesc();
4034 
4035  if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
4036  // When predicated, CPSR is an additional source operand for CPSR updating
4037  // instructions, this apparently increases their latencies.
4038  return 1;
4039  }
4040  return 0;
4041 }
4042 
4043 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4044  const MachineInstr &MI,
4045  unsigned *PredCost) const {
4046  if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4047  MI.isImplicitDef())
4048  return 1;
4049 
4050  // An instruction scheduler typically runs on unbundled instructions, however
4051  // other passes may query the latency of a bundled instruction.
4052  if (MI.isBundle()) {
4053  unsigned Latency = 0;
4056  while (++I != E && I->isInsideBundle()) {
4057  if (I->getOpcode() != ARM::t2IT)
4058  Latency += getInstrLatency(ItinData, *I, PredCost);
4059  }
4060  return Latency;
4061  }
4062 
4063  const MCInstrDesc &MCID = MI.getDesc();
4064  if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
4065  // When predicated, CPSR is an additional source operand for CPSR updating
4066  // instructions, this apparently increases their latencies.
4067  *PredCost = 1;
4068  }
4069  // Be sure to call getStageLatency for an empty itinerary in case it has a
4070  // valid MinLatency property.
4071  if (!ItinData)
4072  return MI.mayLoad() ? 3 : 1;
4073 
4074  unsigned Class = MCID.getSchedClass();
4075 
4076  // For instructions with variable uops, use uops as latency.
4077  if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4078  return getNumMicroOps(ItinData, MI);
4079 
4080  // For the common case, fall back on the itinerary's latency.
4081  unsigned Latency = ItinData->getStageLatency(Class);
4082 
4083  // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4084  unsigned DefAlign =
4085  MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlignment() : 0;
4086  int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign);
4087  if (Adj >= 0 || (int)Latency > -Adj) {
4088  return Latency + Adj;
4089  }
4090  return Latency;
4091 }
4092 
4093 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4094  SDNode *Node) const {
4095  if (!Node->isMachineOpcode())
4096  return 1;
4097 
4098  if (!ItinData || ItinData->isEmpty())
4099  return 1;
4100 
4101  unsigned Opcode = Node->getMachineOpcode();
4102  switch (Opcode) {
4103  default:
4104  return ItinData->getStageLatency(get(Opcode).getSchedClass());
4105  case ARM::VLDMQIA:
4106  case ARM::VSTMQIA:
4107  return 2;
4108  }
4109 }
4110 
4111 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4112  const MachineRegisterInfo *MRI,
4113  const MachineInstr &DefMI,
4114  unsigned DefIdx,
4115  const MachineInstr &UseMI,
4116  unsigned UseIdx) const {
4117  unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4118  unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4119  if (Subtarget.nonpipelinedVFP() &&
4120  (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4121  return true;
4122 
4123  // Hoist VFP / NEON instructions with 4 or higher latency.
4124  unsigned Latency =
4125  SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4126  if (Latency <= 3)
4127  return false;
4128  return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4129  UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4130 }
4131 
4132 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4133  const MachineInstr &DefMI,
4134  unsigned DefIdx) const {
4135  const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4136  if (!ItinData || ItinData->isEmpty())
4137  return false;
4138 
4139  unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4140  if (DDomain == ARMII::DomainGeneral) {
4141  unsigned DefClass = DefMI.getDesc().getSchedClass();
4142  int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4143  return (DefCycle != -1 && DefCycle <= 2);
4144  }
4145  return false;
4146 }
4147 
4148 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4149  StringRef &ErrInfo) const {
4150  if (convertAddSubFlagsOpcode(MI.getOpcode())) {
4151  ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4152  return false;
4153  }
4154  return true;
4155 }
4156 
4157 // LoadStackGuard has so far only been implemented for MachO. Different code
4158 // sequence is needed for other targets.
4160  unsigned LoadImmOpc,
4161  unsigned LoadOpc) const {
4162  assert(!Subtarget.isROPI() && !Subtarget.isRWPI() &&
4163  "ROPI/RWPI not currently supported with stack guard");
4164 
4165  MachineBasicBlock &MBB = *MI->getParent();
4166  DebugLoc DL = MI->getDebugLoc();
4167  unsigned Reg = MI->getOperand(0).getReg();
4168  const GlobalValue *GV =
4169  cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4170  MachineInstrBuilder MIB;
4171 
4172  BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4174 
4175  if (Subtarget.isGVIndirectSymbol(GV)) {
4176  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4177  MIB.addReg(Reg, RegState::Kill).addImm(0);
4181  MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4182  MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, 4);
4183  MIB.addMemOperand(MMO);
4184  AddDefaultPred(MIB);
4185  }
4186 
4187  MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4188  MIB.addReg(Reg, RegState::Kill).addImm(0);
4189  MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4190  AddDefaultPred(MIB);
4191 }
4192 
4193 bool
4194 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4195  unsigned &AddSubOpc,
4196  bool &NegAcc, bool &HasLane) const {
4197  DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4198  if (I == MLxEntryMap.end())
4199  return false;
4200 
4201  const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4202  MulOpc = Entry.MulOpc;
4203  AddSubOpc = Entry.AddSubOpc;
4204  NegAcc = Entry.NegAcc;
4205  HasLane = Entry.HasLane;
4206  return true;
4207 }
4208 
4209 //===----------------------------------------------------------------------===//
4210 // Execution domains.
4211 //===----------------------------------------------------------------------===//
4212 //
4213 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4214 // and some can go down both. The vmov instructions go down the VFP pipeline,
4215 // but they can be changed to vorr equivalents that are executed by the NEON
4216 // pipeline.
4217 //
4218 // We use the following execution domain numbering:
4219 //
4222  ExeVFP = 1,
4224 };
4225 //
4226 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4227 //
4228 std::pair<uint16_t, uint16_t>
4230  // If we don't have access to NEON instructions then we won't be able
4231  // to swizzle anything to the NEON domain. Check to make sure.
4232  if (Subtarget.hasNEON()) {
4233  // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4234  // if they are not predicated.
4235  if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI))
4236  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4237 
4238  // CortexA9 is particularly picky about mixing the two and wants these
4239  // converted.
4240  if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) &&
4241  (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR ||
4242  MI.getOpcode() == ARM::VMOVS))
4243  return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4244  }
4245  // No other instructions can be swizzled, so just determine their domain.
4246  unsigned Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
4247 
4248  if (Domain & ARMII::DomainNEON)
4249  return std::make_pair(ExeNEON, 0);
4250 
4251  // Certain instructions can go either way on Cortex-A8.
4252  // Treat them as NEON instructions.
4253  if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4254  return std::make_pair(ExeNEON, 0);
4255 
4256  if (Domain & ARMII::DomainVFP)
4257  return std::make_pair(ExeVFP, 0);
4258 
4259  return std::make_pair(ExeGeneric, 0);
4260 }
4261 
4263  unsigned SReg, unsigned &Lane) {
4264  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4265  Lane = 0;
4266 
4267  if (DReg != ARM::NoRegister)
4268  return DReg;
4269 
4270  Lane = 1;
4271  DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4272 
4273  assert(DReg && "S-register with no D super-register?");
4274  return DReg;
4275 }
4276 
4277 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4278 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4279 /// zero if no register needs to be defined as implicit-use.
4280 ///
4281 /// If the function cannot determine if an SPR should be marked implicit use or
4282 /// not, it returns false.
4283 ///
4284 /// This function handles cases where an instruction is being modified from taking
4285 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4286 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4287 /// lane of the DPR).
4288 ///
4289 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4290 /// (including the case where the DPR itself is defined), it should not.
4291 ///
4293  MachineInstr &MI, unsigned DReg,
4294  unsigned Lane, unsigned &ImplicitSReg) {
4295  // If the DPR is defined or used already, the other SPR lane will be chained
4296  // correctly, so there is nothing to be done.
4297  if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
4298  ImplicitSReg = 0;
4299  return true;
4300  }
4301 
4302  // Otherwise we need to go searching to see if the SPR is set explicitly.
4303  ImplicitSReg = TRI->getSubReg(DReg,
4304  (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4306  MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4307 
4308  if (LQR == MachineBasicBlock::LQR_Live)
4309  return true;
4310  else if (LQR == MachineBasicBlock::LQR_Unknown)
4311  return false;
4312 
4313  // If the register is known not to be live, there is no need to add an
4314  // implicit-use.
4315  ImplicitSReg = 0;
4316  return true;
4317 }
4318 
4320  unsigned Domain) const {
4321  unsigned DstReg, SrcReg, DReg;
4322  unsigned Lane;
4323  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4324  const TargetRegisterInfo *TRI = &getRegisterInfo();
4325  switch (MI.getOpcode()) {
4326  default:
4327  llvm_unreachable("cannot handle opcode!");
4328  break;
4329  case ARM::VMOVD:
4330  if (Domain != ExeNEON)
4331  break;
4332 
4333  // Zap the predicate operands.
4334  assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4335 
4336  // Make sure we've got NEON instructions.
4337  assert(Subtarget.hasNEON() && "VORRd requires NEON");
4338 
4339  // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4340  DstReg = MI.getOperand(0).getReg();
4341  SrcReg = MI.getOperand(1).getReg();
4342 
4343  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4344  MI.RemoveOperand(i - 1);
4345 
4346  // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4347  MI.setDesc(get(ARM::VORRd));
4349  MIB.addReg(DstReg, RegState::Define).addReg(SrcReg).addReg(SrcReg));
4350  break;
4351  case ARM::VMOVRS:
4352  if (Domain != ExeNEON)
4353  break;
4354  assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4355 
4356  // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4357  DstReg = MI.getOperand(0).getReg();
4358  SrcReg = MI.getOperand(1).getReg();
4359 
4360  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4361  MI.RemoveOperand(i - 1);
4362 
4363  DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4364 
4365  // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4366  // Note that DSrc has been widened and the other lane may be undef, which
4367  // contaminates the entire register.
4368  MI.setDesc(get(ARM::VGETLNi32));
4369  AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4370  .addReg(DReg, RegState::Undef)
4371  .addImm(Lane));
4372 
4373  // The old source should be an implicit use, otherwise we might think it
4374  // was dead before here.
4375  MIB.addReg(SrcReg, RegState::Implicit);
4376  break;
4377  case ARM::VMOVSR: {
4378  if (Domain != ExeNEON)
4379  break;
4380  assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4381 
4382  // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4383  DstReg = MI.getOperand(0).getReg();
4384  SrcReg = MI.getOperand(1).getReg();
4385 
4386  DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4387 
4388  unsigned ImplicitSReg;
4389  if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4390  break;
4391 
4392  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4393  MI.RemoveOperand(i - 1);
4394 
4395  // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4396  // Again DDst may be undefined at the beginning of this instruction.
4397  MI.setDesc(get(ARM::VSETLNi32));
4398  MIB.addReg(DReg, RegState::Define)
4399  .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
4400  .addReg(SrcReg)
4401  .addImm(Lane);
4402  AddDefaultPred(MIB);
4403 
4404  // The narrower destination must be marked as set to keep previous chains
4405  // in place.
4406  MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4407  if (ImplicitSReg != 0)
4408  MIB.addReg(ImplicitSReg, RegState::Implicit);
4409  break;
4410  }
4411  case ARM::VMOVS: {
4412  if (Domain != ExeNEON)
4413  break;
4414 
4415  // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4416  DstReg = MI.getOperand(0).getReg();
4417  SrcReg = MI.getOperand(1).getReg();
4418 
4419  unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4420  DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4421  DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4422 
4423  unsigned ImplicitSReg;
4424  if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4425  break;
4426 
4427  for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4428  MI.RemoveOperand(i - 1);
4429 
4430  if (DSrc == DDst) {
4431  // Destination can be:
4432  // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4433  MI.setDesc(get(ARM::VDUPLN32d));
4434  MIB.addReg(DDst, RegState::Define)
4435  .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
4436  .addImm(SrcLane);
4437  AddDefaultPred(MIB);
4438 
4439  // Neither the source or the destination are naturally represented any
4440  // more, so add them in manually.
4441  MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4442  MIB.addReg(SrcReg, RegState::Implicit);
4443  if (ImplicitSReg != 0)
4444  MIB.addReg(ImplicitSReg, RegState::Implicit);
4445  break;
4446  }
4447 
4448  // In general there's no single instruction that can perform an S <-> S
4449  // move in NEON space, but a pair of VEXT instructions *can* do the
4450  // job. It turns out that the VEXTs needed will only use DSrc once, with
4451  // the position based purely on the combination of lane-0 and lane-1
4452  // involved. For example
4453  // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4454  // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4455  // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4456  // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4457  //
4458  // Pattern of the MachineInstrs is:
4459  // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4460  MachineInstrBuilder NewMIB;
4461  NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
4462  DDst);
4463 
4464  // On the first instruction, both DSrc and DDst may be <undef> if present.
4465  // Specifically when the original instruction didn't have them as an
4466  // <imp-use>.
4467  unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4468  bool CurUndef = !MI.readsRegister(CurReg, TRI);
4469  NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4470 
4471  CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4472  CurUndef = !MI.readsRegister(CurReg, TRI);
4473  NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4474 
4475  NewMIB.addImm(1);
4476  AddDefaultPred(NewMIB);
4477 
4478  if (SrcLane == DstLane)
4479  NewMIB.addReg(SrcReg, RegState::Implicit);
4480 
4481  MI.setDesc(get(ARM::VEXTd32));
4482  MIB.addReg(DDst, RegState::Define);
4483 
4484  // On the second instruction, DDst has definitely been defined above, so
4485  // it is not <undef>. DSrc, if present, can be <undef> as above.
4486  CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4487  CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4488  MIB.addReg(CurReg, getUndefRegState(CurUndef));
4489 
4490  CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4491  CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4492  MIB.addReg(CurReg, getUndefRegState(CurUndef));
4493 
4494  MIB.addImm(1);
4495  AddDefaultPred(MIB);
4496 
4497  if (SrcLane != DstLane)
4498  MIB.addReg(SrcReg, RegState::Implicit);
4499 
4500  // As before, the original destination is no longer represented, add it
4501  // implicitly.
4502  MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4503  if (ImplicitSReg != 0)
4504  MIB.addReg(ImplicitSReg, RegState::Implicit);
4505  break;
4506  }
4507  }
4508 
4509 }
4510 
4511 //===----------------------------------------------------------------------===//
4512 // Partial register updates
4513 //===----------------------------------------------------------------------===//
4514 //
4515 // Swift renames NEON registers with 64-bit granularity. That means any
4516 // instruction writing an S-reg implicitly reads the containing D-reg. The
4517 // problem is mostly avoided by translating f32 operations to v2f32 operations
4518 // on D-registers, but f32 loads are still a problem.
4519 //
4520 // These instructions can load an f32 into a NEON register:
4521 //
4522 // VLDRS - Only writes S, partial D update.
4523 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4524 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4525 //
4526 // FCONSTD can be used as a dependency-breaking instruction.
4528  const MachineInstr &MI, unsigned OpNum,
4529  const TargetRegisterInfo *TRI) const {
4530  auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
4531  if (!PartialUpdateClearance)
4532  return 0;
4533 
4534  assert(TRI && "Need TRI instance");
4535 
4536  const MachineOperand &MO = MI.getOperand(OpNum);
4537  if (MO.readsReg())
4538  return 0;
4539  unsigned Reg = MO.getReg();
4540  int UseOp = -1;
4541 
4542  switch (MI.getOpcode()) {
4543  // Normal instructions writing only an S-register.
4544  case ARM::VLDRS:
4545  case ARM::FCONSTS:
4546  case ARM::VMOVSR:
4547  case ARM::VMOVv8i8:
4548  case ARM::VMOVv4i16:
4549  case ARM::VMOVv2i32:
4550  case ARM::VMOVv2f32:
4551  case ARM::VMOVv1i64:
4552  UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI);
4553  break;
4554 
4555  // Explicitly reads the dependency.
4556  case ARM::VLD1LNd32:
4557  UseOp = 3;
4558  break;
4559  default:
4560  return 0;
4561  }
4562 
4563  // If this instruction actually reads a value from Reg, there is no unwanted
4564  // dependency.
4565  if (UseOp != -1 && MI.getOperand(UseOp).readsReg())
4566  return 0;
4567 
4568  // We must be able to clobber the whole D-reg.
4570  // Virtual register must be a foo:ssub_0<def,undef> operand.
4571  if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
4572  return 0;
4573  } else if (ARM::SPRRegClass.contains(Reg)) {
4574  // Physical register: MI must define the full D-reg.
4575  unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4576  &ARM::DPRRegClass);
4577  if (!DReg || !MI.definesRegister(DReg, TRI))
4578  return 0;
4579  }
4580 
4581  // MI has an unwanted D-register dependency.
4582  // Avoid defs in the previous N instructrions.
4583  return PartialUpdateClearance;
4584 }
4585 
4586 // Break a partial register dependency after getPartialRegUpdateClearance
4587 // returned non-zero.
4589  MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4590  assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
4591  assert(TRI && "Need TRI instance");
4592 
4593  const MachineOperand &MO = MI.getOperand(OpNum);
4594  unsigned Reg = MO.getReg();
4596  "Can't break virtual register dependencies.");
4597  unsigned DReg = Reg;
4598 
4599  // If MI defines an S-reg, find the corresponding D super-register.
4600  if (ARM::SPRRegClass.contains(Reg)) {
4601  DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4602  assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4603  }
4604 
4605  assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4606  assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4607 
4608  // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4609  // the full D-register by loading the same value to both lanes. The
4610  // instruction is micro-coded with 2 uops, so don't do this until we can
4611  // properly schedule micro-coded instructions. The dispatcher stalls cause
4612  // too big regressions.
4613 
4614  // Insert the dependency-breaking FCONSTD before MI.
4615  // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4617  BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
4618  .addImm(96));
4619  MI.addRegisterKilled(DReg, TRI, true);
4620 }
4621 
4623  return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4624 }
4625 
4627  if (MI->getNumOperands() < 4)
4628  return true;
4629  unsigned ShOpVal = MI->getOperand(3).getImm();
4630  unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4631  // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4632  if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4633  ((ShImm == 1 || ShImm == 2) &&
4634  ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4635  return true;
4636 
4637  return false;
4638 }
4639 
4641  const MachineInstr &MI, unsigned DefIdx,
4642  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4643  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4644  assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4645 
4646  switch (MI.getOpcode()) {
4647  case ARM::VMOVDRR:
4648  // dX = VMOVDRR rY, rZ
4649  // is the same as:
4650  // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4651  // Populate the InputRegs accordingly.
4652  // rY
4653  const MachineOperand *MOReg = &MI.getOperand(1);
4654  InputRegs.push_back(
4655  RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4656  // rZ
4657  MOReg = &MI.getOperand(2);
4658  InputRegs.push_back(
4659  RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4660  return true;
4661  }
4662  llvm_unreachable("Target dependent opcode missing");
4663 }
4664 
4666  const MachineInstr &MI, unsigned DefIdx,
4667  RegSubRegPairAndIdx &InputReg) const {
4668  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4669  assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4670 
4671  switch (MI.getOpcode()) {
4672  case ARM::VMOVRRD:
4673  // rX, rY = VMOVRRD dZ
4674  // is the same as:
4675  // rX = EXTRACT_SUBREG dZ, ssub_0
4676  // rY = EXTRACT_SUBREG dZ, ssub_1
4677  const MachineOperand &MOReg = MI.getOperand(2);
4678  InputReg.Reg = MOReg.getReg();
4679  InputReg.SubReg = MOReg.getSubReg();
4680  InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4681  return true;
4682  }
4683  llvm_unreachable("Target dependent opcode missing");
4684 }
4685 
4687  const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4688  RegSubRegPairAndIdx &InsertedReg) const {
4689  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4690  assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4691 
4692  switch (MI.getOpcode()) {
4693  case ARM::VSETLNi32:
4694  // dX = VSETLNi32 dY, rZ, imm
4695  const MachineOperand &MOBaseReg = MI.getOperand(1);
4696  const MachineOperand &MOInsertedReg = MI.getOperand(2);
4697  const MachineOperand &MOIndex = MI.getOperand(3);
4698  BaseReg.Reg = MOBaseReg.getReg();
4699  BaseReg.SubReg = MOBaseReg.getSubReg();
4700 
4701  InsertedReg.Reg = MOInsertedReg.getReg();
4702  InsertedReg.SubReg = MOInsertedReg.getSubReg();
4703  InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4704  return true;
4705  }
4706  llvm_unreachable("Target dependent opcode missing");
4707 }
MachineConstantPoolValue * MachineCPVal
bool isPredicable(MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
bool isImplicit() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
virtual MachineInstr * duplicate(MachineInstr &Orig, MachineFunction &MF) const
Create a duplicate of the Orig instruction in MF.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
const GlobalValue * getGlobal() const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:226
bool isFPOnlySP() const
Definition: ARMSubtarget.h:471
instr_iterator instr_end()
static unsigned char getAM3Offset(unsigned AM3Opc)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:448
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
unsigned getMispredictionPenalty() const
size_t i
unsigned getRegister(unsigned i) const
Return the specified register in the class.
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
bool isCortexA8() const
Definition: ARMSubtarget.h:433
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:643
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Definition: MCInstrDesc.h:229
bool mayStore() const
Return true if this instruction could possibly modify memory.
Definition: MCInstrDesc.h:384
ARMConstantPoolValue - ARM specific constantpool value.
void setIsDef(bool Val=true)
Change a def to a use, or a use to a def.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
bool expandPostRAPseudo(MachineInstr &MI) const override
void setIsUndef(bool Val=true)
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg, int CmpMask, bool CommonUse)
isSuitableForMask - Identify a suitable 'and' instruction that operates on the given source register ...
bool isPredicated(const MachineInstr &MI) const override
bool isTied() const
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:478
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:873
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
bool hasV5TEOps() const
Definition: ARMSubtarget.h:416
bool isROPI() const
const char * getSymbolName() const
VarInfo - This represents the regions where a virtual register is live in the program.
Definition: LiveVariables.h:79
A debug info location.
Definition: DebugLoc.h:34
const SDValue & getOperand(unsigned Num) const
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:489
bool isThumb1Only() const
Definition: ARMSubtarget.h:577
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:464
static bool isThumb(const MCSubtargetInfo &STI)
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
static unsigned getSOImmValRotate(unsigned Imm)
getSOImmValRotate - Try to handle Imm with an immediate shifter operand, computing the rotate amount ...
bool restrictIT() const
Definition: ARMSubtarget.h:609
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:461
return AArch64::GPR64RegClass contains(Reg)
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:345
static unsigned rotr32(unsigned Val, unsigned Amt)
rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:376
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
Definition: LiveVariables.h:94
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:172
void clearKillInfo()
Clears kill flags on all operands.
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:70
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
A description of a memory reference used in the backend.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
mmo_iterator memoperands_begin() const
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:488
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isCall() const
Return true if the instruction is a call.
Definition: MCInstrDesc.h:242
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
bool memoperands_empty() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
void setIndex(int Idx)
The memory access is dereferenceable (i.e., doesn't trap).
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isUndef() const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
bool isThumb() const
Definition: ARMSubtarget.h:576
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
static unsigned getT2SOImmTwoPartFirst(unsigned Imm)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
static unsigned getAlignment(GlobalVariable *GV)
bool isKill() const
static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC)
getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:68
MachineBasicBlock * MBB
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
bool isV8EligibleForIT(InstrType *Instr)
Definition: ARMFeatures.h:25
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:819
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool hasNEON() const
Definition: ARMSubtarget.h:449
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
This class is a data container for one entry in a MachineConstantPool.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
static const ARM_MLxEntry ARM_MLxTable[]
unsigned getMatchingCondBranchOpcode(unsigned Opc)
ARM_MLxEntry - Record information about MLA / MLS instructions.
int64_t getImm() const
struct llvm::MachineOperand::@38::@39 Reg
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:487
unsigned getUndefRegState(bool B)
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been <def>ined and not <kill>ed as of just before Before...
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
Expected< const typename ELFT::Sym * > getSymbol(typename ELFT::SymRange Symbols, uint32_t Index)
Definition: Object/ELF.h:236
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
reverse_iterator rbegin()
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
static bool isCondBranchOpcode(int Opc)
bool IsCPSRDead< MachineInstr >(MachineInstr *MI)
bool isDebugValue() const
Definition: MachineInstr.h:777
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
bool isImplicitDef() const
Definition: MachineInstr.h:788
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:359
bool isInsertSubreg() const
Definition: MachineInstr.h:795
bool isBundle() const
Definition: MachineInstr.h:804
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
#define P(N)
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs)
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
unsigned const MachineRegisterInfo * MRI
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
const InstrItineraryData * getInstrItineraries() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
MachineInstrBuilder & UseMI
static unsigned char getAM5Offset(unsigned AM5Opc)
bool isMClass() const
Definition: ARMSubtarget.h:580
static unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:36
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:560
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
static bool isJumpTableBranchOpcode(int Opc)
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
virtual bool hasSameValue(ARMConstantPoolValue *ACPV)
hasSameValue - Return true if this ARM constpool value can share the same constantpool entry as anoth...
static bool isEligibleForITBlock(const MachineInstr *MI)
static unsigned getT2SOImmTwoPartSecond(unsigned Imm)
Register is known to be fully dead.
bool isCopy() const
Definition: MachineInstr.h:807
static const MachineInstr * getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr &MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist)
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool isPosition() const
Definition: MachineInstr.h:775
uint32_t Offset
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
void setImm(int64_t immVal)
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:373
MachineInstr * duplicate(MachineInstr &Orig, MachineFunction &MF) const override
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
int64_t getOffset() const
Return the offset from the symbol in this operand.
self_iterator getIterator()
Definition: ilist_node.h:81
static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI)
isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:80
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:136
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
LivenessQueryResult
Possible outcome of a register liveness query to computeRegisterLiveness()
Register is known to be (at least partially) live.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned getSubReg() const
VarInfo & getVarInfo(unsigned RegIdx)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static const MachineInstr * getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:645
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:895
bool isRWPI() const
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
The memory access writes data.
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:581
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:64
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
std::vector< MachineInstr * > Kills
Kills - List of MachineInstruction's which are the last use of this virtual register (kill it) in the...
Definition: LiveVariables.h:89
static AddrOpc getAM2Op(unsigned AM2Opc)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:865
ARMConstantPoolConstant - ARM-specific constant pool values for Constants, Functions, and BlockAddresses.
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static bool isIndirectBranchOpcode(int Opc)
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Iterator for intrusive lists based on ilist_node.
bool isSwift() const
Definition: ARMSubtarget.h:436
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false...
Definition: SmallPtrSet.h:375
static unsigned getAM2Offset(unsigned AM2Opc)
ARMConstantPoolSymbol - ARM-specific constantpool values for external symbols.
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI)
Create a copy of a const pool value.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Map pseudo instructions that imply an 'S' bit onto real opcodes.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
bool hasVFP2() const
Definition: ARMSubtarget.h:445
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:378
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
static bool isSOImmTwoPartVal(unsigned V)
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVa...
ARMConstantPoolMBB - ARM-specific constantpool value of a machine basic block.
const MachineInstrBuilder & addFrameIndex(int Idx) const
unsigned short Opcode
Definition: MCInstrDesc.h:165
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
bool isCortexA7() const
Definition: ARMSubtarget.h:432
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
static AddrOpc getAM3Op(unsigned AM3Opc)
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:567
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
int getOperandLatency(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Compute and return the use operand latency of a given itinerary class and operand index if the value ...
static int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ARMBaseInstrInfo(const ARMSubtarget &STI)
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:490
static bool isPopOpcode(int Opc)
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData, const MachineInstr &MI)
bool isSuperRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a super-register of RegA.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:210
Representation of each machine instruction.
Definition: MachineInstr.h:52
static MachineInstr * canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI, const TargetInstrInfo *TII)
Identify instructions that can be folded into a MOVCC instruction, and return the defining instructio...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static CondCodes getOppositeCondition(CondCodes CC)
Definition: ARMBaseInfo.h:47
static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[]
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:556
void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...
uint64_t scale(uint64_t Num) const
Scale a large integer.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isThumb2() const
Definition: ARMSubtarget.h:578
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Register liveness not decidable from local neighborhood.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, unsigned UseClass, unsigned UseIdx) const
Return true if there is a pipeline forwarding between instructions of itinerary classes DefClass and ...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
The memory access always returns the same value (or traps).
iterator end()
Definition: DenseMap.h:69
iterator find(const KeyT &Val)
Definition: DenseMap.h:127
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:477
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
static AddrOpc getAM5Op(unsigned AM5Opc)
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:649
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
static int const Threshold
TODO: Write a new FunctionPass AliasAnalysis so that it can keep a cache.
unsigned getReg() const
getReg - Returns the register number.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
ARMHazardRecognizer handles special constraints that are not expressed in the scheduling itinerary...
bool isLikeA9() const
Definition: ARMSubtarget.h:438
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
static unsigned getSORegOffset(unsigned Op)
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:73
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static use_instr_iterator use_instr_end()
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:312
bool hasImplicitDefOfPhysReg(unsigned Reg, const MCRegisterInfo *MRI=nullptr) const
Return true if this instruction implicitly defines the specified physical register.
Definition: MCInstrDesc.cpp:54
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:65
#define DEBUG(X)
Definition: Debug.h:100
const ARMSubtarget & getSubtarget() const
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
const std::vector< MachineConstantPoolEntry > & getConstants() const
IRTranslator LLVM IR MI
static int adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr &DefMI, const MCInstrDesc &DefMCID, unsigned DefAlign)
Return the number of cycles to add to (or subtract from) the static itinerary based on the def opcode...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:410
union llvm::MachineConstantPoolEntry::@35 Val
The constant itself.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
bool isRegSequence() const
Definition: MachineInstr.h:801
static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr &MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg)
getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane, set ImplicitSReg to a register n...
static bool isT2SOImmTwoPartVal(unsigned Imm)
static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc, unsigned NumRegs)
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
static unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:552
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isEmpty() const
Returns true if there are no itineraries.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:903
void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
static cl::opt< bool > EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, cl::desc("Enable ARM 2-addr to 3-addr conv"))
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
static ShiftOpc getSORegShOp(unsigned Op)
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
BranchProbability getCompl() const
static bool isCPSRDefined(const MachineInstr *MI)
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:358
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.