LLVM  4.0.0
Public Types | Public Member Functions | Protected Types | Protected Attributes | List of all members
llvm::ARMSubtarget Class Reference

#include <ARMSubtarget.h>

Inheritance diagram for llvm::ARMSubtarget:
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Collaboration diagram for llvm::ARMSubtarget:
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Public Types

enum  ARMLdStMultipleTiming { DoubleIssue, DoubleIssueCheckUnalignedAccess, SingleIssue, SingleIssuePlusExtras }
 What kind of timing do load multiple/store multiple instructions have. More...
 

Public Member Functions

 ARMSubtarget (const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
 This constructor initializes the data members to match that of the specified triple. More...
 
void setGISelAccessor (GISelAccessor &GISel)
 This object will take onwership of GISelAccessor. More...
 
unsigned getMaxInlineSizeThreshold () const
 getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call. More...
 
void ParseSubtargetFeatures (StringRef CPU, StringRef FS)
 ParseSubtargetFeatures - Parses features string setting specified subtarget options. More...
 
ARMSubtargetinitializeSubtargetDependencies (StringRef CPU, StringRef FS)
 initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization. More...
 
const ARMSelectionDAGInfogetSelectionDAGInfo () const override
 
const ARMBaseInstrInfogetInstrInfo () const override
 
const ARMTargetLoweringgetTargetLowering () const override
 
const ARMFrameLoweringgetFrameLowering () const override
 
const ARMBaseRegisterInfogetRegisterInfo () const override
 
const CallLoweringgetCallLowering () const override
 
const InstructionSelectorgetInstructionSelector () const override
 
const LegalizerInfogetLegalizerInfo () const override
 
const RegisterBankInfogetRegBankInfo () const override
 
void computeIssueWidth ()
 
bool hasV4TOps () const
 
bool hasV5TOps () const
 
bool hasV5TEOps () const
 
bool hasV6Ops () const
 
bool hasV6MOps () const
 
bool hasV6KOps () const
 
bool hasV6T2Ops () const
 
bool hasV7Ops () const
 
bool hasV8Ops () const
 
bool hasV8_1aOps () const
 
bool hasV8_2aOps () const
 
bool hasV8MBaselineOps () const
 
bool hasV8MMainlineOps () const
 
bool hasARMOps () const
 
bool hasVFP2 () const
 
bool hasVFP3 () const
 
bool hasVFP4 () const
 
bool hasFPARMv8 () const
 
bool hasNEON () const
 
bool hasCrypto () const
 
bool hasCRC () const
 
bool hasRAS () const
 
bool hasVirtualization () const
 
bool useNEONForSinglePrecisionFP () const
 
bool hasDivide () const
 
bool hasDivideInARMMode () const
 
bool hasT2ExtractPack () const
 
bool hasDataBarrier () const
 
bool hasV7Clrex () const
 
bool hasAcquireRelease () const
 
bool hasAnyDataBarrier () const
 
bool useMulOps () const
 
bool useFPVMLx () const
 
bool hasVMLxForwarding () const
 
bool isFPBrccSlow () const
 
bool isFPOnlySP () const
 
bool hasPerfMon () const
 
bool hasTrustZone () const
 
bool has8MSecExt () const
 
bool hasZeroCycleZeroing () const
 
bool hasFPAO () const
 
bool isProfitableToUnpredicate () const
 
bool hasSlowVGETLNi32 () const
 
bool hasSlowVDUP32 () const
 
bool preferVMOVSR () const
 
bool preferISHSTBarriers () const
 
bool expandMLx () const
 
bool hasVMLxHazards () const
 
bool hasSlowOddRegister () const
 
bool hasSlowLoadDSubregister () const
 
bool hasMuxedUnits () const
 
bool dontWidenVMOVS () const
 
bool useNEONForFPMovs () const
 
bool checkVLDnAccessAlignment () const
 
bool nonpipelinedVFP () const
 
bool prefers32BitThumb () const
 
bool avoidCPSRPartialUpdate () const
 
bool avoidMOVsShifterOperand () const
 
bool hasRetAddrStack () const
 
bool hasMPExtension () const
 
bool hasDSP () const
 
bool useNaClTrap () const
 
bool useSjLjEH () const
 
bool genLongCalls () const
 
bool genExecuteOnly () const
 
bool hasFP16 () const
 
bool hasD16 () const
 
bool hasFullFP16 () const
 
const TriplegetTargetTriple () const
 
bool isTargetDarwin () const
 
bool isTargetIOS () const
 
bool isTargetWatchOS () const
 
bool isTargetWatchABI () const
 
bool isTargetLinux () const
 
bool isTargetNaCl () const
 
bool isTargetNetBSD () const
 
bool isTargetWindows () const
 
bool isTargetCOFF () const
 
bool isTargetELF () const
 
bool isTargetMachO () const
 
bool isTargetAEABI () const
 
bool isTargetGNUAEABI () const
 
bool isTargetMuslAEABI () const
 
bool isTargetEHABICompatible () const
 
bool isTargetHardFloat () const
 
bool isTargetAndroid () const
 
virtual bool isXRaySupported () const override
 
bool isAPCS_ABI () const
 
bool isAAPCS_ABI () const
 
bool isAAPCS16_ABI () const
 
bool isROPI () const
 
bool isRWPI () const
 
bool useSoftFloat () const
 
bool isThumb () const
 
bool isThumb1Only () const
 
bool isThumb2 () const
 
bool hasThumb2 () const
 
bool isMClass () const
 
bool isRClass () const
 
bool isAClass () const
 
bool isR9Reserved () const
 
bool useR7AsFramePointer () const
 
bool splitFramePushPop (const MachineFunction &MF) const
 Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr. More...
 
bool useStride4VFPs (const MachineFunction &MF) const
 
bool useMovt (const MachineFunction &MF) const
 
bool supportsTailCall () const
 
bool allowsUnalignedMem () const
 
bool restrictIT () const
 
const std::string & getCPUString () const
 
bool isLittle () const
 
unsigned getMispredictionPenalty () const
 
bool hasSinCos () const
 This function returns true if the target has sincos() routine in its compiler runtime or math libraries. More...
 
bool enableMachineScheduler () const override
 Returns true if machine scheduler should be enabled. More...
 
bool enablePostRAScheduler () const override
 True for some subtargets at > -O0. More...
 
bool enableAtomicExpand () const override
 
const InstrItineraryDatagetInstrItineraryData () const override
 getInstrItins - Return the instruction itineraries based on subtarget selection. More...
 
unsigned getStackAlignment () const
 getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget. More...
 
unsigned getMaxInterleaveFactor () const
 
unsigned getPartialUpdateClearance () const
 
ARMLdStMultipleTiming getLdStMultipleTiming () const
 
int getPreISelOperandLatencyAdjustment () const
 
bool isGVIndirectSymbol (const GlobalValue *GV) const
 True if the GV will be accessed via an indirect symbol. More...
 
bool useFastISel () const
 True if fast-isel is used. More...
 
bool isCortexA5 () const
 
bool isCortexA7 () const
 
bool isCortexA8 () const
 
bool isCortexA9 () const
 
bool isCortexA15 () const
 
bool isSwift () const
 
bool isCortexM3 () const
 
bool isLikeA9 () const
 
bool isCortexR5 () const
 
bool isKrait () const
 

Protected Types

enum  ARMProcFamilyEnum {
  Others, CortexA5, CortexA7, CortexA8,
  CortexA9, CortexA12, CortexA15, CortexA17,
  CortexR4, CortexR4F, CortexR5, CortexR7,
  CortexR52, CortexM3, CortexA32, CortexA35,
  CortexA53, CortexA57, CortexA72, CortexA73,
  Krait, Swift, ExynosM1
}
 
enum  ARMProcClassEnum { None, AClass, RClass, MClass }
 
enum  ARMArchEnum {
  ARMv2, ARMv2a, ARMv3, ARMv3m,
  ARMv4, ARMv4t, ARMv5, ARMv5t,
  ARMv5te, ARMv5tej, ARMv6, ARMv6k,
  ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm,
  ARMv7a, ARMv7r, ARMv7m, ARMv7em,
  ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline,
  ARMv8mBaseline, ARMv8r
}
 

Protected Attributes

ARMProcFamilyEnum ARMProcFamily = Others
 ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. More...
 
ARMProcClassEnum ARMProcClass = None
 ARMProcClass - ARM processor class: None, AClass, RClass or MClass. More...
 
ARMArchEnum ARMArch = ARMv4t
 ARMArch - ARM architecture. More...
 
bool HasV4TOps = false
 HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants. More...
 
bool HasV5TOps = false
 
bool HasV5TEOps = false
 
bool HasV6Ops = false
 
bool HasV6MOps = false
 
bool HasV6KOps = false
 
bool HasV6T2Ops = false
 
bool HasV7Ops = false
 
bool HasV8Ops = false
 
bool HasV8_1aOps = false
 
bool HasV8_2aOps = false
 
bool HasV8MBaselineOps = false
 
bool HasV8MMainlineOps = false
 
bool HasVFPv2 = false
 HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported. More...
 
bool HasVFPv3 = false
 
bool HasVFPv4 = false
 
bool HasFPARMv8 = false
 
bool HasNEON = false
 
bool UseNEONForSinglePrecisionFP = false
 UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified. More...
 
bool UseMulOps = false
 UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used. More...
 
bool SlowFPVMLx = false
 SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them). More...
 
bool HasVMLxForwarding = false
 HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back. More...
 
bool SlowFPBrcc = false
 SlowFPBrcc - True if floating point compare + branch is slow. More...
 
bool InThumbMode = false
 InThumbMode - True if compiling for Thumb, false for ARM. More...
 
bool UseSoftFloat = false
 UseSoftFloat - True if we're using software floating point features. More...
 
bool HasThumb2 = false
 HasThumb2 - True if Thumb2 instructions are supported. More...
 
bool NoARM = false
 NoARM - True if subtarget does not support ARM mode execution. More...
 
bool ReserveR9 = false
 ReserveR9 - True if R9 is not available as a general purpose register. More...
 
bool NoMovt = false
 NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global addresses). More...
 
bool SupportsTailCall = false
 SupportsTailCall - True if the OS supports tail call. More...
 
bool HasFP16 = false
 HasFP16 - True if subtarget supports half-precision FP conversions. More...
 
bool HasFullFP16 = false
 HasFullFP16 - True if subtarget supports half-precision FP operations. More...
 
bool HasD16 = false
 HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3. More...
 
bool HasHardwareDivide = false
 HasHardwareDivide - True if subtarget supports [su]div. More...
 
bool HasHardwareDivideInARM = false
 HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode. More...
 
bool HasT2ExtractPack = false
 HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions. More...
 
bool HasDataBarrier = false
 HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions. More...
 
bool HasV7Clrex = false
 HasV7Clrex - True if the subtarget supports CLREX instructions. More...
 
bool HasAcquireRelease = false
 HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions. More...
 
bool Pref32BitThumb = false
 Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones. More...
 
bool AvoidCPSRPartialUpdate = false
 AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction. More...
 
bool AvoidMOVsShifterOperand = false
 AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e. More...
 
bool HasRetAddrStack = false
 HasRetAddrStack - Some processors perform return stack prediction. More...
 
bool HasMPExtension = false
 HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only). More...
 
bool HasVirtualization = false
 HasVirtualization - True if the subtarget supports the Virtualization extension. More...
 
bool FPOnlySP = false
 FPOnlySP - If true, the floating point unit only supports single precision. More...
 
bool HasPerfMon = false
 If true, the processor supports the Performance Monitor Extensions. More...
 
bool HasTrustZone = false
 HasTrustZone - if true, processor supports TrustZone security extensions. More...
 
bool Has8MSecExt = false
 Has8MSecExt - if true, processor supports ARMv8-M Security Extensions. More...
 
bool HasCrypto = false
 HasCrypto - if true, processor supports Cryptography extensions. More...
 
bool HasCRC = false
 HasCRC - if true, processor supports CRC instructions. More...
 
bool HasRAS = false
 HasRAS - if true, the processor supports RAS extensions. More...
 
bool HasZeroCycleZeroing = false
 If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register. More...
 
bool HasFPAO = false
 HasFPAO - if true, processor does positive address offset computation faster. More...
 
bool IsProfitableToUnpredicate = false
 If true, if conversion may decide to leave some instructions unpredicated. More...
 
bool HasSlowVGETLNi32 = false
 If true, VMOV will be favored over VGETLNi32. More...
 
bool HasSlowVDUP32 = false
 If true, VMOV will be favored over VDUP. More...
 
bool PreferVMOVSR = false
 If true, VMOVSR will be favored over VMOVDRR. More...
 
bool PreferISHST = false
 If true, ISHST barriers will be used for Release semantics. More...
 
bool SlowOddRegister = false
 If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than single VLDRS/VSTRS. More...
 
bool SlowLoadDSubregister = false
 If true, loading into a D subregister will be penalized. More...
 
bool HasMuxedUnits = false
 If true, the AGU and NEON/FPU units are multiplexed. More...
 
bool DontWidenVMOVS = false
 If true, VMOVS will never be widened to VMOVD. More...
 
bool ExpandMLx = false
 If true, run the MLx expansion pass. More...
 
bool HasVMLxHazards = false
 If true, VFP/NEON VMLA/VMLS have special RAW hazards. More...
 
bool UseNEONForFPMovs = false
 If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON. More...
 
bool CheckVLDnAlign = false
 If true, VLDn instructions take an extra cycle for unaligned accesses. More...
 
bool NonpipelinedVFP = false
 If true, VFP instructions are not pipelined. More...
 
bool StrictAlign = false
 StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types. More...
 
bool RestrictIT = false
 RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule. More...
 
bool HasDSP = false
 HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions. More...
 
bool UseNaClTrap = false
 NaCl TRAP instruction is generated instead of the regular TRAP. More...
 
bool GenLongCalls = false
 Generate calls via indirect call instructions. More...
 
bool GenExecuteOnly = false
 Generate code that does not contain data access to code sections. More...
 
bool UnsafeFPMath = false
 Target machine allowed unsafe FP math (such as use of NEON fp) More...
 
bool UseSjLjEH = false
 UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). More...
 
unsigned stackAlignment = 4
 stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function. More...
 
std::string CPUString
 CPUString - String name of used CPU. More...
 
unsigned MaxInterleaveFactor = 1
 
unsigned PartialUpdateClearance = 0
 Clearance before partial register updates (in number of instructions) More...
 
ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue
 What kind of timing do load multiple/store multiple have (double issue, single issue etc). More...
 
int PreISelOperandLatencyAdjustment = 2
 The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands. More...
 
bool IsLittle
 IsLittle - The target is Little Endian. More...
 
Triple TargetTriple
 TargetTriple - What processor and OS we're targeting. More...
 
MCSchedModel SchedModel
 SchedModel - Processor specific instruction costs. More...
 
InstrItineraryData InstrItins
 Selected instruction itineraries (one entry per itinerary class.) More...
 
const TargetOptionsOptions
 Options passed via command line that could influence the target. More...
 
const ARMBaseTargetMachineTM
 

Detailed Description

Definition at line 43 of file ARMSubtarget.h.

Member Enumeration Documentation

Enumerator
ARMv2 
ARMv2a 
ARMv3 
ARMv3m 
ARMv4 
ARMv4t 
ARMv5 
ARMv5t 
ARMv5te 
ARMv5tej 
ARMv6 
ARMv6k 
ARMv6kz 
ARMv6t2 
ARMv6m 
ARMv6sm 
ARMv7a 
ARMv7r 
ARMv7m 
ARMv7em 
ARMv8a 
ARMv81a 
ARMv82a 
ARMv8mMainline 
ARMv8mBaseline 
ARMv8r 

Definition at line 54 of file ARMSubtarget.h.

What kind of timing do load multiple/store multiple instructions have.

Enumerator
DoubleIssue 

Can load/store 2 registers/cycle.

DoubleIssueCheckUnalignedAccess 

Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.

SingleIssue 

Can load/store 1 register/cycle.

SingleIssuePlusExtras 

Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially also for register writeback.

Definition at line 63 of file ARMSubtarget.h.

Enumerator
None 
AClass 
RClass 
MClass 

Definition at line 51 of file ARMSubtarget.h.

Enumerator
Others 
CortexA5 
CortexA7 
CortexA8 
CortexA9 
CortexA12 
CortexA15 
CortexA17 
CortexR4 
CortexR4F 
CortexR5 
CortexR7 
CortexR52 
CortexM3 
CortexA32 
CortexA35 
CortexA53 
CortexA57 
CortexA72 
CortexA73 
Krait 
Swift 
ExynosM1 

Definition at line 45 of file ARMSubtarget.h.

Constructor & Destructor Documentation

ARMSubtarget::ARMSubtarget ( const Triple TT,
const std::string &  CPU,
const std::string &  FS,
const ARMBaseTargetMachine TM,
bool  IsLittle 
)

This constructor initializes the data members to match that of the specified triple.

Definition at line 93 of file ARMSubtarget.cpp.

Member Function Documentation

bool llvm::ARMSubtarget::allowsUnalignedMem ( ) const
inline

Definition at line 607 of file ARMSubtarget.h.

References StrictAlign.

Referenced by llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses().

bool llvm::ARMSubtarget::avoidCPSRPartialUpdate ( ) const
inline

Definition at line 492 of file ARMSubtarget.h.

References AvoidCPSRPartialUpdate.

bool llvm::ARMSubtarget::avoidMOVsShifterOperand ( ) const
inline

Definition at line 493 of file ARMSubtarget.h.

References AvoidMOVsShifterOperand.

bool llvm::ARMSubtarget::checkVLDnAccessAlignment ( ) const
inline

Definition at line 489 of file ARMSubtarget.h.

References CheckVLDnAlign.

Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().

void llvm::ARMSubtarget::computeIssueWidth ( )
bool llvm::ARMSubtarget::dontWidenVMOVS ( ) const
inline

Definition at line 487 of file ARMSubtarget.h.

References DontWidenVMOVS.

Referenced by llvm::ARMBaseInstrInfo::expandPostRAPseudo().

bool ARMSubtarget::enableAtomicExpand ( ) const
override

Definition at line 352 of file ARMSubtarget.cpp.

References hasAnyDataBarrier().

bool ARMSubtarget::enableMachineScheduler ( ) const
override

Returns true if machine scheduler should be enabled.

Definition at line 336 of file ARMSubtarget.cpp.

References isSwift().

bool ARMSubtarget::enablePostRAScheduler ( ) const
override

True for some subtargets at > -O0.

Definition at line 344 of file ARMSubtarget.cpp.

References hasThumb2(), isSwift(), and isThumb().

bool llvm::ARMSubtarget::expandMLx ( ) const
inline

Definition at line 482 of file ARMSubtarget.h.

References ExpandMLx.

bool llvm::ARMSubtarget::genExecuteOnly ( ) const
inline
bool llvm::ARMSubtarget::genLongCalls ( ) const
inline

Definition at line 499 of file ARMSubtarget.h.

References GenLongCalls.

const CallLowering * ARMSubtarget::getCallLowering ( ) const
override

Definition at line 109 of file ARMSubtarget.cpp.

References assert().

const std::string& llvm::ARMSubtarget::getCPUString ( ) const
inline

Definition at line 611 of file ARMSubtarget.h.

References CPUString.

Referenced by llvm::ARMTargetMachine::ARMTargetMachine().

const ARMFrameLowering* llvm::ARMSubtarget::getFrameLowering ( ) const
inlineoverride
const ARMBaseInstrInfo* llvm::ARMSubtarget::getInstrInfo ( ) const
inlineoverride
const InstrItineraryData* llvm::ARMSubtarget::getInstrItineraryData ( ) const
inlineoverride

getInstrItins - Return the instruction itineraries based on subtarget selection.

Definition at line 632 of file ARMSubtarget.h.

References InstrItins.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

const InstructionSelector * ARMSubtarget::getInstructionSelector ( ) const
override

Definition at line 114 of file ARMSubtarget.cpp.

References assert().

ARMLdStMultipleTiming llvm::ARMSubtarget::getLdStMultipleTiming ( ) const
inline

Definition at line 645 of file ARMSubtarget.h.

References LdStMultipleTiming.

Referenced by llvm::ARMBaseInstrInfo::getNumMicroOps().

const LegalizerInfo * ARMSubtarget::getLegalizerInfo ( ) const
override

Definition at line 119 of file ARMSubtarget.cpp.

References assert().

unsigned llvm::ARMSubtarget::getMaxInlineSizeThreshold ( ) const
inline

getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable to inline the call.

Definition at line 362 of file ARMSubtarget.h.

Referenced by llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy().

unsigned llvm::ARMSubtarget::getMaxInterleaveFactor ( ) const
inline

Definition at line 641 of file ARMSubtarget.h.

References MaxInterleaveFactor.

Referenced by llvm::ARMTTIImpl::getMaxInterleaveFactor().

unsigned ARMSubtarget::getMispredictionPenalty ( ) const
unsigned llvm::ARMSubtarget::getPartialUpdateClearance ( ) const
inline
int llvm::ARMSubtarget::getPreISelOperandLatencyAdjustment ( ) const
inline
const RegisterBankInfo * ARMSubtarget::getRegBankInfo ( ) const
override

Definition at line 124 of file ARMSubtarget.cpp.

References assert().

const ARMBaseRegisterInfo* llvm::ARMSubtarget::getRegisterInfo ( ) const
inlineoverride
const ARMSelectionDAGInfo* llvm::ARMSubtarget::getSelectionDAGInfo ( ) const
inlineoverride

Definition at line 373 of file ARMSubtarget.h.

unsigned llvm::ARMSubtarget::getStackAlignment ( ) const
inline

getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function for this subtarget.

Definition at line 639 of file ARMSubtarget.h.

References stackAlignment.

const ARMTargetLowering* llvm::ARMSubtarget::getTargetLowering ( ) const
inlineoverride
const Triple& llvm::ARMSubtarget::getTargetTriple ( ) const
inline
bool llvm::ARMSubtarget::has8MSecExt ( ) const
inline

Definition at line 474 of file ARMSubtarget.h.

References Has8MSecExt.

Referenced by getMClassRegisterMask().

bool llvm::ARMSubtarget::hasAcquireRelease ( ) const
inline

Definition at line 463 of file ARMSubtarget.h.

References HasAcquireRelease.

bool llvm::ARMSubtarget::hasAnyDataBarrier ( ) const
inline
bool llvm::ARMSubtarget::hasARMOps ( ) const
inline
bool llvm::ARMSubtarget::hasCRC ( ) const
inline

Definition at line 451 of file ARMSubtarget.h.

References HasCRC.

bool llvm::ARMSubtarget::hasCrypto ( ) const
inline

Definition at line 450 of file ARMSubtarget.h.

References HasCrypto.

bool llvm::ARMSubtarget::hasD16 ( ) const
inline

Definition at line 503 of file ARMSubtarget.h.

References HasD16.

Referenced by llvm::ARMBaseRegisterInfo::getReservedRegs().

bool llvm::ARMSubtarget::hasDataBarrier ( ) const
inline
bool llvm::ARMSubtarget::hasDivide ( ) const
inline

Definition at line 458 of file ARMSubtarget.h.

References HasHardwareDivide.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

bool llvm::ARMSubtarget::hasDivideInARMMode ( ) const
inline

Definition at line 459 of file ARMSubtarget.h.

References HasHardwareDivideInARM.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

bool llvm::ARMSubtarget::hasDSP ( ) const
inline
bool llvm::ARMSubtarget::hasFP16 ( ) const
inline

Definition at line 502 of file ARMSubtarget.h.

References HasFP16.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

bool llvm::ARMSubtarget::hasFPAO ( ) const
inline

Definition at line 476 of file ARMSubtarget.h.

References HasFPAO.

Referenced by llvm::ARMTargetLowering::getScalingFactorCost().

bool llvm::ARMSubtarget::hasFPARMv8 ( ) const
inline

Definition at line 448 of file ARMSubtarget.h.

References HasFPARMv8.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

bool llvm::ARMSubtarget::hasFullFP16 ( ) const
inline

Definition at line 504 of file ARMSubtarget.h.

References HasFullFP16.

bool llvm::ARMSubtarget::hasMPExtension ( ) const
inline

Definition at line 495 of file ARMSubtarget.h.

References HasMPExtension.

Referenced by LowerPREFETCH().

bool llvm::ARMSubtarget::hasMuxedUnits ( ) const
inline

Definition at line 486 of file ARMSubtarget.h.

References HasMuxedUnits.

Referenced by llvm::ARMHazardRecognizer::getHazardType().

bool llvm::ARMSubtarget::hasNEON ( ) const
inline
bool llvm::ARMSubtarget::hasPerfMon ( ) const
inline

Definition at line 472 of file ARMSubtarget.h.

References HasPerfMon.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

bool llvm::ARMSubtarget::hasRAS ( ) const
inline

Definition at line 452 of file ARMSubtarget.h.

References HasRAS.

bool llvm::ARMSubtarget::hasRetAddrStack ( ) const
inline

Definition at line 494 of file ARMSubtarget.h.

References HasRetAddrStack.

bool ARMSubtarget::hasSinCos ( ) const

This function returns true if the target has sincos() routine in its compiler runtime or math libraries.

Definition at line 331 of file ARMSubtarget.cpp.

References getTargetTriple(), llvm::Triple::isOSVersionLT(), isTargetIOS(), and isTargetWatchOS().

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

bool llvm::ARMSubtarget::hasSlowLoadDSubregister ( ) const
inline

Definition at line 485 of file ARMSubtarget.h.

References SlowLoadDSubregister.

Referenced by llvm::ARMTTIImpl::getVectorInstrCost().

bool llvm::ARMSubtarget::hasSlowOddRegister ( ) const
inline

Definition at line 484 of file ARMSubtarget.h.

References SlowOddRegister.

bool llvm::ARMSubtarget::hasSlowVDUP32 ( ) const
inline

Definition at line 479 of file ARMSubtarget.h.

References HasSlowVDUP32.

bool llvm::ARMSubtarget::hasSlowVGETLNi32 ( ) const
inline

Definition at line 478 of file ARMSubtarget.h.

References HasSlowVGETLNi32.

bool llvm::ARMSubtarget::hasT2ExtractPack ( ) const
inline

Definition at line 460 of file ARMSubtarget.h.

References HasT2ExtractPack.

Referenced by PerformORCombine().

bool llvm::ARMSubtarget::hasThumb2 ( ) const
inline

Definition at line 579 of file ARMSubtarget.h.

References HasThumb2.

Referenced by AddCombineTo64bitUMAAL(), and enablePostRAScheduler().

bool llvm::ARMSubtarget::hasTrustZone ( ) const
inline

Definition at line 473 of file ARMSubtarget.h.

References HasTrustZone.

bool llvm::ARMSubtarget::hasV4TOps ( ) const
inline

Definition at line 414 of file ARMSubtarget.h.

References HasV4TOps.

Referenced by getArchForCPU().

bool llvm::ARMSubtarget::hasV5TEOps ( ) const
inline
bool llvm::ARMSubtarget::hasV5TOps ( ) const
inline
bool llvm::ARMSubtarget::hasV6KOps ( ) const
inline

Definition at line 419 of file ARMSubtarget.h.

References HasV6KOps.

bool llvm::ARMSubtarget::hasV6MOps ( ) const
inline

Definition at line 418 of file ARMSubtarget.h.

References HasV6MOps.

Referenced by getArchForCPU().

bool llvm::ARMSubtarget::hasV6Ops ( ) const
inline
bool llvm::ARMSubtarget::hasV6T2Ops ( ) const
inline
bool llvm::ARMSubtarget::hasV7Clrex ( ) const
inline

Definition at line 462 of file ARMSubtarget.h.

References HasV7Clrex.

bool llvm::ARMSubtarget::hasV7Ops ( ) const
inline
bool llvm::ARMSubtarget::hasV8_1aOps ( ) const
inline

Definition at line 423 of file ARMSubtarget.h.

References HasV8_1aOps.

bool llvm::ARMSubtarget::hasV8_2aOps ( ) const
inline

Definition at line 424 of file ARMSubtarget.h.

References HasV8_2aOps.

bool llvm::ARMSubtarget::hasV8MBaselineOps ( ) const
inline
bool llvm::ARMSubtarget::hasV8MMainlineOps ( ) const
inline

Definition at line 426 of file ARMSubtarget.h.

References HasV8MMainlineOps.

Referenced by getArchForCPU(), getMClassRegisterMask(), and isV8M().

bool llvm::ARMSubtarget::hasV8Ops ( ) const
inline

Definition at line 422 of file ARMSubtarget.h.

References HasV8Ops.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and getArchForCPU().

bool llvm::ARMSubtarget::hasVFP2 ( ) const
inline
bool llvm::ARMSubtarget::hasVFP3 ( ) const
inline
bool llvm::ARMSubtarget::hasVFP4 ( ) const
inline

Definition at line 447 of file ARMSubtarget.h.

References HasVFPv4.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering().

bool llvm::ARMSubtarget::hasVirtualization ( ) const
inline

Definition at line 453 of file ARMSubtarget.h.

References HasVirtualization.

bool llvm::ARMSubtarget::hasVMLxForwarding ( ) const
inline

Definition at line 469 of file ARMSubtarget.h.

References HasVMLxForwarding.

Referenced by PerformVMULCombine().

bool llvm::ARMSubtarget::hasVMLxHazards ( ) const
inline

Definition at line 483 of file ARMSubtarget.h.

References HasVMLxHazards.

bool llvm::ARMSubtarget::hasZeroCycleZeroing ( ) const
inline

Definition at line 475 of file ARMSubtarget.h.

References HasZeroCycleZeroing.

ARMSubtarget & ARMSubtarget::initializeSubtargetDependencies ( StringRef  CPU,
StringRef  FS 
)

initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initializer lists for subtarget initialization.

Definition at line 72 of file ARMSubtarget.cpp.

bool ARMSubtarget::isAAPCS16_ABI ( ) const
bool ARMSubtarget::isAAPCS_ABI ( ) const
bool llvm::ARMSubtarget::isAClass ( ) const
inline

Definition at line 582 of file ARMSubtarget.h.

References AClass, and ARMProcClass.

bool ARMSubtarget::isAPCS_ABI ( ) const
bool llvm::ARMSubtarget::isCortexA15 ( ) const
inline

Definition at line 435 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA15.

Referenced by isLikeA9().

bool llvm::ARMSubtarget::isCortexA5 ( ) const
inline

These functions are obsolete, please consider adding subtarget features or properties instead of calling them.

Definition at line 431 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA5.

bool llvm::ARMSubtarget::isCortexA7 ( ) const
inline

Definition at line 432 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA7.

Referenced by adjustDefLatency(), and llvm::ARMBaseInstrInfo::getOperandLatency().

bool llvm::ARMSubtarget::isCortexA8 ( ) const
inline
bool llvm::ARMSubtarget::isCortexA9 ( ) const
inline

Definition at line 434 of file ARMSubtarget.h.

References ARMProcFamily, and CortexA9.

Referenced by isLikeA9().

bool llvm::ARMSubtarget::isCortexM3 ( ) const
inline

Definition at line 437 of file ARMSubtarget.h.

References ARMProcFamily, and CortexM3.

bool llvm::ARMSubtarget::isCortexR5 ( ) const
inline

Definition at line 439 of file ARMSubtarget.h.

References ARMProcFamily, and CortexR5.

bool llvm::ARMSubtarget::isFPBrccSlow ( ) const
inline

Definition at line 470 of file ARMSubtarget.h.

References SlowFPBrcc.

Referenced by canChangeToInt().

bool llvm::ARMSubtarget::isFPOnlySP ( ) const
inline
bool ARMSubtarget::isGVIndirectSymbol ( const GlobalValue GV) const
bool llvm::ARMSubtarget::isKrait ( ) const
inline

Definition at line 440 of file ARMSubtarget.h.

References ARMProcFamily, and Krait.

Referenced by isLikeA9().

bool llvm::ARMSubtarget::isLikeA9 ( ) const
inline
bool llvm::ARMSubtarget::isLittle ( ) const
inline
bool llvm::ARMSubtarget::isMClass ( ) const
inline
bool llvm::ARMSubtarget::isProfitableToUnpredicate ( ) const
inline
bool llvm::ARMSubtarget::isR9Reserved ( ) const
inline
bool llvm::ARMSubtarget::isRClass ( ) const
inline

Definition at line 581 of file ARMSubtarget.h.

References ARMProcClass, and RClass.

Referenced by getArchForCPU().

bool ARMSubtarget::isROPI ( ) const
bool ARMSubtarget::isRWPI ( ) const
bool llvm::ARMSubtarget::isSwift ( ) const
inline
bool llvm::ARMSubtarget::isTargetAEABI ( ) const
inline
bool llvm::ARMSubtarget::isTargetAndroid ( ) const
inline
bool llvm::ARMSubtarget::isTargetCOFF ( ) const
inline
bool llvm::ARMSubtarget::isTargetDarwin ( ) const
inline
bool llvm::ARMSubtarget::isTargetEHABICompatible ( ) const
inline
bool llvm::ARMSubtarget::isTargetELF ( ) const
inline
bool llvm::ARMSubtarget::isTargetGNUAEABI ( ) const
inline
bool llvm::ARMSubtarget::isTargetHardFloat ( ) const
inline
bool llvm::ARMSubtarget::isTargetIOS ( ) const
inline

Definition at line 509 of file ARMSubtarget.h.

References llvm::Triple::isiOS(), and TargetTriple.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), and hasSinCos().

bool llvm::ARMSubtarget::isTargetLinux ( ) const
inline
bool llvm::ARMSubtarget::isTargetMachO ( ) const
inline
bool llvm::ARMSubtarget::isTargetMuslAEABI ( ) const
inline
bool llvm::ARMSubtarget::isTargetNaCl ( ) const
inline

Definition at line 513 of file ARMSubtarget.h.

References llvm::Triple::isOSNaCl(), and TargetTriple.

Referenced by useFastISel().

bool llvm::ARMSubtarget::isTargetNetBSD ( ) const
inline

Definition at line 514 of file ARMSubtarget.h.

References llvm::Triple::isOSNetBSD(), and TargetTriple.

bool llvm::ARMSubtarget::isTargetWatchABI ( ) const
inline
bool llvm::ARMSubtarget::isTargetWatchOS ( ) const
inline
bool llvm::ARMSubtarget::isTargetWindows ( ) const
inline
bool llvm::ARMSubtarget::isThumb ( ) const
inline
bool llvm::ARMSubtarget::isThumb1Only ( ) const
inline
bool llvm::ARMSubtarget::isThumb2 ( ) const
inline
bool ARMSubtarget::isXRaySupported ( ) const
overridevirtual

Definition at line 129 of file ARMSubtarget.cpp.

References hasARMOps(), hasV6Ops(), and isTargetWindows().

bool llvm::ARMSubtarget::nonpipelinedVFP ( ) const
inline

Definition at line 490 of file ARMSubtarget.h.

References NonpipelinedVFP.

void llvm::ARMSubtarget::ParseSubtargetFeatures ( StringRef  CPU,
StringRef  FS 
)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

Definition of function is auto generated by tblgen.

bool llvm::ARMSubtarget::preferISHSTBarriers ( ) const
inline

Definition at line 481 of file ARMSubtarget.h.

References PreferISHST.

Referenced by llvm::ARMTargetLowering::emitLeadingFence(), and LowerATOMIC_FENCE().

bool llvm::ARMSubtarget::prefers32BitThumb ( ) const
inline

Definition at line 491 of file ARMSubtarget.h.

References Pref32BitThumb.

bool llvm::ARMSubtarget::preferVMOVSR ( ) const
inline

Definition at line 480 of file ARMSubtarget.h.

References PreferVMOVSR.

bool llvm::ARMSubtarget::restrictIT ( ) const
inline

Definition at line 609 of file ARMSubtarget.h.

References RestrictIT.

Referenced by llvm::ARMBaseInstrInfo::isPredicable().

void llvm::ARMSubtarget::setGISelAccessor ( GISelAccessor GISel)
inline

This object will take onwership of GISelAccessor.

Definition at line 358 of file ARMSubtarget.h.

bool llvm::ARMSubtarget::splitFramePushPop ( const MachineFunction MF) const
inline

Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent to lr.

This is always required on Thumb1-only targets, as the push and pop instructions can't access the high registers.

Definition at line 595 of file ARMSubtarget.h.

References llvm::TargetOptions::DisableFramePointerElim(), llvm::MachineFunction::getTarget(), isThumb1Only(), llvm::TargetMachine::Options, and useR7AsFramePointer().

Referenced by llvm::ARMFrameLowering::determineCalleeSaves(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), and llvm::ARMBaseRegisterInfo::getCalleeSavedRegs().

bool llvm::ARMSubtarget::supportsTailCall ( ) const
inline

Definition at line 605 of file ARMSubtarget.h.

References SupportsTailCall.

bool ARMSubtarget::useFastISel ( ) const
bool llvm::ARMSubtarget::useFPVMLx ( ) const
inline

Definition at line 468 of file ARMSubtarget.h.

References SlowFPVMLx.

bool ARMSubtarget::useMovt ( const MachineFunction MF) const
bool llvm::ARMSubtarget::useMulOps ( ) const
inline

Definition at line 467 of file ARMSubtarget.h.

References UseMulOps.

bool llvm::ARMSubtarget::useNaClTrap ( ) const
inline

Definition at line 497 of file ARMSubtarget.h.

References UseNaClTrap.

bool llvm::ARMSubtarget::useNEONForFPMovs ( ) const
inline

Definition at line 488 of file ARMSubtarget.h.

References UseNEONForFPMovs.

Referenced by llvm::ARMBaseInstrInfo::getExecutionDomain().

bool llvm::ARMSubtarget::useNEONForSinglePrecisionFP ( ) const
inline
bool llvm::ARMSubtarget::useR7AsFramePointer ( ) const
inline

Definition at line 588 of file ARMSubtarget.h.

References isTargetDarwin(), isTargetWindows(), and isThumb().

Referenced by getFramePointerReg(), and splitFramePushPop().

bool llvm::ARMSubtarget::useSjLjEH ( ) const
inline
bool llvm::ARMSubtarget::useSoftFloat ( ) const
inline
bool ARMSubtarget::useStride4VFPs ( const MachineFunction MF) const

Member Data Documentation

ARMArchEnum llvm::ARMSubtarget::ARMArch = ARMv4t
protected

ARMArch - ARM architecture.

Definition at line 84 of file ARMSubtarget.h.

ARMProcClassEnum llvm::ARMSubtarget::ARMProcClass = None
protected

ARMProcClass - ARM processor class: None, AClass, RClass or MClass.

Definition at line 81 of file ARMSubtarget.h.

Referenced by isAClass(), isMClass(), and isRClass().

ARMProcFamilyEnum llvm::ARMSubtarget::ARMProcFamily = Others
protected

ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.

Definition at line 78 of file ARMSubtarget.h.

Referenced by isCortexA15(), isCortexA5(), isCortexA7(), isCortexA8(), isCortexA9(), isCortexM3(), isCortexR5(), isKrait(), and isSwift().

bool llvm::ARMSubtarget::AvoidCPSRPartialUpdate = false
protected

AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR and add false dependency on the previous CPSR setting instruction.

Definition at line 193 of file ARMSubtarget.h.

Referenced by avoidCPSRPartialUpdate().

bool llvm::ARMSubtarget::AvoidMOVsShifterOperand = false
protected

AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand (i.e.

asr, lsl, lsr).

Definition at line 197 of file ARMSubtarget.h.

Referenced by avoidMOVsShifterOperand().

bool llvm::ARMSubtarget::CheckVLDnAlign = false
protected

If true, VLDn instructions take an extra cycle for unaligned accesses.

Definition at line 280 of file ARMSubtarget.h.

Referenced by checkVLDnAccessAlignment().

std::string llvm::ARMSubtarget::CPUString
protected

CPUString - String name of used CPU.

Definition at line 318 of file ARMSubtarget.h.

Referenced by getCPUString().

bool llvm::ARMSubtarget::DontWidenVMOVS = false
protected

If true, VMOVS will never be widened to VMOVD.

Definition at line 268 of file ARMSubtarget.h.

Referenced by dontWidenVMOVS().

bool llvm::ARMSubtarget::ExpandMLx = false
protected

If true, run the MLx expansion pass.

Definition at line 271 of file ARMSubtarget.h.

Referenced by expandMLx().

bool llvm::ARMSubtarget::FPOnlySP = false
protected

FPOnlySP - If true, the floating point unit only supports single precision.

Definition at line 213 of file ARMSubtarget.h.

Referenced by isFPOnlySP().

bool llvm::ARMSubtarget::GenExecuteOnly = false
protected

Generate code that does not contain data access to code sections.

Definition at line 305 of file ARMSubtarget.h.

Referenced by genExecuteOnly().

bool llvm::ARMSubtarget::GenLongCalls = false
protected

Generate calls via indirect call instructions.

Definition at line 302 of file ARMSubtarget.h.

Referenced by genLongCalls().

bool llvm::ARMSubtarget::Has8MSecExt = false
protected

Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.

Definition at line 224 of file ARMSubtarget.h.

Referenced by has8MSecExt().

bool llvm::ARMSubtarget::HasAcquireRelease = false
protected

HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.

Definition at line 184 of file ARMSubtarget.h.

Referenced by hasAcquireRelease().

bool llvm::ARMSubtarget::HasCRC = false
protected

HasCRC - if true, processor supports CRC instructions.

Definition at line 230 of file ARMSubtarget.h.

Referenced by hasCRC().

bool llvm::ARMSubtarget::HasCrypto = false
protected

HasCrypto - if true, processor supports Cryptography extensions.

Definition at line 227 of file ARMSubtarget.h.

Referenced by hasCrypto().

bool llvm::ARMSubtarget::HasD16 = false
protected

HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.

Definition at line 163 of file ARMSubtarget.h.

Referenced by hasD16().

bool llvm::ARMSubtarget::HasDataBarrier = false
protected

HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.

Definition at line 177 of file ARMSubtarget.h.

Referenced by hasAnyDataBarrier(), and hasDataBarrier().

bool llvm::ARMSubtarget::HasDSP = false
protected

HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.

Definition at line 296 of file ARMSubtarget.h.

Referenced by hasDSP().

bool llvm::ARMSubtarget::HasFP16 = false
protected

HasFP16 - True if subtarget supports half-precision FP conversions.

Definition at line 156 of file ARMSubtarget.h.

Referenced by hasFP16().

bool llvm::ARMSubtarget::HasFPAO = false
protected

HasFPAO - if true, processor does positive address offset computation faster.

Definition at line 240 of file ARMSubtarget.h.

Referenced by hasFPAO().

bool llvm::ARMSubtarget::HasFPARMv8 = false
protected

Definition at line 108 of file ARMSubtarget.h.

Referenced by hasFPARMv8().

bool llvm::ARMSubtarget::HasFullFP16 = false
protected

HasFullFP16 - True if subtarget supports half-precision FP operations.

Definition at line 159 of file ARMSubtarget.h.

Referenced by hasFullFP16().

bool llvm::ARMSubtarget::HasHardwareDivide = false
protected

HasHardwareDivide - True if subtarget supports [su]div.

Definition at line 166 of file ARMSubtarget.h.

Referenced by hasDivide().

bool llvm::ARMSubtarget::HasHardwareDivideInARM = false
protected

HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.

Definition at line 169 of file ARMSubtarget.h.

Referenced by hasDivideInARMMode().

bool llvm::ARMSubtarget::HasMPExtension = false
protected

HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).

Definition at line 205 of file ARMSubtarget.h.

Referenced by hasMPExtension().

bool llvm::ARMSubtarget::HasMuxedUnits = false
protected

If true, the AGU and NEON/FPU units are multiplexed.

Definition at line 265 of file ARMSubtarget.h.

Referenced by hasMuxedUnits().

bool llvm::ARMSubtarget::HasNEON = false
protected

Definition at line 109 of file ARMSubtarget.h.

Referenced by hasNEON().

bool llvm::ARMSubtarget::HasPerfMon = false
protected

If true, the processor supports the Performance Monitor Extensions.

These include a generic cycle-counter as well as more fine-grained (often implementation-specific) events.

Definition at line 218 of file ARMSubtarget.h.

Referenced by hasPerfMon().

bool llvm::ARMSubtarget::HasRAS = false
protected

HasRAS - if true, the processor supports RAS extensions.

Definition at line 233 of file ARMSubtarget.h.

Referenced by hasRAS().

bool llvm::ARMSubtarget::HasRetAddrStack = false
protected

HasRetAddrStack - Some processors perform return stack prediction.

CodeGen should avoid issue "normal" call instructions to callees which do not return.

Definition at line 201 of file ARMSubtarget.h.

Referenced by hasRetAddrStack().

bool llvm::ARMSubtarget::HasSlowVDUP32 = false
protected

If true, VMOV will be favored over VDUP.

Definition at line 249 of file ARMSubtarget.h.

Referenced by hasSlowVDUP32().

bool llvm::ARMSubtarget::HasSlowVGETLNi32 = false
protected

If true, VMOV will be favored over VGETLNi32.

Definition at line 246 of file ARMSubtarget.h.

Referenced by hasSlowVGETLNi32().

bool llvm::ARMSubtarget::HasT2ExtractPack = false
protected

HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.

Definition at line 173 of file ARMSubtarget.h.

Referenced by hasT2ExtractPack().

bool llvm::ARMSubtarget::HasThumb2 = false
protected

HasThumb2 - True if Thumb2 instructions are supported.

Definition at line 138 of file ARMSubtarget.h.

Referenced by hasThumb2(), isThumb1Only(), and isThumb2().

bool llvm::ARMSubtarget::HasTrustZone = false
protected

HasTrustZone - if true, processor supports TrustZone security extensions.

Definition at line 221 of file ARMSubtarget.h.

Referenced by hasTrustZone().

bool llvm::ARMSubtarget::HasV4TOps = false
protected

HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.

Definition at line 89 of file ARMSubtarget.h.

Referenced by hasV4TOps().

bool llvm::ARMSubtarget::HasV5TEOps = false
protected

Definition at line 91 of file ARMSubtarget.h.

Referenced by hasV5TEOps().

bool llvm::ARMSubtarget::HasV5TOps = false
protected

Definition at line 90 of file ARMSubtarget.h.

Referenced by hasV5TOps().

bool llvm::ARMSubtarget::HasV6KOps = false
protected

Definition at line 94 of file ARMSubtarget.h.

Referenced by hasV6KOps().

bool llvm::ARMSubtarget::HasV6MOps = false
protected

Definition at line 93 of file ARMSubtarget.h.

Referenced by hasV6MOps().

bool llvm::ARMSubtarget::HasV6Ops = false
protected

Definition at line 92 of file ARMSubtarget.h.

Referenced by hasV6Ops(), and isR9Reserved().

bool llvm::ARMSubtarget::HasV6T2Ops = false
protected

Definition at line 95 of file ARMSubtarget.h.

Referenced by hasV6T2Ops().

bool llvm::ARMSubtarget::HasV7Clrex = false
protected

HasV7Clrex - True if the subtarget supports CLREX instructions.

Definition at line 180 of file ARMSubtarget.h.

Referenced by hasV7Clrex().

bool llvm::ARMSubtarget::HasV7Ops = false
protected

Definition at line 96 of file ARMSubtarget.h.

Referenced by hasV7Ops().

bool llvm::ARMSubtarget::HasV8_1aOps = false
protected

Definition at line 98 of file ARMSubtarget.h.

Referenced by hasV8_1aOps().

bool llvm::ARMSubtarget::HasV8_2aOps = false
protected

Definition at line 99 of file ARMSubtarget.h.

Referenced by hasV8_2aOps().

bool llvm::ARMSubtarget::HasV8MBaselineOps = false
protected

Definition at line 100 of file ARMSubtarget.h.

Referenced by hasV8MBaselineOps().

bool llvm::ARMSubtarget::HasV8MMainlineOps = false
protected

Definition at line 101 of file ARMSubtarget.h.

Referenced by hasV8MMainlineOps().

bool llvm::ARMSubtarget::HasV8Ops = false
protected

Definition at line 97 of file ARMSubtarget.h.

Referenced by hasV8Ops().

bool llvm::ARMSubtarget::HasVFPv2 = false
protected

HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported.

Definition at line 105 of file ARMSubtarget.h.

Referenced by hasVFP2().

bool llvm::ARMSubtarget::HasVFPv3 = false
protected

Definition at line 106 of file ARMSubtarget.h.

Referenced by hasVFP3().

bool llvm::ARMSubtarget::HasVFPv4 = false
protected

Definition at line 107 of file ARMSubtarget.h.

Referenced by hasVFP4().

bool llvm::ARMSubtarget::HasVirtualization = false
protected

HasVirtualization - True if the subtarget supports the Virtualization extension.

Definition at line 209 of file ARMSubtarget.h.

Referenced by hasVirtualization().

bool llvm::ARMSubtarget::HasVMLxForwarding = false
protected

HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla being issued back to back.

Definition at line 126 of file ARMSubtarget.h.

Referenced by hasVMLxForwarding().

bool llvm::ARMSubtarget::HasVMLxHazards = false
protected

If true, VFP/NEON VMLA/VMLS have special RAW hazards.

Definition at line 274 of file ARMSubtarget.h.

Referenced by hasVMLxHazards().

bool llvm::ARMSubtarget::HasZeroCycleZeroing = false
protected

If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroing a VFP register.

Definition at line 237 of file ARMSubtarget.h.

Referenced by hasZeroCycleZeroing().

InstrItineraryData llvm::ARMSubtarget::InstrItins
protected

Selected instruction itineraries (one entry per itinerary class.)

Definition at line 343 of file ARMSubtarget.h.

Referenced by getInstrItineraryData().

bool llvm::ARMSubtarget::InThumbMode = false
protected

InThumbMode - True if compiling for Thumb, false for ARM.

Definition at line 132 of file ARMSubtarget.h.

Referenced by isThumb(), isThumb1Only(), and isThumb2().

bool llvm::ARMSubtarget::IsLittle
protected

IsLittle - The target is Little Endian.

Definition at line 334 of file ARMSubtarget.h.

Referenced by isLittle().

bool llvm::ARMSubtarget::IsProfitableToUnpredicate = false
protected

If true, if conversion may decide to leave some instructions unpredicated.

Definition at line 243 of file ARMSubtarget.h.

Referenced by isProfitableToUnpredicate().

ARMLdStMultipleTiming llvm::ARMSubtarget::LdStMultipleTiming = SingleIssue
protected

What kind of timing do load multiple/store multiple have (double issue, single issue etc).

Definition at line 327 of file ARMSubtarget.h.

Referenced by getLdStMultipleTiming().

unsigned llvm::ARMSubtarget::MaxInterleaveFactor = 1
protected

Definition at line 320 of file ARMSubtarget.h.

Referenced by getMaxInterleaveFactor().

bool llvm::ARMSubtarget::NoARM = false
protected

NoARM - True if subtarget does not support ARM mode execution.

Definition at line 141 of file ARMSubtarget.h.

Referenced by hasARMOps().

bool llvm::ARMSubtarget::NoMovt = false
protected

NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global addresses).

Definition at line 148 of file ARMSubtarget.h.

Referenced by useMovt().

bool llvm::ARMSubtarget::NonpipelinedVFP = false
protected

If true, VFP instructions are not pipelined.

Definition at line 283 of file ARMSubtarget.h.

Referenced by nonpipelinedVFP().

const TargetOptions& llvm::ARMSubtarget::Options
protected

Options passed via command line that could influence the target.

Definition at line 346 of file ARMSubtarget.h.

unsigned llvm::ARMSubtarget::PartialUpdateClearance = 0
protected

Clearance before partial register updates (in number of instructions)

Definition at line 323 of file ARMSubtarget.h.

Referenced by getPartialUpdateClearance().

bool llvm::ARMSubtarget::Pref32BitThumb = false
protected

Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones.

Definition at line 188 of file ARMSubtarget.h.

Referenced by prefers32BitThumb().

bool llvm::ARMSubtarget::PreferISHST = false
protected

If true, ISHST barriers will be used for Release semantics.

Definition at line 255 of file ARMSubtarget.h.

Referenced by preferISHSTBarriers().

bool llvm::ARMSubtarget::PreferVMOVSR = false
protected

If true, VMOVSR will be favored over VMOVDRR.

Definition at line 252 of file ARMSubtarget.h.

Referenced by preferVMOVSR().

int llvm::ARMSubtarget::PreISelOperandLatencyAdjustment = 2
protected

The adjustment that we need to apply to get the operand latency from the operand cycle returned by the itinerary data for pre-ISel operands.

Definition at line 331 of file ARMSubtarget.h.

Referenced by getPreISelOperandLatencyAdjustment().

bool llvm::ARMSubtarget::ReserveR9 = false
protected

ReserveR9 - True if R9 is not available as a general purpose register.

Definition at line 144 of file ARMSubtarget.h.

Referenced by isR9Reserved().

bool llvm::ARMSubtarget::RestrictIT = false
protected

RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 rule.

Definition at line 292 of file ARMSubtarget.h.

Referenced by restrictIT().

MCSchedModel llvm::ARMSubtarget::SchedModel
protected

SchedModel - Processor specific instruction costs.

Definition at line 340 of file ARMSubtarget.h.

Referenced by getMispredictionPenalty().

bool llvm::ARMSubtarget::SlowFPBrcc = false
protected

SlowFPBrcc - True if floating point compare + branch is slow.

Definition at line 129 of file ARMSubtarget.h.

Referenced by isFPBrccSlow().

bool llvm::ARMSubtarget::SlowFPVMLx = false
protected

SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instructions are slow (if so, don't use them).

Definition at line 122 of file ARMSubtarget.h.

Referenced by useFPVMLx().

bool llvm::ARMSubtarget::SlowLoadDSubregister = false
protected

If true, loading into a D subregister will be penalized.

Definition at line 262 of file ARMSubtarget.h.

Referenced by hasSlowLoadDSubregister().

bool llvm::ARMSubtarget::SlowOddRegister = false
protected

If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than single VLDRS/VSTRS.

Definition at line 259 of file ARMSubtarget.h.

Referenced by hasSlowOddRegister().

unsigned llvm::ARMSubtarget::stackAlignment = 4
protected

stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and which must be maintained by every function.

Definition at line 315 of file ARMSubtarget.h.

Referenced by getStackAlignment().

bool llvm::ARMSubtarget::StrictAlign = false
protected

StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types.

For details, see ARMTargetLowering::allowsMisalignedMemoryAccesses().

Definition at line 288 of file ARMSubtarget.h.

Referenced by allowsUnalignedMem().

bool llvm::ARMSubtarget::SupportsTailCall = false
protected

SupportsTailCall - True if the OS supports tail call.

The dynamic linker must be able to synthesize call stubs for interworking between ARM and Thumb.

Definition at line 153 of file ARMSubtarget.h.

Referenced by supportsTailCall().

Triple llvm::ARMSubtarget::TargetTriple
protected
const ARMBaseTargetMachine& llvm::ARMSubtarget::TM
protected
bool llvm::ARMSubtarget::UnsafeFPMath = false
protected

Target machine allowed unsafe FP math (such as use of NEON fp)

Definition at line 308 of file ARMSubtarget.h.

bool llvm::ARMSubtarget::UseMulOps = false
protected

UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions should be used.

Definition at line 118 of file ARMSubtarget.h.

Referenced by useMulOps().

bool llvm::ARMSubtarget::UseNaClTrap = false
protected

NaCl TRAP instruction is generated instead of the regular TRAP.

Definition at line 299 of file ARMSubtarget.h.

Referenced by useNaClTrap().

bool llvm::ARMSubtarget::UseNEONForFPMovs = false
protected

If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.

Definition at line 277 of file ARMSubtarget.h.

Referenced by useNEONForFPMovs().

bool llvm::ARMSubtarget::UseNEONForSinglePrecisionFP = false
protected

UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.

Use the method useNEONForSinglePrecisionFP() to determine if NEON should actually be used.

Definition at line 114 of file ARMSubtarget.h.

Referenced by useNEONForSinglePrecisionFP().

bool llvm::ARMSubtarget::UseSjLjEH = false
protected

UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).

Definition at line 311 of file ARMSubtarget.h.

Referenced by useSjLjEH().

bool llvm::ARMSubtarget::UseSoftFloat = false
protected

UseSoftFloat - True if we're using software floating point features.

Definition at line 135 of file ARMSubtarget.h.

Referenced by useSoftFloat().


The documentation for this class was generated from the following files: