LLVM  4.0.0
RegAllocPBQP.cpp
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1 //===------ RegAllocPBQP.cpp ---- PBQP Register Allocator -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a Partitioned Boolean Quadratic Programming (PBQP) based
11 // register allocator for LLVM. This allocator works by constructing a PBQP
12 // problem representing the register allocation problem under consideration,
13 // solving this using a PBQP solver, and mapping the solution back to a
14 // register assignment. If any variables are selected for spilling then spill
15 // code is inserted and the process repeated.
16 //
17 // The PBQP solver (pbqp.c) provided for this allocator uses a heuristic tuned
18 // for register allocation. For more information on PBQP for register
19 // allocation, see the following papers:
20 //
21 // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with
22 // PBQP. In Proceedings of the 7th Joint Modular Languages Conference
23 // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361.
24 //
25 // (2) Scholz, B., Eckstein, E. 2002. Register allocation for irregular
26 // architectures. In Proceedings of the Joint Conference on Languages,
27 // Compilers and Tools for Embedded Systems (LCTES'02), ACM Press, New York,
28 // NY, USA, 139-148.
29 //
30 //===----------------------------------------------------------------------===//
31 
33 #include "RegisterCoalescer.h"
34 #include "Spiller.h"
47 #include "llvm/IR/Module.h"
48 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Printable.h"
54 #include <limits>
55 #include <memory>
56 #include <queue>
57 #include <set>
58 #include <sstream>
59 #include <vector>
60 
61 using namespace llvm;
62 
63 #define DEBUG_TYPE "regalloc"
64 
65 static RegisterRegAlloc
66 RegisterPBQPRepAlloc("pbqp", "PBQP register allocator",
68 
69 static cl::opt<bool>
70 PBQPCoalescing("pbqp-coalescing",
71  cl::desc("Attempt coalescing during PBQP register allocation."),
72  cl::init(false), cl::Hidden);
73 
74 #ifndef NDEBUG
75 static cl::opt<bool>
76 PBQPDumpGraphs("pbqp-dump-graphs",
77  cl::desc("Dump graphs for each function/round in the compilation unit."),
78  cl::init(false), cl::Hidden);
79 #endif
80 
81 namespace {
82 
83 ///
84 /// PBQP based allocators solve the register allocation problem by mapping
85 /// register allocation problems to Partitioned Boolean Quadratic
86 /// Programming problems.
87 class RegAllocPBQP : public MachineFunctionPass {
88 public:
89 
90  static char ID;
91 
92  /// Construct a PBQP register allocator.
93  RegAllocPBQP(char *cPassID = nullptr)
94  : MachineFunctionPass(ID), customPassID(cPassID) {
99  }
100 
101  /// Return the pass name.
102  StringRef getPassName() const override { return "PBQP Register Allocator"; }
103 
104  /// PBQP analysis usage.
105  void getAnalysisUsage(AnalysisUsage &au) const override;
106 
107  /// Perform register allocation
108  bool runOnMachineFunction(MachineFunction &MF) override;
109 
110  MachineFunctionProperties getRequiredProperties() const override {
113  }
114 
115 private:
116 
117  typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
118  typedef std::vector<const LiveInterval*> Node2LIMap;
119  typedef std::vector<unsigned> AllowedSet;
120  typedef std::vector<AllowedSet> AllowedSetMap;
121  typedef std::pair<unsigned, unsigned> RegPair;
122  typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;
123  typedef std::set<unsigned> RegSet;
124 
125  char *customPassID;
126 
127  RegSet VRegsToAlloc, EmptyIntervalVRegs;
128 
129  /// Inst which is a def of an original reg and whose defs are already all
130  /// dead after remat is saved in DeadRemats. The deletion of such inst is
131  /// postponed till all the allocations are done, so its remat expr is
132  /// always available for the remat of all the siblings of the original reg.
134 
135  /// \brief Finds the initial set of vreg intervals to allocate.
136  void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
137 
138  /// \brief Constructs an initial graph.
139  void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
140 
141  /// \brief Spill the given VReg.
142  void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
143  MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
144  Spiller &VRegSpiller);
145 
146  /// \brief Given a solved PBQP problem maps this solution back to a register
147  /// assignment.
148  bool mapPBQPToRegAlloc(const PBQPRAGraph &G,
149  const PBQP::Solution &Solution,
150  VirtRegMap &VRM,
151  Spiller &VRegSpiller);
152 
153  /// \brief Postprocessing before final spilling. Sets basic block "live in"
154  /// variables.
155  void finalizeAlloc(MachineFunction &MF, LiveIntervals &LIS,
156  VirtRegMap &VRM) const;
157 
158  void postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS);
159 };
160 
161 char RegAllocPBQP::ID = 0;
162 
163 /// @brief Set spill costs for each node in the PBQP reg-alloc graph.
164 class SpillCosts : public PBQPRAConstraint {
165 public:
166  void apply(PBQPRAGraph &G) override {
167  LiveIntervals &LIS = G.getMetadata().LIS;
168 
169  // A minimum spill costs, so that register constraints can can be set
170  // without normalization in the [0.0:MinSpillCost( interval.
171  const PBQP::PBQPNum MinSpillCost = 10.0;
172 
173  for (auto NId : G.nodeIds()) {
174  PBQP::PBQPNum SpillCost =
175  LIS.getInterval(G.getNodeMetadata(NId).getVReg()).weight;
176  if (SpillCost == 0.0)
178  else
179  SpillCost += MinSpillCost;
180  PBQPRAGraph::RawVector NodeCosts(G.getNodeCosts(NId));
181  NodeCosts[PBQP::RegAlloc::getSpillOptionIdx()] = SpillCost;
182  G.setNodeCosts(NId, std::move(NodeCosts));
183  }
184  }
185 };
186 
187 /// @brief Add interference edges between overlapping vregs.
188 class Interference : public PBQPRAConstraint {
189 private:
190 
191  typedef const PBQP::RegAlloc::AllowedRegVector* AllowedRegVecPtr;
192  typedef std::pair<AllowedRegVecPtr, AllowedRegVecPtr> IKey;
193  typedef DenseMap<IKey, PBQPRAGraph::MatrixPtr> IMatrixCache;
194  typedef DenseSet<IKey> DisjointAllowedRegsCache;
195  typedef std::pair<PBQP::GraphBase::NodeId, PBQP::GraphBase::NodeId> IEdgeKey;
196  typedef DenseSet<IEdgeKey> IEdgeCache;
197 
198  bool haveDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
200  const DisjointAllowedRegsCache &D) const {
201  const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
202  const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
203 
204  if (NRegs == MRegs)
205  return false;
206 
207  if (NRegs < MRegs)
208  return D.count(IKey(NRegs, MRegs)) > 0;
209 
210  return D.count(IKey(MRegs, NRegs)) > 0;
211  }
212 
213  void setDisjointAllowedRegs(const PBQPRAGraph &G, PBQPRAGraph::NodeId NId,
215  DisjointAllowedRegsCache &D) {
216  const auto *NRegs = &G.getNodeMetadata(NId).getAllowedRegs();
217  const auto *MRegs = &G.getNodeMetadata(MId).getAllowedRegs();
218 
219  assert(NRegs != MRegs && "AllowedRegs can not be disjoint with itself");
220 
221  if (NRegs < MRegs)
222  D.insert(IKey(NRegs, MRegs));
223  else
224  D.insert(IKey(MRegs, NRegs));
225  }
226 
227  // Holds (Interval, CurrentSegmentID, and NodeId). The first two are required
228  // for the fast interference graph construction algorithm. The last is there
229  // to save us from looking up node ids via the VRegToNode map in the graph
230  // metadata.
231  typedef std::tuple<LiveInterval*, size_t, PBQP::GraphBase::NodeId>
232  IntervalInfo;
233 
234  static SlotIndex getStartPoint(const IntervalInfo &I) {
235  return std::get<0>(I)->segments[std::get<1>(I)].start;
236  }
237 
238  static SlotIndex getEndPoint(const IntervalInfo &I) {
239  return std::get<0>(I)->segments[std::get<1>(I)].end;
240  }
241 
242  static PBQP::GraphBase::NodeId getNodeId(const IntervalInfo &I) {
243  return std::get<2>(I);
244  }
245 
246  static bool lowestStartPoint(const IntervalInfo &I1,
247  const IntervalInfo &I2) {
248  // Condition reversed because priority queue has the *highest* element at
249  // the front, rather than the lowest.
250  return getStartPoint(I1) > getStartPoint(I2);
251  }
252 
253  static bool lowestEndPoint(const IntervalInfo &I1,
254  const IntervalInfo &I2) {
255  SlotIndex E1 = getEndPoint(I1);
256  SlotIndex E2 = getEndPoint(I2);
257 
258  if (E1 < E2)
259  return true;
260 
261  if (E1 > E2)
262  return false;
263 
264  // If two intervals end at the same point, we need a way to break the tie or
265  // the set will assume they're actually equal and refuse to insert a
266  // "duplicate". Just compare the vregs - fast and guaranteed unique.
267  return std::get<0>(I1)->reg < std::get<0>(I2)->reg;
268  }
269 
270  static bool isAtLastSegment(const IntervalInfo &I) {
271  return std::get<1>(I) == std::get<0>(I)->size() - 1;
272  }
273 
274  static IntervalInfo nextSegment(const IntervalInfo &I) {
275  return std::make_tuple(std::get<0>(I), std::get<1>(I) + 1, std::get<2>(I));
276  }
277 
278 public:
279 
280  void apply(PBQPRAGraph &G) override {
281  // The following is loosely based on the linear scan algorithm introduced in
282  // "Linear Scan Register Allocation" by Poletto and Sarkar. This version
283  // isn't linear, because the size of the active set isn't bound by the
284  // number of registers, but rather the size of the largest clique in the
285  // graph. Still, we expect this to be better than N^2.
286  LiveIntervals &LIS = G.getMetadata().LIS;
287 
288  // Interferenc matrices are incredibly regular - they're only a function of
289  // the allowed sets, so we cache them to avoid the overhead of constructing
290  // and uniquing them.
291  IMatrixCache C;
292 
293  // Finding an edge is expensive in the worst case (O(max_clique(G))). So
294  // cache locally edges we have already seen.
295  IEdgeCache EC;
296 
297  // Cache known disjoint allowed registers pairs
298  DisjointAllowedRegsCache D;
299 
300  typedef std::set<IntervalInfo, decltype(&lowestEndPoint)> IntervalSet;
301  typedef std::priority_queue<IntervalInfo, std::vector<IntervalInfo>,
302  decltype(&lowestStartPoint)> IntervalQueue;
303  IntervalSet Active(lowestEndPoint);
304  IntervalQueue Inactive(lowestStartPoint);
305 
306  // Start by building the inactive set.
307  for (auto NId : G.nodeIds()) {
308  unsigned VReg = G.getNodeMetadata(NId).getVReg();
309  LiveInterval &LI = LIS.getInterval(VReg);
310  assert(!LI.empty() && "PBQP graph contains node for empty interval");
311  Inactive.push(std::make_tuple(&LI, 0, NId));
312  }
313 
314  while (!Inactive.empty()) {
315  // Tentatively grab the "next" interval - this choice may be overriden
316  // below.
317  IntervalInfo Cur = Inactive.top();
318 
319  // Retire any active intervals that end before Cur starts.
320  IntervalSet::iterator RetireItr = Active.begin();
321  while (RetireItr != Active.end() &&
322  (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {
323  // If this interval has subsequent segments, add the next one to the
324  // inactive list.
325  if (!isAtLastSegment(*RetireItr))
326  Inactive.push(nextSegment(*RetireItr));
327 
328  ++RetireItr;
329  }
330  Active.erase(Active.begin(), RetireItr);
331 
332  // One of the newly retired segments may actually start before the
333  // Cur segment, so re-grab the front of the inactive list.
334  Cur = Inactive.top();
335  Inactive.pop();
336 
337  // At this point we know that Cur overlaps all active intervals. Add the
338  // interference edges.
339  PBQP::GraphBase::NodeId NId = getNodeId(Cur);
340  for (const auto &A : Active) {
341  PBQP::GraphBase::NodeId MId = getNodeId(A);
342 
343  // Do not add an edge when the nodes' allowed registers do not
344  // intersect: there is obviously no interference.
345  if (haveDisjointAllowedRegs(G, NId, MId, D))
346  continue;
347 
348  // Check that we haven't already added this edge
349  IEdgeKey EK(std::min(NId, MId), std::max(NId, MId));
350  if (EC.count(EK))
351  continue;
352 
353  // This is a new edge - add it to the graph.
354  if (!createInterferenceEdge(G, NId, MId, C))
355  setDisjointAllowedRegs(G, NId, MId, D);
356  else
357  EC.insert(EK);
358  }
359 
360  // Finally, add Cur to the Active set.
361  Active.insert(Cur);
362  }
363  }
364 
365 private:
366 
367  // Create an Interference edge and add it to the graph, unless it is
368  // a null matrix, meaning the nodes' allowed registers do not have any
369  // interference. This case occurs frequently between integer and floating
370  // point registers for example.
371  // return true iff both nodes interferes.
372  bool createInterferenceEdge(PBQPRAGraph &G,
374  IMatrixCache &C) {
375 
376  const TargetRegisterInfo &TRI =
377  *G.getMetadata().MF.getSubtarget().getRegisterInfo();
378  const auto &NRegs = G.getNodeMetadata(NId).getAllowedRegs();
379  const auto &MRegs = G.getNodeMetadata(MId).getAllowedRegs();
380 
381  // Try looking the edge costs up in the IMatrixCache first.
382  IKey K(&NRegs, &MRegs);
383  IMatrixCache::iterator I = C.find(K);
384  if (I != C.end()) {
385  G.addEdgeBypassingCostAllocator(NId, MId, I->second);
386  return true;
387  }
388 
389  PBQPRAGraph::RawMatrix M(NRegs.size() + 1, MRegs.size() + 1, 0);
390  bool NodesInterfere = false;
391  for (unsigned I = 0; I != NRegs.size(); ++I) {
392  unsigned PRegN = NRegs[I];
393  for (unsigned J = 0; J != MRegs.size(); ++J) {
394  unsigned PRegM = MRegs[J];
395  if (TRI.regsOverlap(PRegN, PRegM)) {
396  M[I + 1][J + 1] = std::numeric_limits<PBQP::PBQPNum>::infinity();
397  NodesInterfere = true;
398  }
399  }
400  }
401 
402  if (!NodesInterfere)
403  return false;
404 
405  PBQPRAGraph::EdgeId EId = G.addEdge(NId, MId, std::move(M));
406  C[K] = G.getEdgeCostsPtr(EId);
407 
408  return true;
409  }
410 };
411 
412 
413 class Coalescing : public PBQPRAConstraint {
414 public:
415  void apply(PBQPRAGraph &G) override {
416  MachineFunction &MF = G.getMetadata().MF;
417  MachineBlockFrequencyInfo &MBFI = G.getMetadata().MBFI;
419 
420  // Scan the machine function and add a coalescing cost whenever CoalescerPair
421  // gives the Ok.
422  for (const auto &MBB : MF) {
423  for (const auto &MI : MBB) {
424 
425  // Skip not-coalescable or already coalesced copies.
426  if (!CP.setRegisters(&MI) || CP.getSrcReg() == CP.getDstReg())
427  continue;
428 
429  unsigned DstReg = CP.getDstReg();
430  unsigned SrcReg = CP.getSrcReg();
431 
432  const float Scale = 1.0f / MBFI.getEntryFreq();
433  PBQP::PBQPNum CBenefit = MBFI.getBlockFreq(&MBB).getFrequency() * Scale;
434 
435  if (CP.isPhys()) {
436  if (!MF.getRegInfo().isAllocatable(DstReg))
437  continue;
438 
439  PBQPRAGraph::NodeId NId = G.getMetadata().getNodeIdForVReg(SrcReg);
440 
441  const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed =
442  G.getNodeMetadata(NId).getAllowedRegs();
443 
444  unsigned PRegOpt = 0;
445  while (PRegOpt < Allowed.size() && Allowed[PRegOpt] != DstReg)
446  ++PRegOpt;
447 
448  if (PRegOpt < Allowed.size()) {
449  PBQPRAGraph::RawVector NewCosts(G.getNodeCosts(NId));
450  NewCosts[PRegOpt + 1] -= CBenefit;
451  G.setNodeCosts(NId, std::move(NewCosts));
452  }
453  } else {
454  PBQPRAGraph::NodeId N1Id = G.getMetadata().getNodeIdForVReg(DstReg);
455  PBQPRAGraph::NodeId N2Id = G.getMetadata().getNodeIdForVReg(SrcReg);
456  const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed1 =
457  &G.getNodeMetadata(N1Id).getAllowedRegs();
458  const PBQPRAGraph::NodeMetadata::AllowedRegVector *Allowed2 =
459  &G.getNodeMetadata(N2Id).getAllowedRegs();
460 
461  PBQPRAGraph::EdgeId EId = G.findEdge(N1Id, N2Id);
462  if (EId == G.invalidEdgeId()) {
463  PBQPRAGraph::RawMatrix Costs(Allowed1->size() + 1,
464  Allowed2->size() + 1, 0);
465  addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
466  G.addEdge(N1Id, N2Id, std::move(Costs));
467  } else {
468  if (G.getEdgeNode1Id(EId) == N2Id) {
469  std::swap(N1Id, N2Id);
470  std::swap(Allowed1, Allowed2);
471  }
472  PBQPRAGraph::RawMatrix Costs(G.getEdgeCosts(EId));
473  addVirtRegCoalesce(Costs, *Allowed1, *Allowed2, CBenefit);
474  G.updateEdgeCosts(EId, std::move(Costs));
475  }
476  }
477  }
478  }
479  }
480 
481 private:
482 
483  void addVirtRegCoalesce(
484  PBQPRAGraph::RawMatrix &CostMat,
485  const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed1,
486  const PBQPRAGraph::NodeMetadata::AllowedRegVector &Allowed2,
487  PBQP::PBQPNum Benefit) {
488  assert(CostMat.getRows() == Allowed1.size() + 1 && "Size mismatch.");
489  assert(CostMat.getCols() == Allowed2.size() + 1 && "Size mismatch.");
490  for (unsigned I = 0; I != Allowed1.size(); ++I) {
491  unsigned PReg1 = Allowed1[I];
492  for (unsigned J = 0; J != Allowed2.size(); ++J) {
493  unsigned PReg2 = Allowed2[J];
494  if (PReg1 == PReg2)
495  CostMat[I + 1][J + 1] -= Benefit;
496  }
497  }
498  }
499 
500 };
501 
502 } // End anonymous namespace.
503 
504 // Out-of-line destructor/anchor for PBQPRAConstraint.
506 void PBQPRAConstraint::anchor() {}
507 void PBQPRAConstraintList::anchor() {}
508 
509 void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
510  au.setPreservesCFG();
513  au.addRequired<SlotIndexes>();
517  //au.addRequiredID(SplitCriticalEdgesID);
518  if (customPassID)
519  au.addRequiredID(*customPassID);
520  au.addRequired<LiveStacks>();
521  au.addPreserved<LiveStacks>();
528  au.addRequired<VirtRegMap>();
529  au.addPreserved<VirtRegMap>();
531 }
532 
533 void RegAllocPBQP::findVRegIntervalsToAlloc(const MachineFunction &MF,
534  LiveIntervals &LIS) {
535  const MachineRegisterInfo &MRI = MF.getRegInfo();
536 
537  // Iterate over all live ranges.
538  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
540  if (MRI.reg_nodbg_empty(Reg))
541  continue;
542  LiveInterval &LI = LIS.getInterval(Reg);
543 
544  // If this live interval is non-empty we will use pbqp to allocate it.
545  // Empty intervals we allocate in a simple post-processing stage in
546  // finalizeAlloc.
547  if (!LI.empty()) {
548  VRegsToAlloc.insert(LI.reg);
549  } else {
550  EmptyIntervalVRegs.insert(LI.reg);
551  }
552  }
553 }
554 
555 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
556  const MachineFunction &MF) {
557  const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
558  for (unsigned i = 0; CSR[i] != 0; ++i)
559  if (TRI.regsOverlap(reg, CSR[i]))
560  return true;
561  return false;
562 }
563 
564 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
565  Spiller &VRegSpiller) {
566  MachineFunction &MF = G.getMetadata().MF;
567 
568  LiveIntervals &LIS = G.getMetadata().LIS;
569  const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
570  const TargetRegisterInfo &TRI =
571  *G.getMetadata().MF.getSubtarget().getRegisterInfo();
572 
573  std::vector<unsigned> Worklist(VRegsToAlloc.begin(), VRegsToAlloc.end());
574 
575  while (!Worklist.empty()) {
576  unsigned VReg = Worklist.back();
577  Worklist.pop_back();
578 
579  const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
580  LiveInterval &VRegLI = LIS.getInterval(VReg);
581 
582  // Record any overlaps with regmask operands.
583  BitVector RegMaskOverlaps;
584  LIS.checkRegMaskInterference(VRegLI, RegMaskOverlaps);
585 
586  // Compute an initial allowed set for the current vreg.
587  std::vector<unsigned> VRegAllowed;
588  ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
589  for (unsigned I = 0; I != RawPRegOrder.size(); ++I) {
590  unsigned PReg = RawPRegOrder[I];
591  if (MRI.isReserved(PReg))
592  continue;
593 
594  // vregLI crosses a regmask operand that clobbers preg.
595  if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg))
596  continue;
597 
598  // vregLI overlaps fixed regunit interference.
599  bool Interference = false;
600  for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
601  if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
602  Interference = true;
603  break;
604  }
605  }
606  if (Interference)
607  continue;
608 
609  // preg is usable for this virtual register.
610  VRegAllowed.push_back(PReg);
611  }
612 
613  // Check for vregs that have no allowed registers. These should be
614  // pre-spilled and the new vregs added to the worklist.
615  if (VRegAllowed.empty()) {
616  SmallVector<unsigned, 8> NewVRegs;
617  spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
618  Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end());
619  continue;
620  }
621 
622  PBQPRAGraph::RawVector NodeCosts(VRegAllowed.size() + 1, 0);
623 
624  // Tweak cost of callee saved registers, as using then force spilling and
625  // restoring them. This would only happen in the prologue / epilogue though.
626  for (unsigned i = 0; i != VRegAllowed.size(); ++i)
627  if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
628  NodeCosts[1 + i] += 1.0;
629 
630  PBQPRAGraph::NodeId NId = G.addNode(std::move(NodeCosts));
631  G.getNodeMetadata(NId).setVReg(VReg);
632  G.getNodeMetadata(NId).setAllowedRegs(
633  G.getMetadata().getAllowedRegs(std::move(VRegAllowed)));
634  G.getMetadata().setNodeIdForVReg(VReg, NId);
635  }
636 }
637 
638 void RegAllocPBQP::spillVReg(unsigned VReg,
639  SmallVectorImpl<unsigned> &NewIntervals,
640  MachineFunction &MF, LiveIntervals &LIS,
641  VirtRegMap &VRM, Spiller &VRegSpiller) {
642 
643  VRegsToAlloc.erase(VReg);
644  LiveRangeEdit LRE(&LIS.getInterval(VReg), NewIntervals, MF, LIS, &VRM,
645  nullptr, &DeadRemats);
646  VRegSpiller.spill(LRE);
647 
648  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
649  (void)TRI;
650  DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
651  << LRE.getParent().weight << ", New vregs: ");
652 
653  // Copy any newly inserted live intervals into the list of regs to
654  // allocate.
655  for (LiveRangeEdit::iterator I = LRE.begin(), E = LRE.end();
656  I != E; ++I) {
657  const LiveInterval &LI = LIS.getInterval(*I);
658  assert(!LI.empty() && "Empty spill range.");
659  DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
660  VRegsToAlloc.insert(LI.reg);
661  }
662 
663  DEBUG(dbgs() << ")\n");
664 }
665 
666 bool RegAllocPBQP::mapPBQPToRegAlloc(const PBQPRAGraph &G,
667  const PBQP::Solution &Solution,
668  VirtRegMap &VRM,
669  Spiller &VRegSpiller) {
670  MachineFunction &MF = G.getMetadata().MF;
671  LiveIntervals &LIS = G.getMetadata().LIS;
672  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
673  (void)TRI;
674 
675  // Set to true if we have any spills
676  bool AnotherRoundNeeded = false;
677 
678  // Clear the existing allocation.
679  VRM.clearAllVirt();
680 
681  // Iterate over the nodes mapping the PBQP solution to a register
682  // assignment.
683  for (auto NId : G.nodeIds()) {
684  unsigned VReg = G.getNodeMetadata(NId).getVReg();
685  unsigned AllocOption = Solution.getSelection(NId);
686 
687  if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
688  unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
689  DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
690  << TRI.getName(PReg) << "\n");
691  assert(PReg != 0 && "Invalid preg selected.");
692  VRM.assignVirt2Phys(VReg, PReg);
693  } else {
694  // Spill VReg. If this introduces new intervals we'll need another round
695  // of allocation.
696  SmallVector<unsigned, 8> NewVRegs;
697  spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller);
698  AnotherRoundNeeded |= !NewVRegs.empty();
699  }
700  }
701 
702  return !AnotherRoundNeeded;
703 }
704 
705 void RegAllocPBQP::finalizeAlloc(MachineFunction &MF,
706  LiveIntervals &LIS,
707  VirtRegMap &VRM) const {
708  MachineRegisterInfo &MRI = MF.getRegInfo();
709 
710  // First allocate registers for the empty intervals.
711  for (RegSet::const_iterator
712  I = EmptyIntervalVRegs.begin(), E = EmptyIntervalVRegs.end();
713  I != E; ++I) {
714  LiveInterval &LI = LIS.getInterval(*I);
715 
716  unsigned PReg = MRI.getSimpleHint(LI.reg);
717 
718  if (PReg == 0) {
719  const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
720  PReg = RC.getRawAllocationOrder(MF).front();
721  }
722 
723  VRM.assignVirt2Phys(LI.reg, PReg);
724  }
725 }
726 
727 void RegAllocPBQP::postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS) {
728  VRegSpiller.postOptimization();
729  /// Remove dead defs because of rematerialization.
730  for (auto DeadInst : DeadRemats) {
731  LIS.RemoveMachineInstrFromMaps(*DeadInst);
732  DeadInst->eraseFromParent();
733  }
734  DeadRemats.clear();
735 }
736 
737 static inline float normalizePBQPSpillWeight(float UseDefFreq, unsigned Size,
738  unsigned NumInstr) {
739  // All intervals have a spill weight that is mostly proportional to the number
740  // of uses, with uses in loops having a bigger weight.
741  return NumInstr * normalizeSpillWeight(UseDefFreq, Size, 1);
742 }
743 
744 bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
745  LiveIntervals &LIS = getAnalysis<LiveIntervals>();
747  getAnalysis<MachineBlockFrequencyInfo>();
748 
749  VirtRegMap &VRM = getAnalysis<VirtRegMap>();
750 
751  calculateSpillWeightsAndHints(LIS, MF, &VRM, getAnalysis<MachineLoopInfo>(),
753 
754  std::unique_ptr<Spiller> VRegSpiller(createInlineSpiller(*this, MF, VRM));
755 
757 
758  DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n");
759 
760  // Allocator main loop:
761  //
762  // * Map current regalloc problem to a PBQP problem
763  // * Solve the PBQP problem
764  // * Map the solution back to a register allocation
765  // * Spill if necessary
766  //
767  // This process is continued till no more spills are generated.
768 
769  // Find the vreg intervals in need of allocation.
770  findVRegIntervalsToAlloc(MF, LIS);
771 
772 #ifndef NDEBUG
773  const Function &F = *MF.getFunction();
774  std::string FullyQualifiedName =
775  F.getParent()->getModuleIdentifier() + "." + F.getName().str();
776 #endif
777 
778  // If there are non-empty intervals allocate them using pbqp.
779  if (!VRegsToAlloc.empty()) {
780 
781  const TargetSubtargetInfo &Subtarget = MF.getSubtarget();
782  std::unique_ptr<PBQPRAConstraintList> ConstraintsRoot =
783  llvm::make_unique<PBQPRAConstraintList>();
784  ConstraintsRoot->addConstraint(llvm::make_unique<SpillCosts>());
785  ConstraintsRoot->addConstraint(llvm::make_unique<Interference>());
786  if (PBQPCoalescing)
787  ConstraintsRoot->addConstraint(llvm::make_unique<Coalescing>());
788  ConstraintsRoot->addConstraint(Subtarget.getCustomPBQPConstraints());
789 
790  bool PBQPAllocComplete = false;
791  unsigned Round = 0;
792 
793  while (!PBQPAllocComplete) {
794  DEBUG(dbgs() << " PBQP Regalloc round " << Round << ":\n");
795 
796  PBQPRAGraph G(PBQPRAGraph::GraphMetadata(MF, LIS, MBFI));
797  initializeGraph(G, VRM, *VRegSpiller);
798  ConstraintsRoot->apply(G);
799 
800 #ifndef NDEBUG
801  if (PBQPDumpGraphs) {
802  std::ostringstream RS;
803  RS << Round;
804  std::string GraphFileName = FullyQualifiedName + "." + RS.str() +
805  ".pbqpgraph";
806  std::error_code EC;
807  raw_fd_ostream OS(GraphFileName, EC, sys::fs::F_Text);
808  DEBUG(dbgs() << "Dumping graph for round " << Round << " to \""
809  << GraphFileName << "\"\n");
810  G.dump(OS);
811  }
812 #endif
813 
815  PBQPAllocComplete = mapPBQPToRegAlloc(G, Solution, VRM, *VRegSpiller);
816  ++Round;
817  }
818  }
819 
820  // Finalise allocation, allocate empty ranges.
821  finalizeAlloc(MF, LIS, VRM);
822  postOptimization(*VRegSpiller, LIS);
823  VRegsToAlloc.clear();
824  EmptyIntervalVRegs.clear();
825 
826  DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << VRM << "\n");
827 
828  return true;
829 }
830 
831 /// Create Printable object for node and register info.
833  const PBQP::RegAlloc::PBQPRAGraph &G) {
834  return Printable([NId, &G](raw_ostream &OS) {
835  const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
836  const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
837  unsigned VReg = G.getNodeMetadata(NId).getVReg();
838  const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
839  OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
840  });
841 }
842 
844  for (auto NId : nodeIds()) {
845  const Vector &Costs = getNodeCosts(NId);
846  assert(Costs.getLength() != 0 && "Empty vector in graph.");
847  OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
848  }
849  OS << '\n';
850 
851  for (auto EId : edgeIds()) {
852  NodeId N1Id = getEdgeNode1Id(EId);
853  NodeId N2Id = getEdgeNode2Id(EId);
854  assert(N1Id != N2Id && "PBQP graphs should not have self-edges.");
855  const Matrix &M = getEdgeCosts(EId);
856  assert(M.getRows() != 0 && "No rows in matrix.");
857  assert(M.getCols() != 0 && "No cols in matrix.");
858  OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
859  OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
860  OS << M << '\n';
861  }
862 }
863 
865 
867  OS << "graph {\n";
868  for (auto NId : nodeIds()) {
869  OS << " node" << NId << " [ label=\""
870  << PrintNodeInfo(NId, *this) << "\\n"
871  << getNodeCosts(NId) << "\" ]\n";
872  }
873 
874  OS << " edge [ len=" << nodeIds().size() << " ]\n";
875  for (auto EId : edgeIds()) {
876  OS << " node" << getEdgeNode1Id(EId)
877  << " -- node" << getEdgeNode2Id(EId)
878  << " [ label=\"";
879  const Matrix &EdgeCosts = getEdgeCosts(EId);
880  for (unsigned i = 0; i < EdgeCosts.getRows(); ++i) {
881  OS << EdgeCosts.getRowAsVector(i) << "\\n";
882  }
883  OS << "\" ]\n";
884  }
885  OS << "}\n";
886 }
887 
889  return new RegAllocPBQP(customPassID);
890 }
891 
894 }
895 
896 #undef DEBUG_TYPE
Represents a solution to a PBQP problem.
Definition: Solution.h:27
static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId, const PBQP::RegAlloc::PBQPRAGraph &G)
Create Printable object for node and register info.
Abstract base for classes implementing PBQP register allocation constraints (e.g. ...
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const unsigned reg
Definition: LiveInterval.h:656
NodeId getEdgeNode1Id(EdgeId EId) const
Get the first node connected to this edge.
Definition: Graph.h:533
void RemoveMachineInstrFromMaps(MachineInstr &MI)
size_t i
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:450
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
EdgeId addEdge(NodeId N1Id, NodeId N2Id, OtherVectorT Costs)
Add an edge between the given nodes with the given costs.
Definition: Graph.h:397
unsigned getSimpleHint(unsigned VReg) const
getSimpleHint - Return the preferred register allocation hint, or 0 if a standard simple hint (Type =...
Holds a vector of the allowed physical regs for a vreg.
Definition: RegAllocPBQP.h:81
static RegisterRegAlloc RegisterPBQPRepAlloc("pbqp","PBQP register allocator", createDefaultPBQPRegisterAllocator)
const T & front() const
front - Get the first element.
Definition: ArrayRef.h:144
Implements a dense probed hash-table based set.
Definition: DenseSet.h:202
EdgeId findEdge(NodeId N1Id, NodeId N2Id)
Get the edge connecting two nodes.
Definition: Graph.h:561
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
virtual ~PBQPRAConstraint()=0
NodeId getEdgeNode2Id(EdgeId EId) const
Get the second node connected to this edge.
Definition: Graph.h:540
unsigned getSelection(GraphBase::NodeId nodeId) const
Get a node's selection.
Definition: Solution.h:51
Spiller interface.
Definition: Spiller.h:25
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
void updateEdgeCosts(EdgeId EId, OtherMatrixT Costs)
Update an edge's cost matrix.
Definition: Graph.h:496
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
NodeId addEdgeBypassingCostAllocator(NodeId N1Id, NodeId N2Id, OtherMatrixPtrT Costs)
Add an edge bypassing the cost allocator.
Definition: Graph.h:422
RegAllocSolverImpl::GraphMetadata GraphMetadata
Definition: Graph.h:61
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
void assignVirt2Phys(unsigned virtReg, unsigned physReg)
creates a mapping for the specified virtual register to the specified physical register ...
Definition: VirtRegMap.h:105
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
const Vector & getNodeCosts(NodeId NId) const
Get a node's cost vector.
Definition: Graph.h:476
bool empty() const
Definition: LiveInterval.h:357
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
virtual void spill(LiveRangeEdit &LRE)=0
spill - Spill the LRE.getParent() live interval.
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:191
FunctionPass * createPBQPRegisterAllocator(char *customPassID=nullptr)
Create a PBQP register allocator instance.
void dump() const
Dump this graph to dbgs().
RegAllocSolverImpl::RawMatrix RawMatrix
Definition: Graph.h:54
NodeMetadata & getNodeMetadata(NodeId NId)
Definition: Graph.h:480
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
AnalysisUsage & addRequired()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const TargetRegisterInfo * getTargetRegisterInfo() const
virtual std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const
Return PBQPConstraint(s) for the target.
A helper class for register coalescers.
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
SmallVectorImpl< unsigned >::const_iterator iterator
Iterator for accessing the new registers added by this edit.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
const std::string & getModuleIdentifier() const
Get the module identifier which is, essentially, the name of the module.
Definition: Module.h:193
void printDot(raw_ostream &OS) const
Print a representation of this graph in DOT format.
static cl::opt< bool > PBQPCoalescing("pbqp-coalescing", cl::desc("Attempt coalescing during PBQP register allocation."), cl::init(false), cl::Hidden)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
#define F(x, y, z)
Definition: MD5.cpp:51
SlotIndexes pass.
Definition: SlotIndexes.h:323
MachineBasicBlock * MBB
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
RegAllocSolverImpl::Matrix Matrix
Definition: Graph.h:56
RegisterRegAlloc class - Track the registration of register allocators.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
NodeIdSet nodeIds() const
Definition: Graph.h:437
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
void initializeSlotIndexesPass(PassRegistry &)
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void initializeLiveStacksPass(PassRegistry &)
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:116
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
Definition: LiveInterval.h:423
Represent the analysis usage information of a pass.
void initializeLiveIntervalsPass(PassRegistry &)
FunctionPass * createDefaultPBQPRegisterAllocator()
PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean Quadratic Prograaming (PBQ...
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI, const MachineFunction &MF)
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:225
void apply(Opt *O, const Mod &M, const Mods &...Ms)
Definition: CommandLine.h:1156
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
float PBQPNum
Definition: Math.h:21
GraphMetadata & getMetadata()
Get a reference to the graph metadata.
Definition: Graph.h:335
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &MF, VirtRegMap *VRM, const MachineLoopInfo &MLI, const MachineBlockFrequencyInfo &MBFI, VirtRegAuxInfo::NormalizingFn norm=normalizeSpillWeight)
Compute spill weights and allocation hints for all virtual register live intervals.
AnalysisUsage & addRequiredID(const void *ID)
Definition: Pass.cpp:289
Module.h This file contains the declarations for the Module class.
bool test(unsigned Idx) const
Definition: BitVector.h:323
const DataFlowGraph & G
Definition: RDFGraph.cpp:206
const Matrix & getEdgeCosts(EdgeId EId) const
Get an edge's cost matrix.
Definition: Graph.h:518
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
LiveInterval & getInterval(unsigned Reg)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
The file should be opened in text mode on platforms that make this distinction.
Definition: FileSystem.h:638
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
TargetSubtargetInfo - Generic base class for all target subtargets.
void initializeVirtRegMapPass(PassRegistry &)
Spiller * createInlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
Create and return a spiller that will insert spill code directly instead of deferring though VirtRegM...
static EdgeId invalidEdgeId()
Returns a value representing an invalid (non-existent) edge.
Definition: Graph.h:40
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
A raw_ostream that writes to a file descriptor.
Definition: raw_ostream.h:357
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
Solution solve(PBQPRAGraph &G)
Definition: RegAllocPBQP.h:513
virtual void postOptimization()
Definition: Spiller.h:32
RegAllocSolverImpl::Vector Vector
Definition: Graph.h:55
unsigned getSpillOptionIdx()
Spill option index.
Definition: RegAllocPBQP.h:34
static cl::opt< bool > PBQPDumpGraphs("pbqp-dump-graphs", cl::desc("Dump graphs for each function/round in the compilation unit."), cl::init(false), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static float normalizeSpillWeight(float UseDefFreq, unsigned Size, unsigned NumInstr)
Normalize the spill weight of a live interval.
void clearAllVirt()
clears all virtual to physical register mappings
Definition: VirtRegMap.h:124
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:537
simple register Simple Register Coalescing
unsigned NodeId
Definition: Graph.h:31
const MatrixPtr & getEdgeCostsPtr(EdgeId EId) const
Get a MatrixPtr to a node's cost matrix.
Definition: Graph.h:511
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:100
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
NodeId addNode(OtherVectorT Costs)
Add a node with the given costs.
Definition: Graph.h:363
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
RegAllocSolverImpl::RawVector RawVector
Definition: Graph.h:53
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:76
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
void setNodeCosts(NodeId NId, OtherVectorT Costs)
Set a node's cost vector.
Definition: Graph.h:454
static float normalizePBQPSpillWeight(float UseDefFreq, unsigned Size, unsigned NumInstr)
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
Properties which a MachineFunction may have at a given point in time.