225 #ifndef LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H
226 #define LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H
238 #include <functional>
241 #include <unordered_map>
248 static_assert(
sizeof(
uint32_t) ==
sizeof(
unsigned),
"Those should be equal");
252 class MachineBasicBlock;
253 class MachineFunction;
255 class MachineOperand;
256 class MachineDominanceFrontier;
257 class MachineDominatorTree;
258 class TargetInstrInfo;
316 uint16_t KB =
kind(B);
321 return KB ==
Phi || KB ==
Stmt;
381 : NodesPerBlock(NPB), BitsPerIndex(
Log2_32(NPB)),
382 IndexMask((1 << BitsPerIndex)-1) {
388 uint32_t BlockN = N1 >> BitsPerIndex;
398 void startNewBlock();
403 return ((Block << BitsPerIndex) | Index) + 1;
409 char *ActiveEnd =
nullptr;
410 std::vector<char*> Blocks;
457 template <
typename T,
unsigned N = 32>
463 assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size());
471 return F - Map.begin() + 1;
479 return F - Map.begin();
498 return LM.
all() ? 0 :
find(LM);
515 : ExpAliasUnits(tri.getNumRegUnits()), CheckUnits(
false), TRI(tri) {}
518 bool empty()
const {
return Masks.empty(); }
536 typedef std::unordered_map<RegisterId, LaneBitmask> MapType;
568 void init() { memset(
this, 0,
sizeof *
this); }
610 "NodeBase must be at most NodeAllocator::NodeMemSize bytes");
612 typedef std::vector<NodeAddr<NodeBase*>>
NodeList;
652 template <
typename Predicate>
692 return static_cast<T>(
Code.
CP);
706 template <
typename Predicate>
722 return CodeNode::getCode<MachineInstr*>();
728 return CodeNode::getCode<MachineBasicBlock*>();
736 return CodeNode::getCode<MachineFunction*>();
751 return static_cast<T>(
ptr(N));
757 return { ptr<T>(
N), N };
777 Iterator &up() { Pos = DS.nextUp(Pos);
return *
this; }
778 Iterator &down() { Pos = DS.nextDown(Pos);
return *
this; }
782 return DS.Stack[Pos-1];
784 const value_type *operator->()
const {
786 return &DS.Stack[Pos-1];
805 unsigned size()
const;
814 typedef std::vector<value_type> StorageType;
816 bool isDelimiter(
const StorageType::value_type &
P,
NodeId N = 0)
const {
817 return (P.Addr ==
nullptr) && (N == 0 || P.Id ==
N);
820 unsigned nextUp(
unsigned P)
const;
821 unsigned nextDown(
unsigned P)
const;
869 template <u
int16_t Kind>
875 template <u
int16_t Kind>
928 template <
typename Predicate>
933 typedef std::map<NodeId,RegisterSet> BlockRefsMap;
937 void recordDefsForDF(BlockRefsMap &PhiM, BlockRefsMap &RefM,
939 void buildPhis(BlockRefsMap &PhiM, BlockRefsMap &RefM,
941 void removeUnusedPhis();
953 IA.
Addr->removeMember(RA, *
this);
957 return BlockNodes[BB];
960 NodeAddr<FuncNode*>
Func;
961 NodeAllocator Memory;
963 std::map<MachineBasicBlock*,NodeAddr<BlockNode*>> BlockNodes;
968 const TargetInstrInfo &
TII;
969 const TargetRegisterInfo &TRI;
970 const MachineDominatorTree &MDT;
971 const MachineDominanceFrontier &MDF;
972 const TargetOperandInfo &TOI;
975 template <
typename Predicate>
982 while (NA.Addr !=
this) {
985 if (RA.
Addr->getRegRef(G) == RR &&
P(NA))
994 NA = CA.
Addr->getFirstMember(G);
1001 template <
typename Predicate>
1004 auto M = getFirstMember(G);
1008 while (M.Addr !=
this) {
1024 template <
typename T>
1025 raw_ostream &operator<< (raw_ostream &OS, const Print<T> &
P);
1027 template <
typename T>
1034 template <
typename T>
1044 #endif // LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H
NodeList members(const DataFlowGraph &G) const
raw_ostream & operator<<(raw_ostream &OS, const PrintLaneMaskOpt &P)
void pushDefs(NodeAddr< InstrNode * > IA, DefStackMap &DM)
void setReachingDef(NodeId RD)
MachineFunction & getMF() const
A common definition of LaneBitmask for use in TableGen and CodeGen.
PrintLaneMaskOpt(LaneBitmask M)
RegisterRef restrictRef(RegisterRef AR, RegisterRef BR) const
static uint16_t kind(uint16_t T)
LaneBitmask getLaneMaskForIndex(uint32_t K) const
bool alias(RegisterRef RA, RegisterRef RB) const
virtual ~TargetOperandInfo()=default
NodeAddr< RefNode * > getNextRelated(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
NodeAddr< NodeBase * > New()
NodeId getReachedDef() const
uint16_t getFlags() const
bool operator!=(const NodeAddr< T > &NA) const
static uint16_t type(uint16_t T)
NodeBase * ptr(NodeId N) const
bool operator==(const RegisterRef &RR) const
static LaneBitmask getAll()
void push(NodeAddr< DefNode * > DA)
static bool IsPreservingDef(const NodeAddr< DefNode * > DA)
const TargetInstrInfo & getTII() const
virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const
DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii, const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, const MachineDominanceFrontier &mdf, const TargetOperandInfo &toi)
uint16_t getAttrs() const
bool operator==(const NodeAddr< T > &NA) const
RegisterRef(RegisterId R, LaneBitmask M=LaneBitmask::getAll())
MachineInstr * getCode() const
static bool isCoverOf(RegisterRef RA, RegisterRef RB, const TargetRegisterInfo &TRI)
This file defines the MallocAllocator and BumpPtrAllocator interfaces.
void unlinkUse(NodeAddr< UseNode * > UA, bool RemoveFromOwner)
void releaseBlock(NodeId B, DefStackMap &DefM)
const TargetInstrInfo & TII
PackedRegisterRef pack(RegisterRef RR) const
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
A Use represents the edge between a Value definition and its users.
NodeId getReachedUse() const
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< NodeBase * > getFirstMember(const DataFlowGraph &G) const
std::vector< NodeAddr< NodeBase * > > NodeList
constexpr bool any() const
void append(NodeAddr< NodeBase * > NA)
RegisterRef unpack(PackedRegisterRef PR) const
static bool IsDef(const NodeAddr< NodeBase * > BA)
MachineFunction * getCode() const
Function Alias Analysis false
void print(raw_ostream &OS) const
uint32_t find(T Val) const
virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const
static uint16_t set_flags(uint16_t A, uint16_t F)
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
void clear_block(NodeId N)
NodeAddr< BlockNode * > findBlock(const MachineBasicBlock *BB, const DataFlowGraph &G) const
void addMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
NodeList members_if(Predicate P, const DataFlowGraph &G) const
const TargetRegisterInfo & getTRI() const
TargetInstrInfo - Interface to description of machine instruction set.
void linkToDef(NodeId Self, NodeAddr< DefNode * > DA)
NodeAllocator(uint32_t NPB=4096)
RegisterAggr & clear(RegisterRef RR)
void setFlags(uint16_t F)
void setReachedDef(NodeId D)
static bool IsRef(const NodeAddr< NodeBase * > BA)
Control flow instructions. These all have token chains.
bool hasCoverOf(RegisterRef RR) const
PrintNode(const NodeAddr< T > &x, const DataFlowGraph &g)
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
NodeAddr< BlockNode * > getEntryBlock(const DataFlowGraph &G)
static uint16_t flags(uint16_t T)
TargetOperandInfo(const TargetInstrInfo &tii)
bool operator!=(const RegisterRef &RR) const
static bool IsCode(const NodeAddr< NodeBase * > BA)
MapType::const_iterator iterator
NodeAddr< RefNode * > getNextImp(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA, bool Create)
static bool IsPhi(const NodeAddr< NodeBase * > BA)
static bool contains(uint16_t A, uint16_t B)
virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const
BlockMass operator*(BlockMass L, BranchProbability R)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
PackedRegisterRef pack(RegisterRef RR) const
NodeId getPredecessor() const
NodeAddr< NodeBase * > getLastMember(const DataFlowGraph &G) const
void setPredecessor(NodeId B)
RegisterAggr & insert(RegisterRef RR)
void markBlock(NodeId B, DefStackMap &DefM)
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
const MachineDominanceFrontier & getDF() const
MachineOperand class - Representation of each machine instruction operand.
NodeId getSibling() const
NodeAddr(const NodeAddr< S > &NA)
NodeId id(const NodeBase *P) const
void setAttrs(uint16_t A)
static uint16_t set_type(uint16_t A, uint16_t T)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
PackedRegisterRef pack(RegisterRef RR)
void addPhi(NodeAddr< PhiNode * > PA, const DataFlowGraph &G)
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
std::unordered_map< RegisterId, DefStack > DefStackMap
const MachineDominatorTree & getDT() const
std::set< NodeId > NodeSet
NodeAddr< FuncNode * > getFunc() const
RegisterRef getRegRef(const DataFlowGraph &G) const
static bool IsUse(const NodeAddr< NodeBase * > BA)
RegisterRef unpack(PackedRegisterRef PR) const
bool operator!=(uint64_t V1, const APInt &V2)
Representation of each machine instruction.
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)
RegisterRef clearIn(RegisterRef RR) const
static uint16_t set_kind(uint16_t A, uint16_t K)
void setRegRef(RegisterRef RR, DataFlowGraph &G)
PackedRegisterRef pack(RegisterRef RR)
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
void addMemberAfter(NodeAddr< NodeBase * > MA, NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
void build(unsigned Options=BuildOptions::None)
constexpr bool all() const
MachineBasicBlock * getCode() const
RegisterRef normalizeRef(RegisterRef RR) const
Print(const T &x, const DataFlowGraph &g)
bool operator<(const RegisterRef &RR) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void removeMember(NodeAddr< NodeBase * > NA, const DataFlowGraph &G)
NodeId id(const NodeBase *P) const
void unlinkDef(NodeAddr< DefNode * > DA, bool RemoveFromOwner)
MachineInstr * getCode() const
NodeAddr< T > addr(NodeId N) const
NodeId getReachingDef() const
RegisterRef normalize(RegisterRef RR) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This class implements an extremely fast bulk output stream that can only output to a stream...
bool hasAliasOf(RegisterRef RR) const
NodeBase * ptr(NodeId N) const
std::set< RegisterRef > RegisterSet
RegisterAggr(const TargetRegisterInfo &tri)
bool operator==(uint64_t V1, const APInt &V2)
uint32_t getIndexForLaneMask(LaneBitmask LM) const
NodeAddr< RefNode * > getNextRef(RegisterRef RR, Predicate P, bool NextOnly, const DataFlowGraph &G)
void start_block(NodeId N)
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
NodeAddr< RefNode * > getNextShadow(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA, bool Create)
void setReachedUse(NodeId U)
uint32_t getIndexForLaneMask(LaneBitmask LM)
void setSibling(NodeId Sib)