LLVM  4.0.0
LanaiISelLowering.h
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1 //===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Lanai uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
16 #define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
17 
18 #include "Lanai.h"
19 #include "LanaiRegisterInfo.h"
22 
23 namespace llvm {
24 namespace LanaiISD {
25 enum {
27 
29 
30  // Return with a flag operand. Operand 0 is the chain operand.
32 
33  // CALL - These operations represent an abstract call instruction, which
34  // includes a bunch of information.
36 
37  // SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
38  // is condition code and operand 4 is flag operand.
40 
41  // SETCC - Store the conditional code to a register.
43 
44  // SET_FLAG - Set flag compare.
46 
47  // SUBBF - Subtract with borrow that sets flags.
49 
50  // BR_CC - Used to glue together a conditional branch and comparison
52 
53  // Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
54  // and TargetGlobalAddress.
56 
57  // Get the Higher/Lower 16 bits from a 32-bit immediate.
58  HI,
59  LO,
60 
61  // Small 21-bit immediate in global memory.
63 };
64 } // namespace LanaiISD
65 
66 class LanaiSubtarget;
67 
69 public:
70  LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
71 
72  // LowerOperation - Provide custom lowering hooks for some operations.
73  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
74 
75  // getTargetNodeName - This method returns the name of a target specific
76  // DAG node.
77  const char *getTargetNodeName(unsigned Opcode) const override;
78 
80  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
86  SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
89  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
94 
95  unsigned getRegisterByName(const char *RegName, EVT VT,
96  SelectionDAG &DAG) const override;
97  std::pair<unsigned, const TargetRegisterClass *>
99  StringRef Constraint, MVT VT) const override;
102  const char *Constraint) const override;
103  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
104  std::vector<SDValue> &Ops,
105  SelectionDAG &DAG) const override;
106 
107  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
108 
109 private:
110  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
111  CallingConv::ID CallConv, bool IsVarArg,
112  bool IsTailCall,
114  const SmallVectorImpl<SDValue> &OutVals,
116  const SDLoc &dl, SelectionDAG &DAG,
117  SmallVectorImpl<SDValue> &InVals) const;
118 
119  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
120  bool IsVarArg,
122  const SDLoc &DL, SelectionDAG &DAG,
123  SmallVectorImpl<SDValue> &InVals) const;
124 
125  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
126  CallingConv::ID CallConv, bool IsVarArg,
128  const SDLoc &DL, SelectionDAG &DAG,
129  SmallVectorImpl<SDValue> &InVals) const;
130 
132  SmallVectorImpl<SDValue> &InVals) const override;
133 
134  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
135  bool IsVarArg,
137  const SDLoc &DL, SelectionDAG &DAG,
138  SmallVectorImpl<SDValue> &InVals) const override;
139 
140  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
142  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
143  SelectionDAG &DAG) const override;
144 
145  const LanaiRegisterInfo *TRI;
146 };
147 } // namespace llvm
148 
149 #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override
Examine constraint string and operand type and determine a weight value.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)
This contains information for each constraint that we are lowering.
SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
MVT - Machine Value Type.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
This structure contains all information that is necessary for lowering calls.
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
#define N
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Primary interface to the complete machine description for the target machine.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
This file describes how to lower LLVM code to machine code.