39 #define DEBUG_TYPE "mips16-registerinfo"
66 TII.
copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0,
true);
73 return &Mips::CPU16RegsRegClass;
79 int64_t SPOffset)
const {
89 MinCSFI = CSI[0].getFrameIdx();
90 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
102 if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)
106 if (TFI->
hasFP(MF)) {
127 Offset = SPOffset + (int64_t)StackSize;
131 DEBUG(
errs() <<
"Offset : " << Offset <<
"\n" <<
"<--------->\n");
140 FrameReg = TII.
loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm);
141 Offset = SignExtend64<16>(NewImm);
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool useFPForScavengingIndex(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const override
bool requiresRegisterScavenging(const MachineFunction &MF) const override
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static bool validImmediate(unsigned Opcode, unsigned Reg, int64_t Amount)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
const TargetRegisterClass * intRegClass(unsigned Size) const override
Return GPR register class.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
unsigned loadImmediate(unsigned FrameReg, int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned &NewImm) const
Emit a series of instructions to load an immediate.
bool isDebugValue() const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
virtual const TargetFrameLowering * getFrameLowering() const
Information about stack frame layout on the target.
Representation of each machine instruction.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const