14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
34 #define GET_SUBTARGETINFO_HEADER
35 #include "ARMGenSubtargetInfo.inc"
41 class ARMBaseTargetMachine;
377 return InstrInfo.get();
383 return FrameLowering.get();
386 return &InstrInfo->getRegisterInfo();
397 std::unique_ptr<ARMFrameLowering> FrameLowering;
399 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
405 std::unique_ptr<GISelAccessor> GISel;
407 void initializeEnvironment();
661 #endif // ARMSUBTARGET_H
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
bool avoidCPSRPartialUpdate() const
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
bool ExpandMLx
If true, run the MLx expansion pass.
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
bool avoidMOVsShifterOperand() const
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool useR7AsFramePointer() const
unsigned getMispredictionPenalty() const
bool isAAPCS16_ABI() const
const std::string & getCPUString() const
bool hasMuxedUnits() const
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
unsigned getPartialUpdateClearance() const
bool isTargetEHABICompatible() const
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
const ARMTargetLowering * getTargetLowering() const override
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
bool hasT2ExtractPack() const
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
bool useFastISel() const
True if fast-isel is used.
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
bool checkVLDnAccessAlignment() const
const LegalizerInfo * getLegalizerInfo() const override
bool isThumb1Only() const
const ARMBaseTargetMachine & TM
bool GenLongCalls
Generate calls via indirect call instructions.
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
bool isAndroid() const
Tests whether the target is Android.
bool isOSWindows() const
Tests whether the OS is Windows.
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
const ARMBaseInstrInfo * getInstrInfo() const override
bool isR9Reserved() const
Can load/store 1 register/cycle.
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
bool isTargetAEABI() const
Holds all the information related to register banks.
bool useSoftFloat() const
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
bool useNEONForFPMovs() const
bool isTargetDarwin() const
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types...
bool hasV8MMainlineOps() const
bool useStride4VFPs(const MachineFunction &MF) const
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
bool hasMPExtension() const
void setGISelAccessor(GISelAccessor &GISel)
This object will take onwership of GISelAccessor.
bool isFPBrccSlow() const
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
bool isOSLinux() const
Tests whether the OS is Linux.
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
bool IsLittle
IsLittle - The target is Little Endian.
const Triple & getTargetTriple() const
bool isTargetCOFF() const
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
bool enableAtomicExpand() const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
virtual bool isXRaySupported() const override
bool isTargetMachO() const
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
bool prefers32BitThumb() const
bool hasSlowVDUP32() const
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
bool hasAnyDataBarrier() const
Itinerary data supplied by a subtarget to be used by a target.
bool HasT2ExtractPack
HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.
bool isTargetWatchOS() const
bool dontWidenVMOVS() const
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
bool isTargetNetBSD() const
bool isiOS() const
Is this an iOS triple.
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
bool isTargetHardFloat() const
bool supportsTailCall() const
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
bool hasVirtualization() const
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
bool isWatchOS() const
Is this an Apple watchOS triple.
bool isTargetWatchABI() const
bool hasVMLxForwarding() const
bool hasZeroCycleZeroing() const
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
bool useNEONForSinglePrecisionFP() const
const ARMFrameLowering * getFrameLowering() const override
bool hasV8MBaselineOps() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
const CallLowering * getCallLowering() const override
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
bool hasRetAddrStack() const
bool hasVMLxHazards() const
ARMLdStMultipleTiming getLdStMultipleTiming() const
bool genExecuteOnly() const
Triple - Helper class for working with autoconf configuration names.
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
bool hasSlowOddRegister() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
bool genLongCalls() const
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool isTargetNaCl() const
bool hasSlowLoadDSubregister() const
bool preferVMOVSR() const
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
const InstructionSelector * getInstructionSelector() const override
ARMArchEnum ARMArch
ARMArch - ARM architecture.
bool FPOnlySP
FPOnlySP - If true, the floating point unit only supports single precision.
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
bool isTargetAndroid() const
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
bool hasAcquireRelease() const
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
bool hasSlowVGETLNi32() const
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
const TargetOptions & Options
Options passed via command line that could influence the target.
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool UseSoftFloat
UseSoftFloat - True if we're using software floating point features.
bool isTargetGNUAEABI() const
bool nonpipelinedVFP() const
Provides the logic to select generic machine instructions.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
bool isTargetLinux() const
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
unsigned getMaxInterleaveFactor() const
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
const ARMBaseRegisterInfo * getRegisterInfo() const override
bool allowsUnalignedMem() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isProfitableToUnpredicate() const
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
bool useMovt(const MachineFunction &MF) const
int getPreISelOperandLatencyAdjustment() const
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
bool hasTrustZone() const
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
bool isTargetMuslAEABI() const
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
bool HasD16
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Can load/store 2 registers/cycle.
bool preferISHSTBarriers() const
bool hasDataBarrier() const
std::string CPUString
CPUString - String name of used CPU.
bool hasDivideInARMMode() const
StringRef - Represent a constant reference to a string, i.e.
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Machine model for scheduling, bundling, and heuristics.
bool isTargetWindows() const
bool HasHardwareDivide
HasHardwareDivide - True if subtarget supports [su]div.
const RegisterBankInfo * getRegBankInfo() const override
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
unsigned MaxInterleaveFactor