24 using namespace Hexagon;
26 #define DEBUG_TYPE "hexagon-mcduplex-info"
29 static const std::pair<unsigned, unsigned>
opcodeData[] = {
30 std::make_pair((
unsigned)SA1_addi, 0),
31 std::make_pair((
unsigned)SA1_addrx, 6144),
32 std::make_pair((
unsigned)SA1_addsp, 3072),
33 std::make_pair((
unsigned)SA1_and1, 4608),
34 std::make_pair((
unsigned)SA1_clrf, 6768),
35 std::make_pair((
unsigned)SA1_clrfnew, 6736),
36 std::make_pair((
unsigned)SA1_clrt, 6752),
37 std::make_pair((
unsigned)SA1_clrtnew, 6720),
38 std::make_pair((
unsigned)SA1_cmpeqi, 6400),
39 std::make_pair((
unsigned)SA1_combine0i, 7168),
40 std::make_pair((
unsigned)SA1_combine1i, 7176),
41 std::make_pair((
unsigned)SA1_combine2i, 7184),
42 std::make_pair((
unsigned)SA1_combine3i, 7192),
43 std::make_pair((
unsigned)SA1_combinerz, 7432),
44 std::make_pair((
unsigned)SA1_combinezr, 7424),
45 std::make_pair((
unsigned)SA1_dec, 4864),
46 std::make_pair((
unsigned)SA1_inc, 4352),
47 std::make_pair((
unsigned)SA1_seti, 2048),
48 std::make_pair((
unsigned)SA1_setin1, 6656),
49 std::make_pair((
unsigned)SA1_sxtb, 5376),
50 std::make_pair((
unsigned)SA1_sxth, 5120),
51 std::make_pair((
unsigned)SA1_tfr, 4096),
52 std::make_pair((
unsigned)SA1_zxtb, 5888),
53 std::make_pair((
unsigned)SA1_zxth, 5632),
54 std::make_pair((
unsigned)SL1_loadri_io, 0),
55 std::make_pair((
unsigned)SL1_loadrub_io, 4096),
56 std::make_pair((
unsigned)SL2_deallocframe, 7936),
57 std::make_pair((
unsigned)SL2_jumpr31, 8128),
58 std::make_pair((
unsigned)SL2_jumpr31_f, 8133),
59 std::make_pair((
unsigned)SL2_jumpr31_fnew, 8135),
60 std::make_pair((
unsigned)SL2_jumpr31_t, 8132),
61 std::make_pair((
unsigned)SL2_jumpr31_tnew, 8134),
62 std::make_pair((
unsigned)SL2_loadrb_io, 4096),
63 std::make_pair((
unsigned)SL2_loadrd_sp, 7680),
64 std::make_pair((
unsigned)SL2_loadrh_io, 0),
65 std::make_pair((
unsigned)SL2_loadri_sp, 7168),
66 std::make_pair((
unsigned)SL2_loadruh_io, 2048),
67 std::make_pair((
unsigned)SL2_return, 8000),
68 std::make_pair((
unsigned)SL2_return_f, 8005),
69 std::make_pair((
unsigned)SL2_return_fnew, 8007),
70 std::make_pair((
unsigned)SL2_return_t, 8004),
71 std::make_pair((
unsigned)SL2_return_tnew, 8006),
72 std::make_pair((
unsigned)SS1_storeb_io, 4096),
73 std::make_pair((
unsigned)SS1_storew_io, 0),
74 std::make_pair((
unsigned)SS2_allocframe, 7168),
75 std::make_pair((
unsigned)SS2_storebi0, 4608),
76 std::make_pair((
unsigned)SS2_storebi1, 4864),
77 std::make_pair((
unsigned)SS2_stored_sp, 2560),
78 std::make_pair((
unsigned)SS2_storeh_io, 0),
79 std::make_pair((
unsigned)SS2_storew_sp, 2048),
80 std::make_pair((
unsigned)SS2_storewi0, 4096),
81 std::make_pair((
unsigned)SS2_storewi1, 4352)};
178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
188 case Hexagon::L2_loadri_io:
195 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
200 inRange<4, 2>(MCI, 2)) {
205 case Hexagon::L2_loadrub_io:
211 inRange<4>(MCI, 2)) {
225 case Hexagon::L2_loadrh_io:
226 case Hexagon::L2_loadruh_io:
232 inRange<3, 1>(MCI, 2)) {
236 case Hexagon::L2_loadrb_io:
242 inRange<3>(MCI, 2)) {
246 case Hexagon::L2_loadrd_io:
252 inRange<5, 3>(MCI, 2)) {
257 case Hexagon::L4_return:
259 case Hexagon::L2_deallocframe:
262 case Hexagon::EH_RETURN_JMPR:
264 case Hexagon::J2_jumpr:
268 if (Hexagon::R31 == DstReg)
272 case Hexagon::J2_jumprt:
273 case Hexagon::J2_jumprf:
274 case Hexagon::J2_jumprtnew:
275 case Hexagon::J2_jumprfnew:
276 case Hexagon::J2_jumprtnewpt:
277 case Hexagon::J2_jumprfnewpt:
282 (Hexagon::R31 == DstReg)) {
286 case Hexagon::L4_return_t:
288 case Hexagon::L4_return_f:
290 case Hexagon::L4_return_tnew_pnt:
292 case Hexagon::L4_return_fnew_pnt:
294 case Hexagon::L4_return_tnew_pt:
296 case Hexagon::L4_return_fnew_pt:
299 if (Hexagon::P0 == SrcReg) {
308 case Hexagon::S2_storeri_io:
315 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {
321 inRange<4, 2>(MCI, 1)) {
325 case Hexagon::S2_storerb_io:
331 inRange<4>(MCI, 1)) {
344 case Hexagon::S2_storerh_io:
350 inRange<3, 1>(MCI, 1)) {
354 case Hexagon::S2_storerd_io:
360 inSRange<6, 3>(MCI, 1)) {
364 case Hexagon::S4_storeiri_io:
368 inRange<4, 2>(MCI, 1) && inRange<1>(MCI, 2)) {
372 case Hexagon::S4_storeirb_io:
376 inRange<4>(MCI, 1) && inRange<1>(MCI, 2)) {
380 case Hexagon::S2_allocframe:
381 if (inRange<5, 3>(MCI, 0))
402 case Hexagon::A2_addi:
408 inRange<6, 2>(MCI, 2)) {
412 if (DstReg == SrcReg) {
423 case Hexagon::A2_add:
433 case Hexagon::A2_andir:
442 case Hexagon::A2_tfr:
451 case Hexagon::A2_tfrsi:
458 case Hexagon::C2_cmoveit:
459 case Hexagon::C2_cmovenewit:
460 case Hexagon::C2_cmoveif:
461 case Hexagon::C2_cmovenewif:
468 Hexagon::P0 == PredReg &&
minConstant(MCI, 2) == 0) {
472 case Hexagon::C2_cmpeqi:
476 if (Hexagon::P0 == DstReg &&
478 inRange<2>(MCI, 2)) {
482 case Hexagon::A2_combineii:
483 case Hexagon::A4_combineii:
487 inRange<2>(MCI, 1) && inRange<2>(MCI, 2)) {
491 case Hexagon::A4_combineri:
501 case Hexagon::A4_combineir:
511 case Hexagon::A2_sxtb:
512 case Hexagon::A2_sxth:
513 case Hexagon::A2_zxtb:
514 case Hexagon::A2_zxth:
529 unsigned DstReg, SrcReg;
531 case Hexagon::A2_addi:
539 if (!isShiftedInt<7, 0>(Value))
543 case Hexagon::A2_tfrsi:
554 if (!isShiftedUInt<6, 0>(Value))
566 MCInst const &MIa,
bool ExtendedA,
567 MCInst const &MIb,
bool ExtendedB,
568 bool bisReversable) {
575 if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))
590 unsigned zeroedSubInstS0 =
591 subinstOpcodeMap.find(SubInst0.
getOpcode())->second;
592 unsigned zeroedSubInstS1 =
593 subinstOpcodeMap.find(SubInst1.
getOpcode())->second;
595 if (zeroedSubInstS0 < zeroedSubInstS1)
602 if (MIb.
getOpcode() == Hexagon::S2_allocframe)
693 case Hexagon::A2_addi:
695 assert(Absolute);(void)Absolute;
702 else if (Value == -1) {
721 case Hexagon::A2_add:
727 case Hexagon::S2_allocframe:
728 Result.
setOpcode(Hexagon::SS2_allocframe);
731 case Hexagon::A2_andir:
743 case Hexagon::C2_cmpeqi:
748 case Hexagon::A4_combineii:
749 case Hexagon::A2_combineii:
751 assert(Absolute);(void)Absolute;
753 Result.
setOpcode(Hexagon::SA1_combine1i);
759 Result.
setOpcode(Hexagon::SA1_combine3i);
765 Result.
setOpcode(Hexagon::SA1_combine0i);
771 Result.
setOpcode(Hexagon::SA1_combine2i);
776 case Hexagon::A4_combineir:
777 Result.
setOpcode(Hexagon::SA1_combinezr);
782 case Hexagon::A4_combineri:
783 Result.
setOpcode(Hexagon::SA1_combinerz);
787 case Hexagon::L4_return_tnew_pnt:
788 case Hexagon::L4_return_tnew_pt:
789 Result.
setOpcode(Hexagon::SL2_return_tnew);
791 case Hexagon::L4_return_fnew_pnt:
792 case Hexagon::L4_return_fnew_pt:
793 Result.
setOpcode(Hexagon::SL2_return_fnew);
795 case Hexagon::L4_return_f:
798 case Hexagon::L4_return_t:
801 case Hexagon::L4_return:
804 case Hexagon::L2_deallocframe:
805 Result.
setOpcode(Hexagon::SL2_deallocframe);
807 case Hexagon::EH_RETURN_JMPR:
808 case Hexagon::J2_jumpr:
811 case Hexagon::J2_jumprf:
812 Result.
setOpcode(Hexagon::SL2_jumpr31_f);
814 case Hexagon::J2_jumprfnew:
815 case Hexagon::J2_jumprfnewpt:
816 Result.
setOpcode(Hexagon::SL2_jumpr31_fnew);
818 case Hexagon::J2_jumprt:
819 Result.
setOpcode(Hexagon::SL2_jumpr31_t);
821 case Hexagon::J2_jumprtnew:
822 case Hexagon::J2_jumprtnewpt:
823 Result.
setOpcode(Hexagon::SL2_jumpr31_tnew);
825 case Hexagon::L2_loadrb_io:
826 Result.
setOpcode(Hexagon::SL2_loadrb_io);
831 case Hexagon::L2_loadrd_io:
832 Result.
setOpcode(Hexagon::SL2_loadrd_sp);
836 case Hexagon::L2_loadrh_io:
837 Result.
setOpcode(Hexagon::SL2_loadrh_io);
842 case Hexagon::L2_loadrub_io:
843 Result.
setOpcode(Hexagon::SL1_loadrub_io);
848 case Hexagon::L2_loadruh_io:
849 Result.
setOpcode(Hexagon::SL2_loadruh_io);
854 case Hexagon::L2_loadri_io:
856 Result.
setOpcode(Hexagon::SL2_loadri_sp);
861 Result.
setOpcode(Hexagon::SL1_loadri_io);
867 case Hexagon::S4_storeirb_io:
869 assert(Absolute);(void)Absolute;
875 }
else if (Value == 1) {
881 case Hexagon::S2_storerb_io:
882 Result.
setOpcode(Hexagon::SS1_storeb_io);
887 case Hexagon::S2_storerd_io:
888 Result.
setOpcode(Hexagon::SS2_stored_sp);
892 case Hexagon::S2_storerh_io:
893 Result.
setOpcode(Hexagon::SS2_storeh_io);
898 case Hexagon::S4_storeiri_io:
900 assert(Absolute);(void)Absolute;
906 }
else if (Value == 1) {
912 Result.
setOpcode(Hexagon::SS2_storew_sp);
917 case Hexagon::S2_storeri_io:
919 Result.
setOpcode(Hexagon::SS2_storew_sp);
923 Result.
setOpcode(Hexagon::SS1_storew_io);
929 case Hexagon::A2_sxtb:
934 case Hexagon::A2_sxth:
939 case Hexagon::A2_tfr:
944 case Hexagon::C2_cmovenewif:
949 case Hexagon::C2_cmovenewit:
954 case Hexagon::C2_cmoveif:
959 case Hexagon::C2_cmoveit:
964 case Hexagon::A2_tfrsi:
966 if (Absolute && Value == -1) {
976 case Hexagon::A2_zxtb:
982 case Hexagon::A2_zxth:
993 case Hexagon::S2_storeri_io:
994 case Hexagon::S2_storerb_io:
995 case Hexagon::S2_storerh_io:
996 case Hexagon::S2_storerd_io:
997 case Hexagon::S4_storeiri_io:
998 case Hexagon::S4_storeirb_io:
999 case Hexagon::S2_allocframe:
1014 for (
unsigned distance = 1; distance < numInstrInPacket; ++distance) {
1017 (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {
1020 bool bisReversable =
true;
1023 DEBUG(
dbgs() <<
"skip out of order write pair: " << k <<
"," << j
1025 bisReversable =
false;
1028 bisReversable =
false;
1044 DEBUG(
dbgs() <<
"adding pair: " << j <<
"," << k <<
":"
1049 DEBUG(
dbgs() <<
"skipping pair: " << j <<
"," << k <<
":"
1055 if (bisReversable) {
1069 DEBUG(
dbgs() <<
"adding pair:" << k <<
"," << j <<
":"
1073 DEBUG(
dbgs() <<
"skipping pair: " << k <<
"," << j <<
":"
void push_back(const T &Elt)
const_iterator end(StringRef path)
Get end iterator over path.
bool subInstWouldBeExtended(MCInst const &potentialDuplex)
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb)
Symmetrical. See if these two instructions are fit for duplex pair.
static const std::pair< unsigned, unsigned > opcodeData[]
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
const_iterator begin(StringRef path)
Get begin iterator over path.
bool isDblRegForSubInst(unsigned Reg)
unsigned getReg() const
Returns the register number.
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCInst const &MCB)
Instances of this class represent a single low-level machine instruction.
bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
const MCExpr * getExpr() const
unsigned getDuplexCandidateGroup(MCInst const &MI)
Interface to description of machine instruction set.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addOps(MCInst &subInstPtr, MCInst const &Inst, unsigned opNum)
void setOpcode(unsigned Op)
size_t const bundleInstructionsOffset
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
int64_t minConstant(MCInst const &MCI, size_t Index)
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable)
non-Symmetrical. See if these two instructions are fit for duplex pair.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
bool isMemReorderDisabled(MCInst const &MCI)
MCInst deriveSubInst(MCInst const &Inst)
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
unsigned getNumOperands() const
const MCInst * getInst() const
static bool isStoreInst(unsigned opCode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
bool isPredReg(unsigned Reg)
bool isIntReg(unsigned Reg)
void addOperand(const MCOperand &Op)
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb)
const MCOperand & getOperand(unsigned i) const