32 #define DEBUG_TYPE "reg-scavenging"
37 if (UnitMask.
none() || (LaneMask & UnitMask).any())
38 RegUnitsAvailable.
reset((*RUI).first);
54 RegUnitsAvailable.
resize(NumRegUnits);
55 KillRegUnits.
resize(NumRegUnits);
56 DefRegUnits.
resize(NumRegUnits);
57 TmpRegUnits.
resize(NumRegUnits);
68 RegUnitsAvailable.
set();
79 for (
const auto &LI : MBB.
liveins())
92 setLiveInsUsed(*Succ);
96 MBBI = std::prev(MBB.
end());
101 void RegScavenger::addRegUnits(
BitVector &BV,
unsigned Reg) {
106 void RegScavenger::removeRegUnits(
BitVector &BV,
unsigned Reg) {
111 void RegScavenger::determineKillsAndDefs() {
112 assert(Tracking &&
"Must be tracking to determine kills and defs");
119 KillRegUnits.
reset();
122 if (MO.isRegMask()) {
124 for (
unsigned RU = 0, RUEnd = TRI->
getNumRegUnits(); RU != RUEnd; ++RU) {
126 if (MO.clobbersPhysReg(*RURI)) {
134 KillRegUnits |= TmpRegUnits;
138 unsigned Reg = MO.getReg();
147 addRegUnits(KillRegUnits, Reg);
151 addRegUnits(KillRegUnits, Reg);
153 addRegUnits(DefRegUnits, Reg);
159 assert(Tracking &&
"Cannot unprocess because we're not tracking");
163 determineKillsAndDefs();
166 setUsed(KillRegUnits);
167 setUnused(DefRegUnits);
170 if (MBBI == MBB->
begin()) {
183 assert(MBBI != MBB->
end() &&
"Already past the end of the basic block!");
184 MBBI = std::next(MBBI);
186 assert(MBBI != MBB->
end() &&
"Already at the end of the basic block!");
192 if (
I->Restore != &MI)
196 I->Restore =
nullptr;
199 if (MI.isDebugValue())
202 determineKillsAndDefs();
209 unsigned Reg = MO.getReg();
224 bool SubUsed =
false;
230 bool SuperUsed =
false;
237 if (!SubUsed && !SuperUsed) {
249 assert((KillRegs.test(Reg) || isUnused(Reg) ||
250 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
251 "Re-defining a live register!");
258 setUnused(KillRegUnits);
259 setUsed(DefRegUnits);
263 assert(Tracking &&
"Must be tracking to determine kills and defs");
268 if (MO.isRegMask()) {
272 if (MO.clobbersPhysReg(*RURI)) {
273 RegUnitsAvailable.
set(RU);
278 }
else if (MO.isReg() && MO.isDef()) {
279 unsigned Reg = MO.getReg();
283 addRegUnits(RegUnitsAvailable, Reg);
288 if (MO.isReg() && MO.readsReg()) {
289 unsigned Reg = MO.getReg();
293 removeRegUnits(RegUnitsAvailable, Reg);
297 if (MBBI == MBB->
begin()) {
305 if (includeReserved && isReserved(Reg))
308 if (!RegUnitsAvailable.
test(*RUI))
314 for (
unsigned Reg : *RC) {
326 for (
unsigned Reg : *RC)
337 assert(Survivor > 0 &&
"No candidates for scavenging");
340 assert(StartMI != ME &&
"MI already at terminator");
344 bool inVirtLiveRange =
false;
345 for (++MI; InstrLimit > 0 && MI != ME; ++
MI, --
InstrLimit) {
346 if (MI->isDebugValue()) {
350 bool isVirtKillInsn =
false;
351 bool isVirtDefInsn =
false;
356 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
360 isVirtDefInsn =
true;
361 else if (MO.isKill())
362 isVirtKillInsn =
true;
366 Candidates.
reset(*AI);
370 if (!inVirtLiveRange) RestorePointMI =
MI;
373 if (isVirtKillInsn) inVirtLiveRange =
false;
374 if (isVirtDefInsn) inVirtLiveRange =
true;
377 if (Candidates.
test(Survivor))
381 if (Candidates.
none())
387 if (MI == ME) RestorePointMI = ME;
388 assert(RestorePointMI != StartMI &&
389 "No available scavenger restore location!");
392 UseMI = RestorePointMI;
415 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
418 Candidates.
reset(*AI);
424 Available &= Candidates;
426 Candidates = Available;
430 unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
441 unsigned NeedSize = RC->
getSize();
444 unsigned SI = Scavenged.
size(), Diff = UINT_MAX;
446 for (
unsigned I = 0; I < Scavenged.
size(); ++
I) {
447 if (Scavenged[I].Reg != 0)
450 int FI = Scavenged[
I].FrameIndex;
451 if (FI < FIB || FI >= FIE)
455 if (NeedSize > S || NeedAlign > A)
463 unsigned D = (S-NeedSize) + (A-NeedAlign);
470 if (SI == Scavenged.
size()) {
477 Scavenged[SI].Reg = SReg;
483 int FI = Scavenged[SI].FrameIndex;
484 if (FI < FIB || FI >= FIE) {
485 std::string Msg = std::string(
"Error while trying to spill ") +
487 ": Cannot scavenge register without an emergency spill slot!";
500 II = std::prev(UseMI);
506 Scavenged[SI].Restore = &*std::prev(UseMI);
511 DEBUG(
dbgs() <<
"Scavenged register (with spill): " << TRI->
getName(SReg) <<
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isValid() const
Check if the iterator is at the end of the list.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
iterator_range< livein_iterator > liveins() const
bool isValid() const
Returns true if this iterator is not yet at the end.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
Spill the register so it can be used by the register scavenger.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
bool none() const
none - Returns true if none of the bits are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
MachineInstrBundleIterator< MachineInstr > iterator
bool any() const
any - Returns true if any bit is set.
iterator_range< mop_iterator > operands()
iterator_range< succ_iterator > successors()
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
void clear()
clear - Clear all bits.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
MCSuperRegIterator enumerates all super-registers of Reg.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void backward()
Update internal register state and move MBB iterator backwards.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void forward()
Move the internal MBB iterator and update register states.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
int getObjectIndexBegin() const
Return the minimum frame object index.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MCRegUnitRootIterator enumerates the root registers of a register unit.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
const MachineBasicBlock * getParent() const
bool isDebugValue() const
void clearBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsNotInMask - Clear a bit in this vector for every '0' bit in Mask.
This file declares the machine register scavenger class.
constexpr bool none() const
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
const MachineOperand & getOperand(unsigned i) const
void unprocess()
Invert the behavior of forward() on the current instruction (undo the changes to the available regist...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
MCRegAliasIterator enumerates all registers aliasing Reg.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool test(unsigned Idx) const
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
static unsigned getFrameIndexOperandNum(MachineInstr &MI)
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const
Find an unused register of the specified register class.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static cl::opt< unsigned > InstrLimit("dfa-instr-limit", cl::Hidden, cl::init(0), cl::desc("If present, stops packetizing after N instructions"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void setRegUsed(unsigned Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
virtual const TargetInstrInfo * getInstrInfo() const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned scavengeRegister(const TargetRegisterClass *RegClass, MachineBasicBlock::iterator I, int SPAdj)
Make a register of the specific register class available and do the appropriate bookkeeping.