35 #define DEBUG_TYPE "arm-pseudo"
39 cl::desc(
"Verify machine code after expanding ARM pseudos"));
60 return "ARM pseudo instruction expansion pass";
74 unsigned Opc,
bool IsExt);
79 unsigned StrexOp,
unsigned UxtOp,
91 void ARMExpandPseudo::TransferImpOps(
MachineInstr &OldMI,
119 struct NEONLdStTableEntry {
124 bool hasWritebackOperand;
133 bool copyAllListRegs;
136 bool operator<(
const NEONLdStTableEntry &TE)
const {
137 return PseudoOpc < TE.PseudoOpc;
139 friend bool operator<(
const NEONLdStTableEntry &TE,
unsigned PseudoOpc) {
140 return TE.PseudoOpc < PseudoOpc;
143 const NEONLdStTableEntry &TE) {
144 return PseudoOpc < TE.PseudoOpc;
150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16,
true,
false,
false, EvenDblSpc, 1, 4 ,
true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD,
true,
true,
true, EvenDblSpc, 1, 4 ,
true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32,
true,
false,
false, EvenDblSpc, 1, 2 ,
true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD,
true,
true,
true, EvenDblSpc, 1, 2 ,
true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8,
true,
false,
false, EvenDblSpc, 1, 8 ,
true},
155 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD,
true,
true,
true, EvenDblSpc, 1, 8 ,
true},
157 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleSpc, 4, 1 ,
false},
158 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed,
true,
true,
false, SingleSpc, 4, 1 ,
false},
159 { ARM::VLD1d64TPseudo, ARM::VLD1d64T,
true,
false,
false, SingleSpc, 3, 1 ,
false},
160 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed,
true,
true,
false, SingleSpc, 3, 1 ,
false},
162 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16,
true,
false,
false, SingleSpc, 2, 4 ,
true},
163 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD,
true,
true,
true, SingleSpc, 2, 4 ,
true},
164 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32,
true,
false,
false, SingleSpc, 2, 2 ,
true},
165 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD,
true,
true,
true, SingleSpc, 2, 2 ,
true},
166 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8,
true,
false,
false, SingleSpc, 2, 8 ,
true},
167 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD,
true,
true,
true, SingleSpc, 2, 8 ,
true},
168 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16,
true,
false,
false, EvenDblSpc, 2, 4 ,
true},
169 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD,
true,
true,
true, EvenDblSpc, 2, 4 ,
true},
170 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32,
true,
false,
false, EvenDblSpc, 2, 2 ,
true},
171 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD,
true,
true,
true, EvenDblSpc, 2, 2 ,
true},
173 { ARM::VLD2q16Pseudo, ARM::VLD2q16,
true,
false,
false, SingleSpc, 4, 4 ,
false},
174 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
175 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
176 { ARM::VLD2q32Pseudo, ARM::VLD2q32,
true,
false,
false, SingleSpc, 4, 2 ,
false},
177 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
178 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
179 { ARM::VLD2q8Pseudo, ARM::VLD2q8,
true,
false,
false, SingleSpc, 4, 8 ,
false},
180 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
181 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
183 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16,
true,
false,
false, SingleSpc, 3, 4,
true},
184 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD,
true,
true,
true, SingleSpc, 3, 4,
true},
185 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32,
true,
false,
false, SingleSpc, 3, 2,
true},
186 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD,
true,
true,
true, SingleSpc, 3, 2,
true},
187 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8,
true,
false,
false, SingleSpc, 3, 8,
true},
188 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD,
true,
true,
true, SingleSpc, 3, 8,
true},
190 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
191 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
192 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
193 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
194 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
195 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
196 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
197 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
198 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
199 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
201 { ARM::VLD3d16Pseudo, ARM::VLD3d16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
202 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
203 { ARM::VLD3d32Pseudo, ARM::VLD3d32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
204 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
205 { ARM::VLD3d8Pseudo, ARM::VLD3d8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
206 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
208 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
209 { ARM::VLD3q16oddPseudo, ARM::VLD3q16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
210 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
211 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
212 { ARM::VLD3q32oddPseudo, ARM::VLD3q32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
213 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
214 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, EvenDblSpc, 3, 8 ,
true},
215 { ARM::VLD3q8oddPseudo, ARM::VLD3q8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
216 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
218 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16,
true,
false,
false, SingleSpc, 4, 4,
true},
219 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD,
true,
true,
true, SingleSpc, 4, 4,
true},
220 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32,
true,
false,
false, SingleSpc, 4, 2,
true},
221 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD,
true,
true,
true, SingleSpc, 4, 2,
true},
222 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8,
true,
false,
false, SingleSpc, 4, 8,
true},
223 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD,
true,
true,
true, SingleSpc, 4, 8,
true},
225 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
226 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
227 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
228 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
229 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
230 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
231 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
232 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
233 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
234 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
236 { ARM::VLD4d16Pseudo, ARM::VLD4d16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
237 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
238 { ARM::VLD4d32Pseudo, ARM::VLD4d32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
239 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
240 { ARM::VLD4d8Pseudo, ARM::VLD4d8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
241 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
243 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
244 { ARM::VLD4q16oddPseudo, ARM::VLD4q16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
245 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
246 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
247 { ARM::VLD4q32oddPseudo, ARM::VLD4q32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
248 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
249 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, EvenDblSpc, 4, 8 ,
true},
250 { ARM::VLD4q8oddPseudo, ARM::VLD4q8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
251 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
253 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16,
false,
false,
false, EvenDblSpc, 1, 4 ,
true},
254 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,
false,
true,
true, EvenDblSpc, 1, 4 ,
true},
255 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32,
false,
false,
false, EvenDblSpc, 1, 2 ,
true},
256 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,
false,
true,
true, EvenDblSpc, 1, 2 ,
true},
257 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8,
false,
false,
false, EvenDblSpc, 1, 8 ,
true},
258 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD,
false,
true,
true, EvenDblSpc, 1, 8 ,
true},
260 { ARM::VST1d64QPseudo, ARM::VST1d64Q,
false,
false,
false, SingleSpc, 4, 1 ,
false},
261 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed,
false,
true,
false, SingleSpc, 4, 1 ,
false},
262 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register,
false,
true,
true, SingleSpc, 4, 1 ,
false},
263 { ARM::VST1d64TPseudo, ARM::VST1d64T,
false,
false,
false, SingleSpc, 3, 1 ,
false},
264 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed,
false,
true,
false, SingleSpc, 3, 1 ,
false},
265 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register,
false,
true,
true, SingleSpc, 3, 1 ,
false},
267 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16,
false,
false,
false, SingleSpc, 2, 4 ,
true},
268 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD,
false,
true,
true, SingleSpc, 2, 4 ,
true},
269 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32,
false,
false,
false, SingleSpc, 2, 2 ,
true},
270 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD,
false,
true,
true, SingleSpc, 2, 2 ,
true},
271 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8,
false,
false,
false, SingleSpc, 2, 8 ,
true},
272 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD,
false,
true,
true, SingleSpc, 2, 8 ,
true},
273 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16,
false,
false,
false, EvenDblSpc, 2, 4,
true},
274 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD,
false,
true,
true, EvenDblSpc, 2, 4,
true},
275 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32,
false,
false,
false, EvenDblSpc, 2, 2,
true},
276 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD,
false,
true,
true, EvenDblSpc, 2, 2,
true},
278 { ARM::VST2q16Pseudo, ARM::VST2q16,
false,
false,
false, SingleSpc, 4, 4 ,
false},
279 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
280 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
281 { ARM::VST2q32Pseudo, ARM::VST2q32,
false,
false,
false, SingleSpc, 4, 2 ,
false},
282 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
283 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
284 { ARM::VST2q8Pseudo, ARM::VST2q8,
false,
false,
false, SingleSpc, 4, 8 ,
false},
285 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
286 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
288 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
289 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
290 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
291 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
292 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
293 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
294 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16,
false,
false,
false, EvenDblSpc, 3, 4,
true},
295 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD,
false,
true,
true, EvenDblSpc, 3, 4,
true},
296 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32,
false,
false,
false, EvenDblSpc, 3, 2,
true},
297 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD,
false,
true,
true, EvenDblSpc, 3, 2,
true},
299 { ARM::VST3d16Pseudo, ARM::VST3d16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
300 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
301 { ARM::VST3d32Pseudo, ARM::VST3d32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
302 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
303 { ARM::VST3d8Pseudo, ARM::VST3d8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
304 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
306 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, EvenDblSpc, 3, 4 ,
true},
307 { ARM::VST3q16oddPseudo, ARM::VST3q16,
false,
false,
false, OddDblSpc, 3, 4 ,
true},
308 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, OddDblSpc, 3, 4 ,
true},
309 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, EvenDblSpc, 3, 2 ,
true},
310 { ARM::VST3q32oddPseudo, ARM::VST3q32,
false,
false,
false, OddDblSpc, 3, 2 ,
true},
311 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, OddDblSpc, 3, 2 ,
true},
312 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, EvenDblSpc, 3, 8 ,
true},
313 { ARM::VST3q8oddPseudo, ARM::VST3q8,
false,
false,
false, OddDblSpc, 3, 8 ,
true},
314 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, OddDblSpc, 3, 8 ,
true},
316 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
317 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
318 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
319 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
320 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
321 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
322 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16,
false,
false,
false, EvenDblSpc, 4, 4,
true},
323 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD,
false,
true,
true, EvenDblSpc, 4, 4,
true},
324 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32,
false,
false,
false, EvenDblSpc, 4, 2,
true},
325 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD,
false,
true,
true, EvenDblSpc, 4, 2,
true},
327 { ARM::VST4d16Pseudo, ARM::VST4d16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
328 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
329 { ARM::VST4d32Pseudo, ARM::VST4d32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
330 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
331 { ARM::VST4d8Pseudo, ARM::VST4d8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
332 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
334 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, EvenDblSpc, 4, 4 ,
true},
335 { ARM::VST4q16oddPseudo, ARM::VST4q16,
false,
false,
false, OddDblSpc, 4, 4 ,
true},
336 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, OddDblSpc, 4, 4 ,
true},
337 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, EvenDblSpc, 4, 2 ,
true},
338 { ARM::VST4q32oddPseudo, ARM::VST4q32,
false,
false,
false, OddDblSpc, 4, 2 ,
true},
339 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, OddDblSpc, 4, 2 ,
true},
340 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, EvenDblSpc, 4, 8 ,
true},
341 { ARM::VST4q8oddPseudo, ARM::VST4q8,
false,
false,
false, OddDblSpc, 4, 8 ,
true},
342 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, OddDblSpc, 4, 8 ,
true}
350 static bool TableChecked =
false;
353 "NEONLdStTable is not sorted!");
370 unsigned &D1,
unsigned &D2,
unsigned &D3) {
371 if (RegSpc == SingleSpc) {
376 }
else if (RegSpc == EvenDblSpc) {
382 assert(RegSpc == OddDblSpc &&
"unknown register spacing");
397 assert(TableEntry && TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
399 unsigned NumRegs = TableEntry->NumRegs;
402 TII->get(TableEntry->RealOpc));
407 unsigned D0, D1, D2, D3;
410 if (NumRegs > 1 && TableEntry->copyAllListRegs)
412 if (NumRegs > 2 && TableEntry->copyAllListRegs)
414 if (NumRegs > 3 && TableEntry->copyAllListRegs)
417 if (TableEntry->isUpdating)
424 if (TableEntry->hasWritebackOperand)
430 unsigned SrcOpIdx = 0;
431 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
447 TransferImpOps(MI, MIB, MIB);
462 assert(TableEntry && !TableEntry->IsLoad &&
"NEONLdStTable lookup failed");
464 unsigned NumRegs = TableEntry->NumRegs;
467 TII->get(TableEntry->RealOpc));
469 if (TableEntry->isUpdating)
476 if (TableEntry->hasWritebackOperand)
482 unsigned D0, D1, D2, D3;
485 if (NumRegs > 1 && TableEntry->copyAllListRegs)
487 if (NumRegs > 2 && TableEntry->copyAllListRegs)
489 if (NumRegs > 3 && TableEntry->copyAllListRegs)
496 if (SrcIsKill && !SrcIsUndef)
497 MIB->addRegisterKilled(SrcReg, TRI,
true);
498 else if (!SrcIsUndef)
500 TransferImpOps(MI, MIB, MIB);
515 assert(TableEntry &&
"NEONLdStTable lookup failed");
517 unsigned NumRegs = TableEntry->NumRegs;
518 unsigned RegElts = TableEntry->RegElts;
521 TII->get(TableEntry->RealOpc));
528 assert(RegSpc != OddDblSpc &&
"unexpected register spacing for VLD/VST-lane");
529 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
533 assert(Lane < RegElts &&
"out of range lane for VLD/VST-lane");
535 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
537 bool DstIsDead =
false;
538 if (TableEntry->IsLoad) {
551 if (TableEntry->isUpdating)
558 if (TableEntry->hasWritebackOperand)
563 if (!TableEntry->IsLoad)
569 MIB.addReg(D0, SrcFlags);
571 MIB.addReg(D1, SrcFlags);
573 MIB.addReg(D2, SrcFlags);
575 MIB.addReg(D3, SrcFlags);
588 if (TableEntry->IsLoad)
591 TransferImpOps(MI, MIB, MIB);
600 unsigned Opc,
bool IsExt) {
614 unsigned D0, D1, D2, D3;
615 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
627 TransferImpOps(MI, MIB, MIB);
671 unsigned PredReg = 0;
675 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
680 if (!STI->hasV6T2Ops() &&
681 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
683 assert(!STI->isTargetWindows() &&
"Windows on ARM requires ARMv7+");
691 assert (MO.
isImm() &&
"MOVi32imm w/ non-immediate source operand!");
695 LO16 = LO16.addImm(SOImmValV1);
696 HI16 = HI16.addImm(SOImmValV2);
699 LO16.addImm(Pred).addReg(PredReg).addReg(0);
700 HI16.addImm(Pred).addReg(PredReg).addReg(0);
701 TransferImpOps(MI, LO16, HI16);
706 unsigned LO16Opc = 0;
707 unsigned HI16Opc = 0;
708 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
709 LO16Opc = ARM::t2MOVi16;
710 HI16Opc = ARM::t2MOVTi16;
712 LO16Opc = ARM::MOVi16;
713 HI16Opc = ARM::MOVTi16;
723 unsigned Imm = MO.
getImm();
724 unsigned Lo16 = Imm & 0xffff;
725 unsigned Hi16 = (Imm >> 16) & 0xffff;
726 LO16 = LO16.addImm(Lo16);
727 HI16 = HI16.addImm(Hi16);
748 LO16.addImm(Pred).addReg(PredReg);
749 HI16.addImm(Pred).addReg(PredReg);
751 if (RequiresBundling)
754 TransferImpOps(MI, LO16, HI16);
759 for (
auto I = LiveRegs.
begin();
I != LiveRegs.
end(); ++
I)
768 unsigned LdrexOp,
unsigned StrexOp,
771 bool IsThumb = STI->isThumb();
782 for (
auto I = std::prev(MBB.
end());
I != MBBI; --
I)
783 LiveRegs.stepBackward(*
I);
791 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
792 MF->
insert(++StoreBB->getIterator(), DoneBB);
807 LoadCmpBB->addLiveIn(Addr.
getReg());
808 LoadCmpBB->addLiveIn(Dest.
getReg());
809 LoadCmpBB->addLiveIn(Desired.
getReg());
815 if (LdrexOp == ARM::t2LDREX)
819 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
823 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
828 LoadCmpBB->addSuccessor(DoneBB);
829 LoadCmpBB->addSuccessor(StoreBB);
835 StoreBB->addLiveIn(Addr.
getReg());
836 StoreBB->addLiveIn(New.
getReg());
840 MIB =
BuildMI(StoreBB, DL,
TII->get(StrexOp), StatusReg);
843 if (StrexOp == ARM::t2STREX)
847 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
855 StoreBB->addSuccessor(LoadCmpBB);
856 StoreBB->addSuccessor(DoneBB);
858 DoneBB->splice(DoneBB->end(), &
MBB,
MI, MBB.
end());
859 DoneBB->transferSuccessors(&MBB);
864 NextMBBI = MBB.
end();
865 MI.eraseFromParent();
873 unsigned Flags,
bool IsThumb,
888 bool IsThumb = STI->isThumb();
898 unsigned DestHi = TRI->getSubReg(Dest.
getReg(), ARM::gsub_1);
899 unsigned DesiredLo = TRI->getSubReg(Desired.
getReg(), ARM::gsub_0);
900 unsigned DesiredHi = TRI->getSubReg(Desired.
getReg(), ARM::gsub_1);
904 for (
auto I = std::prev(MBB.
end());
I != MBBI; --
I)
905 LiveRegs.stepBackward(*
I);
913 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
914 MF->
insert(++StoreBB->getIterator(), DoneBB);
921 LoadCmpBB->addLiveIn(Addr.
getReg());
922 LoadCmpBB->addLiveIn(Dest.
getReg());
923 LoadCmpBB->addLiveIn(Desired.
getReg());
926 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
928 MIB =
BuildMI(LoadCmpBB, DL,
TII->get(LDREXD));
933 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
943 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
948 LoadCmpBB->addSuccessor(DoneBB);
949 LoadCmpBB->addSuccessor(StoreBB);
955 StoreBB->addLiveIn(Addr.
getReg());
956 StoreBB->addLiveIn(New.
getReg());
959 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
960 MIB =
BuildMI(StoreBB, DL,
TII->get(STREXD), StatusReg);
965 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
973 StoreBB->addSuccessor(LoadCmpBB);
974 StoreBB->addSuccessor(DoneBB);
976 DoneBB->splice(DoneBB->end(), &
MBB,
MI, MBB.
end());
977 DoneBB->transferSuccessors(&MBB);
982 NextMBBI = MBB.
end();
983 MI.eraseFromParent();
997 case ARM::TCRETURNdi:
998 case ARM::TCRETURNri: {
1000 assert(MBBI->isReturn() &&
1001 "Can only insert epilog into returning blocks");
1002 unsigned RetOpcode = MBBI->getOpcode();
1012 if (RetOpcode == ARM::TCRETURNdi) {
1015 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1030 }
else if (RetOpcode == ARM::TCRETURNri) {
1032 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
1036 auto NewMI = std::prev(MBBI);
1037 for (
unsigned i = 1, e = MBBI->getNumOperands();
i != e; ++
i)
1038 NewMI->addOperand(MBBI->getOperand(
i));
1046 case ARM::VMOVDcc: {
1047 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1059 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1070 case ARM::MOVCCsi: {
1082 case ARM::MOVCCsr: {
1095 case ARM::t2MOVCCi16:
1096 case ARM::MOVCCi16: {
1097 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1108 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1121 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1132 case ARM::t2MOVCClsl:
1133 case ARM::t2MOVCClsr:
1134 case ARM::t2MOVCCasr:
1135 case ARM::t2MOVCCror: {
1138 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri;
break;
1139 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri;
break;
1140 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri;
break;
1141 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri;
break;
1154 case ARM::Int_eh_sjlj_dispatchsetup: {
1163 int32_t NumBytes = AFI->getFramePtrSpillOffset();
1166 "base pointer without frame pointer?");
1168 if (AFI->isThumb2Function()) {
1171 }
else if (AFI->isThumbFunction()) {
1180 if (RI.needsStackRealignment(MF)) {
1183 assert (!AFI->isThumb1OnlyFunction());
1185 assert(MaxAlign <= 256 &&
"The BIC instruction cannot encode "
1186 "immediates larger than 256 with all lower "
1188 unsigned bicOpc = AFI->isThumbFunction() ?
1189 ARM::t2BICri : ARM::BICri;
1201 case ARM::MOVsrl_flag:
1202 case ARM::MOVsra_flag: {
1222 TransferImpOps(MI, MIB, MIB);
1228 const bool Thumb = Opcode == ARM::tTPsoft;
1231 if (STI->genLongCalls()) {
1234 unsigned PCLabelID = AFI->createPICLabelUId();
1237 "__aeabi_read_tp", PCLabelID, 0);
1240 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12),
Reg)
1247 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1253 TII->get(Thumb ? ARM::tBL : ARM::BL));
1260 TransferImpOps(MI, MIB, MIB);
1264 case ARM::tLDRpci_pic:
1265 case ARM::t2LDRpci_pic: {
1266 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1267 ? ARM::tLDRpci : ARM::t2LDRpci;
1272 TII->get(NewLdOpc), DstReg)
1276 TII->get(ARM::tPICADD))
1280 TransferImpOps(MI, MIB1, MIB2);
1285 case ARM::LDRLIT_ga_abs:
1286 case ARM::LDRLIT_ga_pcrel:
1287 case ARM::LDRLIT_ga_pcrel_ldr:
1288 case ARM::tLDRLIT_ga_abs:
1289 case ARM::tLDRLIT_ga_pcrel: {
1295 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1297 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1298 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1299 unsigned PICAddOpc =
1301 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1306 unsigned ARMPCLabelIndex = 0;
1310 unsigned PCAdj = IsARM ? 8 : 4;
1311 ARMPCLabelIndex = AFI->createPICLabelUId();
1319 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1329 .
addImm(ARMPCLabelIndex);
1338 case ARM::MOV_ga_pcrel:
1339 case ARM::MOV_ga_pcrel_ldr:
1340 case ARM::t2MOV_ga_pcrel: {
1342 unsigned LabelId = AFI->createPICLabelUId();
1348 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1349 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1350 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1353 unsigned PICAddOpc = isARM
1354 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1357 TII->get(LO16Opc), DstReg)
1358 .addGlobalAddress(GV, MO1.
getOffset(), TF | LO16TF)
1367 TII->get(PICAddOpc))
1369 .addReg(DstReg).
addImm(LabelId);
1372 if (Opcode == ARM::MOV_ga_pcrel_ldr)
1375 TransferImpOps(MI, MIB1, MIB3);
1380 case ARM::MOVi32imm:
1381 case ARM::MOVCCi32imm:
1382 case ARM::t2MOVi32imm:
1383 case ARM::t2MOVCCi32imm:
1384 ExpandMOV32BitImm(MBB, MBBI);
1387 case ARM::SUBS_PC_LR: {
1395 TransferImpOps(MI, MIB, MIB);
1399 case ARM::VLDMQIA: {
1400 unsigned NewOpc = ARM::VLDMDIA;
1417 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1418 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1424 TransferImpOps(MI, MIB, MIB);
1430 case ARM::VSTMQIA: {
1431 unsigned NewOpc = ARM::VSTMDIA;
1448 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1449 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1451 .
addReg(D1, SrcIsKill ? RegState::Kill : 0);
1456 TransferImpOps(MI, MIB, MIB);
1462 case ARM::VLD2q8Pseudo:
1463 case ARM::VLD2q16Pseudo:
1464 case ARM::VLD2q32Pseudo:
1465 case ARM::VLD2q8PseudoWB_fixed:
1466 case ARM::VLD2q16PseudoWB_fixed:
1467 case ARM::VLD2q32PseudoWB_fixed:
1468 case ARM::VLD2q8PseudoWB_register:
1469 case ARM::VLD2q16PseudoWB_register:
1470 case ARM::VLD2q32PseudoWB_register:
1471 case ARM::VLD3d8Pseudo:
1472 case ARM::VLD3d16Pseudo:
1473 case ARM::VLD3d32Pseudo:
1474 case ARM::VLD1d64TPseudo:
1475 case ARM::VLD1d64TPseudoWB_fixed:
1476 case ARM::VLD3d8Pseudo_UPD:
1477 case ARM::VLD3d16Pseudo_UPD:
1478 case ARM::VLD3d32Pseudo_UPD:
1479 case ARM::VLD3q8Pseudo_UPD:
1480 case ARM::VLD3q16Pseudo_UPD:
1481 case ARM::VLD3q32Pseudo_UPD:
1482 case ARM::VLD3q8oddPseudo:
1483 case ARM::VLD3q16oddPseudo:
1484 case ARM::VLD3q32oddPseudo:
1485 case ARM::VLD3q8oddPseudo_UPD:
1486 case ARM::VLD3q16oddPseudo_UPD:
1487 case ARM::VLD3q32oddPseudo_UPD:
1488 case ARM::VLD4d8Pseudo:
1489 case ARM::VLD4d16Pseudo:
1490 case ARM::VLD4d32Pseudo:
1491 case ARM::VLD1d64QPseudo:
1492 case ARM::VLD1d64QPseudoWB_fixed:
1493 case ARM::VLD4d8Pseudo_UPD:
1494 case ARM::VLD4d16Pseudo_UPD:
1495 case ARM::VLD4d32Pseudo_UPD:
1496 case ARM::VLD4q8Pseudo_UPD:
1497 case ARM::VLD4q16Pseudo_UPD:
1498 case ARM::VLD4q32Pseudo_UPD:
1499 case ARM::VLD4q8oddPseudo:
1500 case ARM::VLD4q16oddPseudo:
1501 case ARM::VLD4q32oddPseudo:
1502 case ARM::VLD4q8oddPseudo_UPD:
1503 case ARM::VLD4q16oddPseudo_UPD:
1504 case ARM::VLD4q32oddPseudo_UPD:
1505 case ARM::VLD3DUPd8Pseudo:
1506 case ARM::VLD3DUPd16Pseudo:
1507 case ARM::VLD3DUPd32Pseudo:
1508 case ARM::VLD3DUPd8Pseudo_UPD:
1509 case ARM::VLD3DUPd16Pseudo_UPD:
1510 case ARM::VLD3DUPd32Pseudo_UPD:
1511 case ARM::VLD4DUPd8Pseudo:
1512 case ARM::VLD4DUPd16Pseudo:
1513 case ARM::VLD4DUPd32Pseudo:
1514 case ARM::VLD4DUPd8Pseudo_UPD:
1515 case ARM::VLD4DUPd16Pseudo_UPD:
1516 case ARM::VLD4DUPd32Pseudo_UPD:
1520 case ARM::VST2q8Pseudo:
1521 case ARM::VST2q16Pseudo:
1522 case ARM::VST2q32Pseudo:
1523 case ARM::VST2q8PseudoWB_fixed:
1524 case ARM::VST2q16PseudoWB_fixed:
1525 case ARM::VST2q32PseudoWB_fixed:
1526 case ARM::VST2q8PseudoWB_register:
1527 case ARM::VST2q16PseudoWB_register:
1528 case ARM::VST2q32PseudoWB_register:
1529 case ARM::VST3d8Pseudo:
1530 case ARM::VST3d16Pseudo:
1531 case ARM::VST3d32Pseudo:
1532 case ARM::VST1d64TPseudo:
1533 case ARM::VST3d8Pseudo_UPD:
1534 case ARM::VST3d16Pseudo_UPD:
1535 case ARM::VST3d32Pseudo_UPD:
1536 case ARM::VST1d64TPseudoWB_fixed:
1537 case ARM::VST1d64TPseudoWB_register:
1538 case ARM::VST3q8Pseudo_UPD:
1539 case ARM::VST3q16Pseudo_UPD:
1540 case ARM::VST3q32Pseudo_UPD:
1541 case ARM::VST3q8oddPseudo:
1542 case ARM::VST3q16oddPseudo:
1543 case ARM::VST3q32oddPseudo:
1544 case ARM::VST3q8oddPseudo_UPD:
1545 case ARM::VST3q16oddPseudo_UPD:
1546 case ARM::VST3q32oddPseudo_UPD:
1547 case ARM::VST4d8Pseudo:
1548 case ARM::VST4d16Pseudo:
1549 case ARM::VST4d32Pseudo:
1550 case ARM::VST1d64QPseudo:
1551 case ARM::VST4d8Pseudo_UPD:
1552 case ARM::VST4d16Pseudo_UPD:
1553 case ARM::VST4d32Pseudo_UPD:
1554 case ARM::VST1d64QPseudoWB_fixed:
1555 case ARM::VST1d64QPseudoWB_register:
1556 case ARM::VST4q8Pseudo_UPD:
1557 case ARM::VST4q16Pseudo_UPD:
1558 case ARM::VST4q32Pseudo_UPD:
1559 case ARM::VST4q8oddPseudo:
1560 case ARM::VST4q16oddPseudo:
1561 case ARM::VST4q32oddPseudo:
1562 case ARM::VST4q8oddPseudo_UPD:
1563 case ARM::VST4q16oddPseudo_UPD:
1564 case ARM::VST4q32oddPseudo_UPD:
1568 case ARM::VLD1LNq8Pseudo:
1569 case ARM::VLD1LNq16Pseudo:
1570 case ARM::VLD1LNq32Pseudo:
1571 case ARM::VLD1LNq8Pseudo_UPD:
1572 case ARM::VLD1LNq16Pseudo_UPD:
1573 case ARM::VLD1LNq32Pseudo_UPD:
1574 case ARM::VLD2LNd8Pseudo:
1575 case ARM::VLD2LNd16Pseudo:
1576 case ARM::VLD2LNd32Pseudo:
1577 case ARM::VLD2LNq16Pseudo:
1578 case ARM::VLD2LNq32Pseudo:
1579 case ARM::VLD2LNd8Pseudo_UPD:
1580 case ARM::VLD2LNd16Pseudo_UPD:
1581 case ARM::VLD2LNd32Pseudo_UPD:
1582 case ARM::VLD2LNq16Pseudo_UPD:
1583 case ARM::VLD2LNq32Pseudo_UPD:
1584 case ARM::VLD3LNd8Pseudo:
1585 case ARM::VLD3LNd16Pseudo:
1586 case ARM::VLD3LNd32Pseudo:
1587 case ARM::VLD3LNq16Pseudo:
1588 case ARM::VLD3LNq32Pseudo:
1589 case ARM::VLD3LNd8Pseudo_UPD:
1590 case ARM::VLD3LNd16Pseudo_UPD:
1591 case ARM::VLD3LNd32Pseudo_UPD:
1592 case ARM::VLD3LNq16Pseudo_UPD:
1593 case ARM::VLD3LNq32Pseudo_UPD:
1594 case ARM::VLD4LNd8Pseudo:
1595 case ARM::VLD4LNd16Pseudo:
1596 case ARM::VLD4LNd32Pseudo:
1597 case ARM::VLD4LNq16Pseudo:
1598 case ARM::VLD4LNq32Pseudo:
1599 case ARM::VLD4LNd8Pseudo_UPD:
1600 case ARM::VLD4LNd16Pseudo_UPD:
1601 case ARM::VLD4LNd32Pseudo_UPD:
1602 case ARM::VLD4LNq16Pseudo_UPD:
1603 case ARM::VLD4LNq32Pseudo_UPD:
1604 case ARM::VST1LNq8Pseudo:
1605 case ARM::VST1LNq16Pseudo:
1606 case ARM::VST1LNq32Pseudo:
1607 case ARM::VST1LNq8Pseudo_UPD:
1608 case ARM::VST1LNq16Pseudo_UPD:
1609 case ARM::VST1LNq32Pseudo_UPD:
1610 case ARM::VST2LNd8Pseudo:
1611 case ARM::VST2LNd16Pseudo:
1612 case ARM::VST2LNd32Pseudo:
1613 case ARM::VST2LNq16Pseudo:
1614 case ARM::VST2LNq32Pseudo:
1615 case ARM::VST2LNd8Pseudo_UPD:
1616 case ARM::VST2LNd16Pseudo_UPD:
1617 case ARM::VST2LNd32Pseudo_UPD:
1618 case ARM::VST2LNq16Pseudo_UPD:
1619 case ARM::VST2LNq32Pseudo_UPD:
1620 case ARM::VST3LNd8Pseudo:
1621 case ARM::VST3LNd16Pseudo:
1622 case ARM::VST3LNd32Pseudo:
1623 case ARM::VST3LNq16Pseudo:
1624 case ARM::VST3LNq32Pseudo:
1625 case ARM::VST3LNd8Pseudo_UPD:
1626 case ARM::VST3LNd16Pseudo_UPD:
1627 case ARM::VST3LNd32Pseudo_UPD:
1628 case ARM::VST3LNq16Pseudo_UPD:
1629 case ARM::VST3LNq32Pseudo_UPD:
1630 case ARM::VST4LNd8Pseudo:
1631 case ARM::VST4LNd16Pseudo:
1632 case ARM::VST4LNd32Pseudo:
1633 case ARM::VST4LNq16Pseudo:
1634 case ARM::VST4LNq32Pseudo:
1635 case ARM::VST4LNd8Pseudo_UPD:
1636 case ARM::VST4LNd16Pseudo_UPD:
1637 case ARM::VST4LNd32Pseudo_UPD:
1638 case ARM::VST4LNq16Pseudo_UPD:
1639 case ARM::VST4LNq32Pseudo_UPD:
1643 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3,
false);
return true;
1644 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4,
false);
return true;
1645 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3,
true);
return true;
1646 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4,
true);
return true;
1648 case ARM::CMP_SWAP_8:
1650 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1651 ARM::tUXTB, NextMBBI);
1653 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1655 case ARM::CMP_SWAP_16:
1657 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1658 ARM::tUXTH, NextMBBI);
1660 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1662 case ARM::CMP_SWAP_32:
1664 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1667 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1669 case ARM::CMP_SWAP_64:
1670 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1675 bool Modified =
false;
1680 Modified |= ExpandMI(MBB, MBBI, NMBBI);
1689 TII = STI->getInstrInfo();
1693 bool Modified =
false;
1696 Modified |= ExpandMBB(*MFI);
1698 MF.
verify(
this,
"After expanding ARM pseudo instructions.");
1705 return new ARMExpandPseudo();
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const_iterator end(StringRef path)
Get end iterator over path.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
const GlobalValue * getGlobal() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
static ARMConstantPoolSymbol * Create(LLVMContext &C, StringRef s, unsigned ID, unsigned char PCAdj)
static cl::opt< bool > VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
static unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
static const NEONLdStTableEntry * LookupNEONLdSt(unsigned Opcode)
LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instructi...
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
Address of indexed Jump Table for switch.
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const_iterator begin(StringRef path)
Get begin iterator over path.
MachineBasicBlock reference.
const char * getSymbolName() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Mask of live-out registers.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Mask of preserved registers.
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static const NEONLdStTableEntry NEONLdStTable[]
struct fuzzer::@269 Flags
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Target-dependent index+offset operand.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setImplicit(bool Val=true)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
Immediate >64bit operand.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
unsigned getUndefRegState(bool B)
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
unsigned getKillRegState(bool B)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
unsigned getDeadRegState(bool B)
mmo_iterator memoperands_end() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Address of a global value.
unsigned getTargetFlags() const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder & UseMI
static unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Address of a basic block.
#define LLVM_ATTRIBUTE_UNUSED
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
int64_t getOffset() const
Return the offset from the symbol in this operand.
self_iterator getIterator()
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
unsigned getSubReg() const
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Abstract base class for all machine specific constantpool value subclasses.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
virtual const TargetFrameLowering * getFrameLowering() const
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
Iterator for intrusive lists based on ilist_node.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Generic predicate for ISel.
MachineOperand class - Representation of each machine instruction operand.
static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI)
ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register)...
MCSymbol reference (for debug/eh info)
bool hasBasePointer(const MachineFunction &MF) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
A set of live physical registers with functions to track liveness when walking backward/forward throu...
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3)
GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified regis...
static void addPostLoopLiveIns(MachineBasicBlock *MBB, LivePhysRegs &LiveRegs)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
Abstract Stack Frame Index.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
bool operator<(int64_t V1, const APSInt &V2)
virtual const TargetInstrInfo * getInstrInfo() const
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
Floating-point immediate operand.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
static bool IsAnAddressOperand(const MachineOperand &MO)
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static const unsigned FramePtr
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
StringRef - Represent a constant reference to a string, i.e.
Address of indexed Constant in Constant Pool.
const_iterator end() const
static unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
const_iterator begin() const
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Properties which a MachineFunction may have at a given point in time.
Metadata reference (for debug info)
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.