LLVM  4.0.0
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AMDGPUBaseInfo.cpp File Reference
#include "AMDGPUBaseInfo.h"
#include "AMDGPU.h"
#include "SIDefines.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/SubtargetFeature.h"
#include "AMDGPUGenSubtargetInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"
#include "AMDGPUGenInstrInfo.inc"
Include dependency graph for AMDGPUBaseInfo.cpp:

Go to the source code of this file.

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 
 llvm::AMDGPU
 

Macros

#define GET_SUBTARGETINFO_ENUM
 
#define GET_REGINFO_ENUM
 
#define GET_INSTRINFO_NAMED_OPS
 
#define GET_INSTRINFO_ENUM
 

Functions

IsaVersion llvm::AMDGPU::getIsaVersion (const FeatureBitset &Features)
 
void llvm::AMDGPU::initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const FeatureBitset &Features)
 
MCSection * llvm::AMDGPU::getHSATextSection (MCContext &Ctx)
 
MCSection * llvm::AMDGPU::getHSADataGlobalAgentSection (MCContext &Ctx)
 
MCSection * llvm::AMDGPU::getHSADataGlobalProgramSection (MCContext &Ctx)
 
MCSection * llvm::AMDGPU::getHSARodataReadonlyAgentSection (MCContext &Ctx)
 
bool llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)
 
int llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned llvm::AMDGPU::getWaitcntBitMask (IsaVersion Version)
 
unsigned llvm::AMDGPU::getVmcntBitMask (IsaVersion Version)
 
unsigned llvm::AMDGPU::getExpcntBitMask (IsaVersion Version)
 
unsigned llvm::AMDGPU::getLgkmcntBitMask (IsaVersion Version)
 
unsigned llvm::AMDGPU::decodeVmcnt (IsaVersion Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeExpcnt (IsaVersion Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeLgkmcnt (IsaVersion Version, unsigned Waitcnt)
 
void llvm::AMDGPU::decodeWaitcnt (IsaVersion Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
unsigned llvm::AMDGPU::encodeVmcnt (IsaVersion Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned llvm::AMDGPU::encodeExpcnt (IsaVersion Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned llvm::AMDGPU::encodeLgkmcnt (IsaVersion Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned llvm::AMDGPU::encodeWaitcnt (IsaVersion Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned llvm::AMDGPU::getInitialPSInputAddr (const Function &F)
 
bool llvm::AMDGPU::isShader (CallingConv::ID cc)
 
bool llvm::AMDGPU::isCompute (CallingConv::ID cc)
 
bool llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)
 
unsigned llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
bool llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned llvm::AMDGPU::getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 

Macro Definition Documentation

#define GET_INSTRINFO_ENUM

Definition at line 31 of file AMDGPUBaseInfo.cpp.

#define GET_INSTRINFO_NAMED_OPS

Definition at line 30 of file AMDGPUBaseInfo.cpp.

#define GET_REGINFO_ENUM

Definition at line 26 of file AMDGPUBaseInfo.cpp.

#define GET_SUBTARGETINFO_ENUM

Definition at line 22 of file AMDGPUBaseInfo.cpp.