LLVM  4.0.0
MipsSEInstrInfo.cpp
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1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEInstrInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
25 
26 using namespace llvm;
27 
29  : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
30  RI() {}
31 
33  return RI;
34 }
35 
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot. If
39 /// not, return 0. This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
42  int &FrameIndex) const {
43  unsigned Opc = MI.getOpcode();
44 
45  if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46  (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
47  if ((MI.getOperand(1).isFI()) && // is a stack slot
48  (MI.getOperand(2).isImm()) && // the imm is zero
49  (isZeroImm(MI.getOperand(2)))) {
50  FrameIndex = MI.getOperand(1).getIndex();
51  return MI.getOperand(0).getReg();
52  }
53  }
54 
55  return 0;
56 }
57 
58 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 /// store to a stack slot, return the virtual or physical register number of
60 /// the source reg along with the FrameIndex of the loaded stack slot. If
61 /// not, return 0. This predicate must return 0 if the instruction has
62 /// any side effects other than storing to the stack slot.
64  int &FrameIndex) const {
65  unsigned Opc = MI.getOpcode();
66 
67  if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68  (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
69  if ((MI.getOperand(1).isFI()) && // is a stack slot
70  (MI.getOperand(2).isImm()) && // the imm is zero
71  (isZeroImm(MI.getOperand(2)))) {
72  FrameIndex = MI.getOperand(1).getIndex();
73  return MI.getOperand(0).getReg();
74  }
75  }
76  return 0;
77 }
78 
81  const DebugLoc &DL, unsigned DestReg,
82  unsigned SrcReg, bool KillSrc) const {
83  unsigned Opc = 0, ZeroReg = 0;
84  bool isMicroMips = Subtarget.inMicroMipsMode();
85 
86  if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
87  if (Mips::GPR32RegClass.contains(SrcReg)) {
88  if (isMicroMips)
89  Opc = Mips::MOVE16_MM;
90  else
91  Opc = Mips::OR, ZeroReg = Mips::ZERO;
92  } else if (Mips::CCRRegClass.contains(SrcReg))
93  Opc = Mips::CFC1;
94  else if (Mips::FGR32RegClass.contains(SrcReg))
95  Opc = Mips::MFC1;
96  else if (Mips::HI32RegClass.contains(SrcReg)) {
97  Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
98  SrcReg = 0;
99  } else if (Mips::LO32RegClass.contains(SrcReg)) {
100  Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
101  SrcReg = 0;
102  } else if (Mips::HI32DSPRegClass.contains(SrcReg))
103  Opc = Mips::MFHI_DSP;
104  else if (Mips::LO32DSPRegClass.contains(SrcReg))
105  Opc = Mips::MFLO_DSP;
106  else if (Mips::DSPCCRegClass.contains(SrcReg)) {
107  BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
108  .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
109  return;
110  }
111  else if (Mips::MSACtrlRegClass.contains(SrcReg))
112  Opc = Mips::CFCMSA;
113  }
114  else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
115  if (Mips::CCRRegClass.contains(DestReg))
116  Opc = Mips::CTC1;
117  else if (Mips::FGR32RegClass.contains(DestReg))
118  Opc = Mips::MTC1;
119  else if (Mips::HI32RegClass.contains(DestReg))
120  Opc = Mips::MTHI, DestReg = 0;
121  else if (Mips::LO32RegClass.contains(DestReg))
122  Opc = Mips::MTLO, DestReg = 0;
123  else if (Mips::HI32DSPRegClass.contains(DestReg))
124  Opc = Mips::MTHI_DSP;
125  else if (Mips::LO32DSPRegClass.contains(DestReg))
126  Opc = Mips::MTLO_DSP;
127  else if (Mips::DSPCCRegClass.contains(DestReg)) {
128  BuildMI(MBB, I, DL, get(Mips::WRDSP))
129  .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
130  .addReg(DestReg, RegState::ImplicitDefine);
131  return;
132  } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
133  BuildMI(MBB, I, DL, get(Mips::CTCMSA))
134  .addReg(DestReg)
135  .addReg(SrcReg, getKillRegState(KillSrc));
136  return;
137  }
138  }
139  else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140  Opc = Mips::FMOV_S;
141  else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142  Opc = Mips::FMOV_D32;
143  else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144  Opc = Mips::FMOV_D64;
145  else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146  if (Mips::GPR64RegClass.contains(SrcReg))
147  Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
148  else if (Mips::HI64RegClass.contains(SrcReg))
149  Opc = Mips::MFHI64, SrcReg = 0;
150  else if (Mips::LO64RegClass.contains(SrcReg))
151  Opc = Mips::MFLO64, SrcReg = 0;
152  else if (Mips::FGR64RegClass.contains(SrcReg))
153  Opc = Mips::DMFC1;
154  }
155  else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156  if (Mips::HI64RegClass.contains(DestReg))
157  Opc = Mips::MTHI64, DestReg = 0;
158  else if (Mips::LO64RegClass.contains(DestReg))
159  Opc = Mips::MTLO64, DestReg = 0;
160  else if (Mips::FGR64RegClass.contains(DestReg))
161  Opc = Mips::DMTC1;
162  }
163  else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
164  if (Mips::MSA128BRegClass.contains(SrcReg))
165  Opc = Mips::MOVE_V;
166  }
167 
168  assert(Opc && "Cannot copy registers");
169 
170  MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
171 
172  if (DestReg)
173  MIB.addReg(DestReg, RegState::Define);
174 
175  if (SrcReg)
176  MIB.addReg(SrcReg, getKillRegState(KillSrc));
177 
178  if (ZeroReg)
179  MIB.addReg(ZeroReg);
180 }
181 
184  unsigned SrcReg, bool isKill, int FI,
185  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
186  int64_t Offset) const {
187  DebugLoc DL;
189 
190  unsigned Opc = 0;
191 
192  if (Mips::GPR32RegClass.hasSubClassEq(RC))
193  Opc = Mips::SW;
194  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
195  Opc = Mips::SD;
196  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
197  Opc = Mips::STORE_ACC64;
198  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
199  Opc = Mips::STORE_ACC64DSP;
200  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
201  Opc = Mips::STORE_ACC128;
202  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
203  Opc = Mips::STORE_CCOND_DSP;
204  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
205  Opc = Mips::SWC1;
206  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
207  Opc = Mips::SDC1;
208  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
209  Opc = Mips::SDC164;
210  else if (RC->hasType(MVT::v16i8))
211  Opc = Mips::ST_B;
212  else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
213  Opc = Mips::ST_H;
214  else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
215  Opc = Mips::ST_W;
216  else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
217  Opc = Mips::ST_D;
218  else if (Mips::LO32RegClass.hasSubClassEq(RC))
219  Opc = Mips::SW;
220  else if (Mips::LO64RegClass.hasSubClassEq(RC))
221  Opc = Mips::SD;
222  else if (Mips::HI32RegClass.hasSubClassEq(RC))
223  Opc = Mips::SW;
224  else if (Mips::HI64RegClass.hasSubClassEq(RC))
225  Opc = Mips::SD;
226 
227  // Hi, Lo are normally caller save but they are callee save
228  // for interrupt handling.
229  const Function *Func = MBB.getParent()->getFunction();
230  if (Func->hasFnAttribute("interrupt")) {
231  if (Mips::HI32RegClass.hasSubClassEq(RC)) {
232  BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
233  SrcReg = Mips::K0;
234  } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
235  BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
236  SrcReg = Mips::K0_64;
237  } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
238  BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
239  SrcReg = Mips::K0;
240  } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
241  BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
242  SrcReg = Mips::K0_64;
243  }
244  }
245 
246  assert(Opc && "Register class not handled!");
247  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
248  .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
249 }
250 
253  unsigned DestReg, int FI, const TargetRegisterClass *RC,
254  const TargetRegisterInfo *TRI, int64_t Offset) const {
255  DebugLoc DL;
256  if (I != MBB.end()) DL = I->getDebugLoc();
258  unsigned Opc = 0;
259 
260  const Function *Func = MBB.getParent()->getFunction();
261  bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") &&
262  (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
263  DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
264 
265  if (Mips::GPR32RegClass.hasSubClassEq(RC))
266  Opc = Mips::LW;
267  else if (Mips::GPR64RegClass.hasSubClassEq(RC))
268  Opc = Mips::LD;
269  else if (Mips::ACC64RegClass.hasSubClassEq(RC))
270  Opc = Mips::LOAD_ACC64;
271  else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
272  Opc = Mips::LOAD_ACC64DSP;
273  else if (Mips::ACC128RegClass.hasSubClassEq(RC))
274  Opc = Mips::LOAD_ACC128;
275  else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
276  Opc = Mips::LOAD_CCOND_DSP;
277  else if (Mips::FGR32RegClass.hasSubClassEq(RC))
278  Opc = Mips::LWC1;
279  else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
280  Opc = Mips::LDC1;
281  else if (Mips::FGR64RegClass.hasSubClassEq(RC))
282  Opc = Mips::LDC164;
283  else if (RC->hasType(MVT::v16i8))
284  Opc = Mips::LD_B;
285  else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
286  Opc = Mips::LD_H;
287  else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
288  Opc = Mips::LD_W;
289  else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
290  Opc = Mips::LD_D;
291  else if (Mips::HI32RegClass.hasSubClassEq(RC))
292  Opc = Mips::LW;
293  else if (Mips::HI64RegClass.hasSubClassEq(RC))
294  Opc = Mips::LD;
295  else if (Mips::LO32RegClass.hasSubClassEq(RC))
296  Opc = Mips::LW;
297  else if (Mips::LO64RegClass.hasSubClassEq(RC))
298  Opc = Mips::LD;
299 
300  assert(Opc && "Register class not handled!");
301 
302  if (!ReqIndirectLoad)
303  BuildMI(MBB, I, DL, get(Opc), DestReg)
304  .addFrameIndex(FI)
305  .addImm(Offset)
306  .addMemOperand(MMO);
307  else {
308  // Load HI/LO through K0. Notably the DestReg is encoded into the
309  // instruction itself.
310  unsigned Reg = Mips::K0;
311  unsigned LdOp = Mips::MTLO;
312  if (DestReg == Mips::HI0)
313  LdOp = Mips::MTHI;
314 
315  if (Subtarget.getABI().ArePtrs64bit()) {
316  Reg = Mips::K0_64;
317  if (DestReg == Mips::HI0_64)
318  LdOp = Mips::MTHI64;
319  else
320  LdOp = Mips::MTLO64;
321  }
322 
323  BuildMI(MBB, I, DL, get(Opc), Reg)
324  .addFrameIndex(FI)
325  .addImm(Offset)
326  .addMemOperand(MMO);
327  BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
328  }
329 }
330 
333  bool isMicroMips = Subtarget.inMicroMipsMode();
334  unsigned Opc;
335 
336  switch (MI.getDesc().getOpcode()) {
337  default:
338  return false;
339  case Mips::RetRA:
340  expandRetRA(MBB, MI);
341  break;
342  case Mips::ERet:
343  expandERet(MBB, MI);
344  break;
345  case Mips::PseudoMFHI:
346  Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
347  expandPseudoMFHiLo(MBB, MI, Opc);
348  break;
349  case Mips::PseudoMFLO:
350  Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
351  expandPseudoMFHiLo(MBB, MI, Opc);
352  break;
353  case Mips::PseudoMFHI64:
354  expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
355  break;
356  case Mips::PseudoMFLO64:
357  expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
358  break;
359  case Mips::PseudoMTLOHI:
360  expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
361  break;
362  case Mips::PseudoMTLOHI64:
363  expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
364  break;
365  case Mips::PseudoMTLOHI_DSP:
366  expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
367  break;
368  case Mips::PseudoCVT_S_W:
369  expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
370  break;
371  case Mips::PseudoCVT_D32_W:
372  expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
373  break;
374  case Mips::PseudoCVT_S_L:
375  expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
376  break;
377  case Mips::PseudoCVT_D64_W:
378  expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
379  break;
380  case Mips::PseudoCVT_D64_L:
381  expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
382  break;
383  case Mips::BuildPairF64:
384  expandBuildPairF64(MBB, MI, false);
385  break;
386  case Mips::BuildPairF64_64:
387  expandBuildPairF64(MBB, MI, true);
388  break;
390  expandExtractElementF64(MBB, MI, false);
391  break;
392  case Mips::ExtractElementF64_64:
393  expandExtractElementF64(MBB, MI, true);
394  break;
395  case Mips::MIPSeh_return32:
396  case Mips::MIPSeh_return64:
397  expandEhReturn(MBB, MI);
398  break;
399  }
400 
401  MBB.erase(MI);
402  return true;
403 }
404 
405 /// getOppositeBranchOpc - Return the inverse of the specified
406 /// opcode, e.g. turning BEQ to BNE.
407 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
408  switch (Opc) {
409  default: llvm_unreachable("Illegal opcode!");
410  case Mips::BEQ: return Mips::BNE;
411  case Mips::BEQ_MM: return Mips::BNE_MM;
412  case Mips::BNE: return Mips::BEQ;
413  case Mips::BNE_MM: return Mips::BEQ_MM;
414  case Mips::BGTZ: return Mips::BLEZ;
415  case Mips::BGEZ: return Mips::BLTZ;
416  case Mips::BLTZ: return Mips::BGEZ;
417  case Mips::BLEZ: return Mips::BGTZ;
418  case Mips::BEQ64: return Mips::BNE64;
419  case Mips::BNE64: return Mips::BEQ64;
420  case Mips::BGTZ64: return Mips::BLEZ64;
421  case Mips::BGEZ64: return Mips::BLTZ64;
422  case Mips::BLTZ64: return Mips::BGEZ64;
423  case Mips::BLEZ64: return Mips::BGTZ64;
424  case Mips::BC1T: return Mips::BC1F;
425  case Mips::BC1F: return Mips::BC1T;
426  case Mips::BEQZC_MM: return Mips::BNEZC_MM;
427  case Mips::BNEZC_MM: return Mips::BEQZC_MM;
428  case Mips::BEQZC: return Mips::BNEZC;
429  case Mips::BNEZC: return Mips::BEQZC;
430  case Mips::BEQC: return Mips::BNEC;
431  case Mips::BNEC: return Mips::BEQC;
432  case Mips::BGTZC: return Mips::BLEZC;
433  case Mips::BGEZC: return Mips::BLTZC;
434  case Mips::BLTZC: return Mips::BGEZC;
435  case Mips::BLEZC: return Mips::BGTZC;
436  case Mips::BEQZC64: return Mips::BNEZC64;
437  case Mips::BNEZC64: return Mips::BEQZC64;
438  case Mips::BEQC64: return Mips::BNEC64;
439  case Mips::BNEC64: return Mips::BEQC64;
440  case Mips::BGEC64: return Mips::BLTC64;
441  case Mips::BGEUC64: return Mips::BLTUC64;
442  case Mips::BLTC64: return Mips::BGEC64;
443  case Mips::BLTUC64: return Mips::BGEUC64;
444  case Mips::BGTZC64: return Mips::BLEZC64;
445  case Mips::BGEZC64: return Mips::BLTZC64;
446  case Mips::BLTZC64: return Mips::BGEZC64;
447  case Mips::BLEZC64: return Mips::BGTZC64;
448  }
449 }
450 
451 /// Adjust SP by Amount bytes.
452 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
455  MipsABIInfo ABI = Subtarget.getABI();
456  DebugLoc DL;
457  unsigned ADDiu = ABI.GetPtrAddiuOp();
458 
459  if (Amount == 0)
460  return;
461 
462  if (isInt<16>(Amount)) {
463  // addi sp, sp, amount
464  BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
465  } else {
466  // For numbers which are not 16bit integers we synthesize Amount inline
467  // then add or subtract it from sp.
468  unsigned Opc = ABI.GetPtrAdduOp();
469  if (Amount < 0) {
470  Opc = ABI.GetPtrSubuOp();
471  Amount = -Amount;
472  }
473  unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
474  BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
475  }
476 }
477 
478 /// This function generates the sequence of instructions needed to get the
479 /// result of adding register REG and immediate IMM.
482  const DebugLoc &DL,
483  unsigned *NewImm) const {
484  MipsAnalyzeImmediate AnalyzeImm;
485  const MipsSubtarget &STI = Subtarget;
486  MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
487  unsigned Size = STI.isABI_N64() ? 64 : 32;
488  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
489  unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
490  const TargetRegisterClass *RC = STI.isABI_N64() ?
491  &Mips::GPR64RegClass : &Mips::GPR32RegClass;
492  bool LastInstrIsADDiu = NewImm;
493 
494  const MipsAnalyzeImmediate::InstSeq &Seq =
495  AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
497 
498  assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
499 
500  // The first instruction can be a LUi, which is different from other
501  // instructions (ADDiu, ORI and SLL) in that it does not have a register
502  // operand.
503  unsigned Reg = RegInfo.createVirtualRegister(RC);
504 
505  if (Inst->Opc == LUi)
506  BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
507  else
508  BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
509  .addImm(SignExtend64<16>(Inst->ImmOpnd));
510 
511  // Build the remaining instructions in Seq.
512  for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
513  BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
514  .addImm(SignExtend64<16>(Inst->ImmOpnd));
515 
516  if (LastInstrIsADDiu)
517  *NewImm = Inst->ImmOpnd;
518 
519  return Reg;
520 }
521 
522 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
523  return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
524  Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
525  Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
526  Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
527  Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
528  Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
529  Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
530  Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
531  Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
532  Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
533  Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 ||
534  Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
535  Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
536  Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
537  Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
538  Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
539 }
540 
541 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
543  if (Subtarget.isGP64bit())
544  BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
545  .addReg(Mips::RA_64);
546  else
547  BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA);
548 }
549 
550 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
551  MachineBasicBlock::iterator I) const {
552  BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
553 }
554 
555 std::pair<bool, bool>
556 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
557  const MachineFunction &MF) const {
558  const MCInstrDesc &Desc = get(Opc);
559  assert(Desc.NumOperands == 2 && "Unary instruction expected.");
560  const MipsRegisterInfo *RI = &getRegisterInfo();
561  unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
562  unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
563 
564  return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
565 }
566 
567 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
569  unsigned NewOpc) const {
570  BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
571 }
572 
573 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
575  unsigned LoOpc,
576  unsigned HiOpc,
577  bool HasExplicitDef) const {
578  // Expand
579  // lo_hi pseudomtlohi $gpr0, $gpr1
580  // to these two instructions:
581  // mtlo $gpr0
582  // mthi $gpr1
583 
584  DebugLoc DL = I->getDebugLoc();
585  const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
586  MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
587  MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
588 
589  // Add lo/hi registers if the mtlo/hi instructions created have explicit
590  // def registers.
591  if (HasExplicitDef) {
592  unsigned DstReg = I->getOperand(0).getReg();
593  unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
594  unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
595  LoInst.addReg(DstLo, RegState::Define);
596  HiInst.addReg(DstHi, RegState::Define);
597  }
598 
599  LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
600  HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
601 }
602 
603 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
605  unsigned CvtOpc, unsigned MovOpc,
606  bool IsI64) const {
607  const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
608  const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
609  unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
610  unsigned KillSrc = getKillRegState(Src.isKill());
611  DebugLoc DL = I->getDebugLoc();
612  bool DstIsLarger, SrcIsLarger;
613 
614  std::tie(DstIsLarger, SrcIsLarger) =
615  compareOpndSize(CvtOpc, *MBB.getParent());
616 
617  if (DstIsLarger)
618  TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
619 
620  if (SrcIsLarger)
621  DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
622 
623  BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
624  BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
625 }
626 
627 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
629  bool FP64) const {
630  unsigned DstReg = I->getOperand(0).getReg();
631  unsigned SrcReg = I->getOperand(1).getReg();
632  unsigned N = I->getOperand(2).getImm();
633  DebugLoc dl = I->getDebugLoc();
634 
635  assert(N < 2 && "Invalid immediate");
636  unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
637  unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
638 
639  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
640  // in MipsSEFrameLowering.cpp.
642 
643  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
644  // in MipsSEFrameLowering.cpp.
646 
647  if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
648  // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
649  // claim to read the whole 64-bits as part of a white lie used to
650  // temporarily work around a widespread bug in the -mfp64 support.
651  // The problem is that none of the 32-bit fpu ops mention the fact
652  // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
653  // requires a major overhaul of the FPU implementation which can't
654  // be done right now due to time constraints.
655  // MFHC1 is one of two instructions that are affected since they are
656  // the only instructions that don't read the lower 32-bits.
657  // We therefore pretend that it reads the bottom 32-bits to
658  // artificially create a dependency and prevent the scheduler
659  // changing the behaviour of the code.
660  BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
661  .addReg(SrcReg);
662  } else
663  BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
664 }
665 
666 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
668  bool FP64) const {
669  unsigned DstReg = I->getOperand(0).getReg();
670  unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
671  const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
672  DebugLoc dl = I->getDebugLoc();
673  const TargetRegisterInfo &TRI = getRegisterInfo();
674 
675  // When mthc1 is available, use:
676  // mtc1 Lo, $fp
677  // mthc1 Hi, $fp
678  //
679  // Otherwise, for O32 FPXX ABI:
680  // spill + reload via ldc1
681  // This case is handled by the frame lowering code.
682  //
683  // Otherwise, for FP32:
684  // mtc1 Lo, $fp
685  // mtc1 Hi, $fp + 1
686  //
687  // The case where dmtc1 is available doesn't need to be handled here
688  // because it never creates a BuildPairF64 node.
689 
690  // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
691  // in MipsSEFrameLowering.cpp.
693 
694  // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
695  // in MipsSEFrameLowering.cpp.
697 
698  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
699  .addReg(LoReg);
700 
701  if (Subtarget.hasMTHC1()) {
702  // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
703  // around a widespread bug in the -mfp64 support.
704  // The problem is that none of the 32-bit fpu ops mention the fact
705  // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
706  // requires a major overhaul of the FPU implementation which can't
707  // be done right now due to time constraints.
708  // MTHC1 is one of two instructions that are affected since they are
709  // the only instructions that don't read the lower 32-bits.
710  // We therefore pretend that it reads the bottom 32-bits to
711  // artificially create a dependency and prevent the scheduler
712  // changing the behaviour of the code.
713  BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
714  .addReg(DstReg)
715  .addReg(HiReg);
716  } else if (Subtarget.isABI_FPXX())
717  llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
718  else
719  BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
720  .addReg(HiReg);
721 }
722 
723 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
724  MachineBasicBlock::iterator I) const {
725  // This pseudo instruction is generated as part of the lowering of
726  // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
727  // indirect jump to TargetReg
728  MipsABIInfo ABI = Subtarget.getABI();
729  unsigned ADDU = ABI.GetPtrAdduOp();
730  unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
731  unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
732  unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
733  unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
734  unsigned OffsetReg = I->getOperand(0).getReg();
735  unsigned TargetReg = I->getOperand(1).getReg();
736 
737  // addu $ra, $v0, $zero
738  // addu $sp, $sp, $v1
739  // jr $ra (via RetRA)
740  const TargetMachine &TM = MBB.getParent()->getTarget();
741  if (TM.isPositionIndependent())
742  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
743  .addReg(TargetReg)
744  .addReg(ZERO);
745  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
746  .addReg(TargetReg)
747  .addReg(ZERO);
748  BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
749  expandRetRA(MBB, I);
750 }
751 
753  return new MipsSEInstrInfo(STI);
754 }
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
bool isZeroImm(const MachineOperand &op) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool ArePtrs64bit() const
Definition: MipsABIInfo.h:75
const MipsABIInfo & getABI() const
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
MipsSEInstrInfo(const MipsSubtarget &STI)
return AArch64::GPR64RegClass contains(Reg)
A description of a memory reference used in the backend.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned SubReg
Reg
All possible values of the reg field in the ModR/M byte.
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:35
static int getRegClass(RegisterKind Is, unsigned RegWidth)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
bool isKill() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineBasicBlock * MBB
const InstSeq & Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu)
Analyze - Get an instruction sequence to load immediate Imm.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
unsigned short NumOperands
Definition: MCInstrDesc.h:166
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool useOddSPReg() const
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
bool hasMTHC1() const
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
bool isFP64bit() const
uint32_t Offset
bool isPositionIndependent() const
bool inMicroMipsMode() const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:203
The memory access writes data.
unsigned GetPtrSubuOp() const
Definition: MipsABIInfo.cpp:97
bool isABI_N64() const
MachineOperand class - Representation of each machine instruction operand.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isGP64bit() const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
Representation of each machine instruction.
Definition: MachineInstr.h:52
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasMips32r2() const
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
unsigned GetPtrAdduOp() const
Definition: MipsABIInfo.cpp:89
bool isABI_FPXX() const
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
unsigned GetPtrAddiuOp() const
Definition: MipsABIInfo.cpp:93
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.