LLVM  4.0.0
llvm::AArch64Subtarget Member List

This is the complete list of members for llvm::AArch64Subtarget, including all inherited members.

AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)llvm::AArch64Subtarget
ARMProcFamilyllvm::AArch64Subtargetprotected
ARMProcFamilyEnum enum namellvm::AArch64Subtarget
BalanceFPOpsllvm::AArch64Subtargetprotected
balanceFPOps() const llvm::AArch64Subtargetinline
CacheLineSizellvm::AArch64Subtargetprotected
ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const llvm::AArch64Subtarget
CortexA35 enum valuellvm::AArch64Subtarget
CortexA53 enum valuellvm::AArch64Subtarget
CortexA57 enum valuellvm::AArch64Subtarget
CortexA72 enum valuellvm::AArch64Subtarget
CortexA73 enum valuellvm::AArch64Subtarget
CustomAsCheapAsMovellvm::AArch64Subtargetprotected
Cyclone enum valuellvm::AArch64Subtarget
DisableLatencySchedHeuristicllvm::AArch64Subtargetprotected
enableEarlyIfConversion() const overridellvm::AArch64Subtarget
enableMachineScheduler() const overridellvm::AArch64Subtargetinline
enablePostRAScheduler() const overridellvm::AArch64Subtargetinline
ExynosM1 enum valuellvm::AArch64Subtarget
Falkor enum valuellvm::AArch64Subtarget
FrameLoweringllvm::AArch64Subtargetprotected
getBZeroEntry() const llvm::AArch64Subtarget
getCacheLineSize() const llvm::AArch64Subtargetinline
getCallLowering() const overridellvm::AArch64Subtarget
getCustomPBQPConstraints() const overridellvm::AArch64Subtarget
getFrameLowering() const overridellvm::AArch64Subtargetinline
getInstrInfo() const overridellvm::AArch64Subtargetinline
getInstructionSelector() const overridellvm::AArch64Subtarget
getLegalizerInfo() const overridellvm::AArch64Subtarget
getMaximumJumpTableSize() const llvm::AArch64Subtargetinline
getMaxInlineSizeThreshold() const llvm::AArch64Subtargetinline
getMaxInterleaveFactor() const llvm::AArch64Subtargetinline
getMaxPrefetchIterationsAhead() const llvm::AArch64Subtargetinline
getMinPrefetchStride() const llvm::AArch64Subtargetinline
getPrefetchDistance() const llvm::AArch64Subtargetinline
getPrefFunctionAlignment() const llvm::AArch64Subtargetinline
getPrefLoopAlignment() const llvm::AArch64Subtargetinline
getProcFamily() const llvm::AArch64Subtargetinline
getRegBankInfo() const overridellvm::AArch64Subtarget
getRegisterInfo() const overridellvm::AArch64Subtargetinline
getSelectionDAGInfo() const overridellvm::AArch64Subtargetinline
getTargetLowering() const overridellvm::AArch64Subtargetinline
getTargetTriple() const llvm::AArch64Subtargetinline
getVectorInsertExtractBaseCost() const llvm::AArch64Subtargetinline
GISelllvm::AArch64Subtargetprotected
hasArithmeticBccFusion() const llvm::AArch64Subtargetinline
HasArithmeticBccFusionllvm::AArch64Subtargetprotected
hasArithmeticCbzFusion() const llvm::AArch64Subtargetinline
HasArithmeticCbzFusionllvm::AArch64Subtargetprotected
HasCRCllvm::AArch64Subtargetprotected
hasCRC() const llvm::AArch64Subtargetinline
hasCrypto() const llvm::AArch64Subtargetinline
HasCryptollvm::AArch64Subtargetprotected
hasCustomCheapAsMoveHandling() const llvm::AArch64Subtargetinline
hasFPARMv8() const llvm::AArch64Subtargetinline
HasFPARMv8llvm::AArch64Subtargetprotected
HasFullFP16llvm::AArch64Subtargetprotected
hasFullFP16() const llvm::AArch64Subtargetinline
HasLSEllvm::AArch64Subtargetprotected
hasLSE() const llvm::AArch64Subtargetinline
hasNEON() const llvm::AArch64Subtargetinline
HasNEONllvm::AArch64Subtargetprotected
hasPerfMon() const llvm::AArch64Subtargetinline
HasPerfMonllvm::AArch64Subtargetprotected
hasRAS() const llvm::AArch64Subtargetinline
HasRASllvm::AArch64Subtargetprotected
HasSPEllvm::AArch64Subtargetprotected
hasSPE() const llvm::AArch64Subtargetinline
hasV8_1aOps() const llvm::AArch64Subtargetinline
HasV8_1aOpsllvm::AArch64Subtargetprotected
HasV8_2aOpsllvm::AArch64Subtargetprotected
hasV8_2aOps() const llvm::AArch64Subtargetinline
hasZeroCycleRegMove() const llvm::AArch64Subtargetinline
HasZeroCycleRegMovellvm::AArch64Subtargetprotected
HasZeroCycleZeroingllvm::AArch64Subtargetprotected
hasZeroCycleZeroing() const llvm::AArch64Subtargetinline
InstrInfollvm::AArch64Subtargetprotected
IsLittlellvm::AArch64Subtargetprotected
isLittleEndian() const llvm::AArch64Subtargetinline
isMisaligned128StoreSlow() const llvm::AArch64Subtargetinline
isPaired128Slow() const llvm::AArch64Subtargetinline
isTargetAndroid() const llvm::AArch64Subtargetinline
isTargetCOFF() const llvm::AArch64Subtargetinline
isTargetDarwin() const llvm::AArch64Subtargetinline
isTargetELF() const llvm::AArch64Subtargetinline
isTargetIOS() const llvm::AArch64Subtargetinline
isTargetLinux() const llvm::AArch64Subtargetinline
isTargetMachO() const llvm::AArch64Subtargetinline
isTargetWindows() const llvm::AArch64Subtargetinline
isX18Reserved() const llvm::AArch64Subtargetinline
isXRaySupported() const overridellvm::AArch64Subtargetinline
Kryo enum valuellvm::AArch64Subtarget
MaxInterleaveFactorllvm::AArch64Subtargetprotected
MaxJumpTableSizellvm::AArch64Subtargetprotected
MaxPrefetchIterationsAheadllvm::AArch64Subtargetprotected
MinPrefetchStridellvm::AArch64Subtargetprotected
Misaligned128StoreIsSlowllvm::AArch64Subtargetprotected
Others enum valuellvm::AArch64Subtarget
overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const overridellvm::AArch64Subtarget
Paired128IsSlowllvm::AArch64Subtargetprotected
ParseSubtargetFeatures(StringRef CPU, StringRef FS)llvm::AArch64Subtarget
predictableSelectIsExpensive() const llvm::AArch64Subtargetinline
PredictableSelectIsExpensivellvm::AArch64Subtargetprotected
PrefetchDistancellvm::AArch64Subtargetprotected
PrefFunctionAlignmentllvm::AArch64Subtargetprotected
PrefLoopAlignmentllvm::AArch64Subtargetprotected
requiresStrictAlign() const llvm::AArch64Subtargetinline
ReserveX18llvm::AArch64Subtargetprotected
setGISelAccessor(GISelAccessor &GISel)llvm::AArch64Subtargetinline
StrictAlignllvm::AArch64Subtargetprotected
supportsAddressTopByteIgnored() const llvm::AArch64Subtarget
TargetTriplellvm::AArch64Subtargetprotected
TLInfollvm::AArch64Subtargetprotected
TSInfollvm::AArch64Subtargetprotected
useAA() const overridellvm::AArch64Subtargetinline
UseAAllvm::AArch64Subtargetprotected
useAlternateSExtLoadCVTF32Pattern() const llvm::AArch64Subtargetinline
UseAlternateSExtLoadCVTF32Patternllvm::AArch64Subtargetprotected
UsePostRASchedulerllvm::AArch64Subtargetprotected
useRSqrt() const llvm::AArch64Subtargetinline
UseRSqrtllvm::AArch64Subtargetprotected
VectorInsertExtractBaseCostllvm::AArch64Subtargetprotected
Vulcan enum valuellvm::AArch64Subtarget