35 PPC::R0, PPC::R1,
PPC::R2, PPC::R3,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42 PPC::R28, PPC::R29, PPC::R30, PPC::R31
48 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
49 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53 PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 PPC::X0, PPC::X1, PPC::X2, PPC::X3,
57 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
58 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
59 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63 PPC::X28, PPC::X29, PPC::X30, PPC::X31
67 PPC::X1, PPC::X2, PPC::X3,
68 PPC::X4, PPC::X5, PPC::X6, PPC::X7,
69 PPC::X8, PPC::X9, PPC::X10, PPC::X11,
70 PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74 PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
78 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
79 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
80 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84 PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
88 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
89 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
90 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
91 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
92 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
93 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
94 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
97 PPC::V0, PPC::V1,
PPC::V2, PPC::V3,
98 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
99 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
100 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
101 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
102 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
103 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
104 PPC::V28, PPC::V29, PPC::V30, PPC::V31
107 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
108 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
109 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
110 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
111 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
112 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
113 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
114 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
116 PPC::V0, PPC::V1,
PPC::V2, PPC::V3,
117 PPC::V4, PPC::V5, PPC::V6, PPC::V7,
118 PPC::V8, PPC::V9, PPC::V10, PPC::V11,
119 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
120 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
121 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
122 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
123 PPC::V28, PPC::V29, PPC::V30, PPC::V31
126 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
127 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
128 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
129 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
130 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
131 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
132 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
133 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
135 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
136 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
137 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
138 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
139 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
140 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
141 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
142 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
145 PPC::F0, PPC::F1, PPC::F2, PPC::F3,
146 PPC::F4, PPC::F5, PPC::F6, PPC::F7,
147 PPC::F8, PPC::F9, PPC::F10, PPC::F11,
148 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
149 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
150 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
151 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
152 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
154 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
155 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
156 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
157 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
158 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
159 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
160 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
161 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
164 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
165 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
166 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
167 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
168 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
169 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
170 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
171 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
174 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
175 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
176 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
177 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
178 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
179 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
180 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
181 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
184 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
185 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
198 int64_t Res = cast<MCConstantExpr>(
E)->getValue();
199 return Res < 0 ? -1 : Res;
206 if (Name ==
"lt")
return 0;
207 if (Name ==
"gt")
return 1;
208 if (Name ==
"eq")
return 2;
209 if (Name ==
"so")
return 3;
210 if (Name ==
"un")
return 3;
212 if (Name ==
"cr0")
return 0;
213 if (Name ==
"cr1")
return 1;
214 if (Name ==
"cr2")
return 2;
215 if (Name ==
"cr3")
return 3;
216 if (Name ==
"cr4")
return 4;
217 if (Name ==
"cr5")
return 5;
218 if (Name ==
"cr6")
return 6;
219 if (Name ==
"cr7")
return 7;
233 if (LHSVal < 0 || RHSVal < 0)
242 return Res < 0 ? -1 : Res;
258 void Warning(
SMLoc L,
const Twine &Msg) { getParser().Warning(L, Msg); }
260 bool isPPC64()
const {
return IsPPC64; }
261 bool isDarwin()
const {
return IsDarwin; }
265 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
270 bool ParseExpression(
const MCExpr *&EVal);
271 bool ParseDarwinExpression(
const MCExpr *&EVal);
275 bool ParseDirectiveWord(
unsigned Size,
AsmToken ID);
276 bool ParseDirectiveTC(
unsigned Size,
AsmToken ID);
277 bool ParseDirectiveMachine(
SMLoc L);
278 bool ParseDarwinDirectiveMachine(
SMLoc L);
279 bool ParseDirectiveAbiVersion(
SMLoc L);
280 bool ParseDirectiveLocalEntry(
SMLoc L);
282 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
285 bool MatchingInlineAsm)
override;
292 #define GET_ASSEMBLER_HEADER
293 #include "PPCGenAsmMatcher.inc"
308 setAvailableFeatures(ComputeAvailableFeatures(STI.
getFeatureBits()));
314 bool ParseDirective(
AsmToken DirectiveID)
override;
317 unsigned Kind)
override;
335 SMLoc StartLoc, EndLoc;
360 struct TLSRegOp TLSReg;
367 StartLoc = o.StartLoc;
375 case ContextImmediate:
389 void operator delete(
void *p) { ::operator
delete(p); }
392 SMLoc getStartLoc()
const override {
return StartLoc; }
395 SMLoc getEndLoc()
const override {
return EndLoc; }
398 bool isPPC64()
const {
return IsPPC64; }
400 int64_t getImm()
const {
401 assert(
Kind == Immediate &&
"Invalid access!");
404 int64_t getImmS16Context()
const {
407 if (
Kind == Immediate)
409 return static_cast<int16_t
>(Imm.Val);
411 int64_t getImmU16Context()
const {
418 assert(
Kind == Expression &&
"Invalid access!");
422 int64_t getExprCRVal()
const {
423 assert(
Kind == Expression &&
"Invalid access!");
427 const MCExpr *getTLSReg()
const {
428 assert(
Kind == TLSRegister &&
"Invalid access!");
432 unsigned getReg()
const override {
433 assert(isRegNumber() &&
"Invalid access!");
434 return (
unsigned) Imm.Val;
437 unsigned getVSReg()
const {
438 assert(isVSRegNumber() &&
"Invalid access!");
439 return (
unsigned) Imm.Val;
442 unsigned getCCReg()
const {
443 assert(isCCRegNumber() &&
"Invalid access!");
444 return (
unsigned) (
Kind == Immediate ? Imm.Val : Expr.CRVal);
447 unsigned getCRBit()
const {
448 assert(isCRBitNumber() &&
"Invalid access!");
449 return (
unsigned) (
Kind == Immediate ? Imm.Val : Expr.CRVal);
452 unsigned getCRBitMask()
const {
453 assert(isCRBitMask() &&
"Invalid access!");
454 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
457 bool isToken()
const override {
return Kind ==
Token; }
458 bool isImm()
const override {
459 return Kind == Immediate ||
Kind == Expression;
461 bool isU1Imm()
const {
return Kind == Immediate && isUInt<1>(getImm()); }
462 bool isU2Imm()
const {
return Kind == Immediate && isUInt<2>(getImm()); }
463 bool isU3Imm()
const {
return Kind == Immediate && isUInt<3>(getImm()); }
464 bool isU4Imm()
const {
return Kind == Immediate && isUInt<4>(getImm()); }
465 bool isU5Imm()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
466 bool isS5Imm()
const {
return Kind == Immediate && isInt<5>(getImm()); }
467 bool isU6Imm()
const {
return Kind == Immediate && isUInt<6>(getImm()); }
468 bool isU6ImmX2()
const {
return Kind == Immediate &&
469 isUInt<6>(getImm()) &&
470 (getImm() & 1) == 0; }
471 bool isU7Imm()
const {
return Kind == Immediate && isUInt<7>(getImm()); }
472 bool isU7ImmX4()
const {
return Kind == Immediate &&
473 isUInt<7>(getImm()) &&
474 (getImm() & 3) == 0; }
475 bool isU8Imm()
const {
return Kind == Immediate &&
isUInt<8>(getImm()); }
476 bool isU8ImmX8()
const {
return Kind == Immediate &&
478 (getImm() & 7) == 0; }
480 bool isU10Imm()
const {
return Kind == Immediate && isUInt<10>(getImm()); }
481 bool isU12Imm()
const {
return Kind == Immediate && isUInt<12>(getImm()); }
482 bool isU16Imm()
const {
487 case ContextImmediate:
493 bool isS16Imm()
const {
498 case ContextImmediate:
504 bool isS16ImmX4()
const {
return Kind == Expression ||
506 (getImm() & 3) == 0); }
507 bool isS16ImmX16()
const {
return Kind == Expression ||
509 (getImm() & 15) == 0); }
510 bool isS17Imm()
const {
515 case ContextImmediate:
516 return isInt<17>(getImmS16Context());
521 bool isTLSReg()
const {
return Kind == TLSRegister; }
522 bool isDirectBr()
const {
523 if (
Kind == Expression)
525 if (
Kind != Immediate)
528 if ((getImm() & 3) != 0)
530 if (isInt<26>(getImm()))
534 if (
isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
539 bool isCondBr()
const {
return Kind == Expression ||
541 (getImm() & 3) == 0); }
542 bool isRegNumber()
const {
return Kind == Immediate && isUInt<5>(getImm()); }
543 bool isVSRegNumber()
const {
544 return Kind == Immediate && isUInt<6>(getImm());
546 bool isCCRegNumber()
const {
return (
Kind == Expression
547 && isUInt<3>(getExprCRVal())) ||
549 && isUInt<3>(getImm())); }
550 bool isCRBitNumber()
const {
return (
Kind == Expression
551 && isUInt<5>(getExprCRVal())) ||
553 && isUInt<5>(getImm())); }
554 bool isCRBitMask()
const {
return Kind == Immediate &&
isUInt<8>(getImm()) &&
556 bool isATBitsAsHint()
const {
return false; }
557 bool isMem()
const override {
return false; }
558 bool isReg()
const override {
return false; }
560 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
564 void addRegGPRCOperands(
MCInst &Inst,
unsigned N)
const {
565 assert(N == 1 &&
"Invalid number of operands!");
569 void addRegGPRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
570 assert(N == 1 &&
"Invalid number of operands!");
574 void addRegG8RCOperands(
MCInst &Inst,
unsigned N)
const {
575 assert(N == 1 &&
"Invalid number of operands!");
579 void addRegG8RCNoX0Operands(
MCInst &Inst,
unsigned N)
const {
580 assert(N == 1 &&
"Invalid number of operands!");
584 void addRegGxRCOperands(
MCInst &Inst,
unsigned N)
const {
586 addRegG8RCOperands(Inst, N);
588 addRegGPRCOperands(Inst, N);
591 void addRegGxRCNoR0Operands(
MCInst &Inst,
unsigned N)
const {
593 addRegG8RCNoX0Operands(Inst, N);
595 addRegGPRCNoR0Operands(Inst, N);
598 void addRegF4RCOperands(
MCInst &Inst,
unsigned N)
const {
599 assert(N == 1 &&
"Invalid number of operands!");
603 void addRegF8RCOperands(
MCInst &Inst,
unsigned N)
const {
604 assert(N == 1 &&
"Invalid number of operands!");
608 void addRegVFRCOperands(
MCInst &Inst,
unsigned N)
const {
609 assert(N == 1 &&
"Invalid number of operands!");
613 void addRegVRRCOperands(
MCInst &Inst,
unsigned N)
const {
614 assert(N == 1 &&
"Invalid number of operands!");
618 void addRegVSRCOperands(
MCInst &Inst,
unsigned N)
const {
619 assert(N == 1 &&
"Invalid number of operands!");
623 void addRegVSFRCOperands(
MCInst &Inst,
unsigned N)
const {
624 assert(N == 1 &&
"Invalid number of operands!");
628 void addRegVSSRCOperands(
MCInst &Inst,
unsigned N)
const {
629 assert(N == 1 &&
"Invalid number of operands!");
633 void addRegQFRCOperands(
MCInst &Inst,
unsigned N)
const {
634 assert(N == 1 &&
"Invalid number of operands!");
638 void addRegQSRCOperands(
MCInst &Inst,
unsigned N)
const {
639 assert(N == 1 &&
"Invalid number of operands!");
643 void addRegQBRCOperands(
MCInst &Inst,
unsigned N)
const {
644 assert(N == 1 &&
"Invalid number of operands!");
648 void addRegCRBITRCOperands(
MCInst &Inst,
unsigned N)
const {
649 assert(N == 1 &&
"Invalid number of operands!");
653 void addRegCRRCOperands(
MCInst &Inst,
unsigned N)
const {
654 assert(N == 1 &&
"Invalid number of operands!");
658 void addCRBitMaskOperands(
MCInst &Inst,
unsigned N)
const {
659 assert(N == 1 &&
"Invalid number of operands!");
663 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
664 assert(N == 1 &&
"Invalid number of operands!");
665 if (
Kind == Immediate)
671 void addS16ImmOperands(
MCInst &Inst,
unsigned N)
const {
672 assert(N == 1 &&
"Invalid number of operands!");
677 case ContextImmediate:
686 void addU16ImmOperands(
MCInst &Inst,
unsigned N)
const {
687 assert(N == 1 &&
"Invalid number of operands!");
692 case ContextImmediate:
701 void addBranchTargetOperands(
MCInst &Inst,
unsigned N)
const {
702 assert(N == 1 &&
"Invalid number of operands!");
703 if (
Kind == Immediate)
709 void addTLSRegOperands(
MCInst &Inst,
unsigned N)
const {
710 assert(N == 1 &&
"Invalid number of operands!");
721 static std::unique_ptr<PPCOperand> CreateToken(
StringRef Str,
SMLoc S,
723 auto Op = make_unique<PPCOperand>(
Token);
724 Op->Tok.Data = Str.
data();
725 Op->Tok.Length = Str.
size();
728 Op->IsPPC64 = IsPPC64;
732 static std::unique_ptr<PPCOperand>
739 void *Mem = ::operator
new(
sizeof(PPCOperand) + Str.
size());
740 std::unique_ptr<PPCOperand>
Op(
new (Mem) PPCOperand(
Token));
741 Op->Tok.Data =
reinterpret_cast<const char *
>(
Op.get() + 1);
742 Op->Tok.Length = Str.
size();
743 std::memcpy(const_cast<char *>(
Op->Tok.Data), Str.
data(), Str.
size());
746 Op->IsPPC64 = IsPPC64;
750 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val,
SMLoc S,
SMLoc E,
752 auto Op = make_unique<PPCOperand>(Immediate);
756 Op->IsPPC64 = IsPPC64;
760 static std::unique_ptr<PPCOperand> CreateExpr(
const MCExpr *Val,
SMLoc S,
762 auto Op = make_unique<PPCOperand>(Expression);
767 Op->IsPPC64 = IsPPC64;
771 static std::unique_ptr<PPCOperand>
773 auto Op = make_unique<PPCOperand>(TLSRegister);
774 Op->TLSReg.Sym = Sym;
777 Op->IsPPC64 = IsPPC64;
781 static std::unique_ptr<PPCOperand>
782 CreateContextImm(int64_t Val,
SMLoc S,
SMLoc E,
bool IsPPC64) {
783 auto Op = make_unique<PPCOperand>(ContextImmediate);
787 Op->IsPPC64 = IsPPC64;
791 static std::unique_ptr<PPCOperand>
794 return CreateImm(
CE->getValue(), S,
E, IsPPC64);
798 return CreateTLSReg(SRE, S, E, IsPPC64);
800 if (
const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
802 if (TE->evaluateAsConstant(Res))
803 return CreateContextImm(Res, S, E, IsPPC64);
806 return CreateExpr(Val, S, E, IsPPC64);
818 case ContextImmediate:
837 if (
const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
842 }
else if (
const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
845 BinExpr->getLHS(), Ctx);
853 void PPCAsmParser::ProcessInstruction(
MCInst &Inst,
862 TmpInst.
setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
863 PPC::DCBT : PPC::DCBTST);
865 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
882 case PPC::DCBTSTDS: {
895 if (Opcode == PPC::DCBFL)
897 else if (Opcode == PPC::DCBFLP)
958 TmpInst.
setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
972 TmpInst.
setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
986 TmpInst.
setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
1001 TmpInst.
setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
1012 case PPC::ROTRWIo: {
1015 TmpInst.
setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
1028 TmpInst.
setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
1041 TmpInst.
setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1051 case PPC::CLRRWIo: {
1054 TmpInst.
setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1064 case PPC::CLRLSLWIo: {
1068 TmpInst.
setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1078 case PPC::EXTLDIo: {
1082 TmpInst.
setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1091 case PPC::EXTRDIo: {
1095 TmpInst.
setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1104 case PPC::INSRDIo: {
1108 TmpInst.
setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1118 case PPC::ROTRDIo: {
1121 TmpInst.
setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1133 TmpInst.
setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1145 TmpInst.
setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1154 case PPC::CLRRDIo: {
1157 TmpInst.
setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1166 case PPC::CLRLSLDIo: {
1170 TmpInst.
setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1179 case PPC::RLWINMobm: {
1186 TmpInst.
setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1196 case PPC::RLWIMIobm: {
1203 TmpInst.
setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1214 case PPC::RLWNMobm: {
1221 TmpInst.
setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1231 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1238 case PPC::CP_COPY_FIRST: {
1248 case PPC::CP_PASTEx :
1249 case PPC::CP_PASTE_LAST: {
1251 TmpInst.
setOpcode(Opcode == PPC::CP_PASTEx ?
1252 PPC::CP_PASTE : PPC::CP_PASTEo);
1263 bool PPCAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
1266 bool MatchingInlineAsm) {
1269 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1272 ProcessInstruction(Inst, Operands);
1276 case Match_MissingFeature:
1277 return Error(IDLoc,
"instruction use requires an option to be enabled");
1278 case Match_MnemonicFail:
1279 return Error(IDLoc,
"unrecognized instruction mnemonic");
1280 case Match_InvalidOperand: {
1281 SMLoc ErrorLoc = IDLoc;
1282 if (ErrorInfo != ~0ULL) {
1283 if (ErrorInfo >= Operands.
size())
1284 return Error(IDLoc,
"too few operands for instruction");
1286 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1287 if (ErrorLoc ==
SMLoc()) ErrorLoc = IDLoc;
1290 return Error(ErrorLoc,
"invalid operand for instruction");
1301 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1304 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1307 RegNo = PPC::VRSAVE;
1336 ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
1337 const AsmToken &Tok = getParser().getTok();
1343 return TokError(
"invalid register name");
1353 const MCExpr *PPCAsmParser::
1354 ExtractModifierFromExpr(
const MCExpr *E,
1407 const MCExpr *LHS = ExtractModifierFromExpr(BE->
getLHS(), LHSVariant);
1408 const MCExpr *RHS = ExtractModifierFromExpr(BE->
getRHS(), RHSVariant);
1413 if (!LHS) LHS = BE->
getLHS();
1414 if (!RHS) RHS = BE->
getRHS();
1417 Variant = RHSVariant;
1419 Variant = LHSVariant;
1420 else if (LHSVariant == RHSVariant)
1421 Variant = LHSVariant;
1436 const MCExpr *PPCAsmParser::
1437 FixupVariantKind(
const MCExpr *E) {
1438 MCContext &Context = getParser().getContext();
1486 ParseExpression(
const MCExpr *&EVal) {
1489 return ParseDarwinExpression(EVal);
1493 if (getParser().parseExpression(EVal))
1496 EVal = FixupVariantKind(EVal);
1499 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1513 ParseDarwinExpression(
const MCExpr *&EVal) {
1516 switch (getLexer().getKind()) {
1541 if (getParser().parseExpression(EVal))
1563 switch (getLexer().getKind()) {
1571 return Error(S,
"invalid register name");
1573 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1593 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1599 if (!ParseExpression(EVal))
1604 return Error(S,
"unknown operand");
1608 Operands.
push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1611 bool TLSCall =
false;
1613 TLSCall = Ref->getSymbol().getName() ==
"__tls_get_addr";
1620 if (ParseExpression(TLSSym))
1621 return Error(S,
"invalid TLS call expression");
1627 Operands.
push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1636 switch (getLexer().getKind()) {
1641 return Error(S,
"invalid register name");
1646 return Error(S,
"unexpected integer value");
1647 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1649 return Error(S,
"invalid register number");
1661 return Error(S,
"invalid memory operand");
1667 Operands.
push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1679 std::string NewOpcode;
1692 size_t Dot = Name.
find(
'.');
1694 if (!NewOpcode.empty())
1696 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1698 Operands.
push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1702 if (!NewOpcode.empty())
1704 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1706 Operands.
push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1714 if (ParseOperand(Operands))
1730 if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1731 Operands.
size() == 4 &&
1732 (Name ==
"dcbt" || Name ==
"dcbtst")) {
1741 bool PPCAsmParser::ParseDirective(
AsmToken DirectiveID) {
1744 if (IDVal ==
".machine")
1745 ParseDarwinDirectiveMachine(DirectiveID.
getLoc());
1748 }
else if (IDVal ==
".word")
1749 ParseDirectiveWord(2, DirectiveID);
1750 else if (IDVal ==
".llong")
1751 ParseDirectiveWord(8, DirectiveID);
1752 else if (IDVal ==
".tc")
1753 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1754 else if (IDVal ==
".machine")
1755 ParseDirectiveMachine(DirectiveID.
getLoc());
1756 else if (IDVal ==
".abiversion")
1757 ParseDirectiveAbiVersion(DirectiveID.
getLoc());
1758 else if (IDVal ==
".localentry")
1759 ParseDirectiveLocalEntry(DirectiveID.
getLoc());
1767 bool PPCAsmParser::ParseDirectiveWord(
unsigned Size,
AsmToken ID) {
1768 auto parseOp = [&]() ->
bool {
1770 SMLoc ExprLoc = getParser().getTok().getLoc();
1771 if (getParser().parseExpression(Value))
1773 if (
const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1774 assert(Size <= 8 &&
"Invalid size");
1775 uint64_t IntValue = MCE->getValue();
1776 if (!
isUIntN(8 * Size, IntValue) && !
isIntN(8 * Size, IntValue))
1777 return Error(ExprLoc,
"literal value out of range for '" +
1779 getStreamer().EmitIntValue(IntValue, Size);
1781 getStreamer().EmitValue(Value, Size, ExprLoc);
1785 if (parseMany(parseOp))
1786 return addErrorSuffix(
" in '" + ID.
getIdentifier() +
"' directive");
1792 bool PPCAsmParser::ParseDirectiveTC(
unsigned Size,
AsmToken ID) {
1799 return addErrorSuffix(
" in '.tc' directive");
1802 getParser().getStreamer().EmitValueToAlignment(Size);
1805 return ParseDirectiveWord(Size, ID);
1810 bool PPCAsmParser::ParseDirectiveMachine(
SMLoc L) {
1814 return Error(L,
"unexpected token in '.machine' directive");
1823 if (CPU !=
"any" && CPU !=
"push" && CPU !=
"pop")
1824 return TokError(
"unrecognized machine type");
1829 return addErrorSuffix(
" in '.machine' directive");
1833 getParser().getStreamer().getTargetStreamer());
1841 bool PPCAsmParser::ParseDarwinDirectiveMachine(
SMLoc L) {
1845 return Error(L,
"unexpected token in directive");
1853 if (check(CPU !=
"ppc7400" && CPU !=
"ppc" && CPU !=
"ppc64", L,
1854 "unrecognized cpu type") ||
1855 check(isPPC64() && (CPU ==
"ppc7400" || CPU ==
"ppc"), L,
1856 "wrong cpu type specified for 64bit") ||
1857 check(!isPPC64() && CPU ==
"ppc64", L,
1858 "wrong cpu type specified for 32bit") ||
1860 return addErrorSuffix(
" in '.machine' directive");
1866 bool PPCAsmParser::ParseDirectiveAbiVersion(
SMLoc L) {
1868 if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1869 "expected constant expression") ||
1871 return addErrorSuffix(
" in '.abiversion' directive");
1875 getParser().getStreamer().getTargetStreamer());
1883 bool PPCAsmParser::ParseDirectiveLocalEntry(
SMLoc L) {
1885 if (getParser().parseIdentifier(Name))
1886 return Error(L,
"expected identifier in '.localentry' directive");
1888 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1892 check(getParser().parseExpression(Expr), L,
"expected expression") ||
1894 return addErrorSuffix(
" in '.localentry' directive");
1898 getParser().getStreamer().getTargetStreamer());
1913 #define GET_REGISTER_MATCHER
1914 #define GET_MATCHER_IMPLEMENTATION
1915 #include "PPCGenAsmMatcher.inc"
1926 case MCK_0: ImmVal = 0;
break;
1927 case MCK_1: ImmVal = 1;
break;
1928 case MCK_2: ImmVal = 2;
break;
1929 case MCK_3: ImmVal = 3;
break;
1930 case MCK_4: ImmVal = 4;
break;
1931 case MCK_5: ImmVal = 5;
break;
1932 case MCK_6: ImmVal = 6;
break;
1933 case MCK_7: ImmVal = 7;
break;
1934 default:
return Match_InvalidOperand;
1937 PPCOperand &
Op =
static_cast<PPCOperand &
>(AsmOp);
1938 if (Op.isImm() && Op.getImm() == ImmVal)
1939 return Match_Success;
1941 return Match_InvalidOperand;
1945 PPCAsmParser::applyModifierToExpr(
const MCExpr *E,
static bool isReg(const MCInst &MI, unsigned OpNo)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
constexpr bool isUInt< 32 >(uint64_t x)
static const MCPhysReg XRegsNoX0[32]
void push_back(const T &Elt)
static int64_t EvaluateCRExpr(const MCExpr *E)
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx)
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx)
const MCSymbol & getSymbol() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
const char * getPointer() const
static unsigned MatchRegisterName(StringRef Name)
Generic assembler parser interface, for use by target specific assembly parsers.
static const MCPhysReg VFRegs[32]
static const PPCMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isDarwin, MCContext &Ctx)
static MCOperand createExpr(const MCExpr *Val)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
LLVM_NODISCARD bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Target & getThePPC32Target()
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static const MCPhysReg VRegs[32]
static const MCPhysReg CRBITRegs[32]
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
bool isNot(TokenKind K) const
static const MCPhysReg FRegs[32]
constexpr bool isInt< 16 >(int64_t x)
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static MCOperand createReg(unsigned Reg)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
static const MCPhysReg VSSRegs[64]
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Target independent representation for an assembler token.
Represent a reference to a symbol from inside an expression.
Windows NT (Windows on ARM)
static const MCPhysReg CRRegs[8]
static bool isMem(const MachineInstr &MI, unsigned Op)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static const MCPhysReg XRegs[32]
Context object for machine code objects.
static unsigned QFRegs[32]
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Unary assembler expressions.
virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset)=0
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Target & getThePPC64Target()
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Instances of this class represent a single low-level machine instruction.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MCExpr * getExpr() const
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Streaming machine code generation interface.
constexpr bool isUInt< 8 >(uint64_t x)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t find(char C, size_t From=0) const
Search for the first character C in the string.
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
virtual void emitAbiVersion(int AbiVersion)=0
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Interface to description of machine instruction set.
void LLVMInitializePowerPCAsmParser()
Force static initialization.
MCExpr const & getExpr(MCExpr const &Expr)
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
Binary assembler expressions.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static void addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx)
Triple - Helper class for working with autoconf configuration names.
void setOpcode(unsigned Op)
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
unsigned getOpcode() const
Target & getThePPC64LETarget()
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
static SMLoc getFromPointer(const char *Ptr)
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
static const MCPhysReg VSRegs[64]
const MCExpr * getSubExpr() const
Get the child of this unary expression.
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
StringRef getName() const
getName - Get the symbol name.
unsigned getNumOperands() const
Opcode getOpcode() const
Get the kind of this binary expression.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
const Triple & getTargetTriple() const
getTargetTriple - Return the target triple string.
constexpr bool isUInt< 16 >(uint64_t x)
static const MCPhysReg RRegs[32]
VariantKind getKind() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME)
Returns true iff Val consists of one contiguous run of 1s with any number of 0s on either side...
LLVM Value Representation.
static const MCPhysReg VSFRegs[64]
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
This class implements an extremely fast bulk output stream that can only output to a stream...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
Target specific expression.
virtual void emitMachine(StringRef CPU)=0
Represents a location in source code.
LLVM_NODISCARD bool startswith_lower(StringRef Prefix) const
Check if this string starts with the given Prefix, ignoring case.
bool isUIntN(unsigned N, uint64_t x)
isUIntN - Checks if an unsigned integer fits into the given (dynamic) bit width.
Instances of this class represent operands of the MCInst class.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
static MCOperand createImm(int64_t Val)
const MCOperand & getOperand(unsigned i) const
static const MCPhysReg RRegsNoR0[32]
Opcode getOpcode() const
Get the kind of this unary expression.