34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "AVRGenInstrInfo.inc"
44 const DebugLoc &DL,
unsigned DestReg,
45 unsigned SrcReg,
bool KillSrc)
const {
51 if (AVR::DREGSRegClass.
contains(DestReg, SrcReg)) {
53 BuildMI(MBB, MI, DL,
get(AVR::MOVWRdRr), DestReg)
56 unsigned DestLo, DestHi, SrcLo, SrcHi;
58 TRI.splitReg(DestReg, DestLo, DestHi);
59 TRI.splitReg(SrcReg, SrcLo, SrcHi);
62 BuildMI(MBB, MI, DL,
get(AVR::MOVRdRr), DestLo)
64 BuildMI(MBB, MI, DL,
get(AVR::MOVRdRr), DestHi)
68 if (AVR::GPR8RegClass.
contains(DestReg, SrcReg)) {
70 }
else if (SrcReg == AVR::SP && AVR::DREGSRegClass.
contains(DestReg)) {
72 }
else if (DestReg == AVR::SP && AVR::DREGSRegClass.
contains(SrcReg)) {
78 BuildMI(MBB, MI, DL,
get(Opc), DestReg)
106 case AVR::STDWPtrQRr: {
123 unsigned SrcReg,
bool isKill,
133 if (MI != MBB.
end()) {
134 DL = MI->getDebugLoc();
146 Opcode = AVR::STDPtrQRr;
148 Opcode = AVR::STDWPtrQRr;
153 BuildMI(MBB, MI, DL,
get(Opcode))
166 if (MI != MBB.
end()) {
167 DL = MI->getDebugLoc();
180 Opcode = AVR::LDDRdPtrQ;
184 Opcode = AVR::LDDWRdYQ;
189 BuildMI(MBB, MI, DL,
get(Opcode), DestReg)
200 return get(AVR::BREQk);
202 return get(AVR::BRNEk);
204 return get(AVR::BRGEk);
206 return get(AVR::BRLTk);
208 return get(AVR::BRSHk);
210 return get(AVR::BRLOk);
212 return get(AVR::BRMIk);
214 return get(AVR::BRPLk);
268 bool AllowModify)
const {
274 while (I != MBB.
begin()) {
276 if (I->isDebugValue()) {
282 if (!isUnpredicatedTerminator(*I)) {
288 if (!I->getDesc().isBranch()) {
294 if (I->getOpcode() == AVR::RJMPk) {
298 TBB = I->getOperand(0).getMBB();
303 while (std::next(I) != MBB.
end()) {
304 std::next(I)->eraseFromParent();
313 I->eraseFromParent();
315 UnCondBrIter = MBB.
end();
320 TBB = I->getOperand(0).getMBB();
333 if (AllowModify && UnCondBrIter != MBB.
end() &&
357 .
addMBB(UnCondBrIter->getOperand(0).getMBB());
361 OldInst->eraseFromParent();
362 UnCondBrIter->eraseFromParent();
365 UnCondBrIter = MBB.
end();
371 TBB = I->getOperand(0).getMBB();
383 if (TBB != I->getOperand(0).getMBB()) {
389 if (OldBranchCode == BranchCode) {
404 int *BytesAdded)
const {
405 assert(!BytesAdded &&
"code size not handled");
408 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
410 "AVR branch conditions have one component!");
413 assert(!FBB &&
"Unconditional branch with multiple successors!");
434 int *BytesRemoved)
const {
435 assert(!BytesRemoved &&
"code size not handled");
440 while (I != MBB.
begin()) {
442 if (I->isDebugValue()) {
447 if (I->getOpcode() != AVR::RJMPk &&
453 I->eraseFromParent();
463 assert(Cond.
size() == 1 &&
"Invalid AVR branch condition!");
481 case TargetOpcode::IMPLICIT_DEF:
483 case TargetOpcode::DBG_VALUE:
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
const AVRInstrInfo * getInstrInfo() const override
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
const char * getSymbolName() const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Utilities relating to AVR registers.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
return AArch64::GPR64RegClass contains(Reg)
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
const HexagonInstrInfo * TII
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
LLVM_NODISCARD bool empty() const
A generic AVR implementation.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Contains AVR-specific information for each MachineFunction.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool empty() const
empty - Check if the array is empty.
CondCodes
AVR specific condition codes.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
unsigned getOpcode() const
Return the opcode number for this descriptor.
The memory access writes data.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
const MachineInstrBuilder & addFrameIndex(int Idx) const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
A specific AVR target MCU.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const AVRRegisterInfo * getRegisterInfo() const override
AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
void setHasSpills(bool B)
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.