15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
27 namespace AArch64ISD {
229 static inline bool isDef32(
const SDNode &
N) {
230 unsigned Opc = N.getOpcode();
231 return Opc !=
ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
237 class AArch64Subtarget;
238 class AArch64TargetMachine;
255 unsigned Depth = 0)
const override;
263 bool *
Fast =
nullptr)
const override;
293 EVT VT)
const override;
305 unsigned Intrinsic)
const override;
316 bool hasPairedLoad(
EVT LoadedType,
unsigned &RequiredAligment)
const override;
323 unsigned Factor)
const override;
325 unsigned Factor)
const override;
331 bool IsMemset,
bool ZeroMemset,
bool MemcpyStrSrc,
337 unsigned AS)
const override;
345 unsigned AS)
const override;
360 Type *Ty)
const override;
445 void addTypeForNEON(
MVT VT,
MVT PromotedBitwiseVT);
446 void addDRTypeForNEON(
MVT VT);
447 void addQRTypeForNEON(
MVT VT);
455 SDValue LowerCall(CallLoweringInfo & ,
467 bool isEligibleForTailCallOptimization(
479 bool DoesCalleeRestoreStack(
CallingConv::ID CallCC,
bool TailCallOpt)
const;
541 std::vector<SDNode *> *Created)
const override;
543 int &ExtraSteps,
bool &UseOneConst,
544 bool Reciprocal)
const override;
546 int &ExtraSteps)
const override;
547 unsigned combineRepeatedFPDivisors()
const override;
550 unsigned getRegisterByName(
const char* RegName,
EVT VT,
556 getSingleConstraintMatchWeight(AsmOperandInfo &
info,
557 const char *constraint)
const override;
559 std::pair<unsigned, const TargetRegisterClass *>
563 const char *LowerXConstraint(
EVT ConstraintVT)
const override;
565 void LowerAsmOperandForConstraint(
SDValue Op, std::string &Constraint,
566 std::vector<SDValue> &Ops,
569 unsigned getInlineAsmMemConstraint(
StringRef ConstraintCode)
const override {
570 if (ConstraintCode ==
"Q")
578 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain)
const override;
579 bool mayBeEmittedAsTailCall(CallInst *CI)
const override;
580 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &
Offset,
582 SelectionDAG &DAG)
const;
583 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &
Offset,
585 SelectionDAG &DAG)
const override;
586 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
588 SelectionDAG &DAG)
const override;
590 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &
Results,
591 SelectionDAG &DAG)
const override;
593 bool functionArgumentNeedsConsecutiveRegisters(
Type *Ty,
595 bool isVarArg)
const override;
597 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT)
const override;
602 const TargetLibraryInfo *libInfo);
BUILTIN_OP_END - This must be the last enum value in this list.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
A parsed version of the target data layout string in and methods for querying it. ...
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, unsigned Align=1, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
This class represents a function call, abstracting a target machine's calling convention.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return the cost of the scaling factor used in the addressing mode represented by AM for this target...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
An instruction for reading from memory.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a ldN intrinsic.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ISD::SETCC ValueType.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
AtomicOrdering
Atomic ordering for LLVM's memory model.
Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const override
If the target has a standard location for the unsafe stack pointer, returns the address of that locat...
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override
An instruction for storing to memory.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
Returns true if the target can instruction select the specified FP immediate natively.
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
bool isIntDivCheap(EVT VT, AttributeSet Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) !=...
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
This is an important base class in LLVM.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MachineBasicBlock * EmitF128CSEL(MachineInstr &MI, MachineBasicBlock *BB) const
bool isDesirableToCommuteWithShift(const SDNode *N) const override
Returns false if N is a bit extraction pattern of (X >> C) & Mask.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
CCState - This class holds information needed while lowering arguments and return values...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
AArch64TargetLowering(const TargetMachine &TM, const AArch64Subtarget &STI)
Provides information about what library functions are available for the current target.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
bool isProfitableToHoist(Instruction *I) const override
Check if it is profitable to hoist instruction in then/else to if.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a stN intrinsic.
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Class for arbitrary precision integers.
Value * getIRStackGuard(IRBuilder<> &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
AddrMode
ARM Addressing Modes.
Representation of each machine instruction.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
This method returns a target specific FastISel object, or null if the target does not support "fast" ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
bool isLegalAddImmediate(int64_t) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
LLVM Value Representation.
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
TRUNCATE - Completely drop the high bits.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
This file describes how to lower LLVM code to machine code.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.