LLVM  4.0.0
X86IntelInstPrinter.cpp
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1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as Intel-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86IntelInstPrinter.h"
18 #include "X86InstComments.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
24 #include <cctype>
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "asm-printer"
28 
29 #include "X86GenAsmWriter1.inc"
30 
31 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
32  OS << getRegisterName(RegNo);
33 }
34 
36  StringRef Annot,
37  const MCSubtargetInfo &STI) {
38  const MCInstrDesc &Desc = MII.get(MI->getOpcode());
39  uint64_t TSFlags = Desc.TSFlags;
40 
41  if (TSFlags & X86II::LOCK)
42  OS << "\tlock\n";
43 
44  printInstruction(MI, OS);
45 
46  // Next always print the annotation.
47  printAnnotation(OS, Annot);
48 
49  // If verbose assembly is enabled, we can print some informative comments.
50  if (CommentStream)
52 }
53 
55  raw_ostream &O) {
56  int64_t Imm = MI->getOperand(Op).getImm();
57  switch (Imm) {
58  default: llvm_unreachable("Invalid avxcc argument!");
59  case 0: O << "eq"; break;
60  case 1: O << "lt"; break;
61  case 2: O << "le"; break;
62  case 3: O << "unord"; break;
63  case 4: O << "neq"; break;
64  case 5: O << "nlt"; break;
65  case 6: O << "nle"; break;
66  case 7: O << "ord"; break;
67  case 8: O << "eq_uq"; break;
68  case 9: O << "nge"; break;
69  case 0xa: O << "ngt"; break;
70  case 0xb: O << "false"; break;
71  case 0xc: O << "neq_oq"; break;
72  case 0xd: O << "ge"; break;
73  case 0xe: O << "gt"; break;
74  case 0xf: O << "true"; break;
75  case 0x10: O << "eq_os"; break;
76  case 0x11: O << "lt_oq"; break;
77  case 0x12: O << "le_oq"; break;
78  case 0x13: O << "unord_s"; break;
79  case 0x14: O << "neq_us"; break;
80  case 0x15: O << "nlt_uq"; break;
81  case 0x16: O << "nle_uq"; break;
82  case 0x17: O << "ord_s"; break;
83  case 0x18: O << "eq_us"; break;
84  case 0x19: O << "nge_uq"; break;
85  case 0x1a: O << "ngt_uq"; break;
86  case 0x1b: O << "false_os"; break;
87  case 0x1c: O << "neq_os"; break;
88  case 0x1d: O << "ge_oq"; break;
89  case 0x1e: O << "gt_oq"; break;
90  case 0x1f: O << "true_us"; break;
91  }
92 }
93 
95  raw_ostream &O) {
96  int64_t Imm = MI->getOperand(Op).getImm();
97  switch (Imm) {
98  default: llvm_unreachable("Invalid xopcc argument!");
99  case 0: O << "lt"; break;
100  case 1: O << "le"; break;
101  case 2: O << "gt"; break;
102  case 3: O << "ge"; break;
103  case 4: O << "eq"; break;
104  case 5: O << "neq"; break;
105  case 6: O << "false"; break;
106  case 7: O << "true"; break;
107  }
108 }
109 
111  raw_ostream &O) {
112  int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
113  switch (Imm) {
114  case 0: O << "{rn-sae}"; break;
115  case 1: O << "{rd-sae}"; break;
116  case 2: O << "{ru-sae}"; break;
117  case 3: O << "{rz-sae}"; break;
118  }
119 }
120 
121 /// printPCRelImm - This is used to print an immediate value that ends up
122 /// being encoded as a pc-relative value.
123 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
124  raw_ostream &O) {
125  const MCOperand &Op = MI->getOperand(OpNo);
126  if (Op.isImm())
127  O << formatImm(Op.getImm());
128  else {
129  assert(Op.isExpr() && "unknown pcrel immediate operand");
130  // If a symbolic branch target was added as a constant expression then print
131  // that address in hex.
132  const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
133  int64_t Address;
134  if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
135  O << formatHex((uint64_t)Address);
136  }
137  else {
138  // Otherwise, just print the expression.
139  Op.getExpr()->print(O, &MAI);
140  }
141  }
142 }
143 
144 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
145  raw_ostream &O) {
146  const MCOperand &Op = MI->getOperand(OpNo);
147  if (Op.isReg()) {
148  printRegName(O, Op.getReg());
149  } else if (Op.isImm()) {
150  O << formatImm((int64_t)Op.getImm());
151  } else {
152  assert(Op.isExpr() && "unknown operand kind in printOperand");
153  Op.getExpr()->print(O, &MAI);
154  }
155 }
156 
158  raw_ostream &O) {
159  const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
160  unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
161  const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
162  const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
163  const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
164 
165  // If this has a segment register, print it.
166  if (SegReg.getReg()) {
168  O << ':';
169  }
170 
171  O << '[';
172 
173  bool NeedPlus = false;
174  if (BaseReg.getReg()) {
175  printOperand(MI, Op+X86::AddrBaseReg, O);
176  NeedPlus = true;
177  }
178 
179  if (IndexReg.getReg()) {
180  if (NeedPlus) O << " + ";
181  if (ScaleVal != 1)
182  O << ScaleVal << '*';
183  printOperand(MI, Op+X86::AddrIndexReg, O);
184  NeedPlus = true;
185  }
186 
187  if (!DispSpec.isImm()) {
188  if (NeedPlus) O << " + ";
189  assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
190  DispSpec.getExpr()->print(O, &MAI);
191  } else {
192  int64_t DispVal = DispSpec.getImm();
193  if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
194  if (NeedPlus) {
195  if (DispVal > 0)
196  O << " + ";
197  else {
198  O << " - ";
199  DispVal = -DispVal;
200  }
201  }
202  O << formatImm(DispVal);
203  }
204  }
205 
206  O << ']';
207 }
208 
210  raw_ostream &O) {
211  const MCOperand &SegReg = MI->getOperand(Op+1);
212 
213  // If this has a segment register, print it.
214  if (SegReg.getReg()) {
215  printOperand(MI, Op+1, O);
216  O << ':';
217  }
218  O << '[';
219  printOperand(MI, Op, O);
220  O << ']';
221 }
222 
224  raw_ostream &O) {
225  // DI accesses are always ES-based.
226  O << "es:[";
227  printOperand(MI, Op, O);
228  O << ']';
229 }
230 
232  raw_ostream &O) {
233  const MCOperand &DispSpec = MI->getOperand(Op);
234  const MCOperand &SegReg = MI->getOperand(Op+1);
235 
236  // If this has a segment register, print it.
237  if (SegReg.getReg()) {
238  printOperand(MI, Op+1, O);
239  O << ':';
240  }
241 
242  O << '[';
243 
244  if (DispSpec.isImm()) {
245  O << formatImm(DispSpec.getImm());
246  } else {
247  assert(DispSpec.isExpr() && "non-immediate displacement?");
248  DispSpec.getExpr()->print(O, &MAI);
249  }
250 
251  O << ']';
252 }
253 
255  raw_ostream &O) {
256  if (MI->getOperand(Op).isExpr())
257  return MI->getOperand(Op).getExpr()->print(O, &MAI);
258 
259  O << formatImm(MI->getOperand(Op).getImm() & 0xff);
260 }
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
bool isReg() const
Definition: MCInst.h:56
void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O)
format_object< int64_t > formatHex(int64_t Value) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O)
void printInstruction(const MCInst *MI, raw_ostream &O)
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
bool isImm() const
Definition: MCInst.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
bool isExpr() const
Definition: MCInst.h:59
static const char * getRegisterName(unsigned RegNo)
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:99
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &O)
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:46
unsigned getOpcode() const
Definition: MCInst.h:159
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O)
int64_t getImm() const
Definition: MCInst.h:74
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:47
MCSubtargetInfo - Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:48
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:33
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
printPCRelImm - This is used to print an immediate value that ends up being encoded as a pc-relative ...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const char *(*getRegName)(unsigned))
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...