29 #define DEBUG_TYPE "t2-reduce-size"
31 STATISTIC(NumNarrows,
"Number of 32-bit instrs reduced to 16-bit ones");
32 STATISTIC(Num2Addrs,
"Number of 32-bit instrs reduced to 2addr 16-bit ones");
33 STATISTIC(NumLdSts,
"Number of 32-bit load / store reduced to 16-bit ones");
51 unsigned LowRegs1 : 1;
52 unsigned LowRegs2 : 1;
57 unsigned PartFlag : 1;
59 unsigned AvoidMovs: 1;
62 static const ReduceEntry ReduceTable[] = {
64 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
65 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
66 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
67 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
68 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
69 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
70 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
71 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
72 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
75 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
76 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
77 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
78 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
81 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
82 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
83 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
84 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
85 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
86 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
88 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
89 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
90 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
91 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
92 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
93 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
94 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
95 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
96 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
97 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
98 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
99 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
100 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
101 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
102 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
103 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
104 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
105 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
106 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
107 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
111 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
112 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
113 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
114 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
115 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
116 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
118 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
119 { ARM::t2LDR_POST,ARM::tLDMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
120 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
121 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
122 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
123 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
124 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
125 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
126 { ARM::t2STR_POST,ARM::tSTMIA_UPD,0, 0, 0, 1, 0, 0,0, 0,1,0 },
128 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
129 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
130 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
134 { ARM::t2STMIA, ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
135 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
136 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
155 return "Thumb2 instruction size reduction pass";
166 bool LiveCPSR,
bool &HasCC,
bool &CCDead);
169 const ReduceEntry &Entry);
172 const ReduceEntry &Entry,
bool LiveCPSR,
bool IsSelfLoop);
177 const ReduceEntry &Entry,
bool LiveCPSR,
183 const ReduceEntry &Entry,
bool LiveCPSR,
188 bool LiveCPSR,
bool IsSelfLoop);
200 bool HighLatencyCPSR;
204 bool HighLatencyCPSR;
208 MBBInfo() : HighLatencyCPSR(
false), Visited(
false) {}
213 std::function<bool(const Function &)> PredicateFtor;
220 OptimizeSize = MinimizeSize =
false;
222 unsigned FromOpc = ReduceTable[
i].WideOpc;
223 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc,
i)).second)
230 if (*
Regs == ARM::CPSR)
263 Thumb2SizeReduce::canAddPseudoFlagDep(
MachineInstr *
Use,
bool FirstInSelfLoop) {
265 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
271 return HighLatencyCPSR || FirstInSelfLoop;
275 if (!MO.isReg() || MO.isUndef() || MO.isUse())
277 unsigned Reg = MO.getReg();
278 if (Reg == 0 || Reg == ARM::CPSR)
284 if (!MO.isReg() || MO.isUndef() || MO.isDef())
286 unsigned Reg = MO.getReg();
306 Thumb2SizeReduce::VerifyPredAndCC(
MachineInstr *
MI,
const ReduceEntry &Entry,
308 bool LiveCPSR,
bool &HasCC,
bool &CCDead) {
309 if ((is2Addr && Entry.PredCC2 == 0) ||
310 (!is2Addr && Entry.PredCC1 == 0)) {
329 }
else if ((is2Addr && Entry.PredCC2 == 2) ||
330 (!is2Addr && Entry.PredCC1 == 2)) {
350 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD);
351 bool isLROk = (Opc == ARM::t2STMDB_UPD);
352 bool isSPOk = isPCOk || isLROk;
357 unsigned Reg = MO.
getReg();
358 if (Reg == 0 || Reg == ARM::CPSR)
362 if (isLROk && Reg == ARM::LR)
364 if (Reg == ARM::SP) {
367 if (
i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
379 const ReduceEntry &Entry) {
384 bool HasImmOffset =
false;
385 bool HasShift =
false;
386 bool HasOffReg =
true;
387 bool isLdStMul =
false;
388 unsigned Opc = Entry.NarrowOpc1;
390 uint8_t ImmLimit = Entry.Imm1Limit;
392 switch (Entry.WideOpc) {
398 Opc = Entry.NarrowOpc2;
399 ImmLimit = Entry.Imm2Limit;
428 case ARM::t2LDR_POST:
429 case ARM::t2STR_POST: {
440 bool IsStore = Entry.WideOpc == ARM::t2STR_POST;
454 auto MIB =
BuildMI(MBB, MI, dl,
TII->get(Entry.NarrowOpc1))
501 case ARM::t2LDMIA_RET: {
503 if (BaseReg != ARM::SP)
505 Opc = Entry.NarrowOpc2;
510 case ARM::t2LDMIA_UPD:
511 case ARM::t2STMIA_UPD:
512 case ARM::t2STMDB_UPD: {
516 if (BaseReg == ARM::SP &&
517 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
518 Entry.WideOpc == ARM::t2STMDB_UPD)) {
519 Opc = Entry.NarrowOpc2;
522 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
523 Entry.WideOpc != ARM::t2STMIA_UPD)) {
532 unsigned OffsetReg = 0;
533 bool OffsetKill =
false;
534 bool OffsetInternal =
false;
545 unsigned OffsetImm = 0;
548 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
550 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
561 if (Entry.WideOpc == ARM::t2STMIA)
569 MIB.
addImm(OffsetImm / Scale);
571 assert((!HasShift || OffsetReg) &&
"Invalid so_reg load / store address!");
588 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " << *MIB);
597 const ReduceEntry &Entry,
598 bool LiveCPSR,
bool IsSelfLoop) {
600 if (Opc == ARM::t2ADDri) {
604 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
606 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
613 if (Imm & 3 || Imm > 1020)
625 TII->get(ARM::tADDrSPi))
634 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " <<*MIB);
645 return ReduceLoadStore(MBB, MI, Entry);
650 case ARM::t2ADDSrr: {
651 unsigned PredReg = 0;
655 case ARM::t2ADDSri: {
656 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
661 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
673 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
679 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
687 static const ReduceEntry NarrowEntry =
688 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 };
689 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, IsSelfLoop))
691 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
699 const ReduceEntry &Entry,
700 bool LiveCPSR,
bool IsSelfLoop) {
705 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
729 }
else if (Reg0 != Reg1) {
731 unsigned CommOpIdx1 = 1;
732 unsigned CommOpIdx2 = TargetInstrInfo::CommuteAnyOperandIndex;
733 if (!
TII->findCommutedOpIndices(*MI, CommOpIdx1, CommOpIdx2) ||
737 TII->commuteInstruction(*MI,
false, CommOpIdx1, CommOpIdx2);
743 if (Entry.Imm2Limit) {
745 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
756 unsigned PredReg = 0;
758 bool SkipPred =
false;
776 if (!VerifyPredAndCC(MI, Entry,
true, Pred, LiveCPSR, HasCC, CCDead))
782 canAddPseudoFlagDep(MI, IsSelfLoop))
809 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " << *MIB);
818 const ReduceEntry &Entry,
819 bool LiveCPSR,
bool IsSelfLoop) {
823 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
828 unsigned Limit = ~0U;
830 Limit = (1 << Entry.Imm1Limit) - 1;
838 unsigned Reg = MO.
getReg();
839 if (!Reg || Reg == ARM::CPSR)
843 }
else if (MO.
isImm() &&
845 if (((
unsigned)MO.
getImm()) > Limit)
852 unsigned PredReg = 0;
854 bool SkipPred =
false;
871 if (!VerifyPredAndCC(MI, Entry,
false, Pred, LiveCPSR, HasCC, CCDead))
877 canAddPseudoFlagDep(MI, IsSelfLoop))
896 if ((MCID.
getOpcode() == ARM::t2RSBSri ||
905 if (SkipPred && isPred)
920 DEBUG(
errs() <<
"Converted 32-bit: " << *MI <<
" to 16-bit: " << *MIB);
932 if (MO.
getReg() != ARM::CPSR)
940 return HasDef || LiveCPSR;
947 if (MO.
getReg() != ARM::CPSR)
949 assert(LiveCPSR &&
"CPSR liveness tracking is wrong!");
960 bool LiveCPSR,
bool IsSelfLoop) {
963 if (OPI == ReduceOpcodeMap.
end())
965 const ReduceEntry &Entry = ReduceTable[OPI->second];
969 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
972 if (Entry.NarrowOpc2 &&
973 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
977 if (Entry.NarrowOpc1 &&
978 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
985 bool Modified =
false;
988 bool LiveCPSR = MBB.
isLiveIn(ARM::CPSR);
992 HighLatencyCPSR =
false;
996 const MBBInfo &PInfo = BlockInfo[Pred->getNumber()];
997 if (!PInfo.Visited) {
1001 if (PInfo.HighLatencyCPSR) {
1002 HighLatencyCPSR =
true;
1012 for (; MII !=
E; MII = NextMII) {
1013 NextMII = std::next(MII);
1026 bool NextInSameBundle = NextMII !=
E && NextMII->isBundledWithPred();
1028 if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
1034 if (NextInSameBundle && !NextMII->isBundledWithPred())
1035 NextMII->bundleWithPred();
1053 bool DefCPSR =
false;
1058 HighLatencyCPSR =
false;
1060 }
else if (DefCPSR) {
1068 MBBInfo &Info = BlockInfo[MBB.
getNumber()];
1069 Info.HighLatencyCPSR = HighLatencyCPSR;
1070 Info.Visited =
true;
1075 if (PredicateFtor && !PredicateFtor(*MF.
getFunction()))
1079 if (STI->isThumb1Only() || STI->prefers32BitThumb())
1094 bool Modified =
false;
1096 I = RPOT.begin(),
E = RPOT.end(); I !=
E; ++
I)
1097 Modified |= ReduceMBB(**I);
1105 return new Thumb2SizeReduce(std::move(Ftor));
static bool VerifyLowRegs(MachineInstr *MI)
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
instr_iterator instr_begin()
bool isPredicate() const
Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...
instr_iterator instr_end()
STATISTIC(NumFunctions,"Total number of functions")
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
bool hasOptionalDef() const
Set if this instruction has an optional definition, e.g.
Describe properties that are true of each instruction in the target description file.
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getInternalReadRegState(bool B)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static cl::opt< int > ReduceLimit2Addr("t2-reduce-limit2", cl::init(-1), cl::Hidden)
iterator_range< mop_iterator > operands()
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
static const MachineInstrBuilder & AddNoT1CC(const MachineInstrBuilder &MIB)
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
A Use represents the edge between a Value definition and its users.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
static unsigned getAlignment(GlobalVariable *GV)
Function Alias Analysis false
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isDebugValue() const
mmo_iterator memoperands_end() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
bool isOptionalDef() const
Set if this operand is a optional def.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
std::vector< NodeRef >::reverse_iterator rpo_iterator
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
FunctionPass class - This class is used to implement most global optimizations.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
iterator_range< pred_iterator > predecessors()
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
unsigned getOpcode() const
Return the opcode number for this descriptor.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Iterator for intrusive lists based on ilist_node.
static cl::opt< int > ReduceLimit("t2-reduce-limit", cl::init(-1), cl::Hidden)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
static cl::opt< int > ReduceLimitLdSt("t2-reduce-limit3", cl::init(-1), cl::Hidden)
static bool HasImplicitCPSRDef(const MCInstrDesc &MCID)
static bool isHighLatencyCPSR(MachineInstr *Def)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR)
MachineFunctionProperties & set(Property P)
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Representation of each machine instruction.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
bool isCall(QueryType Type=AnyInBundle) const
iterator find(const KeyT &Val)
uint8_t getFlags() const
Return the MI flags bitvector.
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
print Print MemDeps of function
StringRef - Represent a constant reference to a string, i.e.
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
Properties which a MachineFunction may have at a given point in time.
bool isInternalRead() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.