LLVM  4.0.0
AMDGPUDisassembler.h
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1 //===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 ///
12 /// This file contains declaration for AMDGPU ISA disassembler
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17 #define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
18 
19 #include "llvm/ADT/ArrayRef.h"
23 #include <cstdint>
24 #include <algorithm>
25 #include <memory>
26 
27 namespace llvm {
28 
29 class MCContext;
30 class MCInst;
31 class MCOperand;
32 class MCSubtargetInfo;
33 class Twine;
34 
35 //===----------------------------------------------------------------------===//
36 // AMDGPUDisassembler
37 //===----------------------------------------------------------------------===//
38 
40 private:
41  mutable ArrayRef<uint8_t> Bytes;
42 
43 public:
45  MCDisassembler(STI, Ctx) {}
46 
47  ~AMDGPUDisassembler() override = default;
48 
49  DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
50  ArrayRef<uint8_t> Bytes, uint64_t Address,
51  raw_ostream &WS, raw_ostream &CS) const override;
52 
53  const char* getRegClassName(unsigned RegClassID) const;
54 
55  MCOperand createRegOperand(unsigned int RegId) const;
56  MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
57  MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
58 
59  MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
60 
61  DecodeStatus tryDecodeInst(const uint8_t* Table,
62  MCInst &MI,
63  uint64_t Inst,
64  uint64_t Address) const;
65 
66  MCOperand decodeOperand_VGPR_32(unsigned Val) const;
67  MCOperand decodeOperand_VS_32(unsigned Val) const;
68  MCOperand decodeOperand_VS_64(unsigned Val) const;
69  MCOperand decodeOperand_VSrc16(unsigned Val) const;
70 
71  MCOperand decodeOperand_VReg_64(unsigned Val) const;
72  MCOperand decodeOperand_VReg_96(unsigned Val) const;
73  MCOperand decodeOperand_VReg_128(unsigned Val) const;
74 
75  MCOperand decodeOperand_SReg_32(unsigned Val) const;
76  MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
77  MCOperand decodeOperand_SReg_64(unsigned Val) const;
78  MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
79  MCOperand decodeOperand_SReg_128(unsigned Val) const;
80  MCOperand decodeOperand_SReg_256(unsigned Val) const;
81  MCOperand decodeOperand_SReg_512(unsigned Val) const;
82 
83  enum OpWidthTy {
90  };
91 
92  unsigned getVgprClassId(const OpWidthTy Width) const;
93  unsigned getSgprClassId(const OpWidthTy Width) const;
94  unsigned getTtmpClassId(const OpWidthTy Width) const;
95 
96  static MCOperand decodeIntImmed(unsigned Imm);
97  static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
99 
100  MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const;
101  MCOperand decodeSpecialReg32(unsigned Val) const;
102  MCOperand decodeSpecialReg64(unsigned Val) const;
103 };
104 
105 //===----------------------------------------------------------------------===//
106 // AMDGPUSymbolizer
107 //===----------------------------------------------------------------------===//
108 
110 private:
111  void *DisInfo;
112 
113 public:
114  AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
115  void *disInfo)
116  : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
117 
118  bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
119  int64_t Value, uint64_t Address,
120  bool IsBranch, uint64_t Offset,
121  uint64_t InstSize) override;
122 
124  int64_t Value,
125  uint64_t Address) override;
126 };
127 
128 } // end namespace llvm
129 
130 #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
~AMDGPUDisassembler() override=default
std::unique_ptr< MCRelocationInfo > RelInfo
Definition: MCSymbolizer.h:46
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Superclass for all disassemblers.
MCContext & Ctx
Definition: MCSymbolizer.h:45
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeOperand_VS_64(unsigned Val) const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
MCOperand decodeOperand_VReg_96(unsigned Val) const
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Context object for machine code objects.
Definition: MCContext.h:51
const MCSubtargetInfo & STI
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeSpecialReg32(unsigned Val) const
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
MCOperand decodeOperand_SReg_512(unsigned Val) const
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:40
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
MCOperand decodeOperand_SReg_128(unsigned Val) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
uint32_t Offset
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeOperand_VSrc16(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
MCOperand decodeOperand_VReg_128(unsigned Val) const
static MCOperand decodeIntImmed(unsigned Imm)
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
MCOperand decodeSpecialReg64(unsigned Val) const
MCSubtargetInfo - Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
unsigned getVgprClassId(const OpWidthTy Width) const
LLVM Value Representation.
Definition: Value.h:71
MCOperand decodeOperand_SReg_64(unsigned Val) const
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
MCOperand decodeLiteralConstant() const
IRTranslator LLVM IR MI
MCOperand decodeOperand_SReg_256(unsigned Val) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33