LLVM  4.0.0
MachineCSE.cpp
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1 //===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass performs global common subexpression elimination on machine
11 // instructions using a scoped hash table based value numbering scheme. It
12 // must be run while the machine function is still in SSA form.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Support/Debug.h"
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "machine-cse"
33 
34 STATISTIC(NumCoalesces, "Number of copies coalesced");
35 STATISTIC(NumCSEs, "Number of common subexpression eliminated");
36 STATISTIC(NumPhysCSEs,
37  "Number of physreg referencing common subexpr eliminated");
38 STATISTIC(NumCrossBBCSEs,
39  "Number of cross-MBB physreg referencing CS eliminated");
40 STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
41 
42 namespace {
43  class MachineCSE : public MachineFunctionPass {
44  const TargetInstrInfo *TII;
45  const TargetRegisterInfo *TRI;
46  AliasAnalysis *AA;
49  public:
50  static char ID; // Pass identification
51  MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(0), CurrVN(0) {
53  }
54 
55  bool runOnMachineFunction(MachineFunction &MF) override;
56 
57  void getAnalysisUsage(AnalysisUsage &AU) const override {
58  AU.setPreservesCFG();
64  }
65 
66  void releaseMemory() override {
67  ScopeMap.clear();
68  Exps.clear();
69  }
70 
71  private:
72  unsigned LookAheadLimit;
76  MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
77  typedef ScopedHTType::ScopeTy ScopeType;
79  ScopedHTType VNT;
81  unsigned CurrVN;
82 
83  bool PerformTrivialCopyPropagation(MachineInstr *MI,
85  bool isPhysDefTriviallyDead(unsigned Reg,
88  bool hasLivePhysRegDefUses(const MachineInstr *MI,
89  const MachineBasicBlock *MBB,
90  SmallSet<unsigned,8> &PhysRefs,
91  SmallVectorImpl<unsigned> &PhysDefs,
92  bool &PhysUseDef) const;
93  bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
94  SmallSet<unsigned,8> &PhysRefs,
95  SmallVectorImpl<unsigned> &PhysDefs,
96  bool &NonLocal) const;
97  bool isCSECandidate(MachineInstr *MI);
98  bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
99  MachineInstr *CSMI, MachineInstr *MI);
100  void EnterScope(MachineBasicBlock *MBB);
101  void ExitScope(MachineBasicBlock *MBB);
103  void ExitScopeIfDone(MachineDomTreeNode *Node,
105  bool PerformCSE(MachineDomTreeNode *Node);
106  };
107 } // end anonymous namespace
108 
109 char MachineCSE::ID = 0;
111 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
112  "Machine Common Subexpression Elimination", false, false)
115 INITIALIZE_PASS_END(MachineCSE, "machine-cse",
116  "Machine Common Subexpression Elimination", false, false)
117 
118 /// The source register of a COPY machine instruction can be propagated to all
119 /// its users, and this propagation could increase the probability of finding
120 /// common subexpressions. If the COPY has only one user, the COPY itself can
121 /// be removed.
122 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
124  bool Changed = false;
125  for (MachineOperand &MO : MI->operands()) {
126  if (!MO.isReg() || !MO.isUse())
127  continue;
128  unsigned Reg = MO.getReg();
130  continue;
131  bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
132  MachineInstr *DefMI = MRI->getVRegDef(Reg);
133  if (!DefMI->isCopy())
134  continue;
135  unsigned SrcReg = DefMI->getOperand(1).getReg();
137  continue;
138  if (DefMI->getOperand(0).getSubReg())
139  continue;
140  // FIXME: We should trivially coalesce subregister copies to expose CSE
141  // opportunities on instructions with truncated operands (see
142  // cse-add-with-overflow.ll). This can be done here as follows:
143  // if (SrcSubReg)
144  // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
145  // SrcSubReg);
146  // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
147  //
148  // The 2-addr pass has been updated to handle coalesced subregs. However,
149  // some machine-specific code still can't handle it.
150  // To handle it properly we also need a way find a constrained subregister
151  // class given a super-reg class and subreg index.
152  if (DefMI->getOperand(1).getSubReg())
153  continue;
154  const TargetRegisterClass *RC = MRI->getRegClass(Reg);
155  if (!MRI->constrainRegClass(SrcReg, RC))
156  continue;
157  DEBUG(dbgs() << "Coalescing: " << *DefMI);
158  DEBUG(dbgs() << "*** to: " << *MI);
159  // Propagate SrcReg of copies to MI.
160  MO.setReg(SrcReg);
161  MRI->clearKillFlags(SrcReg);
162  // Coalesce single use copies.
163  if (OnlyOneUse) {
164  DefMI->eraseFromParent();
165  ++NumCoalesces;
166  }
167  Changed = true;
168  }
169 
170  return Changed;
171 }
172 
173 bool
174 MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
177  unsigned LookAheadLeft = LookAheadLimit;
178  while (LookAheadLeft) {
179  // Skip over dbg_value's.
181 
182  if (I == E)
183  // Reached end of block, register is obviously dead.
184  return true;
185 
186  bool SeenDef = false;
187  for (const MachineOperand &MO : I->operands()) {
188  if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
189  SeenDef = true;
190  if (!MO.isReg() || !MO.getReg())
191  continue;
192  if (!TRI->regsOverlap(MO.getReg(), Reg))
193  continue;
194  if (MO.isUse())
195  // Found a use!
196  return false;
197  SeenDef = true;
198  }
199  if (SeenDef)
200  // See a def of Reg (or an alias) before encountering any use, it's
201  // trivially dead.
202  return true;
203 
204  --LookAheadLeft;
205  ++I;
206  }
207  return false;
208 }
209 
210 /// hasLivePhysRegDefUses - Return true if the specified instruction read/write
211 /// physical registers (except for dead defs of physical registers). It also
212 /// returns the physical register def by reference if it's the only one and the
213 /// instruction does not uses a physical register.
214 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
215  const MachineBasicBlock *MBB,
216  SmallSet<unsigned,8> &PhysRefs,
217  SmallVectorImpl<unsigned> &PhysDefs,
218  bool &PhysUseDef) const{
219  // First, add all uses to PhysRefs.
220  for (const MachineOperand &MO : MI->operands()) {
221  if (!MO.isReg() || MO.isDef())
222  continue;
223  unsigned Reg = MO.getReg();
224  if (!Reg)
225  continue;
227  continue;
228  // Reading constant physregs is ok.
229  if (!MRI->isConstantPhysReg(Reg))
230  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
231  PhysRefs.insert(*AI);
232  }
233 
234  // Next, collect all defs into PhysDefs. If any is already in PhysRefs
235  // (which currently contains only uses), set the PhysUseDef flag.
236  PhysUseDef = false;
237  MachineBasicBlock::const_iterator I = MI; I = std::next(I);
238  for (const MachineOperand &MO : MI->operands()) {
239  if (!MO.isReg() || !MO.isDef())
240  continue;
241  unsigned Reg = MO.getReg();
242  if (!Reg)
243  continue;
245  continue;
246  // Check against PhysRefs even if the def is "dead".
247  if (PhysRefs.count(Reg))
248  PhysUseDef = true;
249  // If the def is dead, it's ok. But the def may not marked "dead". That's
250  // common since this pass is run before livevariables. We can scan
251  // forward a few instructions and check if it is obviously dead.
252  if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
253  PhysDefs.push_back(Reg);
254  }
255 
256  // Finally, add all defs to PhysRefs as well.
257  for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
258  for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
259  PhysRefs.insert(*AI);
260 
261  return !PhysRefs.empty();
262 }
263 
264 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
265  SmallSet<unsigned,8> &PhysRefs,
266  SmallVectorImpl<unsigned> &PhysDefs,
267  bool &NonLocal) const {
268  // For now conservatively returns false if the common subexpression is
269  // not in the same basic block as the given instruction. The only exception
270  // is if the common subexpression is in the sole predecessor block.
271  const MachineBasicBlock *MBB = MI->getParent();
272  const MachineBasicBlock *CSMBB = CSMI->getParent();
273 
274  bool CrossMBB = false;
275  if (CSMBB != MBB) {
276  if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
277  return false;
278 
279  for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
280  if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
281  // Avoid extending live range of physical registers if they are
282  //allocatable or reserved.
283  return false;
284  }
285  CrossMBB = true;
286  }
287  MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
290  unsigned LookAheadLeft = LookAheadLimit;
291  while (LookAheadLeft) {
292  // Skip over dbg_value's.
293  while (I != E && I != EE && I->isDebugValue())
294  ++I;
295 
296  if (I == EE) {
297  assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
298  (void)CrossMBB;
299  CrossMBB = false;
300  NonLocal = true;
301  I = MBB->begin();
302  EE = MBB->end();
303  continue;
304  }
305 
306  if (I == E)
307  return true;
308 
309  for (const MachineOperand &MO : I->operands()) {
310  // RegMasks go on instructions like calls that clobber lots of physregs.
311  // Don't attempt to CSE across such an instruction.
312  if (MO.isRegMask())
313  return false;
314  if (!MO.isReg() || !MO.isDef())
315  continue;
316  unsigned MOReg = MO.getReg();
318  continue;
319  if (PhysRefs.count(MOReg))
320  return false;
321  }
322 
323  --LookAheadLeft;
324  ++I;
325  }
326 
327  return false;
328 }
329 
330 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
331  if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
332  MI->isInlineAsm() || MI->isDebugValue())
333  return false;
334 
335  // Ignore copies.
336  if (MI->isCopyLike())
337  return false;
338 
339  // Ignore stuff that we obviously can't move.
340  if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
342  return false;
343 
344  if (MI->mayLoad()) {
345  // Okay, this instruction does a load. As a refinement, we allow the target
346  // to decide whether the loaded value is actually a constant. If so, we can
347  // actually use it as a load.
348  if (!MI->isDereferenceableInvariantLoad(AA))
349  // FIXME: we should be able to hoist loads with no other side effects if
350  // there are no other instructions which can change memory in this loop.
351  // This is a trivial form of alias analysis.
352  return false;
353  }
354 
355  // Ignore stack guard loads, otherwise the register that holds CSEed value may
356  // be spilled and get loaded back with corrupted data.
357  if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD)
358  return false;
359 
360  return true;
361 }
362 
363 /// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
364 /// common expression that defines Reg.
365 bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
366  MachineInstr *CSMI, MachineInstr *MI) {
367  // FIXME: Heuristics that works around the lack the live range splitting.
368 
369  // If CSReg is used at all uses of Reg, CSE should not increase register
370  // pressure of CSReg.
371  bool MayIncreasePressure = true;
374  MayIncreasePressure = false;
376  for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
377  CSUses.insert(&MI);
378  }
379  for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
380  if (!CSUses.count(&MI)) {
381  MayIncreasePressure = true;
382  break;
383  }
384  }
385  }
386  if (!MayIncreasePressure) return true;
387 
388  // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
389  // an immediate predecessor. We don't want to increase register pressure and
390  // end up causing other computation to be spilled.
391  if (TII->isAsCheapAsAMove(*MI)) {
392  MachineBasicBlock *CSBB = CSMI->getParent();
393  MachineBasicBlock *BB = MI->getParent();
394  if (CSBB != BB && !CSBB->isSuccessor(BB))
395  return false;
396  }
397 
398  // Heuristics #2: If the expression doesn't not use a vr and the only use
399  // of the redundant computation are copies, do not cse.
400  bool HasVRegUse = false;
401  for (const MachineOperand &MO : MI->operands()) {
402  if (MO.isReg() && MO.isUse() &&
404  HasVRegUse = true;
405  break;
406  }
407  }
408  if (!HasVRegUse) {
409  bool HasNonCopyUse = false;
410  for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
411  // Ignore copies.
412  if (!MI.isCopyLike()) {
413  HasNonCopyUse = true;
414  break;
415  }
416  }
417  if (!HasNonCopyUse)
418  return false;
419  }
420 
421  // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
422  // it unless the defined value is already used in the BB of the new use.
423  bool HasPHI = false;
425  for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
426  HasPHI |= MI.isPHI();
427  CSBBs.insert(MI.getParent());
428  }
429 
430  if (!HasPHI)
431  return true;
432  return CSBBs.count(MI->getParent());
433 }
434 
435 void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
436  DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
437  ScopeType *Scope = new ScopeType(VNT);
438  ScopeMap[MBB] = Scope;
439 }
440 
441 void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
442  DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
444  assert(SI != ScopeMap.end());
445  delete SI->second;
446  ScopeMap.erase(SI);
447 }
448 
450  bool Changed = false;
451 
453  SmallVector<unsigned, 2> ImplicitDefsToUpdate;
454  SmallVector<unsigned, 2> ImplicitDefs;
455  for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
456  MachineInstr *MI = &*I;
457  ++I;
458 
459  if (!isCSECandidate(MI))
460  continue;
461 
462  bool FoundCSE = VNT.count(MI);
463  if (!FoundCSE) {
464  // Using trivial copy propagation to find more CSE opportunities.
465  if (PerformTrivialCopyPropagation(MI, MBB)) {
466  Changed = true;
467 
468  // After coalescing MI itself may become a copy.
469  if (MI->isCopyLike())
470  continue;
471 
472  // Try again to see if CSE is possible.
473  FoundCSE = VNT.count(MI);
474  }
475  }
476 
477  // Commute commutable instructions.
478  bool Commuted = false;
479  if (!FoundCSE && MI->isCommutable()) {
480  if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
481  Commuted = true;
482  FoundCSE = VNT.count(NewMI);
483  if (NewMI != MI) {
484  // New instruction. It doesn't need to be kept.
485  NewMI->eraseFromParent();
486  Changed = true;
487  } else if (!FoundCSE)
488  // MI was changed but it didn't help, commute it back!
489  (void)TII->commuteInstruction(*MI);
490  }
491  }
492 
493  // If the instruction defines physical registers and the values *may* be
494  // used, then it's not safe to replace it with a common subexpression.
495  // It's also not safe if the instruction uses physical registers.
496  bool CrossMBBPhysDef = false;
497  SmallSet<unsigned, 8> PhysRefs;
498  SmallVector<unsigned, 2> PhysDefs;
499  bool PhysUseDef = false;
500  if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
501  PhysDefs, PhysUseDef)) {
502  FoundCSE = false;
503 
504  // ... Unless the CS is local or is in the sole predecessor block
505  // and it also defines the physical register which is not clobbered
506  // in between and the physical register uses were not clobbered.
507  // This can never be the case if the instruction both uses and
508  // defines the same physical register, which was detected above.
509  if (!PhysUseDef) {
510  unsigned CSVN = VNT.lookup(MI);
511  MachineInstr *CSMI = Exps[CSVN];
512  if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
513  FoundCSE = true;
514  }
515  }
516 
517  if (!FoundCSE) {
518  VNT.insert(MI, CurrVN++);
519  Exps.push_back(MI);
520  continue;
521  }
522 
523  // Found a common subexpression, eliminate it.
524  unsigned CSVN = VNT.lookup(MI);
525  MachineInstr *CSMI = Exps[CSVN];
526  DEBUG(dbgs() << "Examining: " << *MI);
527  DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
528 
529  // Check if it's profitable to perform this CSE.
530  bool DoCSE = true;
531  unsigned NumDefs = MI->getDesc().getNumDefs() +
532  MI->getDesc().getNumImplicitDefs();
533 
534  for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
535  MachineOperand &MO = MI->getOperand(i);
536  if (!MO.isReg() || !MO.isDef())
537  continue;
538  unsigned OldReg = MO.getReg();
539  unsigned NewReg = CSMI->getOperand(i).getReg();
540 
541  // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
542  // we should make sure it is not dead at CSMI.
543  if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
544  ImplicitDefsToUpdate.push_back(i);
545 
546  // Keep track of implicit defs of CSMI and MI, to clear possibly
547  // made-redundant kill flags.
548  if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
549  ImplicitDefs.push_back(OldReg);
550 
551  if (OldReg == NewReg) {
552  --NumDefs;
553  continue;
554  }
555 
558  "Do not CSE physical register defs!");
559 
560  if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
561  DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
562  DoCSE = false;
563  break;
564  }
565 
566  // Don't perform CSE if the result of the old instruction cannot exist
567  // within the register class of the new instruction.
568  const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
569  if (!MRI->constrainRegClass(NewReg, OldRC)) {
570  DEBUG(dbgs() << "*** Not the same register class, avoid CSE!\n");
571  DoCSE = false;
572  break;
573  }
574 
575  CSEPairs.push_back(std::make_pair(OldReg, NewReg));
576  --NumDefs;
577  }
578 
579  // Actually perform the elimination.
580  if (DoCSE) {
581  for (std::pair<unsigned, unsigned> &CSEPair : CSEPairs) {
582  unsigned OldReg = CSEPair.first;
583  unsigned NewReg = CSEPair.second;
584  // OldReg may have been unused but is used now, clear the Dead flag
585  MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
586  assert(Def != nullptr && "CSEd register has no unique definition?");
587  Def->clearRegisterDeads(NewReg);
588  // Replace with NewReg and clear kill flags which may be wrong now.
589  MRI->replaceRegWith(OldReg, NewReg);
590  MRI->clearKillFlags(NewReg);
591  }
592 
593  // Go through implicit defs of CSMI and MI, if a def is not dead at MI,
594  // we should make sure it is not dead at CSMI.
595  for (unsigned ImplicitDefToUpdate : ImplicitDefsToUpdate)
596  CSMI->getOperand(ImplicitDefToUpdate).setIsDead(false);
597 
598  // Go through implicit defs of CSMI and MI, and clear the kill flags on
599  // their uses in all the instructions between CSMI and MI.
600  // We might have made some of the kill flags redundant, consider:
601  // subs ... %NZCV<imp-def> <- CSMI
602  // csinc ... %NZCV<imp-use,kill> <- this kill flag isn't valid anymore
603  // subs ... %NZCV<imp-def> <- MI, to be eliminated
604  // csinc ... %NZCV<imp-use,kill>
605  // Since we eliminated MI, and reused a register imp-def'd by CSMI
606  // (here %NZCV), that register, if it was killed before MI, should have
607  // that kill flag removed, because it's lifetime was extended.
608  if (CSMI->getParent() == MI->getParent()) {
609  for (MachineBasicBlock::iterator II = CSMI, IE = MI; II != IE; ++II)
610  for (auto ImplicitDef : ImplicitDefs)
611  if (MachineOperand *MO = II->findRegisterUseOperand(
612  ImplicitDef, /*isKill=*/true, TRI))
613  MO->setIsKill(false);
614  } else {
615  // If the instructions aren't in the same BB, bail out and clear the
616  // kill flag on all uses of the imp-def'd register.
617  for (auto ImplicitDef : ImplicitDefs)
618  MRI->clearKillFlags(ImplicitDef);
619  }
620 
621  if (CrossMBBPhysDef) {
622  // Add physical register defs now coming in from a predecessor to MBB
623  // livein list.
624  while (!PhysDefs.empty()) {
625  unsigned LiveIn = PhysDefs.pop_back_val();
626  if (!MBB->isLiveIn(LiveIn))
627  MBB->addLiveIn(LiveIn);
628  }
629  ++NumCrossBBCSEs;
630  }
631 
632  MI->eraseFromParent();
633  ++NumCSEs;
634  if (!PhysRefs.empty())
635  ++NumPhysCSEs;
636  if (Commuted)
637  ++NumCommutes;
638  Changed = true;
639  } else {
640  VNT.insert(MI, CurrVN++);
641  Exps.push_back(MI);
642  }
643  CSEPairs.clear();
644  ImplicitDefsToUpdate.clear();
645  ImplicitDefs.clear();
646  }
647 
648  return Changed;
649 }
650 
651 /// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
652 /// dominator tree node if its a leaf or all of its children are done. Walk
653 /// up the dominator tree to destroy ancestors which are now done.
654 void
655 MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
657  if (OpenChildren[Node])
658  return;
659 
660  // Pop scope.
661  ExitScope(Node->getBlock());
662 
663  // Now traverse upwards to pop ancestors whose offsprings are all done.
664  while (MachineDomTreeNode *Parent = Node->getIDom()) {
665  unsigned Left = --OpenChildren[Parent];
666  if (Left != 0)
667  break;
668  ExitScope(Parent->getBlock());
669  Node = Parent;
670  }
671 }
672 
673 bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
677 
678  CurrVN = 0;
679 
680  // Perform a DFS walk to determine the order of visit.
681  WorkList.push_back(Node);
682  do {
683  Node = WorkList.pop_back_val();
684  Scopes.push_back(Node);
685  const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
686  OpenChildren[Node] = Children.size();
687  for (MachineDomTreeNode *Child : Children)
688  WorkList.push_back(Child);
689  } while (!WorkList.empty());
690 
691  // Now perform CSE.
692  bool Changed = false;
693  for (MachineDomTreeNode *Node : Scopes) {
694  MachineBasicBlock *MBB = Node->getBlock();
695  EnterScope(MBB);
696  Changed |= ProcessBlock(MBB);
697  // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
698  ExitScopeIfDone(Node, OpenChildren);
699  }
700 
701  return Changed;
702 }
703 
704 bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
705  if (skipFunction(*MF.getFunction()))
706  return false;
707 
708  TII = MF.getSubtarget().getInstrInfo();
709  TRI = MF.getSubtarget().getRegisterInfo();
710  MRI = &MF.getRegInfo();
711  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
712  DT = &getAnalysis<MachineDominatorTree>();
713  LookAheadLimit = TII->getMachineCSELookAheadLimit();
714  return PerformCSE(DT->getRootNode());
715 }
bool isImplicit() const
void push_back(const T &Elt)
Definition: SmallVector.h:211
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const std::vector< DomTreeNodeBase< NodeT > * > & getChildren() const
STATISTIC(NumFunctions,"Total number of functions")
size_t i
unsigned getNumImplicitDefs() const
Return the number of implicit defs this instruct has.
Definition: MCInstrDesc.h:528
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
void initializeMachineCSEPass(PassRegistry &)
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
size_type count(PtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:380
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
DomTreeNodeBase< NodeT > * getIDom() const
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
LLVM_NODISCARD bool empty() const
Definition: SmallSet.h:55
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:786
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
Reg
All possible values of the reg field in the ModR/M byte.
RecyclingAllocator - This class wraps an Allocator, adding the functionality of recycling deleted obj...
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:110
machine cse
Definition: MachineCSE.cpp:115
MachineBasicBlock * MBB
Base class for the actual dominator tree node.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:819
AnalysisUsage & addPreservedID(const void *ID)
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:303
static bool ProcessBlock(BasicBlock &BB, DominatorTree &DT, LoopInfo &LI, AAResults &AA)
Definition: Sink.cpp:200
NodeT * getBlock() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:777
bool isImplicitDef() const
Definition: MachineInstr.h:788
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template paramaters.
Definition: Allocator.h:361
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
machine Machine Common Subexpression Elimination
Definition: MachineCSE.cpp:115
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:368
bool isCopy() const
Definition: MachineInstr.h:807
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
bool isPosition() const
Definition: MachineInstr.h:775
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:80
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void setIsKill(bool Val=true)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:64
machine Machine Common Subexpression false
Definition: MachineCSE.cpp:115
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool isInlineAsm() const
Definition: MachineInstr.h:789
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:382
bool isKill() const
Definition: MachineInstr.h:787
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
StringRef getName() const
Return the name of the corresponding LLVM basic block, or "(null)".
IterT skipDebugInstructionsForward(IterT It, IterT End)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:633
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
INITIALIZE_PASS_BEGIN(MachineCSE,"machine-cse","Machine Common Subexpression Elimination", false, false) INITIALIZE_PASS_END(MachineCSE
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
unsigned pred_size() const