16 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
31 enum BranchPredicate {
41 static unsigned getBranchOpcode(BranchPredicate Cond);
42 static BranchPredicate getBranchPredicate(
unsigned Opcode);
73 void addUsersToMoveToVALUWorklist(
82 getDestEquivalentVGPRClass(
const MachineInstr &Inst)
const;
86 unsigned findUsedSGPR(
const MachineInstr &MI,
int OpIndices[3])
const;
95 unsigned OpIdx1)
const override;
126 int64_t &Offset2)
const override;
133 unsigned NumLoads)
const final;
136 const DebugLoc &DL,
unsigned DestReg,
unsigned SrcReg,
137 bool KillSrc)
const override;
141 unsigned Offset,
unsigned Size)
const;
170 unsigned &SrcOpIdx2)
const override;
173 int64_t BrOffset)
const override;
188 bool AllowModify)
const;
193 bool AllowModify)
const override;
196 int *BytesRemoved =
nullptr)
const override;
201 int *BytesAdded =
nullptr)
const override;
347 bool isDS(uint16_t Opcode)
const {
466 switch (OperandType) {
524 assert(Size == 8 || Size == 4);
526 uint8_t OpType = (Size == 8) ?
573 unsigned OpName)
const;
588 unsigned OpNo)
const;
592 unsigned getOpSize(uint16_t Opcode,
unsigned OpNo)
const {
601 return RI.getRegClass(OpInfo.
RegClass)->getSize();
691 unsigned OpName)
const {
774 namespace KernelInputOffsets {
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isScalarStore(uint16_t Opcode) const
static bool isSGPRSpill(const MachineInstr &MI)
Interface definition for SIRegisterInfo.
bool isVMEM(uint16_t Opcode) const
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static bool isScalarStore(const MachineInstr &MI)
static bool sopkIsZext(const MachineInstr &MI)
unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Describe properties that are true of each instruction in the target description file.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isSOPP(uint16_t Opcode) const
void moveToVALU(MachineInstr &MI) const
Replace this instruction's opcode with the equivalent VALU opcode.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
static bool isSOPK(const MachineInstr &MI)
bool isSALU(uint16_t Opcode) const
bool isSOP2(uint16_t Opcode) const
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isFixedSize(uint16_t Opcode) const
bool isGather4(uint16_t Opcode) const
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
static bool isSOPP(const MachineInstr &MI)
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool isSOPC(const MachineInstr &MI)
bool isFLAT(uint16_t Opcode) const
static bool isSMRD(const MachineInstr &MI)
static int operandBitWidth(uint8_t OperandType)
LLVM_READONLY int getVOPe64(uint16_t Opcode)
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
static bool isFixedSize(const MachineInstr &MI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
static bool isDS(const MachineInstr &MI)
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
LLVM_READONLY int getAtomicRetOp(uint16_t Opcode)
static bool isFLAT(const MachineInstr &MI)
void insertWaitStates(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
static bool isGather4(const MachineInstr &MI)
bool isVALU(uint16_t Opcode) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static bool isMIMG(const MachineInstr &MI)
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Reg
All possible values of the reg field in the ModR/M byte.
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
static bool isVALU(const MachineInstr &MI)
uint8_t OperandType
Information about the type of the operand.
bool sopkIsZext(uint16_t Opcode) const
LLVM_READONLY int commuteOpcode(unsigned Opc) const
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes...
static bool isMUBUF(const MachineInstr &MI)
bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const
uint64_t getScratchRsrcWords23() const
const uint64_t RSRC_DATA_FORMAT
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
Itinerary data supplied by a subtarget to be used by a target.
bool isInlineConstant(const MachineOperand &MO) const
bool isVOP3(uint16_t Opcode) const
bool isSMRD(uint16_t Opcode) const
const SIRegisterInfo & getRegisterInfo() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned short NumOperands
const MachineBasicBlock * getParent() const
static bool isDPP(const MachineInstr &MI)
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const final
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
unsigned const MachineRegisterInfo * MRI
static bool usesVM_CNT(const MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
MachineInstrBuilder & UseMI
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
const MachineOperand & getOperand(unsigned i) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isSOPK(uint16_t Opcode) const
bool isSGPRSpill(uint16_t Opcode) const
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
static bool isSOP2(const MachineInstr &MI)
uint64_t getDefaultRsrcDataFormat() const
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
static bool isVOP2(const MachineInstr &MI)
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isHighLatencyInstruction(const MachineInstr &MI) const
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Operands with register or inline constant.
SIInstrInfo(const SISubtarget &)
const uint64_t RSRC_TID_ENABLE
bool isVOP1(uint16_t Opcode) const
static bool isWQM(const MachineInstr &MI)
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
static bool isEXP(const MachineInstr &MI)
bool isInlineConstant(const APInt &Imm) const
Iterator for intrusive lists based on ilist_node.
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
bool isWQM(uint16_t Opcode) const
LLVM_READONLY int getVOPe32(uint16_t Opcode)
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
bool isDisableWQM(uint16_t Opcode) const
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isSALU(const MachineInstr &MI)
MachineOperand class - Representation of each machine instruction operand.
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
bool isMIMG(uint16_t Opcode) const
const uint64_t RSRC_INDEX_STRIDE_SHIFT
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
Represents one node in the SelectionDAG.
bool isDS(uint16_t Opcode) const
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
bool isVOP2(uint16_t Opcode) const
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
bool isSOP1(uint16_t Opcode) const
Class for arbitrary precision integers.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isVOP3(const MachineInstr &MI)
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isEXP(uint16_t Opcode) const
bool shouldClusterMemOps(MachineInstr &FirstLdSt, MachineInstr &SecondLdSt, unsigned NumLoads) const final
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
Representation of each machine instruction.
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
bool isVGPRCopy(const MachineInstr &MI) const
bool isVGPRSpill(uint16_t Opcode) const
static bool isMTBUF(const MachineInstr &MI)
OperandType
Types of operands to CF instructions.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
bool isMTBUF(uint16_t Opcode) const
static bool isVOPC(const MachineInstr &MI)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
unsigned getNumWaitStates(const MachineInstr &MI) const
Return the number of wait states that result from executing this instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
static bool isVMEM(const MachineInstr &MI)
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool isLowLatencyInstruction(const MachineInstr &MI) const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
static unsigned getVALUOp(const MachineInstr &MI)
Operands with register or 32-bit immediate.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
bool isSOPC(uint16_t Opcode) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSOP1(const MachineInstr &MI)
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
static bool isScalarUnit(const MachineInstr &MI)
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
static bool isVGPRSpill(const MachineInstr &MI)
unsigned getMachineCSELookAheadLimit() const override
const MCOperandInfo * OpInfo
bool isVOPC(uint16_t Opcode) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
bool isDPP(uint16_t Opcode) const
void legalizeOperands(MachineInstr &MI) const
Legalize all operands in this instruction.
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
StringRef - Represent a constant reference to a string, i.e.
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
This holds information about one operand of a machine instruction, indicating the register class for ...
static bool isVOP1(const MachineInstr &MI)
bool isMUBUF(uint16_t Opcode) const
static bool isDisableWQM(const MachineInstr &MI)
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
LLVM_READONLY int getCommuteRev(uint16_t Opcode)