28 void MachineRegisterInfo::Delegate::anchor() {}
31 : MF(MF), TheDelegate(nullptr),
32 TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
36 RegAllocHints.reserve(256);
37 UsedPhysRegMask.
resize(NumRegs);
57 unsigned MinNumRegs) {
63 if (!NewRC || NewRC == OldRC)
89 if (!NewRC || NewRC == OldRC)
99 RegAllocHints.grow(Reg);
108 assert(RegClass &&
"Cannot create register without RegClass!");
110 "Virtual register RegClass must be allocatable.");
129 "Can't set the size of a non-generic virtual register");
161 for (
auto &
I : LiveIns)
173 <<
" use list MachineOperand " << MO
174 <<
" has no parent instruction.\n";
180 if (!(MO >= MO0 && MO < MO0+NumOps)) {
182 <<
" use list MachineOperand " << MO
183 <<
" doesn't belong to parent MI: " << *
MI;
188 <<
" MachineOperand " << MO <<
": " << *MO
189 <<
" is not a register\n";
194 <<
" use-list MachineOperand " << MO <<
": "
195 << *MO <<
" is the wrong register\n";
199 assert(Valid &&
"Invalid use list");
214 assert(!MO->isOnRegUseList() &&
"Already on list");
224 MO->Contents.
Reg.Prev = MO;
225 MO->Contents.
Reg.Next =
nullptr;
229 assert(MO->
getReg() == Head->getReg() &&
"Different regs on the same list!");
233 assert(Last &&
"Inconsistent use list");
234 assert(MO->
getReg() == Last->getReg() &&
"Different regs on the same list!");
235 Head->Contents.Reg.Prev = MO;
236 MO->Contents.
Reg.Prev = Last;
242 MO->Contents.
Reg.Next = Head;
246 MO->Contents.
Reg.Next =
nullptr;
247 Last->Contents.Reg.Next = MO;
253 assert(MO->isOnRegUseList() &&
"Operand not on use list");
256 assert(Head &&
"List already empty");
266 Prev->Contents.
Reg.Next = Next;
268 (Next ? Next : Head)->Contents.
Reg.Prev = Prev;
270 MO->Contents.
Reg.Prev =
nullptr;
271 MO->Contents.
Reg.Next =
nullptr;
284 assert(Src != Dst && NumOps &&
"Noop moveOperands");
288 if (Dst >= Src && Dst < Src + NumOps) {
303 assert(Head &&
"List empty, but operand is chained");
304 assert(Prev &&
"Operand was not on use-def list");
311 Prev->Contents.
Reg.Next = Dst;
315 (Next ? Next : Head)->Contents.
Reg.Prev = Dst;
329 assert(FromReg != ToReg &&
"Cannot replace a reg with itself");
352 "getVRegDef assumes a single definition or no definition");
353 return !I.
atEnd() ? &*I :
nullptr;
385 if (
I->first == Reg ||
I->second == Reg)
394 if (
I->second == VReg)
403 if (
I->first == PReg)
415 for (
unsigned i = 0, e = LiveIns.size();
i != e; ++
i)
416 if (LiveIns[
i].second) {
423 LiveIns.erase(LiveIns.begin() +
i);
428 TII.
get(TargetOpcode::COPY), LiveIns[
i].second)
429 .addReg(LiveIns[
i].first);
457 "Invalid ReservedRegs vector from target");
484 nextI = std::next(
I);
516 return !(Called ==
nullptr || !Called->
hasFnAttribute(Attribute::NoReturn) ||
521 bool SkipNoReturnDef)
const {
522 if (UsedPhysRegMask.
test(PhysReg))
536 if (UsedPhysRegMask.
test(PhysReg))
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)
EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block...
size_type size() const
size - Returns the number of bits in this bitvector.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
void removeRegOperandFromUseList(MachineOperand *MO)
Remove MO from its use-def list.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
livein_iterator livein_end() const
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
iterator_range< use_iterator > use_operands(unsigned Reg) const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator_range< reg_iterator > reg_operands(unsigned Reg) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
iterator_range< mop_iterator > operands()
void markUsesInDebugValueAsUndef(unsigned Reg) const
markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...
static use_nodbg_iterator use_nodbg_end()
void clearVirtRegs()
clearVirtRegs - Remove all virtual registers (after physreg assignment).
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
VRegToTypeMap & getVRegToType() const
Accessor for VRegToType.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool isPhysRegUsed(unsigned PhysReg) const
Return true if the specified register is modified or read in this function.
const HexagonInstrInfo * TII
const TargetRegisterInfo * getTargetRegisterInfo() const
use_instr_iterator use_instr_begin(unsigned RegNo) const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
Reg
All possible values of the reg field in the ModR/M byte.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
defusechain_iterator - This class provides iterator support for machine operands in the function that...
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
bool isLiveIn(unsigned Reg) const
static def_instr_iterator def_instr_end()
struct llvm::MachineOperand::@38::@39 Reg
bool atEnd() const
atEnd - return true if this iterator is equal to reg_end() on the value.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
void setType(unsigned VReg, LLT Ty)
Set the low-level type of VReg to Ty.
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned createIncompleteVirtualRegister()
Creates a new virtual register that has no register class, register bank or size assigned yet...
void substPhysReg(unsigned Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
iterator_range< use_instr_iterator > use_instructions(unsigned Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const Function * getCalledFunction(const MachineInstr &MI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
MachineOperand class - Representation of each machine instruction operand.
bool test(unsigned Idx) const
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
livein_iterator livein_begin() const
This class implements the register bank concept.
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
unsigned getNumRegs() const
Return the number of registers in this class.
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
def_iterator def_begin(unsigned RegNo) const
void verifyUseList(unsigned Reg) const
Verify the sanity of the use list for Reg.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
def_instr_iterator def_instr_begin(unsigned RegNo) const
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
iterator find(const KeyT &Val)
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
unsigned getReg() const
getReg - Returns the register number.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void dumpUses(unsigned RegNo) const
static def_iterator def_end()
virtual const TargetInstrInfo * getInstrInfo() const
static bool isNoReturnDef(const MachineOperand &MO)
void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)
Move NumOps operands from Src to Dst, updating use-def lists as needed.
static use_instr_iterator use_instr_end()
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
reg_iterator reg_begin(unsigned RegNo) const
virtual void MRI_NoteNewVirtualRegister(unsigned Reg)=0
void verifyUseLists() const
Verify the use list of all registers.
static reg_iterator reg_end()
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
unsigned getLiveInPhysReg(unsigned VReg) const
getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.
void addRegOperandToUseList(MachineOperand *MO)
Add MO to the linked list of operands for its register.