LLVM  4.0.0
PPCRegisterInfo.cpp
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1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "PPCRegisterInfo.h"
16 #include "PPC.h"
17 #include "PPCFrameLowering.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCSubtarget.h"
21 #include "PPCTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
35 #include "llvm/Support/Debug.h"
43 #include <cstdlib>
44 
45 using namespace llvm;
46 
47 #define DEBUG_TYPE "reginfo"
48 
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
51 
52 static cl::opt<bool>
53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true),
54  cl::desc("Enable use of a base pointer for complex stack frames"));
55 
56 static cl::opt<bool>
57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
58  cl::desc("Force the use of a base pointer in every function"));
59 
61  : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
62  TM.isPPC64() ? 0 : 1,
63  TM.isPPC64() ? 0 : 1),
64  TM(TM) {
65  ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66  ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67  ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68  ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69  ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70  ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71  ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72  ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73  ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
74 
75  // 64-bit
76  ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77  ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78  ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79  ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80  ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
81 
82  // VSX
83  ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
84  ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
85  ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
86  ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
87  ImmToIdxMap[PPC::LXV] = PPC::LXVX;
88  ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
89  ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
90  ImmToIdxMap[PPC::STXV] = PPC::STXVX;
91  ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
92  ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
93 }
94 
95 /// getPointerRegClass - Return the register class to use to hold pointers.
96 /// This is used for addressing modes.
97 const TargetRegisterClass *
99  const {
100  // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
101  // when it checks for ZERO folding.
102  if (Kind == 1) {
103  if (TM.isPPC64())
104  return &PPC::G8RC_NOX0RegClass;
105  return &PPC::GPRC_NOR0RegClass;
106  }
107 
108  if (TM.isPPC64())
109  return &PPC::G8RCRegClass;
110  return &PPC::GPRCRegClass;
111 }
112 
113 const MCPhysReg*
115  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
117  if (Subtarget.hasVSX())
118  return CSR_64_AllRegs_VSX_SaveList;
119  if (Subtarget.hasAltivec())
120  return CSR_64_AllRegs_Altivec_SaveList;
121  return CSR_64_AllRegs_SaveList;
122  }
123 
124  if (Subtarget.isDarwinABI())
125  return TM.isPPC64()
126  ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
127  : CSR_Darwin64_SaveList)
128  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
129  : CSR_Darwin32_SaveList);
130 
131  if (TM.isPPC64() && MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
132  return CSR_SRV464_TLS_PE_SaveList;
133 
134  // On PPC64, we might need to save r2 (but only if it is not reserved).
135  bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
136 
137  return TM.isPPC64()
138  ? (Subtarget.hasAltivec()
139  ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
140  : CSR_SVR464_Altivec_SaveList)
141  : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
142  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
143  : CSR_SVR432_SaveList);
144 }
145 
146 const MCPhysReg *
148  assert(MF && "Invalid MachineFunction pointer.");
149  const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
150  if (Subtarget.isDarwinABI())
151  return nullptr;
152  if (!TM.isPPC64())
153  return nullptr;
155  return nullptr;
156  if (!MF->getInfo<PPCFunctionInfo>()->isSplitCSR())
157  return nullptr;
158 
159  // On PPC64, we might need to save r2 (but only if it is not reserved).
160  bool SaveR2 = !getReservedRegs(*MF).test(PPC::X2);
161  if (Subtarget.hasAltivec())
162  return SaveR2
163  ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
164  : CSR_SVR464_Altivec_ViaCopy_SaveList;
165  else
166  return SaveR2
167  ? CSR_SVR464_R2_ViaCopy_SaveList
168  : CSR_SVR464_ViaCopy_SaveList;
169 }
170 
171 const uint32_t *
173  CallingConv::ID CC) const {
174  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
175  if (CC == CallingConv::AnyReg) {
176  if (Subtarget.hasVSX())
177  return CSR_64_AllRegs_VSX_RegMask;
178  if (Subtarget.hasAltivec())
179  return CSR_64_AllRegs_Altivec_RegMask;
180  return CSR_64_AllRegs_RegMask;
181  }
182 
183  if (Subtarget.isDarwinABI())
184  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
185  : CSR_Darwin64_RegMask)
186  : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
187  : CSR_Darwin32_RegMask);
188 
189  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
190  : CSR_SVR464_RegMask)
191  : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
192  : CSR_SVR432_RegMask);
193 }
194 
195 const uint32_t*
197  return CSR_NoRegs_RegMask;
198 }
199 
201  for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
202  Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
203 }
204 
206  BitVector Reserved(getNumRegs());
207  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
208  const PPCFrameLowering *TFI = getFrameLowering(MF);
209 
210  // The ZERO register is not really a register, but the representation of r0
211  // when used in instructions that treat r0 as the constant 0.
212  Reserved.set(PPC::ZERO);
213  Reserved.set(PPC::ZERO8);
214 
215  // The FP register is also not really a register, but is the representation
216  // of the frame pointer register used by ISD::FRAMEADDR.
217  Reserved.set(PPC::FP);
218  Reserved.set(PPC::FP8);
219 
220  // The BP register is also not really a register, but is the representation
221  // of the base pointer register used by setjmp.
222  Reserved.set(PPC::BP);
223  Reserved.set(PPC::BP8);
224 
225  // The counter registers must be reserved so that counter-based loops can
226  // be correctly formed (and the mtctr instructions are not DCE'd).
227  Reserved.set(PPC::CTR);
228  Reserved.set(PPC::CTR8);
229 
230  Reserved.set(PPC::R1);
231  Reserved.set(PPC::LR);
232  Reserved.set(PPC::LR8);
233  Reserved.set(PPC::RM);
234 
235  if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec())
236  Reserved.set(PPC::VRSAVE);
237 
238  // The SVR4 ABI reserves r2 and r13
239  if (Subtarget.isSVR4ABI()) {
240  Reserved.set(PPC::R2); // System-reserved register
241  Reserved.set(PPC::R13); // Small Data Area pointer register
242  }
243 
244  // On PPC64, r13 is the thread pointer. Never allocate this register.
245  if (TM.isPPC64()) {
246  Reserved.set(PPC::R13);
247 
248  Reserved.set(PPC::X1);
249  Reserved.set(PPC::X13);
250 
251  if (TFI->needsFP(MF))
252  Reserved.set(PPC::X31);
253 
254  if (hasBasePointer(MF))
255  Reserved.set(PPC::X30);
256 
257  // The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
258  if (Subtarget.isSVR4ABI()) {
259  // We only reserve r2 if we need to use the TOC pointer. If we have no
260  // explicit uses of the TOC pointer (meaning we're a leaf function with
261  // no constant-pool loads, etc.) and we have no potential uses inside an
262  // inline asm block, then we can treat r2 has an ordinary callee-saved
263  // register.
264  const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
265  if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
266  Reserved.set(PPC::X2);
267  else
268  Reserved.reset(PPC::R2);
269  }
270  }
271 
272  if (TFI->needsFP(MF))
273  Reserved.set(PPC::R31);
274 
275  bool IsPositionIndependent = TM.isPositionIndependent();
276  if (hasBasePointer(MF)) {
277  if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
278  Reserved.set(PPC::R29);
279  else
280  Reserved.set(PPC::R30);
281  }
282 
283  if (Subtarget.isSVR4ABI() && !TM.isPPC64() && IsPositionIndependent)
284  Reserved.set(PPC::R30);
285 
286  // Reserve Altivec registers when Altivec is unavailable.
287  if (!Subtarget.hasAltivec())
288  for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
289  IE = PPC::VRRCRegClass.end(); I != IE; ++I)
290  Reserved.set(*I);
291 
292  return Reserved;
293 }
294 
296  MachineFunction &MF) const {
297  const PPCFrameLowering *TFI = getFrameLowering(MF);
298  const unsigned DefaultSafety = 1;
299 
300  switch (RC->getID()) {
301  default:
302  return 0;
303  case PPC::G8RC_NOX0RegClassID:
304  case PPC::GPRC_NOR0RegClassID:
305  case PPC::G8RCRegClassID:
306  case PPC::GPRCRegClassID: {
307  unsigned FP = TFI->hasFP(MF) ? 1 : 0;
308  return 32 - FP - DefaultSafety;
309  }
310  case PPC::F8RCRegClassID:
311  case PPC::F4RCRegClassID:
312  case PPC::QFRCRegClassID:
313  case PPC::QSRCRegClassID:
314  case PPC::QBRCRegClassID:
315  case PPC::VRRCRegClassID:
316  case PPC::VFRCRegClassID:
317  case PPC::VSLRCRegClassID:
318  return 32 - DefaultSafety;
319  case PPC::VSRCRegClassID:
320  case PPC::VSFRCRegClassID:
321  case PPC::VSSRCRegClassID:
322  return 64 - DefaultSafety;
323  case PPC::CRRCRegClassID:
324  return 8 - DefaultSafety;
325  }
326 }
327 
328 const TargetRegisterClass *
330  const MachineFunction &MF) const {
331  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
332  if (Subtarget.hasVSX()) {
333  // With VSX, we can inflate various sub-register classes to the full VSX
334  // register set.
335 
336  if (RC == &PPC::F8RCRegClass)
337  return &PPC::VSFRCRegClass;
338  else if (RC == &PPC::VRRCRegClass)
339  return &PPC::VSRCRegClass;
340  else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
341  return &PPC::VSSRCRegClass;
342  }
343 
345 }
346 
347 //===----------------------------------------------------------------------===//
348 // Stack Frame Processing methods
349 //===----------------------------------------------------------------------===//
350 
351 /// lowerDynamicAlloc - Generate the code for allocating an object in the
352 /// current frame. The sequence of code will be in the general form
353 ///
354 /// addi R0, SP, \#frameSize ; get the address of the previous frame
355 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
356 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
357 ///
359  // Get the instruction.
360  MachineInstr &MI = *II;
361  // Get the instruction's basic block.
363  // Get the basic block's function.
364  MachineFunction &MF = *MBB.getParent();
365  // Get the frame info.
366  MachineFrameInfo &MFI = MF.getFrameInfo();
367  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
368  // Get the instruction info.
369  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
370  // Determine whether 64-bit pointers are used.
371  bool LP64 = TM.isPPC64();
372  DebugLoc dl = MI.getDebugLoc();
373 
374  // Get the maximum call stack size.
375  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
376  // Get the total frame size.
377  unsigned FrameSize = MFI.getStackSize();
378 
379  // Get stack alignments.
380  const PPCFrameLowering *TFI = getFrameLowering(MF);
381  unsigned TargetAlign = TFI->getStackAlignment();
382  unsigned MaxAlign = MFI.getMaxAlignment();
383  assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
384  "Maximum call-frame size not sufficiently aligned");
385 
386  // Determine the previous frame's address. If FrameSize can't be
387  // represented as 16 bits or we need special alignment, then we load the
388  // previous frame's address from 0(SP). Why not do an addis of the hi?
389  // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
390  // Constructing the constant and adding would take 3 instructions.
391  // Fortunately, a frame greater than 32K is rare.
392  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
393  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
394  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
395 
396  if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
397  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
398  .addReg(PPC::R31)
399  .addImm(FrameSize);
400  } else if (LP64) {
401  BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
402  .addImm(0)
403  .addReg(PPC::X1);
404  } else {
405  BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
406  .addImm(0)
407  .addReg(PPC::R1);
408  }
409 
410  bool KillNegSizeReg = MI.getOperand(1).isKill();
411  unsigned NegSizeReg = MI.getOperand(1).getReg();
412 
413  // Grow the stack and update the stack pointer link, then determine the
414  // address of new allocated space.
415  if (LP64) {
416  if (MaxAlign > TargetAlign) {
417  unsigned UnalNegSizeReg = NegSizeReg;
418  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
419 
420  // Unfortunately, there is no andi, only andi., and we can't insert that
421  // here because we might clobber cr0 while it is live.
422  BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
423  .addImm(~(MaxAlign-1));
424 
425  unsigned NegSizeReg1 = NegSizeReg;
426  NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
427  BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
428  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
429  .addReg(NegSizeReg1, RegState::Kill);
430  KillNegSizeReg = true;
431  }
432 
433  BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
434  .addReg(Reg, RegState::Kill)
435  .addReg(PPC::X1)
436  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
437  BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
438  .addReg(PPC::X1)
439  .addImm(maxCallFrameSize);
440  } else {
441  if (MaxAlign > TargetAlign) {
442  unsigned UnalNegSizeReg = NegSizeReg;
443  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
444 
445  // Unfortunately, there is no andi, only andi., and we can't insert that
446  // here because we might clobber cr0 while it is live.
447  BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
448  .addImm(~(MaxAlign-1));
449 
450  unsigned NegSizeReg1 = NegSizeReg;
451  NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
452  BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
453  .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
454  .addReg(NegSizeReg1, RegState::Kill);
455  KillNegSizeReg = true;
456  }
457 
458  BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
459  .addReg(Reg, RegState::Kill)
460  .addReg(PPC::R1)
461  .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
462  BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
463  .addReg(PPC::R1)
464  .addImm(maxCallFrameSize);
465  }
466 
467  // Discard the DYNALLOC instruction.
468  MBB.erase(II);
469 }
470 
472  MachineBasicBlock::iterator II) const {
473  // Get the instruction.
474  MachineInstr &MI = *II;
475  // Get the instruction's basic block.
477  // Get the basic block's function.
478  MachineFunction &MF = *MBB.getParent();
479  // Get the frame info.
480  MachineFrameInfo &MFI = MF.getFrameInfo();
481  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
482  // Get the instruction info.
483  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
484 
485  unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
486  DebugLoc dl = MI.getDebugLoc();
487  BuildMI(MBB, II, dl, TII.get(PPC::LI), MI.getOperand(0).getReg())
488  .addImm(maxCallFrameSize);
489  MBB.erase(II);
490 }
491 
492 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
493 /// reserving a whole register (R0), we scrounge for one here. This generates
494 /// code like this:
495 ///
496 /// mfcr rA ; Move the conditional register into GPR rA.
497 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
498 /// stw rA, FI ; Store rA to the frame.
499 ///
501  unsigned FrameIndex) const {
502  // Get the instruction.
503  MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
504  // Get the instruction's basic block.
506  MachineFunction &MF = *MBB.getParent();
507  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
508  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
509  DebugLoc dl = MI.getDebugLoc();
510 
511  bool LP64 = TM.isPPC64();
512  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
513  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
514 
515  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
516  unsigned SrcReg = MI.getOperand(0).getReg();
517 
518  // We need to store the CR in the low 4-bits of the saved value. First, issue
519  // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
520  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
521  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
522 
523  // If the saved register wasn't CR0, shift the bits left so that they are in
524  // CR0's slot.
525  if (SrcReg != PPC::CR0) {
526  unsigned Reg1 = Reg;
527  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
528 
529  // rlwinm rA, rA, ShiftBits, 0, 31.
530  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
531  .addReg(Reg1, RegState::Kill)
532  .addImm(getEncodingValue(SrcReg) * 4)
533  .addImm(0)
534  .addImm(31);
535  }
536 
537  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
538  .addReg(Reg, RegState::Kill),
539  FrameIndex);
540 
541  // Discard the pseudo instruction.
542  MBB.erase(II);
543 }
544 
546  unsigned FrameIndex) const {
547  // Get the instruction.
548  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
549  // Get the instruction's basic block.
551  MachineFunction &MF = *MBB.getParent();
552  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
553  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
554  DebugLoc dl = MI.getDebugLoc();
555 
556  bool LP64 = TM.isPPC64();
557  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
558  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
559 
560  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
561  unsigned DestReg = MI.getOperand(0).getReg();
562  assert(MI.definesRegister(DestReg) &&
563  "RESTORE_CR does not define its destination");
564 
565  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
566  Reg), FrameIndex);
567 
568  // If the reloaded register isn't CR0, shift the bits right so that they are
569  // in the right CR's slot.
570  if (DestReg != PPC::CR0) {
571  unsigned Reg1 = Reg;
572  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
573 
574  unsigned ShiftBits = getEncodingValue(DestReg)*4;
575  // rlwinm r11, r11, 32-ShiftBits, 0, 31.
576  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
577  .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
578  .addImm(31);
579  }
580 
581  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
582  .addReg(Reg, RegState::Kill);
583 
584  // Discard the pseudo instruction.
585  MBB.erase(II);
586 }
587 
589  unsigned FrameIndex) const {
590  // Get the instruction.
591  MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
592  // Get the instruction's basic block.
594  MachineFunction &MF = *MBB.getParent();
595  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
596  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
597  DebugLoc dl = MI.getDebugLoc();
598 
599  bool LP64 = TM.isPPC64();
600  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
601  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
602 
603  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
604  unsigned SrcReg = MI.getOperand(0).getReg();
605 
606  BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL),
607  getCRFromCRBit(SrcReg))
608  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
609 
610  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
611  .addReg(getCRFromCRBit(SrcReg));
612 
613  // If the saved register wasn't CR0LT, shift the bits left so that the bit to
614  // store is the first one. Mask all but that bit.
615  unsigned Reg1 = Reg;
616  Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
617 
618  // rlwinm rA, rA, ShiftBits, 0, 0.
619  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
620  .addReg(Reg1, RegState::Kill)
621  .addImm(getEncodingValue(SrcReg))
622  .addImm(0).addImm(0);
623 
624  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
625  .addReg(Reg, RegState::Kill),
626  FrameIndex);
627 
628  // Discard the pseudo instruction.
629  MBB.erase(II);
630 }
631 
633  unsigned FrameIndex) const {
634  // Get the instruction.
635  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
636  // Get the instruction's basic block.
638  MachineFunction &MF = *MBB.getParent();
639  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
640  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
641  DebugLoc dl = MI.getDebugLoc();
642 
643  bool LP64 = TM.isPPC64();
644  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
645  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
646 
647  unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
648  unsigned DestReg = MI.getOperand(0).getReg();
649  assert(MI.definesRegister(DestReg) &&
650  "RESTORE_CRBIT does not define its destination");
651 
652  addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
653  Reg), FrameIndex);
654 
655  BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
656 
657  unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
658  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
659  .addReg(getCRFromCRBit(DestReg));
660 
661  unsigned ShiftBits = getEncodingValue(DestReg);
662  // rlwimi r11, r10, 32-ShiftBits, ..., ...
663  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
664  .addReg(RegO, RegState::Kill)
665  .addReg(Reg, RegState::Kill)
666  .addImm(ShiftBits ? 32 - ShiftBits : 0)
667  .addImm(ShiftBits)
668  .addImm(ShiftBits);
669 
670  BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
671  getCRFromCRBit(DestReg))
672  .addReg(RegO, RegState::Kill)
673  // Make sure we have a use dependency all the way through this
674  // sequence of instructions. We can't have the other bits in the CR
675  // modified in between the mfocrf and the mtocrf.
677 
678  // Discard the pseudo instruction.
679  MBB.erase(II);
680 }
681 
683  unsigned FrameIndex) const {
684  // Get the instruction.
685  MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
686  // Get the instruction's basic block.
688  MachineFunction &MF = *MBB.getParent();
689  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
690  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
691  DebugLoc dl = MI.getDebugLoc();
692 
693  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
694  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
695  unsigned SrcReg = MI.getOperand(0).getReg();
696 
697  BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
698  .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
699 
701  BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
702  FrameIndex);
703 
704  // Discard the pseudo instruction.
705  MBB.erase(II);
706 }
707 
709  unsigned FrameIndex) const {
710  // Get the instruction.
711  MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
712  // Get the instruction's basic block.
714  MachineFunction &MF = *MBB.getParent();
715  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
716  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
717  DebugLoc dl = MI.getDebugLoc();
718 
719  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
720  unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
721  unsigned DestReg = MI.getOperand(0).getReg();
722  assert(MI.definesRegister(DestReg) &&
723  "RESTORE_VRSAVE does not define its destination");
724 
725  addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
726  Reg), FrameIndex);
727 
728  BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
729  .addReg(Reg, RegState::Kill);
730 
731  // Discard the pseudo instruction.
732  MBB.erase(II);
733 }
734 
736  unsigned Reg, int &FrameIdx) const {
737  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
738  // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
739  // ABI, return true to prevent allocating an additional frame slot.
740  // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
741  // is arbitrary and will be subsequently ignored. For 32-bit, we have
742  // previously created the stack slot if needed, so return its FrameIdx.
743  if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
744  if (TM.isPPC64())
745  FrameIdx = 0;
746  else {
747  const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
748  FrameIdx = FI->getCRSpillFrameIndex();
749  }
750  return true;
751  }
752  return false;
753 }
754 
755 // Figure out if the offset in the instruction must be a multiple of 4.
756 // This is true for instructions like "STD".
757 static bool usesIXAddr(const MachineInstr &MI) {
758  unsigned OpC = MI.getOpcode();
759 
760  switch (OpC) {
761  default:
762  return false;
763  case PPC::LWA:
764  case PPC::LWA_32:
765  case PPC::LD:
766  case PPC::STD:
767  return true;
768  }
769 }
770 
771 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
772 static unsigned getOffsetONFromFION(const MachineInstr &MI,
773  unsigned FIOperandNum) {
774  // Take into account whether it's an add or mem instruction
775  unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
776  if (MI.isInlineAsm())
777  OffsetOperandNo = FIOperandNum - 1;
778  else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
779  MI.getOpcode() == TargetOpcode::PATCHPOINT)
780  OffsetOperandNo = FIOperandNum + 1;
781 
782  return OffsetOperandNo;
783 }
784 
785 void
787  int SPAdj, unsigned FIOperandNum,
788  RegScavenger *RS) const {
789  assert(SPAdj == 0 && "Unexpected");
790 
791  // Get the instruction.
792  MachineInstr &MI = *II;
793  // Get the instruction's basic block.
795  // Get the basic block's function.
796  MachineFunction &MF = *MBB.getParent();
797  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
798  // Get the instruction info.
799  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
800  // Get the frame info.
801  MachineFrameInfo &MFI = MF.getFrameInfo();
802  DebugLoc dl = MI.getDebugLoc();
803 
804  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
805 
806  // Get the frame index.
807  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
808 
809  // Get the frame pointer save index. Users of this index are primarily
810  // DYNALLOC instructions.
812  int FPSI = FI->getFramePointerSaveIndex();
813  // Get the instruction opcode.
814  unsigned OpC = MI.getOpcode();
815 
816  if ((OpC == PPC::DYNAREAOFFSET || OpC == PPC::DYNAREAOFFSET8)) {
818  return;
819  }
820 
821  // Special case for dynamic alloca.
822  if (FPSI && FrameIndex == FPSI &&
823  (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
824  lowerDynamicAlloc(II);
825  return;
826  }
827 
828  // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
829  if (OpC == PPC::SPILL_CR) {
830  lowerCRSpilling(II, FrameIndex);
831  return;
832  } else if (OpC == PPC::RESTORE_CR) {
833  lowerCRRestore(II, FrameIndex);
834  return;
835  } else if (OpC == PPC::SPILL_CRBIT) {
836  lowerCRBitSpilling(II, FrameIndex);
837  return;
838  } else if (OpC == PPC::RESTORE_CRBIT) {
839  lowerCRBitRestore(II, FrameIndex);
840  return;
841  } else if (OpC == PPC::SPILL_VRSAVE) {
842  lowerVRSAVESpilling(II, FrameIndex);
843  return;
844  } else if (OpC == PPC::RESTORE_VRSAVE) {
845  lowerVRSAVERestore(II, FrameIndex);
846  return;
847  }
848 
849  // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
850  MI.getOperand(FIOperandNum).ChangeToRegister(
851  FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false);
852 
853  // Figure out if the offset in the instruction is shifted right two bits.
854  bool isIXAddr = usesIXAddr(MI);
855 
856  // If the instruction is not present in ImmToIdxMap, then it has no immediate
857  // form (and must be r+r).
858  bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
859  OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC);
860 
861  // Now add the frame object offset to the offset from r1.
862  int Offset = MFI.getObjectOffset(FrameIndex);
863  Offset += MI.getOperand(OffsetOperandNo).getImm();
864 
865  // If we're not using a Frame Pointer that has been set to the value of the
866  // SP before having the stack size subtracted from it, then add the stack size
867  // to Offset to get the correct offset.
868  // Naked functions have stack size 0, although getStackSize may not reflect
869  // that because we didn't call all the pieces that compute it for naked
870  // functions.
871  if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) {
872  if (!(hasBasePointer(MF) && FrameIndex < 0))
873  Offset += MFI.getStackSize();
874  }
875 
876  // If we can, encode the offset directly into the instruction. If this is a
877  // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
878  // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
879  // clear can be encoded. This is extremely uncommon, because normally you
880  // only "std" to a stack slot that is at least 4-byte aligned, but it can
881  // happen in invalid code.
882  assert(OpC != PPC::DBG_VALUE &&
883  "This should be handled in a target-independent way");
884  if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
885  OpC == TargetOpcode::STACKMAP ||
886  OpC == TargetOpcode::PATCHPOINT)) {
887  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
888  return;
889  }
890 
891  // The offset doesn't fit into a single register, scavenge one to build the
892  // offset in.
893 
894  bool is64Bit = TM.isPPC64();
895  const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
896  const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
897  const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
898  unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
899  SReg = MF.getRegInfo().createVirtualRegister(RC);
900 
901  // Insert a set of rA with the full offset value before the ld, st, or add
902  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
903  .addImm(Offset >> 16);
904  BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
905  .addReg(SRegHi, RegState::Kill)
906  .addImm(Offset);
907 
908  // Convert into indexed form of the instruction:
909  //
910  // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
911  // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
912  unsigned OperandBase;
913 
914  if (noImmForm)
915  OperandBase = 1;
916  else if (OpC != TargetOpcode::INLINEASM) {
917  assert(ImmToIdxMap.count(OpC) &&
918  "No indexed form of load or store available!");
919  unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
920  MI.setDesc(TII.get(NewOpcode));
921  OperandBase = 1;
922  } else {
923  OperandBase = OffsetOperandNo;
924  }
925 
926  unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
927  MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
928  MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
929 }
930 
932  const PPCFrameLowering *TFI = getFrameLowering(MF);
933 
934  if (!TM.isPPC64())
935  return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
936  else
937  return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
938 }
939 
941  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
942  if (!hasBasePointer(MF))
943  return getFrameRegister(MF);
944 
945  if (TM.isPPC64())
946  return PPC::X30;
947 
948  if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
949  return PPC::R29;
950 
951  return PPC::R30;
952 }
953 
955  if (!EnableBasePointer)
956  return false;
957  if (AlwaysBasePointer)
958  return true;
959 
960  // If we need to realign the stack, then the stack pointer can no longer
961  // serve as an offset into the caller's stack space. As a result, we need a
962  // base pointer.
963  return needsStackRealignment(MF);
964 }
965 
966 /// Returns true if the instruction's frame index
967 /// reference would be better served by a base register other than FP
968 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
969 /// references it should create new base registers for.
972  assert(Offset < 0 && "Local offset must be negative");
973 
974  // It's the load/store FI references that cause issues, as it can be difficult
975  // to materialize the offset if it won't fit in the literal field. Estimate
976  // based on the size of the local frame and some conservative assumptions
977  // about the rest of the stack frame (note, this is pre-regalloc, so
978  // we don't know everything for certain yet) whether this offset is likely
979  // to be out of range of the immediate. Return true if so.
980 
981  // We only generate virtual base registers for loads and stores that have
982  // an r+i form. Return false for everything else.
983  unsigned OpC = MI->getOpcode();
984  if (!ImmToIdxMap.count(OpC))
985  return false;
986 
987  // Don't generate a new virtual base register just to add zero to it.
988  if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
989  MI->getOperand(2).getImm() == 0)
990  return false;
991 
992  MachineBasicBlock &MBB = *MI->getParent();
993  MachineFunction &MF = *MBB.getParent();
994  const PPCFrameLowering *TFI = getFrameLowering(MF);
995  unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
996 
997  // If we likely don't need a stack frame, then we probably don't need a
998  // virtual base register either.
999  if (!StackEst)
1000  return false;
1001 
1002  // Estimate an offset from the stack pointer.
1003  // The incoming offset is relating to the SP at the start of the function,
1004  // but when we access the local it'll be relative to the SP after local
1005  // allocation, so adjust our SP-relative offset by that allocation size.
1006  Offset += StackEst;
1007 
1008  // The frame pointer will point to the end of the stack, so estimate the
1009  // offset as the difference between the object offset and the FP location.
1010  return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset);
1011 }
1012 
1013 /// Insert defining instruction(s) for BaseReg to
1014 /// be a pointer to FrameIdx at the beginning of the basic block.
1015 void PPCRegisterInfo::
1017  unsigned BaseReg, int FrameIdx,
1018  int64_t Offset) const {
1019  unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1020 
1022  DebugLoc DL; // Defaults to "unknown"
1023  if (Ins != MBB->end())
1024  DL = Ins->getDebugLoc();
1025 
1026  const MachineFunction &MF = *MBB->getParent();
1027  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1028  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1029  const MCInstrDesc &MCID = TII.get(ADDriOpc);
1031  MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
1032 
1033  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1034  .addFrameIndex(FrameIdx).addImm(Offset);
1035 }
1036 
1038  int64_t Offset) const {
1039  unsigned FIOperandNum = 0;
1040  while (!MI.getOperand(FIOperandNum).isFI()) {
1041  ++FIOperandNum;
1042  assert(FIOperandNum < MI.getNumOperands() &&
1043  "Instr doesn't have FrameIndex operand!");
1044  }
1045 
1046  MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1047  unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1048  Offset += MI.getOperand(OffsetOperandNo).getImm();
1049  MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1050 
1051  MachineBasicBlock &MBB = *MI.getParent();
1052  MachineFunction &MF = *MBB.getParent();
1053  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1054  const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1055  const MCInstrDesc &MCID = MI.getDesc();
1057  MRI.constrainRegClass(BaseReg,
1058  TII.getRegClass(MCID, FIOperandNum, this, MF));
1059 }
1060 
1062  unsigned BaseReg,
1063  int64_t Offset) const {
1064  unsigned FIOperandNum = 0;
1065  while (!MI->getOperand(FIOperandNum).isFI()) {
1066  ++FIOperandNum;
1067  assert(FIOperandNum < MI->getNumOperands() &&
1068  "Instr doesn't have FrameIndex operand!");
1069  }
1070 
1071  unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
1072  Offset += MI->getOperand(OffsetOperandNo).getImm();
1073 
1074  return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
1075  MI->getOpcode() == TargetOpcode::STACKMAP ||
1076  MI->getOpcode() == TargetOpcode::PATCHPOINT ||
1077  (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));
1078 }
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
BitVector & set()
Definition: BitVector.h:219
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool isDarwinABI() const
Definition: PPCSubtarget.h:297
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
const_iterator begin(StringRef path)
Get begin iterator over path.
Definition: Path.cpp:233
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
#define R2(n)
bool hasAltivec() const
Definition: PPCSubtarget.h:239
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
const HexagonInstrInfo * TII
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isKill() const
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineBasicBlock * MBB
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
int64_t getImm() const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
unsigned getBaseRegister(const MachineFunction &MF) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool is64Bit(const char *name)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
BitVector & reset()
Definition: BitVector.h:260
uint32_t Offset
bool isPositionIndependent() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Common code between 32-bit and 64-bit PowerPC targets.
bool isSVR4ABI() const
Definition: PPCSubtarget.h:298
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:895
const uint32_t * getNoPreservedMask() const override
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool usesIXAddr(const MachineInstr &MI)
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:179
bool test(unsigned Idx) const
Definition: BitVector.h:323
bool isInlineAsm() const
Definition: MachineInstr.h:789
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
const MachineInstrBuilder & addFrameIndex(int Idx) const
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:122
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:333
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
#define I(x, y, z)
Definition: MD5.cpp:54
bool hasVSX() const
Definition: PPCSubtarget.h:242
iterator find(const KeyT &Val)
Definition: DenseMap.h:127
bool hasP8Vector() const
Definition: PPCSubtarget.h:243
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
const unsigned Kind
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasBasePointer(const MachineFunction &MF) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override