LLVM  4.0.0
PPCTargetMachine.cpp
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1 //===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the PowerPC target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCTargetMachine.h"
15 #include "PPC.h"
16 #include "PPCTargetObjectFile.h"
17 #include "PPCTargetTransformInfo.h"
19 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Transforms/Scalar.h"
29 using namespace llvm;
30 
31 static cl::
32 opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
33  cl::desc("Disable CTR loops for PPC"));
34 
35 static cl::
36 opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
37  cl::desc("Disable PPC loop preinc prep"));
38 
39 static cl::opt<bool>
40 VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
41  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
42 
43 static cl::
44 opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
45  cl::desc("Disable VSX Swap Removal for PPC"));
46 
47 static cl::
48 opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
49  cl::desc("Disable QPX load splat simplification"));
50 
51 static cl::
52 opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
53  cl::desc("Disable machine peepholes for PPC"));
54 
55 static cl::opt<bool>
56 EnableGEPOpt("ppc-gep-opt", cl::Hidden,
57  cl::desc("Enable optimizations on complex GEPs"),
58  cl::init(true));
59 
60 static cl::opt<bool>
61 EnablePrefetch("enable-ppc-prefetching",
62  cl::desc("disable software prefetching on PPC"),
63  cl::init(false), cl::Hidden);
64 
65 static cl::opt<bool>
66 EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps",
67  cl::desc("Add extra TOC register dependencies"),
68  cl::init(true), cl::Hidden);
69 
70 static cl::opt<bool>
71 EnableMachineCombinerPass("ppc-machine-combiner",
72  cl::desc("Enable the machine combiner pass"),
73  cl::init(true), cl::Hidden);
74 
75 extern "C" void LLVMInitializePowerPCTarget() {
76  // Register the targets
80 
83 }
84 
85 /// Return the datalayout string of a subtarget.
86 static std::string getDataLayoutString(const Triple &T) {
87  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
88  std::string Ret;
89 
90  // Most PPC* platforms are big endian, PPC64LE is little endian.
91  if (T.getArch() == Triple::ppc64le)
92  Ret = "e";
93  else
94  Ret = "E";
95 
97 
98  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
99  // pointers.
100  if (!is64Bit || T.getOS() == Triple::Lv2)
101  Ret += "-p:32:32";
102 
103  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
104  // documentation are wrong; these are correct (i.e. "what gcc does").
105  if (is64Bit || !T.isOSDarwin())
106  Ret += "-i64:64";
107  else
108  Ret += "-f64:32:64";
109 
110  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
111  if (is64Bit)
112  Ret += "-n32:64";
113  else
114  Ret += "-n32";
115 
116  return Ret;
117 }
118 
120  const Triple &TT) {
121  std::string FullFS = FS;
122 
123  // Make sure 64-bit features are available when CPUname is generic
124  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
125  if (!FullFS.empty())
126  FullFS = "+64bit," + FullFS;
127  else
128  FullFS = "+64bit";
129  }
130 
131  if (OL >= CodeGenOpt::Default) {
132  if (!FullFS.empty())
133  FullFS = "+crbits," + FullFS;
134  else
135  FullFS = "+crbits";
136  }
137 
138  if (OL != CodeGenOpt::None) {
139  if (!FullFS.empty())
140  FullFS = "+invariant-function-descriptors," + FullFS;
141  else
142  FullFS = "+invariant-function-descriptors";
143  }
144 
145  return FullFS;
146 }
147 
148 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
149  // If it isn't a Mach-O file then it's going to be a linux ELF
150  // object file.
151  if (TT.isOSDarwin())
152  return make_unique<TargetLoweringObjectFileMachO>();
153 
154  return make_unique<PPC64LinuxTargetObjectFile>();
155 }
156 
158  const TargetOptions &Options) {
159  if (Options.MCOptions.getABIName().startswith("elfv1"))
161  else if (Options.MCOptions.getABIName().startswith("elfv2"))
163 
164  assert(Options.MCOptions.getABIName().empty() &&
165  "Unknown target-abi option!");
166 
167  if (!TT.isMacOSX()) {
168  switch (TT.getArch()) {
169  case Triple::ppc64le:
171  case Triple::ppc64:
173  default:
174  // Fallthrough.
175  ;
176  }
177  }
179 }
180 
183  if (!RM.hasValue()) {
184  if (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le) {
185  if (!TT.isOSBinFormatMachO() && !TT.isMacOSX())
186  return Reloc::PIC_;
187  }
188  if (TT.isOSDarwin())
189  return Reloc::DynamicNoPIC;
190  return Reloc::Static;
191  }
192  return *RM;
193 }
194 
195 // The FeatureString here is a little subtle. We are modifying the feature
196 // string with what are (currently) non-function specific overrides as it goes
197 // into the LLVMTargetMachine constructor and then using the stored value in the
198 // Subtarget constructor below it.
200  StringRef CPU, StringRef FS,
201  const TargetOptions &Options,
204  : LLVMTargetMachine(T, getDataLayoutString(TT), TT, CPU,
205  computeFSAdditions(FS, OL, TT), Options,
206  getEffectiveRelocModel(TT, RM), CM, OL),
207  TLOF(createTLOF(getTargetTriple())),
208  TargetABI(computeTargetABI(TT, Options)),
209  Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) {
210 
211  initAsmInfo();
212 }
213 
215 
216 void PPC32TargetMachine::anchor() { }
217 
219  StringRef CPU, StringRef FS,
220  const TargetOptions &Options,
222  CodeModel::Model CM,
224  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
225 
226 void PPC64TargetMachine::anchor() { }
227 
229  StringRef CPU, StringRef FS,
230  const TargetOptions &Options,
232  CodeModel::Model CM,
234  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {}
235 
236 const PPCSubtarget *
238  Attribute CPUAttr = F.getFnAttribute("target-cpu");
239  Attribute FSAttr = F.getFnAttribute("target-features");
240 
241  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
242  ? CPUAttr.getValueAsString().str()
243  : TargetCPU;
244  std::string FS = !FSAttr.hasAttribute(Attribute::None)
245  ? FSAttr.getValueAsString().str()
246  : TargetFS;
247 
248  // FIXME: This is related to the code below to reset the target options,
249  // we need to know whether or not the soft float flag is set on the
250  // function before we can generate a subtarget. We also need to use
251  // it as a key for the subtarget since that can be the only difference
252  // between two functions.
253  bool SoftFloat =
254  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
255  // If the soft float attribute is set on the function turn on the soft float
256  // subtarget feature.
257  if (SoftFloat)
258  FS += FS.empty() ? "-hard-float" : ",-hard-float";
259 
260  auto &I = SubtargetMap[CPU + FS];
261  if (!I) {
262  // This needs to be done before we create a new subtarget since any
263  // creation will depend on the TM and the code generation flags on the
264  // function that reside in TargetOptions.
266  I = llvm::make_unique<PPCSubtarget>(
267  TargetTriple, CPU,
268  // FIXME: It would be good to have the subtarget additions here
269  // not necessary. Anything that turns them on/off (overrides) ends
270  // up being put at the end of the feature string, but the defaults
271  // shouldn't require adding them. Fixing this means pulling Feature64Bit
272  // out of most of the target cpus in the .td file and making it set only
273  // as part of initialization via the TargetTriple.
275  }
276  return I.get();
277 }
278 
279 //===----------------------------------------------------------------------===//
280 // Pass Pipeline Configuration
281 //===----------------------------------------------------------------------===//
282 
283 namespace {
284 /// PPC Code Generator Pass Configuration Options.
285 class PPCPassConfig : public TargetPassConfig {
286 public:
287  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
288  : TargetPassConfig(TM, PM) {}
289 
290  PPCTargetMachine &getPPCTargetMachine() const {
291  return getTM<PPCTargetMachine>();
292  }
293 
294  void addIRPasses() override;
295  bool addPreISel() override;
296  bool addILPOpts() override;
297  bool addInstSelector() override;
298  void addMachineSSAOptimization() override;
299  void addPreRegAlloc() override;
300  void addPreSched2() override;
301  void addPreEmitPass() override;
302 };
303 } // namespace
304 
306  return new PPCPassConfig(this, PM);
307 }
308 
309 void PPCPassConfig::addIRPasses() {
310  if (TM->getOptLevel() != CodeGenOpt::None)
311  addPass(createPPCBoolRetToIntPass());
312  addPass(createAtomicExpandPass(&getPPCTargetMachine()));
313 
314  // For the BG/Q (or if explicitly requested), add explicit data prefetch
315  // intrinsics.
316  bool UsePrefetching = TM->getTargetTriple().getVendor() == Triple::BGQ &&
317  getOptLevel() != CodeGenOpt::None;
318  if (EnablePrefetch.getNumOccurrences() > 0)
319  UsePrefetching = EnablePrefetch;
320  if (UsePrefetching)
321  addPass(createLoopDataPrefetchPass());
322 
323  if (TM->getOptLevel() >= CodeGenOpt::Default && EnableGEPOpt) {
324  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
325  // and lower a GEP with multiple indices to either arithmetic operations or
326  // multiple GEPs with single index.
328  // Call EarlyCSE pass to find and remove subexpressions in the lowered
329  // result.
330  addPass(createEarlyCSEPass());
331  // Do loop invariant code motion in case part of the lowered result is
332  // invariant.
333  addPass(createLICMPass());
334  }
335 
337 }
338 
339 bool PPCPassConfig::addPreISel() {
340  if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
341  addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
342 
343  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
344  addPass(createPPCCTRLoops(getPPCTargetMachine()));
345 
346  return false;
347 }
348 
349 bool PPCPassConfig::addILPOpts() {
350  addPass(&EarlyIfConverterID);
351 
353  addPass(&MachineCombinerID);
354 
355  return true;
356 }
357 
358 bool PPCPassConfig::addInstSelector() {
359  // Install an instruction selector.
360  addPass(createPPCISelDag(getPPCTargetMachine()));
361 
362 #ifndef NDEBUG
363  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
364  addPass(createPPCCTRLoopsVerify());
365 #endif
366 
367  addPass(createPPCVSXCopyPass());
368  return false;
369 }
370 
371 void PPCPassConfig::addMachineSSAOptimization() {
373  // For little endian, remove where possible the vector swap instructions
374  // introduced at code generation to normalize vector element order.
375  if (TM->getTargetTriple().getArch() == Triple::ppc64le &&
377  addPass(createPPCVSXSwapRemovalPass());
378  // Target-specific peephole cleanups performed after instruction
379  // selection.
380  if (!DisableMIPeephole) {
381  addPass(createPPCMIPeepholePass());
383  }
384 }
385 
386 void PPCPassConfig::addPreRegAlloc() {
387  if (getOptLevel() != CodeGenOpt::None) {
391  }
392 
393  // FIXME: We probably don't need to run these for -fPIE.
394  if (getPPCTargetMachine().isPositionIndependent()) {
395  // FIXME: LiveVariables should not be necessary here!
396  // PPCTLSDYnamicCallPass uses LiveIntervals which previously dependet on
397  // LiveVariables. This (unnecessary) dependency has been removed now,
398  // however a stage-2 clang build fails without LiveVariables computed here.
399  addPass(&LiveVariablesID, false);
400  addPass(createPPCTLSDynamicCallPass());
401  }
403  addPass(createPPCTOCRegDepsPass());
404 }
405 
406 void PPCPassConfig::addPreSched2() {
407  if (getOptLevel() != CodeGenOpt::None) {
408  addPass(&IfConverterID);
409 
410  // This optimization must happen after anything that might do store-to-load
411  // forwarding. Here we're after RA (and, thus, when spills are inserted)
412  // but before post-RA scheduling.
413  if (!DisableQPXLoadSplat)
414  addPass(createPPCQPXLoadSplatPass());
415  }
416 }
417 
418 void PPCPassConfig::addPreEmitPass() {
419  if (getOptLevel() != CodeGenOpt::None)
420  addPass(createPPCEarlyReturnPass(), false);
421  // Must run branch selection immediately preceding the asm printer.
422  addPass(createPPCBranchSelectionPass(), false);
423 }
424 
426  return TargetIRAnalysis([this](const Function &F) {
427  return TargetTransformInfo(PPCTTIImpl(this, F));
428  });
429 }
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:279
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:575
MCTargetOptions MCOptions
Machine level options.
bool hasValue() const
Definition: Optional.h:125
FunctionPass * createPPCVSXSwapRemovalPass()
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
const PPCSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
static cl::opt< bool > DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden, cl::desc("Disable QPX load splat simplification"))
Target & getThePPC32Target()
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
Analysis pass providing the TargetTransformInfo.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:234
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, const Triple &TT)
char & PPCVSXFMAMutateID
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:185
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:155
FunctionPass * createPPCTLSDynamicCallPass()
static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))
FunctionPass * createLoopDataPrefetchPass()
const Triple & getTargetTriple() const
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:427
FunctionPass * createPPCTOCRegDepsPass()
This file a TargetTransformInfo::Concept conforming object specific to the PPC target machine...
static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
No attributes have been set.
Definition: Attributes.h:69
PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
Target-Independent Code Generator Pass Configuration Options.
#define F(x, y, z)
Definition: MD5.cpp:51
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:264
FunctionPass * createPPCCTRLoopsVerify()
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:270
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
FunctionPass * createPPCBoolRetToIntPass()
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Target & getThePPC64Target()
FunctionPass * createPPCBranchSelectionPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
void initializePPCBoolRetToIntPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
FunctionPass * createSeparateConstOffsetFromGEPPass(const TargetMachine *TM=nullptr, bool LowerGEP=false)
FunctionPass * createPPCEarlyReturnPass()
static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
void LLVMInitializePowerPCTarget()
static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))
static bool is64Bit(const char *name)
void initializePPCVSXFMAMutatePass(PassRegistry &)
PPC32TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
Pass * createLICMPass()
Definition: LICM.cpp:217
This class describes a target machine that is implemented with the LLVM target-independent code gener...
TargetIRAnalysis getTargetIRAnalysis() override
Get a TargetIRAnalysis implementation for the target.
Common code between 32-bit and 64-bit PowerPC targets.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:225
FunctionPass * createPPCVSXCopyPass()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:455
static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("disable software prefetching on PPC"), cl::init(false), cl::Hidden)
FunctionPass * createPPCCTRLoops(PPCTargetMachine &TM)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
Target - Wrapper for Target specific information.
Target & getThePPC64LETarget()
static cl::opt< bool > DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden, cl::desc("Disable PPC loop preinc prep"))
PPC64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:130
static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
FunctionPass * createPPCQPXLoadSplatPass()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
#define I(x, y, z)
Definition: MD5.cpp:54
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:178
FunctionPass * createPPCMIPeepholePass()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createPPCLoopPreIncPrepPass(PPCTargetMachine &TM)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
static std::string getDataLayoutString(const Triple &T)
Return the datalayout string of a subtarget.
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1050
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:40
FunctionPass * createPPCISelDag(PPCTargetMachine &TM)
createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG, ready for instruction scheduling.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")