29 #define DEBUG_TYPE "mips-isel"
36 cl::desc(
"Expand double precision loads and "
37 "stores to their single precision "
279 return Subtarget.
hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
403 case ISD::LOAD:
return lowerLOAD(Op, DAG);
446 if (MultLo.
getNode() != MultNode)
488 if (!
SDValue(ADDENode, 0).use_empty()) {
518 if (MultLo.
getNode() != MultNode)
560 if (!
SDValue(SUBENode, 0).use_empty()) {
609 int32_t Log2IfPositive = (Mask->
getAPIntValue() + 1).exactLogBase2();
611 if (Log2IfPositive <= 0)
615 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
617 unsigned Log2 = Log2IfPositive;
620 Log2 == ExtendTySize) {
646 APInt SplatValue, SplatUndef;
647 unsigned SplatBitSize;
650 if (!Node->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
671 APInt SplatValue, SplatUndef;
672 unsigned SplatBitSize;
677 if (BVN->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
722 bool IsLittleEndian = !Subtarget.
isLittle();
725 bool IsConstantMask =
false;
732 if (
isVSplat(Op0Op0, Mask, IsLittleEndian)) {
736 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
739 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
743 IsConstantMask =
true;
753 if (
isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
756 else if (
isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
760 IsConstantMask =
true;
809 if (IsConstantMask) {
855 uint64_t Floor = 1LL <<
Log2_64(C);
856 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
861 if (C - Floor <= Ceil - C) {
892 APInt SplatValue, SplatUndef;
893 unsigned SplatBitSize;
902 !BV->
isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
904 (SplatBitSize != EltSize) ||
960 EVT ExtendTy = cast<VTSDNode>(Op0Op0->
getOperand(2))->getVT();
963 if (TotalBits == 32 ||
1007 default:
return false;
1060 if (Op1 == Op0Op0 && Op2 == Op0Op1)
1063 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1142 DEBUG(
dbgs() <<
"\nMipsSE DAG Combine:\n";
1144 dbgs() <<
"\n=> \n";
1159 case Mips::BPOSGE32_PSEUDO:
1160 return emitBPOSGE32(MI, BB);
1161 case Mips::SNZ_B_PSEUDO:
1162 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1163 case Mips::SNZ_H_PSEUDO:
1164 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1165 case Mips::SNZ_W_PSEUDO:
1166 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1167 case Mips::SNZ_D_PSEUDO:
1168 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1169 case Mips::SNZ_V_PSEUDO:
1170 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1171 case Mips::SZ_B_PSEUDO:
1172 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1173 case Mips::SZ_H_PSEUDO:
1174 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1175 case Mips::SZ_W_PSEUDO:
1176 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1177 case Mips::SZ_D_PSEUDO:
1178 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1179 case Mips::SZ_V_PSEUDO:
1180 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
1181 case Mips::COPY_FW_PSEUDO:
1182 return emitCOPY_FW(MI, BB);
1183 case Mips::COPY_FD_PSEUDO:
1184 return emitCOPY_FD(MI, BB);
1185 case Mips::INSERT_FW_PSEUDO:
1186 return emitINSERT_FW(MI, BB);
1187 case Mips::INSERT_FD_PSEUDO:
1188 return emitINSERT_FD(MI, BB);
1189 case Mips::INSERT_B_VIDX_PSEUDO:
1190 case Mips::INSERT_B_VIDX64_PSEUDO:
1191 return emitINSERT_DF_VIDX(MI, BB, 1,
false);
1192 case Mips::INSERT_H_VIDX_PSEUDO:
1193 case Mips::INSERT_H_VIDX64_PSEUDO:
1194 return emitINSERT_DF_VIDX(MI, BB, 2,
false);
1195 case Mips::INSERT_W_VIDX_PSEUDO:
1196 case Mips::INSERT_W_VIDX64_PSEUDO:
1197 return emitINSERT_DF_VIDX(MI, BB, 4,
false);
1198 case Mips::INSERT_D_VIDX_PSEUDO:
1199 case Mips::INSERT_D_VIDX64_PSEUDO:
1200 return emitINSERT_DF_VIDX(MI, BB, 8,
false);
1201 case Mips::INSERT_FW_VIDX_PSEUDO:
1202 case Mips::INSERT_FW_VIDX64_PSEUDO:
1203 return emitINSERT_DF_VIDX(MI, BB, 4,
true);
1204 case Mips::INSERT_FD_VIDX_PSEUDO:
1205 case Mips::INSERT_FD_VIDX64_PSEUDO:
1206 return emitINSERT_DF_VIDX(MI, BB, 8,
true);
1207 case Mips::FILL_FW_PSEUDO:
1208 return emitFILL_FW(MI, BB);
1209 case Mips::FILL_FD_PSEUDO:
1210 return emitFILL_FD(MI, BB);
1211 case Mips::FEXP2_W_1_PSEUDO:
1212 return emitFEXP2_W_1(MI, BB);
1213 case Mips::FEXP2_D_1_PSEUDO:
1214 return emitFEXP2_D_1(MI, BB);
1216 return emitST_F16_PSEUDO(MI, BB);
1218 return emitLD_F16_PSEUDO(MI, BB);
1219 case Mips::MSA_FP_EXTEND_W_PSEUDO:
1220 return emitFPEXTEND_PSEUDO(MI, BB,
false);
1221 case Mips::MSA_FP_ROUND_W_PSEUDO:
1222 return emitFPROUND_PSEUDO(MI, BB,
false);
1223 case Mips::MSA_FP_EXTEND_D_PSEUDO:
1224 return emitFPEXTEND_PSEUDO(MI, BB,
true);
1225 case Mips::MSA_FP_ROUND_D_PSEUDO:
1226 return emitFPROUND_PSEUDO(MI, BB,
true);
1230 bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1231 const CCState &CCInfo,
unsigned NextStackOffset,
1249 void MipsSETargetLowering::
1251 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1252 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
1253 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
1257 InternalLinkage, IsCallReloc, CLI, Callee,
1320 SDValue MipsSETargetLowering::lowerMulDiv(
SDValue Op,
unsigned NewOpc,
1321 bool HasLo,
bool HasHi,
1337 if (!HasLo || !HasHi)
1338 return HasLo ? Lo :
Hi;
1386 if (Opnd.getValueType() ==
MVT::i64)
1434 EVT ViaVecTy = ResVecTy;
1449 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1450 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
1455 if (ViaVecTy != ResVecTy)
1462 bool IsSigned =
false) {
1471 EVT ViaVecTy = VecTy;
1472 SDValue SplatValueA = SplatValue;
1473 SDValue SplatValueB = SplatValue;
1474 SDLoc DL(SplatValue);
1491 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1492 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1493 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1494 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1499 if (VecTy != ViaVecTy)
1516 APInt BitImm =
APInt(64, 1) << CImm->getAPIntValue();
1528 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
1532 if (!Exp2Imm.getNode()) {
1556 DAG.
getNOT(DL, Bit, ResTy));
1563 << cast<ConstantSDNode>(Op->
getOperand(2))->getAPIntValue();
1569 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(
SDValue Op,
1573 switch (Intrinsic) {
1576 case Intrinsic::mips_shilo:
1578 case Intrinsic::mips_dpau_h_qbl:
1580 case Intrinsic::mips_dpau_h_qbr:
1582 case Intrinsic::mips_dpsu_h_qbl:
1584 case Intrinsic::mips_dpsu_h_qbr:
1586 case Intrinsic::mips_dpa_w_ph:
1588 case Intrinsic::mips_dps_w_ph:
1590 case Intrinsic::mips_dpax_w_ph:
1592 case Intrinsic::mips_dpsx_w_ph:
1594 case Intrinsic::mips_mulsa_w_ph:
1596 case Intrinsic::mips_mult:
1598 case Intrinsic::mips_multu:
1600 case Intrinsic::mips_madd:
1602 case Intrinsic::mips_maddu:
1604 case Intrinsic::mips_msub:
1606 case Intrinsic::mips_msubu:
1608 case Intrinsic::mips_addv_b:
1609 case Intrinsic::mips_addv_h:
1610 case Intrinsic::mips_addv_w:
1611 case Intrinsic::mips_addv_d:
1614 case Intrinsic::mips_addvi_b:
1615 case Intrinsic::mips_addvi_h:
1616 case Intrinsic::mips_addvi_w:
1617 case Intrinsic::mips_addvi_d:
1620 case Intrinsic::mips_and_v:
1623 case Intrinsic::mips_andi_b:
1626 case Intrinsic::mips_bclr_b:
1627 case Intrinsic::mips_bclr_h:
1628 case Intrinsic::mips_bclr_w:
1629 case Intrinsic::mips_bclr_d:
1631 case Intrinsic::mips_bclri_b:
1632 case Intrinsic::mips_bclri_h:
1633 case Intrinsic::mips_bclri_w:
1634 case Intrinsic::mips_bclri_d:
1636 case Intrinsic::mips_binsli_b:
1637 case Intrinsic::mips_binsli_h:
1638 case Intrinsic::mips_binsli_w:
1639 case Intrinsic::mips_binsli_d: {
1651 case Intrinsic::mips_binsri_b:
1652 case Intrinsic::mips_binsri_h:
1653 case Intrinsic::mips_binsri_w:
1654 case Intrinsic::mips_binsri_d: {
1666 case Intrinsic::mips_bmnz_v:
1669 case Intrinsic::mips_bmnzi_b:
1673 case Intrinsic::mips_bmz_v:
1676 case Intrinsic::mips_bmzi_b:
1680 case Intrinsic::mips_bneg_b:
1681 case Intrinsic::mips_bneg_h:
1682 case Intrinsic::mips_bneg_w:
1683 case Intrinsic::mips_bneg_d: {
1691 case Intrinsic::mips_bnegi_b:
1692 case Intrinsic::mips_bnegi_h:
1693 case Intrinsic::mips_bnegi_w:
1694 case Intrinsic::mips_bnegi_d:
1697 case Intrinsic::mips_bnz_b:
1698 case Intrinsic::mips_bnz_h:
1699 case Intrinsic::mips_bnz_w:
1700 case Intrinsic::mips_bnz_d:
1703 case Intrinsic::mips_bnz_v:
1706 case Intrinsic::mips_bsel_v:
1711 case Intrinsic::mips_bseli_b:
1716 case Intrinsic::mips_bset_b:
1717 case Intrinsic::mips_bset_h:
1718 case Intrinsic::mips_bset_w:
1719 case Intrinsic::mips_bset_d: {
1727 case Intrinsic::mips_bseti_b:
1728 case Intrinsic::mips_bseti_h:
1729 case Intrinsic::mips_bseti_w:
1730 case Intrinsic::mips_bseti_d:
1733 case Intrinsic::mips_bz_b:
1734 case Intrinsic::mips_bz_h:
1735 case Intrinsic::mips_bz_w:
1736 case Intrinsic::mips_bz_d:
1739 case Intrinsic::mips_bz_v:
1742 case Intrinsic::mips_ceq_b:
1743 case Intrinsic::mips_ceq_h:
1744 case Intrinsic::mips_ceq_w:
1745 case Intrinsic::mips_ceq_d:
1748 case Intrinsic::mips_ceqi_b:
1749 case Intrinsic::mips_ceqi_h:
1750 case Intrinsic::mips_ceqi_w:
1751 case Intrinsic::mips_ceqi_d:
1754 case Intrinsic::mips_cle_s_b:
1755 case Intrinsic::mips_cle_s_h:
1756 case Intrinsic::mips_cle_s_w:
1757 case Intrinsic::mips_cle_s_d:
1760 case Intrinsic::mips_clei_s_b:
1761 case Intrinsic::mips_clei_s_h:
1762 case Intrinsic::mips_clei_s_w:
1763 case Intrinsic::mips_clei_s_d:
1766 case Intrinsic::mips_cle_u_b:
1767 case Intrinsic::mips_cle_u_h:
1768 case Intrinsic::mips_cle_u_w:
1769 case Intrinsic::mips_cle_u_d:
1772 case Intrinsic::mips_clei_u_b:
1773 case Intrinsic::mips_clei_u_h:
1774 case Intrinsic::mips_clei_u_w:
1775 case Intrinsic::mips_clei_u_d:
1778 case Intrinsic::mips_clt_s_b:
1779 case Intrinsic::mips_clt_s_h:
1780 case Intrinsic::mips_clt_s_w:
1781 case Intrinsic::mips_clt_s_d:
1784 case Intrinsic::mips_clti_s_b:
1785 case Intrinsic::mips_clti_s_h:
1786 case Intrinsic::mips_clti_s_w:
1787 case Intrinsic::mips_clti_s_d:
1790 case Intrinsic::mips_clt_u_b:
1791 case Intrinsic::mips_clt_u_h:
1792 case Intrinsic::mips_clt_u_w:
1793 case Intrinsic::mips_clt_u_d:
1796 case Intrinsic::mips_clti_u_b:
1797 case Intrinsic::mips_clti_u_h:
1798 case Intrinsic::mips_clti_u_w:
1799 case Intrinsic::mips_clti_u_d:
1802 case Intrinsic::mips_copy_s_b:
1803 case Intrinsic::mips_copy_s_h:
1804 case Intrinsic::mips_copy_s_w:
1806 case Intrinsic::mips_copy_s_d:
1817 case Intrinsic::mips_copy_u_b:
1818 case Intrinsic::mips_copy_u_h:
1819 case Intrinsic::mips_copy_u_w:
1821 case Intrinsic::mips_copy_u_d:
1835 case Intrinsic::mips_div_s_b:
1836 case Intrinsic::mips_div_s_h:
1837 case Intrinsic::mips_div_s_w:
1838 case Intrinsic::mips_div_s_d:
1841 case Intrinsic::mips_div_u_b:
1842 case Intrinsic::mips_div_u_h:
1843 case Intrinsic::mips_div_u_w:
1844 case Intrinsic::mips_div_u_d:
1847 case Intrinsic::mips_fadd_w:
1848 case Intrinsic::mips_fadd_d: {
1854 case Intrinsic::mips_fceq_w:
1855 case Intrinsic::mips_fceq_d:
1858 case Intrinsic::mips_fcle_w:
1859 case Intrinsic::mips_fcle_d:
1862 case Intrinsic::mips_fclt_w:
1863 case Intrinsic::mips_fclt_d:
1866 case Intrinsic::mips_fcne_w:
1867 case Intrinsic::mips_fcne_d:
1870 case Intrinsic::mips_fcor_w:
1871 case Intrinsic::mips_fcor_d:
1874 case Intrinsic::mips_fcueq_w:
1875 case Intrinsic::mips_fcueq_d:
1878 case Intrinsic::mips_fcule_w:
1879 case Intrinsic::mips_fcule_d:
1882 case Intrinsic::mips_fcult_w:
1883 case Intrinsic::mips_fcult_d:
1886 case Intrinsic::mips_fcun_w:
1887 case Intrinsic::mips_fcun_d:
1890 case Intrinsic::mips_fcune_w:
1891 case Intrinsic::mips_fcune_d:
1894 case Intrinsic::mips_fdiv_w:
1895 case Intrinsic::mips_fdiv_d: {
1900 case Intrinsic::mips_ffint_u_w:
1901 case Intrinsic::mips_ffint_u_d:
1904 case Intrinsic::mips_ffint_s_w:
1905 case Intrinsic::mips_ffint_s_d:
1908 case Intrinsic::mips_fill_b:
1909 case Intrinsic::mips_fill_h:
1910 case Intrinsic::mips_fill_w:
1911 case Intrinsic::mips_fill_d: {
1920 case Intrinsic::mips_fexp2_w:
1921 case Intrinsic::mips_fexp2_d: {
1928 case Intrinsic::mips_flog2_w:
1929 case Intrinsic::mips_flog2_d:
1931 case Intrinsic::mips_fmadd_w:
1932 case Intrinsic::mips_fmadd_d:
1935 case Intrinsic::mips_fmul_w:
1936 case Intrinsic::mips_fmul_d: {
1941 case Intrinsic::mips_fmsub_w:
1942 case Intrinsic::mips_fmsub_d: {
1949 case Intrinsic::mips_frint_w:
1950 case Intrinsic::mips_frint_d:
1952 case Intrinsic::mips_fsqrt_w:
1953 case Intrinsic::mips_fsqrt_d:
1955 case Intrinsic::mips_fsub_w:
1956 case Intrinsic::mips_fsub_d: {
1961 case Intrinsic::mips_ftrunc_u_w:
1962 case Intrinsic::mips_ftrunc_u_d:
1965 case Intrinsic::mips_ftrunc_s_w:
1966 case Intrinsic::mips_ftrunc_s_d:
1969 case Intrinsic::mips_ilvev_b:
1970 case Intrinsic::mips_ilvev_h:
1971 case Intrinsic::mips_ilvev_w:
1972 case Intrinsic::mips_ilvev_d:
1975 case Intrinsic::mips_ilvl_b:
1976 case Intrinsic::mips_ilvl_h:
1977 case Intrinsic::mips_ilvl_w:
1978 case Intrinsic::mips_ilvl_d:
1981 case Intrinsic::mips_ilvod_b:
1982 case Intrinsic::mips_ilvod_h:
1983 case Intrinsic::mips_ilvod_w:
1984 case Intrinsic::mips_ilvod_d:
1987 case Intrinsic::mips_ilvr_b:
1988 case Intrinsic::mips_ilvr_h:
1989 case Intrinsic::mips_ilvr_w:
1990 case Intrinsic::mips_ilvr_d:
1993 case Intrinsic::mips_insert_b:
1994 case Intrinsic::mips_insert_h:
1995 case Intrinsic::mips_insert_w:
1996 case Intrinsic::mips_insert_d:
1999 case Intrinsic::mips_insve_b:
2000 case Intrinsic::mips_insve_h:
2001 case Intrinsic::mips_insve_w:
2002 case Intrinsic::mips_insve_d: {
2005 switch (Intrinsic) {
2006 case Intrinsic::mips_insve_b: Max = 15;
break;
2007 case Intrinsic::mips_insve_h: Max = 7;
break;
2008 case Intrinsic::mips_insve_w: Max = 3;
break;
2009 case Intrinsic::mips_insve_d: Max = 1;
break;
2012 int64_t
Value = cast<ConstantSDNode>(Op->
getOperand(2))->getSExtValue();
2019 case Intrinsic::mips_ldi_b:
2020 case Intrinsic::mips_ldi_h:
2021 case Intrinsic::mips_ldi_w:
2022 case Intrinsic::mips_ldi_d:
2024 case Intrinsic::mips_lsa:
2025 case Intrinsic::mips_dlsa: {
2031 case Intrinsic::mips_maddv_b:
2032 case Intrinsic::mips_maddv_h:
2033 case Intrinsic::mips_maddv_w:
2034 case Intrinsic::mips_maddv_d: {
2040 case Intrinsic::mips_max_s_b:
2041 case Intrinsic::mips_max_s_h:
2042 case Intrinsic::mips_max_s_w:
2043 case Intrinsic::mips_max_s_d:
2046 case Intrinsic::mips_max_u_b:
2047 case Intrinsic::mips_max_u_h:
2048 case Intrinsic::mips_max_u_w:
2049 case Intrinsic::mips_max_u_d:
2052 case Intrinsic::mips_maxi_s_b:
2053 case Intrinsic::mips_maxi_s_h:
2054 case Intrinsic::mips_maxi_s_w:
2055 case Intrinsic::mips_maxi_s_d:
2058 case Intrinsic::mips_maxi_u_b:
2059 case Intrinsic::mips_maxi_u_h:
2060 case Intrinsic::mips_maxi_u_w:
2061 case Intrinsic::mips_maxi_u_d:
2064 case Intrinsic::mips_min_s_b:
2065 case Intrinsic::mips_min_s_h:
2066 case Intrinsic::mips_min_s_w:
2067 case Intrinsic::mips_min_s_d:
2070 case Intrinsic::mips_min_u_b:
2071 case Intrinsic::mips_min_u_h:
2072 case Intrinsic::mips_min_u_w:
2073 case Intrinsic::mips_min_u_d:
2076 case Intrinsic::mips_mini_s_b:
2077 case Intrinsic::mips_mini_s_h:
2078 case Intrinsic::mips_mini_s_w:
2079 case Intrinsic::mips_mini_s_d:
2082 case Intrinsic::mips_mini_u_b:
2083 case Intrinsic::mips_mini_u_h:
2084 case Intrinsic::mips_mini_u_w:
2085 case Intrinsic::mips_mini_u_d:
2088 case Intrinsic::mips_mod_s_b:
2089 case Intrinsic::mips_mod_s_h:
2090 case Intrinsic::mips_mod_s_w:
2091 case Intrinsic::mips_mod_s_d:
2094 case Intrinsic::mips_mod_u_b:
2095 case Intrinsic::mips_mod_u_h:
2096 case Intrinsic::mips_mod_u_w:
2097 case Intrinsic::mips_mod_u_d:
2100 case Intrinsic::mips_mulv_b:
2101 case Intrinsic::mips_mulv_h:
2102 case Intrinsic::mips_mulv_w:
2103 case Intrinsic::mips_mulv_d:
2106 case Intrinsic::mips_msubv_b:
2107 case Intrinsic::mips_msubv_h:
2108 case Intrinsic::mips_msubv_w:
2109 case Intrinsic::mips_msubv_d: {
2115 case Intrinsic::mips_nlzc_b:
2116 case Intrinsic::mips_nlzc_h:
2117 case Intrinsic::mips_nlzc_w:
2118 case Intrinsic::mips_nlzc_d:
2120 case Intrinsic::mips_nor_v: {
2125 case Intrinsic::mips_nori_b: {
2131 case Intrinsic::mips_or_v:
2134 case Intrinsic::mips_ori_b:
2137 case Intrinsic::mips_pckev_b:
2138 case Intrinsic::mips_pckev_h:
2139 case Intrinsic::mips_pckev_w:
2140 case Intrinsic::mips_pckev_d:
2143 case Intrinsic::mips_pckod_b:
2144 case Intrinsic::mips_pckod_h:
2145 case Intrinsic::mips_pckod_w:
2146 case Intrinsic::mips_pckod_d:
2149 case Intrinsic::mips_pcnt_b:
2150 case Intrinsic::mips_pcnt_h:
2151 case Intrinsic::mips_pcnt_w:
2152 case Intrinsic::mips_pcnt_d:
2154 case Intrinsic::mips_sat_s_b:
2155 case Intrinsic::mips_sat_s_h:
2156 case Intrinsic::mips_sat_s_w:
2157 case Intrinsic::mips_sat_s_d:
2158 case Intrinsic::mips_sat_u_b:
2159 case Intrinsic::mips_sat_u_h:
2160 case Intrinsic::mips_sat_u_w:
2161 case Intrinsic::mips_sat_u_d: {
2164 switch (Intrinsic) {
2165 case Intrinsic::mips_sat_s_b:
2166 case Intrinsic::mips_sat_u_b: Max = 7;
break;
2167 case Intrinsic::mips_sat_s_h:
2168 case Intrinsic::mips_sat_u_h: Max = 15;
break;
2169 case Intrinsic::mips_sat_s_w:
2170 case Intrinsic::mips_sat_u_w: Max = 31;
break;
2171 case Intrinsic::mips_sat_s_d:
2172 case Intrinsic::mips_sat_u_d: Max = 63;
break;
2175 int64_t Value = cast<ConstantSDNode>(Op->
getOperand(2))->getSExtValue();
2180 case Intrinsic::mips_shf_b:
2181 case Intrinsic::mips_shf_h:
2182 case Intrinsic::mips_shf_w: {
2183 int64_t Value = cast<ConstantSDNode>(Op->
getOperand(2))->getSExtValue();
2189 case Intrinsic::mips_sldi_b:
2190 case Intrinsic::mips_sldi_h:
2191 case Intrinsic::mips_sldi_w:
2192 case Intrinsic::mips_sldi_d: {
2195 switch (Intrinsic) {
2196 case Intrinsic::mips_sldi_b: Max = 15;
break;
2197 case Intrinsic::mips_sldi_h: Max = 7;
break;
2198 case Intrinsic::mips_sldi_w: Max = 3;
break;
2199 case Intrinsic::mips_sldi_d: Max = 1;
break;
2202 int64_t Value = cast<ConstantSDNode>(Op->
getOperand(3))->getSExtValue();
2207 case Intrinsic::mips_sll_b:
2208 case Intrinsic::mips_sll_h:
2209 case Intrinsic::mips_sll_w:
2210 case Intrinsic::mips_sll_d:
2213 case Intrinsic::mips_slli_b:
2214 case Intrinsic::mips_slli_h:
2215 case Intrinsic::mips_slli_w:
2216 case Intrinsic::mips_slli_d:
2219 case Intrinsic::mips_splat_b:
2220 case Intrinsic::mips_splat_h:
2221 case Intrinsic::mips_splat_w:
2222 case Intrinsic::mips_splat_d:
2230 case Intrinsic::mips_splati_b:
2231 case Intrinsic::mips_splati_h:
2232 case Intrinsic::mips_splati_w:
2233 case Intrinsic::mips_splati_d:
2237 case Intrinsic::mips_sra_b:
2238 case Intrinsic::mips_sra_h:
2239 case Intrinsic::mips_sra_w:
2240 case Intrinsic::mips_sra_d:
2243 case Intrinsic::mips_srai_b:
2244 case Intrinsic::mips_srai_h:
2245 case Intrinsic::mips_srai_w:
2246 case Intrinsic::mips_srai_d:
2249 case Intrinsic::mips_srari_b:
2250 case Intrinsic::mips_srari_h:
2251 case Intrinsic::mips_srari_w:
2252 case Intrinsic::mips_srari_d: {
2255 switch (Intrinsic) {
2256 case Intrinsic::mips_srari_b: Max = 7;
break;
2257 case Intrinsic::mips_srari_h: Max = 15;
break;
2258 case Intrinsic::mips_srari_w: Max = 31;
break;
2259 case Intrinsic::mips_srari_d: Max = 63;
break;
2262 int64_t Value = cast<ConstantSDNode>(Op->
getOperand(2))->getSExtValue();
2267 case Intrinsic::mips_srl_b:
2268 case Intrinsic::mips_srl_h:
2269 case Intrinsic::mips_srl_w:
2270 case Intrinsic::mips_srl_d:
2273 case Intrinsic::mips_srli_b:
2274 case Intrinsic::mips_srli_h:
2275 case Intrinsic::mips_srli_w:
2276 case Intrinsic::mips_srli_d:
2279 case Intrinsic::mips_srlri_b:
2280 case Intrinsic::mips_srlri_h:
2281 case Intrinsic::mips_srlri_w:
2282 case Intrinsic::mips_srlri_d: {
2285 switch (Intrinsic) {
2286 case Intrinsic::mips_srlri_b: Max = 7;
break;
2287 case Intrinsic::mips_srlri_h: Max = 15;
break;
2288 case Intrinsic::mips_srlri_w: Max = 31;
break;
2289 case Intrinsic::mips_srlri_d: Max = 63;
break;
2292 int64_t Value = cast<ConstantSDNode>(Op->
getOperand(2))->getSExtValue();
2297 case Intrinsic::mips_subv_b:
2298 case Intrinsic::mips_subv_h:
2299 case Intrinsic::mips_subv_w:
2300 case Intrinsic::mips_subv_d:
2303 case Intrinsic::mips_subvi_b:
2304 case Intrinsic::mips_subvi_h:
2305 case Intrinsic::mips_subvi_w:
2306 case Intrinsic::mips_subvi_d:
2309 case Intrinsic::mips_vshf_b:
2310 case Intrinsic::mips_vshf_h:
2311 case Intrinsic::mips_vshf_w:
2312 case Intrinsic::mips_vshf_d:
2315 case Intrinsic::mips_xor_v:
2318 case Intrinsic::mips_xori_b:
2321 case Intrinsic::thread_pointer: {
2350 unsigned Intr = cast<ConstantSDNode>(Op->
getOperand(1))->getZExtValue();
2354 case Intrinsic::mips_extp:
2356 case Intrinsic::mips_extpdp:
2358 case Intrinsic::mips_extr_w:
2360 case Intrinsic::mips_extr_r_w:
2362 case Intrinsic::mips_extr_rs_w:
2364 case Intrinsic::mips_extr_s_h:
2366 case Intrinsic::mips_mthlip:
2368 case Intrinsic::mips_mulsaq_s_w_ph:
2370 case Intrinsic::mips_maq_s_w_phl:
2372 case Intrinsic::mips_maq_s_w_phr:
2374 case Intrinsic::mips_maq_sa_w_phl:
2376 case Intrinsic::mips_maq_sa_w_phr:
2378 case Intrinsic::mips_dpaq_s_w_ph:
2380 case Intrinsic::mips_dpsq_s_w_ph:
2382 case Intrinsic::mips_dpaq_sa_l_w:
2384 case Intrinsic::mips_dpsq_sa_l_w:
2386 case Intrinsic::mips_dpaqx_s_w_ph:
2388 case Intrinsic::mips_dpaqx_sa_w_ph:
2390 case Intrinsic::mips_dpsqx_s_w_ph:
2392 case Intrinsic::mips_dpsqx_sa_w_ph:
2394 case Intrinsic::mips_ld_b:
2395 case Intrinsic::mips_ld_h:
2396 case Intrinsic::mips_ld_w:
2397 case Intrinsic::mips_ld_d:
2425 unsigned Intr = cast<ConstantSDNode>(Op->
getOperand(1))->getZExtValue();
2429 case Intrinsic::mips_st_b:
2430 case Intrinsic::mips_st_h:
2431 case Intrinsic::mips_st_w:
2432 case Intrinsic::mips_st_d:
2443 assert(nOps > 1 &&
"isSplatVector has 0 or 1 sized build vector");
2447 for (
unsigned int i = 1;
i < nOps; ++
i) {
2462 SDValue MipsSETargetLowering::
2485 if (isa<ConstantSDNode>(Op))
2487 if (isa<ConstantFPSDNode>(Op))
2517 APInt SplatValue, SplatUndef;
2518 unsigned SplatBitSize;
2528 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2536 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.
isSignedIntN(10))
2541 switch (SplatBitSize) {
2562 if (ViaVecTy != ResTy)
2578 for (
unsigned i = 0;
i < NumElts; ++
i) {
2610 int SHFIndices[4] = { -1, -1, -1, -1 };
2612 if (Indices.
size() < 4)
2615 for (
unsigned i = 0;
i < 4; ++
i) {
2616 for (
unsigned j =
i; j < Indices.
size(); j += 4) {
2617 int Idx = Indices[j];
2623 if (Idx < 0 || Idx >= 4)
2629 if (SHFIndices[
i] == -1)
2630 SHFIndices[
i] = Idx;
2634 if (!(Idx == -1 || Idx == SHFIndices[
i]))
2641 for (
int i = 3;
i >= 0; --
i) {
2642 int Idx = SHFIndices[
i];
2658 template <
typename ValType>
2661 unsigned CheckStride,
2663 ValType ExpectedIndex,
unsigned ExpectedIndexStride) {
2667 if (*I != -1 && *I != ExpectedIndex)
2669 ExpectedIndex += ExpectedIndexStride;
2673 for (
unsigned n = 0; n < CheckStride && I !=
End; ++n, ++
I)
2692 int SplatIndex = -1;
2693 for (
const auto &V : Indices) {
2700 return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2726 const auto &Begin = Indices.
begin();
2727 const auto &
End = Indices.
end();
2731 if (fitsRegularPattern<int>(Begin, 2,
End, 0, 2))
2733 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size(), 2))
2740 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 0, 2))
2742 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size(), 2))
2772 const auto &Begin = Indices.
begin();
2773 const auto &
End = Indices.
end();
2777 if (fitsRegularPattern<int>(Begin, 2,
End, 1, 2))
2779 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size() + 1, 2))
2786 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 1, 2))
2788 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size() + 1, 2))
2819 const auto &Begin = Indices.
begin();
2820 const auto &
End = Indices.
end();
2824 if (fitsRegularPattern<int>(Begin, 2,
End, 0, 1))
2826 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size(), 1))
2833 if (fitsRegularPattern<int>(Begin + 1, 2,
End, 0, 1))
2835 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size(), 1))
2864 unsigned HalfSize = Indices.
size() / 2;
2867 const auto &Begin = Indices.
begin();
2868 const auto &
End = Indices.
end();
2872 if (fitsRegularPattern<int>(Begin, 2,
End, HalfSize, 1))
2874 else if (fitsRegularPattern<int>(Begin, 2,
End, Indices.
size() + HalfSize, 1))
2881 if (fitsRegularPattern<int>(Begin + 1, 2,
End, HalfSize, 1))
2883 else if (fitsRegularPattern<int>(Begin + 1, 2,
End, Indices.
size() + HalfSize,
2914 const auto &Begin = Indices.
begin();
2915 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2916 const auto &
End = Indices.
end();
2918 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2920 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size(), 2))
2925 if (fitsRegularPattern<int>(Mid, 1,
End, 0, 2))
2927 else if (fitsRegularPattern<int>(Mid, 1,
End, Indices.
size(), 2))
2957 const auto &Begin = Indices.
begin();
2958 const auto &Mid = Indices.
begin() + Indices.
size() / 2;
2959 const auto &
End = Indices.
end();
2961 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2963 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.
size() + 1, 2))
2968 if (fitsRegularPattern<int>(Mid, 1,
End, 1, 2))
2970 else if (fitsRegularPattern<int>(Mid, 1,
End, Indices.
size() + 1, 2))
2994 bool Using1stVec =
false;
2995 bool Using2ndVec =
false;
2999 for (
int i = 0;
i < ResTyNumElts; ++
i) {
3001 int Idx = Indices[
i];
3003 if (0 <= Idx && Idx < ResTyNumElts)
3005 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
3015 if (Using1stVec && Using2ndVec) {
3018 }
else if (Using1stVec)
3020 else if (Using2ndVec)
3023 llvm_unreachable(
"shuffle vector mask references neither vector operand?");
3042 if (!ResTy.is128BitVector())
3045 int ResTyNumElts = ResTy.getVectorNumElements();
3048 for (
int i = 0;
i < ResTyNumElts; ++
i)
3115 BuildMI(BB, DL, TII->
get(Mips::BPOSGE32)).addMBB(TBB);
3117 BuildMI(BB, DL, TII->
get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3122 .addReg(Mips::ZERO).
addImm(0);
3128 .addReg(Mips::ZERO).
addImm(1);
3191 .addReg(Mips::ZERO).
addImm(0);
3197 .addReg(Mips::ZERO).
addImm(1);
3238 BuildMI(*BB, MI, DL, TII->
get(Mips::COPY), Wt).addReg(Ws);
3241 BuildMI(*BB, MI, DL, TII->
get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3245 &Mips::MSA128WEvensRegClass);
3247 BuildMI(*BB, MI, DL, TII->
get(Mips::SPLATI_W), Wt).addReg(Ws).
addImm(Lane);
3248 BuildMI(*BB, MI, DL, TII->
get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3278 BuildMI(*BB, MI, DL, TII->
get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3283 BuildMI(*BB, MI, DL, TII->
get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3308 &Mips::MSA128WEvensRegClass);
3310 BuildMI(*BB, MI, DL, TII->
get(Mips::SUBREG_TO_REG), Wt)
3314 BuildMI(*BB, MI, DL, TII->
get(Mips::INSVE_W), Wd)
3344 BuildMI(*BB, MI, DL, TII->
get(Mips::SUBREG_TO_REG), Wt)
3348 BuildMI(*BB, MI, DL, TII->
get(Mips::INSVE_D), Wd)
3395 unsigned EltLog2Size;
3396 unsigned InsertOp = 0;
3397 unsigned InsveOp = 0;
3398 switch (EltSizeInBytes) {
3403 InsertOp = Mips::INSERT_B;
3404 InsveOp = Mips::INSVE_B;
3405 VecRC = &Mips::MSA128BRegClass;
3409 InsertOp = Mips::INSERT_H;
3410 InsveOp = Mips::INSVE_H;
3411 VecRC = &Mips::MSA128HRegClass;
3415 InsertOp = Mips::INSERT_W;
3416 InsveOp = Mips::INSVE_W;
3417 VecRC = &Mips::MSA128WRegClass;
3421 InsertOp = Mips::INSERT_D;
3422 InsveOp = Mips::INSVE_D;
3423 VecRC = &Mips::MSA128DRegClass;
3429 BuildMI(*BB, MI, DL, TII->
get(Mips::SUBREG_TO_REG), Wt)
3432 .
addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3437 if (EltSizeInBytes != 1) {
3439 BuildMI(*BB, MI, DL, TII->
get(ShiftOp), LaneTmp1)
3447 BuildMI(*BB, MI, DL, TII->
get(Mips::SLD_B), WdTmp1)
3450 .
addReg(LaneReg, 0, SubRegIdx);
3455 BuildMI(*BB, MI, DL, TII->
get(InsveOp), WdTmp2)
3462 BuildMI(*BB, MI, DL, TII->
get(InsertOp), WdTmp2)
3476 BuildMI(*BB, MI, DL, TII->
get(Mips::SLD_B), Wd)
3479 .
addReg(LaneTmp2, 0, SubRegIdx);
3502 : &Mips::MSA128WEvensRegClass);
3505 : &Mips::MSA128WEvensRegClass);
3507 BuildMI(*BB, MI, DL, TII->
get(Mips::IMPLICIT_DEF), Wt1);
3508 BuildMI(*BB, MI, DL, TII->
get(Mips::INSERT_SUBREG), Wt2)
3538 BuildMI(*BB, MI, DL, TII->
get(Mips::IMPLICIT_DEF), Wt1);
3539 BuildMI(*BB, MI, DL, TII->
get(Mips::INSERT_SUBREG), Wt2)
3561 MipsSETargetLowering::emitST_F16_PSEUDO(
MachineInstr &MI,
3578 : &Mips::GPR64RegClass);
3579 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3583 BuildMI(*BB, MI, DL, TII->
get(UsingMips32 ? Mips::SH : Mips::SH64))
3609 MipsSETargetLowering::emitLD_F16_PSEUDO(
MachineInstr &MI,
3623 : &Mips::GPR64RegClass);
3625 const bool UsingMips32 = RC == &Mips::GPR32RegClass;
3629 BuildMI(*BB, MI, DL, TII->
get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3633 BuildMI(*BB, MI, DL, TII->
get(Mips::FILL_H), Wd).addReg(Rt);
3690 MipsSETargetLowering::emitFPROUND_PSEUDO(
MachineInstr &MI,
3692 bool IsFGR64)
const {
3709 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3710 unsigned MFC1Opc = IsFGR64onMips64 ? Mips::DMFC1 : Mips::MFC1;
3711 unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W;
3715 BuildMI(*BB, MI, DL, TII->
get(MFC1Opc), Rtemp).addReg(Fs);
3716 BuildMI(*BB, MI, DL, TII->
get(FILLOpc), Wtemp).addReg(Rtemp);
3717 unsigned WPHI = Wtemp;
3721 BuildMI(*BB, MI, DL, TII->
get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3724 BuildMI(*BB, MI, DL, TII->
get(Mips::INSERT_W), Wtemp2)
3728 BuildMI(*BB, MI, DL, TII->
get(Mips::INSERT_W), Wtemp3)
3737 BuildMI(*BB, MI, DL, TII->
get(Mips::FEXDO_W), Wtemp2)
3743 BuildMI(*BB, MI, DL, TII->
get(Mips::FEXDO_H), Wd).addReg(WPHI).
addReg(WPHI);
3793 MipsSETargetLowering::emitFPEXTEND_PSEUDO(
MachineInstr &MI,
3795 bool IsFGR64)
const {
3812 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
3813 unsigned MTC1Opc = IsFGR64onMips64 ? Mips::DMTC1 : Mips::MTC1;
3814 unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3817 unsigned WPHI = Wtemp;
3819 BuildMI(*BB, MI, DL, TII->
get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3822 BuildMI(*BB, MI, DL, TII->
get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3827 unsigned FPRPHI = IsFGR64onMips32
3831 BuildMI(*BB, MI, DL, TII->
get(MTC1Opc), FPRPHI).addReg(Rtemp);
3833 if (IsFGR64onMips32) {
3835 BuildMI(*BB, MI, DL, TII->
get(Mips::COPY_S_W), Rtemp2)
3838 BuildMI(*BB, MI, DL, TII->
get(Mips::MTHC1_D64), Fd)
3864 BuildMI(*BB, MI, DL, TII->
get(Mips::LDI_W), Ws1).addImm(1);
3865 BuildMI(*BB, MI, DL, TII->
get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3893 BuildMI(*BB, MI, DL, TII->
get(Mips::LDI_D), Ws1).addImm(1);
3894 BuildMI(*BB, MI, DL, TII->
get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
value_iterator value_begin() const
unsigned getIncomingArgSize() const
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
void push_back(const T &Elt)
BUILTIN_OP_END - This must be the last enum value in this list.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Flags getFlags() const
Return the raw flags of the source value,.
uint64_t getZExtValue() const
Get zero extended value.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
const MipsSubtarget & Subtarget
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG)
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDVTList getVTList() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Carry-setting nodes for multiple precision addition and subtraction.
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
const MipsInstrInfo * getInstrInfo() const override
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
unsigned getInRegsParamsCount() const
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the 'representative' register class for the specified value type.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
unsigned getResNo() const
get the index which selects a specific result in the SDNode
bool isUndef() const
Return true if the type of the node type undefined.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
bool isVector() const
isVector - Return true if this is a vector value type.
static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
A description of a memory reference used in the backend.
const HexagonInstrInfo * TII
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG)
static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op)
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
int getMaskElt(unsigned Idx) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector...
static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
value_iterator value_end() const
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
Simple integer binary arithmetic operators.
static bool isConstantOrUndef(const SDValue Op)
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
TargetInstrInfo - Interface to description of machine instruction set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getScalarSizeInBits() const
initializer< Ty > init(const Ty &Val)
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
APInt trunc(unsigned width) const
Truncate to new width.
static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
MVT - Machine Value Type.
LLVM Basic Block Representation.
static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget)
static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG)
const SDValue & getOperand(unsigned i) const
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC)
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const MachineOperand & getOperand(unsigned i) const
Carry-using nodes for multiple precision addition and subtraction.
static bool isVectorAllOnes(SDValue N)
static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
constexpr bool isPowerOf2_64(uint64_t Value)
isPowerOf2_64 - This function returns true if the argument is a power of two 0 (64 bit edition...
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
unsigned getBitWidth() const
Return the number of bits in the APInt.
static const unsigned End
unsigned getOpcode() const
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static mvt_range vector_valuetypes()
bool useSoftFloat() const
const SDValue & getValue() const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
EVT - Extended Value Type.
static bool fitsRegularPattern(typename SmallVectorImpl< ValType >::const_iterator Begin, unsigned CheckStride, typename SmallVectorImpl< ValType >::const_iterator End, ValType ExpectedIndex, unsigned ExpectedIndexStride)
Determine whether a range fits a regular pattern of values.
This class contains a discriminated union of information about pointers in memory operands...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG)
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef...
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
ValType
This is used to indicate local types.
const MipsRegisterInfo * getRegisterInfo() const override
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL)
double Log2(double Value)
Log2 - This function returns the log base 2 of the specified value.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
BRCOND - Conditional branch.
const SDValue & getChain() const
static SDValue genConstMult(SDValue X, uint64_t C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG)
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc)
Represents one node in the SelectionDAG.
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned Log2_64_Ceil(uint64_t Value)
Log2_64_Ceil - This function returns the ceil log base 2 of the specified value, 64 if the value is z...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Class for arbitrary precision integers.
static bool isSplatVector(const BuildVectorSDNode *N)
Check if the given BuildVectorSDNode is a splat.
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
Select(COND, TRUEVAL, FALSEVAL).
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG)
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that when a single input is NaN...
static bool isBitwiseInverse(SDValue N, SDValue OfNode)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
bool isAllOnesValue() const
Determine if all bits are set.
Representation of each machine instruction.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Bitwise operators - logical and, logical or, logical xor.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
bool isSingleFloat() const
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian)
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
FSINCOS - Compute both fsin and fcos as a single operation.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void printrWithDepth(raw_ostream &O, const SelectionDAG *G=nullptr, unsigned depth=100) const
Print a SelectionDAG node and children up to depth "depth." The given SelectionDAG allows target-spec...
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
uint64_t getSize() const
Return the size in bytes of the memory reference.
static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static SDValue extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG)
static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static cl::opt< bool > UseMipsTailCalls("mips-tail-calls", cl::Hidden, cl::desc("MIPS: permit tail calls."), cl::init(false))
SetCC operator - This evaluates to a true value iff the condition is true.
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG)
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
unsigned Log2_64(uint64_t Value)
Log2_64 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
static cl::opt< bool > NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and ""stores to their single precision ""counterparts"))
static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector< int, 16 > Indices, SelectionDAG &DAG)
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
uint64_t getZExtValue() const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.