43 #define GET_REGINFO_TARGET_DESC
44 #include "X86GenRegisterInfo.inc"
48 cl::desc(
"Enable use of a base pointer for complex stack frames"));
54 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
70 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
71 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
72 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
89 return getEncodingValue(i);
97 if (!Is64Bit && Idx == X86::sub_8bit)
98 Idx = X86::sub_8bit_hi;
101 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
107 unsigned SubIdx)
const {
109 if (!Is64Bit && SubIdx == X86::sub_8bit) {
110 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
114 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
128 if (RC == &X86::GR8_NOREXRegClass)
136 switch (Super->getID()) {
137 case X86::FR32RegClassID:
138 case X86::FR64RegClassID:
143 case X86::VR128RegClassID:
144 case X86::VR256RegClassID:
146 if (!Subtarget.
hasVLX() && Super->getSize() == RC->
getSize())
149 case X86::VR128XRegClassID:
150 case X86::VR256XRegClassID:
155 case X86::FR32XRegClassID:
156 case X86::FR64XRegClassID:
161 case X86::GR8RegClassID:
162 case X86::GR16RegClassID:
163 case X86::GR32RegClassID:
164 case X86::GR64RegClassID:
165 case X86::RFP32RegClassID:
166 case X86::RFP64RegClassID:
167 case X86::RFP80RegClassID:
168 case X86::VR512RegClassID:
171 if (Super->getSize() == RC->
getSize())
181 unsigned Kind)
const {
187 return &X86::GR64RegClass;
197 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
198 : &X86::LOW32_ADDR_ACCESSRegClass;
200 return &X86::GR32RegClass;
203 return &X86::GR64_NOSPRegClass;
205 return &X86::GR32_NOSPRegClass;
208 return &X86::GR64_NOREXRegClass;
209 return &X86::GR32_NOREXRegClass;
212 return &X86::GR64_NOREX_NOSPRegClass;
214 return &X86::GR32_NOREX_NOSPRegClass;
224 return &X86::GR64_TCW64RegClass;
226 return &X86::GR64_TCRegClass;
230 return &X86::GR32RegClass;
231 return &X86::GR32_TCRegClass;
236 if (RC == &X86::CCRRegClass) {
238 return &X86::GR64RegClass;
240 return &X86::GR32RegClass;
250 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
251 switch (RC->
getID()) {
254 case X86::GR32RegClassID:
256 case X86::GR64RegClassID:
258 case X86::VR128RegClassID:
259 return Is64Bit ? 10 : 4;
260 case X86::VR64RegClassID:
267 assert(MF &&
"MachineFunction required");
270 bool HasSSE = Subtarget.
hasSSE1();
271 bool HasAVX = Subtarget.
hasAVX();
278 return CSR_NoRegs_SaveList;
281 return CSR_64_AllRegs_AVX_SaveList;
282 return CSR_64_AllRegs_SaveList;
284 return CSR_64_RT_MostRegs_SaveList;
287 return CSR_64_RT_AllRegs_AVX_SaveList;
288 return CSR_64_RT_AllRegs_SaveList;
292 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
295 if (HasAVX512 && IsWin64)
296 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
297 if (HasAVX512 && Is64Bit)
298 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
299 if (HasAVX && IsWin64)
300 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
301 if (HasAVX && Is64Bit)
302 return CSR_64_Intel_OCL_BI_AVX_SaveList;
303 if (!HasAVX && !IsWin64 && Is64Bit)
304 return CSR_64_Intel_OCL_BI_SaveList;
308 return CSR_64_HHVM_SaveList;
312 return (HasSSE ? CSR_Win64_RegCall_SaveList :
313 CSR_Win64_RegCall_NoSSE_SaveList);
315 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
316 CSR_SysV64_RegCall_NoSSE_SaveList);
319 return (HasSSE ? CSR_32_RegCall_SaveList :
320 CSR_32_RegCall_NoSSE_SaveList);
324 return CSR_64_MostRegs_SaveList;
328 return CSR_Win64_NoSSE_SaveList;
329 return CSR_Win64_SaveList;
332 return CSR_64EHRet_SaveList;
333 return CSR_64_SaveList;
337 return CSR_64_AllRegs_AVX512_SaveList;
339 return CSR_64_AllRegs_AVX_SaveList;
340 return CSR_64_AllRegs_SaveList;
343 return CSR_32_AllRegs_AVX512_SaveList;
345 return CSR_32_AllRegs_AVX_SaveList;
347 return CSR_32_AllRegs_SSE_SaveList;
348 return CSR_32_AllRegs_SaveList;
357 return CSR_Win64_NoSSE_SaveList;
358 return CSR_Win64_SaveList;
361 return CSR_64EHRet_SaveList;
364 Attribute::SwiftError))
365 return CSR_64_SwiftError_SaveList;
366 return CSR_64_SaveList;
369 return CSR_32EHRet_SaveList;
370 return CSR_32_SaveList;
375 assert(MF &&
"Invalid MachineFunction pointer.");
378 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
386 bool HasSSE = Subtarget.
hasSSE1();
387 bool HasAVX = Subtarget.
hasAVX();
393 return CSR_NoRegs_RegMask;
396 return CSR_64_AllRegs_AVX_RegMask;
397 return CSR_64_AllRegs_RegMask;
399 return CSR_64_RT_MostRegs_RegMask;
402 return CSR_64_RT_AllRegs_AVX_RegMask;
403 return CSR_64_RT_AllRegs_RegMask;
406 return CSR_64_TLS_Darwin_RegMask;
409 if (HasAVX512 && IsWin64)
410 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
411 if (HasAVX512 && Is64Bit)
412 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
413 if (HasAVX && IsWin64)
414 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
415 if (HasAVX && Is64Bit)
416 return CSR_64_Intel_OCL_BI_AVX_RegMask;
417 if (!HasAVX && !IsWin64 && Is64Bit)
418 return CSR_64_Intel_OCL_BI_RegMask;
422 return CSR_64_HHVM_RegMask;
426 return (HasSSE ? CSR_Win64_RegCall_RegMask :
427 CSR_Win64_RegCall_NoSSE_RegMask);
429 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
430 CSR_SysV64_RegCall_NoSSE_RegMask);
433 return (HasSSE ? CSR_32_RegCall_RegMask :
434 CSR_32_RegCall_NoSSE_RegMask);
438 return CSR_64_MostRegs_RegMask;
441 return CSR_Win64_RegMask;
443 return CSR_64_RegMask;
447 return CSR_64_AllRegs_AVX512_RegMask;
449 return CSR_64_AllRegs_AVX_RegMask;
450 return CSR_64_AllRegs_RegMask;
453 return CSR_32_AllRegs_AVX512_RegMask;
455 return CSR_32_AllRegs_AVX_RegMask;
457 return CSR_32_AllRegs_SSE_RegMask;
458 return CSR_32_AllRegs_RegMask;
468 return CSR_Win64_RegMask;
471 Attribute::SwiftError))
472 return CSR_64_SwiftError_RegMask;
473 return CSR_64_RegMask;
475 return CSR_32_RegMask;
480 return CSR_NoRegs_RegMask;
484 return CSR_64_TLS_Darwin_RegMask;
502 if (TFI->
hasFP(MF)) {
514 "Stack realignment in presence of dynamic allocas is not supported with"
515 "this calling convention.");
524 Reserved.
set(X86::CS);
525 Reserved.
set(X86::SS);
526 Reserved.
set(X86::DS);
527 Reserved.
set(X86::ES);
528 Reserved.
set(X86::FS);
529 Reserved.
set(X86::GS);
532 for (
unsigned n = 0; n != 8; ++n)
533 Reserved.
set(X86::ST0 + n);
539 Reserved.
set(X86::SIL);
540 Reserved.
set(X86::DIL);
541 Reserved.
set(X86::BPL);
542 Reserved.
set(X86::SPL);
544 for (
unsigned n = 0; n != 8; ++n) {
555 for (
unsigned n = 16; n != 32; ++n) {
561 assert(checkAllSuperRegsMarked(Reserved,
562 {X86::SIL, X86::DIL, X86::BPL, X86::SPL}));
574 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
575 "EFLAGS are not live-out from a patchpoint.");
578 for (
auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
579 Mask[
Reg / 32] &= ~(1U << (
Reg % 32));
601 bool CantUseFP = needsStackRealignment(MF);
625 unsigned Reg,
int &FrameIdx)
const {
637 unsigned Opc = II->getOpcode();
639 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
649 if (Opc == X86::LEA64_32r)
662 int SPAdj,
unsigned FIOperandNum,
671 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
672 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
676 else if (needsStackRealignment(MF))
677 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
681 BasePtr = (TFI->
hasFP(MF) ? FramePtr : StackPtr);
688 unsigned IgnoredFrameReg;
689 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
701 unsigned MachineBasePtr = BasePtr;
702 if (Opc == X86::LEA64_32r && X86::GR32RegClass.
contains(BasePtr))
718 if (BasePtr == StackPtr)
723 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
724 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
733 int Offset = FIOffset + Imm;
735 "Requesting 64-bit offset in 32-bit immediate!");
740 uint64_t
Offset = FIOffset +
748 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
bool hasBasePointer(const MachineFunction &MF) const
bool callsEHReturn() const
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
return AArch64::GPR64RegClass contains(Reg)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool isOSWindows() const
Tests whether the OS is Windows.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
const uint32_t * getDarwinTLSCallPreservedMask() const
X86_INTR - x86 hardware interrupt context.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
Register calling convention used for parameters transfer optimization.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isArch64Bit() const
Test whether the architecture is 64-bit.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
Function Alias Analysis false
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
const X86TargetLowering * getTargetLowering() const override
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override
initializer< Ty > init(const Ty &Val)
unsigned const MachineRegisterInfo * MRI
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
Code Generation virtual methods...
const uint32_t * getNoPreservedMask() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
MCRegAliasIterator enumerates all registers aliasing Reg.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
int64_t getOffset() const
Return the offset from the symbol in this operand.
void setOffset(int64_t Offset)
const TargetRegisterClass *const * sc_iterator
MCSubRegIterator enumerates all sub-registers of Reg.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getBaseRegister() const
Triple - Helper class for working with autoconf configuration names.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
constexpr bool isInt< 32 >(int64_t x)
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
MachineOperand class - Representation of each machine instruction operand.
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
int getSEHRegNum(unsigned i) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
AttributeSet getAttributes() const
Return the attribute list for this Function.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
The C convention as implemented on Windows/x86-64.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool canRealignStack(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
static bool CantUseSP(const MachineFrameInfo &MFI)
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
unsigned getFrameRegister(const MachineFunction &MF) const override
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const