LLVM  4.0.0
RegisterBank.cpp
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1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegisterBank class.
11 //===----------------------------------------------------------------------===//
12 
15 
16 #define DEBUG_TYPE "registerbank"
17 
18 using namespace llvm;
19 
20 const unsigned RegisterBank::InvalidID = UINT_MAX;
21 
22 RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
23  const uint32_t *CoveredClasses)
24  : ID(ID), Name(Name), Size(Size) {
25  ContainedRegClasses.resize(200);
26  ContainedRegClasses.setBitsInMask(CoveredClasses);
27 }
28 
29 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
30  assert(isValid() && "Invalid register bank");
31  for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
32  const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
33 
34  if (!covers(RC))
35  continue;
36  // Verify that the register bank covers all the sub classes of the
37  // classes it covers.
38 
39  // Use a different (slow in that case) method than
40  // RegisterBankInfo to find the subclasses of RC, to make sure
41  // both agree on the covers.
42  for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
43  const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
44 
45  if (!RC.hasSubClassEq(&SubRC))
46  continue;
47 
48  // Verify that the Size of the register bank is big enough to cover
49  // all the register classes it covers.
50  assert((getSize() >= SubRC.getSize() * 8) &&
51  "Size is not big enough for all the subclasses!");
52  assert(covers(SubRC) && "Not all subclasses are covered");
53  }
54  }
55  return true;
56 }
57 
59  assert(isValid() && "RB hasn't been initialized yet");
60  return ContainedRegClasses.test(RC.getID());
61 }
62 
63 bool RegisterBank::isValid() const {
64  return ID != InvalidID && Name != nullptr && Size != 0 &&
65  // A register bank that does not cover anything is useless.
66  !ContainedRegClasses.empty();
67 }
68 
69 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
70  // There must be only one instance of a given register bank alive
71  // for the whole compilation.
72  // The RegisterBankInfo is supposed to enforce that.
73  assert((OtherRB.getID() != getID() || &OtherRB == this) &&
74  "ID does not uniquely identify a RegisterBank");
75  return &OtherRB == this;
76 }
77 
79  print(dbgs(), /* IsForDebug */ true, TRI);
80 }
81 
82 void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
83  const TargetRegisterInfo *TRI) const {
84  OS << getName();
85  if (!IsForDebug)
86  return;
87  OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
88  << "isValid:" << isValid() << '\n'
89  << "Number of Covered register classes: " << ContainedRegClasses.count()
90  << '\n';
91  // Print all the subclasses if we can.
92  // This register classes may not be properly initialized yet.
93  if (!TRI || ContainedRegClasses.empty())
94  return;
95  assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
96  "TRI does not match the initialization process?");
97  bool IsFirst = true;
98  OS << "Covered register classes:\n";
99  for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
100  const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
101 
102  if (!covers(RC))
103  continue;
104 
105  if (!IsFirst)
106  OS << ", ";
107  OS << TRI->getRegClassName(&RC);
108  IsFirst = false;
109  }
110 }
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:193
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:119
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:450
void dump(const TargetRegisterInfo *TRI=nullptr) const
Dump the register mask on dbgs() stream.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
unsigned getID() const
Return the register class ID number.
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
RegisterBank(unsigned ID, const char *Name, unsigned Size, const uint32_t *ContainedRegClasses)
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
unsigned getNumRegClasses() const
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:122
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:116
static const unsigned End
void print(raw_ostream &OS, bool IsForDebug=false, const TargetRegisterInfo *TRI=nullptr) const
Print the register mask on OS.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isValid() const
Check whether this instance is ready to be used.
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:52
bool test(unsigned Idx) const
Definition: BitVector.h:323
This class implements the register bank concept.
Definition: RegisterBank.h:29
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
Definition: RegisterBank.h:55
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:483
bool operator==(const RegisterBank &OtherRB) const
Check whether OtherRB is the same as this.