44 #define DEBUG_TYPE "misched"
48 cl::desc(
"Enable use of AA during MI DAG construction"));
61 "prior to scheduling, at which point a trade-off "
62 "is made to avoid excessive compile time."));
66 cl::desc(
"A huge scheduling region will have maps reduced by this many "
67 "nodes at a time. Defaults to HugeRegion / 2."));
78 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
80 for (
const SUnit *su : L) {
81 dbgs() <<
"SU(" << su->NodeNum <<
")";
92 :
ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
93 RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(
false),
94 TrackLaneMasks(
false), AAForDep(nullptr), BarrierChain(nullptr),
96 Type::getVoidTy(mf.getFunction()->getContext()))),
97 FirstDbgValue(nullptr) {
108 if (
const Operator *U = dyn_cast<Operator>(V)) {
111 if (U->getOpcode() == Instruction::PtrToInt)
112 return U->getOperand(0);
120 (!isa<ConstantInt>(U->getOperand(1)) &&
122 !isa<PHINode>(U->getOperand(1))))
124 V = U->getOperand(0);
145 for (
Value *V : Objs) {
146 if (!Visited.
insert(V).second)
156 Objects.
push_back(const_cast<Value *>(V));
158 }
while (!Working.
empty());
168 auto allMMOsOkay = [&]() {
170 if (MMO->isVolatile())
185 if (PSV->isAliased(&MFI))
188 bool MayAlias = PSV->mayAlias(&MFI);
190 }
else if (
const Value *V = MMO->getValue()) {
194 for (
Value *V : Objs) {
226 unsigned regioninstrs) {
227 assert(bb ==
BB &&
"startBlock should set BB");
253 if (!MO.isReg() || MO.isDef())
continue;
254 unsigned Reg = MO.getReg();
266 for (
const auto &LI : Succ->liveins()) {
294 int UseOp =
I->OpIdx;
310 ST.adjustSchedDependency(SU, UseSU, Dep);
347 SDep Dep(SU, Kind, *Alias);
382 for (
bool isBegin = I == B; !isBegin; ) {
383 isBegin = (--
I) == B;
439 "Dead defs should have no uses");
447 if ((LaneMask & KillLaneMask).none()) {
452 if ((LaneMask & DefLaneMask).any()) {
462 LaneMask &= ~KillLaneMask;
464 if (LaneMask.
any()) {
465 I->LaneMask = LaneMask;
487 if ((V2SU.LaneMask & LaneMask).none())
490 SUnit *DefSU = V2SU.SU;
506 LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
507 LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
509 V2SU.LaneMask = OverlapMask;
510 if (NonOverlapMask.
any())
539 if ((PrevDefLaneMask & LaneMask).none())
564 "Dependency checked between two loads");
600 assert ((MMOa->
getOffset() >= 0) &&
"Negative MachineMemOperand offset");
601 assert ((MMOb->
getOffset() >= 0) &&
"Negative MachineMemOperand offset");
644 if (
MI.isDebugValue())
690 unsigned TrueMemOrderLatency;
693 Value2SUsMap(
unsigned lat = 0) : NumNodes(0), TrueMemOrderLatency(lat) {}
711 assert (NumNodes >= Itr->second.size());
712 NumNodes -= Itr->second.size();
724 unsigned inline size()
const {
return NumNodes; }
729 for (
auto &
I : *
this)
730 NumNodes +=
I.second.size();
734 return TrueMemOrderLatency;
742 for (
auto &
I : Val2SUsMap)
744 Val2SUsMap.getTrueMemOrderLatency());
751 if (Itr != Val2SUsMap.
end())
759 for (
auto &
I : map) {
773 SUList &sus = CurrItr->second;
774 SUList::iterator SUItr = sus.begin(), SUEE = sus.end();
775 for (; SUItr != SUEE; ++SUItr) {
788 if (SUItr != sus.begin())
789 sus.erase(sus.begin(), SUItr);
793 map.
remove_if([&](std::pair<ValueType, SUList> &mapEntry) {
794 return (mapEntry.second.empty()); });
807 bool TrackLaneMasks) {
851 "Only BuildGraph should update Defs/Uses");
871 DbgValues.push_back(std::make_pair(DbgMI, &MI));
880 assert(SU &&
"No SUnit mapped to this MI");
885 if (TrackLaneMasks) {
889 if (PDiffs !=
nullptr)
893 assert(&*RPTracker->
getPos() == &MI &&
"RPTracker in sync");
894 RPTracker->
recede(RegOpers);
899 "Cannot schedule terminators or labels!");
906 bool HasVRegDef =
false;
960 DEBUG(
dbgs() <<
"Global memory object and new barrier chain: SU("
1003 bool ThisMayAlias = UnderlObj.mayAlias();
1013 bool ThisMayAlias = UnderlObj.mayAlias();
1016 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
1033 bool ThisMayAlias = UnderlObj.mayAlias();
1040 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
1049 DEBUG(
dbgs() <<
"Reducing Stores and Loads maps.\n";);
1053 DEBUG(
dbgs() <<
"Reducing NonAliasStores and NonAliasLoads maps.\n";);
1068 PSV->printCustom(OS);
1073 for (
auto &Itr : *
this) {
1074 if (Itr.first.is<
const Value*>()) {
1075 const Value *V = Itr.first.get<
const Value*>();
1076 if (isa<UndefValue>(V))
1077 dbgs() <<
"Unknown";
1097 DEBUG(
dbgs() <<
"Before reduction:\nStoring SUnits:\n";
1099 dbgs() <<
"Loading SUnits:\n";
1103 std::vector<unsigned> NodeNums;
1104 NodeNums.reserve(stores.
size() + loads.
size());
1105 for (
auto &
I : stores)
1106 for (
auto *SU :
I.second)
1107 NodeNums.push_back(SU->NodeNum);
1108 for (
auto &
I : loads)
1109 for (
auto *SU :
I.second)
1110 NodeNums.push_back(SU->NodeNum);
1111 std::sort(NodeNums.begin(), NodeNums.end());
1116 assert (N <= NodeNums.size());
1117 SUnit *newBarrierChain = &SUnits[*(NodeNums.end() -
N)];
1123 if (newBarrierChain->NodeNum < BarrierChain->NodeNum) {
1125 BarrierChain = newBarrierChain;
1126 DEBUG(
dbgs() <<
"Inserting new barrier chain: SU("
1127 << BarrierChain->NodeNum <<
").\n";);
1130 DEBUG(
dbgs() <<
"Keeping old barrier chain: SU("
1131 << BarrierChain->NodeNum <<
").\n";);
1134 BarrierChain = newBarrierChain;
1136 insertBarrierChain(stores);
1137 insertBarrierChain(loads);
1139 DEBUG(
dbgs() <<
"After reduction:\nStoring SUnits:\n";
1141 dbgs() <<
"Loading SUnits:\n";
1152 for (
const auto &LI : Succ->liveins()) {
1156 LiveRegs.set(*SubRegs);
1167 if (MI->
getOpcode() != TargetOpcode::BUNDLE)
1176 while (Begin != End) {
1178 if ((--End)->addRegisterKilled(Reg, TRI,
false))
1181 (--End)->clearRegisterKills(Reg, TRI);
1194 if (LiveRegs.test(MO.
getReg())) {
1204 bool AllDead =
true;
1205 const unsigned SuperReg = MO.
getReg();
1208 if (LiveRegs.test(*SubRegs)) {
1225 LiveRegs.resize(TRI->getNumRegs());
1226 BitVector killedRegs(TRI->getNumRegs());
1228 startBlockForKills(MBB);
1231 unsigned Count = MBB->
size();
1244 LiveRegs.clearBitsNotInMask(MO.
getRegMask());
1245 if (!MO.
isReg())
continue;
1247 if (Reg == 0)
continue;
1248 if (!MO.
isDef())
continue;
1255 LiveRegs.reset(*SubRegs);
1271 if ((Reg == 0) ||
MRI.isReserved(Reg))
continue;
1274 if (!killedRegs.test(Reg)) {
1278 if (LiveRegs.test(*SubRegs)) {
1287 kill = !LiveRegs.test(Reg);
1290 if (MO.
isKill() != kill) {
1291 DEBUG(
dbgs() <<
"Fixing " << MO <<
" in ");
1292 toggleKillFlag(&MI, MO);
1295 if (MI.
getOpcode() == TargetOpcode::BUNDLE) {
1298 while (++Begin != End)
1299 DEBUG(Begin->dump());
1304 killedRegs.set(Reg);
1310 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
continue;
1311 unsigned Reg = MO.getReg();
1312 if ((Reg == 0) ||
MRI.isReserved(Reg))
continue;
1316 LiveRegs.set(*SubRegs);
1321 void ScheduleDAGInstrs::dumpNode(
const SUnit *SU)
const {
1322 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1327 std::string ScheduleDAGInstrs::getGraphNodeLabel(
const SUnit *SU)
const {
1332 else if (SU == &ExitSU)
1341 std::string ScheduleDAGInstrs::getDAGName()
const {
1342 return "dag." + BB->getFullName();
1357 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1361 unsigned ParentNodeID;
1362 unsigned SubInstrCount;
1364 RootData(
unsigned id): NodeID(
id),
1365 ParentNodeID(SchedDFSResult::InvalidSubtreeID),
1368 unsigned getSparseSetIndex()
const {
return NodeID; }
1375 RootSet.setUniverse(R.DFSNodeData.size());
1383 return R.DFSNodeData[SU->
NodeNum].SubtreeID
1384 != SchedDFSResult::InvalidSubtreeID;
1390 R.DFSNodeData[SU->
NodeNum].InstrCount =
1411 if (PredDep.
getKind() != SDep::Data)
1414 if ((InstrCount - R.DFSNodeData[PredNum].InstrCount) < R.SubtreeLimit)
1415 joinPredSubtree(PredDep, SU,
false);
1418 if (R.DFSNodeData[PredNum].SubtreeID == PredNum) {
1421 if (RootSet[PredNum].ParentNodeID == SchedDFSResult::InvalidSubtreeID)
1422 RootSet[PredNum].ParentNodeID = SU->
NodeNum;
1424 else if (RootSet.count(PredNum)) {
1429 RData.SubInstrCount += RootSet[PredNum].SubInstrCount;
1430 RootSet.erase(PredNum);
1440 R.DFSNodeData[Succ->
NodeNum].InstrCount
1442 joinPredSubtree(PredDep, Succ);
1447 ConnectionPairs.push_back(std::make_pair(PredDep.
getSUnit(), Succ));
1453 SubtreeClasses.compress();
1454 R.DFSTreeData.resize(SubtreeClasses.getNumClasses());
1455 assert(SubtreeClasses.getNumClasses() == RootSet.size()
1456 &&
"number of roots should match trees");
1457 for (
const RootData &Root : RootSet) {
1458 unsigned TreeID = SubtreeClasses[Root.NodeID];
1459 if (Root.ParentNodeID != SchedDFSResult::InvalidSubtreeID)
1460 R.DFSTreeData[TreeID].ParentTreeID = SubtreeClasses[Root.ParentNodeID];
1461 R.DFSTreeData[TreeID].SubInstrCount = Root.SubInstrCount;
1467 R.SubtreeConnections.resize(SubtreeClasses.getNumClasses());
1468 R.SubtreeConnectLevels.resize(SubtreeClasses.getNumClasses());
1469 DEBUG(
dbgs() << R.getNumSubtrees() <<
" subtrees:\n");
1470 for (
unsigned Idx = 0,
End = R.DFSNodeData.size(); Idx !=
End; ++Idx) {
1471 R.DFSNodeData[Idx].SubtreeID = SubtreeClasses[Idx];
1472 DEBUG(
dbgs() <<
" SU(" << Idx <<
") in tree "
1473 << R.DFSNodeData[Idx].SubtreeID <<
'\n');
1475 for (
const std::pair<const SUnit*, const SUnit*> &
P : ConnectionPairs) {
1476 unsigned PredTree = SubtreeClasses[
P.first->NodeNum];
1477 unsigned SuccTree = SubtreeClasses[
P.second->NodeNum];
1478 if (PredTree == SuccTree)
1480 unsigned Depth =
P.first->getDepth();
1481 addConnection(PredTree, SuccTree, Depth);
1482 addConnection(SuccTree, PredTree, Depth);
1490 bool CheckLimit =
true) {
1491 assert(PredDep.
getKind() == SDep::Data &&
"Subtrees are for data edges");
1495 unsigned PredNum = PredSU->
NodeNum;
1496 if (R.DFSNodeData[PredNum].SubtreeID != PredNum)
1501 unsigned NumDataSucs = 0;
1502 for (
const SDep &SuccDep : PredSU->Succs) {
1503 if (SuccDep.
getKind() == SDep::Data) {
1504 if (++NumDataSucs >= 4)
1508 if (CheckLimit && R.DFSNodeData[PredNum].InstrCount > R.SubtreeLimit)
1510 R.DFSNodeData[PredNum].SubtreeID = Succ->
NodeNum;
1511 SubtreeClasses.join(Succ->
NodeNum, PredNum);
1522 R.SubtreeConnections[FromTree];
1523 for (SchedDFSResult::Connection &
C : Connections) {
1524 if (
C.TreeID == ToTree) {
1525 C.Level = std::max(
C.Level, Depth);
1529 Connections.push_back(SchedDFSResult::Connection(ToTree, Depth));
1530 FromTree = R.DFSTreeData[FromTree].ParentTreeID;
1531 }
while (FromTree != SchedDFSResult::InvalidSubtreeID);
1538 class SchedDAGReverseDFS {
1539 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1541 bool isComplete()
const {
return DFSStack.empty(); }
1543 void follow(
const SUnit *SU) {
1544 DFSStack.push_back(std::make_pair(SU, SU->
Preds.begin()));
1546 void advance() { ++DFSStack.back().second; }
1548 const SDep *backtrack() {
1549 DFSStack.pop_back();
1550 return DFSStack.empty() ?
nullptr : std::prev(DFSStack.back().second);
1553 const SUnit *getCurr()
const {
return DFSStack.back().first; }
1558 return getCurr()->Preds.end();
1565 if (SuccDep.
getKind() == SDep::Data &&
1579 for (
const SUnit &SU : SUnits) {
1583 SchedDAGReverseDFS
DFS;
1588 while (DFS.getPred() != DFS.getPredEnd()) {
1589 const SDep &PredDep = *DFS.getPred();
1592 if (PredDep.
getKind() != SDep::Data
1605 const SUnit *Child = DFS.getCurr();
1606 const SDep *PredDep = DFS.backtrack();
1610 if (DFS.isComplete())
1620 void SchedDFSResult::scheduleTree(
unsigned SubtreeID) {
1621 for (
const Connection &
C : SubtreeConnections[SubtreeID]) {
1622 SubtreeConnectLevels[
C.TreeID] =
1623 std::max(SubtreeConnectLevels[
C.TreeID],
C.Level);
1625 <<
" @" << SubtreeConnectLevels[
C.TreeID] <<
'\n');
1631 OS <<
InstrCount <<
" / " << Length <<
" = ";
1640 dbgs() << *
this <<
'\n';
iterator end()
Returns an iterator past this container.
std::vector< std::pair< ValueType, SUList > >::iterator iterator
void addInstruction(unsigned Idx, const RegisterOperands &RegOpers, const MachineRegisterInfo &MRI)
Record pressure difference induced by the given operand list to node with index Idx.
void print(raw_ostream &OS, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const
void push_back(const T &Elt)
virtual bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
const_iterator end(StringRef path)
Get end iterator over path.
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ, bool CheckLimit=true)
Join the predecessor subtree with the successor that is its DFS parent.
static cl::opt< unsigned > HugeRegion("dag-maps-huge-region", cl::Hidden, cl::init(1000), cl::desc("The limit to use while constructing the DAG ""prior to scheduling, at which point a trade-off ""is made to avoid excessive compile time."))
ValueType & operator[](const SUList &Key)
To keep NumNodes up to date, insert() is used instead of this operator w/ push_back().
iterator insert(const ValueT &Val)
Insert a new element at the tail of the subset list.
void insert(SUnit *SU, ValueType V)
Add SU to the SUList of V.
bool contains(const KeyT &Key) const
Returns true if this set contains an element identified by Key.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
void init(unsigned N)
Initialize an array of N PressureDiffs.
Record a physical register access.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
void addVRegDefDeps(SUnit *SU, unsigned OperIdx)
addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur...
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
bool TrackLaneMasks
Whether lane masks should get tracked.
static LaneBitmask getAll()
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setIsUndef(bool Val=true)
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
Represent the ILP of the subDAG rooted at a DAG node.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti, const TargetInstrInfo *tii)
Initialize the machine model for instruction scheduling.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
MachineBasicBlock::iterator begin() const
begin - Return an iterator to the top of the current scheduling region.
const_iterator begin(StringRef path)
Get begin iterator over path.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
This class implements a map that also provides access to all stored values in a deterministic order...
static void dump(StringRef Title, SpillInfo const &Spills)
const MCSchedClassDesc * getSchedClass(SUnit *SU) const
Resolve and cache a resolved scheduling class for an SUnit.
The two locations do not alias at all.
static cl::opt< bool > EnableAASchedMI("enable-aa-sched-mi", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable use of AA during MI DAG construction"))
static unsigned InstrCount
void GetUnderlyingObjects(Value *V, SmallVectorImpl< Value * > &Objects, const DataLayout &DL, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to GetUnderlyingObject except that it can look through phi and select instruct...
iterator_range< mmo_iterator > memoperands()
Kind
Kind - These are the different kinds of scheduling dependencies.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
iterator_range< mop_iterator > operands()
unsigned NumRegionInstrs
Instructions in this region (distance(RegionBegin, RegionEnd)).
void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
RangePair equal_range(const KeyT &K)
The bounds of the range of items sharing Key K.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
SmallVector< SDep, 4 > Preds
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
The two locations may or may not alias. This is the least precise result.
MachineBasicBlock::const_iterator getPos() const
Get the MI position corresponding to this register pressure.
void clearList(ValueType V)
Clears the list of SUs mapped to V.
iterator_range< succ_iterator > successors()
A register anti-dependedence (aka WAR).
iterator_base< SparseMultiSet * > iterator
void insertBarrierChain(Value2SUsMap &map)
Insert a barrier chain in a huge region, far below current SU.
void recede(SmallVectorImpl< RegisterMaskPair > *LiveUses=nullptr)
Recede across the previous instruction.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB)
The main low level interface to the alias analysis implementation.
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
A description of a memory reference used in the backend.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...
void addSchedBarrierDeps()
addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being sc...
const HexagonInstrInfo * TII
Kind getKind() const
getKind - Return an enum value representing the kind of the dependence.
static void getUnderlyingObjects(const Value *V, SmallVectorImpl< Value * > &Objects, const DataLayout &DL)
getUnderlyingObjects - This is a wrapper around GetUnderlyingObjects and adds support for basic ptrto...
'undef' values are things that do not have specified contents.
An individual mapping from virtual register number to SUnit.
void setInstr(MachineInstr *MI)
setInstr - Assign the instruction for the SUnit.
A Use represents the edge between a Value definition and its users.
static bool hasDataSucc(const SUnit *SU)
static void advance(T &it, size_t Val)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Regular data dependence (aka true-dependence).
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
ValueT & operator[](const KeyT &Key)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
constexpr bool any() const
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isIdentifiedObject(const Value *V)
Return true if this pointer refers to a distinct and identifiable object.
Compute the values of each DAG node for various metrics during DFS.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Value2SUsMap(unsigned lat=0)
A register output-dependence (aka WAW).
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
void addVRegUseDeps(SUnit *SU, unsigned OperIdx)
addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register ...
void printAsOperand(raw_ostream &O, bool PrintType=true, const Module *M=nullptr) const
Print the name of this Value out to the specified raw_ostream.
void print(raw_ostream &OS) const
Function Alias Analysis false
SUnit * BarrierChain
Remember a generic side-effecting instruction as we proceed.
void addChainDependencies(SUnit *SU, SUList &sus, unsigned Latency)
Add dependencies as needed from all SUs in list to SU.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)
Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...
List of registers defined and used by a machine instruction.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
void visitPostorderNode(const SUnit *SU)
Called once for each node after all predecessors are visited.
iterator find(const ValueType &Key)
void visitPreorder(const SUnit *SU)
Initialize this node's instruction count.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
void recedeSkipDebugValues()
Recede until we find an instruction which is not a DebugValue.
SDep - Scheduling dependency.
void remove_if(Predicate Pred)
Remove the elements that match the predicate.
initializer< Ty > init(const Ty &Val)
unsigned const MachineRegisterInfo * MRI
void clearDAG()
clearDAG - clear the DAG state (between regions).
The instances of the Type class are immutable: once they are created, they are never changed...
static unsigned getReductionSize()
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
void visitCrossEdge(const SDep &PredDep, const SUnit *Succ)
Add a connection for cross edges.
Internal state used to compute SchedDFSResult.
const MachineOperand & getOperand(unsigned i) const
Summarize the scheduling resources required for an instruction of a particular scheduling class...
void addConnection(unsigned FromTree, unsigned ToTree, unsigned Depth)
Called by finalize() to record a connection between trees.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
void setUniverse(unsigned U)
Set the universe size which determines the largest key the set can hold.
AliasResult
The possible results of an alias query.
MCRegAliasIterator enumerates all registers aliasing Reg.
static const unsigned End
Track the current register pressure at some position in the instruction stream, and remember the high...
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
self_iterator getIterator()
const MachineFrameInfo & MFI
void clear()
Clears the set.
static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, MachineInstr *MIa, MachineInstr *MIb)
This returns true if the two MIs need a chain edge between them.
unsigned getSubReg() const
bool isPointerTy() const
True if this is an instance of PointerType.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isVisited(const SUnit *SU) const
Return true if this node been visited by the DFS traversal.
ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const
void setIsKill(bool Val=true)
iterator find(const KeyT &Key)
Find an element by its key.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
void addPhysRegDeps(SUnit *SU, unsigned OperIdx)
addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following inst...
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model. ...
Representation for a specific memory location.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)
Use liveness information to find out which uses/defs are partially undefined/dead and adjust the Regi...
static void toggleBundleKillFlag(MachineInstr *MI, unsigned Reg, bool NewKillState, const TargetRegisterInfo *TRI)
If we change a kill flag on the bundle instruction implicit register operands, then we also need to p...
void reduceHugeMemNodeMaps(Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
Remove in FIFO order some SUs from huge maps.
Iterator for intrusive lists based on ilist_node.
bool hasTailCall() const
Returns true if the function contains a tail call.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
const MCProcResourceDesc * getProcResource(unsigned PIdx) const
Get a processor resource by ID for convenience.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
This is a utility class that provides an abstraction for the common functionality between Instruction...
Type * getType() const
All values are typed, get the type of this value.
Reg2SUnitsMap Defs
State internal to DAG building.
void eraseAll(const KeyT &K)
Erase all elements with the given key.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
LLVM_NODISCARD T pop_back_val()
CHAIN = SC CHAIN, Imm128 - System call.
void dump(const TargetInstrInfo *TII=nullptr) const
Nonvolatile load/Store instructions that may alias.
bool addPredBarrier(SUnit *SU)
addPredBarrier - This adds a barrier edge to SU by calling addPred(), with latency 0 generally or lat...
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getTrueMemOrderLatency() const
static cl::opt< unsigned > ReductionSize("dag-maps-reduction-size", cl::Hidden, cl::desc("A huge scheduling region will have maps reduced by this many ""nodes at a time. Defaults to HugeRegion / 2."))
VReg2SUnitOperIdxMultiMap CurrentVRegUses
Tracks the last instructions in this region using each virtual register.
const Value * getValue() const
Return the base address of the memory access.
Special value supplied for machine level alias analysis.
bool isIntegerTy() const
True if this is an instance of IntegerType.
MachineBasicBlock::iterator end() const
end - Return an iterator to the bottom of the current scheduling region.
bool isBoundaryNode() const
Boundary nodes are placeholders for the boundary of the scheduling region.
void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ)
Called once for each tree edge after calling visitPostOrderNode on the predecessor.
void setLatency(unsigned Lat)
setLatency - Set the latency for this edge.
**iterator erase(iterator I)
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
void finalize()
Set each node's subtree ID to the representative ID and record connections between trees...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasOneDef(unsigned RegNo) const
Return true if there is exactly one operand defining the specified register.
const TargetRegisterInfo * TRI
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
bool isCall(QueryType Type=AnyInBundle) const
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Mapping from virtual register to SUnit including an operand index.
void addChainDependency(SUnit *SUa, SUnit *SUb, unsigned Latency=0)
Add a chain edge between SUa and SUb, but only if both AliasAnalysis and Target fail to deny the depe...
const TargetInstrInfo * TII
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
unsigned getReg() const
getReg - Returns the register number.
SUnit * newSUnit(MachineInstr *MI)
newSUnit - Creates a new SUnit and return a ptr to it.
void addBarrierChain(Value2SUsMap &map)
Add barrier chain edges from all SUs in map, and then clear the map.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const
Returns a mask for which lanes get read/written by the given (register) machine operand.
bool addPred(const SDep &D, bool Required=true)
addPred - This adds the specified edge as a pred of the current node if not already.
A raw_ostream that writes to an std::string.
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
void clear()
Clears map from all contents.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
void initSUnits()
Create an SUnit for each real instruction, numbered in top-down topological order.
static void getUnderlyingObjectsForInstr(const MachineInstr *MI, const MachineFrameInfo &MFI, UnderlyingObjectsVector &Objects, const DataLayout &DL)
getUnderlyingObjectsForInstr - If this machine instr has memory reference information and it can be t...
SmallVector< SDep, 4 > Succs
Arbitrary strong DAG edge (no real dependence).
uint64_t getSize() const
Return the size in bytes of the memory reference.
This class implements an extremely fast bulk output stream that can only output to a stream...
MachineInstr * FirstDbgValue
static bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI)
Return true if MI is an instruction we are unable to reason about (like a call or something with unmo...
MachineBasicBlock * BB
State specific to the current scheduling region.
bool empty() const
Returns true if the set is empty.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
static void dumpSUList(ScheduleDAGInstrs::SUList &L)
MachineRegisterInfo & MRI
std::vector< SUnit > SUnits
SchedDFSImpl(SchedDFSResult &r)
ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SlotIndex - An opaque wrapper around machine indexes.
static const Value * getUnderlyingObjectFromInt(const Value *V)
getUnderlyingObjectFromInt - This is the function that does the work of looking through basic ptrtoin...
VReg2SUnitMultiMap CurrentVRegDefs
Tracks the last instruction(s) in this region defining each virtual register.
std::pair< iterator, iterator > RangePair
void reComputeSize(void)
Count the number of SUs in this map after a reduction.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
SUnit - Scheduling unit. This is a node in the scheduling DAG.
std::list< SUnit * > SUList
A list of SUnits, used in Value2SUsMap, during DAG construction.
virtual bool useAA() const
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.