25 #define GET_INSTRINFO_CTOR_DTOR
26 #include "NVPTXGenInstrInfo.inc"
29 void NVPTXInstrInfo::anchor() {}
35 const DebugLoc &DL,
unsigned DestReg,
36 unsigned SrcReg,
bool KillSrc)
const {
45 if (DestRC == &NVPTX::Int1RegsRegClass) {
47 }
else if (DestRC == &NVPTX::Int16RegsRegClass) {
49 }
else if (DestRC == &NVPTX::Int32RegsRegClass) {
50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
51 : NVPTX::BITCONVERT_32_F2I);
52 }
else if (DestRC == &NVPTX::Int64RegsRegClass) {
53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
54 : NVPTX::BITCONVERT_64_F2I);
55 }
else if (DestRC == &NVPTX::Float32RegsRegClass) {
56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
57 : NVPTX::BITCONVERT_32_I2F);
58 }
else if (DestRC == &NVPTX::Float64RegsRegClass) {
59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
60 : NVPTX::BITCONVERT_64_I2F);
64 BuildMI(MBB, I, DL,
get(Op), DestReg)
69 unsigned &DestReg)
const {
75 isMove = (TSFlags == 1);
80 assert(dest.
isReg() &&
"dest of a movrr is not a reg");
81 assert(src.
isReg() &&
"src of a movrr is not a reg");
92 unsigned &AddrSpace)
const {
96 isLoad = (TSFlags == 1);
103 unsigned &AddrSpace)
const {
104 bool isStore =
false;
107 isStore = (TSFlags == 1);
140 bool AllowModify)
const {
143 if (I == MBB.
begin() || !isUnpredicatedTerminator(*--I))
150 if (I == MBB.
begin() || !isUnpredicatedTerminator(*--I)) {
151 if (LastInst.
getOpcode() == NVPTX::GOTO) {
154 }
else if (LastInst.
getOpcode() == NVPTX::CBranch) {
168 if (I != MBB.
begin() && isUnpredicatedTerminator(*--I))
172 if (SecondLastInst.
getOpcode() == NVPTX::CBranch &&
182 if (SecondLastInst.
getOpcode() == NVPTX::GOTO &&
187 I->eraseFromParent();
196 int *BytesRemoved)
const {
197 assert(!BytesRemoved &&
"code size not handled");
199 if (I == MBB.
begin())
202 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
206 I->eraseFromParent();
210 if (I == MBB.
begin())
213 if (I->getOpcode() != NVPTX::CBranch)
217 I->eraseFromParent();
226 int *BytesAdded)
const {
227 assert(!BytesAdded &&
"code size not handled");
230 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
232 "NVPTX branch conditions have two components!");
237 BuildMI(&MBB, DL,
get(NVPTX::GOTO)).addMBB(TBB);
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MachineBasicBlock * getMBB() const
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
const MachineOperand & getOperand(unsigned i) const
bool empty() const
empty - Check if the array is empty.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineOperand class - Representation of each machine instruction operand.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DestReg) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const