LLVM  4.0.0
SIISelLowering.h
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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief SI DAG Lowering interface definition
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
17 
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class SITargetLowering final : public AMDGPUTargetLowering {
24  SDValue LowerParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain,
25  unsigned Offset) const;
26  SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL,
27  SDValue Chain, unsigned Offset, bool Signed,
28  const ISD::InputArg *Arg = nullptr) const;
29  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
30  SelectionDAG &DAG) const override;
31  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
32  MVT VT, unsigned Offset) const;
33 
34  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
35  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
36  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
37  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
38  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
39  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
40  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
41  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
42  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
43  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
44  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
45  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
46  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
47  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
48  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
49  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
50 
51  /// \brief Converts \p Op, which must be of floating point type, to the
52  /// floating point type \p VT, by either extending or truncating it.
53  SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
54  SDValue Op,
55  const SDLoc &DL,
56  EVT VT) const;
57 
58  /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16.
59  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
60 
61  SDValue getSegmentAperture(unsigned AS, SelectionDAG &DAG) const;
62  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
63  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
64 
65  void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
66 
67  SDValue performUCharToFloatCombine(SDNode *N,
68  DAGCombinerInfo &DCI) const;
69  SDValue performSHLPtrCombine(SDNode *N,
70  unsigned AS,
71  DAGCombinerInfo &DCI) const;
72 
73  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
74 
75  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
76  unsigned Opc, SDValue LHS,
77  const ConstantSDNode *CRHS) const;
78 
79  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
83  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
84 
85  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86 
87  unsigned getFusedOpcode(const SelectionDAG &DAG,
88  const SDNode *N0, const SDNode *N1) const;
89  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
92  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
93 
94  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
95  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
96 
97  bool isCFIntrinsic(const SDNode *Intr) const;
98 
99  void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
100 
101  /// \returns True if fixup needs to be emitted for given global value \p GV,
102  /// false otherwise.
103  bool shouldEmitFixup(const GlobalValue *GV) const;
104 
105  /// \returns True if GOT relocation needs to be emitted for given global value
106  /// \p GV, false otherwise.
107  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
108 
109  /// \returns True if PC-relative relocation needs to be emitted for given
110  /// global value \p GV, false otherwise.
111  bool shouldEmitPCReloc(const GlobalValue *GV) const;
112 
113 public:
114  SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
115 
116  const SISubtarget *getSubtarget() const;
117 
118  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
119  unsigned IntrinsicID) const override;
120 
121  bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
122  EVT /*VT*/) const override;
123 
124  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
125  unsigned AS) const override;
126 
127  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
128  unsigned Align,
129  bool *IsFast) const override;
130 
131  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
132  unsigned SrcAlign, bool IsMemset,
133  bool ZeroMemset,
134  bool MemcpyStrSrc,
135  MachineFunction &MF) const override;
136 
137  bool isMemOpUniform(const SDNode *N) const;
138  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
139  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
140  bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
141 
143  getPreferredVectorAction(EVT VT) const override;
144 
146  Type *Ty) const override;
147 
148  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
149 
150  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
151 
153  bool isVarArg,
155  const SDLoc &DL, SelectionDAG &DAG,
156  SmallVectorImpl<SDValue> &InVals) const override;
157 
158  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
160  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
161  SelectionDAG &DAG) const override;
162 
163  unsigned getRegisterByName(const char* RegName, EVT VT,
164  SelectionDAG &DAG) const override;
165 
167  MachineBasicBlock *BB) const;
168 
171  MachineBasicBlock *BB) const override;
172  bool enableAggressiveFMAFusion(EVT VT) const override;
174  EVT VT) const override;
175  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
176  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
177  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
178  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
179  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
181  SDNode *Node) const override;
182 
184  unsigned Reg, EVT VT) const override;
185  void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
186 
188  SDValue Ptr) const;
189  MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
190  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
191  std::pair<unsigned, const TargetRegisterClass *>
193  StringRef Constraint, MVT VT) const override;
194  ConstraintType getConstraintType(StringRef Constraint) const override;
195  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
196  SDValue V) const;
197 };
198 
199 } // End namespace llvm
200 
201 #endif
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
LLVMContext & Context
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
This class represents a function call, abstracting a target machine's calling convention.
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isMemOpUniform(const SDNode *N) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Reg
All possible values of the reg field in the ModR/M byte.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const override
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
SITargetLowering(const TargetMachine &tm, const SISubtarget &STI)
uint32_t Offset
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
Interface definition of the TargetLowering class that is common to all AMD GPUs.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
Class for arbitrary precision integers.
Definition: APInt.h:77
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
const SISubtarget * getSubtarget() const
Representation of each machine instruction.
Definition: MachineInstr.h:52
Interface definition for SIInstrInfo.
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
#define N
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
int * Ptr
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...