15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
37 #define GET_SUBTARGETINFO_HEADER
38 #include "AMDGPUGenSubtargetInfo.inc"
460 return &FrameLowering;
496 std::unique_ptr<GISelAccessor> GISel;
507 return &FrameLowering;
515 assert(GISel &&
"Access to GlobalISel APIs not set");
516 return GISel->getCallLowering();
524 this->GISel.reset(&GISel);
528 unsigned NumRegionInstrs)
const override;
616 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
bool hasCaymanISA() const
const AMDGPURegisterInfo * getRegisterInfo() const override=0
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
bool hasVertexCache() const
Interface definition for R600InstrInfo.
bool isVGPRSpillingEnabled(const Function &F) const
bool hasUnalignedBufferAccess() const
int getLDSBankCount() const
bool hasFastFMAF32() const
AMDGPUSubtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount) const
Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount...
const SIInstrInfo * getInstrInfo() const override
bool enableIEEEBit(const MachineFunction &MF) const
SelectionDAGTargetInfo TSInfo
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
int getLocalMemorySize() const
bool loadStoreOptEnabled() const
bool hasFPExceptions() const
bool isAmdCodeObjectV2(const MachineFunction &MF) const
unsigned getImplicitArgNumBytes(const MachineFunction &MF) const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const
bool isMesaKernel(const MachineFunction &MF) const
unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const
Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.
bool enableSIScheduler() const
bool useFlatForGlobal() const
std::pair< unsigned, unsigned > getWavesPerEU(const Function &F) const
const InstrItineraryData * getInstrItineraryData() const override
bool getScalarizeGlobalBehavior() const
bool isMesaGfxShader(const MachineFunction &MF) const
unsigned getMaxNumUserSGPRs() const
bool isXNACKEnabled() const
bool hasVGPRIndexMode() const
SISubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
const AMDGPUFrameLowering * getFrameLowering() const override=0
Itinerary data supplied by a subtarget to be used by a target.
Generation getGeneration() const
bool EnableUnsafeDSOffsetFolding
const SIRegisterInfo & getRegisterInfo() const
bool hasHalfRate64Ops() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
bool hasSGPRInitBug() const
const R600FrameLowering * getFrameLowering() const override
unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const
unsigned getMaxWavesPerEU() const
bool isShader(CallingConv::ID cc)
unsigned getKernArgSegmentSize(const MachineFunction &MF, unsigned ExplictArgBytes) const
unsigned getMaxWavesPerCU() const
bool DebuggerEmitPrologue
R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
bool hasUnalignedScratchAccess() const
unsigned getMinFlatWorkGroupSize() const
SI DAG Lowering interface definition.
bool isCompute(CallingConv::ID cc)
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const
Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.
const R600InstrInfo * getInstrInfo() const override
bool hasScalarStores() const
bool hasFP32Denormals() const
bool debuggerReserveRegs() const
bool debuggerSupported() const
unsigned getMaxFlatWorkGroupSize() const
bool has16BitInsts() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
const AMDGPUInstrInfo * getInstrInfo() const override=0
bool hasScalarCompareEq64() const
bool hasInv2PiInlineImm() const
bool isPromoteAllocaEnabled() const
bool hasFP64Denormals() const
Triple - Helper class for working with autoconf configuration names.
unsigned getOccupancyWithLocalMemSize(uint32_t Bytes) const
Inverse of getMaxLocalMemWithWaveCount.
const R600RegisterInfo * getRegisterInfo() const override
const AMDGPUTargetLowering * getTargetLowering() const override=0
unsigned getMinWavesPerEU() const
const SIRegisterInfo * getRegisterInfo() const override
bool debuggerInsertNops() const
void setScalarizeGlobalBehavior(bool b)
void setGISelAccessor(GISelAccessor &GISel)
short getTexVTXClauseSize() const
bool enableSubRegLiveness() const override
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
Interface definition for SIInstrInfo.
bool unsafeDSOffsetFoldingEnabled() const
unsigned getMaxPrivateElementSize() const
R600 DAG Lowering interface definition.
Information about the stack frame layout on the AMDGPU targets.
const R600RegisterInfo & getRegisterInfo() const
const CallLowering * getCallLowering() const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
const SIFrameLowering * getFrameLowering() const override
unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument...
bool UnalignedScratchAccess
~AMDGPUSubtarget() override
unsigned getWavefrontSize() const
AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, const TargetMachine &TM)
const SITargetLowering * getTargetLowering() const override
unsigned getEUsPerCU() const
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
unsigned getStackAlignment() const
unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasSMemRealTime() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool UnalignedBufferAccess
bool needWaitcntBeforeBarrier() const
InstrItineraryData InstrItins
unsigned MaxPrivateElementSize
const R600TargetLowering * getTargetLowering() const override
Primary interface to the complete machine description for the target machine.
bool hasBCNT(unsigned Size) const
StringRef - Represent a constant reference to a string, i.e.
std::pair< unsigned, unsigned > getFlatWorkGroupSizes(const Function &F) const
bool hasFP16Denormals() const
bool enableMachineScheduler() const override
unsigned getMaxNumSGPRs() const
bool debuggerEmitPrologue() const
bool hasFlatAddressSpace() const
bool has12DWordStoreHazard() const
unsigned getAlignmentForImplicitArgPtr() const