15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
216 class MipsFunctionInfo;
264 EVT VT)
const override;
281 return ABI.
IsN64() ? Mips::A0_64 : Mips::A0;
288 return ABI.
IsN64() ? Mips::A1_64 : Mips::A1;
296 return SrcAS < 256 && DestAS < 256;
310 template <
class NodeTy>
312 bool IsN32OrN64)
const {
315 getTargetNode(N, Ty, DAG, GOTFlag));
321 getTargetNode(N, Ty, DAG, LoFlag));
329 template <
class NodeTy>
334 getTargetNode(N, Ty, DAG, Flag));
335 return DAG.
getLoad(Ty, DL, Chain, Tgt, PtrInfo);
342 template <
class NodeTy>
345 unsigned LoFlag,
SDValue Chain,
351 getTargetNode(N, Ty, DAG, LoFlag));
352 return DAG.
getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
359 template <
class NodeTy>
373 template <
class NodeTy>
389 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
390 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
391 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
406 unsigned Flag)
const;
410 unsigned Flag)
const;
414 unsigned Flag)
const;
418 unsigned Flag)
const;
422 unsigned Flag)
const;
458 isEligibleForTailCallOptimization(
const CCState &CCInfo,
459 unsigned NextStackOffset,
469 const Argument *FuncArg,
unsigned FirstReg,
475 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
478 unsigned FirstReg,
unsigned LastReg,
485 void writeVarArgRegs(std::vector<SDValue> &OutChains,
SDValue Chain,
515 bool shouldSignExtendTypeInLibCall(
EVT Type,
bool IsSigned)
const override;
527 std::pair<unsigned, const TargetRegisterClass *>
530 std::pair<unsigned, const TargetRegisterClass *>
538 void LowerAsmOperandForConstraint(
SDValue Op,
539 std::string &Constraint,
540 std::vector<SDValue> &Ops,
544 getInlineAsmMemConstraint(
StringRef ConstraintCode)
const override {
545 if (ConstraintCode ==
"R")
547 else if (ConstraintCode ==
"ZC")
553 Type *Ty,
unsigned AS)
const override;
557 EVT getOptimalMemOpType(uint64_t Size,
unsigned DstAlign,
559 bool IsMemset,
bool ZeroMemset,
566 bool isFPImmLegal(
const APFloat &Imm,
EVT VT)
const override;
568 unsigned getJumpTableEncoding()
const override;
569 bool useSoftFloat()
const override;
571 bool shouldInsertFencesForAtomic(
const Instruction *
I)
const override {
576 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &
MI,
577 MachineBasicBlock *BB,
578 unsigned Size,
unsigned DstReg,
579 unsigned SrcRec)
const;
581 MachineBasicBlock *emitAtomicBinary(MachineInstr &
MI, MachineBasicBlock *BB,
582 unsigned Size,
unsigned BinOpcode,
583 bool Nand =
false)
const;
584 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &
MI,
585 MachineBasicBlock *BB,
588 bool Nand =
false)
const;
589 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &
MI,
590 MachineBasicBlock *BB,
591 unsigned Size)
const;
592 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &
MI,
593 MachineBasicBlock *BB,
594 unsigned Size)
const;
595 MachineBasicBlock *emitSEL_D(MachineInstr &
MI, MachineBasicBlock *BB)
const;
596 MachineBasicBlock *emitPseudoSELECT(MachineInstr &
MI, MachineBasicBlock *BB,
597 bool isFPCmp,
unsigned Opc)
const;
601 const MipsTargetLowering *
603 const MipsSubtarget &STI);
604 const MipsTargetLowering *
606 const MipsSubtarget &STI);
610 const TargetLibraryInfo *libInfo);
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Argument representation.
const MipsSubtarget & Subtarget
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
const TargetMachine & getTargetMachine() const
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Function Alias Analysis Results
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
struct fuzzer::@269 Flags
MachineFunction & getMachineFunction() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
This is an important base class in LLVM.
void HandleByVal(CCState *, unsigned &, unsigned) const override
Target-specific cleanup for formal ByVal parameters.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
bool isPositionIndependent() const
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
CCState - This class holds information needed while lowering arguments and return values...
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
Provides information about what library functions are available for the current target.
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
CCValAssign - Represent assignment of one arg/retval to a location.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
AddrMode
ARM Addressing Modes.
Representation of each machine instruction.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isJumpTableRelative() const override
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue getRegister(unsigned Reg, EVT VT)
StringRef - Represent a constant reference to a string, i.e.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
This file describes how to lower LLVM code to machine code.