17 #ifndef LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
18 #define LLVM_LIB_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
33 class RegisterClassInfo;
48 const unsigned NumTargetRegs;
55 std::vector<unsigned> GroupNodes;
61 std::vector<unsigned> GroupNodeIndices;
64 std::multimap<unsigned, RegisterReference> RegRefs;
68 std::vector<unsigned> KillIndices;
72 std::vector<unsigned> DefIndices;
84 std::multimap<unsigned, RegisterReference>&
GetRegRefs() {
return RegRefs; }
88 unsigned GetGroup(
unsigned Reg);
94 std::vector<unsigned> &
Regs,
95 std::multimap<
unsigned,
100 unsigned UnionGroups(
unsigned Reg1,
unsigned Reg2);
105 unsigned LeaveGroup(
unsigned Reg);
108 bool IsLive(
unsigned Reg);
138 unsigned BreakAntiDependencies(
const std::vector<SUnit>& SUnits,
141 unsigned InsertPosIndex,
148 unsigned InsertPosIndex)
override;
151 void FinishBlock()
override;
155 typedef std::map<const TargetRegisterClass *, unsigned> RenameOrderType;
163 void GetPassthruRegs(
MachineInstr &MI, std::set<unsigned> &PassthruRegs);
165 void HandleLastUse(
unsigned Reg,
unsigned KillIdx,
const char *tag,
166 const char *header =
nullptr,
167 const char *footer =
nullptr);
169 void PrescanInstruction(
MachineInstr &MI,
unsigned Count,
170 std::set<unsigned> &PassthruRegs);
172 BitVector GetRenameRegisters(
unsigned Reg);
173 bool FindSuitableFreeRegisters(
unsigned AntiDepGroupIndex,
174 RenameOrderType& RenameOrder,
175 std::map<unsigned, unsigned> &RenameMap);
Information about a register reference within a liverange.
MachineOperand * Operand
The registers operand.
const HexagonInstrInfo * TII
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
static const unsigned End
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
const TargetRegisterClass * RC
The register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineOperand class - Representation of each machine instruction operand.
std::vector< unsigned > & GetDefIndices()
Return the define indices.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
std::multimap< unsigned, RegisterReference > & GetRegRefs()
Return the RegRefs map.
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector
Contains all the state necessary for anti-dep breaking.
std::vector< unsigned > & GetKillIndices()
Return the kill indices.