16 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
17 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
19 #include "llvm/Support/DataTypes.h"
28 class MCSubtargetInfo;
29 class MCTargetOptions;
33 class raw_pwrite_stream;
39 const MCRegisterInfo &
MRI,
43 const MCRegisterInfo &
MRI,
47 const Triple &TT, StringRef CPU,
48 const MCTargetOptions &Options);
51 bool HasRelocationAddend,
52 raw_pwrite_stream &OS);
55 #define GET_REGINFO_ENUM
56 #include "AMDGPUGenRegisterInfo.inc"
58 #define GET_INSTRINFO_ENUM
59 #include "AMDGPUGenInstrInfo.inc"
61 #define GET_SUBTARGETINFO_ENUM
62 #include "AMDGPUGenSubtargetInfo.inc"
Target & getTheGCNTarget()
The target for GCN GPUs.
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Target & getTheAMDGPUTarget()
The target which suports all AMD GPUs.
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
MCObjectWriter * createAMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend, raw_pwrite_stream &OS)
unsigned const MachineRegisterInfo * MRI
static const char * Target