55 #define DEBUG_TYPE "twoaddrinstr"
57 STATISTIC(NumTwoAddressInstrs,
"Number of two-address instructions");
58 STATISTIC(NumCommuted ,
"Number of instructions commuted to coalesce");
59 STATISTIC(NumAggrCommuted ,
"Number of instructions aggressively commuted");
60 STATISTIC(NumConvertedTo3Addr,
"Number of instructions promoted to 3-address");
61 STATISTIC(Num3AddrSunk,
"Number of 3-address instructions sunk");
62 STATISTIC(NumReSchedUps,
"Number of instructions re-scheduled up");
63 STATISTIC(NumReSchedDowns,
"Number of instructions re-scheduled down");
68 cl::desc(
"Coalesce copies by rescheduling (default=true)"),
105 bool isRevCopyChain(
unsigned FromReg,
unsigned ToReg,
int Maxlen);
107 bool noUseAfterLastDef(
unsigned Reg,
unsigned Dist,
unsigned &LastDef);
109 bool isProfitableToCommute(
unsigned regA,
unsigned regB,
unsigned regC,
113 unsigned RegBIdx,
unsigned RegCIdx,
unsigned Dist);
115 bool isProfitableToConv3Addr(
unsigned RegA,
unsigned RegB);
119 unsigned RegA,
unsigned RegB,
unsigned Dist);
132 unsigned SrcIdx,
unsigned DstIdx,
133 unsigned Dist,
bool shouldOnlyCommute);
140 void scanUses(
unsigned DstReg);
147 void processTiedPairs(
MachineInstr *
MI, TiedPairList&,
unsigned &Dist);
175 "Two-Address instruction pass",
false,
false)
187 bool TwoAddressInstructionPass::
188 sink3AddrInstruction(
MachineInstr *MI,
unsigned SavedReg,
195 bool SeenStore =
true;
196 if (!MI->isSafeToMove(AA, SeenStore))
205 unsigned MOReg = MO.getReg();
208 if (MO.isUse() && MOReg != SavedReg)
209 UseRegs.
insert(MO.getReg());
218 DefReg = MO.getReg();
226 "Reg should not have empty live interval.");
230 if (I != LI.
end() && I->start < MBBEndIdx)
234 KillMI = LIS->getInstructionFromIndex(I->end);
248 if (!KillMI || KillMI->
getParent() !=
MBB || KillMI == MI ||
262 unsigned NumVisited = 0;
265 if (OtherMI.isDebugValue())
270 for (
unsigned i = 0, e = OtherMI.getNumOperands();
i != e; ++
i) {
274 unsigned MOReg = MO.
getReg();
281 if (&OtherMI == KillMI && MOReg == SavedReg)
285 else if (UseRegs.
count(MOReg))
291 assert(KillMO &&
"Didn't find kill");
296 KillMO = MI->findRegisterUseOperand(SavedReg,
false, TRI);
300 LV->replaceKillInstruction(SavedReg, *KillMI, *MI);
308 LIS->handleMove(*MI);
319 if (DefMI.getParent() != BB || DefMI.isDebugValue())
323 else if (Ret != &DefMI)
336 bool TwoAddressInstructionPass::isRevCopyChain(
unsigned FromReg,
unsigned ToReg,
338 unsigned TmpReg = FromReg;
339 for (
int i = 0;
i < Maxlen;
i++) {
341 if (!Def || !Def->
isCopy())
356 bool TwoAddressInstructionPass::noUseAfterLastDef(
unsigned Reg,
unsigned Dist,
359 unsigned LastUse = Dist;
365 if (DI == DistanceMap.
end())
367 if (MO.isUse() && DI->second < LastUse)
368 LastUse = DI->second;
369 if (MO.isDef() && DI->second > LastDef)
370 LastDef = DI->second;
373 return !(LastUse > LastDef && LastUse < Dist);
380 unsigned &SrcReg,
unsigned &DstReg,
381 bool &IsSrcPhys,
bool &IsDstPhys) {
418 assert(I != LI.
end() &&
"Reg must be live-in to use.");
446 bool allowFalsePositives) {
451 (allowFalsePositives || MRI->
hasOneUse(Reg)))
460 if (std::next(Begin) != MRI->
def_end())
463 bool IsSrcPhys, IsDstPhys;
464 unsigned SrcReg, DstReg;
467 if (!
isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
496 unsigned &DstReg,
bool &IsDstPhys) {
505 if (
isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
523 if (SI == RegMap.
end())
545 for (
unsigned R : Set)
555 TwoAddressInstructionPass::
556 isProfitableToCommute(
unsigned regA,
unsigned regB,
unsigned regC,
603 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
609 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
615 unsigned LastDefC = 0;
616 if (!noUseAfterLastDef(regC, Dist, LastDefC))
621 unsigned LastDefB = 0;
622 if (!noUseAfterLastDef(regB, Dist, LastDefB))
640 if (isRevCopyChain(regC, regA, 3))
643 if (isRevCopyChain(regB, regA, 3))
648 return LastDefB && LastDefC && LastDefC > LastDefB;
653 bool TwoAddressInstructionPass::commuteInstruction(
MachineInstr *MI,
659 DEBUG(
dbgs() <<
"2addr: COMMUTING : " << *MI);
660 MachineInstr *NewMI =
TII->commuteInstruction(*MI,
false, RegBIdx, RegCIdx);
662 if (NewMI ==
nullptr) {
663 DEBUG(
dbgs() <<
"2addr: COMMUTING FAILED!\n");
667 DEBUG(
dbgs() <<
"2addr: COMMUTED TO: " << *NewMI);
669 "TargetInstrInfo::commuteInstruction() should not return a new "
670 "instruction unless it was requested.");
676 SrcRegMap[RegA] = FromRegC;
685 TwoAddressInstructionPass::isProfitableToConv3Addr(
unsigned RegA,
unsigned RegB){
704 unsigned RegA,
unsigned RegB,
710 "convertToThreeAddress changed iterator reference");
714 DEBUG(
dbgs() <<
"2addr: CONVERTING 2-ADDR: " << *mi);
715 DEBUG(
dbgs() <<
"2addr: TO 3-ADDR: " << *NewMI);
719 LIS->ReplaceMachineInstrInMaps(*mi, *NewMI);
725 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
730 DistanceMap.insert(std::make_pair(NewMI, Dist));
736 SrcRegMap.erase(RegA);
737 DstRegMap.erase(RegB);
744 TwoAddressInstructionPass::scanUses(
unsigned DstReg) {
749 unsigned Reg = DstReg;
751 NewReg, IsDstPhys)) {
752 if (IsCopy && !Processed.insert(
UseMI).second)
756 if (DI != DistanceMap.
end())
764 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
766 assert(SrcRegMap[NewReg] == Reg &&
"Can't map to two src registers!");
771 if (!VirtRegPairs.
empty()) {
772 unsigned ToReg = VirtRegPairs.
back();
774 while (!VirtRegPairs.
empty()) {
775 unsigned FromReg = VirtRegPairs.
back();
777 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
779 assert(DstRegMap[FromReg] == ToReg &&
"Can't map to two dst registers!");
782 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
784 assert(DstRegMap[DstReg] == ToReg &&
"Can't map to two dst registers!");
800 void TwoAddressInstructionPass::processCopy(
MachineInstr *MI) {
801 if (Processed.count(MI))
804 bool IsSrcPhys, IsDstPhys;
805 unsigned SrcReg, DstReg;
809 if (IsDstPhys && !IsSrcPhys)
810 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
811 else if (!IsDstPhys && IsSrcPhys) {
812 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
814 assert(SrcRegMap[DstReg] == SrcReg &&
815 "Can't map to two src physical registers!");
820 Processed.insert(MI);
826 bool TwoAddressInstructionPass::
837 if (DI == DistanceMap.
end())
845 "Reg should not have empty live interval.");
849 if (I != LI.
end() && I->start < MBBEndIdx)
853 KillMI = LIS->getInstructionFromIndex(I->end);
855 KillMI = LV->getVarInfo(Reg).findKill(
MBB);
870 bool SeenStore =
true;
884 unsigned MOReg = MO.getReg();
891 if (MOReg != Reg && (MO.isKill() ||
902 while (End->isCopy() &&
904 Defs.
push_back(End->getOperand(0).getReg());
909 unsigned NumVisited = 0;
914 if (OtherMI.isDebugValue())
919 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
920 OtherMI.isBranch() || OtherMI.isTerminator())
926 unsigned MOReg = MO.getReg();
943 if (MOReg != Reg && ((isKill &&
regOverlapsSet(Uses, MOReg, TRI)) ||
947 if (MOReg == Reg && !isKill)
951 assert((MOReg != Reg || &OtherMI == KillMI) &&
952 "Found multiple kills of a register in a basic block");
958 while (Begin !=
MBB->
begin() && std::prev(Begin)->isDebugValue())
967 auto CopyMI = MBBI++;
969 LIS->handleMove(*CopyMI);
977 DistanceMap.erase(DI);
981 LIS->handleMove(*MI);
983 LV->removeVirtualRegisterKilled(Reg, *KillMI);
984 LV->addVirtualRegisterKilled(Reg, *MI);
987 DEBUG(
dbgs() <<
"\trescheduled below kill: " << *KillMI);
993 bool TwoAddressInstructionPass::isDefTooClose(
unsigned Reg,
unsigned Dist,
996 if (DefMI.getParent() !=
MBB || DefMI.isCopy() || DefMI.isCopyLike())
1001 if (DDI == DistanceMap.
end())
1003 unsigned DefDist = DDI->second;
1004 assert(Dist > DefDist &&
"Visited def already?");
1014 bool TwoAddressInstructionPass::
1025 if (DI == DistanceMap.
end())
1033 "Reg should not have empty live interval.");
1037 if (I != LI.
end() && I->start < MBBEndIdx)
1041 KillMI = LIS->getInstructionFromIndex(I->end);
1043 KillMI = LV->getVarInfo(Reg).findKill(
MBB);
1053 bool SeenStore =
true;
1064 unsigned MOReg = MO.getReg();
1068 if (isDefTooClose(MOReg, DI->second, MI))
1070 bool isKill = MO.isKill() || (LIS &&
isPlainlyKilled(KillMI, MOReg, LIS));
1071 if (MOReg == Reg && !isKill)
1074 if (isKill && MOReg != Reg)
1084 unsigned NumVisited = 0;
1088 if (OtherMI.isDebugValue())
1090 if (NumVisited > 10)
1093 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
1094 OtherMI.isBranch() || OtherMI.isTerminator())
1101 unsigned MOReg = MO.getReg();
1105 if (Defs.
count(MOReg))
1109 if (Kills.
count(MOReg))
1112 if (&OtherMI != MI && MOReg == Reg &&
1121 for (
unsigned i = 0, e = OtherDefs.
size();
i != e; ++
i) {
1122 unsigned MOReg = OtherDefs[
i];
1123 if (Uses.
count(MOReg))
1126 LiveDefs.
count(MOReg))
1135 while (InsertPos !=
MBB->
begin() && std::prev(InsertPos)->isDebugValue())
1139 while (std::prev(From)->isDebugValue())
1143 nmi = std::prev(InsertPos);
1144 DistanceMap.erase(DI);
1148 LIS->handleMove(*KillMI);
1150 LV->removeVirtualRegisterKilled(Reg, *KillMI);
1151 LV->addVirtualRegisterKilled(Reg, *MI);
1154 DEBUG(
dbgs() <<
"\trescheduled kill: " << *KillMI);
1170 bool TwoAddressInstructionPass::tryInstructionCommute(
MachineInstr *MI,
1182 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1188 !
TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx))
1192 bool AggressiveCommute =
false;
1197 !BaseOpKilled &&
isKilled(*MI, OtherOpReg,
MRI,
TII, LIS,
false);
1200 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg, MI, Dist)) {
1202 AggressiveCommute =
true;
1206 if (DoCommute && commuteInstruction(MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1209 if (AggressiveCommute)
1224 bool TwoAddressInstructionPass::
1227 unsigned SrcIdx,
unsigned DstIdx,
1228 unsigned Dist,
bool shouldOnlyCommute) {
1237 "cannot make instruction into two-address form");
1243 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist);
1256 if (shouldOnlyCommute)
1276 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1278 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1279 ++NumConvertedTo3Addr;
1304 if (MI.
mayLoad() && !regBKilled) {
1306 unsigned LoadRegIndex;
1316 DEBUG(
dbgs() <<
"2addr: UNFOLDING: " << MI);
1318 TRI->getAllocatableClass(
1319 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1320 unsigned Reg =
MRI->createVirtualRegister(RC);
1322 if (!
TII->unfoldMemoryOperand(*MF, MI, Reg,
1325 DEBUG(
dbgs() <<
"2addr: ABANDONING UNFOLD\n");
1329 "Unfolded a load into multiple instructions!");
1331 NewMIs[1]->addRegisterKilled(Reg, TRI);
1338 DEBUG(
dbgs() <<
"2addr: NEW LOAD: " << *NewMIs[0]
1339 <<
"2addr: NEW INST: " << *NewMIs[1]);
1342 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1343 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1345 bool TransformResult =
1346 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist,
true);
1347 (void)TransformResult;
1348 assert(!TransformResult &&
1349 "tryInstructionTransform() should return false.");
1350 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1360 if (NewMIs[0]->killsRegister(MO.
getReg()))
1361 LV->replaceKillInstruction(MO.
getReg(),
MI, *NewMIs[0]);
1364 "Kill missing after load unfold!");
1365 LV->replaceKillInstruction(MO.
getReg(),
MI, *NewMIs[1]);
1368 }
else if (LV->removeVirtualRegisterDead(MO.
getReg(),
MI)) {
1369 if (NewMIs[1]->registerDefIsDead(MO.
getReg()))
1370 LV->addVirtualRegisterDead(MO.
getReg(), *NewMIs[1]);
1373 "Dead flag missing after load unfold!");
1374 LV->addVirtualRegisterDead(MO.
getReg(), *NewMIs[0]);
1379 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
1396 LIS->repairIntervalsInRange(
MBB, Begin, End, OrigRegs);
1404 DEBUG(
dbgs() <<
"2addr: ABANDONING UNFOLD\n");
1405 NewMIs[0]->eraseFromParent();
1406 NewMIs[1]->eraseFromParent();
1418 bool TwoAddressInstructionPass::
1419 collectTiedOperands(
MachineInstr *MI, TiedOperandMap &TiedOperands) {
1421 bool AnyOps =
false;
1424 for (
unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1425 unsigned DstIdx = 0;
1431 unsigned SrcReg = SrcMO.
getReg();
1432 unsigned DstReg = DstMO.
getReg();
1434 if (SrcReg == DstReg)
1437 assert(SrcReg && SrcMO.
isUse() &&
"two address instruction invalid");
1445 MRI->constrainRegClass(DstReg, RC);
1448 DEBUG(
dbgs() <<
"\t\trewrite undef:\t" << *MI);
1451 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1459 TwoAddressInstructionPass::processTiedPairs(
MachineInstr *MI,
1460 TiedPairList &TiedPairs,
1462 bool IsEarlyClobber =
false;
1463 for (
unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1468 bool RemovedKillFlag =
false;
1469 bool AllUsesCopied =
true;
1470 unsigned LastCopiedReg = 0;
1473 unsigned SubRegB = 0;
1474 for (
unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1475 unsigned SrcIdx = TiedPairs[tpi].first;
1476 unsigned DstIdx = TiedPairs[tpi].second;
1479 unsigned RegA = DstMO.
getReg();
1490 AllUsesCopied =
false;
1493 LastCopiedReg = RegA;
1496 "cannot make instruction into two-address form");
1510 TII->get(TargetOpcode::COPY), RegA);
1513 MIB.
addReg(RegB, 0, SubRegB);
1517 assert(TRI->getMatchingSuperRegClass(RC,
MRI->getRegClass(RegA),
1519 "tied subregister must be a truncation");
1524 assert(TRI->getMatchingSuperReg(RegA, SubRegB,
MRI->getRegClass(RegB))
1525 &&
"tied subregister must be a truncation");
1532 DistanceMap.insert(std::make_pair(&*PrevMI, Dist));
1533 DistanceMap[
MI] = ++Dist;
1536 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).
getRegSlot();
1542 LIS->getInstructionIndex(*MI).
getRegSlot(IsEarlyClobber);
1543 LI.
addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1547 DEBUG(
dbgs() <<
"\t\tprepend:\t" << *MIB);
1551 "inconsistent operand info for 2-reg pass");
1554 RemovedKillFlag =
true;
1560 MRI->constrainRegClass(RegA, RC);
1568 SrcRegMap[RegA] = RegB;
1571 if (AllUsesCopied) {
1572 if (!IsEarlyClobber) {
1579 RemovedKillFlag =
true;
1581 MO.
setReg(LastCopiedReg);
1588 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) {
1591 LV->addVirtualRegisterKilled(RegB, *PrevMI);
1597 SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
1599 assert(I != LI.
end() &&
"RegB must be live-in to use.");
1602 if (I->end == UseIdx)
1606 }
else if (RemovedKillFlag) {
1624 MRI = &MF->getRegInfo();
1625 TII = MF->getSubtarget().getInstrInfo();
1627 InstrItins = MF->getSubtarget().getInstrItineraryData();
1628 LV = getAnalysisIfAvailable<LiveVariables>();
1629 LIS = getAnalysisIfAvailable<LiveIntervals>();
1630 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
1633 bool MadeChange =
false;
1635 DEBUG(
dbgs() <<
"********** REWRITING TWO-ADDR INSTRS **********\n");
1637 << MF->getName() <<
'\n');
1642 TiedOperandMap TiedOperands;
1644 MBBI != MBBE; ++MBBI) {
1647 DistanceMap.clear();
1654 if (mi->isDebugValue()) {
1661 if (mi->isRegSequence())
1662 eliminateRegSequence(mi);
1664 DistanceMap.insert(std::make_pair(&*mi, ++Dist));
1670 if (!collectTiedOperands(&*mi, TiedOperands)) {
1675 ++NumTwoAddressInstrs;
1682 if (TiedOperands.size() == 1) {
1684 = TiedOperands.
begin()->second;
1685 if (TiedPairs.
size() == 1) {
1686 unsigned SrcIdx = TiedPairs[0].first;
1687 unsigned DstIdx = TiedPairs[0].second;
1688 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1689 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1690 if (SrcReg != DstReg &&
1691 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist,
false)) {
1694 TiedOperands.clear();
1702 for (
auto &TO : TiedOperands) {
1703 processTiedPairs(&*mi, TO.second, Dist);
1704 DEBUG(
dbgs() <<
"\t\trewrite to:\t" << *mi);
1708 if (mi->isInsertSubreg()) {
1711 unsigned SubIdx = mi->getOperand(3).getImm();
1712 mi->RemoveOperand(3);
1713 assert(mi->getOperand(0).getSubReg() == 0 &&
"Unexpected subreg idx");
1714 mi->getOperand(0).setSubReg(SubIdx);
1715 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1716 mi->RemoveOperand(1);
1717 mi->setDesc(
TII->get(TargetOpcode::COPY));
1718 DEBUG(
dbgs() <<
"\t\tconvert to:\t" << *mi);
1723 TiedOperands.clear();
1729 MF->verify(
this,
"After two-address instruction pass");
1745 void TwoAddressInstructionPass::
1752 DEBUG(
dbgs() <<
"Illegal REG_SEQUENCE instruction:" << MI);
1763 bool DefEmitted =
false;
1766 unsigned SrcReg = UseMO.
getReg();
1774 bool isKill = UseMO.
isKill();
1776 for (
unsigned j =
i + 2; j < e; j += 2)
1786 TII->get(TargetOpcode::COPY))
1801 LV->replaceKillInstruction(SrcReg, MI, *CopyMI);
1803 DEBUG(
dbgs() <<
"Inserted: " << *CopyMI);
1810 DEBUG(
dbgs() <<
"Turned: " << MI <<
" into an IMPLICIT_DEF");
1811 MI.
setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
1821 LIS->repairIntervalsInRange(
MBB, MBBI, EndMBBI, OrigRegs);
void push_back(const T &Elt)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
STATISTIC(NumFunctions,"Total number of functions")
static MachineInstr * getSingleDef(unsigned Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI)
Return the MachineInstr* if it is the single def of the Reg in current BB.
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
static unsigned getMappedReg(unsigned Reg, DenseMap< unsigned, unsigned > &RegMap)
Return the physical register the specified virtual register might be mapped to.
static bool isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
LiveInterval - This class represents the liveness of a register, or stack slot.
Describe properties that are true of each instruction in the target description file.
void setIsUndef(bool Val=true)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass,"twoaddressinstruction","Two-Address instruction pass", false, false) INITIALIZE_PASS_END(TwoAddressInstructionPass
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
MachineInstrBundleIterator< MachineInstr > iterator
VNInfo - Value Number Information.
iterator_range< mop_iterator > operands()
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
static bool regOverlapsSet(const SmallVectorImpl< unsigned > &Set, unsigned Reg, const TargetRegisterInfo *TRI)
MCInst const & instruction(MCInst const &MCB, size_t Index)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Reg
All possible values of the reg field in the ModR/M byte.
void initializeTwoAddressInstructionPassPass(PassRegistry &)
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
static bool regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI)
Return true if the two registers are equal or aliased.
Two Address instruction false
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
AnalysisUsage & addPreservedID(const void *ID)
Itinerary data supplied by a subtarget to be used by a target.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
bool isInsertSubreg() const
bool isEarlyClobber() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
bool hasAtLeastOneValue() const
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineInstrBuilder & UseMI
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const MachineOperand & getOperand(unsigned i) const
Two Address instruction pass
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
self_iterator getIterator()
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
static MachineInstr * findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys)
Given a register, if has a single in-basic block use, return the use instruction if it's a copy or a ...
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setIsKill(bool Val=true)
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Segments::const_iterator const_iterator
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys)
Return true if the specified MI is a copy instruction or an extract_subreg instruction.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool hasOneUse(unsigned RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
LiveInterval & getInterval(unsigned Reg)
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isSubregToReg() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
def_iterator def_begin(unsigned RegNo) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void setSubReg(unsigned subReg)
iterator find(const KeyT &Val)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
bool isNotInMIMap(const MachineInstr &Instr) const
isNotInMIMap - returns true if the specified machine instr has been removed or was never entered in t...
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
Primary interface to the complete machine description for the target machine.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
SlotIndex - An opaque wrapper around machine indexes.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg)
Return true if the specified MI uses the specified register as a two-address use. ...