LLVM  4.0.0
SchedulerRegistry.h
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1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the implementation for instruction scheduler function
11 // pass registry (RegisterScheduler).
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
16 #define LLVM_CODEGEN_SCHEDULERREGISTRY_H
17 
20 
21 namespace llvm {
22 
23 //===----------------------------------------------------------------------===//
24 ///
25 /// RegisterScheduler class - Track the registration of instruction schedulers.
26 ///
27 //===----------------------------------------------------------------------===//
28 
29 class SelectionDAGISel;
30 class ScheduleDAGSDNodes;
31 class SelectionDAG;
32 class MachineBasicBlock;
33 
35 public:
36  typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
38 
40 
41  RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
43  { Registry.Add(this); }
44  ~RegisterScheduler() { Registry.Remove(this); }
45 
46 
47  // Accessors.
48  //
51  }
53  return (RegisterScheduler *)Registry.getList();
54  }
56  Registry.setListener(L);
57  }
58 };
59 
60 /// createBURRListDAGScheduler - This creates a bottom up register usage
61 /// reduction list scheduler.
62 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
63  CodeGenOpt::Level OptLevel);
64 
65 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
66 /// schedules nodes in source code order when possible.
67 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
68  CodeGenOpt::Level OptLevel);
69 
70 /// createHybridListDAGScheduler - This creates a bottom up register pressure
71 /// aware list scheduler that make use of latency information to avoid stalls
72 /// for long latency instructions in low register pressure mode. In high
73 /// register pressure mode it schedules to reduce register pressure.
74 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
76 
77 /// createILPListDAGScheduler - This creates a bottom up register pressure
78 /// aware list scheduler that tries to increase instruction level parallelism
79 /// in low register pressure mode. In high register pressure mode it schedules
80 /// to reduce register pressure.
81 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
83 
84 /// createFastDAGScheduler - This creates a "fast" scheduler.
85 ///
86 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
87  CodeGenOpt::Level OptLevel);
88 
89 /// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
90 /// DFA driven list scheduler with clustering heuristic to control
91 /// register pressure.
92 ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
93  CodeGenOpt::Level OptLevel);
94 /// createDefaultScheduler - This creates an instruction scheduler appropriate
95 /// for the target.
96 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
97  CodeGenOpt::Level OptLevel);
98 
99 /// createDAGLinearizer - This creates a "no-scheduling" scheduler which
100 /// linearize the DAG using topological order.
101 ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
102  CodeGenOpt::Level OptLevel);
103 
104 } // end namespace llvm
105 
106 #endif
MachineLoop * L
ScheduleDAGSDNodes *(* FunctionPassCtor)(SelectionDAGISel *, CodeGenOpt::Level)
static void setListener(MachinePassRegistryListener *L)
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:45
void *(* MachinePassCtor)()
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
static MachinePassRegistry Registry
RegisterScheduler class - Track the registration of instruction schedulers.
RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
ScheduleDAGSDNodes * createDAGLinearizer(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topologi...
MachinePassRegistry - Track the registration of machine passes.
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source c...
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target...
ScheduleDAGSDNodes * createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler...
MachinePassRegistryNode * getNext() const
static RegisterScheduler * getList()
ScheduleDAGSDNodes * createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level)
createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that trie...
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
MachinePassRegistryListener - Listener to adds and removals of nodes in registration list...
RegisterScheduler * getNext() const
#define N
MachinePassRegistryNode - Machine pass node stored in registration list.
ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel)
createFastDAGScheduler - This creates a "fast" scheduler.