LLVM  4.0.0
ARMTargetMachine.cpp
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1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMTargetMachine.h"
14 #include "ARM.h"
15 #include "ARMCallLowering.h"
16 #include "ARMFrameLowering.h"
17 #include "ARMInstructionSelector.h"
18 #include "ARMLegalizerInfo.h"
19 #include "ARMRegisterBankInfo.h"
20 #include "ARMTargetObjectFile.h"
21 #include "ARMTargetTransformInfo.h"
26 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/IR/Function.h"
30 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/Transforms/Scalar.h"
37 using namespace llvm;
38 
39 static cl::opt<bool>
40 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
41  cl::desc("Inhibit optimization of S->D register accesses on A15"),
42  cl::init(false));
43 
44 static cl::opt<bool>
45 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
46  cl::desc("Run SimplifyCFG after expanding atomic operations"
47  " to make use of cmpxchg flow-based information"),
48  cl::init(true));
49 
50 static cl::opt<bool>
51 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
52  cl::desc("Enable ARM load/store optimization pass"),
53  cl::init(true));
54 
55 // FIXME: Unify control over GlobalMerge.
57 EnableGlobalMerge("arm-global-merge", cl::Hidden,
58  cl::desc("Enable the global merge pass"));
59 
60 extern "C" void LLVMInitializeARMTarget() {
61  // Register the target.
66 
68  initializeGlobalISel(Registry);
71 }
72 
73 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
74  if (TT.isOSBinFormatMachO())
75  return make_unique<TargetLoweringObjectFileMachO>();
76  if (TT.isOSWindows())
77  return make_unique<TargetLoweringObjectFileCOFF>();
78  return make_unique<ARMElfTargetObjectFile>();
79 }
80 
83  const TargetOptions &Options) {
84  if (Options.MCOptions.getABIName() == "aapcs16")
86  else if (Options.MCOptions.getABIName().startswith("aapcs"))
88  else if (Options.MCOptions.getABIName().startswith("apcs"))
90 
91  assert(Options.MCOptions.getABIName().empty() &&
92  "Unknown target-abi option!");
93 
96 
97  unsigned ArchKind = llvm::ARM::parseCPUArch(CPU);
98  StringRef ArchName = llvm::ARM::getArchName(ArchKind);
99  // FIXME: This is duplicated code from the front end and should be unified.
100  if (TT.isOSBinFormatMachO()) {
101  if (TT.getEnvironment() == llvm::Triple::EABI ||
105  } else if (TT.isWatchABI()) {
107  } else {
109  }
110  } else if (TT.isOSWindows()) {
111  // FIXME: this is invalid for WindowsCE
113  } else {
114  // Select the default based on the platform.
115  switch (TT.getEnvironment()) {
122  case llvm::Triple::EABI:
124  break;
125  case llvm::Triple::GNU:
127  break;
128  default:
129  if (TT.isOSNetBSD())
131  else
133  break;
134  }
135  }
136 
137  return TargetABI;
138 }
139 
140 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
141  const TargetOptions &Options,
142  bool isLittle) {
143  auto ABI = computeTargetABI(TT, CPU, Options);
144  std::string Ret = "";
145 
146  if (isLittle)
147  // Little endian.
148  Ret += "e";
149  else
150  // Big endian.
151  Ret += "E";
152 
154 
155  // Pointers are 32 bits and aligned to 32 bits.
156  Ret += "-p:32:32";
157 
158  // ABIs other than APCS have 64 bit integers with natural alignment.
160  Ret += "-i64:64";
161 
162  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
163  // bits, others to 64 bits. We always try to align to 64 bits.
165  Ret += "-f64:32:64";
166 
167  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
168  // to 64. We always ty to give them natural alignment.
170  Ret += "-v64:32:64-v128:32:128";
172  Ret += "-v128:64:128";
173 
174  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
175  // particular hardware support on 32-bit ARM).
176  Ret += "-a:0:32";
177 
178  // Integer registers are 32 bits.
179  Ret += "-n32";
180 
181  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
182  // aligned everywhere else.
184  Ret += "-S128";
185  else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
186  Ret += "-S64";
187  else
188  Ret += "-S32";
189 
190  return Ret;
191 }
192 
195  if (!RM.hasValue())
196  // Default relocation model on Darwin is PIC.
198 
199  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
200  assert(TT.isOSBinFormatELF() &&
201  "ROPI/RWPI currently only supported for ELF");
202 
203  // DynamicNoPIC is only used on darwin.
204  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
205  return Reloc::Static;
206 
207  return *RM;
208 }
209 
210 /// Create an ARM architecture model.
211 ///
213  StringRef CPU, StringRef FS,
214  const TargetOptions &Options,
216  CodeModel::Model CM,
217  CodeGenOpt::Level OL, bool isLittle)
218  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
219  CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM,
220  OL),
221  TargetABI(computeTargetABI(TT, CPU, Options)),
222  TLOF(createTLOF(getTargetTriple())),
223  Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
224 
225  // Default to triple-appropriate float ABI
226  if (Options.FloatABIType == FloatABI::Default)
227  this->Options.FloatABIType =
229 
230  // Default to triple-appropriate EABI
231  if (Options.EABIVersion == EABI::Default ||
232  Options.EABIVersion == EABI::Unknown) {
233  // musl is compatible with glibc with regard to EABI version
235  this->Options.EABIVersion = EABI::GNU;
236  else
237  this->Options.EABIVersion = EABI::EABI5;
238  }
239 }
240 
242 
243 #ifdef LLVM_BUILD_GLOBAL_ISEL
244 namespace {
245 struct ARMGISelActualAccessor : public GISelAccessor {
246  std::unique_ptr<CallLowering> CallLoweringInfo;
247  std::unique_ptr<InstructionSelector> InstSelector;
248  std::unique_ptr<LegalizerInfo> Legalizer;
249  std::unique_ptr<RegisterBankInfo> RegBankInfo;
250  const CallLowering *getCallLowering() const override {
251  return CallLoweringInfo.get();
252  }
253  const InstructionSelector *getInstructionSelector() const override {
254  return InstSelector.get();
255  }
256  const LegalizerInfo *getLegalizerInfo() const override {
257  return Legalizer.get();
258  }
259  const RegisterBankInfo *getRegBankInfo() const override {
260  return RegBankInfo.get();
261  }
262 };
263 } // End anonymous namespace.
264 #endif
265 
266 const ARMSubtarget *
268  Attribute CPUAttr = F.getFnAttribute("target-cpu");
269  Attribute FSAttr = F.getFnAttribute("target-features");
270 
271  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
272  ? CPUAttr.getValueAsString().str()
273  : TargetCPU;
274  std::string FS = !FSAttr.hasAttribute(Attribute::None)
275  ? FSAttr.getValueAsString().str()
276  : TargetFS;
277 
278  // FIXME: This is related to the code below to reset the target options,
279  // we need to know whether or not the soft float flag is set on the
280  // function before we can generate a subtarget. We also need to use
281  // it as a key for the subtarget since that can be the only difference
282  // between two functions.
283  bool SoftFloat =
284  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
285  // If the soft float attribute is set on the function turn on the soft float
286  // subtarget feature.
287  if (SoftFloat)
288  FS += FS.empty() ? "+soft-float" : ",+soft-float";
289 
290  auto &I = SubtargetMap[CPU + FS];
291  if (!I) {
292  // This needs to be done before we create a new subtarget since any
293  // creation will depend on the TM and the code generation flags on the
294  // function that reside in TargetOptions.
296  I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
297 
298 #ifndef LLVM_BUILD_GLOBAL_ISEL
299  GISelAccessor *GISel = new GISelAccessor();
300 #else
301  ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();
302  GISel->CallLoweringInfo.reset(new ARMCallLowering(*I->getTargetLowering()));
303  GISel->Legalizer.reset(new ARMLegalizerInfo());
304 
305  auto *RBI = new ARMRegisterBankInfo(*I->getRegisterInfo());
306 
307  // FIXME: At this point, we can't rely on Subtarget having RBI.
308  // It's awkward to mix passing RBI and the Subtarget; should we pass
309  // TII/TRI as well?
310  GISel->InstSelector.reset(new ARMInstructionSelector(*I, *RBI));
311 
312  GISel->RegBankInfo.reset(RBI);
313 #endif
314  I->setGISelAccessor(*GISel);
315  }
316  return I.get();
317 }
318 
320  return TargetIRAnalysis([this](const Function &F) {
321  return TargetTransformInfo(ARMTTIImpl(this, F));
322  });
323 }
324 
325 void ARMTargetMachine::anchor() {}
326 
328  StringRef CPU, StringRef FS,
329  const TargetOptions &Options,
332  bool isLittle)
333  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
334  initAsmInfo();
335  if (!Subtarget.hasARMOps())
336  report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
337  "support ARM mode execution!");
338 }
339 
340 void ARMLETargetMachine::anchor() {}
341 
343  StringRef CPU, StringRef FS,
344  const TargetOptions &Options,
346  CodeModel::Model CM,
348  : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
349 
350 void ARMBETargetMachine::anchor() {}
351 
353  StringRef CPU, StringRef FS,
354  const TargetOptions &Options,
356  CodeModel::Model CM,
358  : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
359 
360 void ThumbTargetMachine::anchor() {}
361 
363  StringRef CPU, StringRef FS,
364  const TargetOptions &Options,
366  CodeModel::Model CM,
367  CodeGenOpt::Level OL, bool isLittle)
368  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
369  initAsmInfo();
370 }
371 
372 void ThumbLETargetMachine::anchor() {}
373 
375  StringRef CPU, StringRef FS,
376  const TargetOptions &Options,
378  CodeModel::Model CM,
380  : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
381 
382 void ThumbBETargetMachine::anchor() {}
383 
385  StringRef CPU, StringRef FS,
386  const TargetOptions &Options,
388  CodeModel::Model CM,
390  : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
391 
392 namespace {
393 /// ARM Code Generator Pass Configuration Options.
394 class ARMPassConfig : public TargetPassConfig {
395 public:
396  ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
397  : TargetPassConfig(TM, PM) {}
398 
399  ARMBaseTargetMachine &getARMTargetMachine() const {
400  return getTM<ARMBaseTargetMachine>();
401  }
402 
403  void addIRPasses() override;
404  bool addPreISel() override;
405  bool addInstSelector() override;
406 #ifdef LLVM_BUILD_GLOBAL_ISEL
407  bool addIRTranslator() override;
408  bool addLegalizeMachineIR() override;
409  bool addRegBankSelect() override;
410  bool addGlobalInstructionSelect() override;
411 #endif
412  void addPreRegAlloc() override;
413  void addPreSched2() override;
414  void addPreEmitPass() override;
415 };
416 } // namespace
417 
419  return new ARMPassConfig(this, PM);
420 }
421 
422 void ARMPassConfig::addIRPasses() {
423  if (TM->Options.ThreadModel == ThreadModel::Single)
424  addPass(createLowerAtomicPass());
425  else
426  addPass(createAtomicExpandPass(TM));
427 
428  // Cmpxchg instructions are often used with a subsequent comparison to
429  // determine whether it succeeded. We can exploit existing control-flow in
430  // ldrex/strex loops to simplify this, but it needs tidying up.
431  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
432  addPass(createCFGSimplificationPass(-1, [this](const Function &F) {
433  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
434  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
435  }));
436 
438 
439  // Match interleaved memory accesses to ldN/stN intrinsics.
440  if (TM->getOptLevel() != CodeGenOpt::None)
442 }
443 
444 bool ARMPassConfig::addPreISel() {
445  if ((TM->getOptLevel() != CodeGenOpt::None &&
447  EnableGlobalMerge == cl::BOU_TRUE) {
448  // FIXME: This is using the thumb1 only constant value for
449  // maximal global offset for merging globals. We may want
450  // to look into using the old value for non-thumb1 code of
451  // 4095 based on the TargetMachine, but this starts to become
452  // tricky when doing code gen per function.
453  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
454  (EnableGlobalMerge == cl::BOU_UNSET);
455  // Merging of extern globals is enabled by default on non-Mach-O as we
456  // expect it to be generally either beneficial or harmless. On Mach-O it
457  // is disabled as we emit the .subsections_via_symbols directive which
458  // means that merging extern globals is not safe.
459  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
460  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
461  MergeExternalByDefault));
462  }
463 
464  return false;
465 }
466 
467 bool ARMPassConfig::addInstSelector() {
468  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
469  return false;
470 }
471 
472 #ifdef LLVM_BUILD_GLOBAL_ISEL
473 bool ARMPassConfig::addIRTranslator() {
474  addPass(new IRTranslator());
475  return false;
476 }
477 
478 bool ARMPassConfig::addLegalizeMachineIR() {
479  addPass(new Legalizer());
480  return false;
481 }
482 
483 bool ARMPassConfig::addRegBankSelect() {
484  addPass(new RegBankSelect());
485  return false;
486 }
487 
488 bool ARMPassConfig::addGlobalInstructionSelect() {
489  addPass(new InstructionSelect());
490  return false;
491 }
492 #endif
493 
494 void ARMPassConfig::addPreRegAlloc() {
495  if (getOptLevel() != CodeGenOpt::None) {
496  addPass(createMLxExpansionPass());
497 
499  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
500 
502  addPass(createA15SDOptimizerPass());
503  }
504 }
505 
506 void ARMPassConfig::addPreSched2() {
507  if (getOptLevel() != CodeGenOpt::None) {
510 
511  addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
512  }
513 
514  // Expand some pseudo instructions into multiple instructions to allow
515  // proper scheduling.
516  addPass(createARMExpandPseudoPass());
517 
518  if (getOptLevel() != CodeGenOpt::None) {
519  // in v8, IfConversion depends on Thumb instruction widths
520  addPass(createThumb2SizeReductionPass([this](const Function &F) {
521  return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
522  }));
523 
524  addPass(createIfConverter([](const MachineFunction &MF) {
525  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
526  }));
527  }
528  addPass(createThumb2ITBlockPass());
529 }
530 
531 void ARMPassConfig::addPreEmitPass() {
533 
534  // Constant island pass work on unbundled instructions.
535  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
536  return MF.getSubtarget<ARMSubtarget>().isThumb2();
537  }));
538 
539  // Don't optimize barriers at -O0.
540  if (getOptLevel() != CodeGenOpt::None)
542 
543  addPass(createARMConstantIslandPass());
544 }
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
Definition: Triple.h:279
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
Definition: GISelAccessor.h:29
Thumb target machine.
FunctionPass * createA15SDOptimizerPass()
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
FunctionPass * createMLxExpansionPass()
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:575
unsigned parseCPUArch(StringRef CPU)
TargetIRAnalysis getTargetIRAnalysis() override
Get the TargetIRAnalysis for this target.
MCTargetOptions MCOptions
Machine level options.
bool hasValue() const
Definition: Optional.h:125
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const std::string & getCPUString() const
Definition: ARMSubtarget.h:611
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:45
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass...
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
This class provides the information for the target register banks.
Analysis pass providing the TargetTransformInfo.
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass...
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:234
Target & getTheThumbLETarget()
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:185
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:155
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:540
Holds all the information related to register banks.
StringRef getArchName(unsigned ArchKind)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void initializeGlobalISel(PassRegistry &Registry)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:21
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
No attributes have been set.
Definition: Attributes.h:69
ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
Target & getTheARMBETarget()
Target-Independent Code Generator Pass Configuration Options.
ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
#define F(x, y, z)
Definition: MD5.cpp:51
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:264
void LLVMInitializeARMTarget()
Target & getTheThumbBETarget()
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:545
Function Alias Analysis false
This class provides the information for the target register banks.
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
bool hasARMOps() const
Definition: ARMSubtarget.h:443
FunctionPass * createInterleavedAccessPass(const TargetMachine *TM)
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
bool isOSNetBSD() const
Definition: Triple.h:459
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
void initializeARMLoadStoreOptPass(PassRegistry &)
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
This file declares the targeting of the RegisterBankInfo class for ARM.
bool isTargetHardFloat() const
Definition: ARMSubtarget.h:557
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:83
const ARMSubtarget * getSubtargetImpl() const
This file declares the targeting of the Machinelegalizer class for ARM.
FunctionPass * createCFGSimplificationPass(int Threshold=-1, std::function< bool(const Function &)> Ftor=nullptr)
ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle)
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:225
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
ARM target machine.
ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle)
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:455
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
FunctionPass * createExecutionDependencyFixPass(const TargetRegisterClass *RC)
createExecutionDependencyFixPass - This pass fixes execution time problems with dependent instruction...
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Pass * createLowerAtomicPass()
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:130
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:533
bool isWatchABI() const
Definition: Triple.h:450
Provides the logic to select generic machine instructions.
Basic Alias true
This file declares the targeting of the InstructionSelector class for ARM.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations"" to make use of cmpxchg flow-based information"), cl::init(true))
unsigned parseArchProfile(StringRef Arch)
#define I(x, y, z)
Definition: MD5.cpp:54
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:288
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:178
This file declares the IRTranslator pass.
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:538
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:40
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
This file describes how to lower LLVM calls to machine code calls.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
Target & getTheARMLETarget()
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...