|
LLVM
4.0.0
|
| enum llvm::X86ISD::NodeType : unsigned |
| Enumerator | |
|---|---|
| FIRST_NUMBER | |
| BSF |
Bit scan forward. |
| BSR |
Bit scan reverse. |
| SHLD |
Double shift instructions. These correspond to X86::SHLDxx and X86::SHRDxx instructions. |
| SHRD | |
| FAND |
Bitwise logical AND of floating point values. This corresponds to X86::ANDPS or X86::ANDPD. |
| FOR |
Bitwise logical OR of floating point values. This corresponds to X86::ORPS or X86::ORPD. |
| FXOR |
Bitwise logical XOR of floating point values. This corresponds to X86::XORPS or X86::XORPD. |
| FANDN |
Bitwise logical ANDNOT of floating point values. This corresponds to X86::ANDNPS or X86::ANDNPD. |
| CALL |
These operations represent an abstract X86 call instruction, which includes a bunch of information. In particular the operands of these node are: #0 - The incoming token chain #1 - The callee #2 - The number of arg bytes the caller pushes on the stack. #3 - The number of arg bytes the callee pops off the stack. #4 - The value to pass in AL/AX/EAX (optional) #5 - The value to pass in DL/DX/EDX (optional) The result values of these nodes are: #0 - The outgoing token chain #1 - The first register result value (optional) #2 - The second register result value (optional) |
| RDTSC_DAG |
This operation implements the lowering for readcyclecounter. |
| RDTSCP_DAG |
X86 Read Time-Stamp Counter and Processor ID. |
| RDPMC_DAG |
X86 Read Performance Monitoring Counters. |
| CMP |
X86 compare and logical compare instructions. |
| COMI | |
| UCOMI | |
| BT |
X86 bit-test instructions. |
| SETCC |
X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS operand, usually produced by a CMP instruction. |
| SELECT |
X86 Select. |
| SELECTS | |
| SETCC_CARRY | |
| FSETCC |
X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. Operands are two FP values to compare; result is a mask of 0s or 1s. Generally DTRT for C/C++ with NaNs. |
| FSETCCM |
X86 FP SETCC, similar to above, but with output as an i1 mask and with optional rounding mode. |
| FSETCCM_RND | |
| CMOV |
X86 conditional moves. Operand 0 and operand 1 are the two values to select from. Operand 2 is the condition code, and operand 3 is the flag operand produced by a CMP or TEST instruction. It also writes a flag result. |
| BRCOND |
X86 conditional branches. Operand 0 is the chain operand, operand 1 is the block to branch if condition is true, operand 2 is the condition code, and operand 3 is the flag operand produced by a CMP or TEST instruction. |
| RET_FLAG |
Return with a flag operand. Operand 0 is the chain operand, operand 1 is the number of bytes of stack to pop. |
| IRET |
Return from interrupt. Operand 0 is the number of bytes to pop. |
| REP_STOS |
Repeat fill, corresponds to X86::REP_STOSx. |
| REP_MOVS |
Repeat move, corresponds to X86::REP_MOVSx. |
| GlobalBaseReg |
On Darwin, this node represents the result of the popl at function entry, used for PIC code. |
| Wrapper |
A wrapper node for TargetConstantPool, TargetJumpTable, TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, MCSymbol and TargetBlockAddress. |
| WrapperRIP |
Special wrapper used under X86-64 PIC mode for RIP relative displacements. |
| MOVDQ2Q |
Copies a 64-bit value from the low word of an XMM vector to an MMX vector. If you think this is too close to the previous mnemonic, so do I; blame Intel. |
| MMX_MOVD2W |
Copies a 32-bit value from the low word of a MMX vector to a GPR. |
| MMX_MOVW2D |
Copies a GPR into the low 32-bit word of a MMX vector and zero out the high word. |
| PEXTRB |
Extract an 8-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRB. |
| PEXTRW |
Extract a 16-bit value from a vector and zero extend it to i32, corresponds to X86::PEXTRW. |
| INSERTPS |
Insert any element of a 4 x float vector into any element of a destination 4 x floatvector. |
| PINSRB |
Insert the lower 8-bits of a 32-bit value to a vector, corresponds to X86::PINSRB. |
| PINSRW |
Insert the lower 16-bits of a 32-bit value to a vector, corresponds to X86::PINSRW. |
| MMX_PINSRW | |
| PSHUFB |
Shuffle 16 8-bit values within a vector. |
| PSADBW |
Compute Sum of Absolute Differences. |
| DBPSADBW |
Compute Double Block Packed Sum-Absolute-Differences. |
| ANDNP |
Bitwise Logical AND NOT of Packed FP values. |
| BLENDI |
Blend where the selector is an immediate. |
| SHRUNKBLEND |
Blend where the condition has been shrunk. This is used to emphasize that the condition mask is no more valid for generic VSELECT optimizations. |
| ADDSUB |
Combined add and sub on an FP vector. |
| FADD_RND | |
| FSUB_RND | |
| FMUL_RND | |
| FDIV_RND | |
| FMAX_RND | |
| FMIN_RND | |
| FSQRT_RND | |
| FSQRTS_RND | |
| FGETEXP_RND | |
| FGETEXPS_RND | |
| VGETMANT | |
| VGETMANTS | |
| SCALEF | |
| SCALEFS | |
| ADDUS | |
| SUBUS | |
| ADDS | |
| SUBS | |
| AVG | |
| HADD |
Integer horizontal add/sub. |
| HSUB | |
| FHADD |
Floating point horizontal add/sub. |
| FHSUB | |
| ABS | |
| CONFLICT | |
| FMAX |
Floating point max and min. |
| FMIN | |
| FMAXC |
Commutative FMIN and FMAX. |
| FMINC | |
| FRSQRT |
Floating point reciprocal-sqrt and reciprocal approximation. Note that these typically require refinement in order to obtain suitable precision. |
| FRCP | |
| FRSQRTS | |
| FRCPS | |
| TLSADDR | |
| TLSBASEADDR | |
| TLSCALL | |
| EH_RETURN | |
| EH_SJLJ_SETJMP | |
| EH_SJLJ_LONGJMP | |
| EH_SJLJ_SETUP_DISPATCH | |
| TC_RETURN |
Tail call return. See X86TargetLowering::LowerCall for the list of operands. |
| VZEXT_MOVL | |
| VZEXT | |
| VSEXT | |
| VTRUNC | |
| VTRUNCUS | |
| VTRUNCS | |
| VFPEXT | |
| VFPEXT_RND | |
| VFPEXTS_RND | |
| VFPROUND | |
| VFPROUND_RND | |
| VFPROUNDS_RND | |
| CVT2MASK | |
| VSHLDQ | |
| VSRLDQ | |
| VSHL | |
| VSRL | |
| VSRA | |
| VSRAV | |
| VSHLI | |
| VSRLI | |
| VSRAI | |
| VROTLI | |
| VROTRI | |
| CMPP | |
| PCMPEQ | |
| PCMPGT | |
| PCMPEQM | |
| PCMPGTM | |
| MULTISHIFT | |
| CMPM |
Vector comparison generating mask bits for fp and integer signed and unsigned data types. |
| CMPMU | |
| CMPM_RND | |
| ADD | |
| SUB | |
| ADC | |
| SBB | |
| SMUL | |
| INC | |
| DEC | |
| OR | |
| XOR | |
| AND | |
| BEXTR | |
| UMUL | |
| SMUL8 | |
| UMUL8 | |
| UDIVREM8_ZEXT_HREG | |
| SDIVREM8_SEXT_HREG | |
| MUL_IMM | |
| MOVMSK | |
| PTEST | |
| TESTP | |
| TESTM | |
| TESTNM | |
| KORTEST | |
| KTEST | |
| PACKSS | |
| PACKUS | |
| PALIGNR | |
| VALIGN | |
| PSHUFD | |
| PSHUFHW | |
| PSHUFLW | |
| SHUFP | |
| SHUF128 | |
| MOVDDUP | |
| MOVSHDUP | |
| MOVSLDUP | |
| MOVLHPS | |
| MOVLHPD | |
| MOVHLPS | |
| MOVLPS | |
| MOVLPD | |
| MOVSD | |
| MOVSS | |
| UNPCKL | |
| UNPCKH | |
| VPERMILPV | |
| VPERMILPI | |
| VPERMI | |
| VPERM2X128 | |
| VPERMV | |
| VPERMV3 | |
| VPERMIV3 | |
| VPTERNLOG | |
| VFIXUPIMM | |
| VFIXUPIMMS | |
| VRANGE | |
| VREDUCE | |
| VREDUCES | |
| VRNDSCALE | |
| VRNDSCALES | |
| VFPCLASS | |
| VFPCLASSS | |
| VBROADCAST | |
| VBROADCASTM | |
| SUBV_BROADCAST | |
| VINSERT | |
| VEXTRACT | |
| EXTRQI |
SSE4A Extraction and Insertion. |
| INSERTQI | |
| VPROT | |
| VPROTI | |
| VPSHA | |
| VPSHL | |
| VPCOM | |
| VPCOMU | |
| VPPERM | |
| VPERMIL2 | |
| PMULUDQ | |
| PMULDQ | |
| MULHRS | |
| VPMADDUBSW | |
| VPMADDWD | |
| VPMADD52L | |
| VPMADD52H | |
| FMADD | |
| FNMADD | |
| FMSUB | |
| FNMSUB | |
| FMADDSUB | |
| FMSUBADD | |
| FMADD_RND | |
| FNMADD_RND | |
| FMSUB_RND | |
| FNMSUB_RND | |
| FMADDSUB_RND | |
| FMSUBADD_RND | |
| FMADDS1_RND | |
| FMADDS3_RND | |
| FNMADDS1_RND | |
| FNMADDS3_RND | |
| FMSUBS1_RND | |
| FMSUBS3_RND | |
| FNMSUBS1_RND | |
| FNMSUBS3_RND | |
| COMPRESS | |
| EXPAND | |
| SINT_TO_FP_RND | |
| UINT_TO_FP_RND | |
| SCALAR_SINT_TO_FP_RND | |
| SCALAR_UINT_TO_FP_RND | |
| CVTP2SI | |
| CVTP2UI | |
| CVTP2SI_RND | |
| CVTP2UI_RND | |
| CVTS2SI_RND | |
| CVTS2UI_RND | |
| CVTTP2SI | |
| CVTTP2UI | |
| CVTTP2SI_RND | |
| CVTTP2UI_RND | |
| CVTTS2SI_RND | |
| CVTTS2UI_RND | |
| CVTSI2P | |
| CVTUI2P | |
| VASTART_SAVE_XMM_REGS | |
| WIN_ALLOCA | |
| SEG_ALLOCA | |
| MEMBARRIER | |
| MFENCE | |
| FNSTSW16r | |
| SAHF | |
| RDRAND | |
| RDSEED | |
| PCMPISTRI | |
| PCMPESTRI | |
| XTEST | |
| RSQRT28 | |
| RSQRT28S | |
| RCP28 | |
| RCP28S | |
| EXP2 | |
| CVTPS2PH | |
| CVTPH2PS | |
| LCMPXCHG_DAG | |
| LCMPXCHG8_DAG | |
| LCMPXCHG16_DAG | |
| LCMPXCHG8_SAVE_EBX_DAG | |
| LCMPXCHG16_SAVE_RBX_DAG | |
| LADD |
LOCK-prefixed arithmetic read-modify-write instructions. EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS) |
| LSUB | |
| LOR | |
| LXOR | |
| LAND | |
| VZEXT_LOAD | |
| FNSTCW16m | |
| FP_TO_INT16_IN_MEM |
This instruction implements FP_TO_SINT with the integer destination in memory and a FP reg source. This corresponds to the X86::FIST*m instructions and the rounding mode change stuff. It has two inputs (token chain and address) and two outputs (int value and token chain). |
| FP_TO_INT32_IN_MEM | |
| FP_TO_INT64_IN_MEM | |
| FILD |
This instruction implements SINT_TO_FP with the integer source in memory and FP reg result. This corresponds to the X86::FILD*m instructions. It has three inputs (token chain, address, and source type) and two outputs (FP value and token chain). FILD_FLAG also produces a flag). |
| FILD_FLAG | |
| FLD |
This instruction implements an extending load to FP stack slots. This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain operand, ptr to load from, and a ValueType node indicating the type to load to. |
| FST |
This instruction implements a truncating store to FP stack slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a chain operand, value to store, address, and a ValueType to store it as. |
| VAARG_64 |
This instruction grabs the address of the next argument from a va_list. (reads and modifies the va_list in memory) |
| VTRUNCSTOREUS | |
| VTRUNCSTORES | |
| VMTRUNCSTOREUS | |
| VMTRUNCSTORES | |
Definition at line 29 of file X86ISelLowering.h.
1.8.6