37 #define DEBUG_TYPE "phielim"
42 "during PHI elimination"));
51 cl::desc(
"Do not use an early exit if isLiveOutPastPHIs returns true."));
93 typedef std::pair<unsigned, unsigned> BBVRegPair;
96 VRegPHIUse VRegPHIUseCount;
104 LoweredPHIMap LoweredPHIs;
108 STATISTIC(NumLowered,
"Number of phis lowered");
109 STATISTIC(NumCriticalEdgesSplit,
"Number of critical edges split");
110 STATISTIC(NumReused,
"Number of reused lowered phis");
116 "Eliminate PHI nodes for register allocation",
122 void PHIElimination::getAnalysisUsage(
AnalysisUsage &AU)
const {
134 LV = getAnalysisIfAvailable<LiveVariables>();
135 LIS = getAnalysisIfAvailable<LiveIntervals>();
137 bool Changed =
false;
147 Changed |= SplitPHIEdges(MF,
MBB, MLI);
155 Changed |= EliminatePHINodes(MF,
MBB);
159 unsigned DefReg = DefMI->getOperand(0).getReg();
160 if (
MRI->use_nodbg_empty(DefReg)) {
162 LIS->RemoveMachineInstrFromMaps(*DefMI);
163 DefMI->eraseFromParent();
168 for (
auto &
I : LoweredPHIs) {
170 LIS->RemoveMachineInstrFromMaps(*
I.first);
171 MF.DeleteMachineInstr(
I.first);
176 VRegPHIUseCount.clear();
197 LowerPHINode(MBB, LastPHIIt);
207 if (!DI.isImplicitDef())
241 unsigned IncomingReg = 0;
242 bool reusedIncoming =
false;
252 TII->
get(TargetOpcode::IMPLICIT_DEF), DestReg);
256 unsigned &entry = LoweredPHIs[MPhi];
260 reusedIncoming =
true;
268 TII->
get(TargetOpcode::COPY), DestReg)
269 .addReg(IncomingReg);
280 LV->setPHIJoin(IncomingReg);
287 DEBUG(
dbgs() <<
"Remove old kill from " << *OldKill);
288 LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
296 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
302 LV->removeVirtualRegistersKilled(*MPhi);
306 LV->addVirtualRegisterDead(DestReg, PHICopy);
307 LV->removeVirtualRegisterDead(DestReg, *MPhi);
314 LIS->InsertMachineInstrInMaps(*std::prev(AfterPHIsIt));
316 SlotIndex MBBStartIndex = LIS->getMBBStartIdx(&MBB);
320 LiveInterval &IncomingLI = LIS->createEmptyInterval(IncomingReg);
324 LIS->getVNInfoAllocator());
325 IncomingLI.
addSegment(LiveInterval::Segment(MBBStartIndex,
332 "PHIs should have nonempty LiveIntervals.");
338 assert(OrigDestVNI &&
"PHI destination should be live at block entry.");
341 LIS->getVNInfoAllocator());
348 assert(DestVNI &&
"PHI destination should be live at its definition.");
361 for (
int i = NumSrcs - 1;
i >= 0; --
i) {
367 "Machine PHI Operands must all be virtual registers!");
376 if (!MBBsInsertedInto.
insert(&opBlock).second)
386 if (!reusedIncoming && IncomingReg) {
392 TII->
get(TargetOpcode::IMPLICIT_DEF),
397 if (DefMI->isImplicitDef())
398 ImpDefs.insert(DefMI);
401 TII->
get(TargetOpcode::COPY), IncomingReg)
402 .addReg(SrcReg, 0, SrcSubReg);
409 if (LV && !SrcUndef &&
410 !VRegPHIUseCount[BBVRegPair(opBlock.
getNumber(), SrcReg)] &&
411 !LV->isLiveOut(SrcReg, opBlock)) {
431 Term != opBlock.
end(); ++Term) {
432 if (Term->readsRegister(SrcReg))
436 if (KillInst == opBlock.
end()) {
439 if (reusedIncoming || !IncomingReg) {
441 KillInst = FirstTerm;
442 while (KillInst != opBlock.
begin()) {
444 if (KillInst->isDebugValue())
446 if (KillInst->readsRegister(SrcReg))
451 KillInst = std::prev(InsertPos);
454 assert(KillInst->readsRegister(SrcReg) &&
"Cannot find kill instruction");
457 LV->addVirtualRegisterKilled(SrcReg, *KillInst);
460 unsigned opBlockNum = opBlock.
getNumber();
461 LV->getVarInfo(SrcReg).AliveBlocks.reset(opBlockNum);
466 LIS->InsertMachineInstrInMaps(*NewSrcInstr);
467 LIS->addSegmentToEndOfBlock(IncomingReg, *NewSrcInstr);
471 !VRegPHIUseCount[BBVRegPair(opBlock.
getNumber(), SrcReg)]) {
477 SlotIndex startIdx = LIS->getMBBStartIdx(*SI);
481 if (VNI && VNI->
def != startIdx) {
491 Term != opBlock.
end(); ++Term) {
492 if (Term->readsRegister(SrcReg))
496 if (KillInst == opBlock.
end()) {
499 if (reusedIncoming || !IncomingReg) {
501 KillInst = FirstTerm;
502 while (KillInst != opBlock.
begin()) {
504 if (KillInst->isDebugValue())
506 if (KillInst->readsRegister(SrcReg))
511 KillInst = std::prev(InsertPos);
514 assert(KillInst->readsRegister(SrcReg) &&
515 "Cannot find kill instruction");
517 SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst);
519 LIS->getMBBEndIdx(&opBlock));
526 if (reusedIncoming || !IncomingReg) {
528 LIS->RemoveMachineInstrFromMaps(*MPhi);
539 for (
const auto &MBB : MF)
540 for (
const auto &BBI : MBB) {
543 for (
unsigned i = 1, e = BBI.getNumOperands();
i != e;
i += 2)
544 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(
i+1).getMBB()->getNumber(),
545 BBI.getOperand(
i).getReg())];
556 bool IsLoopHeader = CurLoop && &MBB == CurLoop->
getHeader();
558 bool Changed =
false;
560 BBI != BBE && BBI->isPHI(); ++BBI) {
561 for (
unsigned i = 1, e = BBI->getNumOperands();
i != e;
i += 2) {
562 unsigned Reg = BBI->getOperand(
i).getReg();
582 bool ShouldSplit = isLiveOutPastPHIs(Reg, PreMBB);
587 << PreMBB->
getNumber() <<
" -> BB#" << MBB.getNumber()
599 ShouldSplit = ShouldSplit && !isLiveIn(Reg, &MBB);
602 if (!ShouldSplit && CurLoop != PreLoop) {
604 dbgs() <<
"Split wouldn't help, maybe avoid loop copies?\n";
605 if (PreLoop)
dbgs() <<
"PreLoop: " << *PreLoop;
606 if (CurLoop)
dbgs() <<
"CurLoop: " << *CurLoop;
612 ShouldSplit = PreLoop && !PreLoop->
contains(CurLoop);
617 DEBUG(
dbgs() <<
"Failed to split critical edge.\n");
621 ++NumCriticalEdgesSplit;
629 "isLiveIn() requires either LiveVariables or LiveIntervals");
631 return LIS->isLiveInToMBB(LIS->getInterval(Reg),
MBB);
633 return LV->isLiveIn(Reg, *MBB);
636 bool PHIElimination::isLiveOutPastPHIs(
unsigned Reg,
639 "isLiveOutPastPHIs() requires either LiveVariables or LiveIntervals");
648 if (LI.
liveAt(LIS->getMBBStartIdx(SI)))
652 return LV->isLiveOut(Reg, *MBB);
unsigned succ_size() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isEHPad() const
Returns true if the block is a landing pad.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SlotIndex def
The index of the defining instruction.
STATISTIC(NumFunctions,"Total number of functions")
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, unsigned SrcReg)
findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...
phi node Eliminate PHI nodes for register false
static cl::opt< bool > DisableEdgeSplitting("disable-phi-elim-edge-splitting", cl::init(false), cl::Hidden, cl::desc("Disable critical edge splitting ""during PHI elimination"))
VarInfo - This represents the regions where a virtual register is live in the program.
unsigned SplitAllCriticalEdges(Function &F, const CriticalEdgeSplittingOptions &Options=CriticalEdgeSplittingOptions())
Loop over all of the edges in the CFG, breaking critical edges as they are found. ...
VNInfo - Value Number Information.
static bool isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI)
isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
BlockT * getHeader() const
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
iterator_range< succ_iterator > successors()
#define INITIALIZE_PASS_DEPENDENCY(depName)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
std::vector< MachineBasicBlock * >::iterator succ_iterator
Reg
All possible values of the reg field in the ModR/M byte.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
static cl::opt< bool > NoPhiElimLiveOutEarlyExit("no-phi-elim-live-out-early-exit", cl::init(false), cl::Hidden, cl::desc("Do not use an early exit if isLiveOutPastPHIs returns true."))
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
TargetInstrInfo - Interface to description of machine instruction set.
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions...
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
iterator SkipPHIsAndLabels(iterator I)
Return the first instruction in MBB after I that is not a PHI or a label.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Represent the analysis usage information of a pass.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
succ_iterator succ_begin()
unsigned getSubReg() const
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
bool liveAt(SlotIndex index) const
void initializePHIEliminationPass(PassRegistry &)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
INITIALIZE_PASS_BEGIN(PHIElimination,"phi-node-elimination","Eliminate PHI nodes for register allocation", false, false) INITIALIZE_PASS_END(PHIElimination
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
phi node Eliminate PHI nodes for register allocation
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
createDeadDef - Make sure the range has a value defined at Def.
SlotIndex endIndex() const
endNumber - return the maximum point of the range of the whole, exclusive.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P)
Split the critical edge from this block to the given successor block, and return the newly created bl...
static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, const MachineRegisterInfo *MRI)
isSourceDefinedByImplicitDef - Return true if all sources of the phi node are implicit_def's.
virtual const TargetInstrInfo * getInstrInfo() const
iterator_range< def_instr_iterator > def_instructions(unsigned Reg) const
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
SlotIndex - An opaque wrapper around machine indexes.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...