34 Reserved.
set(AMDGPU::ZERO);
35 Reserved.
set(AMDGPU::HALF);
36 Reserved.
set(AMDGPU::ONE);
37 Reserved.
set(AMDGPU::ONE_INT);
38 Reserved.
set(AMDGPU::NEG_HALF);
39 Reserved.
set(AMDGPU::NEG_ONE);
40 Reserved.
set(AMDGPU::PV_X);
41 Reserved.
set(AMDGPU::ALU_LITERAL_X);
42 Reserved.
set(AMDGPU::ALU_CONST);
43 Reserved.
set(AMDGPU::PREDICATE_BIT);
44 Reserved.
set(AMDGPU::PRED_SEL_OFF);
45 Reserved.
set(AMDGPU::PRED_SEL_ZERO);
46 Reserved.
set(AMDGPU::PRED_SEL_ONE);
47 Reserved.
set(AMDGPU::INDIRECT_BASE_ADDR);
50 E = AMDGPU::R600_AddrRegClass.
end();
I !=
E; ++
I) {
54 TII->reserveIndirectRegisters(Reserved, MF);
71 case MVT::i32:
return &AMDGPU::R600_TReg32RegClass;
95 unsigned FIOperandNum,
const_iterator end(StringRef path)
Get end iterator over path.
Interface definition for R600InstrInfo.
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const_iterator begin(StringRef path)
Get begin iterator over path.
Interface definition for R600RegisterInfo.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * iterator
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MVT - Machine Value Type.
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
const R600InstrInfo * getInstrInfo() const override
The AMDGPU TargetMachine interface definition for hw codgen targets.
unsigned getHWRegIndex(unsigned Reg) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define GET_REG_INDEX(reg)