21 #define DEBUG_TYPE "regalloc"
24 const InterferenceCache::BlockInterference
25 InterferenceCache::Cursor::NoInterference;
36 if (PhysRegEntriesCount == TRI->
getNumRegs())
return;
39 PhysRegEntries = (
unsigned char*)
40 calloc(PhysRegEntriesCount,
sizeof(
unsigned char));
52 for (
unsigned i = 0;
i != CacheEntries; ++
i)
53 Entries[
i].
clear(mf, indexes, lis);
56 InterferenceCache::Entry *InterferenceCache::get(
unsigned PhysReg) {
57 unsigned E = PhysRegEntries[PhysReg];
58 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
59 if (!Entries[E].valid(LIUArray, TRI))
60 Entries[
E].revalidate(LIUArray, TRI);
65 if (++RoundRobin == CacheEntries)
67 for (
unsigned i = 0;
i != CacheEntries; ++
i) {
69 if (Entries[E].hasRefs()) {
70 if (++E == CacheEntries)
74 Entries[
E].reset(PhysReg, LIUArray, TRI, MF);
75 PhysRegEntries[PhysReg] =
E;
90 RegUnits[i].VirtTag = LIUArray[*Units].
getTag();
93 void InterferenceCache::Entry::reset(
unsigned physReg,
97 assert(!hasRefs() &&
"Cannot reset cache entry with references");
107 RegUnits.push_back(LIUArray[*Units]);
108 RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
114 unsigned i = 0, e = RegUnits.size();
118 if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
124 void InterferenceCache::Entry::update(
unsigned MBBNum) {
126 std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
129 if (PrevPos != Start) {
130 if (!PrevPos.isValid() || Start < PrevPos) {
131 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++
i) {
132 RegUnitInfo &RUI = RegUnits[
i];
133 RUI.VirtI.find(Start);
134 RUI.FixedI = RUI.Fixed->find(Start);
137 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++
i) {
138 RegUnitInfo &RUI = RegUnits[
i];
139 RUI.VirtI.advanceTo(Start);
140 if (RUI.FixedI != RUI.Fixed->end())
141 RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
149 BlockInterference *BI = &Blocks[MBBNum];
157 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++
i) {
164 if (!BI->First.isValid() || StartI < BI->First)
169 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++
i) {
177 if (!BI->First.isValid() || StartI < BI->First)
182 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
183 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
185 for (
unsigned i = 0, e = RegMaskSlots.
size();
186 i != e && RegMaskSlots[
i] < Limit; ++
i)
189 BI->First = RegMaskSlots[
i];
194 if (BI->First.isValid())
198 if (++MFI == MF->
end())
200 MBBNum = MFI->getNumber();
201 BI = &Blocks[MBBNum];
204 std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
208 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++
i) {
210 if (!I.valid() || I.start() >= Stop)
213 bool Backup = !I.valid() || I.start() >= Stop;
217 if (!BI->Last.isValid() || StopI > BI->Last)
224 for (
unsigned i = 0, e = RegUnits.size(); i != e; ++
i) {
227 if (I == LR->
end() || I->start >= Stop)
230 bool Backup = I == LR->
end() || I->start >= Stop;
234 if (!BI->Last.isValid() || StopI > BI->Last)
242 for (
unsigned i = RegMaskSlots.
size();
243 i && RegMaskSlots[i-1].getDeadSlot() > Limit; --
i)
247 BI->Last = RegMaskSlots[i-1].getDeadSlot();
Segments::iterator iterator
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
iterator advanceTo(iterator I, SlotIndex Pos)
advanceTo - Advance the specified iterator to point to the Segment containing the specified position...
This class represents the liveness of a register, stack slot, etc.
unsigned getNumBlockIDs() const
getNumBlockIDs - Return the number of MBB ID's allocated.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
void init(MachineFunction *, LiveIntervalUnion *, SlotIndexes *, LiveIntervals *, const TargetRegisterInfo *)
init - Prepare cache for a new function.
bool isValid() const
Returns true if this is a valid index.
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
self_iterator getIterator()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getTag(StringRef TagString)
Iterator for intrusive lists based on ilist_node.
Segments::const_iterator const_iterator
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
LiveSegments::iterator SegmentIter
static void clear(coro::Shape &Shape)
void reinitPhysRegEntries()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SlotIndex - An opaque wrapper around machine indexes.