LLVM  4.0.0
HexagonISelLowering.h
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1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Hexagon uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
17 
18 #include "Hexagon.h"
19 #include "llvm/ADT/StringRef.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/IR/InlineAsm.h"
27 #include <cstdint>
28 #include <utility>
29 
30 namespace llvm {
31 
32 namespace HexagonISD {
33 
34  enum NodeType : unsigned {
36 
38  CONST32_GP, // For marking data present in GP.
40 
41  AT_GOT, // Index in GOT.
42  AT_PCREL, // Offset relative to PC.
43 
44  CALL, // Function call.
45  CALLnr, // Function call that does not return.
47 
48  RET_FLAG, // Return with a flag operand.
49  BARRIER, // Memory barrier.
50  JT, // Jump table.
51  CP, // Constant pool.
52 
79 
89 
91  };
92 
93 } // end namespace HexagonISD
94 
95  class HexagonSubtarget;
96 
98  int VarArgsFrameOffset; // Frame offset to start of varargs area.
99  const HexagonTargetMachine &HTM;
100  const HexagonSubtarget &Subtarget;
101 
102  bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
103  const;
104  void promoteLdStType(MVT VT, MVT PromotedLdStVT);
105 
106  public:
107  explicit HexagonTargetLowering(const TargetMachine &TM,
108  const HexagonSubtarget &ST);
109 
110  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
111  /// for tail call optimization. Targets which want to do tail call
112  /// optimization should implement this function.
114  CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
115  bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
116  const SmallVectorImpl<SDValue> &OutVals,
117  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
118 
119  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
120  bool isTruncateFree(EVT VT1, EVT VT2) const override;
121 
122  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
123 
124  /// Return true if an FMA operation is faster than a pair of mul and add
125  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
126  /// method returns true (and FMAs are legal), otherwise fmuladd is
127  /// expanded to mul + add.
128  bool isFMAFasterThanFMulAndFAdd(EVT) const override;
129 
130  // Should we expand the build vector with shuffles?
132  unsigned DefinedValues) const override;
133 
135  const override;
136 
137  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
138  const char *getTargetNodeName(unsigned Opcode) const override;
147  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
148  SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
149  SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
150  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
151  SDValue
152  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
154  const SDLoc &dl, SelectionDAG &DAG,
155  SmallVectorImpl<SDValue> &InVals) const override;
160  SelectionDAG &DAG) const;
162  SelectionDAG &DAG) const;
164  SelectionDAG &DAG) const;
166  GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT,
167  unsigned ReturnReg, unsigned char OperandFlags) const;
169 
171  SmallVectorImpl<SDValue> &InVals) const override;
172  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
173  CallingConv::ID CallConv, bool isVarArg,
175  const SDLoc &dl, SelectionDAG &DAG,
176  SmallVectorImpl<SDValue> &InVals,
177  const SmallVectorImpl<SDValue> &OutVals,
178  SDValue Callee) const;
179 
180  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
181  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
182  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
183  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
186  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
187 
188  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
190  const SmallVectorImpl<SDValue> &OutVals,
191  const SDLoc &dl, SelectionDAG &DAG) const override;
192 
193  bool mayBeEmittedAsTailCall(CallInst *CI) const override;
194 
195  /// If a physical register, this returns the register that receives the
196  /// exception address on entry to an EH pad.
197  unsigned
198  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
199  return Hexagon::R0;
200  }
201 
202  /// If a physical register, this returns the register that receives the
203  /// exception typeid on entry to a landing pad.
204  unsigned
205  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
206  return Hexagon::R1;
207  }
208 
209  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
211  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
212 
214  EVT VT) const override {
215  if (!VT.isVector())
216  return MVT::i1;
217  else
219  }
220 
222  SDValue &Base, SDValue &Offset,
224  SelectionDAG &DAG) const override;
225 
226  ConstraintType getConstraintType(StringRef Constraint) const override;
227 
228  std::pair<unsigned, const TargetRegisterClass *>
230  StringRef Constraint, MVT VT) const override;
231 
232  unsigned
233  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
234  if (ConstraintCode == "o")
236  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
237  }
238 
239  // Intrinsics
242  /// isLegalAddressingMode - Return true if the addressing mode represented
243  /// by AM is legal for this target, for a load/store of the specified type.
244  /// The type may be VoidTy, in which case only return true if the addressing
245  /// mode is legal for a load/store of any legal type.
246  /// TODO: Handle pre/postinc as well.
247  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
248  Type *Ty, unsigned AS) const override;
249  /// Return true if folding a constant offset with the given GlobalAddress
250  /// is legal. It is frequently not legal in PIC relocation models.
251  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
252 
253  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
254 
255  /// isLegalICmpImmediate - Return true if the specified immediate is legal
256  /// icmp immediate, that is the target has icmp instructions which can
257  /// compare a register against the immediate without having to materialize
258  /// the immediate into a register.
259  bool isLegalICmpImmediate(int64_t Imm) const override;
260 
261  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
262  unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
263  MachineFunction &MF) const override;
264 
265  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
266  unsigned Align, bool *Fast) const override;
267 
268  /// Returns relocation base for the given PIC jumptable.
270  const override;
271 
272  // Handling of atomic RMW instructions.
273  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
274  AtomicOrdering Ord) const override;
276  Value *Addr, AtomicOrdering Ord) const override;
278  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
279  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
280 
284  }
285 
286  protected:
287  std::pair<const TargetRegisterClass*, uint8_t>
289  const override;
290  };
291 
292 } // end namespace llvm
293 
294 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:504
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
bool isFMAFasterThanFMulAndFAdd(EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
This class represents a function call, abstracting a target machine's calling convention.
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:669
SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
SDValue LowerEXTRACT_SUBVECTOR_HVX(SDValue Op, SelectionDAG &DAG) const
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:133
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:588
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
AtomicOrdering
Atomic ordering for LLVM's memory model.
An instruction for storing to memory.
Definition: Instructions.h:300
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
This is an important base class in LLVM.
Definition: Constant.h:42
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:41
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool mayBeEmittedAsTailCall(CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
uint32_t Offset
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
This structure contains all information that is necessary for lowering calls.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
Definition: ValueTypes.h:70
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
bool isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
#define N
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
Determine if the target supports unaligned memory accesses.
SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
LLVM Value Representation.
Definition: Value.h:71
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame)...
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
This file describes how to lower LLVM code to machine code.
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:799
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:248