66 #define DEBUG_TYPE "nvptx-lower"
78 cl::desc(
"NVPTX Specific: FMA contraction (0: don't do it"
79 " 1: do it 2: do it aggressively"),
111 uint64_t StartingOffset = 0) {
116 for (
unsigned i = 0, e = TempVTs.
size();
i != e; ++
i) {
118 uint64_t Off = TempOffsets[
i];
340 return "NVPTXISD::CALL";
342 return "NVPTXISD::RET_FLAG";
344 return "NVPTXISD::LOAD_PARAM";
346 return "NVPTXISD::Wrapper";
348 return "NVPTXISD::DeclareParam";
350 return "NVPTXISD::DeclareScalarParam";
352 return "NVPTXISD::DeclareRet";
354 return "NVPTXISD::DeclareScalarRet";
356 return "NVPTXISD::DeclareRetParam";
358 return "NVPTXISD::PrintCall";
360 return "NVPTXISD::PrintConvergentCall";
362 return "NVPTXISD::PrintCallUni";
364 return "NVPTXISD::PrintConvergentCallUni";
366 return "NVPTXISD::LoadParam";
368 return "NVPTXISD::LoadParamV2";
370 return "NVPTXISD::LoadParamV4";
372 return "NVPTXISD::StoreParam";
374 return "NVPTXISD::StoreParamV2";
376 return "NVPTXISD::StoreParamV4";
378 return "NVPTXISD::StoreParamS32";
380 return "NVPTXISD::StoreParamU32";
382 return "NVPTXISD::CallArgBegin";
384 return "NVPTXISD::CallArg";
386 return "NVPTXISD::LastCallArg";
388 return "NVPTXISD::CallArgEnd";
390 return "NVPTXISD::CallVoid";
392 return "NVPTXISD::CallVal";
394 return "NVPTXISD::CallSymbol";
396 return "NVPTXISD::Prototype";
398 return "NVPTXISD::MoveParam";
400 return "NVPTXISD::StoreRetval";
402 return "NVPTXISD::StoreRetvalV2";
404 return "NVPTXISD::StoreRetvalV4";
406 return "NVPTXISD::PseudoUseParam";
408 return "NVPTXISD::RETURN";
410 return "NVPTXISD::CallSeqBegin";
412 return "NVPTXISD::CallSeqEnd";
414 return "NVPTXISD::CallPrototype";
416 return "NVPTXISD::LoadV2";
418 return "NVPTXISD::LoadV4";
420 return "NVPTXISD::LDGV2";
422 return "NVPTXISD::LDGV4";
424 return "NVPTXISD::LDUV2";
426 return "NVPTXISD::LDUV4";
428 return "NVPTXISD::StoreV2";
430 return "NVPTXISD::StoreV4";
432 return "NVPTXISD::FUN_SHFL_CLAMP";
434 return "NVPTXISD::FUN_SHFR_CLAMP";
436 return "NVPTXISD::IMAD";
438 return "NVPTXISD::Dummy";
440 return "NVPTXISD::MUL_WIDE_SIGNED";
442 return "NVPTXISD::MUL_WIDE_UNSIGNED";
446 return "NVPTXISD::Tex1DFloatFloatLevel";
448 return "NVPTXISD::Tex1DFloatFloatGrad";
452 return "NVPTXISD::Tex1DS32FloatLevel";
454 return "NVPTXISD::Tex1DS32FloatGrad";
458 return "NVPTXISD::Tex1DU32FloatLevel";
460 return "NVPTXISD::Tex1DU32FloatGrad";
464 return "NVPTXISD::Tex1DArrayFloatFloatLevel";
466 return "NVPTXISD::Tex1DArrayFloatFloatGrad";
470 return "NVPTXISD::Tex1DArrayS32FloatLevel";
472 return "NVPTXISD::Tex1DArrayS32FloatGrad";
476 return "NVPTXISD::Tex1DArrayU32FloatLevel";
478 return "NVPTXISD::Tex1DArrayU32FloatGrad";
482 return "NVPTXISD::Tex2DFloatFloatLevel";
484 return "NVPTXISD::Tex2DFloatFloatGrad";
488 return "NVPTXISD::Tex2DS32FloatLevel";
490 return "NVPTXISD::Tex2DS32FloatGrad";
494 return "NVPTXISD::Tex2DU32FloatLevel";
496 return "NVPTXISD::Tex2DU32FloatGrad";
500 return "NVPTXISD::Tex2DArrayFloatFloatLevel";
502 return "NVPTXISD::Tex2DArrayFloatFloatGrad";
506 return "NVPTXISD::Tex2DArrayS32FloatLevel";
508 return "NVPTXISD::Tex2DArrayS32FloatGrad";
512 return "NVPTXISD::Tex2DArrayU32FloatLevel";
514 return "NVPTXISD::Tex2DArrayU32FloatGrad";
518 return "NVPTXISD::Tex3DFloatFloatLevel";
520 return "NVPTXISD::Tex3DFloatFloatGrad";
524 return "NVPTXISD::Tex3DS32FloatLevel";
526 return "NVPTXISD::Tex3DS32FloatGrad";
530 return "NVPTXISD::Tex3DU32FloatLevel";
532 return "NVPTXISD::Tex3DU32FloatGrad";
535 return "NVPTXISD::TexCubeFloatFloatLevel";
538 return "NVPTXISD::TexCubeS32FloatLevel";
541 return "NVPTXISD::TexCubeU32FloatLevel";
543 return "NVPTXISD::TexCubeArrayFloatFloat";
545 return "NVPTXISD::TexCubeArrayFloatFloatLevel";
547 return "NVPTXISD::TexCubeArrayS32Float";
549 return "NVPTXISD::TexCubeArrayS32FloatLevel";
551 return "NVPTXISD::TexCubeArrayU32Float";
553 return "NVPTXISD::TexCubeArrayU32FloatLevel";
555 return "NVPTXISD::Tld4R2DFloatFloat";
557 return "NVPTXISD::Tld4G2DFloatFloat";
559 return "NVPTXISD::Tld4B2DFloatFloat";
561 return "NVPTXISD::Tld4A2DFloatFloat";
563 return "NVPTXISD::Tld4R2DS64Float";
565 return "NVPTXISD::Tld4G2DS64Float";
567 return "NVPTXISD::Tld4B2DS64Float";
569 return "NVPTXISD::Tld4A2DS64Float";
571 return "NVPTXISD::Tld4R2DU64Float";
573 return "NVPTXISD::Tld4G2DU64Float";
575 return "NVPTXISD::Tld4B2DU64Float";
577 return "NVPTXISD::Tld4A2DU64Float";
580 return "NVPTXISD::TexUnified1DFloatS32";
582 return "NVPTXISD::TexUnified1DFloatFloat";
584 return "NVPTXISD::TexUnified1DFloatFloatLevel";
586 return "NVPTXISD::TexUnified1DFloatFloatGrad";
588 return "NVPTXISD::TexUnified1DS32S32";
590 return "NVPTXISD::TexUnified1DS32Float";
592 return "NVPTXISD::TexUnified1DS32FloatLevel";
594 return "NVPTXISD::TexUnified1DS32FloatGrad";
596 return "NVPTXISD::TexUnified1DU32S32";
598 return "NVPTXISD::TexUnified1DU32Float";
600 return "NVPTXISD::TexUnified1DU32FloatLevel";
602 return "NVPTXISD::TexUnified1DU32FloatGrad";
604 return "NVPTXISD::TexUnified1DArrayFloatS32";
606 return "NVPTXISD::TexUnified1DArrayFloatFloat";
608 return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
610 return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
612 return "NVPTXISD::TexUnified1DArrayS32S32";
614 return "NVPTXISD::TexUnified1DArrayS32Float";
616 return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
618 return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
620 return "NVPTXISD::TexUnified1DArrayU32S32";
622 return "NVPTXISD::TexUnified1DArrayU32Float";
624 return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
626 return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
628 return "NVPTXISD::TexUnified2DFloatS32";
630 return "NVPTXISD::TexUnified2DFloatFloat";
632 return "NVPTXISD::TexUnified2DFloatFloatLevel";
634 return "NVPTXISD::TexUnified2DFloatFloatGrad";
636 return "NVPTXISD::TexUnified2DS32S32";
638 return "NVPTXISD::TexUnified2DS32Float";
640 return "NVPTXISD::TexUnified2DS32FloatLevel";
642 return "NVPTXISD::TexUnified2DS32FloatGrad";
644 return "NVPTXISD::TexUnified2DU32S32";
646 return "NVPTXISD::TexUnified2DU32Float";
648 return "NVPTXISD::TexUnified2DU32FloatLevel";
650 return "NVPTXISD::TexUnified2DU32FloatGrad";
652 return "NVPTXISD::TexUnified2DArrayFloatS32";
654 return "NVPTXISD::TexUnified2DArrayFloatFloat";
656 return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
658 return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
660 return "NVPTXISD::TexUnified2DArrayS32S32";
662 return "NVPTXISD::TexUnified2DArrayS32Float";
664 return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
666 return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
668 return "NVPTXISD::TexUnified2DArrayU32S32";
670 return "NVPTXISD::TexUnified2DArrayU32Float";
672 return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
674 return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
676 return "NVPTXISD::TexUnified3DFloatS32";
678 return "NVPTXISD::TexUnified3DFloatFloat";
680 return "NVPTXISD::TexUnified3DFloatFloatLevel";
682 return "NVPTXISD::TexUnified3DFloatFloatGrad";
684 return "NVPTXISD::TexUnified3DS32S32";
686 return "NVPTXISD::TexUnified3DS32Float";
688 return "NVPTXISD::TexUnified3DS32FloatLevel";
690 return "NVPTXISD::TexUnified3DS32FloatGrad";
692 return "NVPTXISD::TexUnified3DU32S32";
694 return "NVPTXISD::TexUnified3DU32Float";
696 return "NVPTXISD::TexUnified3DU32FloatLevel";
698 return "NVPTXISD::TexUnified3DU32FloatGrad";
700 return "NVPTXISD::TexUnifiedCubeFloatFloat";
702 return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
704 return "NVPTXISD::TexUnifiedCubeS32Float";
706 return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
708 return "NVPTXISD::TexUnifiedCubeU32Float";
710 return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
712 return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
714 return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
716 return "NVPTXISD::TexUnifiedCubeArrayS32Float";
718 return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
720 return "NVPTXISD::TexUnifiedCubeArrayU32Float";
722 return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
724 return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
726 return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
728 return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
730 return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
732 return "NVPTXISD::Tld4UnifiedR2DS64Float";
734 return "NVPTXISD::Tld4UnifiedG2DS64Float";
736 return "NVPTXISD::Tld4UnifiedB2DS64Float";
738 return "NVPTXISD::Tld4UnifiedA2DS64Float";
740 return "NVPTXISD::Tld4UnifiedR2DU64Float";
742 return "NVPTXISD::Tld4UnifiedG2DU64Float";
744 return "NVPTXISD::Tld4UnifiedB2DU64Float";
746 return "NVPTXISD::Tld4UnifiedA2DU64Float";
942 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
955 assert(isABI &&
"Non-ABI compilation is not supported");
968 if (
auto *ITy = dyn_cast<IntegerType>(retTy)) {
969 size = ITy->getBitWidth();
974 "Floating point type expected here");
978 O <<
".param .b" << size <<
" _";
979 }
else if (isa<PointerType>(retTy)) {
980 O <<
".param .b" << PtrVT.getSizeInBits() <<
" _";
982 isa<VectorType>(retTy)) {
984 O <<
".param .align " << retAlignment <<
" .b8 _["
996 for (
unsigned i = 0, e = Args.size();
i != e; ++
i, ++OIdx) {
997 Type *Ty = Args[
i].Ty;
1003 if (!Outs[OIdx].
Flags.isByVal()) {
1011 O <<
".param .align " << align <<
" .b8 ";
1013 O <<
"[" << sz <<
"]";
1017 if (
unsigned len = vtparts.
size())
1024 "type mismatch between callee prototype and arguments");
1027 if (isa<IntegerType>(Ty)) {
1031 }
else if (isa<PointerType>(Ty))
1032 sz = PtrVT.getSizeInBits();
1035 O <<
".param .b" << sz <<
" ";
1040 assert(PTy &&
"Param with byval attribute should be a pointer type");
1041 Type *ETy = PTy->getElementType();
1043 unsigned align = Outs[OIdx].Flags.getByValAlign();
1045 O <<
".param .align " << align <<
" .b8 ";
1047 O <<
"[" << sz <<
"]";
1053 unsigned NVPTXTargetLowering::getArgumentAlignment(
SDValue Callee,
1055 Type *Ty,
unsigned Idx,
1065 if (!DirectCallee) {
1069 assert(CalleeI &&
"Call target is not a function or derived value?");
1072 if (isa<CallInst>(CalleeI)) {
1074 if (
getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1077 const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1079 while (isa<ConstantExpr>(CalleeV)) {
1084 CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1089 if (isa<Function>(CalleeV))
1090 DirectCallee = CalleeV;
1097 if (
getAlign(*cast<Function>(DirectCallee), Idx, Align))
1120 assert(isABI &&
"Non-ABI compilation is not supported");
1133 unsigned paramCount = 0;
1146 for (
unsigned i = 0, e = Args.size();
i != e; ++
i, ++OIdx) {
1147 EVT VT = Outs[OIdx].VT;
1148 Type *Ty = Args[
i].Ty;
1150 if (!Outs[OIdx].
Flags.isByVal()) {
1159 getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1171 for (
unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1172 EVT elemtype = vtparts[j];
1176 SDValue StVal = OutVals[OIdx];
1181 SDValue CopyParamOps[] = { Chain,
1186 CopyParamVTs, CopyParamOps,
1192 if (vtparts.size() > 0)
1200 getArgumentAlignment(Callee, CS, Ty, paramCount + 1, DL);
1204 SDValue DeclareParamOps[] = { Chain,
1215 bool NeedExtend =
false;
1223 SDValue Elt = OutVals[OIdx++];
1228 SDValue CopyParamOps[] = { Chain,
1233 CopyParamVTs, CopyParamOps,
1236 }
else if (NumElts == 2) {
1237 SDValue Elt0 = OutVals[OIdx++];
1238 SDValue Elt1 = OutVals[OIdx++];
1245 SDValue CopyParamOps[] = { Chain,
1250 CopyParamVTs, CopyParamOps,
1254 unsigned curOffset = 0;
1265 unsigned VecSize = 4;
1273 for (
unsigned i = 0;
i < NumElts;
i += VecSize) {
1283 StoreVal = OutVals[OIdx++];
1288 if (
i + 1 < NumElts) {
1289 StoreVal = OutVals[OIdx++];
1300 if (
i + 2 < NumElts) {
1301 StoreVal = OutVals[OIdx++];
1310 if (
i + 3 < NumElts) {
1311 StoreVal = OutVals[OIdx++];
1327 curOffset += PerStoreOffset;
1337 bool needExtend =
false;
1345 SDValue DeclareParamOps[] = { Chain,
1356 if (Outs[OIdx].
Flags.isSExt())
1361 SDValue CopyParamOps[] = { Chain,
1382 assert(PTy &&
"Type of a byval parameter should be pointer");
1387 unsigned sz = Outs[OIdx].Flags.getByValSize();
1389 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1405 for (
unsigned j = 0, je = vtparts.
size(); j != je; ++j) {
1406 EVT elemtype = vtparts[j];
1407 int curOffset = Offsets[j];
1418 SDValue CopyParamOps[] = { Chain,
1423 CopyParamOps, elemtype,
1432 unsigned retAlignment = 0;
1435 if (Ins.
size() > 0) {
1460 retAlignment = getArgumentAlignment(Callee, CS, retTy, 0, DL);
1462 SDValue DeclareRetOps[] = { Chain,
1483 const char *ProtoStr =
1501 Chain = DAG.
getNode(Opcode, dl, PrintCallVTs, PrintCallOps);
1506 SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1512 SDValue CallArgBeginOps[] = { Chain, InFlag };
1517 for (
unsigned i = 0, e = paramCount;
i != e; ++
i) {
1526 Chain = DAG.
getNode(opcode, dl, CallArgVTs, CallArgOps);
1530 SDValue CallArgEndOps[] = { Chain,
1538 SDValue PrototypeOps[] = { Chain,
1546 if (Ins.
size() > 0) {
1552 ObjectVT) == NumElts &&
1553 "Vector was not scalarized");
1555 bool needTruncate = sz < 8;
1581 }
else if (NumElts == 2) {
1618 unsigned VecSize = 4;
1625 for (
unsigned i = 0;
i < NumElts;
i += VecSize) {
1632 for (
unsigned j = 0; j < VecSize; ++j)
1635 for (
unsigned j = 0; j < VecSize; ++j)
1653 for (
unsigned j = 0; j < VecSize; ++j) {
1654 if (
i + j >= NumElts)
1670 unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0, DL);
1671 for (
unsigned i = 0, e = Ins.
size();
i != e; ++
i) {
1672 unsigned sz = VTs[
i].getSizeInBits();
1674 bool needTruncate =
false;
1675 if (VTs[i].isInteger() && sz < 8) {
1677 needTruncate =
true;
1681 EVT TheLoadType = VTs[
i];
1687 needTruncate =
true;
1688 }
else if (sz < 16) {
1742 for (
unsigned i = 0;
i < NumOperands; ++
i) {
1747 for (
unsigned j = 0; j < NumSubElem; ++j) {
1827 unsigned VTBits = VT.getSizeInBits();
1891 return LowerCONCAT_VECTORS(Op, DAG);
1893 return LowerSTORE(Op, DAG);
1895 return LowerLOAD(Op, DAG);
1897 return LowerShiftLeftParts(Op, DAG);
1900 return LowerShiftRightParts(Op, DAG);
1902 return LowerSelect(Op, DAG);
1926 return LowerLOADi1(Op, DAG);
1941 "Custom lowering for i1 load only");
1956 return LowerSTOREi1(Op, DAG);
1958 return LowerSTOREVector(Op, DAG);
1997 unsigned PrefAlign =
1999 if (Align < PrefAlign) {
2008 unsigned Opcode = 0;
2015 bool NeedExt =
false;
2036 for (
unsigned i = 0;
i < NumElts; ++
i) {
2078 NVPTXTargetLowering::getParamSymbol(
SelectionDAG &DAG,
int idx,
EVT v)
const {
2079 std::string ParamSym;
2085 std::string *SavedStr =
2093 static const char *
const specialTypes[] = {
"struct._image2d_t",
2094 "struct._image3d_t",
2095 "struct._sampler_t" };
2107 if (!STy || STy->isLiteral())
2111 STy->getName()) !=
std::end(specialTypes);
2127 std::vector<SDValue> OutChains;
2130 assert(isABI &&
"Non-ABI compilation is not supported");
2134 std::vector<Type *> argTypes;
2135 std::vector<const Argument *> theArgs;
2137 theArgs.push_back(&
I);
2138 argTypes.push_back(
I.getType());
2149 unsigned InsIdx = 0;
2152 for (
unsigned i = 0, e = theArgs.size();
i != e; ++
i, ++idx, ++InsIdx) {
2153 Type *Ty = argTypes[
i];
2163 "Only kernels can have image/sampler params");
2168 if (theArgs[i]->use_empty()) {
2174 assert(vtparts.
size() > 0 &&
"empty aggregate type not expected");
2175 for (
unsigned parti = 0, parte = vtparts.
size(); parti != parte;
2180 if (vtparts.
size() > 0)
2187 for (
unsigned parti = 0; parti < NumRegs; ++parti) {
2213 assert(vtparts.size() > 0 &&
"empty aggregate type not expected");
2214 bool aggregateIsPacked =
false;
2215 if (
StructType *STy = dyn_cast<StructType>(Ty))
2216 aggregateIsPacked = STy->isPacked();
2218 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2219 for (
unsigned parti = 0, parte = vtparts.size(); parti != parte;
2221 EVT partVT = vtparts[parti];
2228 unsigned partAlign = aggregateIsPacked
2233 if (Ins[InsIdx].VT.getSizeInBits() > partVT.
getSizeInBits()) {
2236 p = DAG.
getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2239 p = DAG.
getLoad(partVT, dl, Root, srcAddr,
2247 if (vtparts.size() > 0)
2253 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2256 "Vector was not scalarized");
2277 }
else if (NumElts == 2) {
2296 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.
getSizeInBits()) {
2314 unsigned VecSize = 4;
2320 for (
unsigned i = 0; i < NumElts; i += VecSize) {
2334 for (
unsigned j = 0; j < VecSize; ++j) {
2335 if (i + j >= NumElts)
2355 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2359 if (ObjectVT.
getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2385 assert(ObjectVT == Ins[InsIdx].VT &&
2386 "Ins type did not match function type");
2387 SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2402 if (!OutChains.empty())
2420 assert(isABI &&
"Non-ABI compilation is not supported");
2424 if (
VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2427 unsigned NumElts = VTy->getNumElements();
2428 assert(NumElts == Outs.
size() &&
"Bad scalarization of return value");
2432 bool NeedExtend =
false;
2433 if (EltVT.getSizeInBits() < 16)
2438 SDValue StoreVal = OutVals[0];
2446 }
else if (NumElts == 2) {
2448 SDValue StoreVal0 = OutVals[0];
2449 SDValue StoreVal1 = OutVals[1];
2472 unsigned VecSize = 4;
2473 if (OutVals[0].getValueSizeInBits() == 64)
2480 unsigned PerStoreOffset =
2483 for (
unsigned i = 0;
i < NumElts;
i += VecSize) {
2492 StoreVal = OutVals[
i];
2497 if (
i + 1 < NumElts) {
2498 StoreVal = OutVals[
i + 1];
2502 StoreVal = DAG.
getUNDEF(ExtendedVT);
2508 if (
i + 2 < NumElts) {
2509 StoreVal = OutVals[
i + 2];
2514 StoreVal = DAG.
getUNDEF(ExtendedVT);
2518 if (
i + 3 < NumElts) {
2519 StoreVal = OutVals[
i + 3];
2524 StoreVal = DAG.
getUNDEF(ExtendedVT);
2533 Offset += PerStoreOffset;
2540 assert(ValVTs.size() == OutVals.
size() &&
"Bad return value decomposition");
2542 for (
unsigned i = 0, e = Outs.
size();
i != e; ++
i) {
2545 unsigned numElems = 1;
2548 for (
unsigned j = 0, je = numElems; j != je; ++j) {
2554 EVT TheStoreType = ValVTs[
i];
2580 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2582 if (Constraint.length() > 1)
2589 switch (Intrinsic) {
2593 case Intrinsic::nvvm_tex_1d_v4f32_s32:
2595 case Intrinsic::nvvm_tex_1d_v4f32_f32:
2597 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2599 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2601 case Intrinsic::nvvm_tex_1d_v4s32_s32:
2603 case Intrinsic::nvvm_tex_1d_v4s32_f32:
2605 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2607 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2609 case Intrinsic::nvvm_tex_1d_v4u32_s32:
2611 case Intrinsic::nvvm_tex_1d_v4u32_f32:
2613 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2615 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2618 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2620 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2622 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2624 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2626 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2628 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2630 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2632 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2634 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2636 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2638 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2640 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2643 case Intrinsic::nvvm_tex_2d_v4f32_s32:
2645 case Intrinsic::nvvm_tex_2d_v4f32_f32:
2647 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2649 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2651 case Intrinsic::nvvm_tex_2d_v4s32_s32:
2653 case Intrinsic::nvvm_tex_2d_v4s32_f32:
2655 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2657 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2659 case Intrinsic::nvvm_tex_2d_v4u32_s32:
2661 case Intrinsic::nvvm_tex_2d_v4u32_f32:
2663 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2665 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2668 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2670 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2672 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2674 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2676 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2678 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2680 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2682 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2684 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2686 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2688 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2690 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2693 case Intrinsic::nvvm_tex_3d_v4f32_s32:
2695 case Intrinsic::nvvm_tex_3d_v4f32_f32:
2697 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2699 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2701 case Intrinsic::nvvm_tex_3d_v4s32_s32:
2703 case Intrinsic::nvvm_tex_3d_v4s32_f32:
2705 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2707 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2709 case Intrinsic::nvvm_tex_3d_v4u32_s32:
2711 case Intrinsic::nvvm_tex_3d_v4u32_f32:
2713 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2715 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2718 case Intrinsic::nvvm_tex_cube_v4f32_f32:
2720 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2722 case Intrinsic::nvvm_tex_cube_v4s32_f32:
2724 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2726 case Intrinsic::nvvm_tex_cube_v4u32_f32:
2728 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2731 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2733 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2735 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2737 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2739 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2741 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2744 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2746 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2748 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2750 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2752 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2754 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2756 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2758 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2760 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2762 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2764 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2766 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2769 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2771 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2773 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2775 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2777 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2779 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2781 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2783 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2785 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2787 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2789 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2791 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2794 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2796 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2798 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2800 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2802 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2804 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2806 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2808 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2810 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2812 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2814 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2816 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2819 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2821 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2823 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2825 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2827 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2829 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2831 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2833 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2835 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2837 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2839 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2841 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2844 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2846 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2848 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2850 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2852 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2854 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2856 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2858 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2860 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2862 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2864 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2866 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2869 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2871 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2873 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2875 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2877 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2879 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2881 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2883 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2885 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2887 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2889 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2891 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2894 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2896 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2898 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2900 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2902 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2904 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2907 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2909 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2911 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2913 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2915 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2917 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2920 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2922 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2924 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2926 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2928 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2930 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2932 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2934 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2936 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2938 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2940 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2942 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2948 switch (Intrinsic) {
2951 case Intrinsic::nvvm_suld_1d_i8_clamp:
2953 case Intrinsic::nvvm_suld_1d_i16_clamp:
2955 case Intrinsic::nvvm_suld_1d_i32_clamp:
2957 case Intrinsic::nvvm_suld_1d_i64_clamp:
2959 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2961 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2963 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2965 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2967 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2969 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2971 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2973 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2975 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2977 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2979 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2981 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2983 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2985 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2987 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2989 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2991 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2993 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2995 case Intrinsic::nvvm_suld_2d_i8_clamp:
2997 case Intrinsic::nvvm_suld_2d_i16_clamp:
2999 case Intrinsic::nvvm_suld_2d_i32_clamp:
3001 case Intrinsic::nvvm_suld_2d_i64_clamp:
3003 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3005 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3007 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3009 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3011 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3013 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3015 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3017 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3019 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3021 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3023 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3025 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3027 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3029 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3031 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3033 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3035 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3037 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3039 case Intrinsic::nvvm_suld_3d_i8_clamp:
3041 case Intrinsic::nvvm_suld_3d_i16_clamp:
3043 case Intrinsic::nvvm_suld_3d_i32_clamp:
3045 case Intrinsic::nvvm_suld_3d_i64_clamp:
3047 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3049 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3051 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3053 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3055 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3057 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3059 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3061 case Intrinsic::nvvm_suld_1d_i8_trap:
3063 case Intrinsic::nvvm_suld_1d_i16_trap:
3065 case Intrinsic::nvvm_suld_1d_i32_trap:
3067 case Intrinsic::nvvm_suld_1d_i64_trap:
3069 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3071 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3073 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3075 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3077 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3079 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3081 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3083 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3085 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3087 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3089 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3091 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3093 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3095 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3097 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3099 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3101 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3103 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3105 case Intrinsic::nvvm_suld_2d_i8_trap:
3107 case Intrinsic::nvvm_suld_2d_i16_trap:
3109 case Intrinsic::nvvm_suld_2d_i32_trap:
3111 case Intrinsic::nvvm_suld_2d_i64_trap:
3113 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3115 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3117 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3119 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3121 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3123 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3125 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3127 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3129 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3131 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3133 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3135 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3137 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3139 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3141 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3143 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3145 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3147 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3149 case Intrinsic::nvvm_suld_3d_i8_trap:
3151 case Intrinsic::nvvm_suld_3d_i16_trap:
3153 case Intrinsic::nvvm_suld_3d_i32_trap:
3155 case Intrinsic::nvvm_suld_3d_i64_trap:
3157 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3159 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3161 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3163 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3165 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3167 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3169 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3171 case Intrinsic::nvvm_suld_1d_i8_zero:
3173 case Intrinsic::nvvm_suld_1d_i16_zero:
3175 case Intrinsic::nvvm_suld_1d_i32_zero:
3177 case Intrinsic::nvvm_suld_1d_i64_zero:
3179 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3181 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3183 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3185 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3187 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3189 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3191 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3193 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3195 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3197 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3199 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3201 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3203 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3205 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3207 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3209 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3211 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3213 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3215 case Intrinsic::nvvm_suld_2d_i8_zero:
3217 case Intrinsic::nvvm_suld_2d_i16_zero:
3219 case Intrinsic::nvvm_suld_2d_i32_zero:
3221 case Intrinsic::nvvm_suld_2d_i64_zero:
3223 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3225 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3227 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3229 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3231 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3233 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3235 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3237 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3239 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3241 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3243 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3245 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3247 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3249 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3251 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3253 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3255 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3257 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3259 case Intrinsic::nvvm_suld_3d_i8_zero:
3261 case Intrinsic::nvvm_suld_3d_i16_zero:
3263 case Intrinsic::nvvm_suld_3d_i32_zero:
3265 case Intrinsic::nvvm_suld_3d_i64_zero:
3267 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3269 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3271 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3273 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3275 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3277 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3279 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3291 switch (Intrinsic) {
3295 case Intrinsic::nvvm_atomic_load_add_f32:
3296 case Intrinsic::nvvm_atomic_load_inc_32:
3297 case Intrinsic::nvvm_atomic_load_dec_32:
3299 case Intrinsic::nvvm_atomic_add_gen_f_cta:
3300 case Intrinsic::nvvm_atomic_add_gen_f_sys:
3301 case Intrinsic::nvvm_atomic_add_gen_i_cta:
3302 case Intrinsic::nvvm_atomic_add_gen_i_sys:
3303 case Intrinsic::nvvm_atomic_and_gen_i_cta:
3304 case Intrinsic::nvvm_atomic_and_gen_i_sys:
3305 case Intrinsic::nvvm_atomic_cas_gen_i_cta:
3306 case Intrinsic::nvvm_atomic_cas_gen_i_sys:
3307 case Intrinsic::nvvm_atomic_dec_gen_i_cta:
3308 case Intrinsic::nvvm_atomic_dec_gen_i_sys:
3309 case Intrinsic::nvvm_atomic_inc_gen_i_cta:
3310 case Intrinsic::nvvm_atomic_inc_gen_i_sys:
3311 case Intrinsic::nvvm_atomic_max_gen_i_cta:
3312 case Intrinsic::nvvm_atomic_max_gen_i_sys:
3313 case Intrinsic::nvvm_atomic_min_gen_i_cta:
3314 case Intrinsic::nvvm_atomic_min_gen_i_sys:
3315 case Intrinsic::nvvm_atomic_or_gen_i_cta:
3316 case Intrinsic::nvvm_atomic_or_gen_i_sys:
3317 case Intrinsic::nvvm_atomic_exch_gen_i_cta:
3318 case Intrinsic::nvvm_atomic_exch_gen_i_sys:
3319 case Intrinsic::nvvm_atomic_xor_gen_i_cta:
3320 case Intrinsic::nvvm_atomic_xor_gen_i_sys: {
3333 case Intrinsic::nvvm_ldu_global_i:
3334 case Intrinsic::nvvm_ldu_global_f:
3335 case Intrinsic::nvvm_ldu_global_p: {
3338 if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3340 else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3353 case Intrinsic::nvvm_ldg_global_i:
3354 case Intrinsic::nvvm_ldg_global_f:
3355 case Intrinsic::nvvm_ldg_global_p: {
3359 if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3361 else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3375 case Intrinsic::nvvm_tex_1d_v4f32_s32:
3376 case Intrinsic::nvvm_tex_1d_v4f32_f32:
3377 case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3378 case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3379 case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3380 case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3381 case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3382 case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3383 case Intrinsic::nvvm_tex_2d_v4f32_s32:
3384 case Intrinsic::nvvm_tex_2d_v4f32_f32:
3385 case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3386 case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3387 case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3388 case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3389 case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3390 case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3391 case Intrinsic::nvvm_tex_3d_v4f32_s32:
3392 case Intrinsic::nvvm_tex_3d_v4f32_f32:
3393 case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3394 case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3395 case Intrinsic::nvvm_tex_cube_v4f32_f32:
3396 case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3397 case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3398 case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3399 case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3400 case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3401 case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3402 case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3403 case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3404 case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3405 case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3406 case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3407 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3408 case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3409 case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3410 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3411 case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3412 case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3413 case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3414 case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3415 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3416 case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3417 case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3418 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3419 case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3420 case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3421 case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3422 case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3423 case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3424 case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3425 case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3426 case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3427 case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3428 case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3429 case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3430 case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
3441 case Intrinsic::nvvm_tex_1d_v4s32_s32:
3442 case Intrinsic::nvvm_tex_1d_v4s32_f32:
3443 case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3444 case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3445 case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3446 case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3447 case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3448 case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3449 case Intrinsic::nvvm_tex_2d_v4s32_s32:
3450 case Intrinsic::nvvm_tex_2d_v4s32_f32:
3451 case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3452 case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3453 case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3454 case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3455 case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3456 case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3457 case Intrinsic::nvvm_tex_3d_v4s32_s32:
3458 case Intrinsic::nvvm_tex_3d_v4s32_f32:
3459 case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3460 case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3461 case Intrinsic::nvvm_tex_cube_v4s32_f32:
3462 case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3463 case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3464 case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3465 case Intrinsic::nvvm_tex_cube_v4u32_f32:
3466 case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3467 case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3468 case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3469 case Intrinsic::nvvm_tex_1d_v4u32_s32:
3470 case Intrinsic::nvvm_tex_1d_v4u32_f32:
3471 case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3472 case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3473 case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3474 case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3475 case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3476 case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3477 case Intrinsic::nvvm_tex_2d_v4u32_s32:
3478 case Intrinsic::nvvm_tex_2d_v4u32_f32:
3479 case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3480 case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3481 case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3482 case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3483 case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3484 case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3485 case Intrinsic::nvvm_tex_3d_v4u32_s32:
3486 case Intrinsic::nvvm_tex_3d_v4u32_f32:
3487 case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3488 case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3489 case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3490 case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3491 case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3492 case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3493 case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3494 case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3495 case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3496 case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3497 case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3498 case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3499 case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3500 case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3501 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3502 case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3503 case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3504 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3505 case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3506 case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3507 case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3508 case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3509 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3510 case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3511 case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3512 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3513 case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3514 case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3515 case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3516 case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3517 case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3518 case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3519 case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3520 case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3521 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3522 case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3523 case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3524 case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3525 case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3526 case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3527 case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3528 case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3529 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3530 case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3531 case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3532 case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3533 case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3534 case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3535 case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3536 case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3537 case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3538 case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3539 case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3540 case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3541 case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3542 case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3543 case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3544 case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3545 case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3546 case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3547 case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3548 case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3549 case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3550 case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3551 case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3552 case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
3563 case Intrinsic::nvvm_suld_1d_i8_clamp:
3564 case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3565 case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3566 case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3567 case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3568 case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3569 case Intrinsic::nvvm_suld_2d_i8_clamp:
3570 case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3571 case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3572 case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3573 case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3574 case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3575 case Intrinsic::nvvm_suld_3d_i8_clamp:
3576 case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3577 case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3578 case Intrinsic::nvvm_suld_1d_i8_trap:
3579 case Intrinsic::nvvm_suld_1d_v2i8_trap:
3580 case Intrinsic::nvvm_suld_1d_v4i8_trap:
3581 case Intrinsic::nvvm_suld_1d_array_i8_trap:
3582 case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3583 case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3584 case Intrinsic::nvvm_suld_2d_i8_trap:
3585 case Intrinsic::nvvm_suld_2d_v2i8_trap:
3586 case Intrinsic::nvvm_suld_2d_v4i8_trap:
3587 case Intrinsic::nvvm_suld_2d_array_i8_trap:
3588 case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3589 case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3590 case Intrinsic::nvvm_suld_3d_i8_trap:
3591 case Intrinsic::nvvm_suld_3d_v2i8_trap:
3592 case Intrinsic::nvvm_suld_3d_v4i8_trap:
3593 case Intrinsic::nvvm_suld_1d_i8_zero:
3594 case Intrinsic::nvvm_suld_1d_v2i8_zero:
3595 case Intrinsic::nvvm_suld_1d_v4i8_zero:
3596 case Intrinsic::nvvm_suld_1d_array_i8_zero:
3597 case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3598 case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3599 case Intrinsic::nvvm_suld_2d_i8_zero:
3600 case Intrinsic::nvvm_suld_2d_v2i8_zero:
3601 case Intrinsic::nvvm_suld_2d_v4i8_zero:
3602 case Intrinsic::nvvm_suld_2d_array_i8_zero:
3603 case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3604 case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3605 case Intrinsic::nvvm_suld_3d_i8_zero:
3606 case Intrinsic::nvvm_suld_3d_v2i8_zero:
3607 case Intrinsic::nvvm_suld_3d_v4i8_zero:
3618 case Intrinsic::nvvm_suld_1d_i16_clamp:
3619 case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3620 case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3621 case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3622 case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3623 case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3624 case Intrinsic::nvvm_suld_2d_i16_clamp:
3625 case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3626 case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3627 case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3628 case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3629 case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3630 case Intrinsic::nvvm_suld_3d_i16_clamp:
3631 case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3632 case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3633 case Intrinsic::nvvm_suld_1d_i16_trap:
3634 case Intrinsic::nvvm_suld_1d_v2i16_trap:
3635 case Intrinsic::nvvm_suld_1d_v4i16_trap:
3636 case Intrinsic::nvvm_suld_1d_array_i16_trap:
3637 case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3638 case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3639 case Intrinsic::nvvm_suld_2d_i16_trap:
3640 case Intrinsic::nvvm_suld_2d_v2i16_trap:
3641 case Intrinsic::nvvm_suld_2d_v4i16_trap:
3642 case Intrinsic::nvvm_suld_2d_array_i16_trap:
3643 case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3644 case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3645 case Intrinsic::nvvm_suld_3d_i16_trap:
3646 case Intrinsic::nvvm_suld_3d_v2i16_trap:
3647 case Intrinsic::nvvm_suld_3d_v4i16_trap:
3648 case Intrinsic::nvvm_suld_1d_i16_zero:
3649 case Intrinsic::nvvm_suld_1d_v2i16_zero:
3650 case Intrinsic::nvvm_suld_1d_v4i16_zero:
3651 case Intrinsic::nvvm_suld_1d_array_i16_zero:
3652 case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3653 case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3654 case Intrinsic::nvvm_suld_2d_i16_zero:
3655 case Intrinsic::nvvm_suld_2d_v2i16_zero:
3656 case Intrinsic::nvvm_suld_2d_v4i16_zero:
3657 case Intrinsic::nvvm_suld_2d_array_i16_zero:
3658 case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3659 case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3660 case Intrinsic::nvvm_suld_3d_i16_zero:
3661 case Intrinsic::nvvm_suld_3d_v2i16_zero:
3662 case Intrinsic::nvvm_suld_3d_v4i16_zero:
3673 case Intrinsic::nvvm_suld_1d_i32_clamp:
3674 case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3675 case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3676 case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3677 case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3678 case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3679 case Intrinsic::nvvm_suld_2d_i32_clamp:
3680 case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3681 case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3682 case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3683 case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3684 case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3685 case Intrinsic::nvvm_suld_3d_i32_clamp:
3686 case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3687 case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3688 case Intrinsic::nvvm_suld_1d_i32_trap:
3689 case Intrinsic::nvvm_suld_1d_v2i32_trap:
3690 case Intrinsic::nvvm_suld_1d_v4i32_trap:
3691 case Intrinsic::nvvm_suld_1d_array_i32_trap:
3692 case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3693 case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3694 case Intrinsic::nvvm_suld_2d_i32_trap:
3695 case Intrinsic::nvvm_suld_2d_v2i32_trap:
3696 case Intrinsic::nvvm_suld_2d_v4i32_trap:
3697 case Intrinsic::nvvm_suld_2d_array_i32_trap:
3698 case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3699 case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3700 case Intrinsic::nvvm_suld_3d_i32_trap:
3701 case Intrinsic::nvvm_suld_3d_v2i32_trap:
3702 case Intrinsic::nvvm_suld_3d_v4i32_trap:
3703 case Intrinsic::nvvm_suld_1d_i32_zero:
3704 case Intrinsic::nvvm_suld_1d_v2i32_zero:
3705 case Intrinsic::nvvm_suld_1d_v4i32_zero:
3706 case Intrinsic::nvvm_suld_1d_array_i32_zero:
3707 case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3708 case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3709 case Intrinsic::nvvm_suld_2d_i32_zero:
3710 case Intrinsic::nvvm_suld_2d_v2i32_zero:
3711 case Intrinsic::nvvm_suld_2d_v4i32_zero:
3712 case Intrinsic::nvvm_suld_2d_array_i32_zero:
3713 case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3714 case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3715 case Intrinsic::nvvm_suld_3d_i32_zero:
3716 case Intrinsic::nvvm_suld_3d_v2i32_zero:
3717 case Intrinsic::nvvm_suld_3d_v4i32_zero:
3728 case Intrinsic::nvvm_suld_1d_i64_clamp:
3729 case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3730 case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3731 case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3732 case Intrinsic::nvvm_suld_2d_i64_clamp:
3733 case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3734 case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3735 case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3736 case Intrinsic::nvvm_suld_3d_i64_clamp:
3737 case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3738 case Intrinsic::nvvm_suld_1d_i64_trap:
3739 case Intrinsic::nvvm_suld_1d_v2i64_trap:
3740 case Intrinsic::nvvm_suld_1d_array_i64_trap:
3741 case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3742 case Intrinsic::nvvm_suld_2d_i64_trap:
3743 case Intrinsic::nvvm_suld_2d_v2i64_trap:
3744 case Intrinsic::nvvm_suld_2d_array_i64_trap:
3745 case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3746 case Intrinsic::nvvm_suld_3d_i64_trap:
3747 case Intrinsic::nvvm_suld_3d_v2i64_trap:
3748 case Intrinsic::nvvm_suld_1d_i64_zero:
3749 case Intrinsic::nvvm_suld_1d_v2i64_zero:
3750 case Intrinsic::nvvm_suld_1d_array_i64_zero:
3751 case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3752 case Intrinsic::nvvm_suld_2d_i64_zero:
3753 case Intrinsic::nvvm_suld_2d_v2i64_zero:
3754 case Intrinsic::nvvm_suld_2d_array_i64_zero:
3755 case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3756 case Intrinsic::nvvm_suld_3d_i64_zero:
3757 case Intrinsic::nvvm_suld_3d_v2i64_zero:
3778 unsigned AS)
const {
3815 if (Constraint.
size() == 1) {
3816 switch (Constraint[0]) {
3834 std::pair<unsigned, const TargetRegisterClass *>
3838 if (Constraint.
size() == 1) {
3839 switch (Constraint[0]) {
3841 return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3843 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3845 return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3847 return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3850 return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3852 return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3854 return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3872 }
else if (OptLevel == 0) {
3936 int nonAddCount = 0;
3954 if (orderNo - orderNo2 < 500)
3959 bool opIsLive =
false;
3963 if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3970 if (orderNo3 > orderNo) {
3980 if (orderNo3 > orderNo) {
4026 if (isa<ConstantSDNode>(Val)) {
4050 if (MaskVal != 0xff) {
4077 if (AExt.
getNode() !=
nullptr) {
4104 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4130 const bool IsMax = (Larger == True);
4133 unsigned IntrinsicId;
4136 IntrinsicId = IsMax ? Intrinsic::nvvm_max_i : Intrinsic::nvvm_min_i;
4138 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ui : Intrinsic::nvvm_min_ui;
4142 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ll : Intrinsic::nvvm_min_ll;
4144 IntrinsicId = IsMax ? Intrinsic::nvvm_max_ull : Intrinsic::nvvm_min_ull;
4171 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num &&
4176 DAG.
getNode(DivOpc, DL, VT, Num, Den),
4232 IsSigned = (LHSSign ==
Signed);
4236 const APInt &Val = CI->getAPIntValue();
4238 return Val.
isIntN(OptSize);
4247 return LHSSign == RHSSign;
4269 if (isa<ConstantSDNode>(LHS)) {
4283 if (ShiftAmt.
sge(0) && ShiftAmt.
slt(BitWidth)) {
4284 APInt MulVal =
APInt(BitWidth, 1) << ShiftAmt;
4318 return DCI.
DAG.
getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4348 DAGCombinerInfo &DCI)
const {
4403 unsigned PrefAlign =
4405 if (Align < PrefAlign) {
4420 bool NeedTrunc =
false;
4426 unsigned Opcode = 0;
4457 for (
unsigned i = 0;
i < NumElts; ++
i) {
4479 unsigned IntrinNo = cast<ConstantSDNode>(Intrin.
getNode())->getZExtValue();
4483 case Intrinsic::nvvm_ldg_global_i:
4484 case Intrinsic::nvvm_ldg_global_f:
4485 case Intrinsic::nvvm_ldg_global_p:
4486 case Intrinsic::nvvm_ldu_global_i:
4487 case Intrinsic::nvvm_ldu_global_f:
4488 case Intrinsic::nvvm_ldu_global_p: {
4501 bool NeedTrunc =
false;
4507 unsigned Opcode = 0;
4517 case Intrinsic::nvvm_ldg_global_i:
4518 case Intrinsic::nvvm_ldg_global_f:
4519 case Intrinsic::nvvm_ldg_global_p:
4522 case Intrinsic::nvvm_ldu_global_i:
4523 case Intrinsic::nvvm_ldu_global_f:
4524 case Intrinsic::nvvm_ldu_global_p:
4534 case Intrinsic::nvvm_ldg_global_i:
4535 case Intrinsic::nvvm_ldg_global_f:
4536 case Intrinsic::nvvm_ldg_global_p:
4539 case Intrinsic::nvvm_ldu_global_i:
4540 case Intrinsic::nvvm_ldu_global_f:
4541 case Intrinsic::nvvm_ldu_global_p:
4568 for (
unsigned i = 0;
i < NumElts; ++
i) {
4586 "Custom handling of non-i8 ldu/ldg?");
4603 NewLD.getValue(0)));
4610 void NVPTXTargetLowering::ReplaceNodeResults(
4625 void NVPTXSection::anchor() {}
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type (if unknown returns 0).
Instances of this class represent a uniqued identifier for a section in the current translation unit...
void push_back(const T &Elt)
A parsed version of the target data layout string in and methods for querying it. ...
const_iterator end(StringRef path)
Get end iterator over path.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Flags getFlags() const
Return the raw flags of the source value,.
LLVMContext * getContext() const
LLVM Argument representation.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue CombineTo(SDNode *N, ArrayRef< SDValue > To, bool AddTo=true)
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B)
GreatestCommonDivisor64 - Return the greatest common divisor of the two values using Euclid's algorit...
bool getAlign(const Function &F, unsigned index, unsigned &align)
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
MCSection * DwarfPubTypesSection
bool hasOneUse() const
Return true if there is exactly one use of this node.
A Module instance is used to store all the information related to an LLVM module. ...
const TargetMachine & getTargetMachine() const
static cl::opt< unsigned > FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden, cl::desc("NVPTX Specific: FMA contraction (0: don't do it"" 1: do it 2: do it aggressively"), cl::init(2))
Carry-setting nodes for multiple precision addition and subtraction.
MCSection * TextSection
Section directive for standard text.
static SDValue PerformSELECTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
MCSection * StaticCtorSection
This section contains the static constructor pointer list.
This class represents a function call, abstracting a target machine's calling convention.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, unsigned retAlignment, const ImmutableCallSite *CS) const
static bool IsMulWideOperandDemotable(SDValue Op, unsigned OptSize, OperandSignedness &S)
IsMulWideOperandDemotable - Checks if the provided DAG node is an operand that can be demoted to OptS...
static bool isImageOrSamplerVal(const Value *arg, const Module *context)
Function Alias Analysis Results
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
const_iterator begin(StringRef path)
Get begin iterator over path.
unsigned getNumOperands() const
Return the number of values used by this operation.
Type * getReturnType() const
Returns the type of the ret val.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
MCSection * getDataSection() const
unsigned getNumOperands() const
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned Num) const
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
const SDValue & getBasePtr() const
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
uint64_t getTypeAllocSizeInBits(Type *Ty) const
Returns the offset in bits between successive objects of the specified type, including alignment padd...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
MCSection * SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const override
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
static SDValue PerformREMCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel)
static unsigned int uniqueCallSite
static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS, unsigned OptSize, bool &IsSigned)
AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can be demoted to OptSize bits...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
struct fuzzer::@269 Flags
Shift and rotation operations.
static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputePTXValueVTs - For the given Type Ty, returns the set of primitive EVTs that compose it...
Class to represent struct types.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
MCSection * DwarfLineSection
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This file contains the simple types necessary to represent the attributes associated with functions a...
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
The memory access is dereferenceable (i.e., doesn't trap).
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results)
ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MCSection * DwarfFrameSection
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SmallVector< ISD::InputArg, 32 > Ins
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
A constant value that is initialized with an expression using other constant values.
bool isKernelFunction(const Function &F)
unsigned getIROrder() const
Return the node ordering.
const MCSection * DwarfDebugInlineSection
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
unsigned int getSmVersion() const
Simple integer binary arithmetic operators.
MCSection * StaticDtorSection
This section contains the static destructor pointer list.
SmallVector< ISD::OutputArg, 32 > Outs
TypeID getTypeID() const
Return the type id for the type.
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
static SDValue PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel)
PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
void setIROrder(unsigned Order)
Set the node ordering.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
static SDValue PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
const DataLayout & getDataLayout() const
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
MCSection * DataSection
Section directive for standard data.
Class to represent pointers.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const NVPTXSubtarget &Subtarget, CodeGenOpt::Level OptLevel)
PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1...
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
initializer< Ty > init(const Ty &Val)
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned getStoreSizeInBits() const
getStoreSizeInBits - Return the number of bits overwritten by a store of the specified value type...
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const
MVT - Machine Value Type.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static cl::opt< bool > sched4reg("nvptx-sched4reg", cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false))
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool isVectorTy() const
True if this is an instance of VectorType.
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
bool sge(const APInt &RHS) const
Signed greather or equal comparison.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const NVPTXTargetLowering * getTargetLowering() const override
Carry-using nodes for multiple precision addition and subtraction.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
MCSection * DwarfStrSection
static unsigned getOpcForSurfaceInstr(unsigned Intrinsic)
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
This class provides iterator support for SDUse operands that use a specific SDNode.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
unsigned getOpcode() const
TRAP - Trapping instruction.
ManagedStringPool * getManagedStrPool() const
SectionKind - This is a simple POD value that classifies the properties of a section.
static mvt_range vector_valuetypes()
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
const SDValue & getValue() const
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results)
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
EVT - Extended Value Type.
bool isPointerTy() const
True if this is an instance of PointerType.
std::vector< ArgListEntry > ArgListTy
static SDValue PerformSHLCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel)
PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
MCSection * DwarfInfoSection
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool IsPTXVectorType(MVT VT)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
MCSection * DwarfAbbrevSection
const MachinePointerInfo & getPointerInfo() const
static SDValue TryMULWIDECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply of M/2 bits that produces...
MCSection * EHFrameSection
EH frame section.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
InstrTy * getInstruction() const
bool slt(const APInt &RHS) const
Signed less than comparison.
std::string * getManagedString(const char *S)
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
NVPTXTargetLowering(const NVPTXTargetMachine &TM, const NVPTXSubtarget &STI)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
MCSection * DwarfRangesSection
const SDValue & getChain() const
Byte Swap and Counting operators.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
This is an abstract virtual class for memory operations.
MCSection * DwarfARangesSection
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
Value * getArgOperand(unsigned i) const
getArgOperand/setArgOperand - Return/set the i-th call argument.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class to represent vector types.
Class for arbitrary precision integers.
bool isCast() const
Return true if this is a convert constant expression.
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
static SDValue PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel)
PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
iterator_range< use_iterator > uses()
Select(COND, TRUEVAL, FALSEVAL).
op_iterator op_begin() const
bool isIntegerTy() const
True if this is an instance of IntegerType.
static use_iterator use_end()
ZERO_EXTEND - Used for integer types, zeroing the new bits.
ANY_EXTEND - Used for integer types. The high bits are undefined.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
BR_JT - Jumptable branch.
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
SmallVector< SDValue, 32 > OutVals
MCSection * LSDASection
If exception handling is supported by the target, this is the section the Language Specific Data Area...
Bitwise operators - logical and, logical or, logical xor.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool isAggregateType() const
Return true if the type is an aggregate type.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Represents a section in PTX PTX does not have sections.
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
The memory access always returns the same value (or traps).
op_iterator op_end() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
StringRef getValueAsString() const
Return the attribute's value as a string.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
A raw_ostream that writes to an std::string.
FunTy * getCalledFunction() const
getCalledFunction - Return the function being called if this is a direct call, otherwise return null ...
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static const Function * getParent(const Value *V)
const TargetLowering & getTargetLoweringInfo() const
Primary interface to the complete machine description for the target machine.
MCSection * BSSSection
Section that is default initialized to zero.
~NVPTXTargetObjectFile() override
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
MCSection * ReadOnlySection
Section that is readonly and can contain arbitrary initialized data.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
MCSection * DwarfMacinfoSection
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MCSection * DwarfLocSection
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
static unsigned getOpcForTextureInstr(unsigned Intrinsic)
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
This file describes how to lower LLVM code to machine code.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
const NVPTXRegisterInfo * getRegisterInfo() const override
uint64_t getZExtValue() const
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.
const NVPTXTargetMachine * nvTM