28 #define DEBUG_TYPE "postrapseudos"
62 "Post-RA pseudo instruction expansion pass",
false,
false)
73 CopyMI->addOperand(MO);
88 assert(SubIdx != 0 &&
"Invalid index for insert_subreg");
89 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
92 "Insert destination must be in a physical register");
94 "Inserted value must be in a physical register");
96 DEBUG(
dbgs() <<
"subreg: CONVERTING: " << *MI);
100 DEBUG(
dbgs() <<
"subreg: replaced by: " << *MI);
104 if (DstSubReg == InsReg) {
109 if (DstReg != InsReg) {
113 DEBUG(
dbgs() <<
"subreg: replace by: " << *MI);
124 CopyMI->addRegisterDefined(DstReg);
146 DEBUG(
dbgs() <<
"identity copy: " << *MI);
166 TransferImplicitOperands(MI);
169 dbgs() <<
"replaced by: " << *(--dMI);
180 <<
"********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
181 <<
"********** Function: " << MF.
getName() <<
'\n');
185 bool MadeChange =
false;
188 mbbi != mbbe; ++mbbi) {
207 case TargetOpcode::SUBREG_TO_REG:
208 MadeChange |= LowerSubregToReg(&MI);
210 case TargetOpcode::COPY:
211 MadeChange |= LowerCopy(&MI);
213 case TargetOpcode::DBG_VALUE:
215 case TargetOpcode::INSERT_SUBREG:
216 case TargetOpcode::EXTRACT_SUBREG:
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
AnalysisUsage & addPreservedID(const void *ID)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
INITIALIZE_PASS(ExpandPostRA,"postrapseudos","Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.