26 #define DEBUG_TYPE "regalloc"
30 cl::desc(
"Limit all regclasses to N registers"));
33 :
Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
44 PSetLimits.reset(
new unsigned[NumPSets]);
45 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
50 assert(TRI &&
"no register info set");
52 if (Update || CSR != CalleeSaved) {
57 for (
unsigned N = 0;
unsigned Reg = CSR[
N]; ++
N)
66 if (Reserved.
size() != RR.
size() || RR != Reserved) {
80 assert(RC &&
"no register class given");
81 RCInfo &RCI = RegClass[RC->
getID()];
91 unsigned MinCost = 0xff;
92 unsigned LastCost = ~0u;
93 unsigned LastCostChange = 0;
98 for (
unsigned i = 0;
i != RawOrder.
size(); ++
i) {
99 unsigned PhysReg = RawOrder[
i];
101 if (Reserved.
test(PhysReg))
110 if (Cost != LastCost)
112 RCI.Order[N++] = PhysReg;
116 RCI.NumRegs = N + CSRAlias.
size();
117 assert (RCI.NumRegs <= NumRegs &&
"Allocation order larger than regclass");
120 for (
unsigned i = 0, e = CSRAlias.
size();
i != e; ++
i) {
121 unsigned PhysReg = CSRAlias[
i];
123 if (Cost != LastCost)
125 RCI.Order[N++] = PhysReg;
137 RCI.ProperSubClass =
true;
139 RCI.MinCost = uint8_t(MinCost);
140 RCI.LastCostChange = LastCostChange;
144 for (
unsigned I = 0;
I != RCI.NumRegs; ++
I)
146 dbgs() << (RCI.ProperSubClass ?
" ] (sub-class)\n" :
" ]\n");
158 unsigned NumRCUnits = 0;
162 for (; *PSetID != -1; ++PSetID) {
163 if ((
unsigned)*PSetID == Idx)
172 if (!RC || NUnits > NumRCUnits) {
void push_back(const T &Elt)
size_type size() const
size - Returns the number of bits in this bitvector.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
regclass_iterator regclass_end() const
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned getNumRegClasses() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
size_t size() const
size - Get the array size.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
initializer< Ty > init(const Ty &Val)
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
regclass_iterator regclass_begin() const
Register class iterators.
unsigned getCostPerUse(unsigned RegNo) const
Return the additional cost of using this register instead of other registers in its class...
MCRegAliasIterator enumerates all registers aliasing Reg.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
bool test(unsigned Idx) const
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getNumRegs() const
Return the number of registers in this class.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static cl::opt< unsigned > StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), cl::desc("Limit all regclasses to N registers"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const TargetRegisterClass *const * regclass_iterator
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...