19 #define DEBUG_TYPE "ppctti"
28 cl::desc(
"The loop prefetch cache line size"));
88 case Intrinsic::sadd_with_overflow:
89 case Intrinsic::uadd_with_overflow:
90 case Intrinsic::ssub_with_overflow:
91 case Intrinsic::usub_with_overflow:
95 case Intrinsic::experimental_stackmap:
99 case Intrinsic::experimental_patchpoint_void:
100 case Intrinsic::experimental_patchpoint_i64:
119 unsigned ImmIdx = ~0U;
120 bool ShiftedFree =
false, RunFree =
false, UnsignedFree =
false,
125 case Instruction::GetElementPtr:
140 case Instruction::Sub:
141 case Instruction::Mul:
142 case Instruction::Shl:
143 case Instruction::LShr:
144 case Instruction::AShr:
147 case Instruction::ICmp:
155 case Instruction::PHI:
163 if (ZeroFree && Imm == 0)
215 return LoopHasReductions;
225 return ST->
hasVSX() ? 64 : 32;
230 if (ST->
hasQPX())
return 256;
289 Opd1PropInfo, Opd2PropInfo);
319 assert(ISD &&
"Invalid opcode");
339 unsigned LHSPenalty = 2;
366 bool IsVSXType = ST->
hasVSX() &&
368 bool IsQPXType = ST->
hasQPX() &&
377 (MemBytes == 64 || (ST->
hasP8Vector() && MemBytes == 32)))
381 unsigned SrcBytes = LT.second.getStoreSize();
382 if (!SrcBytes || !Alignment || Alignment >= SrcBytes)
393 ((!ST->
hasP8Vector() && IsAltivecType) || IsQPXType) &&
394 Alignment >= LT.second.getScalarType().getStoreSize())
395 return Cost + LT.first;
401 if (IsVSXType || (ST->
hasVSX() && IsAltivecType))
408 Cost += LT.first*(SrcBytes/Alignment-1);
425 assert(isa<VectorType>(VecTy) &&
426 "Expect a vector type for interleaved memory op");
439 Cost += Factor*(LT.first-1);
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
uint64_t getZExtValue() const
Get zero extended value.
Cost tables and simple lookup functions.
bool enableInterleavedAccessVectorization()
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
constexpr bool isInt< 16 >(int64_t x)
unsigned getPrefetchDistance()
int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
int getIntImmCost(const APInt &Imm, Type *Ty)
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
unsigned getMaxInterleaveFactor(unsigned VF)
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Type * getScalarType() const LLVM_READONLY
If this is a vector type, return the element type, otherwise return 'this'.
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
initializer< Ty > init(const Ty &Val)
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
The instances of the Type class are immutable: once they are created, they are never changed...
bool isVectorTy() const
True if this is an instance of VectorType.
int64_t getSExtValue() const
Get sign extended value.
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
POPCNTDKind hasPOPCNTD() const
unsigned getBitWidth() const
Return the number of bits in the APInt.
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
unsigned getCacheLineSize()
unsigned getNumberOfRegisters(bool Vector)
constexpr bool isInt< 32 >(int64_t x)
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
bool enableAggressiveInterleaving(bool LoopHasReductions)
Class for arbitrary precision integers.
bool isIntegerTy() const
True if this is an instance of IntegerType.
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
unsigned getVectorNumElements() const
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
constexpr bool isShiftedMask_64(uint64_t Value)
isShiftedMask_64 - This function returns true if the argument contains a non-empty sequence of ones w...
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Represents a single loop in the control flow graph.
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
constexpr bool isUInt< 16 >(uint64_t x)
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
unsigned getRegisterBitWidth(bool Vector)
constexpr bool isShiftedMask_32(uint32_t Value)
isShiftedMask_32 - This function returns true if the argument contains a non-empty sequence of ones w...
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
This file describes how to lower LLVM code to machine code.