LLVM  4.0.0
AArch64RegisterInfo.cpp
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1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64FrameLowering.h"
17 #include "AArch64InstrInfo.h"
19 #include "AArch64Subtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/Function.h"
31 
32 using namespace llvm;
33 
34 #define GET_REGINFO_TARGET_DESC
35 #include "AArch64GenRegisterInfo.inc"
36 
38  : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
39 
40 const MCPhysReg *
42  assert(MF && "Invalid MachineFunction pointer.");
44  // GHC set of callee saved regs is empty as all those regs are
45  // used for passing STG regs around
46  return CSR_AArch64_NoRegs_SaveList;
48  return CSR_AArch64_AllRegs_SaveList;
50  return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
51  CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
52  CSR_AArch64_CXX_TLS_Darwin_SaveList;
54  ->supportSwiftError() &&
56  Attribute::SwiftError))
57  return CSR_AArch64_AAPCS_SwiftError_SaveList;
59  return CSR_AArch64_RT_MostRegs_SaveList;
60  else
61  return CSR_AArch64_AAPCS_SaveList;
62 }
63 
65  const MachineFunction *MF) const {
66  assert(MF && "Invalid MachineFunction pointer.");
68  MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
69  return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
70  return nullptr;
71 }
72 
73 const uint32_t *
75  CallingConv::ID CC) const {
76  if (CC == CallingConv::GHC)
77  // This is academic becase all GHC calls are (supposed to be) tail calls
78  return CSR_AArch64_NoRegs_RegMask;
79  if (CC == CallingConv::AnyReg)
80  return CSR_AArch64_AllRegs_RegMask;
81  if (CC == CallingConv::CXX_FAST_TLS)
82  return CSR_AArch64_CXX_TLS_Darwin_RegMask;
84  ->supportSwiftError() &&
85  MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
86  return CSR_AArch64_AAPCS_SwiftError_RegMask;
87  if (CC == CallingConv::PreserveMost)
88  return CSR_AArch64_RT_MostRegs_RegMask;
89  else
90  return CSR_AArch64_AAPCS_RegMask;
91 }
92 
94  if (TT.isOSDarwin())
95  return CSR_AArch64_TLS_Darwin_RegMask;
96 
97  assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS");
98  return CSR_AArch64_TLS_ELF_RegMask;
99 }
100 
101 const uint32_t *
103  CallingConv::ID CC) const {
104  // This should return a register mask that is the same as that returned by
105  // getCallPreservedMask but that additionally preserves the register used for
106  // the first i64 argument (which must also be the register used to return a
107  // single i64 return value)
108  //
109  // In case that the calling convention does not use the same register for
110  // both, the function should return NULL (does not currently apply)
111  assert(CC != CallingConv::GHC && "should not be GHC calling convention.");
112  return CSR_AArch64_AAPCS_ThisReturn_RegMask;
113 }
114 
115 BitVector
117  const AArch64FrameLowering *TFI = getFrameLowering(MF);
118 
119  // FIXME: avoid re-calculating this every time.
120  BitVector Reserved(getNumRegs());
121  markSuperRegs(Reserved, AArch64::SP);
122  markSuperRegs(Reserved, AArch64::XZR);
123  markSuperRegs(Reserved, AArch64::WSP);
124  markSuperRegs(Reserved, AArch64::WZR);
125 
126  if (TFI->hasFP(MF) || TT.isOSDarwin()) {
127  markSuperRegs(Reserved, AArch64::FP);
128  markSuperRegs(Reserved, AArch64::W29);
129  }
130 
132  markSuperRegs(Reserved, AArch64::X18); // Platform register
133  markSuperRegs(Reserved, AArch64::W18);
134  }
135 
136  if (hasBasePointer(MF)) {
137  markSuperRegs(Reserved, AArch64::X19);
138  markSuperRegs(Reserved, AArch64::W19);
139  }
140 
141  assert(checkAllSuperRegsMarked(Reserved));
142  return Reserved;
143 }
144 
146  unsigned Reg) const {
147  const AArch64FrameLowering *TFI = getFrameLowering(MF);
148 
149  switch (Reg) {
150  default:
151  break;
152  case AArch64::SP:
153  case AArch64::XZR:
154  case AArch64::WSP:
155  case AArch64::WZR:
156  return true;
157  case AArch64::X18:
158  case AArch64::W18:
159  return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
160  case AArch64::FP:
161  case AArch64::W29:
162  return TFI->hasFP(MF) || TT.isOSDarwin();
163  case AArch64::W19:
164  case AArch64::X19:
165  return hasBasePointer(MF);
166  }
167 
168  return false;
169 }
170 
171 bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
172  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
173 }
174 
175 const TargetRegisterClass *
177  unsigned Kind) const {
178  return &AArch64::GPR64RegClass;
179 }
180 
181 const TargetRegisterClass *
183  if (RC == &AArch64::CCRRegClass)
184  return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV.
185  return RC;
186 }
187 
188 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; }
189 
191  const MachineFrameInfo &MFI = MF.getFrameInfo();
192 
193  // In the presence of variable sized objects, if the fixed stack size is
194  // large enough that referencing from the FP won't result in things being
195  // in range relatively often, we can use a base pointer to allow access
196  // from the other direction like the SP normally works.
197  // Furthermore, if both variable sized objects are present, and the
198  // stack needs to be dynamically re-aligned, the base pointer is the only
199  // reliable way to reference the locals.
200  if (MFI.hasVarSizedObjects()) {
201  if (needsStackRealignment(MF))
202  return true;
203  // Conservatively estimate whether the negative offset from the frame
204  // pointer will be sufficient to reach. If a function has a smallish
205  // frame, it's less likely to have lots of spills and callee saved
206  // space, so it's all more likely to be within range of the frame pointer.
207  // If it's wrong, we'll materialize the constant and still get to the
208  // object; it's just suboptimal. Negative offsets use the unscaled
209  // load/store instructions, which have a 9-bit signed immediate.
210  return MFI.getLocalFrameSize() >= 256;
211  }
212 
213  return false;
214 }
215 
216 unsigned
218  const AArch64FrameLowering *TFI = getFrameLowering(MF);
219  return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
220 }
221 
223  const MachineFunction &MF) const {
224  return true;
225 }
226 
228  const MachineFunction &MF) const {
229  return true;
230 }
231 
232 bool
234  const MachineFrameInfo &MFI = MF.getFrameInfo();
235  // AArch64FrameLowering::resolveFrameIndexReference() can always fall back
236  // to the stack pointer, so only put the emergency spill slot next to the
237  // FP when there's no better way to access it (SP or base pointer).
238  return MFI.hasVarSizedObjects() && !hasBasePointer(MF);
239 }
240 
242  const MachineFunction &MF) const {
243  return true;
244 }
245 
246 bool
248  const MachineFrameInfo &MFI = MF.getFrameInfo();
250  return true;
251  return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken();
252 }
253 
254 /// needsFrameBaseReg - Returns true if the instruction's frame index
255 /// reference would be better served by a base register other than FP
256 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
257 /// references it should create new base registers for.
259  int64_t Offset) const {
260  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
261  assert(i < MI->getNumOperands() &&
262  "Instr doesn't have FrameIndex operand!");
263 
264  // It's the load/store FI references that cause issues, as it can be difficult
265  // to materialize the offset if it won't fit in the literal field. Estimate
266  // based on the size of the local frame and some conservative assumptions
267  // about the rest of the stack frame (note, this is pre-regalloc, so
268  // we don't know everything for certain yet) whether this offset is likely
269  // to be out of range of the immediate. Return true if so.
270 
271  // We only generate virtual base registers for loads and stores, so
272  // return false for everything else.
273  if (!MI->mayLoad() && !MI->mayStore())
274  return false;
275 
276  // Without a virtual base register, if the function has variable sized
277  // objects, all fixed-size local references will be via the frame pointer,
278  // Approximate the offset and see if it's legal for the instruction.
279  // Note that the incoming offset is based on the SP value at function entry,
280  // so it'll be negative.
281  MachineFunction &MF = *MI->getParent()->getParent();
282  const AArch64FrameLowering *TFI = getFrameLowering(MF);
283  MachineFrameInfo &MFI = MF.getFrameInfo();
284 
285  // Estimate an offset from the frame pointer.
286  // Conservatively assume all GPR callee-saved registers get pushed.
287  // FP, LR, X19-X28, D8-D15. 64-bits each.
288  int64_t FPOffset = Offset - 16 * 20;
289  // Estimate an offset from the stack pointer.
290  // The incoming offset is relating to the SP at the start of the function,
291  // but when we access the local it'll be relative to the SP after local
292  // allocation, so adjust our SP-relative offset by that allocation size.
293  Offset += MFI.getLocalFrameSize();
294  // Assume that we'll have at least some spill slots allocated.
295  // FIXME: This is a total SWAG number. We should run some statistics
296  // and pick a real one.
297  Offset += 128; // 128 bytes of spill slots
298 
299  // If there is a frame pointer, try using it.
300  // The FP is only available if there is no dynamic realignment. We
301  // don't know for sure yet whether we'll need that, so we guess based
302  // on whether there are any local variables that would trigger it.
303  if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))
304  return false;
305 
306  // If we can reference via the stack pointer or base pointer, try that.
307  // FIXME: This (and the code that resolves the references) can be improved
308  // to only disallow SP relative references in the live range of
309  // the VLA(s). In practice, it's unclear how much difference that
310  // would make, but it may be worth doing.
311  if (isFrameOffsetLegal(MI, AArch64::SP, Offset))
312  return false;
313 
314  // The offset likely isn't legal; we want to allocate a virtual base register.
315  return true;
316 }
317 
319  unsigned BaseReg,
320  int64_t Offset) const {
321  assert(Offset <= INT_MAX && "Offset too big to fit in int.");
322  assert(MI && "Unable to get the legal offset for nil instruction.");
323  int SaveOffset = Offset;
324  return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal;
325 }
326 
327 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
328 /// at the beginning of the basic block.
330  unsigned BaseReg,
331  int FrameIdx,
332  int64_t Offset) const {
334  DebugLoc DL; // Defaults to "unknown"
335  if (Ins != MBB->end())
336  DL = Ins->getDebugLoc();
337  const MachineFunction &MF = *MBB->getParent();
338  const AArch64InstrInfo *TII =
339  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
340  const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
342  MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
343  unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
344 
345  BuildMI(*MBB, Ins, DL, MCID, BaseReg)
346  .addFrameIndex(FrameIdx)
347  .addImm(Offset)
348  .addImm(Shifter);
349 }
350 
352  int64_t Offset) const {
353  int Off = Offset; // ARM doesn't need the general 64-bit offsets
354  unsigned i = 0;
355 
356  while (!MI.getOperand(i).isFI()) {
357  ++i;
358  assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
359  }
360  const MachineFunction *MF = MI.getParent()->getParent();
361  const AArch64InstrInfo *TII =
362  MF->getSubtarget<AArch64Subtarget>().getInstrInfo();
363  bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
364  assert(Done && "Unable to resolve frame index!");
365  (void)Done;
366 }
367 
369  int SPAdj, unsigned FIOperandNum,
370  RegScavenger *RS) const {
371  assert(SPAdj == 0 && "Unexpected");
372 
373  MachineInstr &MI = *II;
375  MachineFunction &MF = *MBB.getParent();
376  const AArch64InstrInfo *TII =
377  MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
378  const AArch64FrameLowering *TFI = getFrameLowering(MF);
379 
380  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
381  unsigned FrameReg;
382  int Offset;
383 
384  // Special handling of dbg_value, stackmap and patchpoint instructions.
385  if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
386  MI.getOpcode() == TargetOpcode::PATCHPOINT) {
387  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
388  /*PreferFP=*/true);
389  Offset += MI.getOperand(FIOperandNum + 1).getImm();
390  MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
391  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
392  return;
393  }
394 
395  // Modify MI as necessary to handle as much of 'Offset' as possible
396  Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
397  if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
398  return;
399 
400  assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
401  "Emergency spill slot is out of reach");
402 
403  // If we get here, the immediate doesn't fit into the instruction. We folded
404  // as much as possible above. Handle the rest, providing a register that is
405  // SP+LargeImm.
406  unsigned ScratchReg =
407  MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
408  emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
409  MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
410 }
411 
413  MachineFunction &MF) const {
414  const AArch64FrameLowering *TFI = getFrameLowering(MF);
415 
416  switch (RC->getID()) {
417  default:
418  return 0;
419  case AArch64::GPR32RegClassID:
420  case AArch64::GPR32spRegClassID:
421  case AArch64::GPR32allRegClassID:
422  case AArch64::GPR64spRegClassID:
423  case AArch64::GPR64allRegClassID:
424  case AArch64::GPR64RegClassID:
425  case AArch64::GPR32commonRegClassID:
426  case AArch64::GPR64commonRegClassID:
427  return 32 - 1 // XZR/SP
428  - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
430  .isX18Reserved() // X18 reserved as platform register
431  - hasBasePointer(MF); // X19
432  case AArch64::FPR8RegClassID:
433  case AArch64::FPR16RegClassID:
434  case AArch64::FPR32RegClassID:
435  case AArch64::FPR64RegClassID:
436  case AArch64::FPR128RegClassID:
437  return 32;
438 
439  case AArch64::DDRegClassID:
440  case AArch64::DDDRegClassID:
441  case AArch64::DDDDRegClassID:
442  case AArch64::QQRegClassID:
443  case AArch64::QQQRegClassID:
444  case AArch64::QQQQRegClassID:
445  return 32;
446 
447  case AArch64::FPR128_loRegClassID:
448  return 16;
449  }
450 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
bool cannotEliminateFrame(const MachineFunction &MF) const
size_t i
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const uint32_t * getTLSCallPreservedMask() const
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:165
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
unsigned getFrameRegister(const MachineFunction &MF) const override
int64_t getLocalFrameSize() const
Get the size of the local object blob.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset, bool *OutUseUnscaledOp=nullptr, unsigned *OutUnscaledOp=nullptr, int *EmittableOffset=nullptr)
Check if the Offset is a valid frame offset for MI.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineBasicBlock * MBB
AArch64RegisterInfo(const Triple &TT)
int64_t getImm() const
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool isDebugValue() const
Definition: MachineInstr.h:777
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const AArch64InstrInfo *TII)
rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
uint32_t Offset
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isScavengingFrameIndex(int FI) const
Query whether a frame index is a scavenging frame index.
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:455
const uint32_t * getThisReturnPreservedMask(const MachineFunction &MF, CallingConv::ID) const
getThisReturnPreservedMask - Returns a call preserved mask specific to the case that 'returned' is on...
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:176
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
BitVector getReservedRegs(const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
bool useFPForScavengingIndex(const MachineFunction &MF) const override
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const unsigned Kind
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isConstantPhysReg(unsigned PhysReg) const override
IRTranslator LLVM IR MI
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
needsFrameBaseReg - Returns true if the instruction's frame index reference would be better served by...
bool hasBasePointer(const MachineFunction &MF) const