LLVM  4.0.0
Public Member Functions | Static Public Member Functions | List of all members
llvm::AArch64InstrInfo Class Referencefinal

#include <AArch64InstrInfo.h>

Inheritance diagram for llvm::AArch64InstrInfo:
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Collaboration diagram for llvm::AArch64InstrInfo:
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Public Member Functions

 AArch64InstrInfo (const AArch64Subtarget &STI)
 
const AArch64RegisterInfogetRegisterInfo () const
 getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More...
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 GetInstSize - Return the number of bytes of code the specified instruction may be. More...
 
bool isAsCheapAsAMove (const MachineInstr &MI) const override
 
bool isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
 
bool areMemAccessesTriviallyDisjoint (MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
bool hasShiftedReg (const MachineInstr &MI) const
 Returns true if there is a shiftable register and that the shift value is non-zero. More...
 
bool hasExtendedReg (const MachineInstr &MI) const
 Returns true if there is an extendable register and that the extending value is non-zero. More...
 
bool isGPRZero (const MachineInstr &MI) const
 Does this instruction set its full destination register to zero? More...
 
bool isGPRCopy (const MachineInstr &MI) const
 Does this instruction rename a GPR without modifying bits? More...
 
bool isFPRCopy (const MachineInstr &MI) const
 Does this instruction rename an FPR without modifying bits? More...
 
bool isScaledAddr (const MachineInstr &MI) const
 Return true if this is load/store scales or extends its register offset. More...
 
bool isLdStPairSuppressed (const MachineInstr &MI) const
 Return true if pairing the given load or store is hinted to be unprofitable. More...
 
bool isUnscaledLdSt (unsigned Opc) const
 Return true if this is an unscaled load/store. More...
 
bool isUnscaledLdSt (MachineInstr &MI) const
 Return true if this is an unscaled load/store. More...
 
bool isCandidateToMergeOrPair (MachineInstr &MI) const
 Return true if this is a load/store that can be potentially paired/merged. More...
 
void suppressLdStPair (MachineInstr &MI) const
 Hint that pairing the given load or store is unprofitable. More...
 
bool getMemOpBaseRegImmOfs (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
 
bool getMemOpBaseRegImmOfsWidth (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) const
 
bool shouldClusterMemOps (MachineInstr &FirstLdSt, MachineInstr &SecondLdSt, unsigned NumLoads) const override
 Detect opportunities for ldp/stp formation. More...
 
bool shouldScheduleAdjacent (const MachineInstr &First, const MachineInstr &Second) const override
 
MachineInstremitFrameIndexDebugValue (MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var, const MDNode *Expr, const DebugLoc &DL) const
 
void copyPhysRegTuple (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, llvm::ArrayRef< unsigned > Indices) const
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool isSubregFoldable () const override
 
MachineInstrfoldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
MachineBasicBlockgetBranchDestBlock (const MachineInstr &MI) const override
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void getNoopForMachoTarget (MCInst &NopInst) const override
 
bool analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
 analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue. More...
 
bool optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
 optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register. More...
 
bool optimizeCondBranch (MachineInstr &MI) const override
 Replace csincr-branch sequence by simple conditional branch. More...
 
bool isThroughputPattern (MachineCombinerPattern Pattern) const override
 Return true when a code sequence can improve throughput. More...
 
bool getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const override
 Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>. More...
 
bool isAssociativeAndCommutative (const MachineInstr &Inst) const override
 Return true when Inst is associative and commutative so that it can be reassociated. More...
 
void genAlternativeCodeSequence (MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
 When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. More...
 
bool useMachineCombiner () const override
 AArch64 supports MachineCombiner. More...
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
std::pair< unsigned, unsigneddecomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< unsigned,
const char * > > 
getSerializableDirectMachineOperandTargetFlags () const override
 
ArrayRef< std::pair< unsigned,
const char * > > 
getSerializableBitmaskMachineOperandTargetFlags () const override
 

Static Public Member Functions

static bool isPairableLdStInst (const MachineInstr &MI)
 

Detailed Description

Definition at line 30 of file AArch64InstrInfo.h.

Constructor & Destructor Documentation

AArch64InstrInfo::AArch64InstrInfo ( const AArch64Subtarget STI)
explicit

Definition at line 69 of file AArch64InstrInfo.cpp.

Member Function Documentation

bool AArch64InstrInfo::analyzeBranch ( MachineBasicBlock MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override
bool AArch64InstrInfo::analyzeCompare ( const MachineInstr MI,
unsigned SrcReg,
unsigned SrcReg2,
int &  CmpMask,
int &  CmpValue 
) const
override

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2, and the value it compares against in CmpValue.

Return true if the comparison instruction can be analyzed.

Definition at line 820 of file AArch64InstrInfo.cpp.

References llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint ( MachineInstr MIa,
MachineInstr MIb,
AliasAnalysis AA = nullptr 
) const
override
bool AArch64InstrInfo::canInsertSelect ( const MachineBasicBlock MBB,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override
void AArch64InstrInfo::copyPhysReg ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override
void AArch64InstrInfo::copyPhysRegTuple ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  I,
const DebugLoc DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc,
unsigned  Opcode,
llvm::ArrayRef< unsigned Indices 
) const
std::pair< unsigned, unsigned > AArch64InstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override
MachineInstr * AArch64InstrInfo::emitFrameIndexDebugValue ( MachineFunction MF,
int  FrameIx,
uint64_t  Offset,
const MDNode Var,
const MDNode Expr,
const DebugLoc DL 
) const
bool AArch64InstrInfo::expandPostRAPseudo ( MachineInstr MI) const
override
MachineInstr * AArch64InstrInfo::foldMemoryOperandImpl ( MachineFunction MF,
MachineInstr MI,
ArrayRef< unsigned Ops,
MachineBasicBlock::iterator  InsertPt,
int  FrameIndex,
LiveIntervals LIS = nullptr 
) const
override
void AArch64InstrInfo::genAlternativeCodeSequence ( MachineInstr Root,
MachineCombinerPattern  Pattern,
SmallVectorImpl< MachineInstr * > &  InsInstrs,
SmallVectorImpl< MachineInstr * > &  DelInstrs,
DenseMap< unsigned, unsigned > &  InstrIdxForVirtReg 
) const
override

When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence.

When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.

Definition at line 3676 of file AArch64InstrInfo.cpp.

References Accumulator, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::FMLAv1i32_indexed_OP1, llvm::FMLAv1i32_indexed_OP2, llvm::FMLAv1i64_indexed_OP1, llvm::FMLAv1i64_indexed_OP2, llvm::FMLAv2f32_OP1, llvm::FMLAv2f32_OP2, llvm::FMLAv2f64_OP1, llvm::FMLAv2f64_OP2, llvm::FMLAv2i32_indexed_OP1, llvm::FMLAv2i32_indexed_OP2, llvm::FMLAv2i64_indexed_OP1, llvm::FMLAv2i64_indexed_OP2, llvm::FMLAv4f32_OP1, llvm::FMLAv4f32_OP2, llvm::FMLAv4i32_indexed_OP1, llvm::FMLAv4i32_indexed_OP2, llvm::FMLSv1i32_indexed_OP2, llvm::FMLSv1i64_indexed_OP2, llvm::FMLSv2f32_OP2, llvm::FMLSv2f64_OP2, llvm::FMLSv2i32_indexed_OP2, llvm::FMLSv2i64_indexed_OP2, llvm::FMLSv4f32_OP2, llvm::FMLSv4i32_indexed_OP2, llvm::FMULADDD_OP1, llvm::FMULADDD_OP2, llvm::FMULADDS_OP1, llvm::FMULADDS_OP2, llvm::FMULSUBD_OP1, llvm::FMULSUBD_OP2, llvm::FMULSUBS_OP1, llvm::FMULSUBS_OP2, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), Indexed, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isImm(), llvm::ISD::MUL, llvm::MULADDW_OP1, llvm::MULADDW_OP2, llvm::MULADDWI_OP1, llvm::MULADDX_OP1, llvm::MULADDX_OP2, llvm::MULADDXI_OP1, llvm::MULSUBW_OP1, llvm::MULSUBW_OP2, llvm::MULSUBWI_OP1, llvm::MULSUBX_OP1, llvm::MULSUBX_OP2, llvm::MULSUBXI_OP1, llvm::AArch64_AM::processLogicalImmediate(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SignExtend64(), and TII.

MachineBasicBlock * AArch64InstrInfo::getBranchDestBlock ( const MachineInstr MI) const
override
unsigned AArch64InstrInfo::getInstSizeInBytes ( const MachineInstr MI) const
override
bool AArch64InstrInfo::getMachineCombinerPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns 
) const
override

Return true when there is potentially a faster code sequence for an instruction chain ending in <Root>.

Return true when there is potentially a faster code sequence for an instruction chain ending in Root.

All potential patterns are listed in the <Patterns> array.

All potential patterns are listed in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.

Definition at line 3548 of file AArch64InstrInfo.cpp.

References getFMAPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), and getMaddPatterns().

bool AArch64InstrInfo::getMemOpBaseRegImmOfs ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
const TargetRegisterInfo TRI 
) const
override

Definition at line 1670 of file AArch64InstrInfo.cpp.

References getMemOpBaseRegImmOfsWidth().

bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth ( MachineInstr LdSt,
unsigned BaseReg,
int64_t &  Offset,
unsigned Width,
const TargetRegisterInfo TRI 
) const
void AArch64InstrInfo::getNoopForMachoTarget ( MCInst NopInst) const
override
const AArch64RegisterInfo& llvm::AArch64InstrInfo::getRegisterInfo ( ) const
inline

getRegisterInfo - TargetInstrInfo is a superset of MRegister info.

As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 40 of file AArch64InstrInfo.h.

Referenced by areMemAccessesTriviallyDisjoint(), copyPhysReg(), copyPhysRegTuple(), llvm::AArch64Subtarget::getRegisterInfo(), isCandidateToMergeOrPair(), and optimizeCondBranch().

ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableBitmaskMachineOperandTargetFlags ( ) const
override
ArrayRef< std::pair< unsigned, const char * > > AArch64InstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override
bool AArch64InstrInfo::hasExtendedReg ( const MachineInstr MI) const

Returns true if there is an extendable register and that the extending value is non-zero.

Return true if this is this instruction has a non-zero immediate.

Definition at line 1378 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

bool AArch64InstrInfo::hasShiftedReg ( const MachineInstr MI) const

Returns true if there is a shiftable register and that the shift value is non-zero.

Return true if this is this instruction has a non-zero immediate.

Definition at line 1332 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::isImm().

Referenced by shouldScheduleAdjacent().

unsigned AArch64InstrInfo::insertBranch ( MachineBasicBlock MBB,
MachineBasicBlock TBB,
MachineBasicBlock FBB,
ArrayRef< MachineOperand Cond,
const DebugLoc DL,
int *  BytesAdded = nullptr 
) const
override
void AArch64InstrInfo::insertSelect ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  DstReg,
ArrayRef< MachineOperand Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override
bool AArch64InstrInfo::isAsCheapAsAMove ( const MachineInstr MI) const
override
bool AArch64InstrInfo::isAssociativeAndCommutative ( const MachineInstr Inst) const
override
bool AArch64InstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override
Returns
true if a branch from an instruction with opcode BranchOpc bytes is capable of jumping to a position BrOffset bytes away.

Definition at line 169 of file AArch64InstrInfo.cpp.

References assert(), llvm::tgtok::Bits, getBranchDisplacementBits(), and llvm::isIntN().

bool AArch64InstrInfo::isCandidateToMergeOrPair ( MachineInstr MI) const
bool AArch64InstrInfo::isCoalescableExtInstr ( const MachineInstr MI,
unsigned SrcReg,
unsigned DstReg,
unsigned SubIdx 
) const
override
bool AArch64InstrInfo::isFPRCopy ( const MachineInstr MI) const
bool AArch64InstrInfo::isGPRCopy ( const MachineInstr MI) const
bool AArch64InstrInfo::isGPRZero ( const MachineInstr MI) const
bool AArch64InstrInfo::isLdStPairSuppressed ( const MachineInstr MI) const

Return true if pairing the given load or store is hinted to be unprofitable.

Check all MachineMemOperands for a hint to suppress pairing.

Definition at line 1588 of file AArch64InstrInfo.cpp.

References llvm::any_of(), llvm::MachineInstr::memoperands(), and MOSuppressPair.

Referenced by areCandidatesToMergeOrPair(), and isCandidateToMergeOrPair().

unsigned AArch64InstrInfo::isLoadFromStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override
static bool llvm::AArch64InstrInfo::isPairableLdStInst ( const MachineInstr MI)
inlinestatic

Definition at line 90 of file AArch64InstrInfo.h.

References llvm::MachineInstr::getOpcode().

Referenced by shouldClusterMemOps().

bool AArch64InstrInfo::isScaledAddr ( const MachineInstr MI) const

Return true if this is load/store scales or extends its register offset.

This refers to scaling a dynamic index as opposed to scaled immediates. MI should be a memory op that allows scaled addressing.

Definition at line 1529 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::AArch64_AM::getMemDoShift(), llvm::AArch64_AM::getMemExtendType(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::UXTX.

unsigned AArch64InstrInfo::isStoreToStackSlot ( const MachineInstr MI,
int &  FrameIndex 
) const
override
bool llvm::AArch64InstrInfo::isSubregFoldable ( ) const
inlineoverride

Definition at line 167 of file AArch64InstrInfo.h.

bool AArch64InstrInfo::isThroughputPattern ( MachineCombinerPattern  Pattern) const
override
bool AArch64InstrInfo::isUnscaledLdSt ( unsigned  Opc) const

Return true if this is an unscaled load/store.

Definition at line 1601 of file AArch64InstrInfo.cpp.

Referenced by areCandidatesToMergeOrPair(), isLdOffsetInRangeOfSt(), isUnscaledLdSt(), and shouldClusterMemOps().

bool AArch64InstrInfo::isUnscaledLdSt ( MachineInstr MI) const

Return true if this is an unscaled load/store.

Definition at line 1626 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isUnscaledLdSt().

void AArch64InstrInfo::loadRegFromStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
bool AArch64InstrInfo::optimizeCompareInstr ( MachineInstr CmpInstr,
unsigned  SrcReg,
unsigned  SrcReg2,
int  CmpMask,
int  CmpValue,
const MachineRegisterInfo MRI 
) const
override

optimizeCompareInstr - Convert the instruction supplying the argument to the comparison into one that sets the zero bit in the flags register.

Try to optimize a compare instruction.

A compare instruction is an instruction which produces AArch64::NZCV. It can be truly compare instruction when there are no uses of its destination register.

The following steps are tried in order:

  1. Convert CmpInstr into an unconditional version.
  2. Remove CmpInstr if above there is an instruction producing a needed condition code or an instruction which can be converted into such an instruction. Only comparison with zero is supported.

Definition at line 1010 of file AArch64InstrInfo.cpp.

References assert(), convertFlagSettingOpcode(), llvm::MachineInstr::definesRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), UpdateOperandRegClass(), and llvm::MachineRegisterInfo::use_nodbg_empty().

bool AArch64InstrInfo::optimizeCondBranch ( MachineInstr MI) const
override

Replace csincr-branch sequence by simple conditional branch.

Examples: 1. csinc w9, wzr, wzr, <condition code>=""> tbnz w9, #0, 0x44 to b.<inverted condition="" code>="">

2. csinc w9, wzr, wzr, <condition code>=""> tbz w9, #0, 0x44 to b.<condition code>="">

Replace compare and branch sequence by TBZ/TBNZ instruction when the compare's constant operand is power of 2.

Examples: and w8, w8, #0x400 cbnz w8, L1 to tbnz w8, #10, L1

Parameters
MIConditional Branch
Returns
True when the simple conditional branch is generated

Definition at line 4121 of file AArch64InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AK_Write, areCFlagsAccessedBetweenInstrs(), assert(), llvm::BuildMI(), llvm::AArch64_AM::decodeLogicalImmediate(), llvm::MachineRegisterInfo::def_empty(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AArch64CC::getInvertedCondCode(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getRegisterInfo(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineRegisterInfo::hasOneDef(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineInstr::isCopy(), llvm::isPowerOf2_64(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm_unreachable, llvm::Log2_64(), llvm::BitmaskEnumDetail::Mask(), MBB, llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setSubReg().

unsigned AArch64InstrInfo::removeBranch ( MachineBasicBlock MBB,
int *  BytesRemoved = nullptr 
) const
override
bool AArch64InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override
bool AArch64InstrInfo::shouldClusterMemOps ( MachineInstr FirstLdSt,
MachineInstr SecondLdSt,
unsigned  NumLoads 
) const
override

Detect opportunities for ldp/stp formation.

Only called for LdSt for which getMemOpBaseRegImmOfs returns true.

Definition at line 1866 of file AArch64InstrInfo.cpp.

References assert(), canPairLdStOpc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isCandidateToMergeOrPair(), isPairableLdStInst(), isUnscaledLdSt(), and scaleOffset().

bool AArch64InstrInfo::shouldScheduleAdjacent ( const MachineInstr First,
const MachineInstr Second 
) const
override
void AArch64InstrInfo::storeRegToStackSlot ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MBBI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass RC,
const TargetRegisterInfo TRI 
) const
override
void AArch64InstrInfo::suppressLdStPair ( MachineInstr MI) const

Hint that pairing the given load or store is unprofitable.

Set a flag on the first MachineMemOperand to suppress pairing.

Definition at line 1595 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), and MOSuppressPair.

bool AArch64InstrInfo::useMachineCombiner ( ) const
override

AArch64 supports MachineCombiner.

Definition at line 3053 of file AArch64InstrInfo.cpp.


The documentation for this class was generated from the following files: