LLVM  4.0.0
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 /// \file
9 //===----------------------------------------------------------------------===//
10 
11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
13 
15 
16 namespace llvm {
17 
18 class AMDGPUTargetMachine;
19 class FunctionPass;
20 class GCNTargetMachine;
21 class ModulePass;
22 class Pass;
23 class Target;
24 class TargetMachine;
25 class PassRegistry;
26 
27 // R600 Passes
28 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
29 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
30 FunctionPass *createR600EmitClauseMarkers();
31 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
32 FunctionPass *createR600Packetizer(TargetMachine &tm);
33 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
34 FunctionPass *createAMDGPUCFGStructurizerPass();
35 
36 // SI Passes
37 FunctionPass *createSITypeRewriter();
38 FunctionPass *createSIAnnotateControlFlowPass();
39 FunctionPass *createSIFoldOperandsPass();
40 FunctionPass *createSILowerI1CopiesPass();
41 FunctionPass *createSIShrinkInstructionsPass();
42 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
43 FunctionPass *createSIWholeQuadModePass();
45 FunctionPass *createSIFixSGPRCopiesPass();
46 FunctionPass *createSIDebuggerInsertNopsPass();
47 FunctionPass *createSIInsertWaitsPass();
48 FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
49 
53 
54 void initializeSIFoldOperandsPass(PassRegistry &);
55 extern char &SIFoldOperandsID;
56 
57 void initializeSIShrinkInstructionsPass(PassRegistry&);
58 extern char &SIShrinkInstructionsID;
59 
60 void initializeSIFixSGPRCopiesPass(PassRegistry &);
61 extern char &SIFixSGPRCopiesID;
62 
63 void initializeSILowerI1CopiesPass(PassRegistry &);
64 extern char &SILowerI1CopiesID;
65 
66 void initializeSILoadStoreOptimizerPass(PassRegistry &);
67 extern char &SILoadStoreOptimizerID;
68 
69 void initializeSIWholeQuadModePass(PassRegistry &);
70 extern char &SIWholeQuadModeID;
71 
72 void initializeSILowerControlFlowPass(PassRegistry &);
73 extern char &SILowerControlFlowID;
74 
75 void initializeSIInsertSkipsPass(PassRegistry &);
76 extern char &SIInsertSkipsPassID;
77 
78 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
79 extern char &SIOptimizeExecMaskingID;
80 
81 // Passes common to R600 and SI
82 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
83 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
84 extern char &AMDGPUPromoteAllocaID;
85 
87 FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
88  CodeGenOpt::Level OptLevel);
89 ModulePass *createAMDGPUAlwaysInlinePass();
91 FunctionPass *createAMDGPUAnnotateUniformValues();
92 
93 FunctionPass* createAMDGPUUnifyMetadataPass();
94 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
95 extern char &AMDGPUUnifyMetadataID;
96 
99 
102 
103 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
104 extern char &AMDGPUCodeGenPrepareID;
105 
106 void initializeSIAnnotateControlFlowPass(PassRegistry&);
107 extern char &SIAnnotateControlFlowPassID;
108 
109 void initializeSIDebuggerInsertNopsPass(PassRegistry&);
110 extern char &SIDebuggerInsertNopsID;
111 
112 void initializeSIInsertWaitsPass(PassRegistry&);
113 extern char &SIInsertWaitsID;
114 
117 
118 namespace AMDGPU {
125 };
126 }
127 
128 } // End namespace llvm
129 
130 /// OpenCL uses address spaces to differentiate between
131 /// various memory regions on the hardware. On the CPU
132 /// all of the address spaces point to the same memory,
133 /// however on the GPU, each address space points to
134 /// a separate piece of memory that is unique from other
135 /// memory locations.
136 namespace AMDGPUAS {
137 enum AddressSpaces : unsigned {
138  PRIVATE_ADDRESS = 0, ///< Address space for private memory.
139  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
140  CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2)
141  LOCAL_ADDRESS = 3, ///< Address space for local memory.
142  FLAT_ADDRESS = 4, ///< Address space for flat memory.
143  REGION_ADDRESS = 5, ///< Address space for region memory.
144  PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
145  PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
146 
147  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
148  // order to be able to dynamically index a constant buffer, for example:
149  //
150  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
151 
168 
169  // Some places use this if the address space can't be determined.
171 };
172 
173 } // namespace AMDGPUAS
174 
175 #endif
ModulePass * createAMDGPUAnnotateKernelFeaturesPass()
Pass * createAMDGPUStructurizeCFGPass()
Target & getTheGCNTarget()
The target for GCN GPUs.
char & SIWholeQuadModeID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
char & SIShrinkInstructionsID
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
aarch64 AArch64 CCMP Pass
char & SILoadStoreOptimizerID
Target & getTheAMDGPUTarget()
The target which suports all AMD GPUs.
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca(const TargetMachine *TM=nullptr)
Address space for local memory.
Definition: AMDGPU.h:141
FunctionPass * createAMDGPUCFGStructurizerPass()
FunctionPass * createAMDGPUISelDag(TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a AMDGPU-specific.
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
AddressSpaces
Definition: AMDGPU.h:137
char & SIInsertWaitsID
char & AMDGPUUnifyMetadataID
FunctionPass * createR600ExpandSpecialInstrsPass(TargetMachine &tm)
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
char & SIFixControlFlowLiveIntervalsID
FunctionPass * createR600VectorRegMerger(TargetMachine &tm)
FunctionPass * createSITypeRewriter()
FunctionPass * createR600ClauseMergePass(TargetMachine &tm)
FunctionPass * createSILowerI1CopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
char & SILowerI1CopiesID
void initializeSIFixSGPRCopiesPass(PassRegistry &)
FunctionPass * createR600ControlFlowFinalizer(TargetMachine &tm)
FunctionPass * createSILoadStoreOptimizerPass(TargetMachine &tm)
Address space for region memory.
Definition: AMDGPU.h:143
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIDebuggerInsertNopsPass()
Address space for constant memory (VTX2)
Definition: AMDGPU.h:140
FunctionPass * createSIWholeQuadModePass()
Address space for private memory.
Definition: AMDGPU.h:138
char & SIInsertSkipsPassID
char & AMDGPUAnnotateKernelFeaturesID
FunctionPass * createR600Packetizer(TargetMachine &tm)
FunctionPass * createAMDGPUUnifyMetadataPass()
void initializeSILowerControlFlowPass(PassRegistry &)
Address space for flat memory.
Definition: AMDGPU.h:142
void initializeSIShrinkInstructionsPass(PassRegistry &)
void initializeSIInsertSkipsPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
char & SIOptimizeExecMaskingID
ModulePass * createAMDGPUAlwaysInlinePass()
FunctionPass * createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM=nullptr)
void initializeSIWholeQuadModePass(PassRegistry &)
static const char * Target
char & SIAnnotateControlFlowPassID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
FunctionPass * createSIFixSGPRCopiesPass()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
char & SILowerControlFlowID
void initializeSIAnnotateControlFlowPass(PassRegistry &)
void initializeSIFoldOperandsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createSIShrinkInstructionsPass()
void initializeSIDebuggerInsertNopsPass(PassRegistry &)
Address space for indirect addressible parameter memory (VTX1)
Definition: AMDGPU.h:145
FunctionPass * createSIFoldOperandsPass()
char & SIFixSGPRCopiesID
void initializeSIInsertWaitsPass(PassRegistry &)
Address space for direct addressible parameter memory (CONST0)
Definition: AMDGPU.h:144
FunctionPass * createSIInsertWaitsPass()
FunctionPass * createR600EmitClauseMarkers()
void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry &)
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & AMDGPUPromoteAllocaID
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SIDebuggerInsertNopsID
ModulePass * createAMDGPUOpenCLImageTypeLoweringPass()
char & AMDGPUCodeGenPrepareID
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:139