81 printv(
unsigned r) : R(r) {}
117 unsigned n = RC.Bits.
size();
125 bool ConstRef =
false;
127 for (
unsigned i = 1, n = RC.Bits.
size();
i < n; ++
i) {
132 if (!IsRef && V == SV)
148 unsigned Count =
i - Start;
152 OS <<
'-' <<
i-1 <<
"]:";
155 << SV.
RefI.
Pos+(Count-1) <<
']';
160 SeqRef = ConstRef =
false;
164 unsigned Count = n - Start;
166 OS <<
"]:" << RC[Start];
168 OS <<
'-' << n-1 <<
"]:";
172 << SV.
RefI.
Pos+(Count-1) <<
']';
184 for (CellMapType::iterator
I = Map.begin(),
E = Map.end();
I !=
E; ++
I)
205 bool Changed =
false;
206 for (uint16_t
i = 0, n = Bits.
size();
i < n; ++
i) {
208 Changed |= Bits[
i].meet(RCV,
BitRef(SelfR,
i));
224 for (uint16_t
i = 0;
i <=
E-
B; ++
i)
227 for (uint16_t
i = 0;
i < W-
B; ++
i)
229 for (uint16_t
i = 0;
i <=
E; ++
i)
230 Bits[
i] = RC[
i+(W-B)];
240 for (uint16_t
i = B;
i <=
E; ++
i)
241 RC.Bits[
i-B] = Bits[
i];
246 for (uint16_t
i = 0;
i < W-
B; ++
i)
247 RC.Bits[
i] = Bits[
i+B];
248 for (uint16_t
i = 0;
i <=
E; ++
i)
249 RC.Bits[
i+(W-B)] = Bits[
i];
256 uint16_t W =
width();
263 for (uint16_t
i = 0;
i < W-Sh; ++
i)
266 for (uint16_t
i = 0;
i < Sh; ++
i)
267 Bits[
i] = Bits[W-Sh+
i];
269 for (uint16_t
i = 0;
i < W-Sh; ++
i)
270 Bits[
i+Sh] = Tmp.Bits[
i];
287 for (uint16_t
i = 0;
i < WRC; ++
i)
288 Bits[
i+W] = RC.Bits[
i];
293 uint16_t W =
width();
296 while (C < W && Bits[C] == V)
302 uint16_t W =
width();
305 while (C < W && Bits[W-(C+1)] == V)
311 uint16_t W = Bits.
size();
312 if (RC.Bits.
size() != W)
314 for (uint16_t
i = 0;
i < W; ++
i)
315 if (Bits[
i] != RC[
i])
333 PhysR = *VC->
begin();
361 CellMapType::const_iterator
F = M.find(RR.
Reg);
366 return F->second.extract(M);
379 assert(RR.
Sub == 0 &&
"Unexpected sub-register in definition");
381 for (
unsigned i = 0, n = RC.
width();
i < n; ++
i) {
391 uint16_t W = A.
width();
392 for (uint16_t
i = 0;
i < W; ++
i)
393 if (!A[
i].is(0) && !A[
i].is(1))
402 uint16_t W = A.
width();
403 for (uint16_t
i = 0;
i < W; ++
i) {
417 for (uint16_t
i = 0;
i < W; ++
i) {
429 for (uint16_t
i = 0;
i < BW; ++
i)
436 uint16_t W = A1.
width();
441 for (I = 0; I < W; ++
I) {
444 if (!V1.
num() || !V2.
num())
446 unsigned S =
bool(V1) +
bool(V2) + Carry;
457 else if (V2.
is(Carry))
469 uint16_t W = A1.
width();
474 for (I = 0; I < W; ++
I) {
477 if (!V1.
num() || !V2.
num())
479 unsigned S =
bool(V1) -
bool(V2) - Borrow;
503 uint16_t Z = A1.
ct(
false) + A2.
ct(
false);
513 uint16_t Z = A1.
ct(
false) + A2.
ct(
false);
531 uint16_t W = A1.
width();
541 uint16_t W = A1.
width();
546 Res.
fill(W-Sh, W, Sign);
552 uint16_t W = A1.
width();
555 for (uint16_t
i = 0;
i < W; ++
i) {
562 else if (V1.
is(0) || V2.
is(0))
574 uint16_t W = A1.
width();
577 for (uint16_t
i = 0;
i < W; ++
i) {
580 if (V1.
is(1) || V2.
is(1))
596 uint16_t W = A1.
width();
599 for (uint16_t
i = 0;
i < W; ++
i) {
615 uint16_t W = A1.
width();
617 for (uint16_t
i = 0;
i < W; ++
i) {
630 uint16_t BitN)
const {
638 uint16_t BitN)
const {
647 uint16_t
C = A1.
cl(B), AW = A1.
width();
650 if ((C < AW && A1[AW-1-C].num()) || C == AW)
657 uint16_t
C = A1.
ct(B), AW = A1.
width();
660 if ((C < AW && A1[C].num()) || C == AW)
666 uint16_t FromN)
const {
667 uint16_t W = A1.
width();
672 Res.
fill(FromN, W, Sign);
677 uint16_t FromN)
const {
678 uint16_t W = A1.
width();
686 uint16_t
B, uint16_t
E)
const {
687 uint16_t W = A1.
width();
691 uint16_t Last = (E > 0) ? E-1 : W-1;
701 assert(AtN < W1 && AtN+W2 <= W1);
710 assert(Sub == 0 &&
"Generic BitTracker::mask called for Sub != 0");
712 assert(W > 0 &&
"Cannot generate mask for empty register");
721 case TargetOpcode::REG_SEQUENCE: {
738 case TargetOpcode::COPY: {
767 dbgs() <<
"Visit FI(BB#" << ThisN <<
"): " << PI;
770 assert(MD.
getSubReg() == 0 &&
"Unexpected sub-register in definition");
778 bool Changed =
false;
780 for (
unsigned i = 1, n = PI.getNumOperands();
i < n;
i += 2) {
784 dbgs() <<
" edge BB#" << PredN <<
"->BB#" << ThisN;
785 if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
787 dbgs() <<
" not executable\n";
791 RegisterRef RU = PI.getOperand(
i);
792 RegisterCell ResC = ME.
getCell(RU, Map);
795 <<
" cell: " << ResC <<
"\n";
796 Changed |= DefC.
meet(ResC, DefRR.Reg);
802 <<
" cell: " << DefC <<
"\n";
804 visitUsesOf(DefRR.Reg);
811 dbgs() <<
"Visit MI(BB#" << ThisN <<
"): " <<
MI;
827 <<
" cell: " << ME.
getCell(RU, Map) <<
"\n";
829 dbgs() <<
"Outputs:\n";
830 for (CellMapType::iterator
I = ResMap.begin(),
E = ResMap.end();
832 RegisterRef RD(
I->first);
834 << ME.
getCell(RD, ResMap) <<
"\n";
846 assert(RD.Sub == 0 &&
"Unexpected sub-register in definition");
850 bool Changed =
false;
851 if (!Eval || ResMap.count(RD.Reg) == 0) {
855 if (RefC != ME.
getCell(RD, Map)) {
860 RegisterCell DefC = ME.
getCell(RD, Map);
861 RegisterCell ResC = ME.
getCell(RD, ResMap);
869 for (uint16_t
i = 0, w = DefC.width();
i < w; ++
i) {
870 BitValue &V = DefC[
i];
892 bool FallsThrough =
true, DefaultToAll =
false;
899 dbgs() <<
"Visit BR(BB#" << ThisN <<
"): " <<
MI;
900 assert(MI.isBranch() &&
"Expecting branch instruction");
901 InstrExec.insert(&MI);
902 bool Eval = ME.
evaluate(MI, Map, BTs, FallsThrough);
909 dbgs() <<
" failed to evaluate: will add all CFG successors\n";
910 }
else if (!DefaultToAll) {
913 dbgs() <<
" adding targets:";
914 for (
unsigned i = 0, n = BTs.size();
i < n; ++
i)
915 dbgs() <<
" BB#" << BTs[
i]->getNumber();
917 dbgs() <<
"\n falls through\n";
919 dbgs() <<
"\n does not fall through\n";
921 Targets.insert(BTs.begin(), BTs.end());
924 }
while (FallsThrough && It != End);
939 if (Next != MF.
end())
940 Targets.insert(&*Next);
947 for (
unsigned i = 0, n = Targets.size();
i < n; ++
i) {
948 int TargetN = Targets[
i]->getNumber();
949 FlowQ.push(CFGEdge(ThisN, TargetN));
953 void BT::visitUsesOf(
unsigned Reg) {
961 if (!InstrExec.count(UseI))
966 visitNonBranch(*UseI);
968 visitBranchesFrom(*UseI);
983 assert(Map.count(OldRR.
Reg) > 0 &&
"OldRR not present in map");
986 uint16_t OMB = OM.
first(), OME = OM.last();
987 uint16_t NMB = NM.
first(), NME = NM.
last();
989 assert((OME-OMB == NME-NMB) &&
990 "Substituting registers of different lengths");
991 for (CellMapType::iterator
I = Map.begin(),
E = Map.end();
I !=
E; ++
I) {
993 for (uint16_t
i = 0, w = RC.
width();
i < w; ++
i) {
1010 for (EdgeSetType::iterator
I = EdgeExec.begin(),
E = EdgeExec.end();
1012 if (
I->second == BN)
1022 InstrExec.insert(&MI);
1027 while (!FlowQ.empty())
1047 assert(
I->getNumber() >= 0 &&
"Disconnected block");
1048 unsigned BN =
I->getNumber();
1058 FlowQ.push(CFGEdge(-1, EntryN));
1060 while (!FlowQ.empty()) {
1061 CFGEdge Edge = FlowQ.front();
1064 if (EdgeExec.count(Edge))
1066 EdgeExec.insert(Edge);
1071 while (It != End && It->isPHI()) {
1073 InstrExec.insert(&PI);
1080 if (BlockScanned[Edge.second])
1082 BlockScanned[Edge.second] =
true;
1085 while (It != End && !It->isBranch()) {
1087 InstrExec.insert(&MI);
1096 int NextN = Next->getNumber();
1097 FlowQ.push(CFGEdge(ThisN, NextN));
1102 visitBranchesFrom(*It);
bool isEHPad() const
Returns true if the block is a landing pad.
const TargetRegisterInfo & TRI
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
std::map< unsigned, RegisterCell > CellMapType
bool isInt(const RegisterCell &A) const
RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const
void print_cells(raw_ostream &OS) const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
static RegisterCell top(uint16_t Width)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
void visit(const MachineInstr &MI)
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
static RegisterCell self(unsigned Reg, uint16_t Width)
RegisterCell & rol(uint16_t Sh)
uint16_t getRegBitWidth(const RegisterRef &RR) const
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
uint16_t ct(bool B) const
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
static use_nodbg_iterator use_nodbg_end()
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const
const APInt & getValue() const
Return the constant as an APInt value reference.
uint64_t toInt(const RegisterCell &A) const
RegisterCell extract(const BitMask &M) const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
RegisterCell get(RegisterRef RR) const
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
bool is(unsigned T) const
GraphT::NodeRef Eval(DominatorTreeBaseByGraphTraits< GraphT > &DT, typename GraphT::NodeRef VIn, unsigned LastLinked)
Function Alias Analysis false
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
bool isDebugValue() const
INITIALIZE_PASS(HexagonEarlyIfConversion,"hexagon-eif","Hexagon early if conversion", false, false) bool HexagonEarlyIfConversion MachineBasicBlock * SB
unsigned const MachineRegisterInfo * MRI
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
unsigned getBitWidth() const
Return the number of bits in the APInt.
static const unsigned End
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
void subst(RegisterRef OldRR, RegisterRef NewRR)
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
self_iterator getIterator()
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
succ_iterator succ_begin()
unsigned getSubReg() const
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
SetVector< const MachineBasicBlock * > BranchTargetList
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
Iterator for intrusive lists based on ilist_node.
This is the shared class of boolean and integer constants.
static BitValue self(const BitRef &Self=BitRef())
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
MachineRegisterInfo & MRI
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Class for arbitrary precision integers.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
TerminatorInst::SuccIterator< TerminatorInst *, BasicBlock > succ_iterator
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
virtual BitMask mask(unsigned Reg, unsigned Sub) const
RegisterCell & cat(const RegisterCell &RC)
virtual bool track(const TargetRegisterClass *RC) const
BitTracker(const MachineEvaluator &E, MachineFunction &F)
uint16_t cl(bool B) const
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
RegisterCell eIMM(int64_t V, uint16_t W) const
bool operator==(const RegisterCell &RC) const
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
bool reached(const MachineBasicBlock *B) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< MachineBasicBlock * >::const_iterator const_succ_iterator
void put(RegisterRef RR, const RegisterCell &RC)
RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const
RegisterCell eNOT(const RegisterCell &A1) const
This class implements an extremely fast bulk output stream that can only output to a stream...
bool meet(const RegisterCell &RC, unsigned SelfR)
static RegisterCell ref(const RegisterCell &C)
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const
static BitValue ref(const BitValue &V)
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const