LLVM  4.0.0
AArch64MCTargetDesc.h
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1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
16 
17 #include "llvm/Support/DataTypes.h"
18 
19 namespace llvm {
20 class formatted_raw_ostream;
21 class MCAsmBackend;
22 class MCCodeEmitter;
23 class MCContext;
24 class MCInstrInfo;
25 class MCInstPrinter;
26 class MCRegisterInfo;
27 class MCObjectWriter;
28 class MCStreamer;
29 class MCSubtargetInfo;
30 class MCTargetOptions;
31 class MCTargetStreamer;
32 class StringRef;
33 class Target;
34 class Triple;
35 class raw_ostream;
36 class raw_pwrite_stream;
37 
41 
42 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
43  const MCRegisterInfo &MRI,
44  MCContext &Ctx);
45 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
46  const MCRegisterInfo &MRI,
47  const Triple &TT, StringRef CPU,
48  const MCTargetOptions &Options);
49 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
50  const MCRegisterInfo &MRI,
51  const Triple &TT, StringRef CPU,
52  const MCTargetOptions &Options);
53 
54 MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
55  uint8_t OSABI,
56  bool IsLittleEndian,
57  bool IsILP32);
58 
59 MCObjectWriter *createAArch64MachObjectWriter(raw_pwrite_stream &OS,
61  uint32_t CPUSubtype);
62 
63 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
64  formatted_raw_ostream &OS,
65  MCInstPrinter *InstPrint,
66  bool isVerboseAsm);
67 
68 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
69  const MCSubtargetInfo &STI);
70 
71 } // End llvm namespace
72 
73 // Defines symbolic names for AArch64 registers. This defines a mapping from
74 // register name to register number.
75 //
76 #define GET_REGINFO_ENUM
77 #include "AArch64GenRegisterInfo.inc"
78 
79 // Defines symbolic names for the AArch64 instructions.
80 //
81 #define GET_INSTRINFO_ENUM
82 #include "AArch64GenInstrInfo.inc"
83 
84 #define GET_SUBTARGETINFO_ENUM
85 #include "AArch64GenSubtargetInfo.inc"
86 
87 #endif
Target & getTheAArch64beTarget()
Target & getTheAArch64leTarget()
Target & getTheARM64Target()
unsigned const MachineRegisterInfo * MRI
MCObjectWriter * createAArch64MachObjectWriter(raw_pwrite_stream &OS, uint32_t CPUType, uint32_t CPUSubtype)
MCObjectWriter * createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool IsILP32)
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
CPUType
These values correspond to the CV_CPU_TYPE_e enumeration, and are documented here: https://msdn...
Definition: CodeView.h:73
static const char * Target
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)