14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
81 unsigned SrcReg,
bool isKill,
int FrameIdx,
84 bool &NonRI,
bool &SpillsVRS)
const;
86 unsigned DestReg,
int FrameIdx,
89 bool &NonRI,
bool &SpillsVRS)
const;
90 virtual void anchor();
105 unsigned OpIdx2)
const override;
125 unsigned *PredCost =
nullptr)
const override;
130 unsigned UseIdx)
const override;
132 SDNode *DefNode,
unsigned DefIdx,
133 SDNode *UseNode,
unsigned UseIdx)
const override {
134 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
140 unsigned DefIdx)
const override {
161 unsigned &SrcReg,
unsigned &DstReg,
162 unsigned &SubIdx)
const override;
169 unsigned &SrcOpIdx2)
const override;
179 bool AllowModify)
const override;
181 int *BytesRemoved =
nullptr)
const override;
185 int *BytesAdded =
nullptr)
const override;
189 unsigned,
unsigned,
int &,
int &,
int &)
const override;
191 const DebugLoc &DL,
unsigned DstReg,
193 unsigned FalseReg)
const override;
196 const DebugLoc &DL,
unsigned DestReg,
unsigned SrcReg,
197 bool KillSrc)
const override;
221 unsigned NumCycles,
unsigned ExtraPredCycles,
227 unsigned NumT,
unsigned ExtraT,
229 unsigned NumF,
unsigned ExtraF,
254 std::vector<MachineOperand> &Pred)
const override;
261 unsigned &SrcReg2,
int &
Mask,
int &
Value)
const override;
274 std::pair<unsigned, unsigned>
287 return Reg >= PPC::VF0 && Reg <= PPC::VF31;
290 return Reg >= PPC::V0 && Reg <= PPC::V31;
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool useMachineCombiner() const override
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
These are the various PPC970 execution unit pipelines.
bool isPredicable(MachineInstr &MI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static bool isVRRegister(unsigned Reg)
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
Provide an instruction scheduling machine model to CodeGen passes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Shift count to bypass PPC970 flags.
Reg
All possible values of the reg field in the ModR/M byte.
PPCInstrInfo(PPCSubtarget &STI)
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Instances of this class represent a single low-level machine instruction.
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineInstrBuilder & UseMI
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Represents one node in the SelectionDAG.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
static bool isVFRegister(unsigned Reg)
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
Representation of each machine instruction.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
LLVM Value Representation.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool expandPostRAPseudo(MachineInstr &MI) const override