LLVM  4.0.0
HexagonMCTargetDesc.cpp
Go to the documentation of this file.
1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Hexagon specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Hexagon.h"
15 #include "HexagonTargetStreamer.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDwarf.h"
24 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/Support/ELF.h"
33 #include <cassert>
34 #include <cstdint>
35 #include <new>
36 #include <string>
37 
38 using namespace llvm;
39 
40 #define GET_INSTRINFO_MC_DESC
41 #include "HexagonGenInstrInfo.inc"
42 
43 #define GET_SUBTARGETINFO_MC_DESC
44 #include "HexagonGenSubtargetInfo.inc"
45 
46 #define GET_REGINFO_MC_DESC
47 #include "HexagonGenRegisterInfo.inc"
48 
50  ("mno-compound",
51  cl::desc("Disable looking for compound instructions for Hexagon"));
52 
54  ("mno-pairing",
55  cl::desc("Disable looking for duplex instructions for Hexagon"));
56 
58  cl::desc("Build for Hexagon V4"));
59 
61  cl::desc("Build for Hexagon V5"));
62 
64  cl::desc("Build for Hexagon V55"));
65 
67  cl::desc("Build for Hexagon V60"));
68 
69 static StringRef DefaultArch = "hexagonv60";
70 
73  return "hexagonv4";
75  return "hexagonv5";
77  return "hexagonv55";
79  return "hexagonv60";
80  return "";
81 }
82 
85  if (!ArchV.empty() && !CPU.empty()) {
86  if (ArchV != CPU)
87  report_fatal_error("conflicting architectures specified.");
88  return CPU;
89  }
90  if (ArchV.empty()) {
91  if (CPU.empty())
92  CPU = DefaultArch;
93  return CPU;
94  }
95  return ArchV;
96 }
97 
99  MCInstrInfo *X = new MCInstrInfo();
100  InitHexagonMCInstrInfo(X);
101  return X;
102 }
103 
106  InitHexagonMCRegisterInfo(X, Hexagon::R31);
107  return X;
108 }
109 
110 static MCSubtargetInfo *
112  CPU = Hexagon_MC::selectHexagonCPU(TT, CPU);
113  return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
114 }
115 
116 namespace {
117 
118 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
119 public:
120  HexagonTargetAsmStreamer(MCStreamer &S,
121  formatted_raw_ostream &, bool,
122  MCInstPrinter &)
123  : HexagonTargetStreamer(S) {}
124 
125  void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
126  const MCInst &Inst, const MCSubtargetInfo &STI) override {
129  std::string Buffer;
130  {
131  raw_string_ostream TempStream(Buffer);
132  InstPrinter.printInst(&Inst, TempStream, "", STI);
133  }
134  StringRef Contents(Buffer);
135  auto PacketBundle = Contents.rsplit('\n');
136  auto HeadTail = PacketBundle.first.split('\n');
137  StringRef Separator = "\n";
138  StringRef Indent = "\t\t";
139  OS << "\t{\n";
140  while (!HeadTail.first.empty()) {
141  StringRef InstTxt;
142  auto Duplex = HeadTail.first.split('\v');
143  if (!Duplex.second.empty()) {
144  OS << Indent << Duplex.first << Separator;
145  InstTxt = Duplex.second;
146  } else if (!HeadTail.first.trim().startswith("immext")) {
147  InstTxt = Duplex.first;
148  }
149  if (!InstTxt.empty())
150  OS << Indent << InstTxt << Separator;
151  HeadTail = HeadTail.second.split('\n');
152  }
153  OS << "\t}" << PacketBundle.second;
154  }
155 };
156 
157 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
158 public:
159  HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
160  : HexagonTargetStreamer(S) {
161  auto Bits = STI.getFeatureBits();
162  unsigned Flags = 0;
163  if (Bits[Hexagon::ArchV60])
164  Flags = ELF::EF_HEXAGON_MACH_V60;
165  else if (Bits[Hexagon::ArchV55])
166  Flags = ELF::EF_HEXAGON_MACH_V55;
167  else if (Bits[Hexagon::ArchV5])
168  Flags = ELF::EF_HEXAGON_MACH_V5;
169  else if (Bits[Hexagon::ArchV4])
170  Flags = ELF::EF_HEXAGON_MACH_V4;
171  getStreamer().getAssembler().setELFHeaderEFlags(Flags);
172  }
173 
174  MCELFStreamer &getStreamer() {
175  return static_cast<MCELFStreamer &>(Streamer);
176  }
177 
178  void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
179  unsigned ByteAlignment,
180  unsigned AccessSize) override {
181  HexagonMCELFStreamer &HexagonELFStreamer =
182  static_cast<HexagonMCELFStreamer &>(getStreamer());
183  HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
184  AccessSize);
185  }
186 
187  void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
188  unsigned ByteAlignment,
189  unsigned AccessSize) override {
190  HexagonMCELFStreamer &HexagonELFStreamer =
191  static_cast<HexagonMCELFStreamer &>(getStreamer());
192  HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
193  Symbol, Size, ByteAlignment, AccessSize);
194  }
195 };
196 
197 } // end anonymous namespace
198 
200  const Triple &TT) {
201  MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
202 
203  // VirtualFP = (R30 + #0).
204  MCCFIInstruction Inst =
205  MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
206  MAI->addInitialFrameState(Inst);
207 
208  return MAI;
209 }
210 
212  unsigned SyntaxVariant,
213  const MCAsmInfo &MAI,
214  const MCInstrInfo &MII,
215  const MCRegisterInfo &MRI) {
216  if (SyntaxVariant == 0)
217  return (new HexagonInstPrinter(MAI, MII, MRI));
218  else
219  return nullptr;
220 }
221 
224  MCInstPrinter *InstPrint,
225  bool IsVerboseAsm) {
226  return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint);
227 }
228 
231  MCCodeEmitter *Emitter, bool RelaxAll) {
232  return createHexagonELFStreamer(Context, MAB, OS, Emitter);
233 }
234 
235 static MCTargetStreamer *
237  return new HexagonTargetELFStreamer(S, STI);
238 }
239 
240 // Force static initialization.
241 extern "C" void LLVMInitializeHexagonTargetMC() {
242  // Register the MC asm info.
244 
245  // Register the MC instruction info.
248 
249  // Register the MC register info.
252 
253  // Register the MC subtarget info.
256 
257  // Register the MC Code Emitter
260 
261  // Register the asm backend
264 
265  // Register the obj streamer
267 
268  // Register the asm streamer
271 
272  // Register the MC Inst Printer
275 
278 }
static cl::opt< bool > HexagonV55ArchVariant("mv55", cl::Hidden, cl::init(false), cl::desc("Build for Hexagon V55"))
static cl::opt< bool > HexagonV5ArchVariant("mv5", cl::Hidden, cl::init(false), cl::desc("Build for Hexagon V5"))
LLVMContext & Context
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI)=0
Print the specified MCInst to the specified raw_ostream.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool IsVerboseAsm)
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
static MCRegisterInfo * createHexagonMCRegisterInfo(const Triple &TT)
Target specific streamer interface.
Definition: MCStreamer.h:73
StringRef selectHexagonCPU(const Triple &TT, StringRef CPU)
bool isBundle(MCInst const &MCI)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
void LLVMInitializeHexagonTargetMC()
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &MCT)
static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
struct fuzzer::@269 Flags
#define HEXAGON_PACKET_SIZE
Definition: Hexagon.h:33
static cl::opt< bool > HexagonV4ArchVariant("mv4", cl::Hidden, cl::init(false), cl::desc("Build for Hexagon V4"))
Context object for machine code objects.
Definition: MCContext.h:51
static StringRef DefaultArch
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:565
MCInstrInfo * createHexagonMCInstrInfo()
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
Streaming machine code generation interface.
Definition: MCStreamer.h:161
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:369
static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
cl::opt< bool > HexagonDisableCompound
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...
static cl::opt< bool > HexagonV60ArchVariant("mv60", cl::Hidden, cl::init(false), cl::desc("Build for Hexagon V60"))
void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)
static const char * Separator
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:716
MCStreamer * createHexagonELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *CE)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:130
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
static StringRef HexagonGetArchVariant()
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:41
static MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
MCSubtargetInfo - Generic base class for all target subtargets.
size_t bundleSize(MCInst const &MCI)
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
An abstract base class for streams implementations that also support a pwrite operation.
Definition: raw_ostream.h:333
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
cl::opt< bool > RelaxAll("mc-relax-all", cl::desc("When used with filetype=obj, ""relax all fixups in the emitted object file"))
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
MCAsmBackend * createHexagonAsmBackend(Target const &T, MCRegisterInfo const &, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll)
Target & getTheHexagonTarget()
cl::opt< bool > HexagonDisableDuplex
void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, unsigned AccessSize)