LLVM  4.0.0
PPCTargetTransformInfo.cpp
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1 //===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "PPCTargetTransformInfo.h"
14 #include "llvm/Support/Debug.h"
15 #include "llvm/Target/CostTable.h"
17 using namespace llvm;
18 
19 #define DEBUG_TYPE "ppctti"
20 
21 static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
22 cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
23 
24 // This is currently only used for the data prefetch pass which is only enabled
25 // for BG/Q by default.
26 static cl::opt<unsigned>
27 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
28  cl::desc("The loop prefetch cache line size"));
29 
30 //===----------------------------------------------------------------------===//
31 //
32 // PPC cost model.
33 //
34 //===----------------------------------------------------------------------===//
35 
37 PPCTTIImpl::getPopcntSupport(unsigned TyWidth) {
38  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
39  if (ST->hasPOPCNTD() != PPCSubtarget::POPCNTD_Unavailable && TyWidth <= 64)
40  return ST->hasPOPCNTD() == PPCSubtarget::POPCNTD_Slow ?
42  return TTI::PSK_Software;
43 }
44 
45 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
47  return BaseT::getIntImmCost(Imm, Ty);
48 
49  assert(Ty->isIntegerTy());
50 
51  unsigned BitSize = Ty->getPrimitiveSizeInBits();
52  if (BitSize == 0)
53  return ~0U;
54 
55  if (Imm == 0)
56  return TTI::TCC_Free;
57 
58  if (Imm.getBitWidth() <= 64) {
59  if (isInt<16>(Imm.getSExtValue()))
60  return TTI::TCC_Basic;
61 
62  if (isInt<32>(Imm.getSExtValue())) {
63  // A constant that can be materialized using lis.
64  if ((Imm.getZExtValue() & 0xFFFF) == 0)
65  return TTI::TCC_Basic;
66 
67  return 2 * TTI::TCC_Basic;
68  }
69  }
70 
71  return 4 * TTI::TCC_Basic;
72 }
73 
74 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
75  Type *Ty) {
77  return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
78 
79  assert(Ty->isIntegerTy());
80 
81  unsigned BitSize = Ty->getPrimitiveSizeInBits();
82  if (BitSize == 0)
83  return ~0U;
84 
85  switch (IID) {
86  default:
87  return TTI::TCC_Free;
88  case Intrinsic::sadd_with_overflow:
89  case Intrinsic::uadd_with_overflow:
90  case Intrinsic::ssub_with_overflow:
91  case Intrinsic::usub_with_overflow:
92  if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue()))
93  return TTI::TCC_Free;
94  break;
95  case Intrinsic::experimental_stackmap:
96  if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
97  return TTI::TCC_Free;
98  break;
99  case Intrinsic::experimental_patchpoint_void:
100  case Intrinsic::experimental_patchpoint_i64:
101  if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
102  return TTI::TCC_Free;
103  break;
104  }
105  return PPCTTIImpl::getIntImmCost(Imm, Ty);
106 }
107 
108 int PPCTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
109  Type *Ty) {
111  return BaseT::getIntImmCost(Opcode, Idx, Imm, Ty);
112 
113  assert(Ty->isIntegerTy());
114 
115  unsigned BitSize = Ty->getPrimitiveSizeInBits();
116  if (BitSize == 0)
117  return ~0U;
118 
119  unsigned ImmIdx = ~0U;
120  bool ShiftedFree = false, RunFree = false, UnsignedFree = false,
121  ZeroFree = false;
122  switch (Opcode) {
123  default:
124  return TTI::TCC_Free;
125  case Instruction::GetElementPtr:
126  // Always hoist the base address of a GetElementPtr. This prevents the
127  // creation of new constants for every base constant that gets constant
128  // folded with the offset.
129  if (Idx == 0)
130  return 2 * TTI::TCC_Basic;
131  return TTI::TCC_Free;
132  case Instruction::And:
133  RunFree = true; // (for the rotate-and-mask instructions)
135  case Instruction::Add:
136  case Instruction::Or:
137  case Instruction::Xor:
138  ShiftedFree = true;
140  case Instruction::Sub:
141  case Instruction::Mul:
142  case Instruction::Shl:
143  case Instruction::LShr:
144  case Instruction::AShr:
145  ImmIdx = 1;
146  break;
147  case Instruction::ICmp:
148  UnsignedFree = true;
149  ImmIdx = 1;
150  // Zero comparisons can use record-form instructions.
152  case Instruction::Select:
153  ZeroFree = true;
154  break;
155  case Instruction::PHI:
156  case Instruction::Call:
157  case Instruction::Ret:
158  case Instruction::Load:
159  case Instruction::Store:
160  break;
161  }
162 
163  if (ZeroFree && Imm == 0)
164  return TTI::TCC_Free;
165 
166  if (Idx == ImmIdx && Imm.getBitWidth() <= 64) {
167  if (isInt<16>(Imm.getSExtValue()))
168  return TTI::TCC_Free;
169 
170  if (RunFree) {
171  if (Imm.getBitWidth() <= 32 &&
172  (isShiftedMask_32(Imm.getZExtValue()) ||
174  return TTI::TCC_Free;
175 
176  if (ST->isPPC64() &&
177  (isShiftedMask_64(Imm.getZExtValue()) ||
179  return TTI::TCC_Free;
180  }
181 
182  if (UnsignedFree && isUInt<16>(Imm.getZExtValue()))
183  return TTI::TCC_Free;
184 
185  if (ShiftedFree && (Imm.getZExtValue() & 0xFFFF) == 0)
186  return TTI::TCC_Free;
187  }
188 
189  return PPCTTIImpl::getIntImmCost(Imm, Ty);
190 }
191 
194  if (ST->getDarwinDirective() == PPC::DIR_A2) {
195  // The A2 is in-order with a deep pipeline, and concatenation unrolling
196  // helps expose latency-hiding opportunities to the instruction scheduler.
197  UP.Partial = UP.Runtime = true;
198 
199  // We unroll a lot on the A2 (hundreds of instructions), and the benefits
200  // often outweigh the cost of a division to compute the trip count.
201  UP.AllowExpensiveTripCount = true;
202  }
203 
205 }
206 
207 bool PPCTTIImpl::enableAggressiveInterleaving(bool LoopHasReductions) {
208  // On the A2, always unroll aggressively. For QPX unaligned loads, we depend
209  // on combining the loads generated for consecutive accesses, and failure to
210  // do so is particularly expensive. This makes it much more likely (compared
211  // to only using concatenation unrolling).
212  if (ST->getDarwinDirective() == PPC::DIR_A2)
213  return true;
214 
215  return LoopHasReductions;
216 }
217 
219  return true;
220 }
221 
222 unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) {
223  if (Vector && !ST->hasAltivec() && !ST->hasQPX())
224  return 0;
225  return ST->hasVSX() ? 64 : 32;
226 }
227 
228 unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) {
229  if (Vector) {
230  if (ST->hasQPX()) return 256;
231  if (ST->hasAltivec()) return 128;
232  return 0;
233  }
234 
235  if (ST->isPPC64())
236  return 64;
237  return 32;
238 
239 }
240 
242  // This is currently only used for the data prefetch pass which is only
243  // enabled for BG/Q by default.
244  return CacheLineSize;
245 }
246 
248  // This seems like a reasonable default for the BG/Q (this pass is enabled, by
249  // default, only on the BG/Q).
250  return 300;
251 }
252 
253 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
254  unsigned Directive = ST->getDarwinDirective();
255  // The 440 has no SIMD support, but floating-point instructions
256  // have a 5-cycle latency, so unroll by 5x for latency hiding.
257  if (Directive == PPC::DIR_440)
258  return 5;
259 
260  // The A2 has no SIMD support, but floating-point instructions
261  // have a 6-cycle latency, so unroll by 6x for latency hiding.
262  if (Directive == PPC::DIR_A2)
263  return 6;
264 
265  // FIXME: For lack of any better information, do no harm...
266  if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
267  return 1;
268 
269  // For P7 and P8, floating-point instructions have a 6-cycle latency and
270  // there are two execution units, so unroll by 12x for latency hiding.
271  // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
272  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
273  Directive == PPC::DIR_PWR9)
274  return 12;
275 
276  // For most things, modern systems have two execution units (and
277  // out-of-order execution).
278  return 2;
279 }
280 
282  unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
285  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
286 
287  // Fallback to the default implementation.
288  return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
289  Opd1PropInfo, Opd2PropInfo);
290 }
291 
293  Type *SubTp) {
294  // Legalize the type.
295  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
296 
297  // PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
298  // (at least in the sense that there need only be one non-loop-invariant
299  // instruction). We need one such shuffle instruction for each actual
300  // register (this is not true for arbitrary shuffles, but is true for the
301  // structured types of shuffles covered by TTI::ShuffleKind).
302  return LT.first;
303 }
304 
305 int PPCTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
306  assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode");
307 
308  return BaseT::getCastInstrCost(Opcode, Dst, Src);
309 }
310 
311 int PPCTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) {
312  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
313 }
314 
315 int PPCTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
316  assert(Val->isVectorTy() && "This must be a vector type");
317 
318  int ISD = TLI->InstructionOpcodeToISD(Opcode);
319  assert(ISD && "Invalid opcode");
320 
321  if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) {
322  // Double-precision scalars are already located in index #0.
323  if (Index == 0)
324  return 0;
325 
326  return BaseT::getVectorInstrCost(Opcode, Val, Index);
327  } else if (ST->hasQPX() && Val->getScalarType()->isFloatingPointTy()) {
328  // Floating point scalars are already located in index #0.
329  if (Index == 0)
330  return 0;
331 
332  return BaseT::getVectorInstrCost(Opcode, Val, Index);
333  }
334 
335  // Estimated cost of a load-hit-store delay. This was obtained
336  // experimentally as a minimum needed to prevent unprofitable
337  // vectorization for the paq8p benchmark. It may need to be
338  // raised further if other unprofitable cases remain.
339  unsigned LHSPenalty = 2;
340  if (ISD == ISD::INSERT_VECTOR_ELT)
341  LHSPenalty += 7;
342 
343  // Vector element insert/extract with Altivec is very expensive,
344  // because they require store and reload with the attendant
345  // processor stall for load-hit-store. Until VSX is available,
346  // these need to be estimated as very costly.
347  if (ISD == ISD::EXTRACT_VECTOR_ELT ||
348  ISD == ISD::INSERT_VECTOR_ELT)
349  return LHSPenalty + BaseT::getVectorInstrCost(Opcode, Val, Index);
350 
351  return BaseT::getVectorInstrCost(Opcode, Val, Index);
352 }
353 
354 int PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
355  unsigned AddressSpace) {
356  // Legalize the type.
357  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
358  assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
359  "Invalid Opcode");
360 
361  int Cost = BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
362 
363  bool IsAltivecType = ST->hasAltivec() &&
364  (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
365  LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
366  bool IsVSXType = ST->hasVSX() &&
367  (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
368  bool IsQPXType = ST->hasQPX() &&
369  (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
370 
371  // VSX has 32b/64b load instructions. Legalization can handle loading of
372  // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and
373  // PPCTargetLowering can't compute the cost appropriately. So here we
374  // explicitly check this case.
375  unsigned MemBytes = Src->getPrimitiveSizeInBits();
376  if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType &&
377  (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32)))
378  return 1;
379 
380  // Aligned loads and stores are easy.
381  unsigned SrcBytes = LT.second.getStoreSize();
382  if (!SrcBytes || !Alignment || Alignment >= SrcBytes)
383  return Cost;
384 
385  // If we can use the permutation-based load sequence, then this is also
386  // relatively cheap (not counting loop-invariant instructions): one load plus
387  // one permute (the last load in a series has extra cost, but we're
388  // neglecting that here). Note that on the P7, we could do unaligned loads
389  // for Altivec types using the VSX instructions, but that's more expensive
390  // than using the permutation-based load sequence. On the P8, that's no
391  // longer true.
392  if (Opcode == Instruction::Load &&
393  ((!ST->hasP8Vector() && IsAltivecType) || IsQPXType) &&
394  Alignment >= LT.second.getScalarType().getStoreSize())
395  return Cost + LT.first; // Add the cost of the permutations.
396 
397  // For VSX, we can do unaligned loads and stores on Altivec/VSX types. On the
398  // P7, unaligned vector loads are more expensive than the permutation-based
399  // load sequence, so that might be used instead, but regardless, the net cost
400  // is about the same (not counting loop-invariant instructions).
401  if (IsVSXType || (ST->hasVSX() && IsAltivecType))
402  return Cost;
403 
404  // PPC in general does not support unaligned loads and stores. They'll need
405  // to be decomposed based on the alignment factor.
406 
407  // Add the cost of each scalar load or store.
408  Cost += LT.first*(SrcBytes/Alignment-1);
409 
410  // For a vector type, there is also scalarization overhead (only for
411  // stores, loads are expanded using the vector-load + permutation sequence,
412  // which is much less expensive).
413  if (Src->isVectorTy() && Opcode == Instruction::Store)
414  for (int i = 0, e = Src->getVectorNumElements(); i < e; ++i)
415  Cost += getVectorInstrCost(Instruction::ExtractElement, Src, i);
416 
417  return Cost;
418 }
419 
420 int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
421  unsigned Factor,
422  ArrayRef<unsigned> Indices,
423  unsigned Alignment,
424  unsigned AddressSpace) {
425  assert(isa<VectorType>(VecTy) &&
426  "Expect a vector type for interleaved memory op");
427 
428  // Legalize the type.
429  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, VecTy);
430 
431  // Firstly, the cost of load/store operation.
432  int Cost = getMemoryOpCost(Opcode, VecTy, Alignment, AddressSpace);
433 
434  // PPC, for both Altivec/VSX and QPX, support cheap arbitrary permutations
435  // (at least in the sense that there need only be one non-loop-invariant
436  // instruction). For each result vector, we need one shuffle per incoming
437  // vector (except that the first shuffle can take two incoming vectors
438  // because it does not need to take itself).
439  Cost += Factor*(LT.first-1);
440 
441  return Cost;
442 }
443 
MachineLoop * L
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
Definition: BasicTTIImpl.h:536
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1309
size_t i
Cost tables and simple lookup functions.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:148
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:271
bool hasAltivec() const
Definition: PPCSubtarget.h:239
unsigned getIntImmCost(const APInt &Imm, Type *Ty)
int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
bool hasQPX() const
Definition: PPCSubtarget.h:241
int getIntImmCost(const APInt &Imm, Type *Ty)
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
Definition: BasicTTIImpl.h:363
This file a TargetTransformInfo::Concept conforming object specific to the PPC target machine...
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
bool AllowExpensiveTripCount
Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...
unsigned getMaxInterleaveFactor(unsigned VF)
static cl::opt< bool > DisablePPCConstHoist("disable-ppc-constant-hoisting", cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden)
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
PopcntSupportKind
Flags indicating the kind of support for population count.
static cl::opt< unsigned > CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64), cl::desc("The loop prefetch cache line size"))
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:160
Type * getScalarType() const LLVM_READONLY
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.cpp:44
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
Definition: BasicTTIImpl.h:490
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:399
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:219
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1321
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:279
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1947
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1952
POPCNTDKind hasPOPCNTD() const
Definition: PPCSubtarget.h:284
Expected to fold away in lowering.
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1255
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
unsigned getNumberOfRegisters(bool Vector)
OperandValueProperties
Additional properties of an operand's values.
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:274
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:285
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
Definition: BasicTTIImpl.h:306
AddressSpace
Definition: NVPTXBaseInfo.h:22
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
bool enableAggressiveInterleaving(bool LoopHasReductions)
Class for arbitrary precision integers.
Definition: APInt.h:77
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:195
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:438
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1942
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
constexpr bool isShiftedMask_64(uint64_t Value)
isShiftedMask_64 - This function returns true if the argument contains a non-empty sequence of ones w...
Definition: MathExtras.h:393
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:368
Parameters that control the generic loop unrolling transformation.
bool hasVSX() const
Definition: PPCSubtarget.h:242
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:529
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:312
bool hasP8Vector() const
Definition: PPCSubtarget.h:243
const unsigned Kind
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
The cost of a typical 'add' instruction.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:108
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:168
unsigned getRegisterBitWidth(bool Vector)
constexpr bool isShiftedMask_32(uint32_t Value)
isShiftedMask_32 - This function returns true if the argument contains a non-empty sequence of ones w...
Definition: MathExtras.h:387
OperandValueKind
Additional information about an operand's possible values.
This pass exposes codegen information to IR-level passes.
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
Definition: BasicTTIImpl.h:231
This file describes how to lower LLVM code to machine code.
ShuffleKind
The various kinds of shuffle patterns for vector queries.