44 #define DEBUG_TYPE "mips-lower"
46 STATISTIC(NumTailCalls,
"Number of tail calls");
54 cl::desc(
"MIPS: Don't trap on integer division by zero."),
58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
81 unsigned Flag)
const {
87 unsigned Flag)
const {
93 unsigned Flag)
const {
99 unsigned Flag)
const {
105 unsigned Flag)
const {
490 unsigned LO = (Ty ==
MVT::i32) ? Mips::LO0 : Mips::LO0_64;
491 unsigned HI = (Ty ==
MVT::i32) ? Mips::HI0 : Mips::HI0_64;
554 "Illegal Condition Code");
695 return DAG.
getNode(Opc,
SDLoc(N), ValueIfFalse.getValueType(),
696 ValueIfFalse, FCC, ValueIfTrue, Glue);
709 unsigned ShiftRightOpc = ShiftRight.
getOpcode();
717 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.
getOperand(1))))
721 uint64_t SMPos, SMSize;
724 if (!(CN = dyn_cast<ConstantSDNode>(
Mask)) ||
752 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
759 if (!(CN = dyn_cast<ConstantSDNode>(And0.
getOperand(1))) ||
767 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
772 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
779 if (!(CN = dyn_cast<ConstantSDNode>(Shl.
getOperand(1))))
787 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.
getSizeInBits()))
842 EVT WiderVT = cast<VTSDNode>(WiderAssertZext->
getOperand(1))->getVT();
844 if (NarrowerVT.
bitsLT(WiderVT)) {
957 bool Is64Bit,
bool IsMicroMips) {
966 TII.
get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
990 case Mips::ATOMIC_LOAD_ADD_I8:
991 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
992 case Mips::ATOMIC_LOAD_ADD_I16:
993 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
994 case Mips::ATOMIC_LOAD_ADD_I32:
995 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
996 case Mips::ATOMIC_LOAD_ADD_I64:
997 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
999 case Mips::ATOMIC_LOAD_AND_I8:
1000 return emitAtomicBinaryPartword(MI, BB, 1,
Mips::AND);
1001 case Mips::ATOMIC_LOAD_AND_I16:
1002 return emitAtomicBinaryPartword(MI, BB, 2,
Mips::AND);
1003 case Mips::ATOMIC_LOAD_AND_I32:
1004 return emitAtomicBinary(MI, BB, 4,
Mips::AND);
1005 case Mips::ATOMIC_LOAD_AND_I64:
1006 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
1008 case Mips::ATOMIC_LOAD_OR_I8:
1009 return emitAtomicBinaryPartword(MI, BB, 1,
Mips::OR);
1010 case Mips::ATOMIC_LOAD_OR_I16:
1011 return emitAtomicBinaryPartword(MI, BB, 2,
Mips::OR);
1012 case Mips::ATOMIC_LOAD_OR_I32:
1013 return emitAtomicBinary(MI, BB, 4,
Mips::OR);
1014 case Mips::ATOMIC_LOAD_OR_I64:
1015 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1017 case Mips::ATOMIC_LOAD_XOR_I8:
1018 return emitAtomicBinaryPartword(MI, BB, 1,
Mips::XOR);
1019 case Mips::ATOMIC_LOAD_XOR_I16:
1020 return emitAtomicBinaryPartword(MI, BB, 2,
Mips::XOR);
1021 case Mips::ATOMIC_LOAD_XOR_I32:
1022 return emitAtomicBinary(MI, BB, 4,
Mips::XOR);
1023 case Mips::ATOMIC_LOAD_XOR_I64:
1024 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1026 case Mips::ATOMIC_LOAD_NAND_I8:
1027 return emitAtomicBinaryPartword(MI, BB, 1, 0,
true);
1028 case Mips::ATOMIC_LOAD_NAND_I16:
1029 return emitAtomicBinaryPartword(MI, BB, 2, 0,
true);
1030 case Mips::ATOMIC_LOAD_NAND_I32:
1031 return emitAtomicBinary(MI, BB, 4, 0,
true);
1032 case Mips::ATOMIC_LOAD_NAND_I64:
1033 return emitAtomicBinary(MI, BB, 8, 0,
true);
1035 case Mips::ATOMIC_LOAD_SUB_I8:
1036 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1037 case Mips::ATOMIC_LOAD_SUB_I16:
1038 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1039 case Mips::ATOMIC_LOAD_SUB_I32:
1040 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1041 case Mips::ATOMIC_LOAD_SUB_I64:
1042 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1044 case Mips::ATOMIC_SWAP_I8:
1045 return emitAtomicBinaryPartword(MI, BB, 1, 0);
1046 case Mips::ATOMIC_SWAP_I16:
1047 return emitAtomicBinaryPartword(MI, BB, 2, 0);
1048 case Mips::ATOMIC_SWAP_I32:
1049 return emitAtomicBinary(MI, BB, 4, 0);
1050 case Mips::ATOMIC_SWAP_I64:
1051 return emitAtomicBinary(MI, BB, 8, 0);
1053 case Mips::ATOMIC_CMP_SWAP_I8:
1054 return emitAtomicCmpSwapPartword(MI, BB, 1);
1055 case Mips::ATOMIC_CMP_SWAP_I16:
1056 return emitAtomicCmpSwapPartword(MI, BB, 2);
1057 case Mips::ATOMIC_CMP_SWAP_I32:
1058 return emitAtomicCmpSwap(MI, BB, 4);
1059 case Mips::ATOMIC_CMP_SWAP_I64:
1060 return emitAtomicCmpSwap(MI, BB, 8);
1061 case Mips::PseudoSDIV:
1062 case Mips::PseudoUDIV:
1069 case Mips::SDIV_MM_Pseudo:
1070 case Mips::UDIV_MM_Pseudo:
1073 case Mips::DIV_MMR6:
1074 case Mips::DIVU_MMR6:
1075 case Mips::MOD_MMR6:
1076 case Mips::MODU_MMR6:
1078 case Mips::PseudoDSDIV:
1079 case Mips::PseudoDUDIV:
1085 case Mips::DDIV_MM64R6:
1086 case Mips::DDIVU_MM64R6:
1087 case Mips::DMOD_MM64R6:
1088 case Mips::DMODU_MM64R6:
1091 case Mips::SEL_D_MMR6:
1092 return emitSEL_D(MI, BB);
1094 case Mips::PseudoSELECT_I:
1095 case Mips::PseudoSELECT_I64:
1096 case Mips::PseudoSELECT_S:
1097 case Mips::PseudoSELECT_D32:
1098 case Mips::PseudoSELECT_D64:
1099 return emitPseudoSELECT(MI, BB,
false, Mips::BNE);
1100 case Mips::PseudoSELECTFP_F_I:
1101 case Mips::PseudoSELECTFP_F_I64:
1102 case Mips::PseudoSELECTFP_F_S:
1103 case Mips::PseudoSELECTFP_F_D32:
1104 case Mips::PseudoSELECTFP_F_D64:
1105 return emitPseudoSELECT(MI, BB,
true, Mips::BC1F);
1106 case Mips::PseudoSELECTFP_T_I:
1107 case Mips::PseudoSELECTFP_T_I64:
1108 case Mips::PseudoSELECTFP_T_S:
1109 case Mips::PseudoSELECTFP_T_D32:
1110 case Mips::PseudoSELECTFP_T_D64:
1111 return emitPseudoSELECT(MI, BB,
true, Mips::BC1T);
1122 assert((Size == 4 || Size == 8) &&
"Unsupported size for EmitAtomicBinary.");
1130 unsigned LL,
SC,
AND, NOR, ZERO, BEQ;
1138 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1139 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1141 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1142 : (ArePtrs64bit ? Mips::SC64 :
Mips::SC);
1154 ZERO = Mips::ZERO_64;
1198 }
else if (BinOpcode) {
1200 BuildMI(BB, DL, TII->
get(BinOpcode), StoreVal).addReg(OldVal).
addReg(Incr);
1214 unsigned SrcReg)
const {
1219 BuildMI(BB, DL, TII->
get(Mips::SEB), DstReg).addReg(SrcReg);
1224 BuildMI(BB, DL, TII->
get(Mips::SEH), DstReg).addReg(SrcReg);
1234 int64_t ShiftImm = 32 - (Size * 8);
1236 BuildMI(BB, DL, TII->
get(Mips::SLL), ScrReg).addReg(SrcReg).
addImm(ShiftImm);
1245 assert((Size == 1 || Size == 2) &&
1246 "Unsupported size for EmitAtomicBinaryPartial.");
1285 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1287 : (ArePtrs64bit ? Mips::SC64 :
Mips::SC);
1320 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1325 BuildMI(BB, DL, TII->
get(Mips::ANDi), PtrLSB2)
1326 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).
addImm(3);
1332 .addReg(PtrLSB2).
addImm((Size == 1) ? 3 : 2);
1335 BuildMI(BB, DL, TII->
get(Mips::ORi), MaskUpper)
1336 .addReg(Mips::ZERO).
addImm(MaskImm);
1338 .addReg(MaskUpper).
addReg(ShiftAmt);
1339 BuildMI(BB, DL, TII->
get(Mips::NOR), Mask2).addReg(Mips::ZERO).
addReg(Mask);
1340 BuildMI(BB, DL, TII->
get(Mips::SLLV), Incr2).addReg(Incr).
addReg(ShiftAmt);
1368 BuildMI(BB, DL, TII->
get(Mips::NOR), BinOpRes)
1369 .addReg(Mips::ZERO).
addReg(AndRes);
1371 }
else if (BinOpcode) {
1374 BuildMI(BB, DL, TII->
get(BinOpcode), BinOpRes).addReg(OldVal).
addReg(Incr2);
1382 .addReg(OldVal).
addReg(Mask2);
1384 .addReg(MaskedOldVal0).
addReg(NewVal);
1397 .addReg(OldVal).
addReg(Mask);
1398 BuildMI(BB, DL, TII->
get(Mips::SRLV), SrlRes)
1399 .addReg(MaskedOldVal1).
addReg(ShiftAmt);
1400 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1409 unsigned Size)
const {
1410 assert((Size == 4 || Size == 8) &&
"Unsupported size for EmitAtomicCmpSwap.");
1418 unsigned LL,
SC, ZERO, BNE, BEQ;
1426 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1427 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1429 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1430 : (ArePtrs64bit ? Mips::SC64 :
Mips::SC);
1439 ZERO = Mips::ZERO_64;
1457 MF->
insert(It, loop1MBB);
1458 MF->
insert(It, loop2MBB);
1499 assert((Size == 1 || Size == 2) &&
1500 "Unsupported size for EmitAtomicCmpSwapPartial.");
1540 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1542 : (ArePtrs64bit ? Mips::SC64 :
Mips::SC);
1552 MF->
insert(It, loop1MBB);
1553 MF->
insert(It, loop2MBB);
1583 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1584 BuildMI(BB, DL, TII->
get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1587 .addReg(Ptr).
addReg(MaskLSB2);
1588 BuildMI(BB, DL, TII->
get(Mips::ANDi), PtrLSB2)
1589 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).
addImm(3);
1595 .addReg(PtrLSB2).
addImm((Size == 1) ? 3 : 2);
1598 BuildMI(BB, DL, TII->
get(Mips::ORi), MaskUpper)
1599 .addReg(Mips::ZERO).
addImm(MaskImm);
1601 .addReg(MaskUpper).
addReg(ShiftAmt);
1602 BuildMI(BB, DL, TII->
get(Mips::NOR), Mask2).addReg(Mips::ZERO).
addReg(Mask);
1603 BuildMI(BB, DL, TII->
get(Mips::ANDi), MaskedCmpVal)
1604 .addReg(CmpVal).
addImm(MaskImm);
1605 BuildMI(BB, DL, TII->
get(Mips::SLLV), ShiftedCmpVal)
1606 .addReg(MaskedCmpVal).
addReg(ShiftAmt);
1607 BuildMI(BB, DL, TII->
get(Mips::ANDi), MaskedNewVal)
1608 .addReg(NewVal).
addImm(MaskImm);
1609 BuildMI(BB, DL, TII->
get(Mips::SLLV), ShiftedNewVal)
1610 .addReg(MaskedNewVal).
addReg(ShiftAmt);
1618 BuildMI(BB, DL, TII->
get(Mips::AND), MaskedOldVal0)
1619 .addReg(OldVal).
addReg(Mask);
1621 .addReg(MaskedOldVal0).
addReg(ShiftedCmpVal).
addMBB(sinkMBB);
1629 BuildMI(BB, DL, TII->
get(Mips::AND), MaskedOldVal1)
1630 .addReg(OldVal).
addReg(Mask2);
1632 .addReg(MaskedOldVal1).
addReg(ShiftedNewVal);
1643 BuildMI(BB, DL, TII->
get(Mips::SRLV), SrlRes)
1644 .addReg(MaskedOldVal0).
addReg(ShiftAmt);
1645 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1662 const auto &FGR64RegClass = TRI->
getRegClass(Mips::FGR64RegClassID);
1666 BuildMI(*BB, II, DL, TII->
get(Mips::SUBREG_TO_REG), Fc2)
1699 FCC0, Dest, CondRes);
1721 "Floating point operand expected.");
1760 if (GV->hasLocalLinkage())
1770 N,
SDLoc(N), Ty, DAG,
1818 Entry.Node = Argument;
1820 Args.push_back(Entry);
1825 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
1922 const Value *SV = cast<SrcValueSDNode>(Node->
getOperand(2))->getValue();
1938 assert(((Align & (Align-1)) == 0) &&
"Expected Align to be a power of 2");
1950 unsigned ArgSizeInBytes =
1966 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1975 bool HasExtractInsert) {
1994 if (HasExtractInsert) {
2022 bool HasExtractInsert) {
2033 if (HasExtractInsert) {
2039 if (WidthX > WidthY)
2041 else if (WidthY > WidthX)
2060 if (WidthX > WidthY)
2062 else if (WidthY > WidthX)
2083 "Frame address can only be determined for current frame.");
2101 "Return address can be determined only for current frame.");
2106 unsigned RA =
ABI.
IsN64() ? Mips::RA_64 : Mips::RA;
2132 unsigned OffsetReg =
ABI.
IsN64() ? Mips::V1_64 : Mips::V1;
2133 unsigned AddrReg =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
2218 IsSRA ? Ext : DAG.
getConstant(0, DL, VT), ShiftRightHi);
2250 if ((LD->
getAlignment() >= MemVT.getSizeInBits() / 8) ||
2307 SDValue Chain,
unsigned Offset) {
2423 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2424 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2436 else if (ArgFlags.
isZExt())
2448 else if (ArgFlags.
isZExt())
2459 bool AllocateFloatsInIntReg = State.
isVarArg() || ValNo > 1 ||
2462 bool isI64 = (ValVT ==
MVT::i32 && OrigAlign == 8);
2468 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2471 }
else if (ValVT ==
MVT::f64 && AllocateFloatsInIntReg) {
2475 if (Reg == Mips::A1 || Reg == Mips::A3)
2489 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2509 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2511 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2517 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2519 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2526 #include "MipsGenCallingConv.inc"
2534 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2535 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2538 SDValue MipsTargetLowering::passArgOnStack(
SDValue StackPtr,
unsigned Offset,
2540 const SDLoc &DL,
bool IsTailCall,
2558 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2559 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
2572 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2573 unsigned GPReg =
ABI.
IsN64() ? Mips::GP_64 : Mips::GP;
2575 RegsToPass.push_back(std::make_pair(GPReg,
getGlobalReg(CLI.
DAG, Ty)));
2584 for (
unsigned i = 0, e = RegsToPass.size();
i != e; ++
i) {
2586 RegsToPass[i].second, InFlag);
2592 for (
unsigned i = 0, e = RegsToPass.size();
i != e; ++
i)
2594 RegsToPass[i].second.getValueType()));
2600 assert(Mask &&
"Missing call preserved mask for calling convention");
2604 Function *
F =
G->getGlobal()->getParent()->getFunction(Sym);
2651 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2655 bool InternalLinkage =
false;
2657 IsTailCall = isEligibleForTailCallOptimization(
2660 InternalLinkage =
G->getGlobal()->hasInternalLinkage();
2661 IsTailCall &= (InternalLinkage ||
G->getGlobal()->hasLocalLinkage() ||
2662 G->getGlobal()->hasPrivateLinkage() ||
2663 G->getGlobal()->hasHiddenVisibility() ||
2664 G->getGlobal()->hasProtectedVisibility());
2669 "site marked musttail");
2678 NextStackOffset =
alignTo(NextStackOffset, StackAlignment);
2688 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2691 CCInfo.rewindByValRegsInfo();
2694 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
2699 bool UseUpperBits =
false;
2703 unsigned FirstByValReg, LastByValReg;
2704 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2705 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2708 "ByVal args of size 0 should have been ignored by front-end.");
2709 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2711 "Do not tail-call optimize if there is a byval argument.");
2712 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2715 CCInfo.nextInRegsParam();
2738 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2739 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2748 UseUpperBits =
true;
2754 UseUpperBits =
true;
2760 UseUpperBits =
true;
2778 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Arg));
2788 Chain, Arg, DL, IsTailCall, DAG));
2793 if (!MemOpChains.
empty())
2799 bool IsPICCall = (
ABI.
IsN64() || IsPIC);
2803 bool GlobalOrExternal =
false, IsCallReloc =
false;
2810 if (InternalLinkage)
2826 GlobalOrExternal =
true;
2829 const char *Sym = S->getSymbol();
2845 GlobalOrExternal =
true;
2851 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2852 IsCallReloc, CLI, Callee, Chain);
2869 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2875 SDValue MipsTargetLowering::LowerCallResult(
2887 for (
unsigned i = 0;
i != RVLocs.
size(); ++
i) {
2892 RVLocs[
i].getLocVT(), InFlag);
2897 unsigned ValSizeInBits = Ins[
i].ArgVT.getSizeInBits();
2998 SDValue MipsTargetLowering::LowerFormalArguments(
3009 std::vector<SDValue> OutChains;
3021 "Functions with the interrupt attribute cannot have arguments!");
3023 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3025 CCInfo.getInRegsParamsCount() > 0);
3027 unsigned CurArgIdx = 0;
3028 CCInfo.rewindByValRegsInfo();
3030 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
3032 if (Ins[
i].isOrigArg()) {
3033 std::advance(FuncArg, Ins[
i].getOrigArgIndex() - CurArgIdx);
3034 CurArgIdx = Ins[
i].getOrigArgIndex();
3041 assert(Ins[
i].isOrigArg() &&
"Byval arguments cannot be implicit");
3042 unsigned FirstByValReg, LastByValReg;
3043 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3044 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3047 "ByVal args of size 0 should have been ignored by front-end.");
3048 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3049 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3050 FirstByValReg, LastByValReg, VA, CCInfo);
3051 CCInfo.nextInRegsParam();
3082 ArgValue, ArgValue2);
3108 LocVT, DL, Chain, FIN,
3110 OutChains.push_back(ArgValue.
getValue(1));
3118 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
3136 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3140 if (!OutChains.empty()) {
3141 OutChains.push_back(Chain);
3158 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3159 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3163 MipsTargetLowering::shouldSignExtendTypeInLibCall(
EVT Type,
bool IsSigned)
const {
3205 for (
unsigned i = 0;
i != RVLocs.
size(); ++
i) {
3209 bool UseUpperBits =
false;
3220 UseUpperBits =
true;
3226 UseUpperBits =
true;
3232 UseUpperBits =
true;
3240 unsigned ValSizeInBits = Outs[
i].ArgVT.getSizeInBits();
3266 unsigned V0 =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
3281 return LowerInterruptReturn(RetOps, DL, DAG);
3294 MipsTargetLowering::getConstraintType(
StringRef Constraint)
const {
3306 if (Constraint.
size() == 1) {
3307 switch (Constraint[0]) {
3321 if (Constraint ==
"ZC")
3331 MipsTargetLowering::getSingleConstraintMatchWeight(
3332 AsmOperandInfo &
info,
const char *constraint)
const {
3334 Value *CallOperandVal = info.CallOperandVal;
3337 if (!CallOperandVal)
3339 Type *type = CallOperandVal->
getType();
3341 switch (*constraint) {
3370 if (isa<ConstantInt>(CallOperandVal))
3385 unsigned long long &Reg) {
3386 if (C.
front() !=
'{' || C.
back() !=
'}')
3387 return std::make_pair(
false,
false);
3397 return std::make_pair(
true,
false);
3404 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3410 unsigned long long Reg;
3415 return std::make_pair(0U,
nullptr);
3417 if ((Prefix ==
"hi" || Prefix ==
"lo")) {
3420 return std::make_pair(0U,
nullptr);
3423 Mips::HI32RegClassID : Mips::LO32RegClassID);
3424 return std::make_pair(*(RC->
begin()), RC);
3430 return std::make_pair(0U,
nullptr);
3433 .Case(
"$msair", Mips::MSAIR)
3434 .
Case(
"$msacsr", Mips::MSACSR)
3435 .
Case(
"$msaaccess", Mips::MSAAccess)
3436 .
Case(
"$msasave", Mips::MSASave)
3437 .
Case(
"$msamodify", Mips::MSAModify)
3438 .
Case(
"$msarequest", Mips::MSARequest)
3439 .
Case(
"$msamap", Mips::MSAMap)
3440 .
Case(
"$msaunmap", Mips::MSAUnmap)
3444 return std::make_pair(0U,
nullptr);
3447 return std::make_pair(Reg, RC);
3451 return std::make_pair(0U,
nullptr);
3453 if (Prefix ==
"$f") {
3461 if (RC == &Mips::AFGR64RegClass) {
3465 }
else if (Prefix ==
"$fcc")
3467 else if (Prefix ==
"$w") {
3474 assert(Reg < RC->getNumRegs());
3475 return std::make_pair(*(RC->
begin() +
Reg), RC);
3481 std::pair<unsigned, const TargetRegisterClass *>
3485 if (Constraint.
size() == 1) {
3486 switch (Constraint[0]) {
3492 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3493 return std::make_pair(0U, &Mips::GPR32RegClass);
3496 return std::make_pair(0U, &Mips::GPR32RegClass);
3498 return std::make_pair(0U, &Mips::GPR64RegClass);
3500 return std::make_pair(0U,
nullptr);
3503 return std::make_pair(0U, &Mips::MSA128BRegClass);
3505 return std::make_pair(0U, &Mips::MSA128HRegClass);
3507 return std::make_pair(0U, &Mips::MSA128WRegClass);
3509 return std::make_pair(0U, &Mips::MSA128DRegClass);
3511 return std::make_pair(0U, &Mips::FGR32RegClass);
3514 return std::make_pair(0U, &Mips::FGR64RegClass);
3515 return std::make_pair(0U, &Mips::AFGR64RegClass);
3520 return std::make_pair((
unsigned)Mips::T9, &Mips::GPR32RegClass);
3522 return std::make_pair((
unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3525 return std::make_pair((
unsigned)Mips::LO0, &Mips::LO32RegClass);
3526 return std::make_pair((
unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3530 return std::make_pair(0U,
nullptr);
3534 std::pair<unsigned, const TargetRegisterClass *> R;
3535 R = parseRegForInlineAsmConstraint(Constraint, VT);
3545 void MipsTargetLowering::LowerAsmOperandForConstraint(
SDValue Op,
3546 std::string &Constraint,
3547 std::vector<SDValue>&Ops,
3553 if (Constraint.length() > 1)
return;
3555 char ConstraintLetter = Constraint[0];
3556 switch (ConstraintLetter) {
3562 int64_t Val = C->getSExtValue();
3572 int64_t Val = C->getZExtValue();
3582 uint64_t Val = (uint64_t)C->getZExtValue();
3592 int64_t Val = C->getSExtValue();
3593 if ((
isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3602 int64_t Val = C->getSExtValue();
3603 if ((Val >= -65535) && (Val <= -1)) {
3612 int64_t Val = C->getSExtValue();
3613 if ((isInt<15>(Val))) {
3622 int64_t Val = C->getSExtValue();
3623 if ((Val <= 65535) && (Val >= 1)) {
3632 Ops.push_back(Result);
3639 bool MipsTargetLowering::isLegalAddressingMode(
const DataLayout &DL,
3641 unsigned AS)
const {
3666 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size,
unsigned DstAlign,
3668 bool IsMemset,
bool ZeroMemset,
3677 bool MipsTargetLowering::isFPImmLegal(
const APFloat &Imm,
EVT VT)
const {
3685 unsigned MipsTargetLowering::getJumpTableEncoding()
const {
3692 bool MipsTargetLowering::useSoftFloat()
const {
3696 void MipsTargetLowering::copyByValRegs(
3697 SDValue Chain,
const SDLoc &DL, std::vector<SDValue> &OutChains,
3700 unsigned FirstReg,
unsigned LastReg,
const CCValAssign &VA,
3705 unsigned NumRegs = LastReg - FirstReg;
3706 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3707 unsigned FrameObjSize = std::max(Flags.
getByValSize(), RegAreaSize);
3714 (
int)((ByValArgRegs.
size() - FirstReg) * GPRSizeInBytes);
3731 for (
unsigned I = 0;
I < NumRegs; ++
I) {
3732 unsigned ArgReg = ByValArgRegs[FirstReg +
I];
3733 unsigned VReg =
addLiveIn(MF, ArgReg, RC);
3734 unsigned Offset =
I * GPRSizeInBytes;
3739 OutChains.push_back(Store);
3744 void MipsTargetLowering::passByValArg(
3746 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3752 unsigned OffsetInBytes = 0;
3757 unsigned NumRegs = LastReg - FirstReg;
3761 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3765 for (; I < NumRegs - LeftoverBytes; ++
I, OffsetInBytes += RegSizeInBytes) {
3771 unsigned ArgReg = ArgRegs[FirstReg +
I];
3772 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3776 if (ByValSizeInBytes == OffsetInBytes)
3780 if (LeftoverBytes) {
3783 for (
unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3784 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3785 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3787 if (RemainingSizeInBytes < LoadSizeInBytes)
3803 Shamt = TotalBytesLoaded * 8;
3805 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3815 OffsetInBytes += LoadSizeInBytes;
3816 TotalBytesLoaded += LoadSizeInBytes;
3817 Alignment =
std::min(Alignment, LoadSizeInBytes);
3820 unsigned ArgReg = ArgRegs[FirstReg +
I];
3821 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3827 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3832 Chain = DAG.
getMemcpy(Chain, DL, Dst, Src,
3834 Alignment,
false,
false,
3840 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3856 if (ArgRegs.
size() == Idx)
3861 (
int)(RegSizeInBytes * (ArgRegs.
size() - Idx));
3873 for (
unsigned I = Idx; I < ArgRegs.
size();
3874 ++
I, VaArgOffset += RegSizeInBytes) {
3875 unsigned Reg =
addLiveIn(MF, ArgRegs[I], RC);
3881 cast<StoreSDNode>(Store.
getNode())->getMemOperand()->setValue(
3883 OutChains.push_back(Store);
3888 unsigned Align)
const {
3891 assert(Size &&
"Byval argument's size shouldn't be 0.");
3895 unsigned FirstReg = 0;
3896 unsigned NumRegs = 0;
3907 assert(!(Align % RegSizeInBytes) &&
3908 "Byval argument's alignment should be a multiple of"
3917 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3918 State->
AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3923 Size =
alignTo(Size, RegSizeInBytes);
3924 for (
unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.
size());
3925 Size -= RegSizeInBytes, ++
I, ++NumRegs)
3935 unsigned Opc)
const {
3937 "Subtarget already supports SELECT nodes with the use of"
3938 "conditional-move instructions.");
4018 .Case(
"$28", Mips::GP_64)
4024 .Case(
"$28", Mips::GP)
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
static unsigned getBitWidth(Type *Ty, const DataLayout &DL)
Returns the bitwidth of the given scalar or pointer type (if unknown returns 0).
void setFrameAddressIsTaken(bool T)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
static MVT getIntegerVT(unsigned BitWidth)
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
SDValue getValue(unsigned R) const
bool ArePtrs64bit() const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
const char * getSymbol() const
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Flags getFlags() const
Return the raw flags of the source value,.
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
LLVMContext * getContext() const
LLVM Argument representation.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
const MipsSubtarget & Subtarget
STATISTIC(NumFunctions,"Total number of functions")
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
LocInfo getLocInfo() const
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
MO_TLSLDM - Represents the offset into the global offset table at which.
static MVT getVectorVT(MVT VT, unsigned NumElements)
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
const TargetMachine & getTargetMachine() const
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
const TargetMachine & getTarget() const
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
MO_TLSGD - Represents the offset into the global offset table at which.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
const GlobalValue * getGlobal() const
CallingConv::ID getCallingConv() const
const MipsInstrInfo * getInstrInfo() const override
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
unsigned getByValSize() const
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
constexpr bool isInt< 16 >(int64_t x)
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
void setVarArgsFrameIndex(int Index)
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
LLVM_NODISCARD char back() const
back - Get the last character in the string.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
APInt Not(const APInt &APIVal)
Bitwise complement function.
static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size)
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
MachinePointerInfo callPtrInfo(const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
const MipsABIInfo & getABI() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static SDValue performAssertZextCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
struct fuzzer::@269 Flags
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
const HexagonInstrInfo * TII
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG)
unsigned getGPRSizeInBytes() const
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn, const TargetLowering::CallLoweringInfo &CLI)
Shift and rotation operations.
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned getSRetReturnReg() const
bool hasInternalLinkage() const
MachineFunction & getMachineFunction() const
static void advance(T &it, size_t Val)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
virtual TargetLoweringObjectFile * getObjFileLowering() const
void addLoc(const CCValAssign &V)
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
bool isPositionIndependent() const
bool hasExtractInsert() const
Features related to the presence of specific instructions.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
bool isUpperBitsInLoc() const
bool inMips16HardFloat() const
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_NODISCARD bool empty() const
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
MachineFunction & getMachineFunction() const
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
unsigned getLocReg() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
static const MCPhysReg Mips64DPRegs[8]
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
Simple integer binary arithmetic operators.
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
SmallVector< ISD::OutputArg, 32 > Outs
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
LLVM_NODISCARD char front() const
front - Get the first character in the string.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
size_t size() const
size - Get the array size.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned getKillRegState(bool B)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
static unsigned getNextIntArgReg(unsigned Reg)
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
const TargetFrameLowering * getFrameLowering() const override
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
TargetInstrInfo - Interface to description of machine instruction set.
SDNode * getNode() const
get the SDNode which holds the desired result
The memory access is volatile.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
A switch()-like statement whose cases are string literals.
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative...
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
initializer< Ty > init(const Ty &Val)
static mvt_range fp_vector_valuetypes()
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
MVT - Machine Value Type.
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
bool IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
C - The default llvm calling convention, compatible with C.
bool isVectorTy() const
True if this is an instance of VectorType.
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
const Constant * getConstVal() const
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
const MachineOperand & getOperand(unsigned i) const
bool isBeforeLegalizeOps() const
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
static ManagedStatic< OptionRegistry > OR
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void HandleByVal(CCState *, unsigned &, unsigned) const override
Target-specific cleanup for formal ByVal parameters.
static mvt_range fp_valuetypes()
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
#define LLVM_ATTRIBUTE_UNUSED
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
static EVT getFloatingPointVT(unsigned BitWidth)
getFloatingPointVT - Returns the EVT that represents a floating point type with the given number of b...
bool isPositionIndependent() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
TRAP - Trapping instruction.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
self_iterator getIterator()
Class to represent integer types.
bool useSoftFloat() const
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool inMicroMipsMode() const
const SDValue & getValue() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
bool inMips16Mode() const
EVT - Extended Value Type.
std::vector< ArgListEntry > ArgListTy
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
This class contains a discriminated union of information about pointers in memory operands...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
const BlockAddress * getBlockAddress() const
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
const MachinePointerInfo & getPointerInfo() const
void setIsKill(bool Val=true)
unsigned getByValAlign() const
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
unsigned GetNullPtr() const
const char * const_iterator
unsigned countPopulation(T Value)
Count the number of set bits in a value.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
constexpr bool isInt< 32 >(int64_t x)
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
unsigned getGlobalBaseReg()
const MipsRegisterInfo * getRegisterInfo() const override
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
Provides information about what library functions are available for the current target.
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit, bool IsMicroMips)
BRCOND - Conditional branch.
Information about stack frame layout on the target.
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
const SDValue & getChain() const
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
CHAIN = SC CHAIN, Imm128 - System call.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static mvt_range integer_valuetypes()
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
bool isIntegerTy() const
True if this is an instance of IntegerType.
unsigned EmulatedTLS
EmulatedTLS - This flag enables emulated TLS model, using emutls function in the runtime library...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
const GlobalObject * getBaseObject() const
AddrMode
ARM Addressing Modes.
ANY_EXTEND - Used for integer types. The high bits are undefined.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
static const uint32_t * getMips16RetHelperMask()
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
SmallVector< SDValue, 32 > OutVals
constexpr bool isShiftedMask_64(uint64_t Value)
isShiftedMask_64 - This function returns true if the argument contains a non-empty sequence of ones w...
bool isValid() const
isValid - Return true if this is a valid simple valuetype.
void setFormalArgInfo(unsigned Size, bool HasByval)
Bitwise operators - logical and, logical or, logical xor.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
unsigned GetPtrAndOp() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static cl::opt< bool > LargeGOT("mxgot", cl::Hidden, cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false))
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
bool isSingleFloat() const
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
void setSubReg(unsigned subReg)
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
FSINCOS - Compute both fsin and fcos as a single operation.
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
constexpr bool isUInt< 16 >(uint64_t x)
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
int getVarArgsFrameIndex() const
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
unsigned getReg() const
getReg - Returns the register number.
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
unsigned getAlignment() const
void setMinStackArgumentAlignment(unsigned Align)
Set the minimum stack alignment of an argument (in log2(bytes)).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
unsigned getOrigAlign() const
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
unsigned getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
TRUNCATE - Completely drop the high bits.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
auto find_if(R &&Range, UnaryPredicate P) -> decltype(std::begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
unsigned getAlignment() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned GetPtrAddiuOp() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void setSRetReturnReg(unsigned Reg)
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
uint64_t getZExtValue() const
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...