LLVM  4.0.0
AMDGPUTargetTransformInfo.h
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1 //===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// AMDGPU target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
19 
20 #include "AMDGPU.h"
21 #include "AMDGPUTargetMachine.h"
24 
25 namespace llvm {
26 class AMDGPUTargetLowering;
27 
28 class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
30  typedef TargetTransformInfo TTI;
31  friend BaseT;
32 
33  const AMDGPUSubtarget *ST;
34  const AMDGPUTargetLowering *TLI;
35 
36  const AMDGPUSubtarget *getST() const { return ST; }
37  const AMDGPUTargetLowering *getTLI() const { return TLI; }
38 
39 
40  static inline int getFullRateInstrCost() {
42  }
43 
44  static inline int getHalfRateInstrCost() {
46  }
47 
48  // TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
49  // should be 2 or 4.
50  static inline int getQuarterRateInstrCost() {
52  }
53 
54  // On some parts, normal fp64 operations are half rate, and others
55  // quarter. This also applies to some integer operations.
56  inline int get64BitInstrCost() const {
57  return ST->hasHalfRate64Ops() ?
58  getHalfRateInstrCost() : getQuarterRateInstrCost();
59  }
60 
61 public:
62  explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
63  : BaseT(TM, F.getParent()->getDataLayout()),
64  ST(TM->getSubtargetImpl(F)),
65  TLI(ST->getTargetLowering()) {}
66 
67  bool hasBranchDivergence() { return true; }
68 
69  void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
70 
72  assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
73  return TTI::PSK_FastHardware;
74  }
75 
76  unsigned getNumberOfRegisters(bool Vector);
77  unsigned getRegisterBitWidth(bool Vector);
78  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
79  unsigned getMaxInterleaveFactor(unsigned VF);
80 
82  unsigned Opcode, Type *Ty,
88 
89  unsigned getCFInstrCost(unsigned Opcode);
90 
91  int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
92  bool isSourceOfDivergence(const Value *V) const;
93 
94  unsigned getVectorSplitCost() { return 0; }
95 };
96 
97 } // end namespace llvm
98 
99 #endif
MachineLoop * L
unsigned getNumberOfRegisters(bool Vector)
void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP)
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:40
bool isSourceOfDivergence(const Value *V) const
unsigned getRegisterBitWidth(bool Vector)
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
unsigned getMaxInterleaveFactor(unsigned VF)
#define F(x, y, z)
Definition: MD5.cpp:51
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
PopcntSupportKind
Flags indicating the kind of support for population count.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool hasHalfRate64Ops() const
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
Definition: MathExtras.h:399
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
The AMDGPU TargetMachine interface definition for hw codgen targets.
OperandValueProperties
Additional properties of an operand's values.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
unsigned getCFInstrCost(unsigned Opcode)
const DataLayout & getDataLayout() const
int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index)
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:368
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
The cost of a typical 'add' instruction.
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
LLVM Value Representation.
Definition: Value.h:71
static const Function * getParent(const Value *V)
AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
OperandValueKind
Additional information about an operand's possible values.
This pass exposes codegen information to IR-level passes.