15 #ifndef LLVM_AVR_ISEL_LOWERING_H
16 #define LLVM_AVR_ISEL_LOWERING_H
65 class AVRTargetMachine;
84 unsigned AS)
const override;
97 EVT VT)
const override;
107 const char *constraint)
const override;
109 std::pair<unsigned, const TargetRegisterClass *>
116 std::vector<SDValue> &Ops,
166 #endif // LLVM_AVR_ISEL_LOWERING_H
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override
EVT is not used in-tree, but is used by out-of-tree target.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Function Alias Analysis Results
Test for zero or minus instruction.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Compare with carry instruction.
Represents an abstract call instruction, which includes a bunch of information.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
A generic AVR implementation.
NodeType
AVR Specific DAG Nodes.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
AVR conditional branches.
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
AVRTargetLowering(AVRTargetMachine &TM)
A loop of single logical shift right instructions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
Performs target lowering for the AVR.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
AddrMode
ARM Addressing Modes.
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Representation of each machine instruction.
Start the numbering where the builtin ops leave off.
A loop of single arithmetic shift right instructions.
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
StringRef - Represent a constant reference to a string, i.e.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.