280 uint64_t ShiftAmount = cast<ConstantSDNode>(N->
getOperand(1))->getZExtValue();
303 while (ShiftAmount--) {
304 Victim = DAG.
getNode(Opc8, dl, VT, Victim);
310 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG)
const {
313 "Invalid opcode for Div/Rem lowering");
315 EVT VT = Op->getValueType(0);
316 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
319 switch (VT.getSimpleVT().SimpleTy) {
336 SDValue InChain = DAG.getEntryNode();
339 TargetLowering::ArgListEntry Entry;
340 for (SDValue
const &Value : Op->op_values()) {
342 Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
343 Entry.isSExt = isSigned;
344 Entry.isZExt = !isSigned;
345 Args.push_back(Entry);
354 TargetLowering::CallLoweringInfo CLI(DAG);
359 .setSExtResult(isSigned)
360 .setZExtResult(!isSigned);
362 std::pair<SDValue, SDValue> CallInfo =
LowerCallTo(CLI);
363 return CallInfo.first;
366 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
367 SelectionDAG &DAG)
const {
368 auto DL = DAG.getDataLayout();
370 const GlobalValue *GV = cast<GlobalAddressSDNode>(
Op)->getGlobal();
375 DAG.getTargetGlobalAddress(GV, SDLoc(Op),
getPointerTy(DL), Offset);
379 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
380 SelectionDAG &DAG)
const {
381 auto DL = DAG.getDataLayout();
382 const BlockAddress *BA = cast<BlockAddressSDNode>(
Op)->getBlockAddress();
384 SDValue Result = DAG.getTargetBlockAddress(BA,
getPointerTy(DL));
411 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
412 SDValue &AVRcc, SelectionDAG &DAG,
415 EVT VT = LHS.getValueType();
416 bool UseTest =
false;
428 if (
const ConstantSDNode *
C = dyn_cast<ConstantSDNode>(RHS)) {
429 switch (
C->getSExtValue()) {
441 LHS = DAG.getConstant(0, DL, VT);
448 RHS = DAG.getConstant(
C->getSExtValue() + 1, DL, VT);
461 if (
const ConstantSDNode *
C = dyn_cast<ConstantSDNode>(RHS)) {
462 switch (
C->getSExtValue()) {
467 LHS = DAG.getConstant(0, DL, VT);
491 if (
const ConstantSDNode *
C = dyn_cast<ConstantSDNode>(RHS)) {
492 RHS = DAG.getConstant(
C->getSExtValue() + 1, DL, VT);
507 DAG.getIntPtrConstant(0, DL));
509 DAG.getIntPtrConstant(1, DL));
511 DAG.getIntPtrConstant(0, DL));
513 DAG.getIntPtrConstant(1, DL));
518 DAG.getIntPtrConstant(1, DL));
526 DAG.getIntPtrConstant(0, DL));
528 DAG.getIntPtrConstant(1, DL));
531 DAG.getIntPtrConstant(0, DL));
533 DAG.getIntPtrConstant(1, DL));
535 DAG.getIntPtrConstant(0, DL));
537 DAG.getIntPtrConstant(1, DL));
540 DAG.getIntPtrConstant(0, DL));
542 DAG.getIntPtrConstant(1, DL));
545 DAG.getIntPtrConstant(0, DL));
547 DAG.getIntPtrConstant(1, DL));
549 DAG.getIntPtrConstant(0, DL));
551 DAG.getIntPtrConstant(1, DL));
556 DAG.getIntPtrConstant(1, DL));
571 LHS, DAG.getIntPtrConstant(1, DL)));
587 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG)
const {
588 SDValue Chain = Op.getOperand(0);
589 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->
get();
590 SDValue LHS = Op.getOperand(2);
591 SDValue RHS = Op.getOperand(3);
592 SDValue Dest = Op.getOperand(4);
596 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
602 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
const {
603 SDValue LHS = Op.getOperand(0);
604 SDValue RHS = Op.getOperand(1);
605 SDValue TrueV = Op.getOperand(2);
606 SDValue FalseV = Op.getOperand(3);
607 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->
get();
611 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
613 SDVTList VTs = DAG.getVTList(Op.getValueType(),
MVT::Glue);
614 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
619 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG)
const {
620 SDValue LHS = Op.getOperand(0);
621 SDValue RHS = Op.getOperand(1);
622 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->
get();
626 SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
628 SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
629 SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
630 SDVTList VTs = DAG.getVTList(Op.getValueType(),
MVT::Glue);
631 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
636 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG)
const {
637 const MachineFunction &MF = DAG.getMachineFunction();
638 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
639 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
640 auto DL = DAG.getDataLayout();
645 SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
getPointerTy(DL));
647 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
648 MachinePointerInfo(SV), 0);
660 return LowerShifts(Op, DAG);
662 return LowerGlobalAddress(Op, DAG);
664 return LowerBlockAddress(Op, DAG);
666 return LowerBR_CC(Op, DAG);
668 return LowerSELECT_CC(Op, DAG);
670 return LowerSETCC(Op, DAG);
672 return LowerVASTART(Op, DAG);
675 return LowerDivRem(Op, DAG);
694 DAG.
getConstant(-
C->getAPIntValue(), DL,
C->getValueType(0)));
749 VT =
LD->getMemoryVT();
750 Op =
LD->getBasePtr().getNode();
756 }
else if (
const StoreSDNode *
ST = dyn_cast<StoreSDNode>(N)) {
757 VT =
ST->getMemoryVT();
758 Op =
ST->getBasePtr().getNode();
775 int RHSC = RHS->getSExtValue();
805 VT =
LD->getMemoryVT();
808 }
else if (
const StoreSDNode *
ST = dyn_cast<StoreSDNode>(N)) {
809 VT =
ST->getMemoryVT();
826 int RHSC = RHS->getSExtValue();
852 #include "AVRGenCallingConv.inc"
868 for (
unsigned i = 0, e = In.
size();
i != e;) {
871 while ((
i != e) && (In[
i].PartOffset ==
Offset)) {
872 Offset += In[
i].VT.getStoreSize();
884 return G->getSymbol();
888 return G->getGlobal()->getName();
904 CCState &CCInfo,
bool IsCall,
bool IsVarArg) {
905 static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
906 AVR::R18, AVR::R16, AVR::R14,
907 AVR::R12, AVR::R10, AVR::R8};
908 static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
909 AVR::R19R18, AVR::R17R16, AVR::R15R14,
910 AVR::R13R12, AVR::R11R10, AVR::R9R8};
926 assert(F !=
nullptr &&
"function should not be null");
932 bool UsesStack =
false;
933 for (
unsigned i = 0, pos = 0, e = Args.
size();
i != e; ++
i) {
934 unsigned Size = Args[
i];
935 MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
938 if (!UsesStack && (Size <= RegsLeft)) {
941 for (
unsigned j = 0; j != Size; ++j) {
955 for (
unsigned j = 0; j != Size; ++j) {
974 CCState &CCInfo,
bool IsCall,
bool IsVarArg) {
981 CallConv, ArgLocs, CCInfo,
992 CCState &CCInfo,
bool IsCall,
bool IsVarArg) {
996 CallConv, ArgLocs, CCInfo,
1002 CallConv, ArgLocs, CCInfo,
1009 SDValue AVRTargetLowering::LowerFormalArguments(
1011 const SmallVectorImpl<ISD::InputArg> &
Ins,
const SDLoc &dl, SelectionDAG &DAG,
1012 SmallVectorImpl<SDValue> &InVals)
const {
1013 MachineFunction &MF = DAG.getMachineFunction();
1014 MachineFrameInfo &MFI = MF.getFrameInfo();
1015 auto DL = DAG.getDataLayout();
1018 SmallVector<CCValAssign, 16> ArgLocs;
1019 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1026 for (CCValAssign &VA : ArgLocs) {
1029 if (VA.isRegLoc()) {
1030 EVT RegVT = VA.getLocVT();
1031 const TargetRegisterClass *RC;
1033 RC = &AVR::GPR8RegClass;
1035 RC = &AVR::DREGSRegClass;
1040 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1041 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1049 switch (VA.getLocInfo()) {
1055 ArgValue = DAG.getNode(
ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1059 DAG.getValueType(VA.getValVT()));
1060 ArgValue = DAG.getNode(
ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1064 DAG.getValueType(VA.getValVT()));
1065 ArgValue = DAG.getNode(
ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1069 InVals.push_back(ArgValue);
1074 EVT LocVT = VA.getLocVT();
1077 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1078 VA.getLocMemOffset(),
true);
1083 InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1092 unsigned StackSize = CCInfo.getNextStackOffset();
1093 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1095 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize,
true));
1105 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1106 SmallVectorImpl<SDValue> &InVals)
const {
1107 SelectionDAG &DAG = CLI.DAG;
1109 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1110 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1111 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1112 SDValue Chain = CLI.Chain;
1113 SDValue Callee = CLI.Callee;
1114 bool &isTailCall = CLI.IsTailCall;
1116 bool isVarArg = CLI.IsVarArg;
1118 MachineFunction &MF = DAG.getMachineFunction();
1124 SmallVector<CCValAssign, 16> ArgLocs;
1125 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1132 if (
const GlobalAddressSDNode *
G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1133 const GlobalValue *GV =
G->getGlobal();
1135 F = cast<Function>(GV);
1137 DAG.getTargetGlobalAddress(GV, DL,
getPointerTy(DAG.getDataLayout()));
1138 }
else if (
const ExternalSymbolSDNode *ES =
1139 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1140 Callee = DAG.getTargetExternalSymbol(
ES->getSymbol(),
1144 analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1148 unsigned NumBytes = CCInfo.getNextStackOffset();
1150 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
true),
1153 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1157 bool HasStackArgs =
false;
1158 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1159 CCValAssign &VA = ArgLocs[AI];
1160 EVT RegVT = VA.getLocVT();
1161 SDValue Arg = OutVals[AI];
1164 switch (VA.getLocInfo()) {
1185 if (VA.isMemLoc()) {
1186 HasStackArgs =
true;
1192 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1200 for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1201 unsigned Loc = AI - 1;
1202 CCValAssign &VA = ArgLocs[Loc];
1203 SDValue Arg = OutVals[Loc];
1208 SDValue PtrOff = DAG.getNode(
1210 DAG.getRegister(AVR::SP,
getPointerTy(DAG.getDataLayout())),
1211 DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1214 DAG.getStore(Chain, DL, Arg, PtrOff,
1224 for (
auto Reg : RegsToPass) {
1225 Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1226 InFlag = Chain.getValue(1);
1231 SmallVector<SDValue, 8> Ops;
1232 Ops.push_back(Chain);
1233 Ops.push_back(Callee);
1237 for (
auto Reg : RegsToPass) {
1238 Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1245 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1246 assert(Mask &&
"Missing call preserved mask for calling convention");
1247 Ops.push_back(DAG.getRegisterMask(Mask));
1249 if (InFlag.getNode()) {
1250 Ops.push_back(InFlag);
1254 InFlag = Chain.getValue(1);
1257 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL,
true),
1258 DAG.getIntPtrConstant(0, DL,
true), InFlag, DL);
1261 InFlag = Chain.getValue(1);
1266 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1273 SDValue AVRTargetLowering::LowerCallResult(
1274 SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv,
bool isVarArg,
1275 const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &dl, SelectionDAG &DAG,
1276 SmallVectorImpl<SDValue> &InVals)
const {
1279 SmallVector<CCValAssign, 16> RVLocs;
1280 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1284 auto CCFunction = CCAssignFnForReturn(CallConv);
1285 CCInfo.AnalyzeCallResult(Ins, CCFunction);
1294 for (CCValAssign
const &RVLoc : RVLocs) {
1295 Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1298 InFlag = Chain.getValue(2);
1299 InVals.push_back(Chain.getValue(0));
1312 return RetCC_AVR_BUILTIN;
1320 MachineFunction &MF,
bool isVarArg,
1321 const SmallVectorImpl<ISD::OutputArg> &Outs,
1324 SmallVector<CCValAssign, 16> RVLocs;
1325 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1327 auto CCFunction = CCAssignFnForReturn(CallConv);
1328 return CCInfo.CheckReturn(Outs, CCFunction);
1332 AVRTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
1334 const SmallVectorImpl<ISD::OutputArg> &Outs,
1335 const SmallVectorImpl<SDValue> &OutVals,
1336 const SDLoc &dl, SelectionDAG &DAG)
const {
1338 SmallVector<CCValAssign, 16> RVLocs;
1341 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1345 auto CCFunction = CCAssignFnForReturn(CallConv);
1346 CCInfo.AnalyzeReturn(Outs, CCFunction);
1350 MachineFunction &MF = DAG.getMachineFunction();
1351 unsigned e = RVLocs.size();
1360 SmallVector<SDValue, 4> RetOps(1, Chain);
1362 for (
unsigned i = 0;
i != e; ++
i) {
1363 CCValAssign &VA = RVLocs[
i];
1364 assert(VA.isRegLoc() &&
"Can only return in registers!");
1366 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[
i],
Flag);
1369 Flag = Chain.getValue(1);
1370 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1375 if (MF.getFunction()->getAttributes().hasAttribute(
1387 if (Flag.getNode()) {
1388 RetOps.push_back(Flag);
1391 return DAG.getNode(RetOpc, dl,
MVT::Other, RetOps);
1398 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &
MI,
1399 MachineBasicBlock *BB)
const {
1401 const TargetRegisterClass *RC;
1402 MachineFunction *F = BB->getParent();
1403 MachineRegisterInfo &RI = F->getRegInfo();
1405 const TargetInstrInfo &
TII = *TM.getSubtargetImpl()->getInstrInfo();
1406 DebugLoc dl = MI.getDebugLoc();
1408 switch (MI.getOpcode()) {
1413 RC = &AVR::GPR8RegClass;
1417 RC = &AVR::DREGSRegClass;
1421 RC = &AVR::GPR8RegClass;
1425 RC = &AVR::DREGSRegClass;
1429 RC = &AVR::GPR8RegClass;
1433 RC = &AVR::DREGSRegClass;
1437 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1442 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1443 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1445 F->insert(I, LoopBB);
1446 F->insert(I, RemBB);
1452 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1455 BB->addSuccessor(LoopBB);
1456 BB->addSuccessor(RemBB);
1457 LoopBB->addSuccessor(RemBB);
1458 LoopBB->addSuccessor(LoopBB);
1460 unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1461 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1462 unsigned ShiftReg = RI.createVirtualRegister(RC);
1463 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1464 unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1465 unsigned SrcReg = MI.getOperand(1).getReg();
1466 unsigned DstReg = MI.getOperand(0).getReg();
1471 BuildMI(BB, dl, TII.get(AVR::CPRdRr)).addReg(ShiftAmtSrcReg).
addReg(AVR::R0);
1472 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1479 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1484 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1485 .addReg(ShiftAmtSrcReg)
1489 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1490 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1491 .addReg(ShiftAmtReg)
1493 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1497 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1503 MI.eraseFromParent();
1508 if (I->getOpcode() == AVR::COPY) {
1509 unsigned SrcReg = I->getOperand(1).getReg();
1510 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1519 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1520 MachineBasicBlock *BB)
const {
1529 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1549 return insertShift(MI, MBB);
1552 return insertMul(MI, MBB);
1555 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1556 "Unexpected instr type to insert");
1589 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1594 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1614 if (Constraint.
size() == 1) {
1616 switch (Constraint[0]) {
1656 switch (ConstraintCode[0]) {
1672 if (!CallOperandVal) {
1677 switch (*constraint) {
1698 if (
const ConstantFP *
C = dyn_cast<ConstantFP>(CallOperandVal)) {
1705 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1706 if (isUInt<6>(
C->getZExtValue())) {
1712 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1713 if ((
C->getSExtValue() >= -63) && (
C->getSExtValue() <= 0)) {
1719 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1720 if (
C->getZExtValue() == 2) {
1726 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1727 if (
C->getZExtValue() == 0) {
1733 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1740 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1741 if (
C->getSExtValue() == -1) {
1747 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1748 if ((
C->getZExtValue() == 8) || (
C->getZExtValue() == 16) ||
1749 (
C->getZExtValue() == 24)) {
1755 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1756 if (
C->getZExtValue() == 1) {
1762 if (
const ConstantInt *
C = dyn_cast<ConstantInt>(CallOperandVal)) {
1763 if ((
C->getSExtValue() >= -6) && (
C->getSExtValue() <= 5)) {
1776 std::pair<unsigned, const TargetRegisterClass *>
1781 .getSubtargetImpl();
1788 if (Constraint.
size() == 1) {
1789 switch (Constraint[0]) {
1791 return std::make_pair(0U, &AVR::LD8loRegClass);
1793 return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1795 return std::make_pair(0U, &AVR::LD8RegClass);
1797 return std::make_pair(0U, &AVR::GPR8loRegClass);
1799 return std::make_pair(0U, &AVR::PTRREGSRegClass);
1801 return std::make_pair(0U, &AVR::GPRSPRegClass);
1804 return std::make_pair(0U, &AVR::GPR8RegClass);
1807 return std::make_pair(0U, &AVR::DREGSRegClass);
1809 return std::make_pair(
unsigned(AVR::R0), &AVR::GPR8RegClass);
1811 return std::make_pair(0U, &AVR::IWREGSRegClass);
1814 return std::make_pair(
unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1817 return std::make_pair(
unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1820 return std::make_pair(
unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1831 std::string &Constraint,
1832 std::vector<SDValue> &Ops,
1839 if (Constraint.length() != 1) {
1843 char ConstraintLetter = Constraint[0];
1844 switch (ConstraintLetter) {
1864 switch (ConstraintLetter) {
1866 if (!isUInt<6>(CUVal64))
1871 if (CVal64 < -63 || CVal64 > 0)
1902 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1912 if (CVal64 < -6 || CVal64 > 5)
1922 if (!FC || !FC->
isZero())
1930 Ops.push_back(Result);
1947 .
Case(
"r9", AVR::R9).
Case(
"r10", AVR::R10).
Case(
"r11", AVR::R11)
1948 .
Case(
"r12", AVR::R12).
Case(
"r13", AVR::R13).
Case(
"r14", AVR::R14)
1949 .
Case(
"r15", AVR::R15).
Case(
"r16", AVR::R16).
Case(
"r17", AVR::R17)
1950 .
Case(
"r18", AVR::R18).
Case(
"r19", AVR::R19).
Case(
"r20", AVR::R20)
1951 .
Case(
"r21", AVR::R21).
Case(
"r22", AVR::R22).
Case(
"r23", AVR::R23)
1952 .
Case(
"r24", AVR::R24).
Case(
"r25", AVR::R25).
Case(
"r26", AVR::R26)
1953 .
Case(
"r27", AVR::R27).
Case(
"r28", AVR::R28).
Case(
"r29", AVR::R29)
1954 .
Case(
"r30", AVR::R30).
Case(
"r31", AVR::R31)
1955 .
Case(
"X", AVR::R27R26).
Case(
"Y", AVR::R29R28).
Case(
"Z", AVR::R31R30)
1959 .Case(
"r0", AVR::R1R0).
Case(
"r2", AVR::R3R2)
1960 .
Case(
"r4", AVR::R5R4).
Case(
"r6", AVR::R7R6)
1961 .
Case(
"r8", AVR::R9R8).
Case(
"r10", AVR::R11R10)
1962 .
Case(
"r12", AVR::R13R12).
Case(
"r14", AVR::R15R14)
1963 .
Case(
"r16", AVR::R17R16).
Case(
"r18", AVR::R19R18)
1964 .
Case(
"r20", AVR::R21R20).
Case(
"r22", AVR::R23R22)
1965 .
Case(
"r24", AVR::R25R24).
Case(
"r26", AVR::R27R26)
1966 .
Case(
"r28", AVR::R29R28).
Case(
"r30", AVR::R31R30)
1967 .
Case(
"X", AVR::R27R26).
Case(
"Y", AVR::R29R28).
Case(
"Z", AVR::R31R30)
static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
LLVM Argument representation.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
const TargetMachine & getTargetMachine() const
const AVRSubtarget * getSubtargetImpl() const
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
MachineInstrBundleIterator< MachineInstr > iterator
Test for zero or minus instruction.
const SDValue & getOperand(unsigned Num) const
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Compare with carry instruction.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
LLVMContext & getContext() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static void parseExternFuncCallArgs(const SmallVectorImpl< ISD::OutputArg > &In, SmallVectorImpl< unsigned > &Out)
For external symbols there is no function prototype information so we have to rely directly on argume...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Represents an abstract call instruction, which includes a bunch of information.
const HexagonInstrInfo * TII
Shift and rotation operations.
bool isProgramMemoryAccess(MemSDNode const *N)
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Reg
All possible values of the reg field in the ModR/M byte.
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
A generic AVR implementation.
Utilities related to the AVR instruction set.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset)
Stack pointer relative access.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
A switch()-like statement whose cases are string literals.
constexpr bool isUInt< 8 >(uint64_t x)
bool isZero() const
Return true if the value is positive or negative zero.
MVT - Machine Value Type.
LLVM Basic Block Representation.
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
Analyze incoming and outgoing function arguments.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
const MachineOperand & getOperand(unsigned i) const
ConstantFP - Floating Point Values [float, double].
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Used for AVR interrupt routines.
AVR conditional branches.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
static void parseFunctionArgs(const Function *F, const DataLayout *TD, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
CondCodes
AVR specific condition codes.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
EVT - Extended Value Type.
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AVRTargetLowering(AVRTargetMachine &TM)
virtual const TargetSubtargetInfo * getSubtargetImpl(const Function &) const
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
A loop of single logical shift right instructions.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
BRCOND - Conditional branch.
Byte Swap and Counting operators.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
A loop of single arithmetic shift right instructions.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const AVRRegisterInfo * getRegisterInfo() const override
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
BasicBlockListType::iterator iterator
Calling convention used for AVR signal routines.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
SetCC operator - This evaluates to a true value iff the condition is true.
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
TRUNCATE - Completely drop the high bits.
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
iterator_range< arg_iterator > args()
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
uint64_t getZExtValue() const
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...