46 return "R600 Expand special instructions pass";
55 return new R600ExpandSpecialInstrsPass(TM);
58 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(
MachineInstr *NewMI,
60 int OpIdx =
TII->getOperandIdx(*OldMI, Op);
63 TII->setImmOperand(*NewMI, Op, Val);
67 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(
MachineFunction &MF) {
77 while (I != MBB.
end()) {
83 int DstIdx = TII->getOperandIdx(MI.
getOpcode(), AMDGPU::OpName::dst);
87 DstOp.
getReg(), AMDGPU::OQAP);
88 DstOp.
setReg(AMDGPU::OQAP);
89 int LDSPredSelIdx = TII->getOperandIdx(MI.
getOpcode(),
90 AMDGPU::OpName::pred_sel);
91 int MovPredSelIdx = TII->getOperandIdx(Mov->
getOpcode(),
92 AMDGPU::OpName::pred_sel);
101 case AMDGPU::PRED_X: {
105 MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
112 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_exec_mask, 1);
114 TII->setImmOperand(*PredSet, AMDGPU::OpName::update_pred, 1);
119 case AMDGPU::DOT_4: {
124 unsigned DstBase = TRI.getEncodingValue(DstReg) &
HW_REG_MASK;
126 for (
unsigned Chan = 0; Chan < 4; ++Chan) {
129 AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
131 TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
144 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
147 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
151 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
152 (TRI.getEncodingValue(Src1) & 0xff) < 127)
160 bool IsReduction = TII->isReductionOp(MI.
getOpcode());
161 bool IsVector = TII->isVector(MI);
162 bool IsCube = TII->isCubeOp(MI.
getOpcode());
163 if (!IsReduction && !IsVector && !IsCube) {
192 for (
unsigned Chan = 0; Chan < 4; Chan++) {
194 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).
getReg();
196 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).
getReg();
201 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
208 Src0 = TRI.getSubReg(Src0, SubRegIndex);
209 Src1 = TRI.getSubReg(Src1, SubRegIndex);
211 static const int CubeSrcSwz[] = {2, 2, 0, 1};
214 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
215 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
223 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
228 unsigned DstBase = TRI.getEncodingValue(DstReg) &
HW_REG_MASK;
229 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
233 NotLast = (Chan != 3 );
238 case AMDGPU::CUBE_r600_pseudo:
239 Opcode = AMDGPU::CUBE_r600_real;
241 case AMDGPU::CUBE_eg_pseudo:
242 Opcode = AMDGPU::CUBE_eg_real;
249 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
259 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::clamp);
260 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::literal);
261 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_abs);
262 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_abs);
263 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src0_neg);
264 SetFlagInNewMI(NewMI, &MI, AMDGPU::OpName::src1_neg);
void bundleWithPred()
Bundle this instruction with its predecessor.
AMDGPU specific subclass of TargetSubtarget.
Interface definition for R600InstrInfo.
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
Interface definition for R600RegisterInfo.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
struct fuzzer::@269 Flags
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
FunctionPass * createR600ExpandSpecialInstrsPass(TargetMachine &tm)
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define HW_REG_MASK
Defines for extracting register information from register encoding.
const MachineOperand & getOperand(unsigned i) const
unsigned getSubRegFromChannel(unsigned Channel) const
const R600InstrInfo * getInstrInfo() const override
FunctionPass class - This class is used to implement most global optimizations.
const R600RegisterInfo * getRegisterInfo() const override
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Representation of each machine instruction.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.