109 using namespace llvm;
111 #define DEBUG_TYPE "frame-info"
114 cl::desc(
"enable use of redzone on AArch64"),
117 STATISTIC(NumRedZoneFunctions,
"Number of functions using red zone");
163 unsigned Opc = I->getOpcode();
164 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
165 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
171 int64_t Amount = I->getOperand(0).getImm();
172 Amount =
alignTo(Amount, Align);
179 if (CalleePopAmount == 0) {
190 assert(Amount > -0xffffff && Amount < 0xffffff &&
"call frame too large");
193 }
else if (CalleePopAmount != 0) {
196 assert(CalleePopAmount < 0xffffff &&
"call frame too large");
197 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
217 for (
const auto &Info : CSI) {
218 unsigned Reg = Info.getReg();
224 BuildMI(MBB, MBBI, DL, TII->
get(TargetOpcode::CFI_INSTRUCTION))
225 .addCFIIndex(CFIIndex)
256 for (
unsigned i = 0; CSRegs[
i]; ++
i)
261 if (LiveRegs.
available(MRI, AArch64::X9))
264 for (
unsigned Reg : AArch64::GPR64RegClass) {
268 return AArch64::NoRegister;
279 if (!RegInfo->needsStackRealignment(*MF))
286 bool AArch64FrameLowering::shouldCombineCSRLocalStackBump(
298 if (StackBumpBytes >= 512)
301 if (MFI.hasVarSizedObjects())
304 if (RegInfo->needsStackRealignment(MF))
324 bool NewIsUnscaled =
false;
325 switch (MBBI->getOpcode()) {
329 NewOpc = AArch64::STPXpre;
332 NewOpc = AArch64::STPDpre;
334 case AArch64::STRXui:
335 NewOpc = AArch64::STRXpre;
336 NewIsUnscaled =
true;
338 case AArch64::STRDui:
339 NewOpc = AArch64::STRDpre;
340 NewIsUnscaled =
true;
343 NewOpc = AArch64::LDPXpost;
346 NewOpc = AArch64::LDPDpost;
348 case AArch64::LDRXui:
349 NewOpc = AArch64::LDRXpost;
350 NewIsUnscaled =
true;
352 case AArch64::LDRDui:
353 NewOpc = AArch64::LDRDpost;
354 NewIsUnscaled =
true;
362 unsigned OpndIdx = 0;
363 for (
unsigned OpndEnd = MBBI->getNumOperands() - 1; OpndIdx < OpndEnd;
367 assert(MBBI->getOperand(OpndIdx).getImm() == 0 &&
368 "Unexpected immediate offset in first/last callee-save save/restore "
370 assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
371 "Unexpected base register in callee-save save/restore instruction!");
373 assert(CSStackSizeInc % 8 == 0);
374 int64_t CSStackSizeIncImm = CSStackSizeInc;
376 CSStackSizeIncImm /= 8;
377 MIB.
addImm(CSStackSizeIncImm);
380 MIB.
setMemRefs(MBBI->memoperands_begin(), MBBI->memoperands_end());
382 return std::prev(MBB.
erase(MBBI));
388 unsigned LocalStackSize) {
391 assert((Opc == AArch64::STPXi || Opc == AArch64::STPDi ||
392 Opc == AArch64::STRXui || Opc == AArch64::STRDui ||
393 Opc == AArch64::LDPXi || Opc == AArch64::LDPDi ||
394 Opc == AArch64::LDRXui || Opc == AArch64::LDRDui) &&
395 "Unexpected callee-save save/restore opcode!");
399 "Unexpected base register in callee-save save/restore instruction!");
403 assert(LocalStackSize % 8 == 0);
404 OffsetOpnd.setImm(OffsetOpnd.getImm() + LocalStackSize / 8);
418 bool HasFP =
hasFP(MF);
431 assert(!HasFP &&
"unexpected function without stack frame but with FP");
441 ++NumRedZoneFunctions;
443 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
451 BuildMI(MBB, MBBI, DL, TII->
get(TargetOpcode::CFI_INSTRUCTION))
452 .addCFIIndex(CFIIndex)
462 bool CombineSPBump = shouldCombineCSRLocalStackBump(MF, NumBytes);
464 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
467 }
else if (CSStackSize != 0) {
470 NumBytes -= CSStackSize;
472 assert(NumBytes >= 0 &&
"Negative stack allocation size!?");
485 int FPOffset = CSStackSize - 16;
493 emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP, FPOffset, TII,
499 const bool NeedsRealignment = RegInfo->needsStackRealignment(MF);
500 unsigned scratchSPReg = AArch64::SP;
502 if (NeedsRealignment) {
504 assert(scratchSPReg != AArch64::NoRegister);
512 emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP, -NumBytes, TII,
515 if (NeedsRealignment) {
519 assert(scratchSPReg != AArch64::SP);
529 | ((64 - NrBitsToZero) << 6)
530 | ((64 - NrBitsToZero - 1) << 0);
532 BuildMI(MBB, MBBI, DL, TII->
get(AArch64::ANDXri), AArch64::SP)
546 if (RegInfo->hasBasePointer(MF)) {
547 TII->
copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
551 if (needsFrameMoves) {
554 unsigned FramePtr = RegInfo->getFrameRegister(MF);
623 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr,
true);
626 BuildMI(MBB, MBBI, DL, TII->
get(TargetOpcode::CFI_INSTRUCTION))
627 .addCFIIndex(CFIIndex)
633 BuildMI(MBB, MBBI, DL, TII->
get(TargetOpcode::CFI_INSTRUCTION))
634 .addCFIIndex(CFIIndex)
651 bool IsTailCallReturn =
false;
652 if (MBB.
end() != MBBI) {
653 DL = MBBI->getDebugLoc();
654 unsigned RetOpcode = MBBI->getOpcode();
655 IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
656 RetOpcode == AArch64::TCRETURNri;
668 uint64_t ArgumentPopSize = 0;
669 if (IsTailCallReturn) {
675 ArgumentPopSize = StackAdjust.
getImm();
712 bool CombineSPBump = shouldCombineCSRLocalStackBump(MF, NumBytes);
714 if (!CombineSPBump && CSStackSize != 0)
721 while (LastPopI != Begin) {
726 }
else if (CombineSPBump)
733 NumBytes + ArgumentPopSize,
TII,
738 NumBytes -= CSStackSize;
739 assert(NumBytes >= 0 &&
"Negative stack allocation size!?");
745 if (RedZone && ArgumentPopSize == 0)
748 bool NoCalleeSaveRestore = CSStackSize == 0;
749 int StackRestoreBytes = RedZone ? 0 : NumBytes;
750 if (NoCalleeSaveRestore)
751 StackRestoreBytes += ArgumentPopSize;
756 if (NoCalleeSaveRestore || ArgumentPopSize == 0)
769 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, NumBytes, TII,
786 unsigned &FrameReg)
const {
791 int FI,
unsigned &FrameReg,
792 bool PreferFP)
const {
814 !RegInfo->needsStackRealignment(MF)) {
825 (FPOffset >= -256 && Offset > -FPOffset))
830 assert((isFixed || !RegInfo->needsStackRealignment(MF) || !UseFP) &&
831 "In the presence of dynamic stack pointer realignment, "
832 "non-argument objects cannot be accessed through the frame pointer");
843 FrameReg = AArch64::SP;
869 Attrs.hasAttrSomewhere(Attribute::SwiftError));
874 RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {}
880 bool isPaired()
const {
return Reg2 != AArch64::NoRegister; }
894 unsigned Count = CSI.size();
901 "Odd number of callee-saved regs to spill!");
904 for (
unsigned i = 0;
i < Count; ++
i) {
906 RPI.Reg1 = CSI[
i].getReg();
909 AArch64::FPR64RegClass.contains(RPI.Reg1));
910 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1);
914 unsigned NextReg = CSI[
i + 1].getReg();
915 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) ||
916 (!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg)))
926 assert((!RPI.isPaired() ||
927 (CSI[
i].getFrameIdx() + 1 == CSI[
i + 1].getFrameIdx())) &&
928 "Out of order callee saved regs!");
935 ((RPI.Reg1 == AArch64::LR && RPI.Reg2 == AArch64::FP) ||
936 RPI.Reg1 + 1 == RPI.Reg2))) &&
937 "Callee-save registers not saved as adjacent register pair!");
939 RPI.FrameIdx = CSI[
i].getFrameIdx();
945 assert(MFI.getObjectAlignment(RPI.FrameIdx) <= 16);
946 MFI.setObjectAlignment(RPI.FrameIdx, 16);
949 Offset -= RPI.isPaired() ? 16 : 8;
951 RPI.Offset = Offset / 8;
952 assert((RPI.Offset >= -64 && RPI.Offset <= 63) &&
953 "Offset out of bounds for LDP/STP immediate");
963 const std::vector<CalleeSavedInfo> &CSI,
972 for (
auto RPII = RegPairs.
rbegin(), RPIE = RegPairs.
rend(); RPII != RPIE;
974 RegPairInfo
RPI = *RPII;
975 unsigned Reg1 = RPI.Reg1;
976 unsigned Reg2 = RPI.Reg2;
990 StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
992 StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
996 dbgs() <<
") -> fi#(" << RPI.FrameIdx;
998 dbgs() <<
", " << RPI.FrameIdx+1;
1003 if (RPI.isPaired()) {
1011 .addReg(AArch64::SP)
1023 const std::vector<CalleeSavedInfo> &CSI,
1030 if (MI != MBB.
end())
1031 DL = MI->getDebugLoc();
1035 for (
auto RPII = RegPairs.
begin(), RPIE = RegPairs.
end(); RPII != RPIE;
1037 RegPairInfo
RPI = *RPII;
1038 unsigned Reg1 = RPI.Reg1;
1039 unsigned Reg2 = RPI.Reg2;
1051 LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
1053 LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
1057 dbgs() <<
") -> fi#(" << RPI.FrameIdx;
1059 dbgs() <<
", " << RPI.FrameIdx+1;
1063 if (RPI.isPaired()) {
1092 unsigned UnspilledCSGPR = AArch64::NoRegister;
1093 unsigned UnspilledCSGPRPaired = AArch64::NoRegister;
1097 SavedRegs.
set(AArch64::FP);
1098 SavedRegs.
set(AArch64::LR);
1101 unsigned BasePointerReg = AArch64::NoRegister;
1105 bool ExtraCSSpill =
false;
1108 for (
unsigned i = 0; CSRegs[
i]; ++
i) {
1109 const unsigned Reg = CSRegs[
i];
1112 if (Reg == BasePointerReg)
1115 bool RegUsed = SavedRegs.
test(Reg);
1116 unsigned PairedReg = CSRegs[
i ^ 1];
1118 if (AArch64::GPR64RegClass.
contains(Reg) &&
1120 UnspilledCSGPR =
Reg;
1121 UnspilledCSGPRPaired = PairedReg;
1130 SavedRegs.
set(PairedReg);
1131 if (AArch64::GPR64RegClass.
contains(PairedReg) &&
1133 ExtraCSSpill =
true;
1137 DEBUG(
dbgs() <<
"*** determineCalleeSaves\nUsed CSRs:";
1144 unsigned NumRegsSpilled = SavedRegs.
count();
1145 bool CanEliminateFrame = NumRegsSpilled == 0;
1155 DEBUG(
dbgs() <<
"Estimated stack frame size: " << CFSize <<
" bytes.\n");
1156 bool BigStack = (CFSize >= 256);
1166 if (BigStack && !ExtraCSSpill) {
1167 if (UnspilledCSGPR != AArch64::NoRegister) {
1169 <<
" to get a scratch register.\n");
1170 SavedRegs.
set(UnspilledCSGPR);
1175 SavedRegs.
set(UnspilledCSGPRPaired);
1176 ExtraCSSpill =
true;
1177 NumRegsSpilled = SavedRegs.
count();
1182 if (!ExtraCSSpill) {
1186 DEBUG(
dbgs() <<
"No available CS registers, allocated fi#" << FI
1187 <<
" as the emergency spill slot.\n");
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
bool cannotEliminateFrame(const MachineFunction &MF) const
STATISTIC(NumFunctions,"Total number of functions")
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
int resolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, bool PreferFP=false) const
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
return AArch64::GPR64RegClass contains(Reg)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
static unsigned findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB)
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
unsigned getFrameRegister(const MachineFunction &MF) const override
static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg)
unsigned getBaseRegister() const
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const TargetInstrInfo *TII, int CSStackSizeInc)
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - Provide a base+offset reference to an FI slot for debug info.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getArgumentStackToRestore() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool hasDebugInfo() const
Returns true if valid debug info is present.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
const MachineBasicBlock & front() const
bool isLiveIn(unsigned Reg) const
unsigned getCalleeSavedStackSize() const
const AArch64RegisterInfo * getRegisterInfo() const override
bool hasStackFrame() const
bool hasCalleeSaveStackFreeSpace() const
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getLocalStackSize() const
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
unsigned getKillRegState(bool B)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, int Offset, const TargetInstrInfo *TII, MachineInstr::MIFlag=MachineInstr::NoFlags, bool SetNZCV=false)
emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg plus Offset.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getDefRegState(bool B)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const AArch64TargetLowering * getTargetLowering() const override
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
initializer< Ty > init(const Ty &Val)
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
size_type count() const
count - Returns the number of bits which are set.
This file declares the machine register scavenger class.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
void setLocalStackSize(unsigned Size)
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
const MachineOperand & getOperand(unsigned i) const
bool isTargetMachO() const
void setCalleeSaveStackHasFreeSpace(bool s)
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
static const unsigned End
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void setHasStackFrame(bool s)
static cl::opt< bool > EnableRedZone("aarch64-redzone", cl::desc("enable use of redzone on AArch64"), cl::init(false), cl::Hidden)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
The memory access writes data.
bool hasCalls() const
Return true if the current function has any function calls.
virtual const TargetFrameLowering * getFrameLowering() const
static void computeCalleeSaveRegisterPairs(MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI, SmallVectorImpl< RegPairInfo > &RegPairs)
const MCContext & getContext() const
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool test(unsigned Idx) const
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
void setStackRealigned(bool s)
Information about stack frame layout on the target.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
AttributeSet getAttributes() const
Return the attribute list for this Function.
bool enableStackSlotScavenging(const MachineFunction &MF) const override
Returns true if the stack slot holes in the fixed and callee-save stack area should be used when allo...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of live physical registers with functions to track liveness when walking backward/forward throu...
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI, unsigned LocalStackSize)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool isStackRealigned() const
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
static bool produceCompactUnwindFrame(MachineFunction &MF)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
unsigned getReg() const
getReg - Returns the register number.
reverse_iterator rbegin()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool canUseRedZone(const MachineFunction &MF) const
Can this function use the red zone for local allocations.
virtual const TargetInstrInfo * getInstrInfo() const
const AArch64InstrInfo * getInstrInfo() const override
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
static const unsigned FramePtr
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineModuleInfo & getMMI() const
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
bool hasBasePointer(const MachineFunction &MF) const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
void setCalleeSavedStackSize(unsigned Size)
This class contains meta information specific to a module.
void addReg(unsigned Reg)
Adds a physical register and all its sub-registers to the set.