9 #ifndef HEXAGON_BLOCK_RANGES_H
10 #define HEXAGON_BLOCK_RANGES_H
22 class HexagonSubtarget;
23 class MachineBasicBlock;
24 class MachineFunction;
27 class TargetInstrInfo;
28 class TargetRegisterInfo;
77 class IndexRange :
public std::pair<IndexType,IndexType> {
98 void setStart(
const IndexType &S) { first = S; }
107 push_back(
IndexRange(Start, End, Fixed, TiedEnd));
114 void unionize(
bool MergeAdjacent =
false);
138 std::map<IndexType,MachineInstr*> Map;
162 void computeInitialLiveRanges(InstrIndexMap &IndexMap,
172 inline HexagonBlockRanges::IndexType::operator
unsigned()
const {
182 return Index == Idx.Index;
190 return Index != Idx.Index;
210 if (Index == Idx.Index)
214 if (Index ==
None || Idx.Index ==
None)
218 if (Index == Exit || Idx.Index == Entry)
222 if (Index == Entry || Idx.Index == Exit)
225 return Index < Idx.Index;
244 #endif // HEXAGON_BLOCK_RANGES_H
bool operator!=(unsigned x) const
bool operator<(unsigned Idx) const
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
void add(const IndexRange &Range)
bool operator<(RegisterRef R) const
void add(IndexType Start, IndexType End, bool Fixed, bool TiedEnd)
std::set< RegisterRef > RegisterSet
bool overlaps(const IndexRange &A) const
MachineBasicBlock & getBlock() const
IndexType getNextIndex(IndexType Idx) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstr * getInstr(IndexType Idx) const
unsigned const MachineRegisterInfo * MRI
bool operator<(const IndexRange &A) const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
static const unsigned End
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void subtract(const IndexRange &Range)
static bool isInstr(IndexType X)
IndexRange(IndexType Start, IndexType End, bool F=false, bool T=false)
void include(const RangeList &RL)
bool operator<=(IndexType Idx) const
bool operator==(unsigned x) const
HexagonBlockRanges(MachineFunction &MF)
PrintRangeMap(const RegToRangeMap &M, const TargetRegisterInfo &I)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
IndexType getPrevIndex(IndexType Idx) const
Representation of each machine instruction.
bool contains(const IndexRange &A) const
RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap)
std::map< RegisterRef, RangeList > RegToRangeMap
IndexType getIndex(MachineInstr *MI) const
void merge(const IndexRange &A)
friend raw_ostream & operator<<(raw_ostream &OS, const InstrIndexMap &Map)
friend raw_ostream & operator<<(raw_ostream &OS, const PrintRangeMap &P)
RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap)
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool operator<(int64_t V1, const APSInt &V2)
void unionize(bool MergeAdjacent=false)
This class implements an extremely fast bulk output stream that can only output to a stream...
bool operator==(uint64_t V1, const APInt &V2)
void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI)
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
InstrIndexMap(MachineBasicBlock &B)
Statically lint checks LLVM IR