31 #define GET_INSTRINFO_CTOR_DTOR
32 #include "XCoreGenInstrInfo.inc"
47 void XCoreInstrInfo::anchor() {}
66 if (Opcode == XCore::LDWFI)
86 if (Opcode == XCore::STWFI)
102 static inline bool IsBRU(
unsigned BrOpc) {
103 return BrOpc == XCore::BRFU_u6
104 || BrOpc == XCore::BRFU_lu6
105 || BrOpc == XCore::BRBU_u6
106 || BrOpc == XCore::BRBU_lu6;
109 static inline bool IsBRT(
unsigned BrOpc) {
110 return BrOpc == XCore::BRFT_ru6
111 || BrOpc == XCore::BRFT_lru6
112 || BrOpc == XCore::BRBT_ru6
113 || BrOpc == XCore::BRBT_lru6;
116 static inline bool IsBRF(
unsigned BrOpc) {
117 return BrOpc == XCore::BRFF_ru6
118 || BrOpc == XCore::BRFF_lru6
119 || BrOpc == XCore::BRBF_ru6
120 || BrOpc == XCore::BRBF_lru6;
138 }
else if (
IsBRF(BrOpc)) {
194 bool AllowModify)
const {
200 if (!isUnpredicatedTerminator(*I))
207 if (I == MBB.
begin() || !isUnpredicatedTerminator(*--I)) {
230 if (SecondLastInst && I != MBB.
begin() && isUnpredicatedTerminator(*--I))
233 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
256 I->eraseFromParent();
264 I->eraseFromParent();
277 int *BytesAdded)
const {
279 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
281 "Unexpected number of components!");
282 assert(!BytesAdded &&
"code size not handled");
298 assert(Cond.
size() == 2 &&
"Unexpected number of components!");
308 assert(!BytesRemoved &&
"code size not handled");
318 I->eraseFromParent();
322 if (I == MBB.
begin())
return 1;
328 I->eraseFromParent();
334 const DebugLoc &DL,
unsigned DestReg,
335 unsigned SrcReg,
bool KillSrc)
const {
336 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
337 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
339 if (GRDest && GRSrc) {
340 BuildMI(MBB, I, DL,
get(XCore::ADD_2rus), DestReg)
346 if (GRDest && SrcReg == XCore::SP) {
347 BuildMI(MBB, I, DL,
get(XCore::LDAWSP_ru6), DestReg).
addImm(0);
351 if (DestReg == XCore::SP && GRSrc) {
352 BuildMI(MBB, I, DL,
get(XCore::SETSP_1r))
361 unsigned SrcReg,
bool isKill,
367 if (I != MBB.
end() && !I->isDebugValue())
368 DL = I->getDebugLoc();
375 BuildMI(MBB, I, DL,
get(XCore::STWFI))
389 if (I != MBB.
end() && !I->isDebugValue())
390 DL = I->getDebugLoc();
397 BuildMI(MBB, I, DL,
get(XCore::LDWFI), DestReg)
406 "Invalid XCore branch condition!");
412 return val < (1 << 6);
416 return val < (1 << 16);
424 return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
430 unsigned Reg, uint64_t
Value)
const {
432 if (MI != MBB.
end() && !MI->isDebugValue())
433 dl = MI->getDebugLoc();
436 return BuildMI(MBB, MI, dl,
get(XCore::MKMSK_rus), Reg)
441 int Opcode =
isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
448 return BuildMI(MBB, MI, dl,
get(XCore::LDWCP_lru6), Reg)
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
static bool IsBRT(unsigned BrOpc)
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
MachineBasicBlock * getMBB() const
static bool isImmMskBitp(unsigned val)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
static XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified condition, e.g.
constexpr bool isMask_32(uint32_t Value)
isMask_32 - This function returns true if the argument is a non-empty sequence of ones starting at th...
A description of a memory reference used in the backend.
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static bool IsBRF(unsigned BrOpc)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
static bool IsBRU(unsigned BrOpc)
static bool isImmU16(unsigned val)
size_t size() const
size - Get the array size.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static bool isImmU6(unsigned val)
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This is an important base class in LLVM.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const
bool empty() const
empty - Check if the array is empty.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc. ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
The memory access writes data.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
const MachineInstrBuilder & addFrameIndex(int Idx) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
static bool IsCondBranch(unsigned BrOpc)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Representation of each machine instruction.
static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
GetCondFromBranchOpc - Return the XCore CC that matches the correspondent Branch instruction opcode...
static IntegerType * getInt32Ty(LLVMContext &C)
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static bool IsBR_JT(unsigned BrOpc)
static bool isZeroImm(const MachineOperand &op)
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one...
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...