45 R600MCCodeEmitter(
const R600MCCodeEmitter &) =
delete;
46 R600MCCodeEmitter &operator=(
const R600MCCodeEmitter &) =
delete;
62 unsigned getHWReg(
unsigned regNo)
const;
87 return new R600MCCodeEmitter(MCII, MRI);
93 verifyInstructionPredicates(MI,
103 }
else if (
IS_VTX(Desc)) {
104 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
107 InstWord2 |= 1 << 19;
110 Emit(InstWord01, OS);
113 }
else if (
IS_TEX(Desc)) {
116 int64_t SrcSelect[4] = {
128 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
131 SrcSelect[
ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
138 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
142 uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
143 Inst &= ~(0x3FFULL << 39);
144 Inst |= ISAOpCode << 1;
162 uint64_t R600MCCodeEmitter::getMachineOpValue(
const MCInst &MI,
168 return MRI.getEncodingValue(MO.
getReg());
179 const unsigned offset = (&MO == &MI.
getOperand(0)) ? 0 : 4;
188 #define ENABLE_INSTR_PREDICATE_VERIFIER
189 #include "AMDGPUGenMCCodeEmitter.inc"
void push_back(const T &Elt)
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
A four-byte section relative fixup.
#define HAS_NATIVE_OPERANDS(Flags)
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
#define HW_REG_MASK
Defines for extracting register information from register encoding.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
static void write(bool isBE, void *P, T V)
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
Provides AMDGPU specific target descriptions.
MCSubtargetInfo - Generic base class for all target subtargets.
CodeEmitter interface for R600 and SI codegen.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream...
static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr)
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const