58 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
86 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
110 "Can't handle non-64 bits locations");
113 unsigned size = (LocVT ==
MVT::f128) ? 16 : 8;
114 unsigned alignment = (LocVT ==
MVT::f128) ? 16 : 8;
118 if (LocVT ==
MVT::i64 && Offset < 6*8)
120 Reg = SP::I0 + Offset/8;
121 else if (LocVT ==
MVT::f64 && Offset < 16*8)
123 Reg = SP::D0 + Offset/8;
124 else if (LocVT ==
MVT::f32 && Offset < 16*8)
126 Reg = SP::F1 + Offset/4;
127 else if (LocVT ==
MVT::f128 && Offset < 16*8)
129 Reg = SP::Q0 + Offset/16;
156 if (LocVT ==
MVT::f32 && Offset < 16*8) {
163 if (LocVT ==
MVT::i32 && Offset < 6*8) {
165 unsigned Reg = SP::I0 + Offset/8;
182 #include "SparcGenCallingConv.inc"
188 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
190 if (Reg >= SP::I0 && Reg <= SP::I7)
191 return Reg - SP::I0 + SP::O0;
202 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
203 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
230 for (
unsigned i = 0, realRVLocIdx = 0;
232 ++
i, ++realRVLocIdx) {
236 SDValue Arg = OutVals[realRVLocIdx];
264 unsigned RetAddrOffset = 8;
315 for (
unsigned i = 0;
i != RVLocs.
size(); ++
i) {
344 if (
i+1 < RVLocs.
size() && RVLocs[
i+1].getLocReg() == VA.
getLocReg()) {
396 const unsigned StackOffset = 92;
400 for (
unsigned i = 0, e = ArgLocs.size();
i != e; ++
i, ++InIdx) {
403 if (Ins[InIdx].
Flags.isSRet()) {
434 &SP::IntRegsRegClass);
469 if (Offset % 8 == 0) {
536 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
538 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
539 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
540 unsigned ArgOffset = CCInfo.getNextStackOffset();
541 if (NumAllocated == 6)
542 ArgOffset += StackOffset;
545 ArgOffset = 68+4*NumAllocated;
551 std::vector<SDValue> OutChains;
553 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
567 if (!OutChains.empty()) {
568 OutChains.push_back(Chain);
590 const unsigned ArgArea = 128;
592 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
641 Offset += 8 - ValSize;
659 unsigned ArgOffset = CCInfo.getNextStackOffset();
669 for (; ArgOffset < 6*8; ArgOffset += 8) {
670 unsigned VReg = MF.
addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
679 if (!OutChains.
empty())
696 return CS->
hasFnAttr(Attribute::ReturnsTwice);
702 dyn_cast<ExternalSymbolSDNode>(Callee)) {
705 const char *CalleeName =
E->getSymbol();
739 unsigned ArgsSize = CCInfo.getNextStackOffset();
742 ArgsSize = (ArgsSize+7) & ~7;
748 for (
unsigned i = 0, e = Outs.
size();
i != e; ++
i) {
762 Chain = DAG.
getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
781 const unsigned StackOffset = 92;
782 bool hasStructRetAttr =
false;
784 for (
unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.
size();
788 SDValue Arg = OutVals[realArgIdx];
794 Arg = ByValArgs[byvalArgIdx++];
826 hasStructRetAttr =
true;
836 if (Offset % 8 == 0) {
921 if (!MemOpChains.
empty())
929 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i) {
931 Chain = DAG.
getCopyToReg(Chain, dl, Reg, RegsToPass[
i].second, InFlag);
935 unsigned SRetArgSize = (hasStructRetAttr)?
getSRetArgSize(DAG, Callee):0;
952 if (hasStructRetAttr)
954 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i)
956 RegsToPass[
i].second.getValueType()));
964 assert(Mask &&
"Missing call preserved mask for calling convention");
985 for (
unsigned i = 0;
i != RVLocs.
size(); ++
i) {
1004 RVLocs[
i].getValVT(), InFlag)
1019 .Case(
"i0", SP::I0).
Case(
"i1", SP::I1).
Case(
"i2", SP::I2).
Case(
"i3", SP::I3)
1020 .
Case(
"i4", SP::I4).
Case(
"i5", SP::I5).
Case(
"i6", SP::I6).
Case(
"i7", SP::I7)
1021 .
Case(
"o0", SP::O0).
Case(
"o1", SP::O1).
Case(
"o2", SP::O2).
Case(
"o3", SP::O3)
1022 .
Case(
"o4", SP::O4).
Case(
"o5", SP::O5).
Case(
"o6", SP::O6).
Case(
"o7", SP::O7)
1023 .
Case(
"l0", SP::L0).
Case(
"l1", SP::L1).
Case(
"l2", SP::L2).
Case(
"l3", SP::L3)
1024 .
Case(
"l4", SP::L4).
Case(
"l5", SP::L5).
Case(
"l6", SP::L6).
Case(
"l7", SP::L7)
1025 .
Case(
"g0", SP::G0).
Case(
"g1", SP::G1).
Case(
"g2", SP::G2).
Case(
"g3", SP::G3)
1026 .
Case(
"g4", SP::G4).
Case(
"g5", SP::G5).
Case(
"g6", SP::G6).
Case(
"g7", SP::G7)
1039 static const char *
const ABICalls[] =
1040 {
"_Q_add",
"_Q_sub",
"_Q_mul",
"_Q_div",
1041 "_Q_sqrt",
"_Q_neg",
1042 "_Q_itoq",
"_Q_stoq",
"_Q_dtoq",
"_Q_utoq",
1043 "_Q_lltoq",
"_Q_ulltoq",
1046 for (
const char *
const *
I = ABICalls; *
I !=
nullptr; ++
I)
1047 if (
strcmp(CalleeName, *
I) == 0)
1055 const Function *CalleeFn =
nullptr;
1059 dyn_cast<ExternalSymbolSDNode>(Callee)) {
1062 const char *CalleeName =
E->getSymbol();
1090 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
1105 unsigned firstReg = (ValTy ==
MVT::f64) ? SP::D0 : SP::Q0;
1106 unsigned argSize = (ValTy ==
MVT::f64) ? 8 : 16;
1108 assert(Offset < 16*8 &&
"Offset out of range, bad register enum?");
1112 unsigned IReg = SP::I0 + Offset/8;
1155 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1158 ArgsSize =
alignTo(ArgsSize, 16);
1180 for (
unsigned i = 0, e = ArgLocs.
size();
i != e; ++
i) {
1243 if (
i+1 < ArgLocs.
size() && ArgLocs[
i+1].isRegLoc() &&
1244 ArgLocs[
i+1].getLocReg() == VA.
getLocReg()) {
1271 if (!MemOpChains.
empty())
1279 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i) {
1281 RegsToPass[
i].first, RegsToPass[
i].second, InGlue);
1300 for (
unsigned i = 0, e = RegsToPass.
size();
i != e; ++
i)
1302 RegsToPass[i].second.getValueType()));
1310 assert(Mask &&
"Missing call preserved mask for calling convention");
1339 CLI.
Ins[0].Flags.setInReg();
1341 RVInfo.AnalyzeCallResult(CLI.
Ins, RetCC_Sparc64);
1344 for (
unsigned i = 0; i != RVLocs.
size(); ++
i) {
1357 if (!RV.getNode()) {
1358 RV = DAG.
getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1620 if (Subtarget->
isV9())
1651 if (!Subtarget->
isV9()) {
1742 if (Subtarget->
isV9()) {
1881 unsigned Depth)
const {
1882 APInt KnownZero2, KnownOne2;
1894 KnownOne &= KnownOne2;
1895 KnownZero &= KnownZero2;
1914 SPCC = cast<ConstantSDNode>(LHS.
getOperand(2))->getZExtValue();
1926 GA->getValueType(0),
1927 GA->getOffset(), TF);
1931 CP->getValueType(0),
1933 CP->getOffset(), TF);
1943 ES->getValueType(0), TF);
1951 unsigned HiTF,
unsigned LoTF,
2061 Chain = DAG.
getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2069 assert(Mask &&
"Missing call preserved mask for calling convention");
2152 Args.push_back(Entry);
2158 const char *LibFuncName,
2159 unsigned numArgs)
const {
2168 Type *RetTyABI = RetTy;
2177 Entry.
Node = RetPtr;
2182 Args.push_back(Entry);
2187 for (
unsigned i = 0, e = numArgs;
i != e; ++
i) {
2194 std::pair<SDValue, SDValue> CallInfo =
LowerCallTo(CLI);
2197 if (RetTyABI == RetTy)
2198 return CallInfo.first;
2202 Chain = CallInfo.second;
2210 unsigned &SPCC,
const SDLoc &DL,
2213 const char *
LibCall =
nullptr;
2217 case SPCC::FCC_E : LibCall = is64Bit?
"_Qp_feq" :
"_Q_feq";
break;
2218 case SPCC::FCC_NE : LibCall = is64Bit?
"_Qp_fne" :
"_Q_fne";
break;
2219 case SPCC::FCC_L : LibCall = is64Bit?
"_Qp_flt" :
"_Q_flt";
break;
2220 case SPCC::FCC_G : LibCall = is64Bit?
"_Qp_fgt" :
"_Q_fgt";
break;
2221 case SPCC::FCC_LE : LibCall = is64Bit?
"_Qp_fle" :
"_Q_fle";
break;
2222 case SPCC::FCC_GE : LibCall = is64Bit?
"_Qp_fge" :
"_Q_fge";
break;
2230 case SPCC::FCC_UE : LibCall = is64Bit?
"_Qp_cmp" :
"_Q_cmp";
break;
2245 std::pair<SDValue, SDValue> CallInfo =
LowerCallTo(CLI);
2248 SDValue Result = CallInfo.first;
2446 unsigned Opc, SPCC = ~0U;
2483 unsigned Opc, SPCC = ~0U;
2550 const Value *SV = cast<SrcValueSDNode>(Node->
getOperand(2))->getValue();
2571 unsigned Align = cast<ConstantSDNode>(Op.
getOperand(2))->getZExtValue();
2579 if (Align > StackAlign) {
2582 "over-aligned dynamic alloca not supported.");
2587 unsigned regSpillArea;
2617 unsigned SPReg = SP::O6;
2626 SDValue Ops[2] = { NewVal, Chain };
2645 unsigned FrameReg = SP::I6;
2662 unsigned Offset = (Subtarget->
is64Bit()) ? (stackBias + 112) : 56;
2759 &&
"Unexpected node type");
2813 &&
"Unexpected node type");
2869 &&
"invalid opcode");
2884 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl,
MVT::f64,
2886 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl,
MVT::f64,
2889 if (DAG.getDataLayout().isLittleEndian()) {
2901 SDValue DstReg128 =
SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2903 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl,
MVT::f128,
2905 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl,
MVT::f128,
2929 bool hasChain =
false;
2955 SDValue Ops[2] = { Dst, Carry };
2985 Args, isSigned, dl).first;
3001 assert(MulResult->
use_empty() &&
"Illegally typed node still in use!");
3003 SDValue Ops[2] = { BottomHalf, TopHalf } ;
3018 unsigned IntNo = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
3022 case Intrinsic::thread_pointer: {
3033 bool isV9 = Subtarget->
isV9();
3098 case SP::SELECT_CC_Int_ICC:
3099 case SP::SELECT_CC_FP_ICC:
3100 case SP::SELECT_CC_DFP_ICC:
3101 case SP::SELECT_CC_QFP_ICC:
3103 case SP::SELECT_CC_Int_FCC:
3104 case SP::SELECT_CC_FP_FCC:
3105 case SP::SELECT_CC_DFP_FCC:
3106 case SP::SELECT_CC_QFP_FCC:
3108 case SP::EH_SJLJ_SETJMP32ri:
3109 case SP::EH_SJLJ_SETJMP32rr:
3111 case SP::EH_SJLJ_LONGJMP32rr:
3112 case SP::EH_SJLJ_LONGJMP32ri:
3120 unsigned BROpcode)
const {
3199 const unsigned FP = SP::I6;
3200 MIB =
BuildMI(*MBB, MI, DL, TII->
get(SP::LDri))
3206 MIB =
BuildMI(*MBB, MI, DL, TII->
get(SP::LDri))
3212 const unsigned SP = SP::O6;
3213 MIB =
BuildMI(*MBB, MI, DL, TII->
get(SP::LDri))
3219 MIB =
BuildMI(*MBB, MI, DL, TII->
get(SP::LDri))
3280 MF->
insert(It, restoreMBB);
3295 const unsigned FP = SP::I6;
3296 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::STri))
3302 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::SETHIi))
3306 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::ORri))
3311 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::STri))
3317 const unsigned SP = SP::O6;
3318 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::STri))
3324 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::STri))
3335 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::BCOND))
3339 MIB =
BuildMI(thisMBB, DL, TII->
get(SP::BCOND))
3348 MIB =
BuildMI(mainMBB, DL, TII->
get(SP::ORrr))
3358 MIB =
BuildMI(restoreMBB, DL, TII->
get(SP::ORri))
3367 TII->
get(SP::PHI), DstReg)
3368 .addReg(mainDstReg).
addMBB(mainMBB)
3383 if (Constraint.
size() == 1) {
3384 switch (Constraint[0]) {
3397 const char *constraint)
const {
3402 if (!CallOperandVal)
3406 switch (*constraint) {
3412 if (isInt<13>(
C->getSExtValue()))
3424 std::string &Constraint,
3425 std::vector<SDValue> &Ops,
3430 if (Constraint.length() > 1)
3433 char ConstraintLetter = Constraint[0];
3434 switch (ConstraintLetter) {
3438 if (isInt<13>(
C->getSExtValue())) {
3448 Ops.push_back(Result);
3454 std::pair<unsigned, const TargetRegisterClass *>
3458 if (Constraint.
size() == 1) {
3459 switch (Constraint[0]) {
3462 return std::make_pair(0U, &SP::IntPairRegClass);
3464 return std::make_pair(0U, &SP::IntRegsRegClass);
3466 }
else if (!Constraint.
empty() && Constraint.
size() <= 5
3467 && Constraint[0] ==
'{' && *(Constraint.
end()-1) ==
'}') {
3476 uint64_t intVal = 0;
3477 if (
name.substr(0, 1).equals(
"r")
3478 && !
name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3479 const char regTypes[] = {
'g',
'o',
'l',
'i' };
3480 char regType = regTypes[intVal/8];
3481 char regIdx =
'0' + (intVal % 8);
3482 char tmp[] = {
'{', regType, regIdx,
'}', 0 };
3483 std::string newConstraint = std::string(tmp);
3508 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void setFrameAddressIsTaken(bool T)
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
bool use_empty() const
Return true if there are no uses of this node.
static MVT getIntegerVT(unsigned BitWidth)
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
void push_back(const T &Elt)
BUILTIN_OP_END - This must be the last enum value in this list.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
SDValue getValue(unsigned R) const
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Flags getFlags() const
Return the raw flags of the source value,.
LLVMContext * getContext() const
LLVM Argument representation.
DiagnosticInfoOptimizationBase::Argument NV
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd)...
static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC)
IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC condition.
BR_CC - Conditional branch.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
LocInfo getLocInfo() const
unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG)
A Module instance is used to store all the information related to an LLVM module. ...
const TargetMachine & getTargetMachine() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
Carry-setting nodes for multiple precision addition and subtraction.
const TargetMachine & getTarget() const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
bool fixAllFDIVSQRT() const
const GlobalValue * getGlobal() const
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
unsigned getByValSize() const
unsigned getNumOperands() const
Return the number of values used by this operation.
static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
const SDValue & getOperand(unsigned Num) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Type * getElementType() const
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
const SparcInstrInfo * getInstrInfo() const override
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with strcmp
unsigned getValNo() const
const SDValue & getBasePtr() const
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool useSoftFloat() const override
SDValue getExternalSymbol(const char *Sym, EVT VT)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
bool replaceFMULS() const
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
static SDValue LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9)
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) const
struct fuzzer::@269 Flags
const uint32_t * getRTCallPreservedMask(CallingConv::ID CC) const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static SDValue LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
const HexagonInstrInfo * TII
static void fixupVariableFloatArgs(SmallVectorImpl< CCValAssign > &ArgLocs, ArrayRef< ISD::OutputArg > Outs)
Shift and rotation operations.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
MachineFunction & getMachineFunction() const
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
Reg
All possible values of the reg field in the ModR/M byte.
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
bool isPositionIndependent() const
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_NODISCARD bool empty() const
SmallVector< ISD::InputArg, 32 > Ins
STACKSAVE - STACKSAVE has one operand, an input chain.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC)
static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
unsigned getLocReg() const
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
SDValue getRegisterMask(const uint32_t *RegMask)
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI)
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
void setSRetReturnReg(unsigned Reg)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
SmallVector< ISD::OutputArg, 32 > Outs
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isLittleEndian() const
Layout endianness...
const SDValue & getBasePtr() const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
static mvt_range integer_vector_valuetypes()
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Class to represent pointers.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
TargetInstrInfo - Interface to description of machine instruction set.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
int getVarArgsFrameOffset() const
A switch()-like statement whose cases are string literals.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned const MachineRegisterInfo * MRI
CodeModel::Model getCodeModel() const
Returns the code model.
MVT - Machine Value Type.
static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
LLVM Basic Block Representation.
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
Simple binary floating point operators.
C - The default llvm calling convention, compatible with C.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
static bool is64Bit(const char *name)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const MachineOperand & getOperand(unsigned i) const
Carry-using nodes for multiple precision addition and subtraction.
static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, ImmutableCallSite *CS)
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
static mvt_range fp_valuetypes()
static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG)
unsigned getSRetReturnReg() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
static Type * getVoidTy(LLVMContext &C)
unsigned getBitWidth() const
Return the number of bits in the APInt.
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
unsigned getOpcode() const
TRAP - Trapping instruction.
bool hasFnAttr(Attribute::AttrKind Kind) const
Return true if this function has the given attribute.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
MachineBasicBlock * expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const
self_iterator getIterator()
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
const SDValue & getValue() const
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
EVT - Extended Value Type.
bool isFP128Ty() const
Return true if this is 'fp128'.
void setVarArgsFrameOffset(int Offset)
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
This class contains a discriminated union of information about pointers in memory operands...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
const SparcRegisterInfo * getRegisterInfo() const override
const MachinePointerInfo & getPointerInfo() const
const TargetFrameLowering * getFrameLowering() const override
unsigned getByValAlign() const
const SDValue & getOffset() const
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
TokenFactor - This node takes multiple tokens as input and produces a single token result...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the generic address space (address sp...
This is the shared class of boolean and integer constants.
static bool isFP128ABICall(const char *CalleeName)
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
static bool isStrongerThanMonotonic(AtomicOrdering ao)
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isTargetLinux() const
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
CCValAssign - Represent assignment of one arg/retval to a location.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
BRCOND - Conditional branch.
const SDValue & getChain() const
Byte Swap and Counting operators.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
BinOp getOperation() const
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG)
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL)
Return a new CALLSEQ_START node, which always must have a glue result (to ensure it's not CSE'd)...
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI)
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
Select(COND, TRUEVAL, FALSEVAL).
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
unsigned EmulatedTLS
EmulatedTLS - This flag enables emulated TLS model, using emutls function in the runtime library...
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
ZERO_EXTEND - Used for integer types, zeroing the new bits.
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC)
FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC FCC condition.
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
BR_JT - Jumptable branch.
Representation of each machine instruction.
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) const
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
uint64_t getConstantOperandVal(unsigned i) const
SmallVector< SDValue, 32 > OutVals
Bitwise operators - logical and, logical or, logical xor.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static IntegerType * getInt32Ty(LLVMContext &C)
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
ImmutableCallSite - establish a view to a call site for examination.
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
const SDValue & getOffset() const
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
FSINCOS - Compute both fsin and fcos as a single operation.
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.setjmp intrinsic.
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
unsigned getPointerSize() const
Get the pointer size for this target.
unsigned getReg() const
getReg - Returns the register number.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
void insert(iterator MBBI, MachineBasicBlock *MBB)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
void setReturnAddressIsTaken(bool s)
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
SDValue getRegister(unsigned Reg, EVT VT)
static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Primary interface to the complete machine description for the target machine.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
SetCC operator - This evaluates to a true value iff the condition is true.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
int64_t getStackPointerBias() const
The 64-bit ABI uses biased stack and frame pointers, so the stack frame of the current function is th...
unsigned getLocMemOffset() const
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, unsigned opcode)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
TRUNCATE - Completely drop the high bits.
unsigned getAlignment() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
static unsigned toCallerWindow(unsigned Reg)
EVT changeVectorElementTypeToInteger() const
changeVectorElementTypeToInteger - Return a vector with the same number of elements as this vector...
static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
bool useSoftFloat() const
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...