LLVM  4.0.0
HexagonBaseInfo.h
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1 //===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains small standalone helper functions and enum definitions for
11 // the Hexagon target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
18 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
19 
20 #include "HexagonMCTargetDesc.h"
22 #include <stdint.h>
23 
24 namespace llvm {
25 
26 /// HexagonII - This namespace holds all of the target specific flags that
27 /// instruction info tracks.
28 ///
29 namespace HexagonII {
30  // *** The code below must match HexagonInstrFormat*.td *** //
31 
32  // Insn types.
33  // *** Must match HexagonInstrFormat*.td ***
34  enum Type {
36  TypeALU32 = 1,
37  TypeCR = 2,
38  TypeJR = 3,
39  TypeJ = 4,
40  TypeLD = 5,
41  TypeST = 6,
43  TypeXTYPE = 8,
45  TypeNV = 10,
46  TypeDUPLEX = 11,
51  TypeCVI_VX = 15,
53  TypeCVI_VP = 17,
55  TypeCVI_VS = 19,
66  TypePREFIX = 30, // Such as extenders.
67  TypeENDLOOP = 31 // Such as end of a HW loop.
68  };
69 
70  enum SubTarget {
71  HasV2SubT = 0xf,
73  NoV2SubT = 0x0,
74  HasV3SubT = 0xe,
76  NoV3SubT = 0x1,
77  HasV4SubT = 0xc,
78  NoV4SubT = 0x3,
79  HasV5SubT = 0x8,
80  NoV5SubT = 0x7
81  };
82 
83  enum AddrMode {
84  NoAddrMode = 0, // No addressing mode
85  Absolute = 1, // Absolute addressing mode
86  AbsoluteSet = 2, // Absolute set addressing mode
87  BaseImmOffset = 3, // Indirect with offset
88  BaseLongOffset = 4, // Indirect with long offset
89  BaseRegOffset = 5, // Indirect with register offset
90  PostInc = 6 // Post increment addressing mode
91  };
92 
93  // MemAccessSize is represented as 1+log2(N) where N is size in bits.
94  enum class MemAccessSize {
95  NoMemAccess = 0, // Not a memory access instruction.
96  ByteAccess = 1, // Byte access instruction (memb).
97  HalfWordAccess = 2, // Half word access instruction (memh).
98  WordAccess = 3, // Word access instruction (memw).
99  DoubleWordAccess = 4, // Double word access instruction (memd)
100  // 5, // We do not have a 16 byte vector access.
101  Vector64Access = 7, // 64 Byte vector access instruction (vmem).
102  Vector128Access = 8 // 128 Byte vector access instruction (vmem).
103  };
104 
105  // MCInstrDesc TSFlags
106  // *** Must match HexagonInstrFormat*.td ***
107  enum {
108  // This 5-bit field describes the insn type.
109  TypePos = 0,
110  TypeMask = 0x1f,
111 
112  // Solo instructions.
113  SoloPos = 5,
114  SoloMask = 0x1,
115  // Packed only with A or X-type instructions.
117  SoloAXMask = 0x1,
118  // Only A-type instruction in first slot or nothing.
121 
122  // Predicated instructions.
131 
132  // New-Value consumer instructions.
135  // New-Value producer instructions.
138  // Which operand consumes or produces a new value.
141  // Stores that can become new-value stores.
144  // New-value store instructions.
146  NVStoreMask = 0x1,
147  // Loads that can become current-value loads.
150  // Current-value load instructions.
151  CVLoadPos = 20,
152  CVLoadMask = 0x1,
153 
154  // Extendable insns.
157  // Insns must be extended.
160  // Which operand may be extended.
163  // Signed or unsigned range.
166  // Number of bits of range before extending operand.
169  // Alignment power-of-two before extending operand.
172 
173  // Valid subtargets
176 
177  // Addressing mode for load/store instructions.
180  // Access size for load/store instructions.
183 
184  // Branch predicted taken.
185  TakenPos = 47,
186  TakenMask = 0x1,
187 
188  // Floating-point instructions.
189  FPPos = 48,
190  FPMask = 0x1,
191 
192  // New-Value producer-2 instructions.
195 
196  // Which operand consumes or produces a new value.
199 
200  // Accumulator instructions.
203 
204  // Complex XU, prevent xu competition by preferring slot3
207 
210  };
211 
212  // *** The code above must match HexagonInstrFormat*.td *** //
213 
214  // Hexagon specific MO operand flag mask.
216  //===------------------------------------------------------------------===//
217  // Hexagon Specific MachineOperand flags.
219 
221 
222  /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
223  /// Used for computing a global address for PIC compilations
225 
226  /// MO_GOT - Indicates a GOT-relative relocation
228 
229  // Low or high part of a symbol.
231 
232  // Offset from the base of the SDA.
234 
235  // MO_GDGOT - indicates GOT relative relocation for TLS
236  // GeneralDynamic method
238 
239  // MO_GDPLT - indicates PLT relative relocation for TLS
240  // GeneralDynamic method
242 
243  // MO_IE - indicates non PIC relocation for TLS
244  // Initial Executable method
246 
247  // MO_IEGOT - indicates PIC relocation for TLS
248  // Initial Executable method
250 
251  // MO_TPREL - indicates relocation for TLS
252  // local Executable method
254  };
255 
256  // Hexagon Sub-instruction classes.
265  };
266 
267  // Hexagon Compound classes.
269  HCG_None = 0,
273  };
274 
276  INST_PARSE_MASK = 0x0000c000,
277  INST_PARSE_PACKET_END = 0x0000c000,
278  INST_PARSE_LOOP_END = 0x00008000,
279  INST_PARSE_NOT_END = 0x00004000,
280  INST_PARSE_DUPLEX = 0x00000000,
281  INST_PARSE_EXTENDER = 0x00000000
282  };
283 
284  enum InstIClassBits : unsigned {
285  INST_ICLASS_MASK = 0xf0000000,
286  INST_ICLASS_EXTENDER = 0x00000000,
287  INST_ICLASS_J_1 = 0x10000000,
288  INST_ICLASS_J_2 = 0x20000000,
289  INST_ICLASS_LD_ST_1 = 0x30000000,
290  INST_ICLASS_LD_ST_2 = 0x40000000,
291  INST_ICLASS_J_3 = 0x50000000,
292  INST_ICLASS_CR = 0x60000000,
293  INST_ICLASS_ALU32_1 = 0x70000000,
294  INST_ICLASS_XTYPE_1 = 0x80000000,
295  INST_ICLASS_LD = 0x90000000,
296  INST_ICLASS_ST = 0xa0000000,
297  INST_ICLASS_ALU32_2 = 0xb0000000,
298  INST_ICLASS_XTYPE_2 = 0xc0000000,
299  INST_ICLASS_XTYPE_3 = 0xd0000000,
300  INST_ICLASS_XTYPE_4 = 0xe0000000,
301  INST_ICLASS_ALU32_3 = 0xf0000000
302  };
303 
304 } // End namespace HexagonII.
305 
306 } // End namespace llvm.
307 
308 #endif
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
MO_GOT - Indicates a GOT-relative relocation.