17 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
18 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
32 uint16_t LastCostChange;
33 std::unique_ptr<MCPhysReg[]> Order;
36 :
Tag(0), NumRegs(0), ProperSubClass(
false), MinCost(0),
45 std::unique_ptr<RCInfo[]> RegClass;
64 std::unique_ptr<unsigned[]> PSetLimits;
71 const RCInfo &RCI = RegClass[RC->
getID()];
87 return get(RC).NumRegs;
104 return get(RC).ProperSubClass;
111 if (
unsigned N = CSRNum[PhysReg])
112 return CalleeSaved[
N-1];
120 return get(RC).MinCost;
128 return get(RC).LastCostChange;
135 if (!PSetLimits[Idx])
137 return PSetLimits[Idx];
unsigned getLastCalleeSavedAlias(unsigned PhysReg) const
getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
unsigned getLastCostChange(const TargetRegisterClass *RC)
Get the position of the last cost change in getOrder(RC).
unsigned getRegPressureSetLimit(unsigned Idx) const
Get the register unit limit for the given pressure set index.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isProperSubClass(const TargetRegisterClass *RC) const
isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers...
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
unsigned getMinCost(const TargetRegisterClass *RC)
Get the minimum register cost in RC's allocation order.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())