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LLVM
4.0.0
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#include <HexagonMCCodeEmitter.h>
Additional Inherited Members | |
Protected Member Functions inherited from llvm::MCCodeEmitter | |
| MCCodeEmitter () | |
Definition at line 28 of file HexagonMCCodeEmitter.h.
| HexagonMCCodeEmitter::HexagonMCCodeEmitter | ( | MCInstrInfo const & | aMII, |
| MCContext & | aMCT | ||
| ) |
Definition at line 35 of file HexagonMCCodeEmitter.cpp.
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overridevirtual |
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Implements llvm::MCCodeEmitter.
Definition at line 67 of file HexagonMCCodeEmitter.cpp.
References assert(), llvm::HexagonMCInstrInfo::bundleInstructions(), llvm::HexagonMCInstrInfo::bundleSize(), llvm::dbgs(), DEBUG, EncodeSingleInstruction(), llvm::MCSubtargetInfo::getFeatureBits(), HEXAGON_INSTR_SIZE, I, llvm::HexagonMCInstrInfo::isBundle(), llvm::HexagonMCInstrInfo::isImmext(), MI, and parseBits().
| void HexagonMCCodeEmitter::EncodeSingleInstruction | ( | const MCInst & | MI, |
| raw_ostream & | OS, | ||
| SmallVectorImpl< MCFixup > & | Fixups, | ||
| const MCSubtargetInfo & | STI, | ||
| uint32_t | Parse, | ||
| size_t | Index | ||
| ) | const |
EncodeSingleInstruction - Emit a single.
Definition at line 108 of file HexagonMCCodeEmitter.cpp.
References assert(), llvm::HexagonMCInstrInfo::bundleInstructions(), llvm::dbgs(), DEBUG, getBinaryCodeForInstr(), llvm::HexagonMCInstrInfo::getDesc(), llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getInst(), llvm::HexagonMCInstrInfo::getName(), llvm::HexagonMCInstrInfo::getNewValueOp(), llvm::HexagonMCInstrInfo::getNewValueOperand(), llvm::HexagonMCInstrInfo::getNewValueOperand2(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::MCContext::getRegisterInfo(), llvm::HexagonMCInstrInfo::getType(), llvm::HexagonMCInstrInfo::hasNewValue(), llvm::HexagonMCInstrInfo::hasNewValue2(), i, llvm::HexagonII::INST_PARSE_DUPLEX, llvm::HexagonMCInstrInfo::isBundle(), llvm::HexagonMCInstrInfo::isImmext(), llvm::HexagonMCInstrInfo::isNewValue(), llvm::HexagonMCInstrInfo::isPredicated(), llvm::HexagonMCInstrInfo::isPredicatedTrue(), llvm::MCOperand::isReg(), llvm::HexagonMCInstrInfo::isVector(), llvm_unreachable, MI, Offset, Register, RegisterMatches(), llvm::MCOperand::setReg(), llvm::HexagonMCInstrInfo::SubregisterBit(), and llvm::HexagonII::TypeCOMPOUND.
Referenced by encodeInstruction().
| uint64_t llvm::HexagonMCCodeEmitter::getBinaryCodeForInstr | ( | MCInst const & | MI, |
| SmallVectorImpl< MCFixup > & | Fixups, | ||
| MCSubtargetInfo const & | STI | ||
| ) | const |
Referenced by EncodeSingleInstruction().
| unsigned HexagonMCCodeEmitter::getMachineOpValue | ( | MCInst const & | MI, |
| MCOperand const & | MO, | ||
| SmallVectorImpl< MCFixup > & | Fixups, | ||
| MCSubtargetInfo const & | STI | ||
| ) | const |
Return binary encoding of operand.
Definition at line 795 of file HexagonMCCodeEmitter.cpp.
References assert(), llvm::HexagonMCInstrInfo::getDuplexRegisterNumbering(), llvm::MCRegisterInfo::getEncodingValue(), llvm::MCOperand::getExpr(), llvm::MCInst::getOpcode(), llvm::MCOperand::getReg(), llvm::MCContext::getRegisterInfo(), llvm::MCOperand::isImm(), llvm::MCOperand::isReg(), and llvm::HexagonMCInstrInfo::isSubInstruction().
| uint32_t HexagonMCCodeEmitter::parseBits | ( | size_t | Instruction, |
| size_t | Last, | ||
| MCInst const & | MCB, | ||
| MCInst const & | MCI | ||
| ) | const |
Definition at line 40 of file HexagonMCCodeEmitter.cpp.
References assert(), llvm::HexagonII::INST_PARSE_DUPLEX, llvm::HexagonII::INST_PARSE_LOOP_END, llvm::HexagonII::INST_PARSE_NOT_END, llvm::HexagonII::INST_PARSE_PACKET_END, llvm::HexagonMCInstrInfo::isDuplex(), llvm::HexagonMCInstrInfo::isInnerLoop(), and llvm::HexagonMCInstrInfo::isOuterLoop().
Referenced by encodeInstruction().
1.8.6