16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
32 class MachineFunction;
34 template<
class T>
class SmallVectorImpl;
91 bool contains(
unsigned Reg1,
unsigned Reg2)
const {
250 const char *
const *SubRegIndexNames;
261 const char *
const *SRINames,
287 return int(Reg) >= (1 << 30);
293 return int(Reg - (1u << 30));
298 assert(FI >= 0 &&
"Cannot hold a negative frame index.");
299 return FI + (1u << 30);
320 return Reg & ~(1u << 31);
326 return Index | (1u << 31);
361 "This is not a subregister index");
362 return SubRegIndexNames[SubIdx-1];
371 return SubRegIndexLaneMasks[SubIdx];
402 if (regA == regB)
return true;
410 if (*RUA == *RUB)
return true;
411 if (*RUA < *RUB) ++RUA;
420 if (*Units == RegUnit)
514 unsigned SrcSubReg)
const;
530 assert(Idx == 0 &&
"Target has no sub-registers");
579 static void dumpReg(
unsigned Reg,
unsigned SubRegIndex = 0,
626 unsigned &PreA,
unsigned &PreB)
const;
645 return RegClassBegin[
i];
708 unsigned PSetID)
const {
728 unsigned Idx)
const = 0;
825 int &FrameIdx)
const {
861 unsigned BaseReg,
int FrameIdx,
890 unsigned Reg)
const {
902 int SPAdj,
unsigned FIOperandNum,
962 const unsigned RCMaskWords;
972 bool IncludeSelf =
false)
973 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
975 Idx(RC->getSuperRegIndices()),
976 Mask(RC->getSubClassMask()) {
1011 const unsigned NumRegClasses;
1027 void moveToNextID() {
1031 while (!CurrentChunk) {
1034 if (Base >= NumRegClasses) {
1038 CurrentChunk = *++Mask;
1060 void moveNBits(
unsigned NumBits) {
1061 assert(NumBits < 32 &&
"Undefined behavior spotted!");
1063 CurrentChunk >>= NumBits;
1074 : NumRegClasses(TRI.getNumRegClasses()), Base(0), Idx(0), ID(0),
1075 Mask(Mask), CurrentChunk(*Mask) {
1110 Printable
PrintReg(
unsigned Reg,
const TargetRegisterInfo *TRI =
nullptr,
1111 unsigned SubRegIdx = 0);
1125 Printable
PrintVRegOrUnit(
unsigned VRegOrUnit,
const TargetRegisterInfo *TRI);
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
const MCPhysReg * const_iterator
unsigned getID() const
Returns the current register class ID.
virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
vt_iterator vt_end() const
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
virtual StringRef getRegAsmName(unsigned Reg) const
Return the assembly name for Reg.
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const
Spill the register so it can be used by the register scavenger.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
unsigned getRegister(unsigned i) const
Return the specified register in the class.
unsigned operator()(unsigned Reg) const
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
virtual ~TargetRegisterInfo()
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const
Mark a register and all its aliases as reserved in the given set.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const
Subtarget Hooks.
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
regclass_iterator regclass_end() const
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time...
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
const uint32_t * SubClassMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
const MCPhysReg * iterator
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const uint16_t * SuperRegIndices
unsigned getNumRegClasses() const
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
unsigned getSubReg() const
Returns the current sub-register index.
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
const char * getRegClassName(const MCRegisterClass *Class) const
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
void operator++()
Advance iterator to the next entry.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
unsigned getID() const
getID() - Return the register class ID number.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx before insertion point I...
MCRegisterClass - Base class of TargetRegisterClass.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
bool isInAllocatableClass(unsigned RegNo) const
Return true if the register is in the allocation of any register class.
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger. ...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass...
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
bool regsOverlap(unsigned regA, unsigned regB) const
Returns true if the two registers are equal or alias each other.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
regclass_iterator regclass_begin() const
Register class iterators.
bool contains(unsigned Reg1, unsigned Reg2) const
Return true if both registers are in this class.
MVT - Machine Value Type.
const sc_iterator SuperClasses
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
MachineInstrBuilder & UseMI
unsigned getCostPerUse(unsigned RegNo) const
Return the additional cost of using this register instead of other registers in its class...
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
unsigned getSize() const
getSize - Return the size of the register in bytes, which is also the size of a stack slot allocated ...
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well...
virtual ArrayRef< const char * > getRegMaskNames() const =0
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
const TargetRegisterClass *const * sc_iterator
Extra information, not in MCRegisterDesc, about registers.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask...
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
const MVT::SimpleValueType * vt_iterator
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
A range adaptor for a pair of iterators.
const MCRegisterClass * MC
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index...
unsigned getNumRegs() const
Return the number of registers in this class.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes)
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
unsigned getAlignment() const
getAlignment - Return the minimum required alignment for a register of this class.
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
const LaneBitmask LaneMask
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
std::vector< uint8_t > Unit
iterator begin() const
begin/end - Return all of the registers in this class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
StringRef - Represent a constant reference to a string, i.e.
vt_iterator vt_begin() const
vt_begin / vt_end - Loop over all of the value types that can be represented by values in this regist...
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
std::set< RegisterRef > RegisterSet
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
void operator++()
Advance iterator to the next entry.
Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
static unsigned index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
const TargetRegisterClass *const * regclass_iterator
virtual bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
bool hasRegUnit(unsigned Reg, unsigned RegUnit) const
Returns true if Reg contains RegUnit.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.