26 #define DEBUG_TYPE "optimize-mips-pic-call"
30 cl::desc(
"Load target address from GOT"),
40 typedef std::pair<unsigned, unsigned> CntRegP;
45 AllocatorTy> ScopedHTType;
51 bool isVisited()
const;
52 void preVisit(ScopedHTType &ScopedHT);
57 ScopedHTType::ScopeTy *HTScope;
64 StringRef getPassName()
const override {
return "Mips OptimizePICCall"; }
75 bool visitNode(MBBInfo &MBBI);
83 ValueType &Val)
const;
87 unsigned getCount(ValueType Entry);
91 unsigned getReg(ValueType Entry);
94 void incCntAndSetReg(ValueType Entry,
unsigned Reg);
96 ScopedHTType ScopedHT;
134 unsigned SrcReg = I->getOperand(0).getReg();
135 unsigned DstReg =
getRegTy(SrcReg, MF) ==
MVT::i32 ? Mips::T9 : Mips::T9_64;
136 BuildMI(*MBB, I, I->getDebugLoc(), TII.
get(TargetOpcode::COPY), DstReg)
138 I->getOperand(0).setReg(DstReg);
148 unsigned Reg = Ty ==
MVT::i32 ? Mips::GP : Mips::GP_64;
165 bool MBBInfo::isVisited()
const {
return HTScope; }
167 void MBBInfo::preVisit(ScopedHTType &ScopedHT) {
168 HTScope =
new ScopedHTType::ScopeTy(ScopedHT);
171 void MBBInfo::postVisit() {
177 if (static_cast<const MipsSubtarget &>(F.
getSubtarget()).inMips16Mode())
182 bool Changed =
false;
186 while (!WorkList.empty()) {
187 MBBInfo &MBBI = WorkList.back();
191 if (MBBI.isVisited()) {
198 MBBI.preVisit(ScopedHT);
199 Changed |= visitNode(MBBI);
201 const std::vector<MachineDomTreeNode *> &Children = Node->
getChildren();
202 WorkList.append(Children.begin(), Children.end());
208 bool OptimizePICCall::visitNode(MBBInfo &MBBI) {
209 bool Changed =
false;
218 if (!isCallViaRegister(*
I, Reg, Entry))
222 unsigned N = getCount(Entry);
238 incCntAndSetReg(Entry, Reg);
246 bool OptimizePICCall::isCallViaRegister(
MachineInstr &
MI,
unsigned &Reg,
259 Val = (
Value*)
nullptr;
283 unsigned OptimizePICCall::getCount(
ValueType Entry) {
284 return ScopedHT.lookup(Entry).first;
288 unsigned Reg = ScopedHT.lookup(Entry).second;
293 void OptimizePICCall::incCntAndSetReg(
ValueType Entry,
unsigned Reg) {
294 CntRegP
P = ScopedHT.lookup(Entry);
295 ScopedHT.insert(Entry, std::make_pair(P.first + 1, Reg));
300 return new OptimizePICCall(TM);
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
vt_iterator vt_end() const
const std::vector< DomTreeNodeBase< NodeT > * > & getChildren() const
MachineDomTreeNode * getRootNode() const
FunctionPass * createMipsOptimizePICCallPass(MipsTargetMachine &TM)
Return an OptimizeCall object.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static MachineOperand * getCallTargetRegOpnd(MachineInstr &MI)
Return the first MachineOperand of MI if it is a used virtual register.
static void setCallTargetReg(MachineBasicBlock *MBB, MachineBasicBlock::iterator I)
Do the following transformation:
AnalysisUsage & addRequired()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
struct fuzzer::@269 Flags
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
RecyclingAllocator - This class wraps an Allocator, adding the functionality of recycling deleted obj...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Base class for the actual dominator tree node.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
BumpPtrAllocatorImpl BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template paramaters.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
unsigned getTargetFlags() const
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
FunctionPass class - This class is used to implement most global optimizations.
static cl::opt< bool > LoadTargetFromGOT("mips-load-target-from-got", cl::init(true), cl::desc("Load target address from GOT"), cl::Hidden)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
static cl::opt< bool > EraseGPOpnd("mips-erase-gp-opnd", cl::init(true), cl::desc("Erase GP Operand"), cl::Hidden)
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
static void eraseGPOpnd(MachineInstr &MI)
Search MI's operands for register GP and erase it.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
bool isCall(QueryType Type=AnyInBundle) const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF)
Return type of register Reg.
Primary interface to the complete machine description for the target machine.
vt_iterator vt_begin() const
vt_begin / vt_end - Loop over all of the value types that can be represented by values in this regist...
StringRef - Represent a constant reference to a string, i.e.
PointerUnion< const Value *, const PseudoSourceValue * > ValueType
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.