32 #define DEBUG_TYPE "registerbankinfo"
37 "Number of partial mappings dynamically created");
39 "Number of partial mappings dynamically accessed");
41 "Number of value mappings dynamically created");
43 "Number of value mappings dynamically accessed");
45 "Number of operands mappings dynamically created");
47 "Number of operands mappings dynamically accessed");
57 : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
60 assert(RegBanks[Idx] !=
nullptr &&
"Invalid RegisterBank");
61 assert(RegBanks[Idx]->
isValid() &&
"RegisterBank should be valid");
78 "ID does not match the index in the array");
79 DEBUG(
dbgs() <<
"Verify " << RegBank <<
'\n');
92 assert(Reg &&
"NoRegister does not have a register bank");
114 "The mapping of the register bank does not make sense");
128 if (RB && !RB->
covers(RC))
144 unsigned NumOperandsForMapping = isCopyLike ? 1 : MI.
getNumOperands();
148 NumOperandsForMapping);
158 bool CompleteMapping =
true;
161 for (
unsigned OpIdx = 0, EndIdx = MI.
getNumOperands(); OpIdx != EndIdx;
178 const RegisterBank *CurRegBank = isCopyLike ? AltRegBank :
nullptr;
185 CompleteMapping =
false;
196 OperandsMapping[0] = ValMapping;
197 CompleteMapping =
true;
200 OperandsMapping[OpIdx] = ValMapping;
203 if (isCopyLike && !CompleteMapping)
207 assert(CompleteMapping &&
"Setting an uncomplete mapping");
228 ++NumPartialMappingsAccessed;
235 ++NumPartialMappingsCreated;
250 unsigned NumBreakDowns) {
254 for (
unsigned Idx = 0; Idx != NumBreakDowns; ++Idx)
261 unsigned NumBreakDowns)
const {
262 ++NumValueMappingsAccessed;
269 ++NumValueMappingsCreated;
272 ValMapping =
new ValueMapping{BreakDown, NumBreakDowns};
276 template <
typename Iterator>
280 ++NumOperandsMappingsAccessed;
289 ++NumOperandsMappingsCreated;
299 for (Iterator It = Begin; It !=
End; ++It, ++Idx) {
315 std::initializer_list<const RegisterBankInfo::ValueMapping *> OpdsMapping)
329 RegisterBankInfo::getInstrPossibleMappings(
const MachineInstr &
MI)
const {
339 assert(Mapping.verify(MI) &&
"Mapping is invalid");
341 return PossibleMappings;
352 DEBUG(
dbgs() <<
"Applying default-like mapping\n");
353 for (
unsigned OpIdx = 0,
355 OpIdx != EndIdx; ++OpIdx) {
359 DEBUG(
dbgs() <<
" is not a register, nothing to be done\n");
364 "This mapping is too complex for this function");
367 if (NewRegs.begin() == NewRegs.end()) {
368 DEBUG(
dbgs() <<
" has not been repaired, nothing to be done\n");
372 MO.
setReg(*NewRegs.begin());
396 assert(RC &&
"Unable to deduce the register class");
409 assert(RegBank &&
"Register bank not set");
410 assert(Length &&
"Empty mapping");
411 assert((StartIdx <= getHighBitIdx()) &&
"Overflow, switch to APInt?");
413 assert(RegBank->getSize() >= Length &&
"Register bank too small for Mask");
418 OS <<
"[" << StartIdx <<
", " << getHighBitIdx() <<
"], RegBank = ";
426 assert(NumBreakDowns &&
"Value mapped nowhere?!");
427 unsigned OrigValueBitWidth = 0;
431 assert(PartMap.
verify() &&
"Partial mapping is invalid");
437 assert(OrigValueBitWidth >= MeaningfulBitWidth &&
438 "Meaningful bits not covered by the mapping");
439 APInt ValueMask(OrigValueBitWidth, 0);
446 ValueMask ^= PartMapMask;
447 assert((ValueMask & PartMapMask) == PartMapMask &&
448 "Some partial mappings overlap");
460 OS <<
"#BreakDown: " << NumBreakDowns <<
" ";
465 OS <<
'[' << PartMap <<
']';
477 "NumOperands must match, see constructor");
479 "MI must be connected to a MachineFunction");
483 for (
unsigned Idx = 0; Idx < NumOperands; ++Idx) {
487 "We should not care about non-reg mapping");
490 unsigned Reg = MO.
getReg();
494 "We must have a mapping for reg operands");
500 Reg, MF.getRegInfo(), *MF.getSubtarget().getRegisterInfo())) &&
501 "Value mapping is invalid");
512 OS <<
"ID: " <<
getID() <<
" Cost: " << getCost() <<
" Mapping: ";
514 for (
unsigned OpIdx = 0; OpIdx != NumOperands; ++OpIdx) {
515 const ValueMapping &ValMapping = getOperandMapping(OpIdx);
518 OS <<
"{ Idx: " << OpIdx <<
" Map: " << ValMapping <<
'}';
522 const int RegisterBankInfo::OperandsMapper::DontKnowIdx = -1;
527 : MRI(MRI), MI(MI), InstrMapping(InstrMapping) {
529 OpToNewVRegIdx.
resize(NumOpds, OperandsMapper::DontKnowIdx);
530 assert(InstrMapping.
verify(MI) &&
"Invalid mapping for MI");
534 RegisterBankInfo::OperandsMapper::getVRegsMem(
unsigned OpIdx) {
536 unsigned NumPartialVal =
538 int StartIdx = OpToNewVRegIdx[OpIdx];
540 if (StartIdx == OperandsMapper::DontKnowIdx) {
544 StartIdx = NewVRegs.size();
545 OpToNewVRegIdx[OpIdx] = StartIdx;
546 for (
unsigned i = 0;
i < NumPartialVal; ++
i)
547 NewVRegs.push_back(0);
550 getNewVRegsEnd(StartIdx, NumPartialVal);
556 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(
unsigned StartIdx,
557 unsigned NumVal)
const {
558 return const_cast<OperandsMapper *
>(
this)->getNewVRegsEnd(StartIdx, NumVal);
561 RegisterBankInfo::OperandsMapper::getNewVRegsEnd(
unsigned StartIdx,
563 assert((NewVRegs.size() == StartIdx + NumVal ||
564 NewVRegs.size() > StartIdx + NumVal) &&
565 "NewVRegs too small to contain all the partial mapping");
566 return NewVRegs.size() <= StartIdx + NumVal ? NewVRegs.end()
567 : &NewVRegs[StartIdx + NumVal];
576 for (
unsigned &NewVReg : NewVRegsForOpIdx) {
577 assert(PartMap != ValMapping.
end() &&
"Out-of-bound access");
578 assert(NewVReg == 0 &&
"Register has already been created");
586 unsigned PartialMapIdx,
591 "Out-of-bound access for partial mapping");
593 (void)getVRegsMem(OpIdx);
594 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
595 "This value is already set");
596 NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] = NewVReg;
601 bool ForDebug)
const {
604 int StartIdx = OpToNewVRegIdx[OpIdx];
606 if (StartIdx == OperandsMapper::DontKnowIdx)
607 return make_range(NewVRegs.end(), NewVRegs.end());
609 unsigned PartMapSize =
612 getNewVRegsEnd(StartIdx, PartMapSize);
616 for (
unsigned VReg : Res)
617 assert((VReg || ForDebug) &&
"Some registers are uninitialized");
628 bool ForDebug)
const {
631 OS <<
"Mapping for " << getMI() <<
"\nwith " <<
getInstrMapping() <<
'\n';
633 OS <<
"Populated indices (CellNumber, IndexInNewVRegs): ";
635 for (
unsigned Idx = 0; Idx != NumOpds; ++Idx) {
636 if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
639 OS <<
'(' << Idx <<
", " << OpToNewVRegIdx[Idx] <<
')';
647 OS <<
"Operand Mapping: ";
651 getMI().getParent() && getMI().getParent()->getParent()
652 ? getMI().getParent()->getParent()->getSubtarget().getRegisterInfo()
655 for (
unsigned Idx = 0; Idx != NumOpds; ++Idx) {
656 if (OpToNewVRegIdx[Idx] == DontKnowIdx)
661 OS <<
'(' <<
PrintReg(getMI().getOperand(Idx).
getReg(), TRI) <<
", [";
662 bool IsFirstNewVReg =
true;
663 for (
unsigned VReg : getVRegs(Idx)) {
666 IsFirstNewVReg =
false;
unsigned NumRegBanks
Total number of register banks.
void dump() const
Print this on dbgs() stream.
void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
RegisterBank ** RegBanks
Hold the set of supported register banks.
DenseMap< unsigned, ValueMapping * > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const
Get a register bank that covers RC.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
STATISTIC(NumFunctions,"Total number of functions")
DenseMap< unsigned, const PartialMapping * > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
unsigned getHighBitIdx() const
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Methods to get a uniquely generated ValueMapping.
#define LLVM_LIKELY(EXPR)
Helper class that represents how the value of an instruction may be mapped and what is the related co...
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwises returns null...
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Methods to get a uniquely generated ValueMapping.
iterator_range< SmallVectorImpl< unsigned >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
unsigned createGenericVirtualRegister(LLT Ty)
Create and return a new generic virtual register with low-level type Ty.
static hash_code hashValueMapping(const RegisterBankInfo::PartialMapping *BreakDown, unsigned NumBreakDowns)
bool verify(const TargetRegisterInfo &TRI) const
Check if this register bank is valid.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
bool verify() const
Check that the Mask is compatible with the RegBank.
static int getID(struct InternalInstruction *insn, const void *miiArg)
InstructionMapping getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Methods to get a uniquely generated array of ValueMapping.
const RegisterBank * RegBank
Register bank where the partial value lives.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg...
unsigned const MachineRegisterInfo * MRI
SmallVector< InstructionMapping, 4 > InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Get the size in bits of Reg.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
const MachineOperand & getOperand(unsigned i) const
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
unsigned getID() const
Get the identifier of this register bank.
Helper struct that represents how a value is partially mapped into a register.
unsigned Length
Length of this mapping in bits.
static const unsigned End
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
MachineInstr & getMI() const
Getters.
const PartialMapping * begin() const
Iterators through the PartialMappings.
void dump() const
Print this partial mapping on dbgs() stream.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
static hash_code hashPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank *RegBank)
Hashing function for PartialMapping.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
virtual ~RegisterBankInfo()
This class implements the register bank concept.
DenseMap< unsigned, const ValueMapping * > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
Helper struct that represents how a value is mapped through different register banks.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
A range adaptor for a pair of iterators.
void dump() const
Print this operands mapper on dbgs() stream.
Class for arbitrary precision integers.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
void print(raw_ostream &OS) const
Print this on OS;.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isValid() const
Check whether this object is valid.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
An opaque object representing a hash code.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool isAllOnesValue() const
Determine if all bits are set.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
void emplace_back(ArgTypes &&...Args)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void print(raw_ostream &OS) const
Print this on OS;.
const RegClassOrRegBank & getRegClassOrRegBank(unsigned Reg) const
Return the register bank or register class of Reg.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned getNumRegBanks() const
Get the total number of register banks.
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
unsigned getNumOperands() const
Get the number of operands.
unsigned getID() const
Get the ID.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void dump() const
Print this on dbgs() stream.
unsigned NumBreakDowns
Number of partial mapping to break down this value.
virtual const TargetInstrInfo * getInstrInfo() const
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
This class implements an extremely fast bulk output stream that can only output to a stream...
std::string Hash(const Unit &U)
const PartialMapping * end() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
RegisterBankInfo()
This constructor is meaningless.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
A discriminated union of two pointer types, with the discriminator in the low bit of the pointer...