30 #define DEBUG_TYPE "mccodeemitter"
32 #define GET_INSTRMAP_INFO
33 #include "MipsGenInstrInfo.inc"
34 #undef GET_INSTRMAP_INFO
81 case Mips::DSLL_MM64R6:
84 case Mips::DSRL_MM64R6:
87 case Mips::DSRA_MM64R6:
90 case Mips::DROTR_MM64R6:
99 "Invalid no. of machine operands for DINS!");
115 assert(pos < 32 && "DINS cannot have both size and pos > 32
");
116 InstIn.getOperand(3).setImm(size - 32);
117 InstIn.setOpcode(Mips::DINSM);
121 // Fix a bad compact branch encoding for beqc/bnec.
122 void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
124 // Encoding may be illegal !(rs < rt), but this situation is
126 unsigned RegOp0 = Inst.getOperand(0).getReg();
127 unsigned RegOp1 = Inst.getOperand(1).getReg();
129 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
130 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
132 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
133 Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
134 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!
");
137 } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
140 } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
141 Inst.getOpcode() == Mips::BOVC_MMR6) {
145 llvm_unreachable("Cannot rewrite unknown branch!
");
147 Inst.getOperand(0).setReg(RegOp1);
148 Inst.getOperand(1).setReg(RegOp0);
152 bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
153 return STI.getFeatureBits()[Mips::FeatureMicroMips];
156 bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
157 return STI.getFeatureBits()[Mips::FeatureMips32r6];
160 void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
164 void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
165 const MCSubtargetInfo &STI,
166 raw_ostream &OS) const {
167 // Output the instruction encoding in little endian byte order.
168 // Little-endian byte ordering:
169 // mips32r2: 4 | 3 | 2 | 1
170 // microMIPS: 2 | 1 | 4 | 3
171 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) {
172 EmitInstruction(Val >> 16, 2, STI, OS);
173 EmitInstruction(Val, 2, STI, OS);
175 for (unsigned i = 0; i < Size; ++i) {
176 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
177 EmitByte((Val >> Shift) & 0xff, OS);
184 void MipsMCCodeEmitter::
185 encodeInstruction(const MCInst &MI, raw_ostream &OS,
186 SmallVectorImpl<MCFixup> &Fixups,
187 const MCSubtargetInfo &STI) const
190 // Non-pseudo instructions that get changed for direct object
191 // only based on operand values.
192 // If this list of instructions get much longer we will move
193 // the check to a function call. Until then, this is more efficient.
195 switch (MI.getOpcode()) {
196 // If shift amount is >= 32 it the inst needs to be lowered further
201 case Mips::DSLL_MM64R6:
202 case Mips::DSRL_MM64R6:
203 case Mips::DSRA_MM64R6:
204 case Mips::DROTR_MM64R6:
205 LowerLargeShift(TmpInst);
207 // Double extract instruction is chosen by pos and size operands
211 // Compact branches, enforce encoding restrictions.
217 case Mips::BOVC_MMR6:
219 case Mips::BNVC_MMR6:
220 LowerCompactBranch(TmpInst);
223 unsigned long N = Fixups.size();
224 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
226 // Check for unimplemented opcodes.
227 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
228 // so we have to special check for them.
229 unsigned Opcode = TmpInst.getOpcode();
230 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
231 (Opcode != Mips::SLL_MM) && !Binary)
232 llvm_unreachable("unimplemented opcode in encodeInstruction()
");
235 if (isMicroMips(STI)) {
236 if (isMips32r6(STI)) {
237 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
239 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
242 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
244 // Check whether it is Dsp instruction.
246 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
248 if (NewOpcode != -1) {
249 if (Fixups.size() > N)
253 TmpInst.setOpcode (NewOpcode);
254 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
258 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
260 // Get byte count of instruction
261 unsigned Size = Desc.getSize();
263 llvm_unreachable("Desc.getSize() returns 0
");
265 EmitInstruction(Binary, Size, STI, OS);
271 unsigned MipsMCCodeEmitter::
272 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
273 SmallVectorImpl<MCFixup> &Fixups,
274 const MCSubtargetInfo &STI) const {
276 const MCOperand &MO = MI.getOperand(OpNo);
278 // If the destination is an immediate, divide by 4.
279 if (MO.isImm()) return MO.getImm() >> 2;
281 assert(MO.isExpr() &&
284 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
285 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
286 Fixups.push_back(MCFixup::create(0, FixupExpression,
287 MCFixupKind(Mips::fixup_Mips_PC16)));
294 unsigned MipsMCCodeEmitter::
295 getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
296 SmallVectorImpl<MCFixup> &Fixups,
297 const MCSubtargetInfo &STI) const {
299 const MCOperand &MO = MI.getOperand(OpNo);
301 // If the destination is an immediate, divide by 2.
302 if (MO.isImm()) return MO.getImm() >> 1;
304 assert(MO.isExpr() &&
307 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
308 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
309 Fixups.push_back(MCFixup::create(0, FixupExpression,
310 MCFixupKind(Mips::fixup_Mips_PC16)));
317 unsigned MipsMCCodeEmitter::
318 getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
319 SmallVectorImpl<MCFixup> &Fixups,
320 const MCSubtargetInfo &STI) const {
322 const MCOperand &MO = MI.getOperand(OpNo);
324 // If the destination is an immediate, divide by 2.
326 return MO.getImm() >> 1;
328 assert(MO.isExpr() &&
329 "getBranchTargetOpValueMMR6 expects
only expressions or immediates
");
331 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
332 MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
333 Fixups.push_back(MCFixup::create(0, FixupExpression,
334 MCFixupKind(Mips::fixup_Mips_PC16)));
341 unsigned MipsMCCodeEmitter::
342 getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
343 SmallVectorImpl<MCFixup> &Fixups,
344 const MCSubtargetInfo &STI) const {
346 const MCOperand &MO = MI.getOperand(OpNo);
348 // If the destination is an immediate, divide by 4.
350 return MO.getImm() >> 2;
352 assert(MO.isExpr() &&
353 "getBranchTargetOpValueLsl2MMR6 expects
only expressions or immediates
");
355 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
356 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
357 Fixups.push_back(MCFixup::create(0, FixupExpression,
358 MCFixupKind(Mips::fixup_Mips_PC16)));
365 unsigned MipsMCCodeEmitter::
366 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
367 SmallVectorImpl<MCFixup> &Fixups,
368 const MCSubtargetInfo &STI) const {
370 const MCOperand &MO = MI.getOperand(OpNo);
372 // If the destination is an immediate, divide by 2.
373 if (MO.isImm()) return MO.getImm() >> 1;
375 assert(MO.isExpr() &&
376 "getBranchTargetOpValueMM expects
only expressions or immediates
");
378 const MCExpr *Expr = MO.getExpr();
379 Fixups.push_back(MCFixup::create(0, Expr,
380 MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
387 unsigned MipsMCCodeEmitter::
388 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
389 SmallVectorImpl<MCFixup> &Fixups,
390 const MCSubtargetInfo &STI) const {
392 const MCOperand &MO = MI.getOperand(OpNo);
394 // If the destination is an immediate, divide by 2.
395 if (MO.isImm()) return MO.getImm() >> 1;
397 assert(MO.isExpr() &&
398 "getBranchTargetOpValuePC10 expects
only expressions or immediates
");
400 const MCExpr *Expr = MO.getExpr();
401 Fixups.push_back(MCFixup::create(0, Expr,
402 MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
409 unsigned MipsMCCodeEmitter::
410 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
411 SmallVectorImpl<MCFixup> &Fixups,
412 const MCSubtargetInfo &STI) const {
414 const MCOperand &MO = MI.getOperand(OpNo);
416 // If the destination is an immediate, divide by 2.
417 if (MO.isImm()) return MO.getImm() >> 1;
419 assert(MO.isExpr() &&
420 "getBranchTargetOpValueMM expects
only expressions or immediates
");
422 const MCExpr *Expr = MO.getExpr();
423 Fixups.push_back(MCFixup::create(0, Expr,
425 fixup_MICROMIPS_PC16_S1)));
432 unsigned MipsMCCodeEmitter::
433 getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
434 SmallVectorImpl<MCFixup> &Fixups,
435 const MCSubtargetInfo &STI) const {
437 const MCOperand &MO = MI.getOperand(OpNo);
439 // If the destination is an immediate, divide by 4.
440 if (MO.isImm()) return MO.getImm() >> 2;
442 assert(MO.isExpr() &&
443 "getBranchTarget21OpValue expects
only expressions or immediates
");
445 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
446 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
447 Fixups.push_back(MCFixup::create(0, FixupExpression,
448 MCFixupKind(Mips::fixup_MIPS_PC21_S2)));
455 unsigned MipsMCCodeEmitter::
456 getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
457 SmallVectorImpl<MCFixup> &Fixups,
458 const MCSubtargetInfo &STI) const {
460 const MCOperand &MO = MI.getOperand(OpNo);
462 // If the destination is an immediate, divide by 4.
463 if (MO.isImm()) return MO.getImm() >> 2;
465 assert(MO.isExpr() &&
466 "getBranchTarget21OpValueMM expects
only expressions or immediates
");
468 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
469 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
470 Fixups.push_back(MCFixup::create(0, FixupExpression,
471 MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
478 unsigned MipsMCCodeEmitter::
479 getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
480 SmallVectorImpl<MCFixup> &Fixups,
481 const MCSubtargetInfo &STI) const {
483 const MCOperand &MO = MI.getOperand(OpNo);
485 // If the destination is an immediate, divide by 4.
486 if (MO.isImm()) return MO.getImm() >> 2;
488 assert(MO.isExpr() &&
489 "getBranchTarget26OpValue expects
only expressions or immediates
");
491 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
492 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
493 Fixups.push_back(MCFixup::create(0, FixupExpression,
494 MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
501 unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
502 const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
503 const MCSubtargetInfo &STI) const {
505 const MCOperand &MO = MI.getOperand(OpNo);
507 // If the destination is an immediate, divide by 2.
509 return MO.getImm() >> 1;
511 assert(MO.isExpr() &&
512 "getBranchTarget26OpValueMM expects
only expressions or immediates
");
514 const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
515 MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
516 Fixups.push_back(MCFixup::create(0, FixupExpression,
517 MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
524 unsigned MipsMCCodeEmitter::
525 getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
526 SmallVectorImpl<MCFixup> &Fixups,
527 const MCSubtargetInfo &STI) const {
529 const MCOperand &MO = MI.getOperand(OpNo);
531 if (MO.isImm()) return MO.getImm();
533 assert(MO.isExpr() &&
534 "getJumpOffset16OpValue expects
only expressions or an immediate
");
543 unsigned MipsMCCodeEmitter::
544 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
545 SmallVectorImpl<MCFixup> &Fixups,
546 const MCSubtargetInfo &STI) const {
548 const MCOperand &MO = MI.getOperand(OpNo);
549 // If the destination is an immediate, divide by 4.
550 if (MO.isImm()) return MO.getImm()>>2;
552 assert(MO.isExpr() &&
553 "getJumpTargetOpValue expects
only expressions or an immediate
");
555 const MCExpr *Expr = MO.getExpr();
556 Fixups.push_back(MCFixup::create(0, Expr,
557 MCFixupKind(Mips::fixup_Mips_26)));
561 unsigned MipsMCCodeEmitter::
562 getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
563 SmallVectorImpl<MCFixup> &Fixups,
564 const MCSubtargetInfo &STI) const {
566 const MCOperand &MO = MI.getOperand(OpNo);
567 // If the destination is an immediate, divide by 2.
568 if (MO.isImm()) return MO.getImm() >> 1;
570 assert(MO.isExpr() &&
571 "getJumpTargetOpValueMM expects
only expressions or an immediate
");
573 const MCExpr *Expr = MO.getExpr();
574 Fixups.push_back(MCFixup::create(0, Expr,
575 MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
579 unsigned MipsMCCodeEmitter::
580 getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo,
581 SmallVectorImpl<MCFixup> &Fixups,
582 const MCSubtargetInfo &STI) const {
584 const MCOperand &MO = MI.getOperand(OpNo);
586 // The immediate is encoded as 'immediate << 2'.
587 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
588 assert((Res & 3) == 0);
592 assert(MO.isExpr() &&
593 "getUImm5Lsl2Encoding expects
only expressions or an immediate
");
598 unsigned MipsMCCodeEmitter::
599 getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo,
600 SmallVectorImpl<MCFixup> &Fixups,
601 const MCSubtargetInfo &STI) const {
603 const MCOperand &MO = MI.getOperand(OpNo);
605 int Value = MO.getImm();
612 unsigned MipsMCCodeEmitter::
613 getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo,
614 SmallVectorImpl<MCFixup> &Fixups,
615 const MCSubtargetInfo &STI) const {
617 const MCOperand &MO = MI.getOperand(OpNo);
619 unsigned Value = MO.getImm();
626 unsigned MipsMCCodeEmitter::
627 getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo,
628 SmallVectorImpl<MCFixup> &Fixups,
629 const MCSubtargetInfo &STI) const {
631 const MCOperand &MO = MI.getOperand(OpNo);
633 unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff;
634 return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff));
640 unsigned MipsMCCodeEmitter::
641 getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
642 const MCSubtargetInfo &STI) const {
645 if (Expr->evaluateAsAbsolute(Res))
648 MCExpr::ExprKind Kind = Expr->getKind();
649 if (Kind == MCExpr::Constant) {
650 return cast<MCConstantExpr>(Expr)->getValue();
653 if (Kind == MCExpr::Binary) {
654 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups, STI);
655 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups, STI);
659 if (Kind == MCExpr::Target) {
660 const MipsMCExpr *MipsExpr = cast<MipsMCExpr>(Expr);
662 Mips::Fixups FixupKind = Mips::Fixups(0);
663 switch (MipsExpr->getKind()) {
664 case MipsMCExpr::MEK_None:
665 case MipsMCExpr::MEK_Special:
666 llvm_unreachable("Unhandled
fixup kind!
");
668 case MipsMCExpr::MEK_CALL_HI16:
669 FixupKind = Mips::fixup_Mips_CALL_HI16;
671 case MipsMCExpr::MEK_CALL_LO16:
672 FixupKind = Mips::fixup_Mips_CALL_LO16;
674 case MipsMCExpr::MEK_DTPREL_HI:
675 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_HI16
676 : Mips::fixup_Mips_DTPREL_HI;
678 case MipsMCExpr::MEK_DTPREL_LO:
679 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_DTPREL_LO16
680 : Mips::fixup_Mips_DTPREL_LO;
682 case MipsMCExpr::MEK_GOTTPREL:
683 FixupKind = Mips::fixup_Mips_GOTTPREL;
685 case MipsMCExpr::MEK_GOT:
686 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT16
687 : Mips::fixup_Mips_GOT;
689 case MipsMCExpr::MEK_GOT_CALL:
690 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_CALL16
691 : Mips::fixup_Mips_CALL16;
693 case MipsMCExpr::MEK_GOT_DISP:
694 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_DISP
695 : Mips::fixup_Mips_GOT_DISP;
697 case MipsMCExpr::MEK_GOT_HI16:
698 FixupKind = Mips::fixup_Mips_GOT_HI16;
700 case MipsMCExpr::MEK_GOT_LO16:
701 FixupKind = Mips::fixup_Mips_GOT_LO16;
703 case MipsMCExpr::MEK_GOT_PAGE:
704 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_PAGE
705 : Mips::fixup_Mips_GOT_PAGE;
707 case MipsMCExpr::MEK_GOT_OFST:
708 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_GOT_OFST
709 : Mips::fixup_Mips_GOT_OFST;
711 case MipsMCExpr::MEK_GPREL:
712 FixupKind = Mips::fixup_Mips_GPREL16;
714 case MipsMCExpr::MEK_LO: {
715 // Check for %lo(%neg(%gp_rel(X)))
716 if (MipsExpr->isGpOff()) {
717 FixupKind = Mips::fixup_Mips_GPOFF_LO;
720 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16
721 : Mips::fixup_Mips_LO16;
724 case MipsMCExpr::MEK_HIGHEST:
725 FixupKind = Mips::fixup_Mips_HIGHEST;
727 case MipsMCExpr::MEK_HIGHER:
728 FixupKind = Mips::fixup_Mips_HIGHER;
730 case MipsMCExpr::MEK_HI:
731 // Check for %hi(%neg(%gp_rel(X)))
732 if (MipsExpr->isGpOff()) {
733 FixupKind = Mips::fixup_Mips_GPOFF_HI;
736 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_HI16
737 : Mips::fixup_Mips_HI16;
739 case MipsMCExpr::MEK_PCREL_HI16:
740 FixupKind = Mips::fixup_MIPS_PCHI16;
742 case MipsMCExpr::MEK_PCREL_LO16:
743 FixupKind = Mips::fixup_MIPS_PCLO16;
745 case MipsMCExpr::MEK_TLSGD:
746 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_GD
747 : Mips::fixup_Mips_TLSGD;
749 case MipsMCExpr::MEK_TLSLDM:
750 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_LDM
751 : Mips::fixup_Mips_TLSLDM;
753 case MipsMCExpr::MEK_TPREL_HI:
754 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_HI16
755 : Mips::fixup_Mips_TPREL_HI;
757 case MipsMCExpr::MEK_TPREL_LO:
758 FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16
759 : Mips::fixup_Mips_TPREL_LO;
761 case MipsMCExpr::MEK_NEG:
763 isMicroMips(STI) ? Mips::fixup_MICROMIPS_SUB : Mips::fixup_Mips_SUB;
766 Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
770 if (Kind == MCExpr::SymbolRef) {
771 Mips::Fixups FixupKind = Mips::Fixups(0);
773 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
776 case MCSymbolRefExpr::VK_None:
777 FixupKind = Mips::fixup_Mips_32; // FIXME: This is ok for O32/N32 but not N64.
781 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
789 unsigned MipsMCCodeEmitter::
790 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
791 SmallVectorImpl<MCFixup> &Fixups,
792 const MCSubtargetInfo &STI) const {
794 unsigned Reg = MO.getReg();
795 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
797 } else if (MO.isImm()) {
798 return static_cast<unsigned>(MO.getImm());
799 } else if (MO.isFPImm()) {
800 return static_cast<unsigned>(APFloat(MO.getFPImm())
801 .bitcastToAPInt().getHiBits(32).getLimitedValue());
803 // MO must be an Expr.
805 return getExprOpValue(MO.getExpr(),Fixups, STI);
810 template <unsigned ShiftAmount>
811 unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
812 SmallVectorImpl<MCFixup> &Fixups,
813 const MCSubtargetInfo &STI) const {
814 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
815 assert(MI.getOperand(OpNo).isReg());
816 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16;
817 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
819 // Apply the scale factor if there is one.
820 OffBits >>= ShiftAmount;
822 return (OffBits & 0xFFFF) | RegBits;
825 unsigned MipsMCCodeEmitter::
826 getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo,
827 SmallVectorImpl<MCFixup> &Fixups,
828 const MCSubtargetInfo &STI) const {
829 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
830 assert(MI.getOperand(OpNo).isReg());
831 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
833 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
836 return (OffBits & 0xF) | RegBits;
839 unsigned MipsMCCodeEmitter::
840 getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo,
841 SmallVectorImpl<MCFixup> &Fixups,
842 const MCSubtargetInfo &STI) const {
843 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
844 assert(MI.getOperand(OpNo).isReg());
845 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
847 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
850 return (OffBits & 0xF) | RegBits;
853 unsigned MipsMCCodeEmitter::
854 getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo,
855 SmallVectorImpl<MCFixup> &Fixups,
856 const MCSubtargetInfo &STI) const {
857 // Base register is encoded in bits 6-4, offset is encoded in bits 3-0.
858 assert(MI.getOperand(OpNo).isReg());
859 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),
861 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
864 return (OffBits & 0xF) | RegBits;
867 unsigned MipsMCCodeEmitter::
868 getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo,
869 SmallVectorImpl<MCFixup> &Fixups,
870 const MCSubtargetInfo &STI) const {
871 // Register is encoded in bits 9-5, offset is encoded in bits 4-0.
872 assert(MI.getOperand(OpNo).isReg() &&
873 (MI.getOperand(OpNo).getReg() == Mips::SP ||
874 MI.getOperand(OpNo).getReg() == Mips::SP_64) &&
875 "Unexpected base
register!
");
876 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
879 return OffBits & 0x1F;
882 unsigned MipsMCCodeEmitter::
883 getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo,
884 SmallVectorImpl<MCFixup> &Fixups,
885 const MCSubtargetInfo &STI) const {
886 // Register is encoded in bits 9-7, offset is encoded in bits 6-0.
887 assert(MI.getOperand(OpNo).isReg() &&
888 MI.getOperand(OpNo).getReg() == Mips::GP &&
889 "Unexpected base
register!
");
891 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1),
894 return OffBits & 0x7F;
897 unsigned MipsMCCodeEmitter::
898 getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo,
899 SmallVectorImpl<MCFixup> &Fixups,
900 const MCSubtargetInfo &STI) const {
901 // Base register is encoded in bits 20-16, offset is encoded in bits 8-0.
902 assert(MI.getOperand(OpNo).isReg());
903 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
905 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI);
907 return (OffBits & 0x1FF) | RegBits;
910 unsigned MipsMCCodeEmitter::
911 getMemEncodingMMImm11(const MCInst &MI, unsigned OpNo,
912 SmallVectorImpl<MCFixup> &Fixups,
913 const MCSubtargetInfo &STI) const {
914 // Base register is encoded in bits 20-16, offset is encoded in bits 10-0.
915 assert(MI.getOperand(OpNo).isReg());
916 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
918 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
920 return (OffBits & 0x07FF) | RegBits;
923 unsigned MipsMCCodeEmitter::
924 getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
925 SmallVectorImpl<MCFixup> &Fixups,
926 const MCSubtargetInfo &STI) const {
927 // opNum can be invalid if instruction had reglist as operand.
928 // MemOperand is always last operand of instruction (base + offset).
929 switch (MI.getOpcode()) {
934 OpNo = MI.getNumOperands() - 2;
938 // Base register is encoded in bits 20-16, offset is encoded in bits 11-0.
939 assert(MI.getOperand(OpNo).isReg());
940 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16;
941 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
943 return (OffBits & 0x0FFF) | RegBits;
946 unsigned MipsMCCodeEmitter::
947 getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo,
948 SmallVectorImpl<MCFixup> &Fixups,
949 const MCSubtargetInfo &STI) const {
950 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
951 assert(MI.getOperand(OpNo).isReg());
952 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups,
954 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
956 return (OffBits & 0xFFFF) | RegBits;
959 unsigned MipsMCCodeEmitter::
960 getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo,
961 SmallVectorImpl<MCFixup> &Fixups,
962 const MCSubtargetInfo &STI) const {
963 // opNum can be invalid if instruction had reglist as operand
964 // MemOperand is always last operand of instruction (base + offset)
965 switch (MI.getOpcode()) {
969 case Mips::SWM16_MMR6:
971 case Mips::LWM16_MMR6:
972 OpNo = MI.getNumOperands() - 2;
976 // Offset is encoded in bits 4-0.
977 assert(MI.getOperand(OpNo).isReg());
978 // Base register is always SP - thus it is not encoded.
979 assert(MI.getOperand(OpNo+1).isImm());
980 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI);
982 return ((OffBits >> 2) & 0x0F);
985 // FIXME: should be called getMSBEncoding
988 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
989 SmallVectorImpl<MCFixup> &Fixups,
990 const MCSubtargetInfo &STI) const {
991 assert(MI.getOperand(OpNo-1).isImm());
992 assert(MI.getOperand(OpNo).isImm());
993 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI);
994 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
996 return Position + Size - 1;
999 template <unsigned Bits, int Offset>
1001 MipsMCCodeEmitter::getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo,
1002 SmallVectorImpl<MCFixup> &Fixups,
1003 const MCSubtargetInfo &STI) const {
1004 assert(MI.getOperand(OpNo).isImm());
1005 unsigned Value = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1011 MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1012 SmallVectorImpl<MCFixup> &Fixups,
1013 const MCSubtargetInfo &STI) const {
1014 const MCOperand &MO = MI.getOperand(OpNo);
1016 // The immediate is encoded as 'immediate << 2'.
1017 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI);
1018 assert((Res & 3) == 0);
1022 assert(MO.isExpr() &&
1023 "getSimm19Lsl2Encoding expects
only expressions or an immediate
");
1025 const MCExpr *Expr = MO.getExpr();
1026 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
1027 : Mips::fixup_MIPS_PC19_S2;
1028 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
1033 MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
1034 SmallVectorImpl<MCFixup> &Fixups,
1035 const MCSubtargetInfo &STI) const {
1036 const MCOperand &MO = MI.getOperand(OpNo);
1038 // The immediate is encoded as 'immediate << 3'.
1039 unsigned Res = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1040 assert((Res & 7) == 0);
1044 assert(MO.isExpr() &&
1045 "getSimm18Lsl2Encoding expects
only expressions or an immediate
");
1047 const MCExpr *Expr = MO.getExpr();
1048 Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
1049 : Mips::fixup_MIPS_PC18_S3;
1050 Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
1055 MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo,
1056 SmallVectorImpl<MCFixup> &Fixups,
1057 const MCSubtargetInfo &STI) const {
1058 assert(MI.getOperand(OpNo).isImm());
1059 const MCOperand &MO = MI.getOperand(OpNo);
1060 return MO.getImm() % 8;
1064 MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo,
1065 SmallVectorImpl<MCFixup> &Fixups,
1066 const MCSubtargetInfo &STI) const {
1067 assert(MI.getOperand(OpNo).isImm());
1068 const MCOperand &MO = MI.getOperand(OpNo);
1069 unsigned Value = MO.getImm();
1071 case 128: return 0x0;
1078 case 15: return 0x7;
1079 case 16: return 0x8;
1080 case 31: return 0x9;
1081 case 32: return 0xa;
1082 case 63: return 0xb;
1083 case 64: return 0xc;
1084 case 255: return 0xd;
1085 case 32768: return 0xe;
1086 case 65535: return 0xf;
1088 llvm_unreachable("Unexpected value
");
1092 MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
1093 SmallVectorImpl<MCFixup> &Fixups,
1094 const MCSubtargetInfo &STI) const {
1097 // Register list operand is always first operand of instruction and it is
1098 // placed before memory operand (register + imm).
1100 for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) {
1101 unsigned Reg = MI.getOperand(I).getReg();
1102 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
1112 MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
1113 SmallVectorImpl<MCFixup> &Fixups,
1114 const MCSubtargetInfo &STI) const {
1115 return (MI.getNumOperands() - 4);
1119 MipsMCCodeEmitter::getRegisterPairOpValue(const MCInst &MI, unsigned OpNo,
1120 SmallVectorImpl<MCFixup> &Fixups,
1121 const MCSubtargetInfo &STI) const {
1122 return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI);
1126 MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
1127 SmallVectorImpl<MCFixup> &Fixups,
1128 const MCSubtargetInfo &STI) const {
1131 if (MI.getOperand(0).getReg() == Mips::A1 &&
1132 MI.getOperand(1).getReg() == Mips::A2)
1134 else if (MI.getOperand(0).getReg() == Mips::A1 &&
1135 MI.getOperand(1).getReg() == Mips::A3)
1137 else if (MI.getOperand(0).getReg() == Mips::A2 &&
1138 MI.getOperand(1).getReg() == Mips::A3)
1140 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1141 MI.getOperand(1).getReg() == Mips::S5)
1143 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1144 MI.getOperand(1).getReg() == Mips::S6)
1146 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1147 MI.getOperand(1).getReg() == Mips::A1)
1149 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1150 MI.getOperand(1).getReg() == Mips::A2)
1152 else if (MI.getOperand(0).getReg() == Mips::A0 &&
1153 MI.getOperand(1).getReg() == Mips::A3)
1160 MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
1161 SmallVectorImpl<MCFixup> &Fixups,
1162 const MCSubtargetInfo &STI) const {
1163 const MCOperand &MO = MI.getOperand(OpNo);
1164 assert(MO.isImm() && "getSimm23Lsl2Encoding expects
only an immediate
");
1165 // The immediate is encoded as 'immediate >> 2'.
1166 unsigned Res = static_cast<unsigned>(MO.getImm());
1167 assert((Res & 3) == 0);
1171 #include "MipsGenMCCodeEmitter.inc
"
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
static void LowerDins(MCInst &InstIn)
Context object for machine code objects.
Instances of this class represent a single low-level machine instruction.
MCCodeEmitter * createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setOpcode(unsigned Op)
static void LowerLargeShift(MCInst &Inst)
void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value, MCContext *Ctx=nullptr)
Adjusts a value to fix up the immediate of an LDI Rd, K instruction.
unsigned getOpcode() const
MCCodeEmitter * createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
unsigned getNumOperands() const
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCOperand & getOperand(unsigned i) const