LLVM  4.0.0
R600ISelLowering.h
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1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief R600 DAG Lowering interface definition
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
17 
18 #include "AMDGPUISelLowering.h"
19 
20 namespace llvm {
21 
22 class R600InstrInfo;
23 class R600Subtarget;
24 
26 public:
27  R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
28 
29  const R600Subtarget *getSubtarget() const;
30 
33  MachineBasicBlock *BB) const override;
34  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
35  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
36  void ReplaceNodeResults(SDNode * N,
38  SelectionDAG &DAG) const override;
40  bool isVarArg,
42  const SDLoc &DL, SelectionDAG &DAG,
43  SmallVectorImpl<SDValue> &InVals) const override;
45  EVT VT) const override;
46 
47  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
48  unsigned Align,
49  bool *IsFast) const override;
50 
51 private:
52  unsigned Gen;
53  /// Each OpenCL kernel has nine implicit parameters that are stored in the
54  /// first nine dwords of a Vertex Buffer. These implicit parameters are
55  /// lowered to load instructions which retrieve the values from the Vertex
56  /// Buffer.
57  SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
58  unsigned DwordOffset) const;
59 
60  void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
61  MachineRegisterInfo & MRI, unsigned dword_offset) const;
62  SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
63  const SDLoc &DL) const;
64  SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
65 
66  SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
67  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
68  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
69  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
70  SelectionDAG &DAG) const override;
71  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
72 
73  SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
74  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
75  SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
76  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
77 
78  SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
79  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
81  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
82  SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
83  SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
84  SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
85  unsigned mainop, unsigned ovf) const;
86 
87  SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
88  SelectionDAG &DAG) const;
89  void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
90  unsigned &Channel, unsigned &PtrIncr) const;
91  bool isZero(SDValue Op) const;
92  bool isHWTrueValue(SDValue Op) const;
93  bool isHWFalseValue(SDValue Op) const;
94 
95  bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
96  SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
97  SelectionDAG &DAG) const;
98 
99  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
100 };
101 
102 } // End namespace llvm;
103 
104 #endif
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Function Alias Analysis Results
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
This class is used to represent ISD::STORE nodes.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
unsigned const MachineRegisterInfo * MRI
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
XXX Only kernel functions are supported, so we can assume for now that every function is a kernel fun...
EVT - Extended Value Type.
Definition: ValueTypes.h:31
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
Interface definition of the TargetLowering class that is common to all AMD GPUs.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
An SDNode that represents everything that will be needed to construct a MachineInstr.
const R600Subtarget * getSubtarget() const
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI)
#define N
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
int * Ptr
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT VT) const override
Return the ValueType of the result of SETCC operations.