LLVM  4.0.0
IRTranslator.h
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1 //===-- llvm/CodeGen/GlobalISel/IRTranslator.h - IRTranslator ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the IRTranslator pass.
11 /// This pass is responsible for translating LLVM IR into MachineInstr.
12 /// It uses target hooks to lower the ABI but aside from that, the pass
13 /// generated code is generic. This is the default translator used for
14 /// GlobalISel.
15 ///
16 /// \todo Replace the comments with actual doxygen comments.
17 //===----------------------------------------------------------------------===//
18 
19 #ifndef LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
20 #define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
21 
22 #include "Types.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SetVector.h"
27 
28 namespace llvm {
29 // Forward declarations.
30 class BasicBlock;
31 class CallLowering;
32 class Constant;
33 class Instruction;
34 class MachineBasicBlock;
35 class MachineFunction;
36 class MachineInstr;
37 class MachineRegisterInfo;
38 class TargetPassConfig;
39 
40 // Technically the pass should run on an hypothetical MachineModule,
41 // since it should translate Global into some sort of MachineGlobal.
42 // The MachineGlobal should ultimately just be a transfer of ownership of
43 // the interesting bits that are relevant to represent a global value.
44 // That being said, we could investigate what would it cost to just duplicate
45 // the information from the LLVM IR.
46 // The idea is that ultimately we would be able to free up the memory used
47 // by the LLVM IR as soon as the translation is over.
49 public:
50  static char ID;
51 
52 private:
53  /// Interface used to lower the everything related to calls.
54  const CallLowering *CLI;
55  /// Mapping of the values of the current LLVM IR function
56  /// to the related virtual registers.
57  ValueToVReg ValToVReg;
58  // Constants are special because when we encounter one,
59  // we do not know at first where to insert the definition since
60  // this depends on all its uses.
61  // Thus, we will insert the sequences to materialize them when
62  // we know all their users.
63  // In the meantime, just keep it in a set.
64  // Note: Constants that end up as immediate in the related instructions,
65  // do not appear in that map.
67 
68  // N.b. it's not completely obvious that this will be sufficient for every
69  // LLVM IR construct (with "invoke" being the obvious candidate to mess up our
70  // lives.
72 
73  // List of stubbed PHI instructions, for values and basic blocks to be filled
74  // in once all MachineBasicBlocks have been created.
76 
77  /// Record of what frame index has been allocated to specified allocas for
78  /// this function.
80 
81  /// Methods for translating form LLVM IR to MachineInstr.
82  /// \see ::translate for general information on the translate methods.
83  /// @{
84 
85  /// Translate \p Inst into its corresponding MachineInstr instruction(s).
86  /// Insert the newly translated instruction(s) right where the CurBuilder
87  /// is set.
88  ///
89  /// The general algorithm is:
90  /// 1. Look for a virtual register for each operand or
91  /// create one.
92  /// 2 Update the ValToVReg accordingly.
93  /// 2.alt. For constant arguments, if they are compile time constants,
94  /// produce an immediate in the right operand and do not touch
95  /// ValToReg. Actually we will go with a virtual register for each
96  /// constants because it may be expensive to actually materialize the
97  /// constant. Moreover, if the constant spans on several instructions,
98  /// CSE may not catch them.
99  /// => Update ValToVReg and remember that we saw a constant in Constants.
100  /// We will materialize all the constants in finalize.
101  /// Note: we would need to do something so that we can recognize such operand
102  /// as constants.
103  /// 3. Create the generic instruction.
104  ///
105  /// \return true if the translation succeeded.
106  bool translate(const Instruction &Inst);
107 
108  /// Materialize \p C into virtual-register \p Reg. The generic instructions
109  /// performing this materialization will be inserted into the entry block of
110  /// the function.
111  ///
112  /// \return true if the materialization succeeded.
113  bool translate(const Constant &C, unsigned Reg);
114 
115  /// Translate an LLVM bitcast into generic IR. Either a COPY or a G_BITCAST is
116  /// emitted.
117  bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
118 
119  /// Translate an LLVM load instruction into generic IR.
120  bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
121 
122  /// Translate an LLVM store instruction into generic IR.
123  bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
124 
125  bool translateMemcpy(const CallInst &CI, MachineIRBuilder &MIRBuilder);
126 
127  void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
128 
129  bool translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
130  MachineIRBuilder &MIRBuilder);
131 
132  bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
133  MachineIRBuilder &MIRBuilder);
134 
135  /// Translate call instruction.
136  /// \pre \p U is a call instruction.
137  bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
138 
139  bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
140 
141  bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
142 
143  /// Translate one of LLVM's cast instructions into MachineInstrs, with the
144  /// given generic Opcode.
145  bool translateCast(unsigned Opcode, const User &U,
146  MachineIRBuilder &MIRBuilder);
147 
148  /// Translate static alloca instruction (i.e. one of constant size and in the
149  /// first basic block).
150  bool translateStaticAlloca(const AllocaInst &Inst,
151  MachineIRBuilder &MIRBuilder);
152 
153  /// Translate a phi instruction.
154  bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
155 
156  /// Translate a comparison (icmp or fcmp) instruction or constant.
157  bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
158 
159  /// Translate an integer compare instruction (or constant).
160  bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
161  return translateCompare(U, MIRBuilder);
162  }
163 
164  /// Translate a floating-point compare instruction (or constant).
165  bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
166  return translateCompare(U, MIRBuilder);
167  }
168 
169 
170  /// Add remaining operands onto phis we've translated. Executed after all
171  /// MachineBasicBlocks for the function have been created.
172  void finishPendingPhis();
173 
174  /// Translate \p Inst into a binary operation \p Opcode.
175  /// \pre \p U is a binary operation.
176  bool translateBinaryOp(unsigned Opcode, const User &U,
177  MachineIRBuilder &MIRBuilder);
178 
179  /// Translate branch (br) instruction.
180  /// \pre \p U is a branch instruction.
181  bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
182 
183  bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
184 
185  bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
186 
187  bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
188 
189  bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
190 
191  bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
192 
193  /// Translate return (ret) instruction.
194  /// The target needs to implement CallLowering::lowerReturn for
195  /// this to succeed.
196  /// \pre \p U is a return instruction.
197  bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
198 
199  bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
200  return translateBinaryOp(TargetOpcode::G_ADD, U, MIRBuilder);
201  }
202  bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
203  return translateBinaryOp(TargetOpcode::G_SUB, U, MIRBuilder);
204  }
205  bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
206  return translateBinaryOp(TargetOpcode::G_AND, U, MIRBuilder);
207  }
208  bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
209  return translateBinaryOp(TargetOpcode::G_MUL, U, MIRBuilder);
210  }
211  bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
212  return translateBinaryOp(TargetOpcode::G_OR, U, MIRBuilder);
213  }
214  bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
215  return translateBinaryOp(TargetOpcode::G_XOR, U, MIRBuilder);
216  }
217 
218  bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
219  return translateBinaryOp(TargetOpcode::G_UDIV, U, MIRBuilder);
220  }
221  bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
222  return translateBinaryOp(TargetOpcode::G_SDIV, U, MIRBuilder);
223  }
224  bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
225  return translateBinaryOp(TargetOpcode::G_UREM, U, MIRBuilder);
226  }
227  bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
228  return translateBinaryOp(TargetOpcode::G_SREM, U, MIRBuilder);
229  }
230  bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder) {
231  return translateStaticAlloca(cast<AllocaInst>(U), MIRBuilder);
232  }
233  bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
234  return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
235  }
236  bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
237  return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
238  }
239  bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
240  return translateCast(TargetOpcode::G_TRUNC, U, MIRBuilder);
241  }
242  bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
243  return translateCast(TargetOpcode::G_FPTRUNC, U, MIRBuilder);
244  }
245  bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
246  return translateCast(TargetOpcode::G_FPEXT, U, MIRBuilder);
247  }
248  bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
249  return translateCast(TargetOpcode::G_FPTOUI, U, MIRBuilder);
250  }
251  bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
252  return translateCast(TargetOpcode::G_FPTOSI, U, MIRBuilder);
253  }
254  bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
255  return translateCast(TargetOpcode::G_UITOFP, U, MIRBuilder);
256  }
257  bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
258  return translateCast(TargetOpcode::G_SITOFP, U, MIRBuilder);
259  }
260  bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
261  return true;
262  }
263  bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
264  return translateCast(TargetOpcode::G_SEXT, U, MIRBuilder);
265  }
266 
267  bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
268  return translateCast(TargetOpcode::G_ZEXT, U, MIRBuilder);
269  }
270 
271  bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
272  return translateBinaryOp(TargetOpcode::G_SHL, U, MIRBuilder);
273  }
274  bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
275  return translateBinaryOp(TargetOpcode::G_LSHR, U, MIRBuilder);
276  }
277  bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
278  return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
279  }
280 
281  bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
282  return translateBinaryOp(TargetOpcode::G_FADD, U, MIRBuilder);
283  }
284  bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
285  return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
286  }
287  bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
288  return translateBinaryOp(TargetOpcode::G_FMUL, U, MIRBuilder);
289  }
290  bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
291  return translateBinaryOp(TargetOpcode::G_FDIV, U, MIRBuilder);
292  }
293  bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
294  return translateBinaryOp(TargetOpcode::G_FREM, U, MIRBuilder);
295  }
296 
297  // Stubs to keep the compiler happy while we implement the rest of the
298  // translation.
299  bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder) {
300  return false;
301  }
302  bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
303  return false;
304  }
305  bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
306  return false;
307  }
308  bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
309  return false;
310  }
311  bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
312  return false;
313  }
314  bool translateFence(const User &U, MachineIRBuilder &MIRBuilder) {
315  return false;
316  }
317  bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder) {
318  return false;
319  }
320  bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder) {
321  return false;
322  }
323  bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
324  return false;
325  }
326  bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
327  return false;
328  }
329  bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
330  return false;
331  }
332  bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
333  return false;
334  }
335  bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
336  return false;
337  }
338  bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
339  return false;
340  }
341  bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder) {
342  return false;
343  }
344  bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder) {
345  return false;
346  }
347  bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder) {
348  return false;
349  }
350 
351  /// @}
352 
353  // Builder for machine instruction a la IRBuilder.
354  // I.e., compared to regular MIBuilder, this one also inserts the instruction
355  // in the current block, it can creates block, etc., basically a kind of
356  // IRBuilder, but for Machine IR.
357  MachineIRBuilder CurBuilder;
358 
359  // Builder set to the entry block (just after ABI lowering instructions). Used
360  // as a convenient location for Constants.
361  MachineIRBuilder EntryBuilder;
362 
363  // The MachineFunction currently being translated.
364  MachineFunction *MF;
365 
366  /// MachineRegisterInfo used to create virtual registers.
367  MachineRegisterInfo *MRI;
368 
369  const DataLayout *DL;
370 
371  /// Current target configuration. Controls how the pass handles errors.
372  const TargetPassConfig *TPC;
373 
374  // * Insert all the code needed to materialize the constants
375  // at the proper place. E.g., Entry block or dominator block
376  // of each constant depending on how fancy we want to be.
377  // * Clear the different maps.
378  void finalizeFunction();
379 
380  /// Get the VReg that represents \p Val.
381  /// If such VReg does not exist, it is created.
382  unsigned getOrCreateVReg(const Value &Val);
383 
384  /// Get the frame index that represents \p Val.
385  /// If such VReg does not exist, it is created.
386  int getOrCreateFrameIndex(const AllocaInst &AI);
387 
388  /// Get the alignment of the given memory operation instruction. This will
389  /// either be the explicitly specified value or the ABI-required alignment for
390  /// the type being accessed (according to the Module's DataLayout).
391  unsigned getMemOpAlignment(const Instruction &I);
392 
393  /// Get the MachineBasicBlock that represents \p BB.
394  /// If such basic block does not exist, it is created.
395  MachineBasicBlock &getOrCreateBB(const BasicBlock &BB);
396 
397 
398 public:
399  // Ctor, nothing fancy.
400  IRTranslator();
401 
402  StringRef getPassName() const override { return "IRTranslator"; }
403 
404  void getAnalysisUsage(AnalysisUsage &AU) const override;
405 
406  // Algo:
407  // CallLowering = MF.subtarget.getCallLowering()
408  // F = MF.getParent()
409  // MIRBuilder.reset(MF)
410  // MIRBuilder.getOrCreateBB(F.getEntryBB())
411  // CallLowering->translateArguments(MIRBuilder, F, ValToVReg)
412  // for each bb in F
413  // MIRBuilder.getOrCreateBB(bb)
414  // for each inst in bb
415  // if (!translate(MIRBuilder, inst, ValToVReg, ConstantToSequence))
416  // report_fatal_error(“Don’t know how to translate input");
417  // finalize()
418  bool runOnMachineFunction(MachineFunction &MF) override;
419 };
420 
421 } // End namespace llvm.
422 #endif
Various leaf nodes.
Definition: ISDOpcodes.h:60
This class represents a function call, abstracting a target machine's calling convention.
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
Definition: IRTranslator.h:402
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Reg
All possible values of the reg field in the ModR/M byte.
This is an important base class in LLVM.
Definition: Constant.h:42
Helper class to build MachineInstr.
Represent the analysis usage information of a pass.
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:292
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
This file declares the MachineIRBuilder class.
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
static char ID
Definition: IRTranslator.h:50
#define I(x, y, z)
Definition: MD5.cpp:54
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
an instruction to allocate memory on the stack
Definition: Instructions.h:60