14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
50 std::vector<SUnit*> Packet;
53 unsigned TotalPackets;
61 : SchedModel(SM), TotalPackets(0) {
66 assert(ResourcesModel &&
"Unimplemented CreateTargetScheduleState.");
76 delete ResourcesModel;
105 std::unique_ptr<MachineSchedStrategy> S)
119 struct SchedCandidate {
129 SchedCandidate(): SU(
nullptr), SCost(0) {}
133 NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure,
139 struct VLIWSchedBoundary {
154 unsigned MinReadyCycle;
157 unsigned MaxMinLatency;
162 DAG(
nullptr), SchedModel(
nullptr), Available(ID, Name+
".A"),
164 CheckPending(
false), HazardRec(
nullptr), ResourceModel(
nullptr),
165 CurrCycle(0), IssueCount(0),
166 MinReadyCycle(UINT_MAX), MaxMinLatency(0) {}
168 ~VLIWSchedBoundary() {
169 delete ResourceModel;
183 bool checkHazard(
SUnit *SU);
185 void releaseNode(
SUnit *SU,
unsigned ReadyCycle);
189 void bumpNode(
SUnit *SU);
191 void releasePending();
193 void removeReady(
SUnit *SU);
195 SUnit *pickOnlyChoice();
202 VLIWSchedBoundary Top;
203 VLIWSchedBoundary Bot;
214 : DAG(nullptr), SchedModel(nullptr), Top(
TopQID,
"TopQ"),
228 return Top.ResourceModel->getTotalPackets() +
229 Bot.ResourceModel->getTotalPackets();
236 SUnit *SU, SchedCandidate &Candidate,
241 SchedCandidate &Candidate);
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
void schedule() override
Schedule - This is called back from ScheduleDAGInstrs::Run() when it's time to do some work...
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
void readyQueueVerboseDump(const RegPressureTracker &RPTracker, SchedCandidate &Candidate, ReadyQueue &Q)
int SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose)
Single point to compute overall scheduling cost.
bool isInPacket(SUnit *SU) const
CandResult pickNodeFromQueue(ReadyQueue &Q, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
Pick the best candidate from the top queue.
void savePacket()
Save the last formed packet.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
SUnit * pickNodeBidrectional(bool &IsTopNode)
Pick the best candidate node from either the top or bottom queue.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Provide an instruction scheduling machine model to CodeGen passes.
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
VLIWMachineScheduler(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
initializer< Ty > init(const Ty &Val)
Helpers for implementing custom MachineSchedStrategy classes.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
Track the current register pressure at some position in the instruction stream, and remember the high...
bool isResourceAvailable(SUnit *SU)
Check if scheduling of this SU is possible in the current packet.
void schedNode(SUnit *SU, bool IsTopNode) override
Update the scheduler's state after scheduling a node.
ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics to balance the schedule...
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P=PressureChange())
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned getTotalPackets() const
TargetSubtargetInfo - Generic base class for all target subtargets.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
Capture a change in pressure for a single pressure set.
bool reserveResources(SUnit *SU)
Keep track of available resources.
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
Store the effects of a change in pressure on things that MI scheduler cares about.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< SUnit * > OldPacket
Save the last formed packet.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned getIssueWidth() const
Maximum number of micro-ops that may be scheduled per cycle.
ConvergingVLIWScheduler()
SUnit - Scheduling unit. This is a node in the scheduling DAG.
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.