26 #define DEBUG_TYPE "packets"
39 cl::init(0),
cl::desc(
"If present, stops packetizing after N instructions"));
53 DFAInput getDFAInsnInput(
const std::vector<unsigned> &InsnClass) {
56 "Exceeded maximum number of DFA terms");
57 for (
auto U : InsnClass)
58 InsnInput = addDFAFuncUnits(InsnInput, U);
67 InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
68 DFAStateEntryTable(SET) {
72 "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput");
75 "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
87 void DFAPacketizer::ReadTable(
unsigned int state) {
88 unsigned ThisState = DFAStateEntryTable[state];
89 unsigned NextStateInTable = DFAStateEntryTable[state+1];
92 if (CachedTable.
count(UnsignPair(state, DFAStateInputTable[ThisState][0])))
95 for (
unsigned i = ThisState;
i < NextStateInTable;
i++)
96 CachedTable[UnsignPair(state, DFAStateInputTable[
i][0])] =
97 DFAStateInputTable[
i][1];
108 *
IE = InstrItins->
endStage(InsnClass); IS !=
IE; ++IS) {
109 InsnInput = addDFAFuncUnits(InsnInput, IS->getUnits());
118 return getDFAInsnInput(InsnClass);
127 UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
128 ReadTable(CurrentState);
129 return CachedTable.
count(StateTrans) != 0;
138 UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
139 ReadTable(CurrentState);
141 CurrentState = CachedTable[StateTrans];
168 std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
177 Mutations.push_back(std::move(Mutation));
195 for (
auto &M : Mutations)
209 : MF(mf),
TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
228 dbgs() <<
"Finalizing packet:\n";
250 std::distance(BeginItr, EndItr));
254 dbgs() <<
"Scheduling DAG of the packetize region\n";
267 for (; BeginItr != EndItr; ++BeginItr) {
289 assert(SUI &&
"Missing SUnit Info!");
292 DEBUG(
dbgs() <<
"Checking resources for adding MI to packet " << MI);
297 dbgs() <<
" Resources are available for adding MI to packet\n";
299 dbgs() <<
" Resources NOT available\n";
305 assert(SUJ &&
"Missing SUnit Info!");
307 DEBUG(
dbgs() <<
" Checking against MJ " << *MJ);
310 DEBUG(
dbgs() <<
" Not legal to add MI, try to prune\n");
314 DEBUG(
dbgs() <<
" Could not prune dependencies for adding MI\n");
318 DEBUG(
dbgs() <<
" Pruned dependence for adding MI\n");
322 DEBUG(
if (ResourceAvail)
323 dbgs() <<
"Resources are available, but instruction should not be "
324 "added to packet\n " << MI);
331 DEBUG(
dbgs() <<
"* Adding MI to packet " << MI <<
'\n');
344 std::unique_ptr<ScheduleDAGMutation>
Mutation) {
bool canReserveResources(const llvm::MCInstrDesc *MID)
std::vector< MachineInstr * > CurrentPacketMIs
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
virtual void finishBlock()
finishBlock - Clean up after scheduling in the given block.
virtual void initPacketizerState()
DFAInput getInsnInput(unsigned InsnClass)
Describe properties that are true of each instruction in the target description file.
MachineInstr * getInstr() const
getInstr - Return the representative MachineInstr for this SUnit.
bool CanHandleTerminators
The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ)
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
virtual bool ignorePseudoInstruction(const MachineInstr &I, const MachineBasicBlock *MBB)
static unsigned InstrCount
virtual void startBlock(MachineBasicBlock *BB)
startBlock - Prepare to perform scheduling in the given block.
void schedule() override
schedule - Order nodes according to selected style, filling in the Sequence member.
void dumpAll(const ScheduleDAG *G) const
void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.
std::map< MachineInstr *, SUnit * > MIToSUnit
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
void postprocessDAG()
Apply each ScheduleDAGMutation step in order.
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
virtual void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI)
DFAPacketizer * ResourceTracker
virtual MachineBasicBlock::iterator addToPacket(MachineInstr &MI)
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
DefaultVLIWScheduler takes ownership of the Mutation object.
Itinerary data supplied by a subtarget to be used by a target.
void reserveResources(const llvm::MCInstrDesc *MID)
virtual void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the scheduler state for the next scheduling region.
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA)
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
initializer< Ty > init(const Ty &Val)
#define DFA_MAX_RESOURCES
virtual bool shouldAddToPacket(const MachineInstr &MI)
virtual bool isSoloInstruction(const MachineInstr &MI)
virtual void exitRegion()
Notify that the scheduler has finished scheduling the current region.
self_iterator getIterator()
const InstrStage * endStage(unsigned ItinClassIndx) const
Return the last+1 stage of the itinerary.
const TargetInstrInfo * TII
const MachineLoopInfo * MLI
instr_iterator getInstrIterator() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ)
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
Representation of each machine instruction.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
These values represent a non-pipelined step in the execution of an instruction.
virtual ~VLIWPacketizerList()
static cl::opt< unsigned > InstrLimit("dfa-instr-limit", cl::Hidden, cl::init(0), cl::desc("If present, stops packetizing after N instructions"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA)
DFAPacketizer(const InstrItineraryData *I, const DFAStateInput(*SIT)[2], const unsigned *SET)
std::vector< SUnit > SUnits
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
void PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr)
DefaultVLIWScheduler * VLIWScheduler
SUnit - Scheduling unit. This is a node in the scheduling DAG.