26 #define DEBUG_TYPE "wasm-instr-info"
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
33 WebAssembly::ADJCALLSTACKUP),
34 RI(STI.getTargetTriple()) {}
39 case WebAssembly::CONST_I32:
40 case WebAssembly::CONST_I64:
41 case WebAssembly::CONST_F32:
42 case WebAssembly::CONST_F64:
53 const DebugLoc &DL,
unsigned DestReg,
54 unsigned SrcReg,
bool KillSrc)
const {
60 ?
MRI.getRegClass(DestReg)
61 :
MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
64 if (RC == &WebAssembly::I32RegClass)
65 CopyOpcode = WebAssembly::COPY_I32;
66 else if (RC == &WebAssembly::I64RegClass)
67 CopyOpcode = WebAssembly::COPY_I64;
68 else if (RC == &WebAssembly::F32RegClass)
69 CopyOpcode = WebAssembly::COPY_F32;
70 else if (RC == &WebAssembly::F64RegClass)
71 CopyOpcode = WebAssembly::COPY_F64;
75 BuildMI(MBB, I, DL,
get(CopyOpcode), DestReg)
82 unsigned OpIdx2)
const {
100 bool HaveCond =
false;
102 switch (
MI.getOpcode()) {
106 case WebAssembly::BR_IF:
110 if (!
MI.getOperand(0).isMBB())
114 TBB =
MI.getOperand(0).getMBB();
117 case WebAssembly::BR_UNLESS:
121 if (!
MI.getOperand(0).isMBB())
125 TBB =
MI.getOperand(0).getMBB();
130 if (!
MI.getOperand(0).isMBB())
133 TBB =
MI.getOperand(0).getMBB();
135 FBB =
MI.getOperand(0).getMBB();
146 int *BytesRemoved)
const {
147 assert(!BytesRemoved &&
"code size not handled");
154 if (I->isDebugValue())
156 if (!I->isTerminator())
159 I->eraseFromParent();
172 int *BytesAdded)
const {
173 assert(!BytesAdded &&
"code size not handled");
183 assert(Cond.
size() == 2 &&
"Expected a flag and a successor block");
185 if (Cond[0].getImm()) {
188 BuildMI(&MBB, DL,
get(WebAssembly::BR_UNLESS))
201 assert(Cond.
size() == 2 &&
"Expected a flag and a successor block");
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator instr_begin()
instr_iterator instr_end()
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool isVRegStackified(unsigned VReg) const
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
iterator_range< iterator > terminators()
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
size_t size() const
size - Get the array size.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Control flow instructions. These all have token chains.
unsigned const MachineRegisterInfo * MRI
const MachineOperand & getOperand(unsigned i) const
This file provides WebAssembly-specific target descriptions.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool empty() const
empty - Check if the array is empty.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
Iterator for intrusive lists based on ilist_node.
This file contains the WebAssembly implementation of the TargetInstrInfo class.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Representation of each machine instruction.
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
This file declares WebAssembly-specific per-machine-function information.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.