LLVM  4.0.0
CodeGen/GlobalISel/Utils.cpp
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1 //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file This file implements the utility functions used by the GlobalISel
10 /// pipeline.
11 //===----------------------------------------------------------------------===//
12 
20 
21 #define DEBUG_TYPE "globalisel-utils"
22 
23 using namespace llvm;
24 
26  const MachineFunction &MF, const TargetRegisterInfo &TRI,
28  const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
29  unsigned Reg, unsigned OpIdx) {
30  // Assume physical registers are properly constrained.
32  "PhysReg not implemented");
33 
34  const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
35 
36  if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) {
37  unsigned NewReg = MRI.createVirtualRegister(RegClass);
38  BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(),
39  TII.get(TargetOpcode::COPY), NewReg)
40  .addReg(Reg);
41  return NewReg;
42  }
43 
44  return Reg;
45 }
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, unsigned Reg, unsigned OpIdx)
Try to constrain Reg so that it is usable by argument OpIdx of the provided MCInstrDesc II...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Holds all the information related to register banks.
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...