25 #define DEBUG_TYPE "dwarfdebug"
43 auto &Ranges = VarInstrRanges[Var];
44 if (!Ranges.empty() && Ranges.back().second ==
nullptr &&
45 Ranges.back().first->isIdenticalTo(MI)) {
46 DEBUG(
dbgs() <<
"Coalescing identical DBG_VALUE entries:\n"
47 <<
"\t" << Ranges.back().first <<
"\t" << MI <<
"\n");
50 Ranges.push_back(std::make_pair(&MI,
nullptr));
55 auto &Ranges = VarInstrRanges[Var];
57 assert(!Ranges.empty() && Ranges.back().second ==
nullptr);
61 Ranges.back().second = &
MI;
65 const auto &
I = VarInstrRanges.
find(Var);
66 if (
I == VarInstrRanges.
end())
68 const auto &Ranges =
I->second;
69 if (Ranges.empty() || Ranges.back().second !=
nullptr)
77 typedef std::map<unsigned, SmallVector<InlinedVariable, 1>> RegDescribedVarsMap;
82 InlinedVariable Var) {
83 const auto &
I = RegVars.find(RegNo);
84 assert(RegNo != 0U &&
I != RegVars.end());
85 auto &VarSet =
I->second;
86 const auto &VarPos =
find(VarSet, Var);
87 assert(VarPos != VarSet.end());
96 InlinedVariable Var) {
98 auto &VarSet = RegVars[RegNo];
100 VarSet.push_back(Var);
106 RegDescribedVarsMap::iterator
I,
111 for (
const auto &Var : I->second)
121 const auto &
I = RegVars.find(RegNo);
122 if (
I == RegVars.end())
131 if (LastMI == MBB.
end() || !LastMI->isReturn())
135 DebugLoc LastLoc = LastMI->getDebugLoc();
140 if (
I->getDebugLoc() != LastLoc)
146 return &*MBB.
begin();
154 for (
const auto &
MBB : *MF) {
157 for (
const auto &
MI :
MBB) {
159 if (&
MI == FirstEpilogueInst)
168 if (MO.isReg() && MO.isDef() && MO.getReg() &&
173 }
else if (MO.isRegMask()) {
189 RegDescribedVarsMap RegVars;
190 for (
const auto &
MBB : *MF) {
191 for (
const auto &
MI :
MBB) {
192 if (!
MI.isDebugValue()) {
196 if (MO.isReg() && MO.isDef() && MO.getReg()) {
206 if (ChangingRegs.test(*AI))
209 }
else if (MO.isRegMask()) {
212 for (
int I = ChangingRegs.find_first();
I != -1;
213 I = ChangingRegs.find_next(
I)) {
216 MO.clobbersPhysReg(
I)) {
225 assert(
MI.getNumOperands() > 1 &&
"Invalid DBG_VALUE instruction!");
230 assert(RawVar->isValidLocationForIntrinsic(
MI.getDebugLoc()) &&
231 "Expected inlined-at fields to agree");
232 InlinedVariable Var(RawVar,
MI.getDebugLoc()->getInlinedAt());
246 if (!MBB.empty() && &MBB != &MF->back()) {
247 for (
auto I = RegVars.begin(),
E = RegVars.end();
I !=
E;) {
250 ChangingRegs.test(CurElem->first))
void calculateDbgValueHistory(const MachineFunction *MF, const TargetRegisterInfo *TRI, DbgValueHistoryMap &Result)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static void collectChangingRegs(const MachineFunction *MF, const TargetRegisterInfo *TRI, BitVector &Regs)
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
static void clobberRegisterUses(RegDescribedVarsMap &RegVars, RegDescribedVarsMap::iterator I, DbgValueHistoryMap &HistMap, const MachineInstr &ClobberingInstr)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static void dropRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedVariable Var)
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
iterator find(const KeyT &Key)
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
bool isDebugValue() const
const MachineOperand & getOperand(unsigned i) const
void startInstrRange(InlinedVariable Var, const MachineInstr &MI)
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned isDescribedByReg(const MachineInstr &MI)
auto find(R &&Range, const T &Val) -> decltype(std::begin(Range))
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly...
MachineOperand class - Representation of each machine instruction operand.
static const MachineInstr * getFirstEpilogueInst(const MachineBasicBlock &MBB)
virtual const TargetLowering * getTargetLowering() const
static void addRegDescribedVar(RegDescribedVarsMap &RegVars, unsigned RegNo, InlinedVariable Var)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void endInstrRange(InlinedVariable Var, const MachineInstr &MI)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getRegisterForVar(InlinedVariable Var) const
std::pair< const DILocalVariable *, const DILocation * > InlinedVariable
This file describes how to lower LLVM code to machine code.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.