14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
24 #define GET_INSTRINFO_HEADER
25 #include "ARMGenInstrInfo.inc"
29 class ARMBaseRegisterInfo;
39 unsigned LoadImmOpc,
unsigned LoadOpc)
const;
69 RegSubRegPairAndIdx &InputReg)
const override;
85 RegSubRegPair &BaseReg,
86 RegSubRegPairAndIdx &InsertedReg)
const override;
97 unsigned OpIdx2)
const override;
104 getNoopForMachoTarget(NopInst);
130 bool AllowModify =
false)
const override;
132 int *BytesRemoved =
nullptr)
const override;
136 int *BytesAdded =
nullptr)
const override;
157 std::vector<MachineOperand> &Pred)
const override;
175 unsigned SrcReg,
bool KillSrc,
178 unsigned DestReg,
bool KillSrc,
182 const DebugLoc &DL,
unsigned DestReg,
unsigned SrcReg,
183 bool KillSrc)
const override;
200 unsigned DestReg,
unsigned SubIdx,
208 unsigned SubIdx,
unsigned State,
220 int64_t &Offset2)
const override;
231 int64_t Offset1, int64_t Offset2,
232 unsigned NumLoads)
const override;
239 unsigned NumCycles,
unsigned ExtraPredCycles,
244 unsigned NumF,
unsigned ExtraF,
249 return NumCycles == 1;
260 unsigned &SrcReg2,
int &CmpMask,
261 int &CmpValue)
const override;
268 unsigned SrcReg2,
int CmpMask,
int CmpValue,
273 unsigned &FalseOp,
bool &Optimizable)
const override;
277 bool)
const override;
290 unsigned UseIdx)
const override;
292 SDNode *DefNode,
unsigned DefIdx,
293 SDNode *UseNode,
unsigned UseIdx)
const override;
296 std::pair<uint16_t, uint16_t>
310 unsigned getInstBundleLength(
const MachineInstr &MI)
const;
315 unsigned DefIdx,
unsigned DefAlign)
const;
319 unsigned DefIdx,
unsigned DefAlign)
const;
323 unsigned UseIdx,
unsigned UseAlign)
const;
327 unsigned UseIdx,
unsigned UseAlign)
const;
330 unsigned DefIdx,
unsigned DefAlign,
332 unsigned UseIdx,
unsigned UseAlign)
const;
339 const MCInstrDesc &UseMCID,
unsigned UseAdj)
const;
341 unsigned getPredicationCost(
const MachineInstr &MI)
const override;
345 unsigned *PredCost =
nullptr)
const override;
348 SDNode *Node)
const override;
354 unsigned UseIdx)
const override;
357 unsigned DefIdx)
const override;
382 return MLxEntryMap.
count(Opcode);
389 unsigned &AddSubOpc,
bool &NegAcc,
390 bool &HasLane)
const;
396 return MLxHazardOpcodes.
count(Opcode);
416 bool isDead =
false) {
427 return Opc ==
ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
432 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
437 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
438 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
443 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
447 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
448 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
449 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
453 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
454 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
468 const MachineRegisterInfo &
MRI);
480 const DebugLoc &dl,
unsigned DestReg,
481 unsigned BaseReg,
int NumBytes,
483 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
487 const DebugLoc &dl,
unsigned DestReg,
488 unsigned BaseReg,
int NumBytes,
490 const ARMBaseInstrInfo &
TII,
unsigned MIFlags = 0);
493 const DebugLoc &dl,
unsigned DestReg,
494 unsigned BaseReg,
int NumBytes,
495 const TargetInstrInfo &
TII,
496 const ARMBaseRegisterInfo &
MRI,
497 unsigned MIFlags = 0);
505 MachineFunction &MF, MachineInstr *
MI,
513 unsigned FrameReg,
int &
Offset,
514 const ARMBaseInstrInfo &
TII);
517 unsigned FrameReg,
int &
Offset,
518 const ARMBaseInstrInfo &
TII);
bool isPredicable(MachineInstr &MI) const override
isPredicable - Return true if the specified instruction can be predicated.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
virtual void getNoopForElfTarget(MCInst &NopInst) const
bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const override
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
Describe properties that are true of each instruction in the target description file.
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isPredicated(const MachineInstr &MI) const override
MachineInstrBundleIterator< MachineInstr > iterator
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const
unsigned getPartialRegUpdateClearance(const MachineInstr &, unsigned, const TargetRegisterInfo *) const override
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
static const MachineInstrBuilder & AddNoT1CC(const MachineInstrBuilder &MIB)
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP...
Reg
All possible values of the reg field in the ModR/M byte.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
bool isFpMLxInstruction(unsigned Opcode) const
isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS instruction.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
bool canCauseFpMLxStall(unsigned Opcode) const
canCauseFpMLxStall - Return true if an instruction of the specified opcode will cause stalls when sch...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Itinerary data supplied by a subtarget to be used by a target.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
unsigned getMatchingCondBranchOpcode(unsigned Opc)
Instances of this class represent a single low-level machine instruction.
static bool isCondBranchOpcode(int Opc)
unsigned getDeadRegState(bool B)
unsigned getDefRegState(bool B)
unsigned const MachineRegisterInfo * MRI
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
MachineInstrBuilder & UseMI
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
const MachineOperand & getOperand(unsigned i) const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Returns the size of the specified MachineInstr.
static bool isJumpTableBranchOpcode(int Opc)
void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, bool KillSrc, const ARMSubtarget &Subtarget) const
MachineInstr * duplicate(MachineInstr &Orig, MachineFunction &MF) const override
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
VFP/NEON execution domains.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
static bool isIndirectBranchOpcode(int Opc)
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Iterator for intrusive lists based on ilist_node.
static bool isUncondBranchOpcode(int Opc)
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0
MachineOperand class - Representation of each machine instruction operand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
void breakPartialRegDependency(MachineInstr &, unsigned, const TargetRegisterInfo *TRI) const override
bool isSwiftFastImmShift(const MachineInstr *MI) const
Returns true if the instruction has a shift by immediate that can be executed in one cycle less...
Represents one node in the SelectionDAG.
static bool isPushOpcode(int Opc)
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool KillSrc, const ARMSubtarget &Subtarget) const
unsigned getNumLDMAddresses(const MachineInstr &MI) const
Get the number of addresses by LDM or VLDM or zero for unknown.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
unsigned canFoldARMInstrIntoMOVCC(unsigned Reg, MachineInstr *&MI, const MachineRegisterInfo &MRI)
Determine if MI can be folded into an ARM MOVCC instruction, and return the opcode of the SSA instruc...
ARMBaseInstrInfo(const ARMSubtarget &STI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
static bool isPopOpcode(int Opc)
Representation of each machine instruction.
bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const override
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const override
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Convert the instruction to set the zero flag so that we can remove a "comparis...
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
const ARMSubtarget & getSubtarget() const
StringRef - Represent a constant reference to a string, i.e.
bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI) const override
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static const MachineInstrBuilder & AddDefaultT1CC(const MachineInstrBuilder &MIB, bool isDead=false)
const MachineInstrBuilder & AddDReg(MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI) const
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override