30 #define DEBUG_TYPE "wasm-disassembler"
34 std::unique_ptr<const MCInstrInfo> MCII;
43 std::unique_ptr<const MCInstrInfo> MCII)
52 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII));
70 if (Pos +
sizeof(uint64_t) > Bytes.
size())
73 Pos +=
sizeof(uint64_t);
75 if (Opcode >= WebAssembly::INSTRUCTION_LIST_END)
83 unsigned NumExtraOperands = 0;
85 if (Pos +
sizeof(uint64_t) > Bytes.
size())
88 Pos +=
sizeof(uint64_t);
92 for (
unsigned i = 0;
i < NumFixedOperands; ++
i) {
99 if (Pos +
sizeof(uint64_t) > Bytes.
size())
102 Pos +=
sizeof(uint64_t);
107 if (Pos +
sizeof(uint64_t) > Bytes.
size())
110 Pos +=
sizeof(uint64_t);
118 if (Pos +
sizeof(uint64_t) > Bytes.
size())
121 Pos +=
sizeof(uint64_t);
123 memcpy(&Imm, &Bits,
sizeof(Imm));
134 for (
unsigned i = 0;
i < NumExtraOperands; ++
i) {
135 if (Pos +
sizeof(uint64_t) > Bytes.
size())
146 Pos +=
sizeof(uint64_t);
32-bit floating-point immediates.
void LLVMInitializeWebAssemblyDisassembler()
DecodeStatus
Ternary decode status.
Superclass for all disassemblers.
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
Basic block label in a branch construct.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end...
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
static MCOperand createReg(unsigned Reg)
Reg
All possible values of the reg field in the ModR/M byte.
Context object for machine code objects.
uint8_t OperandType
Information about the type of the operand.
size_t size() const
size - Get the array size.
Instances of this class represent a single low-level machine instruction.
unsigned short NumOperands
This file provides WebAssembly-specific target descriptions.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setOpcode(unsigned Op)
static MCOperand createFPImm(double Val)
Target - Wrapper for Target specific information.
64-bit floating-point immediates.
static MCDisassembler * createWebAssemblyDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
uint64_t read64le(const void *P)
p2align immediate for load and store address alignment.
MCSubtargetInfo - Generic base class for all target subtargets.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCOperandInfo * OpInfo
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
Target & getTheWebAssemblyTarget32()
This holds information about one operand of a machine instruction, indicating the register class for ...
Target & getTheWebAssemblyTarget64()
static MCOperand createImm(int64_t Val)