LLVM  4.0.0
ARMTargetTransformInfo.h
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1 //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
19 
20 #include "ARM.h"
21 #include "ARMTargetMachine.h"
25 
26 namespace llvm {
27 
28 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
30  typedef TargetTransformInfo TTI;
31  friend BaseT;
32 
33  const ARMSubtarget *ST;
34  const ARMTargetLowering *TLI;
35 
36  /// Estimate the overhead of scalarizing an instruction. Insert and Extract
37  /// are set if the result needs to be inserted and/or extracted from vectors.
38  unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
39 
40  const ARMSubtarget *getST() const { return ST; }
41  const ARMTargetLowering *getTLI() const { return TLI; }
42 
43 public:
44  explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
45  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
46  TLI(ST->getTargetLowering()) {}
47 
48  bool enableInterleavedAccessVectorization() { return true; }
49 
50  /// Floating-point computation using ARMv8 AArch32 Advanced
51  /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
52  /// is IEEE-754 compliant, but it's not covered in this target.
54  return !ST->isTargetDarwin();
55  }
56 
57  /// \name Scalar TTI Implementations
58  /// @{
59 
60  int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
61  Type *Ty);
62 
64  int getIntImmCost(const APInt &Imm, Type *Ty);
65 
66  int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
67 
68  /// @}
69 
70  /// \name Vector TTI Implementations
71  /// @{
72 
73  unsigned getNumberOfRegisters(bool Vector) {
74  if (Vector) {
75  if (ST->hasNEON())
76  return 16;
77  return 0;
78  }
79 
80  if (ST->isThumb1Only())
81  return 8;
82  return 13;
83  }
84 
85  unsigned getRegisterBitWidth(bool Vector) {
86  if (Vector) {
87  if (ST->hasNEON())
88  return 128;
89  return 0;
90  }
91 
92  return 32;
93  }
94 
95  unsigned getMaxInterleaveFactor(unsigned VF) {
96  return ST->getMaxInterleaveFactor();
97  }
98 
99  int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
100 
101  int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
102 
103  int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
104 
105  int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
106 
108  const SCEV *Ptr);
109 
110  int getFPOpCost(Type *Ty);
111 
113  unsigned Opcode, Type *Ty,
119 
120  int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
121  unsigned AddressSpace);
122 
123  int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
124  ArrayRef<unsigned> Indices, unsigned Alignment,
125  unsigned AddressSpace);
126 
128  // In the ROPI and RWPI relocation models we can't have pointers to global
129  // variables or functions in constant data, so don't convert switches to
130  // lookup tables if any of the values would need relocation.
131  if (ST->isROPI() || ST->isRWPI())
132  return !C->needsRelocation();
133 
134  return true;
135  }
136  /// @}
137 };
138 
139 } // end namespace llvm
140 
141 #endif
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)
bool enableInterleavedAccessVectorization()
bool shouldBuildLookupTablesForConstant(Constant *C) const
unsigned getRegisterBitWidth(bool Vector)
unsigned getMaxInterleaveFactor(unsigned VF)
The main scalar evolution driver.
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace)
bool isROPI() const
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:40
bool isThumb1Only() const
Definition: ARMSubtarget.h:577
unsigned getIntImmCost(const APInt &Imm, Type *Ty)
bool isTargetDarwin() const
Definition: ARMSubtarget.h:508
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src)
int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
#define F(x, y, z)
Definition: MD5.cpp:51
unsigned getNumberOfRegisters(bool Vector)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool hasNEON() const
Definition: ARMSubtarget.h:449
ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important base class in LLVM.
Definition: Constant.h:42
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
bool needsRelocation() const
This method classifies the entry according to whether or not it may generate a relocation entry...
Definition: Constants.cpp:415
bool isRWPI() const
OperandValueProperties
Additional properties of an operand's values.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy)
AddressSpace
Definition: NVPTXBaseInfo.h:22
int getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
Class for arbitrary precision integers.
Definition: APInt.h:77
const DataLayout & getDataLayout() const
bool isFPVectorizationPotentiallyUnsafe()
Floating-point computation using ARMv8 AArch32 Advanced SIMD instructions remains unchanged from ARMv...
This class represents an analyzed expression in the program.
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:641
int getIntImmCost(const APInt &Imm, Type *Ty)
const unsigned Kind
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info=TTI::OK_AnyValue, TTI::OperandValueKind Op2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
static const Function * getParent(const Value *V)
int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
OperandValueKind
Additional information about an operand's possible values.
This pass exposes codegen information to IR-level passes.
int * Ptr
This file describes how to lower LLVM code to machine code.
ShuffleKind
The various kinds of shuffle patterns for vector queries.