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LLVM
4.0.0
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#include "AArch64InstrInfo.h"#include "llvm/ADT/Statistic.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/TargetSchedule.h"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "aarch64-vectorbyelement-opt" |
| #define | AARCH64_VECTOR_BY_ELEMENT_OPT_NAME "AArch64 vector by element instruction optimization pass" |
Functions | |
| STATISTIC (NumModifiedInstr,"Number of vector by element instructions modified") | |
| if (!SCDesc->isValid()||SCDesc->isVariant()||!SCDescRep1->isValid()||SCDescRep1->isVariant()||!SCDescRep2->isValid()||SCDescRep2->isVariant()) | |
| if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > SchedModel.computeInstrLatency(InstDescRep1->getOpcode())+SchedModel.computeInstrLatency(InstDescRep2->getOpcode())) | |
Variables | |
| INITIALIZE_PASS(AArch64VectorByElementOpt,"aarch64-vectorbyelement-opt", AARCH64_VECTOR_BY_ELEMENT_OPT_NAME, false, false) bool AArch64VectorByElementOpt unsigned | SCIdx = InstDesc->getSchedClass() |
| Based only on latency of instructions, determine if it is cost efficient to replace the instruction InstDesc by the two instructions InstDescRep1 and InstDescRep2. More... | |
| unsigned | SCIdxRep1 = InstDescRep1->getSchedClass() |
| unsigned | SCIdxRep2 = InstDescRep2->getSchedClass() |
| const MCSchedClassDesc * | SCDesc |
| const MCSchedClassDesc * | SCDescRep1 |
| const MCSchedClassDesc * | SCDescRep2 |
| VecInstElemTable [InstDesc->getOpcode()] = false | |
| return | false |
| #define AARCH64_VECTOR_BY_ELEMENT_OPT_NAME "AArch64 vector by element instruction optimization pass" |
Definition at line 37 of file AArch64VectorByElementOpt.cpp.
| #define DEBUG_TYPE "aarch64-vectorbyelement-opt" |
Definition at line 32 of file AArch64VectorByElementOpt.cpp.
| if | ( | !SCDesc-> | isValid)||SCDesc->isVariant()||!SCDescRep1->isValid()||SCDescRep1->isVariant()||!SCDescRep2->isValid()||SCDescRep2->isVariant( | ) |
Definition at line 127 of file AArch64VectorByElementOpt.cpp.
| if | ( | SchedModel. | computeInstrLatencyInstDesc->getOpcode(), |
| SchedModel. | computeInstrLatencyInstDescRep1->getOpcode())+SchedModel.computeInstrLatency(InstDescRep2->getOpcode() | ||
| ) |
Definition at line 134 of file AArch64VectorByElementOpt.cpp.
| STATISTIC | ( | NumModifiedInstr | , |
| "Number of vector by element instructions modified" | |||
| ) |
| return false |
Definition at line 141 of file AArch64VectorByElementOpt.cpp.
| const MCSchedClassDesc* SCDesc |
Definition at line 118 of file AArch64VectorByElementOpt.cpp.
Referenced by llvm::TargetSchedModel::computeOperandLatency(), getLatency(), and llvm::TargetSchedModel::resolveSchedClass().
| const MCSchedClassDesc* SCDescRep1 |
Definition at line 120 of file AArch64VectorByElementOpt.cpp.
| const MCSchedClassDesc* SCDescRep2 |
Definition at line 122 of file AArch64VectorByElementOpt.cpp.
| INITIALIZE_PASS (AArch64VectorByElementOpt, "aarch64-vectorbyelement-opt", AARCH64_VECTOR_BY_ELEMENT_OPT_NAME, false, false) bool AArch64VectorByElementOpt unsigned SCIdx = InstDesc->getSchedClass() |
Based only on latency of instructions, determine if it is cost efficient to replace the instruction InstDesc by the two instructions InstDescRep1 and InstDescRep2.
Note that it is assumed in this fuction that an instruction of type InstDesc is always replaced by the same two instructions as results are cached here. Return true if replacement is recommended.
Definition at line 115 of file AArch64VectorByElementOpt.cpp.
Referenced by llvm::TargetSchedModel::computeInstrLatency().
| unsigned SCIdxRep1 = InstDescRep1->getSchedClass() |
Definition at line 116 of file AArch64VectorByElementOpt.cpp.
| unsigned SCIdxRep2 = InstDescRep2->getSchedClass() |
Definition at line 117 of file AArch64VectorByElementOpt.cpp.
| VecInstElemTable[InstDesc->getOpcode()] = false |
Definition at line 140 of file AArch64VectorByElementOpt.cpp.
1.8.6