28 #define DEBUG_TYPE "wasm-lower-br_unless"
33 return "WebAssembly Lower br_unless";
51 return new WebAssemblyLowerBrUnless();
54 bool WebAssemblyLowerBrUnless::runOnMachineFunction(
MachineFunction &MF) {
55 DEBUG(
dbgs() <<
"********** Lowering br_unless **********\n"
56 "********** Function: "
63 for (
auto &
MBB : MF) {
66 if (MI->
getOpcode() != WebAssembly::BR_UNLESS)
70 bool Inverted =
false;
73 if (MFI.isVRegStackified(Cond)) {
76 switch (Def->getOpcode()) {
77 using namespace WebAssembly;
78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted =
true;
break;
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted =
true;
break;
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted =
true;
break;
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted =
true;
break;
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted =
true;
break;
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted =
true;
break;
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted =
true;
break;
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted =
true;
break;
86 case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted =
true;
break;
87 case LE_U_I32: Def->setDesc(TII.get(GT_U_I32)); Inverted =
true;
break;
88 case EQ_I64: Def->setDesc(TII.get(NE_I64)); Inverted =
true;
break;
89 case NE_I64: Def->setDesc(TII.get(EQ_I64)); Inverted =
true;
break;
90 case GT_S_I64: Def->setDesc(TII.get(LE_S_I64)); Inverted =
true;
break;
91 case GE_S_I64: Def->setDesc(TII.get(LT_S_I64)); Inverted =
true;
break;
92 case LT_S_I64: Def->setDesc(TII.get(GE_S_I64)); Inverted =
true;
break;
93 case LE_S_I64: Def->setDesc(TII.get(GT_S_I64)); Inverted =
true;
break;
94 case GT_U_I64: Def->setDesc(TII.get(LE_U_I64)); Inverted =
true;
break;
95 case GE_U_I64: Def->setDesc(TII.get(LT_U_I64)); Inverted =
true;
break;
96 case LT_U_I64: Def->setDesc(TII.get(GE_U_I64)); Inverted =
true;
break;
97 case LE_U_I64: Def->setDesc(TII.get(GT_U_I64)); Inverted =
true;
break;
98 case EQ_F32: Def->setDesc(TII.get(NE_F32)); Inverted =
true;
break;
99 case NE_F32: Def->setDesc(TII.get(EQ_F32)); Inverted =
true;
break;
100 case EQ_F64: Def->setDesc(TII.get(NE_F64)); Inverted =
true;
break;
101 case NE_F64: Def->setDesc(TII.get(EQ_F64)); Inverted =
true;
break;
109 unsigned Tmp =
MRI.createVirtualRegister(&WebAssembly::I32RegClass);
112 MFI.stackifyVReg(Tmp);
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end...
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
This file provides WebAssembly-specific target descriptions.
Represent the analysis usage information of a pass.
FunctionPass * createWebAssemblyLowerBrUnless()
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
FunctionPass class - This class is used to implement most global optimizations.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Representation of each machine instruction.
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This file declares WebAssembly-specific per-machine-function information.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
StringRef - Represent a constant reference to a string, i.e.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.