15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
37 class InstrItineraryData;
270 EVT VT)
const override;
277 SDNode *Node)
const override;
291 bool *
Fast)
const override;
294 unsigned DstAlign,
unsigned SrcAlign,
295 bool IsMemset,
bool ZeroMemset,
310 Type *Ty,
unsigned AS)
const override;
317 unsigned AS)
const override;
350 unsigned Depth)
const override;
360 AsmOperandInfo &
info,
const char *constraint)
const override;
362 std::pair<unsigned, const TargetRegisterClass *>
373 std::vector<SDValue> &Ops,
378 if (ConstraintCode ==
"Q")
380 else if (ConstraintCode ==
"o")
382 else if (ConstraintCode.
size() == 2) {
383 if (ConstraintCode[0] ==
'U') {
384 switch(ConstraintCode[1]) {
422 unsigned &PrefAlign)
const override;
442 unsigned Intrinsic)
const override;
447 Type *Ty)
const override;
477 bool IsStore,
bool IsLoad)
const override;
479 bool IsStore,
bool IsLoad)
const override;
486 unsigned Factor)
const override;
488 unsigned Factor)
const override;
501 unsigned &Cost)
const override;
511 return HasStandaloneRem;
518 std::pair<const TargetRegisterClass *, uint8_t>
520 MVT VT)
const override;
533 unsigned ARMPCLabelIndex;
537 bool InsertFencesForAtomic;
539 bool HasStandaloneRem =
true;
541 void addTypeForNEON(
MVT VT,
MVT PromotedLdStVT,
MVT PromotedBitwiseVT);
542 void addDRTypeForNEON(
MVT VT);
543 void addQRTypeForNEON(
MVT VT);
549 SDValue &Arg, RegsToPassVector &RegsToPass,
556 const SDLoc &dl)
const;
559 bool isVarArg)
const;
561 bool isVarArg)
const;
613 unsigned getRegisterByName(
const char* RegName,
EVT VT,
625 bool isFMAFasterThanFMulAndFAdd(
EVT VT)
const override {
return false; }
627 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG)
const;
629 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
631 const SmallVectorImpl<ISD::InputArg> &
Ins,
632 const SDLoc &dl, SelectionDAG &DAG,
633 SmallVectorImpl<SDValue> &InVals,
bool isThisReturn,
634 SDValue ThisVal)
const;
636 bool supportSplitCSR(MachineFunction *MF)
const override {
638 MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
641 void initializeSplitCSR(MachineBasicBlock *Entry)
const override;
642 void insertCopiesSplitCSR(
643 MachineBasicBlock *Entry,
644 const SmallVectorImpl<MachineBasicBlock *> &Exits)
const override;
647 LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
648 const SmallVectorImpl<ISD::InputArg> &
Ins,
649 const SDLoc &dl, SelectionDAG &DAG,
650 SmallVectorImpl<SDValue> &InVals)
const override;
652 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
const SDLoc &dl,
653 SDValue &Chain,
const Value *OrigArg,
654 unsigned InRegsParamRecordIdx,
int ArgOffset,
657 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
658 const SDLoc &dl, SDValue &Chain,
659 unsigned ArgOffset,
unsigned TotalArgRegsSaveSize,
660 bool ForceMutable =
false)
const;
662 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
663 SmallVectorImpl<SDValue> &InVals)
const override;
666 void HandleByVal(CCState *,
unsigned &,
unsigned)
const override;
671 bool IsEligibleForTailCallOptimization(SDValue Callee,
674 bool isCalleeStructRet,
675 bool isCallerStructRet,
676 const SmallVectorImpl<ISD::OutputArg> &Outs,
677 const SmallVectorImpl<SDValue> &OutVals,
678 const SmallVectorImpl<ISD::InputArg> &
Ins,
679 SelectionDAG& DAG)
const;
682 MachineFunction &MF,
bool isVarArg,
683 const SmallVectorImpl<ISD::OutputArg> &Outs,
684 LLVMContext &
Context)
const override;
686 SDValue LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
687 const SmallVectorImpl<ISD::OutputArg> &Outs,
688 const SmallVectorImpl<SDValue> &OutVals,
689 const SDLoc &dl, SelectionDAG &DAG)
const override;
691 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain)
const override;
693 bool mayBeEmittedAsTailCall(CallInst *CI)
const override;
695 SDValue getCMOV(
const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
696 SDValue ARMcc, SDValue CCR, SDValue Cmp,
697 SelectionDAG &DAG)
const;
698 SDValue getARMCmp(SDValue LHS, SDValue RHS,
ISD::CondCode CC,
699 SDValue &ARMcc, SelectionDAG &DAG,
const SDLoc &dl)
const;
700 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
701 const SDLoc &dl)
const;
702 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG)
const;
704 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG)
const;
706 void SetupEntryBlockForSjLj(MachineInstr &
MI, MachineBasicBlock *
MBB,
707 MachineBasicBlock *DispatchBB,
int FI)
const;
709 void EmitSjLjDispatchBlock(MachineInstr &
MI, MachineBasicBlock *
MBB)
const;
711 bool RemapAddSubWithFlags(MachineInstr &
MI, MachineBasicBlock *BB)
const;
713 MachineBasicBlock *EmitStructByval(MachineInstr &
MI,
714 MachineBasicBlock *
MBB)
const;
716 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &
MI,
717 MachineBasicBlock *
MBB)
const;
718 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &
MI,
719 MachineBasicBlock *
MBB)
const;
731 const TargetLibraryInfo *libInfo);
737 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
BUILTIN_OP_END - This must be the last enum value in this list.
A parsed version of the target data layout string in and methods for querying it. ...
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag...
const char * LowerXConstraint(EVT ConstraintVT) const override
Try to replace an X constraint, which matches anything, with another that has more specific requireme...
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
This class represents a function call, abstracting a target machine's calling convention.
bool hasStandaloneRem(EVT VT) const override
Return true if the target can handle a standalone remainder operation.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
An instruction for reading from memory.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vstN intrinsic.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
struct fuzzer::@269 Flags
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPostIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mo...
AtomicOrdering
Atomic ordering for LLVM's memory model.
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const override
Return true if the target can combine store(extractelement VectorTy, Idx).
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vldN intrinsic.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself...
Itinerary data supplied by a subtarget to be used by a target.
An instruction for storing to memory.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
bool useSoftFloat() const override
SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, unsigned &PrefAlign) const override
Return true if the pointer arguments to CI should be aligned by aligning the object whose address is ...
This is an important class for using LLVM in a threaded context.
This is an important base class in LLVM.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override
Return the largest legal super-reg register class of the register class for the specified type and it...
int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM...
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const
PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
EVT - Extended Value Type.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const ARMSubtarget * getSubtarget() const
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Provides information about what library functions are available for the current target.
CCValAssign - Represent assignment of one arg/retval to a location.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Represents one node in the SelectionDAG.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool ExpandInlineAsm(CallInst *CI) const override
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
Class for arbitrary precision integers.
Instruction * emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
AddrMode
ARM Addressing Modes.
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
const TargetRegisterClass * getRegClassFor(MVT VT) const override
getRegClassFor - Return the register class that should be used for the specified value type...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const override
getTgtMemIntrinsic - Represent NEON load and store intrinsics as MemIntrinsicNodes.
Representation of each machine instruction.
SelectSupportKind
Enum that describes what type of support for selects the target has.
bool isVectorLoadExtDesirable(SDValue ExtVal) const override
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns true if the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass into a ...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const
PerformBRCONDCombine - Target-specific DAG combining for ARMISD::BRCOND.
bool isSelectSupported(SelectSupportKind Kind) const override
bool isShuffleMaskLegal(const SmallVectorImpl< int > &M, EVT VT) const override
isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE oper...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
LLVM Value Representation.
bool useLoadStackGuardNode() const override
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
Instruction * makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const
ARMTargetLowering(const TargetMachine &TM, const ARMSubtarget &STI)
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
bool isBitFieldInvertedMask(unsigned v)
TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Instruction * emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const override
This file describes how to lower LLVM code to machine code.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align, bool *Fast) const override
allowsMisalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses of the s...
void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.