16 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
17 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
22 #define GET_INSTRINFO_HEADER
23 #define GET_INSTRINFO_ENUM
24 #include "AMDGPUGenInstrInfo.inc"
28 class AMDGPUSubtarget;
29 class MachineFunction;
31 class MachineInstrBuilder;
37 virtual void anchor();
43 int64_t Offset1, int64_t Offset2,
44 unsigned NumLoads)
const override;
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Cha...
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
AMDGPUInstrInfo(const AMDGPUSubtarget &st)
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
Represents one node in the SelectionDAG.