LLVM  4.0.0
LiveRegMatrix.cpp
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1 //===-- LiveRegMatrix.cpp - Track register interference -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the LiveRegMatrix analysis pass.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "RegisterCoalescer.h"
16 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "regalloc"
27 
28 STATISTIC(NumAssigned , "Number of registers assigned");
29 STATISTIC(NumUnassigned , "Number of registers unassigned");
30 
31 char LiveRegMatrix::ID = 0;
32 INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix",
33  "Live Register Matrix", false, false)
37  "Live Register Matrix", false, false)
38 
39 LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID),
40  UserTag(0), RegMaskTag(0), RegMaskVirtReg(0) {}
41 
42 void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
43  AU.setPreservesAll();
47 }
48 
49 bool LiveRegMatrix::runOnMachineFunction(MachineFunction &MF) {
50  TRI = MF.getSubtarget().getRegisterInfo();
51  LIS = &getAnalysis<LiveIntervals>();
52  VRM = &getAnalysis<VirtRegMap>();
53 
54  unsigned NumRegUnits = TRI->getNumRegUnits();
55  if (NumRegUnits != Matrix.size())
56  Queries.reset(new LiveIntervalUnion::Query[NumRegUnits]);
57  Matrix.init(LIUAlloc, NumRegUnits);
58 
59  // Make sure no stale queries get reused.
61  return false;
62 }
63 
64 void LiveRegMatrix::releaseMemory() {
65  for (unsigned i = 0, e = Matrix.size(); i != e; ++i) {
66  Matrix[i].clear();
67  // No need to clear Queries here, since LiveIntervalUnion::Query doesn't
68  // have anything important to clear and LiveRegMatrix's runOnFunction()
69  // does a std::unique_ptr::reset anyways.
70  }
71 }
72 
73 template <typename Callable>
74 static bool foreachUnit(const TargetRegisterInfo *TRI,
75  LiveInterval &VRegInterval, unsigned PhysReg,
76  Callable Func) {
77  if (VRegInterval.hasSubRanges()) {
78  for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
79  unsigned Unit = (*Units).first;
80  LaneBitmask Mask = (*Units).second;
81  for (LiveInterval::SubRange &S : VRegInterval.subranges()) {
82  if ((S.LaneMask & Mask).any()) {
83  if (Func(Unit, S))
84  return true;
85  break;
86  }
87  }
88  }
89  } else {
90  for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
91  if (Func(*Units, VRegInterval))
92  return true;
93  }
94  }
95  return false;
96 }
97 
98 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
99  DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
100  << " to " << PrintReg(PhysReg, TRI) << ':');
101  assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
102  VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
103 
104  foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
105  const LiveRange &Range) {
106  DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range);
107  Matrix[Unit].unify(VirtReg, Range);
108  return false;
109  });
110 
111  ++NumAssigned;
112  DEBUG(dbgs() << '\n');
113 }
114 
116  unsigned PhysReg = VRM->getPhys(VirtReg.reg);
117  DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
118  << " from " << PrintReg(PhysReg, TRI) << ':');
119  VRM->clearVirt(VirtReg.reg);
120 
121  foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
122  const LiveRange &Range) {
123  DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI));
124  Matrix[Unit].extract(VirtReg, Range);
125  return false;
126  });
127 
128  ++NumUnassigned;
129  DEBUG(dbgs() << '\n');
130 }
131 
132 bool LiveRegMatrix::isPhysRegUsed(unsigned PhysReg) const {
133  for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
134  if (!Matrix[*Unit].empty())
135  return true;
136  }
137  return false;
138 }
139 
141  unsigned PhysReg) {
142  // Check if the cached information is valid.
143  // The same BitVector can be reused for all PhysRegs.
144  // We could cache multiple VirtRegs if it becomes necessary.
145  if (RegMaskVirtReg != VirtReg.reg || RegMaskTag != UserTag) {
146  RegMaskVirtReg = VirtReg.reg;
147  RegMaskTag = UserTag;
148  RegMaskUsable.clear();
149  LIS->checkRegMaskInterference(VirtReg, RegMaskUsable);
150  }
151 
152  // The BitVector is indexed by PhysReg, not register unit.
153  // Regmask interference is more fine grained than regunits.
154  // For example, a Win64 call can clobber %ymm8 yet preserve %xmm8.
155  return !RegMaskUsable.empty() && (!PhysReg || !RegMaskUsable.test(PhysReg));
156 }
157 
159  unsigned PhysReg) {
160  if (VirtReg.empty())
161  return false;
162  CoalescerPair CP(VirtReg.reg, PhysReg, *TRI);
163 
164  bool Result = foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
165  const LiveRange &Range) {
166  const LiveRange &UnitRange = LIS->getRegUnit(Unit);
167  return Range.overlaps(UnitRange, CP, *LIS->getSlotIndexes());
168  });
169  return Result;
170 }
171 
173  unsigned RegUnit) {
174  LiveIntervalUnion::Query &Q = Queries[RegUnit];
175  Q.init(UserTag, &VirtReg, &Matrix[RegUnit]);
176  return Q;
177 }
178 
180 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) {
181  if (VirtReg.empty())
182  return IK_Free;
183 
184  // Regmask interference is the fastest check.
185  if (checkRegMaskInterference(VirtReg, PhysReg))
186  return IK_RegMask;
187 
188  // Check for fixed interference.
189  if (checkRegUnitInterference(VirtReg, PhysReg))
190  return IK_RegUnit;
191 
192  // Check the matrix for virtual register interference.
193  for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
194  if (query(VirtReg, *Units).checkInterference())
195  return IK_VirtReg;
196 
197  return IK_Free;
198 }
No interference, go ahead and assign.
Definition: LiveRegMatrix.h:81
const unsigned reg
Definition: LiveInterval.h:656
bool isValid() const
Returns true if this iterator is not yet at the end.
STATISTIC(NumFunctions,"Total number of functions")
size_t i
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg)
Check for interference before assigning VirtReg to PhysReg.
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:625
liveregmatrix
A live range for subregisters.
Definition: LiveInterval.h:632
void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU)
bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs)
checkRegMaskInterference - Test if LI is live across any register mask instructions, and compute a bit mask of physical registers that are not clobbered by any of them.
bool empty() const
Definition: LiveInterval.h:357
Live Register Matrix
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:153
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
void clear()
clear - Clear all bits.
Definition: BitVector.h:188
Query interferences between a single live virtual register and a live interval union.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
A helper class for register coalescers.
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:710
Register unit interference.
Definition: LiveRegMatrix.h:91
void assign(LiveInterval &VirtReg, unsigned PhysReg)
Assign VirtReg to PhysReg.
RegMask interference.
Definition: LiveRegMatrix.h:96
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
Definition: LiveRegMatrix.h:77
SlotIndexes * getSlotIndexes() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool empty() const
empty - Tests whether there are no bits in this bitvector.
Definition: BitVector.h:116
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
Definition: LiveInterval.h:423
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
bool isPhysRegUsed(unsigned PhysReg) const
Returns true if the given PhysReg has any live intervals assigned.
void unassign(LiveInterval &VirtReg)
Unassign VirtReg from its PhysReg.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
bool test(unsigned Idx) const
Definition: BitVector.h:323
bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg)
Check for regunit interference only.
void init(LiveIntervalUnion::Allocator &, unsigned Size)
Promote Memory to Register
Definition: Mem2Reg.cpp:100
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void setPreservesAll()
Set by analyses that do not transform their input at all.
static bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, unsigned PhysReg, Callable Func)
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
AnalysisUsage & addRequiredTransitive()
LiveIntervalUnion::Query & query(LiveInterval &VirtReg, unsigned RegUnit)
Query a line of the assigned virtual register matrix directly.
std::vector< uint8_t > Unit
Definition: FuzzerDefs.h:71
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
#define DEBUG(X)
Definition: Debug.h:100
bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg=0)
Check for regmask interference only.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Live Register false
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:738
Virtual register interference.
Definition: LiveRegMatrix.h:86
LiveRange & getRegUnit(unsigned Unit)
getRegUnit - Return the live range for Unit.
INITIALIZE_PASS_BEGIN(LiveRegMatrix,"liveregmatrix","Live Register Matrix", false, false) INITIALIZE_PASS_END(LiveRegMatrix