LLVM  4.0.0
ARMSubtarget.cpp
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1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMSubtarget.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMISelLowering.h"
17 #include "ARMInstrInfo.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSelectionDAGInfo.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "Thumb1FrameLowering.h"
23 #include "Thumb1InstrInfo.h"
24 #include "Thumb2InstrInfo.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "arm-subtarget"
39 
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
43 
44 static cl::opt<bool>
45 UseFusedMulOps("arm-use-mulops",
46  cl::init(true), cl::Hidden);
47 
48 enum ITMode {
52 };
53 
54 static cl::opt<ITMode>
55 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
57  cl::values(clEnumValN(DefaultIT, "arm-default-it",
58  "Generate IT block based on arch"),
59  clEnumValN(RestrictedIT, "arm-restrict-it",
60  "Disallow deprecated IT based on ARMv8"),
61  clEnumValN(NoRestrictedIT, "arm-no-restrict-it",
62  "Allow IT blocks based on ARMv7")));
63 
64 /// ForceFastISel - Use the fast-isel, even for subtargets where it is not
65 /// currently supported (for testing only).
66 static cl::opt<bool>
67 ForceFastISel("arm-force-fast-isel",
68  cl::init(false), cl::Hidden);
69 
70 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
71 /// so that we can use initializer lists for subtarget initialization.
73  StringRef FS) {
74  initializeEnvironment();
75  initSubtargetFeatures(CPU, FS);
76  return *this;
77 }
78 
79 /// EnableExecuteOnly - Enables the generation of execute-only code on supported
80 /// targets
81 static cl::opt<bool>
82 EnableExecuteOnly("arm-execute-only");
83 
84 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
85  StringRef FS) {
87  if (STI.isThumb1Only())
88  return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
89 
90  return new ARMFrameLowering(STI);
91 }
92 
93 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
94  const std::string &FS,
95  const ARMBaseTargetMachine &TM, bool IsLittle)
96  : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
97  GenExecuteOnly(EnableExecuteOnly), CPUString(CPU), IsLittle(IsLittle),
98  TargetTriple(TT), Options(TM.Options), TM(TM),
99  FrameLowering(initializeFrameLowering(CPU, FS)),
100  // At this point initializeSubtargetDependencies has been called so
101  // we can query directly.
102  InstrInfo(isThumb1Only()
103  ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
104  : !isThumb()
105  ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
106  : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
107  TLInfo(TM, *this), GISel() {}
108 
110  assert(GISel && "Access to GlobalISel APIs not set");
111  return GISel->getCallLowering();
112 }
113 
115  assert(GISel && "Access to GlobalISel APIs not set");
116  return GISel->getInstructionSelector();
117 }
118 
120  assert(GISel && "Access to GlobalISel APIs not set");
121  return GISel->getLegalizerInfo();
122 }
123 
125  assert(GISel && "Access to GlobalISel APIs not set");
126  return GISel->getRegBankInfo();
127 }
128 
130  // We don't currently suppport Thumb, but Windows requires Thumb.
131  return hasV6Ops() && hasARMOps() && !isTargetWindows();
132 }
133 
134 void ARMSubtarget::initializeEnvironment() {
135  // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
136  // directly from it, but we can try to make sure they're consistent when both
137  // available.
139  assert((!TM.getMCAsmInfo() ||
142  "inconsistent sjlj choice between CodeGen and MC");
143 }
144 
145 void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
146  if (CPUString.empty()) {
147  CPUString = "generic";
148 
149  if (isTargetDarwin()) {
150  StringRef ArchName = TargetTriple.getArchName();
151  unsigned ArchKind = llvm::ARM::parseArch(ArchName);
152  if (ArchKind == llvm::ARM::AK_ARMV7S)
153  // Default to the Swift CPU when targeting armv7s/thumbv7s.
154  CPUString = "swift";
155  else if (ArchKind == llvm::ARM::AK_ARMV7K)
156  // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
157  // ARMv7k does not use SjLj exception handling.
158  CPUString = "cortex-a7";
159  }
160  }
161 
162  // Insert the architecture feature derived from the target triple into the
163  // feature string. This is important for setting features that are implied
164  // based on the architecture version.
165  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
166  if (!FS.empty()) {
167  if (!ArchFS.empty())
168  ArchFS = (Twine(ArchFS) + "," + FS).str();
169  else
170  ArchFS = FS;
171  }
173 
174  // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
175  // Assert this for now to make the change obvious.
176  assert(hasV6T2Ops() || !hasThumb2());
177 
178  // Execute only support requires movt support
179  if (genExecuteOnly())
180  assert(hasV8MBaselineOps() && !NoMovt && "Cannot generate execute-only code for this target");
181 
182  // Keep a pointer to static instruction cost data for the specified CPU.
183  SchedModel = getSchedModelForCPU(CPUString);
184 
185  // Initialize scheduling itinerary for the specified CPU.
186  InstrItins = getInstrItineraryForCPU(CPUString);
187 
188  // FIXME: this is invalid for WindowsCE
189  if (isTargetWindows())
190  NoARM = true;
191 
192  if (isAAPCS_ABI())
193  stackAlignment = 8;
194  if (isTargetNaCl() || isAAPCS16_ABI())
195  stackAlignment = 16;
196 
197  // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
198  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
199  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
200  // support in the assembler and linker to be used. This would need to be
201  // fixed to fully support tail calls in Thumb1.
202  //
203  // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
204  // LR. This means if we need to reload LR, it takes an extra instructions,
205  // which outweighs the value of the tail call; but here we don't know yet
206  // whether LR is going to be used. Probably the right approach is to
207  // generate the tail call here and turn it back into CALL/RET in
208  // emitEpilogue if LR is used.
209 
210  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
211  // but we need to make sure there are enough registers; the only valid
212  // registers are the 4 used for parameters. We don't currently do this
213  // case.
214 
216 
217  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
218  SupportsTailCall = false;
219 
220  switch (IT) {
221  case DefaultIT:
222  RestrictIT = hasV8Ops();
223  break;
224  case RestrictedIT:
225  RestrictIT = true;
226  break;
227  case NoRestrictedIT:
228  RestrictIT = false;
229  break;
230  }
231 
232  // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
233  const FeatureBitset &Bits = getFeatureBits();
234  if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
237 
238  if (isRWPI())
239  ReserveR9 = true;
240 
241  // FIXME: Teach TableGen to deal with these instead of doing it manually here.
242  switch (ARMProcFamily) {
243  case Others:
244  case CortexA5:
245  break;
246  case CortexA7:
248  break;
249  case CortexA8:
251  break;
252  case CortexA9:
255  break;
256  case CortexA12:
257  break;
258  case CortexA15:
262  break;
263  case CortexA17:
264  case CortexA32:
265  case CortexA35:
266  case CortexA53:
267  case CortexA57:
268  case CortexA72:
269  case CortexA73:
270  case CortexR4:
271  case CortexR4F:
272  case CortexR5:
273  case CortexR7:
274  case CortexM3:
275  case ExynosM1:
276  case CortexR52:
277  break;
278  case Krait:
280  break;
281  case Swift:
286  break;
287  }
288 }
289 
293 }
298 }
302 }
303 
304 bool ARMSubtarget::isROPI() const {
305  return TM.getRelocationModel() == Reloc::ROPI ||
307 }
308 bool ARMSubtarget::isRWPI() const {
309  return TM.getRelocationModel() == Reloc::RWPI ||
311 }
312 
314  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
315  return true;
316 
317  // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
318  // the section that is being relocated. This means we have to use o load even
319  // for GVs that are known to be local to the dso.
321  (GV->isDeclarationForLinker() || GV->hasCommonLinkage()))
322  return true;
323 
324  return false;
325 }
326 
329 }
330 
332  return isTargetWatchOS() ||
333  (isTargetIOS() && !getTargetTriple().isOSVersionLT(7, 0));
334 }
335 
337  // Enable the MachineScheduler before register allocation for out-of-order
338  // architectures where we do not use the PostRA scheduler anymore (for now
339  // restricted to swift).
340  return getSchedModel().isOutOfOrder() && isSwift();
341 }
342 
343 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
345  // No need for PostRA scheduling on out of order CPUs (for now restricted to
346  // swift).
347  if (getSchedModel().isOutOfOrder() && isSwift())
348  return false;
349  return (!isThumb() || hasThumb2());
350 }
351 
353 
355  // For general targets, the prologue can grow when VFPs are allocated with
356  // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
357  // format which it's more important to get right.
358  return isTargetWatchABI() || (isSwift() && !MF.getFunction()->optForMinSize());
359 }
360 
361 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
362  // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
363  // immediates as it is inherently position independent, and may be out of
364  // range otherwise.
365  return !NoMovt && hasV8MBaselineOps() &&
367 }
368 
370  // Enable fast-isel for any target, for testing only.
371  if (ForceFastISel)
372  return true;
373 
374  // Limit fast-isel to the targets that are or have been tested.
375  if (!hasV6Ops())
376  return false;
377 
378  // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
379  return TM.Options.EnableFastISel &&
380  ((isTargetMachO() && !isThumb1Only()) ||
381  (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
382 }
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:148
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT,"arm-default-it","Generate IT block based on arch"), clEnumValN(RestrictedIT,"arm-restrict-it","Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT,"arm-no-restrict-it","Allow IT blocks based on ARMv7")))
unsigned MispredictPenalty
Definition: MCSchedule.h:180
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:315
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:337
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
unsigned getMispredictionPenalty() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
static cl::opt< bool > EnableExecuteOnly("arm-execute-only")
EnableExecuteOnly - Enables the generation of execute-only code on supported targets.
bool isAAPCS16_ABI() const
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
DWARF-like instruction based exceptions.
bool useFastISel() const
True if fast-isel is used.
bool isROPI() const
bool hasV6Ops() const
Definition: ARMSubtarget.h:417
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:420
const LegalizerInfo * getLegalizerInfo() const override
bool isThumb1Only() const
Definition: ARMSubtarget.h:577
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:348
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:153
static bool isThumb(const MCSubtargetInfo &STI)
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:461
Holds all the information related to register banks.
bool hasV8Ops() const
Definition: ARMSubtarget.h:422
bool hasCommonLinkage() const
Definition: GlobalValue.h:419
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool hasThumb2() const
Definition: ARMSubtarget.h:579
bool isTargetDarwin() const
Definition: ARMSubtarget.h:508
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool useStride4VFPs(const MachineFunction &MF) const
This file contains the simple types necessary to represent the attributes associated with functions a...
bool isThumb() const
Definition: ARMSubtarget.h:576
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:506
bool enableAtomicExpand() const override
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:68
virtual bool isXRaySupported() const override
bool isTargetMachO() const
Definition: ARMSubtarget.h:519
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:141
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:331
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:464
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:510
bool hasARMOps() const
Definition: ARMSubtarget.h:443
bool isTargetIOS() const
Definition: ARMSubtarget.h:509
ValuesClass values(OptsTy...Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:615
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:78
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:292
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
bool isPositionIndependent() const
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:538
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:511
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:425
const CallLowering * getCallLowering() const override
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
bool genExecuteOnly() const
Definition: ARMSubtarget.h:500
bool isRWPI() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool isTargetNaCl() const
Definition: ARMSubtarget.h:513
bool isSwift() const
Definition: ARMSubtarget.h:436
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const InstructionSelector * getInstructionSelector() const override
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:340
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:346
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:130
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:388
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:590
Provides the logic to select generic machine instructions.
bool isAPCS_ABI() const
bool isAAPCS_ABI() const
bool isTargetLinux() const
Definition: ARMSubtarget.h:512
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:144
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
Definition: Triple.cpp:903
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:343
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:114
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:323
unsigned parseArch(StringRef Arch)
bool useMovt(const MachineFunction &MF) const
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:327
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:537
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:73
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:65
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:318
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
ITMode
bool isDeclarationForLinker() const
Definition: GlobalValue.h:496
bool isTargetWindows() const
Definition: ARMSubtarget.h:515
const RegisterBankInfo * getRegBankInfo() const override
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:311
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:320