27 #define DEBUG_TYPE "legalize-types"
37 void DAGTypeLegalizer::PromoteIntegerResult(
SDNode *
N,
unsigned ResNo) {
48 dbgs() <<
"PromoteIntegerResult #" << ResNo <<
": ";
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N);
break;
57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N);
break;
61 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N);
break;
62 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N);
break;
64 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N);
break;
66 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N);
break;
67 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));
break;
68 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
70 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
72 case ISD::SELECT: Res = PromoteIntRes_SELECT(N);
break;
73 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N);
break;
75 case ISD::SETCC: Res = PromoteIntRes_SETCC(N);
break;
77 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N);
break;
79 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N);
break;
81 case ISD::SHL: Res = PromoteIntRes_SHL(N);
break;
83 Res = PromoteIntRes_SIGN_EXTEND_INREG(N);
break;
84 case ISD::SRA: Res = PromoteIntRes_SRA(N);
break;
85 case ISD::SRL: Res = PromoteIntRes_SRL(N);
break;
87 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N);
break;
88 case ISD::VAARG: Res = PromoteIntRes_VAARG(N);
break;
91 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N);
break;
93 Res = PromoteIntRes_VECTOR_SHUFFLE(N);
break;
95 Res = PromoteIntRes_INSERT_VECTOR_ELT(N);
break;
97 Res = PromoteIntRes_BUILD_VECTOR(N);
break;
99 Res = PromoteIntRes_SCALAR_TO_VECTOR(N);
break;
101 Res = PromoteIntRes_CONCAT_VECTORS(N);
break;
106 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N);
break;
122 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N);
break;
125 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N);
break;
128 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N);
break;
131 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo);
break;
133 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo);
break;
135 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo);
break;
138 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N));
break;
151 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N));
break;
155 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
161 SetPromotedInteger(
SDValue(N, ResNo), Res);
166 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
167 return GetPromotedInteger(Op);
177 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(
SDNode *N) {
238 for (
unsigned i = 1, NumResults = N->
getNumValues();
i < NumResults; ++
i)
251 switch (getTypeAction(InVT)) {
264 SDValue PromotedOp = GetPromotedFloat(InOp);
275 BitConvertToInteger(GetScalarizedVector(InOp)));
282 Lo = BitConvertToInteger(Lo);
283 Hi = BitConvertToInteger(Hi);
291 JoinIntegers(Lo, Hi));
303 CreateStackStoreLoad(InOp, OutVT));
319 SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(
SDNode *N) {
332 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(
SDNode *N) {
341 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(
SDNode *N) {
351 assert(isa<ConstantSDNode>(Result) &&
"Didn't constant fold ext?");
385 OVT.getScalarSizeInBits());
391 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(
SDNode *N) {
398 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(
SDNode *N) {
426 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(
SDNode *N) {
433 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(
SDNode *N) {
494 "Gather result type and the passThru agrument type should be the same");
509 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(
SDNode *N) {
519 ReplaceValueWith(
SDValue(N, 0), Res);
524 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(
SDNode *N,
unsigned ResNo) {
526 return PromoteIntRes_Overflow(N);
548 ReplaceValueWith(
SDValue(N, 1), Ofl);
565 Mask = PromoteTargetBoolean(Mask, OpTy);
572 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(
SDNode *N) {
592 "Vector compare must return a vector result!");
598 !LHS.getValueType().isVector())
599 LHS = GetPromotedInteger(LHS);
602 RHS = GetPromotedInteger(RHS);
609 assert(NVT.bitsLE(SVT) &&
"Integer type overpromoted?");
618 LHS = GetPromotedInteger(LHS);
620 RHS = ZExtPromotedInteger(RHS);
624 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(
SDNode *N) {
630 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(
SDNode *N) {
640 SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(
SDNode *N) {
648 SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(
SDNode *N) {
661 LHS = SExtPromotedInteger(LHS);
663 RHS = ZExtPromotedInteger(RHS);
672 LHS = ZExtPromotedInteger(LHS);
674 RHS = ZExtPromotedInteger(RHS);
678 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(
SDNode *N) {
691 Res = GetPromotedInteger(InOp);
698 "Dst and Src must have the same number of elements");
700 "Promoted vector type must be a power of two");
703 GetSplitVector(InOp, EOp1, EOp2);
717 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(
SDNode *N,
unsigned ResNo) {
719 return PromoteIntRes_Overflow(N);
740 ReplaceValueWith(
SDValue(N, 1), Ofl);
745 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(
SDNode *N,
unsigned ResNo) {
748 return PromoteIntRes_Overflow(N);
759 LHS = SExtPromotedInteger(LHS);
760 RHS = SExtPromotedInteger(RHS);
762 LHS = ZExtPromotedInteger(LHS);
763 RHS = ZExtPromotedInteger(RHS);
793 ReplaceValueWith(
SDValue(N, 1), Overflow);
813 for (
unsigned i = 0;
i < NumRegs; ++
i) {
826 for (
unsigned i = 1;
i < NumRegs; ++
i) {
837 ReplaceValueWith(
SDValue(N, 1), Chain);
850 bool DAGTypeLegalizer::PromoteIntegerOperand(
SDNode *N,
unsigned OpNo) {
860 dbgs() <<
"PromoteIntegerOperand Op #" << OpNo <<
": ";
867 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
869 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N);
break;
870 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo);
break;
871 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo);
break;
877 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
break;
879 Res = PromoteIntOp_SCALAR_TO_VECTOR(N);
break;
881 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo);
break;
882 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo);
break;
883 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo);
break;
886 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
888 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
890 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
892 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
894 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
906 case ISD::ROTR: Res = PromoteIntOp_Shift(N);
break;
910 if (!Res.getNode())
return false;
914 if (Res.getNode() ==
N)
918 "Invalid operand expansion");
920 ReplaceValueWith(
SDValue(N, 0), Res);
926 void DAGTypeLegalizer::PromoteSetCCOperands(
SDValue &NewLHS,
SDValue &NewRHS,
935 SDValue OpL = GetPromotedInteger(NewLHS);
936 SDValue OpR = GetPromotedInteger(NewRHS);
942 unsigned OpLEffectiveBits =
944 unsigned OpREffectiveBits =
951 NewLHS = ZExtPromotedInteger(NewLHS);
952 NewRHS = ZExtPromotedInteger(NewRHS);
963 NewLHS = ZExtPromotedInteger(NewLHS);
964 NewRHS = ZExtPromotedInteger(NewRHS);
970 NewLHS = SExtPromotedInteger(NewLHS);
971 NewRHS = SExtPromotedInteger(NewRHS);
976 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(
SDNode *N) {
993 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(
SDNode *N,
unsigned OpNo) {
994 assert(OpNo == 2 &&
"Don't know how to promote this operand!");
998 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->
getOperand(1))->
get());
1007 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(
SDNode *N,
unsigned OpNo) {
1008 assert(OpNo == 1 &&
"only know how to promote condition");
1018 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(
SDNode *N) {
1032 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(
SDNode *N) {
1039 "Legal vector of one illegal element?");
1046 "Type of inserted value narrower than vector element type!");
1049 for (
unsigned i = 0; i < NumElts; ++
i)
1055 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(
SDNode *N,
1064 "Type of inserted value narrower than vector element type!");
1071 assert(OpNo == 2 &&
"Different operand and result vector types?");
1080 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(
SDNode *N) {
1087 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(
SDNode *N,
unsigned OpNo) {
1088 assert(OpNo == 0 &&
"Only know how to promote the condition!");
1094 Cond = PromoteTargetBoolean(Cond, OpVT);
1100 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(
SDNode *N,
unsigned OpNo) {
1101 assert(OpNo == 0 &&
"Don't know how to promote this operand!");
1105 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->
getOperand(4))->
get());
1112 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(
SDNode *N,
unsigned OpNo) {
1113 assert(OpNo == 0 &&
"Don't know how to promote this operand!");
1117 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->
getOperand(2))->
get());
1128 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(
SDNode *N) {
1136 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(
SDNode *N) {
1161 bool TruncateStore =
false;
1169 Mask = PromoteTargetBoolean(Mask, DataVT);
1172 return PromoteIntOp_MSTORE(N, 3);
1175 return WidenVecOp_MSTORE(N, 3);
1179 return SplitVecOp_MSTORE(N, 3);
1183 assert(OpNo == 3 &&
"Unexpected operand for promotion");
1184 DataOp = GetPromotedInteger(DataOp);
1185 Mask = PromoteTargetBoolean(Mask, DataOp.
getValueType());
1186 TruncateStore =
true;
1196 assert(OpNo == 2 &&
"Only know how to promote the mask!");
1200 NewOps[OpNo] =
Mask;
1211 NewOps[OpNo] = PromoteTargetBoolean(N->
getOperand(OpNo), DataVT);
1213 NewOps[OpNo] = GetPromotedInteger(N->
getOperand(OpNo));
1217 if (Res.getNode() ==
N)
1231 NewOps[OpNo] = PromoteTargetBoolean(N->
getOperand(OpNo), DataVT);
1233 NewOps[OpNo] = GetPromotedInteger(N->
getOperand(OpNo));
1237 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(
SDNode *N) {
1242 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(
SDNode *N) {
1247 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(
SDNode *N) {
1264 void DAGTypeLegalizer::ExpandIntegerResult(
SDNode *N,
unsigned ResNo) {
1276 dbgs() <<
"ExpandIntegerResult #" << ResNo <<
": ";
1279 llvm_unreachable(
"Do not know how to expand the result of this operator!");
1282 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi);
break;
1284 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi);
break;
1286 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi);
break;
1290 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi);
break;
1296 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi);
break;
1297 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi);
break;
1299 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi);
break;
1300 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi);
break;
1302 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi);
break;
1306 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
break;
1307 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi);
break;
1309 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi);
break;
1312 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi);
break;
1313 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi);
break;
1314 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi);
break;
1315 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi);
break;
1331 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1332 SplitInteger(Tmp.first, Lo, Hi);
1333 ReplaceValueWith(
SDValue(N, 1), Tmp.second);
1350 SplitInteger(Tmp, Lo, Hi);
1351 ReplaceValueWith(
SDValue(N, 1), Success);
1358 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi);
break;
1363 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi);
break;
1366 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi);
break;
1369 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi);
break;
1372 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi);
break;
1376 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi);
break;
1379 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi);
break;
1381 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi);
break;
1383 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi);
break;
1392 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(
SDNode *Node) {
1398 return ExpandChainLibCall(LC, Node,
false);
1403 void DAGTypeLegalizer::ExpandShiftByConstant(
SDNode *N,
const APInt &Amt,
1408 GetExpandedInteger(N->
getOperand(0), InL, InH);
1424 if (Amt.
ugt(VTBits)) {
1426 }
else if (Amt.
ugt(NVTBits)) {
1429 NVT, InL, DAG.
getConstant(Amt - NVTBits, DL, ShTy));
1430 }
else if (Amt == NVTBits) {
1445 if (Amt.
ugt(VTBits)) {
1447 }
else if (Amt.
ugt(NVTBits)) {
1449 NVT, InH, DAG.
getConstant(Amt - NVTBits, DL, ShTy));
1451 }
else if (Amt == NVTBits) {
1466 if (Amt.
ugt(VTBits)) {
1469 }
else if (Amt.
ugt(NVTBits)) {
1474 }
else if (Amt == NVTBits) {
1492 bool DAGTypeLegalizer::
1500 "Expanded integer type size not a power of two!");
1504 APInt KnownZero, KnownOne;
1508 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1513 GetExpandedInteger(N->
getOperand(0), InL, InH);
1542 if ((KnownZero & HighBitMask) == HighBitMask) {
1580 bool DAGTypeLegalizer::
1587 "Expanded integer type size not a power of two!");
1592 GetExpandedInteger(N->
getOperand(0), InL, InH);
1617 Lo = DAG.
getSelect(dl, NVT, isShort, LoS, LoL);
1618 Hi = DAG.
getSelect(dl, NVT, isZero, InH,
1619 DAG.
getSelect(dl, NVT, isShort, HiS, HiL));
1634 Lo = DAG.
getSelect(dl, NVT, isZero, InL,
1635 DAG.
getSelect(dl, NVT, isShort, LoS, LoL));
1636 Hi = DAG.
getSelect(dl, NVT, isShort, HiS, HiL);
1650 Lo = DAG.
getSelect(dl, NVT, isZero, InL,
1651 DAG.
getSelect(dl, NVT, isShort, LoS, LoL));
1652 Hi = DAG.
getSelect(dl, NVT, isShort, HiS, HiL);
1672 void DAGTypeLegalizer::ExpandIntRes_MINMAX(
SDNode *N,
1680 SDValue LHSL, LHSH, RHSL, RHSH;
1681 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
1682 GetExpandedInteger(N->
getOperand(1), RHSL, RHSH);
1685 EVT NVT = LHSL.getValueType();
1686 EVT CCT = getSetCCResultType(NVT);
1702 Lo = DAG.
getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
1705 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(
SDNode *N,
1709 SDValue LHSL, LHSH, RHSL, RHSH;
1710 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
1711 GetExpandedInteger(N->
getOperand(1), RHSL, RHSH);
1714 SDValue LoOps[2] = { LHSL, RHSL };
1715 SDValue HiOps[3] = { LHSH, RHSH };
1768 Hi = DAG.
getNode(RevOpc, dl, NVT, Hi, OVF);
1776 SDValue Cmp1 = DAG.
getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1781 SDValue Cmp2 = DAG.
getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1790 DAG.
getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1799 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(
SDNode *N,
1802 SDValue LHSL, LHSH, RHSL, RHSH;
1804 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
1805 GetExpandedInteger(N->
getOperand(1), RHSL, RHSH);
1807 SDValue LoOps[2] = { LHSL, RHSL };
1808 SDValue HiOps[3] = { LHSH, RHSH };
1825 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(
SDNode *N,
1828 SDValue LHSL, LHSH, RHSL, RHSH;
1830 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
1831 GetExpandedInteger(N->
getOperand(1), RHSL, RHSH);
1834 SDValue HiOps[3] = { LHSH, RHSH };
1845 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(
SDNode *N,
1859 "Only know how to promote this result!");
1860 SDValue Res = GetPromotedInteger(Op);
1862 "Operand over promoted?");
1864 SplitInteger(Res, Lo, Hi);
1868 void DAGTypeLegalizer::ExpandIntRes_AssertSext(
SDNode *N,
1874 unsigned NVTBits = NVT.getSizeInBits();
1877 if (NVTBits < EVTBits) {
1880 EVTBits - NVTBits)));
1890 void DAGTypeLegalizer::ExpandIntRes_AssertZext(
SDNode *N,
1895 EVT EVT = cast<VTSDNode>(N->
getOperand(1))->getVT();
1896 unsigned NVTBits = NVT.getSizeInBits();
1899 if (NVTBits < EVTBits) {
1902 EVTBits - NVTBits)));
1910 void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(
SDNode *N,
1918 void DAGTypeLegalizer::ExpandIntRes_BSWAP(
SDNode *N,
1926 void DAGTypeLegalizer::ExpandIntRes_Constant(
SDNode *N,
1930 auto Constant = cast<ConstantSDNode>(
N);
1932 bool IsTarget =
Constant->isTargetOpcode();
1933 bool IsOpaque =
Constant->isOpaque();
1935 Lo = DAG.
getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1936 Hi = DAG.
getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1940 void DAGTypeLegalizer::ExpandIntRes_CTLZ(
SDNode *N,
1953 Lo = DAG.
getSelect(dl, NVT, HiNotZero, HiLZ,
1960 void DAGTypeLegalizer::ExpandIntRes_CTPOP(
SDNode *N,
1971 void DAGTypeLegalizer::ExpandIntRes_CTTZ(
SDNode *N,
1984 Lo = DAG.
getSelect(dl, NVT, LoNotZero, LoLZ,
1991 void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(
SDNode *N,
SDValue &Lo,
2004 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(
SDNode *N,
SDValue &Lo,
2011 Op = GetPromotedFloat(Op);
2015 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Op,
true, dl).first,
2019 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(
SDNode *N,
SDValue &Lo,
2026 Op = GetPromotedFloat(Op);
2030 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Op,
false, dl).first,
2034 void DAGTypeLegalizer::ExpandIntRes_LOAD(
LoadSDNode *N,
2037 ExpandRes_NormalLoad(N, Lo, Hi);
2059 Alignment, MMOFlags, AAInfo);
2084 unsigned ExcessBits =
2092 Hi = DAG.
getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2094 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2106 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2112 Alignment, MMOFlags, AAInfo);
2121 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2145 ReplaceValueWith(
SDValue(N, 1), Ch);
2148 void DAGTypeLegalizer::ExpandIntRes_Logical(
SDNode *N,
2152 GetExpandedInteger(N->
getOperand(0), LL, LH);
2153 GetExpandedInteger(N->
getOperand(1), RL, RH);
2158 void DAGTypeLegalizer::ExpandIntRes_MUL(
SDNode *N,
2165 GetExpandedInteger(N->
getOperand(0), LL, LH);
2166 GetExpandedInteger(N->
getOperand(1), RL, RH);
2190 unsigned HalfBits = Bits >> 1;
2233 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops,
true, dl).first,
2237 void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(
SDNode *N,
SDValue &Lo,
2248 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(
SDNode *Node,
2259 SplitInteger(Sum, Lo, Hi);
2287 ReplaceValueWith(
SDValue(Node, 1), Cmp);
2290 void DAGTypeLegalizer::ExpandIntRes_SDIV(
SDNode *N,
2313 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops,
true, dl).first,
Lo,
Hi);
2316 void DAGTypeLegalizer::ExpandIntRes_Shift(
SDNode *N,
2324 return ExpandShiftByConstant(N, CN->getAPIntValue(),
Lo,
Hi);
2328 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2350 GetExpandedInteger(N->
getOperand(0), LHSL, LHSH);
2360 "ShiftAmountTy is too small to cover the range of this type!");
2364 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2408 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops, isSigned, dl).first,
Lo,
Hi);
2412 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2416 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(
SDNode *N,
2434 "Only know how to promote this result!");
2435 SDValue Res = GetPromotedInteger(Op);
2437 "Operand over promoted?");
2439 SplitInteger(Res, Lo, Hi);
2447 void DAGTypeLegalizer::
2451 EVT EVT = cast<VTSDNode>(N->
getOperand(1))->getVT();
2473 void DAGTypeLegalizer::ExpandIntRes_SREM(
SDNode *N,
2496 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops,
true, dl).first,
Lo,
Hi);
2499 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(
SDNode *N,
2511 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(
SDNode *N,
2522 SplitInteger(Sum, Lo, Hi);
2531 ReplaceValueWith(
SDValue(N, 1), Ofl);
2534 void DAGTypeLegalizer::ExpandIntRes_XMULO(
SDNode *N,
2544 SplitInteger(MUL, Lo, Hi);
2558 ReplaceValueWith(
SDValue(N, 1), Overflow);
2591 Args.push_back(Entry);
2599 Args.push_back(Entry);
2604 CLI.setDebugLoc(dl).setChain(Chain)
2608 std::pair<SDValue, SDValue> CallInfo = TLI.
LowerCallTo(CLI);
2610 SplitInteger(CallInfo.first, Lo, Hi);
2617 ReplaceValueWith(
SDValue(N, 1), Ofl);
2620 void DAGTypeLegalizer::ExpandIntRes_UDIV(
SDNode *N,
2643 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops,
false, dl).first,
Lo,
Hi);
2646 void DAGTypeLegalizer::ExpandIntRes_UREM(
SDNode *N,
2669 SplitInteger(TLI.
makeLibCall(DAG, LC, VT, Ops,
false, dl).first,
Lo,
Hi);
2672 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(
SDNode *N,
2686 "Only know how to promote this result!");
2687 SDValue Res = GetPromotedInteger(Op);
2689 "Operand over promoted?");
2691 SplitInteger(Res, Lo, Hi);
2699 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(
SDNode *N,
2702 EVT VT = cast<AtomicSDNode>(
N)->getMemoryVT();
2707 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->
getOperand(0),
2722 bool DAGTypeLegalizer::ExpandIntegerOperand(
SDNode *N,
unsigned OpNo) {
2732 dbgs() <<
"ExpandIntegerOperand Op #" << OpNo <<
": ";
2738 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N);
break;
2744 case ISD::SETCC: Res = ExpandIntOp_SETCC(N);
break;
2745 case ISD::SETCCE: Res = ExpandIntOp_SETCCE(N);
break;
2747 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
break;
2755 case ISD::ROTR: Res = ExpandIntOp_Shift(N);
break;
2763 if (!Res.getNode())
return false;
2767 if (Res.getNode() ==
N)
2771 "Invalid operand expansion");
2773 ReplaceValueWith(
SDValue(N, 0), Res);
2779 void DAGTypeLegalizer::IntegerExpandSetCCOperands(
SDValue &NewLHS,
2783 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2784 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2785 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2788 if (RHSLo == RHSHi) {
2790 if (RHSCST->isAllOnesValue()) {
2810 if ((CCCode ==
ISD::SETLT && CST->isNullValue()) ||
2811 (CCCode ==
ISD::SETGT && CST->isAllOnesValue())) {
2843 RHSLo, LowCC,
false, DagCombineInfo, dl);
2850 RHSHi, CCCode,
false, DagCombineInfo, dl);
2862 if ((EqAllowed && (HiCmpC && HiCmpC->isNullValue())) ||
2863 (!EqAllowed && ((HiCmpC && (HiCmpC->getAPIntValue() == 1)) ||
2873 if (LHSHi == RHSHi) {
2888 bool FlipOperands =
false;
2916 DagCombineInfo, dl);
2921 NewLHS, LoCmp, HiCmp);
2928 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
2943 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(
SDNode *N) {
2946 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
2964 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode,
SDLoc(N));
2969 "Unexpected setcc expansion!");
2985 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2986 GetExpandedInteger(LHS, LHSLo, LHSHi);
2987 GetExpandedInteger(RHS, RHSLo, RHSHi);
3005 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(
SDNode *N) {
3014 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(
SDNode *N) {
3019 "Don't know how to expand this SINT_TO_FP!");
3025 return ExpandOp_NormalStore(N, OpNo);
3028 assert(OpNo == 1 &&
"Can only expand the stored value so far");
3055 unsigned ExcessBits =
3065 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
3074 unsigned EBytes = ExtVT.getStoreSize();
3076 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3078 ExtVT.getSizeInBits() - ExcessBits);
3103 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
3109 GetExpandedInteger(N->
getOperand(0), InL, InH);
3114 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(
SDNode *N) {
3134 const uint64_t F32TwoE32 = 0x4F800000ULL;
3135 const uint64_t F32TwoE64 = 0x5F800000ULL;
3136 const uint64_t F32TwoE128 = 0x7F800000ULL;
3140 FF =
APInt(32, F32TwoE32);
3142 FF =
APInt(32, F32TwoE64);
3144 FF =
APInt(32, F32TwoE128);
3150 GetExpandedInteger(Op, Lo, Hi);
3169 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->
getAlignment();
3172 Alignment =
std::min(Alignment, 4u);
3186 "Don't know how to expand this UINT_TO_FP!");
3187 return TLI.
makeLibCall(DAG, LC, DstVT, Op,
true, dl).first;
3190 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(
SDNode *N) {
3193 cast<AtomicSDNode>(N)->getMemoryVT(),
3196 cast<AtomicSDNode>(
N)->getMemOperand());
3201 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(
SDNode *N) {
3207 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3216 for (
unsigned i = 0; i != OutNumElems; ++
i) {
3233 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(
SDNode *N) {
3248 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(
SDNode *N) {
3251 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3259 for (
unsigned i = 0; i != NumElems; ++
i) {
3275 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(
SDNode *N) {
3280 "Input must be a scalar");
3284 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3292 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(
SDNode *N) {
3297 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3305 assert(NumElem * NumOperands == NumOutElem &&
3306 "Unexpected number of elements");
3310 for (
unsigned i = 0; i < NumOperands; ++
i) {
3312 for (
unsigned j = 0; j < NumElem; ++j) {
3323 SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(
SDNode *N) {
3326 assert(NVT.
isVector() &&
"This type must be promoted to a vector type");
3340 Promoted = SExtPromotedInteger(N->
getOperand(0));
3343 Promoted = ZExtPromotedInteger(N->
getOperand(0));
3346 Promoted = GetPromotedInteger(N->
getOperand(0));
3358 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(
SDNode *N) {
3361 assert(NOutVT.
isVector() &&
"This type must be promoted to a vector type");
3374 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(
SDNode *N) {
3388 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(
SDNode *N) {
3398 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(
SDNode *N) {
3408 for (
unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3413 for (
unsigned i=0; i<NumElem; ++
i) {
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
void push_back(const T &Elt)
unsigned Log2_32_Ceil(uint32_t Value)
Log2_32_Ceil - This function returns the ceil log base 2 of the specified value, 32 if the value is z...
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
SDValue getValue(unsigned R) const
const SDValue & getValue() const
static std::pair< ISD::CondCode, ISD::NodeType > getExpandedMinMaxOps(int Op)
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Flags getFlags() const
Return the raw flags of the source value,.
LLVMContext * getContext() const
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
BR_CC - Conditional branch.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
Carry-setting nodes for multiple precision addition and subtraction.
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in the KnownZero/KnownO...
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
const SDValue & getSrc0() const
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
unsigned getNumOperands() const
Return the number of values used by this operation.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned Num) const
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
void reserve(size_type N)
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
const SDValue & getBasePtr() const
SDValue getConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
SDValue getExternalSymbol(const char *Sym, EVT VT)
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
bool isVector() const
isVector - Return true if this is a vector value type.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Shift and rotation operations.
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
MachineFunction & getMachineFunction() const
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
MachinePointerInfo getWithOffset(int64_t O) const
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
This is an SDNode representing atomic operations.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
This class is used to represent an MSTORE node.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
static unsigned getAlignment(GlobalVariable *GV)
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
SDValue getMaskedGather(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO)
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isUNINDEXEDStore(const SDNode *N)
Returns true if the specified node is an unindexed store.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
Try to simplify a setcc built with the specified operands and cc.
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Simple integer binary arithmetic operators.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool isLittleEndian() const
Layout endianness...
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, bool IsTruncating=false, bool IsCompressing=false)
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
EVT getMemoryVT() const
Return the type of the in-memory value.
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value *PtrVal, unsigned Alignment, AtomicOrdering Ordering, SynchronizationScope SynchScope)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands...
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
UNDEF - An undefined node.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDNode * getNode() const
get the SDNode which holds the desired result
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
unsigned getScalarSizeInBits() const
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
bool isCompressingStore() const
Returns true if the op does a compression to the vector before storing.
Simple binary floating point operators.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
This is an important base class in LLVM.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Carry-using nodes for multiple precision addition and subtraction.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
Expand a MUL into two nodes.
const SDValue & getBasePtr() const
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType, bool IsExpanding=false)
const SDValue & getValue() const
Bit counting operators with an undefined result for zero inputs.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
EVT - Extended Value Type.
std::vector< ArgListEntry > ArgListTy
const SDValue & getMask() const
bool bitsEq(EVT VT) const
bitsEq - Return true if this has the same number of bits as VT.
This structure contains all information that is necessary for lowering calls.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
This class contains a discriminated union of information about pointers in memory operands...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Create a stack temporary, suitable for holding the specified value type.
const MachinePointerInfo & getPointerInfo() const
bool isUNINDEXEDLoad(const SDNode *N)
Returns true if the specified node is an unindexed load.
ArrayRef< int > getMask() const
bool ugt(const APInt &RHS) const
Unsigned greather than comparison.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
TokenFactor - This node takes multiple tokens as input and produces a single token result...
void dump() const
Dump this node, for debugging.
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
BRCOND - Conditional branch.
const SDValue & getChain() const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Represents one node in the SelectionDAG.
static unsigned int semanticsPrecision(const fltSemantics &)
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
const SDValue & getValue() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
Class for arbitrary precision integers.
Select(COND, TRUEVAL, FALSEVAL).
op_iterator op_begin() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
ANY_EXTEND - Used for integer types. The high bits are undefined.
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
iterator_range< value_op_iterator > op_values() const
Flags
Flags values. These may be or'd together.
const SDValue & getMask() const
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
Bitwise operators - logical and, logical or, logical xor.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
op_iterator op_end() const
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
This class is used to represent an MSCATTER node.
const SDValue & getIndex() const
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getCondCode(ISD::CondCode Cond)
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a carry value...
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, SynchronizationScope SynchScope)
Gets a node for an atomic cmpxchg op.
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input...
bool isByteSized() const
isByteSized - Return true if the bit size is a multiple of 8.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class is used to represent an MLOAD node.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
const SDValue & getBasePtr() const
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This class is used to represent an MGATHER node.
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits...
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
SetCC operator - This evaluates to a true value iff the condition is true.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
BooleanContent
Enum that describes how the target represents true/false values.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value...
TRUNCATE - Completely drop the high bits.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
unsigned getAlignment() const
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
getIntegerVT - Returns the EVT that represents an integer with the given number of bits...
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.