LLVM  4.0.0
AMDGPUMCInstLower.cpp
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1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12 //
13 //===----------------------------------------------------------------------===//
14 //
15 
16 #include "AMDGPUMCInstLower.h"
17 #include "AMDGPUAsmPrinter.h"
18 #include "AMDGPUSubtarget.h"
19 #include "AMDGPUTargetMachine.h"
21 #include "SIInstrInfo.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
32 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/Support/Format.h"
35 #include <algorithm>
36 
37 using namespace llvm;
38 
39 #include "AMDGPUGenMCPseudoLowering.inc"
40 
41 
43  const AsmPrinter &ap):
44  Ctx(ctx), ST(st), AP(ap) { }
45 
46 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) {
47  switch (MOFlags) {
48  default:
60  }
61 }
62 
63 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr(
64  const MachineBasicBlock &SrcBB,
65  const MachineOperand &MO) const {
66  const MCExpr *DestBBSym
68  const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx);
69 
70  assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 &&
71  ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
72 
73  // s_getpc_b64 returns the address of next instruction.
74  const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
75  SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
76 
78  return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
79 
81  return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
82 }
83 
85  MCOperand &MCOp) const {
86  switch (MO.getType()) {
87  default:
88  llvm_unreachable("unknown operand type");
90  MCOp = MCOperand::createImm(MO.getImm());
91  return true;
94  return true;
96  if (MO.getTargetFlags() != 0) {
97  MCOp = MCOperand::createExpr(
98  getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));
99  } else {
100  MCOp = MCOperand::createExpr(
102  }
103 
104  return true;
105  }
107  const GlobalValue *GV = MO.getGlobal();
108  SmallString<128> SymbolName;
109  AP.getNameWithPrefix(SymbolName, GV);
110  MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName);
111  const MCExpr *SymExpr =
113  const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr,
114  MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
115  MCOp = MCOperand::createExpr(Expr);
116  return true;
117  }
120  Sym->setExternal(true);
121  const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx);
122  MCOp = MCOperand::createExpr(Expr);
123  return true;
124  }
125  }
126 }
127 
128 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
129 
130  int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
131 
132  if (MCOpcode == -1) {
134  C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
135  "a target-specific version: " + Twine(MI->getOpcode()));
136  }
137 
138  OutMI.setOpcode(MCOpcode);
139 
140  for (const MachineOperand &MO : MI->explicit_operands()) {
141  MCOperand MCOp;
142  lowerOperand(MO, MCOp);
143  OutMI.addOperand(MCOp);
144  }
145 }
146 
148  MCOperand &MCOp) const {
150  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
151  return MCInstLowering.lowerOperand(MO, MCOp);
152 }
153 
156  return;
157 
159  AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
160 
161  StringRef Err;
162  if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
164  C.emitError("Illegal instruction detected: " + Err);
165  MI->dump();
166  }
167 
168  if (MI->isBundle()) {
169  const MachineBasicBlock *MBB = MI->getParent();
171  while (I != MBB->instr_end() && I->isInsideBundle()) {
172  EmitInstruction(&*I);
173  ++I;
174  }
175  } else {
176  // We don't want SI_MASK_BRANCH/SI_RETURN encoded. They are placeholder
177  // terminator instructions and should only be printed as comments.
178  if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
179  if (isVerbose()) {
180  SmallVector<char, 16> BBStr;
181  raw_svector_ostream Str(BBStr);
182 
183  const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
184  const MCSymbolRefExpr *Expr
186  Expr->print(Str, MAI);
187  OutStreamer->emitRawComment(" mask branch " + BBStr);
188  }
189 
190  return;
191  }
192 
193  if (MI->getOpcode() == AMDGPU::SI_RETURN) {
194  if (isVerbose())
195  OutStreamer->emitRawComment(" return");
196  return;
197  }
198 
199  if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
200  if (isVerbose())
201  OutStreamer->emitRawComment(" wave barrier");
202  return;
203  }
204 
205  MCInst TmpInst;
206  MCInstLowering.lower(MI, TmpInst);
207  EmitToStreamer(*OutStreamer, TmpInst);
208 
209  if (STI.dumpCode()) {
210  // Disassemble instruction/operands to text.
211  DisasmLines.resize(DisasmLines.size() + 1);
212  std::string &DisasmLine = DisasmLines.back();
213  raw_string_ostream DisasmStream(DisasmLine);
214 
215  AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
216  *STI.getInstrInfo(),
217  *STI.getRegisterInfo());
218  InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI);
219 
220  // Disassemble instruction/operands to hex representation.
222  SmallVector<char, 16> CodeBytes;
223  raw_svector_ostream CodeStream(CodeBytes);
224 
225  auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
226  MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
227  InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
229  HexLines.resize(HexLines.size() + 1);
230  std::string &HexLine = HexLines.back();
231  raw_string_ostream HexStream(HexLine);
232 
233  for (size_t i = 0; i < CodeBytes.size(); i += 4) {
234  unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
235  HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
236  }
237 
238  DisasmStream.flush();
239  DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
240  }
241  }
242 }
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const
Wrapper for MCInstLowering.lowerOperand() for the tblgen'erated pseudo lowering.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const AMDGPURegisterInfo * getRegisterInfo() const override=0
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
const GlobalValue * getGlobal() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:226
AMDGPU specific subclass of TargetSubtarget.
instr_iterator instr_end()
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:84
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:298
size_t i
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:307
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:79
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI)
tblgen'erated driver function for lowering simple MI->MC pseudo instructions.
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:87
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:490
MachineBasicBlock reference.
const char * getSymbolName() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:366
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Name of external global symbol.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:161
Context object for machine code objects.
Definition: MCContext.h:51
void emitError(unsigned LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
void EmitInstruction(const MachineInstr *MI) override
Implemented in AMDGPUMCInstLower.cpp.
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:497
MachineBasicBlock * MBB
Streaming object file generation interface.
void setExternal(bool Value) const
Definition: MCSymbol.h:387
int64_t getImm() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:429
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
format_object< Ts...> format(const char *Fmt, const Ts &...Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
bool isBundle() const
Definition: MachineInstr.h:804
Address of a global value.
unsigned getTargetFlags() const
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:75
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:71
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:67
int64_t getOffset() const
Return the offset from the symbol in this operand.
self_iterator getIterator()
Definition: ilist_node.h:81
The AMDGPU TargetMachine interface definition for hw codgen targets.
const AMDGPUInstrInfo * getInstrInfo() const override=0
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags)
Iterator for intrusive lists based on ilist_node.
std::vector< std::string > HexLines
void setOpcode(unsigned Op)
Definition: MCInst.h:158
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:161
void dump(const TargetInstrInfo *TII=nullptr) const
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
std::vector< std::string > DisasmLines
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
void lower(const MachineInstr *MI, MCInst &OutMI) const
Lower a MachineInstr to an MCInst.
Interface definition for SIInstrInfo.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:114
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
AMDGPU Assembly printer class.
MCSubtargetInfo - Generic base class for all target subtargets.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:33
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool isVerbose() const
Return true if assembly output should contain comments.
Definition: AsmPrinter.h:162
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST, const AsmPrinter &AP)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:149
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const