28 using namespace llvm::AMDGPU;
33 printInstruction(MI, STI, OS);
34 printAnnotation(OS, Annot);
37 void AMDGPUInstPrinter::printU4ImmOperand(
const MCInst *
MI,
unsigned OpNo,
43 void AMDGPUInstPrinter::printU8ImmOperand(
const MCInst *MI,
unsigned OpNo,
48 void AMDGPUInstPrinter::printU16ImmOperand(
const MCInst *MI,
unsigned OpNo,
55 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
57 printU32ImmOperand(MI, OpNo, STI, O);
60 void AMDGPUInstPrinter::printU4ImmDecOperand(
const MCInst *MI,
unsigned OpNo,
65 void AMDGPUInstPrinter::printU8ImmDecOperand(
const MCInst *MI,
unsigned OpNo,
70 void AMDGPUInstPrinter::printU16ImmDecOperand(
const MCInst *MI,
unsigned OpNo,
75 void AMDGPUInstPrinter::printU32ImmOperand(
const MCInst *MI,
unsigned OpNo,
81 void AMDGPUInstPrinter::printNamedBit(
const MCInst *MI,
unsigned OpNo,
88 void AMDGPUInstPrinter::printOffen(
const MCInst *MI,
unsigned OpNo,
90 printNamedBit(MI, OpNo, O,
"offen");
93 void AMDGPUInstPrinter::printIdxen(
const MCInst *MI,
unsigned OpNo,
95 printNamedBit(MI, OpNo, O,
"idxen");
98 void AMDGPUInstPrinter::printAddr64(
const MCInst *MI,
unsigned OpNo,
100 printNamedBit(MI, OpNo, O,
"addr64");
103 void AMDGPUInstPrinter::printMBUFOffset(
const MCInst *MI,
unsigned OpNo,
107 printU16ImmDecOperand(MI, OpNo, O);
111 void AMDGPUInstPrinter::printOffset(
const MCInst *MI,
unsigned OpNo,
117 printU16ImmDecOperand(MI, OpNo, O);
121 void AMDGPUInstPrinter::printOffset0(
const MCInst *MI,
unsigned OpNo,
126 printU8ImmDecOperand(MI, OpNo, O);
130 void AMDGPUInstPrinter::printOffset1(
const MCInst *MI,
unsigned OpNo,
135 printU8ImmDecOperand(MI, OpNo, O);
139 void AMDGPUInstPrinter::printSMRDOffset8(
const MCInst *MI,
unsigned OpNo,
142 printU32ImmOperand(MI, OpNo, STI, O);
145 void AMDGPUInstPrinter::printSMRDOffset20(
const MCInst *MI,
unsigned OpNo,
148 printU32ImmOperand(MI, OpNo, STI, O);
151 void AMDGPUInstPrinter::printSMRDLiteralOffset(
const MCInst *MI,
unsigned OpNo,
154 printU32ImmOperand(MI, OpNo, STI, O);
157 void AMDGPUInstPrinter::printGDS(
const MCInst *MI,
unsigned OpNo,
159 printNamedBit(MI, OpNo, O,
"gds");
162 void AMDGPUInstPrinter::printGLC(
const MCInst *MI,
unsigned OpNo,
164 printNamedBit(MI, OpNo, O,
"glc");
167 void AMDGPUInstPrinter::printSLC(
const MCInst *MI,
unsigned OpNo,
169 printNamedBit(MI, OpNo, O,
"slc");
172 void AMDGPUInstPrinter::printTFE(
const MCInst *MI,
unsigned OpNo,
174 printNamedBit(MI, OpNo, O,
"tfe");
177 void AMDGPUInstPrinter::printDMask(
const MCInst *MI,
unsigned OpNo,
181 printU16ImmOperand(MI, OpNo, STI, O);
185 void AMDGPUInstPrinter::printUNorm(
const MCInst *MI,
unsigned OpNo,
187 printNamedBit(MI, OpNo, O,
"unorm");
190 void AMDGPUInstPrinter::printDA(
const MCInst *MI,
unsigned OpNo,
192 printNamedBit(MI, OpNo, O,
"da");
195 void AMDGPUInstPrinter::printR128(
const MCInst *MI,
unsigned OpNo,
197 printNamedBit(MI, OpNo, O,
"r128");
200 void AMDGPUInstPrinter::printLWE(
const MCInst *MI,
unsigned OpNo,
202 printNamedBit(MI, OpNo, O,
"lwe");
205 void AMDGPUInstPrinter::printExpCompr(
const MCInst *MI,
unsigned OpNo,
212 void AMDGPUInstPrinter::printExpVM(
const MCInst *MI,
unsigned OpNo,
234 case AMDGPU::FLAT_SCR:
255 case AMDGPU::EXEC_LO:
258 case AMDGPU::EXEC_HI:
261 case AMDGPU::FLAT_SCR_LO:
262 O <<
"flat_scratch_lo";
264 case AMDGPU::FLAT_SCR_HI:
265 O <<
"flat_scratch_hi";
329 O <<
'[' << RegIdx <<
':' << (RegIdx + NumRegs - 1) <<
']';
332 void AMDGPUInstPrinter::printVOPDst(
const MCInst *MI,
unsigned OpNo,
346 void AMDGPUInstPrinter::printImmediate16(
uint32_t Imm,
349 int16_t SImm =
static_cast<int16_t
>(Imm);
350 if (SImm >= -16 && SImm <= 64) {
357 else if (Imm == 0xBC00)
359 else if (Imm == 0x3800)
361 else if (Imm == 0xB800)
363 else if (Imm == 0x4000)
365 else if (Imm == 0xC000)
367 else if (Imm == 0x4400)
369 else if (Imm == 0xC400)
371 else if (Imm == 0x3118) {
375 O << formatHex(static_cast<uint64_t>(Imm));
378 void AMDGPUInstPrinter::printImmediate32(
uint32_t Imm,
381 int32_t SImm =
static_cast<int32_t
>(Imm);
382 if (SImm >= -16 && SImm <= 64) {
405 else if (Imm == 0x3e22f983 &&
409 O << formatHex(static_cast<uint64_t>(Imm));
412 void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
415 int64_t SImm =
static_cast<int64_t
>(Imm);
416 if (SImm >= -16 && SImm <= 64) {
439 else if (Imm == 0x3fc45f306dc9c882 &&
447 O << formatHex(static_cast<uint64_t>(Imm));
451 void AMDGPUInstPrinter::printOperand(
const MCInst *MI,
unsigned OpNo,
455 O <<
"/*Missing OP" << OpNo <<
"*/";
463 case AMDGPU::PRED_SEL_OFF:
470 }
else if (Op.
isImm()) {
478 printImmediate32(Op.
getImm(), STI, O);
484 printImmediate64(Op.
getImm(), STI, O);
490 printImmediate16(Op.
getImm(), STI, O);
494 O << formatDec(Op.
getImm());
499 O <<
"/*invalid immediate*/";
516 else if (RCBits == 64)
529 void AMDGPUInstPrinter::printOperandAndFPInputMods(
const MCInst *MI,
539 if (InputModifiers & SISrcMods::ABS)
543 void AMDGPUInstPrinter::printOperandAndIntInputMods(
const MCInst *MI,
551 if (InputModifiers & SISrcMods::SEXT)
555 void AMDGPUInstPrinter::printDPPCtrl(
const MCInst *MI,
unsigned OpNo,
561 O << formatDec(Imm & 0x3) <<
',';
562 O << formatDec((Imm & 0xc) >> 2) <<
',';
563 O << formatDec((Imm & 0x30) >> 4) <<
',';
564 O << formatDec((Imm & 0xc0) >> 6) <<
']';
565 }
else if ((Imm >= 0x101) && (Imm <= 0x10f)) {
567 printU4ImmDecOperand(MI, OpNo, O);
568 }
else if ((Imm >= 0x111) && (Imm <= 0x11f)) {
570 printU4ImmDecOperand(MI, OpNo, O);
571 }
else if ((Imm >= 0x121) && (Imm <= 0x12f)) {
573 printU4ImmDecOperand(MI, OpNo, O);
574 }
else if (Imm == 0x130) {
576 }
else if (Imm == 0x134) {
578 }
else if (Imm == 0x138) {
580 }
else if (Imm == 0x13c) {
582 }
else if (Imm == 0x140) {
584 }
else if (Imm == 0x141) {
585 O <<
" row_half_mirror";
586 }
else if (Imm == 0x142) {
587 O <<
" row_bcast:15";
588 }
else if (Imm == 0x143) {
589 O <<
" row_bcast:31";
595 void AMDGPUInstPrinter::printRowMask(
const MCInst *MI,
unsigned OpNo,
599 printU4ImmOperand(MI, OpNo, STI, O);
602 void AMDGPUInstPrinter::printBankMask(
const MCInst *MI,
unsigned OpNo,
606 printU4ImmOperand(MI, OpNo, STI, O);
609 void AMDGPUInstPrinter::printBoundCtrl(
const MCInst *MI,
unsigned OpNo,
614 O <<
" bound_ctrl:0";
618 void AMDGPUInstPrinter::printSDWASel(
const MCInst *MI,
unsigned OpNo,
635 void AMDGPUInstPrinter::printSDWADstSel(
const MCInst *MI,
unsigned OpNo,
639 printSDWASel(MI, OpNo, O);
642 void AMDGPUInstPrinter::printSDWASrc0Sel(
const MCInst *MI,
unsigned OpNo,
646 printSDWASel(MI, OpNo, O);
649 void AMDGPUInstPrinter::printSDWASrc1Sel(
const MCInst *MI,
unsigned OpNo,
653 printSDWASel(MI, OpNo, O);
656 void AMDGPUInstPrinter::printSDWADstUnused(
const MCInst *MI,
unsigned OpNo,
671 template <
unsigned N>
672 void AMDGPUInstPrinter::printExpSrcN(
const MCInst *MI,
unsigned OpNo,
687 void AMDGPUInstPrinter::printExpSrc0(
const MCInst *MI,
unsigned OpNo,
690 printExpSrcN<0>(
MI, OpNo, STI, O);
693 void AMDGPUInstPrinter::printExpSrc1(
const MCInst *MI,
unsigned OpNo,
696 printExpSrcN<1>(
MI, OpNo, STI, O);
699 void AMDGPUInstPrinter::printExpSrc2(
const MCInst *MI,
unsigned OpNo,
702 printExpSrcN<2>(
MI, OpNo, STI, O);
705 void AMDGPUInstPrinter::printExpSrc3(
const MCInst *MI,
unsigned OpNo,
708 printExpSrcN<3>(
MI, OpNo, STI, O);
711 void AMDGPUInstPrinter::printExpTgt(
const MCInst *MI,
unsigned OpNo,
723 else if (Tgt >= 12 && Tgt <= 15)
724 O <<
" pos" << Tgt - 12;
725 else if (Tgt >= 32 && Tgt <= 63)
726 O <<
" param" << Tgt - 32;
729 O <<
" invalid_target_" << Tgt;
733 void AMDGPUInstPrinter::printInterpSlot(
const MCInst *MI,
unsigned OpNum,
748 O <<
"invalid_param_" << Imm;
752 void AMDGPUInstPrinter::printInterpAttr(
const MCInst *MI,
unsigned OpNum,
759 void AMDGPUInstPrinter::printInterpAttrChan(
const MCInst *MI,
unsigned OpNum,
763 O <<
'.' <<
"xyzw"[Chan & 0x3];
766 void AMDGPUInstPrinter::printVGPRIndexMode(
const MCInst *MI,
unsigned OpNo,
788 void AMDGPUInstPrinter::printMemOperand(
const MCInst *MI,
unsigned OpNo,
796 void AMDGPUInstPrinter::printIfSet(
const MCInst *MI,
unsigned OpNo,
808 void AMDGPUInstPrinter::printIfSet(
const MCInst *MI,
unsigned OpNo,
816 void AMDGPUInstPrinter::printAbs(
const MCInst *MI,
unsigned OpNo,
818 printIfSet(MI, OpNo, O,
'|');
821 void AMDGPUInstPrinter::printClamp(
const MCInst *MI,
unsigned OpNo,
823 printIfSet(MI, OpNo, O,
"_SAT");
826 void AMDGPUInstPrinter::printClampSI(
const MCInst *MI,
unsigned OpNo,
833 void AMDGPUInstPrinter::printOModSI(
const MCInst *MI,
unsigned OpNo,
845 void AMDGPUInstPrinter::printLiteral(
const MCInst *MI,
unsigned OpNo,
851 int64_t Imm = Op.
getImm();
859 void AMDGPUInstPrinter::printLast(
const MCInst *MI,
unsigned OpNo,
861 printIfSet(MI, OpNo, O,
"*",
" ");
864 void AMDGPUInstPrinter::printNeg(
const MCInst *MI,
unsigned OpNo,
866 printIfSet(MI, OpNo, O,
'-');
869 void AMDGPUInstPrinter::printOMOD(
const MCInst *MI,
unsigned OpNo,
885 void AMDGPUInstPrinter::printRel(
const MCInst *MI,
unsigned OpNo,
887 printIfSet(MI, OpNo, O,
'+');
890 void AMDGPUInstPrinter::printUpdateExecMask(
const MCInst *MI,
unsigned OpNo,
893 printIfSet(MI, OpNo, O,
"ExecMask,");
896 void AMDGPUInstPrinter::printUpdatePred(
const MCInst *MI,
unsigned OpNo,
899 printIfSet(MI, OpNo, O,
"Pred,");
902 void AMDGPUInstPrinter::printWrite(
const MCInst *MI,
unsigned OpNo,
910 void AMDGPUInstPrinter::printSel(
const MCInst *MI,
unsigned OpNo,
912 const char * chans =
"XYZW";
922 O << cb <<
'[' << sel <<
']';
923 }
else if (sel >= 448) {
926 }
else if (sel >= 0){
931 O <<
'.' << chans[chan];
934 void AMDGPUInstPrinter::printBankSwizzle(
const MCInst *MI,
unsigned OpNo,
938 switch (BankSwizzle) {
940 O <<
"BS:VEC_021/SCL_122";
943 O <<
"BS:VEC_120/SCL_212";
946 O <<
"BS:VEC_102/SCL_221";
959 void AMDGPUInstPrinter::printRSel(
const MCInst *MI,
unsigned OpNo,
989 void AMDGPUInstPrinter::printCT(
const MCInst *MI,
unsigned OpNo,
1004 void AMDGPUInstPrinter::printKCache(
const MCInst *MI,
unsigned OpNo,
1007 if (KCacheMode > 0) {
1009 O <<
"CB" << KCacheBank <<
':';
1011 int LineSize = (KCacheMode == 1) ? 16 : 32;
1012 O << KCacheAddr * 16 <<
'-' << KCacheAddr * 16 + LineSize;
1016 void AMDGPUInstPrinter::printSendMsg(
const MCInst *MI,
unsigned OpNo,
1019 using namespace llvm::AMDGPU::SendMsg;
1057 void AMDGPUInstPrinter::printWaitFlag(
const MCInst *MI,
unsigned OpNo,
1063 unsigned Vmcnt, Expcnt, Lgkmcnt;
1066 bool NeedSpace =
false;
1069 O <<
"vmcnt(" << Vmcnt <<
')';
1076 O <<
"expcnt(" << Expcnt <<
')';
1083 O <<
"lgkmcnt(" << Lgkmcnt <<
')';
1087 void AMDGPUInstPrinter::printHwreg(
const MCInst *MI,
unsigned OpNo,
1089 using namespace llvm::AMDGPU::Hwreg;
1103 O <<
", " <<
Offset <<
", " << Width;
1108 #include "AMDGPUGenAsmWriter.inc"
unsigned getExpcntBitMask(IsaVersion Version)
constexpr bool isUInt< 32 >(uint64_t x)
unsigned getVmcntBitMask(IsaVersion Version)
Describe properties that are true of each instruction in the target description file.
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
float BitsToFloat(uint32_t Bits)
BitsToFloat - This function takes a 32-bit integer and returns the bit equivalent float...
constexpr bool isInt< 16 >(int64_t x)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
Base class for the full range of assembler expressions which are needed for parsing.
uint8_t OperandType
Information about the type of the operand.
static std::string getRegisterName(const TargetRegisterInfo *TRI, unsigned Reg)
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
IsaVersion getIsaVersion(const FeatureBitset &Features)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const char *const IdSymbolic[]
const char *const IdSymbolic[]
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Operands with register or inline constant.
unsigned getLgkmcntBitMask(IsaVersion Version)
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
void decodeWaitcnt(IsaVersion Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
uint64_t DoubleToBits(double Double)
DoubleToBits - This function takes a double and returns the bit equivalent 64-bit integer...
unsigned getOpcode() const
const char *const OpSysSymbolic[]
const char *const OpGsSymbolic[]
Provides AMDGPU specific target descriptions.
static bool printOperand(raw_ostream &OS, const SelectionDAG *G, const SDValue Value)
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
unsigned getNumOperands() const
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
MCSubtargetInfo - Generic base class for all target subtargets.
constexpr bool isUInt< 16 >(uint64_t x)
Operands with register or 32-bit immediate.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MCOperandInfo * OpInfo
This class implements an extremely fast bulk output stream that can only output to a stream...
StringRef - Represent a constant reference to a string, i.e.
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const