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LLVM
4.0.0
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Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation. More...
#include <SelectionDAGNodes.h>
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| struct | DenseMapInfo< SDValue > |
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Many nodes return multiple values, from loads (which define a token and a return value) to ADDC (which returns a result and a carry value), to calls (which may return an arbitrary number of values).
As such, each use of a SelectionDAG computation must indicate the node that computes it as well as which return value to use from that node. This pair of information is represented with the SDValue value type.
Definition at line 118 of file SelectionDAGNodes.h.
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Definition at line 125 of file SelectionDAGNodes.h.
Referenced by getValue().
Definition at line 942 of file SelectionDAGNodes.h.
References assert().
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Definition at line 1004 of file SelectionDAGNodes.h.
References llvm::SDNode::dump().
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Definition at line 1008 of file SelectionDAGNodes.h.
References llvm::SDNode::dumpr().
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Definition at line 968 of file SelectionDAGNodes.h.
References llvm::SDNode::getConstantOperandVal().
Referenced by checkBoolTestSetCCCombine(), combineCompareEqual(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldXorTruncShiftIntoCmp(), getFauxShuffleMask(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), llvm::SelectionDAG::InferPtrAlignment(), LowerAsSplatVectorLoad(), LowerFRAMEADDR(), LowerRETURNADDR(), OptimizeConditionalInDecrement(), PeepholePPC64ZExtGather(), and willShiftRightEliminate().
Definition at line 1000 of file SelectionDAGNodes.h.
References llvm::SDNode::getDebugLoc().
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Definition at line 984 of file SelectionDAGNodes.h.
References llvm::SDNode::getMachineOpcode().
Referenced by PeepholePPC64ZExtGather().
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get the SDNode which holds the desired result
Definition at line 132 of file SelectionDAGNodes.h.
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineTo64bitUMAAL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), llvm::DOTGraphTraits< SelectionDAG * >::addCustomGraphFeatures(), AddGlue(), llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), areOnlyUsersOf(), BuildExactSDIV(), buildFromShuffleMostly(), llvm::TargetLowering::BuildSDIV(), llvm::PPCTargetLowering::BuildSDIVPow2(), llvm::TargetLowering::BuildUDIV(), buildVector(), canChangeToInt(), canFoldInAddressingMode(), canReduceVMulWidth(), ChangeVSETULTtoVSETULE(), llvm::checkForCycles(), checkForCyclesHelper(), CheckForMaskedLoad(), checkHighLaneIndex(), checkV64LaneV128(), checkValueWidth(), ChooseConstraint(), combineANDXORWithAllOnesIntoANDNP(), CombineBaseUpdate(), combineBitcastForMaskedOp(), combineCMov(), combineExtractVectorElt(), combineFMA(), combineFneg(), combineIntegerAbs(), combineLogicBlendIntoPBLENDV(), combineMaskedLoadConstantMask(), combineOrCmpEqZeroToCtlzSrl(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSelect(), combineSelectAndUse(), combineSelectAndUseCommutative(), combineSetCC(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineTargetShuffle(), combineTruncatedArithmetic(), combineVectorShift(), CombineVLDDUP(), combineVSelectWithAllOnesOrZeros(), combineVSZext(), combineX86SetCC(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), llvm::SelectionDAG::computeKnownBits(), computeZeroableShuffleElements(), ConvertI1VectorToInteger(), ConvertSelectToConcatVector(), createGPRPairNode(), detectZextAbsDiff(), distributeOpThroughSelect(), DumpNodesr(), EltsFromConsecutiveLoads(), emitCmp(), emitConjunctionDisjunctionTreeRec(), emitIntrinsicWithChainAndGlue(), EmitVectorComparison(), llvm::TargetLowering::expandMUL_LOHI(), ExpandPowI(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendToType(), ExtendUsesToFormExtLoad(), FindBFIToCombineWith(), findConsecutiveLoad(), findUser(), foldFreeOpFromSelect(), foldVectorXorShiftIntoCmp(), GenerateTBL(), llvm::PPC::get_VSPLTI_elt(), getAArch64Cmp(), getBuildPairElt(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::ScheduleDAGSDNodes::getCustomGraphFeatures(), getExtractVEXTRACTImmediate(), llvm::MipsDAGToDAGISel::getGlobalBaseReg(), llvm::SDNode::getGluedNode(), llvm::DenseMapInfo< SDValue >::getHashValue(), getInsertVINSERTImmediate(), llvm::SelectionDAG::getMemcpy(), getMemcpyLoadsAndStores(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), getMemsetStores(), GetNegatedExpression(), llvm::SDUse::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAGBuilder::getNonRegisterValue(), llvm::MipsTargetLowering::getOpndList(), llvm::HexagonTargetLowering::getPostIndexedAddressParts(), getPowerOf2Factor(), llvm::ARMTargetLowering::getPreIndexedAddressParts(), llvm::PPCTargetLowering::getPreIndexedAddressParts(), getPSHUFShuffleMask(), getShuffleScalarElt(), llvm::simplify_type< SDValue >::getSimplifiedValue(), llvm::simplify_type< const SDValue >::getSimplifiedValue(), getTargetVShiftByConstNode(), getUsefulBits(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), llvm::SelectionDAGBuilder::getValue(), llvm::SelectionDAGBuilder::getValueImpl(), getVShiftImm(), hasNormalLoadOperand(), haveEfficientBuildVectorPattern(), llvm::SelectionDAG::InferPtrAlignment(), insert1BitVector(), insertDAGNode(), isAddSubSExt(), isAddSubZExt(), isBitfieldExtractOp(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), isBLACompatibleAddress(), isBSwapHWordElement(), llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), isCalleeLoad(), isConsecutiveLSLoc(), isConstantFPBuildVectorOrConstantFP(), llvm::SelectionDAG::isConstantFPBuildVectorOrConstantFP(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), isExtendedBUILD_VECTOR(), isFloatingPointZero(), llvm::TargetLowering::isGAPlusOffset(), isHorizontalBinOp(), isInt32Immediate(), isIntImmediate(), isIntS16Immediate(), llvm::SelectionDAGISel::IsLegalToFold(), isLoadIncOrDecStore(), isNaturalMemoryOperand(), isNegatibleForFree(), isNullFPScalarOrVectorConst(), isOpcodeHandled(), isOpcWithIntImmediate(), llvm::SDNode::isOperandOf(), IsPredicateKnownToFail(), isSeveralBitsExtractOpFromShr(), isShuffleFoldableLoad(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), isVEXTRACTIndex(), isVINSERTIndex(), isVSplat(), llvm::SelectionDAG::Legalize(), lower1BitVectorShuffle(), LowerADDC_ADDE_SUBC_SUBE(), LowerAndToBT(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::PPCTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), lowerAtomicArith(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBuildVectorv16i8(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), lowerCallFromStatepointLoweringInfo(), llvm::TargetLowering::LowerCallTo(), LowerCONCAT_VECTORSvXi1(), lowerCTPOP32BitElements(), lowerDSPIntr(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128Load(), LowerF128Store(), LowerFNEGorFABS(), llvm::NVPTXTargetLowering::LowerFormalArguments(), LowerFPOWI(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerINTRINSIC_WO_CHAIN(), LowerLOAD(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), llvm::R600TargetLowering::LowerOperation(), llvm::XCoreTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperationWrapper(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), LowerREADCYCLECOUNTER(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerShift(), llvm::MSP430TargetLowering::LowerShifts(), lowerStatepointMetaArgs(), LowerSTORE(), LowerTruncatingStore(), lowerV2X128VectorShuffle(), LowerVAARG(), LowerVACOPY(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorAllZeroTest(), LowerVectorBroadcast(), LowerVectorCTPOP(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsBlend(), lowerVectorShuffleAsBroadcast(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerXALUO(), materializeVectorConstant(), MayFoldIntoStore(), MayFoldIntoZeroExtend(), MayFoldLoad(), moveBelowOrigChain(), llvm::SDNodeIterator::operator*(), peekThroughBitcasts(), peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), PerformADDCombineWithOperands(), performAddSubLongCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), PerformBFICombine(), PerformBUILD_VECTORCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::MipsSETargetLowering::PerformDAGCombine(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformInsertEltCombine(), performIntegerAbsCombine(), performIntToFpCombine(), performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), performNEONPostLDSTCombine(), performORCombine(), PerformORCombine(), performPostLD1Combine(), PerformSTORECombine(), PerformSUBCombine(), PerformVDIVCombine(), PerformVDUPCombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), performXORCombine(), PrepareCall(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::SelectionDAG::ReplaceAllUsesOfValuesWith(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), ReplaceINTRINSIC_W_CHAIN(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), reservePreviousStackSlotForValue(), llvm::SelectionDAGBuilder::resolveDanglingDebugInfo(), llvm::DAGTypeLegalizer::run(), llvm::ResourcePriorityQueue::scheduledNode(), SearchSignedMulLong(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(), llvm::NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(), selectMADD(), selectMSUB(), llvm::SelectionDAG::setRoot(), setTargetShuffleZeroElements(), llvm::SelectionDAGBuilder::setUnusedArgValue(), llvm::SelectionDAGBuilder::setValue(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(), llvm::TargetLowering::TargetLoweringOpt::SimplifyDemandedBits(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), SkipExtensionForVMULL(), spillIncomingStatepointValue(), llvm::AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(), TranslateX86CC(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), tryBuildVectorShuffle(), tryCombineLongOpWithDup(), tryToFoldExtendOfConstant(), useSinCos(), and XFormVExtractWithShuffleIntoLoad().
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Definition at line 960 of file SelectionDAGNodes.h.
References llvm::SDNode::getNumOperands().
Referenced by buildFromShuffleMostly(), CheckChildInteger(), CheckChildSame(), CheckChildType(), combineShuffleOfConcatUndef(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), computeZeroableShuffleElements(), ConvertI1VectorToInteger(), detectAVGPattern(), llvm::InstrEmitter::EmitDbgValue(), emitIntrinsicWithChainAndGlue(), emitIntrinsicWithGlue(), ExtendToType(), llvm::SelectionDAG::getNode(), isCalleeLoad(), isLoadIncOrDecStore(), isScalarToVector(), LowerAVXCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerINTRINSIC_WO_CHAIN(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), LowerVECTOR_SHUFFLE(), moveBelowOrigChain(), partitionShuffleOfConcats(), PerformVECTOR_SHUFFLECombine(), reachesChainWithoutSideEffects(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::SelectionDAGISel::SelectCodeCommon(), setTargetShuffleZeroElements(), and llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedOp().
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Definition at line 952 of file SelectionDAGNodes.h.
References llvm::SDNode::getOpcode().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitUMAAL(), AddCombineVUZPToVPADDL(), llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), buildFromShuffleMostly(), buildScalarToVector(), buildVector(), CanCombineFCOPYSIGN_EXTEND_ROUND(), canReduceVMulWidth(), checkBoolTestAndOrSetCCCombine(), checkBoolTestSetCCCombine(), checkHighLaneIndex(), combineAnd(), combineANDXORWithAllOnesIntoANDNP(), combineBasicSADPattern(), combineBitcast(), combineBitcastForMaskedOp(), combineBVOfConsecutiveLoads(), combineCMov(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineFAndFNotToFAndn(), combineFneg(), combineGatherScatter(), combineIntegerAbs(), combineLogicBlendIntoPBLENDV(), combineLoopSADPattern(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combinePCMPAnd1(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineShiftLeft(), combineShiftRightAlgebraic(), combineShuffle(), combineShuffleOfConcatUndef(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineTargetShuffle(), combineTruncate(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineVSZext(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), combineZext(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), computeKnownBits(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::PPCTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLowering::ComputeNumSignBitsForTargetNode(), computeZeroableShuffleElements(), convertIntLogicToFPLogic(), ConvertSelectToConcatVector(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createFPCmp(), detectAVGPattern(), detectZextAbsDiff(), EmitCMP(), emitComparison(), emitConditionalComparison(), EmitKTEST(), ExtendToType(), extractSubVector(), FindBaseOffset(), FindBFIToCombineWith(), findEXTRHalf(), foldBitcastedFPLogic(), FoldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), getAArch64XALUOOp(), getARMIndexedAddressParts(), getBuildPairElt(), getCmp(), llvm::SelectionDAGBuilder::getControlRoot(), getDivRem8(), getExtendTypeForNode(), getFauxShuffleMask(), GetNegatedExpression(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), getPSHUFShuffleMask(), getScalarMaskingNode(), getScalarValueForVectorElement(), getShiftTypeForNode(), getShuffleScalarElt(), llvm::SelectionDAG::getSplatBuildVector(), getTargetShuffleMaskIndices(), getTargetVShiftNode(), getUnderlyingArgReg(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), getVShiftImm(), haveEfficientBuildVectorPattern(), InferPointerInfo(), isAbsolute(), isADDADDMUL(), isAddSub(), isAndOrOfSetCCs(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isBitwiseNot(), isBSwapHWordElement(), isCalleeLoad(), isConsecutiveLSLoc(), llvm::BuildVectorSDNode::isConstant(), isConstantOrConstantVector(), llvm::AArch64TargetLowering::isDesirableToCommuteWithShift(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isEssentiallyExtractSubvector(), isFloatingPointZero(), isFMAddSub(), isFNEG(), isFrameIndexOp(), isFunctionGlobalAddress(), isHorizontalBinOp(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), isLoadIncOrDecStore(), isMemSrcFromString(), IsMulWideOperandDemotable(), isNegatibleForFree(), isSaturatingConditional(), isSetCC(), isSetCCOrZExtSetCC(), isSExtFree(), isTargetConstant(), isTruncWithZeroHighBitsInput(), isX86LogicalCmp(), isXor1OfSetCC(), llvm::XCoreTargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), LookThroughSetCC(), Lower256IntArith(), Lower256IntVSETCC(), Lower512IntArith(), LowerADDC_ADDE_SUBC_SUBE(), LowerAndToBT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAVXExtend(), lowerBuildVectorToBitOp(), LowerBuildVectorv4x32(), llvm::AMDGPUTargetLowering::LowerCTLZ(), LowerCTLZ(), LowerCTTZ(), lowerDSPIntr(), LowerEXTEND_VECTOR_INREG(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerFABSorFNEG(), LowerFNEGorFABS(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerINSERT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), LowerMUL_LOHI(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::MipsSETargetLowering::LowerOperation(), llvm::BPFTargetLowering::LowerOperation(), llvm::SparcTargetLowering::LowerOperation(), llvm::LanaiTargetLowering::LowerOperation(), llvm::AVRTargetLowering::LowerOperation(), llvm::MSP430TargetLowering::LowerOperation(), llvm::XCoreTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerOperation(), llvm::AMDGPUTargetLowering::LowerOperation(), llvm::SITargetLowering::LowerOperation(), llvm::MipsTargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::AArch64TargetLowering::LowerOperation(), llvm::NVPTXTargetLowering::LowerOperation(), llvm::SystemZTargetLowering::LowerOperation(), llvm::PPCTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperation(), LowerRotate(), LowerScalarImmediateShift(), LowerScalarVariableShift(), llvm::MSP430TargetLowering::LowerSETCC(), LowerSETCCE(), LowerShift(), LowerShiftParts(), llvm::MSP430TargetLowering::LowerShifts(), LowerSIGN_EXTEND_AVX512(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerTruncateToBT(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUMULO_SMULO(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), LowerVectorAllZeroTest(), LowerVectorBroadcast(), LowerVectorCTLZ_AVX512(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), lowerVectorShuffleAsTruncBroadcast(), LowerVSETCC(), LowerXALUO(), LowerXOR(), MatchingStackOffset(), matchRotateSub(), moveBelowOrigChain(), NormalizeBuildVector(), OptimizeConditionalInDecrement(), peekThroughBitcasts(), peekThroughOneUseBitcasts(), performAcrossLaneMinMaxReductionCombine(), performADDCombine(), PerformADDCombineWithOperands(), performAddSubLongCombine(), performANDCombine(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), performAssertZextCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), performCONDCombine(), llvm::AMDGPUTargetLowering::performCtlzCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), performExtendCombine(), PerformExtendCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), performIntegerAbsCombine(), performORCombine(), PerformORCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), PerformSELECTCombine(), performSelectCombine(), PerformShiftCombine(), performSRLCombine(), PerformVCVTCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), PerformVMULCombine(), performVSELECTCombine(), performVSelectCombine(), promoteExtBeforeAdd(), reachesChainWithoutSideEffects(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReorganizeVector(), replaceSplatVectorStore(), replaceZeroVectorStore(), SearchSignedMulLong(), SearchSignedMulShort(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::SelectionDAGISel::SelectCodeCommon(), selectMADD(), selectMSUB(), setTargetShuffleZeroElements(), llvm::X86TargetLowering::shouldReduceLoadWidth(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), simplifyShuffleOperandRecursively(), tryBuildVectorByteMask(), tryBuildVectorShuffle(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryCombineToBSL(), tryExtendDUPToExtractHigh(), tryLowerToSLI(), tryMatchAcrossLaneShuffleForReduction(), WidenMaskArithmetic(), willShiftRightEliminate(), and XFormVExtractWithShuffleIntoLoad().
Definition at line 964 of file SelectionDAGNodes.h.
References llvm::SDNode::getOperand().
Referenced by AddCombineVUZPToVPADDL(), llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), canReduceVMulWidth(), CheckAndImm(), checkBoolTestSetCCCombine(), CheckChildInteger(), CheckChildSame(), CheckChildType(), checkHighLaneIndex(), CheckOrImm(), combineAnd(), combineANDXORWithAllOnesIntoANDNP(), combineBitcast(), combineBitcastForMaskedOp(), combineBVOfConsecutiveLoads(), combineCMov(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineFAndFNotToFAndn(), combineFneg(), combineGatherScatter(), combineIntegerAbs(), combineLogicBlendIntoPBLENDV(), combineOr(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineShiftLeft(), combineShiftRightAlgebraic(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineSignExtendInReg(), combineStore(), combineSub(), combineTargetShuffle(), combineTruncate(), combineTruncatedArithmetic(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineVSZext(), combineZext(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), computeKnownBits(), llvm::SparcTargetLowering::computeKnownBitsForTargetNode(), llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::PPCTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), computeZeroableShuffleElements(), ConvertI1VectorToInteger(), convertIntLogicToFPLogic(), ConvertSelectToConcatVector(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), createCMovFP(), createFPCmp(), createPSADBW(), detectAVGPattern(), detectZextAbsDiff(), distributeOpThroughSelect(), emitComparison(), emitConditionalComparison(), emitIntrinsicWithChainAndGlue(), emitIntrinsicWithGlue(), EmitKTEST(), ExtendToType(), FindBaseOffset(), FindBFIToCombineWith(), findEXTRHalf(), foldBitcastedFPLogic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), GenerateTBL(), getAArch64XALUOOp(), getBaseWithConstantOffset(), getBuildPairElt(), getDivRem8(), getExtendTypeForNode(), getFauxShuffleMask(), GetNegatedExpression(), llvm::SelectionDAG::getNode(), getPowerOf2Factor(), getScalarValueForVectorElement(), getShuffleScalarElt(), getTargetShuffleMaskIndices(), getTargetVShiftNode(), getUnderlyingArgReg(), getUsefulBitsFromAndWithImmediate(), getUsefulBitsFromBFM(), getUsefulBitsFromOrWithShiftedReg(), getUsefulBitsFromUBFM(), getValidShiftAmountConstant(), getVectorCompareInfo(), getVShiftImm(), haveEfficientBuildVectorPattern(), InferPointerInfo(), llvm::SelectionDAG::InferPtrAlignment(), insert1BitVector(), isAbsolute(), isADDADDMUL(), isAddSub(), isAndOrOfSetCCs(), llvm::SelectionDAG::isBaseWithConstantOffset(), isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOp(), llvm::isBitwiseNot(), isBSwapHWordElement(), isCalleeLoad(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isEssentiallyExtractSubvector(), isFloatingPointZero(), isFMAddSub(), isFNEG(), isFrameIndexOp(), isHorizontalBinOp(), isIntrinsicWithCC(), isIntrinsicWithCCAndChain(), llvm::SelectionDAG::isKnownNeverZero(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), isLoadIncOrDecStore(), isMemSrcFromString(), IsMulWideOperandDemotable(), isNegatibleForFree(), isSaturatingConditional(), isScalarToVector(), isSetCC(), isSeveralBitsExtractOpFromShr(), isSExtFree(), isSimpleShift(), isTruncWithZeroHighBitsInput(), isXor1OfSetCC(), LookThroughSetCC(), Lower256IntArith(), Lower256IntVSETCC(), Lower512IntArith(), LowerADD(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), LowerAndToBT(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerATOMIC_FENCE(), LowerATOMIC_FENCE(), LowerAVXCONCAT_VECTORS(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBoolVSETCC_AVX512(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), lowerBuildVectorToBitOp(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerBuildVectorv8i16(), llvm::SparcTargetLowering::LowerCall_64(), LowerCMP_SWAP(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::AMDGPUTargetLowering::LowerCTLZ(), LowerCTLZ(), llvm::HexagonTargetLowering::LowerCTPOP(), LowerCTTZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), llvm::LanaiTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerDYNAMIC_STACKALLOC(), llvm::HexagonTargetLowering::LowerEH_RETURN(), llvm::SparcTargetLowering::LowerEH_SJLJ_LONGJMP(), llvm::SparcTargetLowering::LowerEH_SJLJ_SETJMP(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), llvm::SparcTargetLowering::LowerF128Op(), LowerFABSorFNEG(), llvm::AMDGPUTargetLowering::LowerFCEIL(), LowerFCOPYSIGN(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::LowerFFLOOR(), LowerFGETSIGN(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::AMDGPUTargetLowering::LowerFP64_TO_INT(), LowerFP_EXTEND(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), lowerFP_TO_SINT_STORE(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFP_TO_UINT(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND32(), llvm::AMDGPUTargetLowering::LowerFROUND64(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), LowerINSERT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), LowerINSERT_VECTOR_ELT(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP32(), llvm::AMDGPUTargetLowering::LowerINT_TO_FP64(), llvm::HexagonTargetLowering::LowerINTRINSIC_VOID(), LowerINTRINSIC_W_CHAIN(), llvm::AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(), llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(), LowerINTRINSIC_WO_CHAIN(), LowerIntVSETCC_AVX512(), llvm::HexagonTargetLowering::LowerLOAD(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), llvm::R600TargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerPREFETCH(), LowerPREFETCH(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSETCCE(), LowerSETCCE(), LowerShift(), LowerShiftParts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), LowerSIGN_EXTEND_AVX512(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerSUB(), LowerTruncateToBT(), LowerTruncateVecI1(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP(), lowerUINT_TO_FP_v2i32(), LowerUMULO_SMULO(), LowerVACOPY(), llvm::LanaiTargetLowering::LowerVASTART(), llvm::MSP430TargetLowering::LowerVASTART(), llvm::HexagonTargetLowering::LowerVASTART(), LowerVASTART(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLEv8i8(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), lowerVectorShuffle(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsTruncBroadcast(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), lowerX86CmpEqZeroToCtlzSrl(), LowerXOR(), LowerZERO_EXTEND(), MarkEHGuard(), MarkEHRegistrationNode(), MatchingStackOffset(), matchRotateSub(), moveBelowOrigChain(), OptimizeConditionalInDecrement(), partitionShuffleOfConcats(), peekThroughBitcasts(), peekThroughOneUseBitcasts(), PeepholePPC64ZExtGather(), performAcrossLaneMinMaxReductionCombine(), performADDCombine(), PerformADDCombineWithOperands(), performAddSubLongCombine(), performANDCombine(), PerformARMBUILD_VECTORCombine(), performAssertZextCombine(), PerformBFICombine(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::AMDGPUTargetLowering::performCtlzCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFPMed3ImmCombine(), performIntegerAbsCombine(), performIntMed3ImmCombine(), performORCombine(), PerformORCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), PerformSELECTCombine(), performSelectCombine(), PerformShiftCombine(), performSRLCombine(), PerformSTORECombine(), PerformVDIVCombine(), PerformVDUPLANECombine(), PerformVECTOR_SHUFFLECombine(), PerformVMOVDRRCombine(), PerformVMOVRRDCombine(), performVSELECTCombine(), performVSelectCombine(), promoteExtBeforeAdd(), reachesChainWithoutSideEffects(), llvm::AArch64TargetLowering::ReconstructShuffle(), ReorganizeVector(), replaceSplatVectorStore(), replaceZeroVectorStore(), SearchSignedMulLong(), SearchSignedMulShort(), llvm::AVRDAGToDAGISel::SelectAddr(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegReg(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::SelectionDAGISel::SelectCodeCommon(), setTargetShuffleZeroElements(), llvm::X86TargetLowering::shouldReduceLoadWidth(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOrAndImm(), tryBuildVectorShuffle(), tryCombineCRC32(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), tryLowerToSLI(), tryMatchAcrossLaneShuffleForReduction(), llvm::TargetLowering::verifyReturnAddressArgumentIsConstant(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), willShiftRightEliminate(), and XFormVExtractWithShuffleIntoLoad().
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get the index which selects a specific result in the SDNode
Definition at line 129 of file SelectionDAGNodes.h.
Referenced by llvm::DOTGraphTraits< SelectionDAG * >::addCustomGraphFeatures(), checkBoolTestSetCCCombine(), CheckForPhysRegDependency(), CombineBaseUpdate(), combineExtractVectorElt(), CombineVLDDUP(), llvm::SelectionDAG::computeKnownBits(), llvm::ARMTargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), ExtendUsesToFormExtLoad(), getBuildPairElt(), getCmp(), llvm::RegsForValue::getCopyToRegs(), getDivRem8(), llvm::DenseMapInfo< SDValue >::getHashValue(), llvm::SDUse::getResNo(), isLoadIncOrDecStore(), isX86LogicalCmp(), performNEONPostLDSTCombine(), performPostLD1Combine(), PerformVMOVDRRCombine(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::SelectionDAG::ReplaceAllUsesOfValuesWith(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), llvm::ResourcePriorityQueue::scheduledNode(), selectMADD(), and selectMSUB().
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Definition at line 172 of file SelectionDAGNodes.h.
References llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), and getValueType().
Referenced by combineSelect(), combineX86ShuffleChain(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), ConvertI1VectorToInteger(), getUsefulBits(), getValidShiftAmountConstant(), llvm::SelectionDAG::getZeroExtendInReg(), isAllOnesConstantOrAllOnesSplatConstant(), isConstantOrConstantVector(), isFNEG(), isOneConstantOrOneSplatConstant(), LowerEXTRACT_VECTOR_ELT(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformVDUPLANECombine(), llvm::SelectionDAG::SignBitIsZero(), and llvm::TargetLowering::SimplifyDemandedBits().
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Return the simple ValueType of the referenced return value.
Definition at line 163 of file SelectionDAGNodes.h.
References llvm::EVT::getSimpleVT(), and getValueType().
Referenced by llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), ChangeVSETULTtoVSETULE(), combineAcrossLanesIntrinsic(), combineBasicSADPattern(), combineBitcastForMaskedOp(), combineLockSub(), combineRedundantDWordShuffle(), combineTargetShuffle(), combineVSZext(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), ExpandHorizontalBinOp(), ExtendToType(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), getCopyFromPartsVector(), getExtractVEXTRACTImmediate(), getFauxShuffleMask(), getGatherNode(), getMaskNode(), llvm::SelectionDAG::getNode(), getNullFPConstForNullVal(), getPrefetchNode(), getPSHUFShuffleMask(), getScalarMaskingNode(), getScalarValueForVectorElement(), getScatterNode(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getTargetShuffleMaskIndices(), getTargetVShiftByConstNode(), getTargetVShiftNode(), getUnderlyingExtractedFromVec(), getVectorMaskingNode(), insert1BitVector(), isAddSub(), isHorizontalBinOp(), Lower256IntArith(), Lower256IntVSETCC(), Lower512IntArith(), LowerADD(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), LowerBoolVSETCC_AVX512(), LowerBuildVectorv4x32(), LowerCMP_SWAP(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerCTLZ(), LowerCTPOP(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerExtendedLoad(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFGETSIGN(), LowerFP_EXTEND(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), LowerHorizontalByteSum(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerINTRINSIC_WO_CHAIN(), LowerIntVSETCC_AVX512(), LowerMGATHER(), LowerMINMAX(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMUL_LOHI(), LowerMULH(), LowerRotate(), LowerSCALAR_TO_VECTOR(), LowerScalarImmediateShift(), LowerScalarVariableShift(), LowerSETCCE(), LowerShift(), LowerShiftParts(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_AVX512(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerSUB(), LowerTruncateVecI1(), lowerUINT_TO_FP_v2i32(), lowerUINT_TO_FP_vXi32(), lowerV16F32VectorShuffle(), lowerV16I16VectorShuffle(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV32I16VectorShuffle(), lowerV32I8VectorShuffle(), lowerV4F32VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I32VectorShuffle(), lowerV4I64VectorShuffle(), lowerV64I8VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8F64VectorShuffle(), lowerV8I16VectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPBitmath(), LowerVectorCTPOPInRegLUT(), lowerVectorShuffle(), lowerVectorShuffleAsBroadcast(), lowerVectorShuffleAsInsertPS(), lowerVSELECTtoVectorShuffle(), LowerVSETCC(), LowerZERO_EXTEND(), LowerZERO_EXTEND_AVX512(), matchVectorShuffleAsInsertPS(), materializeVectorConstant(), llvm::R600TargetLowering::PerformDAGCombine(), performFDivCombine(), performFpToIntCombine(), PerformVCVTCombine(), PerformVDIVCombine(), setTargetShuffleZeroElements(), llvm::TargetLowering::SimplifySetCC(), splitAndLowerVectorShuffle(), tryExtendDUPToExtractHigh(), and tryMatchAcrossLaneShuffleForReduction().
Definition at line 152 of file SelectionDAGNodes.h.
References SDValue().
Referenced by AddCombineTo64bitMLAL(), llvm::AVRDAGToDAGISel::select< AVRISD::CALL >(), llvm::AVRDAGToDAGISel::select< ISD::LOAD >(), llvm::X86TargetLowering::BuildFILD(), combineLoad(), combineMaskedLoad(), combineMaskedLoadConstantMask(), combineSetCCAtomicArith(), combineSIntToFP(), combineStore(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemcmp(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), Expand64BitShift(), ExpandBITCAST(), llvm::TargetLowering::expandMUL_LOHI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::SelectionDAG::expandVAArg(), llvm::SelectionDAG::expandVACopy(), llvm::PPCTargetLowering::expandVSXLoadForLE(), llvm::PPCTargetLowering::expandVSXStoreForLE(), getAArch64XALUOOp(), getBoundedStrlen(), llvm::RegsForValue::getCopyFromRegs(), llvm::RegsForValue::getCopyToRegs(), getDivRem8(), llvm::HexagonTargetLowering::GetDynamicTLSAddr(), getExtendedControlRegister(), getFPBinOp(), getFPTernOp(), getMemCmpLoad(), getMemmoveLoadsAndStores(), getMul24(), llvm::MipsTargetLowering::getOpndList(), getReadPerformanceCounter(), getReadTimeStampCounter(), GetTLSADDR(), getv64i1Argument(), isCalleeLoad(), isLoadIncOrDecStore(), LowerADDC_ADDE_SUBC_SUBE(), llvm::SelectionDAGBuilder::LowerAsSTATEPOINT(), LowerATOMIC_STORE(), lowerAtomicArith(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerCall(), llvm::SparcTargetLowering::LowerCall_32(), llvm::SparcTargetLowering::LowerCall_64(), llvm::HexagonTargetLowering::LowerCallResult(), LowerCallResult(), llvm::TargetLowering::LowerCallTo(), LowerCMP_SWAP(), LowerCTLZ(), LowerCTTZ(), LowerDYNAMIC_STACKALLOC(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerLOAD(), llvm::MipsTargetLowering::lowerLOAD(), LowerMGATHER(), LowerMLOAD(), LowerMUL_LOHI(), llvm::MipsTargetLowering::LowerOperationWrapper(), llvm::X86TargetLowering::LowerOperationWrapper(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::SITargetLowering::LowerReturn(), llvm::HexagonTargetLowering::LowerReturn(), llvm::SystemZTargetLowering::LowerReturn(), llvm::SparcTargetLowering::LowerReturn_32(), llvm::SparcTargetLowering::LowerReturn_64(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), LowerSETCCE(), llvm::HexagonTargetLowering::LowerToTLSGeneralDynamicModel(), LowerToTLSGeneralDynamicModel32(), LowerToTLSLocalDynamicModel(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), LowerVAARG(), LowerVECTOR_SHUFFLE(), llvm::PPCTargetLowering::PerformDAGCombine(), performDivRemCombine(), performIntToFpCombine(), llvm::AMDGPUTargetLowering::performLoadCombine(), PerformSTORECombine(), PerformVDUPCombine(), PerformVMOVRRDCombine(), PrepareCall(), PrepareTailCall(), reduceMaskedLoadToScalarLoad(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::R600TargetLowering::ReplaceNodeResults(), llvm::AVRTargetLowering::ReplaceNodeResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::ARMTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), ReplaceREADCYCLECOUNTER(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::SelectionDAGISel::SelectCodeCommon(), splitStores(), splitStoreSplat(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), and llvm::SelectionDAGBuilder::visitJumpTable().
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Returns the size of the value in bits.
Definition at line 168 of file SelectionDAGNodes.h.
References llvm::EVT::getSizeInBits(), and getValueType().
Referenced by llvm::X86TargetLowering::BuildFILD(), CalculateTailCallArgDest(), llvm::SelectionDAGISel::CheckAndMask(), CheckForMaskedLoad(), llvm::SelectionDAGISel::CheckOrMask(), combineBT(), combineLoopSADPattern(), combineShiftLeft(), combineStore(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), ConvertI1VectorToInteger(), EltsFromConsecutiveLoads(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), GenerateTBL(), llvm::SelectionDAG::getAnyExtendVectorInReg(), getBitTestCondition(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignExtendVectorInReg(), llvm::SelectionDAG::getZeroExtendVectorInReg(), isSimpleShift(), isTruncateOf(), isTruncWithZeroHighBitsInput(), LowerAndToBT(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), lowerFCOPYSIGN64(), lowerFP_TO_SINT_STORE(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), LowerINTRINSIC_WO_CHAIN(), llvm::NVPTXTargetLowering::LowerReturn(), LowerVectorBroadcast(), MatchingStackOffset(), performIntToFpCombine(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), spillIncomingStatepointValue(), tryCombineFixedPointConvert(), tryFormConcatFromShuffle(), and VerifySDNode().
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Return the ValueType of the referenced return value.
Definition at line 956 of file SelectionDAGNodes.h.
References llvm::SDNode::getValueType().
Referenced by AddCombineBUILD_VECTORToVPADDL(), AddCombineTo64bitMLAL(), AddCombineVUZPToVPADDL(), llvm::AVRDAGToDAGISel::select< ISD::STORE >(), BuildExactSDIV(), llvm::X86TargetLowering::BuildFILD(), buildFromShuffleMostly(), BuildIntrinsicOp(), llvm::TargetLowering::BuildSDIV(), llvm::TargetLowering::BuildUDIV(), canChangeToInt(), canReduceVMulWidth(), CheckForMaskedLoad(), CheckType(), clampDynamicVectorIndex(), CombineBaseUpdate(), combineBasicSADPattern(), combineBitcast(), combineCMov(), combineCompareEqual(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineExtractVectorElt(), combineFneg(), combineLogicBlendIntoPBLENDV(), combineMaskedLoad(), combineMaskedStore(), combineOr(), combineOrCmpEqZeroToCtlzSrl(), combinePCMPAnd1(), combineRedundantDWordShuffle(), combineSelect(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSext(), combineShiftLeft(), combineShiftRightAlgebraic(), combineShuffle(), combineShuffleOfScalars(), combineSignExtendInReg(), combineSIntToFP(), combineStore(), combineSub(), combineToExtendVectorInReg(), combineTruncate(), combineUIntToFP(), combineVectorSignBitsTruncation(), combineVectorTruncation(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineX86ShufflesRecursively(), CompactSwizzlableVector(), llvm::SelectionDAG::computeKnownBits(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), llvm::X86TargetLowering::computeKnownBitsForTargetNode(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), convertIntLogicToFPLogic(), countOperands(), createCMovFP(), createFPCmp(), createLoadLR(), createPSADBW(), createStoreLR(), detectAVGPattern(), detectZextAbsDiff(), distributeOpThroughSelect(), EltsFromConsecutiveLoads(), emitCLC(), EmitCMP(), emitComparison(), emitConditionalComparison(), emitConjunctionDisjunctionTreeRec(), EmitKTEST(), emitMemMem(), llvm::ARMSelectionDAGInfo::EmitSpecializedLibcall(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemchr(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForMemset(), llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcmp(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrcpy(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrlen(), llvm::SystemZSelectionDAGInfo::EmitTargetCodeForStrnlen(), EmitTruncSStore(), EmitVectorComparison(), ExpandBITCAST(), expandExp(), expandExp2(), expandf64Toi32(), llvm::TargetLowering::expandFP_TO_SINT(), expandLog(), expandLog10(), expandLog2(), expandPow(), ExpandPowI(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::PPCTargetLowering::expandVSXStoreForLE(), ExtendUsesToFormExtLoad(), extract128BitVector(), extract256BitVector(), extractSubVector(), llvm::SelectionDAG::ExtractVectorElements(), findChainOperand(), foldBitcastedFPLogic(), FoldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), foldFreeOpFromSelect(), FoldIntToFPToInt(), foldMaskAndShiftToScale(), llvm::SelectionDAG::FoldSetCC(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), GeneratePerfectShuffle(), GenerateTBL(), getAArch64Cmp(), getAArch64XALUOOp(), getAbsolute(), llvm::SelectionDAG::getAnyExtendVectorInReg(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getAtomicCmpSwap(), llvm::SelectionDAG::getBitcast(), getBitTestCondition(), llvm::SelectionDAG::getBoolExtOrTrunc(), getBoundedStrlen(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), llvm::SelectionDAG::getCopyToReg(), getDivRem8(), getDivRemArgList(), llvm::DOTGraphTraits< SelectionDAG * >::getEdgeAttributes(), getEstimate(), getExtendTypeForNode(), getExtFactor(), llvm::SelectionDAG::getExtLoad(), getFRAMEADDR(), getGatherNode(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), getInputChainForNode(), getLeftShift(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMaskedStore(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), getMemsetStores(), getMemsetValue(), GetNegatedExpression(), llvm::SelectionDAG::getNode(), getNullFPConstForNullVal(), getNumOperandsNoGlue(), llvm::HexagonTargetLowering::getPICJumpTableRelocBase(), llvm::AMDGPUTargetLowering::getRecipEstimate(), getScalarValueSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getShiftAmountOperand(), getShuffleScalarElt(), llvm::SelectionDAG::getSignExtendVectorInReg(), getSimpleValueType(), llvm::SelectionDAG::getSplatBuildVector(), llvm::AMDGPUTargetLowering::getSqrtEstimate(), llvm::SelectionDAG::getStore(), getTargetShuffleMask(), llvm::SelectionDAG::getTruncStore(), getUniformBase(), getValueSizeInBits(), llvm::SDUse::getValueType(), getVectorCmp(), llvm::SelectionDAG::getVectorShuffle(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::SelectionDAG::getZeroExtendVectorInReg(), llvm::SelectionDAG::getZExtOrTrunc(), HandleMergeInputChains(), llvm::X86TargetLowering::hasAndNotCompare(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::TargetLowering::IncrementMemoryAddress(), insert128BitVector(), insert256BitVector(), insertSubVector(), IntCondCCodeToICC(), isBitfieldPositioningOp(), isConditionalZeroOrAllOnes(), isConjunctionDisjunctionTree(), llvm::isConstOrConstSplat(), llvm::X86TargetLowering::IsDesirableToPromoteOp(), isFNEG(), isHorizontalBinOp(), isI24(), llvm::SelectionDAG::isKnownToBeAPowerOfTwo(), IsMulWideOperandDemotable(), isNegatibleForFree(), isTruncateOf(), isU24(), llvm::ARMTargetLowering::isVectorLoadExtDesirable(), llvm::XCoreTargetLowering::isZExtFree(), llvm::MSP430TargetLowering::isZExtFree(), llvm::AMDGPUTargetLowering::isZExtFree(), llvm::ARMTargetLowering::isZExtFree(), llvm::AArch64TargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::TargetLoweringBase::isZExtFree(), llvm::SITargetLowering::legalizeTargetIndependentNode(), LowerADD(), LowerADDC_ADDE_SUBC_SUBE(), LowerAndToBT(), llvm::SparcTargetLowering::LowerAsmOperandForConstraint(), llvm::LanaiTargetLowering::LowerAsmOperandForConstraint(), llvm::AVRTargetLowering::LowerAsmOperandForConstraint(), llvm::ARMTargetLowering::LowerAsmOperandForConstraint(), llvm::SystemZTargetLowering::LowerAsmOperandForConstraint(), llvm::X86TargetLowering::LowerAsmOperandForConstraint(), llvm::TargetLowering::LowerAsmOperandForConstraint(), LowerAsSplatVectorLoad(), LowerBITCAST(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUTargetLowering::LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), llvm::HexagonTargetLowering::LowerConstantPool(), LowerConstantPool(), llvm::AMDGPUTargetLowering::LowerCTLZ(), llvm::AMDGPUTargetLowering::LowerDIVREM24(), lowerDSPIntr(), llvm::AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(), LowerExtended1BitVectorLoad(), LowerExtendedLoad(), llvm::AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(), llvm::HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR(), LowerEXTRACT_VECTOR_ELT(), LowerF128_FPEXTEND(), LowerF128_FPROUND(), llvm::SparcTargetLowering::LowerF128_LibCallArg(), llvm::SparcTargetLowering::LowerF128Compare(), LowerF128Load(), llvm::SparcTargetLowering::LowerF128Op(), LowerF128Store(), LowerF64Op(), lowerFCOPYSIGN32(), lowerFCOPYSIGN64(), llvm::AMDGPUTargetLowering::LowerFNEARBYINT(), LowerFNEGorFABS(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUTargetLowering::LowerFP_TO_FP16(), llvm::AMDGPUTargetLowering::LowerFP_TO_SINT(), LowerFP_TO_SINT(), llvm::AMDGPUTargetLowering::LowerFP_TO_UINT(), LowerFP_TO_UINT(), LowerFPOWI(), llvm::LanaiTargetLowering::LowerFRAMEADDR(), llvm::MSP430TargetLowering::LowerFRAMEADDR(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::AMDGPUTargetLowering::LowerFREM(), llvm::AMDGPUTargetLowering::LowerFRINT(), llvm::AMDGPUTargetLowering::LowerFROUND(), LowerFSINCOS(), llvm::AMDGPUTargetLowering::LowerFTRUNC(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), lowerIncomingStatepointValue(), llvm::HexagonTargetLowering::LowerINLINEASM(), llvm::HexagonTargetLowering::LowerINSERT_VECTOR(), LowerINTRINSIC_W_CHAIN(), llvm::AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(), LowerINTRINSIC_WO_CHAIN(), llvm::HexagonTargetLowering::LowerJumpTable(), LowerLabelRef(), llvm::HexagonTargetLowering::LowerLOAD(), llvm::MipsTargetLowering::lowerLOAD(), lowerMasksToReg(), LowerMUL(), llvm::R600TargetLowering::LowerOperation(), llvm::ARMTargetLowering::LowerOperation(), llvm::SelectionDAGBuilder::lowerRangeToAssertZExt(), llvm::NVPTXTargetLowering::LowerReturn(), llvm::LanaiTargetLowering::LowerRETURNADDR(), llvm::HexagonTargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(), LowerSDIV(), llvm::AMDGPUTargetLowering::LowerSDIVREM(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), llvm::LanaiTargetLowering::LowerSETCCE(), LowerSETCCE(), LowerShift(), llvm::MSP430TargetLowering::LowerShifts(), llvm::LanaiTargetLowering::LowerSHL_PARTS(), llvm::MSP430TargetLowering::LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSINT_TO_FP(), LowerSINT_TO_FP(), lowerStatepointMetaArgs(), LowerSUB(), LowerTruncateToBT(), LowerUDIV(), llvm::AMDGPUTargetLowering::LowerUDIVREM(), llvm::AMDGPUTargetLowering::LowerUDIVREM64(), llvm::AMDGPUTargetLowering::LowerUINT_TO_FP(), LowerUINT_TO_FP(), LowerUMULO_SMULO(), lowerUnalignedIntStore(), LowerVAARG(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVectorAllZeroTest(), LowerVectorBroadcast(), LowerVectorCTLZ(), LowerVectorFP_TO_INT(), LowerVectorINT_TO_FP(), lowerVectorSETCC(), lowerVectorShuffleAsElementInsertion(), lowerVectorShuffleAsTruncBroadcast(), lowerVectorShuffleToEXPAND(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowerWRITE_REGISTER(), lowerX86CmpEqZeroToCtlzSrl(), LowerXALUO(), LowerXOR(), llvm::SparcTargetLowering::makeHiLoPair(), llvm::TargetLowering::makeLibCall(), matchBinOpReduction(), MatchingStackOffset(), narrowIfNeeded(), NarrowVector(), NormalizeBuildVector(), OptimizeConditionalInDecrement(), partitionShuffleOfConcats(), Passv64i1ArgInRegs(), performAcrossLaneAddReductionCombine(), performAcrossLaneMinMaxReductionCombine(), PerformADDCombineWithOperands(), PerformANDCombine(), PerformARMBUILD_VECTORCombine(), performAssertZextCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performConcatVectorsCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformExtendCombine(), performFDivCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performFpToIntCombine(), PerformIntrinsicCombine(), performNEONPostLDSTCombine(), performNVCASTCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), performSelectCombine(), performSetccAddFolding(), PerformSTORECombine(), PerformVCVTCombine(), PerformVDIVCombine(), PerformVECTOR_SHUFFLECombine(), performVSelectCombine(), PrepareCall(), llvm::AArch64TargetLowering::ReconstructShuffle(), reduceMaskedStoreToScalarStore(), reduceVMULWidth(), ReorganizeVector(), ReplaceBITCASTResults(), llvm::SparcTargetLowering::ReplaceNodeResults(), llvm::PPCTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), replaceSplatVectorStore(), replaceZeroVectorStore(), reservePreviousStackSlotForValue(), llvm::DAGTypeLegalizer::run(), llvm::TargetLowering::scalarizeVectorLoad(), llvm::TargetLowering::scalarizeVectorStore(), SearchSignedMulShort(), llvm::PPCTargetLowering::SelectAddressRegImm(), llvm::PPCTargetLowering::SelectAddressRegRegOnly(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::SelectionDAG::setRoot(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(), llvm::TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(), ShrinkLoadReplaceStoreWithStore(), llvm::TargetLowering::SimplifyDemandedBits(), simplifyI24(), llvm::TargetLowering::SimplifySetCC(), simplifyShuffleOperandRecursively(), llvm::TargetLowering::softenSetCCOperands(), spillIncomingStatepointValue(), splitStores(), splitStoreSplat(), llvm::SelectionDAG::SplitVector(), llvm::AMDGPUTargetLowering::SplitVectorLoad(), llvm::AMDGPUTargetLowering::SplitVectorStore(), TranslateX86CC(), truncateVectorCompareWithPACKSS(), tryCombineFixedPointConvert(), tryCombineLongOpWithDup(), tryFormConcatFromShuffle(), tryMatchAcrossLaneShuffleForReduction(), llvm::SelectionDAG::UnrollVectorOp(), VerifySDNode(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorParent(), llvm::SelectionDAGBuilder::visitSwitchCase(), WidenVector(), llvm::SparcTargetLowering::withTargetFlags(), and XFormVExtractWithShuffleIntoLoad().
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Return true if there is exactly one node using value ResNo of Node.
Definition at line 996 of file SelectionDAGNodes.h.
References llvm::SDNode::hasNUsesOfValue().
Referenced by combineBitcast(), combineBitcastForMaskedOp(), combineBT(), combineExtractVectorElt(), combineFneg(), combineOr(), combineRedundantDWordShuffle(), combineRedundantHalfShuffle(), combineSetCC(), combineSetCCAtomicArith(), combineShiftRightAlgebraic(), combineShuffle(), combineSIntToFP(), combineStore(), combineTargetShuffle(), CombineVMOVDRRCandidateWithVecOp(), combineVSelectWithAllOnesOrZeros(), combineX86ShufflesConstants(), combineZext(), foldFreeOpFromSelect(), foldMaskAndShiftToExtract(), foldMaskAndShiftToScale(), foldMaskedShiftToScaledMask(), foldVectorXorShiftIntoCmp(), foldXorTruncShiftIntoCmp(), GetNegatedExpression(), isADDADDMUL(), isAndOrOfSetCCs(), isBitfieldPositioningOp(), isCalleeLoad(), isConjunctionDisjunctionTree(), isLoadIncOrDecStore(), isNegatibleForFree(), llvm::SelectionDAGISel::IsProfitableToFold(), isXor1OfSetCC(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::MSP430TargetLowering::LowerSETCC(), MayFoldIntoStore(), MayFoldIntoZeroExtend(), MayFoldLoad(), OptimizeConditionalInDecrement(), peekThroughOneUseBitcasts(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::performFNegCombine(), performIntToFpCombine(), PerformORCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), llvm::AMDGPUTargetLowering::performStoreCombine(), PerformVDUPCombine(), replaceZeroVectorStore(), selectMADD(), selectMSUB(), llvm::TargetLowering::SimplifyDemandedBits(), llvm::TargetLowering::SimplifySetCC(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), and XFormVExtractWithShuffleIntoLoad().
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Definition at line 980 of file SelectionDAGNodes.h.
References llvm::SDNode::isMachineOpcode().
Referenced by PeepholePPC64ZExtGather().
Return true if this node is an operand of N.
isOperand - Return true if this node is an operand of N.
Definition at line 7054 of file SelectionDAG.cpp.
References llvm::SDNode::op_values().
Referenced by isCalleeLoad().
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Definition at line 976 of file SelectionDAGNodes.h.
References llvm::SDNode::isTargetMemoryOpcode().
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Definition at line 972 of file SelectionDAGNodes.h.
References llvm::SDNode::isTargetOpcode().
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Definition at line 988 of file SelectionDAGNodes.h.
References llvm::SDNode::isUndef().
Referenced by buildMergeScalars(), buildScalarToVector(), buildVector(), combineANDXORWithAllOnesIntoANDNP(), combineConcatVectorOfExtracts(), combineConcatVectorOfScalars(), combineMaskedLoad(), combineMaskedLoadConstantMask(), combineShuffle(), combineShuffleOfConcatUndef(), combineShuffleOfScalars(), combineTargetShuffle(), computeZeroableShuffleElements(), ConvertI1VectorToInteger(), EltsFromConsecutiveLoads(), ExpandBVWithShuffles(), ExtendToType(), extractSubVector(), FoldCONCAT_VECTORS(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SelectionDAG::FoldConstantVectorArithmetic(), llvm::PPC::get_VSPLTI_elt(), getGatherNode(), llvm::SelectionDAG::getIndexedLoad(), llvm::SelectionDAG::getIndexedStore(), llvm::SelectionDAG::getLoad(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), getMemsetStores(), getMemsetValue(), llvm::SelectionDAG::getNode(), getOneTrueElt(), getScalarMaskingNode(), llvm::BuildVectorSDNode::getSplatValue(), getVectorMaskingNode(), llvm::SelectionDAG::getVectorShuffle(), haveEfficientBuildVectorPattern(), InferPointerInfo(), insert128BitVector(), insert1BitVector(), insertSubVector(), isAddSub(), llvm::ISD::isBuildVectorAllOnes(), isConstantOrConstantVector(), llvm::BuildVectorSDNode::isConstantSplat(), isHorizontalBinOp(), isScalarToVector(), llvm::PPC::isXXINSERTWMask(), joinDwords(), lower1BitVectorShuffle(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerF128Load(), LowerF128Store(), LowerScalarVariableShift(), LowerToHorizontalOp(), lowerV16F32VectorShuffle(), lowerV16I16VectorShuffle(), lowerV16I32VectorShuffle(), lowerV16I8VectorShuffle(), lowerV2F64VectorShuffle(), lowerV2I64VectorShuffle(), lowerV2X128VectorShuffle(), lowerV32I16VectorShuffle(), lowerV32I8VectorShuffle(), lowerV4F64VectorShuffle(), lowerV4I64VectorShuffle(), lowerV8F32VectorShuffle(), lowerV8F64VectorShuffle(), lowerV8I32VectorShuffle(), lowerV8I64VectorShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), lowerVectorShuffle(), lowerVectorShuffleAsLanePermuteAndBlend(), lowerVectorShuffleAsPermuteAndUnpack(), lowerVectorShuffleAsSplitOrBlend(), lowerVectorShuffleByMerging128BitLanes(), lowerVectorShuffleWithPERMV(), partitionShuffleOfConcats(), PerformARMBUILD_VECTORCombine(), llvm::R600TargetLowering::PerformDAGCombine(), llvm::SITargetLowering::PerformDAGCombine(), PerformVECTOR_SHUFFLECombine(), llvm::AArch64TargetLowering::ReconstructShuffle(), setTargetShuffleZeroElements(), llvm::TargetLowering::SimplifyDemandedBits(), tryBuildVectorByteMask(), and tryBuildVectorShuffle().
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Definition at line 148 of file SelectionDAGNodes.h.
Definition at line 142 of file SelectionDAGNodes.h.
References operator==().
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Definition at line 137 of file SelectionDAGNodes.h.
Definition at line 145 of file SelectionDAGNodes.h.
Definition at line 139 of file SelectionDAGNodes.h.
Referenced by operator!=().
Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions.
reachesChainWithoutSideEffects - Return true if this operand (which must be a chain) reaches the specified operand without crossing any side-effecting instructions on any chain path.
In practice, this looks through token factors and non-volatile loads. In order to remain efficient, this only looks a couple of nodes in, it does not do an exhaustive search.
Definition at line 7073 of file SelectionDAG.cpp.
References getNumOperands(), getOpcode(), getOperand(), i, and llvm::ISD::TokenFactor.
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set the SDNode
Definition at line 135 of file SelectionDAGNodes.h.
References N.
Referenced by PrepareCall().
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Return true if there are no nodes using value ResNo of Node.
Definition at line 992 of file SelectionDAGNodes.h.
References llvm::SDNode::hasAnyUseOfValue().
Referenced by combineADC(), combineCMov(), selectMADD(), and selectMSUB().
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Definition at line 119 of file SelectionDAGNodes.h.
1.8.6