15 #ifndef LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
16 #define LLVM_LIB_CODEGEN_ANTIDEPBREAKER_H
32 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
42 virtual unsigned BreakAntiDependencies(
const std::vector<SUnit>& SUnits,
45 unsigned InsertPosIndex,
51 unsigned InsertPosIndex) = 0;
54 virtual void FinishBlock() =0;
This class works in conjunction with the post-RA scheduler to rename registers to break register anti...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isDebugValue() const
const MachineOperand & getOperand(unsigned i) const
static const unsigned End
#define LLVM_LIBRARY_VISIBILITY
LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library...
void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg)
Update DBG_VALUE if dependency breaker is updating other machine instruction to use NewReg...
Representation of each machine instruction.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector