LLVM  4.0.0
AVRISelLowering.h
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1 //===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_AVR_ISEL_LOWERING_H
16 #define LLVM_AVR_ISEL_LOWERING_H
17 
20 
21 namespace llvm {
22 
23 namespace AVRISD {
24 
25 /// AVR Specific DAG Nodes
26 enum NodeType {
27  /// Start the numbering where the builtin ops leave off.
29  /// Return from subroutine.
31  /// Return from ISR.
33  /// Represents an abstract call instruction,
34  /// which includes a bunch of information.
36  /// A wrapper node for TargetConstantPool,
37  /// TargetExternalSymbol, and TargetGlobalAddress.
39  LSL, ///< Logical shift left.
40  LSR, ///< Logical shift right.
41  ASR, ///< Arithmetic shift right.
42  ROR, ///< Bit rotate right.
43  ROL, ///< Bit rotate left.
44  LSLLOOP, ///< A loop of single logical shift left instructions.
45  LSRLOOP, ///< A loop of single logical shift right instructions.
46  ASRLOOP, ///< A loop of single arithmetic shift right instructions.
47  /// AVR conditional branches. Operand 0 is the chain operand, operand 1
48  /// is the block to branch if condition is true, operand 2 is the
49  /// condition code, and operand 3 is the flag operand produced by a CMP
50  /// or TEST instruction.
52  /// Compare instruction.
53  CMP,
54  /// Compare with carry instruction.
56  /// Test for zero or minus instruction.
57  TST,
58  /// Operand 0 and operand 1 are selection variable, operand 2
59  /// is condition code and operand 3 is flag operand.
61 };
62 
63 } // end of namespace AVRISD
64 
65 class AVRTargetMachine;
66 
67 /// Performs target lowering for the AVR.
69 public:
70  explicit AVRTargetLowering(AVRTargetMachine &TM);
71 
72 public:
73  MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
74  return MVT::i8;
75  }
76  const char *getTargetNodeName(unsigned Opcode) const override;
77 
78  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
79 
81  SelectionDAG &DAG) const override;
82 
83  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
84  unsigned AS) const override;
85 
88  SelectionDAG &DAG) const override;
89 
92  SelectionDAG &DAG) const override;
93 
94  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
95 
97  EVT VT) const override;
98 
101  MachineBasicBlock *MBB) const override;
102 
103  ConstraintType getConstraintType(StringRef Constraint) const override;
104 
106  getSingleConstraintMatchWeight(AsmOperandInfo &info,
107  const char *constraint) const override;
108 
109  std::pair<unsigned, const TargetRegisterClass *>
111  StringRef Constraint, MVT VT) const override;
112 
113  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
114 
115  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
116  std::vector<SDValue> &Ops,
117  SelectionDAG &DAG) const override;
118 
119  unsigned getRegisterByName(const char* RegName, EVT VT,
120  SelectionDAG &DAG) const override;
121 
122 private:
123  SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
124  SelectionDAG &DAG, SDLoc dl) const;
125  SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
126  SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
127  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
128  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
129  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
130  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
131  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
132  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
133  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
134 
135  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
136 
137  bool CanLowerReturn(CallingConv::ID CallConv,
138  MachineFunction &MF, bool isVarArg,
140  LLVMContext &Context) const override;
141 
142  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
144  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
145  SelectionDAG &DAG) const override;
146  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
147  bool isVarArg,
149  const SDLoc &dl, SelectionDAG &DAG,
150  SmallVectorImpl<SDValue> &InVals) const override;
152  SmallVectorImpl<SDValue> &InVals) const override;
153  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
154  CallingConv::ID CallConv, bool isVarArg,
156  const SDLoc &dl, SelectionDAG &DAG,
157  SmallVectorImpl<SDValue> &InVals) const;
158 
159 private:
160  MachineBasicBlock *insertShift(MachineInstr &MI, MachineBasicBlock *BB) const;
161  MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
162 };
163 
164 } // end namespace llvm
165 
166 #endif // LLVM_AVR_ISEL_LOWERING_H
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override
EVT is not used in-tree, but is used by out-of-tree target.
LLVMContext & Context
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Bit rotate right.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Function Alias Analysis Results
Test for zero or minus instruction.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Compare with carry instruction.
lazy value info
Represents an abstract call instruction, which includes a bunch of information.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
A generic AVR implementation.
Return from subroutine.
MachineBasicBlock * MBB
NodeType
AVR Specific DAG Nodes.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
uint32_t Offset
AVR conditional branches.
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
AVRTargetLowering(AVRTargetMachine &TM)
Compare instruction.
A loop of single logical shift right instructions.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
Performs target lowering for the AVR.
Logical shift left.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Return from ISR.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
AddrMode
ARM Addressing Modes.
Definition: ARMBaseInfo.h:235
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Bit rotate left.
Representation of each machine instruction.
Definition: MachineInstr.h:52
Start the numbering where the builtin ops leave off.
A loop of single arithmetic shift right instructions.
#define N
Logical shift right.
Arithmetic shift right.
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:799