26 using namespace Hexagon;
28 #define DEBUG_TYPE "hexagon-mccompound"
42 J4_tstbit0_fp0_jump_nt, J4_tstbit0_fp0_jump_t, J4_tstbit0_fp1_jump_nt,
43 J4_tstbit0_fp1_jump_t, J4_tstbit0_tp0_jump_nt, J4_tstbit0_tp0_jump_t,
44 J4_tstbit0_tp1_jump_nt, J4_tstbit0_tp1_jump_t};
46 J4_cmpeq_fp0_jump_nt, J4_cmpeq_fp0_jump_t, J4_cmpeq_fp1_jump_nt,
47 J4_cmpeq_fp1_jump_t, J4_cmpeq_tp0_jump_nt, J4_cmpeq_tp0_jump_t,
48 J4_cmpeq_tp1_jump_nt, J4_cmpeq_tp1_jump_t};
50 J4_cmpgt_fp0_jump_nt, J4_cmpgt_fp0_jump_t, J4_cmpgt_fp1_jump_nt,
51 J4_cmpgt_fp1_jump_t, J4_cmpgt_tp0_jump_nt, J4_cmpgt_tp0_jump_t,
52 J4_cmpgt_tp1_jump_nt, J4_cmpgt_tp1_jump_t};
54 J4_cmpgtu_fp0_jump_nt, J4_cmpgtu_fp0_jump_t, J4_cmpgtu_fp1_jump_nt,
55 J4_cmpgtu_fp1_jump_t, J4_cmpgtu_tp0_jump_nt, J4_cmpgtu_tp0_jump_t,
56 J4_cmpgtu_tp1_jump_nt, J4_cmpgtu_tp1_jump_t};
58 J4_cmpeqi_fp0_jump_nt, J4_cmpeqi_fp0_jump_t, J4_cmpeqi_fp1_jump_nt,
59 J4_cmpeqi_fp1_jump_t, J4_cmpeqi_tp0_jump_nt, J4_cmpeqi_tp0_jump_t,
60 J4_cmpeqi_tp1_jump_nt, J4_cmpeqi_tp1_jump_t};
62 J4_cmpgti_fp0_jump_nt, J4_cmpgti_fp0_jump_t, J4_cmpgti_fp1_jump_nt,
63 J4_cmpgti_fp1_jump_t, J4_cmpgti_tp0_jump_nt, J4_cmpgti_tp0_jump_t,
64 J4_cmpgti_tp1_jump_nt, J4_cmpgti_tp1_jump_t};
66 J4_cmpgtui_fp0_jump_nt, J4_cmpgtui_fp0_jump_t, J4_cmpgtui_fp1_jump_nt,
67 J4_cmpgtui_fp1_jump_t, J4_cmpgtui_tp0_jump_nt, J4_cmpgtui_tp0_jump_t,
68 J4_cmpgtui_tp1_jump_nt, J4_cmpgtui_tp1_jump_t};
70 J4_cmpeqn1_fp0_jump_nt, J4_cmpeqn1_fp0_jump_t, J4_cmpeqn1_fp1_jump_nt,
71 J4_cmpeqn1_fp1_jump_t, J4_cmpeqn1_tp0_jump_nt, J4_cmpeqn1_tp0_jump_t,
72 J4_cmpeqn1_tp1_jump_nt, J4_cmpeqn1_tp1_jump_t};
74 J4_cmpgtn1_fp0_jump_nt, J4_cmpgtn1_fp0_jump_t, J4_cmpgtn1_fp1_jump_nt,
75 J4_cmpgtn1_fp1_jump_t, J4_cmpgtn1_tp0_jump_nt, J4_cmpgtn1_tp0_jump_t,
76 J4_cmpgtn1_tp1_jump_nt, J4_cmpgtn1_tp1_jump_t,
81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
92 case Hexagon::C2_cmpeq:
93 case Hexagon::C2_cmpgt:
94 case Hexagon::C2_cmpgtu:
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
105 case Hexagon::C2_cmpeqi:
106 case Hexagon::C2_cmpgti:
107 case Hexagon::C2_cmpgtui:
113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
115 (HexagonMCInstrInfo::inRange<5>(MI, 2) ||
119 case Hexagon::A2_tfr:
129 case Hexagon::A2_tfrsi:
139 case Hexagon::S2_tstbit_i:
144 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
153 case Hexagon::J2_jumptnew:
154 case Hexagon::J2_jumpfnew:
155 case Hexagon::J2_jumptnewpt:
156 case Hexagon::J2_jumpfnewpt:
158 if (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)
165 case Hexagon::J2_jump:
166 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
177 unsigned PredReg = Predicate.
getReg();
179 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) ||
180 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3));
186 case Hexagon::J2_jumpfnew:
188 case Hexagon::J2_jumpfnewpt:
190 case Hexagon::J2_jumptnew:
192 case Hexagon::J2_jumptnewpt:
199 MCInst *CompoundInsn =
nullptr;
200 unsigned compoundOpcode;
207 DEBUG(
dbgs() <<
"Possible compound ignored\n");
210 case Hexagon::A2_tfrsi:
212 compoundOpcode = J4_jumpseti;
221 case Hexagon::A2_tfr:
225 compoundOpcode = J4_jumpsetr;
234 case Hexagon::C2_cmpeq:
247 case Hexagon::C2_cmpgt:
260 case Hexagon::C2_cmpgtu:
273 case Hexagon::C2_cmpeqi:
291 case Hexagon::C2_cmpgti:
309 case Hexagon::C2_cmpgtui:
320 case Hexagon::S2_tstbit_i:
336 MCInst const &MIb,
bool IsExtendedB) {
343 (Opca == Hexagon::A2_tfr || Opca == Hexagon::A2_tfrsi))
352 bool JExtended =
false;
355 J != MCI.
end(); ++J) {
356 MCInst const *JumpInst = J->getInst();
363 bool BExtended =
false;
366 B != MCI.
end(); ++
B) {
367 MCInst const *Inst =
B->getInst();
368 if (JumpInst == Inst)
380 << JumpInst->
getOpcode() <<
" Compounds to "
382 J->setInst(CompoundInsn);
402 "Non-Bundle where Bundle expected");
void tryCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
bool isIntRegForSubInst(unsigned Reg)
bool isBundle(MCInst const &MCI)
static const unsigned tstBitOpcode[8]
bool isImmext(MCInst const &MCI)
static const unsigned cmpeqBitOpcode[8]
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
Instances of this class represent a single low-level machine instruction.
const MCExpr * getExpr() const
static const unsigned cmpgtuBitOpcode[8]
static unsigned getCompoundOp(MCInst const &HMCI)
getCompoundOp - Return the index from 0-7 into the above opcode lists.
static const unsigned cmpeqiBitOpcode[8]
Interface to description of machine instruction set.
static MCInst * getCompoundInsn(MCContext &Context, MCInst const &L, MCInst const &R)
static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, MCInst const &MIb, bool IsExtendedB)
Non-Symmetrical. See if these two instructions are fit for compound pair.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setOpcode(unsigned Op)
size_t const bundleInstructionsOffset
static unsigned getCompoundCandidateGroup(MCInst const &MI, bool IsExtended)
static const unsigned cmpgtn1BitOpcode[8]
int64_t minConstant(MCInst const &MCI, size_t Index)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned getOpcode() const
static const unsigned cmpeqn1BitOpcode[8]
static const unsigned cmpgtiBitOpcode[8]
static const unsigned cmpgtuiBitOpcode[8]
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
static const unsigned cmpgtBitOpcode[8]
void addOperand(const MCOperand &Op)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)
const MCOperand & getOperand(unsigned i) const