LLVM  4.0.0
llvm::AMDGPUTargetLowering Member List

This is the complete list of members for llvm::AMDGPUTargetLowering, including all inherited members.

addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)llvm::TargetLoweringBaseinlineprotected
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
addRegisterClass(MVT VT, const TargetRegisterClass *RC)llvm::TargetLoweringBaseinlineprotected
AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const llvm::TargetLoweringvirtual
aggressivelyPreferBuildVectorSources(EVT VecVT) const overridellvm::AMDGPUTargetLoweringvirtual
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const llvm::TargetLoweringBase
allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, bool *=nullptr) const llvm::TargetLoweringBaseinlinevirtual
allowTruncateForTailCall(Type *FromTy, Type *ToTy) const llvm::TargetLoweringBaseinlinevirtual
AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI)llvm::AMDGPUTargetLowering
AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const llvm::AMDGPUTargetLoweringprotected
analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const llvm::AMDGPUTargetLoweringprotected
AnalyzeReturn(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs) const llvm::AMDGPUTargetLoweringprotected
ArgListTy typedefllvm::TargetLowering
AsmOperandInfoVector typedefllvm::TargetLowering
AtomicExpansionKind enum namellvm::TargetLoweringBase
BooleanContent enum namellvm::TargetLoweringBase
BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const llvm::TargetLoweringvirtual
BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const llvm::TargetLowering
C_Memory enum valuellvm::TargetLowering
C_Other enum valuellvm::TargetLowering
C_Register enum valuellvm::TargetLowering
C_RegisterClass enum valuellvm::TargetLowering
C_Unknown enum valuellvm::TargetLowering
canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const llvm::TargetLoweringBaseinlinevirtual
CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const llvm::TargetLoweringinlinevirtual
canOpTrap(unsigned Op, EVT VT) const llvm::TargetLoweringBasevirtual
CombineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLowering
combineRepeatedFPDivisors() const llvm::TargetLoweringinlinevirtual
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const llvm::TargetLoweringvirtual
computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::AMDGPUTargetLoweringvirtual
ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth=0) const overridellvm::AMDGPUTargetLoweringvirtual
computeRegisterProperties(const TargetRegisterInfo *TRI)llvm::TargetLoweringBaseprotected
ConstraintType enum namellvm::TargetLowering
ConstraintWeight enum namellvm::TargetLowering
createFastISel(FunctionLoweringInfo &, const TargetLibraryInfo *) const llvm::TargetLoweringinlinevirtual
CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const llvm::AMDGPUTargetLoweringvirtual
Custom enum valuellvm::TargetLoweringBase
CW_Best enum valuellvm::TargetLowering
CW_Better enum valuellvm::TargetLowering
CW_Constant enum valuellvm::TargetLowering
CW_Default enum valuellvm::TargetLowering
CW_Good enum valuellvm::TargetLowering
CW_Invalid enum valuellvm::TargetLowering
CW_Memory enum valuellvm::TargetLowering
CW_Okay enum valuellvm::TargetLowering
CW_Register enum valuellvm::TargetLowering
CW_SpecificReg enum valuellvm::TargetLowering
Disabled enum valuellvm::TargetLoweringBase
emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const llvm::TargetLoweringBaseinlinevirtual
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const llvm::TargetLoweringvirtual
emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const llvm::TargetLoweringBaseinlinevirtual
emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const llvm::TargetLoweringBaseinlinevirtual
emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const llvm::TargetLoweringBaseprotected
emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const llvm::TargetLoweringBaseinlinevirtual
emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const llvm::TargetLoweringBaseinlinevirtual
enableAggressiveFMAFusion(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
Enabled enum valuellvm::TargetLoweringBase
enableExtLdPromotion() const llvm::TargetLoweringBaseinline
EnableExtLdPromotionllvm::TargetLoweringBaseprotected
Expand enum valuellvm::TargetLoweringBase
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const llvm::TargetLowering
ExpandInlineAsm(CallInst *) const llvm::TargetLoweringinlinevirtual
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const llvm::TargetLowering
expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const llvm::TargetLowering
expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const llvm::TargetLowering
expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const llvm::TargetLowering
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const llvm::TargetLoweringBaseprotectedvirtual
FIRST_IMPLICIT enum valuellvm::AMDGPUTargetLowering
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const llvm::TargetLoweringinlinevirtual
GatherAllAliasesMaxDepthllvm::TargetLoweringBaseprotected
GetAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&, unsigned AddrSpace=0) const llvm::TargetLoweringBaseinlinevirtual
getBooleanContents(bool isVec, bool isFloat) const llvm::TargetLoweringBaseinline
getBooleanContents(EVT Type) const llvm::TargetLoweringBaseinline
getBypassSlowDivWidths() const llvm::TargetLoweringBaseinline
getByValTypeAlignment(Type *Ty, const DataLayout &DL) const llvm::TargetLoweringBasevirtual
getClearCacheBuiltinName() const llvm::TargetLoweringinlinevirtual
getCmpLibcallCC(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getCmpLibcallReturnType() const llvm::TargetLoweringBasevirtual
getCondCodeAction(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBaseinline
getConstraintType(StringRef Constraint) const llvm::TargetLoweringvirtual
getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const llvm::TargetLowering
getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const llvm::TargetLoweringBaseprotected
getDivRefinementSteps(EVT VT, MachineFunction &MF) const llvm::TargetLoweringBase
getEquivalentMemType(LLVMContext &Context, EVT VT)llvm::AMDGPUTargetLoweringprotectedstatic
getExceptionPointerRegister(const Constant *PersonalityFn) const llvm::TargetLoweringBaseinlinevirtual
getExceptionSelectorRegister(const Constant *PersonalityFn) const llvm::TargetLoweringBaseinlinevirtual
getExtendForAtomicOps() const llvm::TargetLoweringBaseinlinevirtual
getExtendForContent(BooleanContent Content)llvm::TargetLoweringBaseinlinestatic
getGatherAllAliasesMaxDepth() const llvm::TargetLoweringBaseinline
getHiHalf64(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const llvm::AMDGPUTargetLowering
getIndexedLoadAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBaseinline
getIndexedStoreAction(unsigned IdxMode, MVT VT) const llvm::TargetLoweringBaseinline
getInlineAsmMemConstraint(StringRef ConstraintCode) const llvm::TargetLoweringinlinevirtual
getIRStackGuard(IRBuilder<> &IRB) const llvm::TargetLoweringBasevirtual
getJumpBufAlignment() const llvm::TargetLoweringBaseinline
getJumpBufSize() const llvm::TargetLoweringBaseinline
getJumpTableEncoding() const llvm::TargetLoweringvirtual
getLibcallCallingConv(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getLibcallName(RTLIB::Libcall Call) const llvm::TargetLoweringBaseinline
getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
getLoHalf64(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
getMaxAtomicSizeInBitsSupported() const llvm::TargetLoweringBaseinline
getMaximumJumpTableSize() const llvm::TargetLoweringBase
getMaxStoresPerMemcpy(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxStoresPerMemmove(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxStoresPerMemset(bool OptSize) const llvm::TargetLoweringBaseinline
getMaxSupportedInterleaveFactor() const llvm::TargetLoweringBaseinlinevirtual
getMinCmpXchgSizeInBits() const llvm::TargetLoweringBaseinline
getMinFunctionAlignment() const llvm::TargetLoweringBaseinline
getMinimumJumpTableEntries() const llvm::TargetLoweringBase
getMinStackArgumentAlignment() const llvm::TargetLoweringBaseinline
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const llvm::TargetLoweringvirtual
getNumRegisters(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getOperationAction(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, MachineFunction &) const llvm::TargetLoweringBaseinlinevirtual
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const llvm::TargetLoweringvirtual
getPointerTy(const DataLayout &DL, uint32_t AS=0) const llvm::TargetLoweringBaseinline
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLoweringinlinevirtual
getPredictableBranchThreshold() const llvm::TargetLoweringBasevirtual
getPreferredVectorAction(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
getPrefFunctionAlignment() const llvm::TargetLoweringBaseinline
getPrefLoopAlignment(MachineLoop *ML=nullptr) const llvm::TargetLoweringBaseinlinevirtual
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const llvm::TargetLoweringinlinevirtual
getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const overridellvm::AMDGPUTargetLoweringvirtual
getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const llvm::TargetLoweringBase
getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const llvm::TargetLoweringBase
getRegClassFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const llvm::TargetLoweringvirtual
getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const llvm::TargetLoweringinlinevirtual
getRegisterType(MVT VT) const llvm::TargetLoweringBaseinline
getRegisterType(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getRepRegClassCostFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getRepRegClassFor(MVT VT) const llvm::TargetLoweringBaseinlinevirtual
getSafeStackPointerLocation(IRBuilder<> &IRB) const llvm::TargetLoweringBasevirtual
getScalarShiftAmountTy(const DataLayout &, EVT) const llvm::TargetLoweringBasevirtual
getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS=0) const llvm::TargetLoweringBaseinlinevirtual
getSchedulingPreference() const llvm::TargetLoweringBaseinline
getSchedulingPreference(SDNode *) const llvm::TargetLoweringBaseinlinevirtual
getScratchRegisters(CallingConv::ID CC) const llvm::TargetLoweringinlinevirtual
getSDagStackGuard(const Module &M) const llvm::TargetLoweringBasevirtual
getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const llvm::TargetLoweringBasevirtual
getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const llvm::TargetLoweringBase
getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBaseinline
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const llvm::TargetLoweringvirtual
getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const overridellvm::AMDGPUTargetLoweringvirtual
getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const llvm::TargetLoweringBase
getSSPStackGuardCheck(const Module &M) const llvm::TargetLoweringBasevirtual
getStackPointerRegisterToSaveRestore() const llvm::TargetLoweringBaseinline
getTargetMachine() const llvm::TargetLoweringBaseinline
getTargetNodeName(unsigned Opcode) const overridellvm::AMDGPUTargetLoweringvirtual
getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned) const llvm::TargetLoweringBaseinlinevirtual
getTruncStoreAction(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
getTypeAction(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getTypeAction(MVT VT) const llvm::TargetLoweringBaseinline
getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const llvm::TargetLoweringinlinevirtual
getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const llvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getTypeToPromoteTo(unsigned Op, MVT VT) const llvm::TargetLoweringBaseinline
getTypeToTransformTo(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinline
getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const llvm::TargetLoweringBaseinline
getValueTypeActions() const llvm::TargetLoweringBaseinline
getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Idx) const llvm::TargetLowering
getVectorIdxTy(const DataLayout &) const overridellvm::AMDGPUTargetLoweringvirtual
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const llvm::TargetLoweringBase
GRID_DIM enum valuellvm::AMDGPUTargetLowering
GRID_OFFSET enum valuellvm::AMDGPUTargetLowering
HandleByVal(CCState *, unsigned &, unsigned) const llvm::TargetLoweringinlinevirtual
hasAndNot(SDValue X) const llvm::TargetLoweringBaseinlinevirtual
hasAndNotCompare(SDValue Y) const llvm::TargetLoweringBaseinlinevirtual
hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const llvm::TargetLoweringBaseinline
hasBitPreservingFPLogic(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
hasCopyImplyingStackAdjustment(MachineFunction *MF) const llvm::TargetLoweringinlinevirtual
hasExtractBitsInsn() const llvm::TargetLoweringBaseinline
hasFloatingPointExceptions() const llvm::TargetLoweringBaseinline
hasMultipleConditionRegisters() const llvm::TargetLoweringBaseinline
hasPairedLoad(EVT, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
hasStandaloneRem(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
hasTargetDAGCombine(ISD::NodeType NT) const llvm::TargetLoweringBaseinline
ImplicitParameter enum namellvm::AMDGPUTargetLowering
IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const llvm::TargetLowering
initActions()llvm::TargetLoweringBaseprotected
initializeSplitCSR(MachineBasicBlock *Entry) const llvm::TargetLoweringinlinevirtual
insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const llvm::TargetLoweringinlinevirtual
insertSSPDeclarations(Module &M) const llvm::TargetLoweringBasevirtual
InstructionOpcodeToISD(unsigned Opcode) const llvm::TargetLoweringBase
isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const llvm::TargetLoweringBaseinlinevirtual
isCheapToSpeculateCtlz() const overridellvm::AMDGPUTargetLoweringvirtual
isCheapToSpeculateCttz() const overridellvm::AMDGPUTargetLoweringvirtual
isCondCodeLegal(ISD::CondCode CC, MVT VT) const llvm::TargetLoweringBaseinline
isConstFalseVal(const SDNode *N) const llvm::TargetLowering
isConstTrueVal(const SDNode *N) const llvm::TargetLowering
isCtlzFast() const llvm::TargetLoweringBaseinlinevirtual
isDesirableToCommuteWithShift(const SDNode *N) const llvm::TargetLoweringinlinevirtual
IsDesirableToPromoteOp(SDValue, EVT &) const llvm::TargetLoweringinlinevirtual
isDesirableToTransformToIntegerOp(unsigned, EVT) const llvm::TargetLoweringinlinevirtual
isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const llvm::TargetLowering
isExtFree(const Instruction *I) const llvm::TargetLoweringBaseinline
isExtFreeImpl(const Instruction *I) const llvm::TargetLoweringBaseinlineprotectedvirtual
isExtractSubvectorCheap(EVT ResVT, unsigned Index) const llvm::TargetLoweringBaseinlinevirtual
isFAbsFree(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
isFMAFasterThanFMulAndFAdd(EVT) const llvm::TargetLoweringBaseinlinevirtual
isFNegFree(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const llvm::TargetLoweringBaseinlinevirtual
isFPExtFree(EVT VT) const llvm::TargetLoweringBaseinlinevirtual
isFPImmLegal(const APFloat &Imm, EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringinlinevirtual
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const llvm::TargetLoweringvirtual
isIndexedLoadLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBaseinline
isIndexedStoreLegal(unsigned IdxMode, EVT VT) const llvm::TargetLoweringBaseinline
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const llvm::TargetLowering
isIntDivCheap(EVT VT, AttributeSet Attr) const llvm::TargetLoweringBaseinlinevirtual
isJumpExpensive() const llvm::TargetLoweringBaseinline
isJumpTableRelative() const llvm::TargetLoweringBaseinlinevirtual
isLegalAddImmediate(int64_t) const llvm::TargetLoweringBaseinlinevirtual
isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace) const llvm::TargetLoweringBasevirtual
isLegalICmpImmediate(int64_t) const llvm::TargetLoweringBaseinlinevirtual
isLegalRC(const TargetRegisterClass *RC) const llvm::TargetLoweringBaseprotected
isLoadBitCastBeneficial(EVT, EVT) const finalllvm::AMDGPUTargetLoweringvirtual
isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isMaskAndBranchFoldingLegal() const llvm::TargetLoweringBaseinline
isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const llvm::TargetLoweringBaseinlinevirtual
isNarrowingProfitable(EVT VT1, EVT VT2) const overridellvm::AMDGPUTargetLoweringvirtual
isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const llvm::TargetLoweringBaseinlinevirtual
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const llvm::TargetLoweringvirtual
isOperationCustom(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationExpand(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegal(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegalOrCustom(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isOperationLegalOrPromote(unsigned Op, EVT VT) const llvm::TargetLoweringBaseinline
isPositionIndependent() const llvm::TargetLowering
isPredictableSelectExpensive() const llvm::TargetLoweringBaseinline
isProfitableToHoist(Instruction *I) const llvm::TargetLoweringBaseinlinevirtual
isSafeMemOpType(MVT) const llvm::TargetLoweringBaseinlinevirtual
isSelectSupported(SelectSupportKind) const overridellvm::AMDGPUTargetLoweringvirtual
isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBaseinlinevirtual
isSlowDivBypassed() const llvm::TargetLoweringBaseinline
isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const llvm::TargetLoweringBaseinlinevirtual
isTruncateFree(EVT Src, EVT Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isTruncateFree(Type *Src, Type *Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isTruncStoreLegal(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const llvm::TargetLoweringBaseinline
isTypeDesirableForOp(unsigned, EVT VT) const llvm::TargetLoweringinlinevirtual
isTypeLegal(EVT VT) const llvm::TargetLoweringBaseinline
isUsedByReturnOnly(SDNode *, SDValue &) const llvm::TargetLoweringinlinevirtual
isVectorClearMaskLegal(const SmallVectorImpl< int > &, EVT) const llvm::TargetLoweringBaseinlinevirtual
isVectorLoadExtDesirable(SDValue ExtVal) const llvm::TargetLoweringBaseinlinevirtual
isVectorShiftByScalarCheap(Type *Ty) const llvm::TargetLoweringBaseinlinevirtual
isZExtFree(Type *Src, Type *Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isZExtFree(EVT Src, EVT Dest) const overridellvm::AMDGPUTargetLoweringvirtual
isZExtFree(SDValue Val, EVT VT2) const overridellvm::AMDGPUTargetLoweringvirtual
Legal enum valuellvm::TargetLoweringBase
LegalizeAction enum namellvm::TargetLoweringBase
LegalizeKind typedefllvm::TargetLoweringBase
LegalizeTypeAction enum namellvm::TargetLoweringBase
LibCall enum valuellvm::TargetLoweringBase
LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const overridellvm::AMDGPUTargetLoweringvirtual
LowerCallTo(CallLoweringInfo &CLI) const llvm::TargetLowering
lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const llvm::TargetLowering
LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerCTLZ(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const llvm::TargetLoweringinlinevirtual
LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const llvm::AMDGPUTargetLoweringprotected
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLowering
LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFCEIL(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const llvm::TargetLoweringinlinevirtual
LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const llvm::AMDGPUTargetLoweringprotected
LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFREM(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFRINT(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFROUND(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFROUND32(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFROUND64(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotectedvirtual
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const llvm::TargetLoweringBaseinlinevirtual
LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const llvm::AMDGPUTargetLoweringprotected
LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const llvm::AMDGPUTargetLoweringprotected
lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const llvm::TargetLoweringBaseinlinevirtual
lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const llvm::TargetLoweringBaseinlinevirtual
LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerOperation(SDValue Op, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringvirtual
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringvirtual
LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerSTORE(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const llvm::TargetLoweringvirtual
LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerUDIVREM64(SDValue Op, SelectionDAG &DAG, SmallVectorImpl< SDValue > &Results) const llvm::AMDGPUTargetLoweringprotected
LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
LowerXConstraint(EVT ConstraintVT) const llvm::TargetLoweringvirtual
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, bool isSigned, const SDLoc &dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const llvm::TargetLowering
MaskAndBranchFoldingIsLegalllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyllvm::TargetLoweringBaseprotected
MaxStoresPerMemcpyOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemmovellvm::TargetLoweringBaseprotected
MaxStoresPerMemmoveOptSizellvm::TargetLoweringBaseprotected
MaxStoresPerMemsetllvm::TargetLoweringBaseprotected
MaxStoresPerMemsetOptSizellvm::TargetLoweringBaseprotected
mayBeEmittedAsTailCall(CallInst *) const llvm::TargetLoweringinlinevirtual
mayIgnoreSignedZero(SDValue Op) const llvm::AMDGPUTargetLoweringinline
MulExpansionKind enum namellvm::TargetLoweringBase
needsFixedCatchObjects() const llvm::TargetLoweringBaseinlinevirtual
operator=(const TargetLowering &)=deletellvm::TargetLowering
llvm::TargetLoweringBase::operator=(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const llvm::TargetLowering
ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, ImmutableCallSite CS) const llvm::TargetLoweringvirtual
performCtlzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS, SDValue RHS, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const overridellvm::AMDGPUTargetLoweringvirtual
performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const llvm::AMDGPUTargetLoweringprotected
PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const =0llvm::AMDGPUTargetLoweringpure virtual
PredictableSelectIsExpensivellvm::TargetLoweringBaseprotected
prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const llvm::TargetLoweringinlinevirtual
Promote enum valuellvm::TargetLoweringBase
ReciprocalEstimate enum namellvm::TargetLoweringBase
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const overridellvm::AMDGPUTargetLoweringvirtual
ScalarCondVectorVal enum valuellvm::TargetLoweringBase
scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const llvm::TargetLowering
scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const llvm::TargetLowering
ScalarValSelect enum valuellvm::TargetLoweringBase
SelectSupportKind enum namellvm::TargetLoweringBase
setBooleanContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)llvm::TargetLoweringBaseinlineprotected
setBooleanVectorContents(BooleanContent Ty)llvm::TargetLoweringBaseinlineprotected
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)llvm::TargetLoweringBaseinline
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setHasExtractBitsInsn(bool hasExtractInsn=true)llvm::TargetLoweringBaseinlineprotected
setHasFloatingPointExceptions(bool FPExceptions=true)llvm::TargetLoweringBaseinlineprotected
setHasMultipleConditionRegisters(bool hasManyRegs=true)llvm::TargetLoweringBaseinlineprotected
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setJumpBufAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setJumpBufSize(unsigned Size)llvm::TargetLoweringBaseinlineprotected
setJumpIsExpensive(bool isExpensive=true)llvm::TargetLoweringBaseprotected
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)llvm::TargetLoweringBaseinline
setLibcallName(RTLIB::Libcall Call, const char *Name)llvm::TargetLoweringBaseinline
setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMaximumJumpTableSize(unsigned)llvm::TargetLoweringBaseprotected
setMinCmpXchgSizeInBits(unsigned SizeInBits)llvm::TargetLoweringBaseinlineprotected
setMinFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setMinimumJumpTableEntries(unsigned Val)llvm::TargetLoweringBaseprotected
setMinStackArgumentAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)llvm::TargetLoweringBaseinlineprotected
setPrefFunctionAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setPrefLoopAlignment(unsigned Align)llvm::TargetLoweringBaseinlineprotected
setSchedulingPreference(Sched::Preference Pref)llvm::TargetLoweringBaseinlineprotected
setStackPointerRegisterToSaveRestore(unsigned R)llvm::TargetLoweringBaseinlineprotected
setTargetDAGCombine(ISD::NodeType NT)llvm::TargetLoweringBaseinlineprotected
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreLongJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
setUseUnderscoreSetJmp(bool Val)llvm::TargetLoweringBaseinlineprotected
shouldAlignPointerArgs(CallInst *, unsigned &, unsigned &) const llvm::TargetLoweringBaseinlinevirtual
shouldCombineMemoryType(EVT VT) const llvm::AMDGPUTargetLoweringprotected
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicLoadInIR(LoadInst *LI) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicRMWInIR(AtomicRMWInst *) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandAtomicStoreInIR(StoreInst *SI) const llvm::TargetLoweringBaseinlinevirtual
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const llvm::TargetLoweringBaseinlinevirtual
shouldInsertFencesForAtomic(const Instruction *I) const llvm::TargetLoweringBaseinlinevirtual
shouldNormalizeToSelectSequence(LLVMContext &Context, EVT VT) const llvm::TargetLoweringBaseinlinevirtual
shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtType, EVT ExtVT) const overridellvm::AMDGPUTargetLoweringvirtual
ShouldShrinkFPConstant(EVT VT) const overridellvm::AMDGPUTargetLoweringvirtual
shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const llvm::TargetLoweringBaseinlinevirtual
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const llvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const llvm::TargetLowering
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL) const llvm::TargetLowering
split64BitValue(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const llvm::AMDGPUTargetLoweringprotected
SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
SplitVectorStore(SDValue Op, SelectionDAG &DAG) const llvm::AMDGPUTargetLoweringprotected
storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AS) const overridellvm::AMDGPUTargetLoweringvirtual
Subtargetllvm::AMDGPUTargetLoweringprotected
supportSplitCSR(MachineFunction *MF) const llvm::TargetLoweringinlinevirtual
supportSwiftError() const llvm::TargetLoweringinlinevirtual
TargetLowering(const TargetLowering &)=deletellvm::TargetLowering
TargetLowering(const TargetMachine &TM)llvm::TargetLoweringexplicit
TargetLoweringBase(const TargetMachine &TM)llvm::TargetLoweringBaseexplicit
TargetLoweringBase(const TargetLoweringBase &)=deletellvm::TargetLoweringBase
TypeExpandFloat enum valuellvm::TargetLoweringBase
TypeExpandInteger enum valuellvm::TargetLoweringBase
TypeLegal enum valuellvm::TargetLoweringBase
TypePromoteFloat enum valuellvm::TargetLoweringBase
TypePromoteInteger enum valuellvm::TargetLoweringBase
TypeScalarizeVector enum valuellvm::TargetLoweringBase
TypeSoftenFloat enum valuellvm::TargetLoweringBase
TypeSplitVector enum valuellvm::TargetLoweringBase
TypeWidenVector enum valuellvm::TargetLoweringBase
UndefinedBooleanContent enum valuellvm::TargetLoweringBase
Unspecified enum valuellvm::TargetLoweringBase
useLoadStackGuardNode() const llvm::TargetLoweringinlinevirtual
useSoftFloat() const llvm::TargetLoweringBaseinlinevirtual
usesUnderscoreLongJmp() const llvm::TargetLoweringBaseinline
usesUnderscoreSetJmp() const llvm::TargetLoweringBaseinline
ValueTypeActionsllvm::TargetLoweringBaseprotected
VectorMaskSelect enum valuellvm::TargetLoweringBase
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const llvm::TargetLowering
ZeroOrNegativeOneBooleanContent enum valuellvm::TargetLoweringBase
ZeroOrOneBooleanContent enum valuellvm::TargetLoweringBase
~TargetLoweringBase()=defaultllvm::TargetLoweringBasevirtual