34 PPC::V0 , PPC::V1 ,
PPC::V2 , PPC::V3 ,
PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
58 return STI.
isPPC64() ? -8U : -4U;
61 return STI.
isPPC64() ? -8U : -4U;
74 return STI.
isPPC64() ? -16U : -8U;
84 STI.getPlatformStackAlignment(), 0),
93 unsigned &NumEntries)
const {
97 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
98 return &darwin64Offsets;
100 static const SpillSlot darwinOffsets = {PPC::R31, -4};
101 return &darwinOffsets;
263 assert(MBBI != Entry->
end() && MBBI->getOpcode() == PPC::MTVRSAVE);
264 MBBI->eraseFromParent();
266 bool RemovedAllMTVRSAVEs =
true;
271 if (
I->isReturnBlock()) {
272 bool FoundIt =
false;
273 for (MBBI =
I->end(); MBBI !=
I->begin(); ) {
275 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
276 MBBI->eraseFromParent();
281 RemovedAllMTVRSAVEs &= FoundIt;
287 if (RemovedAllMTVRSAVEs) {
289 assert(MBBI != Entry->
begin() &&
"UPDATE_VRSAVE is first instr in block?");
291 assert(MBBI->getOpcode() == PPC::MFVRSAVE &&
"VRSAVE instrs wandered?");
292 MBBI->eraseFromParent();
308 unsigned UsedRegMask = 0;
309 for (
unsigned i = 0;
i != 32; ++
i)
311 UsedRegMask |= 1 << (31-i);
320 UsedRegMask &= ~(1 << (31-RegNo));
325 UsedRegMask != 0 && BI != BE; ++BI) {
332 if (!MO.
isReg() || !PPC::VRRCRegClass.contains(MO.
getReg()))
335 UsedRegMask &= ~(1 << (31-RegNo));
340 if (UsedRegMask == 0) {
349 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
350 if (DstReg != SrcReg)
358 }
else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
359 if (DstReg != SrcReg)
362 .
addImm(UsedRegMask >> 16);
366 .
addImm(UsedRegMask >> 16);
368 if (DstReg != SrcReg)
371 .
addImm(UsedRegMask >> 16);
375 .
addImm(UsedRegMask >> 16);
379 .
addImm(UsedRegMask & 0xFFFF);
424 bool UseEstimate)
const {
434 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
445 unsigned LR = RegInfo->getRARegister();
446 if (!DisableRedZone &&
466 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
471 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
478 FrameSize += maxCallFrameSize;
481 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
519 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
520 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
526 unsigned BP8Reg = HasBP ? (
unsigned) PPC::X30 : FPReg;
532 for (
unsigned I = 0,
E = MBBI->getNumOperands();
I !=
E; ++
I) {
575 bool TwoUniqueRegsRequired,
577 unsigned *SR2)
const {
579 unsigned R0 = Subtarget.
isPPC64() ? PPC::X0 : PPC::R0;
580 unsigned R12 = Subtarget.
isPPC64() ? PPC::X12 : PPC::R12;
587 assert (SR1 &&
"Asking for the second scratch register but not the first?");
598 if (UseAtEnd && !MBB->
empty()) {
604 if (MBBI == MBB->
end())
605 MBBI = std::prev(MBBI);
607 if (MBBI != MBB->
begin())
631 for (
int i = 0; CSRegs[
i]; ++
i)
637 *SR1 = FirstScratchReg == -1 ? (
unsigned)PPC::NoRegister : FirstScratchReg;
644 int SecondScratchReg = BV.
find_next(*SR1);
645 if (SecondScratchReg != -1)
646 *SR2 = SecondScratchReg;
648 *SR2 = TwoUniqueRegsRequired ? (
unsigned)PPC::NoRegister : *SR1;
653 if (BV.
count() < (TwoUniqueRegsRequired ? 2U : 1U))
671 int NegFrameSize = -FrameSize;
672 bool IsLargeFrame = !
isInt<16>(NegFrameSize);
677 return (IsLargeFrame || !HasRedZone) && HasBP && MaxAlign > 1;
683 return findScratchRegister(TmpMBB,
false,
684 twoUniqueScratchRegsRequired(TmpMBB));
690 return findScratchRegister(TmpMBB,
true);
709 bool isPPC64 = Subtarget.
isPPC64();
714 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
719 for (
unsigned i = 0; MBBI != MBB.
end(); ++
i, ++MBBI) {
720 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
731 int NegFrameSize = -FrameSize;
742 bool MustSaveCR = !MustSaveCRs.
empty();
744 bool HasFP =
hasFP(MF);
746 bool HasRedZone = isPPC64 || !isSVR4ABI;
748 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
750 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
751 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
752 unsigned ScratchReg = 0;
753 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12;
755 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
759 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
761 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
763 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
765 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
767 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
769 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
771 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
778 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
779 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
782 bool SingleScratchReg =
783 findScratchRegister(&MBB,
false, twoUniqueScratchRegsRequired(&MBB),
784 &ScratchReg, &TempReg);
785 assert(SingleScratchReg &&
786 "Required number of registers not available in this block");
788 SingleScratchReg = ScratchReg == TempReg;
797 assert(FPIndex &&
"No Frame Pointer Save Slot!");
809 assert(BPIndex &&
"No Base Pointer Save Slot!");
820 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
826 if (HasBP && MaxAlign > 1)
828 "Invalid alignment!");
832 bool isLargeFrame = !
isInt<16>(NegFrameSize);
834 assert((isPPC64 || !MustSaveCR) &&
835 "Prologue CR saving supported only in 64-bit mode");
839 if (MustSaveCR && SingleScratchReg && MustSaveLR) {
844 unsigned MfcrOpcode = PPC::MFCR8;
846 if (isELFv2ABI && MustSaveCRs.
size() == 1) {
847 MfcrOpcode = PPC::MFOCRF8;
851 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
852 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++
i)
853 MIB.
addReg(MustSaveCRs[i], CrState);
854 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
861 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
864 !(SingleScratchReg && MustSaveLR)) {
869 unsigned MfcrOpcode = PPC::MFCR8;
871 if (isELFv2ABI && MustSaveCRs.
size() == 1) {
872 MfcrOpcode = PPC::MFOCRF8;
876 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
877 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++
i)
878 MIB.
addReg(MustSaveCRs[i], CrState);
883 BuildMI(MBB, MBBI, dl, StoreInst)
888 BuildMI(MBB, MBBI, dl, StoreInst)
893 BuildMI(MBB, MBBI, dl, StoreInst)
900 BuildMI(MBB, MBBI, dl, StoreInst)
906 !(SingleScratchReg && MustSaveLR)) {
907 assert(HasRedZone &&
"A red zone is always available on PPC64");
908 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
921 if (HasBP && HasRedZone) {
923 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
930 bool HasSTUX =
false;
933 if (HasBP && MaxAlign > 1) {
935 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
940 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
946 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
950 assert(!SingleScratchReg &&
"Only a single scratch reg available");
951 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
952 .
addImm(NegFrameSize >> 16);
953 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
955 .
addImm(NegFrameSize & 0xFFFF);
956 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
961 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
967 }
else if (!isLargeFrame) {
968 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
974 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
975 .
addImm(NegFrameSize >> 16);
976 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
978 .
addImm(NegFrameSize & 0xFFFF);
979 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
987 assert(!isPPC64 &&
"A red zone is always available on PPC64");
999 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
1003 if (ScratchReg == PPC::R0) {
1010 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1012 .
addImm(FPOffset-LastOffset);
1013 LastOffset = FPOffset;
1015 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1022 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1024 .
addImm(PBPOffset-LastOffset);
1025 LastOffset = PBPOffset;
1026 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1033 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1035 .
addImm(BPOffset-LastOffset);
1036 LastOffset = BPOffset;
1037 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1042 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1053 BuildMI(MBB, MBBI, dl, StoreInst)
1058 BuildMI(MBB, MBBI, dl, StoreInst)
1063 BuildMI(MBB, MBBI, dl, StoreInst)
1067 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1078 BuildMI(MBB, MBBI, dl, StoreInst)
1080 .
addImm(FrameSize + FPOffset)
1083 BuildMI(MBB, MBBI, dl, StoreInst)
1085 .
addImm(FrameSize + PBPOffset)
1088 BuildMI(MBB, MBBI, dl, StoreInst)
1090 .
addImm(FrameSize + BPOffset)
1092 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1116 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1117 .addCFIIndex(CFIIndex);
1124 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1125 .addCFIIndex(CFIIndex);
1133 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1134 .addCFIIndex(CFIIndex);
1142 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1143 .addCFIIndex(CFIIndex);
1151 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1152 .addCFIIndex(CFIIndex);
1158 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1162 if (!HasBP && needsCFI) {
1169 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1170 .addCFIIndex(CFIIndex);
1178 for (
unsigned I = 0,
E = CSI.size();
I !=
E; ++
I) {
1179 unsigned Reg = CSI[
I].getReg();
1180 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg ==
PPC::RM)
continue;
1184 if (PPC::CRBITRCRegClass.
contains(Reg))
1189 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1195 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1199 unsigned CRReg = isELFv2ABI? Reg : (
unsigned) PPC::CR2;
1202 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1203 .addCFIIndex(CFIIndex);
1210 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1211 .addCFIIndex(CFIIndex);
1221 if (MBBI != MBB.
end())
1222 dl = MBBI->getDebugLoc();
1236 bool isPPC64 = Subtarget.
isPPC64();
1244 bool MustSaveCR = !MustSaveCRs.
empty();
1246 bool HasFP =
hasFP(MF);
1250 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1252 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1253 unsigned ScratchReg = 0;
1254 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12;
1255 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1259 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1261 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1263 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1265 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1267 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1275 bool SingleScratchReg = findScratchRegister(&MBB,
true,
false, &ScratchReg,
1277 assert(SingleScratchReg &&
1278 "Could not find an available scratch register");
1280 SingleScratchReg = ScratchReg == TempReg;
1285 assert(FPIndex &&
"No Frame Pointer Save Slot!");
1296 assert(BPIndex &&
"No Base Pointer Save Slot!");
1306 assert(PBPIndex &&
"No PIC Base Pointer Save Slot!");
1310 bool IsReturnBlock = (MBBI != MBB.
end() && MBBI->isReturn());
1312 if (IsReturnBlock) {
1313 unsigned RetOpcode = MBBI->getOpcode();
1314 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1315 RetOpcode == PPC::TCRETURNdi ||
1316 RetOpcode == PPC::TCRETURNai ||
1317 RetOpcode == PPC::TCRETURNri8 ||
1318 RetOpcode == PPC::TCRETURNdi8 ||
1319 RetOpcode == PPC::TCRETURNai8;
1324 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
1326 int StackAdj = StackAdjust.
getImm();
1327 int Delta = StackAdj - MaxTCRetDelta;
1328 assert((Delta >= 0) &&
"Delta must be positive");
1329 if (MaxTCRetDelta>0)
1330 FrameSize += (StackAdj +Delta);
1332 FrameSize += StackAdj;
1338 bool isLargeFrame = !
isInt<16>(FrameSize);
1352 unsigned RBReg = SPReg;
1365 assert(HasFP &&
"Expecting a valid frame pointer.");
1368 if (!isLargeFrame) {
1369 BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1372 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1373 .
addImm(FrameSize >> 16);
1374 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1376 .
addImm(FrameSize & 0xFFFF);
1377 BuildMI(MBB, MBBI, dl, AddInst)
1384 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1390 assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 &&
1391 "Local offsets should be negative");
1393 FPOffset += FrameSize;
1394 BPOffset += FrameSize;
1395 PBPOffset += FrameSize;
1403 BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1408 BuildMI(MBB, MBBI, dl, LoadInst, RBReg)
1413 assert(RBReg != ScratchReg &&
"Should have avoided ScratchReg");
1418 assert((isPPC64 || !MustSaveCR) &&
1419 "Epilogue CR restoring supported only in 64-bit mode");
1423 if (MustSaveCR && SingleScratchReg && MustSaveLR) {
1426 assert(HasRedZone &&
"Expecting red zone");
1427 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1430 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++
i)
1431 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[
i])
1439 bool LoadedLR =
false;
1440 if (MustSaveLR && RBReg == SPReg &&
isInt<16>(LROffset+SPAdd)) {
1441 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1447 if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
1449 assert(isPPC64 &&
"Expecting 64-bit mode");
1450 assert(RBReg == SPReg &&
"Should be using SP as a base register");
1451 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1459 if (HasRedZone || RBReg == SPReg)
1460 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1464 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1470 BuildMI(MBB, MBBI, dl, LoadInst)
1476 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1482 if (RBReg != SPReg || SPAdd != 0) {
1483 assert(!HasRedZone &&
"This should not happen with red zone");
1486 BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1490 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1494 assert(RBReg != ScratchReg &&
"Should be using FP or SP as base register");
1496 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1501 if (MustSaveLR && !LoadedLR)
1502 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1508 !(SingleScratchReg && MustSaveLR))
1509 for (
unsigned i = 0, e = MustSaveCRs.
size(); i != e; ++
i)
1510 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[
i])
1518 if (IsReturnBlock) {
1519 unsigned RetOpcode = MBBI->getOpcode();
1521 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1526 if (CallerAllocatedAmt &&
isInt<16>(CallerAllocatedAmt)) {
1527 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1530 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1531 .
addImm(CallerAllocatedAmt >> 16);
1532 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1534 .
addImm(CallerAllocatedAmt & 0xFFFF);
1535 BuildMI(MBB, MBBI, dl, AddInst)
1541 createTailCallBranchInstr(MBB);
1546 void PPCFrameLowering::createTailCallBranchInstr(
MachineBasicBlock &MBB)
const {
1550 if (MBBI != MBB.
end())
1551 dl = MBBI->getDebugLoc();
1557 unsigned RetOpcode = MBBI->getOpcode();
1558 if (RetOpcode == PPC::TCRETURNdi) {
1561 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1563 }
else if (RetOpcode == PPC::TCRETURNri) {
1565 assert(MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1566 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1567 }
else if (RetOpcode == PPC::TCRETURNai) {
1570 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.
getImm());
1571 }
else if (RetOpcode == PPC::TCRETURNdi8) {
1574 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1576 }
else if (RetOpcode == PPC::TCRETURNri8) {
1578 assert(MBBI->getOperand(0).isReg() &&
"Expecting register operand.");
1579 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1580 }
else if (RetOpcode == PPC::TCRETURNai8) {
1583 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.
getImm());
1597 unsigned LR = RegInfo->getRARegister();
1599 SavedRegs.
reset(LR);
1603 bool isPPC64 = Subtarget.
isPPC64();
1638 SavedRegs.
reset(isPPC64 ? PPC::X31 : PPC::R31);
1642 SavedRegs.
reset(PPC::R30);
1653 if (!isPPC64 && !isDarwinABI &&
1654 (SavedRegs.
test(PPC::CR2) ||
1655 SavedRegs.
test(PPC::CR3) ||
1656 SavedRegs.
test(PPC::CR4))) {
1682 createTailCallBranchInstr(MBB);
1687 if (CSI.empty() && !
needsFP(MF)) {
1692 unsigned MinGPR = PPC::R31;
1693 unsigned MinG8R = PPC::X31;
1694 unsigned MinFPR = PPC::F31;
1695 unsigned MinVR = PPC::V31;
1697 bool HasGPSaveArea =
false;
1698 bool HasG8SaveArea =
false;
1699 bool HasFPSaveArea =
false;
1700 bool HasVRSAVESaveArea =
false;
1701 bool HasVRSaveArea =
false;
1708 for (
unsigned i = 0, e = CSI.size(); i != e; ++
i) {
1709 unsigned Reg = CSI[
i].getReg();
1710 if (PPC::GPRCRegClass.
contains(Reg)) {
1711 HasGPSaveArea =
true;
1718 }
else if (PPC::G8RCRegClass.
contains(Reg)) {
1719 HasG8SaveArea =
true;
1726 }
else if (PPC::F8RCRegClass.
contains(Reg)) {
1727 HasFPSaveArea =
true;
1734 }
else if (PPC::CRBITRCRegClass.
contains(Reg) ||
1737 }
else if (PPC::VRSAVERCRegClass.
contains(Reg)) {
1738 HasVRSAVESaveArea =
true;
1739 }
else if (PPC::VRRCRegClass.
contains(Reg)) {
1740 HasVRSaveArea =
true;
1755 int64_t LowerBound = 0;
1761 LowerBound = TCSPDelta;
1766 if (HasFPSaveArea) {
1767 for (
unsigned i = 0, e = FPRegs.
size(); i != e; ++
i) {
1768 int FI = FPRegs[
i].getFrameIdx();
1773 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1779 HasGPSaveArea =
true;
1782 assert(FI &&
"No Frame Pointer Save Slot!");
1788 HasGPSaveArea =
true;
1791 assert(FI &&
"No PIC Base Pointer Save Slot!");
1799 HasGPSaveArea =
true;
1802 assert(FI &&
"No Base Pointer Save Slot!");
1809 if (HasGPSaveArea || HasG8SaveArea) {
1812 for (
unsigned i = 0, e = GPRegs.
size(); i != e; ++
i) {
1813 int FI = GPRegs[
i].getFrameIdx();
1820 for (
unsigned i = 0, e = G8Regs.
size(); i != e; ++
i) {
1821 int FI = G8Regs[
i].getFrameIdx();
1827 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1828 TRI->getEncodingValue(MinG8R));
1831 LowerBound -= (31 - MinReg + 1) * 8;
1833 LowerBound -= (31 - MinReg + 1) * 4;
1844 for (
unsigned i = 0, e = CSI.size(); i != e; ++
i) {
1845 unsigned Reg = CSI[
i].getReg();
1847 if ((Subtarget.
isSVR4ABI() && Reg == PPC::CR2)
1850 (PPC::CRBITRCRegClass.contains(Reg) ||
1851 PPC::CRRCRegClass.contains(Reg)))) {
1852 int FI = CSI[
i].getFrameIdx();
1861 if (HasVRSAVESaveArea) {
1865 for (
unsigned i = 0, e = CSI.size(); i != e; ++
i) {
1866 unsigned Reg = CSI[
i].getReg();
1868 if (PPC::VRSAVERCRegClass.
contains(Reg)) {
1869 int FI = CSI[
i].getFrameIdx();
1878 if (HasVRSaveArea) {
1880 LowerBound = (LowerBound - 15) & ~(15);
1882 for (
unsigned i = 0, e = VRegs.
size(); i != e; ++
i) {
1883 int FI = VRegs[
i].getFrameIdx();
1935 const std::vector<CalleeSavedInfo> &CSI,
1947 bool CRSpilled =
false;
1950 for (
unsigned i = 0, e = CSI.size(); i != e; ++
i) {
1951 unsigned Reg = CSI[
i].getReg();
1955 if (Reg == PPC::VRSAVE && !Subtarget.
isDarwinABI())
1959 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1964 if (CRSpilled && IsCRField) {
1981 CRMIB =
BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1988 CSI[i].getFrameIdx()));
1993 CSI[i].getFrameIdx(), RC, TRI);
2001 bool CR2Spilled,
bool CR3Spilled,
bool CR4Spilled,
2003 const std::vector<CalleeSavedInfo> &CSI,
unsigned CSIIndex) {
2008 unsigned RestoreOp, MoveReg;
2017 CSI[CSIIndex].getFrameIdx()));
2018 RestoreOp = PPC::MTOCRF;
2023 MBB.
insert(MI,
BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2027 MBB.
insert(MI,
BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2031 MBB.
insert(MI,
BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2040 I->getOpcode() == PPC::ADJCALLSTACKUP) {
2042 if (
int CalleeAmt = I->getOperand(1).getImm()) {
2045 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
2046 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
2047 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
2048 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
2049 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
2050 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
2051 const DebugLoc &dl = I->getDebugLoc();
2054 BuildMI(MBB, I, dl, TII.
get(ADDIInstr), StackReg)
2059 BuildMI(MBB, MBBI, dl, TII.
get(LISInstr), TmpReg)
2060 .addImm(CalleeAmt >> 16);
2061 BuildMI(MBB, MBBI, dl, TII.
get(ORIInstr), TmpReg)
2063 .
addImm(CalleeAmt & 0xFFFF);
2064 BuildMI(MBB, MBBI, dl, TII.
get(ADDInstr), StackReg)
2071 return MBB.
erase(I);
2077 const std::vector<CalleeSavedInfo> &CSI,
2088 bool CR2Spilled =
false;
2089 bool CR3Spilled =
false;
2090 bool CR4Spilled =
false;
2091 unsigned CSIIndex = 0;
2096 bool AtStart = I == MBB.
begin();
2101 for (
unsigned i = 0, e = CSI.size(); i != e; ++
i) {
2102 unsigned Reg = CSI[
i].getReg();
2107 if (Reg == PPC::VRSAVE && !Subtarget.
isDarwinABI())
2110 if (Reg == PPC::CR2) {
2116 }
else if (Reg == PPC::CR3) {
2119 }
else if (Reg == PPC::CR4) {
2125 if ((CR2Spilled || CR3Spilled || CR4Spilled)
2126 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
2129 CR2Spilled, CR3Spilled, CR4Spilled,
2130 MBB,
I, CSI, CSIIndex);
2131 CR2Spilled = CR3Spilled = CR4Spilled =
false;
2139 "loadRegFromStackSlot didn't insert any code!");
2152 if (CR2Spilled || CR3Spilled || CR4Spilled) {
2155 MBB,
I, CSI, CSIIndex);
void replaceFPWithRealFP(MachineFunction &MF) const
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const GlobalValue * getGlobal() const
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
int getTailCallSPDelta() const
static const unsigned GPRegs[]
livein_iterator livein_end() const
const PPCTargetMachine & getTargetMachine() const
void addMustSaveCR(unsigned Reg)
MachineBasicBlock * getRestorePoint() const
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
void setFramePointerSaveIndex(int Idx)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
static unsigned computeTOCSaveOffset(const PPCSubtarget &STI)
static const MCPhysReg VRegs[32]
bool isLRStoreRequired() const
constexpr bool isInt< 16 >(int64_t x)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
An instruction for reading from memory.
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
return AArch64::GPR64RegClass contains(Reg)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
static void restoreCRs(bool isPPC64, bool is31, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, unsigned CSIIndex)
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getMinReservedArea() const
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
bool isVRSAVESpilled() const
bool hasDebugInfo() const
Returns true if valid debug info is present.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
int getBasePointerSaveIndex() const
static bool hasNonRISpills(const MachineFunction &MF)
void forward()
Move the internal MBB iterator and update register states.
const MachineBasicBlock & front() const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
unsigned getBasePointerSaveOffset() const
getBasePointerSaveOffset - Return the previous frame offset to save the base pointer.
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
int getPICBasePointerSaveIndex() const
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
An instruction for storing to memory.
int getFramePointerSaveIndex() const
const SmallVectorImpl< unsigned > & getMustSaveCRs() const
unsigned getKillRegState(bool B)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool hasStackMap() const
This method may be called any time after instruction selection is complete to determine if there is a...
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
size_type count() const
count - Returns the number of bits which are set.
This file declares the machine register scavenger class.
static const unsigned G8Regs[]
unsigned const MachineRegisterInfo * MRI
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
constexpr bool isPowerOf2_32(uint32_t Value)
isPowerOf2_32 - This function returns true if the argument is a power of two > 0. ...
void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const
unsigned getBaseRegister(const MachineFunction &MF) const
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Methods used by shrink wrapping to determine if MBB can be used for the function prologue/epilogue.
void setStackSize(uint64_t Size)
Set the size of the stack.
static bool is64Bit(const char *name)
const MachineOperand & getOperand(unsigned i) const
static ManagedStatic< OptionRegistry > OR
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool isPositionIndependent() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned computeReturnSaveOffset(const PPCSubtarget &STI)
void setBasePointerSaveIndex(int Idx)
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
int64_t getOffset() const
Return the offset from the symbol in this operand.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void setCRSpillFrameIndex(int idx)
const PPCRegisterInfo * getRegisterInfo() const override
Iterator for intrusive lists based on ilist_node.
bool hasTailCall() const
Returns true if the function contains a tail call.
constexpr bool isInt< 32 >(int64_t x)
const MCContext & getContext() const
const PPCInstrInfo * getInstrInfo() const override
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool test(unsigned Idx) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isRegUsed(unsigned Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Information about stack frame layout on the target.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
static bool spillsVRSAVE(const MachineFunction &MF)
livein_iterator livein_begin() const
static bool hasSpills(const MachineFunction &MF)
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
static bool spillsCR(const MachineFunction &MF)
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
static bool MustSaveLR(const MachineFunction &MF, unsigned LR)
MustSaveLR - Return true if this function requires that we save the LR register onto the stack in the...
def_iterator def_begin(unsigned RegNo) const
bool needsFP(const MachineFunction &MF) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const MCRegisterInfo * getRegisterInfo() const
MachineBasicBlock * getSavePoint() const
void setPICBasePointerSaveIndex(int Idx)
Representation of each machine instruction.
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII)
PPCFrameLowering(const PPCSubtarget &STI)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
void setMaxCallFrameSize(unsigned S)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool hasNonRISpills() const
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI)
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
static void RemoveVRSaveCode(MachineInstr &MI)
RemoveVRSaveCode - We have found that this function does not need any code to manipulate the VRSAVE r...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static def_iterator def_end()
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineModuleInfo & getMMI() const
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
static const MCPhysReg VRRegNo[]
VRRegNo - Map from a numbered VR register to its enum value.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Fast - This calling convention attempts to make calls as fast as possible (e.g.
bool hasBasePointer(const MachineFunction &MF) const
static unsigned computeLinkageSize(const PPCSubtarget &STI)
void setMustSaveLR(bool U)
MustSaveLR - This is set when the prolog/epilog inserter does its initial scan of the function...
This class contains meta information specific to a module.