68 #define DEBUG_TYPE "systemz-long-branch"
70 STATISTIC(LongBranches,
"Number of long branches.");
87 unsigned NumTerminators;
90 :
Address(0), Size(0), Alignment(0), NumTerminators(0) {}
94 struct TerminatorInfo {
107 unsigned TargetBlock;
111 unsigned ExtraRelaxSize;
113 TerminatorInfo() :
Branch(nullptr), Size(0), TargetBlock(0),
118 struct BlockPosition {
126 BlockPosition(
unsigned InitialAlignment)
127 :
Address(0), KnownBits(InitialAlignment) {}
136 StringRef getPassName()
const override {
return "SystemZ Long Branch"; }
145 void skipNonTerminators(BlockPosition &Position, MBBInfo &Block);
146 void skipTerminator(BlockPosition &Position, TerminatorInfo &
Terminator,
149 uint64_t initMBBInfo();
151 bool mustRelaxABranch();
152 void setWorstCaseAddresses();
154 void splitCompareBranch(
MachineInstr *
MI,
unsigned CompareOpcode);
156 void relaxBranches();
166 const uint64_t MaxBackwardRange = 0x10000;
167 const uint64_t MaxForwardRange = 0xfffe;
171 return new SystemZLongBranch(TM);
177 void SystemZLongBranch::skipNonTerminators(BlockPosition &Position,
179 if (Block.Alignment > Position.KnownBits) {
182 Position.Address += ((uint64_t(1) << Block.Alignment) -
183 (uint64_t(1) << Position.KnownBits));
184 Position.KnownBits = Block.Alignment;
188 uint64_t AlignMask = (uint64_t(1) << Block.Alignment) - 1;
189 Position.Address = (Position.Address + AlignMask) & ~AlignMask;
192 Block.Address = Position.Address;
195 Position.Address += Block.Size;
201 void SystemZLongBranch::skipTerminator(BlockPosition &Position,
203 bool AssumeRelaxed) {
204 Terminator.Address = Position.Address;
205 Position.Address += Terminator.Size;
207 Position.Address += Terminator.ExtraRelaxSize;
211 TerminatorInfo SystemZLongBranch::describeTerminator(
MachineInstr &
MI) {
213 Terminator.Size =
TII->getInstSizeInBytes(MI);
218 Terminator.ExtraRelaxSize = 2;
222 Terminator.ExtraRelaxSize = 2;
227 Terminator.ExtraRelaxSize = 6;
231 Terminator.ExtraRelaxSize = 0;
236 Terminator.ExtraRelaxSize = 2;
241 Terminator.ExtraRelaxSize = 4;
246 Terminator.ExtraRelaxSize = 4;
251 Terminator.ExtraRelaxSize = 6;
256 Terminator.Branch = &
MI;
257 Terminator.TargetBlock =
258 TII->getBranchInfo(MI).Target->getMBB()->getNumber();
266 uint64_t SystemZLongBranch::initMBBInfo() {
267 MF->RenumberBlocks();
268 unsigned NumBlocks = MF->size();
271 MBBs.resize(NumBlocks);
274 Terminators.reserve(NumBlocks);
276 BlockPosition Position(MF->getAlignment());
277 for (
unsigned I = 0;
I < NumBlocks; ++
I) {
279 MBBInfo &Block = MBBs[
I];
287 while (MI != End && !MI->isTerminator()) {
288 Block.Size +=
TII->getInstSizeInBytes(*MI);
291 skipNonTerminators(Position, Block);
295 if (!MI->isDebugValue()) {
296 assert(MI->isTerminator() &&
"Terminator followed by non-terminator");
297 Terminators.push_back(describeTerminator(*MI));
298 skipTerminator(Position, Terminators.back(),
false);
299 ++Block.NumTerminators;
305 return Position.Address;
310 bool SystemZLongBranch::mustRelaxBranch(
const TerminatorInfo &Terminator,
312 if (!Terminator.Branch)
315 const MBBInfo &
Target = MBBs[Terminator.TargetBlock];
316 if (Address >= Target.Address) {
317 if (Address - Target.Address <= MaxBackwardRange)
320 if (Target.Address - Address <= MaxForwardRange)
329 bool SystemZLongBranch::mustRelaxABranch() {
330 for (
auto &Terminator : Terminators)
331 if (mustRelaxBranch(Terminator, Terminator.Address))
338 void SystemZLongBranch::setWorstCaseAddresses() {
340 BlockPosition Position(MF->getAlignment());
341 for (
auto &Block : MBBs) {
342 skipNonTerminators(Position, Block);
343 for (
unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
344 skipTerminator(Position, *TI,
true);
352 void SystemZLongBranch::splitBranchOnCount(
MachineInstr *MI,
353 unsigned AddOpcode) {
371 void SystemZLongBranch::splitCompareBranch(
MachineInstr *MI,
372 unsigned CompareOpcode) {
375 BuildMI(*MBB, MI, DL,
TII->get(CompareOpcode))
388 void SystemZLongBranch::relaxBranch(TerminatorInfo &Terminator) {
398 splitBranchOnCount(Branch, SystemZ::AHI);
401 splitBranchOnCount(Branch, SystemZ::AGHI);
404 splitCompareBranch(Branch, SystemZ::CR);
407 splitCompareBranch(Branch, SystemZ::CGR);
410 splitCompareBranch(Branch, SystemZ::CHI);
413 splitCompareBranch(Branch, SystemZ::CGHI);
416 splitCompareBranch(Branch, SystemZ::CLR);
419 splitCompareBranch(Branch, SystemZ::CLGR);
422 splitCompareBranch(Branch, SystemZ::CLFI);
425 splitCompareBranch(Branch, SystemZ::CLGFI);
431 Terminator.Size += Terminator.ExtraRelaxSize;
432 Terminator.ExtraRelaxSize = 0;
433 Terminator.Branch =
nullptr;
439 void SystemZLongBranch::relaxBranches() {
441 BlockPosition Position(MF->getAlignment());
442 for (
auto &Block : MBBs) {
443 skipNonTerminators(Position, Block);
444 for (
unsigned BTI = 0, BTE = Block.NumTerminators; BTI != BTE; ++BTI) {
445 assert(Position.Address <= TI->Address &&
446 "Addresses shouldn't go forwards");
447 if (mustRelaxBranch(*TI, Position.Address))
449 skipTerminator(Position, *TI,
false);
458 uint64_t Size = initMBBInfo();
459 if (Size <= MaxForwardRange || !mustRelaxABranch())
462 setWorstCaseAddresses();
STATISTIC(NumFunctions,"Total number of functions")
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
const unsigned CCMASK_ICMP
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
const MachineOperand & getOperand(unsigned i) const
static const unsigned End
FunctionPass class - This class is used to implement most global optimizations.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
const unsigned CCMASK_CMP_NE
FunctionPass * createSystemZLongBranchPass(SystemZTargetMachine &TM)
Target - Wrapper for Target specific information.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
StringRef - Represent a constant reference to a string, i.e.
Properties which a MachineFunction may have at a given point in time.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
unsigned getAlignment() const
Return alignment of the basic block.