26 #define DEBUG_TYPE "target-reg-info"
32 const char *
const *SRINames,
35 : InfoDesc(ID), SubRegIndexNames(SRINames),
36 SubRegIndexLaneMasks(SRILaneMasks),
37 RegClassBegin(RCB), RegClassEnd(RCE),
38 CoveringLanes(SRICoveringLanes) {
58 if (!RegisterSet[*SR] && !
is_contained(Exceptions, Reg)) {
59 dbgs() <<
"Error: Super register " <<
PrintReg(*SR,
this)
60 <<
" of reserved register " <<
PrintReg(Reg,
this)
61 <<
" is not reserved.\n";
84 else if (TRI && Reg < TRI->getNumRegs())
87 OS <<
"%physreg" <<
Reg;
92 OS <<
":sub(" << SubIdx <<
')';
101 OS <<
"Unit~" <<
Unit;
107 OS <<
"BadUnit~" <<
Unit;
115 for (++Roots; Roots.
isValid(); ++Roots)
116 OS <<
'~' << TRI->
getName(*Roots);
165 assert(BestRC &&
"Couldn't find the register class");
175 for (
unsigned i = 0;
i != Order.size(); ++
i)
190 if ((*I)->isAllocatable())
196 Allocatable &= Reserved.
flip();
209 if (
unsigned Common = *A++ & *B++) {
236 unsigned Idx)
const {
237 assert(A && B &&
"Missing register class");
238 assert(Idx &&
"Bad sub-register index");
242 if (RCI.getSubReg() == Idx)
252 unsigned &PreA,
unsigned &PreB)
const {
253 assert(RCA && SubA && RCB && SubB &&
"Invalid arguments");
268 unsigned *BestPreA = &PreA;
269 unsigned *BestPreB = &PreB;
278 unsigned MinSize = RCA->
getSize();
286 if (!RC || RC->
getSize() < MinSize)
291 if (FinalA != FinalB)
300 *BestPreA = IA.getSubReg();
301 *BestPreB = IB.getSubReg();
304 if (BestRC->
getSize() == MinSize)
317 unsigned SrcSubReg) {
323 unsigned SrcIdx, DefIdx;
324 if (SrcSubReg && DefSubReg) {
326 SrcIdx, DefIdx) !=
nullptr;
347 unsigned SrcSubReg)
const {
366 assert(Hint.first == 0 &&
"Target must implement TRI::getRegAllocationHints");
369 unsigned Phys = Hint.second;
403 DEBUG(
dbgs() <<
"Can't realign function's stack: " << F->
getName() <<
"\n");
411 for (
unsigned I = 0;
I <
N; ++
I)
412 if ((mask0[
I] & mask1[
I]) != mask0[
I])
417 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
bool hasType(MVT vt) const
Return true if this TargetRegisterClass has the ValueType vt.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
void push_back(const T &Elt)
bool isValid() const
Check if the iterator is at the end of the list.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
virtual ~TargetRegisterInfo()
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const
Mark a register and all its aliases as reserved in the given set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
regclass_iterator regclass_end() const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
StringRef getName() const
Return a constant reference to the value's name.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
unsigned getNumRegClasses() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MCSuperRegIterator enumerates all super-registers of Reg.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Reg
All possible values of the reg field in the ModR/M byte.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
MCRegUnitRootIterator enumerates the root registers of a register unit.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
MCRegisterClass - Base class of TargetRegisterClass.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any)
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
regclass_iterator regclass_begin() const
Register class iterators.
MVT - Machine Value Type.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well...
Extra information, not in MCRegisterDesc, about registers.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
virtual const TargetFrameLowering * getFrameLowering() const
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file...
Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Information about stack frame layout on the target.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes)
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT=MVT::SimpleValueType::Any) const
Find the largest common subclass of A and B.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
std::vector< uint8_t > Unit
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This class implements an extremely fast bulk output stream that can only output to a stream...
const char * getName(unsigned RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
unsigned getPhys(unsigned virtReg) const
returns the physical register mapped to the specified virtual register
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
std::set< RegisterRef > RegisterSet
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
std::pair< unsigned, unsigned > getRegAllocationHint(unsigned VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register...
Simple wrapper around std::function<void(raw_ostream&)>.
Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
virtual void getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
const TargetRegisterClass *const * regclass_iterator
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.