LLVM  4.0.0
HexagonSubtarget.h
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1 //===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Hexagon specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
16 
17 #include "HexagonFrameLowering.h"
18 #include "HexagonISelLowering.h"
19 #include "HexagonInstrInfo.h"
23 #include <string>
24 
25 #define GET_SUBTARGETINFO_HEADER
26 #include "HexagonGenSubtargetInfo.inc"
27 
28 #define Hexagon_SMALL_DATA_THRESHOLD 8
29 #define Hexagon_SLOTS 4
30 
31 namespace llvm {
32 
34  virtual void anchor();
35 
36  bool UseMemOps, UseHVXOps, UseHVXDblOps;
37  bool UseLongCalls;
38  bool ModeIEEERndNear;
39 
40 public:
42  V4, V5, V55, V60
43  };
44 
46  /// True if the target should use Back-Skip-Back scheduling. This is the
47  /// default for V60.
49 
51  public:
52  void apply(ScheduleDAGInstrs *DAG) override;
53  };
54 
55 private:
56  std::string CPUString;
57  HexagonInstrInfo InstrInfo;
58  HexagonTargetLowering TLInfo;
60  HexagonFrameLowering FrameLowering;
61  InstrItineraryData InstrItins;
62  void initializeEnvironment();
63 
64 public:
65  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
66  const TargetMachine &TM);
67 
68  /// getInstrItins - Return the instruction itineraries based on subtarget
69  /// selection.
70  const InstrItineraryData *getInstrItineraryData() const override {
71  return &InstrItins;
72  }
73  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
74  const HexagonRegisterInfo *getRegisterInfo() const override {
75  return &InstrInfo.getRegisterInfo();
76  }
77  const HexagonTargetLowering *getTargetLowering() const override {
78  return &TLInfo;
79  }
80  const HexagonFrameLowering *getFrameLowering() const override {
81  return &FrameLowering;
82  }
83  const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
84  return &TSInfo;
85  }
86 
88  StringRef FS);
89 
90  /// ParseSubtargetFeatures - Parses features string setting specified
91  /// subtarget options. Definition of function is auto generated by tblgen.
93 
94  bool useMemOps() const { return UseMemOps; }
95  bool hasV5TOps() const { return getHexagonArchVersion() >= V5; }
96  bool hasV5TOpsOnly() const { return getHexagonArchVersion() == V5; }
97  bool hasV55TOps() const { return getHexagonArchVersion() >= V55; }
98  bool hasV55TOpsOnly() const { return getHexagonArchVersion() == V55; }
99  bool hasV60TOps() const { return getHexagonArchVersion() >= V60; }
100  bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; }
101  bool modeIEEERndNear() const { return ModeIEEERndNear; }
102  bool useHVXOps() const { return UseHVXOps; }
103  bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; }
104  bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; }
105  bool useLongCalls() const { return UseLongCalls; }
106 
107  bool useBSBScheduling() const { return UseBSBScheduling; }
108  bool enableMachineScheduler() const override;
109  // Always use the TargetLowering default scheduler.
110  // FIXME: This will use the vliw scheduler which is probably just hurting
111  // compiler time and will be removed eventually anyway.
112  bool enableMachineSchedDefaultSched() const override { return false; }
113 
114  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
115  bool enablePostRAScheduler() const override { return true; }
116 
117  bool enableSubRegLiveness() const override;
118 
119  const std::string &getCPUString () const { return CPUString; }
120 
121  // Threshold for small data section
122  unsigned getSmallDataThreshold() const {
124  }
126  return HexagonArchVersion;
127  }
128 
129  void getPostRAMutations(
130  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
131  const override;
132 
133  void getSMSMutations(
134  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
135  const override;
136 
137  /// \brief Perform target specific adjustments to the latency of a schedule
138  /// dependency.
139  void adjustSchedDependency(SUnit *def, SUnit *use, SDep& dep) const override;
140 
141  unsigned getL1CacheLineSize() const;
142  unsigned getL1PrefetchDistance() const;
143 
144 private:
145  // Helper function responsible for increasing the latency only.
146  void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
147  const;
148  void changeLatency(SUnit *Src, SmallVector<SDep, 4> &Deps, SUnit *Dst,
149  unsigned Lat) const;
150  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII)
151  const;
152  void changePhiLatency(MachineInstr &SrcInst, SUnit *Dst, SDep &Dep) const;
153 };
154 
155 } // end namespace llvm
156 
157 #endif
const HexagonArchEnum & getHexagonArchVersion() const
AntiDepBreakMode getAntiDepBreakMode() const override
Mutate the DAG as a postpass after normal DAG building.
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
const HexagonFrameLowering * getFrameLowering() const override
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
unsigned getSmallDataThreshold() const
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
bool enablePostRAScheduler() const override
const HexagonInstrInfo * TII
unsigned getL1CacheLineSize() const
const HexagonRegisterInfo * getRegisterInfo() const override
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
const HexagonTargetLowering * getTargetLowering() const override
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Itinerary data supplied by a subtarget to be used by a target.
bool hasV60TOpsOnly() const
SDep - Scheduling dependency.
Definition: ScheduleDAG.h:45
HexagonArchEnum HexagonArchVersion
#define Hexagon_SMALL_DATA_THRESHOLD
unsigned getL1PrefetchDistance() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void apply(ScheduleDAGInstrs *DAG) override
bool useBSBScheduling() const
bool enableMachineScheduler() const override
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
bool enableSubRegLiveness() const override
void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
const std::string & getCPUString() const
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
Representation of each machine instruction.
Definition: MachineInstr.h:52
bool enableMachineSchedDefaultSched() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool modeIEEERndNear() const
pgo instr use
const HexagonInstrInfo * getInstrInfo() const override
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
bool hasV55TOpsOnly() const
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool hasV5TOpsOnly() const
SUnit - Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:244