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LLVM
4.0.0
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Helper class to build MachineInstr. More...
#include <MachineIRBuilder.h>
Public Member Functions | |
| MachineFunction & | getMF () |
| Getter for the function we currently build. More... | |
| MachineBasicBlock & | getMBB () |
| Getter for the basic block we currently build. More... | |
| MachineBasicBlock::iterator | getInsertPt () |
| Current insertion point for new instructions. More... | |
| void | setInsertPt (MachineBasicBlock &MBB, MachineBasicBlock::iterator II) |
| Set the insertion point before the specified position. More... | |
| void | setDebugLoc (const DebugLoc &DL) |
Set the debug location to DL for all the next build instructions. More... | |
| MachineInstrBuilder | buildInstr (unsigned Opcode) |
Build and insert <empty> = Opcode <empty>. More... | |
| MachineInstrBuilder | buildInstrNoInsert (unsigned Opcode) |
Build but don't insert <empty> = Opcode <empty>. More... | |
| MachineInstrBuilder | insertInstr (MachineInstrBuilder MIB) |
| Insert an existing instruction at the insertion point. More... | |
| MachineInstrBuilder | buildFrameIndex (unsigned Res, int Idx) |
Build and insert Res<def> = G_FRAME_INDEX Idx. More... | |
| MachineInstrBuilder | buildGlobalValue (unsigned Res, const GlobalValue *GV) |
Build and insert Res<def> = G_GLOBAL_VALUE GV. More... | |
| MachineInstrBuilder | buildAdd (unsigned Res, unsigned Op0, unsigned Op1) |
Build and insert Res<def> = G_ADD Op0, Op1. More... | |
| MachineInstrBuilder | buildSub (unsigned Res, unsigned Op0, unsigned Op1) |
Build and insert Res<def> = G_SUB Op0, Op1. More... | |
| MachineInstrBuilder | buildMul (unsigned Res, unsigned Op0, unsigned Op1) |
Build and insert Res<def> = G_MUL Op0, Op1. More... | |
| MachineInstrBuilder | buildGEP (unsigned Res, unsigned Op0, unsigned Op1) |
Build and insert Res<def> = G_GEP Op0, Op1. More... | |
| MachineInstrBuilder | buildUAdde (unsigned Res, unsigned CarryOut, unsigned Op0, unsigned Op1, unsigned CarryIn) |
Build and insert Res<def>, CarryOut<def> = G_UADDE Op0, Op1, CarryIn. More... | |
| MachineInstrBuilder | buildAnyExt (unsigned Res, unsigned Op) |
Build and insert Res<def> = G_ANYEXT Op0. More... | |
| MachineInstrBuilder | buildSExt (unsigned Res, unsigned Op) |
Build and insert Res<def> = G_SEXT Op. More... | |
| MachineInstrBuilder | buildZExt (unsigned Res, unsigned Op) |
Build and insert Res<def> = G_ZEXT Op. More... | |
| MachineInstrBuilder | buildSExtOrTrunc (unsigned Res, unsigned Op) |
Build and insert Res<def> = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op. More... | |
| MachineInstrBuilder | buildBr (MachineBasicBlock &BB) |
Build and insert G_BR Dest. More... | |
| MachineInstrBuilder | buildBrCond (unsigned Tst, MachineBasicBlock &BB) |
Build and insert G_BRCOND Tst, Dest. More... | |
| MachineInstrBuilder | buildConstant (unsigned Res, const ConstantInt &Val) |
Build and insert Res = G_CONSTANT Val. More... | |
| MachineInstrBuilder | buildConstant (unsigned Res, int64_t Val) |
Build and insert Res = G_CONSTANT Val. More... | |
| MachineInstrBuilder | buildFConstant (unsigned Res, const ConstantFP &Val) |
Build and insert Res = G_FCONSTANT Val. More... | |
| MachineInstrBuilder | buildCopy (unsigned Res, unsigned Op) |
Build and insert Res<def> = COPY Op. More... | |
| MachineInstrBuilder | buildLoad (unsigned Res, unsigned Addr, MachineMemOperand &MMO) |
Build and insert Res<def> = G_LOAD Addr, MMO. More... | |
| MachineInstrBuilder | buildStore (unsigned Val, unsigned Addr, MachineMemOperand &MMO) |
Build and insert G_STORE Val, Addr, MMO. More... | |
| MachineInstrBuilder | buildExtract (ArrayRef< unsigned > Results, ArrayRef< uint64_t > Indices, unsigned Src) |
| Build and insert `Res0<def>, ... More... | |
| MachineInstrBuilder | buildSequence (unsigned Res, ArrayRef< unsigned > Ops, ArrayRef< uint64_t > Indices) |
Build and insert Res<def> = G_SEQUENCE Op0, Idx0... More... | |
| void | addUsesWithIndices (MachineInstrBuilder MIB) |
| template<typename... ArgTys> | |
| void | addUsesWithIndices (MachineInstrBuilder MIB, unsigned Reg, unsigned BitIndex, ArgTys...Args) |
| template<typename... ArgTys> | |
| MachineInstrBuilder | buildSequence (unsigned Res, unsigned Op, unsigned Index, ArgTys...Args) |
| template<typename... ArgTys> | |
| MachineInstrBuilder | buildInsert (unsigned Res, unsigned Src, unsigned Op, unsigned Index, ArgTys...Args) |
| MachineInstrBuilder | buildIntrinsic (Intrinsic::ID ID, unsigned Res, bool HasSideEffects) |
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction. More... | |
| MachineInstrBuilder | buildFPTrunc (unsigned Res, unsigned Op) |
Build and insert Res<def> = G_FPTRUNC Op. More... | |
| MachineInstrBuilder | buildTrunc (unsigned Res, unsigned Op) |
Build and insert Res<def> = G_TRUNC Op. More... | |
| MachineInstrBuilder | buildICmp (CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1) |
Build and insert a Res = G_ICMP Pred, Op0, Op1. More... | |
| MachineInstrBuilder | buildFCmp (CmpInst::Predicate Pred, unsigned Res, unsigned Op0, unsigned Op1) |
Build and insert a Res = G_FCMP Pred Op1. More... | |
| MachineInstrBuilder | buildSelect (unsigned Res, unsigned Tst, unsigned Op0, unsigned Op1) |
Build and insert a Res = G_SELECT Tst, Op0, Op1. More... | |
| void | setMF (MachineFunction &) |
| Setters for the insertion point. More... | |
| void | setMBB (MachineBasicBlock &MBB) |
Set the insertion point to the end of MBB. More... | |
| void | setInstr (MachineInstr &MI) |
| Set the insertion point to before MI. More... | |
| void | recordInsertions (std::function< void(MachineInstr *)> InsertedInstr) |
| Control where instructions we create are recorded (typically for visiting again later during legalization). More... | |
| void | stopRecordingInsertions () |
Helper class to build MachineInstr.
It keeps internally the insertion point and debug location for all the new instructions we want to create. This information can be modify via the related setters.
Definition at line 38 of file MachineIRBuilder.h.
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Definition at line 396 of file MachineIRBuilder.h.
Referenced by addUsesWithIndices(), buildInsert(), and buildSequence().
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Definition at line 399 of file MachineIRBuilder.h.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addUse(), addUsesWithIndices(), and AMDGPU::RuntimeMD::KeyName::Args.
| MachineInstrBuilder MachineIRBuilder::buildAdd | ( | unsigned | Res, |
| unsigned | Op0, | ||
| unsigned | Op1 | ||
| ) |
Build and insert Res<def> = G_ADD Op0, Op1.
G_ADD sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).Definition at line 104 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isScalar(), and llvm::LLT::isVector().
Referenced by llvm::LegalizerHelper::fewerElementsVector().
| MachineInstrBuilder MachineIRBuilder::buildAnyExt | ( | unsigned | Res, |
| unsigned | Op | ||
| ) |
Build and insert Res<def> = G_ANYEXT Op0.
G_ANYEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are unspecified (i.e. this is neither zero nor sign-extension). For a vector register, each element is extended individually.
Res must be a generic virtual register with scalar or vector type. Op must be a generic virtual register with scalar or vector type. Op must be smaller than Res Definition at line 239 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), and buildInstr().
Referenced by llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildBr | ( | MachineBasicBlock & | BB | ) |
Build and insert G_BR Dest.
G_BR is an unconditional branch to Dest.
Definition at line 155 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addMBB(), and buildInstr().
| MachineInstrBuilder MachineIRBuilder::buildBrCond | ( | unsigned | Tst, |
| MachineBasicBlock & | BB | ||
| ) |
Build and insert G_BRCOND Tst, Dest.
G_BRCOND is a conditional branch to Dest.
Tst must be a generic virtual register with scalar type. At the beginning of legalization, this will be a single bit (s1). Targets with interesting flags registers may change this. For a wider type, whether the branch is taken must only depend on bit 0 (for now).Definition at line 192 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), and llvm::LLT::isScalar().
Referenced by llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildConstant | ( | unsigned | Res, |
| const ConstantInt & | Val | ||
| ) |
Build and insert Res = G_CONSTANT Val.
G_CONSTANT is an integer constant with the specified size and value. Val will be extended or truncated to the size of Reg.
Res must be a generic virtual register with scalar or pointer type.Definition at line 163 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addCImm(), llvm::MachineInstrBuilder::addDef(), assert(), buildInstr(), llvm::ConstantInt::get(), llvm::ConstantInt::getBitWidth(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::ConstantInt::getValue(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::APInt::sextOrTrunc().
Referenced by buildConstant(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildConstant | ( | unsigned | Res, |
| int64_t | Val | ||
| ) |
Build and insert Res = G_CONSTANT Val.
G_CONSTANT is an integer constant with the specified size and value.
Res must be a generic virtual register with scalar type.Definition at line 177 of file MachineIRBuilder.cpp.
References buildConstant(), llvm::IntegerType::get(), llvm::ConstantInt::get(), llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::LLT::getSizeInBits(), and llvm::MachineRegisterInfo::getType().
| MachineInstrBuilder MachineIRBuilder::buildCopy | ( | unsigned | Res, |
| unsigned | Op | ||
| ) |
Build and insert Res<def> = COPY Op.
Register-to-register COPY sets Res to Op.
Definition at line 159 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), and buildInstr().
| MachineInstrBuilder MachineIRBuilder::buildExtract | ( | ArrayRef< unsigned > | Results, |
| ArrayRef< uint64_t > | Indices, | ||
| unsigned | Src | ||
| ) |
Build and insert `Res0<def>, ...
= G_EXTRACT Src, Idx0, ...`.
If Res[i] has size N bits, G_EXTRACT sets Res[i] to bits [Idxs[i], Idxs[i] + N) of Src.
Results and Src must be a generic virtual register.Definition at line 265 of file MachineIRBuilder.cpp.
References assert(), llvm::ArrayRef< T >::begin(), llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::end(), getInsertPt(), getMBB(), getMF(), llvm::MachineRegisterInfo::getType(), llvm::MachineBasicBlock::insert(), llvm::LLT::isValid(), and llvm::ArrayRef< T >::size().
Referenced by llvm::AArch64CallLowering::lowerCall(), and llvm::AArch64CallLowering::lowerReturn().
| MachineInstrBuilder MachineIRBuilder::buildFCmp | ( | CmpInst::Predicate | Pred, |
| unsigned | Res, | ||
| unsigned | Op0, | ||
| unsigned | Op1 | ||
| ) |
Build and insert a Res = G_FCMP Pred Op0,Op1.
Res must be a generic virtual register with scalar or vector type. Typically this starts as s1 or <N x="" s1>="">. Op0 and Op1 must be generic virtual registers with the same number of elements as Res (or scalar, if Res is scalar). Pred must be a floating-point predicate.Definition at line 363 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addPredicate(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), llvm::CmpInst::isFPPredicate(), llvm::LLT::isScalar(), and llvm::LLT::isVector().
| MachineInstrBuilder MachineIRBuilder::buildFConstant | ( | unsigned | Res, |
| const ConstantFP & | Val | ||
| ) |
Build and insert Res = G_FCONSTANT Val.
G_FCONSTANT is a floating-point constant with the specified size and value.
Res must be a generic virtual register with scalar type.Definition at line 185 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addFPImm(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), and llvm::LLT::isScalar().
Referenced by llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildFPTrunc | ( | unsigned | Res, |
| unsigned | Op | ||
| ) |
Build and insert Res<def> = G_FPTRUNC Op.
G_FPTRUNC converts a floating-point value into one with a smaller type.
Res must be a generic virtual register with scalar or vector type. Op must be a generic virtual register with scalar or vector type. Res must be smaller than Op Definition at line 336 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), and buildInstr().
Referenced by llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildFrameIndex | ( | unsigned | Res, |
| int | Idx | ||
| ) |
Build and insert Res<def> = G_FRAME_INDEX Idx.
G_FRAME_INDEX materializes the address of an alloca value or other stack-based object.
Res must be a generic virtual register with pointer type.Definition at line 85 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addFrameIndex(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), and llvm::LLT::isPointer().
| MachineInstrBuilder MachineIRBuilder::buildGEP | ( | unsigned | Res, |
| unsigned | Op0, | ||
| unsigned | Op1 | ||
| ) |
Build and insert Res<def> = G_GEP Op0, Op1.
G_GEP adds Op1 bytes to the pointer specified by Op0, storing the resulting pointer in Res.
Res and Op0 must be generic virtual registers with pointer type. Op1 must be a generic virtual register with scalar type.Definition at line 117 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), and llvm::LLT::isScalar().
| MachineInstrBuilder MachineIRBuilder::buildGlobalValue | ( | unsigned | Res, |
| const GlobalValue * | GV | ||
| ) |
Build and insert Res<def> = G_GLOBAL_VALUE GV.
G_GLOBAL_VALUE materializes the address of the specified global into Res.
Res must be a generic virtual register with pointer type in the same address space as GV.Definition at line 92 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addGlobalAddress(), assert(), buildInstr(), llvm::LLT::getAddressSpace(), llvm::PointerType::getAddressSpace(), llvm::GlobalValue::getType(), llvm::MachineRegisterInfo::getType(), and llvm::LLT::isPointer().
| MachineInstrBuilder MachineIRBuilder::buildICmp | ( | CmpInst::Predicate | Pred, |
| unsigned | Res, | ||
| unsigned | Op0, | ||
| unsigned | Op1 | ||
| ) |
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Res must be a generic virtual register with scalar or vector type. Typically this starts as s1 or <N x="" s1>="">. Op0 and Op1 must be generic virtual registers with the same number of elements as Res. If Res is a scalar, Op0 must be either a scalar or pointer. Pred must be an integer predicate.Definition at line 341 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addPredicate(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), llvm::CmpInst::isIntPredicate(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isVector().
Referenced by llvm::LegalizerHelper::widenScalar().
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Definition at line 415 of file MachineIRBuilder.h.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), addUsesWithIndices(), AMDGPU::RuntimeMD::KeyName::Args, and buildInstr().
| MachineInstrBuilder MachineIRBuilder::buildInstr | ( | unsigned | Opcode | ) |
Build and insert <empty> = Opcode <empty>.
The insertion point is the one set by the last call of either setBasicBlock or setMI.
Definition at line 68 of file MachineIRBuilder.cpp.
References buildInstrNoInsert(), and insertInstr().
Referenced by buildAdd(), buildAnyExt(), buildBr(), buildBrCond(), buildConstant(), buildCopy(), buildFCmp(), buildFConstant(), buildFPTrunc(), buildFrameIndex(), buildGEP(), buildGlobalValue(), buildICmp(), buildInsert(), buildIntrinsic(), buildLoad(), buildMul(), buildSelect(), buildSequence(), buildSExt(), buildSExtOrTrunc(), buildStore(), buildSub(), buildTrunc(), buildUAdde(), buildZExt(), llvm::X86CallLowering::lowerReturn(), and llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert | ( | unsigned | Opcode | ) |
Build but don't insert <empty> = Opcode <empty>.
Definition at line 72 of file MachineIRBuilder.cpp.
References llvm::BuildMI(), and getMF().
Referenced by buildInstr(), llvm::AArch64CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerReturn(), and llvm::ARMCallLowering::lowerReturn().
| MachineInstrBuilder MachineIRBuilder::buildIntrinsic | ( | Intrinsic::ID | ID, |
| unsigned | Res, | ||
| bool | HasSideEffects | ||
| ) |
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction.
Its first operand will be the result register definition unless Reg is NoReg (== 0). The second operand will be the intrinsic's ID.
Callers are expected to add the required definitions and uses afterwards.
Definition at line 319 of file MachineIRBuilder.cpp.
References buildInstr().
| MachineInstrBuilder MachineIRBuilder::buildLoad | ( | unsigned | Res, |
| unsigned | Addr, | ||
| MachineMemOperand & | MMO | ||
| ) |
Build and insert Res<def> = G_LOAD Addr, MMO.
Loads the value stored at Addr. Puts the result in Res.
Res must be a generic virtual register. Addr must be a generic virtual register with pointer type.Definition at line 199 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), and llvm::LLT::isValid().
Referenced by llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildMul | ( | unsigned | Res, |
| unsigned | Op0, | ||
| unsigned | Op1 | ||
| ) |
Build and insert Res<def> = G_MUL Op0, Op1.
G_MUL sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).Definition at line 142 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isScalar(), and llvm::LLT::isVector().
| MachineInstrBuilder MachineIRBuilder::buildSelect | ( | unsigned | Res, |
| unsigned | Tst, | ||
| unsigned | Op0, | ||
| unsigned | Op1 | ||
| ) |
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Res, Op0 and Op1 must be generic virtual registers with the same type. Tst must be a generic virtual register with scalar, pointer or vector type. If vector then it must have the same number of elements as the other parameters.Definition at line 387 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::LLT::getNumElements(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isVector().
| MachineInstrBuilder MachineIRBuilder::buildSequence | ( | unsigned | Res, |
| ArrayRef< unsigned > | Ops, | ||
| ArrayRef< uint64_t > | Indices | ||
| ) |
Build and insert Res<def> = G_SEQUENCE Op0, Idx0...
G_SEQUENCE inserts each element of Ops into an IMPLICIT_DEF register, where each entry starts at the bit-index specified by Indices.
Indices must be in ascending order of bit position.Definition at line 296 of file MachineIRBuilder.cpp.
References assert(), llvm::ArrayRef< T >::begin(), buildInstr(), llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::end(), llvm::MachineRegisterInfo::getType(), i, llvm::LLT::isValid(), and llvm::ArrayRef< T >::size().
Referenced by llvm::LegalizerHelper::fewerElementsVector(), llvm::AArch64CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerFormalArguments(), and llvm::LegalizerHelper::narrowScalar().
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Definition at line 406 of file MachineIRBuilder.h.
References llvm::MachineInstrBuilder::addDef(), addUsesWithIndices(), AMDGPU::RuntimeMD::KeyName::Args, and buildInstr().
| MachineInstrBuilder MachineIRBuilder::buildSExt | ( | unsigned | Res, |
| unsigned | Op | ||
| ) |
Build and insert Res<def> = G_SEXT Op.
G_SEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are duplicated from the high bit of Op (i.e. 2s-complement sign extended).
Res must be a generic virtual register with scalar or vector type. Op must be a generic virtual register with scalar or vector type. Op must be smaller than Res Definition at line 244 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), and buildInstr().
Referenced by llvm::CallLowering::ValueHandler::extendRegister(), and llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc | ( | unsigned | Res, |
| unsigned | Op | ||
| ) |
Build and insert Res<def> = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op.
///
Res must be a generic virtual register with scalar or vector type. Op must be a generic virtual register with scalar or vector type.Definition at line 254 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), buildInstr(), llvm::LLT::getSizeInBits(), and llvm::MachineRegisterInfo::getType().
| MachineInstrBuilder MachineIRBuilder::buildStore | ( | unsigned | Val, |
| unsigned | Addr, | ||
| MachineMemOperand & | MMO | ||
| ) |
Build and insert G_STORE Val, Addr, MMO.
Stores the value Val to Addr.
Val must be a generic virtual register. Addr must be a generic virtual register with pointer type.Definition at line 210 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), and llvm::LLT::isValid().
Referenced by llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildSub | ( | unsigned | Res, |
| unsigned | Op0, | ||
| unsigned | Op1 | ||
| ) |
Build and insert Res<def> = G_SUB Op0, Op1.
G_SUB sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).Definition at line 129 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isScalar(), and llvm::LLT::isVector().
| MachineInstrBuilder MachineIRBuilder::buildTrunc | ( | unsigned | Res, |
| unsigned | Op | ||
| ) |
Build and insert Res<def> = G_TRUNC Op.
G_TRUNC extracts the low bits of a type. For a vector type each element is truncated independently before being packed into the destination.
Res must be a generic virtual register with scalar or vector type. Op must be a generic virtual register with scalar or vector type. Res must be smaller than Op Definition at line 331 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), and buildInstr().
Referenced by llvm::LegalizerHelper::widenScalar().
| MachineInstrBuilder MachineIRBuilder::buildUAdde | ( | unsigned | Res, |
| unsigned | CarryOut, | ||
| unsigned | Op0, | ||
| unsigned | Op1, | ||
| unsigned | CarryIn | ||
| ) |
Build and insert Res<def>, CarryOut<def> = G_UADDE Op0, Op1, CarryIn.
G_UADDE sets Res to Op0 + Op1 + CarryIn (truncated to the bit width) and sets CarryOut to 1 if the result overflowed in unsigned arithmetic.
Res, Op0 and Op1 must be generic virtual registers with the same scalar type. CarryOut and CarryIn must be generic virtual registers with the same scalar type (typically s1)Definition at line 221 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), llvm::MachineRegisterInfo::getType(), and llvm::LLT::isScalar().
Referenced by llvm::LegalizerHelper::narrowScalar().
| MachineInstrBuilder MachineIRBuilder::buildZExt | ( | unsigned | Res, |
| unsigned | Op | ||
| ) |
Build and insert Res<def> = G_ZEXT Op.
G_ZEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are 0. For a vector register, each element is extended individually.
Res must be a generic virtual register with scalar or vector type. Op must be a generic virtual register with scalar or vector type. Op must be smaller than Res Definition at line 249 of file MachineIRBuilder.cpp.
References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), and buildInstr().
Referenced by llvm::CallLowering::ValueHandler::extendRegister(), and llvm::LegalizerHelper::widenScalar().
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Current insertion point for new instructions.
Definition at line 77 of file MachineIRBuilder.h.
Referenced by buildExtract(), and insertInstr().
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Getter for the basic block we currently build.
Definition at line 71 of file MachineIRBuilder.h.
References assert().
Referenced by buildExtract(), insertInstr(), and llvm::AArch64CallLowering::lowerFormalArguments().
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Getter for the function we currently build.
Definition at line 65 of file MachineIRBuilder.h.
References assert().
Referenced by buildExtract(), buildInstrNoInsert(), llvm::CallLowering::handleAssignments(), llvm::LegalizerHelper::libcall(), llvm::AArch64CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::ARMCallLowering::lowerFormalArguments(), llvm::AArch64CallLowering::lowerReturn(), setInsertPt(), and setMBB().
| MachineInstrBuilder MachineIRBuilder::insertInstr | ( | MachineInstrBuilder | MIB | ) |
Insert an existing instruction at the insertion point.
Definition at line 78 of file MachineIRBuilder.cpp.
References getInsertPt(), getMBB(), and llvm::MachineBasicBlock::insert().
Referenced by buildInstr(), llvm::AArch64CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerReturn(), and llvm::ARMCallLowering::lowerReturn().
| void MachineIRBuilder::recordInsertions | ( | std::function< void(MachineInstr *)> | InsertedInstr | ) |
Control where instructions we create are recorded (typically for visiting again later during legalization).
Definition at line 55 of file MachineIRBuilder.cpp.
Referenced by llvm::LegalizerHelper::legalizeInstr().
Set the debug location to DL for all the next build instructions.
Definition at line 109 of file MachineIRBuilder.h.
| void MachineIRBuilder::setInsertPt | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | II | ||
| ) |
Set the insertion point before the specified position.
Definition at line 47 of file MachineIRBuilder.cpp.
References assert(), getMF(), and llvm::MachineBasicBlock::getParent().
| void MachineIRBuilder::setInstr | ( | MachineInstr & | MI | ) |
Set the insertion point to before MI.
Definition at line 41 of file MachineIRBuilder.cpp.
References assert(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), and setMBB().
Referenced by llvm::LegalizerHelper::fewerElementsVector(), llvm::LegalizerHelper::libcall(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::widenScalar().
| void MachineIRBuilder::setMBB | ( | MachineBasicBlock & | MBB | ) |
Set the insertion point to the end of MBB.
MBB must be contained by getMF(). Definition at line 34 of file MachineIRBuilder.cpp.
References assert(), llvm::MachineBasicBlock::end(), getMF(), and llvm::MachineBasicBlock::getParent().
Referenced by llvm::AArch64CallLowering::lowerFormalArguments(), llvm::IRTranslator::runOnMachineFunction(), llvm::RegBankSelect::runOnMachineFunction(), and setInstr().
| void MachineIRBuilder::setMF | ( | MachineFunction & | MF | ) |
Setters for the insertion point.
Set the MachineFunction where to build instructions.
Definition at line 24 of file MachineIRBuilder.cpp.
References llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), and llvm::MachineFunction::getSubtarget().
Referenced by llvm::LegalizerHelper::LegalizerHelper(), and llvm::IRTranslator::runOnMachineFunction().
| void MachineIRBuilder::stopRecordingInsertions | ( | ) |
Definition at line 60 of file MachineIRBuilder.cpp.
Referenced by llvm::LegalizerHelper::legalizeInstr().
1.8.6