14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
27 class MachineInstrBuilder;
28 class X86RegisterInfo;
74 bool HasMemoryOperand =
false);
104 switch (TargetFlag) {
166 uint16_t RegOp, uint16_t MemOp, uint16_t
Flags);
168 virtual void anchor();
174 bool AllowModify)
const;
197 unsigned &SrcReg,
unsigned &DstReg,
198 unsigned &SubIdx)
const override;
219 unsigned DestReg,
unsigned SubIdx,
232 unsigned LEAOpcode,
bool AllowSP,
unsigned &NewSrc,
233 bool &isKill,
bool &isUndef,
266 unsigned &SrcOpIdx2)
const override;
322 bool AllowModify)
const override;
329 bool AllowModify =
false)
const override;
332 int *BytesRemoved =
nullptr)
const override;
336 int *BytesAdded =
nullptr)
const override;
338 unsigned,
unsigned,
int&,
int&,
int&)
const override;
340 const DebugLoc &DL,
unsigned DstReg,
342 unsigned FalseReg)
const override;
344 const DebugLoc &DL,
unsigned DestReg,
unsigned SrcReg,
345 bool KillSrc)
const override;
403 bool UnfoldLoad,
bool UnfoldStore,
416 bool UnfoldLoad,
bool UnfoldStore,
417 unsigned *LoadRegIndex =
nullptr)
const override;
425 int64_t &Offset2)
const override;
436 int64_t Offset1, int64_t Offset2,
437 unsigned NumLoads)
const override;
468 std::pair<uint16_t, uint16_t>
485 unsigned Size,
unsigned Alignment,
486 bool AllowCommute)
const;
494 unsigned UseIdx)
const override;
514 unsigned &SrcReg2,
int &CmpMask,
515 int &CmpValue)
const override;
521 unsigned SrcReg2,
int CmpMask,
int CmpValue,
533 unsigned &FoldAsLoadDefReg,
536 std::pair<unsigned, unsigned>
557 unsigned CommuteOpIdx1,
558 unsigned CommuteOpIdx2)
const override;
561 MachineInstr *convertToThreeAddressWithLEA(
unsigned MIOpc,
572 unsigned Size,
unsigned Align)
const;
596 unsigned &SrcOpIdx2)
const;
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned GetCondBranchFromCond(CondCode CC)
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
static bool isScale(const MachineOperand &MO)
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool shouldScheduleAdjacent(const MachineInstr &First, const MachineInstr &Second) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
CondCode getCondFromCMovOpc(unsigned Opc)
Return condition code of a CMov opcode.
bool isHighLatencyDef(int opc) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register rea...
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
Represents a predicate at the MachineFunction level.
AddrSegmentReg - The operand # of the segment in the memory operand.
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
bool findFMA3CommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns true if the routine could find two commutable operands in the given FMA instruction MI...
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
A description of a memory reference used in the backend.
struct fuzzer::@269 Flags
Provide an instruction scheduling machine model to CodeGen passes.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use...
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
Reg
All possible values of the reg field in the ModR/M byte.
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction...
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
static bool isMem(const MachineInstr &MI, unsigned Op)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp, LiveVariables *LV) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Instances of this class represent a single low-level machine instruction.
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
AddrNumOperands - Total number of operands in a memory reference.
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction. ...
unsigned const MachineRegisterInfo * MRI
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
X86InstrInfo(X86Subtarget &STI)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool useMachineCombiner() const override
This class is used to group {132, 213, 231} forms of FMA opcodes together.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand=false)
Return a set opcode for the given condition and whether it has a memory operand.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS c...
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
Iterator for intrusive lists based on ilist_node.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
MachineOperand class - Representation of each machine instruction operand.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Represents one node in the SelectionDAG.
void getNoopForMachoTarget(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given condition, register size in bytes, and operand type...
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
Representation of each machine instruction.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool isTailCall(const MachineInstr &Inst) const override
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override