LLVM  4.0.0
ARMSubtarget.h
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1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the ARM specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
16 
17 
18 #include "ARMFrameLowering.h"
19 #include "ARMISelLowering.h"
20 #include "ARMInstrInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
24 #include "Thumb1FrameLowering.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/Triple.h"
29 #include "llvm/IR/DataLayout.h"
32 #include <string>
33 
34 #define GET_SUBTARGETINFO_HEADER
35 #include "ARMGenSubtargetInfo.inc"
36 
37 namespace llvm {
38 class GlobalValue;
39 class StringRef;
40 class TargetOptions;
41 class ARMBaseTargetMachine;
42 
44 protected:
50  };
53  };
54  enum ARMArchEnum {
59  };
60 
61 public:
62  /// What kind of timing do load multiple/store multiple instructions have.
64  /// Can load/store 2 registers/cycle.
66  /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
67  /// is not 64-bit aligned.
69  /// Can load/store 1 register/cycle.
71  /// Can load/store 1 register/cycle, but needs an extra cycle for address
72  /// computation and potentially also for register writeback.
74  };
75 
76 protected:
77  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
79 
80  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
82 
83  /// ARMArch - ARM architecture
85 
86  /// HasV4TOps, HasV5TOps, HasV5TEOps,
87  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
88  /// Specify whether target support specific ARM ISA variants.
89  bool HasV4TOps = false;
90  bool HasV5TOps = false;
91  bool HasV5TEOps = false;
92  bool HasV6Ops = false;
93  bool HasV6MOps = false;
94  bool HasV6KOps = false;
95  bool HasV6T2Ops = false;
96  bool HasV7Ops = false;
97  bool HasV8Ops = false;
98  bool HasV8_1aOps = false;
99  bool HasV8_2aOps = false;
100  bool HasV8MBaselineOps = false;
101  bool HasV8MMainlineOps = false;
102 
103  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
104  /// floating point ISAs are supported.
105  bool HasVFPv2 = false;
106  bool HasVFPv3 = false;
107  bool HasVFPv4 = false;
108  bool HasFPARMv8 = false;
109  bool HasNEON = false;
110 
111  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
112  /// specified. Use the method useNEONForSinglePrecisionFP() to
113  /// determine if NEON should actually be used.
115 
116  /// UseMulOps - True if non-microcoded fused integer multiply-add and
117  /// multiply-subtract instructions should be used.
118  bool UseMulOps = false;
119 
120  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
121  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
122  bool SlowFPVMLx = false;
123 
124  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
125  /// forwarding to allow mul + mla being issued back to back.
126  bool HasVMLxForwarding = false;
127 
128  /// SlowFPBrcc - True if floating point compare + branch is slow.
129  bool SlowFPBrcc = false;
130 
131  /// InThumbMode - True if compiling for Thumb, false for ARM.
132  bool InThumbMode = false;
133 
134  /// UseSoftFloat - True if we're using software floating point features.
135  bool UseSoftFloat = false;
136 
137  /// HasThumb2 - True if Thumb2 instructions are supported.
138  bool HasThumb2 = false;
139 
140  /// NoARM - True if subtarget does not support ARM mode execution.
141  bool NoARM = false;
142 
143  /// ReserveR9 - True if R9 is not available as a general purpose register.
144  bool ReserveR9 = false;
145 
146  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
147  /// 32-bit imms (including global addresses).
148  bool NoMovt = false;
149 
150  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
151  /// must be able to synthesize call stubs for interworking between ARM and
152  /// Thumb.
153  bool SupportsTailCall = false;
154 
155  /// HasFP16 - True if subtarget supports half-precision FP conversions
156  bool HasFP16 = false;
157 
158  /// HasFullFP16 - True if subtarget supports half-precision FP operations
159  bool HasFullFP16 = false;
160 
161  /// HasD16 - True if subtarget is limited to 16 double precision
162  /// FP registers for VFPv3.
163  bool HasD16 = false;
164 
165  /// HasHardwareDivide - True if subtarget supports [su]div
166  bool HasHardwareDivide = false;
167 
168  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
170 
171  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
172  /// instructions.
173  bool HasT2ExtractPack = false;
174 
175  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
176  /// instructions.
177  bool HasDataBarrier = false;
178 
179  /// HasV7Clrex - True if the subtarget supports CLREX instructions
180  bool HasV7Clrex = false;
181 
182  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
183  /// instructions
184  bool HasAcquireRelease = false;
185 
186  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
187  /// over 16-bit ones.
188  bool Pref32BitThumb = false;
189 
190  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
191  /// that partially update CPSR and add false dependency on the previous
192  /// CPSR setting instruction.
194 
195  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
196  /// movs with shifter operand (i.e. asr, lsl, lsr).
198 
199  /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
200  /// avoid issue "normal" call instructions to callees which do not return.
201  bool HasRetAddrStack = false;
202 
203  /// HasMPExtension - True if the subtarget supports Multiprocessing
204  /// extension (ARMv7 only).
205  bool HasMPExtension = false;
206 
207  /// HasVirtualization - True if the subtarget supports the Virtualization
208  /// extension.
209  bool HasVirtualization = false;
210 
211  /// FPOnlySP - If true, the floating point unit only supports single
212  /// precision.
213  bool FPOnlySP = false;
214 
215  /// If true, the processor supports the Performance Monitor Extensions. These
216  /// include a generic cycle-counter as well as more fine-grained (often
217  /// implementation-specific) events.
218  bool HasPerfMon = false;
219 
220  /// HasTrustZone - if true, processor supports TrustZone security extensions
221  bool HasTrustZone = false;
222 
223  /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
224  bool Has8MSecExt = false;
225 
226  /// HasCrypto - if true, processor supports Cryptography extensions
227  bool HasCrypto = false;
228 
229  /// HasCRC - if true, processor supports CRC instructions
230  bool HasCRC = false;
231 
232  /// HasRAS - if true, the processor supports RAS extensions
233  bool HasRAS = false;
234 
235  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
236  /// particularly effective at zeroing a VFP register.
237  bool HasZeroCycleZeroing = false;
238 
239  /// HasFPAO - if true, processor does positive address offset computation faster
240  bool HasFPAO = false;
241 
242  /// If true, if conversion may decide to leave some instructions unpredicated.
244 
245  /// If true, VMOV will be favored over VGETLNi32.
246  bool HasSlowVGETLNi32 = false;
247 
248  /// If true, VMOV will be favored over VDUP.
249  bool HasSlowVDUP32 = false;
250 
251  /// If true, VMOVSR will be favored over VMOVDRR.
252  bool PreferVMOVSR = false;
253 
254  /// If true, ISHST barriers will be used for Release semantics.
255  bool PreferISHST = false;
256 
257  /// If true, a VLDM/VSTM starting with an odd register number is considered to
258  /// take more microops than single VLDRS/VSTRS.
259  bool SlowOddRegister = false;
260 
261  /// If true, loading into a D subregister will be penalized.
262  bool SlowLoadDSubregister = false;
263 
264  /// If true, the AGU and NEON/FPU units are multiplexed.
265  bool HasMuxedUnits = false;
266 
267  /// If true, VMOVS will never be widened to VMOVD
268  bool DontWidenVMOVS = false;
269 
270  /// If true, run the MLx expansion pass.
271  bool ExpandMLx = false;
272 
273  /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
274  bool HasVMLxHazards = false;
275 
276  /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
277  bool UseNEONForFPMovs = false;
278 
279  /// If true, VLDn instructions take an extra cycle for unaligned accesses.
280  bool CheckVLDnAlign = false;
281 
282  /// If true, VFP instructions are not pipelined.
283  bool NonpipelinedVFP = false;
284 
285  /// StrictAlign - If true, the subtarget disallows unaligned memory
286  /// accesses for some types. For details, see
287  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
288  bool StrictAlign = false;
289 
290  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
291  /// blocks to conform to ARMv8 rule.
292  bool RestrictIT = false;
293 
294  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
295  /// and such) instructions.
296  bool HasDSP = false;
297 
298  /// NaCl TRAP instruction is generated instead of the regular TRAP.
299  bool UseNaClTrap = false;
300 
301  /// Generate calls via indirect call instructions.
302  bool GenLongCalls = false;
303 
304  /// Generate code that does not contain data access to code sections.
305  bool GenExecuteOnly = false;
306 
307  /// Target machine allowed unsafe FP math (such as use of NEON fp)
308  bool UnsafeFPMath = false;
309 
310  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
311  bool UseSjLjEH = false;
312 
313  /// stackAlignment - The minimum alignment known to hold of the stack frame on
314  /// entry to the function and which must be maintained by every function.
315  unsigned stackAlignment = 4;
316 
317  /// CPUString - String name of used CPU.
318  std::string CPUString;
319 
320  unsigned MaxInterleaveFactor = 1;
321 
322  /// Clearance before partial register updates (in number of instructions)
324 
325  /// What kind of timing do load multiple/store multiple have (double issue,
326  /// single issue etc).
328 
329  /// The adjustment that we need to apply to get the operand latency from the
330  /// operand cycle returned by the itinerary data for pre-ISel operands.
332 
333  /// IsLittle - The target is Little Endian
334  bool IsLittle;
335 
336  /// TargetTriple - What processor and OS we're targeting.
338 
339  /// SchedModel - Processor specific instruction costs.
341 
342  /// Selected instruction itineraries (one entry per itinerary class.)
344 
345  /// Options passed via command line that could influence the target
347 
349 
350 public:
351  /// This constructor initializes the data members to match that
352  /// of the specified triple.
353  ///
354  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
355  const ARMBaseTargetMachine &TM, bool IsLittle);
356 
357  /// This object will take onwership of \p GISelAccessor.
358  void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); }
359 
360  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
361  /// that still makes it profitable to inline the call.
362  unsigned getMaxInlineSizeThreshold() const {
363  return 64;
364  }
365  /// ParseSubtargetFeatures - Parses features string setting specified
366  /// subtarget options. Definition of function is auto generated by tblgen.
368 
369  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
370  /// so that we can use initializer lists for subtarget initialization.
372 
373  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
374  return &TSInfo;
375  }
376  const ARMBaseInstrInfo *getInstrInfo() const override {
377  return InstrInfo.get();
378  }
379  const ARMTargetLowering *getTargetLowering() const override {
380  return &TLInfo;
381  }
382  const ARMFrameLowering *getFrameLowering() const override {
383  return FrameLowering.get();
384  }
385  const ARMBaseRegisterInfo *getRegisterInfo() const override {
386  return &InstrInfo->getRegisterInfo();
387  }
388 
389  const CallLowering *getCallLowering() const override;
390  const InstructionSelector *getInstructionSelector() const override;
391  const LegalizerInfo *getLegalizerInfo() const override;
392  const RegisterBankInfo *getRegBankInfo() const override;
393 
394 private:
395  ARMSelectionDAGInfo TSInfo;
396  // Either Thumb1FrameLowering or ARMFrameLowering.
397  std::unique_ptr<ARMFrameLowering> FrameLowering;
398  // Either Thumb1InstrInfo or Thumb2InstrInfo.
399  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
400  ARMTargetLowering TLInfo;
401 
402  /// Gather the accessor points to GlobalISel-related APIs.
403  /// This is used to avoid ifndefs spreading around while GISel is
404  /// an optional library.
405  std::unique_ptr<GISelAccessor> GISel;
406 
407  void initializeEnvironment();
408  void initSubtargetFeatures(StringRef CPU, StringRef FS);
409  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
410 
411 public:
412  void computeIssueWidth();
413 
414  bool hasV4TOps() const { return HasV4TOps; }
415  bool hasV5TOps() const { return HasV5TOps; }
416  bool hasV5TEOps() const { return HasV5TEOps; }
417  bool hasV6Ops() const { return HasV6Ops; }
418  bool hasV6MOps() const { return HasV6MOps; }
419  bool hasV6KOps() const { return HasV6KOps; }
420  bool hasV6T2Ops() const { return HasV6T2Ops; }
421  bool hasV7Ops() const { return HasV7Ops; }
422  bool hasV8Ops() const { return HasV8Ops; }
423  bool hasV8_1aOps() const { return HasV8_1aOps; }
424  bool hasV8_2aOps() const { return HasV8_2aOps; }
425  bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
426  bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
427 
428  /// @{
429  /// These functions are obsolete, please consider adding subtarget features
430  /// or properties instead of calling them.
431  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
432  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
433  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
434  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
435  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
436  bool isSwift() const { return ARMProcFamily == Swift; }
437  bool isCortexM3() const { return ARMProcFamily == CortexM3; }
438  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
439  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
440  bool isKrait() const { return ARMProcFamily == Krait; }
441  /// @}
442 
443  bool hasARMOps() const { return !NoARM; }
444 
445  bool hasVFP2() const { return HasVFPv2; }
446  bool hasVFP3() const { return HasVFPv3; }
447  bool hasVFP4() const { return HasVFPv4; }
448  bool hasFPARMv8() const { return HasFPARMv8; }
449  bool hasNEON() const { return HasNEON; }
450  bool hasCrypto() const { return HasCrypto; }
451  bool hasCRC() const { return HasCRC; }
452  bool hasRAS() const { return HasRAS; }
453  bool hasVirtualization() const { return HasVirtualization; }
456  }
457 
458  bool hasDivide() const { return HasHardwareDivide; }
460  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
461  bool hasDataBarrier() const { return HasDataBarrier; }
462  bool hasV7Clrex() const { return HasV7Clrex; }
463  bool hasAcquireRelease() const { return HasAcquireRelease; }
464  bool hasAnyDataBarrier() const {
465  return HasDataBarrier || (hasV6Ops() && !isThumb());
466  }
467  bool useMulOps() const { return UseMulOps; }
468  bool useFPVMLx() const { return !SlowFPVMLx; }
469  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
470  bool isFPBrccSlow() const { return SlowFPBrcc; }
471  bool isFPOnlySP() const { return FPOnlySP; }
472  bool hasPerfMon() const { return HasPerfMon; }
473  bool hasTrustZone() const { return HasTrustZone; }
474  bool has8MSecExt() const { return Has8MSecExt; }
475  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
476  bool hasFPAO() const { return HasFPAO; }
478  bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
479  bool hasSlowVDUP32() const { return HasSlowVDUP32; }
480  bool preferVMOVSR() const { return PreferVMOVSR; }
481  bool preferISHSTBarriers() const { return PreferISHST; }
482  bool expandMLx() const { return ExpandMLx; }
483  bool hasVMLxHazards() const { return HasVMLxHazards; }
484  bool hasSlowOddRegister() const { return SlowOddRegister; }
486  bool hasMuxedUnits() const { return HasMuxedUnits; }
487  bool dontWidenVMOVS() const { return DontWidenVMOVS; }
488  bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
489  bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
490  bool nonpipelinedVFP() const { return NonpipelinedVFP; }
491  bool prefers32BitThumb() const { return Pref32BitThumb; }
494  bool hasRetAddrStack() const { return HasRetAddrStack; }
495  bool hasMPExtension() const { return HasMPExtension; }
496  bool hasDSP() const { return HasDSP; }
497  bool useNaClTrap() const { return UseNaClTrap; }
498  bool useSjLjEH() const { return UseSjLjEH; }
499  bool genLongCalls() const { return GenLongCalls; }
500  bool genExecuteOnly() const { return GenExecuteOnly; }
501 
502  bool hasFP16() const { return HasFP16; }
503  bool hasD16() const { return HasD16; }
504  bool hasFullFP16() const { return HasFullFP16; }
505 
506  const Triple &getTargetTriple() const { return TargetTriple; }
507 
508  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
509  bool isTargetIOS() const { return TargetTriple.isiOS(); }
510  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
511  bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
512  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
513  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
514  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
515  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
516 
517  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
518  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
519  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
520 
521  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
522  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
523  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
524  // even for GNUEABI, so we can make a distinction here and still conform to
525  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
526  // FIXME: The Darwin exception is temporary, while we move users to
527  // "*-*-*-macho" triples as quickly as possible.
528  bool isTargetAEABI() const {
532  }
533  bool isTargetGNUAEABI() const {
537  }
538  bool isTargetMuslAEABI() const {
542  }
543 
544  // ARM Targets that support EHABI exception handling standard
545  // Darwin uses SjLj. Other targets might need more checks.
546  bool isTargetEHABICompatible() const {
553  isTargetAndroid()) &&
555  }
556 
557  bool isTargetHardFloat() const {
558  // FIXME: this is invalid for WindowsCE
563  }
564  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
565 
566  virtual bool isXRaySupported() const override;
567 
568  bool isAPCS_ABI() const;
569  bool isAAPCS_ABI() const;
570  bool isAAPCS16_ABI() const;
571 
572  bool isROPI() const;
573  bool isRWPI() const;
574 
575  bool useSoftFloat() const { return UseSoftFloat; }
576  bool isThumb() const { return InThumbMode; }
577  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
578  bool isThumb2() const { return InThumbMode && HasThumb2; }
579  bool hasThumb2() const { return HasThumb2; }
580  bool isMClass() const { return ARMProcClass == MClass; }
581  bool isRClass() const { return ARMProcClass == RClass; }
582  bool isAClass() const { return ARMProcClass == AClass; }
583 
584  bool isR9Reserved() const {
585  return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
586  }
587 
588  bool useR7AsFramePointer() const {
589  return isTargetDarwin() || (!isTargetWindows() && isThumb());
590  }
591  /// Returns true if the frame setup is split into two separate pushes (first
592  /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
593  /// to lr. This is always required on Thumb1-only targets, as the push and
594  /// pop instructions can't access the high registers.
595  bool splitFramePushPop(const MachineFunction &MF) const {
596  return (useR7AsFramePointer() &&
598  isThumb1Only();
599  }
600 
601  bool useStride4VFPs(const MachineFunction &MF) const;
602 
603  bool useMovt(const MachineFunction &MF) const;
604 
605  bool supportsTailCall() const { return SupportsTailCall; }
606 
607  bool allowsUnalignedMem() const { return !StrictAlign; }
608 
609  bool restrictIT() const { return RestrictIT; }
610 
611  const std::string & getCPUString() const { return CPUString; }
612 
613  bool isLittle() const { return IsLittle; }
614 
615  unsigned getMispredictionPenalty() const;
616 
617  /// This function returns true if the target has sincos() routine in its
618  /// compiler runtime or math libraries.
619  bool hasSinCos() const;
620 
621  /// Returns true if machine scheduler should be enabled.
622  bool enableMachineScheduler() const override;
623 
624  /// True for some subtargets at > -O0.
625  bool enablePostRAScheduler() const override;
626 
627  // enableAtomicExpand- True if we need to expand our atomics.
628  bool enableAtomicExpand() const override;
629 
630  /// getInstrItins - Return the instruction itineraries based on subtarget
631  /// selection.
632  const InstrItineraryData *getInstrItineraryData() const override {
633  return &InstrItins;
634  }
635 
636  /// getStackAlignment - Returns the minimum alignment known to hold of the
637  /// stack frame on entry to the function and which must be maintained by every
638  /// function for this subtarget.
639  unsigned getStackAlignment() const { return stackAlignment; }
640 
641  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
642 
644 
646  return LdStMultipleTiming;
647  }
648 
651  }
652 
653  /// True if the GV will be accessed via an indirect symbol.
654  bool isGVIndirectSymbol(const GlobalValue *GV) const;
655 
656  /// True if fast-isel is used.
657  bool useFastISel() const;
658 };
659 } // End llvm namespace
660 
661 #endif // ARMSUBTARGET_H
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
Definition: ARMSubtarget.h:148
bool hasV4TOps() const
Definition: ARMSubtarget.h:414
bool avoidCPSRPartialUpdate() const
Definition: ARMSubtarget.h:492
bool useSjLjEH() const
Definition: ARMSubtarget.h:498
bool UseNEONForFPMovs
If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
Definition: ARMSubtarget.h:277
The goal of this helper class is to gather the accessor to all the APIs related to GlobalISel...
Definition: GISelAccessor.h:29
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:315
bool ExpandMLx
If true, run the MLx expansion pass.
Definition: ARMSubtarget.h:271
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:337
bool isFPOnlySP() const
Definition: ARMSubtarget.h:471
bool avoidMOVsShifterOperand() const
Definition: ARMSubtarget.h:493
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:575
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:588
unsigned getMispredictionPenalty() const
bool hasV8_1aOps() const
Definition: ARMSubtarget.h:423
bool isAAPCS16_ABI() const
const std::string & getCPUString() const
Definition: ARMSubtarget.h:611
bool hasMuxedUnits() const
Definition: ARMSubtarget.h:486
bool SlowFPVMLx
SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates whether the FP VML[AS] instruct...
Definition: ARMSubtarget.h:122
bool SlowLoadDSubregister
If true, loading into a D subregister will be penalized.
Definition: ARMSubtarget.h:262
bool isCortexA8() const
Definition: ARMSubtarget.h:433
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:373
bool hasFPAO() const
Definition: ARMSubtarget.h:476
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:643
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:546
bool HasRetAddrStack
HasRetAddrStack - Some processors perform return stack prediction.
Definition: ARMSubtarget.h:201
bool isAClass() const
Definition: ARMSubtarget.h:582
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:379
bool HasFullFP16
HasFullFP16 - True if subtarget supports half-precision FP operations.
Definition: ARMSubtarget.h:159
bool hasT2ExtractPack() const
Definition: ARMSubtarget.h:460
bool HasSlowVDUP32
If true, VMOV will be favored over VDUP.
Definition: ARMSubtarget.h:249
bool useFastISel() const
True if fast-isel is used.
bool HasVFPv2
HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what floating point ISAs are supported...
Definition: ARMSubtarget.h:105
bool has8MSecExt() const
Definition: ARMSubtarget.h:474
bool hasV5TEOps() const
Definition: ARMSubtarget.h:416
bool isROPI() const
bool hasV6Ops() const
Definition: ARMSubtarget.h:417
bool HasHardwareDivideInARM
HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode.
Definition: ARMSubtarget.h:169
bool checkVLDnAccessAlignment() const
Definition: ARMSubtarget.h:489
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:420
const LegalizerInfo * getLegalizerInfo() const override
bool isThumb1Only() const
Definition: ARMSubtarget.h:577
bool expandMLx() const
Definition: ARMSubtarget.h:482
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:348
bool hasDivide() const
Definition: ARMSubtarget.h:458
bool isCortexR5() const
Definition: ARMSubtarget.h:439
bool GenLongCalls
Generate calls via indirect call instructions.
Definition: ARMSubtarget.h:302
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:153
bool restrictIT() const
Definition: ARMSubtarget.h:609
bool HasMuxedUnits
If true, the AGU and NEON/FPU units are multiplexed.
Definition: ARMSubtarget.h:265
bool HasSlowVGETLNi32
If true, VMOV will be favored over VGETLNi32.
Definition: ARMSubtarget.h:246
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:593
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:540
bool hasPerfMon() const
Definition: ARMSubtarget.h:472
bool hasV6MOps() const
Definition: ARMSubtarget.h:418
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:118
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:376
bool isCortexA9() const
Definition: ARMSubtarget.h:434
bool isR9Reserved() const
Definition: ARMSubtarget.h:584
bool hasV8_2aOps() const
Definition: ARMSubtarget.h:424
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:70
bool Has8MSecExt
Has8MSecExt - if true, processor supports ARMv8-M Security Extensions.
Definition: ARMSubtarget.h:224
bool isTargetAEABI() const
Definition: ARMSubtarget.h:528
Holds all the information related to register banks.
bool useSoftFloat() const
Definition: ARMSubtarget.h:575
bool hasV8Ops() const
Definition: ARMSubtarget.h:422
bool HasRAS
HasRAS - if true, the processor supports RAS extensions.
Definition: ARMSubtarget.h:233
bool hasVFP3() const
Definition: ARMSubtarget.h:446
bool SlowOddRegister
If true, a VLDM/VSTM starting with an odd register number is considered to take more microops than si...
Definition: ARMSubtarget.h:259
bool useNEONForFPMovs() const
Definition: ARMSubtarget.h:488
bool hasThumb2() const
Definition: ARMSubtarget.h:579
bool isTargetELF() const
Definition: ARMSubtarget.h:518
bool isTargetDarwin() const
Definition: ARMSubtarget.h:508
bool HasZeroCycleZeroing
If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are particularly effective at zeroi...
Definition: ARMSubtarget.h:237
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
bool isRClass() const
Definition: ARMSubtarget.h:581
bool StrictAlign
StrictAlign - If true, the subtarget disallows unaligned memory accesses for some types...
Definition: ARMSubtarget.h:288
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:426
bool useStride4VFPs(const MachineFunction &MF) const
bool HasThumb2
HasThumb2 - True if Thumb2 instructions are supported.
Definition: ARMSubtarget.h:138
bool UnsafeFPMath
Target machine allowed unsafe FP math (such as use of NEON fp)
Definition: ARMSubtarget.h:308
bool isLittle() const
Definition: ARMSubtarget.h:613
bool hasMPExtension() const
Definition: ARMSubtarget.h:495
void setGISelAccessor(GISelAccessor &GISel)
This object will take onwership of GISelAccessor.
Definition: ARMSubtarget.h:358
bool isFPBrccSlow() const
Definition: ARMSubtarget.h:470
bool isThumb() const
Definition: ARMSubtarget.h:576
bool DontWidenVMOVS
If true, VMOVS will never be widened to VMOVD.
Definition: ARMSubtarget.h:268
bool PreferVMOVSR
If true, VMOVSR will be favored over VMOVDRR.
Definition: ARMSubtarget.h:252
bool hasV7Ops() const
Definition: ARMSubtarget.h:421
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:550
bool Pref32BitThumb
Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions over 16-bit ones...
Definition: ARMSubtarget.h:188
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:334
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:506
bool isTargetCOFF() const
Definition: ARMSubtarget.h:517
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:63
bool enableAtomicExpand() const override
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:545
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
Definition: ARMSubtarget.h:68
virtual bool isXRaySupported() const override
bool isTargetMachO() const
Definition: ARMSubtarget.h:519
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
Definition: ARMSubtarget.h:141
bool hasFPARMv8() const
Definition: ARMSubtarget.h:448
bool prefers32BitThumb() const
Definition: ARMSubtarget.h:491
bool hasSlowVDUP32() const
Definition: ARMSubtarget.h:479
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:331
bool hasCrypto() const
Definition: ARMSubtarget.h:450
bool hasNEON() const
Definition: ARMSubtarget.h:449
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:464
Itinerary data supplied by a subtarget to be used by a target.
bool hasVFP4() const
Definition: ARMSubtarget.h:447
bool HasT2ExtractPack
HasT2ExtractPack - True if subtarget supports thumb2 extract/pack instructions.
Definition: ARMSubtarget.h:173
bool useMulOps() const
Definition: ARMSubtarget.h:467
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:510
bool dontWidenVMOVS() const
Definition: ARMSubtarget.h:487
bool hasARMOps() const
Definition: ARMSubtarget.h:443
bool HasPerfMon
If true, the processor supports the Performance Monitor Extensions.
Definition: ARMSubtarget.h:218
bool isOSNetBSD() const
Definition: Triple.h:459
bool hasV7Clrex() const
Definition: ARMSubtarget.h:462
bool isTargetIOS() const
Definition: ARMSubtarget.h:509
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:514
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:436
bool AvoidMOVsShifterOperand
AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting movs with shifter operand ...
Definition: ARMSubtarget.h:197
bool HasCRC
HasCRC - if true, processor supports CRC instructions.
Definition: ARMSubtarget.h:230
bool HasDSP
HasDSP - If true, the subtarget supports the DSP (saturating arith and such) instructions.
Definition: ARMSubtarget.h:296
bool HasV7Clrex
HasV7Clrex - True if the subtarget supports CLREX instructions.
Definition: ARMSubtarget.h:180
bool HasVirtualization
HasVirtualization - True if the subtarget supports the Virtualization extension.
Definition: ARMSubtarget.h:209
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:78
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
Definition: ARMSubtarget.h:292
bool isTargetHardFloat() const
Definition: ARMSubtarget.h:557
bool supportsTailCall() const
Definition: ARMSubtarget.h:605
bool isMClass() const
Definition: ARMSubtarget.h:580
bool IsProfitableToUnpredicate
If true, if conversion may decide to leave some instructions unpredicated.
Definition: ARMSubtarget.h:243
bool hasVirtualization() const
Definition: ARMSubtarget.h:453
bool isCortexA5() const
Definition: ARMSubtarget.h:431
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11)...
Definition: ARMSubtarget.h:595
bool HasV4TOps
HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - Specify whether target support specific ARM ISA variants.
Definition: ARMSubtarget.h:89
bool HasVMLxForwarding
HasVMLxForwarding - If true, NEON has special multiplier accumulator forwarding to allow mul + mla be...
Definition: ARMSubtarget.h:126
bool HasVMLxHazards
If true, VFP/NEON VMLA/VMLS have special RAW hazards.
Definition: ARMSubtarget.h:274
bool isCortexM3() const
Definition: ARMSubtarget.h:437
bool HasCrypto
HasCrypto - if true, processor supports Cryptography extensions.
Definition: ARMSubtarget.h:227
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:446
bool isKrait() const
Definition: ARMSubtarget.h:440
bool isCortexA15() const
Definition: ARMSubtarget.h:435
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:511
bool hasVMLxForwarding() const
Definition: ARMSubtarget.h:469
bool hasZeroCycleZeroing() const
Definition: ARMSubtarget.h:475
bool HasMPExtension
HasMPExtension - True if the subtarget supports Multiprocessing extension (ARMv7 only).
Definition: ARMSubtarget.h:205
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:454
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:382
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:425
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:570
unsigned getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:639
const CallLowering * getCallLowering() const override
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
bool NonpipelinedVFP
If true, VFP instructions are not pipelined.
Definition: ARMSubtarget.h:283
bool hasRetAddrStack() const
Definition: ARMSubtarget.h:494
bool hasVMLxHazards() const
Definition: ARMSubtarget.h:483
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:645
bool genExecuteOnly() const
Definition: ARMSubtarget.h:500
bool isRWPI() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool HasFP16
HasFP16 - True if subtarget supports half-precision FP conversions.
Definition: ARMSubtarget.h:156
bool HasTrustZone
HasTrustZone - if true, processor supports TrustZone security extensions.
Definition: ARMSubtarget.h:221
bool hasSlowOddRegister() const
Definition: ARMSubtarget.h:484
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:455
bool genLongCalls() const
Definition: ARMSubtarget.h:499
bool InThumbMode
InThumbMode - True if compiling for Thumb, false for ARM.
Definition: ARMSubtarget.h:132
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool hasV6KOps() const
Definition: ARMSubtarget.h:419
bool isTargetNaCl() const
Definition: ARMSubtarget.h:513
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:485
bool preferVMOVSR() const
Definition: ARMSubtarget.h:480
bool isSwift() const
Definition: ARMSubtarget.h:436
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:632
const InstructionSelector * getInstructionSelector() const override
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:84
bool FPOnlySP
FPOnlySP - If true, the floating point unit only supports single precision.
Definition: ARMSubtarget.h:213
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:81
bool hasVFP2() const
Definition: ARMSubtarget.h:445
bool isTargetAndroid() const
Definition: ARMSubtarget.h:564
bool GenExecuteOnly
Generate code that does not contain data access to code sections.
Definition: ARMSubtarget.h:305
bool hasAcquireRelease() const
Definition: ARMSubtarget.h:463
bool UseNaClTrap
NaCl TRAP instruction is generated instead of the regular TRAP.
Definition: ARMSubtarget.h:299
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:362
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:340
bool hasSlowVGETLNi32() const
Definition: ARMSubtarget.h:478
bool PreferISHST
If true, ISHST barriers will be used for Release semantics.
Definition: ARMSubtarget.h:255
bool isCortexA7() const
Definition: ARMSubtarget.h:432
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:346
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool UseSoftFloat
UseSoftFloat - True if we're using software floating point features.
Definition: ARMSubtarget.h:135
bool useNaClTrap() const
Definition: ARMSubtarget.h:497
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:533
bool isWatchABI() const
Definition: Triple.h:450
bool nonpipelinedVFP() const
Definition: ARMSubtarget.h:490
Provides the logic to select generic machine instructions.
bool isAPCS_ABI() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
bool isThumb2() const
Definition: ARMSubtarget.h:578
bool isAAPCS_ABI() const
bool hasV5TOps() const
Definition: ARMSubtarget.h:415
bool isTargetLinux() const
Definition: ARMSubtarget.h:512
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
Definition: ARMSubtarget.h:144
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:641
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:343
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
Definition: ARMSubtarget.h:114
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:385
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:607
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isProfitableToUnpredicate() const
Definition: ARMSubtarget.h:477
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:323
bool hasCRC() const
Definition: ARMSubtarget.h:451
bool hasDSP() const
Definition: ARMSubtarget.h:496
bool useMovt(const MachineFunction &MF) const
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:649
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:288
bool hasTrustZone() const
Definition: ARMSubtarget.h:473
bool SlowFPBrcc
SlowFPBrcc - True if floating point compare + branch is slow.
Definition: ARMSubtarget.h:129
bool isLikeA9() const
Definition: ARMSubtarget.h:438
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:538
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
Definition: ARMSubtarget.h:327
bool HasD16
HasD16 - True if subtarget is limited to 16 double precision FP registers for VFPv3.
Definition: ARMSubtarget.h:163
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
bool hasRAS() const
Definition: ARMSubtarget.h:452
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:73
bool AvoidCPSRPartialUpdate
AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions that partially update CPSR a...
Definition: ARMSubtarget.h:193
bool hasFP16() const
Definition: ARMSubtarget.h:502
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:65
bool preferISHSTBarriers() const
Definition: ARMSubtarget.h:481
bool hasDataBarrier() const
Definition: ARMSubtarget.h:461
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:318
bool useFPVMLx() const
Definition: ARMSubtarget.h:468
bool hasDivideInARMMode() const
Definition: ARMSubtarget.h:459
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
bool HasAcquireRelease
HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
Definition: ARMSubtarget.h:184
bool hasD16() const
Definition: ARMSubtarget.h:503
bool HasFPAO
HasFPAO - if true, processor does positive address offset computation faster.
Definition: ARMSubtarget.h:240
bool HasDataBarrier
HasDataBarrier - True if the subtarget supports DMB / DSB data barrier instructions.
Definition: ARMSubtarget.h:177
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:136
bool hasFullFP16() const
Definition: ARMSubtarget.h:504
bool isTargetWindows() const
Definition: ARMSubtarget.h:515
bool HasHardwareDivide
HasHardwareDivide - True if subtarget supports [su]div.
Definition: ARMSubtarget.h:166
const RegisterBankInfo * getRegBankInfo() const override
bool CheckVLDnAlign
If true, VLDn instructions take an extra cycle for unaligned accesses.
Definition: ARMSubtarget.h:280
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:311
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:320