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LLVM
4.0.0
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#include "X86InstrInfo.h"#include "X86.h"#include "X86InstrBuilder.h"#include "X86MachineFunctionInfo.h"#include "X86Subtarget.h"#include "X86TargetMachine.h"#include "llvm/ADT/STLExtras.h"#include "llvm/CodeGen/LivePhysRegs.h"#include "llvm/CodeGen/LiveVariables.h"#include "llvm/CodeGen/MachineConstantPool.h"#include "llvm/CodeGen/MachineDominators.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineModuleInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/StackMaps.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/LLVMContext.h"#include "llvm/MC/MCAsmInfo.h"#include "llvm/MC/MCExpr.h"#include "llvm/MC/MCInst.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetOptions.h"#include "X86GenInstrInfo.inc"Go to the source code of this file.
Classes | |
| struct | X86MemoryFoldTableEntry |
Macros | |
| #define | DEBUG_TYPE "x86-instr-info" |
| #define | GET_INSTRINFO_CTOR_DTOR |
| #define | VPERM_CASES(Suffix) |
| #define | VPERM_CASES_BROADCAST(Suffix) |
| #define | VPERM_CASES(Orig, New) |
| #define | VPERM_CASES_BROADCAST(Orig, New) |
Enumerations | |
| enum | { TB_INDEX_0 = 0, TB_INDEX_1 = 1, TB_INDEX_2 = 2, TB_INDEX_3 = 3, TB_INDEX_4 = 4, TB_INDEX_MASK = 0xf, TB_NO_REVERSE = 1 << 4, TB_NO_FORWARD = 1 << 5, TB_FOLDED_LOAD = 1 << 6, TB_FOLDED_STORE = 1 << 7, TB_ALIGN_SHIFT = 8, TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT, TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT } |
Functions | |
| static bool | isFrameLoadOpcode (int Opcode) |
| static bool | isFrameStoreOpcode (int Opcode) |
| static bool | regIsPICBase (unsigned BaseReg, const MachineRegisterInfo &MRI) |
| Return true if register is PIC base; i.e.g defined by X86::MOVPC32r. More... | |
| static unsigned | getTruncatedShiftCount (MachineInstr &MI, unsigned ShiftAmtOperandIdx) |
| Check whether the shift count for a machine operand is non-zero. More... | |
| static bool | isTruncatedShiftCountForLEA (unsigned ShAmt) |
| Check whether the given shift count is appropriate can be represented by a LEA instruction. More... | |
| static int | getThreeSrcCommuteCase (uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2) |
| This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands. More... | |
| static bool | commuteVPTERNLOG (MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) |
| static bool | isCommutableVPERMV3Instruction (unsigned Opcode) |
| static unsigned | getCommutedVPERMV3Opcode (unsigned Opcode) |
| static X86::CondCode | getCondFromBranchOpc (unsigned BrOpc) |
| static X86::CondCode | getCondFromSETOpc (unsigned Opc) |
| Return condition code of a SET opcode. More... | |
| static X86::CondCode | getSwappedCondition (X86::CondCode CC) |
| Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a). More... | |
| static MachineBasicBlock * | getFallThroughMBB (MachineBasicBlock *MBB, MachineBasicBlock *TBB) |
| static bool | isHReg (unsigned Reg) |
| Test if the given register is a physical h register. More... | |
| static unsigned | CopyToFromAsymmetricReg (unsigned &DestReg, unsigned &SrcReg, const X86Subtarget &Subtarget) |
| static unsigned | getLoadStoreRegOpcode (unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load) |
| static unsigned | getStoreRegOpcode (unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) |
| static unsigned | getLoadRegOpcode (unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI) |
| static bool | isRedundantFlagInstr (MachineInstr &FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr &OI) |
| Check whether the first instruction, whose only purpose is to update flags, can be made redundant. More... | |
| static bool | isDefConvertible (MachineInstr &MI) |
| Check whether the definition can be converted to remove a comparison against zero. More... | |
| static X86::CondCode | isUseDefConvertible (MachineInstr &MI) |
| Check whether the use can be converted to remove a comparison against zero. More... | |
| static bool | Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc) |
| Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined. More... | |
| static bool | Expand2AddrKreg (MachineInstrBuilder &MIB, const MCInstrDesc &Desc, unsigned Reg) |
| Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads. More... | |
| static bool | expandMOV32r1 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne) |
| static bool | ExpandMOVImmSExti8 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget) |
| static void | expandLoadStackGuard (MachineInstrBuilder &MIB, const TargetInstrInfo &TII) |
| static bool | expandNOVLXLoad (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx) |
| static bool | expandNOVLXStore (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx) |
| static void | addOperands (MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0) |
| static MachineInstr * | FuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII) |
| static MachineInstr * | FuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0) |
| static MachineInstr * | MakeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI) |
| static bool | hasPartialRegUpdate (unsigned Opcode) |
| Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified. More... | |
| static bool | hasUndefRegUpdate (unsigned Opcode) |
| static bool | isNonFoldablePartialRegisterLoad (const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF) |
Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version. More... | |
| static const uint16_t * | lookup (unsigned opcode, unsigned domain, ArrayRef< uint16_t[3]> Table) |
| static const uint16_t * | lookupAVX512 (unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table) |
Variables | |
| static cl::opt< bool > | NoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions")) |
| static cl::opt< bool > | PrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden) |
| static cl::opt< bool > | ReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden) |
| static cl::opt< unsigned > | PartialRegUpdateClearance ("partial-reg-update-clearance", cl::desc("Clearance between two register writes ""for inserting XOR to avoid partial ""register update"), cl::init(64), cl::Hidden) |
| static cl::opt< unsigned > | UndefRegClearance ("undef-reg-clearance", cl::desc("How many idle instructions we would like before ""certain undef register reads"), cl::init(128), cl::Hidden) |
| static const uint16_t | ReplaceableInstrs [][3] |
| static const uint16_t | ReplaceableInstrsAVX2 [][3] |
| static const uint16_t | ReplaceableInstrsAVX512 [][4] |
| static const uint16_t | ReplaceableInstrsAVX512DQ [][4] |
| static const uint16_t | ReplaceableInstrsAVX512DQMasked [][4] |
| #define DEBUG_TYPE "x86-instr-info" |
Definition at line 44 of file X86InstrInfo.cpp.
| #define GET_INSTRINFO_CTOR_DTOR |
Definition at line 46 of file X86InstrInfo.cpp.
| #define VPERM_CASES | ( | Suffix | ) |
Referenced by getCommutedVPERMV3Opcode(), and isCommutableVPERMV3Instruction().
| #define VPERM_CASES | ( | Orig, | |
| New | |||
| ) |
| #define VPERM_CASES_BROADCAST | ( | Suffix | ) |
Referenced by getCommutedVPERMV3Opcode(), and isCommutableVPERMV3Instruction().
| #define VPERM_CASES_BROADCAST | ( | Orig, | |
| New | |||
| ) |
| anonymous enum |
Definition at line 73 of file X86InstrInfo.cpp.
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Definition at line 6856 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addDisp(), llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), assert(), i, and llvm::ArrayRef< T >::size().
Referenced by FuseInst(), FuseTwoAddrInst(), and MakeM0Inst().
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Definition at line 4190 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), getThreeSrcCommuteCase(), and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
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Definition at line 5510 of file X86InstrInfo.cpp.
References assert(), contains(), llvm::getX86SubSuperRegister(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasBWI(), and llvm::X86Subtarget::hasDQI().
Referenced by llvm::X86InstrInfo::copyPhysReg().
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Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.
This is used for mapping: k4 = K_SET1 to: k4 = KXNORrr k0, k0
Definition at line 6585 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.
This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr xmm4<undef>, xmm4<undef>
Definition at line 6564 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 6669 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachinePointerInfo::getGOT(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::RegState::Kill, llvm::MachineInstr::memoperands_begin(), llvm::X86II::MO_GOTPCREL, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, llvm::MachineInstr::setDebugLoc(), and llvm::MachineInstr::setDesc().
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 6593 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 6611 of file X86InstrInfo.cpp.
References assert(), llvm::X86FrameLowering::BuildCFI(), llvm::BuildMI(), llvm::MCCFIInstruction::createAdjustCfaOffset(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineInstrBuilder::getInstr(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineFunction::getMMI(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getTarget(), llvm::getX86SubSuperRegister(), llvm::MachineModuleInfo::hasDebugInfo(), llvm::X86FrameLowering::hasFP(), llvm::X86Subtarget::is64Bit(), llvm::Function::needsUnwindTableEntry(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), llvm::ARM::WinEH::StackAdjustment(), and llvm::MCAsmInfo::usesWindowsCFI().
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 6694 of file X86InstrInfo.cpp.
References llvm::MCRegisterInfo::getEncodingValue(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setReg().
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 6717 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::X86::AddrNumOperands, llvm::MCRegisterInfo::getEncodingValue(), llvm::TargetRegisterInfo::getMatchingSuperReg(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setReg().
Referenced by llvm::X86InstrInfo::expandPostRAPseudo().
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Definition at line 6909 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), addOperands(), assert(), llvm::MachineFunction::CreateMachineInstr(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), i, llvm::MachineBasicBlock::insert(), and llvm::MachineOperand::isReg().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Definition at line 6880 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), addOperands(), llvm::MachineFunction::CreateMachineInstr(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), i, and llvm::MachineBasicBlock::insert().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
Definition at line 4262 of file X86InstrInfo.cpp.
References llvm_unreachable, VPERM_CASES, and VPERM_CASES_BROADCAST.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
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Definition at line 4859 of file X86InstrInfo.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_P, and llvm::X86::COND_S.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::X86InstrInfo::removeBranch().
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Return condition code of a SET opcode.
Definition at line 4882 of file X86InstrInfo.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_P, and llvm::X86::COND_S.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
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Definition at line 5114 of file X86InstrInfo.cpp.
References SI, llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().
Referenced by llvm::X86InstrInfo::insertBranch().
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Definition at line 5929 of file X86InstrInfo.cpp.
References getLoadStoreRegOpcode().
Referenced by llvm::X86InstrInfo::loadRegFromAddr(), llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Definition at line 5781 of file X86InstrInfo.cpp.
References assert(), llvm::TargetRegisterClass::getSize(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasVLX(), llvm::X86Subtarget::is64Bit(), isHReg(), and llvm_unreachable.
Referenced by getLoadRegOpcode(), and getStoreRegOpcode().
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Definition at line 5921 of file X86InstrInfo.cpp.
References getLoadStoreRegOpcode().
Referenced by llvm::X86InstrInfo::storeRegToAddr(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
Definition at line 5009 of file X86InstrInfo.cpp.
References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
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This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands.
All prevents commuting a passthru operand. Returns -1 if the commute isn't possible. Case 0 - Possible to commute the first and second operands. Case 1 - Possible to commute the first and third operands. Case 2 - Possible to commute the second and third operands.
Definition at line 4081 of file X86InstrInfo.cpp.
References llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), and std::swap().
Referenced by commuteVPTERNLOG(), and llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands().
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Check whether the shift count for a machine operand is non-zero.
Definition at line 3596 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::X86II::REX_W, and llvm::MCInstrDesc::TSFlags.
Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().
Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.
This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:
movss (rdi), xmm0 cvtss2sd xmm0, xmm0
Instead of cvtss2sd (rdi), xmm0
FIXME: This should be turned into a TSFlags.
Definition at line 7185 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().
Definition at line 7256 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getUndefRegClearance().
Definition at line 4222 of file X86InstrInfo.cpp.
References B, D, llvm::X86II::PD, llvm::X86II::PS, VPERM_CASES, and VPERM_CASES_BROADCAST.
Referenced by llvm::X86InstrInfo::commuteInstructionImpl().
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Check whether the definition can be converted to remove a comparison against zero.
Definition at line 6123 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), getTruncatedShiftCount(), and isTruncatedShiftCountForLEA().
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
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Definition at line 3137 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::isLoadFromStackSlot(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().
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Definition at line 3214 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::isStoreToStackSlot(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().
Test if the given register is a physical h register.
Definition at line 5505 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::copyPhysReg(), and getLoadStoreRegOpcode().
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Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.
For instance, this transformation isn't legal: movss (rdi), xmm0 addps xmm0, xmm0 -> addps (rdi), xmm0
But this one is: movss (rdi), xmm0 addss xmm0, xmm0 -> addss (rdi), xmm0
Definition at line 7504 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), and llvm::MachineFunction::getRegInfo().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Check whether the first instruction, whose only purpose is to update flags, can be made redundant.
CMPrr can be made redundant by SUBrr if the operands are the same. This function can be extended later on. SrcReg, SrcRegs: register operands for FlagI. ImmValue: immediate for FlagI if it takes an immediate.
Definition at line 6091 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
Check whether the given shift count is appropriate can be represented by a LEA instruction.
Definition at line 3606 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::convertToThreeAddress(), and isDefConvertible().
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Check whether the use can be converted to remove a comparison against zero.
Definition at line 6208 of file X86InstrInfo.cpp.
References llvm::X86::COND_B, llvm::X86::COND_E, llvm::X86::COND_INVALID, and llvm::MachineInstr::getOpcode().
Referenced by llvm::X86InstrInfo::optimizeCompareInstr().
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Definition at line 8745 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), llvm::Module::getNamedMetadata(), llvm::isAtLeastOrStrongerThan(), llvm::isStrongerThan(), llvm::X86InstrInfo::setExecutionDomain(), and llvm::toCABI().
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Definition at line 8753 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
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Definition at line 6935 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), addOperands(), llvm::BuildMI(), llvm::MCInstrInfo::get(), and llvm::MachineInstr::getDebugLoc().
Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Definition at line 3336 of file X86InstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::def_instr_begin(), llvm::MachineRegisterInfo::def_instr_end(), E, llvm::MachineInstr::getOpcode(), I, and llvm::TargetRegisterInfo::isVirtualRegister().
Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().
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Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Referenced by llvm::X86InstrInfo::getPartialRegUpdateClearance().
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Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().
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Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().
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Definition at line 8419 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().
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Definition at line 8486 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::setExecutionDomain().
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Definition at line 8511 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::setExecutionDomain().
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Definition at line 8531 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::setExecutionDomain().
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Definition at line 8560 of file X86InstrInfo.cpp.
Referenced by llvm::X86InstrInfo::setExecutionDomain().
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Referenced by llvm::X86InstrInfo::getUndefRegClearance().
1.8.6