24 #define GET_INSTRINFO_CTOR_DTOR
25 #include "BPFGenInstrInfo.inc"
34 const DebugLoc &DL,
unsigned DestReg,
35 unsigned SrcReg,
bool KillSrc)
const {
36 if (BPF::GPRRegClass.
contains(DestReg, SrcReg))
37 BuildMI(MBB, I, DL,
get(BPF::MOV_rr), DestReg)
45 unsigned SrcReg,
bool IsKill,
int FI,
50 DL = I->getDebugLoc();
52 if (RC == &BPF::GPRRegClass)
53 BuildMI(MBB, I, DL,
get(BPF::STD))
63 unsigned DestReg,
int FI,
68 DL = I->getDebugLoc();
70 if (RC == &BPF::GPRRegClass)
80 bool AllowModify)
const {
84 while (I != MBB.
begin()) {
86 if (I->isDebugValue())
91 if (!isUnpredicatedTerminator(*I))
100 if (I->getOpcode() == BPF::JMP) {
102 TBB = I->getOperand(0).getMBB();
107 while (std::next(I) != MBB.
end())
108 std::next(I)->eraseFromParent();
115 I->eraseFromParent();
121 TBB = I->getOperand(0).getMBB();
136 int *BytesAdded)
const {
137 assert(!BytesAdded &&
"code size not handled");
140 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
144 assert(!FBB &&
"Unconditional branch with multiple successors!");
153 int *BytesRemoved)
const {
154 assert(!BytesRemoved &&
"code size not handled");
159 while (I != MBB.
begin()) {
161 if (I->isDebugValue())
163 if (I->getOpcode() != BPF::JMP)
166 I->eraseFromParent();
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned getKillRegState(bool B)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool empty() const
empty - Check if the array is empty.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const MachineInstrBuilder & addFrameIndex(int Idx) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.