14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
24 class MachineRegisterInfo;
84 unsigned ScratchRSrcReg;
85 unsigned ScratchWaveOffsetReg;
88 unsigned PrivateMemoryPtrUserSGPR;
92 unsigned PrivateSegmentBufferUserSGPR;
93 unsigned DispatchPtrUserSGPR;
94 unsigned QueuePtrUserSGPR;
95 unsigned KernargSegmentPtrUserSGPR;
96 unsigned DispatchIDUserSGPR;
97 unsigned FlatScratchInitUserSGPR;
98 unsigned PrivateSegmentSizeUserSGPR;
99 unsigned GridWorkGroupCountXUserSGPR;
100 unsigned GridWorkGroupCountYUserSGPR;
101 unsigned GridWorkGroupCountZUserSGPR;
104 unsigned WorkGroupIDXSystemSGPR;
105 unsigned WorkGroupIDYSystemSGPR;
106 unsigned WorkGroupIDZSystemSGPR;
107 unsigned WorkGroupInfoSystemSGPR;
108 unsigned PrivateSegmentWaveByteOffsetSystemSGPR;
111 unsigned PSInputAddr;
116 std::pair<unsigned, unsigned> FlatWorkGroupSizes;
120 std::pair<unsigned, unsigned> WavesPerEU;
123 std::array<int, 3> DebuggerWorkGroupIDStackObjectIndices;
213 WorkGroupIDXSystemSGPR = getNextSystemSGPR();
215 return WorkGroupIDXSystemSGPR;
219 WorkGroupIDYSystemSGPR = getNextSystemSGPR();
221 return WorkGroupIDYSystemSGPR;
225 WorkGroupIDZSystemSGPR = getNextSystemSGPR();
227 return WorkGroupIDZSystemSGPR;
231 WorkGroupInfoSystemSGPR = getNextSystemSGPR();
233 return WorkGroupInfoSystemSGPR;
237 PrivateSegmentWaveByteOffsetSystemSGPR = getNextSystemSGPR();
239 return PrivateSegmentWaveByteOffsetSystemSGPR;
243 PrivateSegmentWaveByteOffsetSystemSGPR =
Reg;
247 return PrivateSegmentBuffer;
259 return KernargSegmentPtr;
267 return FlatScratchInit;
271 return GridWorkgroupCountX;
275 return GridWorkgroupCountY;
279 return GridWorkgroupCountZ;
295 return WorkGroupInfo;
299 return PrivateSegmentWaveByteOffset;
315 return PrivateMemoryInputPtr;
327 return PrivateSegmentWaveByteOffsetSystemSGPR;
333 return ScratchRSrcReg;
337 assert(Reg != AMDGPU::NoRegister &&
"Should never be unset");
338 ScratchRSrcReg =
Reg;
342 return ScratchWaveOffsetReg;
346 assert(Reg != AMDGPU::NoRegister &&
"Should never be unset");
347 ScratchWaveOffsetReg =
Reg;
351 return QueuePtrUserSGPR;
355 return PrivateMemoryPtrUserSGPR;
359 return HasSpilledSGPRs;
363 HasSpilledSGPRs =
Spill;
367 return HasSpilledVGPRs;
371 HasSpilledVGPRs =
Spill;
375 return HasNonSpillStackObjects;
379 HasNonSpillStackObjects = StackObject;
383 return NumSpilledSGPRs;
387 return NumSpilledVGPRs;
391 NumSpilledSGPRs += num;
395 NumSpilledVGPRs += num;
403 return PSInputAddr & (1 << Index);
407 PSInputAddr |= 1 << Index;
421 return FlatWorkGroupSizes;
426 return FlatWorkGroupSizes.first;
431 return FlatWorkGroupSizes.second;
442 return WavesPerEU.first;
447 return WavesPerEU.second;
453 return DebuggerWorkGroupIDStackObjectIndices[Dim];
459 DebuggerWorkGroupIDStackObjectIndices[Dim] = ObjectIdx;
465 return DebuggerWorkItemIDStackObjectIndices[Dim];
471 DebuggerWorkItemIDStackObjectIndices[Dim] = ObjectIdx;
479 return WorkGroupIDXSystemSGPR;
482 return WorkGroupIDYSystemSGPR;
485 return WorkGroupIDZSystemSGPR;
495 return AMDGPU::VGPR0;
498 return AMDGPU::VGPR1;
501 return AMDGPU::VGPR2;
Interface definition for SIRegisterInfo.
PrivateMemoryInputPtr(false)
unsigned getNumUserSGPRs() const
int getDebuggerWorkGroupIDStackObjectIndex(unsigned Dim) const
unsigned getQueuePtrUserSGPR() const
bool hasFlatScratchInit() const
void addToSpilledSGPRs(unsigned num)
unsigned getNumPreloadedSGPRs() const
bool hasSpilledVGPRs() const
AMDGPUImagePseudoSourceValue()
void addToSpilledVGPRs(unsigned num)
unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const
HasNonSpillStackObjects(false)
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
bool hasDispatchID() const
unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI)
unsigned addWorkGroupIDY()
GridWorkgroupCountZ(false)
bool hasWorkGroupIDZ() const
unsigned getScratchWaveOffsetReg() const
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned addPrivateMemoryPtr(const SIRegisterInfo &TRI)
bool hasWorkItemIDZ() const
PrivateSegmentWaveByteOffset(false)
SIMachineFunctionInfo(const MachineFunction &MF)
const AMDGPUImagePseudoSourceValue * getImagePSV() const
unsigned getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses...
unsigned getMinFlatWorkGroupSize() const
bool hasWorkGroupIDY() const
std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const
unsigned getMaxFlatWorkGroupSize() const
void setPrivateSegmentWaveByteOffset(unsigned Reg)
void setDebuggerWorkGroupIDStackObjectIndex(unsigned Dim, int ObjectIdx)
Sets stack object index for Dim's work group ID to ObjectIdx.
bool hasSpilledSGPRs() const
void setScratchRSrcReg(unsigned Reg)
const AMDGPUBufferPseudoSourceValue * getBufferPSV() const
bool hasWorkGroupInfo() const
void setHasNonSpillStackObjects(bool StackObject=true)
unsigned addDispatchID(const SIRegisterInfo &TRI)
void setDebuggerWorkItemIDStackObjectIndex(unsigned Dim, int ObjectIdx)
Sets stack object index for Dim's work item ID to ObjectIdx.
void setIfReturnsVoid(bool Value)
void setHasSpilledVGPRs(bool Spill=true)
void setTIDReg(unsigned Reg)
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getWorkItemIDVGPR(unsigned Dim) const
bool hasNonSpillStackObjects() const
unsigned getPSInputAddr() const
int getDebuggerWorkItemIDStackObjectIndex(unsigned Dim) const
bool hasWorkGroupIDX() const
unsigned getWorkGroupIDSGPR(unsigned Dim) const
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
GridWorkgroupCountY(false)
void markPSInputAllocated(unsigned Index)
bool isPSInputAllocated(unsigned Index) const
GridWorkgroupCountX(false)
DebuggerWorkItemIDStackObjectIndices({{0, 0, 0}})
unsigned addWorkGroupInfo()
unsigned LDSWaveSpillSize
bool hasDispatchPtr() const
bool hasKernargSegmentPtr() const
AMDGPUBufferPseudoSourceValue()
unsigned addQueuePtr(const SIRegisterInfo &TRI)
bool hasWorkItemIDX() const
unsigned getPrivateMemoryPtrUserSGPR() const
void setHasSpilledSGPRs(bool Spill=true)
void setScratchWaveOffsetReg(unsigned Reg)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned addDispatchPtr(const SIRegisterInfo &TRI)
bool hasGridWorkgroupCountX() const
unsigned getNumSpilledVGPRs() const
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value...
SpilledReg getSpilledReg(MachineFunction *MF, unsigned FrameIndex, unsigned SubIdx)
unsigned getMaxWavesPerEU() const
std::map< unsigned, unsigned > LaneVGPRs
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
Special value supplied for machine level alias analysis.
unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
unsigned addFlatScratchInit(const SIRegisterInfo &TRI)
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
std::pair< unsigned, unsigned > getWavesPerEU() const
unsigned getMinWavesPerEU() const
unsigned ScratchOffsetReg
bool hasGridWorkgroupCountZ() const
SpilledReg(unsigned R, int L)
unsigned addWorkGroupIDZ()
unsigned getNumSpilledSGPRs() const
bool hasWorkItemIDY() const
unsigned addPrivateSegmentWaveByteOffset()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value...
bool hasPrivateMemoryInputPtr() const
PrivateSegmentBuffer(false)
bool hasCalculatedTID() const
unsigned addWorkGroupIDX()
unsigned getTIDReg() const
bool hasGridWorkgroupCountY() const
bool hasPrivateSegmentWaveByteOffset() const
bool hasPrivateSegmentBuffer() const