LLVM  4.0.0
llvm::TargetSubtargetInfo Member List

This is the complete list of members for llvm::TargetSubtargetInfo, including all inherited members.

adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const llvm::TargetSubtargetInfoinlinevirtual
ANTIDEP_ALL enum valuellvm::TargetSubtargetInfo
ANTIDEP_CRITICAL enum valuellvm::TargetSubtargetInfo
ANTIDEP_NONE enum valuellvm::TargetSubtargetInfo
AntiDepBreakMode enum namellvm::TargetSubtargetInfo
ApplyFeatureFlag(StringRef FS)llvm::MCSubtargetInfo
enableAtomicExpand() const llvm::TargetSubtargetInfovirtual
enableEarlyIfConversion() const llvm::TargetSubtargetInfoinlinevirtual
enableJoinGlobalCopies() const llvm::TargetSubtargetInfovirtual
enableMachineSchedDefaultSched() const llvm::TargetSubtargetInfoinlinevirtual
enableMachineScheduler() const llvm::TargetSubtargetInfovirtual
enablePostRAScheduler() const llvm::TargetSubtargetInfovirtual
enableRALocalReassignment(CodeGenOpt::Level OptLevel) const llvm::TargetSubtargetInfovirtual
enableSubRegLiveness() const llvm::TargetSubtargetInfoinlinevirtual
getAntiDepBreakMode() const llvm::TargetSubtargetInfoinlinevirtual
getCallLowering() const llvm::TargetSubtargetInfoinlinevirtual
getCPU() const llvm::MCSubtargetInfoinline
getCriticalPathRCs(RegClassVector &CriticalPathRCs) const llvm::TargetSubtargetInfoinlinevirtual
getCustomPBQPConstraints() const llvm::TargetSubtargetInfoinlinevirtual
getDAGScheduler(CodeGenOpt::Level) const llvm::TargetSubtargetInfoinlinevirtual
getFeatureBits() const llvm::MCSubtargetInfoinline
getFrameLowering() const llvm::TargetSubtargetInfoinlinevirtual
getInstrInfo() const llvm::TargetSubtargetInfoinlinevirtual
getInstrItineraryData() const llvm::TargetSubtargetInfoinlinevirtual
getInstrItineraryForCPU(StringRef CPU) const llvm::MCSubtargetInfo
getInstructionSelector() const llvm::TargetSubtargetInfoinlinevirtual
getLegalizerInfo() const llvm::TargetSubtargetInfoinlinevirtual
getOptLevelToEnablePostRAScheduler() const llvm::TargetSubtargetInfoinlinevirtual
getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const llvm::TargetSubtargetInfoinlinevirtual
getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const llvm::MCSubtargetInfoinline
getRegBankInfo() const llvm::TargetSubtargetInfoinlinevirtual
getRegisterInfo() const llvm::TargetSubtargetInfoinlinevirtual
getSchedModel() const llvm::MCSubtargetInfoinline
getSchedModelForCPU(StringRef CPU) const llvm::MCSubtargetInfo
getSelectionDAGInfo() const llvm::TargetSubtargetInfoinlinevirtual
getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const llvm::TargetSubtargetInfoinlinevirtual
getTargetLowering() const llvm::TargetSubtargetInfoinlinevirtual
getTargetTriple() const llvm::MCSubtargetInfoinline
getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const llvm::MCSubtargetInfoinline
getWriteProcResBegin(const MCSchedClassDesc *SC) const llvm::MCSubtargetInfoinline
getWriteProcResEnd(const MCSchedClassDesc *SC) const llvm::MCSubtargetInfoinline
initInstrItins(InstrItineraryData &InstrItins) const llvm::MCSubtargetInfo
InitMCProcessorInfo(StringRef CPU, StringRef FS)llvm::MCSubtargetInfoprotected
isCPUStringValid(StringRef CPU) const llvm::MCSubtargetInfoinline
isXRaySupported() const llvm::TargetSubtargetInfoinlinevirtual
MCSubtargetInfo(const MCSubtargetInfo &)=defaultllvm::MCSubtargetInfo
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)llvm::MCSubtargetInfo
operator=(const TargetSubtargetInfo &)=deletellvm::TargetSubtargetInfo
overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const llvm::TargetSubtargetInfoinlinevirtual
RegClassVector typedefllvm::TargetSubtargetInfo
resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const llvm::TargetSubtargetInfoinlinevirtual
setDefaultFeatures(StringRef CPU, StringRef FS)llvm::MCSubtargetInfo
setFeatureBits(const FeatureBitset &FeatureBits_)llvm::MCSubtargetInfoinline
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)llvm::TargetSubtargetInfoprotected
TargetSubtargetInfo()=deletellvm::TargetSubtargetInfo
TargetSubtargetInfo(const TargetSubtargetInfo &)=deletellvm::TargetSubtargetInfo
ToggleFeature(uint64_t FB)llvm::MCSubtargetInfo
ToggleFeature(const FeatureBitset &FB)llvm::MCSubtargetInfo
ToggleFeature(StringRef FS)llvm::MCSubtargetInfo
useAA() const llvm::TargetSubtargetInfovirtual
~TargetSubtargetInfo()llvm::TargetSubtargetInfovirtual