LLVM  4.0.0
LivePhysRegs.cpp
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1 //===--- LivePhysRegs.cpp - Live Physical Register Set --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the LivePhysRegs utility for tracking liveness of
11 // physical registers across machine instructions in forward or backward order.
12 // A more detailed description can be found in the corresponding header file.
13 //
14 //===----------------------------------------------------------------------===//
15 
21 #include "llvm/Support/Debug.h"
23 using namespace llvm;
24 
25 
26 /// \brief Remove all registers from the set that get clobbered by the register
27 /// mask.
28 /// The clobbers set will be the list of live registers clobbered
29 /// by the regmask.
31  SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> *Clobbers) {
32  SparseSet<unsigned>::iterator LRI = LiveRegs.begin();
33  while (LRI != LiveRegs.end()) {
34  if (MO.clobbersPhysReg(*LRI)) {
35  if (Clobbers)
36  Clobbers->push_back(std::make_pair(*LRI, &MO));
37  LRI = LiveRegs.erase(LRI);
38  } else
39  ++LRI;
40  }
41 }
42 
43 /// Simulates liveness when stepping backwards over an instruction(bundle):
44 /// Remove Defs, add uses. This is the recommended way of calculating liveness.
46  // Remove defined registers and regmask kills from the set.
47  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
48  if (O->isReg()) {
49  if (!O->isDef())
50  continue;
51  unsigned Reg = O->getReg();
53  continue;
54  removeReg(Reg);
55  } else if (O->isRegMask())
56  removeRegsInMask(*O, nullptr);
57  }
58 
59  // Add uses to the set.
60  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
61  if (!O->isReg() || !O->readsReg())
62  continue;
63  unsigned Reg = O->getReg();
65  continue;
66  addReg(Reg);
67  }
68 }
69 
70 /// Simulates liveness when stepping forward over an instruction(bundle): Remove
71 /// killed-uses, add defs. This is the not recommended way, because it depends
72 /// on accurate kill flags. If possible use stepBackward() instead of this
73 /// function.
75  SmallVectorImpl<std::pair<unsigned, const MachineOperand*>> &Clobbers) {
76  // Remove killed registers from the set.
77  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
78  if (O->isReg()) {
79  unsigned Reg = O->getReg();
81  continue;
82  if (O->isDef()) {
83  // Note, dead defs are still recorded. The caller should decide how to
84  // handle them.
85  Clobbers.push_back(std::make_pair(Reg, &*O));
86  } else {
87  if (!O->isKill())
88  continue;
89  assert(O->isUse());
90  removeReg(Reg);
91  }
92  } else if (O->isRegMask())
93  removeRegsInMask(*O, &Clobbers);
94  }
95 
96  // Add defs to the set.
97  for (auto Reg : Clobbers) {
98  // Skip dead defs. They shouldn't be added to the set.
99  if (Reg.second->isReg() && Reg.second->isDead())
100  continue;
101  addReg(Reg.first);
102  }
103 }
104 
105 /// Prin the currently live registers to OS.
107  OS << "Live Registers:";
108  if (!TRI) {
109  OS << " (uninitialized)\n";
110  return;
111  }
112 
113  if (empty()) {
114  OS << " (empty)\n";
115  return;
116  }
117 
118  for (const_iterator I = begin(), E = end(); I != E; ++I)
119  OS << " " << PrintReg(*I, TRI);
120  OS << "\n";
121 }
122 
123 /// Dumps the currently live registers to the debug output.
125 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
126  dbgs() << " " << *this;
127 #endif
128 }
129 
131  unsigned Reg) const {
132  if (LiveRegs.count(Reg))
133  return false;
134  if (MRI.isReserved(Reg))
135  return false;
136  for (MCRegAliasIterator R(Reg, TRI, false); R.isValid(); ++R) {
137  if (LiveRegs.count(*R))
138  return false;
139  }
140  return true;
141 }
142 
143 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
144 void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
145  for (const auto &LI : MBB.liveins()) {
146  MCSubRegIndexIterator S(LI.PhysReg, TRI);
147  if (LI.LaneMask.all() || (LI.LaneMask.any() && !S.isValid())) {
148  addReg(LI.PhysReg);
149  continue;
150  }
151  for (; S.isValid(); ++S) {
152  unsigned SI = S.getSubRegIndex();
153  if ((LI.LaneMask & TRI->getSubRegIndexLaneMask(SI)).any())
154  addReg(S.getSubReg());
155  }
156  }
157 }
158 
159 /// Add pristine registers to the given \p LiveRegs. This function removes
160 /// actually saved callee save registers when \p InPrologueEpilogue is false.
161 static void addPristines(LivePhysRegs &LiveRegs, const MachineFunction &MF,
162  const MachineFrameInfo &MFI,
163  const TargetRegisterInfo &TRI) {
164  for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
165  LiveRegs.addReg(*CSR);
166  for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
167  LiveRegs.removeReg(Info.getReg());
168 }
169 
171  // To get the live-outs we simply merge the live-ins of all successors.
172  for (const MachineBasicBlock *Succ : MBB.successors())
173  addBlockLiveIns(*Succ);
174 }
175 
177  const MachineFunction &MF = *MBB.getParent();
178  const MachineFrameInfo &MFI = MF.getFrameInfo();
179  if (MFI.isCalleeSavedInfoValid()) {
180  if (MBB.isReturnBlock()) {
181  // The return block has no successors whose live-ins we could merge
182  // below. So instead we add the callee saved registers manually.
183  for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I)
184  addReg(*I);
185  } else {
186  addPristines(*this, MF, MFI, *TRI);
187  }
188  }
189 
191 }
192 
194  const MachineFunction &MF = *MBB.getParent();
195  const MachineFrameInfo &MFI = MF.getFrameInfo();
196  if (MFI.isCalleeSavedInfoValid())
197  addPristines(*this, MF, MFI, *TRI);
198  addBlockLiveIns(MBB);
199 }
200 
202  MachineBasicBlock &MBB) {
203  assert(MBB.livein_empty());
204  LiveRegs.init(TRI);
205  LiveRegs.addLiveOutsNoPristines(MBB);
206  for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend()))
207  LiveRegs.stepBackward(MI);
208 
209  for (unsigned Reg : LiveRegs) {
210  // Skip the register if we are about to add one of its super registers.
211  bool ContainsSuperReg = false;
212  for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
213  if (LiveRegs.contains(*SReg)) {
214  ContainsSuperReg = true;
215  break;
216  }
217  }
218  if (ContainsSuperReg)
219  continue;
220  MBB.addLiveIn(Reg);
221  }
222 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< livein_iterator > liveins() const
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:450
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
size_type count(const KeyT &Key) const
count - Returns 1 if this set contains an element identified by Key, 0 otherwise. ...
Definition: SparseSet.h:235
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
void computeLiveIns(LivePhysRegs &LiveRegs, const TargetRegisterInfo &TRI, MachineBasicBlock &MBB)
Compute the live-in list for MBB assuming all of its successors live-in lists are up-to-date...
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
SparseSet< unsigned >::const_iterator const_iterator
Definition: LivePhysRegs.h:137
iterator_range< succ_iterator > successors()
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
MCSuperRegIterator enumerates all super-registers of Reg.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
const_iterator end() const
Definition: SparseSet.h:175
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
void print(raw_ostream &OS) const
Prints the currently live registers to OS.
MachineBasicBlock * MBB
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< unsigned, const MachineOperand * >> &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle): Remove killed-uses, add defs.
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
reverse_iterator rend()
reverse_iterator rbegin()
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
iterator erase(iterator I)
erase - Erases an existing element identified by a valid iterator.
Definition: SparseSet.h:285
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
void init(const TargetRegisterInfo &TRI)
Clear and initialize the LivePhysRegs set.
Definition: LivePhysRegs.h:63
MCRegAliasIterator enumerates all registers aliasing Reg.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle): Remove Defs, add uses.
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void addLiveOutsNoPristines(const MachineBasicBlock &MBB)
Like addLiveOuts() but does not add pristine registers/callee saved registers.
const_iterator begin() const
Definition: SparseSet.h:174
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction. ...
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void removeRegsInMask(const MachineOperand &MO, SmallVectorImpl< std::pair< unsigned, const MachineOperand * >> *Clobbers)
Removes physical registers clobbered by the regmask operand MO.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
bool empty() const
Returns true if the set is empty.
Definition: LivePhysRegs.h:73
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void removeReg(unsigned Reg)
Removes a physical register, all its sub-registers, and all its super-registers from the set...
Definition: LivePhysRegs.h:86
SparseSet - Fast set implmentation for objects that can be identified by small unsigned keys...
Definition: SparseSet.h:123
A set of live physical registers with functions to track liveness when walking backward/forward throu...
Definition: LivePhysRegs.h:45
#define I(x, y, z)
Definition: MD5.cpp:54
bool isValid() const
isValid - Returns true until all the operands have been visited.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void dump() const
Dumps the currently live registers to the debug output.
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
static void addPristines(LivePhysRegs &LiveRegs, const MachineFunction &MF, const MachineFrameInfo &MFI, const TargetRegisterInfo &TRI)
Add pristine registers to the given LiveRegs.
const_iterator end() const
Definition: LivePhysRegs.h:139
const_iterator begin() const
Definition: LivePhysRegs.h:138
void addReg(unsigned Reg)
Adds a physical register and all its sub-registers to the set.
Definition: LivePhysRegs.h:76