14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
28 #define GET_INSTRINFO_HEADER
29 #include "HexagonGenInstrInfo.inc"
34 class HexagonSubtarget;
39 virtual void anchor();
61 int &FrameIndex)
const override;
91 bool AllowModify)
const override;
97 int *BytesRemoved =
nullptr)
const override;
112 int *BytesAdded =
nullptr)
const override;
128 unsigned Iter,
unsigned MaxIter)
const override;
136 unsigned ExtraPredCycles,
146 unsigned NumTCycles,
unsigned ExtraTCycles,
148 unsigned NumFCycles,
unsigned ExtraFCycles,
169 const DebugLoc &DL,
unsigned DestReg,
unsigned SrcReg,
170 bool KillSrc)
const override;
178 unsigned SrcReg,
bool isKill,
int FrameIndex,
187 unsigned DestReg,
int FrameIndex,
233 std::vector<MachineOperand> &Pred)
const override;
262 unsigned &SrcReg2,
int &
Mask,
int &
Value)
const override;
269 unsigned *PredCost =
nullptr)
const override;
286 unsigned &OffsetPos)
const override;
318 bool isExpr(
unsigned OpType)
const;
361 bool isValidOffset(
unsigned Opcode,
int Offset,
bool Extend =
true)
const;
390 unsigned &AccessSize)
const;
421 unsigned &PredRegPos,
unsigned &PredRegFlags)
const;
446 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
bool hasPseudoInstrPair(const MachineInstr &MI) const
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
bool isIndirectCall(const MachineInstr &MI) const
This class is the base class for the comparison instructions.
short getBaseWithLongOffset(short Opcode) const
unsigned reversePrediction(unsigned Opcode) const
bool isTC1(const MachineInstr &MI) const
bool isIndirectL4Return(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
bool isNewValueInst(const MachineInstr &MI) const
Instructions::const_iterator const_instr_iterator
bool isPredicateLate(unsigned Opcode) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
short getPseudoInstrPair(const MachineInstr &MI) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
short getNonExtOpcode(const MachineInstr &MI) const
bool isPredicatedTrue(const MachineInstr &MI) const
bool PredOpcodeHasJMP_c(unsigned Opcode) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
bool isMemOp(const MachineInstr &MI) const
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isNewValue(const MachineInstr &MI) const
bool isTailCall(const MachineInstr &MI) const override
bool isVecAcc(const MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isAbsoluteSet(const MachineInstr &MI) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
bool isExpr(unsigned OpType) const
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isTC4x(const MachineInstr &MI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
short getAbsoluteForm(const MachineInstr &MI) const
bool isSpillPredRegOp(const MachineInstr &MI) const
bool isLateResultInstr(const MachineInstr &MI) const
short xformRegToImmOffset(const MachineInstr &MI) const
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
bool isCondInst(const MachineInstr &MI) const
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isLoopN(const MachineInstr &MI) const
int getMaxValue(const MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
void genAllInsnTimingClasses(MachineFunction &MF) const
bool isComplex(const MachineInstr &MI) const
bool isConditionalALU32(const MachineInstr &MI) const
bool isAccumulator(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool isPredictedTaken(unsigned Opcode) const
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Itinerary data supplied by a subtarget to be used by a target.
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
bool isEarlySourceInstr(const MachineInstr &MI) const
unsigned getInvertedPredicatedOpcode(const int Opc) const
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
bool isJumpR(const MachineInstr &MI) const
This class is intended to be used as a base class for asm properties and features specific to the tar...
int getDotOldOp(const int opc) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
bool isVecALU(const MachineInstr &MI) const
unsigned getCExtOpNum(const MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
MVT - Machine Value Type.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
bool reversePredSense(MachineInstr &MI) const
bool isLateSourceInstr(const MachineInstr &MI) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isNewValueStore(const MachineInstr &MI) const
unsigned getSize(const MachineInstr &MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
MachineInstr * getFirstNonDbgInst(MachineBasicBlock *BB) const
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isTC2(const MachineInstr &MI) const
EVT - Extended Value Type.
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
bool isDotCurInst(const MachineInstr &MI) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isExtended(const MachineInstr &MI) const
static cl::opt< unsigned > MaxIter("bb-vectorize-max-iter", cl::init(0), cl::Hidden, cl::desc("The maximum number of pairing iterations"))
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
bool hasUncondBranch(const MachineBasicBlock *B) const
bool hasNonExtEquivalent(const MachineInstr &MI) const
bool isConditionalTransfer(const MachineInstr &MI) const
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
short getEquivalentHWInstr(const MachineInstr &MI) const
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
unsigned getMemAccessSize(const MachineInstr &MI) const
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isZeroExtendingLoad(const MachineInstr &MI) const
bool hasEHLabel(const MachineBasicBlock *B) const
HexagonInstrInfo(HexagonSubtarget &ST)
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isCompoundBranchInstr(const MachineInstr &MI) const
int getCondOpcode(int Opc, bool sense) const
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
bool isTC2Early(const MachineInstr &MI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
bool isPredicable(MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
bool isV60VectorInstruction(const MachineInstr &MI) const
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
bool isEndLoopN(unsigned Opcode) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
bool isSignExtendingLoad(const MachineInstr &MI) const
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
bool isPredicatedNew(const MachineInstr &MI) const
bool isDeallocRet(const MachineInstr &MI) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
TargetSubtargetInfo - Generic base class for all target subtargets.
bool isFloat(const MachineInstr &MI) const
Representation of each machine instruction.
unsigned getAddrMode(const MachineInstr &MI) const
bool isDotNewInst(const MachineInstr &MI) const
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
bool isValidAutoIncImm(const EVT VT, const int Offset) const
bool isExtendable(const MachineInstr &MI) const
int getDotNewOp(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
short getBaseWithRegOffset(const MachineInstr &MI) const
unsigned getValidSubTargets(const unsigned Opcode) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
int getDotCurOp(const MachineInstr &MI) const
bool isConditionalStore(const MachineInstr &MI) const
bool isConditionalLoad(const MachineInstr &MI) const
bool mayBeNewStore(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
bool doesNotReturn(const MachineInstr &CallMI) const
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
LLVM Value Representation.
bool mayBeCurLoad(const MachineInstr &MI) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
int getMinValue(const MachineInstr &MI) const
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code, return true if it cannot be understood.
bool isConstExtended(const MachineInstr &MI) const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
uint64_t getType(const MachineInstr &MI) const
unsigned getUnits(const MachineInstr &MI) const
bool isNewValueJump(const MachineInstr &MI) const
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const