LLVM  4.0.0
SystemZInstrInfo.h
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1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
16 
17 #include "SystemZ.h"
18 #include "SystemZRegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
23 
24 namespace llvm {
25 
26 class SystemZTargetMachine;
27 
28 namespace SystemZII {
29 enum {
30  // See comments in SystemZInstrFormats.td.
31  SimpleBDXLoad = (1 << 0),
32  SimpleBDXStore = (1 << 1),
33  Has20BitOffset = (1 << 2),
34  HasIndex = (1 << 3),
35  Is128Bit = (1 << 4),
36  AccessSizeMask = (31 << 5),
38  CCValuesMask = (15 << 10),
40  CompareZeroCCMaskMask = (15 << 14),
42  CCMaskFirst = (1 << 18),
43  CCMaskLast = (1 << 19),
44  IsLogical = (1 << 20)
45 };
46 static inline unsigned getAccessSize(unsigned int Flags) {
47  return (Flags & AccessSizeMask) >> AccessSizeShift;
48 }
49 static inline unsigned getCCValues(unsigned int Flags) {
50  return (Flags & CCValuesMask) >> CCValuesShift;
51 }
52 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
54 }
55 
56 // SystemZ MachineOperand target flags.
57 enum {
58  // Masks out the bits for the access model.
59  MO_SYMBOL_MODIFIER = (3 << 0),
60 
61  // @GOT (aka @GOTENT)
62  MO_GOT = (1 << 0),
63 
64  // @INDNTPOFF
65  MO_INDNTPOFF = (2 << 0)
66 };
67 // Classifies a branch.
68 enum BranchType {
69  // An instruction that branches on the current value of CC.
71 
72  // An instruction that peforms a 32-bit signed comparison and branches
73  // on the result.
75 
76  // An instruction that peforms a 32-bit unsigned comparison and branches
77  // on the result.
79 
80  // An instruction that peforms a 64-bit signed comparison and branches
81  // on the result.
83 
84  // An instruction that peforms a 64-bit unsigned comparison and branches
85  // on the result.
87 
88  // An instruction that decrements a 32-bit register and branches if
89  // the result is nonzero.
91 
92  // An instruction that decrements a 64-bit register and branches if
93  // the result is nonzero.
95 };
96 // Information about a branch instruction.
97 struct Branch {
98  // The type of the branch.
100 
101  // CCMASK_<N> is set if CC might be equal to N.
102  unsigned CCValid;
103 
104  // CCMASK_<N> is set if the branch should be taken when CC == N.
105  unsigned CCMask;
106 
107  // The target of the branch.
109 
110  Branch(BranchType type, unsigned ccValid, unsigned ccMask,
111  const MachineOperand *target)
112  : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
113 };
114 // Kinds of fused compares in compare-and-* instructions. Together with type
115 // of the converted compare, this identifies the compare-and-*
116 // instruction.
118  // Relative branch - CRJ etc.
120 
121  // Indirect branch, used for return - CRBReturn etc.
123 
124  // Indirect branch, used for sibcall - CRBCall etc.
126 
127  // Trap
129 };
130 } // end namespace SystemZII
131 
132 class SystemZSubtarget;
134  const SystemZRegisterInfo RI;
135  SystemZSubtarget &STI;
136 
137  void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
138  void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
139  void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
140  bool ConvertHigh) const;
141  void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
142  unsigned LowOpcodeK, unsigned HighOpcode) const;
143  void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
144  unsigned HighOpcode) const;
145  void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
146  unsigned HighOpcode) const;
147  void expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode,
148  unsigned HighOpcode) const;
149  void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
150  unsigned Size) const;
151  void expandLoadStackGuard(MachineInstr *MI) const;
152  void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
153  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
154  unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
155  virtual void anchor();
156 
157 protected:
158  /// Commutes the operands in the given instruction by changing the operands
159  /// order and/or changing the instruction's opcode and/or the immediate value
160  /// operand.
161  ///
162  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
163  /// to be commuted.
164  ///
165  /// Do not call this method for a non-commutable instruction or
166  /// non-commutable operands.
167  /// Even though the instruction is commutable, the method may still
168  /// fail to commute the operands, null pointer is returned in such cases.
169  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
170  unsigned CommuteOpIdx1,
171  unsigned CommuteOpIdx2) const override;
172 
173 public:
174  explicit SystemZInstrInfo(SystemZSubtarget &STI);
175 
176  // Override TargetInstrInfo.
177  unsigned isLoadFromStackSlot(const MachineInstr &MI,
178  int &FrameIndex) const override;
179  unsigned isStoreToStackSlot(const MachineInstr &MI,
180  int &FrameIndex) const override;
181  bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
182  int &SrcFrameIndex) const override;
183  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
184  MachineBasicBlock *&FBB,
186  bool AllowModify) const override;
187  unsigned removeBranch(MachineBasicBlock &MBB,
188  int *BytesRemoved = nullptr) const override;
189  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
191  const DebugLoc &DL,
192  int *BytesAdded = nullptr) const override;
193  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
194  unsigned &SrcReg2, int &Mask, int &Value) const override;
195  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
196  unsigned SrcReg2, int Mask, int Value,
197  const MachineRegisterInfo *MRI) const override;
198  bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
199  unsigned, unsigned, int&, int&, int&) const override;
200  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
201  const DebugLoc &DL, unsigned DstReg,
202  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
203  unsigned FalseReg) const override;
204  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
205  MachineRegisterInfo *MRI) const override;
206  bool isPredicable(MachineInstr &MI) const override;
207  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
208  unsigned ExtraPredCycles,
209  BranchProbability Probability) const override;
210  bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
211  unsigned NumCyclesT, unsigned ExtraPredCyclesT,
212  MachineBasicBlock &FMBB,
213  unsigned NumCyclesF, unsigned ExtraPredCyclesF,
214  BranchProbability Probability) const override;
215  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
216  BranchProbability Probability) const override;
217  bool PredicateInstruction(MachineInstr &MI,
218  ArrayRef<MachineOperand> Pred) const override;
219  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
220  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
221  bool KillSrc) const override;
222  void storeRegToStackSlot(MachineBasicBlock &MBB,
224  unsigned SrcReg, bool isKill, int FrameIndex,
225  const TargetRegisterClass *RC,
226  const TargetRegisterInfo *TRI) const override;
227  void loadRegFromStackSlot(MachineBasicBlock &MBB,
229  unsigned DestReg, int FrameIdx,
230  const TargetRegisterClass *RC,
231  const TargetRegisterInfo *TRI) const override;
232  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
233  MachineInstr &MI,
234  LiveVariables *LV) const override;
235  MachineInstr *
236  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
237  ArrayRef<unsigned> Ops,
238  MachineBasicBlock::iterator InsertPt, int FrameIndex,
239  LiveIntervals *LIS = nullptr) const override;
240  MachineInstr *foldMemoryOperandImpl(
242  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
243  LiveIntervals *LIS = nullptr) const override;
244  bool expandPostRAPseudo(MachineInstr &MBBI) const override;
245  bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
246  override;
247 
248  // Return the SystemZRegisterInfo, which this class owns.
249  const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
250 
251  // Return the size in bytes of MI.
252  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
253 
254  // Return true if MI is a conditional or unconditional branch.
255  // When returning true, set Cond to the mask of condition-code
256  // values on which the instruction will branch, and set Target
257  // to the operand that contains the branch target. This target
258  // can be a register or a basic block.
259  SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
260 
261  // Get the load and store opcodes for a given register class.
262  void getLoadStoreOpcodes(const TargetRegisterClass *RC,
263  unsigned &LoadOpcode, unsigned &StoreOpcode) const;
264 
265  // Opcode is the opcode of an instruction that has an address operand,
266  // and the caller wants to perform that instruction's operation on an
267  // address that has displacement Offset. Return the opcode of a suitable
268  // instruction (which might be Opcode itself) or 0 if no such instruction
269  // exists.
270  unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
271 
272  // If Opcode is a load instruction that has a LOAD AND TEST form,
273  // return the opcode for the testing form, otherwise return 0.
274  unsigned getLoadAndTest(unsigned Opcode) const;
275 
276  // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
277  // Mask of the R2 operand, given that only the low BitSize bits of Mask are
278  // significant. Set Start and End to the I3 and I4 operands if so.
279  bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
280  unsigned &Start, unsigned &End) const;
281 
282  // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
283  // operation exists, return the opcode for the latter, otherwise return 0.
284  // MI, if nonnull, is the compare instruction.
285  unsigned getFusedCompare(unsigned Opcode,
287  const MachineInstr *MI = nullptr) const;
288 
289  // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
290  // operation exists, returh the opcode for the latter, otherwise return 0.
291  unsigned getLoadAndTrap(unsigned Opcode) const;
292 
293  // Emit code before MBBI in MI to move immediate value Value into
294  // physical register Reg.
295  void loadImmediate(MachineBasicBlock &MBB,
297  unsigned Reg, uint64_t Value) const;
298 
299  // Sometimes, it is possible for the target to tell, even without
300  // aliasing information, that two MIs access different memory
301  // addresses. This function returns true if two MIs access different
302  // memory addresses and false otherwise.
303  bool
304  areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
305  AliasAnalysis *AA = nullptr) const override;
306 };
307 } // end namespace llvm
308 
309 #endif
A debug info location.
Definition: DebugLoc.h:34
const SystemZRegisterInfo & getRegisterInfo() const
struct fuzzer::@269 Flags
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Reg
All possible values of the reg field in the ModR/M byte.
MachineBasicBlock * MBB
Branch(BranchType type, unsigned ccValid, unsigned ccMask, const MachineOperand *target)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
const MachineOperand * Target
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
static unsigned getAccessSize(unsigned int Flags)
MachineInstrBuilder & UseMI
static void expandLoadStackGuard(MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
uint32_t Offset
static const unsigned End
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned getCompareZeroCCMask(unsigned int Flags)
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
Target - Wrapper for Target specific information.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static unsigned getCCValues(unsigned int Flags)
LLVM Value Representation.
Definition: Value.h:71
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
IRTranslator LLVM IR MI