25 static bool inRange(
const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
26 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
27 int64_t
Value = CE->getValue();
28 return Value >= MinValue && Value <= MaxValue;
71 SMLoc StartLoc, EndLoc;
100 unsigned MemKind : 4;
101 unsigned RegKind : 4;
128 else if (
auto *CE = dyn_cast<MCConstantExpr>(Expr))
135 SystemZOperand(OperandKind kind,
SMLoc startLoc,
SMLoc endLoc)
136 :
Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
139 static std::unique_ptr<SystemZOperand> createInvalid(
SMLoc StartLoc,
141 return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
143 static std::unique_ptr<SystemZOperand> createToken(
StringRef Str,
SMLoc Loc) {
144 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
145 Op->Token.Data = Str.
data();
146 Op->Token.Length = Str.
size();
149 static std::unique_ptr<SystemZOperand>
151 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
156 static std::unique_ptr<SystemZOperand>
158 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
162 static std::unique_ptr<SystemZOperand>
164 const MCExpr *Disp,
unsigned Index,
const MCExpr *LengthImm,
165 unsigned LengthReg,
SMLoc StartLoc,
SMLoc EndLoc) {
166 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
167 Op->Mem.MemKind = MemKind;
168 Op->Mem.RegKind = RegKind;
170 Op->Mem.Index = Index;
172 if (MemKind == BDLMem)
173 Op->Mem.Length.Imm = LengthImm;
174 if (MemKind == BDRMem)
175 Op->Mem.Length.Reg = LengthReg;
178 static std::unique_ptr<SystemZOperand>
181 auto Op = make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc);
182 Op->ImmTLS.Imm = Imm;
183 Op->ImmTLS.Sym = Sym;
188 bool isToken()
const override {
189 return Kind == KindToken;
197 bool isReg()
const override {
198 return Kind == KindReg;
201 return Kind == KindReg &&
Reg.Kind == RegKind;
203 unsigned getReg()
const override {
209 bool isImm()
const override {
210 return Kind == KindImm;
212 bool isImm(int64_t MinValue, int64_t MaxValue)
const {
213 return Kind == KindImm &&
inRange(Imm, MinValue, MaxValue);
215 const MCExpr *getImm()
const {
216 assert(
Kind == KindImm &&
"Not an immediate");
221 bool isImmTLS()
const {
222 return Kind == KindImmTLS;
226 bool isMem()
const override {
227 return Kind == KindMem;
230 return (
Kind == KindMem &&
231 (Mem.MemKind == MemKind ||
234 (Mem.MemKind == BDMem && MemKind == BDXMem)));
237 return isMem(MemKind) && Mem.RegKind == RegKind;
240 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, 0, 0xfff);
243 return isMem(MemKind, RegKind) &&
inRange(Mem.Disp, -524288, 524287);
246 return isMemDisp12(BDLMem, RegKind) &&
inRange(Mem.Length.Imm, 1, 0x100);
250 SMLoc getStartLoc()
const override {
return StartLoc; }
251 SMLoc getEndLoc()
const override {
return EndLoc; }
256 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
257 assert(N == 1 &&
"Invalid number of operands");
260 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
261 assert(N == 1 &&
"Invalid number of operands");
262 addExpr(Inst, getImm());
264 void addBDAddrOperands(
MCInst &Inst,
unsigned N)
const {
265 assert(N == 2 &&
"Invalid number of operands");
268 addExpr(Inst, Mem.Disp);
270 void addBDXAddrOperands(
MCInst &Inst,
unsigned N)
const {
271 assert(N == 3 &&
"Invalid number of operands");
274 addExpr(Inst, Mem.Disp);
277 void addBDLAddrOperands(
MCInst &Inst,
unsigned N)
const {
278 assert(N == 3 &&
"Invalid number of operands");
281 addExpr(Inst, Mem.Disp);
282 addExpr(Inst, Mem.Length.Imm);
284 void addBDRAddrOperands(
MCInst &Inst,
unsigned N)
const {
285 assert(N == 3 &&
"Invalid number of operands");
288 addExpr(Inst, Mem.Disp);
291 void addBDVAddrOperands(
MCInst &Inst,
unsigned N)
const {
292 assert(N == 3 &&
"Invalid number of operands");
295 addExpr(Inst, Mem.Disp);
298 void addImmTLSOperands(
MCInst &Inst,
unsigned N)
const {
299 assert(N == 2 &&
"Invalid number of operands");
300 assert(
Kind == KindImmTLS &&
"Invalid operand type");
301 addExpr(Inst, ImmTLS.Imm);
303 addExpr(Inst, ImmTLS.Sym);
307 bool isGR32()
const {
return isReg(GR32Reg); }
308 bool isGRH32()
const {
return isReg(GRH32Reg); }
309 bool isGRX32()
const {
return false; }
310 bool isGR64()
const {
return isReg(GR64Reg); }
311 bool isGR128()
const {
return isReg(GR128Reg); }
312 bool isADDR32()
const {
return isReg(ADDR32Reg); }
313 bool isADDR64()
const {
return isReg(ADDR64Reg); }
314 bool isADDR128()
const {
return false; }
315 bool isFP32()
const {
return isReg(FP32Reg); }
316 bool isFP64()
const {
return isReg(FP64Reg); }
317 bool isFP128()
const {
return isReg(FP128Reg); }
318 bool isVR32()
const {
return isReg(VR32Reg); }
319 bool isVR64()
const {
return isReg(VR64Reg); }
320 bool isVF128()
const {
return false; }
321 bool isVR128()
const {
return isReg(VR128Reg); }
322 bool isAR32()
const {
return isReg(AR32Reg); }
323 bool isAnyReg()
const {
return (
isReg() || isImm(0, 15)); }
324 bool isBDAddr32Disp12()
const {
return isMemDisp12(BDMem, ADDR32Reg); }
325 bool isBDAddr32Disp20()
const {
return isMemDisp20(BDMem, ADDR32Reg); }
326 bool isBDAddr64Disp12()
const {
return isMemDisp12(BDMem, ADDR64Reg); }
327 bool isBDAddr64Disp20()
const {
return isMemDisp20(BDMem, ADDR64Reg); }
328 bool isBDXAddr64Disp12()
const {
return isMemDisp12(BDXMem, ADDR64Reg); }
329 bool isBDXAddr64Disp20()
const {
return isMemDisp20(BDXMem, ADDR64Reg); }
330 bool isBDLAddr64Disp12Len8()
const {
return isMemDisp12Len8(ADDR64Reg); }
331 bool isBDRAddr64Disp12()
const {
return isMemDisp12(BDRMem, ADDR64Reg); }
332 bool isBDVAddr64Disp12()
const {
return isMemDisp12(BDVMem, ADDR64Reg); }
333 bool isU1Imm()
const {
return isImm(0, 1); }
334 bool isU2Imm()
const {
return isImm(0, 3); }
335 bool isU3Imm()
const {
return isImm(0, 7); }
336 bool isU4Imm()
const {
return isImm(0, 15); }
337 bool isU6Imm()
const {
return isImm(0, 63); }
338 bool isU8Imm()
const {
return isImm(0, 255); }
339 bool isS8Imm()
const {
return isImm(-128, 127); }
340 bool isU12Imm()
const {
return isImm(0, 4095); }
341 bool isU16Imm()
const {
return isImm(0, 65535); }
342 bool isS16Imm()
const {
return isImm(-32768, 32767); }
343 bool isU32Imm()
const {
return isImm(0, (1LL << 32) - 1); }
344 bool isS32Imm()
const {
return isImm(-(1LL << 31), (1LL << 31) - 1); }
345 bool isU48Imm()
const {
return isImm(0, (1LL << 48) - 1); }
349 #define GET_ASSEMBLER_HEADER
350 #include "SystemZGenAsmMatcher.inc"
363 SMLoc StartLoc, EndLoc;
368 bool parseRegister(
Register &
Reg, RegisterGroup Group,
const unsigned *
Regs,
369 bool IsAddress =
false);
372 RegisterGroup Group,
const unsigned *
Regs,
377 bool parseAddress(
bool &HaveReg1,
Register &Reg1,
382 bool ParseDirectiveInsn(
SMLoc L);
389 int64_t MaxVal,
bool AllowTLS);
404 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
408 bool ParseDirective(
AsmToken DirectiveID)
override;
409 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
412 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
415 bool MatchingInlineAsm)
override;
467 return parseAnyRegister(Operands);
488 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1,
false);
491 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1,
false);
494 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1,
false);
497 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1,
false);
500 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1,
true);
503 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1,
true);
508 #define GET_REGISTER_MATCHER
509 #define GET_SUBTARGET_FEATURE_NAME
510 #define GET_MATCHER_IMPLEMENTATION
511 #include "SystemZGenAsmMatcher.inc"
519 MatchClassKind OperandKinds[5];
538 {
"e", SystemZ::InsnE, 1,
540 {
"ri", SystemZ::InsnRI, 3,
541 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } },
542 {
"rie", SystemZ::InsnRIE, 4,
543 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
544 {
"ril", SystemZ::InsnRIL, 3,
545 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } },
546 {
"rilu", SystemZ::InsnRILU, 3,
547 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } },
548 {
"ris", SystemZ::InsnRIS, 5,
549 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } },
550 {
"rr", SystemZ::InsnRR, 3,
551 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } },
552 {
"rre", SystemZ::InsnRRE, 3,
553 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } },
554 {
"rrf", SystemZ::InsnRRF, 5,
555 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } },
556 {
"rrs", SystemZ::InsnRRS, 5,
557 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } },
558 {
"rs", SystemZ::InsnRS, 4,
559 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
560 {
"rse", SystemZ::InsnRSE, 4,
561 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } },
562 {
"rsi", SystemZ::InsnRSI, 4,
563 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } },
564 {
"rsy", SystemZ::InsnRSY, 4,
565 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } },
566 {
"rx", SystemZ::InsnRX, 3,
567 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
568 {
"rxe", SystemZ::InsnRXE, 3,
569 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
570 {
"rxf", SystemZ::InsnRXF, 4,
571 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } },
572 {
"rxy", SystemZ::InsnRXY, 3,
573 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } },
574 {
"s", SystemZ::InsnS, 2,
575 { MCK_U32Imm, MCK_BDAddr64Disp12 } },
576 {
"si", SystemZ::InsnSI, 3,
577 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } },
578 {
"sil", SystemZ::InsnSIL, 3,
579 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } },
580 {
"siy", SystemZ::InsnSIY, 3,
581 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } },
582 {
"ss", SystemZ::InsnSS, 4,
583 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
584 {
"sse", SystemZ::InsnSSE, 3,
585 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
586 {
"ssf", SystemZ::InsnSSF, 4,
587 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
590 void SystemZOperand::print(
raw_ostream &OS)
const {
595 bool SystemZAsmParser::parseRegister(
Register &
Reg) {
596 Reg.StartLoc = Parser.getTok().getLoc();
600 return Error(Parser.getTok().getLoc(),
"register expected");
605 return Error(Reg.StartLoc,
"invalid register");
610 return Error(Reg.StartLoc,
"invalid register");
615 return Error(Reg.StartLoc,
"invalid register");
618 if (Prefix ==
'r' && Reg.Num < 16)
620 else if (Prefix ==
'f' && Reg.Num < 16)
622 else if (Prefix ==
'v' && Reg.Num < 32)
624 else if (Prefix ==
'a' && Reg.Num < 16)
627 return Error(Reg.StartLoc,
"invalid register");
629 Reg.EndLoc = Parser.getTok().getLoc();
640 bool SystemZAsmParser::parseRegister(
Register &Reg, RegisterGroup Group,
641 const unsigned *
Regs,
bool IsAddress) {
642 if (parseRegister(Reg))
644 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV))
645 return Error(Reg.StartLoc,
"invalid operand for instruction");
646 if (Regs && Regs[Reg.Num] == 0)
647 return Error(Reg.StartLoc,
"invalid register pair");
648 if (Reg.Num == 0 && IsAddress)
649 return Error(Reg.StartLoc,
"%r0 used in an address");
651 Reg.Num = Regs[Reg.Num];
657 SystemZAsmParser::parseRegister(
OperandVector &Operands, RegisterGroup Group,
663 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
664 if (parseRegister(Reg, Group, Regs, IsAddress))
667 Operands.
push_back(SystemZOperand::createReg(Kind, Reg.Num,
668 Reg.StartLoc, Reg.EndLoc));
674 SystemZAsmParser::parseAnyRegister(
OperandVector &Operands) {
678 SMLoc StartLoc = Parser.getTok().getLoc();
679 if (Parser.parseExpression(Register))
682 if (
auto *CE = dyn_cast<MCConstantExpr>(Register)) {
683 int64_t
Value =
CE->getValue();
685 Error(StartLoc,
"invalid register");
693 Operands.
push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
697 if (parseRegister(Reg))
703 if (Reg.Group == RegGR) {
707 else if (Reg.Group == RegFP) {
711 else if (Reg.Group == RegV) {
715 else if (Reg.Group == RegAR) {
723 Operands.
push_back(SystemZOperand::createReg(Kind, RegNo,
724 Reg.StartLoc, Reg.EndLoc));
730 bool SystemZAsmParser::parseAddress(
bool &HaveReg1, Register &Reg1,
731 bool &HaveReg2, Register &Reg2,
735 if (getParser().parseExpression(Disp))
748 if (parseRegister(Reg1))
752 if (getParser().parseExpression(Length))
760 if (parseRegister(Reg2))
766 return Error(Parser.getTok().getLoc(),
"unexpected token in address");
774 SystemZAsmParser::parseAddressRegister(Register &Reg) {
775 if (Reg.Group == RegV) {
776 Error(Reg.StartLoc,
"invalid use of vector addressing");
778 }
else if (Reg.Group != RegGR) {
779 Error(Reg.StartLoc,
"invalid address register");
781 }
else if (Reg.Num == 0) {
782 Error(Reg.StartLoc,
"%r0 used in an address");
793 SMLoc StartLoc = Parser.getTok().getLoc();
794 unsigned Base = 0, Index = 0, LengthReg = 0;
796 bool HaveReg1, HaveReg2;
799 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
806 if (parseAddressRegister(Reg1))
808 Base = Regs[Reg1.Num];
812 Error(StartLoc,
"invalid use of length addressing");
816 Error(StartLoc,
"invalid use of indexed addressing");
823 if (parseAddressRegister(Reg1))
828 Index = Regs[Reg1.Num];
830 Base = Regs[Reg1.Num];
834 if (parseAddressRegister(Reg2))
836 Base = Regs[Reg2.Num];
840 Error(StartLoc,
"invalid use of length addressing");
847 if (parseAddressRegister(Reg2))
849 Base = Regs[Reg2.Num];
852 if (HaveReg1 && HaveReg2) {
853 Error(StartLoc,
"invalid use of indexed addressing");
858 Error(StartLoc,
"missing length in address");
864 if (!HaveReg1 || Reg1.Group != RegGR) {
865 Error(StartLoc,
"invalid operand for instruction");
871 if (parseAddressRegister(Reg2))
873 Base = Regs[Reg2.Num];
877 Error(StartLoc,
"invalid use of length addressing");
883 if (!HaveReg1 || Reg1.Group != RegV) {
884 Error(StartLoc,
"vector index required in address");
890 if (parseAddressRegister(Reg2))
892 Base = Regs[Reg2.Num];
896 Error(StartLoc,
"invalid use of length addressing");
904 Operands.
push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
905 Index, Length, LengthReg,
910 bool SystemZAsmParser::ParseDirective(
AsmToken DirectiveID) {
913 if (IDVal ==
".insn")
914 return ParseDirectiveInsn(DirectiveID.
getLoc());
921 bool SystemZAsmParser::ParseDirectiveInsn(
SMLoc L) {
928 return Error(ErrorLoc,
"expected instruction format");
938 if (EntryRange.first == EntryRange.second)
939 return Error(ErrorLoc,
"unrecognized format");
954 return Error(StartLoc,
"unexpected token in directive");
959 if (Kind == MCK_AnyReg)
960 ResTy = parseAnyReg(Operands);
961 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
962 ResTy = parseBDXAddr64(Operands);
963 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
964 ResTy = parseBDAddr64(Operands);
965 else if (Kind == MCK_PCRel32)
966 ResTy = parsePCRel32(Operands);
967 else if (Kind == MCK_PCRel16)
968 ResTy = parsePCRel16(Operands);
976 return Error(StartLoc,
"unexpected token in directive");
981 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
992 for (
size_t i = 0;
i < Operands.
size();
i++) {
997 unsigned Res = validateOperandClass(Operand, Kind);
998 if (Res != Match_Success)
1002 SystemZOperand &ZOperand =
static_cast<SystemZOperand &
>(Operand);
1003 if (ZOperand.isReg())
1004 ZOperand.addRegOperands(Inst, 1);
1005 else if (ZOperand.isMem(BDMem))
1006 ZOperand.addBDAddrOperands(Inst, 2);
1007 else if (ZOperand.isMem(BDXMem))
1008 ZOperand.addBDXAddrOperands(Inst, 3);
1009 else if (ZOperand.isImm())
1010 ZOperand.addImmOperands(Inst, 1);
1021 bool SystemZAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
1024 if (parseRegister(Reg))
1026 if (Reg.Group == RegGR)
1028 else if (Reg.Group == RegFP)
1030 else if (Reg.Group == RegV)
1032 else if (Reg.Group == RegAR)
1034 StartLoc = Reg.StartLoc;
1035 EndLoc = Reg.EndLoc;
1042 Operands.
push_back(SystemZOperand::createToken(Name, NameLoc));
1047 if (parseOperand(Operands, Name)) {
1054 if (parseOperand(Operands, Name)) {
1059 SMLoc Loc = getLexer().getLoc();
1060 return Error(Loc,
"unexpected token in argument list");
1069 bool SystemZAsmParser::parseOperand(
OperandVector &Operands,
1076 uint64_t AvailableFeatures = getAvailableFeatures();
1077 setAvailableFeatures(~(uint64_t)0);
1079 setAvailableFeatures(AvailableFeatures);
1095 if (parseRegister(Reg))
1097 Operands.
push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
1105 Register Reg1, Reg2;
1106 bool HaveReg1, HaveReg2;
1109 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
1113 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
1114 && parseAddressRegister(Reg1))
1116 if (HaveReg2 && parseAddressRegister(Reg2))
1121 if (HaveReg1 || HaveReg2 || Length)
1122 Operands.
push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
1124 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
1128 bool SystemZAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &
Opcode,
1132 bool MatchingInlineAsm) {
1134 unsigned MatchResult;
1136 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
1138 switch (MatchResult) {
1144 case Match_MissingFeature: {
1145 assert(ErrorInfo &&
"Unknown missing feature!");
1148 std::string Msg =
"instruction requires:";
1150 for (
unsigned I = 0;
I <
sizeof(ErrorInfo) * 8 - 1; ++
I) {
1151 if (ErrorInfo & Mask) {
1157 return Error(IDLoc, Msg);
1160 case Match_InvalidOperand: {
1161 SMLoc ErrorLoc = IDLoc;
1162 if (ErrorInfo != ~0ULL) {
1163 if (ErrorInfo >= Operands.
size())
1164 return Error(IDLoc,
"too few operands for instruction");
1166 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
1167 if (ErrorLoc ==
SMLoc())
1170 return Error(ErrorLoc,
"invalid operand for instruction");
1173 case Match_MnemonicFail:
1174 return Error(IDLoc,
"invalid instruction");
1181 SystemZAsmParser::parsePCRel(
OperandVector &Operands, int64_t MinVal,
1182 int64_t MaxVal,
bool AllowTLS) {
1187 if (getParser().parseExpression(Expr))
1192 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
1193 int64_t Value =
CE->getValue();
1195 Error(StartLoc,
"offset out of range");
1206 const MCExpr *Sym =
nullptr;
1217 if (Name ==
"tls_gdcall")
1219 else if (Name ==
"tls_ldcall")
1248 Operands.
push_back(SystemZOperand::createImmTLS(Expr, Sym,
1251 Operands.
push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
static bool isReg(const MCInst &MI, unsigned OpNo)
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
void push_back(const T &Elt)
const_iterator end(StringRef path)
Get end iterator over path.
const unsigned GR32Regs[16]
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
const char * getPointer() const
const unsigned FP128Regs[16]
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Generic assembler parser interface, for use by target specific assembly parsers.
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
static MCOperand createExpr(const MCExpr *Val)
MCTargetAsmParser - Generic interface to target specific assembly parsers.
MatchClassKind OperandKinds[5]
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
bool isNot(TokenKind K) const
const_iterator begin(StringRef path)
Get begin iterator over path.
const unsigned FP32Regs[16]
static struct InsnMatchEntry InsnMatchTable[]
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
const unsigned VR64Regs[32]
static MCOperand createReg(unsigned Reg)
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
const unsigned AR32Regs[16]
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
Target independent representation for an assembler token.
Windows NT (Windows on ARM)
const unsigned GRH32Regs[16]
static bool isMem(const MachineInstr &MI, unsigned Op)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
Context object for machine code objects.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Instances of this class represent a single low-level machine instruction.
virtual void addAliasForDirective(StringRef Directive, StringRef Alias)=0
Streaming machine code generation interface.
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Interface to description of machine instruction set.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
void LLVMInitializeSystemZAsmParser()
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
const unsigned FP64Regs[16]
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
Promote Memory to Register
const unsigned GR128Regs[16]
bool is(TokenKind K) const
const unsigned GR64Regs[16]
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
static SMLoc getFromPointer(const char *Ptr)
Target & getTheSystemZTarget()
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
MCSubtargetInfo - Generic base class for all target subtargets.
const unsigned VR32Regs[32]
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
This class implements an extremely fast bulk output stream that can only output to a stream...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
virtual bool parseIdentifier(StringRef &Res)=0
Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents...
Represents a location in source code.
static const char * getSubtargetFeatureName(uint64_t Val)
static MCOperand createImm(int64_t Val)
const unsigned VR128Regs[32]