37 unsigned RDFCount = 0;
53 return "Hexagon RDF optimizations";
81 bool interpretAsCopy(
const MachineInstr *
MI, EqualityMap &EM)
override;
96 bool HexagonCP::interpretAsCopy(
const MachineInstr *
MI, EqualityMap &EM) {
98 EM.insert(std::make_pair(DstR, SrcR));
104 case Hexagon::A2_combinew: {
115 case Hexagon::A2_addi: {
121 case Hexagon::A2_tfr: {
134 bool HexagonDCE::run() {
135 bool Collected = collect();
151 R2I.insert(std::make_pair(RA.Id, SA.
Id));
163 bool Changed =
false;
168 Changed |= rewrite(SA, Remove);
171 return erase(Remove) || Changed;
188 OpMap.
insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp())));
193 unsigned N = OpMap[RA.Id];
197 RA.Addr->setRegRef(&MI->
getOperand(N-1), DFG);
203 if (!getDFG().IsCode<NodeAttrs::Stmt>(IA))
211 unsigned OpNum, NewOpc;
213 case Hexagon::L2_loadri_pi:
214 NewOpc = Hexagon::L2_loadri_io;
217 case Hexagon::L2_loadrd_pi:
218 NewOpc = Hexagon::L2_loadrd_io;
221 case Hexagon::V6_vL32b_pi:
222 NewOpc = Hexagon::V6_vL32b_ai;
225 case Hexagon::S2_storeri_pi:
226 NewOpc = Hexagon::S2_storeri_io;
229 case Hexagon::S2_storerd_pi:
230 NewOpc = Hexagon::S2_storerd_io;
233 case Hexagon::V6_vS32b_pi:
234 NewOpc = Hexagon::V6_vS32b_ai;
241 return getDeadNodes().count(DA.Id);
246 if (&DA.Addr->getOp() != &
Op)
249 if (!
all_of(Defs, IsDead))
259 dbgs() <<
"Rewriting: " <<
MI;
262 removeOperand(IA, OpNum);
274 if (RDFLimit.getPosition()) {
275 if (RDFCount >= RDFLimit)
280 MDT = &getAnalysis<MachineDominatorTree>();
281 const auto &MDF = getAnalysis<MachineDominanceFrontier>();
288 MF.
print(
dbgs() <<
"Before " << getPassName() <<
"\n",
nullptr);
298 dbgs() <<
"Starting copy propagation on: " << MF.
getName() <<
'\n'
305 dbgs() <<
"Starting dead code elimination on: " << MF.
getName() <<
'\n'
307 HexagonDCE DCE(
G, *
MRI);
309 Changed |= DCE.run();
313 dbgs() <<
"Starting liveness recomputation on: " << MF.
getName() <<
'\n';
322 MF.
print(
dbgs() <<
"After " << getPassName() <<
"\n",
nullptr);
329 return new HexagonRDFOpt();
NodeList members(const DataFlowGraph &G) const
void initializeHexagonRDFOptPass(PassRegistry &)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const TargetInstrInfo & getTII() const
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static GCRegistry::Add< StatepointGC > D("statepoint-example","an example strategy for statepoint")
std::vector< NodeAddr< NodeBase * > > NodeList
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool insert(const value_type &X)
Insert a new element into the SetVector.
static bool IsDef(const NodeAddr< NodeBase * > BA)
Function Alias Analysis false
NodeList members_if(Predicate P, const DataFlowGraph &G) const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
initializer< Ty > init(const Ty &Val)
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
static bool IsCode(const NodeAddr< NodeBase * > BA)
unsigned getSubReg() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
FunctionPass * createHexagonRDFOpt()
MachineOperand class - Representation of each machine instruction operand.
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
NodeAddr< FuncNode * > getFunc() const
void setPreservesAll()
Set by analyses that do not transform their input at all.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
void build(unsigned Options=BuildOptions::None)
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream...
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineInstr * getCode() const
A vector that has set insertion semantics.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
NodeAddr< T > addr(NodeId N) const
StringRef - Represent a constant reference to a string, i.e.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Properties which a MachineFunction may have at a given point in time.