15 #ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
16 #define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H
62 if (!
f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State,
true))
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
84 assert((!Reg || Reg == ARM::R3) &&
"Wrong GPRs usage for f64");
98 for (i = 0; i < 2; ++
i)
99 if (HiRegList[i] == Reg)
104 assert(T == LoRegList[i] &&
"Could not allocate register");
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
134 for (i = 0; i < 2; ++
i)
135 if (HiRegList[i] == Reg)
166 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
167 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
168 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
170 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
187 if (PendingMembers.
size() > 0)
188 assert(PendingMembers[0].getLocVT() == LocVT);
203 unsigned StackAlign = DL.getStackAlignment();
204 unsigned Align =
std::min(PendingMembers[0].getExtraInfo(), StackAlign);
214 unsigned RegAlign =
alignTo(Align, 4) / 4;
215 while (RegIdx % RegAlign != 0 && RegIdx < RegList.
size())
237 It != PendingMembers.
end(); ++It) {
238 It->convertToReg(RegResult);
242 PendingMembers.
clear();
252 for (
auto &It : PendingMembers) {
253 if (RegIdx >= RegList.
size())
256 It.convertToReg(State.
AllocateReg(RegList[RegIdx++]));
260 PendingMembers.clear();
266 for (
auto Reg : RegList)
269 for (
auto &It : PendingMembers) {
280 PendingMembers.clear();
void push_back(const T &Elt)
static CCValAssign getPending(unsigned ValNo, MVT ValVT, MVT LocVT, LocInfo HTP, unsigned ExtraInfo=0)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getSizeInBits() const
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void addLoc(const CCValAssign &V)
Reg
All possible values of the reg field in the ModR/M byte.
static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail)
static const MCPhysReg RRegList[]
SmallVectorImpl< llvm::CCValAssign > & getPendingLocs()
MachineFunction & getMachineFunction() const
bool isInConsecutiveRegsLast() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
static const MCPhysReg GPRArgRegs[]
size_t size() const
size - Get the array size.
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set, or Regs.size() if they are all allocated.
MVT - Machine Value Type.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State)
static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
CCState - This class holds information needed while lowering arguments and return values...
unsigned AllocateRegBlock(ArrayRef< MCPhysReg > Regs, unsigned RegsRequired)
AllocateRegBlock - Attempt to allocate a block of RegsRequired consecutive registers.
static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const MCPhysReg QRegList[]
static const MCPhysReg DRegList[]
unsigned getOrigAlign() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
static const MCPhysReg SRegList[]