28 { SystemZ::R2D, 0x10 },
29 { SystemZ::R3D, 0x18 },
30 { SystemZ::R4D, 0x20 },
31 { SystemZ::R5D, 0x28 },
32 { SystemZ::R6D, 0x30 },
33 { SystemZ::R7D, 0x38 },
34 { SystemZ::R8D, 0x40 },
35 { SystemZ::R9D, 0x48 },
36 { SystemZ::R10D, 0x50 },
37 { SystemZ::R11D, 0x58 },
38 { SystemZ::R12D, 0x60 },
39 { SystemZ::R13D, 0x68 },
40 { SystemZ::R14D, 0x70 },
41 { SystemZ::R15D, 0x78 },
42 { SystemZ::F0D, 0x80 },
43 { SystemZ::F2D, 0x88 },
44 { SystemZ::F4D, 0x90 },
45 { SystemZ::F6D, 0x98 }
54 RegSpillOffsets.
grow(SystemZ::NUM_TARGET_REGS);
56 RegSpillOffsets[SpillOffsetTable[
I].
Reg] = SpillOffsetTable[
I].
Offset;
62 return SpillOffsetTable;
72 bool HasFP =
hasFP(MF);
86 SavedRegs.
set(SystemZ::R6D);
87 SavedRegs.
set(SystemZ::R7D);
93 SavedRegs.
set(SystemZ::R11D);
98 SavedRegs.
set(SystemZ::R14D);
105 for (
unsigned I = 0; CSRegs[
I]; ++
I) {
106 unsigned Reg = CSRegs[
I];
107 if (SystemZ::GR64BitRegClass.
contains(Reg) && SavedRegs.
test(Reg)) {
108 SavedRegs.
set(SystemZ::R15D);
119 unsigned GPR64,
bool IsImplicit) {
122 unsigned GPR32 = RI->
getSubReg(GPR64, SystemZ::subreg_l32);
124 if (!IsLive || !IsImplicit) {
134 const std::vector<CalleeSavedInfo> &CSI,
147 unsigned HighGPR = SystemZ::R15D;
148 unsigned StartOffset = -1U;
149 for (
unsigned I = 0,
E = CSI.size();
I !=
E; ++
I) {
150 unsigned Reg = CSI[
I].getReg();
151 if (SystemZ::GR64BitRegClass.
contains(Reg)) {
153 assert(Offset &&
"Unexpected GPR save");
154 if (StartOffset > Offset) {
173 if (StartOffset > Offset) {
181 assert(LowGPR != HighGPR &&
"Should be saving %r15 and something else");
195 for (
unsigned I = 0,
E = CSI.size();
I !=
E; ++
I) {
196 unsigned Reg = CSI[
I].getReg();
197 if (SystemZ::GR64BitRegClass.
contains(Reg))
208 for (
unsigned I = 0,
E = CSI.size();
I !=
E; ++
I) {
209 unsigned Reg = CSI[
I].getReg();
210 if (SystemZ::FP64BitRegClass.
contains(Reg)) {
213 &SystemZ::FP64BitRegClass, TRI);
223 const std::vector<CalleeSavedInfo> &CSI,
231 bool HasFP =
hasFP(MF);
235 for (
unsigned I = 0,
E = CSI.size();
I !=
E; ++
I) {
236 unsigned Reg = CSI[
I].getReg();
237 if (SystemZ::FP64BitRegClass.
contains(Reg))
239 &SystemZ::FP64BitRegClass, TRI);
246 unsigned StartOffset = RegSpillOffsets[LowGPR];
251 assert(LowGPR != HighGPR &&
"Should be loading %r15 and something else");
261 MIB.
addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
265 for (
unsigned I = 0,
E = CSI.size();
I !=
E; ++
I) {
266 unsigned Reg = CSI[
I].getReg();
267 if (Reg != LowGPR && Reg != HighGPR &&
268 SystemZ::GR64BitRegClass.
contains(Reg))
282 if (!isUInt<12>(MaxReach)) {
296 unsigned Reg, int64_t NumBytes,
300 int64_t ThisVal = NumBytes;
302 Opcode = SystemZ::AGHI;
304 Opcode = SystemZ::AGFI;
306 int64_t MinVal = -uint64_t(1) << 31;
307 int64_t MaxVal = (int64_t(1) << 31) - 8;
308 if (ThisVal < MinVal)
310 else if (ThisVal > MaxVal)
314 .addReg(Reg).
addImm(ThisVal);
323 assert(&MF.
front() == &MBB &&
"Shrink-wrapping not yet supported");
331 const std::vector<CalleeSavedInfo> &CSI = MFFrame.getCalleeSavedInfo();
332 bool HasFP =
hasFP(MF);
343 if (MBBI != MBB.
end() && MBBI->getOpcode() == SystemZ::STMG)
349 for (
auto &Save : CSI) {
350 unsigned Reg = Save.getReg();
351 if (SystemZ::GR64BitRegClass.
contains(Reg)) {
352 int64_t
Offset = SPOffsetFromCFA + RegSpillOffsets[
Reg];
355 BuildMI(MBB, MBBI, DL, ZII->
get(TargetOpcode::CFI_INSTRUCTION))
356 .addCFIIndex(CFIIndex);
369 BuildMI(MBB, MBBI, DL, ZII->
get(SystemZ::LGR))
373 int64_t Delta = -int64_t(StackSize);
379 BuildMI(MBB, MBBI, DL, ZII->
get(TargetOpcode::CFI_INSTRUCTION))
380 .addCFIIndex(CFIIndex);
381 SPOffsetFromCFA += Delta;
384 BuildMI(MBB, MBBI, DL, ZII->
get(SystemZ::STG))
390 BuildMI(MBB, MBBI, DL, ZII->
get(SystemZ::LGR), SystemZ::R11D)
391 .addReg(SystemZ::R15D);
397 BuildMI(MBB, MBBI, DL, ZII->
get(TargetOpcode::CFI_INSTRUCTION))
398 .addCFIIndex(CFIIndex);
403 for (
auto I = std::next(MF.
begin()),
E = MF.
end();
I !=
E; ++
I)
404 I->addLiveIn(SystemZ::R11D);
409 for (
auto &Save : CSI) {
410 unsigned Reg = Save.getReg();
411 if (SystemZ::FP64BitRegClass.
contains(Reg)) {
412 if (MBBI != MBB.
end() &&
413 (MBBI->getOpcode() == SystemZ::STD ||
414 MBBI->getOpcode() == SystemZ::STDY))
421 unsigned IgnoredFrameReg;
426 nullptr, DwarfReg, SPOffsetFromCFA + Offset));
432 for (
auto CFIIndex : CFIIndexes) {
433 BuildMI(MBB, MBBI, DL, ZII->
get(TargetOpcode::CFI_INSTRUCTION))
434 .addCFIIndex(CFIIndex);
446 assert(MBBI->isReturn() &&
"Can only insert epilogue into returning blocks");
451 unsigned Opcode = MBBI->getOpcode();
452 if (Opcode != SystemZ::LMG)
455 unsigned AddrOpNo = 2;
457 uint64_t
Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
458 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
463 uint64_t NumBytes = Offset - 0x7fff8;
464 emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
467 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
468 assert(NewOpcode &&
"No restore instruction available");
471 MBBI->setDesc(ZII->get(NewOpcode));
472 MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
473 }
else if (StackSize) {
487 unsigned &FrameReg)
const {
538 switch (MI->getOpcode()) {
539 case SystemZ::ADJCALLSTACKDOWN:
540 case SystemZ::ADJCALLSTACKUP:
542 "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
543 return MBB.
erase(MI);
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const int64_t CallFrameSize
static void emitIncrement(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, unsigned Reg, int64_t NumBytes, const TargetInstrInfo *TII)
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
constexpr bool isInt< 16 >(int64_t x)
void setIsDead(bool Val=true)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const unsigned NumArgGPRs
static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
return AArch64::GPR64RegClass contains(Reg)
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineBasicBlock & front() const
int getOffsetAdjustment() const
Return the correction for frame offsets.
Function Alias Analysis false
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
unsigned getHighSavedGPR() const
unsigned getKillRegState(bool B)
unsigned estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
This file declares the machine register scavenger class.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
const int64_t CFAOffsetFromInitialSP
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getLowSavedGPR() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool hasCalls() const
Return true if the current function has any function calls.
static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, unsigned GPR64, bool IsImplicit)
const MCContext & getContext() const
void setHighSavedGPR(unsigned Reg)
uint64_t getAllocatedStackSize(const MachineFunction &MF) const
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
bool test(unsigned Idx) const
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Information about stack frame layout on the target.
void setLowSavedGPR(unsigned Reg)
const MCRegisterInfo * getRegisterInfo() const
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Representation of each machine instruction.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBII, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
unsigned getImplRegState(bool B)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Create a new statically sized stack object, returning a nonnegative identifier to represent it...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
const MCPhysReg ArgGPRs[NumArgGPRs]
unsigned getVarArgsFirstGPR() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineModuleInfo & getMMI() const
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const std::vector< CalleeSavedInfo > &CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
This class contains meta information specific to a module.