LLVM  4.0.0
HexagonTargetMachine.cpp
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1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Hexagon target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonTargetMachine.h"
15 #include "Hexagon.h"
16 #include "HexagonISelLowering.h"
20 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/IR/Module.h"
26 #include "llvm/Transforms/Scalar.h"
27 
28 using namespace llvm;
29 
31  cl::init(true), cl::desc("Enable RDF-based optimizations"));
32 
33 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
34  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
35 
36 static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
38  cl::desc("Disable Hexagon Addressing Mode Optimization"));
39 
40 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
42  cl::desc("Disable Hexagon CFG Optimization"));
43 
44 static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden,
45  cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"));
46 
47 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
48  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
49 
50 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
52  cl::desc("Early expansion of MUX"));
53 
54 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
55  cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
56 
57 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
58  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
59 
60 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
61  cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
62 
63 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
64  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
65 
66 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
67  cl::desc("Enable converting conditional transfers into MUX instructions"));
68 
69 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
70  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
71  "predicate instructions"));
72 
73 static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch",
75  cl::desc("Enable loop data prefetch on Hexagon"));
76 
77 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
78  cl::desc("Disable splitting double registers"));
79 
80 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
81  cl::Hidden, cl::desc("Bit simplification"));
82 
83 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
84  cl::Hidden, cl::desc("Loop rescheduling"));
85 
86 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
87  cl::Hidden, cl::desc("Disable backend optimizations"));
88 
89 static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print",
91  cl::desc("Enable Hexagon Vector print instr pass"));
92 
93 /// HexagonTargetMachineModule - Note that this is used on hosts that
94 /// cannot link in a library unless there are references into the
95 /// library. In particular, it seems that it is not possible to get
96 /// things to work on Win32 without this. Though it is unused, do not
97 /// remove it.
100 
101 extern "C" void LLVMInitializeHexagonTarget() {
102  // Register the target.
104 }
105 
107  return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
108 }
109 
111 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
113 
114 namespace llvm {
115  extern char &HexagonExpandCondsetsID;
117 
133  CodeGenOpt::Level OptLevel);
145 } // end namespace llvm;
146 
148  if (!RM.hasValue())
149  return Reloc::Static;
150  return *RM;
151 }
152 
154  StringRef CPU, StringRef FS,
155  const TargetOptions &Options,
157  CodeModel::Model CM,
159  // Specify the vector alignment explicitly. For v512x1, the calculated
160  // alignment would be 512*alignment(i1), which is 512 bytes, instead of
161  // the required minimum of 64 bytes.
163  T, "e-m:e-p:32:32:32-a:0-n16:32-"
164  "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
165  "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
166  TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
167  (HexagonNoOpt ? CodeGenOpt::None : OL)),
170  initAsmInfo();
171 }
172 
173 const HexagonSubtarget *
175  AttributeSet FnAttrs = F.getAttributes();
176  Attribute CPUAttr =
177  FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
178  Attribute FSAttr =
179  FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
180 
181  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
182  ? CPUAttr.getValueAsString().str()
183  : TargetCPU;
184  std::string FS = !FSAttr.hasAttribute(Attribute::None)
185  ? FSAttr.getValueAsString().str()
186  : TargetFS;
187 
188  auto &I = SubtargetMap[CPU + FS];
189  if (!I) {
190  // This needs to be done before we create a new subtarget since any
191  // creation will depend on the TM and the code generation flags on the
192  // function that reside in TargetOptions.
194  I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
195  }
196  return I.get();
197 }
198 
200  return TargetIRAnalysis([this](const Function &F) {
201  return TargetTransformInfo(HexagonTTIImpl(this, F));
202  });
203 }
204 
205 
207 
208 namespace {
209 /// Hexagon Code Generator Pass Configuration Options.
210 class HexagonPassConfig : public TargetPassConfig {
211 public:
212  HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
213  : TargetPassConfig(TM, PM) {}
214 
215  HexagonTargetMachine &getHexagonTargetMachine() const {
216  return getTM<HexagonTargetMachine>();
217  }
218 
220  createMachineScheduler(MachineSchedContext *C) const override {
221  return createVLIWMachineSched(C);
222  }
223 
224  void addIRPasses() override;
225  bool addInstSelector() override;
226  void addPreRegAlloc() override;
227  void addPostRegAlloc() override;
228  void addPreSched2() override;
229  void addPreEmitPass() override;
230 };
231 } // namespace
232 
234  return new HexagonPassConfig(this, PM);
235 }
236 
237 void HexagonPassConfig::addIRPasses() {
239  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
240 
241  addPass(createAtomicExpandPass(TM));
242  if (!NoOpt) {
243  if (EnableLoopPrefetch)
244  addPass(createLoopDataPrefetchPass());
245  if (EnableCommGEP)
246  addPass(createHexagonCommonGEP());
247  // Replace certain combinations of shifts and ands with extracts.
248  if (EnableGenExtract)
249  addPass(createHexagonGenExtract());
250  }
251 }
252 
253 bool HexagonPassConfig::addInstSelector() {
254  HexagonTargetMachine &TM = getHexagonTargetMachine();
255  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
256 
257  if (!NoOpt)
259 
260  addPass(createHexagonISelDag(TM, getOptLevel()));
261 
262  if (!NoOpt) {
263  // Create logical operations on predicate registers.
264  if (EnableGenPred)
265  addPass(createHexagonGenPredicate(), false);
266  // Rotate loops to expose bit-simplification opportunities.
267  if (EnableLoopResched)
268  addPass(createHexagonLoopRescheduling(), false);
269  // Split double registers.
270  if (!DisableHSDR)
271  addPass(createHexagonSplitDoubleRegs());
272  // Bit simplification.
273  if (EnableBitSimplify)
274  addPass(createHexagonBitSimplify(), false);
275  addPass(createHexagonPeephole());
276  printAndVerify("After hexagon peephole pass");
277  // Constant propagation.
278  if (!DisableHCP) {
279  addPass(createHexagonConstPropagationPass(), false);
280  addPass(&UnreachableMachineBlockElimID, false);
281  }
282  if (EnableGenInsert)
283  addPass(createHexagonGenInsert(), false);
284  if (EnableEarlyIf)
285  addPass(createHexagonEarlyIfConversion(), false);
286  }
287 
288  return false;
289 }
290 
291 void HexagonPassConfig::addPreRegAlloc() {
292  if (getOptLevel() != CodeGenOpt::None) {
296  addPass(createHexagonStoreWidening(), false);
298  addPass(createHexagonHardwareLoops(), false);
299  }
300  if (TM->getOptLevel() >= CodeGenOpt::Default)
301  addPass(&MachinePipelinerID);
302 }
303 
304 void HexagonPassConfig::addPostRegAlloc() {
305  if (getOptLevel() != CodeGenOpt::None) {
306  if (EnableRDFOpt)
307  addPass(createHexagonRDFOpt());
309  addPass(createHexagonCFGOptimizer(), false);
310  if (!DisableAModeOpt)
311  addPass(createHexagonOptAddrMode(), false);
312  }
313 }
314 
315 void HexagonPassConfig::addPreSched2() {
316  addPass(createHexagonCopyToCombine(), false);
317  if (getOptLevel() != CodeGenOpt::None)
318  addPass(&IfConverterID, false);
320 }
321 
322 void HexagonPassConfig::addPreEmitPass() {
323  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
324 
325  if (!NoOpt)
326  addPass(createHexagonNewValueJump(), false);
327 
328  addPass(createHexagonBranchRelaxation(), false);
329 
330  // Create Packets.
331  if (!NoOpt) {
333  addPass(createHexagonFixupHwLoops(), false);
334  // Generate MUX from pairs of conditional transfers.
335  if (EnableGenMux)
336  addPass(createHexagonGenMux(), false);
337 
338  addPass(createHexagonPacketizer(), false);
339  }
340  if (EnableVectorPrint)
341  addPass(createHexagonVectorPrint(), false);
342 
343  // Add CFI instructions if necessary.
344  addPass(createHexagonCallFrameInformation(), false);
345 }
const NoneType None
Definition: None.h:23
FunctionPass * createHexagonCopyToCombine()
char & HexagonExpandCondsetsID
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool hasValue() const
Definition: Optional.h:125
Extend the standard ScheduleDAGMI to provide more context and override the top-level schedule() drive...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createHexagonVectorPrint()
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable loop data prefetch on Hexagon"))
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Analysis pass providing the TargetTransformInfo.
static cl::opt< bool > DisableHCP("disable-hcp", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation"))
static MachineSchedRegistry SchedCustomRegistry("hexagon","Run Hexagon's custom scheduler", createVLIWMachineSched)
FunctionPass * createHexagonHardwareLoops()
MachineSchedRegistry provides a selection of available machine instruction schedulers.
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:185
FunctionPass * createHexagonGenPredicate()
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHexagonCommonGEP()
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable RDF-based optimizations"))
FunctionPass * createHexagonOptimizeSZextends()
FunctionPass * createAtomicExpandPass(const TargetMachine *TM)
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
No attributes have been set.
Definition: Attributes.h:69
Target-Independent Code Generator Pass Configuration Options.
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
#define F(x, y, z)
Definition: MD5.cpp:51
FunctionPass * createHexagonBitSimplify()
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to ""predicate instructions"))
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Early expansion of MUX"))
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable early if-conversion"))
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, CodeModel::Model CM, CodeGenOpt::Level OL)
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
FunctionPass * createHexagonConstPropagationPass()
This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon Vector print instr pass"))
FunctionPass * createHexagonEarlyIfConversion()
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
std::enable_if<!std::is_array< T >::value, std::unique_ptr< T > >::type make_unique(Args &&...args)
Constructs a new T() with the given args and returns a unique_ptr<T> which owns the object...
Definition: STLExtras.h:845
FunctionPass * createHexagonPacketizer()
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"))
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon Addressing Mode Optimization"))
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon CFG Optimization"))
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
FunctionPass * createHexagonSplitDoubleRegs()
FunctionPass * createHexagonLoopRescheduling()
TargetIRAnalysis getTargetIRAnalysis() override
Get a TargetIRAnalysis implementation for the target.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:225
FunctionPass * createHexagonStoreWidening()
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
FunctionPass * createHexagonBranchRelaxation()
FunctionPass * createHexagonNewValueJump()
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
FunctionPass * createHexagonRDFOpt()
Module.h This file contains the declarations for the Module class.
FunctionPass * createHexagonGenMux()
FunctionPass * createHexagonPeephole()
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
FunctionPass * createHexagonGenInsert()
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:176
Target - Wrapper for Target specific information.
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
FunctionPass * createHexagonCallFrameInformation()
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
FunctionPass * createHexagonSplitConst32AndConst64()
FunctionPass * createHexagonFixupHwLoops()
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:54
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
Attribute getAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return the attribute object that exists at the given index.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:178
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
FunctionPass * createHexagonGenExtract()
FunctionPass * createHexagonOptAddrMode()
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:40
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
void initializeHexagonExpandCondsetsPass(PassRegistry &)
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
void LLVMInitializeHexagonTarget()
Target & getTheHexagonTarget()
FunctionPass * createHexagonCFGOptimizer()