LLVM  4.0.0
ExpandPostRAPseudos.cpp
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1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
11 // instructions after register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Support/Debug.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "postrapseudos"
29 
30 namespace {
31 struct ExpandPostRA : public MachineFunctionPass {
32 private:
33  const TargetRegisterInfo *TRI;
34  const TargetInstrInfo *TII;
35 
36 public:
37  static char ID; // Pass identification, replacement for typeid
38  ExpandPostRA() : MachineFunctionPass(ID) {}
39 
40  void getAnalysisUsage(AnalysisUsage &AU) const override {
41  AU.setPreservesCFG();
45  }
46 
47  /// runOnMachineFunction - pass entry point
48  bool runOnMachineFunction(MachineFunction&) override;
49 
50 private:
51  bool LowerSubregToReg(MachineInstr *MI);
52  bool LowerCopy(MachineInstr *MI);
53 
54  void TransferImplicitOperands(MachineInstr *MI);
55 };
56 } // end anonymous namespace
57 
58 char ExpandPostRA::ID = 0;
60 
61 INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
62  "Post-RA pseudo instruction expansion pass", false, false)
63 
64 /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
65 /// replacement instructions immediately precede it. Copy any implicit
66 /// operands from MI to the replacement instruction.
67 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
69  --CopyMI;
70 
71  for (const MachineOperand &MO : MI->implicit_operands())
72  if (MO.isReg())
73  CopyMI->addOperand(MO);
74 }
75 
76 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
78  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
79  MI->getOperand(1).isImm() &&
80  (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
81  MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
82 
83  unsigned DstReg = MI->getOperand(0).getReg();
84  unsigned InsReg = MI->getOperand(2).getReg();
85  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
86  unsigned SubIdx = MI->getOperand(3).getImm();
87 
88  assert(SubIdx != 0 && "Invalid index for insert_subreg");
89  unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
90 
92  "Insert destination must be in a physical register");
94  "Inserted value must be in a physical register");
95 
96  DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
97 
98  if (MI->allDefsAreDead()) {
99  MI->setDesc(TII->get(TargetOpcode::KILL));
100  DEBUG(dbgs() << "subreg: replaced by: " << *MI);
101  return true;
102  }
103 
104  if (DstSubReg == InsReg) {
105  // No need to insert an identity copy instruction.
106  // Watch out for case like this:
107  // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
108  // We must leave %RAX live.
109  if (DstReg != InsReg) {
110  MI->setDesc(TII->get(TargetOpcode::KILL));
111  MI->RemoveOperand(3); // SubIdx
112  MI->RemoveOperand(1); // Imm
113  DEBUG(dbgs() << "subreg: replace by: " << *MI);
114  return true;
115  }
116  DEBUG(dbgs() << "subreg: eliminated!");
117  } else {
118  TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
119  MI->getOperand(2).isKill());
120 
121  // Implicitly define DstReg for subsequent uses.
123  --CopyMI;
124  CopyMI->addRegisterDefined(DstReg);
125  DEBUG(dbgs() << "subreg: " << *CopyMI);
126  }
127 
128  DEBUG(dbgs() << '\n');
129  MBB->erase(MI);
130  return true;
131 }
132 
133 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
134 
135  if (MI->allDefsAreDead()) {
136  DEBUG(dbgs() << "dead copy: " << *MI);
137  MI->setDesc(TII->get(TargetOpcode::KILL));
138  DEBUG(dbgs() << "replaced by: " << *MI);
139  return true;
140  }
141 
142  MachineOperand &DstMO = MI->getOperand(0);
143  MachineOperand &SrcMO = MI->getOperand(1);
144 
145  if (SrcMO.getReg() == DstMO.getReg()) {
146  DEBUG(dbgs() << "identity copy: " << *MI);
147  // No need to insert an identity copy instruction, but replace with a KILL
148  // if liveness is changed.
149  if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
150  // We must make sure the super-register gets killed. Replace the
151  // instruction with KILL.
152  MI->setDesc(TII->get(TargetOpcode::KILL));
153  DEBUG(dbgs() << "replaced by: " << *MI);
154  return true;
155  }
156  // Vanilla identity copy.
157  MI->eraseFromParent();
158  return true;
159  }
160 
161  DEBUG(dbgs() << "real copy: " << *MI);
162  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
163  DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
164 
165  if (MI->getNumOperands() > 2)
166  TransferImplicitOperands(MI);
167  DEBUG({
169  dbgs() << "replaced by: " << *(--dMI);
170  });
171  MI->eraseFromParent();
172  return true;
173 }
174 
175 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
176 /// copies.
177 ///
178 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
179  DEBUG(dbgs() << "Machine Function\n"
180  << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
181  << "********** Function: " << MF.getName() << '\n');
182  TRI = MF.getSubtarget().getRegisterInfo();
183  TII = MF.getSubtarget().getInstrInfo();
184 
185  bool MadeChange = false;
186 
187  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
188  mbbi != mbbe; ++mbbi) {
189  for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
190  mi != me;) {
191  MachineInstr &MI = *mi;
192  // Advance iterator here because MI may be erased.
193  ++mi;
194 
195  // Only expand pseudos.
196  if (!MI.isPseudo())
197  continue;
198 
199  // Give targets a chance to expand even standard pseudos.
200  if (TII->expandPostRAPseudo(MI)) {
201  MadeChange = true;
202  continue;
203  }
204 
205  // Expand standard pseudos.
206  switch (MI.getOpcode()) {
207  case TargetOpcode::SUBREG_TO_REG:
208  MadeChange |= LowerSubregToReg(&MI);
209  break;
210  case TargetOpcode::COPY:
211  MadeChange |= LowerCopy(&MI);
212  break;
213  case TargetOpcode::DBG_VALUE:
214  continue;
215  case TargetOpcode::INSERT_SUBREG:
216  case TargetOpcode::EXTRACT_SUBREG:
217  llvm_unreachable("Sub-register pseudos should have been eliminated.");
218  }
219  }
220  }
221 
222  return MadeChange;
223 }
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
Definition: MachineInstr.h:416
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool isUndef() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
bool isKill() const
MachineBasicBlock * MBB
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
AnalysisUsage & addPreservedID(const void *ID)
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Represent the analysis usage information of a pass.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
INITIALIZE_PASS(ExpandPostRA,"postrapseudos","Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.