LLVM  4.0.0
llvm::SIRegisterInfo Member List

This is the complete list of members for llvm::SIRegisterInfo, including all inherited members.

AMDGPURegisterInfo()llvm::AMDGPURegisterInfo
DISPATCH_ID enum valuellvm::SIRegisterInfo
DISPATCH_PTR enum valuellvm::SIRegisterInfo
eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const overridellvm::SIRegisterInfo
findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const llvm::SIRegisterInfo
FIRST_VGPR_VALUE enum valuellvm::SIRegisterInfo
FLAT_SCRATCH_INIT enum valuellvm::SIRegisterInfo
getCalleeSavedRegs(const MachineFunction *MF) const overridellvm::AMDGPURegisterInfo
getEquivalentSGPRClass(const TargetRegisterClass *VRC) const llvm::SIRegisterInfo
getEquivalentVGPRClass(const TargetRegisterClass *SRC) const llvm::SIRegisterInfo
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const overridellvm::SIRegisterInfo
getFrameRegister(const MachineFunction &MF) const overridellvm::AMDGPURegisterInfo
getHWRegIndex(unsigned Reg) const llvm::SIRegisterInfoinline
getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU, bool Addressable) const llvm::SIRegisterInfo
getMaxNumSGPRs(const MachineFunction &MF) const llvm::SIRegisterInfo
getMaxNumVGPRs(unsigned WavesPerEU) const llvm::SIRegisterInfo
getMaxNumVGPRs(const MachineFunction &MF) const llvm::SIRegisterInfo
getMinNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU) const llvm::SIRegisterInfo
getMinNumVGPRs(unsigned WavesPerEU) const llvm::SIRegisterInfo
getMUBUFInstrOffset(const MachineInstr *MI) const llvm::SIRegisterInfo
getNumAddressableSGPRs(const SISubtarget &ST) const llvm::SIRegisterInfo
getNumDebuggerReservedVGPRs(const SISubtarget &ST) const llvm::SIRegisterInfo
getNumReservedSGPRs(const SISubtarget &ST, const SIMachineFunctionInfo &MFI) const llvm::SIRegisterInfo
getPhysRegClass(unsigned Reg) const llvm::SIRegisterInfo
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const overridellvm::SIRegisterInfo
getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const llvm::SIRegisterInfo
getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const llvm::SIRegisterInfo
getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const llvm::SIRegisterInfo
getReservedRegs(const MachineFunction &MF) const overridellvm::SIRegisterInfo
getSGPRAllocGranule() const llvm::SIRegisterInfoinline
getSGPRPressureSet() const llvm::SIRegisterInfoinline
getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const llvm::SIRegisterInfo
getSubRegFromChannel(unsigned Channel) const llvm::AMDGPURegisterInfo
getTotalNumSGPRs(const SISubtarget &ST) const llvm::SIRegisterInfo
getTotalNumVGPRs() const llvm::SIRegisterInfoinline
getVGPRAllocGranule() const llvm::SIRegisterInfoinline
getVGPRPressureSet() const llvm::SIRegisterInfoinline
hasVGPRs(const TargetRegisterClass *RC) const llvm::SIRegisterInfo
isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const overridellvm::SIRegisterInfo
isSGPRClass(const TargetRegisterClass *RC) const llvm::SIRegisterInfoinline
isSGPRClassID(unsigned RCID) const llvm::SIRegisterInfoinline
isSGPRPressureSet(unsigned SetID) const llvm::SIRegisterInfoinline
isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const llvm::SIRegisterInfoinline
isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const llvm::SIRegisterInfo
isVGPRPressureSet(unsigned SetID) const llvm::SIRegisterInfoinline
KERNARG_SEGMENT_PTR enum valuellvm::SIRegisterInfo
materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const overridellvm::SIRegisterInfo
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const overridellvm::SIRegisterInfo
opCanUseInlineConstant(unsigned OpType) const llvm::SIRegisterInfoinline
opCanUseLiteralConstant(unsigned OpType) const llvm::SIRegisterInfoinline
PreloadedValue enum namellvm::SIRegisterInfo
PRIVATE_SEGMENT_BUFFER enum valuellvm::SIRegisterInfo
PRIVATE_SEGMENT_WAVE_BYTE_OFFSET enum valuellvm::SIRegisterInfo
QUEUE_PTR enum valuellvm::SIRegisterInfo
requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const overridellvm::SIRegisterInfo
requiresFrameIndexScavenging(const MachineFunction &MF) const overridellvm::SIRegisterInfo
requiresRegisterScavenging(const MachineFunction &Fn) const overridellvm::SIRegisterInfo
requiresVirtualBaseRegisters(const MachineFunction &Fn) const overridellvm::SIRegisterInfo
reservedPrivateSegmentBufferReg(const MachineFunction &MF) const llvm::SIRegisterInfo
reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const llvm::SIRegisterInfo
resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const overridellvm::SIRegisterInfo
restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const llvm::SIRegisterInfo
shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const overridellvm::SIRegisterInfo
SIRegisterInfo()llvm::SIRegisterInfo
spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const llvm::SIRegisterInfo
trackLivenessAfterRegAlloc(const MachineFunction &MF) const overridellvm::SIRegisterInfo
WORKGROUP_ID_X enum valuellvm::SIRegisterInfo
WORKGROUP_ID_Y enum valuellvm::SIRegisterInfo
WORKGROUP_ID_Z enum valuellvm::SIRegisterInfo
WORKITEM_ID_X enum valuellvm::SIRegisterInfo
WORKITEM_ID_Y enum valuellvm::SIRegisterInfo
WORKITEM_ID_Z enum valuellvm::SIRegisterInfo