LLVM  4.0.0
Public Types | Public Member Functions | Protected Member Functions | List of all members
llvm::TargetSubtargetInfo Class Reference

TargetSubtargetInfo - Generic base class for all target subtargets. More...

#include <TargetSubtargetInfo.h>

Inheritance diagram for llvm::TargetSubtargetInfo:
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Collaboration diagram for llvm::TargetSubtargetInfo:
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Public Types

enum  AntiDepBreakMode { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }
 
typedef SmallVectorImpl< const
TargetRegisterClass * > 
RegClassVector
 

Public Member Functions

 TargetSubtargetInfo ()=delete
 
 TargetSubtargetInfo (const TargetSubtargetInfo &)=delete
 
void operator= (const TargetSubtargetInfo &)=delete
 
virtual ~TargetSubtargetInfo ()
 
virtual bool isXRaySupported () const
 
virtual const TargetInstrInfogetInstrInfo () const
 
virtual const TargetFrameLoweringgetFrameLowering () const
 
virtual const TargetLoweringgetTargetLowering () const
 
virtual const
SelectionDAGTargetInfo
getSelectionDAGInfo () const
 
virtual const CallLoweringgetCallLowering () const
 
virtual const InstructionSelectorgetInstructionSelector () const
 
virtual
RegisterScheduler::FunctionPassCtor 
getDAGScheduler (CodeGenOpt::Level) const
 Target can subclass this hook to select a different DAG scheduler. More...
 
virtual const LegalizerInfogetLegalizerInfo () const
 
virtual const TargetRegisterInfogetRegisterInfo () const
 getRegisterInfo - If register information is available, return it. More...
 
virtual const RegisterBankInfogetRegBankInfo () const
 If the information for the register banks is available, return it. More...
 
virtual const InstrItineraryDatagetInstrItineraryData () const
 getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget. More...
 
virtual unsigned resolveSchedClass (unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
 Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property. More...
 
virtual bool enableMachineScheduler () const
 True if the subtarget should run MachineScheduler after aggressive coalescing. More...
 
virtual bool enableMachineSchedDefaultSched () const
 True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler. More...
 
virtual bool enableJoinGlobalCopies () const
 True if the subtarget should enable joining global copies. More...
 
virtual bool enablePostRAScheduler () const
 True if the subtarget should run a scheduler after register allocation. More...
 
virtual bool enableAtomicExpand () const
 True if the subtarget should run the atomic expansion pass. More...
 
virtual void overrideSchedPolicy (MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const
 Override generic scheduling policy within a region. More...
 
virtual void adjustSchedDependency (SUnit *def, SUnit *use, SDep &dep) const
 
virtual AntiDepBreakMode getAntiDepBreakMode () const
 
virtual void getCriticalPathRCs (RegClassVector &CriticalPathRCs) const
 
virtual void getPostRAMutations (std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
 
virtual void getSMSMutations (std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const
 
virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler () const
 
virtual bool enableRALocalReassignment (CodeGenOpt::Level OptLevel) const
 True if the subtarget should run the local reassignment heuristic of the register allocator. More...
 
virtual bool useAA () const
 Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.). More...
 
virtual bool enableEarlyIfConversion () const
 Enable the use of the early if conversion pass. More...
 
virtual std::unique_ptr
< PBQPRAConstraint
getCustomPBQPConstraints () const
 Return PBQPConstraint(s) for the target. More...
 
virtual bool enableSubRegLiveness () const
 Enable tracking of subregister liveness in register allocator. More...
 
- Public Member Functions inherited from llvm::MCSubtargetInfo
 MCSubtargetInfo (const MCSubtargetInfo &)=default
 
 MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
 
const TriplegetTargetTriple () const
 getTargetTriple - Return the target triple string. More...
 
StringRef getCPU () const
 getCPU - Return the CPU string. More...
 
const FeatureBitsetgetFeatureBits () const
 getFeatureBits - Return the feature bits. More...
 
void setFeatureBits (const FeatureBitset &FeatureBits_)
 setFeatureBits - Set the feature bits. More...
 
void setDefaultFeatures (StringRef CPU, StringRef FS)
 Set the features to the default for the given CPU with an appended feature string. More...
 
FeatureBitset ToggleFeature (uint64_t FB)
 ToggleFeature - Toggle a feature and returns the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (const FeatureBitset &FB)
 ToggleFeature - Toggle a feature and returns the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (StringRef FS)
 ToggleFeature - Toggle a set of features and returns the re-computed feature bits. More...
 
FeatureBitset ApplyFeatureFlag (StringRef FS)
 Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag. More...
 
const MCSchedModelgetSchedModelForCPU (StringRef CPU) const
 getSchedModelForCPU - Get the machine model of a CPU. More...
 
const MCSchedModelgetSchedModel () const
 Get the machine model for this subtarget's CPU. More...
 
const MCWriteProcResEntrygetWriteProcResBegin (const MCSchedClassDesc *SC) const
 Return an iterator at the first process resource consumed by the given scheduling class. More...
 
const MCWriteProcResEntrygetWriteProcResEnd (const MCSchedClassDesc *SC) const
 
const MCWriteLatencyEntrygetWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const
 
int getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
 
InstrItineraryData getInstrItineraryForCPU (StringRef CPU) const
 getInstrItineraryForCPU - Get scheduling itinerary of a CPU. More...
 
void initInstrItins (InstrItineraryData &InstrItins) const
 Initialize an InstrItineraryData instance. More...
 
bool isCPUStringValid (StringRef CPU) const
 Check whether the CPU string is valid. More...
 

Protected Member Functions

 TargetSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetFeatureKV > PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
 
- Protected Member Functions inherited from llvm::MCSubtargetInfo
void InitMCProcessorInfo (StringRef CPU, StringRef FS)
 Initialize the scheduling model and feature bits. More...
 

Detailed Description

TargetSubtargetInfo - Generic base class for all target subtargets.

All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.

Definition at line 52 of file TargetSubtargetInfo.h.

Member Typedef Documentation

Definition at line 67 of file TargetSubtargetInfo.h.

Member Enumeration Documentation

Enumerator
ANTIDEP_NONE 
ANTIDEP_CRITICAL 
ANTIDEP_ALL 

Definition at line 66 of file TargetSubtargetInfo.h.

Constructor & Destructor Documentation

TargetSubtargetInfo::TargetSubtargetInfo ( const Triple TT,
StringRef  CPU,
StringRef  FS,
ArrayRef< SubtargetFeatureKV PF,
ArrayRef< SubtargetFeatureKV PD,
const SubtargetInfoKV ProcSched,
const MCWriteProcResEntry WPR,
const MCWriteLatencyEntry WL,
const MCReadAdvanceEntry RA,
const InstrStage IS,
const unsigned OC,
const unsigned FP 
)
protected

Definition at line 20 of file TargetSubtargetInfo.cpp.

llvm::TargetSubtargetInfo::TargetSubtargetInfo ( )
delete
llvm::TargetSubtargetInfo::TargetSubtargetInfo ( const TargetSubtargetInfo )
delete
TargetSubtargetInfo::~TargetSubtargetInfo ( )
virtual

Definition at line 29 of file TargetSubtargetInfo.cpp.

Member Function Documentation

virtual void llvm::TargetSubtargetInfo::adjustSchedDependency ( SUnit def,
SUnit use,
SDep dep 
) const
inlinevirtual

Definition at line 175 of file TargetSubtargetInfo.h.

Referenced by llvm::ScheduleDAGInstrs::addVRegDefDeps().

bool TargetSubtargetInfo::enableAtomicExpand ( ) const
virtual

True if the subtarget should run the atomic expansion pass.

Definition at line 31 of file TargetSubtargetInfo.cpp.

virtual bool llvm::TargetSubtargetInfo::enableEarlyIfConversion ( ) const
inlinevirtual

Enable the use of the early if conversion pass.

Definition at line 217 of file TargetSubtargetInfo.h.

bool TargetSubtargetInfo::enableJoinGlobalCopies ( ) const
virtual

True if the subtarget should enable joining global copies.

By default this is enabled if the machine scheduler is enabled, but can be overridden.

Definition at line 39 of file TargetSubtargetInfo.cpp.

References enableMachineScheduler().

virtual bool llvm::TargetSubtargetInfo::enableMachineSchedDefaultSched ( ) const
inlinevirtual

True if the machine scheduler should disable the TLI preference for preRA scheduling with the source level scheduler.

Definition at line 148 of file TargetSubtargetInfo.h.

Referenced by llvm::createDefaultScheduler().

bool TargetSubtargetInfo::enableMachineScheduler ( ) const
virtual

True if the subtarget should run MachineScheduler after aggressive coalescing.

This currently replaces the SelectionDAG scheduler with the "source" order scheduler (though see below for an option to turn this off and use the TargetLowering preference). It does not yet disable the postRA scheduler.

Definition at line 35 of file TargetSubtargetInfo.cpp.

Referenced by llvm::createDefaultScheduler(), and enableJoinGlobalCopies().

bool TargetSubtargetInfo::enablePostRAScheduler ( ) const
virtual

True if the subtarget should run a scheduler after register allocation.

By default this queries the PostRAScheduling bit in the scheduling model which is the preferred way to influence this.

Definition at line 48 of file TargetSubtargetInfo.cpp.

References llvm::MCSubtargetInfo::getSchedModel(), and llvm::MCSchedModel::PostRAScheduler.

bool TargetSubtargetInfo::enableRALocalReassignment ( CodeGenOpt::Level  OptLevel) const
virtual

True if the subtarget should run the local reassignment heuristic of the register allocator.

This heuristic may be compile time intensive, OptLevel provides a finer grain to tune the register allocator.

Definition at line 43 of file TargetSubtargetInfo.cpp.

virtual bool llvm::TargetSubtargetInfo::enableSubRegLiveness ( ) const
inlinevirtual

Enable tracking of subregister liveness in register allocator.

Please use MachineRegisterInfo::subRegLivenessEnabled() instead where possible.

Definition at line 229 of file TargetSubtargetInfo.h.

virtual AntiDepBreakMode llvm::TargetSubtargetInfo::getAntiDepBreakMode ( ) const
inlinevirtual

Definition at line 179 of file TargetSubtargetInfo.h.

References ANTIDEP_NONE.

virtual const CallLowering* llvm::TargetSubtargetInfo::getCallLowering ( ) const
inlinevirtual
virtual void llvm::TargetSubtargetInfo::getCriticalPathRCs ( RegClassVector CriticalPathRCs) const
inlinevirtual

Definition at line 184 of file TargetSubtargetInfo.h.

References llvm::SmallVectorImpl< T >::clear().

virtual std::unique_ptr<PBQPRAConstraint> llvm::TargetSubtargetInfo::getCustomPBQPConstraints ( ) const
inlinevirtual

Return PBQPConstraint(s) for the target.

Override to provide custom PBQP constraints.

Definition at line 222 of file TargetSubtargetInfo.h.

virtual RegisterScheduler::FunctionPassCtor llvm::TargetSubtargetInfo::getDAGScheduler ( CodeGenOpt::Level  ) const
inlinevirtual

Target can subclass this hook to select a different DAG scheduler.

Definition at line 106 of file TargetSubtargetInfo.h.

Referenced by llvm::createDefaultScheduler().

virtual const TargetFrameLowering* llvm::TargetSubtargetInfo::getFrameLowering ( ) const
inlinevirtual
virtual const TargetInstrInfo* llvm::TargetSubtargetInfo::getInstrInfo ( ) const
inlinevirtual

Definition at line 86 of file TargetSubtargetInfo.h.

Referenced by llvm::MachineBasicBlock::addLiveIn(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), llvm::MachineBasicBlock::canFallThrough(), llvm::MachineBasicBlock::canSplitCriticalEdge(), llvm::computeBlockSize(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createSourceListDAGScheduler(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), emitComments(), llvm::SparcFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), llvm::SystemZFrameLowering::emitEpilogue(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), llvm::NVPTXFrameLowering::emitPrologue(), llvm::SparcFrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), llvm::SystemZFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitThumb2LoadConstPool(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::getFuncletMembership(), llvm::ARMHazardRecognizer::getHazardType(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::SDNode::getOperationName(), getTargetIndexName(), llvm::ConvergingVLIWScheduler::initialize(), llvm::PostGenericScheduler::initialize(), llvm::TailDuplicator::initMF(), insertCSRSpillsAndRestores(), llvm::HexagonInstrInfo::isComplex(), llvm::AArch64CallLowering::lowerCall(), llvm::MachineSSAUpdater::MachineSSAUpdater(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), MIsNeedChainEdge(), llvm::MachineInstr::print(), llvm::MIPrinter::printTargetFlags(), propagateSwiftErrorVRegs(), llvm::TargetInstrInfo::reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), replaceFI(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::X86AsmPrinter::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::Mips16RegisterInfo::saveScavengerRegister(), llvm::FunctionLoweringInfo::set(), setCallTargetReg(), llvm::MachineIRBuilder::setMF(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), llvm::MachineBasicBlock::updateTerminator(), and llvm::VLIWResourceModel::VLIWResourceModel().

virtual const InstrItineraryData* llvm::TargetSubtargetInfo::getInstrItineraryData ( ) const
inlinevirtual

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.

Definition at line 124 of file TargetSubtargetInfo.h.

Referenced by llvm::R600InstrInfo::CreateTargetScheduleState(), llvm::HexagonInstrInfo::CreateTargetScheduleState(), and llvm::HexagonInstrInfo::getUnits().

virtual const InstructionSelector* llvm::TargetSubtargetInfo::getInstructionSelector ( ) const
inlinevirtual
virtual const LegalizerInfo* llvm::TargetSubtargetInfo::getLegalizerInfo ( ) const
inlinevirtual
virtual CodeGenOpt::Level llvm::TargetSubtargetInfo::getOptLevelToEnablePostRAScheduler ( ) const
inlinevirtual

Definition at line 202 of file TargetSubtargetInfo.h.

References llvm::CodeGenOpt::Default.

virtual void llvm::TargetSubtargetInfo::getPostRAMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation >> &  Mutations) const
inlinevirtual

Definition at line 190 of file TargetSubtargetInfo.h.

virtual const RegisterBankInfo* llvm::TargetSubtargetInfo::getRegBankInfo ( ) const
inlinevirtual

If the information for the register banks is available, return it.

Otherwise return nullptr.

Definition at line 119 of file TargetSubtargetInfo.h.

Referenced by llvm::AArch64CallLowering::lowerCall().

virtual const TargetRegisterInfo* llvm::TargetSubtargetInfo::getRegisterInfo ( ) const
inlinevirtual

getRegisterInfo - If register information is available, return it.

If not, return null.

Definition at line 115 of file TargetSubtargetInfo.h.

Referenced by llvm::DwarfCompileUnit::addAddress(), llvm::DwarfUnit::addBlockByrefAddress(), llvm::DwarfCompileUnit::addComplexAddress(), addLiveInRegs(), addSavedGPR(), llvm::A57ChainingConstraint::apply(), assignCalleeSavedSpillSlots(), llvm::DebugHandlerBase::beginFunction(), llvm::LiveRangeEdit::calculateRegClassAndHint(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), checkNumAlignedDPRCS2Regs(), computeLiveOuts(), llvm::TargetSchedModel::computeOutputLatency(), llvm::MIRPrinter::convertStackObjects(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createSourceListDAGScheduler(), llvm::SystemZFrameLowering::determineCalleeSaves(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::determineCalleeSaves(), llvm::TargetFrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), emitDebugLocValue(), emitDebugValueComment(), llvm::ARMFrameLowering::emitEpilogue(), llvm::MipsAsmPrinter::emitFrameDirective(), llvm::AsmPrinter::emitImplicitDef(), emitKill(), llvm::SparcFrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::MachineFrameInfo::estimateStackSize(), findScratchNonCalleeSaveRegister(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::SystemZFrameLowering::getFrameIndexReference(), llvm::TargetFrameLowering::getFrameIndexReference(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::RegisterBankInfo::getInstrMappingImpl(), getMemcpyLoadsAndStores(), llvm::MachineFrameInfo::getPristineRegs(), GetRegistersForValue(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), HandleVRSaveUpdate(), llvm::SparcFrameLowering::hasFP(), llvm::ARMFrameLowering::hasFP(), llvm::AArch64FrameLowering::hasFP(), llvm::RegPressureTracker::init(), llvm::TailDuplicator::initMF(), insertCSRSpillsAndRestores(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::AArch64CallLowering::lowerCall(), patchMatchingInput(), llvm::PhysicalRegisterUsageInfo::print(), llvm::MIRPrinter::print(), llvm::MachineFunction::print(), llvm::MachineBasicBlock::print(), llvm::MachineInstr::print(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::TargetInstrInfo::reassociateOps(), llvm::AArch64FrameLowering::resolveFrameIndexReference(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::LiveStacks::runOnMachineFunction(), llvm::X86AsmPrinter::runOnMachineFunction(), llvm::LiveVariables::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::FunctionLoweringInfo::set(), setAliasRegs(), llvm::X86MachineFunctionInfo::setRestoreBasePointer(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), UpdatePredRedefs(), and llvm::DwarfCompileUnit::updateSubprogramScopeDIE().

virtual const SelectionDAGTargetInfo* llvm::TargetSubtargetInfo::getSelectionDAGInfo ( ) const
inlinevirtual

Definition at line 91 of file TargetSubtargetInfo.h.

Referenced by llvm::SelectionDAG::init().

virtual void llvm::TargetSubtargetInfo::getSMSMutations ( std::vector< std::unique_ptr< ScheduleDAGMutation >> &  Mutations) const
inlinevirtual

Definition at line 196 of file TargetSubtargetInfo.h.

virtual const TargetLowering* llvm::TargetSubtargetInfo::getTargetLowering ( ) const
inlinevirtual
virtual bool llvm::TargetSubtargetInfo::isXRaySupported ( ) const
inlinevirtual

Definition at line 74 of file TargetSubtargetInfo.h.

void llvm::TargetSubtargetInfo::operator= ( const TargetSubtargetInfo )
delete
virtual void llvm::TargetSubtargetInfo::overrideSchedPolicy ( MachineSchedPolicy Policy,
unsigned  NumRegionInstrs 
) const
inlinevirtual

Override generic scheduling policy within a region.

This is a convenient way for targets that don't provide any custom scheduling heuristics (no custom MachineSchedStrategy) to make changes to the generic scheduling policy.

Definition at line 170 of file TargetSubtargetInfo.h.

Referenced by llvm::GenericScheduler::initPolicy().

virtual unsigned llvm::TargetSubtargetInfo::resolveSchedClass ( unsigned  SchedClass,
const MachineInstr MI,
const TargetSchedModel SchedModel 
) const
inlinevirtual

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property.

This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.

Definition at line 132 of file TargetSubtargetInfo.h.

Referenced by llvm::TargetSchedModel::resolveSchedClass().

bool TargetSubtargetInfo::useAA ( ) const
virtual

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 52 of file TargetSubtargetInfo.cpp.

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph().


The documentation for this class was generated from the following files: