26 #define DEBUG_TYPE "regalloc"
28 STATISTIC(NumDCEDeleted,
"Number of instructions deleted by DCE");
29 STATISTIC(NumDCEFoldedLoads,
"Number of single use loads folded after DCE");
30 STATISTIC(NumFracRanges,
"Number of live ranges fractured by DCE");
32 void LiveRangeEdit::Delegate::anchor() { }
61 assert(DefMI &&
"Missing instruction");
62 ScannedRemattable =
true;
65 Remattable.insert(VNI);
83 ScannedRemattable =
true;
87 if (!ScannedRemattable)
89 return !Remattable.empty();
94 bool LiveRangeEdit::allUsesAvailableAt(
const MachineInstr *OrigMI,
130 assert(ScannedRemattable &&
"Call anyRematerializable first");
133 if (!Remattable.count(OrigVNI))
138 assert(RM.
OrigMI &&
"No defining instruction for remattable value");
146 if (!allUsesAvailableAt(RM.
OrigMI, DefIdx, UseIdx))
163 (*--
MI).getOperand(0).setIsDead(
false);
181 if (DefMI && DefMI != MI)
195 if (!DefMI || !
UseMI)
210 DEBUG(
dbgs() <<
"Try to fold single def: " << *DefMI
211 <<
" into single use: " << *
UseMI);
239 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
246 void LiveRangeEdit::eliminateDeadDef(
MachineInstr *MI, ToShrinkSet &ToShrink,
257 DEBUG(
dbgs() <<
"Won't delete: " << Idx <<
'\t' << *MI);
262 bool SawStore =
false;
264 DEBUG(
dbgs() <<
"Can't delete: " << Idx <<
'\t' << *MI);
268 DEBUG(
dbgs() <<
"Deleting dead def " << Idx <<
'\t' << *MI);
272 bool ReadsPhysRegs =
false;
273 bool isOrigDef =
false;
297 unsigned Reg = MOI->getReg();
300 if (Reg && MOI->readsReg() && !MRI.
isReserved(Reg))
301 ReadsPhysRegs =
true;
302 else if (MOI->isDef())
313 (MOI->readsReg() && (MRI.
hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
314 ToShrink.insert(&LI);
342 DEBUG(
dbgs() <<
"Converted physregs to:\t" << *MI);
353 NewLI.
addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
370 for (
unsigned i = 0, e = RegsToErase.
size();
i != e; ++
i) {
371 unsigned Reg = RegsToErase[
i];
386 while (!Dead.
empty())
389 if (ToShrink.
empty())
395 if (foldAsLoad(LI, Dead))
397 unsigned VReg = LI->
reg;
407 bool BeingSpilled =
false;
408 for (
unsigned i = 0, e = RegsBeingSpilled.
size();
i != e; ++
i) {
409 if (VReg == RegsBeingSpilled[
i]) {
415 if (BeingSpilled)
continue;
421 if (!SplitLIs.
empty())
424 unsigned Original = VRM ? VRM->
getOriginal(VReg) : 0;
429 if (Original != VReg && Original != 0)
440 LiveRangeEdit::MRI_NoteNewVirtualRegister(
unsigned VReg)
456 for (
unsigned I = 0, Size =
size();
I < Size; ++
I) {
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
void push_back(const T &Elt)
mop_iterator operands_end()
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint...
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
SlotIndex def
The index of the defining instruction.
STATISTIC(NumFunctions,"Total number of functions")
void RemoveMachineInstrFromMaps(MachineInstr &MI)
bool anyRematerializable(AliasAnalysis *)
anyRematerializable - Return true if any parent values may be rematerializable.
void removePhysRegDefAt(unsigned Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
LiveInterval - This class represents the liveness of a register, or stack slot.
bool isSpillable() const
isSpillable - Can this interval be spilled?
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
bool isKill() const
Return true if the live-in value is killed by this instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
A live range for subregisters.
void setIsDead(bool Val=true)
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
VNInfo - Value Number Information.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterInfo * getTargetRegisterInfo() const
VNInfo::Allocator & getVNInfoAllocator()
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
iterator_range< subrange_iterator > subranges()
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
void pop_back()
Remove the last element of the SetVector.
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void markDeadRemat(MachineInstr *inst)
void setIsSplitFromReg(unsigned virtReg, unsigned SReg)
records virtReg is a split live interval from SReg.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FrameIndex, LiveIntervals *LIS=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
bool isBundled() const
Return true if this instruction part of a bundle.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses...
bool empty() const
Determine if the SetVector is empty or not.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
size_t size() const
size - Get the array size.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
unsigned createFrom(unsigned OldReg)
createFrom - Create a new virtual register based on OldReg.
SlotIndexes * getSlotIndexes() const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Allocate memory in an ever growing pool, as if by bump-pointer.
void removeInterval(unsigned Reg)
unsigned getOriginal(unsigned VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting...
MachineInstrBuilder & UseMI
bool isReserved(unsigned PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
const MachineOperand & getOperand(unsigned i) const
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< unsigned > RegsBeingSpilled=None, AliasAnalysis *AA=nullptr)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
virtual bool LRE_CanEraseVirtReg(unsigned)
Called when a virtual register is no longer used.
LiveInterval & getParent() const
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
MachineOperand class - Representation of each machine instruction operand.
void calculateSpillWeightAndHint(LiveInterval &li)
(re)compute li's spill weight and allocation hint.
LLVM_NODISCARD T pop_back_val()
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
LiveInterval & getInterval(unsigned Reg)
bool recomputeRegClass(unsigned Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LiveInterval & createEmptyInterval(unsigned Reg)
virtual void LRE_WillShrinkVirtReg(unsigned)
Called before shrinking the live range of a virtual register.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old)
Called after cloning a virtual register.
bool isConstantPhysReg(unsigned PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
const T & back() const
Return the last element of the SetVector.
bool hasInterval(unsigned Reg) const
Remat - Information needed to rematerialize at a specific location.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
unsigned getReg() const
getReg - Returns the register number.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(unsigned Reg) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
mop_iterator operands_begin()
LiveInterval & createEmptyIntervalFrom(unsigned OldReg)
createEmptyIntervalFrom - Create a new empty interval based on OldReg.
A vector that has set insertion semantics.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
void calculateRegClassAndHint(MachineFunction &, const MachineLoopInfo &, const MachineBlockFrequencyInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void eraseVirtReg(unsigned Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS...
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
SlotIndex - An opaque wrapper around machine indexes.
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos...