LLVM  4.0.0
Macros | Functions | Variables
PPCISelDAGToDAG.cpp File Reference
#include "PPC.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCTargetMachine.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include "PPCGenDAGISel.inc"
Include dependency graph for PPCISelDAGToDAG.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "ppc-codegen"
 

Functions

static bool isIntS16Immediate (SDNode *N, short &Imm)
 isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value. More...
 
static bool isIntS16Immediate (SDValue Op, short &Imm)
 
static bool isInt32Immediate (SDNode *N, unsigned &Imm)
 isInt32Immediate - This method tests to see if the node is a 32-bit constant operand. More...
 
static bool isInt64Immediate (SDNode *N, uint64_t &Imm)
 isInt64Immediate - This method tests to see if the node is a 64-bit constant operand. More...
 
static bool isInt32Immediate (SDValue N, unsigned &Imm)
 
static unsigned getBranchHint (unsigned PCC, FunctionLoweringInfo *FuncInfo, const SDValue &DestMBB)
 
static bool isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
 
static unsigned getInt64CountDirect (int64_t Imm)
 
static uint64_t Rot64 (uint64_t Imm, unsigned R)
 
static unsigned getInt64Count (int64_t Imm)
 
static SDNodegetInt64Direct (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm)
 
static SDNodegetInt64 (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm)
 
static SDNodegetInt64 (SelectionDAG *CurDAG, SDNode *N)
 
static PPC::Predicate getPredicateForSetCC (ISD::CondCode CC)
 
static unsigned getCRIdxForSetCC (ISD::CondCode CC, bool &Invert)
 getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted. More...
 
static unsigned int getVCmpInst (MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate)
 
static bool PeepholePPC64ZExtGather (SDValue Op32, SmallPtrSetImpl< SDNode * > &ToPromote)
 

Variables

cl::opt< boolANDIGlueBug ("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
 
static cl::opt< boolUseBitPermRewriter ("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
 
static cl::opt< boolBPermRewriterNoMasking ("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for ""bit permutations"), cl::Hidden)
 
static cl::opt< boolEnableBranchHint ("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
 

Macro Definition Documentation

#define DEBUG_TYPE   "ppc-codegen"

Definition at line 41 of file PPCISelDAGToDAG.cpp.

Function Documentation

static unsigned getBranchHint ( unsigned  PCC,
FunctionLoweringInfo FuncInfo,
const SDValue DestMBB 
)
static
static unsigned getCRIdxForSetCC ( ISD::CondCode  CC,
bool Invert 
)
static

getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.

That is, lt = 0; ge = 0 inverted.

Definition at line 2154 of file PPCISelDAGToDAG.cpp.

References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

static SDNode* getInt64 ( SelectionDAG CurDAG,
const SDLoc dl,
int64_t  Imm 
)
static
static SDNode* getInt64 ( SelectionDAG CurDAG,
SDNode N 
)
static

Definition at line 827 of file PPCISelDAGToDAG.cpp.

References getInt64(), and N.

static unsigned getInt64Count ( int64_t  Imm)
static
static unsigned getInt64CountDirect ( int64_t  Imm)
static

Definition at line 592 of file PPCISelDAGToDAG.cpp.

References llvm::isInt< 16 >(), llvm::isInt< 32 >(), and llvm::MipsISD::Lo.

Referenced by getInt64(), and getInt64Count().

static SDNode* getInt64Direct ( SelectionDAG CurDAG,
const SDLoc dl,
int64_t  Imm 
)
static
static PPC::Predicate getPredicateForSetCC ( ISD::CondCode  CC)
static
static unsigned int getVCmpInst ( MVT  VecVT,
ISD::CondCode  CC,
bool  HasVSX,
bool Swap,
bool Negate 
)
static
static bool isInt32Immediate ( SDNode N,
unsigned Imm 
)
static

isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.

If so Imm will receive the 32-bit value.

Definition at line 374 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i32, and N.

Referenced by isInt32Immediate(), and isOpcWithIntImmediate().

static bool isInt32Immediate ( SDValue  N,
unsigned Imm 
)
static

Definition at line 394 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getNode(), and isInt32Immediate().

static bool isInt64Immediate ( SDNode N,
uint64_t &  Imm 
)
static

isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 384 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i64, and N.

static bool isIntS16Immediate ( SDNode N,
short &  Imm 
)
static

isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value.

If so, this returns true and the immediate.

Definition at line 356 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i32, and N.

Referenced by isIntS16Immediate().

static bool isIntS16Immediate ( SDValue  Op,
short &  Imm 
)
static

Definition at line 367 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getNode(), and isIntS16Immediate().

static bool isOpcWithIntImmediate ( SDNode N,
unsigned  Opc,
unsigned Imm 
)
static
static bool PeepholePPC64ZExtGather ( SDValue  Op32,
SmallPtrSetImpl< SDNode * > &  ToPromote 
)
static
static uint64_t Rot64 ( uint64_t  Imm,
unsigned  R 
)
static

Definition at line 656 of file PPCISelDAGToDAG.cpp.

Referenced by getInt64(), and getInt64Count().

Variable Documentation

cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for ""bit permutations"), cl::Hidden)
static
cl::opt<bool> EnableBranchHint("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
static
cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
static