LLVM  4.0.0
AVRISelLowering.cpp
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1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AVRISelLowering.h"
16 
17 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/IR/Function.h"
26 
27 #include "AVR.h"
28 #include "AVRMachineFunctionInfo.h"
29 #include "AVRTargetMachine.h"
31 
32 namespace llvm {
33 
35  : TargetLowering(tm) {
36  // Set up the register classes.
37  addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
38  addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
39 
40  // Compute derived properties from the register classes.
42 
47 
50 
53 
54  for (MVT VT : MVT::integer_valuetypes()) {
55  for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
58  }
59  }
60 
62 
63  // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
64  // revert into a sub since we don't have an add with immediate instruction.
67 
68  // our shift instructions are only able to shift 1 bit at a time, so handle
69  // this in a custom way.
79 
85 
96 
98 
99  // Add support for postincrement and predecrement load/stores.
108 
110 
115 
116  // Atomic operations which must be lowered to rtlib calls
117  for (MVT VT : MVT::integer_valuetypes()) {
125  }
126 
127  // Division/remainder
136 
137  // Make division and modulus custom
138  for (MVT VT : MVT::integer_valuetypes()) {
141  }
142 
143  // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
146 
147  // Expand 16 bit multiplications.
150 
151  for (MVT VT : MVT::integer_valuetypes()) {
154  }
155 
156  for (MVT VT : MVT::integer_valuetypes()) {
160  }
161 
162  for (MVT VT : MVT::integer_valuetypes()) {
164  // TODO: The generated code is pretty poor. Investigate using the
165  // same "shift and subtract with carry" trick that we do for
166  // extending 8-bit to 16-bit. This may require infrastructure
167  // improvements in how we treat 16-bit "registers" to be feasible.
168  }
169 
170  // Division rtlib functions (not supported)
171  setLibcallName(RTLIB::SDIV_I8, nullptr);
176  setLibcallName(RTLIB::UDIV_I8, nullptr);
181 
182  // Modulus rtlib functions (not supported)
183  setLibcallName(RTLIB::SREM_I8, nullptr);
188  setLibcallName(RTLIB::UREM_I8, nullptr);
193 
194  // Division and modulus rtlib functions
195  setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
196  setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
197  setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
198  setLibcallName(RTLIB::SDIVREM_I64, "__divmoddi4");
199  setLibcallName(RTLIB::SDIVREM_I128, "__divmodti4");
200  setLibcallName(RTLIB::UDIVREM_I8, "__udivmodqi4");
201  setLibcallName(RTLIB::UDIVREM_I16, "__udivmodhi4");
202  setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
203  setLibcallName(RTLIB::UDIVREM_I64, "__udivmoddi4");
204  setLibcallName(RTLIB::UDIVREM_I128, "__udivmodti4");
205 
206  // Several of the runtime library functions use a special calling conv
211 
212  // Trigonometric rtlib functions
215 
218 }
219 
220 const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
221 #define NODE(name) \
222  case AVRISD::name: \
223  return #name
224 
225  switch (Opcode) {
226  default:
227  return nullptr;
228  NODE(RET_FLAG);
229  NODE(RETI_FLAG);
230  NODE(CALL);
231  NODE(WRAPPER);
232  NODE(LSL);
233  NODE(LSR);
234  NODE(ROL);
235  NODE(ROR);
236  NODE(ASR);
237  NODE(LSLLOOP);
238  NODE(LSRLOOP);
239  NODE(ASRLOOP);
240  NODE(BRCOND);
241  NODE(CMP);
242  NODE(CMPC);
243  NODE(TST);
244  NODE(SELECT_CC);
245 #undef NODE
246  }
247 }
248 
250  EVT VT) const {
251  assert(!VT.isVector() && "No AVR SetCC type for vectors!");
252  return MVT::i8;
253 }
254 
255 SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
256  //:TODO: this function has to be completely rewritten to produce optimal
257  // code, for now it's producing very long but correct code.
258  unsigned Opc8;
259  const SDNode *N = Op.getNode();
260  EVT VT = Op.getValueType();
261  SDLoc dl(N);
262 
263  // Expand non-constant shifts to loops.
264  if (!isa<ConstantSDNode>(N->getOperand(1))) {
265  switch (Op.getOpcode()) {
266  default:
267  llvm_unreachable("Invalid shift opcode!");
268  case ISD::SHL:
269  return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0),
270  N->getOperand(1));
271  case ISD::SRL:
272  return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
273  N->getOperand(1));
274  case ISD::SRA:
275  return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
276  N->getOperand(1));
277  }
278  }
279 
280  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
281  SDValue Victim = N->getOperand(0);
282 
283  switch (Op.getOpcode()) {
284  case ISD::SRA:
285  Opc8 = AVRISD::ASR;
286  break;
287  case ISD::ROTL:
288  Opc8 = AVRISD::ROL;
289  break;
290  case ISD::ROTR:
291  Opc8 = AVRISD::ROR;
292  break;
293  case ISD::SRL:
294  Opc8 = AVRISD::LSR;
295  break;
296  case ISD::SHL:
297  Opc8 = AVRISD::LSL;
298  break;
299  default:
300  llvm_unreachable("Invalid shift opcode");
301  }
302 
303  while (ShiftAmount--) {
304  Victim = DAG.getNode(Opc8, dl, VT, Victim);
305  }
306 
307  return Victim;
308 }
309 
310 SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
311  unsigned Opcode = Op->getOpcode();
312  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
313  "Invalid opcode for Div/Rem lowering");
314  bool isSigned = (Opcode == ISD::SDIVREM);
315  EVT VT = Op->getValueType(0);
316  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
317 
318  RTLIB::Libcall LC;
319  switch (VT.getSimpleVT().SimpleTy) {
320  default:
321  llvm_unreachable("Unexpected request for libcall!");
322  case MVT::i8:
323  LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
324  break;
325  case MVT::i16:
326  LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
327  break;
328  case MVT::i32:
329  LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
330  break;
331  case MVT::i64:
332  LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64;
333  break;
334  }
335 
336  SDValue InChain = DAG.getEntryNode();
337 
339  TargetLowering::ArgListEntry Entry;
340  for (SDValue const &Value : Op->op_values()) {
341  Entry.Node = Value;
342  Entry.Ty = Value.getValueType().getTypeForEVT(*DAG.getContext());
343  Entry.isSExt = isSigned;
344  Entry.isZExt = !isSigned;
345  Args.push_back(Entry);
346  }
347 
348  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
349  getPointerTy(DAG.getDataLayout()));
350 
351  Type *RetTy = (Type *)StructType::get(Ty, Ty, nullptr);
352 
353  SDLoc dl(Op);
354  TargetLowering::CallLoweringInfo CLI(DAG);
355  CLI.setDebugLoc(dl)
356  .setChain(InChain)
357  .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))
358  .setInRegister()
359  .setSExtResult(isSigned)
360  .setZExtResult(!isSigned);
361 
362  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
363  return CallInfo.first;
364 }
365 
366 SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
367  SelectionDAG &DAG) const {
368  auto DL = DAG.getDataLayout();
369 
370  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
371  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
372 
373  // Create the TargetGlobalAddress node, folding in the constant offset.
374  SDValue Result =
375  DAG.getTargetGlobalAddress(GV, SDLoc(Op), getPointerTy(DL), Offset);
376  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
377 }
378 
379 SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
380  SelectionDAG &DAG) const {
381  auto DL = DAG.getDataLayout();
382  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
383 
384  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(DL));
385 
386  return DAG.getNode(AVRISD::WRAPPER, SDLoc(Op), getPointerTy(DL), Result);
387 }
388 
389 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
391  switch (CC) {
392  default:
393  llvm_unreachable("Unknown condition code!");
394  case ISD::SETEQ:
395  return AVRCC::COND_EQ;
396  case ISD::SETNE:
397  return AVRCC::COND_NE;
398  case ISD::SETGE:
399  return AVRCC::COND_GE;
400  case ISD::SETLT:
401  return AVRCC::COND_LT;
402  case ISD::SETUGE:
403  return AVRCC::COND_SH;
404  case ISD::SETULT:
405  return AVRCC::COND_LO;
406  }
407 }
408 
409 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
410 /// the given operands.
411 SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
412  SDValue &AVRcc, SelectionDAG &DAG,
413  SDLoc DL) const {
414  SDValue Cmp;
415  EVT VT = LHS.getValueType();
416  bool UseTest = false;
417 
418  switch (CC) {
419  default:
420  break;
421  case ISD::SETLE: {
422  // Swap operands and reverse the branching condition.
423  std::swap(LHS, RHS);
424  CC = ISD::SETGE;
425  break;
426  }
427  case ISD::SETGT: {
428  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
429  switch (C->getSExtValue()) {
430  case -1: {
431  // When doing lhs > -1 use a tst instruction on the top part of lhs
432  // and use brpl instead of using a chain of cp/cpc.
433  UseTest = true;
434  AVRcc = DAG.getConstant(AVRCC::COND_PL, DL, MVT::i8);
435  break;
436  }
437  case 0: {
438  // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
439  // __zero_reg__ in lhs.
440  RHS = LHS;
441  LHS = DAG.getConstant(0, DL, VT);
442  CC = ISD::SETLT;
443  break;
444  }
445  default: {
446  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
447  // us to fold the constant into the cmp instruction.
448  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
449  CC = ISD::SETGE;
450  break;
451  }
452  }
453  break;
454  }
455  // Swap operands and reverse the branching condition.
456  std::swap(LHS, RHS);
457  CC = ISD::SETLT;
458  break;
459  }
460  case ISD::SETLT: {
461  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
462  switch (C->getSExtValue()) {
463  case 1: {
464  // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
465  // __zero_reg__ in lhs.
466  RHS = LHS;
467  LHS = DAG.getConstant(0, DL, VT);
468  CC = ISD::SETGE;
469  break;
470  }
471  case 0: {
472  // When doing lhs < 0 use a tst instruction on the top part of lhs
473  // and use brmi instead of using a chain of cp/cpc.
474  UseTest = true;
475  AVRcc = DAG.getConstant(AVRCC::COND_MI, DL, MVT::i8);
476  break;
477  }
478  }
479  }
480  break;
481  }
482  case ISD::SETULE: {
483  // Swap operands and reverse the branching condition.
484  std::swap(LHS, RHS);
485  CC = ISD::SETUGE;
486  break;
487  }
488  case ISD::SETUGT: {
489  // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
490  // fold the constant into the cmp instruction.
491  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
492  RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT);
493  CC = ISD::SETUGE;
494  break;
495  }
496  // Swap operands and reverse the branching condition.
497  std::swap(LHS, RHS);
498  CC = ISD::SETULT;
499  break;
500  }
501  }
502 
503  // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
504  // using the default and/or/xor expansion code which is much longer.
505  if (VT == MVT::i32) {
506  SDValue LHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
507  DAG.getIntPtrConstant(0, DL));
508  SDValue LHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS,
509  DAG.getIntPtrConstant(1, DL));
510  SDValue RHSlo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
511  DAG.getIntPtrConstant(0, DL));
512  SDValue RHShi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS,
513  DAG.getIntPtrConstant(1, DL));
514 
515  if (UseTest) {
516  // When using tst we only care about the highest part.
517  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHShi,
518  DAG.getIntPtrConstant(1, DL));
519  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
520  } else {
521  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHSlo, RHSlo);
522  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHShi, RHShi, Cmp);
523  }
524  } else if (VT == MVT::i64) {
525  SDValue LHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
526  DAG.getIntPtrConstant(0, DL));
527  SDValue LHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, LHS,
528  DAG.getIntPtrConstant(1, DL));
529 
530  SDValue LHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
531  DAG.getIntPtrConstant(0, DL));
532  SDValue LHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_0,
533  DAG.getIntPtrConstant(1, DL));
534  SDValue LHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
535  DAG.getIntPtrConstant(0, DL));
536  SDValue LHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, LHS_1,
537  DAG.getIntPtrConstant(1, DL));
538 
539  SDValue RHS_0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
540  DAG.getIntPtrConstant(0, DL));
541  SDValue RHS_1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, RHS,
542  DAG.getIntPtrConstant(1, DL));
543 
544  SDValue RHS0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
545  DAG.getIntPtrConstant(0, DL));
546  SDValue RHS1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_0,
547  DAG.getIntPtrConstant(1, DL));
548  SDValue RHS2 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
549  DAG.getIntPtrConstant(0, DL));
550  SDValue RHS3 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i16, RHS_1,
551  DAG.getIntPtrConstant(1, DL));
552 
553  if (UseTest) {
554  // When using tst we only care about the highest part.
555  SDValue Top = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8, LHS3,
556  DAG.getIntPtrConstant(1, DL));
557  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue, Top);
558  } else {
559  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS0, RHS0);
560  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS1, RHS1, Cmp);
561  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS2, RHS2, Cmp);
562  Cmp = DAG.getNode(AVRISD::CMPC, DL, MVT::Glue, LHS3, RHS3, Cmp);
563  }
564  } else if (VT == MVT::i8 || VT == MVT::i16) {
565  if (UseTest) {
566  // When using tst we only care about the highest part.
567  Cmp = DAG.getNode(AVRISD::TST, DL, MVT::Glue,
568  (VT == MVT::i8)
569  ? LHS
570  : DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i8,
571  LHS, DAG.getIntPtrConstant(1, DL)));
572  } else {
573  Cmp = DAG.getNode(AVRISD::CMP, DL, MVT::Glue, LHS, RHS);
574  }
575  } else {
576  llvm_unreachable("Invalid comparison size");
577  }
578 
579  // When using a test instruction AVRcc is already set.
580  if (!UseTest) {
581  AVRcc = DAG.getConstant(intCCToAVRCC(CC), DL, MVT::i8);
582  }
583 
584  return Cmp;
585 }
586 
587 SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
588  SDValue Chain = Op.getOperand(0);
589  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
590  SDValue LHS = Op.getOperand(2);
591  SDValue RHS = Op.getOperand(3);
592  SDValue Dest = Op.getOperand(4);
593  SDLoc dl(Op);
594 
595  SDValue TargetCC;
596  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
597 
598  return DAG.getNode(AVRISD::BRCOND, dl, MVT::Other, Chain, Dest, TargetCC,
599  Cmp);
600 }
601 
602 SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
603  SDValue LHS = Op.getOperand(0);
604  SDValue RHS = Op.getOperand(1);
605  SDValue TrueV = Op.getOperand(2);
606  SDValue FalseV = Op.getOperand(3);
607  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
608  SDLoc dl(Op);
609 
610  SDValue TargetCC;
611  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, dl);
612 
613  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
614  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
615 
616  return DAG.getNode(AVRISD::SELECT_CC, dl, VTs, Ops);
617 }
618 
619 SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
620  SDValue LHS = Op.getOperand(0);
621  SDValue RHS = Op.getOperand(1);
622  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
623  SDLoc DL(Op);
624 
625  SDValue TargetCC;
626  SDValue Cmp = getAVRCmp(LHS, RHS, CC, TargetCC, DAG, DL);
627 
628  SDValue TrueV = DAG.getConstant(1, DL, Op.getValueType());
629  SDValue FalseV = DAG.getConstant(0, DL, Op.getValueType());
630  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
631  SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
632 
633  return DAG.getNode(AVRISD::SELECT_CC, DL, VTs, Ops);
634 }
635 
636 SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
637  const MachineFunction &MF = DAG.getMachineFunction();
638  const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
639  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
640  auto DL = DAG.getDataLayout();
641  SDLoc dl(Op);
642 
643  // Vastart just stores the address of the VarArgsFrameIndex slot into the
644  // memory location argument.
645  SDValue FI = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), getPointerTy(DL));
646 
647  return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
648  MachinePointerInfo(SV), 0);
649 }
650 
652  switch (Op.getOpcode()) {
653  default:
654  llvm_unreachable("Don't know how to custom lower this!");
655  case ISD::SHL:
656  case ISD::SRA:
657  case ISD::SRL:
658  case ISD::ROTL:
659  case ISD::ROTR:
660  return LowerShifts(Op, DAG);
661  case ISD::GlobalAddress:
662  return LowerGlobalAddress(Op, DAG);
663  case ISD::BlockAddress:
664  return LowerBlockAddress(Op, DAG);
665  case ISD::BR_CC:
666  return LowerBR_CC(Op, DAG);
667  case ISD::SELECT_CC:
668  return LowerSELECT_CC(Op, DAG);
669  case ISD::SETCC:
670  return LowerSETCC(Op, DAG);
671  case ISD::VASTART:
672  return LowerVASTART(Op, DAG);
673  case ISD::SDIVREM:
674  case ISD::UDIVREM:
675  return LowerDivRem(Op, DAG);
676  }
677 
678  return SDValue();
679 }
680 
681 /// Replace a node with an illegal result type
682 /// with a new node built out of custom code.
685  SelectionDAG &DAG) const {
686  SDLoc DL(N);
687 
688  switch (N->getOpcode()) {
689  case ISD::ADD: {
690  // Convert add (x, imm) into sub (x, -imm).
691  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
692  SDValue Sub = DAG.getNode(
693  ISD::SUB, DL, N->getValueType(0), N->getOperand(0),
694  DAG.getConstant(-C->getAPIntValue(), DL, C->getValueType(0)));
695  Results.push_back(Sub);
696  }
697  break;
698  }
699  default: {
700  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
701 
702  for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
703  Results.push_back(Res.getValue(I));
704 
705  break;
706  }
707  }
708 }
709 
710 /// Return true if the addressing mode represented
711 /// by AM is legal for this target, for a load/store of the specified type.
713  const AddrMode &AM, Type *Ty,
714  unsigned AS) const {
715  int64_t Offs = AM.BaseOffs;
716 
717  // Allow absolute addresses.
718  if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
719  return true;
720  }
721 
722  // Flash memory instructions only allow zero offsets.
723  if (isa<PointerType>(Ty) && AS == AVR::ProgramMemory) {
724  return false;
725  }
726 
727  // Allow reg+<6bit> offset.
728  if (Offs < 0)
729  Offs = -Offs;
730  if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
731  return true;
732  }
733 
734  return false;
735 }
736 
737 /// Returns true by value, base pointer and
738 /// offset pointer and addressing mode by reference if the node's address
739 /// can be legally represented as pre-indexed load / store address.
741  SDValue &Offset,
743  SelectionDAG &DAG) const {
744  EVT VT;
745  const SDNode *Op;
746  SDLoc DL(N);
747 
748  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
749  VT = LD->getMemoryVT();
750  Op = LD->getBasePtr().getNode();
751  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
752  return false;
754  return false;
755  }
756  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
757  VT = ST->getMemoryVT();
758  Op = ST->getBasePtr().getNode();
760  return false;
761  }
762  } else {
763  return false;
764  }
765 
766  if (VT != MVT::i8 && VT != MVT::i16) {
767  return false;
768  }
769 
770  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
771  return false;
772  }
773 
774  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
775  int RHSC = RHS->getSExtValue();
776  if (Op->getOpcode() == ISD::SUB)
777  RHSC = -RHSC;
778 
779  if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
780  return false;
781  }
782 
783  Base = Op->getOperand(0);
784  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
785  AM = ISD::PRE_DEC;
786 
787  return true;
788  }
789 
790  return false;
791 }
792 
793 /// Returns true by value, base pointer and
794 /// offset pointer and addressing mode by reference if this node can be
795 /// combined with a load / store to form a post-indexed load / store.
797  SDValue &Base,
798  SDValue &Offset,
800  SelectionDAG &DAG) const {
801  EVT VT;
802  SDLoc DL(N);
803 
804  if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
805  VT = LD->getMemoryVT();
806  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
807  return false;
808  } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
809  VT = ST->getMemoryVT();
811  return false;
812  }
813  } else {
814  return false;
815  }
816 
817  if (VT != MVT::i8 && VT != MVT::i16) {
818  return false;
819  }
820 
821  if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
822  return false;
823  }
824 
825  if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
826  int RHSC = RHS->getSExtValue();
827  if (Op->getOpcode() == ISD::SUB)
828  RHSC = -RHSC;
829  if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
830  return false;
831  }
832 
833  Base = Op->getOperand(0);
834  Offset = DAG.getConstant(RHSC, DL, MVT::i8);
835  AM = ISD::POST_INC;
836 
837  return true;
838  }
839 
840  return false;
841 }
842 
844  const GlobalAddressSDNode *GA) const {
845  return true;
846 }
847 
848 //===----------------------------------------------------------------------===//
849 // Formal Arguments Calling Convention Implementation
850 //===----------------------------------------------------------------------===//
851 
852 #include "AVRGenCallingConv.inc"
853 
854 /// For each argument in a function store the number of pieces it is composed
855 /// of.
856 static void parseFunctionArgs(const Function *F, const DataLayout *TD,
858  for (Argument const &Arg : F->args()) {
859  unsigned Bytes = (TD->getTypeSizeInBits(Arg.getType()) + 7) / 8;
860  Out.push_back((Bytes + 1) / 2);
861  }
862 }
863 
864 /// For external symbols there is no function prototype information so we
865 /// have to rely directly on argument sizes.
868  for (unsigned i = 0, e = In.size(); i != e;) {
869  unsigned Size = 0;
870  unsigned Offset = 0;
871  while ((i != e) && (In[i].PartOffset == Offset)) {
872  Offset += In[i].VT.getStoreSize();
873  ++i;
874  ++Size;
875  }
876  Out.push_back(Size);
877  }
878 }
879 
881  SDValue Callee = CLI.Callee;
882 
883  if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
884  return G->getSymbol();
885  }
886 
887  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
888  return G->getGlobal()->getName();
889  }
890 
891  llvm_unreachable("don't know how to get the name for this callee");
892 }
893 
894 /// Analyze incoming and outgoing function arguments. We need custom C++ code
895 /// to handle special constraints in the ABI like reversing the order of the
896 /// pieces of splitted arguments. In addition, all pieces of a certain argument
897 /// have to be passed either using registers or the stack but never mixing both.
899  const Function *F, const DataLayout *TD,
902  CallingConv::ID CallConv,
904  CCState &CCInfo, bool IsCall, bool IsVarArg) {
905  static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
906  AVR::R18, AVR::R16, AVR::R14,
907  AVR::R12, AVR::R10, AVR::R8};
908  static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
909  AVR::R19R18, AVR::R17R16, AVR::R15R14,
910  AVR::R13R12, AVR::R11R10, AVR::R9R8};
911  if (IsVarArg) {
912  // Variadic functions do not need all the analisys below.
913  if (IsCall) {
914  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
915  } else {
916  CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
917  }
918  return;
919  }
920 
921  // Fill in the Args array which will contain original argument sizes.
923  if (IsCall) {
924  parseExternFuncCallArgs(*Outs, Args);
925  } else {
926  assert(F != nullptr && "function should not be null");
927  parseFunctionArgs(F, TD, Args);
928  }
929 
930  unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
931  // Variadic functions always use the stack.
932  bool UsesStack = false;
933  for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
934  unsigned Size = Args[i];
935  MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
936 
937  // If we have plenty of regs to pass the whole argument do it.
938  if (!UsesStack && (Size <= RegsLeft)) {
939  const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
940 
941  for (unsigned j = 0; j != Size; ++j) {
942  unsigned Reg = CCInfo.AllocateReg(
943  ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
944  CCInfo.addLoc(
945  CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
946  --RegsLeft;
947  }
948 
949  // Reverse the order of the pieces to agree with the "big endian" format
950  // required in the calling convention ABI.
951  std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
952  } else {
953  // Pass the rest of arguments using the stack.
954  UsesStack = true;
955  for (unsigned j = 0; j != Size; ++j) {
956  unsigned Offset = CCInfo.AllocateStack(
957  TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
959  EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
960  CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
962  }
963  }
964  pos += Size;
965  }
966 }
967 
969  const Function *F, const DataLayout *TD,
972  CallingConv::ID CallConv,
974  CCState &CCInfo, bool IsCall, bool IsVarArg) {
975  StringRef FuncName = getFunctionName(CLI);
976 
977  if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
978  CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
979  } else {
980  analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
981  CallConv, ArgLocs, CCInfo,
982  IsCall, IsVarArg);
983  }
984 }
985 
987  const Function *F, const DataLayout *TD,
990  CallingConv::ID CallConv,
992  CCState &CCInfo, bool IsCall, bool IsVarArg) {
993  switch (CallConv) {
995  analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
996  CallConv, ArgLocs, CCInfo,
997  IsCall, IsVarArg);
998  return;
999  }
1000  default: {
1001  analyzeStandardArguments(CLI, F, TD, Outs, Ins,
1002  CallConv, ArgLocs, CCInfo,
1003  IsCall, IsVarArg);
1004  return;
1005  }
1006  }
1007 }
1008 
1009 SDValue AVRTargetLowering::LowerFormalArguments(
1010  SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1011  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1012  SmallVectorImpl<SDValue> &InVals) const {
1013  MachineFunction &MF = DAG.getMachineFunction();
1014  MachineFrameInfo &MFI = MF.getFrameInfo();
1015  auto DL = DAG.getDataLayout();
1016 
1017  // Assign locations to all of the incoming arguments.
1018  SmallVector<CCValAssign, 16> ArgLocs;
1019  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1020  *DAG.getContext());
1021 
1022  analyzeArguments(nullptr, MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
1023  false, isVarArg);
1024 
1025  SDValue ArgValue;
1026  for (CCValAssign &VA : ArgLocs) {
1027 
1028  // Arguments stored on registers.
1029  if (VA.isRegLoc()) {
1030  EVT RegVT = VA.getLocVT();
1031  const TargetRegisterClass *RC;
1032  if (RegVT == MVT::i8) {
1033  RC = &AVR::GPR8RegClass;
1034  } else if (RegVT == MVT::i16) {
1035  RC = &AVR::DREGSRegClass;
1036  } else {
1037  llvm_unreachable("Unknown argument type!");
1038  }
1039 
1040  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1041  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1042 
1043  // :NOTE: Clang should not promote any i8 into i16 but for safety the
1044  // following code will handle zexts or sexts generated by other
1045  // front ends. Otherwise:
1046  // If this is an 8 bit value, it is really passed promoted
1047  // to 16 bits. Insert an assert[sz]ext to capture this, then
1048  // truncate to the right size.
1049  switch (VA.getLocInfo()) {
1050  default:
1051  llvm_unreachable("Unknown loc info!");
1052  case CCValAssign::Full:
1053  break;
1054  case CCValAssign::BCvt:
1055  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1056  break;
1057  case CCValAssign::SExt:
1058  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1059  DAG.getValueType(VA.getValVT()));
1060  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1061  break;
1062  case CCValAssign::ZExt:
1063  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1064  DAG.getValueType(VA.getValVT()));
1065  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1066  break;
1067  }
1068 
1069  InVals.push_back(ArgValue);
1070  } else {
1071  // Sanity check.
1072  assert(VA.isMemLoc());
1073 
1074  EVT LocVT = VA.getLocVT();
1075 
1076  // Create the frame index object for this incoming parameter.
1077  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
1078  VA.getLocMemOffset(), true);
1079 
1080  // Create the SelectionDAG nodes corresponding to a load
1081  // from this parameter.
1082  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DL));
1083  InVals.push_back(DAG.getLoad(LocVT, dl, Chain, FIN,
1085  0));
1086  }
1087  }
1088 
1089  // If the function takes variable number of arguments, make a frame index for
1090  // the start of the first vararg value... for expansion of llvm.va_start.
1091  if (isVarArg) {
1092  unsigned StackSize = CCInfo.getNextStackOffset();
1093  AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1094 
1095  AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(2, StackSize, true));
1096  }
1097 
1098  return Chain;
1099 }
1100 
1101 //===----------------------------------------------------------------------===//
1102 // Call Calling Convention Implementation
1103 //===----------------------------------------------------------------------===//
1104 
1105 SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1106  SmallVectorImpl<SDValue> &InVals) const {
1107  SelectionDAG &DAG = CLI.DAG;
1108  SDLoc &DL = CLI.DL;
1109  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1110  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1111  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1112  SDValue Chain = CLI.Chain;
1113  SDValue Callee = CLI.Callee;
1114  bool &isTailCall = CLI.IsTailCall;
1115  CallingConv::ID CallConv = CLI.CallConv;
1116  bool isVarArg = CLI.IsVarArg;
1117 
1118  MachineFunction &MF = DAG.getMachineFunction();
1119 
1120  // AVR does not yet support tail call optimization.
1121  isTailCall = false;
1122 
1123  // Analyze operands of the call, assigning locations to each operand.
1124  SmallVector<CCValAssign, 16> ArgLocs;
1125  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1126  *DAG.getContext());
1127 
1128  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1129  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1130  // node so that legalize doesn't hack it.
1131  const Function *F = nullptr;
1132  if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1133  const GlobalValue *GV = G->getGlobal();
1134 
1135  F = cast<Function>(GV);
1136  Callee =
1137  DAG.getTargetGlobalAddress(GV, DL, getPointerTy(DAG.getDataLayout()));
1138  } else if (const ExternalSymbolSDNode *ES =
1139  dyn_cast<ExternalSymbolSDNode>(Callee)) {
1140  Callee = DAG.getTargetExternalSymbol(ES->getSymbol(),
1141  getPointerTy(DAG.getDataLayout()));
1142  }
1143 
1144  analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
1145  true, isVarArg);
1146 
1147  // Get a count of how many bytes are to be pushed on the stack.
1148  unsigned NumBytes = CCInfo.getNextStackOffset();
1149 
1150  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1151  DL);
1152 
1153  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1154 
1155  // First, walk the register assignments, inserting copies.
1156  unsigned AI, AE;
1157  bool HasStackArgs = false;
1158  for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1159  CCValAssign &VA = ArgLocs[AI];
1160  EVT RegVT = VA.getLocVT();
1161  SDValue Arg = OutVals[AI];
1162 
1163  // Promote the value if needed. With Clang this should not happen.
1164  switch (VA.getLocInfo()) {
1165  default:
1166  llvm_unreachable("Unknown loc info!");
1167  case CCValAssign::Full:
1168  break;
1169  case CCValAssign::SExt:
1170  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
1171  break;
1172  case CCValAssign::ZExt:
1173  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
1174  break;
1175  case CCValAssign::AExt:
1176  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
1177  break;
1178  case CCValAssign::BCvt:
1179  Arg = DAG.getNode(ISD::BITCAST, DL, RegVT, Arg);
1180  break;
1181  }
1182 
1183  // Stop when we encounter a stack argument, we need to process them
1184  // in reverse order in the loop below.
1185  if (VA.isMemLoc()) {
1186  HasStackArgs = true;
1187  break;
1188  }
1189 
1190  // Arguments that can be passed on registers must be kept in the RegsToPass
1191  // vector.
1192  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1193  }
1194 
1195  // Second, stack arguments have to walked in reverse order by inserting
1196  // chained stores, this ensures their order is not changed by the scheduler
1197  // and that the push instruction sequence generated is correct, otherwise they
1198  // can be freely intermixed.
1199  if (HasStackArgs) {
1200  for (AE = AI, AI = ArgLocs.size(); AI != AE; --AI) {
1201  unsigned Loc = AI - 1;
1202  CCValAssign &VA = ArgLocs[Loc];
1203  SDValue Arg = OutVals[Loc];
1204 
1205  assert(VA.isMemLoc());
1206 
1207  // SP points to one stack slot further so add one to adjust it.
1208  SDValue PtrOff = DAG.getNode(
1209  ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
1210  DAG.getRegister(AVR::SP, getPointerTy(DAG.getDataLayout())),
1211  DAG.getIntPtrConstant(VA.getLocMemOffset() + 1, DL));
1212 
1213  Chain =
1214  DAG.getStore(Chain, DL, Arg, PtrOff,
1215  MachinePointerInfo::getStack(MF, VA.getLocMemOffset()),
1216  0);
1217  }
1218  }
1219 
1220  // Build a sequence of copy-to-reg nodes chained together with token chain and
1221  // flag operands which copy the outgoing args into registers. The InFlag in
1222  // necessary since all emited instructions must be stuck together.
1223  SDValue InFlag;
1224  for (auto Reg : RegsToPass) {
1225  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, InFlag);
1226  InFlag = Chain.getValue(1);
1227  }
1228 
1229  // Returns a chain & a flag for retval copy to use.
1230  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1231  SmallVector<SDValue, 8> Ops;
1232  Ops.push_back(Chain);
1233  Ops.push_back(Callee);
1234 
1235  // Add argument registers to the end of the list so that they are known live
1236  // into the call.
1237  for (auto Reg : RegsToPass) {
1238  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
1239  }
1240 
1241  // Add a register mask operand representing the call-preserved registers.
1242  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1243  const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
1244  const uint32_t *Mask =
1245  TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
1246  assert(Mask && "Missing call preserved mask for calling convention");
1247  Ops.push_back(DAG.getRegisterMask(Mask));
1248 
1249  if (InFlag.getNode()) {
1250  Ops.push_back(InFlag);
1251  }
1252 
1253  Chain = DAG.getNode(AVRISD::CALL, DL, NodeTys, Ops);
1254  InFlag = Chain.getValue(1);
1255 
1256  // Create the CALLSEQ_END node.
1257  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
1258  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
1259 
1260  if (!Ins.empty()) {
1261  InFlag = Chain.getValue(1);
1262  }
1263 
1264  // Handle result values, copying them out of physregs into vregs that we
1265  // return.
1266  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, DL, DAG,
1267  InVals);
1268 }
1269 
1270 /// Lower the result values of a call into the
1271 /// appropriate copies out of appropriate physical registers.
1272 ///
1273 SDValue AVRTargetLowering::LowerCallResult(
1274  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1275  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
1276  SmallVectorImpl<SDValue> &InVals) const {
1277 
1278  // Assign locations to each value returned by this call.
1279  SmallVector<CCValAssign, 16> RVLocs;
1280  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1281  *DAG.getContext());
1282 
1283  // Handle runtime calling convs.
1284  auto CCFunction = CCAssignFnForReturn(CallConv);
1285  CCInfo.AnalyzeCallResult(Ins, CCFunction);
1286 
1287  if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
1288  // Reverse splitted return values to get the "big endian" format required
1289  // to agree with the calling convention ABI.
1290  std::reverse(RVLocs.begin(), RVLocs.end());
1291  }
1292 
1293  // Copy all of the result registers out of their specified physreg.
1294  for (CCValAssign const &RVLoc : RVLocs) {
1295  Chain = DAG.getCopyFromReg(Chain, dl, RVLoc.getLocReg(), RVLoc.getValVT(),
1296  InFlag)
1297  .getValue(1);
1298  InFlag = Chain.getValue(2);
1299  InVals.push_back(Chain.getValue(0));
1300  }
1301 
1302  return Chain;
1303 }
1304 
1305 //===----------------------------------------------------------------------===//
1306 // Return Value Calling Convention Implementation
1307 //===----------------------------------------------------------------------===//
1308 
1309 CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
1310  switch (CC) {
1312  return RetCC_AVR_BUILTIN;
1313  default:
1314  return RetCC_AVR;
1315  }
1316 }
1317 
1318 bool
1319 AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1320  MachineFunction &MF, bool isVarArg,
1321  const SmallVectorImpl<ISD::OutputArg> &Outs,
1322  LLVMContext &Context) const
1323 {
1324  SmallVector<CCValAssign, 16> RVLocs;
1325  CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1326 
1327  auto CCFunction = CCAssignFnForReturn(CallConv);
1328  return CCInfo.CheckReturn(Outs, CCFunction);
1329 }
1330 
1331 SDValue
1332 AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1333  bool isVarArg,
1334  const SmallVectorImpl<ISD::OutputArg> &Outs,
1335  const SmallVectorImpl<SDValue> &OutVals,
1336  const SDLoc &dl, SelectionDAG &DAG) const {
1337  // CCValAssign - represent the assignment of the return value to locations.
1338  SmallVector<CCValAssign, 16> RVLocs;
1339 
1340  // CCState - Info about the registers and stack slot.
1341  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1342  *DAG.getContext());
1343 
1344  // Analyze return values.
1345  auto CCFunction = CCAssignFnForReturn(CallConv);
1346  CCInfo.AnalyzeReturn(Outs, CCFunction);
1347 
1348  // If this is the first return lowered for this function, add the regs to
1349  // the liveout set for the function.
1350  MachineFunction &MF = DAG.getMachineFunction();
1351  unsigned e = RVLocs.size();
1352 
1353  // Reverse splitted return values to get the "big endian" format required
1354  // to agree with the calling convention ABI.
1355  if (e > 1) {
1356  std::reverse(RVLocs.begin(), RVLocs.end());
1357  }
1358 
1359  SDValue Flag;
1360  SmallVector<SDValue, 4> RetOps(1, Chain);
1361  // Copy the result values into the output registers.
1362  for (unsigned i = 0; i != e; ++i) {
1363  CCValAssign &VA = RVLocs[i];
1364  assert(VA.isRegLoc() && "Can only return in registers!");
1365 
1366  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1367 
1368  // Guarantee that all emitted copies are stuck together with flags.
1369  Flag = Chain.getValue(1);
1370  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1371  }
1372 
1373  // Don't emit the ret/reti instruction when the naked attribute is present in
1374  // the function being compiled.
1375  if (MF.getFunction()->getAttributes().hasAttribute(
1376  AttributeSet::FunctionIndex, Attribute::Naked)) {
1377  return Chain;
1378  }
1379 
1380  unsigned RetOpc =
1381  (CallConv == CallingConv::AVR_INTR || CallConv == CallingConv::AVR_SIGNAL)
1383  : AVRISD::RET_FLAG;
1384 
1385  RetOps[0] = Chain; // Update chain.
1386 
1387  if (Flag.getNode()) {
1388  RetOps.push_back(Flag);
1389  }
1390 
1391  return DAG.getNode(RetOpc, dl, MVT::Other, RetOps);
1392 }
1393 
1394 //===----------------------------------------------------------------------===//
1395 // Custom Inserters
1396 //===----------------------------------------------------------------------===//
1397 
1398 MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1399  MachineBasicBlock *BB) const {
1400  unsigned Opc;
1401  const TargetRegisterClass *RC;
1402  MachineFunction *F = BB->getParent();
1403  MachineRegisterInfo &RI = F->getRegInfo();
1404  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1405  const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
1406  DebugLoc dl = MI.getDebugLoc();
1407 
1408  switch (MI.getOpcode()) {
1409  default:
1410  llvm_unreachable("Invalid shift opcode!");
1411  case AVR::Lsl8:
1412  Opc = AVR::LSLRd;
1413  RC = &AVR::GPR8RegClass;
1414  break;
1415  case AVR::Lsl16:
1416  Opc = AVR::LSLWRd;
1417  RC = &AVR::DREGSRegClass;
1418  break;
1419  case AVR::Asr8:
1420  Opc = AVR::ASRRd;
1421  RC = &AVR::GPR8RegClass;
1422  break;
1423  case AVR::Asr16:
1424  Opc = AVR::ASRWRd;
1425  RC = &AVR::DREGSRegClass;
1426  break;
1427  case AVR::Lsr8:
1428  Opc = AVR::LSRRd;
1429  RC = &AVR::GPR8RegClass;
1430  break;
1431  case AVR::Lsr16:
1432  Opc = AVR::LSRWRd;
1433  RC = &AVR::DREGSRegClass;
1434  break;
1435  }
1436 
1437  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1438  MachineFunction::iterator I = BB->getParent()->begin();
1439  ++I;
1440 
1441  // Create loop block.
1442  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1443  MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1444 
1445  F->insert(I, LoopBB);
1446  F->insert(I, RemBB);
1447 
1448  // Update machine-CFG edges by transferring all successors of the current
1449  // block to the block containing instructions after shift.
1450  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1451  BB->end());
1452  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1453 
1454  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB.
1455  BB->addSuccessor(LoopBB);
1456  BB->addSuccessor(RemBB);
1457  LoopBB->addSuccessor(RemBB);
1458  LoopBB->addSuccessor(LoopBB);
1459 
1460  unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1461  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1462  unsigned ShiftReg = RI.createVirtualRegister(RC);
1463  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1464  unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg();
1465  unsigned SrcReg = MI.getOperand(1).getReg();
1466  unsigned DstReg = MI.getOperand(0).getReg();
1467 
1468  // BB:
1469  // cp 0, N
1470  // breq RemBB
1471  BuildMI(BB, dl, TII.get(AVR::CPRdRr)).addReg(ShiftAmtSrcReg).addReg(AVR::R0);
1472  BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1473 
1474  // LoopBB:
1475  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1476  // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1477  // ShiftReg2 = shift ShiftReg
1478  // ShiftAmt2 = ShiftAmt - 1;
1479  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1480  .addReg(SrcReg)
1481  .addMBB(BB)
1482  .addReg(ShiftReg2)
1483  .addMBB(LoopBB);
1484  BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1485  .addReg(ShiftAmtSrcReg)
1486  .addMBB(BB)
1487  .addReg(ShiftAmtReg2)
1488  .addMBB(LoopBB);
1489  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1490  BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1491  .addReg(ShiftAmtReg)
1492  .addImm(1);
1493  BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1494 
1495  // RemBB:
1496  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1497  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1498  .addReg(SrcReg)
1499  .addMBB(BB)
1500  .addReg(ShiftReg2)
1501  .addMBB(LoopBB);
1502 
1503  MI.eraseFromParent(); // The pseudo instruction is gone now.
1504  return RemBB;
1505 }
1506 
1508  if (I->getOpcode() == AVR::COPY) {
1509  unsigned SrcReg = I->getOperand(1).getReg();
1510  return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1511  }
1512 
1513  return false;
1514 }
1515 
1516 // The mul instructions wreak havock on our zero_reg R1. We need to clear it
1517 // after the result has been evacuated. This is probably not the best way to do
1518 // it, but it works for now.
1519 MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
1520  MachineBasicBlock *BB) const {
1521  const AVRTargetMachine &TM = (const AVRTargetMachine &)getTargetMachine();
1522  const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
1524  ++I; // in any case insert *after* the mul instruction
1525  if (isCopyMulResult(I))
1526  ++I;
1527  if (isCopyMulResult(I))
1528  ++I;
1529  BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1530  .addReg(AVR::R1)
1531  .addReg(AVR::R1);
1532  return BB;
1533 }
1534 
1535 MachineBasicBlock *
1537  MachineBasicBlock *MBB) const {
1538  int Opc = MI.getOpcode();
1539 
1540  // Pseudo shift instructions with a non constant shift amount are expanded
1541  // into a loop.
1542  switch (Opc) {
1543  case AVR::Lsl8:
1544  case AVR::Lsl16:
1545  case AVR::Lsr8:
1546  case AVR::Lsr16:
1547  case AVR::Asr8:
1548  case AVR::Asr16:
1549  return insertShift(MI, MBB);
1550  case AVR::MULRdRr:
1551  case AVR::MULSRdRr:
1552  return insertMul(MI, MBB);
1553  }
1554 
1555  assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
1556  "Unexpected instr type to insert");
1557 
1558  const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
1559  ->getParent()
1560  ->getSubtarget()
1561  .getInstrInfo();
1562  DebugLoc dl = MI.getDebugLoc();
1563 
1564  // To "insert" a SELECT instruction, we insert the diamond
1565  // control-flow pattern. The incoming instruction knows the
1566  // destination vreg to set, the condition code register to branch
1567  // on, the true/false values to select between, and a branch opcode
1568  // to use.
1569 
1570  MachineFunction *MF = MBB->getParent();
1571  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1572  MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1573  MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1574 
1576  ++I;
1577  MF->insert(I, trueMBB);
1578  MF->insert(I, falseMBB);
1579 
1580  // Transfer remaining instructions and all successors of the current
1581  // block to the block which will contain the Phi node for the
1582  // select.
1583  trueMBB->splice(trueMBB->begin(), MBB,
1584  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
1585  trueMBB->transferSuccessorsAndUpdatePHIs(MBB);
1586 
1588  BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1589  BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1590  MBB->addSuccessor(falseMBB);
1591  MBB->addSuccessor(trueMBB);
1592 
1593  // Unconditionally flow back to the true block
1594  BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1595  falseMBB->addSuccessor(trueMBB);
1596 
1597  // Set up the Phi node to determine where we came from
1598  BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1599  .addReg(MI.getOperand(1).getReg())
1600  .addMBB(MBB)
1601  .addReg(MI.getOperand(2).getReg())
1602  .addMBB(falseMBB) ;
1603 
1604  MI.eraseFromParent(); // The pseudo instruction is gone now.
1605  return trueMBB;
1606 }
1607 
1608 //===----------------------------------------------------------------------===//
1609 // Inline Asm Support
1610 //===----------------------------------------------------------------------===//
1611 
1614  if (Constraint.size() == 1) {
1615  // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
1616  switch (Constraint[0]) {
1617  case 'a': // Simple upper registers
1618  case 'b': // Base pointer registers pairs
1619  case 'd': // Upper register
1620  case 'l': // Lower registers
1621  case 'e': // Pointer register pairs
1622  case 'q': // Stack pointer register
1623  case 'r': // Any register
1624  case 'w': // Special upper register pairs
1625  return C_RegisterClass;
1626  case 't': // Temporary register
1627  case 'x': case 'X': // Pointer register pair X
1628  case 'y': case 'Y': // Pointer register pair Y
1629  case 'z': case 'Z': // Pointer register pair Z
1630  return C_Register;
1631  case 'Q': // A memory address based on Y or Z pointer with displacement.
1632  return C_Memory;
1633  case 'G': // Floating point constant
1634  case 'I': // 6-bit positive integer constant
1635  case 'J': // 6-bit negative integer constant
1636  case 'K': // Integer constant (Range: 2)
1637  case 'L': // Integer constant (Range: 0)
1638  case 'M': // 8-bit integer constant
1639  case 'N': // Integer constant (Range: -1)
1640  case 'O': // Integer constant (Range: 8, 16, 24)
1641  case 'P': // Integer constant (Range: 1)
1642  case 'R': // Integer constant (Range: -6 to 5)x
1643  return C_Other;
1644  default:
1645  break;
1646  }
1647  }
1648 
1649  return TargetLowering::getConstraintType(Constraint);
1650 }
1651 
1652 unsigned
1654  // Not sure if this is actually the right thing to do, but we got to do
1655  // *something* [agnat]
1656  switch (ConstraintCode[0]) {
1657  case 'Q':
1658  return InlineAsm::Constraint_Q;
1659  }
1660  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
1661 }
1662 
1665  AsmOperandInfo &info, const char *constraint) const {
1666  ConstraintWeight weight = CW_Invalid;
1667  Value *CallOperandVal = info.CallOperandVal;
1668 
1669  // If we don't have a value, we can't do a match,
1670  // but allow it at the lowest weight.
1671  // (this behaviour has been copied from the ARM backend)
1672  if (!CallOperandVal) {
1673  return CW_Default;
1674  }
1675 
1676  // Look at the constraint type.
1677  switch (*constraint) {
1678  default:
1679  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1680  break;
1681  case 'd':
1682  case 'r':
1683  case 'l':
1684  weight = CW_Register;
1685  break;
1686  case 'a':
1687  case 'b':
1688  case 'e':
1689  case 'q':
1690  case 't':
1691  case 'w':
1692  case 'x': case 'X':
1693  case 'y': case 'Y':
1694  case 'z': case 'Z':
1695  weight = CW_SpecificReg;
1696  break;
1697  case 'G':
1698  if (const ConstantFP *C = dyn_cast<ConstantFP>(CallOperandVal)) {
1699  if (C->isZero()) {
1700  weight = CW_Constant;
1701  }
1702  }
1703  break;
1704  case 'I':
1705  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1706  if (isUInt<6>(C->getZExtValue())) {
1707  weight = CW_Constant;
1708  }
1709  }
1710  break;
1711  case 'J':
1712  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1713  if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
1714  weight = CW_Constant;
1715  }
1716  }
1717  break;
1718  case 'K':
1719  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1720  if (C->getZExtValue() == 2) {
1721  weight = CW_Constant;
1722  }
1723  }
1724  break;
1725  case 'L':
1726  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1727  if (C->getZExtValue() == 0) {
1728  weight = CW_Constant;
1729  }
1730  }
1731  break;
1732  case 'M':
1733  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1734  if (isUInt<8>(C->getZExtValue())) {
1735  weight = CW_Constant;
1736  }
1737  }
1738  break;
1739  case 'N':
1740  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1741  if (C->getSExtValue() == -1) {
1742  weight = CW_Constant;
1743  }
1744  }
1745  break;
1746  case 'O':
1747  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1748  if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
1749  (C->getZExtValue() == 24)) {
1750  weight = CW_Constant;
1751  }
1752  }
1753  break;
1754  case 'P':
1755  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1756  if (C->getZExtValue() == 1) {
1757  weight = CW_Constant;
1758  }
1759  }
1760  break;
1761  case 'R':
1762  if (const ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
1763  if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
1764  weight = CW_Constant;
1765  }
1766  }
1767  break;
1768  case 'Q':
1769  weight = CW_Memory;
1770  break;
1771  }
1772 
1773  return weight;
1774 }
1775 
1776 std::pair<unsigned, const TargetRegisterClass *>
1778  StringRef Constraint,
1779  MVT VT) const {
1780  auto STI = static_cast<const AVRTargetMachine &>(this->getTargetMachine())
1781  .getSubtargetImpl();
1782 
1783  // We only support i8 and i16.
1784  //
1785  //:FIXME: remove this assert for now since it gets sometimes executed
1786  // assert((VT == MVT::i16 || VT == MVT::i8) && "Wrong operand type.");
1787 
1788  if (Constraint.size() == 1) {
1789  switch (Constraint[0]) {
1790  case 'a': // Simple upper registers r16..r23.
1791  return std::make_pair(0U, &AVR::LD8loRegClass);
1792  case 'b': // Base pointer registers: y, z.
1793  return std::make_pair(0U, &AVR::PTRDISPREGSRegClass);
1794  case 'd': // Upper registers r16..r31.
1795  return std::make_pair(0U, &AVR::LD8RegClass);
1796  case 'l': // Lower registers r0..r15.
1797  return std::make_pair(0U, &AVR::GPR8loRegClass);
1798  case 'e': // Pointer register pairs: x, y, z.
1799  return std::make_pair(0U, &AVR::PTRREGSRegClass);
1800  case 'q': // Stack pointer register: SPH:SPL.
1801  return std::make_pair(0U, &AVR::GPRSPRegClass);
1802  case 'r': // Any register: r0..r31.
1803  if (VT == MVT::i8)
1804  return std::make_pair(0U, &AVR::GPR8RegClass);
1805 
1806  assert(VT == MVT::i16 && "inline asm constraint too large");
1807  return std::make_pair(0U, &AVR::DREGSRegClass);
1808  case 't': // Temporary register: r0.
1809  return std::make_pair(unsigned(AVR::R0), &AVR::GPR8RegClass);
1810  case 'w': // Special upper register pairs: r24, r26, r28, r30.
1811  return std::make_pair(0U, &AVR::IWREGSRegClass);
1812  case 'x': // Pointer register pair X: r27:r26.
1813  case 'X':
1814  return std::make_pair(unsigned(AVR::R27R26), &AVR::PTRREGSRegClass);
1815  case 'y': // Pointer register pair Y: r29:r28.
1816  case 'Y':
1817  return std::make_pair(unsigned(AVR::R29R28), &AVR::PTRREGSRegClass);
1818  case 'z': // Pointer register pair Z: r31:r30.
1819  case 'Z':
1820  return std::make_pair(unsigned(AVR::R31R30), &AVR::PTRREGSRegClass);
1821  default:
1822  break;
1823  }
1824  }
1825 
1826  return TargetLowering::getRegForInlineAsmConstraint(STI->getRegisterInfo(),
1827  Constraint, VT);
1828 }
1829 
1831  std::string &Constraint,
1832  std::vector<SDValue> &Ops,
1833  SelectionDAG &DAG) const {
1834  SDValue Result(0, 0);
1835  SDLoc DL(Op);
1836  EVT Ty = Op.getValueType();
1837 
1838  // Currently only support length 1 constraints.
1839  if (Constraint.length() != 1) {
1840  return;
1841  }
1842 
1843  char ConstraintLetter = Constraint[0];
1844  switch (ConstraintLetter) {
1845  default:
1846  break;
1847  // Deal with integers first:
1848  case 'I':
1849  case 'J':
1850  case 'K':
1851  case 'L':
1852  case 'M':
1853  case 'N':
1854  case 'O':
1855  case 'P':
1856  case 'R': {
1858  if (!C) {
1859  return;
1860  }
1861 
1862  int64_t CVal64 = C->getSExtValue();
1863  uint64_t CUVal64 = C->getZExtValue();
1864  switch (ConstraintLetter) {
1865  case 'I': // 0..63
1866  if (!isUInt<6>(CUVal64))
1867  return;
1868  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1869  break;
1870  case 'J': // -63..0
1871  if (CVal64 < -63 || CVal64 > 0)
1872  return;
1873  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1874  break;
1875  case 'K': // 2
1876  if (CUVal64 != 2)
1877  return;
1878  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1879  break;
1880  case 'L': // 0
1881  if (CUVal64 != 0)
1882  return;
1883  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1884  break;
1885  case 'M': // 0..255
1886  if (!isUInt<8>(CUVal64))
1887  return;
1888  // i8 type may be printed as a negative number,
1889  // e.g. 254 would be printed as -2,
1890  // so we force it to i16 at least.
1891  if (Ty.getSimpleVT() == MVT::i8) {
1892  Ty = MVT::i16;
1893  }
1894  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1895  break;
1896  case 'N': // -1
1897  if (CVal64 != -1)
1898  return;
1899  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1900  break;
1901  case 'O': // 8, 16, 24
1902  if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
1903  return;
1904  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1905  break;
1906  case 'P': // 1
1907  if (CUVal64 != 1)
1908  return;
1909  Result = DAG.getTargetConstant(CUVal64, DL, Ty);
1910  break;
1911  case 'R': // -6..5
1912  if (CVal64 < -6 || CVal64 > 5)
1913  return;
1914  Result = DAG.getTargetConstant(CVal64, DL, Ty);
1915  break;
1916  }
1917 
1918  break;
1919  }
1920  case 'G':
1922  if (!FC || !FC->isZero())
1923  return;
1924  // Soften float to i8 0
1925  Result = DAG.getTargetConstant(0, DL, MVT::i8);
1926  break;
1927  }
1928 
1929  if (Result.getNode()) {
1930  Ops.push_back(Result);
1931  return;
1932  }
1933 
1934  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1935 }
1936 
1937 unsigned AVRTargetLowering::getRegisterByName(const char *RegName,
1938  EVT VT,
1939  SelectionDAG &DAG) const {
1940  unsigned Reg;
1941 
1942  if (VT == MVT::i8) {
1943  Reg = StringSwitch<unsigned>(RegName)
1944  .Case("r0", AVR::R0).Case("r1", AVR::R1).Case("r2", AVR::R2)
1945  .Case("r3", AVR::R3).Case("r4", AVR::R4).Case("r5", AVR::R5)
1946  .Case("r6", AVR::R6).Case("r7", AVR::R7).Case("r8", AVR::R8)
1947  .Case("r9", AVR::R9).Case("r10", AVR::R10).Case("r11", AVR::R11)
1948  .Case("r12", AVR::R12).Case("r13", AVR::R13).Case("r14", AVR::R14)
1949  .Case("r15", AVR::R15).Case("r16", AVR::R16).Case("r17", AVR::R17)
1950  .Case("r18", AVR::R18).Case("r19", AVR::R19).Case("r20", AVR::R20)
1951  .Case("r21", AVR::R21).Case("r22", AVR::R22).Case("r23", AVR::R23)
1952  .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
1953  .Case("r27", AVR::R27).Case("r28", AVR::R28).Case("r29", AVR::R29)
1954  .Case("r30", AVR::R30).Case("r31", AVR::R31)
1955  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
1956  .Default(0);
1957  } else {
1958  Reg = StringSwitch<unsigned>(RegName)
1959  .Case("r0", AVR::R1R0).Case("r2", AVR::R3R2)
1960  .Case("r4", AVR::R5R4).Case("r6", AVR::R7R6)
1961  .Case("r8", AVR::R9R8).Case("r10", AVR::R11R10)
1962  .Case("r12", AVR::R13R12).Case("r14", AVR::R15R14)
1963  .Case("r16", AVR::R17R16).Case("r18", AVR::R19R18)
1964  .Case("r20", AVR::R21R20).Case("r22", AVR::R23R22)
1965  .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
1966  .Case("r28", AVR::R29R28).Case("r30", AVR::R31R30)
1967  .Case("X", AVR::R27R26).Case("Y", AVR::R29R28).Case("Z", AVR::R31R30)
1968  .Default(0);
1969  }
1970 
1971  if (Reg)
1972  return Reg;
1973 
1974  report_fatal_error("Invalid register name global variable");
1975 }
1976 
1977 } // end of namespace llvm
1978 
static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI)
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:500
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:184
#define R4(n)
LLVM Argument representation.
Definition: Argument.h:34
LLVMContext & Context
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
size_t i
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:572
Various leaf nodes.
Definition: ISDOpcodes.h:60
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
const TargetMachine & getTargetMachine() const
const AVRSubtarget * getSubtargetImpl() const
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
Unsigned lower.
Definition: AVRInstrInfo.h:38
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Bit rotate right.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Function Alias Analysis Results
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
MachineInstrBundleIterator< MachineInstr > iterator
Test for zero or minus instruction.
A debug info location.
Definition: DebugLoc.h:34
const SDValue & getOperand(unsigned Num) const
#define R2(n)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Compare with carry instruction.
Value * CallOperandVal
If this is the result output operand or a clobber, this is null, otherwise it is the incoming operand...
LLVMContext & getContext() const
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:369
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
static void parseExternFuncCallArgs(const SmallVectorImpl< ISD::OutputArg > &In, SmallVectorImpl< unsigned > &Out)
For external symbols there is no function prototype information so we have to rely directly on argume...
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:388
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:133
lazy value info
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Represents an abstract call instruction, which includes a bunch of information.
const HexagonInstrInfo * TII
Shift and rotation operations.
Definition: ISDOpcodes.h:344
bool isProgramMemoryAccess(MemSDNode const *N)
Definition: AVR.h:48
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void addLoc(const CCValAssign &V)
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
Definition: StringSwitch.h:244
Reg
All possible values of the reg field in the ModR/M byte.
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:719
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
auto reverse(ContainerTy &&C, typename std::enable_if< has_rbegin< ContainerTy >::value >::type *=nullptr) -> decltype(make_range(C.rbegin(), C.rend()))
Definition: STLExtras.h:241
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:74
A generic AVR implementation.
Utilities related to the AVR instruction set.
Definition: AVRInstrInfo.h:65
#define F(x, y, z)
Definition: MD5.cpp:51
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:264
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
Return from subroutine.
MachineBasicBlock * MBB
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:842
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
int64_t getImm() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:487
Calling convention used for special AVR rtlib functions which have an "optimized" convention to prese...
Definition: CallingConv.h:179
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset)
Stack pointer relative access.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
SDNode * getNode() const
get the SDNode which holds the desired result
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:43
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:309
bool isZero() const
Return true if the value is positive or negative zero.
MVT - Machine Value Type.
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
Unsigned same or higher.
Definition: AVRInstrInfo.h:37
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:48
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
Analyze incoming and outgoing function arguments.
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE...
Definition: ISDOpcodes.h:637
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:269
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
uint32_t Offset
unsigned getOpcode() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:57
Used for AVR interrupt routines.
Definition: CallingConv.h:172
AVR conditional branches.
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:628
static void parseFunctionArgs(const Function *F, const DataLayout *TD, SmallVectorImpl< unsigned > &Out)
For each argument in a function store the number of pieces it is composed of.
CondCodes
AVR specific condition codes.
Definition: AVRInstrInfo.h:32
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:705
EVT - Extended Value Type.
Definition: ValueTypes.h:31
std::vector< ArgListEntry > ArgListTy
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
AVRTargetLowering(AVRTargetMachine &TM)
Compare instruction.
virtual const TargetSubtargetInfo * getSubtargetImpl(const Function &) const
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
A loop of single logical shift right instructions.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:689
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
This is the shared class of boolean and integer constants.
Definition: Constants.h:88
#define R6(n)
static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:408
static StructType * get(LLVMContext &Context, ArrayRef< Type * > Elements, bool isPacked=false)
This static method is the primary way to create a literal StructType.
Definition: Type.cpp:330
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
#define NODE(name)
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:566
const DataFlowGraph & G
Definition: RDFGraph.cpp:206
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:347
Logical shift left.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Return from ISR.
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static mvt_range integer_valuetypes()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:354
void setMinFunctionAlignment(unsigned Align)
Set the target's minimum function alignment (in log2(bytes))
int64_t getSExtValue() const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:400
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:403
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
A loop of single logical shift left instructions.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Bit rotate left.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:560
Representation of each machine instruction.
Definition: MachineInstr.h:52
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the source.
Definition: ISDOpcodes.h:633
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:205
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:418
static bool isCopyMulResult(MachineBasicBlock::iterator const &I)
A loop of single arithmetic shift right instructions.
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void setStackPointerRegisterToSaveRestore(unsigned R)
If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.
static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F, const DataLayout *TD, const SmallVectorImpl< ISD::OutputArg > *Outs, const SmallVectorImpl< ISD::InputArg > *Ins, CallingConv::ID CallConv, SmallVectorImpl< CCValAssign > &ArgLocs, CCState &CCInfo, bool IsCall, bool IsVarArg)
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
Logical shift right.
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
Arithmetic shift right.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
Operand 0 and operand 1 are selection variable, operand 2 is condition code and operand 3 is flag ope...
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
Definition: Value.h:71
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
Greater than or equal.
Definition: AVRInstrInfo.h:35
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:47
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:533
BasicBlockListType::iterator iterator
Calling convention used for AVR signal routines.
Definition: CallingConv.h:175
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:377
const MCInstrDesc & getBrCond(AVRCC::CondCodes CC) const
Conversion operators.
Definition: ISDOpcodes.h:397
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:406
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC)
IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
unsigned AllocateStack(unsigned Size, unsigned Align)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:226
iterator_range< arg_iterator > args()
Definition: Function.h:568
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
uint64_t getZExtValue() const
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:799
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:326
This class is used to represent ISD::LOAD nodes.
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary...
Definition: ISDOpcodes.h:545