LLVM  4.0.0
RegBankSelect.cpp
Go to the documentation of this file.
1 //===- llvm/CodeGen/GlobalISel/RegBankSelect.cpp - RegBankSelect -*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegBankSelect class.
11 //===----------------------------------------------------------------------===//
12 
21 #include "llvm/IR/Function.h"
24 #include "llvm/Support/Debug.h"
26 
27 #define DEBUG_TYPE "regbankselect"
28 
29 using namespace llvm;
30 
32  cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional,
33  cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast",
34  "Run the Fast mode (default mapping)"),
35  clEnumValN(RegBankSelect::Mode::Greedy, "regbankselect-greedy",
36  "Use the Greedy mode (best local mapping)")));
37 
38 char RegBankSelect::ID = 0;
40  "Assign register bank of generic virtual registers",
41  false, false);
46  "Assign register bank of generic virtual registers", false,
47  false)
48 
49 RegBankSelect::RegBankSelect(Mode RunningMode)
50  : MachineFunctionPass(ID), RBI(nullptr), MRI(nullptr), TRI(nullptr),
51  MBFI(nullptr), MBPI(nullptr), OptMode(RunningMode) {
53  if (RegBankSelectMode.getNumOccurrences() != 0) {
54  OptMode = RegBankSelectMode;
55  if (RegBankSelectMode != RunningMode)
56  DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");
57  }
58 }
59 
60 void RegBankSelect::init(MachineFunction &MF) {
61  RBI = MF.getSubtarget().getRegBankInfo();
62  assert(RBI && "Cannot work without RegisterBankInfo");
63  MRI = &MF.getRegInfo();
64  TRI = MF.getSubtarget().getRegisterInfo();
65  TPC = &getAnalysis<TargetPassConfig>();
66  if (OptMode != Mode::Fast) {
67  MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
68  MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
69  } else {
70  MBFI = nullptr;
71  MBPI = nullptr;
72  }
73  MIRBuilder.setMF(MF);
74 }
75 
77  if (OptMode != Mode::Fast) {
78  // We could preserve the information from these two analysis but
79  // the APIs do not allow to do so yet.
82  }
85 }
86 
87 bool RegBankSelect::assignmentMatch(
88  unsigned Reg, const RegisterBankInfo::ValueMapping &ValMapping,
89  bool &OnlyAssign) const {
90  // By default we assume we will have to repair something.
91  OnlyAssign = false;
92  // Each part of a break down needs to end up in a different register.
93  // In other word, Reg assignement does not match.
94  if (ValMapping.NumBreakDowns > 1)
95  return false;
96 
97  const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI);
98  const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
99  // Reg is free of assignment, a simple assignment will make the
100  // register bank to match.
101  OnlyAssign = CurRegBank == nullptr;
102  DEBUG(dbgs() << "Does assignment already match: ";
103  if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none";
104  dbgs() << " against ";
105  assert(DesiredRegBrank && "The mapping must be valid");
106  dbgs() << *DesiredRegBrank << '\n';);
107  return CurRegBank == DesiredRegBrank;
108 }
109 
110 bool RegBankSelect::repairReg(
111  MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping,
114  if (ValMapping.NumBreakDowns != 1 && !TPC->isGlobalISelAbortEnabled())
115  return false;
116  assert(ValMapping.NumBreakDowns == 1 && "Not yet implemented");
117  // An empty range of new register means no repairing.
118  assert(NewVRegs.begin() != NewVRegs.end() && "We should not have to repair");
119 
120  // Assume we are repairing a use and thus, the original reg will be
121  // the source of the repairing.
122  unsigned Src = MO.getReg();
123  unsigned Dst = *NewVRegs.begin();
124 
125  // If we repair a definition, swap the source and destination for
126  // the repairing.
127  if (MO.isDef())
128  std::swap(Src, Dst);
129 
130  assert((RepairPt.getNumInsertPoints() == 1 ||
132  "We are about to create several defs for Dst");
133 
134  // Build the instruction used to repair, then clone it at the right places.
135  MachineInstr *MI = MIRBuilder.buildCopy(Dst, Src);
136  MI->removeFromParent();
137  DEBUG(dbgs() << "Copy: " << PrintReg(Src) << " to: " << PrintReg(Dst)
138  << '\n');
139  // TODO:
140  // Check if MI is legal. if not, we need to legalize all the
141  // instructions we are going to insert.
142  std::unique_ptr<MachineInstr *[]> NewInstrs(
143  new MachineInstr *[RepairPt.getNumInsertPoints()]);
144  bool IsFirst = true;
145  unsigned Idx = 0;
146  for (const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
147  MachineInstr *CurMI;
148  if (IsFirst)
149  CurMI = MI;
150  else
151  CurMI = MIRBuilder.getMF().CloneMachineInstr(MI);
152  InsertPt->insert(*CurMI);
153  NewInstrs[Idx++] = CurMI;
154  IsFirst = false;
155  }
156  // TODO:
157  // Legalize NewInstrs if need be.
158  return true;
159 }
160 
161 uint64_t RegBankSelect::getRepairCost(
162  const MachineOperand &MO,
163  const RegisterBankInfo::ValueMapping &ValMapping) const {
164  assert(MO.isReg() && "We should only repair register operand");
165  assert(ValMapping.NumBreakDowns && "Nothing to map??");
166 
167  bool IsSameNumOfValues = ValMapping.NumBreakDowns == 1;
168  const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI);
169  // If MO does not have a register bank, we should have just been
170  // able to set one unless we have to break the value down.
171  assert((!IsSameNumOfValues || CurRegBank) && "We should not have to repair");
172  // Def: Val <- NewDefs
173  // Same number of values: copy
174  // Different number: Val = build_sequence Defs1, Defs2, ...
175  // Use: NewSources <- Val.
176  // Same number of values: copy.
177  // Different number: Src1, Src2, ... =
178  // extract_value Val, Src1Begin, Src1Len, Src2Begin, Src2Len, ...
179  // We should remember that this value is available somewhere else to
180  // coalesce the value.
181 
182  if (IsSameNumOfValues) {
183  const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank;
184  // If we repair a definition, swap the source and destination for
185  // the repairing.
186  if (MO.isDef())
187  std::swap(CurRegBank, DesiredRegBrank);
188  // TODO: It may be possible to actually avoid the copy.
189  // If we repair something where the source is defined by a copy
190  // and the source of that copy is on the right bank, we can reuse
191  // it for free.
192  // E.g.,
193  // RegToRepair<BankA> = copy AlternativeSrc<BankB>
194  // = op RegToRepair<BankA>
195  // We can simply propagate AlternativeSrc instead of copying RegToRepair
196  // into a new virtual register.
197  // We would also need to propagate this information in the
198  // repairing placement.
199  unsigned Cost =
200  RBI->copyCost(*DesiredRegBrank, *CurRegBank,
201  RegisterBankInfo::getSizeInBits(MO.getReg(), *MRI, *TRI));
202  // TODO: use a dedicated constant for ImpossibleCost.
203  if (Cost != UINT_MAX)
204  return Cost;
206  "Legalization not available yet");
207  // Return the legalization cost of that repairing.
208  }
210  "Complex repairing not implemented yet");
211  return UINT_MAX;
212 }
213 
214 RegisterBankInfo::InstructionMapping &RegBankSelect::findBestMapping(
217  assert(!PossibleMappings.empty() &&
218  "Do not know how to map this instruction");
219 
220  RegisterBankInfo::InstructionMapping *BestMapping = nullptr;
221  MappingCost Cost = MappingCost::ImpossibleCost();
222  SmallVector<RepairingPlacement, 4> LocalRepairPts;
223  for (RegisterBankInfo::InstructionMapping &CurMapping : PossibleMappings) {
224  MappingCost CurCost = computeMapping(MI, CurMapping, LocalRepairPts, &Cost);
225  if (CurCost < Cost) {
226  DEBUG(dbgs() << "New best: " << CurCost << '\n');
227  Cost = CurCost;
228  BestMapping = &CurMapping;
229  RepairPts.clear();
230  for (RepairingPlacement &RepairPt : LocalRepairPts)
231  RepairPts.emplace_back(std::move(RepairPt));
232  }
233  }
234  if (!BestMapping && !TPC->isGlobalISelAbortEnabled()) {
235  // If none of the mapping worked that means they are all impossible.
236  // Thus, pick the first one and set an impossible repairing point.
237  // It will trigger the failed isel mode.
238  BestMapping = &(*PossibleMappings.begin());
239  RepairPts.emplace_back(
240  RepairingPlacement(MI, 0, *TRI, *this, RepairingPlacement::Impossible));
241  } else
242  assert(BestMapping && "No suitable mapping for instruction");
243  return *BestMapping;
244 }
245 
246 void RegBankSelect::tryAvoidingSplit(
248  const RegisterBankInfo::ValueMapping &ValMapping) const {
249  const MachineInstr &MI = *MO.getParent();
250  assert(RepairPt.hasSplit() && "We should not have to adjust for split");
251  // Splitting should only occur for PHIs or between terminators,
252  // because we only do local repairing.
253  assert((MI.isPHI() || MI.isTerminator()) && "Why do we split?");
254 
255  assert(&MI.getOperand(RepairPt.getOpIdx()) == &MO &&
256  "Repairing placement does not match operand");
257 
258  // If we need splitting for phis, that means it is because we
259  // could not find an insertion point before the terminators of
260  // the predecessor block for this argument. In other words,
261  // the input value is defined by one of the terminators.
262  assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?");
263 
264  // We split to repair the use of a phi or a terminator.
265  if (!MO.isDef()) {
266  if (MI.isTerminator()) {
267  assert(&MI != &(*MI.getParent()->getFirstTerminator()) &&
268  "Need to split for the first terminator?!");
269  } else {
270  // For the PHI case, the split may not be actually required.
271  // In the copy case, a phi is already a copy on the incoming edge,
272  // therefore there is no need to split.
273  if (ValMapping.NumBreakDowns == 1)
274  // This is a already a copy, there is nothing to do.
275  RepairPt.switchTo(RepairingPlacement::RepairingKind::Reassign);
276  }
277  return;
278  }
279 
280  // At this point, we need to repair a defintion of a terminator.
281 
282  // Technically we need to fix the def of MI on all outgoing
283  // edges of MI to keep the repairing local. In other words, we
284  // will create several definitions of the same register. This
285  // does not work for SSA unless that definition is a physical
286  // register.
287  // However, there are other cases where we can get away with
288  // that while still keeping the repairing local.
289  assert(MI.isTerminator() && MO.isDef() &&
290  "This code is for the def of a terminator");
291 
292  // Since we use RPO traversal, if we need to repair a definition
293  // this means this definition could be:
294  // 1. Used by PHIs (i.e., this VReg has been visited as part of the
295  // uses of a phi.), or
296  // 2. Part of a target specific instruction (i.e., the target applied
297  // some register class constraints when creating the instruction.)
298  // If the constraints come for #2, the target said that another mapping
299  // is supported so we may just drop them. Indeed, if we do not change
300  // the number of registers holding that value, the uses will get fixed
301  // when we get to them.
302  // Uses in PHIs may have already been proceeded though.
303  // If the constraints come for #1, then, those are weak constraints and
304  // no actual uses may rely on them. However, the problem remains mainly
305  // the same as for #2. If the value stays in one register, we could
306  // just switch the register bank of the definition, but we would need to
307  // account for a repairing cost for each phi we silently change.
308  //
309  // In any case, if the value needs to be broken down into several
310  // registers, the repairing is not local anymore as we need to patch
311  // every uses to rebuild the value in just one register.
312  //
313  // To summarize:
314  // - If the value is in a physical register, we can do the split and
315  // fix locally.
316  // Otherwise if the value is in a virtual register:
317  // - If the value remains in one register, we do not have to split
318  // just switching the register bank would do, but we need to account
319  // in the repairing cost all the phi we changed.
320  // - If the value spans several registers, then we cannot do a local
321  // repairing.
322 
323  // Check if this is a physical or virtual register.
324  unsigned Reg = MO.getReg();
326  // We are going to split every outgoing edges.
327  // Check that this is possible.
328  // FIXME: The machine representation is currently broken
329  // since it also several terminators in one basic block.
330  // Because of that we would technically need a way to get
331  // the targets of just one terminator to know which edges
332  // we have to split.
333  // Assert that we do not hit the ill-formed representation.
334 
335  // If there are other terminators before that one, some of
336  // the outgoing edges may not be dominated by this definition.
337  assert(&MI == &(*MI.getParent()->getFirstTerminator()) &&
338  "Do not know which outgoing edges are relevant");
339  const MachineInstr *Next = MI.getNextNode();
340  assert((!Next || Next->isUnconditionalBranch()) &&
341  "Do not know where each terminator ends up");
342  if (Next)
343  // If the next terminator uses Reg, this means we have
344  // to split right after MI and thus we need a way to ask
345  // which outgoing edges are affected.
346  assert(!Next->readsRegister(Reg) && "Need to split between terminators");
347  // We will split all the edges and repair there.
348  } else {
349  // This is a virtual register defined by a terminator.
350  if (ValMapping.NumBreakDowns == 1) {
351  // There is nothing to repair, but we may actually lie on
352  // the repairing cost because of the PHIs already proceeded
353  // as already stated.
354  // Though the code will be correct.
355  assert(0 && "Repairing cost may not be accurate");
356  } else {
357  // We need to do non-local repairing. Basically, patch all
358  // the uses (i.e., phis) that we already proceeded.
359  // For now, just say this mapping is not possible.
360  RepairPt.switchTo(RepairingPlacement::RepairingKind::Impossible);
361  }
362  }
363 }
364 
365 RegBankSelect::MappingCost RegBankSelect::computeMapping(
366  MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
368  const RegBankSelect::MappingCost *BestCost) {
369  assert((MBFI || !BestCost) && "Costs comparison require MBFI");
370 
371  if (!InstrMapping.isValid())
372  return MappingCost::ImpossibleCost();
373 
374  // If mapped with InstrMapping, MI will have the recorded cost.
375  MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
376  bool Saturated = Cost.addLocalCost(InstrMapping.getCost());
377  assert(!Saturated && "Possible mapping saturated the cost");
378  DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
379  DEBUG(dbgs() << "With: " << InstrMapping << '\n');
380  RepairPts.clear();
381  if (BestCost && Cost > *BestCost) {
382  DEBUG(dbgs() << "Mapping is too expensive from the start\n");
383  return Cost;
384  }
385 
386  // Moreover, to realize this mapping, the register bank of each operand must
387  // match this mapping. In other words, we may need to locally reassign the
388  // register banks. Account for that repairing cost as well.
389  // In this context, local means in the surrounding of MI.
390  for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands();
391  OpIdx != EndOpIdx; ++OpIdx) {
392  const MachineOperand &MO = MI.getOperand(OpIdx);
393  if (!MO.isReg())
394  continue;
395  unsigned Reg = MO.getReg();
396  if (!Reg)
397  continue;
398  DEBUG(dbgs() << "Opd" << OpIdx << '\n');
399  const RegisterBankInfo::ValueMapping &ValMapping =
400  InstrMapping.getOperandMapping(OpIdx);
401  // If Reg is already properly mapped, this is free.
402  bool Assign;
403  if (assignmentMatch(Reg, ValMapping, Assign)) {
404  DEBUG(dbgs() << "=> is free (match).\n");
405  continue;
406  }
407  if (Assign) {
408  DEBUG(dbgs() << "=> is free (simple assignment).\n");
409  RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this,
411  continue;
412  }
413 
414  // Find the insertion point for the repairing code.
415  RepairPts.emplace_back(
416  RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert));
417  RepairingPlacement &RepairPt = RepairPts.back();
418 
419  // If we need to split a basic block to materialize this insertion point,
420  // we may give a higher cost to this mapping.
421  // Nevertheless, we may get away with the split, so try that first.
422  if (RepairPt.hasSplit())
423  tryAvoidingSplit(RepairPt, MO, ValMapping);
424 
425  // Check that the materialization of the repairing is possible.
426  if (!RepairPt.canMaterialize()) {
427  DEBUG(dbgs() << "Mapping involves impossible repairing\n");
428  return MappingCost::ImpossibleCost();
429  }
430 
431  // Account for the split cost and repair cost.
432  // Unless the cost is already saturated or we do not care about the cost.
433  if (!BestCost || Saturated)
434  continue;
435 
436  // To get accurate information we need MBFI and MBPI.
437  // Thus, if we end up here this information should be here.
438  assert(MBFI && MBPI && "Cost computation requires MBFI and MBPI");
439 
440  // FIXME: We will have to rework the repairing cost model.
441  // The repairing cost depends on the register bank that MO has.
442  // However, when we break down the value into different values,
443  // MO may not have a register bank while still needing repairing.
444  // For the fast mode, we don't compute the cost so that is fine,
445  // but still for the repairing code, we will have to make a choice.
446  // For the greedy mode, we should choose greedily what is the best
447  // choice based on the next use of MO.
448 
449  // Sums up the repairing cost of MO at each insertion point.
450  uint64_t RepairCost = getRepairCost(MO, ValMapping);
451  // Bias used for splitting: 5%.
452  const uint64_t PercentageForBias = 5;
453  uint64_t Bias = (RepairCost * PercentageForBias + 99) / 100;
454  // We should not need more than a couple of instructions to repair
455  // an assignment. In other words, the computation should not
456  // overflow because the repairing cost is free of basic block
457  // frequency.
458  assert(((RepairCost < RepairCost * PercentageForBias) &&
459  (RepairCost * PercentageForBias <
460  RepairCost * PercentageForBias + 99)) &&
461  "Repairing involves more than a billion of instructions?!");
462  for (const std::unique_ptr<InsertPoint> &InsertPt : RepairPt) {
463  assert(InsertPt->canMaterialize() && "We should not have made it here");
464  // We will applied some basic block frequency and those uses uint64_t.
465  if (!InsertPt->isSplit())
466  Saturated = Cost.addLocalCost(RepairCost);
467  else {
468  uint64_t CostForInsertPt = RepairCost;
469  // Again we shouldn't overflow here givent that
470  // CostForInsertPt is frequency free at this point.
471  assert(CostForInsertPt + Bias > CostForInsertPt &&
472  "Repairing + split bias overflows");
473  CostForInsertPt += Bias;
474  uint64_t PtCost = InsertPt->frequency(*this) * CostForInsertPt;
475  // Check if we just overflowed.
476  if ((Saturated = PtCost < CostForInsertPt))
477  Cost.saturate();
478  else
479  Saturated = Cost.addNonLocalCost(PtCost);
480  }
481 
482  // Stop looking into what it takes to repair, this is already
483  // too expensive.
484  if (BestCost && Cost > *BestCost) {
485  DEBUG(dbgs() << "Mapping is too expensive, stop processing\n");
486  return Cost;
487  }
488 
489  // No need to accumulate more cost information.
490  // We need to still gather the repairing information though.
491  if (Saturated)
492  break;
493  }
494  }
495  DEBUG(dbgs() << "Total cost is: " << Cost << "\n");
496  return Cost;
497 }
498 
499 bool RegBankSelect::applyMapping(
500  MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
502  // OpdMapper will hold all the information needed for the rewritting.
503  RegisterBankInfo::OperandsMapper OpdMapper(MI, InstrMapping, *MRI);
504 
505  // First, place the repairing code.
506  for (RepairingPlacement &RepairPt : RepairPts) {
507  if (!RepairPt.canMaterialize() ||
508  RepairPt.getKind() == RepairingPlacement::Impossible)
509  return false;
510  assert(RepairPt.getKind() != RepairingPlacement::None &&
511  "This should not make its way in the list");
512  unsigned OpIdx = RepairPt.getOpIdx();
513  MachineOperand &MO = MI.getOperand(OpIdx);
514  const RegisterBankInfo::ValueMapping &ValMapping =
515  InstrMapping.getOperandMapping(OpIdx);
516  unsigned Reg = MO.getReg();
517 
518  switch (RepairPt.getKind()) {
520  assert(ValMapping.NumBreakDowns == 1 &&
521  "Reassignment should only be for simple mapping");
522  MRI->setRegBank(Reg, *ValMapping.BreakDown[0].RegBank);
523  break;
525  OpdMapper.createVRegs(OpIdx);
526  if (!repairReg(MO, ValMapping, RepairPt, OpdMapper.getVRegs(OpIdx)))
527  return false;
528  break;
529  default:
530  llvm_unreachable("Other kind should not happen");
531  }
532  }
533  // Second, rewrite the instruction.
534  DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n');
535  RBI->applyMapping(OpdMapper);
536  return true;
537 }
538 
539 bool RegBankSelect::assignInstr(MachineInstr &MI) {
540  DEBUG(dbgs() << "Assign: " << MI);
541  // Remember the repairing placement for all the operands.
543 
545  if (OptMode == RegBankSelect::Mode::Fast) {
546  BestMapping = RBI->getInstrMapping(MI);
547  MappingCost DefaultCost = computeMapping(MI, BestMapping, RepairPts);
548  (void)DefaultCost;
549  if (DefaultCost == MappingCost::ImpossibleCost())
550  return false;
551  } else {
552  RegisterBankInfo::InstructionMappings PossibleMappings =
553  RBI->getInstrPossibleMappings(MI);
554  if (PossibleMappings.empty())
555  return false;
556  BestMapping = std::move(findBestMapping(MI, PossibleMappings, RepairPts));
557  }
558  // Make sure the mapping is valid for MI.
559  assert(BestMapping.verify(MI) && "Invalid instruction mapping");
560 
561  DEBUG(dbgs() << "Best Mapping: " << BestMapping << '\n');
562 
563  // After this call, MI may not be valid anymore.
564  // Do not use it.
565  return applyMapping(MI, BestMapping, RepairPts);
566 }
567 
569  // If the ISel pipeline failed, do not bother running that pass.
570  if (MF.getProperties().hasProperty(
572  return false;
573 
574  DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
575  const Function *F = MF.getFunction();
576  Mode SaveOptMode = OptMode;
577  if (F->hasFnAttribute(Attribute::OptimizeNone))
578  OptMode = Mode::Fast;
579  init(MF);
580 
581 #ifndef NDEBUG
582  // Check that our input is fully legal: we require the function to have the
583  // Legalized property, so it should be.
584  // FIXME: This should be in the MachineVerifier, but it can't use the
585  // LegalizerInfo as it's currently in the separate GlobalISel library.
586  const MachineRegisterInfo &MRI = MF.getRegInfo();
587  if (const LegalizerInfo *MLI = MF.getSubtarget().getLegalizerInfo()) {
588  for (const MachineBasicBlock &MBB : MF) {
589  for (const MachineInstr &MI : MBB) {
590  if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI)) {
591  if (!TPC->isGlobalISelAbortEnabled()) {
592  MF.getProperties().set(
594  return false;
595  }
596  std::string ErrStorage;
597  raw_string_ostream Err(ErrStorage);
598  Err << "Instruction is not legal: " << MI << '\n';
599  report_fatal_error(Err.str());
600  }
601  }
602  }
603  }
604 #endif
605 
606  // Walk the function and assign register banks to all operands.
607  // Use a RPOT to make sure all registers are assigned before we choose
608  // the best mapping of the current instruction.
610  for (MachineBasicBlock *MBB : RPOT) {
611  // Set a sensible insertion point so that subsequent calls to
612  // MIRBuilder.
613  MIRBuilder.setMBB(*MBB);
614  for (MachineBasicBlock::iterator MII = MBB->begin(), End = MBB->end();
615  MII != End;) {
616  // MI might be invalidated by the assignment, so move the
617  // iterator before hand.
618  MachineInstr &MI = *MII++;
619 
620  // Ignore target-specific instructions: they should use proper regclasses.
622  continue;
623 
624  if (!assignInstr(MI)) {
625  if (TPC->isGlobalISelAbortEnabled())
626  report_fatal_error("Unable to map instruction");
628  return false;
629  }
630  }
631  }
632  OptMode = SaveOptMode;
633  return false;
634 }
635 
636 //------------------------------------------------------------------------------
637 // Helper Classes Implementation
638 //------------------------------------------------------------------------------
640  MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P,
642  // Default is, we are going to insert code to repair OpIdx.
643  : Kind(Kind),
644  OpIdx(OpIdx),
645  CanMaterialize(Kind != RepairingKind::Impossible),
646  HasSplit(false),
647  P(P) {
648  const MachineOperand &MO = MI.getOperand(OpIdx);
649  assert(MO.isReg() && "Trying to repair a non-reg operand");
650 
651  if (Kind != RepairingKind::Insert)
652  return;
653 
654  // Repairings for definitions happen after MI, uses happen before.
655  bool Before = !MO.isDef();
656 
657  // Check if we are done with MI.
658  if (!MI.isPHI() && !MI.isTerminator()) {
659  addInsertPoint(MI, Before);
660  // We are done with the initialization.
661  return;
662  }
663 
664  // Now, look for the special cases.
665  if (MI.isPHI()) {
666  // - PHI must be the first instructions:
667  // * Before, we have to split the related incoming edge.
668  // * After, move the insertion point past the last phi.
669  if (!Before) {
671  if (It != MI.getParent()->end())
672  addInsertPoint(*It, /*Before*/ true);
673  else
674  addInsertPoint(*(--It), /*Before*/ false);
675  return;
676  }
677  // We repair a use of a phi, we may need to split the related edge.
678  MachineBasicBlock &Pred = *MI.getOperand(OpIdx + 1).getMBB();
679  // Check if we can move the insertion point prior to the
680  // terminators of the predecessor.
681  unsigned Reg = MO.getReg();
683  for (auto Begin = Pred.begin(); It != Begin && It->isTerminator(); --It)
684  if (It->modifiesRegister(Reg, &TRI)) {
685  // We cannot hoist the repairing code in the predecessor.
686  // Split the edge.
687  addInsertPoint(Pred, *MI.getParent());
688  return;
689  }
690  // At this point, we can insert in Pred.
691 
692  // - If It is invalid, Pred is empty and we can insert in Pred
693  // wherever we want.
694  // - If It is valid, It is the first non-terminator, insert after It.
695  if (It == Pred.end())
696  addInsertPoint(Pred, /*Beginning*/ false);
697  else
698  addInsertPoint(*It, /*Before*/ false);
699  } else {
700  // - Terminators must be the last instructions:
701  // * Before, move the insert point before the first terminator.
702  // * After, we have to split the outcoming edges.
703  unsigned Reg = MO.getReg();
704  if (Before) {
705  // Check whether Reg is defined by any terminator.
707  for (auto Begin = MI.getParent()->begin();
708  --It != Begin && It->isTerminator();)
709  if (It->modifiesRegister(Reg, &TRI)) {
710  // Insert the repairing code right after the definition.
711  addInsertPoint(*It, /*Before*/ false);
712  return;
713  }
714  addInsertPoint(*It, /*Before*/ true);
715  return;
716  }
717  // Make sure Reg is not redefined by other terminators, otherwise
718  // we do not know how to split.
719  for (MachineBasicBlock::iterator It = MI, End = MI.getParent()->end();
720  ++It != End;)
721  // The machine verifier should reject this kind of code.
722  assert(It->modifiesRegister(Reg, &TRI) && "Do not know where to split");
723  // Split each outcoming edges.
724  MachineBasicBlock &Src = *MI.getParent();
725  for (auto &Succ : Src.successors())
726  addInsertPoint(Src, Succ);
727  }
728 }
729 
731  bool Before) {
732  addInsertPoint(*new InstrInsertPoint(MI, Before));
733 }
734 
736  bool Beginning) {
737  addInsertPoint(*new MBBInsertPoint(MBB, Beginning));
738 }
739 
741  MachineBasicBlock &Dst) {
742  addInsertPoint(*new EdgeInsertPoint(Src, Dst, P));
743 }
744 
747  CanMaterialize &= Point.canMaterialize();
748  HasSplit |= Point.isSplit();
749  InsertPoints.emplace_back(&Point);
750 }
751 
753  bool Before)
754  : InsertPoint(), Instr(Instr), Before(Before) {
755  // Since we do not support splitting, we do not need to update
756  // liveness and such, so do not do anything with P.
757  assert((!Before || !Instr.isPHI()) &&
758  "Splitting before phis requires more points");
759  assert((!Before || !Instr.getNextNode() || !Instr.getNextNode()->isPHI()) &&
760  "Splitting between phis does not make sense");
761 }
762 
763 void RegBankSelect::InstrInsertPoint::materialize() {
764  if (isSplit()) {
765  // Slice and return the beginning of the new block.
766  // If we need to split between the terminators, we theoritically
767  // need to know where the first and second set of terminators end
768  // to update the successors properly.
769  // Now, in pratice, we should have a maximum of 2 branch
770  // instructions; one conditional and one unconditional. Therefore
771  // we know how to update the successor by looking at the target of
772  // the unconditional branch.
773  // If we end up splitting at some point, then, we should update
774  // the liveness information and such. I.e., we would need to
775  // access P here.
776  // The machine verifier should actually make sure such cases
777  // cannot happen.
778  llvm_unreachable("Not yet implemented");
779  }
780  // Otherwise the insertion point is just the current or next
781  // instruction depending on Before. I.e., there is nothing to do
782  // here.
783 }
784 
786  // If the insertion point is after a terminator, we need to split.
787  if (!Before)
788  return Instr.isTerminator();
789  // If we insert before an instruction that is after a terminator,
790  // we are still after a terminator.
791  return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator();
792 }
793 
795  // Even if we need to split, because we insert between terminators,
796  // this split has actually the same frequency as the instruction.
797  const MachineBlockFrequencyInfo *MBFI =
799  if (!MBFI)
800  return 1;
801  return MBFI->getBlockFreq(Instr.getParent()).getFrequency();
802 }
803 
805  const MachineBlockFrequencyInfo *MBFI =
807  if (!MBFI)
808  return 1;
809  return MBFI->getBlockFreq(&MBB).getFrequency();
810 }
811 
812 void RegBankSelect::EdgeInsertPoint::materialize() {
813  // If we end up repairing twice at the same place before materializing the
814  // insertion point, we may think we have to split an edge twice.
815  // We should have a factory for the insert point such that identical points
816  // are the same instance.
817  assert(Src.isSuccessor(DstOrSplit) && DstOrSplit->isPredecessor(&Src) &&
818  "This point has already been split");
819  MachineBasicBlock *NewBB = Src.SplitCriticalEdge(DstOrSplit, P);
820  assert(NewBB && "Invalid call to materialize");
821  // We reuse the destination block to hold the information of the new block.
822  DstOrSplit = NewBB;
823 }
824 
826  const MachineBlockFrequencyInfo *MBFI =
828  if (!MBFI)
829  return 1;
830  if (WasMaterialized)
831  return MBFI->getBlockFreq(DstOrSplit).getFrequency();
832 
833  const MachineBranchProbabilityInfo *MBPI =
835  if (!MBPI)
836  return 1;
837  // The basic block will be on the edge.
838  return (MBFI->getBlockFreq(&Src) * MBPI->getEdgeProbability(&Src, DstOrSplit))
839  .getFrequency();
840 }
841 
843  // If this is not a critical edge, we should not have used this insert
844  // point. Indeed, either the successor or the predecessor should
845  // have do.
846  assert(Src.succ_size() > 1 && DstOrSplit->pred_size() > 1 &&
847  "Edge is not critical");
848  return Src.canSplitCriticalEdge(DstOrSplit);
849 }
850 
851 RegBankSelect::MappingCost::MappingCost(const BlockFrequency &LocalFreq)
852  : LocalCost(0), NonLocalCost(0), LocalFreq(LocalFreq.getFrequency()) {}
853 
854 bool RegBankSelect::MappingCost::addLocalCost(uint64_t Cost) {
855  // Check if this overflows.
856  if (LocalCost + Cost < LocalCost) {
857  saturate();
858  return true;
859  }
860  LocalCost += Cost;
861  return isSaturated();
862 }
863 
864 bool RegBankSelect::MappingCost::addNonLocalCost(uint64_t Cost) {
865  // Check if this overflows.
866  if (NonLocalCost + Cost < NonLocalCost) {
867  saturate();
868  return true;
869  }
870  NonLocalCost += Cost;
871  return isSaturated();
872 }
873 
874 bool RegBankSelect::MappingCost::isSaturated() const {
875  return LocalCost == UINT64_MAX - 1 && NonLocalCost == UINT64_MAX &&
876  LocalFreq == UINT64_MAX;
877 }
878 
879 void RegBankSelect::MappingCost::saturate() {
880  *this = ImpossibleCost();
881  --LocalCost;
882 }
883 
884 RegBankSelect::MappingCost RegBankSelect::MappingCost::ImpossibleCost() {
885  return MappingCost(UINT64_MAX, UINT64_MAX, UINT64_MAX);
886 }
887 
888 bool RegBankSelect::MappingCost::operator<(const MappingCost &Cost) const {
889  // Sort out the easy cases.
890  if (*this == Cost)
891  return false;
892  // If one is impossible to realize the other is cheaper unless it is
893  // impossible as well.
894  if ((*this == ImpossibleCost()) || (Cost == ImpossibleCost()))
895  return (*this == ImpossibleCost()) < (Cost == ImpossibleCost());
896  // If one is saturated the other is cheaper, unless it is saturated
897  // as well.
898  if (isSaturated() || Cost.isSaturated())
899  return isSaturated() < Cost.isSaturated();
900  // At this point we know both costs hold sensible values.
901 
902  // If both values have a different base frequency, there is no much
903  // we can do but to scale everything.
904  // However, if they have the same base frequency we can avoid making
905  // complicated computation.
906  uint64_t ThisLocalAdjust;
907  uint64_t OtherLocalAdjust;
908  if (LLVM_LIKELY(LocalFreq == Cost.LocalFreq)) {
909 
910  // At this point, we know the local costs are comparable.
911  // Do the case that do not involve potential overflow first.
912  if (NonLocalCost == Cost.NonLocalCost)
913  // Since the non-local costs do not discriminate on the result,
914  // just compare the local costs.
915  return LocalCost < Cost.LocalCost;
916 
917  // The base costs are comparable so we may only keep the relative
918  // value to increase our chances of avoiding overflows.
919  ThisLocalAdjust = 0;
920  OtherLocalAdjust = 0;
921  if (LocalCost < Cost.LocalCost)
922  OtherLocalAdjust = Cost.LocalCost - LocalCost;
923  else
924  ThisLocalAdjust = LocalCost - Cost.LocalCost;
925 
926  } else {
927  ThisLocalAdjust = LocalCost;
928  OtherLocalAdjust = Cost.LocalCost;
929  }
930 
931  // The non-local costs are comparable, just keep the relative value.
932  uint64_t ThisNonLocalAdjust = 0;
933  uint64_t OtherNonLocalAdjust = 0;
934  if (NonLocalCost < Cost.NonLocalCost)
935  OtherNonLocalAdjust = Cost.NonLocalCost - NonLocalCost;
936  else
937  ThisNonLocalAdjust = NonLocalCost - Cost.NonLocalCost;
938  // Scale everything to make them comparable.
939  uint64_t ThisScaledCost = ThisLocalAdjust * LocalFreq;
940  // Check for overflow on that operation.
941  bool ThisOverflows = ThisLocalAdjust && (ThisScaledCost < ThisLocalAdjust ||
942  ThisScaledCost < LocalFreq);
943  uint64_t OtherScaledCost = OtherLocalAdjust * Cost.LocalFreq;
944  // Check for overflow on the last operation.
945  bool OtherOverflows =
946  OtherLocalAdjust &&
947  (OtherScaledCost < OtherLocalAdjust || OtherScaledCost < Cost.LocalFreq);
948  // Add the non-local costs.
949  ThisOverflows |= ThisNonLocalAdjust &&
950  ThisScaledCost + ThisNonLocalAdjust < ThisNonLocalAdjust;
951  ThisScaledCost += ThisNonLocalAdjust;
952  OtherOverflows |= OtherNonLocalAdjust &&
953  OtherScaledCost + OtherNonLocalAdjust < OtherNonLocalAdjust;
954  OtherScaledCost += OtherNonLocalAdjust;
955  // If both overflows, we cannot compare without additional
956  // precision, e.g., APInt. Just give up on that case.
957  if (ThisOverflows && OtherOverflows)
958  return false;
959  // If one overflows but not the other, we can still compare.
960  if (ThisOverflows || OtherOverflows)
961  return ThisOverflows < OtherOverflows;
962  // Otherwise, just compare the values.
963  return ThisScaledCost < OtherScaledCost;
964 }
965 
966 bool RegBankSelect::MappingCost::operator==(const MappingCost &Cost) const {
967  return LocalCost == Cost.LocalCost && NonLocalCost == Cost.NonLocalCost &&
968  LocalFreq == Cost.LocalFreq;
969 }
970 
972  print(dbgs());
973  dbgs() << '\n';
974 }
975 
976 void RegBankSelect::MappingCost::print(raw_ostream &OS) const {
977  if (*this == ImpossibleCost()) {
978  OS << "impossible";
979  return;
980  }
981  if (isSaturated()) {
982  OS << "saturated";
983  return;
984  }
985  OS << LocalFreq << " * " << LocalCost << " + " << NonLocalCost;
986 }
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:81
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
bool canMaterialize() const override
Check whether this insertion point can be materialized.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SI Whole Quad Mode
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:274
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasProperty(Property P) const
MachineBasicBlock * getMBB() const
#define LLVM_LIKELY(EXPR)
Definition: Compiler.h:181
Helper class that represents how the value of an instruction may be mapped and what is the related co...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Reparing code needs to happen before InsertPoints.
static bool isTargetSpecificOpcode(unsigned Opcode)
Check whether the given Opcode is a target-specific opcode.
Definition: TargetOpcodes.h:37
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
static void dump(StringRef Title, SpillInfo const &Spills)
Definition: CoroFrame.cpp:283
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
void setRegBank(unsigned Reg, const RegisterBank &RegBank)
Set the register bank to RegBank for Reg.
Mode
List of the modes supported by the RegBankSelect pass.
Definition: RegBankSelect.h:88
void switchTo(RepairingKind NewKind)
Change the type of this repairing placement to NewKind.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
iterator_range< succ_iterator > successors()
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
Mark this repairing placement as impossible.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
bool isPHI() const
Definition: MachineInstr.h:786
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Abstract class used to represent an insertion point in a CFG.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
const MachineFunctionProperties & getProperties() const
Get the function properties.
Reg
All possible values of the reg field in the ModR/M byte.
RepairingKind
Define the kind of action this repairing needs.
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Target-Independent Code Generator Pass Configuration Options.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
#define F(x, y, z)
Definition: MD5.cpp:51
MachineBasicBlock * MBB
virtual bool isSplit() const
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus...
Function Alias Analysis false
virtual InstructionMapping getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
MachineFunction & getMF()
Getter for the function we currently build.
virtual bool canMaterialize() const
Check whether this insertion point can be materialized.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
#define DEBUG_TYPE
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
RepairingPlacement(MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P, RepairingKind Kind=RepairingKind::Insert)
Create a repairing placement for the OpIdx-th operand of MI.
const RegisterBank * RegBank
Register bank where the partial value lives.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
ValuesClass values(OptsTy...Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:615
#define P(N)
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:83
Insertion point on an edge.
static unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
Get the size in bits of Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
static const unsigned End
void initializeRegBankSelectPass(PassRegistry &)
void setMF(MachineFunction &)
Setters for the insertion point.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:479
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:865
Struct used to represent the placement of a repairing point for a given operand.
static cl::opt< RegBankSelect::Mode > RegBankSelectMode(cl::desc("Mode of the RegBankSelect pass"), cl::Hidden, cl::Optional, cl::values(clEnumValN(RegBankSelect::Mode::Fast,"regbankselect-fast","Run the Fast mode (default mapping)"), clEnumValN(RegBankSelect::Mode::Greedy,"regbankselect-greedy","Use the Greedy mode (best local mapping)")))
MachineInstr * CloneMachineInstr(const MachineInstr *Orig)
CloneMachineInstr - Create a new MachineInstr which is a copy of the 'Orig' instruction, identical in all ways except the instruction has no parent, prev, or next.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
MachineInstrBuilder buildCopy(unsigned Res, unsigned Op)
Build and insert Res<def> = COPY Op.
This class implements the register bank concept.
Definition: RegisterBank.h:29
Helper struct that represents how a value is mapped through different register banks.
unsigned getCost() const
Get the cost.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:586
A range adaptor for a pair of iterators.
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
bool isValid() const
Check whether this object is valid.
INITIALIZE_PASS_BEGIN(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false)
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:590
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void emplace_back(ArgTypes &&...Args)
Definition: SmallVector.h:635
Insertion point before or after an instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
InstrInsertPoint(MachineInstr &Instr, bool Before=true)
Create an insertion point before (Before=true) or after Instr.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
unsigned getNumOperands() const
Get the number of operands.
void addInsertPoint(MachineBasicBlock &MBB, bool Beginning)
Overloaded methods to add an insertion point.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool runOnMachineFunction(MachineFunction &MF) override
Walk through MF and assign a register bank to every virtual register that are still mapped to nothing...
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
const unsigned Kind
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P)
Split the critical edge from this block to the given successor block, and return the newly created bl...
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:326
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
unsigned NumBreakDowns
Number of partial mapping to break down this value.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
(Re)assign the register bank of the operand.
virtual const LegalizerInfo * getLegalizerInfo() const
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual void print(raw_ostream &O, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:117
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1722
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
uint64_t frequency(const Pass &P) const override
Frequency of the insertion point.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Insertion point at the beginning or end of a basic block.
Nothing to repair, just drop this action.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:470
bool isSplit() const override
Does this point involve splitting an edge or block? As soon as ::getPoint is called and thus...