LLVM  4.0.0
X86MCInstLower.cpp
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1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower X86 MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/ADT/SmallString.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/GlobalValue.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCCodeEmitter.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCFixup.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCInstBuilder.h"
40 #include "llvm/MC/MCSection.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/MC/MCSymbolELF.h"
44 #include "llvm/MC/MCSectionELF.h"
45 #include "llvm/MC/MCSectionMachO.h"
47 #include "llvm/Support/ELF.h"
49 
50 using namespace llvm;
51 
52 namespace {
53 
54 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
55 class X86MCInstLower {
56  MCContext &Ctx;
57  const MachineFunction &MF;
58  const TargetMachine &TM;
59  const MCAsmInfo &MAI;
61 public:
62  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
63 
64  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
65  const MachineOperand &MO) const;
66  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
67 
69  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
70 
71 private:
73 };
74 
75 } // end anonymous namespace
76 
77 // Emit a minimal sequence of nops spanning NumBytes bytes.
78 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
79  const MCSubtargetInfo &STI);
80 
82  const MCSubtargetInfo &STI,
83  MCCodeEmitter *CodeEmitter) {
84  if (InShadow) {
87  raw_svector_ostream VecOS(Code);
88  CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
89  CurrentShadowSize += Code.size();
90  if (CurrentShadowSize >= RequiredShadowSize)
91  InShadow = false; // The shadow is big enough. Stop counting.
92  }
93 }
94 
95 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
96  MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
97  if (InShadow && CurrentShadowSize < RequiredShadowSize) {
98  InShadow = false;
99  EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
100  MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
101  }
102 }
103 
104 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
105  OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
106  SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
107 }
108 
109 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
110  X86AsmPrinter &asmprinter)
111  : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
112  AsmPrinter(asmprinter) {}
113 
115  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
116 }
117 
118 
119 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
120 /// operand to an MCSymbol.
122 GetSymbolFromOperand(const MachineOperand &MO) const {
123  const DataLayout &DL = MF.getDataLayout();
124  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
125 
126  MCSymbol *Sym = nullptr;
128  StringRef Suffix;
129 
130  switch (MO.getTargetFlags()) {
131  case X86II::MO_DLLIMPORT:
132  // Handle dllimport linkage.
133  Name += "__imp_";
134  break;
137  Suffix = "$non_lazy_ptr";
138  break;
139  }
140 
141  if (!Suffix.empty())
142  Name += DL.getPrivateGlobalPrefix();
143 
144  if (MO.isGlobal()) {
145  const GlobalValue *GV = MO.getGlobal();
146  AsmPrinter.getNameWithPrefix(Name, GV);
147  } else if (MO.isSymbol()) {
148  Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
149  } else if (MO.isMBB()) {
150  assert(Suffix.empty());
151  Sym = MO.getMBB()->getSymbol();
152  }
153 
154  Name += Suffix;
155  if (!Sym)
156  Sym = Ctx.getOrCreateSymbol(Name);
157 
158  // If the target flags on the operand changes the name of the symbol, do that
159  // before we return the symbol.
160  switch (MO.getTargetFlags()) {
161  default: break;
166  if (!StubSym.getPointer()) {
167  assert(MO.isGlobal() && "Extern symbol not handled yet");
168  StubSym =
171  !MO.getGlobal()->hasInternalLinkage());
172  }
173  break;
174  }
175  }
176 
177  return Sym;
178 }
179 
181  MCSymbol *Sym) const {
182  // FIXME: We would like an efficient form for this, so we don't have to do a
183  // lot of extra uniquing.
184  const MCExpr *Expr = nullptr;
185  MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
186 
187  switch (MO.getTargetFlags()) {
188  default: llvm_unreachable("Unknown target flag on GV operand");
189  case X86II::MO_NO_FLAG: // No flag.
190  // These affect the name of the symbol, not any suffix.
192  case X86II::MO_DLLIMPORT:
193  break;
194 
195  case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
197  Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
198  // Subtract the pic base.
199  Expr = MCBinaryExpr::createSub(Expr,
200  MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
201  Ctx),
202  Ctx);
203  break;
204  case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
205  case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
206  case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
207  case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
208  case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
209  case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
210  case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
211  case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
212  case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
213  case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
214  case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
215  case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
216  case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
217  case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
220  Expr = MCSymbolRefExpr::create(Sym, Ctx);
221  // Subtract the pic base.
222  Expr = MCBinaryExpr::createSub(Expr,
223  MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
224  Ctx);
225  if (MO.isJTI()) {
226  assert(MAI.doesSetDirectiveSuppressReloc());
227  // If .set directive is supported, use it to reduce the number of
228  // relocations the assembler will generate for differences between
229  // local labels. This is only safe when the symbols are in the same
230  // section so we are restricting it to jumptable references.
231  MCSymbol *Label = Ctx.createTempSymbol();
232  AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
233  Expr = MCSymbolRefExpr::create(Label, Ctx);
234  }
235  break;
236  }
237 
238  if (!Expr)
239  Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
240 
241  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
242  Expr = MCBinaryExpr::createAdd(Expr,
243  MCConstantExpr::create(MO.getOffset(), Ctx),
244  Ctx);
245  return MCOperand::createExpr(Expr);
246 }
247 
248 
249 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
250 /// a short fixed-register form.
251 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
252  unsigned ImmOp = Inst.getNumOperands() - 1;
253  assert(Inst.getOperand(0).isReg() &&
254  (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
255  ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
256  Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
257  Inst.getNumOperands() == 2) && "Unexpected instruction!");
258 
259  // Check whether the destination register can be fixed.
260  unsigned Reg = Inst.getOperand(0).getReg();
261  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
262  return;
263 
264  // If so, rewrite the instruction.
265  MCOperand Saved = Inst.getOperand(ImmOp);
266  Inst = MCInst();
267  Inst.setOpcode(Opcode);
268  Inst.addOperand(Saved);
269 }
270 
271 /// \brief If a movsx instruction has a shorter encoding for the used register
272 /// simplify the instruction to use it instead.
273 static void SimplifyMOVSX(MCInst &Inst) {
274  unsigned NewOpcode = 0;
275  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
276  switch (Inst.getOpcode()) {
277  default:
278  llvm_unreachable("Unexpected instruction!");
279  case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
280  if (Op0 == X86::AX && Op1 == X86::AL)
281  NewOpcode = X86::CBW;
282  break;
283  case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
284  if (Op0 == X86::EAX && Op1 == X86::AX)
285  NewOpcode = X86::CWDE;
286  break;
287  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
288  if (Op0 == X86::RAX && Op1 == X86::EAX)
289  NewOpcode = X86::CDQE;
290  break;
291  }
292 
293  if (NewOpcode != 0) {
294  Inst = MCInst();
295  Inst.setOpcode(NewOpcode);
296  }
297 }
298 
299 /// \brief Simplify things like MOV32rm to MOV32o32a.
301  unsigned Opcode) {
302  // Don't make these simplifications in 64-bit mode; other assemblers don't
303  // perform them because they make the code larger.
304  if (Printer.getSubtarget().is64Bit())
305  return;
306 
307  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
308  unsigned AddrBase = IsStore;
309  unsigned RegOp = IsStore ? 0 : 5;
310  unsigned AddrOp = AddrBase + 3;
311  assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
312  Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
313  Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
314  Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
315  Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
316  (Inst.getOperand(AddrOp).isExpr() ||
317  Inst.getOperand(AddrOp).isImm()) &&
318  "Unexpected instruction!");
319 
320  // Check whether the destination register can be fixed.
321  unsigned Reg = Inst.getOperand(RegOp).getReg();
322  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
323  return;
324 
325  // Check whether this is an absolute address.
326  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
327  // to do this here.
328  bool Absolute = true;
329  if (Inst.getOperand(AddrOp).isExpr()) {
330  const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
331  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
332  if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
333  Absolute = false;
334  }
335 
336  if (Absolute &&
337  (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
338  Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
339  Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
340  return;
341 
342  // If so, rewrite the instruction.
343  MCOperand Saved = Inst.getOperand(AddrOp);
344  MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
345  Inst = MCInst();
346  Inst.setOpcode(Opcode);
347  Inst.addOperand(Saved);
348  Inst.addOperand(Seg);
349 }
350 
351 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
352  return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
353 }
354 
356 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
357  const MachineOperand &MO) const {
358  switch (MO.getType()) {
359  default:
360  MI->dump();
361  llvm_unreachable("unknown operand type");
362  case MachineOperand::MO_Register:
363  // Ignore all implicit register operands.
364  if (MO.isImplicit())
365  return None;
366  return MCOperand::createReg(MO.getReg());
367  case MachineOperand::MO_Immediate:
368  return MCOperand::createImm(MO.getImm());
369  case MachineOperand::MO_MachineBasicBlock:
370  case MachineOperand::MO_GlobalAddress:
371  case MachineOperand::MO_ExternalSymbol:
373  case MachineOperand::MO_MCSymbol:
374  return LowerSymbolOperand(MO, MO.getMCSymbol());
375  case MachineOperand::MO_JumpTableIndex:
377  case MachineOperand::MO_ConstantPoolIndex:
379  case MachineOperand::MO_BlockAddress:
380  return LowerSymbolOperand(
382  case MachineOperand::MO_RegisterMask:
383  // Ignore call clobbers.
384  return None;
385  }
386 }
387 
388 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
389  OutMI.setOpcode(MI->getOpcode());
390 
391  for (const MachineOperand &MO : MI->operands())
392  if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
393  OutMI.addOperand(MaybeMCOp.getValue());
394 
395  // Handle a few special cases to eliminate operand modifiers.
396 ReSimplify:
397  switch (OutMI.getOpcode()) {
398  case X86::LEA64_32r:
399  case X86::LEA64r:
400  case X86::LEA16r:
401  case X86::LEA32r:
402  // LEA should have a segment register, but it must be empty.
404  "Unexpected # of LEA operands");
405  assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
406  "LEA has segment specified!");
407  break;
408 
409  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
410  // if one of the registers is extended, but other isn't.
411  case X86::VMOVZPQILo2PQIrr:
412  case X86::VMOVAPDrr:
413  case X86::VMOVAPDYrr:
414  case X86::VMOVAPSrr:
415  case X86::VMOVAPSYrr:
416  case X86::VMOVDQArr:
417  case X86::VMOVDQAYrr:
418  case X86::VMOVDQUrr:
419  case X86::VMOVDQUYrr:
420  case X86::VMOVUPDrr:
421  case X86::VMOVUPDYrr:
422  case X86::VMOVUPSrr:
423  case X86::VMOVUPSYrr: {
424  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
426  unsigned NewOpc;
427  switch (OutMI.getOpcode()) {
428  default: llvm_unreachable("Invalid opcode");
429  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
430  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
431  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
432  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
433  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
434  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
435  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
436  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
437  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
438  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
439  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
440  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
441  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
442  }
443  OutMI.setOpcode(NewOpc);
444  }
445  break;
446  }
447  case X86::VMOVSDrr:
448  case X86::VMOVSSrr: {
449  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
451  unsigned NewOpc;
452  switch (OutMI.getOpcode()) {
453  default: llvm_unreachable("Invalid opcode");
454  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
455  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
456  }
457  OutMI.setOpcode(NewOpc);
458  }
459  break;
460  }
461 
462  // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
463  // inputs modeled as normal uses instead of implicit uses. As such, truncate
464  // off all but the first operand (the callee). FIXME: Change isel.
465  case X86::TAILJMPr64:
466  case X86::TAILJMPr64_REX:
467  case X86::CALL64r:
468  case X86::CALL64pcrel32: {
469  unsigned Opcode = OutMI.getOpcode();
470  MCOperand Saved = OutMI.getOperand(0);
471  OutMI = MCInst();
472  OutMI.setOpcode(Opcode);
473  OutMI.addOperand(Saved);
474  break;
475  }
476 
477  case X86::EH_RETURN:
478  case X86::EH_RETURN64: {
479  OutMI = MCInst();
480  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
481  break;
482  }
483 
484  case X86::CLEANUPRET: {
485  // Replace CATCHRET with the appropriate RET.
486  OutMI = MCInst();
487  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
488  break;
489  }
490 
491  case X86::CATCHRET: {
492  // Replace CATCHRET with the appropriate RET.
493  const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
494  unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
495  OutMI = MCInst();
496  OutMI.setOpcode(getRetOpcode(Subtarget));
497  OutMI.addOperand(MCOperand::createReg(ReturnReg));
498  break;
499  }
500 
501  // TAILJMPd, TAILJMPd64 - Lower to the correct jump instruction.
502  { unsigned Opcode;
503  case X86::TAILJMPr: Opcode = X86::JMP32r; goto SetTailJmpOpcode;
504  case X86::TAILJMPd:
505  case X86::TAILJMPd64: Opcode = X86::JMP_1; goto SetTailJmpOpcode;
506 
507  SetTailJmpOpcode:
508  MCOperand Saved = OutMI.getOperand(0);
509  OutMI = MCInst();
510  OutMI.setOpcode(Opcode);
511  OutMI.addOperand(Saved);
512  break;
513  }
514 
515  case X86::DEC16r:
516  case X86::DEC32r:
517  case X86::INC16r:
518  case X86::INC32r:
519  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
520  if (!AsmPrinter.getSubtarget().is64Bit()) {
521  unsigned Opcode;
522  switch (OutMI.getOpcode()) {
523  default: llvm_unreachable("Invalid opcode");
524  case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
525  case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
526  case X86::INC16r: Opcode = X86::INC16r_alt; break;
527  case X86::INC32r: Opcode = X86::INC32r_alt; break;
528  }
529  OutMI.setOpcode(Opcode);
530  }
531  break;
532 
533  // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
534  // this with an ugly goto in case the resultant OR uses EAX and needs the
535  // short form.
536  case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
537  case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
538  case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
539  case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
540  case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
541  case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
542  case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
543  case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
544  case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
545 
546  // Atomic load and store require a separate pseudo-inst because Acquire
547  // implies mayStore and Release implies mayLoad; fix these to regular MOV
548  // instructions here
549  case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
550  case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
551  case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
552  case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
553  case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
554  case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
555  case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
556  case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
557  case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
558  case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
559  case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
560  case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
561  case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
562  case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify;
563  case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
564  case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify;
565  case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
566  case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify;
567  case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
568  case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify;
569  case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
570  case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify;
571  case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
572  case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify;
573  case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
574  case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify;
575  case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
576  case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify;
577  case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
578  case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify;
579  case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
580  case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify;
581  case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
582  case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify;
583  case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
584  case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify;
585  case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
586  case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
587  case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
588  case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
589  case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
590  case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
591  case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
592  case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
593 
594  // We don't currently select the correct instruction form for instructions
595  // which have a short %eax, etc. form. Handle this by custom lowering, for
596  // now.
597  //
598  // Note, we are currently not handling the following instructions:
599  // MOV64ao8, MOV64o8a
600  // XCHG16ar, XCHG32ar, XCHG64ar
601  case X86::MOV8mr_NOREX:
602  case X86::MOV8mr:
603  case X86::MOV8rm_NOREX:
604  case X86::MOV8rm:
605  case X86::MOV16mr:
606  case X86::MOV16rm:
607  case X86::MOV32mr:
608  case X86::MOV32rm: {
609  unsigned NewOpc;
610  switch (OutMI.getOpcode()) {
611  default: llvm_unreachable("Invalid opcode");
612  case X86::MOV8mr_NOREX:
613  case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
614  case X86::MOV8rm_NOREX:
615  case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
616  case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
617  case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
618  case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
619  case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
620  }
621  SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
622  break;
623  }
624 
625  case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
626  case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
627  case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
628  case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
629  case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
630  case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
631  case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
632  case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
633  case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
634  unsigned NewOpc;
635  switch (OutMI.getOpcode()) {
636  default: llvm_unreachable("Invalid opcode");
637  case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
638  case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
639  case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
640  case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
641  case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
642  case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
643  case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
644  case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
645  case X86::AND8ri: NewOpc = X86::AND8i8; break;
646  case X86::AND16ri: NewOpc = X86::AND16i16; break;
647  case X86::AND32ri: NewOpc = X86::AND32i32; break;
648  case X86::AND64ri32: NewOpc = X86::AND64i32; break;
649  case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
650  case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
651  case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
652  case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
653  case X86::OR8ri: NewOpc = X86::OR8i8; break;
654  case X86::OR16ri: NewOpc = X86::OR16i16; break;
655  case X86::OR32ri: NewOpc = X86::OR32i32; break;
656  case X86::OR64ri32: NewOpc = X86::OR64i32; break;
657  case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
658  case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
659  case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
660  case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
661  case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
662  case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
663  case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
664  case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
665  case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
666  case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
667  case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
668  case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
669  case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
670  case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
671  case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
672  case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
673  }
674  SimplifyShortImmForm(OutMI, NewOpc);
675  break;
676  }
677 
678  // Try to shrink some forms of movsx.
679  case X86::MOVSX16rr8:
680  case X86::MOVSX32rr16:
681  case X86::MOVSX64rr32:
682  SimplifyMOVSX(OutMI);
683  break;
684  }
685 }
686 
687 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
688  const MachineInstr &MI) {
689 
690  bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
691  MI.getOpcode() == X86::TLS_base_addr64;
692 
693  bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
694 
695  MCContext &context = OutStreamer->getContext();
696 
697  if (needsPadding)
698  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
699 
701  switch (MI.getOpcode()) {
702  case X86::TLS_addr32:
703  case X86::TLS_addr64:
705  break;
706  case X86::TLS_base_addr32:
708  break;
709  case X86::TLS_base_addr64:
711  break;
712  default:
713  llvm_unreachable("unexpected opcode");
714  }
715 
716  MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
717  const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
718 
719  MCInst LEA;
720  if (is64Bits) {
721  LEA.setOpcode(X86::LEA64r);
722  LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
723  LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
724  LEA.addOperand(MCOperand::createImm(1)); // scale
725  LEA.addOperand(MCOperand::createReg(0)); // index
726  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
727  LEA.addOperand(MCOperand::createReg(0)); // seg
728  } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
729  LEA.setOpcode(X86::LEA32r);
730  LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
731  LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
732  LEA.addOperand(MCOperand::createImm(1)); // scale
733  LEA.addOperand(MCOperand::createReg(0)); // index
734  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
735  LEA.addOperand(MCOperand::createReg(0)); // seg
736  } else {
737  LEA.setOpcode(X86::LEA32r);
738  LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
739  LEA.addOperand(MCOperand::createReg(0)); // base
740  LEA.addOperand(MCOperand::createImm(1)); // scale
741  LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
742  LEA.addOperand(MCOperand::createExpr(symRef)); // disp
743  LEA.addOperand(MCOperand::createReg(0)); // seg
744  }
745  EmitAndCountInstruction(LEA);
746 
747  if (needsPadding) {
748  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
749  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
750  EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
751  }
752 
753  StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
754  MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
755  const MCSymbolRefExpr *tlsRef =
756  MCSymbolRefExpr::create(tlsGetAddr,
758  context);
759 
760  EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
761  : X86::CALLpcrel32)
762  .addExpr(tlsRef));
763 }
764 
765 /// \brief Emit the largest nop instruction smaller than or equal to \p NumBytes
766 /// bytes. Return the size of nop emitted.
767 static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
768  const MCSubtargetInfo &STI) {
769  // This works only for 64bit. For 32bit we have to do additional checking if
770  // the CPU supports multi-byte nops.
771  assert(Is64Bit && "EmitNops only supports X86-64");
772 
773  unsigned NopSize;
774  unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
775  Opc = IndexReg = Displacement = SegmentReg = 0;
776  BaseReg = X86::RAX;
777  ScaleVal = 1;
778  switch (NumBytes) {
779  case 0: llvm_unreachable("Zero nops?"); break;
780  case 1: NopSize = 1; Opc = X86::NOOP; break;
781  case 2: NopSize = 2; Opc = X86::XCHG16ar; break;
782  case 3: NopSize = 3; Opc = X86::NOOPL; break;
783  case 4: NopSize = 4; Opc = X86::NOOPL; Displacement = 8; break;
784  case 5: NopSize = 5; Opc = X86::NOOPL; Displacement = 8;
785  IndexReg = X86::RAX; break;
786  case 6: NopSize = 6; Opc = X86::NOOPW; Displacement = 8;
787  IndexReg = X86::RAX; break;
788  case 7: NopSize = 7; Opc = X86::NOOPL; Displacement = 512; break;
789  case 8: NopSize = 8; Opc = X86::NOOPL; Displacement = 512;
790  IndexReg = X86::RAX; break;
791  case 9: NopSize = 9; Opc = X86::NOOPW; Displacement = 512;
792  IndexReg = X86::RAX; break;
793  default: NopSize = 10; Opc = X86::NOOPW; Displacement = 512;
794  IndexReg = X86::RAX; SegmentReg = X86::CS; break;
795  }
796 
797  unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
798  NopSize += NumPrefixes;
799  for (unsigned i = 0; i != NumPrefixes; ++i)
800  OS.EmitBytes("\x66");
801 
802  switch (Opc) {
803  default:
804  llvm_unreachable("Unexpected opcode");
805  break;
806  case X86::NOOP:
807  OS.EmitInstruction(MCInstBuilder(Opc), STI);
808  break;
809  case X86::XCHG16ar:
810  OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
811  break;
812  case X86::NOOPL:
813  case X86::NOOPW:
815  .addReg(BaseReg)
816  .addImm(ScaleVal)
817  .addReg(IndexReg)
818  .addImm(Displacement)
819  .addReg(SegmentReg),
820  STI);
821  break;
822  }
823  assert(NopSize <= NumBytes && "We overemitted?");
824  return NopSize;
825 }
826 
827 /// \brief Emit the optimal amount of multi-byte nops on X86.
828 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
829  const MCSubtargetInfo &STI) {
830  unsigned NopsToEmit = NumBytes;
831  (void)NopsToEmit;
832  while (NumBytes) {
833  NumBytes -= EmitNop(OS, NumBytes, Is64Bit, STI);
834  assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
835  }
836 }
837 
838 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
839  X86MCInstLower &MCIL) {
840  assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
841 
842  StatepointOpers SOpers(&MI);
843  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
844  EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
845  getSubtargetInfo());
846  } else {
847  // Lower call target and choose correct opcode
848  const MachineOperand &CallTarget = SOpers.getCallTarget();
849  MCOperand CallTargetMCOp;
850  unsigned CallOpcode;
851  switch (CallTarget.getType()) {
854  CallTargetMCOp = MCIL.LowerSymbolOperand(
855  CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
856  CallOpcode = X86::CALL64pcrel32;
857  // Currently, we only support relative addressing with statepoints.
858  // Otherwise, we'll need a scratch register to hold the target
859  // address. You'll fail asserts during load & relocation if this
860  // symbol is to far away. (TODO: support non-relative addressing)
861  break;
863  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
864  CallOpcode = X86::CALL64pcrel32;
865  // Currently, we only support relative addressing with statepoints.
866  // Otherwise, we'll need a scratch register to hold the target
867  // immediate. You'll fail asserts during load & relocation if this
868  // address is to far away. (TODO: support non-relative addressing)
869  break;
871  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
872  CallOpcode = X86::CALL64r;
873  break;
874  default:
875  llvm_unreachable("Unsupported operand type in statepoint call target");
876  break;
877  }
878 
879  // Emit call
881  CallInst.setOpcode(CallOpcode);
882  CallInst.addOperand(CallTargetMCOp);
883  OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
884  }
885 
886  // Record our statepoint node in the same section used by STACKMAP
887  // and PATCHPOINT
888  SM.recordStatepoint(MI);
889 }
890 
891 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI,
892  X86MCInstLower &MCIL) {
893  // FAULTING_LOAD_OP <def>, <MBB handler>, <load opcode>, <load operands>
894 
895  unsigned LoadDefRegister = MI.getOperand(0).getReg();
896  MCSymbol *HandlerLabel = MI.getOperand(1).getMBB()->getSymbol();
897  unsigned LoadOpcode = MI.getOperand(2).getImm();
898  unsigned LoadOperandsBeginIdx = 3;
899 
900  FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel);
901 
902  MCInst LoadMI;
903  LoadMI.setOpcode(LoadOpcode);
904 
905  if (LoadDefRegister != X86::NoRegister)
906  LoadMI.addOperand(MCOperand::createReg(LoadDefRegister));
907 
908  for (auto I = MI.operands_begin() + LoadOperandsBeginIdx,
909  E = MI.operands_end();
910  I != E; ++I)
911  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I))
912  LoadMI.addOperand(MaybeOperand.getValue());
913 
914  OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo());
915 }
916 
917 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
918  X86MCInstLower &MCIL) {
919  // PATCHABLE_OP minsize, opcode, operands
920 
921  unsigned MinSize = MI.getOperand(0).getImm();
922  unsigned Opcode = MI.getOperand(1).getImm();
923 
924  MCInst MCI;
925  MCI.setOpcode(Opcode);
926  for (auto &MO : make_range(MI.operands_begin() + 2, MI.operands_end()))
927  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
928  MCI.addOperand(MaybeOperand.getValue());
929 
930  SmallString<256> Code;
932  raw_svector_ostream VecOS(Code);
933  CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
934 
935  if (Code.size() < MinSize) {
936  if (MinSize == 2 && Opcode == X86::PUSH64r) {
937  // This is an optimization that lets us get away without emitting a nop in
938  // many cases.
939  //
940  // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %R9) takes two
941  // bytes too, so the check on MinSize is important.
942  MCI.setOpcode(X86::PUSH64rmr);
943  } else {
944  unsigned NopSize = EmitNop(*OutStreamer, MinSize, Subtarget->is64Bit(),
945  getSubtargetInfo());
946  assert(NopSize == MinSize && "Could not implement MinSize!");
947  (void) NopSize;
948  }
949  }
950 
951  OutStreamer->EmitInstruction(MCI, getSubtargetInfo());
952 }
953 
954 // Lower a stackmap of the form:
955 // <id>, <shadowBytes>, ...
956 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
957  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
958  SM.recordStackMap(MI);
959  unsigned NumShadowBytes = MI.getOperand(1).getImm();
960  SMShadowTracker.reset(NumShadowBytes);
961 }
962 
963 // Lower a patchpoint of the form:
964 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
965 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
966  X86MCInstLower &MCIL) {
967  assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
968 
969  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
970 
971  SM.recordPatchPoint(MI);
972 
973  PatchPointOpers opers(&MI);
974  unsigned ScratchIdx = opers.getNextScratchIdx();
975  unsigned EncodedBytes = 0;
976  const MachineOperand &CalleeMO = opers.getCallTarget();
977 
978  // Check for null target. If target is non-null (i.e. is non-zero or is
979  // symbolic) then emit a call.
980  if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
981  MCOperand CalleeMCOp;
982  switch (CalleeMO.getType()) {
983  default:
984  /// FIXME: Add a verifier check for bad callee types.
985  llvm_unreachable("Unrecognized callee operand type.");
987  if (CalleeMO.getImm())
988  CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
989  break;
992  CalleeMCOp =
993  MCIL.LowerSymbolOperand(CalleeMO,
994  MCIL.GetSymbolFromOperand(CalleeMO));
995  break;
996  }
997 
998  // Emit MOV to materialize the target address and the CALL to target.
999  // This is encoded with 12-13 bytes, depending on which register is used.
1000  unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
1001  if (X86II::isX86_64ExtendedReg(ScratchReg))
1002  EncodedBytes = 13;
1003  else
1004  EncodedBytes = 12;
1005 
1006  EmitAndCountInstruction(
1007  MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1008  EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1009  }
1010 
1011  // Emit padding.
1012  unsigned NumBytes = opers.getNumPatchBytes();
1013  assert(NumBytes >= EncodedBytes &&
1014  "Patchpoint can't request size less than the length of a call.");
1015 
1016  EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
1017  getSubtargetInfo());
1018 }
1019 
1020 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1021  X86MCInstLower &MCIL) {
1022  // We want to emit the following pattern:
1023  //
1024  // .p2align 1, ...
1025  // .Lxray_sled_N:
1026  // jmp .tmpN
1027  // # 9 bytes worth of noops
1028  // .tmpN
1029  //
1030  // We need the 9 bytes because at runtime, we'd be patching over the full 11
1031  // bytes with the following pattern:
1032  //
1033  // mov %r10, <function id, 32-bit> // 6 bytes
1034  // call <relative offset, 32-bits> // 5 bytes
1035  //
1036  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1037  OutStreamer->EmitCodeAlignment(2);
1038  OutStreamer->EmitLabel(CurSled);
1040 
1041  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1042  // an operand (computed as an offset from the jmp instruction).
1043  // FIXME: Find another less hacky way do force the relative jump.
1044  OutStreamer->EmitBytes("\xeb\x09");
1045  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1046  OutStreamer->EmitLabel(Target);
1047  recordSled(CurSled, MI, SledKind::FUNCTION_ENTER);
1048 }
1049 
1050 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1051  X86MCInstLower &MCIL) {
1052  // Since PATCHABLE_RET takes the opcode of the return statement as an
1053  // argument, we use that to emit the correct form of the RET that we want.
1054  // i.e. when we see this:
1055  //
1056  // PATCHABLE_RET X86::RET ...
1057  //
1058  // We should emit the RET followed by sleds.
1059  //
1060  // .p2align 1, ...
1061  // .Lxray_sled_N:
1062  // ret # or equivalent instruction
1063  // # 10 bytes worth of noops
1064  //
1065  // This just makes sure that the alignment for the next instruction is 2.
1066  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1067  OutStreamer->EmitCodeAlignment(2);
1068  OutStreamer->EmitLabel(CurSled);
1069  unsigned OpCode = MI.getOperand(0).getImm();
1070  MCInst Ret;
1071  Ret.setOpcode(OpCode);
1072  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1073  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1074  Ret.addOperand(MaybeOperand.getValue());
1075  OutStreamer->EmitInstruction(Ret, getSubtargetInfo());
1076  EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo());
1077  recordSled(CurSled, MI, SledKind::FUNCTION_EXIT);
1078 }
1079 
1080 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL) {
1081  // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1082  // instruction so we lower that particular instruction and its operands.
1083  // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1084  // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1085  // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1086  // tail call much like how we have it in PATCHABLE_RET.
1087  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1088  OutStreamer->EmitCodeAlignment(2);
1089  OutStreamer->EmitLabel(CurSled);
1091 
1092  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1093  // an operand (computed as an offset from the jmp instruction).
1094  // FIXME: Find another less hacky way do force the relative jump.
1095  OutStreamer->EmitBytes("\xeb\x09");
1096  EmitNops(*OutStreamer, 9, Subtarget->is64Bit(), getSubtargetInfo());
1097  OutStreamer->EmitLabel(Target);
1098  recordSled(CurSled, MI, SledKind::TAIL_CALL);
1099 
1100  unsigned OpCode = MI.getOperand(0).getImm();
1101  MCInst TC;
1102  TC.setOpcode(OpCode);
1103 
1104  // Before emitting the instruction, add a comment to indicate that this is
1105  // indeed a tail call.
1106  OutStreamer->AddComment("TAILCALL");
1107  for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end()))
1108  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1109  TC.addOperand(MaybeOperand.getValue());
1110  OutStreamer->EmitInstruction(TC, getSubtargetInfo());
1111 }
1112 
1113 // Returns instruction preceding MBBI in MachineFunction.
1114 // If MBBI is the first instruction of the first basic block, returns null.
1117  const MachineBasicBlock *MBB = MBBI->getParent();
1118  while (MBBI == MBB->begin()) {
1119  if (MBB == &MBB->getParent()->front())
1121  MBB = MBB->getPrevNode();
1122  MBBI = MBB->end();
1123  }
1124  return --MBBI;
1125 }
1126 
1128  const MachineOperand &Op) {
1129  if (!Op.isCPI())
1130  return nullptr;
1131 
1134  const MachineConstantPoolEntry &ConstantEntry =
1135  Constants[Op.getIndex()];
1136 
1137  // Bail if this is a machine constant pool entry, we won't be able to dig out
1138  // anything useful.
1139  if (ConstantEntry.isMachineConstantPoolEntry())
1140  return nullptr;
1141 
1142  auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
1143  assert((!C || ConstantEntry.getType() == C->getType()) &&
1144  "Expected a constant of the same type!");
1145  return C;
1146 }
1147 
1148 static std::string getShuffleComment(const MachineInstr *MI,
1149  unsigned SrcOp1Idx,
1150  unsigned SrcOp2Idx,
1151  ArrayRef<int> Mask) {
1152  std::string Comment;
1153 
1154  // Compute the name for a register. This is really goofy because we have
1155  // multiple instruction printers that could (in theory) use different
1156  // names. Fortunately most people use the ATT style (outside of Windows)
1157  // and they actually agree on register naming here. Ultimately, this is
1158  // a comment, and so its OK if it isn't perfect.
1159  auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1160  return X86ATTInstPrinter::getRegisterName(RegNum);
1161  };
1162 
1163  const MachineOperand &DstOp = MI->getOperand(0);
1164  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1165  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1166 
1167  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1168  StringRef Src1Name =
1169  SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1170  StringRef Src2Name =
1171  SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1172 
1173  // One source operand, fix the mask to print all elements in one span.
1174  SmallVector<int, 8> ShuffleMask(Mask.begin(), Mask.end());
1175  if (Src1Name == Src2Name)
1176  for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1177  if (ShuffleMask[i] >= e)
1178  ShuffleMask[i] -= e;
1179 
1180  raw_string_ostream CS(Comment);
1181  CS << DstName;
1182 
1183  // Handle AVX512 MASK/MASXZ write mask comments.
1184  // MASK: zmmX {%kY}
1185  // MASKZ: zmmX {%kY} {z}
1186  if (SrcOp1Idx > 1) {
1187  assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1188 
1189  const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1190  if (WriteMaskOp.isReg()) {
1191  CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1192 
1193  if (SrcOp1Idx == 2) {
1194  CS << " {z}";
1195  }
1196  }
1197  }
1198 
1199  CS << " = ";
1200 
1201  for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1202  if (i != 0)
1203  CS << ",";
1204  if (ShuffleMask[i] == SM_SentinelZero) {
1205  CS << "zero";
1206  continue;
1207  }
1208 
1209  // Otherwise, it must come from src1 or src2. Print the span of elements
1210  // that comes from this src.
1211  bool isSrc1 = ShuffleMask[i] < (int)e;
1212  CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1213 
1214  bool IsFirst = true;
1215  while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1216  (ShuffleMask[i] < (int)e) == isSrc1) {
1217  if (!IsFirst)
1218  CS << ',';
1219  else
1220  IsFirst = false;
1221  if (ShuffleMask[i] == SM_SentinelUndef)
1222  CS << "u";
1223  else
1224  CS << ShuffleMask[i] % (int)e;
1225  ++i;
1226  }
1227  CS << ']';
1228  --i; // For loop increments element #.
1229  }
1230  CS.flush();
1231 
1232  return Comment;
1233 }
1234 
1236  X86MCInstLower MCInstLowering(*MF, *this);
1237  const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1238 
1239  // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
1240  // are compressed from EVEX encoding to VEX encoding.
1242  if (MI->getAsmPrinterFlags() & AC_EVEX_2_VEX)
1243  OutStreamer->AddComment("EVEX TO VEX Compression ", false);
1244  }
1245 
1246  switch (MI->getOpcode()) {
1247  case TargetOpcode::DBG_VALUE:
1248  llvm_unreachable("Should be handled target independently");
1249 
1250  // Emit nothing here but a comment if we can.
1251  case X86::Int_MemBarrier:
1252  OutStreamer->emitRawComment("MEMBARRIER");
1253  return;
1254 
1255 
1256  case X86::EH_RETURN:
1257  case X86::EH_RETURN64: {
1258  // Lower these as normal, but add some comments.
1259  unsigned Reg = MI->getOperand(0).getReg();
1260  OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1262  break;
1263  }
1264  case X86::CLEANUPRET: {
1265  // Lower these as normal, but add some comments.
1266  OutStreamer->AddComment("CLEANUPRET");
1267  break;
1268  }
1269 
1270  case X86::CATCHRET: {
1271  // Lower these as normal, but add some comments.
1272  OutStreamer->AddComment("CATCHRET");
1273  break;
1274  }
1275 
1276  case X86::TAILJMPr:
1277  case X86::TAILJMPm:
1278  case X86::TAILJMPd:
1279  case X86::TAILJMPr64:
1280  case X86::TAILJMPm64:
1281  case X86::TAILJMPd64:
1282  case X86::TAILJMPr64_REX:
1283  case X86::TAILJMPm64_REX:
1284  // Lower these as normal, but add some comments.
1285  OutStreamer->AddComment("TAILCALL");
1286  break;
1287 
1288  case X86::TLS_addr32:
1289  case X86::TLS_addr64:
1290  case X86::TLS_base_addr32:
1291  case X86::TLS_base_addr64:
1292  return LowerTlsAddr(MCInstLowering, *MI);
1293 
1294  case X86::MOVPC32r: {
1295  // This is a pseudo op for a two instruction sequence with a label, which
1296  // looks like:
1297  // call "L1$pb"
1298  // "L1$pb":
1299  // popl %esi
1300 
1301  // Emit the call.
1302  MCSymbol *PICBase = MF->getPICBaseSymbol();
1303  // FIXME: We would like an efficient form for this, so we don't have to do a
1304  // lot of extra uniquing.
1305  EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1306  .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1307 
1308  const X86FrameLowering* FrameLowering =
1309  MF->getSubtarget<X86Subtarget>().getFrameLowering();
1310  bool hasFP = FrameLowering->hasFP(*MF);
1311 
1312  // TODO: This is needed only if we require precise CFA.
1313  bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
1314  !OutStreamer->getDwarfFrameInfos().back().End;
1315 
1316  int stackGrowth = -RI->getSlotSize();
1317 
1318  if (HasActiveDwarfFrame && !hasFP) {
1319  OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth);
1320  }
1321 
1322  // Emit the label.
1323  OutStreamer->EmitLabel(PICBase);
1324 
1325  // popl $reg
1326  EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1327  .addReg(MI->getOperand(0).getReg()));
1328 
1329  if (HasActiveDwarfFrame && !hasFP) {
1330  OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth);
1331  }
1332  return;
1333  }
1334 
1335  case X86::ADD32ri: {
1336  // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1338  break;
1339 
1340  // Okay, we have something like:
1341  // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1342 
1343  // For this, we want to print something like:
1344  // MYGLOBAL + (. - PICBASE)
1345  // However, we can't generate a ".", so just emit a new label here and refer
1346  // to it.
1347  MCSymbol *DotSym = OutContext.createTempSymbol();
1348  OutStreamer->EmitLabel(DotSym);
1349 
1350  // Now that we have emitted the label, lower the complex operand expression.
1351  MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1352 
1353  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1354  const MCExpr *PICBase =
1356  DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1357 
1359  DotExpr, OutContext);
1360 
1361  EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1362  .addReg(MI->getOperand(0).getReg())
1363  .addReg(MI->getOperand(1).getReg())
1364  .addExpr(DotExpr));
1365  return;
1366  }
1367  case TargetOpcode::STATEPOINT:
1368  return LowerSTATEPOINT(*MI, MCInstLowering);
1369 
1370  case TargetOpcode::FAULTING_LOAD_OP:
1371  return LowerFAULTING_LOAD_OP(*MI, MCInstLowering);
1372 
1373  case TargetOpcode::PATCHABLE_OP:
1374  return LowerPATCHABLE_OP(*MI, MCInstLowering);
1375 
1376  case TargetOpcode::STACKMAP:
1377  return LowerSTACKMAP(*MI);
1378 
1379  case TargetOpcode::PATCHPOINT:
1380  return LowerPATCHPOINT(*MI, MCInstLowering);
1381 
1382  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1383  return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
1384 
1385  case TargetOpcode::PATCHABLE_RET:
1386  return LowerPATCHABLE_RET(*MI, MCInstLowering);
1387 
1388  case TargetOpcode::PATCHABLE_TAIL_CALL:
1389  return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
1390 
1391  case X86::MORESTACK_RET:
1392  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1393  return;
1394 
1395  case X86::MORESTACK_RET_RESTORE_R10:
1396  // Return, then restore R10.
1397  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1398  EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1399  .addReg(X86::R10)
1400  .addReg(X86::RAX));
1401  return;
1402 
1403  case X86::SEH_PushReg:
1404  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1405  OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1406  return;
1407 
1408  case X86::SEH_SaveReg:
1409  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1410  OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1411  MI->getOperand(1).getImm());
1412  return;
1413 
1414  case X86::SEH_SaveXMM:
1415  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1416  OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1417  MI->getOperand(1).getImm());
1418  return;
1419 
1420  case X86::SEH_StackAlloc:
1421  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1422  OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1423  return;
1424 
1425  case X86::SEH_SetFrame:
1426  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1427  OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1428  MI->getOperand(1).getImm());
1429  return;
1430 
1431  case X86::SEH_PushFrame:
1432  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1433  OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1434  return;
1435 
1436  case X86::SEH_EndPrologue:
1437  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1438  OutStreamer->EmitWinCFIEndProlog();
1439  return;
1440 
1441  case X86::SEH_Epilogue: {
1442  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1444  // Check if preceded by a call and emit nop if so.
1445  for (MBBI = PrevCrossBBInst(MBBI);
1447  MBBI = PrevCrossBBInst(MBBI)) {
1448  // Conservatively assume that pseudo instructions don't emit code and keep
1449  // looking for a call. We may emit an unnecessary nop in some cases.
1450  if (!MBBI->isPseudo()) {
1451  if (MBBI->isCall())
1452  EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1453  break;
1454  }
1455  }
1456  return;
1457  }
1458 
1459  // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1460  // a constant shuffle mask. We won't be able to do this at the MC layer
1461  // because the mask isn't an immediate.
1462  case X86::PSHUFBrm:
1463  case X86::VPSHUFBrm:
1464  case X86::VPSHUFBYrm:
1465  case X86::VPSHUFBZ128rm:
1466  case X86::VPSHUFBZ128rmk:
1467  case X86::VPSHUFBZ128rmkz:
1468  case X86::VPSHUFBZ256rm:
1469  case X86::VPSHUFBZ256rmk:
1470  case X86::VPSHUFBZ256rmkz:
1471  case X86::VPSHUFBZrm:
1472  case X86::VPSHUFBZrmk:
1473  case X86::VPSHUFBZrmkz: {
1474  if (!OutStreamer->isVerboseAsm())
1475  break;
1476  unsigned SrcIdx, MaskIdx;
1477  switch (MI->getOpcode()) {
1478  default: llvm_unreachable("Invalid opcode");
1479  case X86::PSHUFBrm:
1480  case X86::VPSHUFBrm:
1481  case X86::VPSHUFBYrm:
1482  case X86::VPSHUFBZ128rm:
1483  case X86::VPSHUFBZ256rm:
1484  case X86::VPSHUFBZrm:
1485  SrcIdx = 1; MaskIdx = 5; break;
1486  case X86::VPSHUFBZ128rmkz:
1487  case X86::VPSHUFBZ256rmkz:
1488  case X86::VPSHUFBZrmkz:
1489  SrcIdx = 2; MaskIdx = 6; break;
1490  case X86::VPSHUFBZ128rmk:
1491  case X86::VPSHUFBZ256rmk:
1492  case X86::VPSHUFBZrmk:
1493  SrcIdx = 3; MaskIdx = 7; break;
1494  }
1495 
1496  assert(MI->getNumOperands() >= 6 &&
1497  "We should always have at least 6 operands!");
1498 
1499  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1500  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1502  DecodePSHUFBMask(C, Mask);
1503  if (!Mask.empty())
1504  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1505  }
1506  break;
1507  }
1508 
1509  case X86::VPERMILPSrm:
1510  case X86::VPERMILPSYrm:
1511  case X86::VPERMILPSZ128rm:
1512  case X86::VPERMILPSZ128rmk:
1513  case X86::VPERMILPSZ128rmkz:
1514  case X86::VPERMILPSZ256rm:
1515  case X86::VPERMILPSZ256rmk:
1516  case X86::VPERMILPSZ256rmkz:
1517  case X86::VPERMILPSZrm:
1518  case X86::VPERMILPSZrmk:
1519  case X86::VPERMILPSZrmkz:
1520  case X86::VPERMILPDrm:
1521  case X86::VPERMILPDYrm:
1522  case X86::VPERMILPDZ128rm:
1523  case X86::VPERMILPDZ128rmk:
1524  case X86::VPERMILPDZ128rmkz:
1525  case X86::VPERMILPDZ256rm:
1526  case X86::VPERMILPDZ256rmk:
1527  case X86::VPERMILPDZ256rmkz:
1528  case X86::VPERMILPDZrm:
1529  case X86::VPERMILPDZrmk:
1530  case X86::VPERMILPDZrmkz: {
1531  if (!OutStreamer->isVerboseAsm())
1532  break;
1533  unsigned SrcIdx, MaskIdx;
1534  unsigned ElSize;
1535  switch (MI->getOpcode()) {
1536  default: llvm_unreachable("Invalid opcode");
1537  case X86::VPERMILPSrm:
1538  case X86::VPERMILPSYrm:
1539  case X86::VPERMILPSZ128rm:
1540  case X86::VPERMILPSZ256rm:
1541  case X86::VPERMILPSZrm:
1542  SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
1543  case X86::VPERMILPSZ128rmkz:
1544  case X86::VPERMILPSZ256rmkz:
1545  case X86::VPERMILPSZrmkz:
1546  SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
1547  case X86::VPERMILPSZ128rmk:
1548  case X86::VPERMILPSZ256rmk:
1549  case X86::VPERMILPSZrmk:
1550  SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
1551  case X86::VPERMILPDrm:
1552  case X86::VPERMILPDYrm:
1553  case X86::VPERMILPDZ128rm:
1554  case X86::VPERMILPDZ256rm:
1555  case X86::VPERMILPDZrm:
1556  SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
1557  case X86::VPERMILPDZ128rmkz:
1558  case X86::VPERMILPDZ256rmkz:
1559  case X86::VPERMILPDZrmkz:
1560  SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
1561  case X86::VPERMILPDZ128rmk:
1562  case X86::VPERMILPDZ256rmk:
1563  case X86::VPERMILPDZrmk:
1564  SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
1565  }
1566 
1567  assert(MI->getNumOperands() >= 6 &&
1568  "We should always have at least 6 operands!");
1569 
1570  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
1571  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1573  DecodeVPERMILPMask(C, ElSize, Mask);
1574  if (!Mask.empty())
1575  OutStreamer->AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1576  }
1577  break;
1578  }
1579 
1580  case X86::VPERMIL2PDrm:
1581  case X86::VPERMIL2PSrm:
1582  case X86::VPERMIL2PDrmY:
1583  case X86::VPERMIL2PSrmY: {
1584  if (!OutStreamer->isVerboseAsm())
1585  break;
1586  assert(MI->getNumOperands() >= 8 &&
1587  "We should always have at least 8 operands!");
1588 
1589  const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
1590  if (!CtrlOp.isImm())
1591  break;
1592 
1593  unsigned ElSize;
1594  switch (MI->getOpcode()) {
1595  default: llvm_unreachable("Invalid opcode");
1596  case X86::VPERMIL2PSrm: case X86::VPERMIL2PSrmY: ElSize = 32; break;
1597  case X86::VPERMIL2PDrm: case X86::VPERMIL2PDrmY: ElSize = 64; break;
1598  }
1599 
1600  const MachineOperand &MaskOp = MI->getOperand(6);
1601  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1603  DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Mask);
1604  if (!Mask.empty())
1605  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
1606  }
1607  break;
1608  }
1609 
1610  case X86::VPPERMrrm: {
1611  if (!OutStreamer->isVerboseAsm())
1612  break;
1613  assert(MI->getNumOperands() >= 7 &&
1614  "We should always have at least 7 operands!");
1615 
1616  const MachineOperand &MaskOp = MI->getOperand(6);
1617  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1619  DecodeVPPERMMask(C, Mask);
1620  if (!Mask.empty())
1621  OutStreamer->AddComment(getShuffleComment(MI, 1, 2, Mask));
1622  }
1623  break;
1624  }
1625 
1626 #define MOV_CASE(Prefix, Suffix) \
1627  case X86::Prefix##MOVAPD##Suffix##rm: \
1628  case X86::Prefix##MOVAPS##Suffix##rm: \
1629  case X86::Prefix##MOVUPD##Suffix##rm: \
1630  case X86::Prefix##MOVUPS##Suffix##rm: \
1631  case X86::Prefix##MOVDQA##Suffix##rm: \
1632  case X86::Prefix##MOVDQU##Suffix##rm:
1633 
1634 #define MOV_AVX512_CASE(Suffix) \
1635  case X86::VMOVDQA64##Suffix##rm: \
1636  case X86::VMOVDQA32##Suffix##rm: \
1637  case X86::VMOVDQU64##Suffix##rm: \
1638  case X86::VMOVDQU32##Suffix##rm: \
1639  case X86::VMOVDQU16##Suffix##rm: \
1640  case X86::VMOVDQU8##Suffix##rm: \
1641  case X86::VMOVAPS##Suffix##rm: \
1642  case X86::VMOVAPD##Suffix##rm: \
1643  case X86::VMOVUPS##Suffix##rm: \
1644  case X86::VMOVUPD##Suffix##rm:
1645 
1646 #define CASE_ALL_MOV_RM() \
1647  MOV_CASE(, ) /* SSE */ \
1648  MOV_CASE(V, ) /* AVX-128 */ \
1649  MOV_CASE(V, Y) /* AVX-256 */ \
1650  MOV_AVX512_CASE(Z) \
1651  MOV_AVX512_CASE(Z256) \
1652  MOV_AVX512_CASE(Z128)
1653 
1654  // For loads from a constant pool to a vector register, print the constant
1655  // loaded.
1656  CASE_ALL_MOV_RM()
1657  if (!OutStreamer->isVerboseAsm())
1658  break;
1659  if (MI->getNumOperands() <= 4)
1660  break;
1661  if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1662  std::string Comment;
1663  raw_string_ostream CS(Comment);
1664  const MachineOperand &DstOp = MI->getOperand(0);
1665  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1666  if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1667  CS << "[";
1668  for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1669  if (i != 0)
1670  CS << ",";
1671  if (CDS->getElementType()->isIntegerTy())
1672  CS << CDS->getElementAsInteger(i);
1673  else if (CDS->getElementType()->isFloatTy())
1674  CS << CDS->getElementAsFloat(i);
1675  else if (CDS->getElementType()->isDoubleTy())
1676  CS << CDS->getElementAsDouble(i);
1677  else
1678  CS << "?";
1679  }
1680  CS << "]";
1681  OutStreamer->AddComment(CS.str());
1682  } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1683  CS << "<";
1684  for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1685  if (i != 0)
1686  CS << ",";
1687  Constant *COp = CV->getOperand(i);
1688  if (isa<UndefValue>(COp)) {
1689  CS << "u";
1690  } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1691  if (CI->getBitWidth() <= 64) {
1692  CS << CI->getZExtValue();
1693  } else {
1694  // print multi-word constant as (w0,w1)
1695  const auto &Val = CI->getValue();
1696  CS << "(";
1697  for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1698  if (i > 0)
1699  CS << ",";
1700  CS << Val.getRawData()[i];
1701  }
1702  CS << ")";
1703  }
1704  } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1705  SmallString<32> Str;
1706  CF->getValueAPF().toString(Str);
1707  CS << Str;
1708  } else {
1709  CS << "?";
1710  }
1711  }
1712  CS << ">";
1713  OutStreamer->AddComment(CS.str());
1714  }
1715  }
1716  break;
1717  }
1718 
1719  MCInst TmpInst;
1720  MCInstLowering.Lower(MI, TmpInst);
1721 
1722  // Stackmap shadows cannot include branch targets, so we can count the bytes
1723  // in a call towards the shadow, but must ensure that the no thread returns
1724  // in to the stackmap shadow. The only way to achieve this is if the call
1725  // is at the end of the shadow.
1726  if (MI->isCall()) {
1727  // Count then size of the call towards the shadow
1728  SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
1729  // Then flush the shadow so that we fill with nops before the call, not
1730  // after it.
1731  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1732  // Then emit the call
1733  OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1734  return;
1735  }
1736 
1737  EmitAndCountInstruction(TmpInst);
1738 }
const NoneType None
Definition: None.h:23
bool isImplicit() const
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:299
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void DecodeVPERMILPMask(MVT VT, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
mop_iterator operands_end()
Definition: MachineInstr.h:296
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:284
const GlobalValue * getGlobal() const
static const char * getRegisterName(unsigned RegNo)
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:84
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:298
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:371
virtual void EmitWinCFIEndProlog()
Definition: MCStreamer.cpp:678
MCTargetOptions MCOptions
Machine level options.
size_t i
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:63
bool isReg() const
Definition: MCInst.h:56
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:123
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:209
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:79
static MachineModuleInfoMachO & getMachOMMI(AsmPrinter &AP)
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
iterator end() const
Definition: ArrayRef.h:130
virtual void EmitBytes(StringRef Data)
Emit the bytes in Data into the output.
Definition: MCStreamer.cpp:807
This class represents a function call, abstracting a target machine's calling convention.
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:87
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:490
const char * getSymbolName() const
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:97
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:166
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:156
static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the optimal amount of multi-byte nops on X86.
ArrayRef< MCDwarfFrameInfo > getDwarfFrameInfos() const
Definition: MCStreamer.h:228
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
print alias Alias Set Printer
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:765
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:366
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:606
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:197
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool hasInternalLinkage() const
Definition: GlobalValue.h:413
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:161
virtual bool isVerboseAsm() const
Return true if this streamer supports verbose assembly and if it is enabled.
Definition: MCStreamer.h:246
#define CASE_ALL_MOV_RM()
MCContext & getContext() const
Definition: MCStreamer.h:221
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:60
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Context object for machine code objects.
Definition: MCContext.h:51
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:28
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:269
const MachineBasicBlock & front() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:497
PointerTy getPointer() const
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:63
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:135
MachineBasicBlock * MBB
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:381
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:141
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:72
This class is a data container for one entry in a MachineConstantPool.
auto count(R &&Range, const E &Element) -> typename std::iterator_traits< decltype(std::begin(Range))>::difference_type
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:791
int64_t getImm() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:429
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:192
void recordStatepoint(const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:381
Maximum length of the test input libFuzzer tries to guess a good value based on the corpus and reports it always prefer smaller inputs during the corpus shuffle When libFuzzer itself reports a bug this exit code will be used If indicates the maximal total time in seconds to run the fuzzer minimizes the provided crash input Use with etc Experimental Use value profile to guide fuzzing Number of simultaneous worker processes to run the jobs If min(jobs, NumberOfCpuCores()/2)\" is used.") FUZZER_FLAG_INT(reload
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool isX86_64ExtendedReg(unsigned RegNo)
isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) register? e.g.
Definition: X86BaseInfo.h:732
bool isImm() const
Definition: MCInst.h:57
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:57
const MCExpr * getExpr() const
Definition: MCInst.h:93
Address of a global value.
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: ARMBaseInfo.h:305
unsigned getTargetFlags() const
Streaming machine code generation interface.
Definition: MCStreamer.h:161
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:218
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [...
Definition: X86BaseInfo.h:70
PointerIntPair - This class implements a pair of a pointer and small integer.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:182
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:203
virtual void EmitWinCFIPushReg(unsigned Register)
Definition: MCStreamer.cpp:604
This is an important base class in LLVM.
Definition: Constant.h:42
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind)
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:23
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:71
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:67
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isExpr() const
Definition: MCInst.h:59
iterator begin() const
Definition: ArrayRef.h:129
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
Value * getOperand(unsigned i) const
Definition: User.h:145
int64_t getOffset() const
Return the offset from the symbol in this operand.
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:174
MI-level patchpoint operands.
Definition: StackMaps.h:70
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
void DecodeVPERMIL2PMask(MVT VT, unsigned M2Z, ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:479
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void recordPatchPoint(const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:361
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:158
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
Definition: MCInst.h:158
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:293
virtual void EmitWinCFISaveXMM(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:655
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
virtual void EmitCodeAlignment(unsigned ByteAlignment, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:820
int getSEHRegNum(unsigned i) const
const X86Subtarget & getSubtarget() const
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void dump(const TargetInstrInfo *TII=nullptr) const
virtual void EmitWinCFIAllocStack(unsigned Size)
Definition: MCStreamer.cpp:630
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
unsigned getOpcode() const
Definition: MCInst.h:159
Target - Wrapper for Target specific information.
void recordStackMap(const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:352
int64_t getImm() const
Definition: MCInst.h:74
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:130
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:602
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:89
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
unsigned getNumFrameInfos()
Definition: MCStreamer.h:227
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:114
unsigned getNumOperands() const
Definition: MCInst.h:166
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
MCSymbol * getMCSymbol() const
MCSubtargetInfo - Generic base class for all target subtargets.
MI-level Statepoint operands.
Definition: StackMaps.h:145
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
unsigned getSlotSize() const
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin...
Definition: ISDOpcodes.h:102
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
mop_iterator operands_begin()
Definition: MachineInstr.h:295
static const char * name
MachineInstrBundleIterator< const MachineInstr > const_iterator
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
Primary interface to the complete machine description for the target machine.
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:75
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
virtual void EmitWinCFISaveReg(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:643
virtual void EmitWinCFIPushFrame(bool Code)
Definition: MCStreamer.cpp:667
const std::vector< MachineConstantPoolEntry > & getConstants() const
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
const BlockAddress * getBlockAddress() const
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
union llvm::MachineConstantPoolEntry::@35 Val
The constant itself.
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:66
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form...
virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment)
Definition: MCStreamer.cpp:372
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:164
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
virtual void EmitWinCFISetFrame(unsigned Register, unsigned Offset)
Definition: MCStreamer.cpp:613