LLVM  4.0.0
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HexagonCopyToCombine.cpp File Reference
#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/PassSupport.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
Include dependency graph for HexagonCopyToCombine.cpp:

Go to the source code of this file.

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Macros

#define DEBUG_TYPE   "hexagon-copy-combine"
 

Functions

FunctionPassllvm::createHexagonCopyToCombine ()
 
void llvm::initializeHexagonCopyToCombinePass (PassRegistry &)
 
 INITIALIZE_PASS (HexagonCopyToCombine,"hexagon-copy-combine","Hexagon Copy-To-Combine Pass", false, false) static bool isCombinableInstType(MachineInstr &MI
 
const HexagonInstrInfo bool
ShouldCombineAggressively 
switch (MI.getOpcode())
 
template<unsigned N>
static bool isGreaterThanNBitTFRI (const MachineInstr &I)
 
static bool areCombinableOperations (const TargetRegisterInfo *TRI, MachineInstr &HighRegInst, MachineInstr &LowRegInst, bool AllowC64)
 areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring register constraints). More...
 
static bool isEvenReg (unsigned Reg)
 
static void removeKillInfo (MachineInstr &MI, unsigned RegNotKilled)
 
static bool isUnsafeToMoveAcross (MachineInstr &MI, unsigned UseReg, unsigned DestReg, const TargetRegisterInfo *TRI)
 Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction MI. More...
 
static unsigned UseReg (const MachineOperand &MO)
 

Variables

static cl::opt< boolIsCombinesDisabled ("disable-merge-into-combines", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable merging into combines"))
 
static cl::opt< boolIsConst64Disabled ("disable-const64", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable generation of const64"))
 
static cl::opt< unsignedMaxNumOfInstsBetweenNewValueStoreAndTFR ("max-num-inst-between-tfr-and-nv-store", cl::Hidden, cl::init(4), cl::desc("Maximum distance between a tfr feeding a store we ""consider the store still to be newifiable"))
 
const HexagonInstrInfoTII
 
return false
 

Macro Definition Documentation

#define DEBUG_TYPE   "hexagon-copy-combine"

Definition at line 33 of file HexagonCopyToCombine.cpp.

Function Documentation

static bool areCombinableOperations ( const TargetRegisterInfo TRI,
MachineInstr HighRegInst,
MachineInstr LowRegInst,
bool  AllowC64 
)
static

areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring register constraints).

Definition at line 185 of file HexagonCopyToCombine.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), and llvm_unreachable.

INITIALIZE_PASS ( HexagonCopyToCombine  ,
"hexagon-copy-combine"  ,
"Hexagon Copy-To-Combine Pass ,
false  ,
false   
)
static bool isEvenReg ( unsigned  Reg)
static
template<unsigned N>
static bool isGreaterThanNBitTFRI ( const MachineInstr I)
static
static bool isUnsafeToMoveAcross ( MachineInstr MI,
unsigned  UseReg,
unsigned  DestReg,
const TargetRegisterInfo TRI 
)
static

Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction MI.

Definition at line 251 of file HexagonCopyToCombine.cpp.

References llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::modifiesRegister(), and llvm::MachineInstr::readsRegister().

static void removeKillInfo ( MachineInstr MI,
unsigned  RegNotKilled 
)
static
const HexagonInstrInfo bool ShouldCombineAggressively switch ( MI.  getOpcode())
static unsigned UseReg ( const MachineOperand MO)
static

Variable Documentation

return false

Definition at line 171 of file HexagonCopyToCombine.cpp.

cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable merging into combines"))
static
cl::opt<bool> IsConst64Disabled("disable-const64", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable generation of const64"))
static
cl::opt<unsigned> MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store", cl::Hidden, cl::init(4), cl::desc("Maximum distance between a tfr feeding a store we ""consider the store still to be newifiable"))
static

Definition at line 128 of file HexagonCopyToCombine.cpp.

Referenced by llvm::MachineBasicBlock::addLiveIn(), llvm::GCNHazardRecognizer::AdvanceCycle(), llvm::MachineBasicBlock::canFallThrough(), llvm::MachineBasicBlock::canSplitCriticalEdge(), CombineCVTAToLocal(), llvm::computeBlockSize(), llvm::createBURRListDAGScheduler(), llvm::createCopyConstrainDAGMutation(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createLoadClusterDAGMutation(), llvm::createSourceListDAGScheduler(), llvm::createStoreClusterDAGMutation(), llvm::Mips16FrameLowering::determineCalleeSaves(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::WebAssemblyFrameLowering::eliminateCallFramePseudoInstr(), llvm::AVRFrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), emitComments(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AVRFrameLowering::emitEpilogue(), llvm::Mips16FrameLowering::emitEpilogue(), llvm::MipsSEFrameLowering::emitEpilogue(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::WebAssemblyFrameLowering::emitEpilogue(), llvm::PPCFrameLowering::emitEpilogue(), llvm::AArch64TargetLowering::EmitF128CSEL(), emitIndirectDst(), emitIndirectSrc(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::AVRFrameLowering::emitPrologue(), llvm::Mips16FrameLowering::emitPrologue(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::AArch64FrameLowering::emitPrologue(), llvm::WebAssemblyFrameLowering::emitPrologue(), llvm::PPCFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitThumb1LoadConstPool(), emitThumb2LoadConstPool(), llvm::SparcTargetLowering::expandSelectCC(), FindCallSeqStart(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::getFuncletMembership(), llvm::ARMHazardRecognizer::getHazardType(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::SystemZTTIImpl::getIntImmCost(), llvm::SDNode::getOperationName(), llvm::PPCTargetLowering::getPrefLoopAlignment(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), llvm::R600RegisterInfo::getReservedRegs(), llvm::ARMTargetLowering::getSchedulingPreference(), getTargetIndexName(), llvm::ConvergingVLIWScheduler::initialize(), INITIALIZE_PASS(), llvm::AArch64TargetLowering::insertCopiesSplitCSR(), llvm::PPCTargetLowering::insertCopiesSplitCSR(), IsChainDependent(), llvm::HexagonInstrInfo::isComplex(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), llvm::SIRegisterInfo::materializeFrameBaseRegister(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), MIsNeedChainEdge(), llvm::MIPrinter::print(), llvm::MIPrinter::printTargetFlags(), propagateSwiftErrorVRegs(), llvm::TargetInstrInfo::reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), replaceFI(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::AVRFrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::rewriteAArch64FrameIndex(), llvm::InsertNOPLoad::runOnMachineFunction(), llvm::Legalizer::runOnMachineFunction(), llvm::FixFSMULD::runOnMachineFunction(), llvm::VirtRegMap::runOnMachineFunction(), llvm::ReplaceFMULS::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::FixAllFDIVSQRT::runOnMachineFunction(), llvm::AVRDynAllocaSR::runOnMachineFunction(), llvm::Mips16RegisterInfo::saveScavengerRegister(), llvm::ThumbRegisterInfo::saveScavengerRegister(), llvm::ARMInstructionSelector::select(), llvm::FunctionLoweringInfo::set(), setCallTargetReg(), llvm::AVRFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), llvm::SITargetLowering::splitKillBlock(), tryOptimizeLEAtoMOV(), UpdateOperandRegClass(), llvm::MachineBasicBlock::updateTerminator(), and writeSPToMemory().