LLVM  4.0.0
SparcFrameLowering.cpp
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1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Sparc implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcFrameLowering.h"
15 #include "SparcInstrInfo.h"
17 #include "SparcSubtarget.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/Function.h"
27 
28 using namespace llvm;
29 
30 static cl::opt<bool>
31 DisableLeafProc("disable-sparc-leaf-proc",
32  cl::init(false),
33  cl::desc("Disable Sparc leaf procedure optimization."),
34  cl::Hidden);
35 
37  : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
38  ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
39 
40 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
43  int NumBytes,
44  unsigned ADDrr,
45  unsigned ADDri) const {
46 
47  DebugLoc dl;
48  const SparcInstrInfo &TII =
49  *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
50 
51  if (NumBytes >= -4096 && NumBytes < 4096) {
52  BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53  .addReg(SP::O6).addImm(NumBytes);
54  return;
55  }
56 
57  // Emit this the hard way. This clobbers G1 which we always know is
58  // available here.
59  if (NumBytes >= 0) {
60  // Emit nonnegative numbers with sethi + or.
61  // sethi %hi(NumBytes), %g1
62  // or %g1, %lo(NumBytes), %g1
63  // add %sp, %g1, %sp
64  BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
65  .addImm(HI22(NumBytes));
66  BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67  .addReg(SP::G1).addImm(LO10(NumBytes));
68  BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69  .addReg(SP::O6).addReg(SP::G1);
70  return ;
71  }
72 
73  // Emit negative numbers with sethi + xor.
74  // sethi %hix(NumBytes), %g1
75  // xor %g1, %lox(NumBytes), %g1
76  // add %sp, %g1, %sp
77  BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
78  .addImm(HIX22(NumBytes));
79  BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80  .addReg(SP::G1).addImm(LOX10(NumBytes));
81  BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82  .addReg(SP::O6).addReg(SP::G1);
83 }
84 
86  MachineBasicBlock &MBB) const {
88 
89  assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
90  MachineFrameInfo &MFI = MF.getFrameInfo();
91  const SparcInstrInfo &TII =
92  *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
93  const SparcRegisterInfo &RegInfo =
94  *static_cast<const SparcRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
96  // Debug location must be unknown since the first debug location is used
97  // to determine the end of the prologue.
98  DebugLoc dl;
99  bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
100 
101  // FIXME: unfortunately, returning false from canRealignStack
102  // actually just causes needsStackRealignment to return false,
103  // rather than reporting an error, as would be sensible. This is
104  // poor, but fixing that bogosity is going to be a large project.
105  // For now, just see if it's lied, and report an error here.
106  if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment())
107  report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
108  "stack re-alignment, but LLVM couldn't handle it "
109  "(probably because it has a dynamic alloca).");
110 
111  // Get the number of bytes to allocate from the FrameInfo
112  int NumBytes = (int) MFI.getStackSize();
113 
114  unsigned SAVEri = SP::SAVEri;
115  unsigned SAVErr = SP::SAVErr;
116  if (FuncInfo->isLeafProc()) {
117  if (NumBytes == 0)
118  return;
119  SAVEri = SP::ADDri;
120  SAVErr = SP::ADDrr;
121  }
122 
123  // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
124  // (128 in v9) area in the user's stack, starting at %sp. Thus, the
125  // first part of the stack that can actually be used is located at
126  // %sp + 92.
127  //
128  // We therefore need to add that offset to the total stack size
129  // after all the stack objects are placed by
130  // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
131  // aligned *after* the extra size is added, we need to disable
132  // calculateFrameObjectOffsets's built-in stack alignment, by having
133  // targetHandlesStackFrameRounding return true.
134 
135 
136  // Add the extra call frame stack size, if needed. (This is the same
137  // code as in PrologEpilogInserter, but also gets disabled by
138  // targetHandlesStackFrameRounding)
139  if (MFI.adjustsStack() && hasReservedCallFrame(MF))
140  NumBytes += MFI.getMaxCallFrameSize();
141 
142  // Adds the SPARC subtarget-specific spill area to the stack
143  // size. Also ensures target-required alignment.
144  NumBytes = MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes);
145 
146  // Finally, ensure that the size is sufficiently aligned for the
147  // data on the stack.
148  if (MFI.getMaxAlignment() > 0) {
149  NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());
150  }
151 
152  // Update stack size with corrected value.
153  MFI.setStackSize(NumBytes);
154 
155  emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
156 
157  unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
158 
159  // Emit ".cfi_def_cfa_register 30".
160  unsigned CFIIndex =
162  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
163  .addCFIIndex(CFIIndex);
164 
165  // Emit ".cfi_window_save".
166  CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
167  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
168  .addCFIIndex(CFIIndex);
169 
170  unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
171  unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
172  // Emit ".cfi_register 15, 31".
173  CFIIndex = MF.addFrameInst(
174  MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
175  BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
176  .addCFIIndex(CFIIndex);
177 
178  if (NeedsStackRealignment) {
179  // andn %o6, MaxAlign-1, %o6
180  int MaxAlign = MFI.getMaxAlignment();
181  BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1);
182  }
183 }
184 
188  if (!hasReservedCallFrame(MF)) {
189  MachineInstr &MI = *I;
190  int Size = MI.getOperand(0).getImm();
191  if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
192  Size = -Size;
193 
194  if (Size)
195  emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
196  }
197  return MBB.erase(I);
198 }
199 
200 
202  MachineBasicBlock &MBB) const {
205  const SparcInstrInfo &TII =
206  *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
207  DebugLoc dl = MBBI->getDebugLoc();
208  assert(MBBI->getOpcode() == SP::RETL &&
209  "Can only put epilog before 'retl' instruction!");
210  if (!FuncInfo->isLeafProc()) {
211  BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
212  .addReg(SP::G0);
213  return;
214  }
215  MachineFrameInfo &MFI = MF.getFrameInfo();
216 
217  int NumBytes = (int) MFI.getStackSize();
218  if (NumBytes == 0)
219  return;
220 
221  emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
222 }
223 
225  // Reserve call frame if there are no variable sized objects on the stack.
226  return !MF.getFrameInfo().hasVarSizedObjects();
227 }
228 
229 // hasFP - Return true if the specified function should have a dedicated frame
230 // pointer register. This is true if the function has variable sized allocas or
231 // if frame pointer elimination is disabled.
233  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
234 
235  const MachineFrameInfo &MFI = MF.getFrameInfo();
236  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
237  RegInfo->needsStackRealignment(MF) ||
238  MFI.hasVarSizedObjects() ||
239  MFI.isFrameAddressTaken();
240 }
241 
242 
244  unsigned &FrameReg) const {
245  const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
246  const MachineFrameInfo &MFI = MF.getFrameInfo();
247  const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
249  bool isFixed = MFI.isFixedObjectIndex(FI);
250 
251  // Addressable stack objects are accessed using neg. offsets from
252  // %fp, or positive offsets from %sp.
253  bool UseFP;
254 
255  // Sparc uses FP-based references in general, even when "hasFP" is
256  // false. That function is rather a misnomer, because %fp is
257  // actually always available, unless isLeafProc.
258  if (FuncInfo->isLeafProc()) {
259  // If there's a leaf proc, all offsets need to be %sp-based,
260  // because we haven't caused %fp to actually point to our frame.
261  UseFP = false;
262  } else if (isFixed) {
263  // Otherwise, argument access should always use %fp.
264  UseFP = true;
265  } else if (RegInfo->needsStackRealignment(MF)) {
266  // If there is dynamic stack realignment, all local object
267  // references need to be via %sp, to take account of the
268  // re-alignment.
269  UseFP = false;
270  } else {
271  // Finally, default to using %fp.
272  UseFP = true;
273  }
274 
275  int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) +
276  Subtarget.getStackPointerBias();
277 
278  if (UseFP) {
279  FrameReg = RegInfo->getFrameRegister(MF);
280  return FrameOffset;
281  } else {
282  FrameReg = SP::O6; // %sp
283  return FrameOffset + MF.getFrameInfo().getStackSize();
284  }
285 }
286 
288 {
289 
290  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
291  if (!MRI->reg_nodbg_empty(reg))
292  return false;
293 
294  for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
295  if (!MRI->reg_nodbg_empty(reg))
296  return false;
297 
298  return true;
299 }
300 
301 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
302 {
303 
305  MachineFrameInfo &MFI = MF.getFrameInfo();
306 
307  return !(MFI.hasCalls() // has calls
308  || !MRI.reg_nodbg_empty(SP::L0) // Too many registers needed
309  || !MRI.reg_nodbg_empty(SP::O6) // %SP is used
310  || hasFP(MF)); // need %FP
311 }
312 
313 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
314  MachineRegisterInfo &MRI = MF.getRegInfo();
315  // Remap %i[0-7] to %o[0-7].
316  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
317  if (MRI.reg_nodbg_empty(reg))
318  continue;
319 
320  unsigned mapped_reg = reg - SP::I0 + SP::O0;
321  assert(MRI.reg_nodbg_empty(mapped_reg));
322 
323  // Replace I register with O register.
324  MRI.replaceRegWith(reg, mapped_reg);
325 
326  // Also replace register pair super-registers.
327  if ((reg - SP::I0) % 2 == 0) {
328  unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
329  unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
330  MRI.replaceRegWith(preg, mapped_preg);
331  }
332  }
333 
334  // Rewrite MBB's Live-ins.
335  for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
336  MBB != E; ++MBB) {
337  for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
338  if (!MBB->isLiveIn(reg))
339  continue;
340  MBB->removeLiveIn(reg);
341  MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
342  }
343  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
344  if (!MBB->isLiveIn(reg))
345  continue;
346  MBB->removeLiveIn(reg);
347  MBB->addLiveIn(reg - SP::I0 + SP::O0);
348  }
349  }
350 
352 #ifdef EXPENSIVE_CHECKS
353  MF.verify(0, "After LeafProc Remapping");
354 #endif
355 }
356 
358  BitVector &SavedRegs,
359  RegScavenger *RS) const {
361  if (!DisableLeafProc && isLeafProc(MF)) {
363  MFI->setLeafProc(true);
364 
365  remapRegsForLeafProc(MF);
366  }
367 
368 }
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
int getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
A debug info location.
Definition: DebugLoc.h:34
uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the next integer (mod 2**64) that is greater than or equal to Value and is a multiple of Alig...
Definition: MathExtras.h:664
static unsigned LO10(int64_t imm)
Definition: Sparc.h:154
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
const HexagonInstrInfo * TII
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineBasicBlock & front() const
static unsigned HIX22(int64_t imm)
Definition: Sparc.h:158
MachineBasicBlock * MBB
static unsigned HI22(int64_t imm)
Definition: Sparc.h:150
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:395
void addLiveIn(MCPhysReg PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned const MachineRegisterInfo * MRI
static unsigned LOX10(int64_t imm)
Definition: Sparc.h:162
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:376
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static MCCFIInstruction createWindowSave(MCSymbol *L)
.cfi_window_save SPARC register window is saved.
Definition: MCDwarf.h:417
static bool is64Bit(const char *name)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
static cl::opt< bool > DisableLeafProc("disable-sparc-leaf-proc", cl::init(false), cl::desc("Disable Sparc leaf procedure optimization."), cl::Hidden)
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:150
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const SparcRegisterInfo * getRegisterInfo() const override
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
bool hasCalls() const
Return true if the current function has any function calls.
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
Iterator for intrusive lists based on ilist_node.
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Information about stack frame layout on the target.
void replaceRegWith(unsigned FromReg, unsigned ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
SparcFrameLowering(const SparcSubtarget &ST)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
int64_t getStackPointerBias() const
The 64-bit ABI uses biased stack and frame pointers, so the stack frame of the current function is th...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool reg_nodbg_empty(unsigned RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2)
.cfi_register Previous value of Register1 is saved in register Register2.
Definition: MCDwarf.h:411