LLVM  4.0.0
PPCInstrInfo.cpp
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1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPCInstrInfo.h"
16 #include "PPC.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/Debug.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "ppc-instr-info"
44 
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
48 
49 static cl::
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51  cl::desc("Disable analysis for CTR loops"));
52 
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
55 
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
58 cl::Hidden);
59 
60 static cl::opt<bool>
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62  cl::desc("Use the old (incorrect) instruction latency calculation"));
63 
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
66 
68  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69  Subtarget(STI), RI(STI.getTargetMachine()) {}
70 
71 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72 /// this target when scheduling the DAG.
75  const ScheduleDAG *DAG) const {
76  unsigned Directive =
77  static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79  Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80  const InstrItineraryData *II =
81  static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82  return new ScoreboardHazardRecognizer(II, DAG);
83  }
84 
86 }
87 
88 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89 /// to use for this target when scheduling the DAG.
92  const ScheduleDAG *DAG) const {
93  unsigned Directive =
94  DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
95 
96  // FIXME: Leaving this as-is until we have POWER9 scheduling info
97  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
98  return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
99 
100  // Most subtargets use a PPC970 recognizer.
101  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
102  Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
103  assert(DAG->TII && "No InstrInfo?");
104 
105  return new PPCHazardRecognizer970(*DAG);
106  }
107 
108  return new ScoreboardHazardRecognizer(II, DAG);
109 }
110 
112  const MachineInstr &MI,
113  unsigned *PredCost) const {
114  if (!ItinData || UseOldLatencyCalc)
115  return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
116 
117  // The default implementation of getInstrLatency calls getStageLatency, but
118  // getStageLatency does not do the right thing for us. While we have
119  // itinerary, most cores are fully pipelined, and so the itineraries only
120  // express the first part of the pipeline, not every stage. Instead, we need
121  // to use the listed output operand cycle number (using operand 0 here, which
122  // is an output).
123 
124  unsigned Latency = 1;
125  unsigned DefClass = MI.getDesc().getSchedClass();
126  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
127  const MachineOperand &MO = MI.getOperand(i);
128  if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
129  continue;
130 
131  int Cycle = ItinData->getOperandCycle(DefClass, i);
132  if (Cycle < 0)
133  continue;
134 
135  Latency = std::max(Latency, (unsigned) Cycle);
136  }
137 
138  return Latency;
139 }
140 
142  const MachineInstr &DefMI, unsigned DefIdx,
143  const MachineInstr &UseMI,
144  unsigned UseIdx) const {
145  int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
146  UseMI, UseIdx);
147 
148  if (!DefMI.getParent())
149  return Latency;
150 
151  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
152  unsigned Reg = DefMO.getReg();
153 
154  bool IsRegCR;
156  const MachineRegisterInfo *MRI =
157  &DefMI.getParent()->getParent()->getRegInfo();
158  IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
159  MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
160  } else {
161  IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
162  PPC::CRBITRCRegClass.contains(Reg);
163  }
164 
165  if (UseMI.isBranch() && IsRegCR) {
166  if (Latency < 0)
167  Latency = getInstrLatency(ItinData, DefMI);
168 
169  // On some cores, there is an additional delay between writing to a condition
170  // register, and using it from a branch.
171  unsigned Directive = Subtarget.getDarwinDirective();
172  switch (Directive) {
173  default: break;
174  case PPC::DIR_7400:
175  case PPC::DIR_750:
176  case PPC::DIR_970:
177  case PPC::DIR_E5500:
178  case PPC::DIR_PWR4:
179  case PPC::DIR_PWR5:
180  case PPC::DIR_PWR5X:
181  case PPC::DIR_PWR6:
182  case PPC::DIR_PWR6X:
183  case PPC::DIR_PWR7:
184  case PPC::DIR_PWR8:
185  // FIXME: Is this needed for POWER9?
186  Latency += 2;
187  break;
188  }
189  }
190 
191  return Latency;
192 }
193 
194 // This function does not list all associative and commutative operations, but
195 // only those worth feeding through the machine combiner in an attempt to
196 // reduce the critical path. Mostly, this means floating-point operations,
197 // because they have high latencies (compared to other operations, such and
198 // and/or, which are also associative and commutative, but have low latencies).
200  switch (Inst.getOpcode()) {
201  // FP Add:
202  case PPC::FADD:
203  case PPC::FADDS:
204  // FP Multiply:
205  case PPC::FMUL:
206  case PPC::FMULS:
207  // Altivec Add:
208  case PPC::VADDFP:
209  // VSX Add:
210  case PPC::XSADDDP:
211  case PPC::XVADDDP:
212  case PPC::XVADDSP:
213  case PPC::XSADDSP:
214  // VSX Multiply:
215  case PPC::XSMULDP:
216  case PPC::XVMULDP:
217  case PPC::XVMULSP:
218  case PPC::XSMULSP:
219  // QPX Add:
220  case PPC::QVFADD:
221  case PPC::QVFADDS:
222  case PPC::QVFADDSs:
223  // QPX Multiply:
224  case PPC::QVFMUL:
225  case PPC::QVFMULS:
226  case PPC::QVFMULSs:
227  return true;
228  default:
229  return false;
230  }
231 }
232 
234  MachineInstr &Root,
235  SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
236  // Using the machine combiner in this way is potentially expensive, so
237  // restrict to when aggressive optimizations are desired.
239  return false;
240 
241  // FP reassociation is only legal when we don't need strict IEEE semantics.
243  return false;
244 
245  return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
246 }
247 
248 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
250  unsigned &SrcReg, unsigned &DstReg,
251  unsigned &SubIdx) const {
252  switch (MI.getOpcode()) {
253  default: return false;
254  case PPC::EXTSW:
255  case PPC::EXTSW_32_64:
256  SrcReg = MI.getOperand(1).getReg();
257  DstReg = MI.getOperand(0).getReg();
258  SubIdx = PPC::sub_32;
259  return true;
260  }
261 }
262 
264  int &FrameIndex) const {
265  // Note: This list must be kept consistent with LoadRegFromStackSlot.
266  switch (MI.getOpcode()) {
267  default: break;
268  case PPC::LD:
269  case PPC::LWZ:
270  case PPC::LFS:
271  case PPC::LFD:
272  case PPC::RESTORE_CR:
273  case PPC::RESTORE_CRBIT:
274  case PPC::LVX:
275  case PPC::LXVD2X:
276  case PPC::LXVX:
277  case PPC::QVLFDX:
278  case PPC::QVLFSXs:
279  case PPC::QVLFDXb:
280  case PPC::RESTORE_VRSAVE:
281  // Check for the operands added by addFrameReference (the immediate is the
282  // offset which defaults to 0).
283  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
284  MI.getOperand(2).isFI()) {
285  FrameIndex = MI.getOperand(2).getIndex();
286  return MI.getOperand(0).getReg();
287  }
288  break;
289  }
290  return 0;
291 }
292 
294  int &FrameIndex) const {
295  // Note: This list must be kept consistent with StoreRegToStackSlot.
296  switch (MI.getOpcode()) {
297  default: break;
298  case PPC::STD:
299  case PPC::STW:
300  case PPC::STFS:
301  case PPC::STFD:
302  case PPC::SPILL_CR:
303  case PPC::SPILL_CRBIT:
304  case PPC::STVX:
305  case PPC::STXVD2X:
306  case PPC::STXVX:
307  case PPC::QVSTFDX:
308  case PPC::QVSTFSXs:
309  case PPC::QVSTFDXb:
310  case PPC::SPILL_VRSAVE:
311  // Check for the operands added by addFrameReference (the immediate is the
312  // offset which defaults to 0).
313  if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
314  MI.getOperand(2).isFI()) {
315  FrameIndex = MI.getOperand(2).getIndex();
316  return MI.getOperand(0).getReg();
317  }
318  break;
319  }
320  return 0;
321 }
322 
324  unsigned OpIdx1,
325  unsigned OpIdx2) const {
326  MachineFunction &MF = *MI.getParent()->getParent();
327 
328  // Normal instructions can be commuted the obvious way.
329  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
330  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
331  // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
332  // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
333  // changing the relative order of the mask operands might change what happens
334  // to the high-bits of the mask (and, thus, the result).
335 
336  // Cannot commute if it has a non-zero rotate count.
337  if (MI.getOperand(3).getImm() != 0)
338  return nullptr;
339 
340  // If we have a zero rotate count, we have:
341  // M = mask(MB,ME)
342  // Op0 = (Op1 & ~M) | (Op2 & M)
343  // Change this to:
344  // M = mask((ME+1)&31, (MB-1)&31)
345  // Op0 = (Op2 & ~M) | (Op1 & M)
346 
347  // Swap op1/op2
348  assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
349  "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
350  unsigned Reg0 = MI.getOperand(0).getReg();
351  unsigned Reg1 = MI.getOperand(1).getReg();
352  unsigned Reg2 = MI.getOperand(2).getReg();
353  unsigned SubReg1 = MI.getOperand(1).getSubReg();
354  unsigned SubReg2 = MI.getOperand(2).getSubReg();
355  bool Reg1IsKill = MI.getOperand(1).isKill();
356  bool Reg2IsKill = MI.getOperand(2).isKill();
357  bool ChangeReg0 = false;
358  // If machine instrs are no longer in two-address forms, update
359  // destination register as well.
360  if (Reg0 == Reg1) {
361  // Must be two address instruction!
363  "Expecting a two-address instruction!");
364  assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
365  Reg2IsKill = false;
366  ChangeReg0 = true;
367  }
368 
369  // Masks.
370  unsigned MB = MI.getOperand(4).getImm();
371  unsigned ME = MI.getOperand(5).getImm();
372 
373  // We can't commute a trivial mask (there is no way to represent an all-zero
374  // mask).
375  if (MB == 0 && ME == 31)
376  return nullptr;
377 
378  if (NewMI) {
379  // Create a new instruction.
380  unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
381  bool Reg0IsDead = MI.getOperand(0).isDead();
382  return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
383  .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
384  .addReg(Reg2, getKillRegState(Reg2IsKill))
385  .addReg(Reg1, getKillRegState(Reg1IsKill))
386  .addImm((ME + 1) & 31)
387  .addImm((MB - 1) & 31);
388  }
389 
390  if (ChangeReg0) {
391  MI.getOperand(0).setReg(Reg2);
392  MI.getOperand(0).setSubReg(SubReg2);
393  }
394  MI.getOperand(2).setReg(Reg1);
395  MI.getOperand(1).setReg(Reg2);
396  MI.getOperand(2).setSubReg(SubReg1);
397  MI.getOperand(1).setSubReg(SubReg2);
398  MI.getOperand(2).setIsKill(Reg1IsKill);
399  MI.getOperand(1).setIsKill(Reg2IsKill);
400 
401  // Swap the mask around.
402  MI.getOperand(4).setImm((ME + 1) & 31);
403  MI.getOperand(5).setImm((MB - 1) & 31);
404  return &MI;
405 }
406 
408  unsigned &SrcOpIdx2) const {
409  // For VSX A-Type FMA instructions, it is the first two operands that can be
410  // commuted, however, because the non-encoded tied input operand is listed
411  // first, the operands to swap are actually the second and third.
412 
413  int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
414  if (AltOpc == -1)
415  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
416 
417  // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
418  // and SrcOpIdx2.
419  return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
420 }
421 
424  // This function is used for scheduling, and the nop wanted here is the type
425  // that terminates dispatch groups on the POWER cores.
426  unsigned Directive = Subtarget.getDarwinDirective();
427  unsigned Opcode;
428  switch (Directive) {
429  default: Opcode = PPC::NOP; break;
430  case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
431  case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
432  case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
433  // FIXME: Update when POWER9 scheduling model is ready.
434  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
435  }
436 
437  DebugLoc DL;
438  BuildMI(MBB, MI, DL, get(Opcode));
439 }
440 
441 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
443  NopInst.setOpcode(PPC::NOP);
444 }
445 
446 // Branch analysis.
447 // Note: If the condition register is set to CTR or CTR8 then this is a
448 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
450  MachineBasicBlock *&TBB,
451  MachineBasicBlock *&FBB,
453  bool AllowModify) const {
454  bool isPPC64 = Subtarget.isPPC64();
455 
456  // If the block has no terminators, it just falls into the block after it.
458  if (I == MBB.end())
459  return false;
460 
461  if (!isUnpredicatedTerminator(*I))
462  return false;
463 
464  // Get the last instruction in the block.
465  MachineInstr &LastInst = *I;
466 
467  // If there is only one terminator instruction, process it.
468  if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
469  if (LastInst.getOpcode() == PPC::B) {
470  if (!LastInst.getOperand(0).isMBB())
471  return true;
472  TBB = LastInst.getOperand(0).getMBB();
473  return false;
474  } else if (LastInst.getOpcode() == PPC::BCC) {
475  if (!LastInst.getOperand(2).isMBB())
476  return true;
477  // Block ends with fall-through condbranch.
478  TBB = LastInst.getOperand(2).getMBB();
479  Cond.push_back(LastInst.getOperand(0));
480  Cond.push_back(LastInst.getOperand(1));
481  return false;
482  } else if (LastInst.getOpcode() == PPC::BC) {
483  if (!LastInst.getOperand(1).isMBB())
484  return true;
485  // Block ends with fall-through condbranch.
486  TBB = LastInst.getOperand(1).getMBB();
488  Cond.push_back(LastInst.getOperand(0));
489  return false;
490  } else if (LastInst.getOpcode() == PPC::BCn) {
491  if (!LastInst.getOperand(1).isMBB())
492  return true;
493  // Block ends with fall-through condbranch.
494  TBB = LastInst.getOperand(1).getMBB();
496  Cond.push_back(LastInst.getOperand(0));
497  return false;
498  } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
499  LastInst.getOpcode() == PPC::BDNZ) {
500  if (!LastInst.getOperand(0).isMBB())
501  return true;
502  if (DisableCTRLoopAnal)
503  return true;
504  TBB = LastInst.getOperand(0).getMBB();
506  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
507  true));
508  return false;
509  } else if (LastInst.getOpcode() == PPC::BDZ8 ||
510  LastInst.getOpcode() == PPC::BDZ) {
511  if (!LastInst.getOperand(0).isMBB())
512  return true;
513  if (DisableCTRLoopAnal)
514  return true;
515  TBB = LastInst.getOperand(0).getMBB();
517  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
518  true));
519  return false;
520  }
521 
522  // Otherwise, don't know what this is.
523  return true;
524  }
525 
526  // Get the instruction before it if it's a terminator.
527  MachineInstr &SecondLastInst = *I;
528 
529  // If there are three terminators, we don't know what sort of block this is.
530  if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
531  return true;
532 
533  // If the block ends with PPC::B and PPC:BCC, handle it.
534  if (SecondLastInst.getOpcode() == PPC::BCC &&
535  LastInst.getOpcode() == PPC::B) {
536  if (!SecondLastInst.getOperand(2).isMBB() ||
537  !LastInst.getOperand(0).isMBB())
538  return true;
539  TBB = SecondLastInst.getOperand(2).getMBB();
540  Cond.push_back(SecondLastInst.getOperand(0));
541  Cond.push_back(SecondLastInst.getOperand(1));
542  FBB = LastInst.getOperand(0).getMBB();
543  return false;
544  } else if (SecondLastInst.getOpcode() == PPC::BC &&
545  LastInst.getOpcode() == PPC::B) {
546  if (!SecondLastInst.getOperand(1).isMBB() ||
547  !LastInst.getOperand(0).isMBB())
548  return true;
549  TBB = SecondLastInst.getOperand(1).getMBB();
551  Cond.push_back(SecondLastInst.getOperand(0));
552  FBB = LastInst.getOperand(0).getMBB();
553  return false;
554  } else if (SecondLastInst.getOpcode() == PPC::BCn &&
555  LastInst.getOpcode() == PPC::B) {
556  if (!SecondLastInst.getOperand(1).isMBB() ||
557  !LastInst.getOperand(0).isMBB())
558  return true;
559  TBB = SecondLastInst.getOperand(1).getMBB();
561  Cond.push_back(SecondLastInst.getOperand(0));
562  FBB = LastInst.getOperand(0).getMBB();
563  return false;
564  } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
565  SecondLastInst.getOpcode() == PPC::BDNZ) &&
566  LastInst.getOpcode() == PPC::B) {
567  if (!SecondLastInst.getOperand(0).isMBB() ||
568  !LastInst.getOperand(0).isMBB())
569  return true;
570  if (DisableCTRLoopAnal)
571  return true;
572  TBB = SecondLastInst.getOperand(0).getMBB();
574  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
575  true));
576  FBB = LastInst.getOperand(0).getMBB();
577  return false;
578  } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
579  SecondLastInst.getOpcode() == PPC::BDZ) &&
580  LastInst.getOpcode() == PPC::B) {
581  if (!SecondLastInst.getOperand(0).isMBB() ||
582  !LastInst.getOperand(0).isMBB())
583  return true;
584  if (DisableCTRLoopAnal)
585  return true;
586  TBB = SecondLastInst.getOperand(0).getMBB();
588  Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
589  true));
590  FBB = LastInst.getOperand(0).getMBB();
591  return false;
592  }
593 
594  // If the block ends with two PPC:Bs, handle it. The second one is not
595  // executed, so remove it.
596  if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
597  if (!SecondLastInst.getOperand(0).isMBB())
598  return true;
599  TBB = SecondLastInst.getOperand(0).getMBB();
600  I = LastInst;
601  if (AllowModify)
602  I->eraseFromParent();
603  return false;
604  }
605 
606  // Otherwise, can't handle this.
607  return true;
608 }
609 
611  int *BytesRemoved) const {
612  assert(!BytesRemoved && "code size not handled");
613 
615  if (I == MBB.end())
616  return 0;
617 
618  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
619  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
620  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
621  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
622  return 0;
623 
624  // Remove the branch.
625  I->eraseFromParent();
626 
627  I = MBB.end();
628 
629  if (I == MBB.begin()) return 1;
630  --I;
631  if (I->getOpcode() != PPC::BCC &&
632  I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
633  I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
634  I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
635  return 1;
636 
637  // Remove the branch.
638  I->eraseFromParent();
639  return 2;
640 }
641 
643  MachineBasicBlock *TBB,
644  MachineBasicBlock *FBB,
646  const DebugLoc &DL,
647  int *BytesAdded) const {
648  // Shouldn't be a fall through.
649  assert(TBB && "insertBranch must not be told to insert a fallthrough");
650  assert((Cond.size() == 2 || Cond.size() == 0) &&
651  "PPC branch conditions have two components!");
652  assert(!BytesAdded && "code size not handled");
653 
654  bool isPPC64 = Subtarget.isPPC64();
655 
656  // One-way branch.
657  if (!FBB) {
658  if (Cond.empty()) // Unconditional branch
659  BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
660  else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
661  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
662  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
663  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
664  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
665  BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
666  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
667  BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
668  else // Conditional branch
669  BuildMI(&MBB, DL, get(PPC::BCC))
670  .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
671  return 1;
672  }
673 
674  // Two-way Conditional Branch.
675  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
676  BuildMI(&MBB, DL, get(Cond[0].getImm() ?
677  (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
678  (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
679  else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
680  BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
681  else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
682  BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
683  else
684  BuildMI(&MBB, DL, get(PPC::BCC))
685  .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
686  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
687  return 2;
688 }
689 
690 // Select analysis.
693  unsigned TrueReg, unsigned FalseReg,
694  int &CondCycles, int &TrueCycles, int &FalseCycles) const {
695  if (!Subtarget.hasISEL())
696  return false;
697 
698  if (Cond.size() != 2)
699  return false;
700 
701  // If this is really a bdnz-like condition, then it cannot be turned into a
702  // select.
703  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
704  return false;
705 
706  // Check register classes.
707  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
708  const TargetRegisterClass *RC =
709  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
710  if (!RC)
711  return false;
712 
713  // isel is for regular integer GPRs only.
714  if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
715  !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
716  !PPC::G8RCRegClass.hasSubClassEq(RC) &&
717  !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
718  return false;
719 
720  // FIXME: These numbers are for the A2, how well they work for other cores is
721  // an open question. On the A2, the isel instruction has a 2-cycle latency
722  // but single-cycle throughput. These numbers are used in combination with
723  // the MispredictPenalty setting from the active SchedMachineModel.
724  CondCycles = 1;
725  TrueCycles = 1;
726  FalseCycles = 1;
727 
728  return true;
729 }
730 
733  const DebugLoc &dl, unsigned DestReg,
734  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
735  unsigned FalseReg) const {
736  assert(Cond.size() == 2 &&
737  "PPC branch conditions have two components!");
738 
739  assert(Subtarget.hasISEL() &&
740  "Cannot insert select on target without ISEL support");
741 
742  // Get the register classes.
744  const TargetRegisterClass *RC =
745  RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
746  assert(RC && "TrueReg and FalseReg must have overlapping register classes");
747 
748  bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
749  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
750  assert((Is64Bit ||
751  PPC::GPRCRegClass.hasSubClassEq(RC) ||
752  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
753  "isel is for regular integer GPRs only");
754 
755  unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
756  auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
757 
758  unsigned SubIdx = 0;
759  bool SwapOps = false;
760  switch (SelectPred) {
761  case PPC::PRED_EQ:
762  case PPC::PRED_EQ_MINUS:
763  case PPC::PRED_EQ_PLUS:
764  SubIdx = PPC::sub_eq; SwapOps = false; break;
765  case PPC::PRED_NE:
766  case PPC::PRED_NE_MINUS:
767  case PPC::PRED_NE_PLUS:
768  SubIdx = PPC::sub_eq; SwapOps = true; break;
769  case PPC::PRED_LT:
770  case PPC::PRED_LT_MINUS:
771  case PPC::PRED_LT_PLUS:
772  SubIdx = PPC::sub_lt; SwapOps = false; break;
773  case PPC::PRED_GE:
774  case PPC::PRED_GE_MINUS:
775  case PPC::PRED_GE_PLUS:
776  SubIdx = PPC::sub_lt; SwapOps = true; break;
777  case PPC::PRED_GT:
778  case PPC::PRED_GT_MINUS:
779  case PPC::PRED_GT_PLUS:
780  SubIdx = PPC::sub_gt; SwapOps = false; break;
781  case PPC::PRED_LE:
782  case PPC::PRED_LE_MINUS:
783  case PPC::PRED_LE_PLUS:
784  SubIdx = PPC::sub_gt; SwapOps = true; break;
785  case PPC::PRED_UN:
786  case PPC::PRED_UN_MINUS:
787  case PPC::PRED_UN_PLUS:
788  SubIdx = PPC::sub_un; SwapOps = false; break;
789  case PPC::PRED_NU:
790  case PPC::PRED_NU_MINUS:
791  case PPC::PRED_NU_PLUS:
792  SubIdx = PPC::sub_un; SwapOps = true; break;
793  case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
794  case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
795  }
796 
797  unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
798  SecondReg = SwapOps ? TrueReg : FalseReg;
799 
800  // The first input register of isel cannot be r0. If it is a member
801  // of a register class that can be r0, then copy it first (the
802  // register allocator should eliminate the copy).
803  if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
804  MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
805  const TargetRegisterClass *FirstRC =
806  MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
807  &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
808  unsigned OldFirstReg = FirstReg;
809  FirstReg = MRI.createVirtualRegister(FirstRC);
810  BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
811  .addReg(OldFirstReg);
812  }
813 
814  BuildMI(MBB, MI, dl, get(OpCode), DestReg)
815  .addReg(FirstReg).addReg(SecondReg)
816  .addReg(Cond[1].getReg(), 0, SubIdx);
817 }
818 
819 static unsigned getCRBitValue(unsigned CRBit) {
820  unsigned Ret = 4;
821  if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
822  CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
823  CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
824  CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
825  Ret = 3;
826  if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
827  CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
828  CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
829  CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
830  Ret = 2;
831  if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
832  CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
833  CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
834  CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
835  Ret = 1;
836  if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
837  CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
838  CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
839  CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
840  Ret = 0;
841 
842  assert(Ret != 4 && "Invalid CR bit register");
843  return Ret;
844 }
845 
848  const DebugLoc &DL, unsigned DestReg,
849  unsigned SrcReg, bool KillSrc) const {
850  // We can end up with self copies and similar things as a result of VSX copy
851  // legalization. Promote them here.
852  const TargetRegisterInfo *TRI = &getRegisterInfo();
853  if (PPC::F8RCRegClass.contains(DestReg) &&
854  PPC::VSRCRegClass.contains(SrcReg)) {
855  unsigned SuperReg =
856  TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
857 
858  if (VSXSelfCopyCrash && SrcReg == SuperReg)
859  llvm_unreachable("nop VSX copy");
860 
861  DestReg = SuperReg;
862  } else if (PPC::F8RCRegClass.contains(SrcReg) &&
863  PPC::VSRCRegClass.contains(DestReg)) {
864  unsigned SuperReg =
865  TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
866 
867  if (VSXSelfCopyCrash && DestReg == SuperReg)
868  llvm_unreachable("nop VSX copy");
869 
870  SrcReg = SuperReg;
871  }
872 
873  // Different class register copy
874  if (PPC::CRBITRCRegClass.contains(SrcReg) &&
875  PPC::GPRCRegClass.contains(DestReg)) {
876  unsigned CRReg = getCRFromCRBit(SrcReg);
877  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
878  getKillRegState(KillSrc);
879  // Rotate the CR bit in the CR fields to be the least significant bit and
880  // then mask with 0x1 (MB = ME = 31).
881  BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
882  .addReg(DestReg, RegState::Kill)
883  .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
884  .addImm(31)
885  .addImm(31);
886  return;
887  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
888  PPC::G8RCRegClass.contains(DestReg)) {
889  BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
890  getKillRegState(KillSrc);
891  return;
892  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
893  PPC::GPRCRegClass.contains(DestReg)) {
894  BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
895  getKillRegState(KillSrc);
896  return;
897  }
898 
899  unsigned Opc;
900  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
901  Opc = PPC::OR;
902  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
903  Opc = PPC::OR8;
904  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
905  Opc = PPC::FMR;
906  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
907  Opc = PPC::MCRF;
908  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
909  Opc = PPC::VOR;
910  else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
911  // There are two different ways this can be done:
912  // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
913  // issue in VSU pipeline 0.
914  // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
915  // can go to either pipeline.
916  // We'll always use xxlor here, because in practically all cases where
917  // copies are generated, they are close enough to some use that the
918  // lower-latency form is preferable.
919  Opc = PPC::XXLOR;
920  else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
921  PPC::VSSRCRegClass.contains(DestReg, SrcReg))
922  Opc = PPC::XXLORf;
923  else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
924  Opc = PPC::QVFMR;
925  else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
926  Opc = PPC::QVFMRs;
927  else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
928  Opc = PPC::QVFMRb;
929  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
930  Opc = PPC::CROR;
931  else
932  llvm_unreachable("Impossible reg-to-reg copy");
933 
934  const MCInstrDesc &MCID = get(Opc);
935  if (MCID.getNumOperands() == 3)
936  BuildMI(MBB, I, DL, MCID, DestReg)
937  .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
938  else
939  BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
940 }
941 
942 // This function returns true if a CR spill is necessary and false otherwise.
943 bool
944 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
945  unsigned SrcReg, bool isKill,
946  int FrameIdx,
947  const TargetRegisterClass *RC,
949  bool &NonRI, bool &SpillsVRS) const{
950  // Note: If additional store instructions are added here,
951  // update isStoreToStackSlot.
952 
953  DebugLoc DL;
954  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
955  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
956  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
957  .addReg(SrcReg,
958  getKillRegState(isKill)),
959  FrameIdx));
960  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
961  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
962  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
963  .addReg(SrcReg,
964  getKillRegState(isKill)),
965  FrameIdx));
966  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
967  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
968  .addReg(SrcReg,
969  getKillRegState(isKill)),
970  FrameIdx));
971  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
972  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
973  .addReg(SrcReg,
974  getKillRegState(isKill)),
975  FrameIdx));
976  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
977  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
978  .addReg(SrcReg,
979  getKillRegState(isKill)),
980  FrameIdx));
981  return true;
982  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
983  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
984  .addReg(SrcReg,
985  getKillRegState(isKill)),
986  FrameIdx));
987  return true;
988  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
989  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
990  .addReg(SrcReg,
991  getKillRegState(isKill)),
992  FrameIdx));
993  NonRI = true;
994  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
995  unsigned Op = Subtarget.hasP9Vector() ? PPC::STXVX : PPC::STXVD2X;
996  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op))
997  .addReg(SrcReg,
998  getKillRegState(isKill)),
999  FrameIdx));
1000  NonRI = true;
1001  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1002  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf64 : PPC::STXSDX;
1003  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1004  .addReg(SrcReg,
1005  getKillRegState(isKill)),
1006  FrameIdx));
1007  NonRI = true;
1008  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1009  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFSTOREf32 : PPC::STXSSPX;
1010  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc))
1011  .addReg(SrcReg,
1012  getKillRegState(isKill)),
1013  FrameIdx));
1014  NonRI = true;
1015  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1016  assert(Subtarget.isDarwin() &&
1017  "VRSAVE only needs spill/restore on Darwin");
1018  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1019  .addReg(SrcReg,
1020  getKillRegState(isKill)),
1021  FrameIdx));
1022  SpillsVRS = true;
1023  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1024  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1025  .addReg(SrcReg,
1026  getKillRegState(isKill)),
1027  FrameIdx));
1028  NonRI = true;
1029  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1030  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1031  .addReg(SrcReg,
1032  getKillRegState(isKill)),
1033  FrameIdx));
1034  NonRI = true;
1035  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1036  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1037  .addReg(SrcReg,
1038  getKillRegState(isKill)),
1039  FrameIdx));
1040  NonRI = true;
1041  } else {
1042  llvm_unreachable("Unknown regclass!");
1043  }
1044 
1045  return false;
1046 }
1047 
1048 void
1051  unsigned SrcReg, bool isKill, int FrameIdx,
1052  const TargetRegisterClass *RC,
1053  const TargetRegisterInfo *TRI) const {
1054  MachineFunction &MF = *MBB.getParent();
1056 
1057  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1058  FuncInfo->setHasSpills();
1059 
1060  // We need to avoid a situation in which the value from a VRRC register is
1061  // spilled using an Altivec instruction and reloaded into a VSRC register
1062  // using a VSX instruction. The issue with this is that the VSX
1063  // load/store instructions swap the doublewords in the vector and the Altivec
1064  // ones don't. The register classes on the spill/reload may be different if
1065  // the register is defined using an Altivec instruction and is then used by a
1066  // VSX instruction.
1067  RC = updatedRC(RC);
1068 
1069  bool NonRI = false, SpillsVRS = false;
1070  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1071  NonRI, SpillsVRS))
1072  FuncInfo->setSpillsCR();
1073 
1074  if (SpillsVRS)
1075  FuncInfo->setSpillsVRSAVE();
1076 
1077  if (NonRI)
1078  FuncInfo->setHasNonRISpills();
1079 
1080  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1081  MBB.insert(MI, NewMIs[i]);
1082 
1083  const MachineFrameInfo &MFI = MF.getFrameInfo();
1085  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1087  MFI.getObjectAlignment(FrameIdx));
1088  NewMIs.back()->addMemOperand(MF, MMO);
1089 }
1090 
1091 bool PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1092  unsigned DestReg, int FrameIdx,
1093  const TargetRegisterClass *RC,
1095  bool &NonRI, bool &SpillsVRS) const {
1096  // Note: If additional load instructions are added here,
1097  // update isLoadFromStackSlot.
1098 
1099  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1100  PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1101  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1102  DestReg), FrameIdx));
1103  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1104  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1105  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1106  FrameIdx));
1107  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1108  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1109  FrameIdx));
1110  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1111  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1112  FrameIdx));
1113  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1114  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1115  get(PPC::RESTORE_CR), DestReg),
1116  FrameIdx));
1117  return true;
1118  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1119  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1120  get(PPC::RESTORE_CRBIT), DestReg),
1121  FrameIdx));
1122  return true;
1123  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1124  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1125  FrameIdx));
1126  NonRI = true;
1127  } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1128  unsigned Op = Subtarget.hasP9Vector() ? PPC::LXVX : PPC::LXVD2X;
1129  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Op), DestReg),
1130  FrameIdx));
1131  NonRI = true;
1132  } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1133  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf64 : PPC::LXSDX;
1134  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1135  DestReg), FrameIdx));
1136  NonRI = true;
1137  } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1138  unsigned Opc = Subtarget.hasP9Vector() ? PPC::DFLOADf32 : PPC::LXSSPX;
1139  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opc),
1140  DestReg), FrameIdx));
1141  NonRI = true;
1142  } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1143  assert(Subtarget.isDarwin() &&
1144  "VRSAVE only needs spill/restore on Darwin");
1145  NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1146  get(PPC::RESTORE_VRSAVE),
1147  DestReg),
1148  FrameIdx));
1149  SpillsVRS = true;
1150  } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1151  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1152  FrameIdx));
1153  NonRI = true;
1154  } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1155  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1156  FrameIdx));
1157  NonRI = true;
1158  } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1159  NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1160  FrameIdx));
1161  NonRI = true;
1162  } else {
1163  llvm_unreachable("Unknown regclass!");
1164  }
1165 
1166  return false;
1167 }
1168 
1169 void
1172  unsigned DestReg, int FrameIdx,
1173  const TargetRegisterClass *RC,
1174  const TargetRegisterInfo *TRI) const {
1175  MachineFunction &MF = *MBB.getParent();
1177  DebugLoc DL;
1178  if (MI != MBB.end()) DL = MI->getDebugLoc();
1179 
1180  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1181  FuncInfo->setHasSpills();
1182 
1183  // We need to avoid a situation in which the value from a VRRC register is
1184  // spilled using an Altivec instruction and reloaded into a VSRC register
1185  // using a VSX instruction. The issue with this is that the VSX
1186  // load/store instructions swap the doublewords in the vector and the Altivec
1187  // ones don't. The register classes on the spill/reload may be different if
1188  // the register is defined using an Altivec instruction and is then used by a
1189  // VSX instruction.
1190  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1191  RC = &PPC::VSRCRegClass;
1192 
1193  bool NonRI = false, SpillsVRS = false;
1194  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1195  NonRI, SpillsVRS))
1196  FuncInfo->setSpillsCR();
1197 
1198  if (SpillsVRS)
1199  FuncInfo->setSpillsVRSAVE();
1200 
1201  if (NonRI)
1202  FuncInfo->setHasNonRISpills();
1203 
1204  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1205  MBB.insert(MI, NewMIs[i]);
1206 
1207  const MachineFrameInfo &MFI = MF.getFrameInfo();
1209  MachinePointerInfo::getFixedStack(MF, FrameIdx),
1211  MFI.getObjectAlignment(FrameIdx));
1212  NewMIs.back()->addMemOperand(MF, MMO);
1213 }
1214 
1215 bool PPCInstrInfo::
1217  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1218  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1219  Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1220  else
1221  // Leave the CR# the same, but invert the condition.
1222  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1223  return false;
1224 }
1225 
1227  unsigned Reg, MachineRegisterInfo *MRI) const {
1228  // For some instructions, it is legal to fold ZERO into the RA register field.
1229  // A zero immediate should always be loaded with a single li.
1230  unsigned DefOpc = DefMI.getOpcode();
1231  if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1232  return false;
1233  if (!DefMI.getOperand(1).isImm())
1234  return false;
1235  if (DefMI.getOperand(1).getImm() != 0)
1236  return false;
1237 
1238  // Note that we cannot here invert the arguments of an isel in order to fold
1239  // a ZERO into what is presented as the second argument. All we have here
1240  // is the condition bit, and that might come from a CR-logical bit operation.
1241 
1242  const MCInstrDesc &UseMCID = UseMI.getDesc();
1243 
1244  // Only fold into real machine instructions.
1245  if (UseMCID.isPseudo())
1246  return false;
1247 
1248  unsigned UseIdx;
1249  for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1250  if (UseMI.getOperand(UseIdx).isReg() &&
1251  UseMI.getOperand(UseIdx).getReg() == Reg)
1252  break;
1253 
1254  assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI");
1255  assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1256 
1257  const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1258 
1259  // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1260  // register (which might also be specified as a pointer class kind).
1261  if (UseInfo->isLookupPtrRegClass()) {
1262  if (UseInfo->RegClass /* Kind */ != 1)
1263  return false;
1264  } else {
1265  if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1266  UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1267  return false;
1268  }
1269 
1270  // Make sure this is not tied to an output register (or otherwise
1271  // constrained). This is true for ST?UX registers, for example, which
1272  // are tied to their output registers.
1273  if (UseInfo->Constraints != 0)
1274  return false;
1275 
1276  unsigned ZeroReg;
1277  if (UseInfo->isLookupPtrRegClass()) {
1278  bool isPPC64 = Subtarget.isPPC64();
1279  ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1280  } else {
1281  ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1282  PPC::ZERO8 : PPC::ZERO;
1283  }
1284 
1285  bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1286  UseMI.getOperand(UseIdx).setReg(ZeroReg);
1287 
1288  if (DeleteDef)
1289  DefMI.eraseFromParent();
1290 
1291  return true;
1292 }
1293 
1295  for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1296  I != IE; ++I)
1297  if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1298  return true;
1299  return false;
1300 }
1301 
1302 // We should make sure that, if we're going to predicate both sides of a
1303 // condition (a diamond), that both sides don't define the counter register. We
1304 // can predicate counter-decrement-based branches, but while that predicates
1305 // the branching, it does not predicate the counter decrement. If we tried to
1306 // merge the triangle into one predicated block, we'd decrement the counter
1307 // twice.
1309  unsigned NumT, unsigned ExtraT,
1310  MachineBasicBlock &FMBB,
1311  unsigned NumF, unsigned ExtraF,
1312  BranchProbability Probability) const {
1313  return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1314 }
1315 
1316 
1318  // The predicated branches are identified by their type, not really by the
1319  // explicit presence of a predicate. Furthermore, some of them can be
1320  // predicated more than once. Because if conversion won't try to predicate
1321  // any instruction which already claims to be predicated (by returning true
1322  // here), always return false. In doing so, we let isPredicable() be the
1323  // final word on whether not the instruction can be (further) predicated.
1324 
1325  return false;
1326 }
1327 
1329  if (!MI.isTerminator())
1330  return false;
1331 
1332  // Conditional branch is a special case.
1333  if (MI.isBranch() && !MI.isBarrier())
1334  return true;
1335 
1336  return !isPredicated(MI);
1337 }
1338 
1340  ArrayRef<MachineOperand> Pred) const {
1341  unsigned OpC = MI.getOpcode();
1342  if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1343  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1344  bool isPPC64 = Subtarget.isPPC64();
1345  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1346  : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1347  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1348  MI.setDesc(get(PPC::BCLR));
1350  .addReg(Pred[1].getReg());
1351  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1352  MI.setDesc(get(PPC::BCLRn));
1354  .addReg(Pred[1].getReg());
1355  } else {
1356  MI.setDesc(get(PPC::BCCLR));
1358  .addImm(Pred[0].getImm())
1359  .addReg(Pred[1].getReg());
1360  }
1361 
1362  return true;
1363  } else if (OpC == PPC::B) {
1364  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1365  bool isPPC64 = Subtarget.isPPC64();
1366  MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1367  : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1368  } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1370  MI.RemoveOperand(0);
1371 
1372  MI.setDesc(get(PPC::BC));
1374  .addReg(Pred[1].getReg())
1375  .addMBB(MBB);
1376  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1378  MI.RemoveOperand(0);
1379 
1380  MI.setDesc(get(PPC::BCn));
1382  .addReg(Pred[1].getReg())
1383  .addMBB(MBB);
1384  } else {
1386  MI.RemoveOperand(0);
1387 
1388  MI.setDesc(get(PPC::BCC));
1390  .addImm(Pred[0].getImm())
1391  .addReg(Pred[1].getReg())
1392  .addMBB(MBB);
1393  }
1394 
1395  return true;
1396  } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1397  OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1398  if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1399  llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1400 
1401  bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1402  bool isPPC64 = Subtarget.isPPC64();
1403 
1404  if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1405  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1406  : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1408  .addReg(Pred[1].getReg());
1409  return true;
1410  } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1411  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1412  : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1414  .addReg(Pred[1].getReg());
1415  return true;
1416  }
1417 
1418  MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1419  : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1421  .addImm(Pred[0].getImm())
1422  .addReg(Pred[1].getReg());
1423  return true;
1424  }
1425 
1426  return false;
1427 }
1428 
1430  ArrayRef<MachineOperand> Pred2) const {
1431  assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1432  assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1433 
1434  if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1435  return false;
1436  if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1437  return false;
1438 
1439  // P1 can only subsume P2 if they test the same condition register.
1440  if (Pred1[1].getReg() != Pred2[1].getReg())
1441  return false;
1442 
1443  PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1444  PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1445 
1446  if (P1 == P2)
1447  return true;
1448 
1449  // Does P1 subsume P2, e.g. GE subsumes GT.
1450  if (P1 == PPC::PRED_LE &&
1451  (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1452  return true;
1453  if (P1 == PPC::PRED_GE &&
1454  (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1455  return true;
1456 
1457  return false;
1458 }
1459 
1461  std::vector<MachineOperand> &Pred) const {
1462  // Note: At the present time, the contents of Pred from this function is
1463  // unused by IfConversion. This implementation follows ARM by pushing the
1464  // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1465  // predicate, instructions defining CTR or CTR8 are also included as
1466  // predicate-defining instructions.
1467 
1468  const TargetRegisterClass *RCs[] =
1469  { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1470  &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1471 
1472  bool Found = false;
1473  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1474  const MachineOperand &MO = MI.getOperand(i);
1475  for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1476  const TargetRegisterClass *RC = RCs[c];
1477  if (MO.isReg()) {
1478  if (MO.isDef() && RC->contains(MO.getReg())) {
1479  Pred.push_back(MO);
1480  Found = true;
1481  }
1482  } else if (MO.isRegMask()) {
1483  for (TargetRegisterClass::iterator I = RC->begin(),
1484  IE = RC->end(); I != IE; ++I)
1485  if (MO.clobbersPhysReg(*I)) {
1486  Pred.push_back(MO);
1487  Found = true;
1488  }
1489  }
1490  }
1491  }
1492 
1493  return Found;
1494 }
1495 
1497  unsigned OpC = MI.getOpcode();
1498  switch (OpC) {
1499  default:
1500  return false;
1501  case PPC::B:
1502  case PPC::BLR:
1503  case PPC::BLR8:
1504  case PPC::BCTR:
1505  case PPC::BCTR8:
1506  case PPC::BCTRL:
1507  case PPC::BCTRL8:
1508  return true;
1509  }
1510 }
1511 
1512 bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1513  unsigned &SrcReg2, int &Mask,
1514  int &Value) const {
1515  unsigned Opc = MI.getOpcode();
1516 
1517  switch (Opc) {
1518  default: return false;
1519  case PPC::CMPWI:
1520  case PPC::CMPLWI:
1521  case PPC::CMPDI:
1522  case PPC::CMPLDI:
1523  SrcReg = MI.getOperand(1).getReg();
1524  SrcReg2 = 0;
1525  Value = MI.getOperand(2).getImm();
1526  Mask = 0xFFFF;
1527  return true;
1528  case PPC::CMPW:
1529  case PPC::CMPLW:
1530  case PPC::CMPD:
1531  case PPC::CMPLD:
1532  case PPC::FCMPUS:
1533  case PPC::FCMPUD:
1534  SrcReg = MI.getOperand(1).getReg();
1535  SrcReg2 = MI.getOperand(2).getReg();
1536  return true;
1537  }
1538 }
1539 
1540 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1541  unsigned SrcReg2, int Mask, int Value,
1542  const MachineRegisterInfo *MRI) const {
1543  if (DisableCmpOpt)
1544  return false;
1545 
1546  int OpC = CmpInstr.getOpcode();
1547  unsigned CRReg = CmpInstr.getOperand(0).getReg();
1548 
1549  // FP record forms set CR1 based on the execption status bits, not a
1550  // comparison with zero.
1551  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1552  return false;
1553 
1554  // The record forms set the condition register based on a signed comparison
1555  // with zero (so says the ISA manual). This is not as straightforward as it
1556  // seems, however, because this is always a 64-bit comparison on PPC64, even
1557  // for instructions that are 32-bit in nature (like slw for example).
1558  // So, on PPC32, for unsigned comparisons, we can use the record forms only
1559  // for equality checks (as those don't depend on the sign). On PPC64,
1560  // we are restricted to equality for unsigned 64-bit comparisons and for
1561  // signed 32-bit comparisons the applicability is more restricted.
1562  bool isPPC64 = Subtarget.isPPC64();
1563  bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1564  bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1565  bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1566 
1567  // Get the unique definition of SrcReg.
1568  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1569  if (!MI) return false;
1570  int MIOpC = MI->getOpcode();
1571 
1572  bool equalityOnly = false;
1573  bool noSub = false;
1574  if (isPPC64) {
1575  if (is32BitSignedCompare) {
1576  // We can perform this optimization only if MI is sign-extending.
1577  if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1578  MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1579  MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1580  MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1581  MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1582  noSub = true;
1583  } else
1584  return false;
1585  } else if (is32BitUnsignedCompare) {
1586  // 32-bit rotate and mask instructions are zero extending only if MB <= ME
1587  bool isZeroExtendingRotate =
1588  (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINMo ||
1589  MIOpC == PPC::RLWNM || MIOpC == PPC::RLWNMo)
1590  && MI->getOperand(3).getImm() <= MI->getOperand(4).getImm();
1591 
1592  // We can perform this optimization, equality only, if MI is
1593  // zero-extending.
1594  if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1595  MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1596  MIOpC == PPC::SRW || MIOpC == PPC::SRWo ||
1597  isZeroExtendingRotate) {
1598  noSub = true;
1599  equalityOnly = true;
1600  } else
1601  return false;
1602  } else
1603  equalityOnly = is64BitUnsignedCompare;
1604  } else
1605  equalityOnly = is32BitUnsignedCompare;
1606 
1607  if (equalityOnly) {
1608  // We need to check the uses of the condition register in order to reject
1609  // non-equality comparisons.
1611  IE = MRI->use_instr_end(); I != IE; ++I) {
1612  MachineInstr *UseMI = &*I;
1613  if (UseMI->getOpcode() == PPC::BCC) {
1614  unsigned Pred = UseMI->getOperand(0).getImm();
1615  if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1616  return false;
1617  } else if (UseMI->getOpcode() == PPC::ISEL ||
1618  UseMI->getOpcode() == PPC::ISEL8) {
1619  unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1620  if (SubIdx != PPC::sub_eq)
1621  return false;
1622  } else
1623  return false;
1624  }
1625  }
1626 
1627  MachineBasicBlock::iterator I = CmpInstr;
1628 
1629  // Scan forward to find the first use of the compare.
1630  for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1631  ++I) {
1632  bool FoundUse = false;
1634  JE = MRI->use_instr_end(); J != JE; ++J)
1635  if (&*J == &*I) {
1636  FoundUse = true;
1637  break;
1638  }
1639 
1640  if (FoundUse)
1641  break;
1642  }
1643 
1644  // There are two possible candidates which can be changed to set CR[01].
1645  // One is MI, the other is a SUB instruction.
1646  // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1647  MachineInstr *Sub = nullptr;
1648  if (SrcReg2 != 0)
1649  // MI is not a candidate for CMPrr.
1650  MI = nullptr;
1651  // FIXME: Conservatively refuse to convert an instruction which isn't in the
1652  // same BB as the comparison. This is to allow the check below to avoid calls
1653  // (and other explicit clobbers); instead we should really check for these
1654  // more explicitly (in at least a few predecessors).
1655  else if (MI->getParent() != CmpInstr.getParent() || Value != 0) {
1656  // PPC does not have a record-form SUBri.
1657  return false;
1658  }
1659 
1660  // Search for Sub.
1661  const TargetRegisterInfo *TRI = &getRegisterInfo();
1662  --I;
1663 
1664  // Get ready to iterate backward from CmpInstr.
1665  MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1666 
1667  for (; I != E && !noSub; --I) {
1668  const MachineInstr &Instr = *I;
1669  unsigned IOpC = Instr.getOpcode();
1670 
1671  if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1672  Instr.readsRegister(PPC::CR0, TRI)))
1673  // This instruction modifies or uses the record condition register after
1674  // the one we want to change. While we could do this transformation, it
1675  // would likely not be profitable. This transformation removes one
1676  // instruction, and so even forcing RA to generate one move probably
1677  // makes it unprofitable.
1678  return false;
1679 
1680  // Check whether CmpInstr can be made redundant by the current instruction.
1681  if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1682  OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1683  (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1684  ((Instr.getOperand(1).getReg() == SrcReg &&
1685  Instr.getOperand(2).getReg() == SrcReg2) ||
1686  (Instr.getOperand(1).getReg() == SrcReg2 &&
1687  Instr.getOperand(2).getReg() == SrcReg))) {
1688  Sub = &*I;
1689  break;
1690  }
1691 
1692  if (I == B)
1693  // The 'and' is below the comparison instruction.
1694  return false;
1695  }
1696 
1697  // Return false if no candidates exist.
1698  if (!MI && !Sub)
1699  return false;
1700 
1701  // The single candidate is called MI.
1702  if (!MI) MI = Sub;
1703 
1704  int NewOpC = -1;
1705  MIOpC = MI->getOpcode();
1706  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1707  NewOpC = MIOpC;
1708  else {
1709  NewOpC = PPC::getRecordFormOpcode(MIOpC);
1710  if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1711  NewOpC = MIOpC;
1712  }
1713 
1714  // FIXME: On the non-embedded POWER architectures, only some of the record
1715  // forms are fast, and we should use only the fast ones.
1716 
1717  // The defining instruction has a record form (or is already a record
1718  // form). It is possible, however, that we'll need to reverse the condition
1719  // code of the users.
1720  if (NewOpC == -1)
1721  return false;
1722 
1725 
1726  // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1727  // needs to be updated to be based on SUB. Push the condition code
1728  // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1729  // condition code of these operands will be modified.
1730  bool ShouldSwap = false;
1731  if (Sub) {
1732  ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1733  Sub->getOperand(2).getReg() == SrcReg;
1734 
1735  // The operands to subf are the opposite of sub, so only in the fixed-point
1736  // case, invert the order.
1737  ShouldSwap = !ShouldSwap;
1738  }
1739 
1740  if (ShouldSwap)
1742  I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1743  I != IE; ++I) {
1744  MachineInstr *UseMI = &*I;
1745  if (UseMI->getOpcode() == PPC::BCC) {
1746  PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1747  assert((!equalityOnly ||
1748  Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1749  "Invalid predicate for equality-only optimization");
1750  PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1751  PPC::getSwappedPredicate(Pred)));
1752  } else if (UseMI->getOpcode() == PPC::ISEL ||
1753  UseMI->getOpcode() == PPC::ISEL8) {
1754  unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1755  assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1756  "Invalid CR bit for equality-only optimization");
1757 
1758  if (NewSubReg == PPC::sub_lt)
1759  NewSubReg = PPC::sub_gt;
1760  else if (NewSubReg == PPC::sub_gt)
1761  NewSubReg = PPC::sub_lt;
1762 
1763  SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1764  NewSubReg));
1765  } else // We need to abort on a user we don't understand.
1766  return false;
1767  }
1768 
1769  // Create a new virtual register to hold the value of the CR set by the
1770  // record-form instruction. If the instruction was not previously in
1771  // record form, then set the kill flag on the CR.
1772  CmpInstr.eraseFromParent();
1773 
1775  BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1776  get(TargetOpcode::COPY), CRReg)
1777  .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1778 
1779  // Even if CR0 register were dead before, it is alive now since the
1780  // instruction we just built uses it.
1781  MI->clearRegisterDeads(PPC::CR0);
1782 
1783  if (MIOpC != NewOpC) {
1784  // We need to be careful here: we're replacing one instruction with
1785  // another, and we need to make sure that we get all of the right
1786  // implicit uses and defs. On the other hand, the caller may be holding
1787  // an iterator to this instruction, and so we can't delete it (this is
1788  // specifically the case if this is the instruction directly after the
1789  // compare).
1790 
1791  const MCInstrDesc &NewDesc = get(NewOpC);
1792  MI->setDesc(NewDesc);
1793 
1794  if (NewDesc.ImplicitDefs)
1795  for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1796  *ImpDefs; ++ImpDefs)
1797  if (!MI->definesRegister(*ImpDefs))
1798  MI->addOperand(*MI->getParent()->getParent(),
1799  MachineOperand::CreateReg(*ImpDefs, true, true));
1800  if (NewDesc.ImplicitUses)
1801  for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1802  *ImpUses; ++ImpUses)
1803  if (!MI->readsRegister(*ImpUses))
1804  MI->addOperand(*MI->getParent()->getParent(),
1805  MachineOperand::CreateReg(*ImpUses, false, true));
1806  }
1807  assert(MI->definesRegister(PPC::CR0) &&
1808  "Record-form instruction does not define cr0?");
1809 
1810  // Modify the condition code of operands in OperandsToUpdate.
1811  // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1812  // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1813  for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1814  PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1815 
1816  for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1817  SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1818 
1819  return true;
1820 }
1821 
1822 /// GetInstSize - Return the number of bytes of code the specified
1823 /// instruction may be. This returns the maximum number of bytes.
1824 ///
1826  unsigned Opcode = MI.getOpcode();
1827 
1828  if (Opcode == PPC::INLINEASM) {
1829  const MachineFunction *MF = MI.getParent()->getParent();
1830  const char *AsmStr = MI.getOperand(0).getSymbolName();
1831  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1832  } else if (Opcode == TargetOpcode::STACKMAP) {
1833  StackMapOpers Opers(&MI);
1834  return Opers.getNumPatchBytes();
1835  } else if (Opcode == TargetOpcode::PATCHPOINT) {
1836  PatchPointOpers Opers(&MI);
1837  return Opers.getNumPatchBytes();
1838  } else {
1839  const MCInstrDesc &Desc = get(Opcode);
1840  return Desc.getSize();
1841  }
1842 }
1843 
1844 std::pair<unsigned, unsigned>
1846  const unsigned Mask = PPCII::MO_ACCESS_MASK;
1847  return std::make_pair(TF & Mask, TF & ~Mask);
1848 }
1849 
1852  using namespace PPCII;
1853  static const std::pair<unsigned, const char *> TargetFlags[] = {
1854  {MO_LO, "ppc-lo"},
1855  {MO_HA, "ppc-ha"},
1856  {MO_TPREL_LO, "ppc-tprel-lo"},
1857  {MO_TPREL_HA, "ppc-tprel-ha"},
1858  {MO_DTPREL_LO, "ppc-dtprel-lo"},
1859  {MO_TLSLD_LO, "ppc-tlsld-lo"},
1860  {MO_TOC_LO, "ppc-toc-lo"},
1861  {MO_TLS, "ppc-tls"}};
1862  return makeArrayRef(TargetFlags);
1863 }
1864 
1867  using namespace PPCII;
1868  static const std::pair<unsigned, const char *> TargetFlags[] = {
1869  {MO_PLT, "ppc-plt"},
1870  {MO_PIC_FLAG, "ppc-pic"},
1871  {MO_NLP_FLAG, "ppc-nlp"},
1872  {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1873  return makeArrayRef(TargetFlags);
1874 }
1875 
1877  switch (MI.getOpcode()) {
1878  case TargetOpcode::LOAD_STACK_GUARD: {
1879  assert(Subtarget.isTargetLinux() &&
1880  "Only Linux target is expected to contain LOAD_STACK_GUARD");
1881  const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
1882  const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
1883  MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
1885  .addImm(Offset)
1886  .addReg(Reg);
1887  return true;
1888  }
1889  case PPC::DFLOADf32:
1890  case PPC::DFLOADf64:
1891  case PPC::DFSTOREf32:
1892  case PPC::DFSTOREf64: {
1893  assert(Subtarget.hasP9Vector() &&
1894  "Invalid D-Form Pseudo-ops on non-P9 target.");
1895  unsigned UpperOpcode, LowerOpcode;
1896  switch (MI.getOpcode()) {
1897  case PPC::DFLOADf32:
1898  UpperOpcode = PPC::LXSSP;
1899  LowerOpcode = PPC::LFS;
1900  break;
1901  case PPC::DFLOADf64:
1902  UpperOpcode = PPC::LXSD;
1903  LowerOpcode = PPC::LFD;
1904  break;
1905  case PPC::DFSTOREf32:
1906  UpperOpcode = PPC::STXSSP;
1907  LowerOpcode = PPC::STFS;
1908  break;
1909  case PPC::DFSTOREf64:
1910  UpperOpcode = PPC::STXSD;
1911  LowerOpcode = PPC::STFD;
1912  break;
1913  }
1914  unsigned TargetReg = MI.getOperand(0).getReg();
1915  unsigned Opcode;
1916  if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
1917  (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
1918  Opcode = LowerOpcode;
1919  else
1920  Opcode = UpperOpcode;
1921  MI.setDesc(get(Opcode));
1922  return true;
1923  }
1924  }
1925  return false;
1926 }
1927 
1928 const TargetRegisterClass *
1930  if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1931  return &PPC::VSRCRegClass;
1932  return RC;
1933 }
bool isImplicit() const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given patchpoint should emit.
Definition: StackMaps.h:98
int getNonRecordFormOpcode(uint16_t)
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:448
size_t i
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
MachineBasicBlock * getMBB() const
const PPCTargetMachine & getTargetMachine() const
Definition: PPCSubtarget.h:189
bool hasISEL() const
Definition: PPCSubtarget.h:249
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static cl::opt< bool > DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden)
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
bool isDarwin() const
isDarwin - True if this is any darwin platform.
Definition: PPCSubtarget.h:289
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const char * getSymbolName() const
A debug info location.
Definition: DebugLoc.h:34
bool isPredicable(MachineInstr &MI) const override
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
#define R2(n)
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
return AArch64::GPR64RegClass contains(Reg)
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MachineFunction & MF
Definition: ScheduleDAG.h:581
bool hasP9Vector() const
Definition: PPCSubtarget.h:246
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based hazard recognizer for P...
A description of a memory reference used in the backend.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:440
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
use_instr_iterator use_instr_begin(unsigned RegNo) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
iterator begin() const
begin/end - Return all of the registers in this class.
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
defusechain_iterator - This class provides iterator support for machine operands in the function that...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
PPCInstrInfo(PPCSubtarget &STI)
bool isKill() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
MachineBasicBlock * MBB
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a symbol with hidden visibility...
Definition: PPC.h:79
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
Definition: MCInstrDesc.h:525
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
int64_t getImm() const
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:141
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
unsigned getDeadRegState(bool B)
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
int getAltVSXFMAOpcode(uint16_t Opcode)
Simple binary floating point operators.
Definition: ISDOpcodes.h:246
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
MachineInstrBuilder & UseMI
MO_NLP_FLAG - If this bit is set, the symbol reference is actually to the non_lazy_ptr for the global...
Definition: PPC.h:74
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:560
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:173
uint32_t Offset
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
void setImm(int64_t immVal)
MI-level patchpoint operands.
Definition: StackMaps.h:70
PPCHazardRecognizer970 - This class defines a finite state automata that models the dispatch logic on...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:136
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isPseudo() const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
Definition: MCInstrDesc.h:233
static unsigned getCRFromCRBit(unsigned SrcReg)
MO_TLS - Indicates that the operand being accessed is some kind of thread-local symbol.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:895
bool isTargetLinux() const
Definition: PPCSubtarget.h:295
void setIsKill(bool Val=true)
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
The next are not flags but distinct values.
Definition: PPC.h:82
The memory access writes data.
static bool MBBDefinesCTR(MachineBasicBlock &MBB)
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:865
void setOpcode(unsigned Op)
Definition: MCInst.h:158
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static unsigned getCRBitValue(unsigned CRBit)
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:649
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:27
static cl::opt< bool > VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy", cl::desc("Causes the backend to crash instead of generating a nop VSX copy"), cl::Hidden)
static cl::opt< bool > UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden, cl::desc("Use the old (incorrect) instruction latency calculation"))
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineInstr * getUniqueVRegDef(unsigned Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:53
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
Definition: StackMaps.h:44
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:114
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Predicate InvertPredicate(Predicate Opcode)
Invert the specified predicate. != -> ==, < -> >=.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:556
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MI-level stackmap operands.
Definition: StackMaps.h:29
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
bool hasOneNonDBGUse(unsigned RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...
void setReg(unsigned Reg)
Change the register this operand corresponds to.
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void setSubReg(unsigned subReg)
bool hasVSX() const
Definition: PPCSubtarget.h:242
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const MCPhysReg * getImplicitUses() const
Return a list of registers that are potentially read by any instance of this machine instruction...
Definition: MCInstrDesc.h:503
const TargetInstrInfo * TII
Definition: ScheduleDAG.h:579
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
LLVM Value Representation.
Definition: Value.h:71
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
static use_instr_iterator use_instr_end()
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:210
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
unsigned getDarwinDirective() const
getDarwinDirective - Returns the -m directive specified for the cpu.
Definition: PPCSubtarget.h:168
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:70
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
Definition: PPC.h:66
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:220
static cl::opt< bool > DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, cl::desc("Disable analysis for CTR loops"))
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:903
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:431
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function's picbase...
Definition: PPC.h:70
bool expandPostRAPseudo(MachineInstr &MI) const override
const MCPhysReg * ImplicitUses
Definition: MCInstrDesc.h:172
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...