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LLVM
4.0.0
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#include "llvm/CodeGen/AtomicExpandUtils.h"#include "llvm/CodeGen/Passes.h"#include "llvm/IR/Function.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/InstIterator.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/Module.h"#include "llvm/Support/Debug.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetLowering.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetSubtargetInfo.h"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "atomic-expand" |
Functions | |
| INITIALIZE_TM_PASS (AtomicExpand,"atomic-expand","Expand Atomic instructions", false, false) FunctionPass *llvm | |
| static void | createCmpXchgInstFun (IRBuilder<> &Builder, Value *Addr, Value *Loaded, Value *NewVal, AtomicOrdering MemOpOrder, Value *&Success, Value *&NewLoaded) |
| static Value * | performAtomicOp (AtomicRMWInst::BinOp Op, IRBuilder<> &Builder, Value *Loaded, Value *Inc) |
| Emit IR to implement the given atomicrmw operation on values in registers, returning the new value. More... | |
| static PartwordMaskValues | createMaskInstrs (IRBuilder<> &Builder, Instruction *I, Type *ValueType, Value *Addr, unsigned WordSize) |
| This is a helper function which builds instructions to provide values necessary for partword atomic operations. More... | |
| static Value * | performMaskedAtomicOp (AtomicRMWInst::BinOp Op, IRBuilder<> &Builder, Value *Loaded, Value *Shifted_Inc, Value *Inc, const PartwordMaskValues &PMV) |
| Emit IR to implement a masked version of a given atomicrmw operation. More... | |
| static bool | canUseSizedAtomicCall (unsigned Size, unsigned Align, const DataLayout &DL) |
| static ArrayRef< RTLIB::Libcall > | GetRMWLibcall (AtomicRMWInst::BinOp Op) |
| #define DEBUG_TYPE "atomic-expand" |
Definition at line 34 of file AtomicExpandPass.cpp.
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Definition at line 1296 of file AtomicExpandPass.cpp.
References llvm::DataLayout::getLargestLegalIntTypeSizeInBits().
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Definition at line 477 of file AtomicExpandPass.cpp.
References llvm::IRBuilder< T, Inserter >::CreateAtomicCmpXchg(), llvm::IRBuilder< T, Inserter >::CreateExtractValue(), and llvm::AtomicCmpXchgInst::getStrongestFailureOrdering().
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This is a helper function which builds instructions to provide values necessary for partword atomic operations.
It takes an incoming address, Addr, and ValueType, and constructs the address, shift-amounts and masks needed to work with a larger value of size WordSize.
AlignedAddr: Addr rounded down to a multiple of WordSize
ShiftAmt: Number of bits to right-shift a WordSize value loaded from AlignAddr for it to have the same value as if ValueType was loaded from Addr.
Mask: Value to mask with the value loaded from AlignAddr to include only the part that would've been loaded from Addr.
Inv_Mask: The inverse of Mask.
Definition at line 591 of file AtomicExpandPass.cpp.
References assert(), llvm::IRBuilder< T, Inserter >::CreateAnd(), llvm::IRBuilder< T, Inserter >::CreateIntToPtr(), llvm::IRBuilder< T, Inserter >::CreateNot(), llvm::IRBuilder< T, Inserter >::CreatePtrToInt(), llvm::IRBuilder< T, Inserter >::CreateShl(), llvm::IRBuilder< T, Inserter >::CreateTrunc(), llvm::IRBuilder< T, Inserter >::CreateXor(), llvm::ConstantInt::get(), llvm::Function::getContext(), llvm::Module::getDataLayout(), llvm::Type::getIntNTy(), llvm::DataLayout::getIntPtrType(), llvm::Instruction::getModule(), llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), llvm::Type::getPointerAddressSpace(), llvm::Value::getType(), llvm::DataLayout::getTypeStoreSize(), llvm::DataLayout::isLittleEndian(), and llvm::MipsISD::Ret.
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Definition at line 1355 of file AtomicExpandPass.cpp.
References llvm::AtomicRMWInst::Add, llvm::AtomicRMWInst::And, llvm::RTLIB::ATOMIC_EXCHANGE, llvm::RTLIB::ATOMIC_EXCHANGE_1, llvm::RTLIB::ATOMIC_EXCHANGE_16, llvm::RTLIB::ATOMIC_EXCHANGE_2, llvm::RTLIB::ATOMIC_EXCHANGE_4, llvm::RTLIB::ATOMIC_EXCHANGE_8, llvm::RTLIB::ATOMIC_FETCH_ADD_1, llvm::RTLIB::ATOMIC_FETCH_ADD_16, llvm::RTLIB::ATOMIC_FETCH_ADD_2, llvm::RTLIB::ATOMIC_FETCH_ADD_4, llvm::RTLIB::ATOMIC_FETCH_ADD_8, llvm::RTLIB::ATOMIC_FETCH_AND_1, llvm::RTLIB::ATOMIC_FETCH_AND_16, llvm::RTLIB::ATOMIC_FETCH_AND_2, llvm::RTLIB::ATOMIC_FETCH_AND_4, llvm::RTLIB::ATOMIC_FETCH_AND_8, llvm::RTLIB::ATOMIC_FETCH_NAND_1, llvm::RTLIB::ATOMIC_FETCH_NAND_16, llvm::RTLIB::ATOMIC_FETCH_NAND_2, llvm::RTLIB::ATOMIC_FETCH_NAND_4, llvm::RTLIB::ATOMIC_FETCH_NAND_8, llvm::RTLIB::ATOMIC_FETCH_OR_1, llvm::RTLIB::ATOMIC_FETCH_OR_16, llvm::RTLIB::ATOMIC_FETCH_OR_2, llvm::RTLIB::ATOMIC_FETCH_OR_4, llvm::RTLIB::ATOMIC_FETCH_OR_8, llvm::RTLIB::ATOMIC_FETCH_SUB_1, llvm::RTLIB::ATOMIC_FETCH_SUB_16, llvm::RTLIB::ATOMIC_FETCH_SUB_2, llvm::RTLIB::ATOMIC_FETCH_SUB_4, llvm::RTLIB::ATOMIC_FETCH_SUB_8, llvm::RTLIB::ATOMIC_FETCH_XOR_1, llvm::RTLIB::ATOMIC_FETCH_XOR_16, llvm::RTLIB::ATOMIC_FETCH_XOR_2, llvm::RTLIB::ATOMIC_FETCH_XOR_4, llvm::RTLIB::ATOMIC_FETCH_XOR_8, llvm::AtomicRMWInst::BAD_BINOP, llvm_unreachable, llvm::makeArrayRef(), llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Or, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, llvm::RTLIB::UNKNOWN_LIBCALL, llvm::AtomicRMWInst::Xchg, and llvm::AtomicRMWInst::Xor.
| INITIALIZE_TM_PASS | ( | AtomicExpand | , |
| "atomic-expand" | , | ||
| "Expand Atomic instructions" | , | ||
| false | , | ||
| false | |||
| ) |
Definition at line 101 of file AtomicExpandPass.cpp.
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Emit IR to implement the given atomicrmw operation on values in registers, returning the new value.
Definition at line 490 of file AtomicExpandPass.cpp.
References llvm::AtomicRMWInst::Add, llvm::AtomicRMWInst::And, llvm::IRBuilder< T, Inserter >::CreateAdd(), llvm::IRBuilder< T, Inserter >::CreateAnd(), llvm::IRBuilder< T, Inserter >::CreateICmpSGT(), llvm::IRBuilder< T, Inserter >::CreateICmpSLE(), llvm::IRBuilder< T, Inserter >::CreateICmpUGT(), llvm::IRBuilder< T, Inserter >::CreateICmpULE(), llvm::IRBuilder< T, Inserter >::CreateNot(), llvm::IRBuilder< T, Inserter >::CreateOr(), llvm::IRBuilder< T, Inserter >::CreateSelect(), llvm::IRBuilder< T, Inserter >::CreateSub(), llvm::IRBuilder< T, Inserter >::CreateXor(), llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Or, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, llvm::AtomicRMWInst::Xchg, and llvm::AtomicRMWInst::Xor.
Referenced by llvm::expandAtomicRMWToCmpXchg(), and performMaskedAtomicOp().
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Emit IR to implement a masked version of a given atomicrmw operation.
(That is, only the bits under the Mask should be affected by the operation)
Definition at line 640 of file AtomicExpandPass.cpp.
References llvm::AtomicRMWInst::Add, llvm::AtomicRMWInst::And, llvm::IRBuilder< T, Inserter >::CreateAnd(), llvm::IRBuilder< T, Inserter >::CreateLShr(), llvm::IRBuilder< T, Inserter >::CreateOr(), llvm::IRBuilder< T, Inserter >::CreateShl(), llvm::IRBuilder< T, Inserter >::CreateTrunc(), llvm::IRBuilder< T, Inserter >::CreateZExt(), llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Or, performAtomicOp(), llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, llvm::AtomicRMWInst::Xchg, and llvm::AtomicRMWInst::Xor.
1.8.6