LLVM  4.0.0
NVPTXInstrInfo.h
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1 //===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the niversity of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
15 #define LLVM_LIB_TARGET_NVPTX_NVPTXINSTRINFO_H
16 
17 #include "NVPTX.h"
18 #include "NVPTXRegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "NVPTXGenInstrInfo.inc"
23 
24 namespace llvm {
25 
27  const NVPTXRegisterInfo RegInfo;
28  virtual void anchor();
29 public:
30  explicit NVPTXInstrInfo();
31 
32  const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
33 
34  /* The following virtual functions are used in register allocation.
35  * They are not implemented because the existing interface and the logic
36  * at the caller side do not work for the elementized vector load and store.
37  *
38  * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
39  * int &FrameIndex) const;
40  * virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
41  * int &FrameIndex) const;
42  * virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
43  * MachineBasicBlock::iterator MBBI,
44  * unsigned SrcReg, bool isKill, int FrameIndex,
45  * const TargetRegisterClass *RC) const;
46  * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
47  * MachineBasicBlock::iterator MBBI,
48  * unsigned DestReg, int FrameIndex,
49  * const TargetRegisterClass *RC) const;
50  */
51 
53  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
54  bool KillSrc) const override;
55  virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
56  unsigned &DestReg) const;
57  bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
58  bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
59 
60  // Branch analysis.
62  MachineBasicBlock *&FBB,
64  bool AllowModify) const override;
66  int *BytesRemoved = nullptr) const override;
69  const DebugLoc &DL,
70  int *BytesAdded = nullptr) const override;
71  unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
72  return MI.getOperand(2).getImm();
73  }
74 
75 };
76 
77 } // namespace llvm
78 
79 #endif
bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
A debug info location.
Definition: DebugLoc.h:34
unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
MachineBasicBlock * MBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
int64_t getImm() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understo...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Representation of each machine instruction.
Definition: MachineInstr.h:52
const NVPTXRegisterInfo & getRegisterInfo() const
#define I(x, y, z)
Definition: MD5.cpp:54
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DestReg) const
IRTranslator LLVM IR MI
bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const