40 #define DEBUG_TYPE "mips-reg-info"
42 #define GET_REGINFO_TARGET_DESC
43 #include "MipsGenRegisterInfo.inc"
51 unsigned Kind)
const {
55 switch (PtrClassKind) {
57 return ABI.
ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
60 : &Mips::GPRMM16RegClass;
62 return ABI.
ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass;
64 return ABI.
ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass;
73 switch (RC->
getID()) {
76 case Mips::GPR32RegClassID:
77 case Mips::GPR64RegClassID:
78 case Mips::DSPRRegClassID: {
80 return 28 - TFI->
hasFP(MF);
82 case Mips::FGR32RegClassID:
84 case Mips::AFGR64RegClassID:
86 case Mips::FGR64RegClassID:
100 if (F->hasFnAttribute(
"interrupt")) {
102 return Subtarget.
hasMips64r6() ? CSR_Interrupt_64R6_SaveList
103 : CSR_Interrupt_64_SaveList;
105 return Subtarget.
hasMips32r6() ? CSR_Interrupt_32R6_SaveList
106 : CSR_Interrupt_32_SaveList;
110 return CSR_SingleFloatOnly_SaveList;
113 return CSR_N64_SaveList;
116 return CSR_N32_SaveList;
119 return CSR_O32_FP64_SaveList;
122 return CSR_O32_FPXX_SaveList;
124 return CSR_O32_SaveList;
132 return CSR_SingleFloatOnly_RegMask;
135 return CSR_N64_RegMask;
138 return CSR_N32_RegMask;
141 return CSR_O32_FP64_RegMask;
144 return CSR_O32_FPXX_RegMask;
146 return CSR_O32_RegMask;
150 return CSR_Mips16RetHelper_RegMask;
155 static const MCPhysReg ReservedGPR32[] = {
156 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
159 static const MCPhysReg ReservedGPR64[] = {
160 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
168 Reserved.
set(ReservedGPR32[
I]);
172 Reserved.
set(Mips::T6);
173 Reserved.
set(Mips::T7);
178 Reserved.
set(ReservedGPR64[I]);
182 Reserved.
set(Mips::GP);
183 Reserved.
set(Mips::GP_64);
188 for (RegIter
Reg = Mips::AFGR64RegClass.
begin(),
189 EReg = Mips::AFGR64RegClass.
end();
Reg != EReg; ++
Reg)
193 for (RegIter
Reg = Mips::FGR64RegClass.
begin(),
194 EReg = Mips::FGR64RegClass.
end();
Reg != EReg; ++
Reg)
200 Reserved.
set(Mips::S0);
202 Reserved.
set(Mips::FP);
203 Reserved.
set(Mips::FP_64);
208 if (needsStackRealignment(MF) &&
210 Reserved.
set(Mips::S7);
211 Reserved.
set(Mips::S7_64);
217 Reserved.
set(Mips::HWR29);
220 Reserved.
set(Mips::DSPPos);
221 Reserved.
set(Mips::DSPSCount);
222 Reserved.
set(Mips::DSPCarry);
223 Reserved.
set(Mips::DSPEFI);
224 Reserved.
set(Mips::DSPOutFlag);
227 Reserved.
set(Mips::MSAIR);
228 Reserved.
set(Mips::MSACSR);
229 Reserved.
set(Mips::MSAAccess);
230 Reserved.
set(Mips::MSASave);
231 Reserved.
set(Mips::MSAModify);
232 Reserved.
set(Mips::MSARequest);
233 Reserved.
set(Mips::MSAMap);
234 Reserved.
set(Mips::MSAUnmap);
239 Reserved.
set(Mips::RA);
240 Reserved.
set(Mips::RA_64);
241 Reserved.
set(Mips::T0);
244 Reserved.
set(Mips::S2);
249 Reserved.
set(Mips::GP);
250 Reserved.
set(Mips::GP_64);
254 for (
const auto &
Reg : Mips::OddSPRegClass)
281 errs() <<
"<--------->\n" <<
MI);
287 DEBUG(
errs() <<
"FrameIndex : " << FrameIndex <<
"\n"
288 <<
"spOffset : " << spOffset <<
"\n"
289 <<
"stackSize : " << stackSize <<
"\n");
291 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
302 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
304 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
305 (IsN64 ? Mips::SP_64 : Mips::SP);
320 unsigned FP = Subtarget.
isGP32bit() ? Mips::FP : Mips::FP_64;
321 unsigned BP = Subtarget.
isGP32bit() ? Mips::S7 : Mips::S7_64;
const MCPhysReg * const_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const_iterator end(StringRef path)
Get end iterator over path.
bool ArePtrs64bit() const
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
The subset of registers permitted in certain microMIPS instructions such as lw16. ...
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
unsigned getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
const_iterator begin(StringRef path)
Get begin iterator over path.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
bool canReserveReg(unsigned PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register...
Reg
All possible values of the reg field in the ModR/M byte.
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetFrameLowering * getFrameLowering() const override
const MachineBasicBlock * getParent() const
friend const_iterator end(StringRef path)
Get end iterator over path.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind) const override
Code Generation virtual methods...
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
The default register class for integer values.
bool inMips16Mode() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required, we reserve argument space for call sites in the function immediately on entry to the current function.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
virtual const TargetFrameLowering * getFrameLowering() const
bool isTargetNaCl() const
static unsigned getPICCallReg()
Get PIC indirect call register.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Mips Callee Saved Registers.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Information about stack frame layout on the target.
bool hasStandardEncoding() const
Representation of each machine instruction.
static const uint32_t * getMips16RetHelperMask()
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool isSingleFloat() const
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool useSmallSection() const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Stack Frame Processing Methods.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool canRealignStack(const MachineFunction &MF) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override