LLVM  4.0.0
TargetPassConfig.h
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1 //===-- TargetPassConfig.h - Code Generation pass options -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// Target-Independent Code Generator Pass Configuration Options pass.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_TARGETPASSCONFIG_H
15 #define LLVM_CODEGEN_TARGETPASSCONFIG_H
16 
17 #include "llvm/Pass.h"
18 #include "llvm/Support/CodeGen.h"
19 #include <string>
20 
21 namespace llvm {
22 
23 class PassConfigImpl;
24 class ScheduleDAGInstrs;
25 class TargetMachine;
26 struct MachineSchedContext;
27 
28 // The old pass manager infrastructure is hidden in a legacy namespace now.
29 namespace legacy {
30 class PassManagerBase;
31 }
33 
34 /// Discriminated union of Pass ID types.
35 ///
36 /// The PassConfig API prefers dealing with IDs because they are safer and more
37 /// efficient. IDs decouple configuration from instantiation. This way, when a
38 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
39 /// refer to a Pass pointer after adding it to a pass manager, which deletes
40 /// redundant pass instances.
41 ///
42 /// However, it is convient to directly instantiate target passes with
43 /// non-default ctors. These often don't have a registered PassInfo. Rather than
44 /// force all target passes to implement the pass registry boilerplate, allow
45 /// the PassConfig API to handle either type.
46 ///
47 /// AnalysisID is sadly char*, so PointerIntPair won't work.
49  union {
51  Pass *P;
52  };
53  bool IsInstance;
54 public:
55  IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
56  IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
57  IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
58 
59  bool isValid() const { return P; }
60  bool isInstance() const { return IsInstance; }
61 
62  AnalysisID getID() const {
63  assert(!IsInstance && "Not a Pass ID");
64  return ID;
65  }
66  Pass *getInstance() const {
67  assert(IsInstance && "Not a Pass Instance");
68  return P;
69  }
70 };
71 
72 template <> struct isPodLike<IdentifyingPassPtr> {
73  static const bool value = true;
74 };
75 
76 /// Target-Independent Code Generator Pass Configuration Options.
77 ///
78 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
79 /// to the internals of other CodeGen passes.
81 public:
82  /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
83  /// are unregistered pass IDs. They are only useful for use with
84  /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
85  ///
86 
87  /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
88  /// during codegen, on SSA form.
89  static char EarlyTailDuplicateID;
90 
91  /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
92  /// optimization after regalloc.
93  static char PostRAMachineLICMID;
94 
95 private:
96  PassManagerBase *PM;
97  AnalysisID StartBefore = nullptr;
98  AnalysisID StartAfter = nullptr;
99  AnalysisID StopBefore = nullptr;
100  AnalysisID StopAfter = nullptr;
101  bool Started;
102  bool Stopped;
103  bool AddingMachinePasses;
104 
105 protected:
107  PassConfigImpl *Impl; // Internal data structures
108  bool Initialized; // Flagged after all passes are configured.
109 
110  // Target Pass Options
111  // Targets provide a default setting, user flags override.
112  //
114 
115  /// Default setting for -enable-tail-merge on this target.
117 
118 public:
119  TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
120  // Dummy constructor.
122 
123  ~TargetPassConfig() override;
124 
125  static char ID;
126 
127  /// Get the right type of TargetMachine for this target.
128  template<typename TMC> TMC &getTM() const {
129  return *static_cast<TMC*>(TM);
130  }
131 
132  //
133  void setInitialized() { Initialized = true; }
134 
136 
137  /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
138  /// a portion of the normal code-gen pass sequence.
139  ///
140  /// If the StartAfter and StartBefore pass ID is zero, then compilation will
141  /// begin at the normal point; otherwise, clear the Started flag to indicate
142  /// that passes should not be added until the starting pass is seen. If the
143  /// Stop pass ID is zero, then compilation will continue to the end.
144  ///
145  /// This function expects that at least one of the StartAfter or the
146  /// StartBefore pass IDs is null.
147  void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter,
148  AnalysisID StopBefore, AnalysisID StopAfter) {
149  assert(!(StartBefore && StartAfter) &&
150  "Start after and start before passes are given");
151  assert(!(StopBefore && StopAfter) &&
152  "Stop after and stop before passed are given");
153  this->StartBefore = StartBefore;
154  this->StartAfter = StartAfter;
155  this->StopBefore = StopBefore;
156  this->StopAfter = StopAfter;
157  Started = (StartAfter == nullptr) && (StartBefore == nullptr);
158  }
159 
160  void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
161 
162  bool getEnableTailMerge() const { return EnableTailMerge; }
163  void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
164 
165  /// Allow the target to override a specific pass without overriding the pass
166  /// pipeline. When passes are added to the standard pipeline at the
167  /// point where StandardID is expected, add TargetID in its place.
168  void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
169 
170  /// Insert InsertedPassID pass after TargetPassID pass.
171  void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
172  bool VerifyAfter = true, bool PrintAfter = true);
173 
174  /// Allow the target to enable a specific standard pass by default.
175  void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
176 
177  /// Allow the target to disable a specific standard pass by default.
178  void disablePass(AnalysisID PassID) {
180  }
181 
182  /// Return the pass substituted for StandardID by the target.
183  /// If no substitution exists, return StandardID.
185 
186  /// Return true if the pass has been substituted by the target or
187  /// overridden on the command line.
189 
190  /// Return true if the optimized regalloc pipeline is enabled.
191  bool getOptimizeRegAlloc() const;
192 
193  /// Return true if shrink wrapping is enabled.
194  bool getEnableShrinkWrap() const;
195 
196  /// Return true if the default global register allocator is in use and
197  /// has not be overriden on the command line with '-regalloc=...'
198  bool usingDefaultRegAlloc() const;
199 
200  /// Add common target configurable passes that perform LLVM IR to IR
201  /// transforms following machine independent optimization.
202  virtual void addIRPasses();
203 
204  /// Add passes to lower exception handling for the code generator.
206 
207  /// Add pass to prepare the LLVM IR for code generation. This should be done
208  /// before exception handling preparation passes.
209  virtual void addCodeGenPrepare();
210 
211  /// Add common passes that perform LLVM IR to IR transforms in preparation for
212  /// instruction selection.
213  virtual void addISelPrepare();
214 
215  /// addInstSelector - This method should install an instruction selector pass,
216  /// which converts from LLVM code to machine instructions.
217  virtual bool addInstSelector() {
218  return true;
219  }
220 
221  /// This method should install an IR translator pass, which converts from
222  /// LLVM code to machine instructions with possibly generic opcodes.
223  virtual bool addIRTranslator() { return true; }
224 
225  /// This method may be implemented by targets that want to run passes
226  /// immediately before legalization.
227  virtual void addPreLegalizeMachineIR() {}
228 
229  /// This method should install a legalize pass, which converts the instruction
230  /// sequence into one that can be selected by the target.
231  virtual bool addLegalizeMachineIR() { return true; }
232 
233  /// This method may be implemented by targets that want to run passes
234  /// immediately before the register bank selection.
235  virtual void addPreRegBankSelect() {}
236 
237  /// This method should install a register bank selector pass, which
238  /// assigns register banks to virtual registers without a register
239  /// class or register banks.
240  virtual bool addRegBankSelect() { return true; }
241 
242  /// This method may be implemented by targets that want to run passes
243  /// immediately before the (global) instruction selection.
245 
246  /// This method should install a (global) instruction selector pass, which
247  /// converts possibly generic instructions to fully target-specific
248  /// instructions, thereby constraining all generic virtual registers to
249  /// register classes.
250  virtual bool addGlobalInstructionSelect() { return true; }
251 
252  /// Add the complete, standard set of LLVM CodeGen passes.
253  /// Fully developed targets will not generally override this.
254  virtual void addMachinePasses();
255 
256  /// Create an instance of ScheduleDAGInstrs to be run within the standard
257  /// MachineScheduler pass for this function and target at the current
258  /// optimization level.
259  ///
260  /// This can also be used to plug a new MachineSchedStrategy into an instance
261  /// of the standard ScheduleDAGMI:
262  /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /*RemoveKillFlags=*/false)
263  ///
264  /// Return NULL to select the default (generic) machine scheduler.
265  virtual ScheduleDAGInstrs *
266  createMachineScheduler(MachineSchedContext *C) const {
267  return nullptr;
268  }
269 
270  /// Similar to createMachineScheduler but used when postRA machine scheduling
271  /// is enabled.
272  virtual ScheduleDAGInstrs *
274  return nullptr;
275  }
276 
277  /// printAndVerify - Add a pass to dump then verify the machine function, if
278  /// those steps are enabled.
279  ///
280  void printAndVerify(const std::string &Banner);
281 
282  /// Add a pass to print the machine function if printing is enabled.
283  void addPrintPass(const std::string &Banner);
284 
285  /// Add a pass to perform basic verification of the machine function if
286  /// verification is enabled.
287  void addVerifyPass(const std::string &Banner);
288 
289  /// Check whether or not GlobalISel should abort on error.
290  /// When this is disable, GlobalISel will fall back on SDISel instead of
291  /// erroring out.
292  virtual bool isGlobalISelAbortEnabled() const;
293 
294  /// Check whether or not a diagnostic should be emitted when GlobalISel
295  /// uses the fallback path. In other words, it will emit a diagnostic
296  /// when GlobalISel failed and isGlobalISelAbortEnabled is false.
297  virtual bool reportDiagnosticWhenGlobalISelFallback() const;
298 
299 protected:
300  // Helper to verify the analysis is really immutable.
301  void setOpt(bool &Opt, bool Val);
302 
303  /// Methods with trivial inline returns are convenient points in the common
304  /// codegen pass pipeline where targets may insert passes. Methods with
305  /// out-of-line standard implementations are major CodeGen stages called by
306  /// addMachinePasses. Some targets may override major stages when inserting
307  /// passes is insufficient, but maintaining overriden stages is more work.
308  ///
309 
310  /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
311  /// passes (which are run just before instruction selector).
312  virtual bool addPreISel() {
313  return true;
314  }
315 
316  /// addMachineSSAOptimization - Add standard passes that optimize machine
317  /// instructions in SSA form.
318  virtual void addMachineSSAOptimization();
319 
320  /// Add passes that optimize instruction level parallelism for out-of-order
321  /// targets. These passes are run while the machine code is still in SSA
322  /// form, so they can use MachineTraceMetrics to control their heuristics.
323  ///
324  /// All passes added here should preserve the MachineDominatorTree,
325  /// MachineLoopInfo, and MachineTraceMetrics analyses.
326  virtual bool addILPOpts() {
327  return false;
328  }
329 
330  /// This method may be implemented by targets that want to run passes
331  /// immediately before register allocation.
332  virtual void addPreRegAlloc() { }
333 
334  /// createTargetRegisterAllocator - Create the register allocator pass for
335  /// this target at the current optimization level.
336  virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
337 
338  /// addFastRegAlloc - Add the minimum set of target-independent passes that
339  /// are required for fast register allocation.
340  virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
341 
342  /// addOptimizedRegAlloc - Add passes related to register allocation.
343  /// LLVMTargetMachine provides standard regalloc passes for most targets.
344  virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
345 
346  /// addPreRewrite - Add passes to the optimized register allocation pipeline
347  /// after register allocation is complete, but before virtual registers are
348  /// rewritten to physical registers.
349  ///
350  /// These passes must preserve VirtRegMap and LiveIntervals, and when running
351  /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
352  /// When these passes run, VirtRegMap contains legal physreg assignments for
353  /// all virtual registers.
354  virtual bool addPreRewrite() {
355  return false;
356  }
357 
358  /// This method may be implemented by targets that want to run passes after
359  /// register allocation pass pipeline but before prolog-epilog insertion.
360  virtual void addPostRegAlloc() { }
361 
362  /// Add passes that optimize machine instructions after register allocation.
363  virtual void addMachineLateOptimization();
364 
365  /// This method may be implemented by targets that want to run passes after
366  /// prolog-epilog insertion and before the second instruction scheduling pass.
367  virtual void addPreSched2() { }
368 
369  /// addGCPasses - Add late codegen passes that analyze code for garbage
370  /// collection. This should return true if GC info should be printed after
371  /// these passes.
372  virtual bool addGCPasses();
373 
374  /// Add standard basic block placement passes.
375  virtual void addBlockPlacement();
376 
377  /// This pass may be implemented by targets that want to run passes
378  /// immediately before machine code is emitted.
379  virtual void addPreEmitPass() { }
380 
381  /// Utilities for targets to add passes to the pass manager.
382  ///
383 
384  /// Add a CodeGen pass at this point in the pipeline after checking overrides.
385  /// Return the pass that was added, or zero if no pass was added.
386  /// @p printAfter if true and adding a machine function pass add an extra
387  /// machine printer pass afterwards
388  /// @p verifyAfter if true and adding a machine function pass add an extra
389  /// machine verification pass afterwards.
390  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
391  bool printAfter = true);
392 
393  /// Add a pass to the PassManager if that pass is supposed to be run, as
394  /// determined by the StartAfter and StopAfter options. Takes ownership of the
395  /// pass.
396  /// @p printAfter if true and adding a machine function pass add an extra
397  /// machine printer pass afterwards
398  /// @p verifyAfter if true and adding a machine function pass add an extra
399  /// machine verification pass afterwards.
400  void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
401 
402  /// addMachinePasses helper to create the target-selected or overriden
403  /// regalloc pass.
404  FunctionPass *createRegAllocPass(bool Optimized);
405 };
406 
407 } // end namespace llvm
408 
409 #endif
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:81
void enablePass(AnalysisID PassID)
Allow the target to enable a specific standard pass by default.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
void setDisableVerify(bool Disable)
virtual bool addPreRewrite()
addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is...
bool getEnableShrinkWrap() const
Return true if shrink wrapping is enabled.
static const bool value
Definition: type_traits.h:48
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Pass * getInstance() const
CodeGenOpt::Level getOptLevel() const
TMC & getTM() const
Get the right type of TargetMachine for this target.
virtual bool addLegalizeMachineIR()
This method should install a legalize pass, which converts the instruction sequence into one that can...
bool getOptimizeRegAlloc() const
Return true if the optimized regalloc pipeline is enabled.
IdentifyingPassPtr(Pass *InstancePtr)
virtual void addPreSched2()
This method may be implemented by targets that want to run passes after prolog-epilog insertion and b...
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
FunctionPass * createRegAllocPass(bool Optimized)
addMachinePasses helper to create the target-selected or overriden regalloc pass. ...
Target-Independent Code Generator Pass Configuration Options.
virtual void addMachinePasses()
Add the complete, standard set of LLVM CodeGen passes.
void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter, AnalysisID StopBefore, AnalysisID StopAfter)
Set the StartAfter, StartBefore and StopAfter passes to allow running only a portion of the normal co...
IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const
Return the pass substituted for StandardID by the target.
virtual bool reportDiagnosticWhenGlobalISelFallback() const
Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path...
virtual void addPreLegalizeMachineIR()
This method may be implemented by targets that want to run passes immediately before legalization...
Function Alias Analysis false
virtual void addPreRegAlloc()
This method may be implemented by targets that want to run passes immediately before register allocat...
void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID)
Allow the target to override a specific pass without overriding the pass pipeline.
virtual bool addILPOpts()
Add passes that optimize instruction level parallelism for out-of-order targets.
virtual FunctionPass * createTargetRegisterAllocator(bool Optimized)
createTargetRegisterAllocator - Create the register allocator pass for this target at the current opt...
virtual bool addGCPasses()
addGCPasses - Add late codegen passes that analyze code for garbage collection.
static PassOptionList PrintAfter("print-after", llvm::cl::desc("Print IR after specified passes"), cl::Hidden)
#define P(N)
static char PostRAMachineLICMID
PostRAMachineLICM - A clone of the LICM pass that runs during late machine optimization after regallo...
void printAndVerify(const std::string &Banner)
printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled...
void disablePass(AnalysisID PassID)
Allow the target to disable a specific standard pass by default.
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass)
addOptimizedRegAlloc - Add passes related to register allocation.
void setEnableTailMerge(bool Enable)
virtual void addMachineLateOptimization()
Add passes that optimize machine instructions after register allocation.
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
bool isPassSubstitutedOrOverridden(AnalysisID ID) const
Return true if the pass has been substituted by the target or overridden on the command line...
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
bool getEnableTailMerge() const
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, bool VerifyAfter=true, bool PrintAfter=true)
Insert InsertedPassID pass after TargetPassID pass.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection...
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
void pm(uint64_t &Value)
Adjusts a program memory address.
void addPrintPass(const std::string &Banner)
Add a pass to print the machine function if printing is enabled.
void addPassesToHandleExceptions()
Add passes to lower exception handling for the code generator.
virtual void addPreRegBankSelect()
This method may be implemented by targets that want to run passes immediately before the register ban...
isPodLike - This is a type trait that is used to determine whether a given type can be copied around ...
Definition: ArrayRef.h:507
ImmutablePass class - This class is used to provide information that does not need to be run...
Definition: Pass.h:266
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
virtual bool addGlobalInstructionSelect()
This method should install a (global) instruction selector pass, which converts possibly generic inst...
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
Discriminated union of Pass ID types.
virtual bool addRegBankSelect()
This method should install a register bank selector pass, which assigns register banks to virtual reg...
virtual void addFastRegAlloc(FunctionPass *RegAllocPass)
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs. ...
Basic Alias true
virtual void addPreGlobalInstructionSelect()
This method may be implemented by targets that want to run passes immediately before the (global) ins...
AnalysisID addPass(AnalysisID PassID, bool verifyAfter=true, bool printAfter=true)
Utilities for targets to add passes to the pass manager.
virtual void addBlockPlacement()
Add standard basic block placement passes.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
AnalysisID getID() const
void setOpt(bool &Opt, bool Val)
const void * AnalysisID
Definition: Pass.h:46
void addVerifyPass(const std::string &Banner)
Add a pass to perform basic verification of the machine function if verification is enabled...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static char EarlyTailDuplicateID
Pseudo Pass IDs.
IdentifyingPassPtr(AnalysisID IDPtr)
Primary interface to the complete machine description for the target machine.
bool usingDefaultRegAlloc() const
Return true if the default global register allocator is in use and has not be overriden on the comman...
virtual bool addIRTranslator()
This method should install an IR translator pass, which converts from LLVM code to machine instructio...
bool EnableTailMerge
Default setting for -enable-tail-merge on this target.