23 #define DEBUG_TYPE "processimplicitdefs"
55 "Process Implicit Definitions",
false,
false)
59 void ProcessImplicitDefs::getAnalysisUsage(
AnalysisUsage &AU)
const {
65 bool ProcessImplicitDefs::canTurnIntoImplicitDef(
MachineInstr *
MI) {
72 if (MO.isReg() && MO.isUse() && MO.readsReg())
77 void ProcessImplicitDefs::processImplicitDef(
MachineInstr *MI) {
87 if (!canTurnIntoImplicitDef(UserMI))
89 DEBUG(
dbgs() <<
"Converting to IMPLICIT_DEF: " << *UserMI);
90 UserMI->
setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
91 WorkList.insert(UserMI);
102 for (++UserMI; UserMI != UserE; ++UserMI) {
106 unsigned UserReg = MO.getReg();
108 !TRI->regsOverlap(Reg, UserReg))
121 DEBUG(
dbgs() <<
"Physreg user: " << *UserMI);
130 DEBUG(
dbgs() <<
"Keeping physreg: " << *MI);
137 DEBUG(
dbgs() <<
"********** PROCESS IMPLICIT DEFS **********\n"
138 <<
"********** Function: " << MF.
getName() <<
'\n');
140 bool Changed =
false;
145 assert(
MRI->isSSA() &&
"ProcessImplicitDefs only works on SSA form.");
146 assert(WorkList.empty() &&
"Inconsistent worklist state");
152 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
153 if (MBBI->isImplicitDef())
154 WorkList.insert(&*MBBI);
156 if (WorkList.empty())
159 DEBUG(
dbgs() <<
"BB#" << MFI->getNumber() <<
" has " << WorkList.size()
160 <<
" implicit defs.\n");
164 do processImplicitDef(WorkList.pop_back_val());
165 while (!WorkList.empty());
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_end()
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
iterator_range< mop_iterator > operands()
INITIALIZE_PASS_BEGIN(ProcessImplicitDefs,"processimpdefs","Process Implicit Definitions", false, false) INITIALIZE_PASS_END(ProcessImplicitDefs
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Process Implicit Definitions
bool isCopyLike() const
Return true if the instruction behaves like a copy.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isInsertSubreg() const
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
void initializeProcessImplicitDefsPass(PassRegistry &)
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
self_iterator getIterator()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A SetVector that performs no allocations if smaller than a certain size.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
A collection of legacy interfaces for querying information about the current executing process...
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
bool isRegSequence() const