30 #define DEBUG_TYPE "r600mergeclause"
37 case AMDGPU::CF_ALU_PUSH_BEFORE:
57 void cleanPotentialDisabledCFAlu(
MachineInstr &CFAlu)
const;
74 unsigned R600ClauseMergePass::getCFAluSize(
const MachineInstr &MI)
const {
81 bool R600ClauseMergePass::isCFAluEnabled(
const MachineInstr &MI)
const {
88 void R600ClauseMergePass::cleanPotentialDisabledCFAlu(
90 int CntIdx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
94 while (I != E && !isCFAlu(*I))
99 if (isCFAluEnabled(MI))
106 bool R600ClauseMergePass::mergeIfPossible(
MachineInstr &RootCFAlu,
108 assert(isCFAlu(RootCFAlu) && isCFAlu(LatrCFAlu));
109 int CntIdx =
TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT);
110 unsigned RootInstCount = getCFAluSize(RootCFAlu),
111 LaterInstCount = getCFAluSize(LatrCFAlu);
112 unsigned CumuledInsts = RootInstCount + LaterInstCount;
113 if (CumuledInsts >=
TII->getMaxAlusPerClause()) {
117 if (RootCFAlu.
getOpcode() == AMDGPU::CF_ALU_PUSH_BEFORE)
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0);
123 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0);
125 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0);
137 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1);
139 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK1);
141 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR1);
186 if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) ||
191 cleanPotentialDisabledCFAlu(MI);
193 if (LatestCFAlu !=
E && mergeIfPossible(*LatestCFAlu, MI)) {
204 StringRef R600ClauseMergePass::getPassName()
const {
205 return "R600 Merge Clause Markers Pass";
212 return new R600ClauseMergePass(TM);
AMDGPU specific subclass of TargetSubtarget.
Interface definition for R600InstrInfo.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
Interface definition for R600RegisterInfo.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
FunctionPass * createR600ClauseMergePass(TargetMachine &tm)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
const MachineOperand & getOperand(unsigned i) const
const R600InstrInfo * getInstrInfo() const override
void setImm(int64_t immVal)
FunctionPass class - This class is used to implement most global optimizations.
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
StringRef - Represent a constant reference to a string, i.e.