LLVM  4.0.0
PPCInstrInfo.h
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1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
16 
17 #include "PPC.h"
18 #include "PPCRegisterInfo.h"
20 
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
23 
24 namespace llvm {
25 
26 /// PPCII - This namespace holds all of the PowerPC target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// PPC.td and PPCInstrFormats.td.
29 namespace PPCII {
30 enum {
31  // PPC970 Instruction Flags. These flags describe the characteristics of the
32  // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33  // raw machine instructions.
34 
35  /// PPC970_First - This instruction starts a new dispatch group, so it will
36  /// always be the first one in the group.
37  PPC970_First = 0x1,
38 
39  /// PPC970_Single - This instruction starts a new dispatch group and
40  /// terminates it, so it will be the sole instruction in the group.
42 
43  /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44  /// two dispatch pipes to be available to issue.
46 
47  /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48  /// an instruction is issued to.
51 };
53  /// These are the various PPC970 execution unit pipelines. Each instruction
54  /// is one of these.
55  PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
56  PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
57  PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
58  PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
59  PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
60  PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
61  PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
62  PPC970_BRU = 7 << PPC970_Shift // Branch Unit
63 };
64 
65 enum {
66  /// Shift count to bypass PPC970 flags
68 
69  /// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX
70  /// register (v0-v31).
72 };
73 } // end namespace PPCII
74 
75 class PPCSubtarget;
76 class PPCInstrInfo : public PPCGenInstrInfo {
77  PPCSubtarget &Subtarget;
78  const PPCRegisterInfo RI;
79 
80  bool StoreRegToStackSlot(MachineFunction &MF,
81  unsigned SrcReg, bool isKill, int FrameIdx,
82  const TargetRegisterClass *RC,
84  bool &NonRI, bool &SpillsVRS) const;
85  bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
86  unsigned DestReg, int FrameIdx,
87  const TargetRegisterClass *RC,
89  bool &NonRI, bool &SpillsVRS) const;
90  virtual void anchor();
91 
92 protected:
93  /// Commutes the operands in the given instruction.
94  /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
95  ///
96  /// Do not call this method for a non-commutable instruction or for
97  /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
98  /// Even though the instruction is commutable, the method may still
99  /// fail to commute the operands, null pointer is returned in such cases.
100  ///
101  /// For example, we can commute rlwimi instructions, but only if the
102  /// rotate amt is zero. We also have to munge the immediates a bit.
104  unsigned OpIdx1,
105  unsigned OpIdx2) const override;
106 
107 public:
108  explicit PPCInstrInfo(PPCSubtarget &STI);
109 
110  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
111  /// such, whenever a client has an instance of instruction info, it should
112  /// always be able to get register info as well (through this method).
113  ///
114  const PPCRegisterInfo &getRegisterInfo() const { return RI; }
115 
118  const ScheduleDAG *DAG) const override;
121  const ScheduleDAG *DAG) const override;
122 
123  unsigned getInstrLatency(const InstrItineraryData *ItinData,
124  const MachineInstr &MI,
125  unsigned *PredCost = nullptr) const override;
126 
127  int getOperandLatency(const InstrItineraryData *ItinData,
128  const MachineInstr &DefMI, unsigned DefIdx,
129  const MachineInstr &UseMI,
130  unsigned UseIdx) const override;
132  SDNode *DefNode, unsigned DefIdx,
133  SDNode *UseNode, unsigned UseIdx) const override {
134  return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
135  UseNode, UseIdx);
136  }
137 
138  bool hasLowDefLatency(const TargetSchedModel &SchedModel,
139  const MachineInstr &DefMI,
140  unsigned DefIdx) const override {
141  // Machine LICM should hoist all instructions in low-register-pressure
142  // situations; none are sufficiently free to justify leaving in a loop
143  // body.
144  return false;
145  }
146 
147  bool useMachineCombiner() const override {
148  return true;
149  }
150 
151  /// Return true when there is potentially a faster code sequence
152  /// for an instruction chain ending in <Root>. All potential patterns are
153  /// output in the <Pattern> array.
155  MachineInstr &Root,
157 
158  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
159 
160  bool isCoalescableExtInstr(const MachineInstr &MI,
161  unsigned &SrcReg, unsigned &DstReg,
162  unsigned &SubIdx) const override;
163  unsigned isLoadFromStackSlot(const MachineInstr &MI,
164  int &FrameIndex) const override;
165  unsigned isStoreToStackSlot(const MachineInstr &MI,
166  int &FrameIndex) const override;
167 
168  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
169  unsigned &SrcOpIdx2) const override;
170 
172  MachineBasicBlock::iterator MI) const override;
173 
174 
175  // Branch analysis.
177  MachineBasicBlock *&FBB,
179  bool AllowModify) const override;
181  int *BytesRemoved = nullptr) const override;
184  const DebugLoc &DL,
185  int *BytesAdded = nullptr) const override;
186 
187  // Select analysis.
189  unsigned, unsigned, int &, int &, int &) const override;
191  const DebugLoc &DL, unsigned DstReg,
192  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
193  unsigned FalseReg) const override;
194 
196  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
197  bool KillSrc) const override;
198 
201  unsigned SrcReg, bool isKill, int FrameIndex,
202  const TargetRegisterClass *RC,
203  const TargetRegisterInfo *TRI) const override;
204 
207  unsigned DestReg, int FrameIndex,
208  const TargetRegisterClass *RC,
209  const TargetRegisterInfo *TRI) const override;
210 
211  bool
213 
214  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
215  MachineRegisterInfo *MRI) const override;
216 
217  // If conversion by predication (only supported by some branch instructions).
218  // All of the profitability checks always return true; it is always
219  // profitable to use the predicated branches.
221  unsigned NumCycles, unsigned ExtraPredCycles,
222  BranchProbability Probability) const override {
223  return true;
224  }
225 
227  unsigned NumT, unsigned ExtraT,
228  MachineBasicBlock &FMBB,
229  unsigned NumF, unsigned ExtraF,
230  BranchProbability Probability) const override;
231 
233  BranchProbability Probability) const override {
234  return true;
235  }
236 
238  MachineBasicBlock &FMBB) const override {
239  return false;
240  }
241 
242  // Predication support.
243  bool isPredicated(const MachineInstr &MI) const override;
244 
245  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
246 
248  ArrayRef<MachineOperand> Pred) const override;
249 
251  ArrayRef<MachineOperand> Pred2) const override;
252 
254  std::vector<MachineOperand> &Pred) const override;
255 
256  bool isPredicable(MachineInstr &MI) const override;
257 
258  // Comparison optimization.
259 
260  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
261  unsigned &SrcReg2, int &Mask, int &Value) const override;
262 
263  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
264  unsigned SrcReg2, int Mask, int Value,
265  const MachineRegisterInfo *MRI) const override;
266 
267  /// GetInstSize - Return the number of bytes of code the specified
268  /// instruction may be. This returns the maximum number of bytes.
269  ///
270  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
271 
272  void getNoopForMachoTarget(MCInst &NopInst) const override;
273 
274  std::pair<unsigned, unsigned>
275  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
276 
279 
282 
283  // Lower pseudo instructions after register allocation.
284  bool expandPostRAPseudo(MachineInstr &MI) const override;
285 
286  static bool isVFRegister(unsigned Reg) {
287  return Reg >= PPC::VF0 && Reg <= PPC::VF31;
288  }
289  static bool isVRRegister(unsigned Reg) {
290  return Reg >= PPC::V0 && Reg <= PPC::V31;
291  }
292  const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
293 };
294 
295 }
296 
297 #endif
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
bool useMachineCombiner() const override
Definition: PPCInstrInfo.h:147
PPC970_First - This instruction starts a new dispatch group, so it will always be the first one in th...
Definition: PPCInstrInfo.h:37
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
These are the various PPC970 execution unit pipelines.
Definition: PPCInstrInfo.h:55
A debug info location.
Definition: DebugLoc.h:34
bool isPredicable(MachineInstr &MI) const override
ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override
CreateTargetHazardRecognizer - Return the hazard recognizer to use for this target when scheduling th...
static bool isVRRegister(unsigned Reg)
Definition: PPCInstrInfo.h:289
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: PPCInstrInfo.h:237
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
Provide an instruction scheduling machine model to CodeGen passes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
Shift count to bypass PPC970 flags.
Definition: PPCInstrInfo.h:67
Reg
All possible values of the reg field in the ModR/M byte.
PPCInstrInfo(PPCSubtarget &STI)
MachineBasicBlock * MBB
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
Itinerary data supplied by a subtarget to be used by a target.
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
#define P(N)
unsigned const MachineRegisterInfo * MRI
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
The VSX instruction that uses VSX register (vs0-vs63), instead of VMX register (v0-v31).
Definition: PPCInstrInfo.h:71
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
MachineInstrBuilder & UseMI
const TargetRegisterClass * updatedRC(const TargetRegisterClass *RC) const
PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that an instruction is issued to...
Definition: PPCInstrInfo.h:49
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:232
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Commutes the operands in the given instruction.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
PPC970_Single - This instruction starts a new dispatch group and terminates it, so it will be the sol...
Definition: PPCInstrInfo.h:41
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Represents one node in the SelectionDAG.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
void getNoopForMachoTarget(MCInst &NopInst) const override
getNoopForMachoTarget - Return the noop instruction to use for a noop.
static bool isVFRegister(unsigned Reg)
Definition: PPCInstrInfo.h:286
bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const override
Definition: PPCInstrInfo.h:138
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
const PPCRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: PPCInstrInfo.h:114
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &P) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in <Root...
bool isPredicated(const MachineInstr &MI) const override
Representation of each machine instruction.
Definition: MachineInstr.h:52
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override
int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override
Definition: PPCInstrInfo.h:131
#define I(x, y, z)
Definition: MD5.cpp:54
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
LLVM Value Representation.
Definition: Value.h:71
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer to use for this target when ...
IRTranslator LLVM IR MI
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
PPC970_Cracked - This instruction is cracked into two pieces, requiring two dispatch pipes to be avai...
Definition: PPCInstrInfo.h:45
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: PPCInstrInfo.h:220
bool expandPostRAPseudo(MachineInstr &MI) const override