42 #define DEBUG_TYPE "rename-independent-subregs"
52 return "Rename Disconnected Subregister Components";
74 : ConEQ(LIS), SR(&SR), Index(Index) {}
94 void computeMainRangesFixFlags(
const IntEqClasses &Classes,
116 "Rename Independent Subregisters",
false,
false)
122 bool RenameIndependentSubregs::renameComponents(
LiveInterval &LI)
const {
124 if (LI.valnos.size() < 2)
129 if (!findComponents(Classes, SubRangeInfos, LI))
133 unsigned Reg = LI.reg;
138 <<
" equivalence classes.\n");
140 for (
unsigned I = 1, NumClasses = Classes.
getNumClasses();
I < NumClasses;
142 unsigned NewVReg =
MRI->createVirtualRegister(RegClass);
143 LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
149 rewriteOperands(Classes, SubRangeInfos, Intervals);
150 distribute(Classes, SubRangeInfos, Intervals);
151 computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals);
155 bool RenameIndependentSubregs::findComponents(
IntEqClasses &Classes,
160 unsigned NumComponents = 0;
162 SubRangeInfos.
push_back(SubRangeInfo(*LIS, SR, NumComponents));
165 unsigned NumSubComponents = ConEQ.
Classify(SR);
166 NumComponents += NumSubComponents;
171 if (SubRangeInfos.
size() < 2)
177 Classes.
grow(NumComponents);
180 if (!MO.isDef() && !MO.readsReg())
182 unsigned SubRegIdx = MO.getSubReg();
184 unsigned MergedID = ~0u;
185 for (RenameIndependentSubregs::SubRangeInfo &SRInfo : SubRangeInfos) {
187 if ((SR.
LaneMask & LaneMask).none())
189 SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
190 Pos = MO.isDef() ? Pos.
getRegSlot(MO.isEarlyClobber())
197 unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
199 unsigned ID = LocalID + SRInfo.Index;
201 MergedID = MergedID == ~0u ? ID : Classes.
join(MergedID, ID);
208 return NumClasses > 1;
211 void RenameIndependentSubregs::rewriteOperands(
const IntEqClasses &Classes,
215 unsigned Reg = Intervals[0]->reg;;
217 E =
MRI->reg_nodbg_end();
I !=
E; ) {
229 for (
const SubRangeInfo &SRInfo : SubRangeInfos) {
231 if ((SR.
LaneMask & LaneMask).none())
238 unsigned LocalID = SRInfo.ConEQ.getEqClass(VNI);
240 ID = Classes[LocalID + SRInfo.Index];
244 unsigned VReg = Intervals[
ID]->reg;
259 for (
const SubRangeInfo &SRInfo : SubRangeInfos) {
265 SubRanges.
resize(NumClasses-1,
nullptr);
266 for (
unsigned I = 0;
I < NumValNos; ++
I) {
268 unsigned LocalID = SRInfo.ConEQ.getEqClass(&VNI);
269 unsigned ID = Classes[LocalID + SRInfo.Index];
271 if (ID > 0 && SubRanges[ID-1] ==
nullptr)
272 SubRanges[ID-1] = Intervals[
ID]->createSubRange(Allocator, SR.
LaneMask);
286 void RenameIndependentSubregs::computeMainRangesFixFlags(
291 const SlotIndexes &Indexes = *LIS->getSlotIndexes();
292 for (
size_t I = 0,
E = Intervals.
size();
I <
E; ++
I) {
294 unsigned Reg = LI.
reg;
322 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef);
355 LIS->constructMainRangeFromSubranges(LI);
360 LIS->shrinkToUses(&LI);
364 bool RenameIndependentSubregs::runOnMachineFunction(
MachineFunction &MF) {
367 if (!
MRI->subRegLivenessEnabled())
370 DEBUG(
dbgs() <<
"Renaming independent subregister live ranges in "
373 LIS = &getAnalysis<LiveIntervals>();
379 bool Changed =
false;
380 for (
size_t I = 0, E =
MRI->getNumVirtRegs();
I <
E; ++
I) {
382 if (!LIS->hasInterval(Reg))
388 Changed |= renameComponents(LI);
void push_back(const T &Elt)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
char & RenameIndependentSubregsID
This pass detects subregister lanes in a virtual register that are used independently of other lanes ...
rename independent subregs
void grow(unsigned N)
grow - Increase capacity to hold 0 .
SlotIndex def
The index of the defining instruction.
static unsigned index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
LiveInterval - This class represents the liveness of a register, or stack slot.
Describe properties that are true of each instruction in the target description file.
void setIsUndef(bool Val=true)
MachineBasicBlock::iterator findPHICopyInsertPoint(MachineBasicBlock *MBB, MachineBasicBlock *SuccMBB, unsigned SrcReg)
findPHICopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg when following the CFG...
void compress()
compress - Compress equivalence classes by numbering them 0 .
A live range for subregisters.
This represents a simple continuous liveness interval for a value.
void setIsDead(bool Val=true)
INITIALIZE_PASS_BEGIN(RenameIndependentSubregs,"rename-independent-subregs","Rename Independent Subregisters", false, false) INITIALIZE_PASS_END(RenameIndependentSubregs
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
void reserve(size_type N)
VNInfo - Value Number Information.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
rename independent Rename Independent Subregisters
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
iterator_range< subrange_iterator > subranges()
Reg
All possible values of the reg field in the ModR/M byte.
bool isUnused() const
Returns true if this value is unused.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
static void DistributeRange(LiveRangeT &LR, LiveRangeT *SplitLRs[], EqClassesT VNIClasses)
Helper function that distributes live range value numbers and the corresponding segments of a master ...
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
TargetInstrInfo - Interface to description of machine instruction set.
bool isEarlyClobber() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
IdxPair distribute(unsigned Nodes, unsigned Elements, unsigned Capacity, const unsigned *CurSize, unsigned NewSize[], unsigned Position, bool Grow)
IntervalMapImpl::distribute - Compute a new distribution of node elements after an overflow or underf...
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Allocate memory in an ever growing pool, as if by bump-pointer.
unsigned Classify(const LiveRange &LR)
Classify the values in LR into connected components.
Represent the analysis usage information of a pass.
Greedy Register Allocator
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
iterator_range< pred_iterator > predecessors()
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool liveAt(SlotIndex index) const
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
unsigned join(unsigned a, unsigned b)
Join the equivalence classes of a and b.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
pointer data()
Return a pointer to the vector's buffer, even if empty().
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void setReg(unsigned Reg)
Change the register this operand corresponds to.
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
static void rename(GlobalValue *GV)
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def...
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
virtual const TargetInstrInfo * getInstrInfo() const
static bool subRangeLiveAt(const LiveInterval &LI, SlotIndex Pos)
unsigned getNumClasses() const
getNumClasses - Return the number of equivalence classes after compress() was called.
rename independent Rename Independent false
StringRef - Represent a constant reference to a string, i.e.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register. ...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
SlotIndex - An opaque wrapper around machine indexes.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...