LLVM  4.0.0
RegAllocFast.cpp
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1 //===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This register allocator allocates registers to a basic block at a time,
11 // attempting to keep values in registers and reusing registers as appropriate.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/IndexedMap.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/SparseSet.h"
21 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/DebugInfo.h"
31 #include "llvm/Support/Debug.h"
35 #include <algorithm>
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "regalloc"
39 
40 STATISTIC(NumStores, "Number of stores added");
41 STATISTIC(NumLoads , "Number of loads added");
42 STATISTIC(NumCopies, "Number of copies coalesced");
43 
44 static RegisterRegAlloc
45  fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
46 
47 namespace {
48  class RAFast : public MachineFunctionPass {
49  public:
50  static char ID;
51  RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
52  isBulkSpilling(false) {}
53 
54  private:
55  MachineFunction *MF;
57  const TargetRegisterInfo *TRI;
58  const TargetInstrInfo *TII;
59  RegisterClassInfo RegClassInfo;
60 
61  // Basic block currently being allocated.
63 
64  // StackSlotForVirtReg - Maps virtual regs to the frame index where these
65  // values are spilled.
66  IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
67 
68  // Everything we know about a live virtual register.
69  struct LiveReg {
70  MachineInstr *LastUse; // Last instr to use reg.
71  unsigned VirtReg; // Virtual register number.
72  unsigned PhysReg; // Currently held here.
73  unsigned short LastOpNum; // OpNum on LastUse.
74  bool Dirty; // Register needs spill.
75 
76  explicit LiveReg(unsigned v)
77  : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
78 
79  unsigned getSparseSetIndex() const {
80  return TargetRegisterInfo::virtReg2Index(VirtReg);
81  }
82  };
83 
84  typedef SparseSet<LiveReg> LiveRegMap;
85 
86  // LiveVirtRegs - This map contains entries for each virtual register
87  // that is currently available in a physical register.
88  LiveRegMap LiveVirtRegs;
89 
91 
92  // RegState - Track the state of a physical register.
93  enum RegState {
94  // A disabled register is not available for allocation, but an alias may
95  // be in use. A register can only be moved out of the disabled state if
96  // all aliases are disabled.
97  regDisabled,
98 
99  // A free register is not currently in use and can be allocated
100  // immediately without checking aliases.
101  regFree,
102 
103  // A reserved register has been assigned explicitly (e.g., setting up a
104  // call parameter), and it remains reserved until it is used.
105  regReserved
106 
107  // A register state may also be a virtual register number, indication that
108  // the physical register is currently allocated to a virtual register. In
109  // that case, LiveVirtRegs contains the inverse mapping.
110  };
111 
112  // PhysRegState - One of the RegState enums, or a virtreg.
113  std::vector<unsigned> PhysRegState;
114 
115  // Set of register units.
116  typedef SparseSet<unsigned> UsedInInstrSet;
117 
118  // Set of register units that are used in the current instruction, and so
119  // cannot be allocated.
120  UsedInInstrSet UsedInInstr;
121 
122  // Mark a physreg as used in this instruction.
123  void markRegUsedInInstr(unsigned PhysReg) {
124  for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
125  UsedInInstr.insert(*Units);
126  }
127 
128  // Check if a physreg or any of its aliases are used in this instruction.
129  bool isRegUsedInInstr(unsigned PhysReg) const {
130  for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
131  if (UsedInInstr.count(*Units))
132  return true;
133  return false;
134  }
135 
136  // SkippedInstrs - Descriptors of instructions whose clobber list was
137  // ignored because all registers were spilled. It is still necessary to
138  // mark all the clobbered registers as used by the function.
140 
141  // isBulkSpilling - This flag is set when LiveRegMap will be cleared
142  // completely after spilling all live registers. LiveRegMap entries should
143  // not be erased.
144  bool isBulkSpilling;
145 
146  enum : unsigned {
147  spillClean = 1,
148  spillDirty = 100,
149  spillImpossible = ~0u
150  };
151  public:
152  StringRef getPassName() const override { return "Fast Register Allocator"; }
153 
154  void getAnalysisUsage(AnalysisUsage &AU) const override {
155  AU.setPreservesCFG();
157  }
158 
159  MachineFunctionProperties getRequiredProperties() const override {
162  }
163 
164  MachineFunctionProperties getSetProperties() const override {
167  }
168 
169  private:
170  bool runOnMachineFunction(MachineFunction &Fn) override;
171  void AllocateBasicBlock();
172  void handleThroughOperands(MachineInstr *MI,
173  SmallVectorImpl<unsigned> &VirtDead);
174  int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
175  bool isLastUseOfLocalReg(MachineOperand&);
176 
177  void addKillFlag(const LiveReg&);
178  void killVirtReg(LiveRegMap::iterator);
179  void killVirtReg(unsigned VirtReg);
180  void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
181  void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
182 
183  void usePhysReg(MachineOperand&);
184  void definePhysReg(MachineInstr &MI, unsigned PhysReg, RegState NewState);
185  unsigned calcSpillCost(unsigned PhysReg) const;
186  void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
187  LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
188  return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
189  }
190  LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
191  return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
192  }
193  LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
194  LiveRegMap::iterator allocVirtReg(MachineInstr &MI, LiveRegMap::iterator,
195  unsigned Hint);
196  LiveRegMap::iterator defineVirtReg(MachineInstr &MI, unsigned OpNum,
197  unsigned VirtReg, unsigned Hint);
198  LiveRegMap::iterator reloadVirtReg(MachineInstr &MI, unsigned OpNum,
199  unsigned VirtReg, unsigned Hint);
200  void spillAll(MachineBasicBlock::iterator MI);
201  bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
202  };
203  char RAFast::ID = 0;
204 }
205 
206 /// getStackSpaceFor - This allocates space for the specified virtual register
207 /// to be held on the stack.
208 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
209  // Find the location Reg would belong...
210  int SS = StackSlotForVirtReg[VirtReg];
211  if (SS != -1)
212  return SS; // Already has space allocated?
213 
214  // Allocate a new stack object for this spill location...
215  int FrameIdx = MF->getFrameInfo().CreateSpillStackObject(RC->getSize(),
216  RC->getAlignment());
217 
218  // Assign the slot.
219  StackSlotForVirtReg[VirtReg] = FrameIdx;
220  return FrameIdx;
221 }
222 
223 /// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
224 /// its virtual register, and it is guaranteed to be a block-local register.
225 ///
226 bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
227  // If the register has ever been spilled or reloaded, we conservatively assume
228  // it is a global register used in multiple blocks.
229  if (StackSlotForVirtReg[MO.getReg()] != -1)
230  return false;
231 
232  // Check that the use/def chain has exactly one operand - MO.
233  MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
234  if (&*I != &MO)
235  return false;
236  return ++I == MRI->reg_nodbg_end();
237 }
238 
239 /// addKillFlag - Set kill flags on last use of a virtual register.
240 void RAFast::addKillFlag(const LiveReg &LR) {
241  if (!LR.LastUse) return;
242  MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
243  if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
244  if (MO.getReg() == LR.PhysReg)
245  MO.setIsKill();
246  else
247  LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
248  }
249 }
250 
251 /// killVirtReg - Mark virtreg as no longer available.
252 void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
253  addKillFlag(*LRI);
254  assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
255  "Broken RegState mapping");
256  PhysRegState[LRI->PhysReg] = regFree;
257  // Erase from LiveVirtRegs unless we're spilling in bulk.
258  if (!isBulkSpilling)
259  LiveVirtRegs.erase(LRI);
260 }
261 
262 /// killVirtReg - Mark virtreg as no longer available.
263 void RAFast::killVirtReg(unsigned VirtReg) {
265  "killVirtReg needs a virtual register");
266  LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
267  if (LRI != LiveVirtRegs.end())
268  killVirtReg(LRI);
269 }
270 
271 /// spillVirtReg - This method spills the value specified by VirtReg into the
272 /// corresponding stack slot if needed.
273 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
275  "Spilling a physical register is illegal!");
276  LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
277  assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
278  spillVirtReg(MI, LRI);
279 }
280 
281 /// spillVirtReg - Do the actual work of spilling.
282 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
283  LiveRegMap::iterator LRI) {
284  LiveReg &LR = *LRI;
285  assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
286 
287  if (LR.Dirty) {
288  // If this physreg is used by the instruction, we want to kill it on the
289  // instruction, not on the spill.
290  bool SpillKill = MachineBasicBlock::iterator(LR.LastUse) != MI;
291  LR.Dirty = false;
292  DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
293  << " in " << PrintReg(LR.PhysReg, TRI));
294  const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
295  int FI = getStackSpaceFor(LRI->VirtReg, RC);
296  DEBUG(dbgs() << " to stack slot #" << FI << "\n");
297  TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
298  ++NumStores; // Update statistics
299 
300  // If this register is used by DBG_VALUE then insert new DBG_VALUE to
301  // identify spilled location as the place to find corresponding variable's
302  // value.
303  SmallVectorImpl<MachineInstr *> &LRIDbgValues =
304  LiveDbgValueMap[LRI->VirtReg];
305  for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
306  MachineInstr *DBG = LRIDbgValues[li];
307  const MDNode *Var = DBG->getDebugVariable();
308  const MDNode *Expr = DBG->getDebugExpression();
309  bool IsIndirect = DBG->isIndirectDebugValue();
310  uint64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0;
311  DebugLoc DL = DBG->getDebugLoc();
312  assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
313  "Expected inlined-at fields to agree");
314  MachineInstr *NewDV =
315  BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
316  .addFrameIndex(FI)
317  .addImm(Offset)
318  .addMetadata(Var)
319  .addMetadata(Expr);
320  assert(NewDV->getParent() == MBB && "dangling parent pointer");
321  (void)NewDV;
322  DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
323  }
324  // Now this register is spilled there is should not be any DBG_VALUE
325  // pointing to this register because they are all pointing to spilled value
326  // now.
327  LRIDbgValues.clear();
328  if (SpillKill)
329  LR.LastUse = nullptr; // Don't kill register again
330  }
331  killVirtReg(LRI);
332 }
333 
334 /// spillAll - Spill all dirty virtregs without killing them.
335 void RAFast::spillAll(MachineBasicBlock::iterator MI) {
336  if (LiveVirtRegs.empty()) return;
337  isBulkSpilling = true;
338  // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
339  // of spilling here is deterministic, if arbitrary.
340  for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
341  i != e; ++i)
342  spillVirtReg(MI, i);
343  LiveVirtRegs.clear();
344  isBulkSpilling = false;
345 }
346 
347 /// usePhysReg - Handle the direct use of a physical register.
348 /// Check that the register is not used by a virtreg.
349 /// Kill the physreg, marking it free.
350 /// This may add implicit kills to MO->getParent() and invalidate MO.
351 void RAFast::usePhysReg(MachineOperand &MO) {
352  unsigned PhysReg = MO.getReg();
354  "Bad usePhysReg operand");
355 
356  // Ignore undef uses.
357  if (MO.isUndef())
358  return;
359 
360  markRegUsedInInstr(PhysReg);
361  switch (PhysRegState[PhysReg]) {
362  case regDisabled:
363  break;
364  case regReserved:
365  PhysRegState[PhysReg] = regFree;
367  case regFree:
368  MO.setIsKill();
369  return;
370  default:
371  // The physreg was allocated to a virtual register. That means the value we
372  // wanted has been clobbered.
373  llvm_unreachable("Instruction uses an allocated register");
374  }
375 
376  // Maybe a superregister is reserved?
377  for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
378  unsigned Alias = *AI;
379  switch (PhysRegState[Alias]) {
380  case regDisabled:
381  break;
382  case regReserved:
383  // Either PhysReg is a subregister of Alias and we mark the
384  // whole register as free, or PhysReg is the superregister of
385  // Alias and we mark all the aliases as disabled before freeing
386  // PhysReg.
387  // In the latter case, since PhysReg was disabled, this means that
388  // its value is defined only by physical sub-registers. This check
389  // is performed by the assert of the default case in this loop.
390  // Note: The value of the superregister may only be partial
391  // defined, that is why regDisabled is a valid state for aliases.
392  assert((TRI->isSuperRegister(PhysReg, Alias) ||
393  TRI->isSuperRegister(Alias, PhysReg)) &&
394  "Instruction is not using a subregister of a reserved register");
396  case regFree:
397  if (TRI->isSuperRegister(PhysReg, Alias)) {
398  // Leave the superregister in the working set.
399  PhysRegState[Alias] = regFree;
400  MO.getParent()->addRegisterKilled(Alias, TRI, true);
401  return;
402  }
403  // Some other alias was in the working set - clear it.
404  PhysRegState[Alias] = regDisabled;
405  break;
406  default:
407  llvm_unreachable("Instruction uses an alias of an allocated register");
408  }
409  }
410 
411  // All aliases are disabled, bring register into working set.
412  PhysRegState[PhysReg] = regFree;
413  MO.setIsKill();
414 }
415 
416 /// definePhysReg - Mark PhysReg as reserved or free after spilling any
417 /// virtregs. This is very similar to defineVirtReg except the physreg is
418 /// reserved instead of allocated.
419 void RAFast::definePhysReg(MachineInstr &MI, unsigned PhysReg,
420  RegState NewState) {
421  markRegUsedInInstr(PhysReg);
422  switch (unsigned VirtReg = PhysRegState[PhysReg]) {
423  case regDisabled:
424  break;
425  default:
426  spillVirtReg(MI, VirtReg);
428  case regFree:
429  case regReserved:
430  PhysRegState[PhysReg] = NewState;
431  return;
432  }
433 
434  // This is a disabled register, disable all aliases.
435  PhysRegState[PhysReg] = NewState;
436  for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
437  unsigned Alias = *AI;
438  switch (unsigned VirtReg = PhysRegState[Alias]) {
439  case regDisabled:
440  break;
441  default:
442  spillVirtReg(MI, VirtReg);
444  case regFree:
445  case regReserved:
446  PhysRegState[Alias] = regDisabled;
447  if (TRI->isSuperRegister(PhysReg, Alias))
448  return;
449  break;
450  }
451  }
452 }
453 
454 
455 // calcSpillCost - Return the cost of spilling clearing out PhysReg and
456 // aliases so it is free for allocation.
457 // Returns 0 when PhysReg is free or disabled with all aliases disabled - it
458 // can be allocated directly.
459 // Returns spillImpossible when PhysReg or an alias can't be spilled.
460 unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
461  if (isRegUsedInInstr(PhysReg)) {
462  DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
463  return spillImpossible;
464  }
465  switch (unsigned VirtReg = PhysRegState[PhysReg]) {
466  case regDisabled:
467  break;
468  case regFree:
469  return 0;
470  case regReserved:
471  DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
472  << PrintReg(PhysReg, TRI) << " is reserved already.\n");
473  return spillImpossible;
474  default: {
475  LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
476  assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
477  return I->Dirty ? spillDirty : spillClean;
478  }
479  }
480 
481  // This is a disabled register, add up cost of aliases.
482  DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
483  unsigned Cost = 0;
484  for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
485  unsigned Alias = *AI;
486  switch (unsigned VirtReg = PhysRegState[Alias]) {
487  case regDisabled:
488  break;
489  case regFree:
490  ++Cost;
491  break;
492  case regReserved:
493  return spillImpossible;
494  default: {
495  LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
496  assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
497  Cost += I->Dirty ? spillDirty : spillClean;
498  break;
499  }
500  }
501  }
502  return Cost;
503 }
504 
505 
506 /// assignVirtToPhysReg - This method updates local state so that we know
507 /// that PhysReg is the proper container for VirtReg now. The physical
508 /// register must not be used for anything else when this is called.
509 ///
510 void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) {
511  DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
512  << PrintReg(PhysReg, TRI) << "\n");
513  PhysRegState[PhysReg] = LR.VirtReg;
514  assert(!LR.PhysReg && "Already assigned a physreg");
515  LR.PhysReg = PhysReg;
516 }
517 
519 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
520  LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
521  assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
522  assignVirtToPhysReg(*LRI, PhysReg);
523  return LRI;
524 }
525 
526 /// allocVirtReg - Allocate a physical register for VirtReg.
527 RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr &MI,
528  LiveRegMap::iterator LRI,
529  unsigned Hint) {
530  const unsigned VirtReg = LRI->VirtReg;
531 
533  "Can only allocate virtual registers");
534 
535  const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
536 
537  // Ignore invalid hints.
538  if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
539  !RC->contains(Hint) || !MRI->isAllocatable(Hint)))
540  Hint = 0;
541 
542  // Take hint when possible.
543  if (Hint) {
544  // Ignore the hint if we would have to spill a dirty register.
545  unsigned Cost = calcSpillCost(Hint);
546  if (Cost < spillDirty) {
547  if (Cost)
548  definePhysReg(MI, Hint, regFree);
549  // definePhysReg may kill virtual registers and modify LiveVirtRegs.
550  // That invalidates LRI, so run a new lookup for VirtReg.
551  return assignVirtToPhysReg(VirtReg, Hint);
552  }
553  }
554 
555  ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
556 
557  // First try to find a completely free register.
558  for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
559  unsigned PhysReg = *I;
560  if (PhysRegState[PhysReg] == regFree && !isRegUsedInInstr(PhysReg)) {
561  assignVirtToPhysReg(*LRI, PhysReg);
562  return LRI;
563  }
564  }
565 
566  DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
567  << TRI->getRegClassName(RC) << "\n");
568 
569  unsigned BestReg = 0, BestCost = spillImpossible;
570  for (ArrayRef<MCPhysReg>::iterator I = AO.begin(), E = AO.end(); I != E; ++I){
571  unsigned Cost = calcSpillCost(*I);
572  DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
573  DEBUG(dbgs() << "\tCost: " << Cost << "\n");
574  DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
575  // Cost is 0 when all aliases are already disabled.
576  if (Cost == 0) {
577  assignVirtToPhysReg(*LRI, *I);
578  return LRI;
579  }
580  if (Cost < BestCost)
581  BestReg = *I, BestCost = Cost;
582  }
583 
584  if (BestReg) {
585  definePhysReg(MI, BestReg, regFree);
586  // definePhysReg may kill virtual registers and modify LiveVirtRegs.
587  // That invalidates LRI, so run a new lookup for VirtReg.
588  return assignVirtToPhysReg(VirtReg, BestReg);
589  }
590 
591  // Nothing we can do. Report an error and keep going with a bad allocation.
592  if (MI.isInlineAsm())
593  MI.emitError("inline assembly requires more registers than available");
594  else
595  MI.emitError("ran out of registers during register allocation");
596  definePhysReg(MI, *AO.begin(), regFree);
597  return assignVirtToPhysReg(VirtReg, *AO.begin());
598 }
599 
600 /// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
601 RAFast::LiveRegMap::iterator RAFast::defineVirtReg(MachineInstr &MI,
602  unsigned OpNum,
603  unsigned VirtReg,
604  unsigned Hint) {
606  "Not a virtual register");
607  LiveRegMap::iterator LRI;
608  bool New;
609  std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
610  if (New) {
611  // If there is no hint, peek at the only use of this register.
612  if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
613  MRI->hasOneNonDBGUse(VirtReg)) {
614  const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
615  // It's a copy, use the destination register as a hint.
616  if (UseMI.isCopyLike())
617  Hint = UseMI.getOperand(0).getReg();
618  }
619  LRI = allocVirtReg(MI, LRI, Hint);
620  } else if (LRI->LastUse) {
621  // Redefining a live register - kill at the last use, unless it is this
622  // instruction defining VirtReg multiple times.
623  if (LRI->LastUse != &MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
624  addKillFlag(*LRI);
625  }
626  assert(LRI->PhysReg && "Register not assigned");
627  LRI->LastUse = &MI;
628  LRI->LastOpNum = OpNum;
629  LRI->Dirty = true;
630  markRegUsedInInstr(LRI->PhysReg);
631  return LRI;
632 }
633 
634 /// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
635 RAFast::LiveRegMap::iterator RAFast::reloadVirtReg(MachineInstr &MI,
636  unsigned OpNum,
637  unsigned VirtReg,
638  unsigned Hint) {
640  "Not a virtual register");
641  LiveRegMap::iterator LRI;
642  bool New;
643  std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
644  MachineOperand &MO = MI.getOperand(OpNum);
645  if (New) {
646  LRI = allocVirtReg(MI, LRI, Hint);
647  const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
648  int FrameIndex = getStackSpaceFor(VirtReg, RC);
649  DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
650  << PrintReg(LRI->PhysReg, TRI) << "\n");
651  TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
652  ++NumLoads;
653  } else if (LRI->Dirty) {
654  if (isLastUseOfLocalReg(MO)) {
655  DEBUG(dbgs() << "Killing last use: " << MO << "\n");
656  if (MO.isUse())
657  MO.setIsKill();
658  else
659  MO.setIsDead();
660  } else if (MO.isKill()) {
661  DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
662  MO.setIsKill(false);
663  } else if (MO.isDead()) {
664  DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
665  MO.setIsDead(false);
666  }
667  } else if (MO.isKill()) {
668  // We must remove kill flags from uses of reloaded registers because the
669  // register would be killed immediately, and there might be a second use:
670  // %foo = OR %x<kill>, %x
671  // This would cause a second reload of %x into a different register.
672  DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
673  MO.setIsKill(false);
674  } else if (MO.isDead()) {
675  DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
676  MO.setIsDead(false);
677  }
678  assert(LRI->PhysReg && "Register not assigned");
679  LRI->LastUse = &MI;
680  LRI->LastOpNum = OpNum;
681  markRegUsedInInstr(LRI->PhysReg);
682  return LRI;
683 }
684 
685 // setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
686 // subregs. This may invalidate any operand pointers.
687 // Return true if the operand kills its register.
688 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
689  MachineOperand &MO = MI->getOperand(OpNum);
690  bool Dead = MO.isDead();
691  if (!MO.getSubReg()) {
692  MO.setReg(PhysReg);
693  return MO.isKill() || Dead;
694  }
695 
696  // Handle subregister index.
697  MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
698  MO.setSubReg(0);
699 
700  // A kill flag implies killing the full register. Add corresponding super
701  // register kill.
702  if (MO.isKill()) {
703  MI->addRegisterKilled(PhysReg, TRI, true);
704  return true;
705  }
706 
707  // A <def,read-undef> of a sub-register requires an implicit def of the full
708  // register.
709  if (MO.isDef() && MO.isUndef())
710  MI->addRegisterDefined(PhysReg, TRI);
711 
712  return Dead;
713 }
714 
715 // Handle special instruction operand like early clobbers and tied ops when
716 // there are additional physreg defines.
717 void RAFast::handleThroughOperands(MachineInstr *MI,
718  SmallVectorImpl<unsigned> &VirtDead) {
719  DEBUG(dbgs() << "Scanning for through registers:");
720  SmallSet<unsigned, 8> ThroughRegs;
721  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
722  MachineOperand &MO = MI->getOperand(i);
723  if (!MO.isReg()) continue;
724  unsigned Reg = MO.getReg();
726  continue;
727  if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
728  (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
729  if (ThroughRegs.insert(Reg).second)
730  DEBUG(dbgs() << ' ' << PrintReg(Reg));
731  }
732  }
733 
734  // If any physreg defines collide with preallocated through registers,
735  // we must spill and reallocate.
736  DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
737  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
738  MachineOperand &MO = MI->getOperand(i);
739  if (!MO.isReg() || !MO.isDef()) continue;
740  unsigned Reg = MO.getReg();
741  if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
742  markRegUsedInInstr(Reg);
743  for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
744  if (ThroughRegs.count(PhysRegState[*AI]))
745  definePhysReg(*MI, *AI, regFree);
746  }
747  }
748 
749  SmallVector<unsigned, 8> PartialDefs;
750  DEBUG(dbgs() << "Allocating tied uses.\n");
751  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
752  MachineOperand &MO = MI->getOperand(i);
753  if (!MO.isReg()) continue;
754  unsigned Reg = MO.getReg();
755  if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
756  if (MO.isUse()) {
757  unsigned DefIdx = 0;
758  if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
759  DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
760  << DefIdx << ".\n");
761  LiveRegMap::iterator LRI = reloadVirtReg(*MI, i, Reg, 0);
762  unsigned PhysReg = LRI->PhysReg;
763  setPhysReg(MI, i, PhysReg);
764  // Note: we don't update the def operand yet. That would cause the normal
765  // def-scan to attempt spilling.
766  } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
767  DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
768  // Reload the register, but don't assign to the operand just yet.
769  // That would confuse the later phys-def processing pass.
770  LiveRegMap::iterator LRI = reloadVirtReg(*MI, i, Reg, 0);
771  PartialDefs.push_back(LRI->PhysReg);
772  }
773  }
774 
775  DEBUG(dbgs() << "Allocating early clobbers.\n");
776  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
777  MachineOperand &MO = MI->getOperand(i);
778  if (!MO.isReg()) continue;
779  unsigned Reg = MO.getReg();
780  if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
781  if (!MO.isEarlyClobber())
782  continue;
783  // Note: defineVirtReg may invalidate MO.
784  LiveRegMap::iterator LRI = defineVirtReg(*MI, i, Reg, 0);
785  unsigned PhysReg = LRI->PhysReg;
786  if (setPhysReg(MI, i, PhysReg))
787  VirtDead.push_back(Reg);
788  }
789 
790  // Restore UsedInInstr to a state usable for allocating normal virtual uses.
791  UsedInInstr.clear();
792  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
793  MachineOperand &MO = MI->getOperand(i);
794  if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
795  unsigned Reg = MO.getReg();
796  if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
797  DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)
798  << " as used in instr\n");
799  markRegUsedInInstr(Reg);
800  }
801 
802  // Also mark PartialDefs as used to avoid reallocation.
803  for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
804  markRegUsedInInstr(PartialDefs[i]);
805 }
806 
807 void RAFast::AllocateBasicBlock() {
808  DEBUG(dbgs() << "\nAllocating " << *MBB);
809 
810  PhysRegState.assign(TRI->getNumRegs(), regDisabled);
811  assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?");
812 
814 
815  // Add live-in registers as live.
816  for (const auto &LI : MBB->liveins())
817  if (MRI->isAllocatable(LI.PhysReg))
818  definePhysReg(*MII, LI.PhysReg, regReserved);
819 
820  SmallVector<unsigned, 8> VirtDead;
822 
823  // Otherwise, sequentially allocate each instruction in the MBB.
824  while (MII != MBB->end()) {
825  MachineInstr *MI = &*MII++;
826  const MCInstrDesc &MCID = MI->getDesc();
827  DEBUG({
828  dbgs() << "\n>> " << *MI << "Regs:";
829  for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
830  if (PhysRegState[Reg] == regDisabled) continue;
831  dbgs() << " " << TRI->getName(Reg);
832  switch(PhysRegState[Reg]) {
833  case regFree:
834  break;
835  case regReserved:
836  dbgs() << "*";
837  break;
838  default: {
839  dbgs() << '=' << PrintReg(PhysRegState[Reg]);
840  LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
841  assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
842  if (I->Dirty)
843  dbgs() << "*";
844  assert(I->PhysReg == Reg && "Bad inverse map");
845  break;
846  }
847  }
848  }
849  dbgs() << '\n';
850  // Check that LiveVirtRegs is the inverse.
851  for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
852  e = LiveVirtRegs.end(); i != e; ++i) {
854  "Bad map key");
856  "Bad map value");
857  assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
858  }
859  });
860 
861  // Debug values are not allowed to change codegen in any way.
862  if (MI->isDebugValue()) {
863  bool ScanDbgValue = true;
864  while (ScanDbgValue) {
865  ScanDbgValue = false;
866  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
867  MachineOperand &MO = MI->getOperand(i);
868  if (!MO.isReg()) continue;
869  unsigned Reg = MO.getReg();
870  if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
871  LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
872  if (LRI != LiveVirtRegs.end())
873  setPhysReg(MI, i, LRI->PhysReg);
874  else {
875  int SS = StackSlotForVirtReg[Reg];
876  if (SS == -1) {
877  // We can't allocate a physreg for a DebugValue, sorry!
878  DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
879  MO.setReg(0);
880  }
881  else {
882  // Modify DBG_VALUE now that the value is in a spill slot.
883  bool IsIndirect = MI->isIndirectDebugValue();
884  uint64_t Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
885  const MDNode *Var = MI->getDebugVariable();
886  const MDNode *Expr = MI->getDebugExpression();
887  DebugLoc DL = MI->getDebugLoc();
889  assert(
890  cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&
891  "Expected inlined-at fields to agree");
892  MachineInstr *NewDV = BuildMI(*MBB, MBB->erase(MI), DL,
893  TII->get(TargetOpcode::DBG_VALUE))
894  .addFrameIndex(SS)
895  .addImm(Offset)
896  .addMetadata(Var)
897  .addMetadata(Expr);
898  DEBUG(dbgs() << "Modifying debug info due to spill:"
899  << "\t" << *NewDV);
900  // Scan NewDV operands from the beginning.
901  MI = NewDV;
902  ScanDbgValue = true;
903  break;
904  }
905  }
906  LiveDbgValueMap[Reg].push_back(MI);
907  }
908  }
909  // Next instruction.
910  continue;
911  }
912 
913  // If this is a copy, we may be able to coalesce.
914  unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
915  if (MI->isCopy()) {
916  CopyDst = MI->getOperand(0).getReg();
917  CopySrc = MI->getOperand(1).getReg();
918  CopyDstSub = MI->getOperand(0).getSubReg();
919  CopySrcSub = MI->getOperand(1).getSubReg();
920  }
921 
922  // Track registers used by instruction.
923  UsedInInstr.clear();
924 
925  // First scan.
926  // Mark physreg uses and early clobbers as used.
927  // Find the end of the virtreg operands
928  unsigned VirtOpEnd = 0;
929  bool hasTiedOps = false;
930  bool hasEarlyClobbers = false;
931  bool hasPartialRedefs = false;
932  bool hasPhysDefs = false;
933  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
934  MachineOperand &MO = MI->getOperand(i);
935  // Make sure MRI knows about registers clobbered by regmasks.
936  if (MO.isRegMask()) {
937  MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
938  continue;
939  }
940  if (!MO.isReg()) continue;
941  unsigned Reg = MO.getReg();
942  if (!Reg) continue;
944  VirtOpEnd = i+1;
945  if (MO.isUse()) {
946  hasTiedOps = hasTiedOps ||
947  MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
948  } else {
949  if (MO.isEarlyClobber())
950  hasEarlyClobbers = true;
951  if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
952  hasPartialRedefs = true;
953  }
954  continue;
955  }
956  if (!MRI->isAllocatable(Reg)) continue;
957  if (MO.isUse()) {
958  usePhysReg(MO);
959  } else if (MO.isEarlyClobber()) {
960  definePhysReg(*MI, Reg,
961  (MO.isImplicit() || MO.isDead()) ? regFree : regReserved);
962  hasEarlyClobbers = true;
963  } else
964  hasPhysDefs = true;
965  }
966 
967  // The instruction may have virtual register operands that must be allocated
968  // the same register at use-time and def-time: early clobbers and tied
969  // operands. If there are also physical defs, these registers must avoid
970  // both physical defs and uses, making them more constrained than normal
971  // operands.
972  // Similarly, if there are multiple defs and tied operands, we must make
973  // sure the same register is allocated to uses and defs.
974  // We didn't detect inline asm tied operands above, so just make this extra
975  // pass for all inline asm.
976  if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
977  (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
978  handleThroughOperands(MI, VirtDead);
979  // Don't attempt coalescing when we have funny stuff going on.
980  CopyDst = 0;
981  // Pretend we have early clobbers so the use operands get marked below.
982  // This is not necessary for the common case of a single tied use.
983  hasEarlyClobbers = true;
984  }
985 
986  // Second scan.
987  // Allocate virtreg uses.
988  for (unsigned i = 0; i != VirtOpEnd; ++i) {
989  MachineOperand &MO = MI->getOperand(i);
990  if (!MO.isReg()) continue;
991  unsigned Reg = MO.getReg();
992  if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
993  if (MO.isUse()) {
994  LiveRegMap::iterator LRI = reloadVirtReg(*MI, i, Reg, CopyDst);
995  unsigned PhysReg = LRI->PhysReg;
996  CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
997  if (setPhysReg(MI, i, PhysReg))
998  killVirtReg(LRI);
999  }
1000  }
1001 
1002  // Track registers defined by instruction - early clobbers and tied uses at
1003  // this point.
1004  UsedInInstr.clear();
1005  if (hasEarlyClobbers) {
1006  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1007  MachineOperand &MO = MI->getOperand(i);
1008  if (!MO.isReg()) continue;
1009  unsigned Reg = MO.getReg();
1010  if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1011  // Look for physreg defs and tied uses.
1012  if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
1013  markRegUsedInInstr(Reg);
1014  }
1015  }
1016 
1017  unsigned DefOpEnd = MI->getNumOperands();
1018  if (MI->isCall()) {
1019  // Spill all virtregs before a call. This serves one purpose: If an
1020  // exception is thrown, the landing pad is going to expect to find
1021  // registers in their spill slots.
1022  // Note: although this is appealing to just consider all definitions
1023  // as call-clobbered, this is not correct because some of those
1024  // definitions may be used later on and we do not want to reuse
1025  // those for virtual registers in between.
1026  DEBUG(dbgs() << " Spilling remaining registers before call.\n");
1027  spillAll(MI);
1028 
1029  // The imp-defs are skipped below, but we still need to mark those
1030  // registers as used by the function.
1031  SkippedInstrs.insert(&MCID);
1032  }
1033 
1034  // Third scan.
1035  // Allocate defs and collect dead defs.
1036  for (unsigned i = 0; i != DefOpEnd; ++i) {
1037  MachineOperand &MO = MI->getOperand(i);
1038  if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1039  continue;
1040  unsigned Reg = MO.getReg();
1041 
1043  if (!MRI->isAllocatable(Reg)) continue;
1044  definePhysReg(*MI, Reg, MO.isDead() ? regFree : regReserved);
1045  continue;
1046  }
1047  LiveRegMap::iterator LRI = defineVirtReg(*MI, i, Reg, CopySrc);
1048  unsigned PhysReg = LRI->PhysReg;
1049  if (setPhysReg(MI, i, PhysReg)) {
1050  VirtDead.push_back(Reg);
1051  CopyDst = 0; // cancel coalescing;
1052  } else
1053  CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1054  }
1055 
1056  // Kill dead defs after the scan to ensure that multiple defs of the same
1057  // register are allocated identically. We didn't need to do this for uses
1058  // because we are crerating our own kill flags, and they are always at the
1059  // last use.
1060  for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
1061  killVirtReg(VirtDead[i]);
1062  VirtDead.clear();
1063 
1064  if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1065  DEBUG(dbgs() << "-- coalescing: " << *MI);
1066  Coalesced.push_back(MI);
1067  } else {
1068  DEBUG(dbgs() << "<< " << *MI);
1069  }
1070  }
1071 
1072  // Spill all physical registers holding virtual registers now.
1073  DEBUG(dbgs() << "Spilling live registers at end of block.\n");
1074  spillAll(MBB->getFirstTerminator());
1075 
1076  // Erase all the coalesced copies. We are delaying it until now because
1077  // LiveVirtRegs might refer to the instrs.
1078  for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
1079  MBB->erase(Coalesced[i]);
1080  NumCopies += Coalesced.size();
1081 
1082  DEBUG(MBB->dump());
1083 }
1084 
1085 /// runOnMachineFunction - Register allocate the whole function
1086 ///
1087 bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1088  DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
1089  << "********** Function: " << Fn.getName() << '\n');
1090  MF = &Fn;
1091  MRI = &MF->getRegInfo();
1092  TRI = MF->getSubtarget().getRegisterInfo();
1093  TII = MF->getSubtarget().getInstrInfo();
1094  MRI->freezeReservedRegs(Fn);
1095  RegClassInfo.runOnMachineFunction(Fn);
1096  UsedInInstr.clear();
1097  UsedInInstr.setUniverse(TRI->getNumRegUnits());
1098 
1099  // initialize the virtual->physical register map to have a 'null'
1100  // mapping for all virtual registers
1101  StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
1102  LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
1103 
1104  // Loop over all of the basic blocks, eliminating virtual register references
1105  for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
1106  MBBi != MBBe; ++MBBi) {
1107  MBB = &*MBBi;
1108  AllocateBasicBlock();
1109  }
1110 
1111  // All machine operands and other references to virtual registers have been
1112  // replaced. Remove the virtual registers.
1113  MRI->clearVirtRegs();
1114 
1115  SkippedInstrs.clear();
1116  StackSlotForVirtReg.clear();
1117  LiveDbgValueMap.clear();
1118  return true;
1119 }
1120 
1122  return new RAFast();
1123 }
bool isImplicit() const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
void push_back(const T &Elt)
Definition: SmallVector.h:211
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
iterator_range< livein_iterator > liveins() const
STATISTIC(NumFunctions,"Total number of functions")
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
size_t i
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
std::pair< iterator, bool > insert(const ValueT &Val)
insert - Attempts to insert a new element.
Definition: SparseSet.h:249
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:216
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
iterator end() const
Definition: ArrayRef.h:130
bool isDead() const
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:873
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
MachineInstrBundleIterator< MachineInstr > iterator
A debug info location.
Definition: DebugLoc.h:34
Metadata node.
Definition: Metadata.h:830
void setIsDead(bool Val=true)
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
bool isUndef() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isKill() const
MachineBasicBlock * MBB
Function Alias Analysis false
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:819
RegisterRegAlloc class - Track the registration of register allocators.
int64_t getImm() const
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:777
bool isEarlyClobber() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
unsigned getAlignment() const
Return the minimum required alignment for a register of this class.
MachineInstrBuilder & UseMI
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
Definition: MachineInstr.h:780
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
bool isCopy() const
Definition: MachineInstr.h:807
MCRegAliasIterator enumerates all registers aliasing Reg.
Represent the analysis usage information of a pass.
uint32_t Offset
iterator begin() const
Definition: ArrayRef.h:129
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:80
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specific constraint if it is set.
Definition: MCInstrDesc.h:187
void setIsKill(bool Val=true)
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:64
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
Definition: SmallPtrSet.h:425
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:789
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:276
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SparseSet - Fast set implmentation for objects that can be identified by small unsigned keys...
Definition: SparseSet.h:123
static RegisterRegAlloc fastRegAlloc("fast","fast register allocator", createFastRegisterAllocator)
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
void setSubReg(unsigned subReg)
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
#define DEBUG(X)
Definition: Debug.h:100
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Properties which a MachineFunction may have at a given point in time.
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.