33 DefaultActions[TargetOpcode::G_ANYEXT] =
Legal;
34 DefaultActions[TargetOpcode::G_TRUNC] =
Legal;
36 DefaultActions[TargetOpcode::G_INTRINSIC] =
Legal;
37 DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] =
Legal;
43 DefaultActions[TargetOpcode::G_BRCOND] =
WidenScalar;
47 for (
unsigned Opcode = 0; Opcode <= LastOp - FirstOp; ++Opcode) {
48 for (
unsigned Idx = 0; Idx != Actions[Opcode].size(); ++Idx) {
49 for (
auto &Action : Actions[Opcode][Idx]) {
50 LLT Ty = Action.first;
54 auto &Entry = MaxLegalVectorElts[std::make_pair(Opcode + FirstOp,
61 TablesInitialized =
true;
68 std::pair<LegalizerInfo::LegalizeAction, LLT>
70 assert(TablesInitialized &&
"backend forgot to call computeTables");
81 if (Aspect.
Opcode == TargetOpcode::G_SEQUENCE ||
82 Aspect.
Opcode == TargetOpcode::G_EXTRACT)
83 return std::make_pair(
Legal, Aspect.
Type);
89 unsigned Opcode = Aspect.
Opcode;
92 auto DefaultAction = DefaultActions.
find(Aspect.
Opcode);
93 if (DefaultAction != DefaultActions.
end() && DefaultAction->second ==
Legal)
94 return std::make_pair(
Legal, Ty);
96 if (DefaultAction == DefaultActions.
end() ||
105 auto ScalarAction = ScalarInVectorActions.
find(std::make_pair(Opcode, EltTy));
106 if (ScalarAction != ScalarInVectorActions.
end() &&
107 ScalarAction->second !=
Legal)
112 auto MaxLegalElts = MaxLegalVectorElts.lookup(std::make_pair(Opcode, EltTy));
113 if (MaxLegalElts > NumElts)
116 if (MaxLegalElts == 0) {
125 std::tuple<LegalizerInfo::LegalizeAction, unsigned, LLT>
131 if (!OpInfo[
i].isGenericType())
137 if (SeenTypes[TypeIdx])
140 SeenTypes.
set(TypeIdx);
144 if (Action.first !=
Legal)
145 return std::make_tuple(Action.first, TypeIdx, Action.second);
147 return std::make_tuple(
Legal, 0,
LLT{});
LLT doubleElements() const
Get a low-level type with twice the size of the original, by doubling the number of vector elements o...
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
std::pair< LegalizeAction, LLT > getAction(const InstrAspect &Aspect) const
Determine what action should be taken to legalize the given generic instruction opcode, type-index and type.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Sentinel value for when no action was found in the specified table.
void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
Function Alias Analysis false
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
LLT doubleScalarSize() const
Get a low-level type with twice the size of the original, by doubling the size of the scalar type inv...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned const MachineRegisterInfo * MRI
The (vector) operation should be implemented by splitting it into sub-vectors where the operation is ...
const MachineOperand & getOperand(unsigned i) const
unsigned getGenericTypeIndex() const
constexpr bool isPowerOf2_64(uint64_t Value)
isPowerOf2_64 - This function returns true if the argument is a power of two 0 (64 bit edition...
The (vector) operation should be implemented by widening the input vector and ignoring the lanes adde...
std::pair< LegalizeAction, LLT > findLegalAction(const InstrAspect &Aspect, LegalizeAction Action) const
Legalization is decided based on an instruction's opcode, which type slot we're considering, and what the existing type is.
LLT findLegalType(const InstrAspect &Aspect, std::function< LLT(LLT)> NextType) const
Iterate the given function (typically something like doubling the width) on Ty until we find a legal ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
The operation should be synthesized from multiple instructions acting on a narrower scalar base-type...
The operation should be implemented as a call to some kind of runtime support library.
The operation should be implemented in terms of a wider scalar base-type.
The operation itself must be expressed in terms of simpler actions on this target.
The operation is expected to be selectable directly by the target, and no transformation is necessary...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
LLT halfScalarSize() const
Get a low-level type with half the size of the original, by halving the size of the scalar type invol...
LLT halfElements() const
Get a low-level type with half the size of the original, by halving the number of vector elements of ...
iterator find(const KeyT &Val)
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This operation is completely unsupported on the target.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
const MCOperandInfo * OpInfo
LegalizeAction findInActions(const InstrAspect &Aspect) const
Find the specified Aspect in the primary (explicitly set) Actions table.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isLegal(const MachineInstr &MI, const MachineRegisterInfo &MRI) const