LLVM  4.0.0
MSP430ISelLowering.h
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1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that MSP430 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16 #define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
17 
18 #include "MSP430.h"
21 
22 namespace llvm {
23  namespace MSP430ISD {
24  enum NodeType : unsigned {
26 
27  /// Return with a flag operand. Operand 0 is the chain operand.
29 
30  /// Same as RET_FLAG, but used for returning from ISRs.
32 
33  /// Y = R{R,L}A X, rotate right (left) arithmetically
34  RRA, RLA,
35 
36  /// Y = RRC X, rotate right via carry
37  RRC,
38 
39  /// CALL - These operations represent an abstract call
40  /// instruction, which includes a bunch of information.
42 
43  /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
44  /// and TargetGlobalAddress.
46 
47  /// CMP - Compare instruction.
48  CMP,
49 
50  /// SetCC - Operand 0 is condition code, and operand 1 is the flag
51  /// operand produced by a CMP instruction.
53 
54  /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
55  /// is the block to branch if condition is true, operand 2 is the
56  /// condition code, and operand 3 is the flag operand produced by a CMP
57  /// instruction.
59 
60  /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
61  /// is condition code and operand 4 is flag operand.
63 
64  /// SHL, SRA, SRL - Non-constant shifts.
66  };
67  }
68 
69  class MSP430Subtarget;
71  public:
72  explicit MSP430TargetLowering(const TargetMachine &TM,
73  const MSP430Subtarget &STI);
74 
75  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
76  return MVT::i8;
77  }
78 
79  /// LowerOperation - Provide custom lowering hooks for some operations.
80  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
81 
82  /// getTargetNodeName - This method returns the name of a target specific
83  /// DAG node.
84  const char *getTargetNodeName(unsigned Opcode) const override;
85 
99 
101  getConstraintType(StringRef Constraint) const override;
102  std::pair<unsigned, const TargetRegisterClass *>
104  StringRef Constraint, MVT VT) const override;
105 
106  /// isTruncateFree - Return true if it's free to truncate a value of type
107  /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
108  /// register R15W to i8 by referencing its sub-register R15B.
109  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
110  bool isTruncateFree(EVT VT1, EVT VT2) const override;
111 
112  /// isZExtFree - Return true if any actual instruction that defines a value
113  /// of type Ty1 implicit zero-extends the value to Ty2 in the result
114  /// register. This does not necessarily include registers defined in unknown
115  /// ways, such as incoming arguments, or copies from unknown virtual
116  /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
117  /// necessarily apply to truncate instructions. e.g. on msp430, all
118  /// instructions that define 8-bit values implicit zero-extend the result
119  /// out to 16 bits.
120  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
121  bool isZExtFree(EVT VT1, EVT VT2) const override;
122  bool isZExtFree(SDValue Val, EVT VT2) const override;
123 
126  MachineBasicBlock *BB) const override;
128  MachineBasicBlock *BB) const;
129 
130  private:
131  SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
132  CallingConv::ID CallConv, bool isVarArg,
133  bool isTailCall,
135  const SmallVectorImpl<SDValue> &OutVals,
137  const SDLoc &dl, SelectionDAG &DAG,
138  SmallVectorImpl<SDValue> &InVals) const;
139 
140  SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
141  bool isVarArg,
143  const SDLoc &dl, SelectionDAG &DAG,
144  SmallVectorImpl<SDValue> &InVals) const;
145 
146  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
147  CallingConv::ID CallConv, bool isVarArg,
149  const SDLoc &dl, SelectionDAG &DAG,
150  SmallVectorImpl<SDValue> &InVals) const;
151 
152  SDValue
153  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
155  const SDLoc &dl, SelectionDAG &DAG,
156  SmallVectorImpl<SDValue> &InVals) const override;
157  SDValue
158  LowerCall(TargetLowering::CallLoweringInfo &CLI,
159  SmallVectorImpl<SDValue> &InVals) const override;
160 
161  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
163  const SmallVectorImpl<SDValue> &OutVals,
164  const SDLoc &dl, SelectionDAG &DAG) const override;
165 
166  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
167  SDValue &Base,
168  SDValue &Offset,
170  SelectionDAG &DAG) const override;
171  };
172 } // namespace llvm
173 
174 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:762
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
Return with a flag operand. Operand 0 is the chain operand.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
MSP430 conditional branches.
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Y = RRC X, rotate right via carry.
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Same as RET_FLAG, but used for returning from ISRs.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
MVT - Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
uint32_t Offset
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction...
EVT - Extended Value Type.
Definition: ValueTypes.h:31
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
CMP - Compare instruction.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target...
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
Representation of each machine instruction.
Definition: MachineInstr.h:52
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
#define N
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
Y = R{R,L}A X, rotate right (left) arithmetically.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
Primary interface to the complete machine description for the target machine.
IRTranslator LLVM IR MI
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
SHL, SRA, SRL - Non-constant shifts.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:799
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const