LLVM  4.0.0
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AMDGPU.h File Reference
#include "llvm/Target/TargetMachine.h"
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Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 
 llvm::AMDGPU
 
 AMDGPUAS
 OpenCL uses address spaces to differentiate between various memory regions on the hardware.
 

Enumerations

enum  llvm::AMDGPU::TargetIndex {
  llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2,
  llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3
}
 
enum  AMDGPUAS::AddressSpaces : unsigned {
  AMDGPUAS::PRIVATE_ADDRESS = 0, AMDGPUAS::GLOBAL_ADDRESS = 1, AMDGPUAS::CONSTANT_ADDRESS = 2, AMDGPUAS::LOCAL_ADDRESS = 3,
  AMDGPUAS::FLAT_ADDRESS = 4, AMDGPUAS::REGION_ADDRESS = 5, AMDGPUAS::PARAM_D_ADDRESS = 6, AMDGPUAS::PARAM_I_ADDRESS = 7,
  AMDGPUAS::CONSTANT_BUFFER_0 = 8, AMDGPUAS::CONSTANT_BUFFER_1 = 9, AMDGPUAS::CONSTANT_BUFFER_2 = 10, AMDGPUAS::CONSTANT_BUFFER_3 = 11,
  AMDGPUAS::CONSTANT_BUFFER_4 = 12, AMDGPUAS::CONSTANT_BUFFER_5 = 13, AMDGPUAS::CONSTANT_BUFFER_6 = 14, AMDGPUAS::CONSTANT_BUFFER_7 = 15,
  AMDGPUAS::CONSTANT_BUFFER_8 = 16, AMDGPUAS::CONSTANT_BUFFER_9 = 17, AMDGPUAS::CONSTANT_BUFFER_10 = 18, AMDGPUAS::CONSTANT_BUFFER_11 = 19,
  AMDGPUAS::CONSTANT_BUFFER_12 = 20, AMDGPUAS::CONSTANT_BUFFER_13 = 21, AMDGPUAS::CONSTANT_BUFFER_14 = 22, AMDGPUAS::CONSTANT_BUFFER_15 = 23,
  AMDGPUAS::UNKNOWN_ADDRESS_SPACE = ~0u
}
 

Functions

FunctionPassllvm::createR600VectorRegMerger (TargetMachine &tm)
 
FunctionPassllvm::createR600ExpandSpecialInstrsPass (TargetMachine &tm)
 
FunctionPassllvm::createR600EmitClauseMarkers ()
 
FunctionPassllvm::createR600ClauseMergePass (TargetMachine &tm)
 
FunctionPassllvm::createR600Packetizer (TargetMachine &tm)
 
FunctionPassllvm::createR600ControlFlowFinalizer (TargetMachine &tm)
 
FunctionPassllvm::createAMDGPUCFGStructurizerPass ()
 
FunctionPassllvm::createSITypeRewriter ()
 
FunctionPassllvm::createSIAnnotateControlFlowPass ()
 Create the annotation pass. More...
 
FunctionPassllvm::createSIFoldOperandsPass ()
 
FunctionPassllvm::createSILowerI1CopiesPass ()
 
FunctionPass * llvm::createSIShrinkInstructionsPass ()
 
FunctionPassllvm::createSILoadStoreOptimizerPass (TargetMachine &tm)
 
FunctionPassllvm::createSIWholeQuadModePass ()
 
FunctionPassllvm::createSIFixControlFlowLiveIntervalsPass ()
 
FunctionPassllvm::createSIFixSGPRCopiesPass ()
 
FunctionPassllvm::createSIDebuggerInsertNopsPass ()
 
FunctionPassllvm::createSIInsertWaitsPass ()
 
FunctionPassllvm::createAMDGPUCodeGenPreparePass (const GCNTargetMachine *TM=nullptr)
 
ModulePassllvm::createAMDGPUAnnotateKernelFeaturesPass ()
 
void llvm::initializeAMDGPUAnnotateKernelFeaturesPass (PassRegistry &)
 
void llvm::initializeSIFoldOperandsPass (PassRegistry &)
 
void llvm::initializeSIShrinkInstructionsPass (PassRegistry &)
 
void llvm::initializeSIFixSGPRCopiesPass (PassRegistry &)
 
void llvm::initializeSILowerI1CopiesPass (PassRegistry &)
 
void llvm::initializeSILoadStoreOptimizerPass (PassRegistry &)
 
void llvm::initializeSIWholeQuadModePass (PassRegistry &)
 
void llvm::initializeSILowerControlFlowPass (PassRegistry &)
 
void llvm::initializeSIInsertSkipsPass (PassRegistry &)
 
void llvm::initializeSIOptimizeExecMaskingPass (PassRegistry &)
 
FunctionPassllvm::createAMDGPUPromoteAlloca (const TargetMachine *TM=nullptr)
 
void llvm::initializeAMDGPUPromoteAllocaPass (PassRegistry &)
 
Passllvm::createAMDGPUStructurizeCFGPass ()
 
FunctionPassllvm::createAMDGPUISelDag (TargetMachine &TM, CodeGenOpt::Level OptLevel)
 This pass converts a legalized DAG into a AMDGPU-specific. More...
 
ModulePassllvm::createAMDGPUAlwaysInlinePass ()
 
ModulePassllvm::createAMDGPUOpenCLImageTypeLoweringPass ()
 
FunctionPassllvm::createAMDGPUAnnotateUniformValues ()
 
FunctionPass * llvm::createAMDGPUUnifyMetadataPass ()
 
void llvm::initializeAMDGPUUnifyMetadataPass (PassRegistry &)
 
void llvm::initializeSIFixControlFlowLiveIntervalsPass (PassRegistry &)
 
void llvm::initializeAMDGPUAnnotateUniformValuesPass (PassRegistry &)
 
void llvm::initializeAMDGPUCodeGenPreparePass (PassRegistry &)
 
void llvm::initializeSIAnnotateControlFlowPass (PassRegistry &)
 
void llvm::initializeSIDebuggerInsertNopsPass (PassRegistry &)
 
void llvm::initializeSIInsertWaitsPass (PassRegistry &)
 
Targetllvm::getTheAMDGPUTarget ()
 The target which suports all AMD GPUs. More...
 
Targetllvm::getTheGCNTarget ()
 The target for GCN GPUs. More...
 

Variables

char & llvm::AMDGPUAnnotateKernelFeaturesID = AMDGPUAnnotateKernelFeatures::ID
 
char & llvm::SIFoldOperandsID
 
char & llvm::SIShrinkInstructionsID
 
char & llvm::SIFixSGPRCopiesID = SIFixSGPRCopies::ID
 
char & llvm::SILowerI1CopiesID
 
char & llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID
 
char & llvm::SIWholeQuadModeID = SIWholeQuadMode::ID
 
char & llvm::SILowerControlFlowID = SILowerControlFlow::ID
 
char & llvm::SIInsertSkipsPassID
 
char & llvm::SIOptimizeExecMaskingID = SIOptimizeExecMasking::ID
 
char & llvm::AMDGPUPromoteAllocaID
 
char & llvm::AMDGPUUnifyMetadataID = AMDGPUUnifyMetadata::ID
 
char & llvm::SIFixControlFlowLiveIntervalsID = SIFixControlFlowLiveIntervals::ID
 
char & llvm::AMDGPUAnnotateUniformValuesPassID
 
char & llvm::AMDGPUCodeGenPrepareID
 
char & llvm::SIAnnotateControlFlowPassID
 
char & llvm::SIDebuggerInsertNopsID = SIDebuggerInsertNops::ID
 
char & llvm::SIInsertWaitsID = SIInsertWaits::ID