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LLVM
4.0.0
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This is the complete list of members for llvm::HexagonInstrInfo, including all inherited members.
| addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const | llvm::HexagonInstrInfo | |
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::HexagonInstrInfo | |
| analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override | llvm::HexagonInstrInfo | |
| analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override | llvm::HexagonInstrInfo | |
| areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override | llvm::HexagonInstrInfo | |
| canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const | llvm::HexagonInstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override | llvm::HexagonInstrInfo | |
| CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const override | llvm::HexagonInstrInfo | |
| CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override | llvm::HexagonInstrInfo | |
| createVR(MachineFunction *MF, MVT VT) const | llvm::HexagonInstrInfo | |
| DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override | llvm::HexagonInstrInfo | |
| doesNotReturn(const MachineInstr &CallMI) const | llvm::HexagonInstrInfo | |
| expandPostRAPseudo(MachineInstr &MI) const override | llvm::HexagonInstrInfo | |
| genAllInsnTimingClasses(MachineFunction &MF) const | llvm::HexagonInstrInfo | |
| getAbsoluteForm(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getAddrMode(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const | llvm::HexagonInstrInfo | |
| getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override | llvm::HexagonInstrInfo | |
| getBaseWithLongOffset(short Opcode) const | llvm::HexagonInstrInfo | |
| getBaseWithLongOffset(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getBaseWithRegOffset(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getBranchingInstrs(MachineBasicBlock &MBB) const | llvm::HexagonInstrInfo | |
| getCExtOpNum(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getCompoundCandidateGroup(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const | llvm::HexagonInstrInfo | |
| getCondOpcode(int Opc, bool sense) const | llvm::HexagonInstrInfo | |
| getDotCurOp(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getDotNewOp(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const | llvm::HexagonInstrInfo | |
| getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const | llvm::HexagonInstrInfo | |
| getDotOldOp(const int opc) const | llvm::HexagonInstrInfo | |
| getDuplexCandidateGroup(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getEquivalentHWInstr(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getFirstNonDbgInst(MachineBasicBlock *BB) const | llvm::HexagonInstrInfo | |
| getIncrementValue(const MachineInstr &MI, int &Value) const override | llvm::HexagonInstrInfo | |
| getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override | llvm::HexagonInstrInfo | |
| getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override | llvm::HexagonInstrInfo | |
| getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getInvertedPredicatedOpcode(const int Opc) const | llvm::HexagonInstrInfo | |
| getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const | llvm::HexagonInstrInfo | |
| getMaxValue(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getMemAccessSize(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override | llvm::HexagonInstrInfo | |
| getMinValue(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getNonExtOpcode(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const | llvm::HexagonInstrInfo | |
| getPseudoInstrPair(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getRegForm(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getRegisterInfo() const | llvm::HexagonInstrInfo | inline |
| getSize(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getType(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getUnits(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| getValidSubTargets(const unsigned Opcode) const | llvm::HexagonInstrInfo | |
| hasEHLabel(const MachineBasicBlock *B) const | llvm::HexagonInstrInfo | |
| hasNonExtEquivalent(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| hasPseudoInstrPair(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| hasUncondBranch(const MachineBasicBlock *B) const | llvm::HexagonInstrInfo | |
| HexagonInstrInfo(HexagonSubtarget &ST) | llvm::HexagonInstrInfo | explicit |
| immediateExtend(MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::HexagonInstrInfo | |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::HexagonInstrInfo | |
| invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const | llvm::HexagonInstrInfo | |
| isAbsoluteSet(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isAccumulator(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isComplex(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isCompoundBranchInstr(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isCondInst(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isConditionalALU32(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isConditionalLoad(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isConditionalStore(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isConditionalTransfer(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isConstExtended(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isDeallocRet(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const | llvm::HexagonInstrInfo | |
| isDotCurInst(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isDotNewInst(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const | llvm::HexagonInstrInfo | |
| isEarlySourceInstr(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isEndLoopN(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isExpr(unsigned OpType) const | llvm::HexagonInstrInfo | |
| isExtendable(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isExtended(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isFloat(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const | llvm::HexagonInstrInfo | |
| isIndirectCall(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isIndirectL4Return(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isJumpR(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const | llvm::HexagonInstrInfo | |
| isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const | llvm::HexagonInstrInfo | |
| isLateResultInstr(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isLateSourceInstr(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::HexagonInstrInfo | |
| isLoopN(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isMemOp(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isNewValue(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isNewValue(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isNewValueInst(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isNewValueJump(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isNewValueJump(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isNewValueStore(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isNewValueStore(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const | llvm::HexagonInstrInfo | |
| isPostIncrement(const MachineInstr &MI) const override | llvm::HexagonInstrInfo | |
| isPredicable(MachineInstr &MI) const override | llvm::HexagonInstrInfo | |
| isPredicated(const MachineInstr &MI) const override | llvm::HexagonInstrInfo | |
| isPredicated(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isPredicatedNew(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isPredicatedNew(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isPredicatedTrue(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isPredicatedTrue(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isPredicateLate(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isPredictedTaken(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override | llvm::HexagonInstrInfo | |
| isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override | llvm::HexagonInstrInfo | |
| isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override | llvm::HexagonInstrInfo | |
| isSaveCalleeSavedRegsCall(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override | llvm::HexagonInstrInfo | |
| isSignExtendingLoad(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isSolo(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isSpillPredRegOp(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::HexagonInstrInfo | |
| isTailCall(const MachineInstr &MI) const override | llvm::HexagonInstrInfo | |
| isTC1(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isTC2(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isTC2Early(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isTC4x(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const | llvm::HexagonInstrInfo | |
| isV60VectorInstruction(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isValidAutoIncImm(const EVT VT, const int Offset) const | llvm::HexagonInstrInfo | |
| isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const | llvm::HexagonInstrInfo | |
| isVecAcc(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isVecALU(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const | llvm::HexagonInstrInfo | |
| isZeroExtendingLoad(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::HexagonInstrInfo | |
| mayBeCurLoad(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| mayBeNewStore(const MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| nonDbgBBSize(const MachineBasicBlock *BB) const | llvm::HexagonInstrInfo | |
| nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const | llvm::HexagonInstrInfo | |
| predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const | llvm::HexagonInstrInfo | |
| PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override | llvm::HexagonInstrInfo | |
| PredOpcodeHasJMP_c(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const | llvm::HexagonInstrInfo | |
| producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const | llvm::HexagonInstrInfo | |
| producesStall(const MachineInstr &MI, MachineBasicBlock::const_instr_iterator MII) const | llvm::HexagonInstrInfo | |
| reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const override | llvm::HexagonInstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::HexagonInstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::HexagonInstrInfo | |
| reversePrediction(unsigned Opcode) const | llvm::HexagonInstrInfo | |
| reversePredSense(MachineInstr &MI) const | llvm::HexagonInstrInfo | |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override | llvm::HexagonInstrInfo | |
| SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override | llvm::HexagonInstrInfo | |
| validateBranchCond(const ArrayRef< MachineOperand > &Cond) const | llvm::HexagonInstrInfo | |
| xformRegToImmOffset(const MachineInstr &MI) const | llvm::HexagonInstrInfo |
1.8.6