47 #define DEBUG_TYPE "reginfo"
49 #define GET_REGINFO_TARGET_DESC
50 #include "PPCGenRegisterInfo.inc"
54 cl::desc(
"Enable use of a base pointer for complex stack frames"));
58 cl::desc(
"Force the use of a base pointer in every function"));
63 TM.isPPC64() ? 0 : 1),
65 ImmToIdxMap[
PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
83 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
84 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
85 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
86 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
87 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
88 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
89 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
90 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
91 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
92 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
104 return &PPC::G8RC_NOX0RegClass;
105 return &PPC::GPRC_NOR0RegClass;
109 return &PPC::G8RCRegClass;
110 return &PPC::GPRCRegClass;
118 return CSR_64_AllRegs_VSX_SaveList;
120 return CSR_64_AllRegs_Altivec_SaveList;
121 return CSR_64_AllRegs_SaveList;
126 ? (Subtarget.
hasAltivec() ? CSR_Darwin64_Altivec_SaveList
127 : CSR_Darwin64_SaveList)
128 : (Subtarget.
hasAltivec() ? CSR_Darwin32_Altivec_SaveList
129 : CSR_Darwin32_SaveList);
132 return CSR_SRV464_TLS_PE_SaveList;
139 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
140 : CSR_SVR464_Altivec_SaveList)
141 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
142 : (Subtarget.
hasAltivec() ? CSR_SVR432_Altivec_SaveList
143 : CSR_SVR432_SaveList);
148 assert(MF &&
"Invalid MachineFunction pointer.");
163 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList
164 : CSR_SVR464_Altivec_ViaCopy_SaveList;
167 ? CSR_SVR464_R2_ViaCopy_SaveList
168 : CSR_SVR464_ViaCopy_SaveList;
177 return CSR_64_AllRegs_VSX_RegMask;
179 return CSR_64_AllRegs_Altivec_RegMask;
180 return CSR_64_AllRegs_RegMask;
185 : CSR_Darwin64_RegMask)
186 : (Subtarget.
hasAltivec() ? CSR_Darwin32_Altivec_RegMask
187 : CSR_Darwin32_RegMask);
190 : CSR_SVR464_RegMask)
191 : (Subtarget.
hasAltivec() ? CSR_SVR432_Altivec_RegMask
192 : CSR_SVR432_RegMask);
197 return CSR_NoRegs_RegMask;
201 for (
unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8,
PPC::RM})
202 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
212 Reserved.
set(PPC::ZERO);
213 Reserved.
set(PPC::ZERO8);
217 Reserved.
set(PPC::FP);
218 Reserved.
set(PPC::FP8);
222 Reserved.
set(PPC::BP);
223 Reserved.
set(PPC::BP8);
227 Reserved.
set(PPC::CTR);
228 Reserved.
set(PPC::CTR8);
230 Reserved.
set(PPC::R1);
231 Reserved.
set(PPC::LR);
232 Reserved.
set(PPC::LR8);
236 Reserved.
set(PPC::VRSAVE);
241 Reserved.
set(PPC::R13);
246 Reserved.
set(PPC::R13);
248 Reserved.
set(PPC::X1);
249 Reserved.
set(PPC::X13);
251 if (TFI->needsFP(MF))
252 Reserved.
set(PPC::X31);
255 Reserved.
set(PPC::X30);
266 Reserved.
set(PPC::X2);
272 if (TFI->needsFP(MF))
273 Reserved.
set(PPC::R31);
278 Reserved.
set(PPC::R29);
280 Reserved.
set(PPC::R30);
284 Reserved.
set(PPC::R30);
289 IE = PPC::VRRCRegClass.end();
I !=
IE; ++
I)
298 const unsigned DefaultSafety = 1;
300 switch (RC->
getID()) {
303 case PPC::G8RC_NOX0RegClassID:
304 case PPC::GPRC_NOR0RegClassID:
305 case PPC::G8RCRegClassID:
306 case PPC::GPRCRegClassID: {
307 unsigned FP = TFI->
hasFP(MF) ? 1 : 0;
308 return 32 - FP - DefaultSafety;
310 case PPC::F8RCRegClassID:
311 case PPC::F4RCRegClassID:
312 case PPC::QFRCRegClassID:
313 case PPC::QSRCRegClassID:
314 case PPC::QBRCRegClassID:
315 case PPC::VRRCRegClassID:
316 case PPC::VFRCRegClassID:
317 case PPC::VSLRCRegClassID:
318 return 32 - DefaultSafety;
319 case PPC::VSRCRegClassID:
320 case PPC::VSFRCRegClassID:
321 case PPC::VSSRCRegClassID:
322 return 64 - DefaultSafety;
323 case PPC::CRRCRegClassID:
324 return 8 - DefaultSafety;
336 if (RC == &PPC::F8RCRegClass)
337 return &PPC::VSFRCRegClass;
338 else if (RC == &PPC::VRRCRegClass)
339 return &PPC::VSRCRegClass;
340 else if (RC == &PPC::F4RCRegClass && Subtarget.
hasP8Vector())
341 return &PPC::VSSRCRegClass;
383 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
384 "Maximum call-frame size not sufficiently aligned");
396 if (MaxAlign < TargetAlign &&
isInt<16>(FrameSize)) {
416 if (MaxAlign > TargetAlign) {
417 unsigned UnalNegSizeReg = NegSizeReg;
422 BuildMI(MBB, II, dl, TII.
get(PPC::LI8), NegSizeReg)
423 .addImm(~(MaxAlign-1));
425 unsigned NegSizeReg1 = NegSizeReg;
427 BuildMI(MBB, II, dl, TII.
get(PPC::AND8), NegSizeReg)
430 KillNegSizeReg =
true;
433 BuildMI(MBB, II, dl, TII.
get(PPC::STDUX), PPC::X1)
439 .
addImm(maxCallFrameSize);
441 if (MaxAlign > TargetAlign) {
442 unsigned UnalNegSizeReg = NegSizeReg;
447 BuildMI(MBB, II, dl, TII.
get(PPC::LI), NegSizeReg)
448 .addImm(~(MaxAlign-1));
450 unsigned NegSizeReg1 = NegSizeReg;
455 KillNegSizeReg =
true;
458 BuildMI(MBB, II, dl, TII.
get(PPC::STWUX), PPC::R1)
464 .
addImm(maxCallFrameSize);
488 .addImm(maxCallFrameSize);
525 if (SrcReg != PPC::CR0) {
530 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
532 .
addImm(getEncodingValue(SrcReg) * 4)
563 "RESTORE_CR does not define its destination");
570 if (DestReg != PPC::CR0) {
574 unsigned ShiftBits = getEncodingValue(DestReg)*4;
576 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
581 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
619 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWINM8 : PPC::RLWINM),
Reg)
621 .
addImm(getEncodingValue(SrcReg))
650 "RESTORE_CRBIT does not define its destination");
655 BuildMI(MBB, II, dl, TII.
get(TargetOpcode::IMPLICIT_DEF), DestReg);
661 unsigned ShiftBits = getEncodingValue(DestReg);
663 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
666 .
addImm(ShiftBits ? 32 - ShiftBits : 0)
670 BuildMI(MBB, II, dl, TII.
get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
723 "RESTORE_VRSAVE does not define its destination");
728 BuildMI(MBB, II, dl, TII.
get(PPC::MTVRSAVEv), DestReg)
736 unsigned Reg,
int &FrameIdx)
const {
743 if (Subtarget.
isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
773 unsigned FIOperandNum) {
775 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
777 OffsetOperandNo = FIOperandNum - 1;
778 else if (MI.
getOpcode() == TargetOpcode::STACKMAP ||
779 MI.
getOpcode() == TargetOpcode::PATCHPOINT)
780 OffsetOperandNo = FIOperandNum + 1;
782 return OffsetOperandNo;
787 int SPAdj,
unsigned FIOperandNum,
789 assert(SPAdj == 0 &&
"Unexpected");
822 if (FPSI && FrameIndex == FPSI &&
829 if (OpC == PPC::SPILL_CR) {
832 }
else if (OpC == PPC::RESTORE_CR) {
835 }
else if (OpC == PPC::SPILL_CRBIT) {
838 }
else if (OpC == PPC::RESTORE_CRBIT) {
841 }
else if (OpC == PPC::SPILL_VRSAVE) {
844 }
else if (OpC == PPC::RESTORE_VRSAVE) {
858 bool noImmForm = !MI.
isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
859 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.
count(OpC);
882 assert(OpC != PPC::DBG_VALUE &&
883 "This should be handled in a target-independent way");
884 if (!noImmForm && ((
isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) ||
885 OpC == TargetOpcode::STACKMAP ||
886 OpC == TargetOpcode::PATCHPOINT)) {
902 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
903 .addImm(Offset >> 16);
904 BuildMI(MBB, II, dl, TII.
get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
912 unsigned OperandBase;
918 "No indexed form of load or store available!");
919 unsigned NewOpcode = ImmToIdxMap.
find(OpC)->second;
920 MI.
setDesc(TII.get(NewOpcode));
923 OperandBase = OffsetOperandNo;
935 return TFI->
hasFP(MF) ? PPC::R31 : PPC::R1;
937 return TFI->
hasFP(MF) ? PPC::X31 : PPC::X1;
963 return needsStackRealignment(MF);
972 assert(Offset < 0 &&
"Local offset must be negative");
984 if (!ImmToIdxMap.
count(OpC))
988 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1017 unsigned BaseReg,
int FrameIdx,
1019 unsigned ADDriOpc = TM.
isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1023 if (Ins != MBB->
end())
1024 DL = Ins->getDebugLoc();
1033 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
1039 unsigned FIOperandNum = 0;
1043 "Instr doesn't have FrameIndex operand!");
1058 TII.getRegClass(MCID, FIOperandNum,
this, MF));
1064 unsigned FIOperandNum = 0;
1067 assert(FIOperandNum < MI->getNumOperands() &&
1068 "Instr doesn't have FrameIndex operand!");
1074 return MI->
getOpcode() == PPC::DBG_VALUE ||
1075 MI->
getOpcode() == TargetOpcode::STACKMAP ||
1076 MI->
getOpcode() == TargetOpcode::PATCHPOINT ||
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
Describe properties that are true of each instruction in the target description file.
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
unsigned getID() const
Return the register class ID number.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const_iterator begin(StringRef path)
Get begin iterator over path.
constexpr bool isInt< 16 >(int64_t x)
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * iterator
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
DILocation * get() const
Get the underlying DILocation.
const HexagonInstrInfo * TII
static unsigned getOffsetONFromFION(const MachineInstr &MI, unsigned FIOperandNum)
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
int getFramePointerSaveIndex() const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const TargetRegisterClass * constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
This file declares the machine register scavenger class.
unsigned const MachineRegisterInfo * MRI
unsigned getBaseRegister(const MachineFunction &MF) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static bool is64Bit(const char *name)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
bool isPositionIndependent() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Common code between 32-bit and 64-bit PowerPC targets.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
const uint32_t * getNoPreservedMask() const override
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
static cl::opt< bool > AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Force the use of a base pointer in every function"))
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool usesIXAddr(const MachineInstr &MI)
const PPCInstrInfo * getInstrInfo() const override
bool test(unsigned Idx) const
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call...
bool isAllocatable(unsigned PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
unsigned determineFrameLayout(MachineFunction &MF, bool UpdateMF=true, bool UseEstimate=false) const
determineFrameLayout - Determine the size of the frame and maximum call frame size.
const MachineInstrBuilder & addFrameIndex(int Idx) const
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Bitwise operators - logical and, logical or, logical xor.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
iterator find(const KeyT &Val)
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
static cl::opt< bool > EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
int getCRSpillFrameIndex() const
bool usesTOCBasePtr() const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool hasBasePointer(const MachineFunction &MF) const
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override