LLVM  4.0.0
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMAsmPrinter.h"
16 #include "ARM.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DebugInfo.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCSectionMachO.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/COFF.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ELF.h"
54 #include <cctype>
55 using namespace llvm;
56 
57 #define DEBUG_TYPE "asm-printer"
58 
60  std::unique_ptr<MCStreamer> Streamer)
61  : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
62  InConstantPool(false), OptimizationGoals(-1) {}
63 
65  // Make sure to terminate any constant pools that were at the end
66  // of the function.
67  if (!InConstantPool)
68  return;
69  InConstantPool = false;
70  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
71 }
72 
74  if (AFI->isThumbFunction()) {
75  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
76  OutStreamer->EmitThumbFunc(CurrentFnSym);
77  } else {
78  OutStreamer->EmitAssemblerFlag(MCAF_Code32);
79  }
80  OutStreamer->EmitLabel(CurrentFnSym);
81 }
82 
84  uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
85  assert(Size && "C++ constructor pointer had zero size!");
86 
88  assert(GV && "C++ constructor pointer was not a GlobalValue!");
89 
90  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
92  (Subtarget->isTargetELF()
95  OutContext);
96 
97  OutStreamer->EmitValue(E, Size);
98 }
99 
101  if (PromotedGlobals.count(GV))
102  // The global was promoted into a constant pool. It should not be emitted.
103  return;
105 }
106 
107 /// runOnMachineFunction - This uses the EmitInstruction()
108 /// method to print assembly for each instruction.
109 ///
111  AFI = MF.getInfo<ARMFunctionInfo>();
112  MCP = MF.getConstantPool();
113  Subtarget = &MF.getSubtarget<ARMSubtarget>();
114 
116  const Function* F = MF.getFunction();
117  const TargetMachine& TM = MF.getTarget();
118 
119  // Collect all globals that had their storage promoted to a constant pool.
120  // Functions are emitted before variables, so this accumulates promoted
121  // globals from all functions in PromotedGlobals.
122  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
123  PromotedGlobals.insert(GV);
124 
125  // Calculate this function's optimization goal.
126  unsigned OptimizationGoal;
127  if (F->hasFnAttribute(Attribute::OptimizeNone))
128  // For best debugging illusion, speed and small size sacrificed
129  OptimizationGoal = 6;
130  else if (F->optForMinSize())
131  // Aggressively for small size, speed and debug illusion sacrificed
132  OptimizationGoal = 4;
133  else if (F->optForSize())
134  // For small size, but speed and debugging illusion preserved
135  OptimizationGoal = 3;
136  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
137  // Aggressively for speed, small size and debug illusion sacrificed
138  OptimizationGoal = 2;
139  else if (TM.getOptLevel() > CodeGenOpt::None)
140  // For speed, but small size and good debug illusion preserved
141  OptimizationGoal = 1;
142  else // TM.getOptLevel() == CodeGenOpt::None
143  // For good debugging, but speed and small size preserved
144  OptimizationGoal = 5;
145 
146  // Combine a new optimization goal with existing ones.
147  if (OptimizationGoals == -1) // uninitialized goals
148  OptimizationGoals = OptimizationGoal;
149  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
150  OptimizationGoals = 0;
151 
152  if (Subtarget->isTargetCOFF()) {
153  bool Internal = F->hasInternalLinkage();
157 
158  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
159  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
160  OutStreamer->EmitCOFFSymbolType(Type);
161  OutStreamer->EndCOFFSymbolDef();
162  }
163 
164  // Emit the rest of the function body.
166 
167  // Emit the XRay table for this function.
168  emitXRayTable();
169 
170  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
171  // These are created per function, rather than per TU, since it's
172  // relatively easy to exceed the thumb branch range within a TU.
173  if (! ThumbIndirectPads.empty()) {
174  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
175  EmitAlignment(1);
176  for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
177  OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
179  .addReg(ThumbIndirectPads[i].first)
180  // Add predicate operands.
181  .addImm(ARMCC::AL)
182  .addReg(0));
183  }
184  ThumbIndirectPads.clear();
185  }
186 
187  // We didn't modify anything.
188  return false;
189 }
190 
192  raw_ostream &O) {
193  const MachineOperand &MO = MI->getOperand(OpNum);
194  unsigned TF = MO.getTargetFlags();
195 
196  switch (MO.getType()) {
197  default: llvm_unreachable("<unknown operand type>");
199  unsigned Reg = MO.getReg();
201  assert(!MO.getSubReg() && "Subregs should be eliminated!");
202  if(ARM::GPRPairRegClass.contains(Reg)) {
203  const MachineFunction &MF = *MI->getParent()->getParent();
204  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
205  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
206  }
208  break;
209  }
211  int64_t Imm = MO.getImm();
212  O << '#';
213  if (TF == ARMII::MO_LO16)
214  O << ":lower16:";
215  else if (TF == ARMII::MO_HI16)
216  O << ":upper16:";
217  O << Imm;
218  break;
219  }
221  MO.getMBB()->getSymbol()->print(O, MAI);
222  return;
224  const GlobalValue *GV = MO.getGlobal();
225  if (TF & ARMII::MO_LO16)
226  O << ":lower16:";
227  else if (TF & ARMII::MO_HI16)
228  O << ":upper16:";
229  GetARMGVSymbol(GV, TF)->print(O, MAI);
230 
231  printOffset(MO.getOffset(), O);
232  break;
233  }
235  if (Subtarget->genExecuteOnly())
236  llvm_unreachable("execute-only should not generate constant pools");
237  GetCPISymbol(MO.getIndex())->print(O, MAI);
238  break;
239  }
240 }
241 
242 //===--------------------------------------------------------------------===//
243 
244 MCSymbol *ARMAsmPrinter::
245 GetARMJTIPICJumpTableLabel(unsigned uid) const {
246  const DataLayout &DL = getDataLayout();
248  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
249  << getFunctionNumber() << '_' << uid;
250  return OutContext.getOrCreateSymbol(Name);
251 }
252 
253 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
254  unsigned AsmVariant, const char *ExtraCode,
255  raw_ostream &O) {
256  // Does this asm operand have a single letter operand modifier?
257  if (ExtraCode && ExtraCode[0]) {
258  if (ExtraCode[1] != 0) return true; // Unknown modifier.
259 
260  switch (ExtraCode[0]) {
261  default:
262  // See if this is a generic print operand
263  return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
264  case 'a': // Print as a memory address.
265  if (MI->getOperand(OpNum).isReg()) {
266  O << "["
268  << "]";
269  return false;
270  }
272  case 'c': // Don't print "#" before an immediate operand.
273  if (!MI->getOperand(OpNum).isImm())
274  return true;
275  O << MI->getOperand(OpNum).getImm();
276  return false;
277  case 'P': // Print a VFP double precision register.
278  case 'q': // Print a NEON quad precision register.
279  printOperand(MI, OpNum, O);
280  return false;
281  case 'y': // Print a VFP single precision register as indexed double.
282  if (MI->getOperand(OpNum).isReg()) {
283  unsigned Reg = MI->getOperand(OpNum).getReg();
285  // Find the 'd' register that has this 's' register as a sub-register,
286  // and determine the lane number.
287  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
288  if (!ARM::DPRRegClass.contains(*SR))
289  continue;
290  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
291  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
292  return false;
293  }
294  }
295  return true;
296  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
297  if (!MI->getOperand(OpNum).isImm())
298  return true;
299  O << ~(MI->getOperand(OpNum).getImm());
300  return false;
301  case 'L': // The low 16 bits of an immediate constant.
302  if (!MI->getOperand(OpNum).isImm())
303  return true;
304  O << (MI->getOperand(OpNum).getImm() & 0xffff);
305  return false;
306  case 'M': { // A register range suitable for LDM/STM.
307  if (!MI->getOperand(OpNum).isReg())
308  return true;
309  const MachineOperand &MO = MI->getOperand(OpNum);
310  unsigned RegBegin = MO.getReg();
311  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
312  // already got the operands in registers that are operands to the
313  // inline asm statement.
314  O << "{";
315  if (ARM::GPRPairRegClass.contains(RegBegin)) {
317  unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
318  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
319  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
320  }
321  O << ARMInstPrinter::getRegisterName(RegBegin);
322 
323  // FIXME: The register allocator not only may not have given us the
324  // registers in sequence, but may not be in ascending registers. This
325  // will require changes in the register allocator that'll need to be
326  // propagated down here if the operands change.
327  unsigned RegOps = OpNum + 1;
328  while (MI->getOperand(RegOps).isReg()) {
329  O << ", "
331  RegOps++;
332  }
333 
334  O << "}";
335 
336  return false;
337  }
338  case 'R': // The most significant register of a pair.
339  case 'Q': { // The least significant register of a pair.
340  if (OpNum == 0)
341  return true;
342  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
343  if (!FlagsOP.isImm())
344  return true;
345  unsigned Flags = FlagsOP.getImm();
346 
347  // This operand may not be the one that actually provides the register. If
348  // it's tied to a previous one then we should refer instead to that one
349  // for registers and their classes.
350  unsigned TiedIdx;
351  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
352  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
353  unsigned OpFlags = MI->getOperand(OpNum).getImm();
354  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
355  }
356  Flags = MI->getOperand(OpNum).getImm();
357 
358  // Later code expects OpNum to be pointing at the register rather than
359  // the flags.
360  OpNum += 1;
361  }
362 
363  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
364  unsigned RC;
366  if (RC == ARM::GPRPairRegClassID) {
367  if (NumVals != 1)
368  return true;
369  const MachineOperand &MO = MI->getOperand(OpNum);
370  if (!MO.isReg())
371  return true;
373  unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
374  ARM::gsub_0 : ARM::gsub_1);
376  return false;
377  }
378  if (NumVals != 2)
379  return true;
380  unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
381  if (RegOp >= MI->getNumOperands())
382  return true;
383  const MachineOperand &MO = MI->getOperand(RegOp);
384  if (!MO.isReg())
385  return true;
386  unsigned Reg = MO.getReg();
388  return false;
389  }
390 
391  case 'e': // The low doubleword register of a NEON quad register.
392  case 'f': { // The high doubleword register of a NEON quad register.
393  if (!MI->getOperand(OpNum).isReg())
394  return true;
395  unsigned Reg = MI->getOperand(OpNum).getReg();
396  if (!ARM::QPRRegClass.contains(Reg))
397  return true;
399  unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
400  ARM::dsub_0 : ARM::dsub_1);
401  O << ARMInstPrinter::getRegisterName(SubReg);
402  return false;
403  }
404 
405  // This modifier is not yet supported.
406  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
407  return true;
408  case 'H': { // The highest-numbered register of a pair.
409  const MachineOperand &MO = MI->getOperand(OpNum);
410  if (!MO.isReg())
411  return true;
412  const MachineFunction &MF = *MI->getParent()->getParent();
413  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
414  unsigned Reg = MO.getReg();
415  if(!ARM::GPRPairRegClass.contains(Reg))
416  return false;
417  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
419  return false;
420  }
421  }
422  }
423 
424  printOperand(MI, OpNum, O);
425  return false;
426 }
427 
429  unsigned OpNum, unsigned AsmVariant,
430  const char *ExtraCode,
431  raw_ostream &O) {
432  // Does this asm operand have a single letter operand modifier?
433  if (ExtraCode && ExtraCode[0]) {
434  if (ExtraCode[1] != 0) return true; // Unknown modifier.
435 
436  switch (ExtraCode[0]) {
437  case 'A': // A memory operand for a VLD1/VST1 instruction.
438  default: return true; // Unknown modifier.
439  case 'm': // The base register of a memory operand.
440  if (!MI->getOperand(OpNum).isReg())
441  return true;
443  return false;
444  }
445  }
446 
447  const MachineOperand &MO = MI->getOperand(OpNum);
448  assert(MO.isReg() && "unexpected inline asm memory operand");
449  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
450  return false;
451 }
452 
453 static bool isThumb(const MCSubtargetInfo& STI) {
454  return STI.getFeatureBits()[ARM::ModeThumb];
455 }
456 
458  const MCSubtargetInfo *EndInfo) const {
459  // If either end mode is unknown (EndInfo == NULL) or different than
460  // the start mode, then restore the start mode.
461  const bool WasThumb = isThumb(StartInfo);
462  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
463  OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
464  }
465 }
466 
468  const Triple &TT = TM.getTargetTriple();
469  // Use unified assembler syntax.
470  OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
471 
472  // Emit ARM Build Attributes
473  if (TT.isOSBinFormatELF())
474  emitAttributes();
475 
476  // Use the triple's architecture and subarchitecture to determine
477  // if we're thumb for the purposes of the top level code16 assembler
478  // flag.
479  bool isThumb = TT.getArch() == Triple::thumb ||
480  TT.getArch() == Triple::thumbeb ||
483  if (!M.getModuleInlineAsm().empty() && isThumb)
484  OutStreamer->EmitAssemblerFlag(MCAF_Code16);
485 }
486 
487 static void
490  // L_foo$stub:
491  OutStreamer.EmitLabel(StubLabel);
492  // .indirect_symbol _foo
493  OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
494 
495  if (MCSym.getInt())
496  // External to current translation unit.
497  OutStreamer.EmitIntValue(0, 4/*size*/);
498  else
499  // Internal to current translation unit.
500  //
501  // When we place the LSDA into the TEXT section, the type info
502  // pointers need to be indirect and pc-rel. We accomplish this by
503  // using NLPs; however, sometimes the types are local to the file.
504  // We need to fill in the value for the NLP in those cases.
505  OutStreamer.EmitValue(
506  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
507  4 /*size*/);
508 }
509 
510 
512  const Triple &TT = TM.getTargetTriple();
513  if (TT.isOSBinFormatMachO()) {
514  // All darwin targets use mach-o.
515  const TargetLoweringObjectFileMachO &TLOFMacho =
516  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
517  MachineModuleInfoMachO &MMIMacho =
519 
520  // Output non-lazy-pointers for external and common global variables.
522 
523  if (!Stubs.empty()) {
524  // Switch with ".non_lazy_symbol_pointer" directive.
525  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
526  EmitAlignment(2);
527 
528  for (auto &Stub : Stubs)
529  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
530 
531  Stubs.clear();
532  OutStreamer->AddBlankLine();
533  }
534 
535  Stubs = MMIMacho.GetThreadLocalGVStubList();
536  if (!Stubs.empty()) {
537  // Switch with ".non_lazy_symbol_pointer" directive.
538  OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
539  EmitAlignment(2);
540 
541  for (auto &Stub : Stubs)
542  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
543 
544  Stubs.clear();
545  OutStreamer->AddBlankLine();
546  }
547 
548  // Funny Darwin hack: This flag tells the linker that no global symbols
549  // contain code that falls through to other global symbols (e.g. the obvious
550  // implementation of multiple entry points). If this doesn't occur, the
551  // linker can safely perform dead code stripping. Since LLVM never
552  // generates code that does this, it is always safe to set.
553  OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
554  }
555 
556  if (TT.isOSBinFormatCOFF()) {
557  const auto &TLOF =
558  static_cast<const TargetLoweringObjectFileCOFF &>(getObjFileLowering());
559 
560  std::string Flags;
561  raw_string_ostream OS(Flags);
562 
563  for (const auto &Function : M)
564  TLOF.emitLinkerFlagsForGlobal(OS, &Function);
565  for (const auto &Global : M.globals())
566  TLOF.emitLinkerFlagsForGlobal(OS, &Global);
567  for (const auto &Alias : M.aliases())
568  TLOF.emitLinkerFlagsForGlobal(OS, &Alias);
569 
570  OS.flush();
571 
572  // Output collected flags
573  if (!Flags.empty()) {
574  OutStreamer->SwitchSection(TLOF.getDrectveSection());
575  OutStreamer->EmitBytes(Flags);
576  }
577  }
578 
579  // The last attribute to be emitted is ABI_optimization_goals
580  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
581  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
582 
583  if (OptimizationGoals > 0 &&
584  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
585  Subtarget->isTargetMuslAEABI()))
587  OptimizationGoals = -1;
588 
590 }
591 
592 static bool isV8M(const ARMSubtarget *Subtarget) {
593  // Note that v8M Baseline is a subset of v6T2!
594  return (Subtarget->hasV8MBaselineOps() && !Subtarget->hasV6T2Ops()) ||
595  Subtarget->hasV8MMainlineOps();
596 }
597 
598 //===----------------------------------------------------------------------===//
599 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
600 // FIXME:
601 // The following seem like one-off assembler flags, but they actually need
602 // to appear in the .ARM.attributes section in ELF.
603 // Instead of subclassing the MCELFStreamer, we do the work here.
604 
606  const ARMSubtarget *Subtarget) {
607  if (CPU == "xscale")
608  return ARMBuildAttrs::v5TEJ;
609 
610  if (Subtarget->hasV8Ops()) {
611  if (Subtarget->isRClass())
612  return ARMBuildAttrs::v8_R;
613  return ARMBuildAttrs::v8_A;
614  } else if (Subtarget->hasV8MMainlineOps())
616  else if (Subtarget->hasV7Ops()) {
617  if (Subtarget->isMClass() && Subtarget->hasDSP())
618  return ARMBuildAttrs::v7E_M;
619  return ARMBuildAttrs::v7;
620  } else if (Subtarget->hasV6T2Ops())
621  return ARMBuildAttrs::v6T2;
622  else if (Subtarget->hasV8MBaselineOps())
624  else if (Subtarget->hasV6MOps())
625  return ARMBuildAttrs::v6S_M;
626  else if (Subtarget->hasV6Ops())
627  return ARMBuildAttrs::v6;
628  else if (Subtarget->hasV5TEOps())
629  return ARMBuildAttrs::v5TE;
630  else if (Subtarget->hasV5TOps())
631  return ARMBuildAttrs::v5T;
632  else if (Subtarget->hasV4TOps())
633  return ARMBuildAttrs::v4T;
634  else
635  return ARMBuildAttrs::v4;
636 }
637 
638 // Returns true if all functions have the same function attribute value.
639 // It also returns true when the module has no functions.
641  StringRef Value) {
642  return !any_of(M, [&](const Function &F) {
643  return F.getFnAttribute(Attr).getValueAsString() != Value;
644  });
645 }
646 
647 void ARMAsmPrinter::emitAttributes() {
648  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
649  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
650 
652 
653  ATS.switchVendor("aeabi");
654 
655  // Compute ARM ELF Attributes based on the default subtarget that
656  // we'd have constructed. The existing ARM behavior isn't LTO clean
657  // anyhow.
658  // FIXME: For ifunc related functions we could iterate over and look
659  // for a feature string that doesn't match the default one.
660  const Triple &TT = TM.getTargetTriple();
661  StringRef CPU = TM.getTargetCPU();
663  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
664  if (!FS.empty()) {
665  if (!ArchFS.empty())
666  ArchFS = (Twine(ArchFS) + "," + FS).str();
667  else
668  ArchFS = FS;
669  }
670  const ARMBaseTargetMachine &ATM =
671  static_cast<const ARMBaseTargetMachine &>(TM);
672  const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
673 
674  const std::string &CPUString = STI.getCPUString();
675 
676  if (!StringRef(CPUString).startswith("generic")) {
677  // FIXME: remove krait check when GNU tools support krait cpu
678  if (STI.isKrait()) {
679  ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
680  // We consider krait as a "cortex-a9" + hwdiv CPU
681  // Enable hwdiv through ".arch_extension idiv"
682  if (STI.hasDivide() || STI.hasDivideInARMMode())
684  } else
686  }
687 
688  ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
689 
690  // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
691  // profile is not applicable (e.g. pre v7, or cross-profile code)".
692  if (STI.hasV7Ops() || isV8M(&STI)) {
693  if (STI.isAClass()) {
696  } else if (STI.isRClass()) {
699  } else if (STI.isMClass()) {
702  }
703  }
704 
706  STI.hasARMOps() ? ARMBuildAttrs::Allowed
708  if (isV8M(&STI)) {
711  } else if (STI.isThumb1Only()) {
713  } else if (STI.hasThumb2()) {
716  }
717 
718  if (STI.hasNEON()) {
719  /* NEON is not exactly a VFP architecture, but GAS emit one of
720  * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
721  if (STI.hasFPARMv8()) {
722  if (STI.hasCrypto())
723  ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
724  else
725  ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
726  } else if (STI.hasVFP4())
727  ATS.emitFPU(ARM::FK_NEON_VFPV4);
728  else
729  ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
730  // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
731  if (STI.hasV8Ops())
733  STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
735  } else {
736  if (STI.hasFPARMv8())
737  // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
738  // FPU, but there are two different names for it depending on the CPU.
739  ATS.emitFPU(STI.hasD16()
740  ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
741  : ARM::FK_FP_ARMV8);
742  else if (STI.hasVFP4())
743  ATS.emitFPU(STI.hasD16()
744  ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
745  : ARM::FK_VFPV4);
746  else if (STI.hasVFP3())
747  ATS.emitFPU(STI.hasD16()
748  // +d16
749  ? (STI.isFPOnlySP()
750  ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
751  : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
752  // -d16
753  : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
754  else if (STI.hasVFP2())
755  ATS.emitFPU(ARM::FK_VFPV2);
756  }
757 
758  // RW data addressing.
759  if (isPositionIndependent()) {
762  } else if (STI.isRWPI()) {
763  // RWPI specific attributes.
766  }
767 
768  // RO data addressing.
769  if (isPositionIndependent() || STI.isROPI()) {
772  }
773 
774  // GOT use.
775  if (isPositionIndependent()) {
778  } else {
781  }
782 
783  // Set FP Denormals.
785  "denormal-fp-math",
786  "preserve-sign") ||
791  "denormal-fp-math",
792  "positive-zero") ||
796  else if (!TM.Options.UnsafeFPMath)
799  else {
800  if (!STI.hasVFP2()) {
801  // When the target doesn't have an FPU (by design or
802  // intention), the assumptions made on the software support
803  // mirror that of the equivalent hardware support *if it
804  // existed*. For v7 and better we indicate that denormals are
805  // flushed preserving sign, and for V6 we indicate that
806  // denormals are flushed to positive zero.
807  if (STI.hasV7Ops())
810  } else if (STI.hasVFP3()) {
811  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
812  // the sign bit of the zero matches the sign bit of the input or
813  // result that is being flushed to zero.
816  }
817  // For VFPv2 implementations it is implementation defined as
818  // to whether denormals are flushed to positive zero or to
819  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
820  // LLVM has chosen to flush this to positive zero (most likely for
821  // GCC compatibility), so that's the chosen value here (the
822  // absence of its emission implies zero).
823  }
824 
825  // Set FP exceptions and rounding
827  "no-trapping-math", "true") ||
831  else if (!TM.Options.UnsafeFPMath) {
833 
834  // If the user has permitted this code to choose the IEEE 754
835  // rounding at run-time, emit the rounding attribute.
838  }
839 
840  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
841  // equivalent of GCC's -ffinite-math-only flag.
845  else
848 
849  if (STI.allowsUnalignedMem())
852  else
855 
856  // FIXME: add more flags to ARMBuildAttributes.h
857  // 8-bytes alignment stuff.
860 
861  // ABI_HardFP_use attribute to indicate single precision FP.
862  if (STI.isFPOnlySP())
865 
866  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
867  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
869 
870  // FIXME: Should we signal R9 usage?
871 
872  if (STI.hasFP16())
874 
875  // FIXME: To support emitting this build attribute as GCC does, the
876  // -mfp16-format option and associated plumbing must be
877  // supported. For now the __fp16 type is exposed by default, so this
878  // attribute should be emitted with value 1.
881 
882  if (STI.hasMPExtension())
884 
885  // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
886  // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
887  // It is not possible to produce DisallowDIV: if hwdiv is present in the base
888  // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
889  // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
890  // otherwise, the default value (AllowDIVIfExists) applies.
891  if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
893 
894  if (STI.hasDSP() && isV8M(&STI))
896 
897  if (MMI) {
898  if (const Module *SourceModule = MMI->getModule()) {
899  // ABI_PCS_wchar_t to indicate wchar_t width
900  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
901  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
902  SourceModule->getModuleFlag("wchar_size"))) {
903  int WCharWidth = WCharWidthValue->getZExtValue();
904  assert((WCharWidth == 2 || WCharWidth == 4) &&
905  "wchar_t width must be 2 or 4 bytes");
907  }
908 
909  // ABI_enum_size to indicate enum width
910  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
911  // (all enums contain a value needing 32 bits to encode).
912  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
913  SourceModule->getModuleFlag("min_enum_size"))) {
914  int EnumWidth = EnumWidthValue->getZExtValue();
915  assert((EnumWidth == 1 || EnumWidth == 4) &&
916  "Minimum enum width must be 1 or 4 bytes");
917  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
918  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
919  }
920  }
921  }
922 
923  // We currently do not support using R9 as the TLS pointer.
924  if (STI.isRWPI())
927  else if (STI.isR9Reserved())
930  else
933 
934  if (STI.hasTrustZone() && STI.hasVirtualization())
937  else if (STI.hasTrustZone())
940  else if (STI.hasVirtualization())
943 }
944 
945 //===----------------------------------------------------------------------===//
946 
948  unsigned LabelId, MCContext &Ctx) {
949 
950  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
951  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
952  return Label;
953 }
954 
957  switch (Modifier) {
958  case ARMCP::no_modifier:
960  case ARMCP::TLSGD:
962  case ARMCP::TPOFF:
964  case ARMCP::GOTTPOFF:
966  case ARMCP::SBREL:
968  case ARMCP::GOT_PREL:
970  case ARMCP::SECREL:
972  }
973  llvm_unreachable("Invalid ARMCPModifier!");
974 }
975 
976 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
977  unsigned char TargetFlags) {
978  if (Subtarget->isTargetMachO()) {
979  bool IsIndirect =
980  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
981 
982  if (!IsIndirect)
983  return getSymbol(GV);
984 
985  // FIXME: Remove this when Darwin transition to @GOT like syntax.
986  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
987  MachineModuleInfoMachO &MMIMachO =
990  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
991  : MMIMachO.getGVStubEntry(MCSym);
992 
993  if (!StubSym.getPointer())
995  !GV->hasInternalLinkage());
996  return MCSym;
997  } else if (Subtarget->isTargetCOFF()) {
998  assert(Subtarget->isTargetWindows() &&
999  "Windows is the only supported COFF target");
1000 
1001  bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
1002  if (!IsIndirect)
1003  return getSymbol(GV);
1004 
1006  Name = "__imp_";
1007  getNameWithPrefix(Name, GV);
1008 
1009  return OutContext.getOrCreateSymbol(Name);
1010  } else if (Subtarget->isTargetELF()) {
1011  return getSymbol(GV);
1012  }
1013  llvm_unreachable("unexpected target");
1014 }
1015 
1016 void ARMAsmPrinter::
1018  const DataLayout &DL = getDataLayout();
1019  int Size = DL.getTypeAllocSize(MCPV->getType());
1020 
1021  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
1022 
1023  if (ACPV->isPromotedGlobal()) {
1024  // This constant pool entry is actually a global whose storage has been
1025  // promoted into the constant pool. This global may be referenced still
1026  // by debug information, and due to the way AsmPrinter is set up, the debug
1027  // info is immutable by the time we decide to promote globals to constant
1028  // pools. Because of this, we need to ensure we emit a symbol for the global
1029  // with private linkage (the default) so debug info can refer to it.
1030  //
1031  // However, if this global is promoted into several functions we must ensure
1032  // we don't try and emit duplicate symbols!
1033  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
1034  auto *GV = ACPC->getPromotedGlobal();
1035  if (!EmittedPromotedGlobalLabels.count(GV)) {
1036  MCSymbol *GVSym = getSymbol(GV);
1037  OutStreamer->EmitLabel(GVSym);
1038  EmittedPromotedGlobalLabels.insert(GV);
1039  }
1040  return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
1041  }
1042 
1043  MCSymbol *MCSym;
1044  if (ACPV->isLSDA()) {
1045  MCSym = getCurExceptionSym();
1046  } else if (ACPV->isBlockAddress()) {
1047  const BlockAddress *BA =
1048  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
1049  MCSym = GetBlockAddressSymbol(BA);
1050  } else if (ACPV->isGlobalValue()) {
1051  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
1052 
1053  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
1054  // flag the global as MO_NONLAZY.
1055  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
1056  MCSym = GetARMGVSymbol(GV, TF);
1057  } else if (ACPV->isMachineBasicBlock()) {
1058  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
1059  MCSym = MBB->getSymbol();
1060  } else {
1061  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
1062  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
1063  MCSym = GetExternalSymbolSymbol(Sym);
1064  }
1065 
1066  // Create an MCSymbol for the reference.
1067  const MCExpr *Expr =
1069  OutContext);
1070 
1071  if (ACPV->getPCAdjustment()) {
1072  MCSymbol *PCLabel =
1074  ACPV->getLabelId(), OutContext);
1075  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
1076  PCRelExpr =
1077  MCBinaryExpr::createAdd(PCRelExpr,
1079  OutContext),
1080  OutContext);
1081  if (ACPV->mustAddCurrentAddress()) {
1082  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
1083  // label, so just emit a local label end reference that instead.
1084  MCSymbol *DotSym = OutContext.createTempSymbol();
1085  OutStreamer->EmitLabel(DotSym);
1086  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1087  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
1088  }
1089  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
1090  }
1091  OutStreamer->EmitValue(Expr, Size);
1092 }
1093 
1095  const MachineOperand &MO1 = MI->getOperand(1);
1096  unsigned JTI = MO1.getIndex();
1097 
1098  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1099  // ARM mode tables.
1100  EmitAlignment(2);
1101 
1102  // Emit a label for the jump table.
1103  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1104  OutStreamer->EmitLabel(JTISymbol);
1105 
1106  // Mark the jump table as data-in-code.
1107  OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
1108 
1109  // Emit each entry of the table.
1110  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1111  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1112  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1113 
1114  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1115  MachineBasicBlock *MBB = JTBBs[i];
1116  // Construct an MCExpr for the entry. We want a value of the form:
1117  // (BasicBlockAddr - TableBeginAddr)
1118  //
1119  // For example, a table with entries jumping to basic blocks BB0 and BB1
1120  // would look like:
1121  // LJTI_0_0:
1122  // .word (LBB0 - LJTI_0_0)
1123  // .word (LBB1 - LJTI_0_0)
1124  const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
1125 
1126  if (isPositionIndependent() || Subtarget->isROPI())
1127  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
1128  OutContext),
1129  OutContext);
1130  // If we're generating a table of Thumb addresses in static relocation
1131  // model, we need to add one to keep interworking correctly.
1132  else if (AFI->isThumbFunction())
1134  OutContext);
1135  OutStreamer->EmitValue(Expr, 4);
1136  }
1137  // Mark the end of jump table data-in-code region.
1138  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1139 }
1140 
1142  const MachineOperand &MO1 = MI->getOperand(1);
1143  unsigned JTI = MO1.getIndex();
1144 
1145  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1146  OutStreamer->EmitLabel(JTISymbol);
1147 
1148  // Emit each entry of the table.
1149  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1150  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1151  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1152 
1153  for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1154  MachineBasicBlock *MBB = JTBBs[i];
1155  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1156  OutContext);
1157  // If this isn't a TBB or TBH, the entries are direct branch instructions.
1159  .addExpr(MBBSymbolExpr)
1160  .addImm(ARMCC::AL)
1161  .addReg(0));
1162  }
1163 }
1164 
1166  unsigned OffsetWidth) {
1167  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1168  const MachineOperand &MO1 = MI->getOperand(1);
1169  unsigned JTI = MO1.getIndex();
1170 
1171  if (Subtarget->isThumb1Only())
1172  EmitAlignment(2);
1173 
1174  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1175  OutStreamer->EmitLabel(JTISymbol);
1176 
1177  // Emit each entry of the table.
1178  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1179  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1180  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1181 
1182  // Mark the jump table as data-in-code.
1183  OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1185 
1186  for (auto MBB : JTBBs) {
1187  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1188  OutContext);
1189  // Otherwise it's an offset from the dispatch instruction. Construct an
1190  // MCExpr for the entry. We want a value of the form:
1191  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1192  //
1193  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1194  // would look like:
1195  // LJTI_0_0:
1196  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1197  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1198  // where LCPI0_0 is a label defined just before the TBB instruction using
1199  // this table.
1200  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1201  const MCExpr *Expr = MCBinaryExpr::createAdd(
1204  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1206  OutContext);
1207  OutStreamer->EmitValue(Expr, OffsetWidth);
1208  }
1209  // Mark the end of jump table data-in-code region. 32-bit offsets use
1210  // actual branch instructions here, so we don't mark those as a data-region
1211  // at all.
1212  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1213 
1214  // Make sure the next instruction is 2-byte aligned.
1215  EmitAlignment(1);
1216 }
1217 
1218 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1220  "Only instruction which are involved into frame setup code are allowed");
1221 
1222  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1223  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1224  const MachineFunction &MF = *MI->getParent()->getParent();
1225  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1226  const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1227 
1228  unsigned FramePtr = RegInfo->getFrameRegister(MF);
1229  unsigned Opc = MI->getOpcode();
1230  unsigned SrcReg, DstReg;
1231 
1232  if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1233  // Two special cases:
1234  // 1) tPUSH does not have src/dst regs.
1235  // 2) for Thumb1 code we sometimes materialize the constant via constpool
1236  // load. Yes, this is pretty fragile, but for now I don't see better
1237  // way... :(
1238  SrcReg = DstReg = ARM::SP;
1239  } else {
1240  SrcReg = MI->getOperand(1).getReg();
1241  DstReg = MI->getOperand(0).getReg();
1242  }
1243 
1244  // Try to figure out the unwinding opcode out of src / dst regs.
1245  if (MI->mayStore()) {
1246  // Register saves.
1247  assert(DstReg == ARM::SP &&
1248  "Only stack pointer as a destination reg is supported");
1249 
1250  SmallVector<unsigned, 4> RegList;
1251  // Skip src & dst reg, and pred ops.
1252  unsigned StartOp = 2 + 2;
1253  // Use all the operands.
1254  unsigned NumOffset = 0;
1255 
1256  switch (Opc) {
1257  default:
1258  MI->dump();
1259  llvm_unreachable("Unsupported opcode for unwinding information");
1260  case ARM::tPUSH:
1261  // Special case here: no src & dst reg, but two extra imp ops.
1262  StartOp = 2; NumOffset = 2;
1263  case ARM::STMDB_UPD:
1264  case ARM::t2STMDB_UPD:
1265  case ARM::VSTMDDB_UPD:
1266  assert(SrcReg == ARM::SP &&
1267  "Only stack pointer as a source reg is supported");
1268  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1269  i != NumOps; ++i) {
1270  const MachineOperand &MO = MI->getOperand(i);
1271  // Actually, there should never be any impdef stuff here. Skip it
1272  // temporary to workaround PR11902.
1273  if (MO.isImplicit())
1274  continue;
1275  RegList.push_back(MO.getReg());
1276  }
1277  break;
1278  case ARM::STR_PRE_IMM:
1279  case ARM::STR_PRE_REG:
1280  case ARM::t2STR_PRE:
1281  assert(MI->getOperand(2).getReg() == ARM::SP &&
1282  "Only stack pointer as a source reg is supported");
1283  RegList.push_back(SrcReg);
1284  break;
1285  }
1287  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1288  } else {
1289  // Changes of stack / frame pointer.
1290  if (SrcReg == ARM::SP) {
1291  int64_t Offset = 0;
1292  switch (Opc) {
1293  default:
1294  MI->dump();
1295  llvm_unreachable("Unsupported opcode for unwinding information");
1296  case ARM::MOVr:
1297  case ARM::tMOVr:
1298  Offset = 0;
1299  break;
1300  case ARM::ADDri:
1301  case ARM::t2ADDri:
1302  Offset = -MI->getOperand(2).getImm();
1303  break;
1304  case ARM::SUBri:
1305  case ARM::t2SUBri:
1306  Offset = MI->getOperand(2).getImm();
1307  break;
1308  case ARM::tSUBspi:
1309  Offset = MI->getOperand(2).getImm()*4;
1310  break;
1311  case ARM::tADDspi:
1312  case ARM::tADDrSPi:
1313  Offset = -MI->getOperand(2).getImm()*4;
1314  break;
1315  case ARM::tLDRpci: {
1316  // Grab the constpool index and check, whether it corresponds to
1317  // original or cloned constpool entry.
1318  unsigned CPI = MI->getOperand(1).getIndex();
1319  const MachineConstantPool *MCP = MF.getConstantPool();
1320  if (CPI >= MCP->getConstants().size())
1321  CPI = AFI.getOriginalCPIdx(CPI);
1322  assert(CPI != -1U && "Invalid constpool index");
1323 
1324  // Derive the actual offset.
1325  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1326  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1327  // FIXME: Check for user, it should be "add" instruction!
1328  Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1329  break;
1330  }
1331  }
1332 
1334  if (DstReg == FramePtr && FramePtr != ARM::SP)
1335  // Set-up of the frame pointer. Positive values correspond to "add"
1336  // instruction.
1337  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1338  else if (DstReg == ARM::SP) {
1339  // Change of SP by an offset. Positive values correspond to "sub"
1340  // instruction.
1341  ATS.emitPad(Offset);
1342  } else {
1343  // Move of SP to a register. Positive values correspond to an "add"
1344  // instruction.
1345  ATS.emitMovSP(DstReg, -Offset);
1346  }
1347  }
1348  } else if (DstReg == ARM::SP) {
1349  MI->dump();
1350  llvm_unreachable("Unsupported opcode for unwinding information");
1351  }
1352  else {
1353  MI->dump();
1354  llvm_unreachable("Unsupported opcode for unwinding information");
1355  }
1356  }
1357 }
1358 
1359 // Simple pseudo-instructions have their lowering (with expansion to real
1360 // instructions) auto-generated.
1361 #include "ARMGenMCPseudoLowering.inc"
1362 
1364  const DataLayout &DL = getDataLayout();
1365  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1366  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1367 
1368  // If we just ended a constant pool, mark it as such.
1369  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1370  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1371  InConstantPool = false;
1372  }
1373 
1374  // Emit unwinding stuff for frame-related instructions
1375  if (Subtarget->isTargetEHABICompatible() &&
1377  EmitUnwindingInstruction(MI);
1378 
1379  // Do any auto-generated pseudo lowerings.
1380  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1381  return;
1382 
1384  "Pseudo flag setting opcode should be expanded early");
1385 
1386  // Check for manual lowerings.
1387  unsigned Opc = MI->getOpcode();
1388  switch (Opc) {
1389  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1390  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1391  case ARM::LEApcrel:
1392  case ARM::tLEApcrel:
1393  case ARM::t2LEApcrel: {
1394  // FIXME: Need to also handle globals and externals
1395  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1397  ARM::t2LEApcrel ? ARM::t2ADR
1398  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1399  : ARM::ADR))
1400  .addReg(MI->getOperand(0).getReg())
1401  .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1402  // Add predicate operands.
1403  .addImm(MI->getOperand(2).getImm())
1404  .addReg(MI->getOperand(3).getReg()));
1405  return;
1406  }
1407  case ARM::LEApcrelJT:
1408  case ARM::tLEApcrelJT:
1409  case ARM::t2LEApcrelJT: {
1410  MCSymbol *JTIPICSymbol =
1411  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1413  ARM::t2LEApcrelJT ? ARM::t2ADR
1414  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1415  : ARM::ADR))
1416  .addReg(MI->getOperand(0).getReg())
1417  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1418  // Add predicate operands.
1419  .addImm(MI->getOperand(2).getImm())
1420  .addReg(MI->getOperand(3).getReg()));
1421  return;
1422  }
1423  // Darwin call instructions are just normal call instructions with different
1424  // clobber semantics (they clobber R9).
1425  case ARM::BX_CALL: {
1427  .addReg(ARM::LR)
1428  .addReg(ARM::PC)
1429  // Add predicate operands.
1430  .addImm(ARMCC::AL)
1431  .addReg(0)
1432  // Add 's' bit operand (always reg0 for this)
1433  .addReg(0));
1434 
1436  .addReg(MI->getOperand(0).getReg()));
1437  return;
1438  }
1439  case ARM::tBX_CALL: {
1440  if (Subtarget->hasV5TOps())
1441  llvm_unreachable("Expected BLX to be selected for v5t+");
1442 
1443  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1444  // that the saved lr has its LSB set correctly (the arch doesn't
1445  // have blx).
1446  // So here we generate a bl to a small jump pad that does bx rN.
1447  // The jump pads are emitted after the function body.
1448 
1449  unsigned TReg = MI->getOperand(0).getReg();
1450  MCSymbol *TRegSym = nullptr;
1451  for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1452  if (ThumbIndirectPads[i].first == TReg) {
1453  TRegSym = ThumbIndirectPads[i].second;
1454  break;
1455  }
1456  }
1457 
1458  if (!TRegSym) {
1459  TRegSym = OutContext.createTempSymbol();
1460  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1461  }
1462 
1463  // Create a link-saving branch to the Reg Indirect Jump Pad.
1465  // Predicate comes first here.
1466  .addImm(ARMCC::AL).addReg(0)
1467  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1468  return;
1469  }
1470  case ARM::BMOVPCRX_CALL: {
1472  .addReg(ARM::LR)
1473  .addReg(ARM::PC)
1474  // Add predicate operands.
1475  .addImm(ARMCC::AL)
1476  .addReg(0)
1477  // Add 's' bit operand (always reg0 for this)
1478  .addReg(0));
1479 
1481  .addReg(ARM::PC)
1482  .addReg(MI->getOperand(0).getReg())
1483  // Add predicate operands.
1484  .addImm(ARMCC::AL)
1485  .addReg(0)
1486  // Add 's' bit operand (always reg0 for this)
1487  .addReg(0));
1488  return;
1489  }
1490  case ARM::BMOVPCB_CALL: {
1492  .addReg(ARM::LR)
1493  .addReg(ARM::PC)
1494  // Add predicate operands.
1495  .addImm(ARMCC::AL)
1496  .addReg(0)
1497  // Add 's' bit operand (always reg0 for this)
1498  .addReg(0));
1499 
1500  const MachineOperand &Op = MI->getOperand(0);
1501  const GlobalValue *GV = Op.getGlobal();
1502  const unsigned TF = Op.getTargetFlags();
1503  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1504  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1506  .addExpr(GVSymExpr)
1507  // Add predicate operands.
1508  .addImm(ARMCC::AL)
1509  .addReg(0));
1510  return;
1511  }
1512  case ARM::MOVi16_ga_pcrel:
1513  case ARM::t2MOVi16_ga_pcrel: {
1514  MCInst TmpInst;
1515  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1516  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1517 
1518  unsigned TF = MI->getOperand(1).getTargetFlags();
1519  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1520  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1521  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1522 
1523  MCSymbol *LabelSym =
1525  MI->getOperand(2).getImm(), OutContext);
1526  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1527  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1528  const MCExpr *PCRelExpr =
1530  MCBinaryExpr::createAdd(LabelSymExpr,
1533  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1534 
1535  // Add predicate operands.
1537  TmpInst.addOperand(MCOperand::createReg(0));
1538  // Add 's' bit operand (always reg0 for this)
1539  TmpInst.addOperand(MCOperand::createReg(0));
1540  EmitToStreamer(*OutStreamer, TmpInst);
1541  return;
1542  }
1543  case ARM::MOVTi16_ga_pcrel:
1544  case ARM::t2MOVTi16_ga_pcrel: {
1545  MCInst TmpInst;
1546  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1547  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1548  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1549  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1550 
1551  unsigned TF = MI->getOperand(2).getTargetFlags();
1552  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1553  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1554  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1555 
1556  MCSymbol *LabelSym =
1558  MI->getOperand(3).getImm(), OutContext);
1559  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1560  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1561  const MCExpr *PCRelExpr =
1563  MCBinaryExpr::createAdd(LabelSymExpr,
1566  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1567  // Add predicate operands.
1569  TmpInst.addOperand(MCOperand::createReg(0));
1570  // Add 's' bit operand (always reg0 for this)
1571  TmpInst.addOperand(MCOperand::createReg(0));
1572  EmitToStreamer(*OutStreamer, TmpInst);
1573  return;
1574  }
1575  case ARM::tPICADD: {
1576  // This is a pseudo op for a label + instruction sequence, which looks like:
1577  // LPC0:
1578  // add r0, pc
1579  // This adds the address of LPC0 to r0.
1580 
1581  // Emit the label.
1584  MI->getOperand(2).getImm(), OutContext));
1585 
1586  // Form and emit the add.
1587  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1588  .addReg(MI->getOperand(0).getReg())
1589  .addReg(MI->getOperand(0).getReg())
1590  .addReg(ARM::PC)
1591  // Add predicate operands.
1592  .addImm(ARMCC::AL)
1593  .addReg(0));
1594  return;
1595  }
1596  case ARM::PICADD: {
1597  // This is a pseudo op for a label + instruction sequence, which looks like:
1598  // LPC0:
1599  // add r0, pc, r0
1600  // This adds the address of LPC0 to r0.
1601 
1602  // Emit the label.
1605  MI->getOperand(2).getImm(), OutContext));
1606 
1607  // Form and emit the add.
1609  .addReg(MI->getOperand(0).getReg())
1610  .addReg(ARM::PC)
1611  .addReg(MI->getOperand(1).getReg())
1612  // Add predicate operands.
1613  .addImm(MI->getOperand(3).getImm())
1614  .addReg(MI->getOperand(4).getReg())
1615  // Add 's' bit operand (always reg0 for this)
1616  .addReg(0));
1617  return;
1618  }
1619  case ARM::PICSTR:
1620  case ARM::PICSTRB:
1621  case ARM::PICSTRH:
1622  case ARM::PICLDR:
1623  case ARM::PICLDRB:
1624  case ARM::PICLDRH:
1625  case ARM::PICLDRSB:
1626  case ARM::PICLDRSH: {
1627  // This is a pseudo op for a label + instruction sequence, which looks like:
1628  // LPC0:
1629  // OP r0, [pc, r0]
1630  // The LCP0 label is referenced by a constant pool entry in order to get
1631  // a PC-relative address at the ldr instruction.
1632 
1633  // Emit the label.
1636  MI->getOperand(2).getImm(), OutContext));
1637 
1638  // Form and emit the load
1639  unsigned Opcode;
1640  switch (MI->getOpcode()) {
1641  default:
1642  llvm_unreachable("Unexpected opcode!");
1643  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1644  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1645  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1646  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1647  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1648  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1649  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1650  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1651  }
1653  .addReg(MI->getOperand(0).getReg())
1654  .addReg(ARM::PC)
1655  .addReg(MI->getOperand(1).getReg())
1656  .addImm(0)
1657  // Add predicate operands.
1658  .addImm(MI->getOperand(3).getImm())
1659  .addReg(MI->getOperand(4).getReg()));
1660 
1661  return;
1662  }
1663  case ARM::CONSTPOOL_ENTRY: {
1664  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1665  /// in the function. The first operand is the ID# for this instruction, the
1666  /// second is the index into the MachineConstantPool that this is, the third
1667  /// is the size in bytes of this constant pool entry.
1668  /// The required alignment is specified on the basic block holding this MI.
1669  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1670  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1671 
1672  // If this is the first entry of the pool, mark it.
1673  if (!InConstantPool) {
1674  OutStreamer->EmitDataRegion(MCDR_DataRegion);
1675  InConstantPool = true;
1676  }
1677 
1678  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1679 
1680  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1681  if (MCPE.isMachineConstantPoolEntry())
1683  else
1684  EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1685  return;
1686  }
1687  case ARM::JUMPTABLE_ADDRS:
1688  EmitJumpTableAddrs(MI);
1689  return;
1690  case ARM::JUMPTABLE_INSTS:
1691  EmitJumpTableInsts(MI);
1692  return;
1693  case ARM::JUMPTABLE_TBB:
1694  case ARM::JUMPTABLE_TBH:
1695  EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1696  return;
1697  case ARM::t2BR_JT: {
1698  // Lower and emit the instruction itself, then the jump table following it.
1700  .addReg(ARM::PC)
1701  .addReg(MI->getOperand(0).getReg())
1702  // Add predicate operands.
1703  .addImm(ARMCC::AL)
1704  .addReg(0));
1705  return;
1706  }
1707  case ARM::t2TBB_JT:
1708  case ARM::t2TBH_JT: {
1709  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1710  // Lower and emit the PC label, then the instruction itself.
1711  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1713  .addReg(MI->getOperand(0).getReg())
1714  .addReg(MI->getOperand(1).getReg())
1715  // Add predicate operands.
1716  .addImm(ARMCC::AL)
1717  .addReg(0));
1718  return;
1719  }
1720  case ARM::tTBB_JT:
1721  case ARM::tTBH_JT: {
1722 
1723  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1724  unsigned Base = MI->getOperand(0).getReg();
1725  unsigned Idx = MI->getOperand(1).getReg();
1726  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1727 
1728  // Multiply up idx if necessary.
1729  if (!Is8Bit)
1731  .addReg(Idx)
1732  .addReg(ARM::CPSR)
1733  .addReg(Idx)
1734  .addImm(1)
1735  // Add predicate operands.
1736  .addImm(ARMCC::AL)
1737  .addReg(0));
1738 
1739  if (Base == ARM::PC) {
1740  // TBB [base, idx] =
1741  // ADDS idx, idx, base
1742  // LDRB idx, [idx, #4] ; or LDRH if TBH
1743  // LSLS idx, #1
1744  // ADDS pc, pc, idx
1745 
1746  // When using PC as the base, it's important that there is no padding
1747  // between the last ADDS and the start of the jump table. The jump table
1748  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1749  //
1750  // FIXME: Ideally we could vary the LDRB index based on the padding
1751  // between the sequence and jump table, however that relies on MCExprs
1752  // for load indexes which are currently not supported.
1753  OutStreamer->EmitCodeAlignment(4);
1754  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1755  .addReg(Idx)
1756  .addReg(Idx)
1757  .addReg(Base)
1758  // Add predicate operands.
1759  .addImm(ARMCC::AL)
1760  .addReg(0));
1761 
1762  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1764  .addReg(Idx)
1765  .addReg(Idx)
1766  .addImm(Is8Bit ? 4 : 2)
1767  // Add predicate operands.
1768  .addImm(ARMCC::AL)
1769  .addReg(0));
1770  } else {
1771  // TBB [base, idx] =
1772  // LDRB idx, [base, idx] ; or LDRH if TBH
1773  // LSLS idx, #1
1774  // ADDS pc, pc, idx
1775 
1776  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1778  .addReg(Idx)
1779  .addReg(Base)
1780  .addReg(Idx)
1781  // Add predicate operands.
1782  .addImm(ARMCC::AL)
1783  .addReg(0));
1784  }
1785 
1787  .addReg(Idx)
1788  .addReg(ARM::CPSR)
1789  .addReg(Idx)
1790  .addImm(1)
1791  // Add predicate operands.
1792  .addImm(ARMCC::AL)
1793  .addReg(0));
1794 
1795  OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1796  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1797  .addReg(ARM::PC)
1798  .addReg(ARM::PC)
1799  .addReg(Idx)
1800  // Add predicate operands.
1801  .addImm(ARMCC::AL)
1802  .addReg(0));
1803  return;
1804  }
1805  case ARM::tBR_JTr:
1806  case ARM::BR_JTr: {
1807  // Lower and emit the instruction itself, then the jump table following it.
1808  // mov pc, target
1809  MCInst TmpInst;
1810  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1811  ARM::MOVr : ARM::tMOVr;
1812  TmpInst.setOpcode(Opc);
1814  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1815  // Add predicate operands.
1817  TmpInst.addOperand(MCOperand::createReg(0));
1818  // Add 's' bit operand (always reg0 for this)
1819  if (Opc == ARM::MOVr)
1820  TmpInst.addOperand(MCOperand::createReg(0));
1821  EmitToStreamer(*OutStreamer, TmpInst);
1822  return;
1823  }
1824  case ARM::BR_JTm: {
1825  // Lower and emit the instruction itself, then the jump table following it.
1826  // ldr pc, target
1827  MCInst TmpInst;
1828  if (MI->getOperand(1).getReg() == 0) {
1829  // literal offset
1830  TmpInst.setOpcode(ARM::LDRi12);
1832  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1833  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1834  } else {
1835  TmpInst.setOpcode(ARM::LDRrs);
1837  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1838  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1839  TmpInst.addOperand(MCOperand::createImm(0));
1840  }
1841  // Add predicate operands.
1843  TmpInst.addOperand(MCOperand::createReg(0));
1844  EmitToStreamer(*OutStreamer, TmpInst);
1845  return;
1846  }
1847  case ARM::BR_JTadd: {
1848  // Lower and emit the instruction itself, then the jump table following it.
1849  // add pc, target, idx
1851  .addReg(ARM::PC)
1852  .addReg(MI->getOperand(0).getReg())
1853  .addReg(MI->getOperand(1).getReg())
1854  // Add predicate operands.
1855  .addImm(ARMCC::AL)
1856  .addReg(0)
1857  // Add 's' bit operand (always reg0 for this)
1858  .addReg(0));
1859  return;
1860  }
1861  case ARM::SPACE:
1862  OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1863  return;
1864  case ARM::TRAP: {
1865  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1866  // FIXME: Remove this special case when they do.
1867  if (!Subtarget->isTargetMachO()) {
1868  uint32_t Val = 0xe7ffdefeUL;
1869  OutStreamer->AddComment("trap");
1870  ATS.emitInst(Val);
1871  return;
1872  }
1873  break;
1874  }
1875  case ARM::TRAPNaCl: {
1876  uint32_t Val = 0xe7fedef0UL;
1877  OutStreamer->AddComment("trap");
1878  ATS.emitInst(Val);
1879  return;
1880  }
1881  case ARM::tTRAP: {
1882  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1883  // FIXME: Remove this special case when they do.
1884  if (!Subtarget->isTargetMachO()) {
1885  uint16_t Val = 0xdefe;
1886  OutStreamer->AddComment("trap");
1887  ATS.emitInst(Val, 'n');
1888  return;
1889  }
1890  break;
1891  }
1892  case ARM::t2Int_eh_sjlj_setjmp:
1893  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1894  case ARM::tInt_eh_sjlj_setjmp: {
1895  // Two incoming args: GPR:$src, GPR:$val
1896  // mov $val, pc
1897  // adds $val, #7
1898  // str $val, [$src, #4]
1899  // movs r0, #0
1900  // b LSJLJEH
1901  // movs r0, #1
1902  // LSJLJEH:
1903  unsigned SrcReg = MI->getOperand(0).getReg();
1904  unsigned ValReg = MI->getOperand(1).getReg();
1905  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1906  OutStreamer->AddComment("eh_setjmp begin");
1908  .addReg(ValReg)
1909  .addReg(ARM::PC)
1910  // Predicate.
1911  .addImm(ARMCC::AL)
1912  .addReg(0));
1913 
1915  .addReg(ValReg)
1916  // 's' bit operand
1917  .addReg(ARM::CPSR)
1918  .addReg(ValReg)
1919  .addImm(7)
1920  // Predicate.
1921  .addImm(ARMCC::AL)
1922  .addReg(0));
1923 
1925  .addReg(ValReg)
1926  .addReg(SrcReg)
1927  // The offset immediate is #4. The operand value is scaled by 4 for the
1928  // tSTR instruction.
1929  .addImm(1)
1930  // Predicate.
1931  .addImm(ARMCC::AL)
1932  .addReg(0));
1933 
1935  .addReg(ARM::R0)
1936  .addReg(ARM::CPSR)
1937  .addImm(0)
1938  // Predicate.
1939  .addImm(ARMCC::AL)
1940  .addReg(0));
1941 
1942  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1944  .addExpr(SymbolExpr)
1945  .addImm(ARMCC::AL)
1946  .addReg(0));
1947 
1948  OutStreamer->AddComment("eh_setjmp end");
1950  .addReg(ARM::R0)
1951  .addReg(ARM::CPSR)
1952  .addImm(1)
1953  // Predicate.
1954  .addImm(ARMCC::AL)
1955  .addReg(0));
1956 
1957  OutStreamer->EmitLabel(Label);
1958  return;
1959  }
1960 
1961  case ARM::Int_eh_sjlj_setjmp_nofp:
1962  case ARM::Int_eh_sjlj_setjmp: {
1963  // Two incoming args: GPR:$src, GPR:$val
1964  // add $val, pc, #8
1965  // str $val, [$src, #+4]
1966  // mov r0, #0
1967  // add pc, pc, #0
1968  // mov r0, #1
1969  unsigned SrcReg = MI->getOperand(0).getReg();
1970  unsigned ValReg = MI->getOperand(1).getReg();
1971 
1972  OutStreamer->AddComment("eh_setjmp begin");
1974  .addReg(ValReg)
1975  .addReg(ARM::PC)
1976  .addImm(8)
1977  // Predicate.
1978  .addImm(ARMCC::AL)
1979  .addReg(0)
1980  // 's' bit operand (always reg0 for this).
1981  .addReg(0));
1982 
1984  .addReg(ValReg)
1985  .addReg(SrcReg)
1986  .addImm(4)
1987  // Predicate.
1988  .addImm(ARMCC::AL)
1989  .addReg(0));
1990 
1992  .addReg(ARM::R0)
1993  .addImm(0)
1994  // Predicate.
1995  .addImm(ARMCC::AL)
1996  .addReg(0)
1997  // 's' bit operand (always reg0 for this).
1998  .addReg(0));
1999 
2001  .addReg(ARM::PC)
2002  .addReg(ARM::PC)
2003  .addImm(0)
2004  // Predicate.
2005  .addImm(ARMCC::AL)
2006  .addReg(0)
2007  // 's' bit operand (always reg0 for this).
2008  .addReg(0));
2009 
2010  OutStreamer->AddComment("eh_setjmp end");
2012  .addReg(ARM::R0)
2013  .addImm(1)
2014  // Predicate.
2015  .addImm(ARMCC::AL)
2016  .addReg(0)
2017  // 's' bit operand (always reg0 for this).
2018  .addReg(0));
2019  return;
2020  }
2021  case ARM::Int_eh_sjlj_longjmp: {
2022  // ldr sp, [$src, #8]
2023  // ldr $scratch, [$src, #4]
2024  // ldr r7, [$src]
2025  // bx $scratch
2026  unsigned SrcReg = MI->getOperand(0).getReg();
2027  unsigned ScratchReg = MI->getOperand(1).getReg();
2029  .addReg(ARM::SP)
2030  .addReg(SrcReg)
2031  .addImm(8)
2032  // Predicate.
2033  .addImm(ARMCC::AL)
2034  .addReg(0));
2035 
2037  .addReg(ScratchReg)
2038  .addReg(SrcReg)
2039  .addImm(4)
2040  // Predicate.
2041  .addImm(ARMCC::AL)
2042  .addReg(0));
2043 
2045  .addReg(ARM::R7)
2046  .addReg(SrcReg)
2047  .addImm(0)
2048  // Predicate.
2049  .addImm(ARMCC::AL)
2050  .addReg(0));
2051 
2053  .addReg(ScratchReg)
2054  // Predicate.
2055  .addImm(ARMCC::AL)
2056  .addReg(0));
2057  return;
2058  }
2059  case ARM::tInt_eh_sjlj_longjmp: {
2060  // ldr $scratch, [$src, #8]
2061  // mov sp, $scratch
2062  // ldr $scratch, [$src, #4]
2063  // ldr r7, [$src]
2064  // bx $scratch
2065  unsigned SrcReg = MI->getOperand(0).getReg();
2066  unsigned ScratchReg = MI->getOperand(1).getReg();
2067 
2069  .addReg(ScratchReg)
2070  .addReg(SrcReg)
2071  // The offset immediate is #8. The operand value is scaled by 4 for the
2072  // tLDR instruction.
2073  .addImm(2)
2074  // Predicate.
2075  .addImm(ARMCC::AL)
2076  .addReg(0));
2077 
2079  .addReg(ARM::SP)
2080  .addReg(ScratchReg)
2081  // Predicate.
2082  .addImm(ARMCC::AL)
2083  .addReg(0));
2084 
2086  .addReg(ScratchReg)
2087  .addReg(SrcReg)
2088  .addImm(1)
2089  // Predicate.
2090  .addImm(ARMCC::AL)
2091  .addReg(0));
2092 
2094  .addReg(ARM::R7)
2095  .addReg(SrcReg)
2096  .addImm(0)
2097  // Predicate.
2098  .addImm(ARMCC::AL)
2099  .addReg(0));
2100 
2102  .addReg(ScratchReg)
2103  // Predicate.
2104  .addImm(ARMCC::AL)
2105  .addReg(0));
2106  return;
2107  }
2108  case ARM::tInt_WIN_eh_sjlj_longjmp: {
2109  // ldr.w r11, [$src, #0]
2110  // ldr.w sp, [$src, #8]
2111  // ldr.w pc, [$src, #4]
2112 
2113  unsigned SrcReg = MI->getOperand(0).getReg();
2114 
2115  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2116  .addReg(ARM::R11)
2117  .addReg(SrcReg)
2118  .addImm(0)
2119  // Predicate
2120  .addImm(ARMCC::AL)
2121  .addReg(0));
2122  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2123  .addReg(ARM::SP)
2124  .addReg(SrcReg)
2125  .addImm(8)
2126  // Predicate
2127  .addImm(ARMCC::AL)
2128  .addReg(0));
2129  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2130  .addReg(ARM::PC)
2131  .addReg(SrcReg)
2132  .addImm(4)
2133  // Predicate
2134  .addImm(ARMCC::AL)
2135  .addReg(0));
2136  return;
2137  }
2138  case ARM::PATCHABLE_FUNCTION_ENTER:
2140  return;
2141  case ARM::PATCHABLE_FUNCTION_EXIT:
2143  return;
2144  case ARM::PATCHABLE_TAIL_CALL:
2146  return;
2147  }
2148 
2149  MCInst TmpInst;
2150  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2151 
2152  EmitToStreamer(*OutStreamer, TmpInst);
2153 }
2154 
2155 //===----------------------------------------------------------------------===//
2156 // Target Registry Stuff
2157 //===----------------------------------------------------------------------===//
2158 
2159 // Force static initialization.
2160 extern "C" void LLVMInitializeARMAsmPrinter() {
2165 }
bool hasV4TOps() const
Definition: ARMSubtarget.h:414
virtual void EmitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:376
MCSection * getNonLazySymbolPointerSection() const
MachineConstantPoolValue * MachineCPVal
bool isImplicit() const
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:299
void push_back(const T &Elt)
Definition: SmallVector.h:211
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
virtual void emitInst(uint32_t Inst, char Suffix= '\0')
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:102
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
virtual void emitFPU(unsigned FPU)
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:284
StringRef getTargetCPU() const
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const GlobalValue * getGlobal() const
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:575
static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU, const ARMSubtarget *Subtarget)
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:84
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:371
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:298
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:53
size_t i
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const std::string & getCPUString() const
Definition: ARMSubtarget.h:611
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:148
void EmitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:79
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
virtual void emitArchExtension(unsigned ArchExt)
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:546
ARMConstantPoolValue - ARM specific constantpool value.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
Target specific streamer interface.
Definition: MCStreamer.h:73
virtual void emitPad(int64_t Offset)
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:87
Global Offset Table, Thread Pointer Offset.
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:490
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
bool hasV5TEOps() const
Definition: ARMSubtarget.h:416
bool isROPI() const
MachineBasicBlock reference.
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:140
bool hasV6Ops() const
Definition: ARMSubtarget.h:417
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the EmitInstruction() method to print assembly for each instruction...
virtual void finishAttributeSection()
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:234
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
setjmp/longjmp based exceptions
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:420
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Global Offset Table, PC Relative.
Thread Pointer Offset.
Target & getTheThumbLETarget()
bool isThumb1Only() const
Definition: ARMSubtarget.h:577
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
bool optForSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:464
static bool isThumb(const MCSubtargetInfo &STI)
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:341
void LLVMInitializeARMAsmPrinter()
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:461
return AArch64::GPR64RegClass contains(Reg)
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:366
bool hasV6MOps() const
Definition: ARMSubtarget.h:418
void EmitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
const Triple & getTargetTriple() const
const std::vector< MachineJumpTableEntry > & getJumpTables() const
The address of a basic block.
Definition: Constants.h:822
bool isTargetAEABI() const
Definition: ARMSubtarget.h:528
bool hasV8Ops() const
Definition: ARMSubtarget.h:422
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
MCSuperRegIterator enumerates all super-registers of Reg.
struct fuzzer::@269 Flags
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
bool isTargetELF() const
Definition: ARMSubtarget.h:518
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool hasInternalLinkage() const
Definition: GlobalValue.h:413
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:437
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRClass() const
Definition: ARMSubtarget.h:581
unsigned SubReg
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
bool hasV8MMainlineOps() const
Definition: ARMSubtarget.h:426
const Module * getModule() const
Reg
All possible values of the reg field in the ModR/M byte.
.data_region jt16
Definition: MCDirectives.h:59
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
MCContext & getContext() const
Definition: MCStreamer.h:221
Target & getTheARMBETarget()
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
void EmitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Context object for machine code objects.
Definition: MCContext.h:51
bool hasV7Ops() const
Definition: ARMSubtarget.h:421
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:43
void EmitFunctionBody()
This method emits the body and trailer for a function.
Definition: AsmPrinter.cpp:876
#define F(x, y, z)
Definition: MD5.cpp:51
bool isKill() const
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file. ...
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:497
PointerTy getPointer() const
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:51
bool isTargetCOFF() const
Definition: ARMSubtarget.h:517
Target & getTheThumbBETarget()
MachineBasicBlock * MBB
bool isTargetMachO() const
Definition: ARMSubtarget.h:519
Function Alias Analysis false
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:270
This class is a data container for one entry in a MachineConstantPool.
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
IntType getInt() const
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
int64_t getImm() const
static const char * getRegisterName(unsigned RegNo)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:429
virtual void EmitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers...
Definition: MCStreamer.cpp:85
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:116
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:90
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
SubArchType getSubArch() const
getSubArch - get the parsed subarchitecture type for this triple.
Definition: Triple.h:273
virtual void emitAttribute(unsigned Attribute, unsigned Value)
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
.data_region jt32
Definition: MCDirectives.h:60
Address of a global value.
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
unsigned getTargetFlags() const
Streaming machine code generation interface.
Definition: MCStreamer.h:161
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:32
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:218
Constant * stripPointerCasts()
Definition: Constant.h:155
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:95
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:75
PointerIntPair - This class implements a pair of a pointer and small integer.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important base class in LLVM.
Definition: Constant.h:42
bool isMClass() const
Definition: ARMSubtarget.h:580
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: Support/COFF.h:233
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:71
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:67
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
bool any_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:743
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
uint32_t Offset
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:161
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:50
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:676
Thread Local Storage (General Dynamic Mode)
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:538
A function that returns a base type.
Definition: Support/COFF.h:229
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
int64_t getOffset() const
Return the offset from the symbol in this operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:38
Ty & getObjFileInfo()
Keep track of various per-function pieces of information for backends that would like to do so...
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
bool hasV8MBaselineOps() const
Definition: ARMSubtarget.h:425
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:570
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:232
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
FPDenormal::DenormalMode FPDenormalMode
FPDenormalMode - This flags specificies which denormal numbers the code is permitted to require...
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Abstract base class for all machine specific constantpool value subclasses.
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
static bool isV8M(const ARMSubtarget *Subtarget)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address...
Definition: ARMBaseInfo.h:286
bool genExecuteOnly() const
Definition: ARMSubtarget.h:500
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCSection * getThreadLocalPointerSection() const
void EmitAlignment(unsigned NumBits, const GlobalObject *GO=nullptr) const
Emit an alignment directive to the specified power of two boundary.
const std::string & getModuleInlineAsm() const
Get any module-scope inline assembly blocks.
Definition: Module.h:226
void EmitJumpTableInsts(const MachineInstr *MI)
void setOpcode(unsigned Op)
Definition: MCInst.h:158
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
StringRef getTargetFeatureString() const
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:293
uint64_t getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:408
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
MachineOperand class - Representation of each machine instruction operand.
Module.h This file contains the declarations for the Module class.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:230
.indirect_symbol (MachO)
Definition: MCDirectives.h:32
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:161
void dump(const TargetInstrInfo *TII=nullptr) const
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
Type * getType() const
getType - get type of this MachineConstantPoolValue.
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:134
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: Support/COFF.h:171
.syntax (ARM/ELF)
Definition: MCDirectives.h:49
MCSymbol * getCurExceptionSym()
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:130
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:533
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:52
FunctionNumber(functionNumber)
Definition: LLParser.cpp:2459
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:350
Section Relative (Windows TLS)
static bool startswith(StringRef Magic, const char(&S)[N])
Definition: Path.cpp:994
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:565
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:114
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
bool hasV5TOps() const
Definition: ARMSubtarget.h:415
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void EmitJumpTableAddrs(const MachineInstr *MI)
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:39
MCSubtargetInfo - Generic base class for all target subtargets.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
bool hasDSP() const
Definition: ARMSubtarget.h:496
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets...
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
unsigned getReg() const
getReg - Returns the register number.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:178
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:144
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:538
unsigned char getPCAdjustment() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
.data_region jt8
Definition: MCDirectives.h:58
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:71
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:239
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which...
Definition: ARMBaseInfo.h:312
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
static const unsigned FramePtr
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
static TraceState * TS
Primary interface to the complete machine description for the target machine.
const std::vector< MachineConstantPoolEntry > & getConstants() const
IRTranslator LLVM IR MI
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
virtual void print(raw_ostream &O, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:117
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
Address of indexed Constant in Constant Pool.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
union llvm::MachineConstantPoolEntry::@35 Val
The constant itself.
unsigned getOriginalCPIdx(unsigned CloneIdx) const
Target & getTheARMLETarget()
void EmitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
ARMCP::ARMCPModifier getModifier() const
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
bool isTargetWindows() const
Definition: ARMSubtarget.h:515
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
Definition: MCExpr.cpp:149
.end_data_region
Definition: MCDirectives.h:61
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address...
Definition: ARMBaseInfo.h:290
virtual void switchVendor(StringRef Vendor)
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line...
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
char * PC
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...