LLVM  4.0.0
HexagonBitTracker.cpp
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1 //===--- HexagonBitTracker.cpp --------------------------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "Hexagon.h"
11 #include "HexagonBitTracker.h"
12 #include "HexagonInstrInfo.h"
13 #include "HexagonRegisterInfo.h"
14 #include "HexagonTargetMachine.h"
19 #include "llvm/IR/Argument.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/Type.h"
23 #include "llvm/Support/Debug.h"
28 #include <cassert>
29 #include <cstddef>
30 #include <cstdint>
31 #include <cstdlib>
32 #include <utility>
33 #include <vector>
34 
35 using namespace llvm;
36 
37 typedef BitTracker BT;
38 
41  const HexagonInstrInfo &tii,
42  MachineFunction &mf)
43  : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) {
44  // Populate the VRX map (VR to extension-type).
45  // Go over all the formal parameters of the function. If a given parameter
46  // P is sign- or zero-extended, locate the virtual register holding that
47  // parameter and create an entry in the VRX map indicating the type of ex-
48  // tension (and the source type).
49  // This is a bit complicated to do accurately, since the memory layout in-
50  // formation is necessary to precisely determine whether an aggregate para-
51  // meter will be passed in a register or in memory. What is given in MRI
52  // is the association between the physical register that is live-in (i.e.
53  // holds an argument), and the virtual register that this value will be
54  // copied into. This, by itself, is not sufficient to map back the virtual
55  // register to a formal parameter from Function (since consecutive live-ins
56  // from MRI may not correspond to consecutive formal parameters from Func-
57  // tion). To avoid the complications with in-memory arguments, only consi-
58  // der the initial sequence of formal parameters that are known to be
59  // passed via registers.
60  unsigned AttrIdx = 0;
61  unsigned InVirtReg, InPhysReg = 0;
62  const Function &F = *MF.getFunction();
63  typedef Function::const_arg_iterator arg_iterator;
64  for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
65  AttrIdx++;
66  const Argument &Arg = *I;
67  Type *ATy = Arg.getType();
68  unsigned Width = 0;
69  if (ATy->isIntegerTy())
70  Width = ATy->getIntegerBitWidth();
71  else if (ATy->isPointerTy())
72  Width = 32;
73  // If pointer size is not set through target data, it will default to
74  // Module::AnyPointerSize.
75  if (Width == 0 || Width > 64)
76  break;
77  AttributeSet Attrs = F.getAttributes();
78  if (Attrs.hasAttribute(AttrIdx, Attribute::ByVal))
79  continue;
80  InPhysReg = getNextPhysReg(InPhysReg, Width);
81  if (!InPhysReg)
82  break;
83  InVirtReg = getVirtRegFor(InPhysReg);
84  if (!InVirtReg)
85  continue;
86  if (Attrs.hasAttribute(AttrIdx, Attribute::SExt))
87  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
88  else if (Attrs.hasAttribute(AttrIdx, Attribute::ZExt))
89  VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
90  }
91 }
92 
93 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
94  using namespace Hexagon;
95 
96  if (Sub == 0)
97  return MachineEvaluator::mask(Reg, 0);
98  const TargetRegisterClass *RC = MRI.getRegClass(Reg);
99  unsigned ID = RC->getID();
100  uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
101  auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
102  bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
103  switch (ID) {
104  case DoubleRegsRegClassID:
105  case VecDblRegsRegClassID:
106  case VecDblRegs128BRegClassID:
107  return IsSubLo ? BT::BitMask(0, RW-1)
108  : BT::BitMask(RW, 2*RW-1);
109  default:
110  break;
111  }
112 #ifndef NDEBUG
113  dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
114 #endif
115  llvm_unreachable("Unexpected register/subregister");
116 }
117 
118 namespace {
119 
120 class RegisterRefs {
121  std::vector<BT::RegisterRef> Vector;
122 
123 public:
124  RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
125  for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
126  const MachineOperand &MO = MI.getOperand(i);
127  if (MO.isReg())
128  Vector[i] = BT::RegisterRef(MO);
129  // For indices that don't correspond to registers, the entry will
130  // remain constructed via the default constructor.
131  }
132  }
133 
134  size_t size() const { return Vector.size(); }
135 
136  const BT::RegisterRef &operator[](unsigned n) const {
137  // The main purpose of this operator is to assert with bad argument.
138  assert(n < Vector.size());
139  return Vector[n];
140  }
141 };
142 
143 } // end anonymous namespace
144 
146  const CellMapType &Inputs,
147  CellMapType &Outputs) const {
148  using namespace Hexagon;
149 
150  unsigned NumDefs = 0;
151 
152  // Sanity verification: there should not be any defs with subregisters.
153  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
154  const MachineOperand &MO = MI.getOperand(i);
155  if (!MO.isReg() || !MO.isDef())
156  continue;
157  NumDefs++;
158  assert(MO.getSubReg() == 0);
159  }
160 
161  if (NumDefs == 0)
162  return false;
163 
164  unsigned Opc = MI.getOpcode();
165 
166  if (MI.mayLoad()) {
167  switch (Opc) {
168  // These instructions may be marked as mayLoad, but they are generating
169  // immediate values, so skip them.
170  case CONST32:
171  case CONST64:
172  break;
173  default:
174  return evaluateLoad(MI, Inputs, Outputs);
175  }
176  }
177 
178  // Check COPY instructions that copy formal parameters into virtual
179  // registers. Such parameters can be sign- or zero-extended at the
180  // call site, and we should take advantage of this knowledge. The MRI
181  // keeps a list of pairs of live-in physical and virtual registers,
182  // which provides information about which virtual registers will hold
183  // the argument values. The function will still contain instructions
184  // defining those virtual registers, and in practice those are COPY
185  // instructions from a physical to a virtual register. In such cases,
186  // applying the argument extension to the virtual register can be seen
187  // as simply mirroring the extension that had already been applied to
188  // the physical register at the call site. If the defining instruction
189  // was not a COPY, it would not be clear how to mirror that extension
190  // on the callee's side. For that reason, only check COPY instructions
191  // for potential extensions.
192  if (MI.isCopy()) {
193  if (evaluateFormalCopy(MI, Inputs, Outputs))
194  return true;
195  }
196 
197  // Beyond this point, if any operand is a global, skip that instruction.
198  // The reason is that certain instructions that can take an immediate
199  // operand can also have a global symbol in that operand. To avoid
200  // checking what kind of operand a given instruction has individually
201  // for each instruction, do it here. Global symbols as operands gene-
202  // rally do not provide any useful information.
203  for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
204  const MachineOperand &MO = MI.getOperand(i);
205  if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
206  MO.isCPI())
207  return false;
208  }
209 
210  RegisterRefs Reg(MI);
211 #define op(i) MI.getOperand(i)
212 #define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
213 #define im(i) MI.getOperand(i).getImm()
214 
215  // If the instruction has no register operands, skip it.
216  if (Reg.size() == 0)
217  return false;
218 
219  // Record result for register in operand 0.
220  auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
221  -> bool {
222  putCell(Reg[0], Val, Outputs);
223  return true;
224  };
225  // Get the cell corresponding to the N-th operand.
226  auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
227  uint16_t W) -> BT::RegisterCell {
228  const MachineOperand &Op = MI.getOperand(N);
229  if (Op.isImm())
230  return eIMM(Op.getImm(), W);
231  if (!Op.isReg())
232  return RegisterCell::self(0, W);
233  assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
234  return rc(N);
235  };
236  // Extract RW low bits of the cell.
237  auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
238  -> BT::RegisterCell {
239  assert(RW <= RC.width());
240  return eXTR(RC, 0, RW);
241  };
242  // Extract RW high bits of the cell.
243  auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
244  -> BT::RegisterCell {
245  uint16_t W = RC.width();
246  assert(RW <= W);
247  return eXTR(RC, W-RW, W);
248  };
249  // Extract N-th halfword (counting from the least significant position).
250  auto half = [this] (const BT::RegisterCell &RC, unsigned N)
251  -> BT::RegisterCell {
252  assert(N*16+16 <= RC.width());
253  return eXTR(RC, N*16, N*16+16);
254  };
255  // Shuffle bits (pick even/odd from cells and merge into result).
256  auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
257  uint16_t BW, bool Odd) -> BT::RegisterCell {
258  uint16_t I = Odd, Ws = Rs.width();
259  assert(Ws == Rt.width());
260  RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
261  I += 2;
262  while (I*BW < Ws) {
263  RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
264  I += 2;
265  }
266  return RC;
267  };
268 
269  // The bitwidth of the 0th operand. In most (if not all) of the
270  // instructions below, the 0th operand is the defined register.
271  // Pre-compute the bitwidth here, because it is needed in many cases
272  // cases below.
273  uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
274 
275  switch (Opc) {
276  // Transfer immediate:
277 
278  case A2_tfrsi:
279  case A2_tfrpi:
280  case CONST32:
281  case CONST64:
282  return rr0(eIMM(im(1), W0), Outputs);
283  case PS_false:
284  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
285  case PS_true:
286  return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
287  case PS_fi: {
288  int FI = op(1).getIndex();
289  int Off = op(2).getImm();
290  unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
291  unsigned L = Log2_32(A);
292  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
293  RC.fill(0, L, BT::BitValue::Zero);
294  return rr0(RC, Outputs);
295  }
296 
297  // Transfer register:
298 
299  case A2_tfr:
300  case A2_tfrp:
301  case C2_pxfer_map:
302  return rr0(rc(1), Outputs);
303  case C2_tfrpr: {
304  uint16_t RW = W0;
305  uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
306  assert(PW <= RW);
307  RegisterCell PC = eXTR(rc(1), 0, PW);
308  RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
309  RC.fill(PW, RW, BT::BitValue::Zero);
310  return rr0(RC, Outputs);
311  }
312  case C2_tfrrp: {
313  RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
314  W0 = 8; // XXX Pred size
315  return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs);
316  }
317 
318  // Arithmetic:
319 
320  case A2_abs:
321  case A2_absp:
322  // TODO
323  break;
324 
325  case A2_addsp: {
326  uint16_t W1 = getRegBitWidth(Reg[1]);
327  assert(W0 == 64 && W1 == 32);
328  RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
329  RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
330  return rr0(RC, Outputs);
331  }
332  case A2_add:
333  case A2_addp:
334  return rr0(eADD(rc(1), rc(2)), Outputs);
335  case A2_addi:
336  return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
337  case S4_addi_asl_ri: {
338  RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
339  return rr0(RC, Outputs);
340  }
341  case S4_addi_lsr_ri: {
342  RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
343  return rr0(RC, Outputs);
344  }
345  case S4_addaddi: {
346  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
347  return rr0(RC, Outputs);
348  }
349  case M4_mpyri_addi: {
350  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
351  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
352  return rr0(RC, Outputs);
353  }
354  case M4_mpyrr_addi: {
355  RegisterCell M = eMLS(rc(2), rc(3));
356  RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
357  return rr0(RC, Outputs);
358  }
359  case M4_mpyri_addr_u2: {
360  RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
361  RegisterCell RC = eADD(rc(1), lo(M, W0));
362  return rr0(RC, Outputs);
363  }
364  case M4_mpyri_addr: {
365  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
366  RegisterCell RC = eADD(rc(1), lo(M, W0));
367  return rr0(RC, Outputs);
368  }
369  case M4_mpyrr_addr: {
370  RegisterCell M = eMLS(rc(2), rc(3));
371  RegisterCell RC = eADD(rc(1), lo(M, W0));
372  return rr0(RC, Outputs);
373  }
374  case S4_subaddi: {
375  RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
376  return rr0(RC, Outputs);
377  }
378  case M2_accii: {
379  RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
380  return rr0(RC, Outputs);
381  }
382  case M2_acci: {
383  RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
384  return rr0(RC, Outputs);
385  }
386  case M2_subacc: {
387  RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
388  return rr0(RC, Outputs);
389  }
390  case S2_addasl_rrri: {
391  RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
392  return rr0(RC, Outputs);
393  }
394  case C4_addipc: {
395  RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
396  RPC.fill(0, 2, BT::BitValue::Zero);
397  return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
398  }
399  case A2_sub:
400  case A2_subp:
401  return rr0(eSUB(rc(1), rc(2)), Outputs);
402  case A2_subri:
403  return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
404  case S4_subi_asl_ri: {
405  RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
406  return rr0(RC, Outputs);
407  }
408  case S4_subi_lsr_ri: {
409  RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
410  return rr0(RC, Outputs);
411  }
412  case M2_naccii: {
413  RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
414  return rr0(RC, Outputs);
415  }
416  case M2_nacci: {
417  RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
418  return rr0(RC, Outputs);
419  }
420  // 32-bit negation is done by "Rd = A2_subri 0, Rs"
421  case A2_negp:
422  return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
423 
424  case M2_mpy_up: {
425  RegisterCell M = eMLS(rc(1), rc(2));
426  return rr0(hi(M, W0), Outputs);
427  }
428  case M2_dpmpyss_s0:
429  return rr0(eMLS(rc(1), rc(2)), Outputs);
430  case M2_dpmpyss_acc_s0:
431  return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
432  case M2_dpmpyss_nac_s0:
433  return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
434  case M2_mpyi: {
435  RegisterCell M = eMLS(rc(1), rc(2));
436  return rr0(lo(M, W0), Outputs);
437  }
438  case M2_macsip: {
439  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
440  RegisterCell RC = eADD(rc(1), lo(M, W0));
441  return rr0(RC, Outputs);
442  }
443  case M2_macsin: {
444  RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
445  RegisterCell RC = eSUB(rc(1), lo(M, W0));
446  return rr0(RC, Outputs);
447  }
448  case M2_maci: {
449  RegisterCell M = eMLS(rc(2), rc(3));
450  RegisterCell RC = eADD(rc(1), lo(M, W0));
451  return rr0(RC, Outputs);
452  }
453  case M2_mpysmi: {
454  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
455  return rr0(lo(M, 32), Outputs);
456  }
457  case M2_mpysin: {
458  RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
459  return rr0(lo(M, 32), Outputs);
460  }
461  case M2_mpysip: {
462  RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
463  return rr0(lo(M, 32), Outputs);
464  }
465  case M2_mpyu_up: {
466  RegisterCell M = eMLU(rc(1), rc(2));
467  return rr0(hi(M, W0), Outputs);
468  }
469  case M2_dpmpyuu_s0:
470  return rr0(eMLU(rc(1), rc(2)), Outputs);
471  case M2_dpmpyuu_acc_s0:
472  return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
473  case M2_dpmpyuu_nac_s0:
474  return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
475  //case M2_mpysu_up:
476 
477  // Logical/bitwise:
478 
479  case A2_andir:
480  return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
481  case A2_and:
482  case A2_andp:
483  return rr0(eAND(rc(1), rc(2)), Outputs);
484  case A4_andn:
485  case A4_andnp:
486  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
487  case S4_andi_asl_ri: {
488  RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
489  return rr0(RC, Outputs);
490  }
491  case S4_andi_lsr_ri: {
492  RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
493  return rr0(RC, Outputs);
494  }
495  case M4_and_and:
496  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
497  case M4_and_andn:
498  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
499  case M4_and_or:
500  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
501  case M4_and_xor:
502  return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
503  case A2_orir:
504  return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
505  case A2_or:
506  case A2_orp:
507  return rr0(eORL(rc(1), rc(2)), Outputs);
508  case A4_orn:
509  case A4_ornp:
510  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
511  case S4_ori_asl_ri: {
512  RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
513  return rr0(RC, Outputs);
514  }
515  case S4_ori_lsr_ri: {
516  RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
517  return rr0(RC, Outputs);
518  }
519  case M4_or_and:
520  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
521  case M4_or_andn:
522  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
523  case S4_or_andi:
524  case S4_or_andix: {
525  RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
526  return rr0(RC, Outputs);
527  }
528  case S4_or_ori: {
529  RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
530  return rr0(RC, Outputs);
531  }
532  case M4_or_or:
533  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
534  case M4_or_xor:
535  return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
536  case A2_xor:
537  case A2_xorp:
538  return rr0(eXOR(rc(1), rc(2)), Outputs);
539  case M4_xor_and:
540  return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
541  case M4_xor_andn:
542  return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
543  case M4_xor_or:
544  return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
545  case M4_xor_xacc:
546  return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
547  case A2_not:
548  case A2_notp:
549  return rr0(eNOT(rc(1)), Outputs);
550 
551  case S2_asl_i_r:
552  case S2_asl_i_p:
553  return rr0(eASL(rc(1), im(2)), Outputs);
554  case A2_aslh:
555  return rr0(eASL(rc(1), 16), Outputs);
556  case S2_asl_i_r_acc:
557  case S2_asl_i_p_acc:
558  return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
559  case S2_asl_i_r_nac:
560  case S2_asl_i_p_nac:
561  return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
562  case S2_asl_i_r_and:
563  case S2_asl_i_p_and:
564  return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
565  case S2_asl_i_r_or:
566  case S2_asl_i_p_or:
567  return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
568  case S2_asl_i_r_xacc:
569  case S2_asl_i_p_xacc:
570  return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
571  case S2_asl_i_vh:
572  case S2_asl_i_vw:
573  // TODO
574  break;
575 
576  case S2_asr_i_r:
577  case S2_asr_i_p:
578  return rr0(eASR(rc(1), im(2)), Outputs);
579  case A2_asrh:
580  return rr0(eASR(rc(1), 16), Outputs);
581  case S2_asr_i_r_acc:
582  case S2_asr_i_p_acc:
583  return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
584  case S2_asr_i_r_nac:
585  case S2_asr_i_p_nac:
586  return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
587  case S2_asr_i_r_and:
588  case S2_asr_i_p_and:
589  return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
590  case S2_asr_i_r_or:
591  case S2_asr_i_p_or:
592  return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
593  case S2_asr_i_r_rnd: {
594  // The input is first sign-extended to 64 bits, then the output
595  // is truncated back to 32 bits.
596  assert(W0 == 32);
597  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
598  RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
599  return rr0(eXTR(RC, 0, W0), Outputs);
600  }
601  case S2_asr_i_r_rnd_goodsyntax: {
602  int64_t S = im(2);
603  if (S == 0)
604  return rr0(rc(1), Outputs);
605  // Result: S2_asr_i_r_rnd Rs, u5-1
606  RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
607  RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
608  return rr0(eXTR(RC, 0, W0), Outputs);
609  }
610  case S2_asr_r_vh:
611  case S2_asr_i_vw:
612  case S2_asr_i_svw_trun:
613  // TODO
614  break;
615 
616  case S2_lsr_i_r:
617  case S2_lsr_i_p:
618  return rr0(eLSR(rc(1), im(2)), Outputs);
619  case S2_lsr_i_r_acc:
620  case S2_lsr_i_p_acc:
621  return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
622  case S2_lsr_i_r_nac:
623  case S2_lsr_i_p_nac:
624  return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
625  case S2_lsr_i_r_and:
626  case S2_lsr_i_p_and:
627  return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
628  case S2_lsr_i_r_or:
629  case S2_lsr_i_p_or:
630  return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
631  case S2_lsr_i_r_xacc:
632  case S2_lsr_i_p_xacc:
633  return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
634 
635  case S2_clrbit_i: {
636  RegisterCell RC = rc(1);
637  RC[im(2)] = BT::BitValue::Zero;
638  return rr0(RC, Outputs);
639  }
640  case S2_setbit_i: {
641  RegisterCell RC = rc(1);
642  RC[im(2)] = BT::BitValue::One;
643  return rr0(RC, Outputs);
644  }
645  case S2_togglebit_i: {
646  RegisterCell RC = rc(1);
647  uint16_t BX = im(2);
648  RC[BX] = RC[BX].is(0) ? BT::BitValue::One
649  : RC[BX].is(1) ? BT::BitValue::Zero
650  : BT::BitValue::self();
651  return rr0(RC, Outputs);
652  }
653 
654  case A4_bitspliti: {
655  uint16_t W1 = getRegBitWidth(Reg[1]);
656  uint16_t BX = im(2);
657  // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
659  RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
660  .fill(W1+(W1-BX), W0, Zero);
661  RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
662  RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
663  return rr0(RC, Outputs);
664  }
665  case S4_extract:
666  case S4_extractp:
667  case S2_extractu:
668  case S2_extractup: {
669  uint16_t Wd = im(2), Of = im(3);
670  assert(Wd <= W0);
671  if (Wd == 0)
672  return rr0(eIMM(0, W0), Outputs);
673  // If the width extends beyond the register size, pad the register
674  // with 0 bits.
675  RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
676  RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
677  // Ext is short, need to extend it with 0s or sign bit.
678  RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
679  if (Opc == S2_extractu || Opc == S2_extractup)
680  return rr0(eZXT(RC, Wd), Outputs);
681  return rr0(eSXT(RC, Wd), Outputs);
682  }
683  case S2_insert:
684  case S2_insertp: {
685  uint16_t Wd = im(3), Of = im(4);
686  assert(Wd < W0 && Of < W0);
687  // If Wd+Of exceeds W0, the inserted bits are truncated.
688  if (Wd+Of > W0)
689  Wd = W0-Of;
690  if (Wd == 0)
691  return rr0(rc(1), Outputs);
692  return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
693  }
694 
695  // Bit permutations:
696 
697  case A2_combineii:
698  case A4_combineii:
699  case A4_combineir:
700  case A4_combineri:
701  case A2_combinew:
702  case V6_vcombine:
703  case V6_vcombine_128B:
704  assert(W0 % 2 == 0);
705  return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
706  case A2_combine_ll:
707  case A2_combine_lh:
708  case A2_combine_hl:
709  case A2_combine_hh: {
710  assert(W0 == 32);
711  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
712  // Low half in the output is 0 for _ll and _hl, 1 otherwise:
713  unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
714  // High half in the output is 0 for _ll and _lh, 1 otherwise:
715  unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
716  RegisterCell R1 = rc(1);
717  RegisterCell R2 = rc(2);
718  RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
719  return rr0(RC, Outputs);
720  }
721  case S2_packhl: {
722  assert(W0 == 64);
723  assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
724  RegisterCell R1 = rc(1);
725  RegisterCell R2 = rc(2);
726  RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
727  .cat(half(R1, 1));
728  return rr0(RC, Outputs);
729  }
730  case S2_shuffeb: {
731  RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
732  return rr0(RC, Outputs);
733  }
734  case S2_shuffeh: {
735  RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
736  return rr0(RC, Outputs);
737  }
738  case S2_shuffob: {
739  RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
740  return rr0(RC, Outputs);
741  }
742  case S2_shuffoh: {
743  RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
744  return rr0(RC, Outputs);
745  }
746  case C2_mask: {
747  uint16_t WR = W0;
748  uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
749  assert(WR == 64 && WP == 8);
750  RegisterCell R1 = rc(1);
751  RegisterCell RC(WR);
752  for (uint16_t i = 0; i < WP; ++i) {
753  const BT::BitValue &V = R1[i];
754  BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
755  RC.fill(i*8, i*8+8, F);
756  }
757  return rr0(RC, Outputs);
758  }
759 
760  // Mux:
761 
762  case C2_muxii:
763  case C2_muxir:
764  case C2_muxri:
765  case C2_mux: {
766  BT::BitValue PC0 = rc(1)[0];
767  RegisterCell R2 = cop(2, W0);
768  RegisterCell R3 = cop(3, W0);
769  if (PC0.is(0) || PC0.is(1))
770  return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
771  R2.meet(R3, Reg[0].Reg);
772  return rr0(R2, Outputs);
773  }
774  case C2_vmux:
775  // TODO
776  break;
777 
778  // Sign- and zero-extension:
779 
780  case A2_sxtb:
781  return rr0(eSXT(rc(1), 8), Outputs);
782  case A2_sxth:
783  return rr0(eSXT(rc(1), 16), Outputs);
784  case A2_sxtw: {
785  uint16_t W1 = getRegBitWidth(Reg[1]);
786  assert(W0 == 64 && W1 == 32);
787  RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
788  return rr0(RC, Outputs);
789  }
790  case A2_zxtb:
791  return rr0(eZXT(rc(1), 8), Outputs);
792  case A2_zxth:
793  return rr0(eZXT(rc(1), 16), Outputs);
794 
795  // Bit count:
796 
797  case S2_cl0:
798  case S2_cl0p:
799  // Always produce a 32-bit result.
800  return rr0(eCLB(rc(1), false/*bit*/, 32), Outputs);
801  case S2_cl1:
802  case S2_cl1p:
803  return rr0(eCLB(rc(1), true/*bit*/, 32), Outputs);
804  case S2_clb:
805  case S2_clbp: {
806  uint16_t W1 = getRegBitWidth(Reg[1]);
807  RegisterCell R1 = rc(1);
808  BT::BitValue TV = R1[W1-1];
809  if (TV.is(0) || TV.is(1))
810  return rr0(eCLB(R1, TV, 32), Outputs);
811  break;
812  }
813  case S2_ct0:
814  case S2_ct0p:
815  return rr0(eCTB(rc(1), false/*bit*/, 32), Outputs);
816  case S2_ct1:
817  case S2_ct1p:
818  return rr0(eCTB(rc(1), true/*bit*/, 32), Outputs);
819  case S5_popcountp:
820  // TODO
821  break;
822 
823  case C2_all8: {
824  RegisterCell P1 = rc(1);
825  bool Has0 = false, All1 = true;
826  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
827  if (!P1[i].is(1))
828  All1 = false;
829  if (!P1[i].is(0))
830  continue;
831  Has0 = true;
832  break;
833  }
834  if (!Has0 && !All1)
835  break;
836  RegisterCell RC(W0);
837  RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
838  return rr0(RC, Outputs);
839  }
840  case C2_any8: {
841  RegisterCell P1 = rc(1);
842  bool Has1 = false, All0 = true;
843  for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
844  if (!P1[i].is(0))
845  All0 = false;
846  if (!P1[i].is(1))
847  continue;
848  Has1 = true;
849  break;
850  }
851  if (!Has1 && !All0)
852  break;
853  RegisterCell RC(W0);
854  RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
855  return rr0(RC, Outputs);
856  }
857  case C2_and:
858  return rr0(eAND(rc(1), rc(2)), Outputs);
859  case C2_andn:
860  return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
861  case C2_not:
862  return rr0(eNOT(rc(1)), Outputs);
863  case C2_or:
864  return rr0(eORL(rc(1), rc(2)), Outputs);
865  case C2_orn:
866  return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
867  case C2_xor:
868  return rr0(eXOR(rc(1), rc(2)), Outputs);
869  case C4_and_and:
870  return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
871  case C4_and_andn:
872  return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
873  case C4_and_or:
874  return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
875  case C4_and_orn:
876  return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
877  case C4_or_and:
878  return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
879  case C4_or_andn:
880  return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
881  case C4_or_or:
882  return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
883  case C4_or_orn:
884  return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
885  case C2_bitsclr:
886  case C2_bitsclri:
887  case C2_bitsset:
888  case C4_nbitsclr:
889  case C4_nbitsclri:
890  case C4_nbitsset:
891  // TODO
892  break;
893  case S2_tstbit_i:
894  case S4_ntstbit_i: {
895  BT::BitValue V = rc(1)[im(2)];
896  if (V.is(0) || V.is(1)) {
897  // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
898  bool TV = (Opc == S2_tstbit_i);
900  return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
901  }
902  break;
903  }
904 
905  default:
906  return MachineEvaluator::evaluate(MI, Inputs, Outputs);
907  }
908  #undef im
909  #undef rc
910  #undef op
911  return false;
912 }
913 
915  const CellMapType &Inputs,
916  BranchTargetList &Targets,
917  bool &FallsThru) const {
918  // We need to evaluate one branch at a time. TII::analyzeBranch checks
919  // all the branches in a basic block at once, so we cannot use it.
920  unsigned Opc = BI.getOpcode();
921  bool SimpleBranch = false;
922  bool Negated = false;
923  switch (Opc) {
924  case Hexagon::J2_jumpf:
925  case Hexagon::J2_jumpfpt:
926  case Hexagon::J2_jumpfnew:
927  case Hexagon::J2_jumpfnewpt:
928  Negated = true;
929  case Hexagon::J2_jumpt:
930  case Hexagon::J2_jumptpt:
931  case Hexagon::J2_jumptnew:
932  case Hexagon::J2_jumptnewpt:
933  // Simple branch: if([!]Pn) jump ...
934  // i.e. Op0 = predicate, Op1 = branch target.
935  SimpleBranch = true;
936  break;
937  case Hexagon::J2_jump:
938  Targets.insert(BI.getOperand(0).getMBB());
939  FallsThru = false;
940  return true;
941  default:
942  // If the branch is of unknown type, assume that all successors are
943  // executable.
944  return false;
945  }
946 
947  if (!SimpleBranch)
948  return false;
949 
950  // BI is a conditional branch if we got here.
951  RegisterRef PR = BI.getOperand(0);
952  RegisterCell PC = getCell(PR, Inputs);
953  const BT::BitValue &Test = PC[0];
954 
955  // If the condition is neither true nor false, then it's unknown.
956  if (!Test.is(0) && !Test.is(1))
957  return false;
958 
959  // "Test.is(!Negated)" means "branch condition is true".
960  if (!Test.is(!Negated)) {
961  // Condition known to be false.
962  FallsThru = true;
963  return true;
964  }
965 
966  Targets.insert(BI.getOperand(1).getMBB());
967  FallsThru = false;
968  return true;
969 }
970 
971 bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
972  const CellMapType &Inputs,
973  CellMapType &Outputs) const {
974  using namespace Hexagon;
975 
976  if (TII.isPredicated(MI))
977  return false;
978  assert(MI.mayLoad() && "A load that mayn't?");
979  unsigned Opc = MI.getOpcode();
980 
981  uint16_t BitNum;
982  bool SignEx;
983 
984  switch (Opc) {
985  default:
986  return false;
987 
988 #if 0
989  // memb_fifo
990  case L2_loadalignb_pbr:
991  case L2_loadalignb_pcr:
992  case L2_loadalignb_pi:
993  // memh_fifo
994  case L2_loadalignh_pbr:
995  case L2_loadalignh_pcr:
996  case L2_loadalignh_pi:
997  // membh
998  case L2_loadbsw2_pbr:
999  case L2_loadbsw2_pci:
1000  case L2_loadbsw2_pcr:
1001  case L2_loadbsw2_pi:
1002  case L2_loadbsw4_pbr:
1003  case L2_loadbsw4_pci:
1004  case L2_loadbsw4_pcr:
1005  case L2_loadbsw4_pi:
1006  // memubh
1007  case L2_loadbzw2_pbr:
1008  case L2_loadbzw2_pci:
1009  case L2_loadbzw2_pcr:
1010  case L2_loadbzw2_pi:
1011  case L2_loadbzw4_pbr:
1012  case L2_loadbzw4_pci:
1013  case L2_loadbzw4_pcr:
1014  case L2_loadbzw4_pi:
1015 #endif
1016 
1017  case L2_loadrbgp:
1018  case L2_loadrb_io:
1019  case L2_loadrb_pbr:
1020  case L2_loadrb_pci:
1021  case L2_loadrb_pcr:
1022  case L2_loadrb_pi:
1023  case PS_loadrbabs:
1024  case L4_loadrb_ap:
1025  case L4_loadrb_rr:
1026  case L4_loadrb_ur:
1027  BitNum = 8;
1028  SignEx = true;
1029  break;
1030 
1031  case L2_loadrubgp:
1032  case L2_loadrub_io:
1033  case L2_loadrub_pbr:
1034  case L2_loadrub_pci:
1035  case L2_loadrub_pcr:
1036  case L2_loadrub_pi:
1037  case PS_loadrubabs:
1038  case L4_loadrub_ap:
1039  case L4_loadrub_rr:
1040  case L4_loadrub_ur:
1041  BitNum = 8;
1042  SignEx = false;
1043  break;
1044 
1045  case L2_loadrhgp:
1046  case L2_loadrh_io:
1047  case L2_loadrh_pbr:
1048  case L2_loadrh_pci:
1049  case L2_loadrh_pcr:
1050  case L2_loadrh_pi:
1051  case PS_loadrhabs:
1052  case L4_loadrh_ap:
1053  case L4_loadrh_rr:
1054  case L4_loadrh_ur:
1055  BitNum = 16;
1056  SignEx = true;
1057  break;
1058 
1059  case L2_loadruhgp:
1060  case L2_loadruh_io:
1061  case L2_loadruh_pbr:
1062  case L2_loadruh_pci:
1063  case L2_loadruh_pcr:
1064  case L2_loadruh_pi:
1065  case L4_loadruh_rr:
1066  case PS_loadruhabs:
1067  case L4_loadruh_ap:
1068  case L4_loadruh_ur:
1069  BitNum = 16;
1070  SignEx = false;
1071  break;
1072 
1073  case L2_loadrigp:
1074  case L2_loadri_io:
1075  case L2_loadri_pbr:
1076  case L2_loadri_pci:
1077  case L2_loadri_pcr:
1078  case L2_loadri_pi:
1079  case L2_loadw_locked:
1080  case PS_loadriabs:
1081  case L4_loadri_ap:
1082  case L4_loadri_rr:
1083  case L4_loadri_ur:
1084  case LDriw_pred:
1085  BitNum = 32;
1086  SignEx = true;
1087  break;
1088 
1089  case L2_loadrdgp:
1090  case L2_loadrd_io:
1091  case L2_loadrd_pbr:
1092  case L2_loadrd_pci:
1093  case L2_loadrd_pcr:
1094  case L2_loadrd_pi:
1095  case L4_loadd_locked:
1096  case PS_loadrdabs:
1097  case L4_loadrd_ap:
1098  case L4_loadrd_rr:
1099  case L4_loadrd_ur:
1100  BitNum = 64;
1101  SignEx = true;
1102  break;
1103  }
1104 
1105  const MachineOperand &MD = MI.getOperand(0);
1106  assert(MD.isReg() && MD.isDef());
1107  RegisterRef RD = MD;
1108 
1109  uint16_t W = getRegBitWidth(RD);
1110  assert(W >= BitNum && BitNum > 0);
1111  RegisterCell Res(W);
1112 
1113  for (uint16_t i = 0; i < BitNum; ++i)
1114  Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1115 
1116  if (SignEx) {
1117  const BT::BitValue &Sign = Res[BitNum-1];
1118  for (uint16_t i = BitNum; i < W; ++i)
1119  Res[i] = BT::BitValue::ref(Sign);
1120  } else {
1121  for (uint16_t i = BitNum; i < W; ++i)
1122  Res[i] = BT::BitValue::Zero;
1123  }
1124 
1125  putCell(RD, Res, Outputs);
1126  return true;
1127 }
1128 
1129 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
1130  const CellMapType &Inputs,
1131  CellMapType &Outputs) const {
1132  // If MI defines a formal parameter, but is not a copy (loads are handled
1133  // in evaluateLoad), then it's not clear what to do.
1134  assert(MI.isCopy());
1135 
1136  RegisterRef RD = MI.getOperand(0);
1137  RegisterRef RS = MI.getOperand(1);
1138  assert(RD.Sub == 0);
1140  return false;
1141  RegExtMap::const_iterator F = VRX.find(RD.Reg);
1142  if (F == VRX.end())
1143  return false;
1144 
1145  uint16_t EW = F->second.Width;
1146  // Store RD's cell into the map. This will associate the cell with a virtual
1147  // register, and make zero-/sign-extends possible (otherwise we would be ex-
1148  // tending "self" bit values, which will have no effect, since "self" values
1149  // cannot be references to anything).
1150  putCell(RD, getCell(RS, Inputs), Outputs);
1151 
1152  RegisterCell Res;
1153  // Read RD's cell from the outputs instead of RS's cell from the inputs:
1154  if (F->second.Type == ExtType::SExt)
1155  Res = eSXT(getCell(RD, Outputs), EW);
1156  else if (F->second.Type == ExtType::ZExt)
1157  Res = eZXT(getCell(RD, Outputs), EW);
1158 
1159  putCell(RD, Res, Outputs);
1160  return true;
1161 }
1162 
1163 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1164  using namespace Hexagon;
1165 
1166  bool Is64 = DoubleRegsRegClass.contains(PReg);
1167  assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1168 
1169  static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1170  static const unsigned Phys64[] = { D0, D1, D2 };
1171  const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1172  const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1173 
1174  // Return the first parameter register of the required width.
1175  if (PReg == 0)
1176  return (Width <= 32) ? Phys32[0] : Phys64[0];
1177 
1178  // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1179  // next register.
1180  unsigned Idx32 = 0, Idx64 = 0;
1181  if (!Is64) {
1182  while (Idx32 < Num32) {
1183  if (Phys32[Idx32] == PReg)
1184  break;
1185  Idx32++;
1186  }
1187  Idx64 = Idx32/2;
1188  } else {
1189  while (Idx64 < Num64) {
1190  if (Phys64[Idx64] == PReg)
1191  break;
1192  Idx64++;
1193  }
1194  Idx32 = Idx64*2+1;
1195  }
1196 
1197  if (Width <= 32)
1198  return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1199  return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1200 }
1201 
1202 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1203  typedef MachineRegisterInfo::livein_iterator iterator;
1204  for (iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) {
1205  if (I->first == PReg)
1206  return I->second;
1207  }
1208  return 0;
1209 }
MachineLoop * L
#define R4(n)
LLVM Argument representation.
Definition: Argument.h:34
const TargetRegisterInfo & TRI
Definition: BitTracker.h:433
RegisterCell & fill(uint16_t B, uint16_t E, const BitValue &V)
Definition: BitTracker.cpp:274
size_t i
livein_iterator livein_end() const
MachineBasicBlock * getMBB() const
RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:539
static RegisterCell self(unsigned Reg, uint16_t Width)
Definition: BitTracker.h:317
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
arg_iterator arg_end()
Definition: Function.h:559
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override
uint16_t getRegBitWidth(const RegisterRef &RR) const
Definition: BitTracker.cpp:320
MachineFrameInfo & MFI
#define R2(n)
RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:594
const HexagonInstrInfo & TII
#define op(i)
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:994
RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:550
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri, const HexagonInstrInfo &tii, MachineFunction &mf)
bool evaluate(const MachineInstr &MI, const CellMapType &Inputs, CellMapType &Outputs) const override
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:172
void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const
Definition: BitTracker.cpp:372
RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const
Definition: BitTracker.cpp:685
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const HexagonInstrInfo * TII
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Reg
All possible values of the reg field in the ModR/M byte.
This file contains the simple types necessary to represent the attributes associated with functions a...
#define im(i)
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:500
bool is(unsigned T) const
Definition: BitTracker.h:165
#define F(x, y, z)
Definition: MD5.cpp:51
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:136
RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:467
int64_t getImm() const
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
#define rc(i)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:665
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:520
bool isCopy() const
Definition: MachineInstr.h:807
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const
Definition: BitTracker.cpp:345
arg_iterator arg_begin()
Definition: Function.h:550
RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:655
unsigned getIntegerBitWidth() const
Definition: DerivedTypes.h:96
RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const
Definition: BitTracker.cpp:676
RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const
Definition: BitTracker.cpp:645
unsigned getSubReg() const
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:213
DenseMapIterator< KeyT, ValueT, KeyInfoT, BucketT, true > const_iterator
Definition: DenseMap.h:64
RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:434
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
MachineFunction & MF
RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:572
Iterator for intrusive lists based on ilist_node.
static BitValue self(const BitRef &Self=BitRef())
Definition: BitTracker.h:236
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:230
RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const
Definition: BitTracker.cpp:529
livein_iterator livein_begin() const
MachineRegisterInfo & MRI
Definition: BitTracker.h:434
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned Log2_32(uint32_t Value)
Log2_32 - This function returns the floor log base 2 of the specified value, -1 if the value is zero...
Definition: MathExtras.h:513
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:176
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:195
RegisterCell & insert(const RegisterCell &RC, const BitMask &M)
Definition: BitTracker.cpp:214
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
RegisterCell & cat(const RegisterCell &RC)
Definition: BitTracker.cpp:282
BitTracker::RegisterRef RegisterRef
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const
Definition: BitTracker.cpp:510
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1099
iterator end()
Definition: DenseMap.h:69
iterator find(const KeyT &Val)
Definition: DenseMap.h:127
RegisterCell eIMM(int64_t V, uint16_t W) const
Definition: BitTracker.cpp:414
static volatile int Zero
BitTracker::CellMapType CellMapType
std::vector< std::pair< unsigned, unsigned > >::const_iterator livein_iterator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A vector that has set insertion semantics.
Definition: SetVector.h:41
RegisterCell eNOT(const RegisterCell &A1) const
Definition: BitTracker.cpp:614
bool meet(const RegisterCell &RC, unsigned SelfR)
Definition: BitTracker.cpp:201
IRTranslator LLVM IR MI
static RegisterCell ref(const RegisterCell &C)
Definition: BitTracker.h:333
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
BitTracker::RegisterCell RegisterCell
BitTracker BT
static BitValue ref(const BitValue &V)
Definition: BitTracker.h:227
RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2, uint16_t AtN) const
Definition: BitTracker.cpp:697
char * PC