LLVM  4.0.0
AArch64InstructionSelector.h
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1 //===- AArch64InstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the targeting of the InstructionSelector class for
11 /// AArch64.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H
16 
18 
19 namespace llvm {
20 
21 class AArch64InstrInfo;
22 class AArch64RegisterBankInfo;
23 class AArch64RegisterInfo;
24 class AArch64Subtarget;
25 class AArch64TargetMachine;
26 
28 public:
30  const AArch64Subtarget &STI,
31  const AArch64RegisterBankInfo &RBI);
32 
33  bool select(MachineInstr &I) const override;
34 
35 private:
36  /// tblgen-erated 'select' implementation, used as the initial selector for
37  /// the patterns that don't require complex C++.
38  bool selectImpl(MachineInstr &I) const;
39 
40  const AArch64TargetMachine &TM;
41  const AArch64Subtarget &STI;
42  const AArch64InstrInfo &TII;
43  const AArch64RegisterInfo &TRI;
44  const AArch64RegisterBankInfo &RBI;
45 };
46 
47 } // end namespace llvm
48 
49 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64INSTRUCTIONSELECTOR_H
bool select(MachineInstr &I) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:52
This class provides the information for the target register banks.
#define I(x, y, z)
Definition: MD5.cpp:54
AArch64InstructionSelector(const AArch64TargetMachine &TM, const AArch64Subtarget &STI, const AArch64RegisterBankInfo &RBI)