LLVM  4.0.0
MachineInstr.h
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1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
12 // the back end.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
18 
19 #include "llvm/ADT/DenseMapInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/ilist.h"
22 #include "llvm/ADT/ilist_node.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/MC/MCInstrDesc.h"
31 
32 namespace llvm {
33 
34 class StringRef;
35 template <typename T> class ArrayRef;
36 template <typename T> class SmallVectorImpl;
37 class DILocalVariable;
38 class DIExpression;
39 class TargetInstrInfo;
40 class TargetRegisterClass;
41 class TargetRegisterInfo;
42 class MachineFunction;
43 class MachineMemOperand;
44 
45 //===----------------------------------------------------------------------===//
46 /// Representation of each machine instruction.
47 ///
48 /// This class isn't a POD type, but it must have a trivial destructor. When a
49 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
50 /// without having their destructor called.
51 ///
53  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
54  ilist_sentinel_tracking<true>> {
55 public:
57 
58  /// Flags to specify different kinds of comments to output in
59  /// assembly code. These flags carry semantic information not
60  /// otherwise easily derivable from the IR text.
61  ///
62  enum CommentFlag {
63  ReloadReuse = 0x1 // higher bits are reserved for target dep comments.
64  };
65 
66  enum MIFlag {
67  NoFlags = 0,
68  FrameSetup = 1 << 0, // Instruction is used as a part of
69  // function frame setup code.
70  FrameDestroy = 1 << 1, // Instruction is used as a part of
71  // function frame destruction code.
72  BundledPred = 1 << 2, // Instruction has bundled predecessors.
73  BundledSucc = 1 << 3 // Instruction has bundled successors.
74  };
75 private:
76  const MCInstrDesc *MCID; // Instruction descriptor.
77  MachineBasicBlock *Parent; // Pointer to the owning basic block.
78 
79  // Operands are allocated by an ArrayRecycler.
80  MachineOperand *Operands; // Pointer to the first operand.
81  unsigned NumOperands; // Number of operands on instruction.
82  typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
83  OperandCapacity CapOperands; // Capacity of the Operands array.
84 
85  uint8_t Flags; // Various bits of additional
86  // information about machine
87  // instruction.
88 
89  uint8_t AsmPrinterFlags; // Various bits of information used by
90  // the AsmPrinter to emit helpful
91  // comments. This is *not* semantic
92  // information. Do not use this for
93  // anything other than to convey comment
94  // information to AsmPrinter.
95 
96  uint8_t NumMemRefs; // Information on memory references.
97  // Note that MemRefs == nullptr, means 'don't know', not 'no memory access'.
98  // Calling code must treat missing information conservatively. If the number
99  // of memory operands required to be precise exceeds the maximum value of
100  // NumMemRefs - currently 256 - we remove the operands entirely. Note also
101  // that this is a non-owning reference to a shared copy on write buffer owned
102  // by the MachineFunction and created via MF.allocateMemRefsArray.
103  mmo_iterator MemRefs;
104 
105  DebugLoc debugLoc; // Source line information.
106 
107  MachineInstr(const MachineInstr&) = delete;
108  void operator=(const MachineInstr&) = delete;
109  // Use MachineFunction::DeleteMachineInstr() instead.
110  ~MachineInstr() = delete;
111 
112  // Intrusive list support
113  friend struct ilist_traits<MachineInstr>;
115  void setParent(MachineBasicBlock *P) { Parent = P; }
116 
117  /// This constructor creates a copy of the given
118  /// MachineInstr in the given MachineFunction.
120 
121  /// This constructor create a MachineInstr and add the implicit operands.
122  /// It reserves space for number of operands specified by
123  /// MCInstrDesc. An explicit DebugLoc is supplied.
125  bool NoImp = false);
126 
127  // MachineInstrs are pool-allocated and owned by MachineFunction.
128  friend class MachineFunction;
129 
130 public:
131  const MachineBasicBlock* getParent() const { return Parent; }
132  MachineBasicBlock* getParent() { return Parent; }
133 
134  /// Return the asm printer flags bitvector.
135  uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
136 
137  /// Clear the AsmPrinter bitvector.
138  void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
139 
140  /// Return whether an AsmPrinter flag is set.
142  return AsmPrinterFlags & Flag;
143  }
144 
145  /// Set a flag for the AsmPrinter.
146  void setAsmPrinterFlag(uint8_t Flag) {
147  AsmPrinterFlags |= Flag;
148  }
149 
150  /// Clear specific AsmPrinter flags.
152  AsmPrinterFlags &= ~Flag;
153  }
154 
155  /// Return the MI flags bitvector.
156  uint8_t getFlags() const {
157  return Flags;
158  }
159 
160  /// Return whether an MI flag is set.
161  bool getFlag(MIFlag Flag) const {
162  return Flags & Flag;
163  }
164 
165  /// Set a MI flag.
167  Flags |= (uint8_t)Flag;
168  }
169 
170  void setFlags(unsigned flags) {
171  // Filter out the automatically maintained flags.
172  unsigned Mask = BundledPred | BundledSucc;
173  Flags = (Flags & Mask) | (flags & ~Mask);
174  }
175 
176  /// clearFlag - Clear a MI flag.
178  Flags &= ~((uint8_t)Flag);
179  }
180 
181 
182  /// Return true if MI is in a bundle (but not the first MI in a bundle).
183  ///
184  /// A bundle looks like this before it's finalized:
185  /// ----------------
186  /// | MI |
187  /// ----------------
188  /// |
189  /// ----------------
190  /// | MI * |
191  /// ----------------
192  /// |
193  /// ----------------
194  /// | MI * |
195  /// ----------------
196  /// In this case, the first MI starts a bundle but is not inside a bundle, the
197  /// next 2 MIs are considered "inside" the bundle.
198  ///
199  /// After a bundle is finalized, it looks like this:
200  /// ----------------
201  /// | Bundle |
202  /// ----------------
203  /// |
204  /// ----------------
205  /// | MI * |
206  /// ----------------
207  /// |
208  /// ----------------
209  /// | MI * |
210  /// ----------------
211  /// |
212  /// ----------------
213  /// | MI * |
214  /// ----------------
215  /// The first instruction has the special opcode "BUNDLE". It's not "inside"
216  /// a bundle, but the next three MIs are.
217  bool isInsideBundle() const {
218  return getFlag(BundledPred);
219  }
220 
221  /// Return true if this instruction part of a bundle. This is true
222  /// if either itself or its following instruction is marked "InsideBundle".
223  bool isBundled() const {
224  return isBundledWithPred() || isBundledWithSucc();
225  }
226 
227  /// Return true if this instruction is part of a bundle, and it is not the
228  /// first instruction in the bundle.
229  bool isBundledWithPred() const { return getFlag(BundledPred); }
230 
231  /// Return true if this instruction is part of a bundle, and it is not the
232  /// last instruction in the bundle.
233  bool isBundledWithSucc() const { return getFlag(BundledSucc); }
234 
235  /// Bundle this instruction with its predecessor. This can be an unbundled
236  /// instruction, or it can be the first instruction in a bundle.
237  void bundleWithPred();
238 
239  /// Bundle this instruction with its successor. This can be an unbundled
240  /// instruction, or it can be the last instruction in a bundle.
241  void bundleWithSucc();
242 
243  /// Break bundle above this instruction.
244  void unbundleFromPred();
245 
246  /// Break bundle below this instruction.
247  void unbundleFromSucc();
248 
249  /// Returns the debug location id of this MachineInstr.
250  const DebugLoc &getDebugLoc() const { return debugLoc; }
251 
252  /// Return the debug variable referenced by
253  /// this DBG_VALUE instruction.
254  const DILocalVariable *getDebugVariable() const;
255 
256  /// Return the complex address expression referenced by
257  /// this DBG_VALUE instruction.
258  const DIExpression *getDebugExpression() const;
259 
260  /// Emit an error referring to the source location of this instruction.
261  /// This should only be used for inline assembly that is somehow
262  /// impossible to compile. Other errors should have been handled much
263  /// earlier.
264  ///
265  /// If this method returns, the caller should try to recover from the error.
266  ///
267  void emitError(StringRef Msg) const;
268 
269  /// Returns the target instruction descriptor of this MachineInstr.
270  const MCInstrDesc &getDesc() const { return *MCID; }
271 
272  /// Returns the opcode of this MachineInstr.
273  unsigned getOpcode() const { return MCID->Opcode; }
274 
275  /// Access to explicit operands of the instruction.
276  ///
277  unsigned getNumOperands() const { return NumOperands; }
278 
279  const MachineOperand& getOperand(unsigned i) const {
280  assert(i < getNumOperands() && "getOperand() out of range!");
281  return Operands[i];
282  }
284  assert(i < getNumOperands() && "getOperand() out of range!");
285  return Operands[i];
286  }
287 
288  /// Returns the number of non-implicit operands.
289  unsigned getNumExplicitOperands() const;
290 
291  /// iterator/begin/end - Iterate over all operands of a machine instruction.
294 
295  mop_iterator operands_begin() { return Operands; }
296  mop_iterator operands_end() { return Operands + NumOperands; }
297 
298  const_mop_iterator operands_begin() const { return Operands; }
299  const_mop_iterator operands_end() const { return Operands + NumOperands; }
300 
303  }
306  }
308  return make_range(operands_begin(),
310  }
312  return make_range(operands_begin(),
314  }
317  }
320  }
321  /// Returns a range over all explicit operands that are register definitions.
322  /// Implicit definition are not included!
324  return make_range(operands_begin(),
325  operands_begin() + getDesc().getNumDefs());
326  }
327  /// \copydoc defs()
329  return make_range(operands_begin(),
330  operands_begin() + getDesc().getNumDefs());
331  }
332  /// Returns a range that includes all operands that are register uses.
333  /// This may include unrelated operands which are not register uses.
335  return make_range(operands_begin() + getDesc().getNumDefs(),
336  operands_end());
337  }
338  /// \copydoc uses()
340  return make_range(operands_begin() + getDesc().getNumDefs(),
341  operands_end());
342  }
344  return make_range(operands_begin() + getDesc().getNumDefs(),
346  }
348  return make_range(operands_begin() + getDesc().getNumDefs(),
350  }
351 
352  /// Returns the number of the operand iterator \p I points to.
354  return I - operands_begin();
355  }
356 
357  /// Access to memory operands of the instruction
358  mmo_iterator memoperands_begin() const { return MemRefs; }
359  mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
360  /// Return true if we don't have any memory operands which described the the
361  /// memory access done by this instruction. If this is true, calling code
362  /// must be conservative.
363  bool memoperands_empty() const { return NumMemRefs == 0; }
364 
367  }
370  }
371 
372  /// Return true if this instruction has exactly one MachineMemOperand.
373  bool hasOneMemOperand() const {
374  return NumMemRefs == 1;
375  }
376 
377  /// API for querying MachineInstr properties. They are the same as MCInstrDesc
378  /// queries but they are bundle aware.
379 
380  enum QueryType {
381  IgnoreBundle, // Ignore bundles
382  AnyInBundle, // Return true if any instruction in bundle has property
383  AllInBundle // Return true if all instructions in bundle have property
384  };
385 
386  /// Return true if the instruction (or in the case of a bundle,
387  /// the instructions inside the bundle) has the specified property.
388  /// The first argument is the property being queried.
389  /// The second argument indicates whether the query should look inside
390  /// instruction bundles.
391  bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
392  // Inline the fast path for unbundled or bundle-internal instructions.
393  if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
394  return getDesc().getFlags() & (1ULL << MCFlag);
395 
396  // If this is the first instruction in a bundle, take the slow path.
397  return hasPropertyInBundle(1ULL << MCFlag, Type);
398  }
399 
400  /// Return true if this instruction can have a variable number of operands.
401  /// In this case, the variable operands will be after the normal
402  /// operands but before the implicit definitions and uses (if any are
403  /// present).
406  }
407 
408  /// Set if this instruction has an optional definition, e.g.
409  /// ARM instructions which can set condition code if 's' bit is set.
412  }
413 
414  /// Return true if this is a pseudo instruction that doesn't
415  /// correspond to a real machine instruction.
417  return hasProperty(MCID::Pseudo, Type);
418  }
419 
421  return hasProperty(MCID::Return, Type);
422  }
423 
425  return hasProperty(MCID::Call, Type);
426  }
427 
428  /// Returns true if the specified instruction stops control flow
429  /// from executing the instruction immediately following it. Examples include
430  /// unconditional branches and return instructions.
432  return hasProperty(MCID::Barrier, Type);
433  }
434 
435  /// Returns true if this instruction part of the terminator for a basic block.
436  /// Typically this is things like return and branch instructions.
437  ///
438  /// Various passes use this to insert code into the bottom of a basic block,
439  /// but before control flow occurs.
442  }
443 
444  /// Returns true if this is a conditional, unconditional, or indirect branch.
445  /// Predicates below can be used to discriminate between
446  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
447  /// get more information.
449  return hasProperty(MCID::Branch, Type);
450  }
451 
452  /// Return true if this is an indirect branch, such as a
453  /// branch through a register.
456  }
457 
458  /// Return true if this is a branch which may fall
459  /// through to the next instruction or may transfer control flow to some other
460  /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
461  /// information about this branch.
464  }
465 
466  /// Return true if this is a branch which always
467  /// transfers control flow to some other block. The
468  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
469  /// about this branch.
472  }
473 
474  /// Return true if this instruction has a predicate operand that
475  /// controls execution. It may be set to 'always', or may be set to other
476  /// values. There are various methods in TargetInstrInfo that can be used to
477  /// control and modify the predicate in this instruction.
479  // If it's a bundle than all bundled instructions must be predicable for this
480  // to return true.
482  }
483 
484  /// Return true if this instruction is a comparison.
486  return hasProperty(MCID::Compare, Type);
487  }
488 
489  /// Return true if this instruction is a move immediate
490  /// (including conditional moves) instruction.
492  return hasProperty(MCID::MoveImm, Type);
493  }
494 
495  /// Return true if this instruction is a bitcast instruction.
497  return hasProperty(MCID::Bitcast, Type);
498  }
499 
500  /// Return true if this instruction is a select instruction.
502  return hasProperty(MCID::Select, Type);
503  }
504 
505  /// Return true if this instruction cannot be safely duplicated.
506  /// For example, if the instruction has a unique labels attached
507  /// to it, duplicating it would cause multiple definition errors.
510  }
511 
512  /// Return true if this instruction is convergent.
513  /// Convergent instructions can not be made control-dependent on any
514  /// additional values.
516  if (isInlineAsm()) {
517  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
518  if (ExtraInfo & InlineAsm::Extra_IsConvergent)
519  return true;
520  }
522  }
523 
524  /// Returns true if the specified instruction has a delay slot
525  /// which must be filled by the code generator.
528  }
529 
530  /// Return true for instructions that can be folded as
531  /// memory operands in other instructions. The most common use for this
532  /// is instructions that are simple loads from memory that don't modify
533  /// the loaded value in any way, but it can also be used for instructions
534  /// that can be expressed as constant-pool loads, such as V_SETALLONES
535  /// on x86, to allow them to be folded when it is beneficial.
536  /// This should only be set on instructions that return a value in their
537  /// only virtual register definition.
540  }
541 
542  /// \brief Return true if this instruction behaves
543  /// the same way as the generic REG_SEQUENCE instructions.
544  /// E.g., on ARM,
545  /// dX VMOVDRR rY, rZ
546  /// is equivalent to
547  /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
548  ///
549  /// Note that for the optimizers to be able to take advantage of
550  /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
551  /// override accordingly.
554  }
555 
556  /// \brief Return true if this instruction behaves
557  /// the same way as the generic EXTRACT_SUBREG instructions.
558  /// E.g., on ARM,
559  /// rX, rY VMOVRRD dZ
560  /// is equivalent to two EXTRACT_SUBREG:
561  /// rX = EXTRACT_SUBREG dZ, ssub_0
562  /// rY = EXTRACT_SUBREG dZ, ssub_1
563  ///
564  /// Note that for the optimizers to be able to take advantage of
565  /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
566  /// override accordingly.
569  }
570 
571  /// \brief Return true if this instruction behaves
572  /// the same way as the generic INSERT_SUBREG instructions.
573  /// E.g., on ARM,
574  /// dX = VSETLNi32 dY, rZ, Imm
575  /// is equivalent to a INSERT_SUBREG:
576  /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
577  ///
578  /// Note that for the optimizers to be able to take advantage of
579  /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
580  /// override accordingly.
583  }
584 
585  //===--------------------------------------------------------------------===//
586  // Side Effect Analysis
587  //===--------------------------------------------------------------------===//
588 
589  /// Return true if this instruction could possibly read memory.
590  /// Instructions with this flag set are not necessarily simple load
591  /// instructions, they may load a value and modify it, for example.
593  if (isInlineAsm()) {
594  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
595  if (ExtraInfo & InlineAsm::Extra_MayLoad)
596  return true;
597  }
598  return hasProperty(MCID::MayLoad, Type);
599  }
600 
601  /// Return true if this instruction could possibly modify memory.
602  /// Instructions with this flag set are not necessarily simple store
603  /// instructions, they may store a modified value based on their operands, or
604  /// may not actually modify anything, for example.
606  if (isInlineAsm()) {
607  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
608  if (ExtraInfo & InlineAsm::Extra_MayStore)
609  return true;
610  }
612  }
613 
614  /// Return true if this instruction could possibly read or modify memory.
616  return mayLoad(Type) || mayStore(Type);
617  }
618 
619  //===--------------------------------------------------------------------===//
620  // Flags that indicate whether an instruction can be modified by a method.
621  //===--------------------------------------------------------------------===//
622 
623  /// Return true if this may be a 2- or 3-address
624  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
625  /// result if Y and Z are exchanged. If this flag is set, then the
626  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
627  /// instruction.
628  ///
629  /// Note that this flag may be set on instructions that are only commutable
630  /// sometimes. In these cases, the call to commuteInstruction will fail.
631  /// Also note that some instructions require non-trivial modification to
632  /// commute them.
635  }
636 
637  /// Return true if this is a 2-address instruction
638  /// which can be changed into a 3-address instruction if needed. Doing this
639  /// transformation can be profitable in the register allocator, because it
640  /// means that the instruction can use a 2-address form if possible, but
641  /// degrade into a less efficient form if the source and dest register cannot
642  /// be assigned to the same register. For example, this allows the x86
643  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
644  /// is the same speed as the shift but has bigger code size.
645  ///
646  /// If this returns true, then the target must implement the
647  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
648  /// is allowed to fail if the transformation isn't valid for this specific
649  /// instruction (e.g. shl reg, 4 on x86).
650  ///
653  }
654 
655  /// Return true if this instruction requires
656  /// custom insertion support when the DAG scheduler is inserting it into a
657  /// machine basic block. If this is true for the instruction, it basically
658  /// means that it is a pseudo instruction used at SelectionDAG time that is
659  /// expanded out into magic code by the target when MachineInstrs are formed.
660  ///
661  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
662  /// is used to insert this into the MachineBasicBlock.
665  }
666 
667  /// Return true if this instruction requires *adjustment*
668  /// after instruction selection by calling a target hook. For example, this
669  /// can be used to fill in ARM 's' optional operand depending on whether
670  /// the conditional flag register is used.
673  }
674 
675  /// Returns true if this instruction is a candidate for remat.
676  /// This flag is deprecated, please don't use it anymore. If this
677  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
678  /// verify the instruction is really rematable.
680  // It's only possible to re-mat a bundle if all bundled instructions are
681  // re-materializable.
683  }
684 
685  /// Returns true if this instruction has the same cost (or less) than a move
686  /// instruction. This is useful during certain types of optimizations
687  /// (e.g., remat during two-address conversion or machine licm)
688  /// where we would like to remat or hoist the instruction, but not if it costs
689  /// more than moving the instruction into the appropriate register. Note, we
690  /// are not marking copies from and to the same register class with this flag.
692  // Only returns true for a bundle if all bundled instructions are cheap.
694  }
695 
696  /// Returns true if this instruction source operands
697  /// have special register allocation requirements that are not captured by the
698  /// operand register classes. e.g. ARM::STRD's two source registers must be an
699  /// even / odd pair, ARM::STM registers have to be in ascending order.
700  /// Post-register allocation passes should not attempt to change allocations
701  /// for sources of instructions with this flag.
704  }
705 
706  /// Returns true if this instruction def operands
707  /// have special register allocation requirements that are not captured by the
708  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
709  /// even / odd pair, ARM::LDM registers have to be in ascending order.
710  /// Post-register allocation passes should not attempt to change allocations
711  /// for definitions of instructions with this flag.
714  }
715 
716 
717  enum MICheckType {
718  CheckDefs, // Check all operands for equality
719  CheckKillDead, // Check all operands including kill / dead markers
720  IgnoreDefs, // Ignore all definitions
721  IgnoreVRegDefs // Ignore virtual register definitions
722  };
723 
724  /// Return true if this instruction is identical to \p Other.
725  /// Two instructions are identical if they have the same opcode and all their
726  /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
727  /// Note that this means liveness related flags (dead, undef, kill) do not
728  /// affect the notion of identical.
729  bool isIdenticalTo(const MachineInstr &Other,
730  MICheckType Check = CheckDefs) const;
731 
732  /// Unlink 'this' from the containing basic block, and return it without
733  /// deleting it.
734  ///
735  /// This function can not be used on bundled instructions, use
736  /// removeFromBundle() to remove individual instructions from a bundle.
738 
739  /// Unlink this instruction from its basic block and return it without
740  /// deleting it.
741  ///
742  /// If the instruction is part of a bundle, the other instructions in the
743  /// bundle remain bundled.
745 
746  /// Unlink 'this' from the containing basic block and delete it.
747  ///
748  /// If this instruction is the header of a bundle, the whole bundle is erased.
749  /// This function can not be used for instructions inside a bundle, use
750  /// eraseFromBundle() to erase individual bundled instructions.
751  void eraseFromParent();
752 
753  /// Unlink 'this' from the containing basic block and delete it.
754  ///
755  /// For all definitions mark their uses in DBG_VALUE nodes
756  /// as undefined. Otherwise like eraseFromParent().
758 
759  /// Unlink 'this' form its basic block and delete it.
760  ///
761  /// If the instruction is part of a bundle, the other instructions in the
762  /// bundle remain bundled.
763  void eraseFromBundle();
764 
765  bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
766  bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
767 
768  /// Returns true if the MachineInstr represents a label.
769  bool isLabel() const { return isEHLabel() || isGCLabel(); }
770  bool isCFIInstruction() const {
771  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
772  }
773 
774  // True if the instruction represents a position in the function.
775  bool isPosition() const { return isLabel() || isCFIInstruction(); }
776 
777  bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
778  /// A DBG_VALUE is indirect iff the first operand is a register and
779  /// the second operand is an immediate.
780  bool isIndirectDebugValue() const {
781  return isDebugValue()
782  && getOperand(0).isReg()
783  && getOperand(1).isImm();
784  }
785 
786  bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
787  bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
788  bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
789  bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
790  bool isMSInlineAsm() const {
792  }
793  bool isStackAligningInlineAsm() const;
795  bool isInsertSubreg() const {
796  return getOpcode() == TargetOpcode::INSERT_SUBREG;
797  }
798  bool isSubregToReg() const {
799  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
800  }
801  bool isRegSequence() const {
802  return getOpcode() == TargetOpcode::REG_SEQUENCE;
803  }
804  bool isBundle() const {
805  return getOpcode() == TargetOpcode::BUNDLE;
806  }
807  bool isCopy() const {
808  return getOpcode() == TargetOpcode::COPY;
809  }
810  bool isFullCopy() const {
811  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
812  }
813  bool isExtractSubreg() const {
814  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
815  }
816 
817  /// Return true if the instruction behaves like a copy.
818  /// This does not include native copy instructions.
819  bool isCopyLike() const {
820  return isCopy() || isSubregToReg();
821  }
822 
823  /// Return true is the instruction is an identity copy.
824  bool isIdentityCopy() const {
825  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
827  }
828 
829  /// Return true if this is a transient instruction that is
830  /// either very likely to be eliminated during register allocation (such as
831  /// copy-like instructions), or if this instruction doesn't have an
832  /// execution-time cost.
833  bool isTransient() const {
834  switch(getOpcode()) {
835  default: return false;
836  // Copy-like instructions are usually eliminated during register allocation.
837  case TargetOpcode::PHI:
838  case TargetOpcode::COPY:
839  case TargetOpcode::INSERT_SUBREG:
840  case TargetOpcode::SUBREG_TO_REG:
841  case TargetOpcode::REG_SEQUENCE:
842  // Pseudo-instructions that don't produce any real output.
843  case TargetOpcode::IMPLICIT_DEF:
844  case TargetOpcode::KILL:
845  case TargetOpcode::CFI_INSTRUCTION:
847  case TargetOpcode::GC_LABEL:
848  case TargetOpcode::DBG_VALUE:
849  return true;
850  }
851  }
852 
853  /// Return the number of instructions inside the MI bundle, excluding the
854  /// bundle header.
855  ///
856  /// This is the number of instructions that MachineBasicBlock::iterator
857  /// skips, 0 for unbundled instructions.
858  unsigned getBundleSize() const;
859 
860  /// Return true if the MachineInstr reads the specified register.
861  /// If TargetRegisterInfo is passed, then it also checks if there
862  /// is a read of a super-register.
863  /// This does not count partial redefines of virtual registers as reads:
864  /// %reg1024:6 = OP.
865  bool readsRegister(unsigned Reg,
866  const TargetRegisterInfo *TRI = nullptr) const {
867  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
868  }
869 
870  /// Return true if the MachineInstr reads the specified virtual register.
871  /// Take into account that a partial define is a
872  /// read-modify-write operation.
873  bool readsVirtualRegister(unsigned Reg) const {
874  return readsWritesVirtualRegister(Reg).first;
875  }
876 
877  /// Return a pair of bools (reads, writes) indicating if this instruction
878  /// reads or writes Reg. This also considers partial defines.
879  /// If Ops is not null, all operand indices for Reg are added.
880  std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
881  SmallVectorImpl<unsigned> *Ops = nullptr) const;
882 
883  /// Return true if the MachineInstr kills the specified register.
884  /// If TargetRegisterInfo is passed, then it also checks if there is
885  /// a kill of a super-register.
886  bool killsRegister(unsigned Reg,
887  const TargetRegisterInfo *TRI = nullptr) const {
888  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
889  }
890 
891  /// Return true if the MachineInstr fully defines the specified register.
892  /// If TargetRegisterInfo is passed, then it also checks
893  /// if there is a def of a super-register.
894  /// NOTE: It's ignoring subreg indices on virtual registers.
895  bool definesRegister(unsigned Reg,
896  const TargetRegisterInfo *TRI = nullptr) const {
897  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
898  }
899 
900  /// Return true if the MachineInstr modifies (fully define or partially
901  /// define) the specified register.
902  /// NOTE: It's ignoring subreg indices on virtual registers.
903  bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
904  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
905  }
906 
907  /// Returns true if the register is dead in this machine instruction.
908  /// If TargetRegisterInfo is passed, then it also checks
909  /// if there is a dead def of a super-register.
910  bool registerDefIsDead(unsigned Reg,
911  const TargetRegisterInfo *TRI = nullptr) const {
912  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
913  }
914 
915  /// Returns true if the MachineInstr has an implicit-use operand of exactly
916  /// the given register (not considering sub/super-registers).
917  bool hasRegisterImplicitUseOperand(unsigned Reg) const;
918 
919  /// Returns the operand index that is a use of the specific register or -1
920  /// if it is not found. It further tightens the search criteria to a use
921  /// that kills the register if isKill is true.
922  int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
923  const TargetRegisterInfo *TRI = nullptr) const;
924 
925  /// Wrapper for findRegisterUseOperandIdx, it returns
926  /// a pointer to the MachineOperand rather than an index.
928  const TargetRegisterInfo *TRI = nullptr) {
929  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
930  return (Idx == -1) ? nullptr : &getOperand(Idx);
931  }
932 
934  unsigned Reg, bool isKill = false,
935  const TargetRegisterInfo *TRI = nullptr) const {
936  return const_cast<MachineInstr *>(this)->
937  findRegisterUseOperand(Reg, isKill, TRI);
938  }
939 
940  /// Returns the operand index that is a def of the specified register or
941  /// -1 if it is not found. If isDead is true, defs that are not dead are
942  /// skipped. If Overlap is true, then it also looks for defs that merely
943  /// overlap the specified register. If TargetRegisterInfo is non-null,
944  /// then it also checks if there is a def of a super-register.
945  /// This may also return a register mask operand when Overlap is true.
946  int findRegisterDefOperandIdx(unsigned Reg,
947  bool isDead = false, bool Overlap = false,
948  const TargetRegisterInfo *TRI = nullptr) const;
949 
950  /// Wrapper for findRegisterDefOperandIdx, it returns
951  /// a pointer to the MachineOperand rather than an index.
952  MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
953  const TargetRegisterInfo *TRI = nullptr) {
954  int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
955  return (Idx == -1) ? nullptr : &getOperand(Idx);
956  }
957 
958  /// Find the index of the first operand in the
959  /// operand list that is used to represent the predicate. It returns -1 if
960  /// none is found.
961  int findFirstPredOperandIdx() const;
962 
963  /// Find the index of the flag word operand that
964  /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
965  /// getOperand(OpIdx) does not belong to an inline asm operand group.
966  ///
967  /// If GroupNo is not NULL, it will receive the number of the operand group
968  /// containing OpIdx.
969  ///
970  /// The flag operand is an immediate that can be decoded with methods like
971  /// InlineAsm::hasRegClassConstraint().
972  ///
973  int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
974 
975  /// Compute the static register class constraint for operand OpIdx.
976  /// For normal instructions, this is derived from the MCInstrDesc.
977  /// For inline assembly it is derived from the flag words.
978  ///
979  /// Returns NULL if the static register class constraint cannot be
980  /// determined.
981  ///
982  const TargetRegisterClass*
983  getRegClassConstraint(unsigned OpIdx,
984  const TargetInstrInfo *TII,
985  const TargetRegisterInfo *TRI) const;
986 
987  /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
988  /// the given \p CurRC.
989  /// If \p ExploreBundle is set and MI is part of a bundle, all the
990  /// instructions inside the bundle will be taken into account. In other words,
991  /// this method accumulates all the constraints of the operand of this MI and
992  /// the related bundle if MI is a bundle or inside a bundle.
993  ///
994  /// Returns the register class that satisfies both \p CurRC and the
995  /// constraints set by MI. Returns NULL if such a register class does not
996  /// exist.
997  ///
998  /// \pre CurRC must not be NULL.
1000  unsigned Reg, const TargetRegisterClass *CurRC,
1001  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1002  bool ExploreBundle = false) const;
1003 
1004  /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
1005  /// to the given \p CurRC.
1006  ///
1007  /// Returns the register class that satisfies both \p CurRC and the
1008  /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1009  /// does not exist.
1010  ///
1011  /// \pre CurRC must not be NULL.
1012  /// \pre The operand at \p OpIdx must be a register.
1013  const TargetRegisterClass *
1014  getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1015  const TargetInstrInfo *TII,
1016  const TargetRegisterInfo *TRI) const;
1017 
1018  /// Add a tie between the register operands at DefIdx and UseIdx.
1019  /// The tie will cause the register allocator to ensure that the two
1020  /// operands are assigned the same physical register.
1021  ///
1022  /// Tied operands are managed automatically for explicit operands in the
1023  /// MCInstrDesc. This method is for exceptional cases like inline asm.
1024  void tieOperands(unsigned DefIdx, unsigned UseIdx);
1025 
1026  /// Given the index of a tied register operand, find the
1027  /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1028  /// index of the tied operand which must exist.
1029  unsigned findTiedOperandIdx(unsigned OpIdx) const;
1030 
1031  /// Given the index of a register def operand,
1032  /// check if the register def is tied to a source operand, due to either
1033  /// two-address elimination or inline assembly constraints. Returns the
1034  /// first tied use operand index by reference if UseOpIdx is not null.
1035  bool isRegTiedToUseOperand(unsigned DefOpIdx,
1036  unsigned *UseOpIdx = nullptr) const {
1037  const MachineOperand &MO = getOperand(DefOpIdx);
1038  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1039  return false;
1040  if (UseOpIdx)
1041  *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1042  return true;
1043  }
1044 
1045  /// Return true if the use operand of the specified index is tied to a def
1046  /// operand. It also returns the def operand index by reference if DefOpIdx
1047  /// is not null.
1048  bool isRegTiedToDefOperand(unsigned UseOpIdx,
1049  unsigned *DefOpIdx = nullptr) const {
1050  const MachineOperand &MO = getOperand(UseOpIdx);
1051  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1052  return false;
1053  if (DefOpIdx)
1054  *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1055  return true;
1056  }
1057 
1058  /// Clears kill flags on all operands.
1059  void clearKillInfo();
1060 
1061  /// Replace all occurrences of FromReg with ToReg:SubIdx,
1062  /// properly composing subreg indices where necessary.
1063  void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1064  const TargetRegisterInfo &RegInfo);
1065 
1066  /// We have determined MI kills a register. Look for the
1067  /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1068  /// add a implicit operand if it's not found. Returns true if the operand
1069  /// exists / is added.
1070  bool addRegisterKilled(unsigned IncomingReg,
1071  const TargetRegisterInfo *RegInfo,
1072  bool AddIfNotFound = false);
1073 
1074  /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1075  /// all aliasing registers.
1076  void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1077 
1078  /// We have determined MI defined a register without a use.
1079  /// Look for the operand that defines it and mark it as IsDead. If
1080  /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1081  /// true if the operand exists / is added.
1082  bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1083  bool AddIfNotFound = false);
1084 
1085  /// Clear all dead flags on operands defining register @p Reg.
1086  void clearRegisterDeads(unsigned Reg);
1087 
1088  /// Mark all subregister defs of register @p Reg with the undef flag.
1089  /// This function is used when we determined to have a subregister def in an
1090  /// otherwise undefined super register.
1091  void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1092 
1093  /// We have determined MI defines a register. Make sure there is an operand
1094  /// defining Reg.
1095  void addRegisterDefined(unsigned Reg,
1096  const TargetRegisterInfo *RegInfo = nullptr);
1097 
1098  /// Mark every physreg used by this instruction as
1099  /// dead except those in the UsedRegs list.
1100  ///
1101  /// On instructions with register mask operands, also add implicit-def
1102  /// operands for all registers in UsedRegs.
1104  const TargetRegisterInfo &TRI);
1105 
1106  /// Return true if it is safe to move this instruction. If
1107  /// SawStore is set to true, it means that there is a store (or call) between
1108  /// the instruction's location and its intended destination.
1109  bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1110 
1111  /// Return true if this instruction may have an ordered
1112  /// or volatile memory reference, or if the information describing the memory
1113  /// reference is not available. Return false if it is known to have no
1114  /// ordered or volatile memory references.
1115  bool hasOrderedMemoryRef() const;
1116 
1117  /// Return true if this load instruction never traps and points to a memory
1118  /// location whose value doesn't change during the execution of this function.
1119  ///
1120  /// Examples include loading a value from the constant pool or from the
1121  /// argument area of a function (if it does not change). If the instruction
1122  /// does multiple loads, this returns true only if all of the loads are
1123  /// dereferenceable and invariant.
1125 
1126  /// If the specified instruction is a PHI that always merges together the
1127  /// same virtual register, return the register, otherwise return 0.
1128  unsigned isConstantValuePHI() const;
1129 
1130  /// Return true if this instruction has side effects that are not modeled
1131  /// by mayLoad / mayStore, etc.
1132  /// For all instructions, the property is encoded in MCInstrDesc::Flags
1133  /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1134  /// INLINEASM instruction, in which case the side effect property is encoded
1135  /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1136  ///
1137  bool hasUnmodeledSideEffects() const;
1138 
1139  /// Returns true if it is illegal to fold a load across this instruction.
1140  bool isLoadFoldBarrier() const;
1141 
1142  /// Return true if all the defs of this instruction are dead.
1143  bool allDefsAreDead() const;
1144 
1145  /// Copy implicit register operands from specified
1146  /// instruction to this instruction.
1147  void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1148 
1149  //
1150  // Debugging support
1151  //
1152  void print(raw_ostream &OS, bool SkipOpers = false,
1153  const TargetInstrInfo *TII = nullptr) const;
1154  void print(raw_ostream &OS, ModuleSlotTracker &MST, bool SkipOpers = false,
1155  const TargetInstrInfo *TII = nullptr) const;
1156  void dump(const TargetInstrInfo *TII = nullptr) const;
1157 
1158  //===--------------------------------------------------------------------===//
1159  // Accessors used to build up machine instructions.
1160 
1161  /// Add the specified operand to the instruction. If it is an implicit
1162  /// operand, it is added to the end of the operand list. If it is an
1163  /// explicit operand it is added at the end of the explicit operand list
1164  /// (before the first implicit operand).
1165  ///
1166  /// MF must be the machine function that was used to allocate this
1167  /// instruction.
1168  ///
1169  /// MachineInstrBuilder provides a more convenient interface for creating
1170  /// instructions and adding operands.
1171  void addOperand(MachineFunction &MF, const MachineOperand &Op);
1172 
1173  /// Add an operand without providing an MF reference. This only works for
1174  /// instructions that are inserted in a basic block.
1175  ///
1176  /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1177  /// preferred.
1178  void addOperand(const MachineOperand &Op);
1179 
1180  /// Replace the instruction descriptor (thus opcode) of
1181  /// the current instruction with a new one.
1182  void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1183 
1184  /// Replace current source information with new such.
1185  /// Avoid using this, the constructor argument is preferable.
1187  debugLoc = std::move(dl);
1188  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1189  }
1190 
1191  /// Erase an operand from an instruction, leaving it with one
1192  /// fewer operand than it started with.
1193  void RemoveOperand(unsigned i);
1194 
1195  /// Add a MachineMemOperand to the machine instruction.
1196  /// This function should be used only occasionally. The setMemRefs function
1197  /// is the primary method for setting up a MachineInstr's MemRefs list.
1199 
1200  /// Assign this MachineInstr's memory reference descriptor list.
1201  /// This does not transfer ownership.
1202  void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1203  setMemRefs(std::make_pair(NewMemRefs, NewMemRefsEnd-NewMemRefs));
1204  }
1205 
1206  /// Assign this MachineInstr's memory reference descriptor list. First
1207  /// element in the pair is the begin iterator/pointer to the array; the
1208  /// second is the number of MemoryOperands. This does not transfer ownership
1209  /// of the underlying memory.
1210  void setMemRefs(std::pair<mmo_iterator, unsigned> NewMemRefs) {
1211  MemRefs = NewMemRefs.first;
1212  NumMemRefs = uint8_t(NewMemRefs.second);
1213  assert(NumMemRefs == NewMemRefs.second &&
1214  "Too many memrefs - must drop memory operands");
1215  }
1216 
1217  /// Return a set of memrefs (begin iterator, size) which conservatively
1218  /// describe the memory behavior of both MachineInstrs. This is appropriate
1219  /// for use when merging two MachineInstrs into one. This routine does not
1220  /// modify the memrefs of the this MachineInstr.
1221  std::pair<mmo_iterator, unsigned> mergeMemRefsWith(const MachineInstr& Other);
1222 
1223  /// Clear this MachineInstr's memory reference descriptor list. This resets
1224  /// the memrefs to their most conservative state. This should be used only
1225  /// as a last resort since it greatly pessimizes our knowledge of the memory
1226  /// access performed by the instruction.
1227  void dropMemRefs() {
1228  MemRefs = nullptr;
1229  NumMemRefs = 0;
1230  }
1231 
1232  /// Break any tie involving OpIdx.
1233  void untieRegOperand(unsigned OpIdx) {
1234  MachineOperand &MO = getOperand(OpIdx);
1235  if (MO.isReg() && MO.isTied()) {
1236  getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1237  MO.TiedTo = 0;
1238  }
1239  }
1240 
1241  /// Add all implicit def and use operands to this instruction.
1243 
1244 private:
1245  /// If this instruction is embedded into a MachineFunction, return the
1246  /// MachineRegisterInfo object for the current function, otherwise
1247  /// return null.
1248  MachineRegisterInfo *getRegInfo();
1249 
1250  /// Unlink all of the register operands in this instruction from their
1251  /// respective use lists. This requires that the operands already be on their
1252  /// use lists.
1253  void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1254 
1255  /// Add all of the register operands in this instruction from their
1256  /// respective use lists. This requires that the operands not be on their
1257  /// use lists yet.
1258  void AddRegOperandsToUseLists(MachineRegisterInfo&);
1259 
1260  /// Slow path for hasProperty when we're dealing with a bundle.
1261  bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1262 
1263  /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1264  /// this MI and the given operand index \p OpIdx.
1265  /// If the related operand does not constrained Reg, this returns CurRC.
1266  const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1267  unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1268  const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1269 };
1270 
1271 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1272 /// instruction rather than by pointer value.
1273 /// The hashing and equality testing functions ignore definitions so this is
1274 /// useful for CSE, etc.
1276  static inline MachineInstr *getEmptyKey() {
1277  return nullptr;
1278  }
1279 
1280  static inline MachineInstr *getTombstoneKey() {
1281  return reinterpret_cast<MachineInstr*>(-1);
1282  }
1283 
1284  static unsigned getHashValue(const MachineInstr* const &MI);
1285 
1286  static bool isEqual(const MachineInstr* const &LHS,
1287  const MachineInstr* const &RHS) {
1288  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1289  LHS == getEmptyKey() || LHS == getTombstoneKey())
1290  return LHS == RHS;
1291  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1292  }
1293 };
1294 
1295 //===----------------------------------------------------------------------===//
1296 // Debugging Support
1297 
1299  MI.print(OS);
1300  return OS;
1301 }
1302 
1303 } // End llvm namespace
1304 
1305 #endif
bool isInsideBundle() const
Return true if MI is in a bundle (but not the first MI in a bundle).
Definition: MachineInstr.h:217
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isFullCopy() const
Definition: MachineInstr.h:810
void bundleWithPred()
Bundle this instruction with its predecessor.
void print(raw_ostream &OS, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:241
mop_iterator operands_end()
Definition: MachineInstr.h:296
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires adjustment after instruction selection by calling a target h...
Definition: MachineInstr.h:671
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:448
size_t i
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:334
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:952
iterator_range< mmo_iterator > memoperands() const
Definition: MachineInstr.h:368
iterator_range< const_mop_iterator > operands() const
Definition: MachineInstr.h:304
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:651
iterator_range< mop_iterator > explicit_operands()
Definition: MachineInstr.h:307
void setRegisterDefReadUndef(unsigned Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
iterator_range< const_mop_iterator > defs() const
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:328
bool isPseudo(QueryType Type=IgnoreBundle) const
Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction...
Definition: MachineInstr.h:416
This provides a very simple, boring adaptor for a begin and end iterator into a range type...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:605
bool hasRegisterImplicitUseOperand(unsigned Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:927
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:353
static bool isEqual(const MachineInstr *const &LHS, const MachineInstr *const &RHS)
bool isTied() const
bool isPredicable(QueryType Type=AllInBundle) const
Return true if this instruction has a predicate operand that controls execution.
Definition: MachineInstr.h:478
bool readsVirtualRegister(unsigned Reg) const
Return true if the MachineInstr reads the specified virtual register.
Definition: MachineInstr.h:873
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
Template traits for intrusive list.
Definition: ilist.h:101
void clearAsmPrinterFlag(CommentFlag Flag)
Clear specific AsmPrinter flags.
Definition: MachineInstr.h:151
Recycle small arrays allocated from a BumpPtrAllocator.
Definition: ArrayRecycler.h:29
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:270
bool isCFIInstruction() const
Definition: MachineInstr.h:770
A debug info location.
Definition: DebugLoc.h:34
Manage lifetime of a slot tracker for printing IR.
iterator_range< mmo_iterator > memoperands()
Definition: MachineInstr.h:365
MachineOperand & getOperand(unsigned i)
Definition: MachineInstr.h:283
bool canFoldAsLoad(QueryType Type=IgnoreBundle) const
Return true for instructions that can be folded as memory operands in other instructions.
Definition: MachineInstr.h:538
bool isConditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Definition: MachineInstr.h:462
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:301
bool isExtractSubreg() const
Definition: MachineInstr.h:813
void setPhysRegsDeadExcept(ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isSelect(QueryType Type=IgnoreBundle) const
Return true if this instruction is a select instruction.
Definition: MachineInstr.h:501
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:440
const_mop_iterator operands_end() const
Definition: MachineInstr.h:299
Special DenseMapInfo traits to compare MachineInstr* by value of the instruction rather than by point...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void clearKillInfo()
Clears kill flags on all operands.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
A description of a memory reference used in the backend.
bool getAsmPrinterFlag(CommentFlag Flag) const
Return whether an AsmPrinter flag is set.
Definition: MachineInstr.h:141
iterator_range< const_mop_iterator > implicit_operands() const
Definition: MachineInstr.h:318
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:786
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
std::pair< bool, bool > readsWritesVirtualRegister(unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:592
Reg
All possible values of the reg field in the ModR/M byte.
MachineMemOperand ** mmo_iterator
Definition: MachineInstr.h:56
void bundleWithSucc()
Bundle this instruction with its successor.
ELFYAML::ELF_STO Other
Definition: ELFYAML.cpp:662
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:589
void eraseFromParentAndMarkDBGValuesForRemoval()
Unlink 'this' from the containing basic block and delete it.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:233
void unbundleFromPred()
Break bundle above this instruction.
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:70
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool hasDelaySlot(QueryType Type=AnyInBundle) const
Returns true if the specified instruction has a delay slot which must be filled by the code generator...
Definition: MachineInstr.h:526
uint8_t getAsmPrinterFlags() const
Return the asm printer flags bitvector.
Definition: MachineInstr.h:135
bool isBundled() const
Return true if this instruction part of a bundle.
Definition: MachineInstr.h:223
bool hasExtraSrcRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction source operands have special register allocation requirements that a...
Definition: MachineInstr.h:702
bool isBitcast(QueryType Type=IgnoreBundle) const
Return true if this instruction is a bitcast instruction.
Definition: MachineInstr.h:496
static MachineInstr * getEmptyKey()
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:819
MachineBasicBlock * getParent()
Definition: MachineInstr.h:132
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
int64_t getImm() const
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
iterator_range< const_mop_iterator > uses() const
Returns a range that includes all operands that are register uses.
Definition: MachineInstr.h:339
bool isConvergent(QueryType Type=AnyInBundle) const
Return true if this instruction is convergent.
Definition: MachineInstr.h:515
void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
Definition: MachineInstr.h:777
bool isImplicitDef() const
Definition: MachineInstr.h:788
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:359
bool isInsertSubreg() const
Definition: MachineInstr.h:795
bool isBundle() const
Definition: MachineInstr.h:804
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
static MachineInstr * getTombstoneKey()
#define P(N)
An ilist node that can access its parent list.
Definition: ilist_node.h:243
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:420
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
const MachineOperand * findRegisterUseOperand(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Definition: MachineInstr.h:933
void clearRegisterDeads(unsigned Reg)
Clear all dead flags on operands defining register Reg.
int findRegisterDefOperandIdx(unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found...
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:691
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate...
Definition: MachineInstr.h:780
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand...
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:454
bool isCopy() const
Definition: MachineInstr.h:807
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:166
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:177
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool isGCLabel() const
Definition: MachineInstr.h:766
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool isPosition() const
Definition: MachineInstr.h:775
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:404
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:323
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:161
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:373
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Returns true if the register is dead in this machine instruction.
Definition: MachineInstr.h:910
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:229
bool isLabel() const
Returns true if the MachineInstr represents a label.
Definition: MachineInstr.h:769
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
unsigned getSubReg() const
static unsigned getHashValue(const MachineInstr *const &MI)
bool isNotDuplicable(QueryType Type=AnyInBundle) const
Return true if this instruction cannot be safely duplicated.
Definition: MachineInstr.h:508
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:895
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:594
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
iterator_range< mop_iterator > explicit_uses()
Definition: MachineInstr.h:343
bool isInsertSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions...
Definition: MachineInstr.h:581
bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
const_mop_iterator operands_begin() const
Definition: MachineInstr.h:298
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:865
int findRegisterUseOperandIdx(unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found...
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
bool memoperands_empty() const
Return true if we don't have any memory operands which described the the memory access done by this i...
Definition: MachineInstr.h:363
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isMSInlineAsm() const
Definition: MachineInstr.h:790
void dropMemRefs()
Clear this MachineInstr's memory reference descriptor list.
void setFlags(unsigned flags)
Definition: MachineInstr.h:170
MachineOperand class - Representation of each machine instruction operand.
bool isInlineAsm() const
Definition: MachineInstr.h:789
bool hasExtraDefRegAllocReq(QueryType Type=AnyInBundle) const
Returns true if this instruction def operands have special register allocation requirements that are ...
Definition: MachineInstr.h:712
MachineOperand * mop_iterator
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition: MachineInstr.h:292
bool isIdentityCopy() const
Return true is the instruction is an identity copy.
Definition: MachineInstr.h:824
bool isKill() const
Definition: MachineInstr.h:787
void dump(const TargetInstrInfo *TII=nullptr) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:833
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:485
DWARF expression.
unsigned short Opcode
Definition: MCInstrDesc.h:165
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
A range adaptor for a pair of iterators.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void setDebugLoc(DebugLoc dl)
Replace current source information with new such.
bool isSubregToReg() const
Definition: MachineInstr.h:798
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:315
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate...
bool isExtractSubregLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions...
Definition: MachineInstr.h:567
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:380
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:391
Representation of each machine instruction.
Definition: MachineInstr.h:52
uint64_t getFlags() const
Return flags of this instruction.
Definition: MCInstrDesc.h:219
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:615
std::pair< mmo_iterator, unsigned > mergeMemRefsWith(const MachineInstr &Other)
Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of b...
#define I(x, y, z)
Definition: MD5.cpp:54
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:424
bool usesCustomInsertionHook(QueryType Type=IgnoreBundle) const
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...
Definition: MachineInstr.h:663
uint8_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:156
bool isEHLabel() const
Definition: MachineInstr.h:765
const TargetRegisterClass * getRegClassConstraintEffectForVReg(unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1726
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it. ...
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
iterator_range< const_mop_iterator > explicit_operands() const
Definition: MachineInstr.h:311
unsigned getReg() const
getReg - Returns the register number.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
Definition: MachineInstr.h:633
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:886
void clearAsmPrinterFlags()
Clear the AsmPrinter bitvector.
Definition: MachineInstr.h:138
void unbundleFromSucc()
Break bundle below this instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register...
bool isRematerializable(QueryType Type=AllInBundle) const
Returns true if this instruction is a candidate for remat.
Definition: MachineInstr.h:679
mop_iterator operands_begin()
Definition: MachineInstr.h:295
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:81
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
Callbacks do nothing by default in iplist and ilist.
Definition: ilist.h:65
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
iterator_range< const_mop_iterator > explicit_uses() const
Definition: MachineInstr.h:347
void setMemRefs(std::pair< mmo_iterator, unsigned > NewMemRefs)
Assign this MachineInstr's memory reference descriptor list.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
Definition: MachineInstr.h:146
CommentFlag
Flags to specify different kinds of comments to output in assembly code.
Definition: MachineInstr.h:62
bool hasOptionalDef(QueryType Type=IgnoreBundle) const
Set if this instruction has an optional definition, e.g.
Definition: MachineInstr.h:410
bool isStackAligningInlineAsm() const
bool isRegSequence() const
Definition: MachineInstr.h:801
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction...
Definition: MachineInstr.h:491
bool isRegSequenceLike(QueryType Type=IgnoreBundle) const
Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
Definition: MachineInstr.h:552
InlineAsm::AsmDialect getInlineAsmDialect() const
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Assign this MachineInstr's memory reference descriptor list.
const MachineOperand * const_mop_iterator
Definition: MachineInstr.h:293
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
Definition: MachineInstr.h:903
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
Definition: MachineInstr.h:431
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:470
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:358
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.