26 #ifndef LLVM_CODEGEN_DFAPACKETIZER_H
27 #define LLVM_CODEGEN_DFAPACKETIZER_H
38 class MachineLoopInfo;
39 class MachineDominatorTree;
40 class InstrItineraryData;
41 class DefaultVLIWScheduler;
64 #define DFA_MAX_RESTERMS 4 // The max # of AND'ed resource terms.
65 #define DFA_MAX_RESOURCES 16 // The max # of resource bits in one term.
69 #define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable.
74 typedef std::pair<unsigned, DFAInput> UnsignPair;
79 const unsigned *DFAStateEntryTable;
85 void ReadTable(
unsigned state);
bool canReserveResources(const llvm::MCInstrDesc *MID)
std::vector< MachineInstr * > CurrentPacketMIs
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
virtual void initPacketizerState()
DFAInput getInsnInput(unsigned InsnClass)
Describe properties that are true of each instruction in the target description file.
virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ)
virtual bool ignorePseudoInstruction(const MachineInstr &I, const MachineBasicBlock *MBB)
std::map< MachineInstr *, SUnit * > MIToSUnit
virtual void endPacket(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI)
const InstrItineraryData * getInstrItins() const
DFAPacketizer * ResourceTracker
virtual MachineBasicBlock::iterator addToPacket(MachineInstr &MI)
Itinerary data supplied by a subtarget to be used by a target.
void reserveResources(const llvm::MCInstrDesc *MID)
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool shouldAddToPacket(const MachineInstr &MI)
virtual bool isSoloInstruction(const MachineInstr &MI)
const TargetInstrInfo * TII
virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ)
Representation of each machine instruction.
DFAPacketizer * getResourceTracker()
virtual ~VLIWPacketizerList()
VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA)
DFAPacketizer(const InstrItineraryData *I, const DFAStateInput(*SIT)[2], const unsigned *SET)
void PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr)
DefaultVLIWScheduler * VLIWScheduler
SUnit - Scheduling unit. This is a node in the scheduling DAG.