LLVM  4.0.0
Legalizer.cpp
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1 //===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize individual
11 /// instructions and the LegalizePass wrapper pass for the primary
12 /// legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
21 #include "llvm/Support/Debug.h"
24 
25 #define DEBUG_TYPE "legalizer"
26 
27 using namespace llvm;
28 
29 char Legalizer::ID = 0;
31  "Legalize the Machine IR a function's Machine IR", false,
32  false)
35  "Legalize the Machine IR a function's Machine IR", false,
36  false)
37 
38 Legalizer::Legalizer() : MachineFunctionPass(ID) {
40 }
41 
45 }
46 
47 void Legalizer::init(MachineFunction &MF) {
48 }
49 
51  const TargetInstrInfo &TII) {
52  bool Changed = false;
53  if (MI.getOpcode() != TargetOpcode::G_EXTRACT)
54  return Changed;
55 
56  unsigned NumDefs = (MI.getNumOperands() - 1) / 2;
57  unsigned SrcReg = MI.getOperand(NumDefs).getReg();
58  MachineInstr &SeqI = *MRI.def_instr_begin(SrcReg);
59  if (SeqI.getOpcode() != TargetOpcode::G_SEQUENCE)
60  return Changed;
61 
62  unsigned NumSeqSrcs = (SeqI.getNumOperands() - 1) / 2;
63  bool AllDefsReplaced = true;
64 
65  // Try to match each register extracted with a corresponding insertion formed
66  // by the G_SEQUENCE.
67  for (unsigned Idx = 0, SeqIdx = 0; Idx < NumDefs; ++Idx) {
68  MachineOperand &ExtractMO = MI.getOperand(Idx);
69  assert(ExtractMO.isReg() && ExtractMO.isDef() &&
70  "unexpected extract operand");
71 
72  unsigned ExtractReg = ExtractMO.getReg();
73  unsigned ExtractPos = MI.getOperand(NumDefs + Idx + 1).getImm();
74 
75  while (SeqIdx < NumSeqSrcs &&
76  SeqI.getOperand(2 * SeqIdx + 2).getImm() < ExtractPos)
77  ++SeqIdx;
78 
79  if (SeqIdx == NumSeqSrcs) {
80  AllDefsReplaced = false;
81  continue;
82  }
83 
84  unsigned OrigReg = SeqI.getOperand(2 * SeqIdx + 1).getReg();
85  if (SeqI.getOperand(2 * SeqIdx + 2).getImm() != ExtractPos ||
86  MRI.getType(OrigReg) != MRI.getType(ExtractReg)) {
87  AllDefsReplaced = false;
88  continue;
89  }
90 
92  "unexpected physical register in G_SEQUENCE");
93 
94  // Finally we can replace the uses.
95  for (auto &Use : MRI.use_operands(ExtractReg)) {
96  Changed = true;
97  Use.setReg(OrigReg);
98  }
99  }
100 
101  if (AllDefsReplaced) {
102  // If SeqI was the next instruction in the BB and we removed it, we'd break
103  // the outer iteration.
104  assert(std::next(MachineBasicBlock::iterator(MI)) != SeqI &&
105  "G_SEQUENCE does not dominate G_EXTRACT");
106 
107  MI.eraseFromParent();
108 
109  if (MRI.use_empty(SrcReg))
110  SeqI.eraseFromParent();
111  Changed = true;
112  }
113 
114  return Changed;
115 }
116 
118  // If the ISel pipeline failed, do not bother running that pass.
119  if (MF.getProperties().hasProperty(
121  return false;
122  DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
123  init(MF);
124  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
126  LegalizerHelper Helper(MF);
127 
128  // FIXME: an instruction may need more than one pass before it is legal. For
129  // example on most architectures <3 x i3> is doubly-illegal. It would
130  // typically proceed along a path like: <3 x i3> -> <3 x i8> -> <8 x i8>. We
131  // probably want a worklist of instructions rather than naive iterate until
132  // convergence for performance reasons.
133  bool Changed = false;
135  for (auto &MBB : MF)
136  for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
137  // Get the next Instruction before we try to legalize, because there's a
138  // good chance MI will be deleted.
139  NextMI = std::next(MI);
140 
141  // Only legalize pre-isel generic instructions: others don't have types
142  // and are assumed to be legal.
143  if (!isPreISelGenericOpcode(MI->getOpcode()))
144  continue;
145 
146  auto Res = Helper.legalizeInstr(*MI, LegalizerInfo);
147 
148  // Error out if we couldn't legalize this instruction. We may want to fall
149  // back to DAG ISel instead in the future.
151  if (!TPC.isGlobalISelAbortEnabled()) {
152  MF.getProperties().set(
154  return false;
155  }
156  std::string Msg;
157  raw_string_ostream OS(Msg);
158  OS << "unable to legalize instruction: ";
159  MI->print(OS);
160  report_fatal_error(OS.str());
161  }
162 
163  Changed |= Res == LegalizerHelper::Legalized;
164  }
165 
166 
167  MachineRegisterInfo &MRI = MF.getRegInfo();
168  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
169  for (auto &MBB : MF) {
170  for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
171  // Get the next Instruction before we try to legalize, because there's a
172  // good chance MI will be deleted.
173  NextMI = std::next(MI);
174 
175  Changed |= combineExtracts(*MI, MRI, TII);
176  }
177  }
178 
179  return Changed;
180 }
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
LegalizeResult legalizeInstr(MachineInstr &MI, const LegalizerInfo &LegalizerInfo)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasProperty(Property P) const
iterator_range< use_iterator > use_operands(unsigned Reg) const
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:53
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
A Use represents the edge between a Value definition and its users.
Definition: Use.h:56
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Legalize the Machine IR a function s Machine false
Definition: Legalizer.cpp:34
const MachineFunctionProperties & getProperties() const
Get the function properties.
virtual bool isGlobalISelAbortEnabled() const
Check whether or not GlobalISel should abort on error.
Target-Independent Code Generator Pass Configuration Options.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE,"Legalize the Machine IR a function's Machine IR", false, false) INITIALIZE_PASS_END(Legalizer
MachineBasicBlock * MBB
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:303
int64_t getImm() const
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
TargetInstrInfo - Interface to description of machine instruction set.
TracePC TPC
unsigned const MachineRegisterInfo * MRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
Represent the analysis usage information of a pass.
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE,"Assign register bank of generic virtual registers", false, false) RegBankSelect
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: Legalizer.cpp:117
Some kind of error has occurred and we could not legalize this instruction.
bool combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII)
Definition: Legalizer.cpp:50
Legalize the Machine IR a function s Machine IR
Definition: Legalizer.cpp:34
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:479
MachineOperand class - Representation of each machine instruction operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
static char ID
Definition: Legalizer.h:33
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Instruction has been legalized and the MachineFunction changed.
#define DEBUG_TYPE
Definition: Legalizer.cpp:25
def_instr_iterator def_instr_begin(unsigned RegNo) const
void initializeLegalizerPass(PassRegistry &)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: Legalizer.cpp:42
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:463
virtual const LegalizerInfo * getLegalizerInfo() const
#define DEBUG(X)
Definition: Debug.h:100
print Print MemDeps of function
IRTranslator LLVM IR MI
virtual void print(raw_ostream &O, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:117
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool use_empty(unsigned RegNo) const
use_empty - Return true if there are no instructions using the specified register.