21 #define DEBUG_TYPE "arm-isel"
25 #ifndef LLVM_BUILD_GLOBAL_ISEL
26 #error "You shouldn't build this"
32 TRI(*STI.getRegisterInfo()), RBI(RBI) {}
43 assert(RegBank &&
"Can't get reg bank for virtual register");
48 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
50 assert((DstSize == SrcSize ||
54 DstSize <= SrcSize)) &&
55 "Copy with different width?!");
77 auto &
MRI = MF.getRegInfo();
88 using namespace TargetOpcode;
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Holds all the information related to register banks.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const HexagonInstrInfo * TII
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
This class provides the information for the target register banks.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
This file declares the targeting of the RegisterBankInfo class for ARM.
ARMInstructionSelector(const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
const MachineOperand & getOperand(unsigned i) const
unsigned getID() const
Get the identifier of this register bank.
virtual bool select(MachineInstr &I) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
This file declares the targeting of the InstructionSelector class for ARM.
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.