LLVM  4.0.0
A15SDOptimizer.cpp
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1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The Cortex-A15 processor employs a tracking scheme in its register renaming
11 // in order to process each instruction's micro-ops speculatively and
12 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
13 // instructions to read and write 32-bit S-registers. Each S-register
14 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
15 //
16 // There are several instruction patterns which can be used to provide this
17 // capability which can provide higher performance than other, potentially more
18 // direct patterns, specifically around when one micro-op reads a D-register
19 // operand that has recently been written as one or more S-register results.
20 //
21 // This file defines a pre-regalloc pass which looks for SPR producers which
22 // are going to be used by a DPR (or QPR) consumers and creates the more
23 // optimized access pattern.
24 //
25 //===----------------------------------------------------------------------===//
26 
27 #include "ARM.h"
28 #include "ARMBaseInstrInfo.h"
29 #include "ARMBaseRegisterInfo.h"
30 #include "ARMSubtarget.h"
31 #include "llvm/ADT/Statistic.h"
37 #include "llvm/Support/Debug.h"
41 #include <map>
42 #include <set>
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "a15-sd-optimizer"
47 
48 namespace {
49  struct A15SDOptimizer : public MachineFunctionPass {
50  static char ID;
51  A15SDOptimizer() : MachineFunctionPass(ID) {}
52 
53  bool runOnMachineFunction(MachineFunction &Fn) override;
54 
55  StringRef getPassName() const override { return "ARM A15 S->D optimizer"; }
56 
57  private:
58  const ARMBaseInstrInfo *TII;
59  const TargetRegisterInfo *TRI;
61 
62  bool runOnInstruction(MachineInstr *MI);
63 
64  //
65  // Instruction builder helpers
66  //
67  unsigned createDupLane(MachineBasicBlock &MBB,
68  MachineBasicBlock::iterator InsertBefore,
69  const DebugLoc &DL, unsigned Reg, unsigned Lane,
70  bool QPR = false);
71 
72  unsigned createExtractSubreg(MachineBasicBlock &MBB,
73  MachineBasicBlock::iterator InsertBefore,
74  const DebugLoc &DL, unsigned DReg,
75  unsigned Lane, const TargetRegisterClass *TRC);
76 
77  unsigned createVExt(MachineBasicBlock &MBB,
78  MachineBasicBlock::iterator InsertBefore,
79  const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
80 
81  unsigned createRegSequence(MachineBasicBlock &MBB,
82  MachineBasicBlock::iterator InsertBefore,
83  const DebugLoc &DL, unsigned Reg1,
84  unsigned Reg2);
85 
86  unsigned createInsertSubreg(MachineBasicBlock &MBB,
87  MachineBasicBlock::iterator InsertBefore,
88  const DebugLoc &DL, unsigned DReg,
89  unsigned Lane, unsigned ToInsert);
90 
91  unsigned createImplicitDef(MachineBasicBlock &MBB,
92  MachineBasicBlock::iterator InsertBefore,
93  const DebugLoc &DL);
94 
95  //
96  // Various property checkers
97  //
98  bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
99  bool hasPartialWrite(MachineInstr *MI);
100  SmallVector<unsigned, 8> getReadDPRs(MachineInstr *MI);
101  unsigned getDPRLaneFromSPR(unsigned SReg);
102 
103  //
104  // Methods used for getting the definitions of partial registers
105  //
106 
107  MachineInstr *elideCopies(MachineInstr *MI);
108  void elideCopiesAndPHIs(MachineInstr *MI,
110 
111  //
112  // Pattern optimization methods
113  //
114  unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
115  unsigned optimizeSDPattern(MachineInstr *MI);
116  unsigned getPrefSPRLane(unsigned SReg);
117 
118  //
119  // Sanitizing method - used to make sure if don't leave dead code around.
120  //
121  void eraseInstrWithNoUses(MachineInstr *MI);
122 
123  //
124  // A map used to track the changes done by this pass.
125  //
126  std::map<MachineInstr*, unsigned> Replacements;
127  std::set<MachineInstr *> DeadInstr;
128  };
129  char A15SDOptimizer::ID = 0;
130 } // end anonymous namespace
131 
132 // Returns true if this is a use of a SPR register.
133 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
134  const TargetRegisterClass *TRC) {
135  if (!MO.isReg())
136  return false;
137  unsigned Reg = MO.getReg();
138 
140  return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
141  else
142  return TRC->contains(Reg);
143 }
144 
145 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
146  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
147  &ARM::DPRRegClass);
148  if (DReg != ARM::NoRegister) return ARM::ssub_1;
149  return ARM::ssub_0;
150 }
151 
152 // Get the subreg type that is most likely to be coalesced
153 // for an SPR register that will be used in VDUP32d pseudo.
154 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
155  if (!TRI->isVirtualRegister(SReg))
156  return getDPRLaneFromSPR(SReg);
157 
158  MachineInstr *MI = MRI->getVRegDef(SReg);
159  if (!MI) return ARM::ssub_0;
160  MachineOperand *MO = MI->findRegisterDefOperand(SReg);
161 
162  assert(MO->isReg() && "Non-register operand found!");
163  if (!MO) return ARM::ssub_0;
164 
165  if (MI->isCopy() && usesRegClass(MI->getOperand(1),
166  &ARM::SPRRegClass)) {
167  SReg = MI->getOperand(1).getReg();
168  }
169 
171  if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
172  return ARM::ssub_0;
173  }
174  return getDPRLaneFromSPR(SReg);
175 }
176 
177 // MI is known to be dead. Figure out what instructions
178 // are also made dead by this and mark them for removal.
179 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
181  DeadInstr.insert(MI);
182 
183  DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
184  Front.push_back(MI);
185 
186  while (Front.size() != 0) {
187  MI = Front.back();
188  Front.pop_back();
189 
190  // MI is already known to be dead. We need to see
191  // if other instructions can also be removed.
192  for (unsigned int i = 0; i < MI->getNumOperands(); ++i) {
193  MachineOperand &MO = MI->getOperand(i);
194  if ((!MO.isReg()) || (!MO.isUse()))
195  continue;
196  unsigned Reg = MO.getReg();
197  if (!TRI->isVirtualRegister(Reg))
198  continue;
200 
201  if (!Op)
202  continue;
203 
204  MachineInstr *Def = Op->getParent();
205 
206  // We don't need to do anything if we have already marked
207  // this instruction as being dead.
208  if (DeadInstr.find(Def) != DeadInstr.end())
209  continue;
210 
211  // Check if all the uses of this instruction are marked as
212  // dead. If so, we can also mark this instruction as being
213  // dead.
214  bool IsDead = true;
215  for (unsigned int j = 0; j < Def->getNumOperands(); ++j) {
216  MachineOperand &MODef = Def->getOperand(j);
217  if ((!MODef.isReg()) || (!MODef.isDef()))
218  continue;
219  unsigned DefReg = MODef.getReg();
220  if (!TRI->isVirtualRegister(DefReg)) {
221  IsDead = false;
222  break;
223  }
225  II = MRI->use_instr_begin(Reg), EE = MRI->use_instr_end();
226  II != EE; ++II) {
227  // We don't care about self references.
228  if (&*II == Def)
229  continue;
230  if (DeadInstr.find(&*II) == DeadInstr.end()) {
231  IsDead = false;
232  break;
233  }
234  }
235  }
236 
237  if (!IsDead) continue;
238 
239  DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
240  DeadInstr.insert(Def);
241  }
242  }
243 }
244 
245 // Creates the more optimized patterns and generally does all the code
246 // transformations in this pass.
247 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
248  if (MI->isCopy()) {
249  return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
250  }
251 
252  if (MI->isInsertSubreg()) {
253  unsigned DPRReg = MI->getOperand(1).getReg();
254  unsigned SPRReg = MI->getOperand(2).getReg();
255 
256  if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
257  MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
258  MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
259 
260  if (DPRMI && SPRMI) {
261  // See if the first operand of this insert_subreg is IMPLICIT_DEF
262  MachineInstr *ECDef = elideCopies(DPRMI);
263  if (ECDef && ECDef->isImplicitDef()) {
264  // Another corner case - if we're inserting something that is purely
265  // a subreg copy of a DPR, just use that DPR.
266 
267  MachineInstr *EC = elideCopies(SPRMI);
268  // Is it a subreg copy of ssub_0?
269  if (EC && EC->isCopy() &&
270  EC->getOperand(1).getSubReg() == ARM::ssub_0) {
271  DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
272 
273  // Find the thing we're subreg copying out of - is it of the same
274  // regclass as DPRMI? (i.e. a DPR or QPR).
275  unsigned FullReg = SPRMI->getOperand(1).getReg();
276  const TargetRegisterClass *TRC =
277  MRI->getRegClass(MI->getOperand(1).getReg());
278  if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
279  DEBUG(dbgs() << "Subreg copy is compatible - returning ");
280  DEBUG(dbgs() << PrintReg(FullReg) << "\n");
281  eraseInstrWithNoUses(MI);
282  return FullReg;
283  }
284  }
285 
286  return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
287  }
288  }
289  }
290  return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
291  }
292 
293  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
294  &ARM::SPRRegClass)) {
295  // See if all bar one of the operands are IMPLICIT_DEF and insert the
296  // optimizer pattern accordingly.
297  unsigned NumImplicit = 0, NumTotal = 0;
298  unsigned NonImplicitReg = ~0U;
299 
300  for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
301  if (!MI->getOperand(I).isReg())
302  continue;
303  ++NumTotal;
304  unsigned OpReg = MI->getOperand(I).getReg();
305 
306  if (!TRI->isVirtualRegister(OpReg))
307  break;
308 
309  MachineInstr *Def = MRI->getVRegDef(OpReg);
310  if (!Def)
311  break;
312  if (Def->isImplicitDef())
313  ++NumImplicit;
314  else
315  NonImplicitReg = MI->getOperand(I).getReg();
316  }
317 
318  if (NumImplicit == NumTotal - 1)
319  return optimizeAllLanesPattern(MI, NonImplicitReg);
320  else
321  return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
322  }
323 
324  llvm_unreachable("Unhandled update pattern!");
325 }
326 
327 // Return true if this MachineInstr inserts a scalar (SPR) value into
328 // a D or Q register.
329 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
330  // The only way we can do a partial register update is through a COPY,
331  // INSERT_SUBREG or REG_SEQUENCE.
332  if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
333  return true;
334 
335  if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
336  &ARM::SPRRegClass))
337  return true;
338 
339  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
340  return true;
341 
342  return false;
343 }
344 
345 // Looks through full copies to get the instruction that defines the input
346 // operand for MI.
347 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
348  if (!MI->isFullCopy())
349  return MI;
350  if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
351  return nullptr;
352  MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
353  if (!Def)
354  return nullptr;
355  return elideCopies(Def);
356 }
357 
358 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
359 // that can produce MI.
360 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
362  // Looking through PHIs may create loops so we need to track what
363  // instructions we have visited before.
364  std::set<MachineInstr *> Reached;
366  Front.push_back(MI);
367  while (Front.size() != 0) {
368  MI = Front.back();
369  Front.pop_back();
370 
371  // If we have already explored this MachineInstr, ignore it.
372  if (Reached.find(MI) != Reached.end())
373  continue;
374  Reached.insert(MI);
375  if (MI->isPHI()) {
376  for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
377  unsigned Reg = MI->getOperand(I).getReg();
378  if (!TRI->isVirtualRegister(Reg)) {
379  continue;
380  }
381  MachineInstr *NewMI = MRI->getVRegDef(Reg);
382  if (!NewMI)
383  continue;
384  Front.push_back(NewMI);
385  }
386  } else if (MI->isFullCopy()) {
387  if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
388  continue;
389  MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
390  if (!NewMI)
391  continue;
392  Front.push_back(NewMI);
393  } else {
394  DEBUG(dbgs() << "Found partial copy" << *MI <<"\n");
395  Outs.push_back(MI);
396  }
397  }
398 }
399 
400 // Return the DPR virtual registers that are read by this machine instruction
401 // (if any).
402 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
403  if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
404  MI->isKill())
405  return SmallVector<unsigned, 8>();
406 
408  for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
409  MachineOperand &MO = MI->getOperand(i);
410 
411  if (!MO.isReg() || !MO.isUse())
412  continue;
413  if (!usesRegClass(MO, &ARM::DPRRegClass) &&
414  !usesRegClass(MO, &ARM::QPRRegClass) &&
415  !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
416  continue;
417 
418  Defs.push_back(MO.getReg());
419  }
420  return Defs;
421 }
422 
423 // Creates a DPR register from an SPR one by using a VDUP.
424 unsigned A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
425  MachineBasicBlock::iterator InsertBefore,
426  const DebugLoc &DL, unsigned Reg,
427  unsigned Lane, bool QPR) {
428  unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass :
429  &ARM::DPRRegClass);
431  InsertBefore,
432  DL,
433  TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d),
434  Out)
435  .addReg(Reg)
436  .addImm(Lane));
437 
438  return Out;
439 }
440 
441 // Creates a SPR register from a DPR by copying the value in lane 0.
442 unsigned A15SDOptimizer::createExtractSubreg(
444  const DebugLoc &DL, unsigned DReg, unsigned Lane,
445  const TargetRegisterClass *TRC) {
446  unsigned Out = MRI->createVirtualRegister(TRC);
447  BuildMI(MBB,
448  InsertBefore,
449  DL,
450  TII->get(TargetOpcode::COPY), Out)
451  .addReg(DReg, 0, Lane);
452 
453  return Out;
454 }
455 
456 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
457 unsigned A15SDOptimizer::createRegSequence(
459  const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
460  unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
461  BuildMI(MBB,
462  InsertBefore,
463  DL,
464  TII->get(TargetOpcode::REG_SEQUENCE), Out)
465  .addReg(Reg1)
466  .addImm(ARM::dsub_0)
467  .addReg(Reg2)
468  .addImm(ARM::dsub_1);
469  return Out;
470 }
471 
472 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
473 // and merges them into one DPR register.
474 unsigned A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
475  MachineBasicBlock::iterator InsertBefore,
476  const DebugLoc &DL, unsigned Ssub0,
477  unsigned Ssub1) {
478  unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
480  InsertBefore,
481  DL,
482  TII->get(ARM::VEXTd32), Out)
483  .addReg(Ssub0)
484  .addReg(Ssub1)
485  .addImm(1));
486  return Out;
487 }
488 
489 unsigned A15SDOptimizer::createInsertSubreg(
491  const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
492  unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
493  BuildMI(MBB,
494  InsertBefore,
495  DL,
496  TII->get(TargetOpcode::INSERT_SUBREG), Out)
497  .addReg(DReg)
498  .addReg(ToInsert)
499  .addImm(Lane);
500 
501  return Out;
502 }
503 
504 unsigned
505 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
506  MachineBasicBlock::iterator InsertBefore,
507  const DebugLoc &DL) {
508  unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
509  BuildMI(MBB,
510  InsertBefore,
511  DL,
512  TII->get(TargetOpcode::IMPLICIT_DEF), Out);
513  return Out;
514 }
515 
516 // This function inserts instructions in order to optimize interactions between
517 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
518 // lanes, and the using VEXT instructions to recompose the result.
519 unsigned
520 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
521  MachineBasicBlock::iterator InsertPt(MI);
522  DebugLoc DL = MI->getDebugLoc();
523  MachineBasicBlock &MBB = *MI->getParent();
524  InsertPt++;
525  unsigned Out;
526 
527  // DPair has the same length as QPR and also has two DPRs as subreg.
528  // Treat DPair as QPR.
529  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
530  MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
531  unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
532  ARM::dsub_0, &ARM::DPRRegClass);
533  unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
534  ARM::dsub_1, &ARM::DPRRegClass);
535 
536  unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
537  unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
538  Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
539 
540  unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
541  unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
542  Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
543 
544  Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
545 
546  } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
547  unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
548  unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
549  Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
550 
551  } else {
552  assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
553  "Found unexpected regclass!");
554 
555  unsigned PrefLane = getPrefSPRLane(Reg);
556  unsigned Lane;
557  switch (PrefLane) {
558  case ARM::ssub_0: Lane = 0; break;
559  case ARM::ssub_1: Lane = 1; break;
560  default: llvm_unreachable("Unknown preferred lane!");
561  }
562 
563  // Treat DPair as QPR
564  bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
565  usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
566 
567  Out = createImplicitDef(MBB, InsertPt, DL);
568  Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
569  Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
570  eraseInstrWithNoUses(MI);
571  }
572  return Out;
573 }
574 
575 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
576  // We look for instructions that write S registers that are then read as
577  // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
578  // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
579  // merge two SPR values to form a DPR register. In order avoid false
580  // positives we make sure that there is an SPR producer so we look past
581  // COPY and PHI nodes to find it.
582  //
583  // The best code pattern for when an SPR producer is going to be used by a
584  // DPR or QPR consumer depends on whether the other lanes of the
585  // corresponding DPR/QPR are currently defined.
586  //
587  // We can handle these efficiently, depending on the type of
588  // pseudo-instruction that is producing the pattern
589  //
590  // * COPY: * VDUP all lanes and merge the results together
591  // using VEXTs.
592  //
593  // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
594  // lane, and the other lane(s) of the DPR/QPR register
595  // that we are inserting in are undefined, use the
596  // original DPR/QPR value.
597  // * Otherwise, fall back on the same stategy as COPY.
598  //
599  // * REG_SEQUENCE: * If all except one of the input operands are
600  // IMPLICIT_DEFs, insert the VDUP pattern for just the
601  // defined input operand
602  // * Otherwise, fall back on the same stategy as COPY.
603  //
604 
605  // First, get all the reads of D-registers done by this instruction.
606  SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
607  bool Modified = false;
608 
609  for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
610  I != E; ++I) {
611  // Follow the def-use chain for this DPR through COPYs, and also through
612  // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
613  // we can end up with multiple defs of this DPR.
614 
616  if (!TRI->isVirtualRegister(*I))
617  continue;
618  MachineInstr *Def = MRI->getVRegDef(*I);
619  if (!Def)
620  continue;
621 
622  elideCopiesAndPHIs(Def, DefSrcs);
623 
625  EE = DefSrcs.end(); II != EE; ++II) {
626  MachineInstr *MI = *II;
627 
628  // If we've already analyzed and replaced this operand, don't do
629  // anything.
630  if (Replacements.find(MI) != Replacements.end())
631  continue;
632 
633  // Now, work out if the instruction causes a SPR->DPR dependency.
634  if (!hasPartialWrite(MI))
635  continue;
636 
637  // Collect all the uses of this MI's DPR def for updating later.
639  unsigned DPRDefReg = MI->getOperand(0).getReg();
640  for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
641  E = MRI->use_end(); I != E; ++I)
642  Uses.push_back(&*I);
643 
644  // We can optimize this.
645  unsigned NewReg = optimizeSDPattern(MI);
646 
647  if (NewReg != 0) {
648  Modified = true;
650  E = Uses.end(); I != E; ++I) {
651  // Make sure to constrain the register class of the new register to
652  // match what we're replacing. Otherwise we can optimize a DPR_VFP2
653  // reference into a plain DPR, and that will end poorly. NewReg is
654  // always virtual here, so there will always be a matching subclass
655  // to find.
656  MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
657 
658  DEBUG(dbgs() << "Replacing operand "
659  << **I << " with "
660  << PrintReg(NewReg) << "\n");
661  (*I)->substVirtReg(NewReg, 0, *TRI);
662  }
663  }
664  Replacements[MI] = NewReg;
665  }
666  }
667  return Modified;
668 }
669 
670 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
671  if (skipFunction(*Fn.getFunction()))
672  return false;
673 
674  const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
675  // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
676  // enabled when NEON is available.
677  if (!(STI.isCortexA15() && STI.hasNEON()))
678  return false;
679  TII = STI.getInstrInfo();
680  TRI = STI.getRegisterInfo();
681  MRI = &Fn.getRegInfo();
682  bool Modified = false;
683 
684  DEBUG(dbgs() << "Running on function " << Fn.getName()<< "\n");
685 
686  DeadInstr.clear();
687  Replacements.clear();
688 
689  for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
690  ++MFI) {
691 
692  for (MachineBasicBlock::iterator MI = MFI->begin(), ME = MFI->end();
693  MI != ME;) {
694  Modified |= runOnInstruction(&*MI++);
695  }
696 
697  }
698 
699  for (std::set<MachineInstr *>::iterator I = DeadInstr.begin(),
700  E = DeadInstr.end();
701  I != E; ++I) {
702  (*I)->eraseFromParent();
703  }
704 
705  return Modified;
706 }
707 
709  return new A15SDOptimizer();
710 }
bool isFullCopy() const
Definition: MachineInstr.h:810
FunctionPass * createA15SDOptimizerPass()
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
size_t i
MachineOperand * findRegisterDefOperand(unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
Definition: MachineInstr.h:952
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
A debug info location.
Definition: DebugLoc.h:34
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:376
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
bool isPHI() const
Definition: MachineInstr.h:786
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Reg
All possible values of the reg field in the ModR/M byte.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineBasicBlock * MBB
bool isCopyLike() const
Return true if the instruction behaves like a copy.
Definition: MachineInstr.h:819
bool hasNEON() const
Definition: ARMSubtarget.h:449
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool isImplicitDef() const
Definition: MachineInstr.h:788
bool isInsertSubreg() const
Definition: MachineInstr.h:795
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned const MachineRegisterInfo * MRI
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
Definition: SmallVector.h:115
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
bool isCopy() const
Definition: MachineInstr.h:807
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isCortexA15() const
Definition: ARMSubtarget.h:435
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
unsigned getSubReg() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
bool isKill() const
Definition: MachineInstr.h:787
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:250
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:464
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:52
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
Definition: SmallVector.h:119
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
#define I(x, y, z)
Definition: MD5.cpp:54
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:135
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:385
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:100
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool isRegSequence() const
Definition: MachineInstr.h:801
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.