67 bool CheckOk = Check ? Check->
check() :
true;
100 if (exOp.
getExpr()->evaluateAsAbsolute(Value)) {
117 assert((iClass <= 0xf) &&
"iClass must have range of 0 to 0xf");
119 duplexInst->
setOpcode(Hexagon::DuplexIClass0 + iClass);
195 using namespace Hexagon;
244 const auto &HExpr = cast<HexagonMCExpr>(Expr);
246 return *HExpr.getExpr();
289 return ~(-1U << (bits - 1));
291 return ~(-1U <<
bits);
304 return -1U << (bits - 1);
361 return Hexagon::ArchV4;
363 return Hexagon::ArchV5;
389 auto MI =
I.getInst();
422 auto Result = Hexagon::BUNDLE == MCI.
getOpcode();
445 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
446 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
468 if (isa<HexagonMCExpr>(MO.
getExpr()) &&
484 if (isa<HexagonMCExpr>(MO.
getExpr()) &&
488 if (!MO.
getExpr()->evaluateAsAbsolute(Value))
492 return (MinValue > Value || Value > MaxValue);
514 return (
Op == Hexagon::A4_ext_b ||
Op == Hexagon::A4_ext_c ||
515 Op == Hexagon::A4_ext_g ||
Op == Hexagon::A4_ext);
525 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
529 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
530 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
543 unsigned short OperandNum) {
582 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
610 case Hexagon::SA1_addi:
611 case Hexagon::SA1_addrx:
612 case Hexagon::SA1_addsp:
613 case Hexagon::SA1_and1:
614 case Hexagon::SA1_clrf:
615 case Hexagon::SA1_clrfnew:
616 case Hexagon::SA1_clrt:
617 case Hexagon::SA1_clrtnew:
618 case Hexagon::SA1_cmpeqi:
619 case Hexagon::SA1_combine0i:
620 case Hexagon::SA1_combine1i:
621 case Hexagon::SA1_combine2i:
622 case Hexagon::SA1_combine3i:
623 case Hexagon::SA1_combinerz:
624 case Hexagon::SA1_combinezr:
625 case Hexagon::SA1_dec:
626 case Hexagon::SA1_inc:
627 case Hexagon::SA1_seti:
628 case Hexagon::SA1_setin1:
629 case Hexagon::SA1_sxtb:
630 case Hexagon::SA1_sxth:
631 case Hexagon::SA1_tfr:
632 case Hexagon::SA1_zxtb:
633 case Hexagon::SA1_zxth:
634 case Hexagon::SL1_loadri_io:
635 case Hexagon::SL1_loadrub_io:
636 case Hexagon::SL2_deallocframe:
637 case Hexagon::SL2_jumpr31:
638 case Hexagon::SL2_jumpr31_f:
639 case Hexagon::SL2_jumpr31_fnew:
640 case Hexagon::SL2_jumpr31_t:
641 case Hexagon::SL2_jumpr31_tnew:
642 case Hexagon::SL2_loadrb_io:
643 case Hexagon::SL2_loadrd_sp:
644 case Hexagon::SL2_loadrh_io:
645 case Hexagon::SL2_loadri_sp:
646 case Hexagon::SL2_loadruh_io:
647 case Hexagon::SL2_return:
648 case Hexagon::SL2_return_f:
649 case Hexagon::SL2_return_fnew:
650 case Hexagon::SL2_return_t:
651 case Hexagon::SL2_return_tnew:
652 case Hexagon::SS1_storeb_io:
653 case Hexagon::SS1_storew_io:
654 case Hexagon::SS2_allocframe:
655 case Hexagon::SS2_storebi0:
656 case Hexagon::SS2_storebi1:
657 case Hexagon::SS2_stored_sp:
658 case Hexagon::SS2_storeh_io:
659 case Hexagon::SS2_storew_sp:
660 case Hexagon::SS2_storewi0:
661 case Hexagon::SS2_storewi1:
685 auto Sentinal =
static_cast<int64_t
>(std::numeric_limits<uint32_t>::max())
687 if (MCI.
size() <= Index)
693 if (!MCO.
getExpr()->evaluateAsAbsolute(Value))
734 switch (SchedClass) {
735 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
736 case Hexagon::Sched::ALU64_tc_2_SLOT23:
737 case Hexagon::Sched::ALU64_tc_3x_SLOT23:
738 case Hexagon::Sched::M_tc_2_SLOT23:
739 case Hexagon::Sched::M_tc_3x_SLOT23:
740 case Hexagon::Sched::S_2op_tc_2_SLOT23:
741 case Hexagon::Sched::S_3op_tc_2_SLOT23:
742 case Hexagon::Sched::S_3op_tc_3x_SLOT23:
757 assert(Duplex !=
nullptr);
783 const_cast<HexagonMCExpr &
>(*llvm::cast<HexagonMCExpr>(&Expr));
787 HexagonMCExpr const &HExpr = *llvm::cast<HexagonMCExpr>(&Expr);
799 unsigned Producer2) {
802 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
803 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
804 return (Consumer - Hexagon::V0) & 0x1;
805 if (Consumer == Producer2)
bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with an A-type insn in slot #1.
#define HEXAGON_PACKET_INNER_SIZE
static bool Check(DecodeStatus &Out, DecodeStatus In)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustExtend(bool Val=true)
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI)
void tryCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)
tryCompound - Given a bundle check for compound insns when one is found update the contents fo the bu...
static MCOperand createExpr(const MCExpr *Val)
void setInst(const MCInst *Val)
void setMustNotExtend(bool Val=true)
Describe properties that are true of each instruction in the target description file.
bool isIntRegForSubInst(unsigned Reg)
MachineInstrBuilder MachineInstrBuilder &DefMI const MCInstrDesc & Desc
bool isBundle(MCInst const &MCI)
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
bool isSubInstruction(MCInst const &MCI)
bool isDblRegForSubInst(unsigned Reg)
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
bool isMemStoreReorderEnabled(MCInst const &MCI)
void setInnerLoop(MCInst &MCI)
bool isImmext(MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
struct fuzzer::@269 Flags
MCInst const & instruction(MCInst const &MCB, size_t Index)
#define HEXAGON_PACKET_SIZE
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
bool isCall() const
Return true if the instruction is a call.
bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI)
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Base class for the full range of assembler expressions which are needed for parsing.
Reg
All possible values of the reg field in the ModR/M byte.
void padEndloop(MCContext &Context, MCInst &MCI)
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
StringRef getName(MCInstrInfo const &MCII, MCInst const &MCI)
void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate)
void setMemReorderDisabled(MCInst &MCI)
Context object for machine code objects.
bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short OperandNum)
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI)
void setS23_2_reloc(MCExpr const &Expr, bool Val=true)
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker)
unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI)
Return the new value or the newly produced value.
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
SmallVector< DuplexCandidate, 8 > getDuplexPossibilties(MCInstrInfo const &MCII, MCInst const &MCB)
void setS23_2_reloc(bool Val=true)
void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
bool s23_2_reloc(MCExpr const &Expr)
void setMustExtend(MCExpr const &Expr, bool Val=true)
const InstrItinerary * InstrItineraries
Instances of this class represent a single low-level machine instruction.
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI)
const MCExpr * getExpr() const
void setMemStoreReorderEnabled(MCInst &MCI)
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI)
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
bool mustExtend(MCExpr const &Expr)
Interface to description of machine instruction set.
int64_t const outerLoopMask
int64_t const memReorderDisabledMask
cl::opt< bool > HexagonDisableCompound
void setOuterLoop(MCInst &MCI)
MCExpr const & getExpr(MCExpr const &Expr)
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2)
void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI)
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
int64_t const memStoreReorderEnabledMask
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void setOpcode(unsigned Op)
size_t const bundleInstructionsOffset
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &)
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t minConstant(MCInst const &MCI, size_t Index)
A range adaptor for a pair of iterators.
unsigned getOpcode() const
Target - Wrapper for Target specific information.
bool isMemReorderDisabled(MCInst const &MCI)
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
#define HEXAGON_PACKET_OUTER_SIZE
static MCOperand createInst(const MCInst *Val)
MCInst deriveSubInst(MCInst const &Inst)
bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn can be packaged only with A and X-type insns.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
bool hasExtenderForIndex(MCInst const &MCB, size_t Index)
MCSubtargetInfo - Generic base class for all target subtargets.
const InstrStage HexagonStages[]
const MCInst * getInst() const
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
size_t bundleSize(MCInst const &MCI)
int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI)
bool mustNotExtend() const
bool hasImmExt(MCInst const &MCI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isInnerLoop(MCInst const &MCI)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
An itinerary represents the scheduling information for an instruction.
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
LLVM Value Representation.
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
bool isPredReg(unsigned Reg)
Check for a valid bundle.
void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
Return the slots used by the insn.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getDuplexRegisterNumbering(unsigned Reg)
bool isIntReg(unsigned Reg)
void addOperand(const MCOperand &Op)
StringRef - Represent a constant reference to a string, i.e.
MCInst * deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
int64_t const innerLoopMask
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI)
Instances of this class represent operands of the MCInst class.
bool mustNotExtend(MCExpr const &Expr)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
static MCOperand createImm(int64_t Val)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
cl::opt< bool > HexagonDisableDuplex
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
void setExpr(const MCExpr *Val)
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)