LLVM
4.0.0
Main Page
Related Pages
Modules
Namespaces
Classes
Files
Examples
File List
File Members
llvm.src
lib
Target
ARM
MCTargetDesc
ARMFixupKinds.h
Go to the documentation of this file.
1
//===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
2
//
3
// The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
10
#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
11
#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
12
13
#include "
llvm/MC/MCFixup.h
"
14
15
namespace
llvm {
16
namespace
ARM
{
17
enum
Fixups
{
18
// fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
19
// addresses
20
fixup_arm_ldst_pcrel_12
=
FirstTargetFixupKind
,
21
22
// fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
23
// the 16-bit halfwords reordered.
24
fixup_t2_ldst_pcrel_12
,
25
26
// fixup_arm_pcrel_10_unscaled - 10-bit PC relative relocation for symbol
27
// addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
28
fixup_arm_pcrel_10_unscaled
,
29
// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
30
// used in VFP instructions where the lower 2 bits are not encoded
31
// (so it's encoded as an 8-bit immediate).
32
fixup_arm_pcrel_10
,
33
// fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
34
// the short-swapped encoding of Thumb2 instructions.
35
fixup_t2_pcrel_10
,
36
// fixup_arm_pcrel_9 - 9-bit PC relative relocation for symbol addresses
37
// used in VFP instructions where bit 0 not encoded (so it's encoded as an
38
// 8-bit immediate).
39
fixup_arm_pcrel_9
,
40
// fixup_t2_pcrel_9 - Equivalent to fixup_arm_pcrel_9, accounting for
41
// the short-swapped encoding of Thumb2 instructions.
42
fixup_t2_pcrel_9
,
43
// fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
44
// addresses where the lower 2 bits are not encoded (so it's encoded as an
45
// 8-bit immediate).
46
fixup_thumb_adr_pcrel_10
,
47
// fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
48
// instruction.
49
fixup_arm_adr_pcrel_12
,
50
// fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
51
// instruction.
52
fixup_t2_adr_pcrel_12
,
53
// fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch
54
// instructions.
55
fixup_arm_condbranch
,
56
// fixup_arm_uncondbranch - 24-bit PC relative relocation for
57
// branch instructions. (unconditional)
58
fixup_arm_uncondbranch
,
59
// fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
60
// uconditional branch instructions.
61
fixup_t2_condbranch
,
62
// fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
63
// branch unconditional branch instructions.
64
fixup_t2_uncondbranch
,
65
66
// fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
67
fixup_arm_thumb_br
,
68
69
// The following fixups handle the ARM BL instructions. These can be
70
// conditionalised; however, the ARM ELF ABI requires a different relocation
71
// in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
72
// R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
73
// no conditional version; R_ARM_JUMP24 would have to insert a veneer.
74
//
75
// MachO does not draw a distinction between the two cases, so it will treat
76
// fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
77
78
// fixup_arm_uncondbl - Fixup for unconditional ARM BL instructions.
79
fixup_arm_uncondbl
,
80
81
// fixup_arm_condbl - Fixup for ARM BL instructions with nontrivial
82
// conditionalisation.
83
fixup_arm_condbl
,
84
85
// fixup_arm_blx - Fixup for ARM BLX instructions.
86
fixup_arm_blx
,
87
88
// fixup_arm_thumb_bl - Fixup for Thumb BL instructions.
89
fixup_arm_thumb_bl
,
90
91
// fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
92
fixup_arm_thumb_blx
,
93
94
// fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
95
fixup_arm_thumb_cb
,
96
97
// fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
98
fixup_arm_thumb_cp
,
99
100
// fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
101
fixup_arm_thumb_bcc
,
102
103
// The next two are for the movt/movw pair
104
// the 16bit imm field are split into imm{15-12} and imm{11-0}
105
fixup_arm_movt_hi16
,
// :upper16:
106
fixup_arm_movw_lo16
,
// :lower16:
107
fixup_t2_movt_hi16
,
// :upper16:
108
fixup_t2_movw_lo16
,
// :lower16:
109
110
// fixup_arm_mod_imm - Fixup for mod_imm
111
fixup_arm_mod_imm
,
112
113
// Marker
114
LastTargetFixupKind
,
115
NumTargetFixupKinds
=
LastTargetFixupKind
-
FirstTargetFixupKind
116
};
117
}
118
}
119
120
#endif
llvm::ARM::fixup_t2_pcrel_9
Definition:
ARMFixupKinds.h:42
llvm::ARM::fixup_t2_ldst_pcrel_12
Definition:
ARMFixupKinds.h:24
llvm::ARM::Fixups
Fixups
Definition:
ARMFixupKinds.h:17
llvm::ARM::fixup_arm_blx
Definition:
ARMFixupKinds.h:86
llvm::ARM::fixup_arm_uncondbl
Definition:
ARMFixupKinds.h:79
llvm::FirstTargetFixupKind
Definition:
MCFixup.h:45
llvm::ARM::fixup_arm_thumb_br
Definition:
ARMFixupKinds.h:67
llvm::ARM::fixup_arm_condbranch
Definition:
ARMFixupKinds.h:55
llvm::ARM::fixup_arm_pcrel_9
Definition:
ARMFixupKinds.h:39
llvm::ARM::fixup_arm_uncondbranch
Definition:
ARMFixupKinds.h:58
llvm::ARM::NumTargetFixupKinds
Definition:
ARMFixupKinds.h:115
llvm::ARM::fixup_arm_condbl
Definition:
ARMFixupKinds.h:83
llvm::ARM::fixup_arm_movw_lo16
Definition:
ARMFixupKinds.h:106
llvm::ARM::fixup_arm_adr_pcrel_12
Definition:
ARMFixupKinds.h:49
llvm::ARM::fixup_t2_condbranch
Definition:
ARMFixupKinds.h:61
llvm::WinEH::EncodingType::ARM
Windows AXP64.
llvm::ARM::fixup_thumb_adr_pcrel_10
Definition:
ARMFixupKinds.h:46
llvm::ARM::fixup_t2_movt_hi16
Definition:
ARMFixupKinds.h:107
llvm::ARM::fixup_arm_mod_imm
Definition:
ARMFixupKinds.h:111
llvm::ARM::fixup_arm_pcrel_10
Definition:
ARMFixupKinds.h:32
llvm::ARM::fixup_arm_thumb_bcc
Definition:
ARMFixupKinds.h:101
llvm::ARM::fixup_t2_movw_lo16
Definition:
ARMFixupKinds.h:108
llvm::ARM::fixup_t2_adr_pcrel_12
Definition:
ARMFixupKinds.h:52
llvm::ARM::fixup_arm_ldst_pcrel_12
Definition:
ARMFixupKinds.h:20
llvm::ARM::fixup_t2_pcrel_10
Definition:
ARMFixupKinds.h:35
llvm::ARM::fixup_arm_thumb_blx
Definition:
ARMFixupKinds.h:92
llvm::ARM::fixup_arm_movt_hi16
Definition:
ARMFixupKinds.h:105
llvm::ARM::fixup_t2_uncondbranch
Definition:
ARMFixupKinds.h:64
llvm::ARM::fixup_arm_pcrel_10_unscaled
Definition:
ARMFixupKinds.h:28
llvm::ARM::LastTargetFixupKind
Definition:
ARMFixupKinds.h:114
llvm::ARM::fixup_arm_thumb_cb
Definition:
ARMFixupKinds.h:95
llvm::ARM::fixup_arm_thumb_bl
Definition:
ARMFixupKinds.h:89
llvm::ARM::fixup_arm_thumb_cp
Definition:
ARMFixupKinds.h:98
MCFixup.h
Generated on Wed Mar 8 2017 17:05:59 for LLVM by
1.8.6