10 #define DEBUG_TYPE "hbr"
37 bool SbAE = (S < AE) || (S == AE && A.
TiedEnd);
38 bool ASbE = (AS <
E) || (AS ==
E &&
TiedEnd);
39 if ((AS < S && SbAE) || (S < AS && ASbE))
46 if (start() <= A.
start()) {
86 iterator Iter =
begin();
88 while (Iter !=
end()-1) {
89 iterator Next = std::next(Iter);
92 bool Merge = MergeAdjacent && (Iter->end() == Next->start());
93 if (Merge || Iter->overlaps(*Next)) {
103 void HexagonBlockRanges::RangeList::addsub(
const IndexRange &
A,
113 IndexType AS = A.
start(), AE = A.
end();
114 IndexType BS = B.
start(), BE = B.
end();
143 for (iterator Next,
I =
begin();
I !=
end();
I = Next) {
147 Next = this->erase(
I);
160 if (
In.isDebugValue())
163 Map.insert(std::make_pair(Idx, &
In));
170 auto F = Map.find(Idx);
171 return (
F != Map.end()) ?
F->second :
nullptr;
206 for (
auto &
I : Map) {
207 if (
I.second != OldMI)
209 if (NewMI !=
nullptr)
219 TII(*HST.getInstrInfo()), TRI(*HST.getRegisterInfo()),
220 Reserved(TRI.getReservedRegs(mf)) {
224 if (RC->isAllocatable())
226 for (
unsigned R : *RC)
237 if (
I.LaneMask.all()) {
238 Tmp.insert({
I.PhysReg,0});
243 if ((M &
I.LaneMask).any())
244 Tmp.insert({S.getSubReg(), 0});
249 if (!Reserved[R.Reg])
251 for (
auto S : expandToSubRegs(R, MRI, TRI))
252 if (!Reserved[S.Reg])
271 SRs.insert({R.
Reg, 0});
272 for (;
I.isValid(); ++
I)
277 unsigned PReg = *RC.
begin();
280 SRs.insert({R.Reg, 0});
281 for (;
I.isValid(); ++
I)
282 SRs.insert({R.Reg,
I.getSubRegIndex()});
287 void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
288 RegToRangeMap &LiveMap) {
289 std::map<RegisterRef,IndexType> LastDef, LastUse;
294 for (
auto R : getLiveIns(B, MRI, TRI))
295 LiveOnEntry.insert(R);
297 for (
auto R : LiveOnEntry)
300 auto closeRange = [&LastUse,&LastDef,&LiveMap] (RegisterRef R) ->
void {
301 auto LD = LastDef[R], LU = LastUse[R];
306 LiveMap[R].add(
LD, LU,
false,
false);
311 if (
In.isDebugValue())
313 IndexType Index = IndexMap.getIndex(&
In);
315 for (
auto &
Op :
In.operands()) {
316 if (!
Op.isReg() || !
Op.isUse() ||
Op.isUndef())
318 RegisterRef R = {
Op.getReg(),
Op.getSubReg() };
321 bool IsKill =
Op.isKill();
329 for (
auto &
Op :
In.operands()) {
330 if (!
Op.isReg() || !
Op.isDef() ||
Op.isUndef())
332 RegisterRef R = {
Op.getReg(),
Op.getSubReg() };
345 for (
auto *
SB : B.successors())
346 for (
auto R : getLiveIns(*
SB, MRI, TRI))
347 LiveOnExit.insert(R);
349 for (
auto R : LiveOnExit)
354 for (
auto &
I : LastUse)
356 Left.insert(
I.first);
357 for (
auto &
I : LastDef)
359 Left.insert(
I.first);
364 for (
auto &
P : LiveMap)
371 DEBUG(
dbgs() << __func__ <<
": index map\n" << IndexMap <<
'\n');
372 computeInitialLiveRanges(IndexMap, LiveMap);
373 DEBUG(
dbgs() << __func__ <<
": live map\n"
382 auto addDeadRanges = [&IndexMap,&LiveMap,&DeadMap] (
RegisterRef R) ->
void {
383 auto F = LiveMap.find(R);
384 if (
F == LiveMap.end() ||
F->second.empty()) {
390 RangeList::iterator A = RL.begin(), Z = RL.end()-1;
407 DeadMap[R].add(DS, DE,
false,
false);
423 for (
unsigned R = 1; R < NumRegs; ++R) {
425 if (Reserved[S.Reg] || Visited[S.Reg])
428 Visited[S.Reg] =
true;
431 for (
auto &
P : LiveMap)
433 addDeadRanges(
P.first);
435 DEBUG(
dbgs() << __func__ <<
": dead map\n"
454 OS <<
'[' << IR.
start() <<
':' << IR.
end() << (IR.
TiedEnd ?
'}' :
']');
469 for (
auto &
In : M.Block) {
471 OS << Idx << (Idx == M.
Last ?
". " :
" ") <<
In;
478 for (
auto &
I : P.Map) {
480 OS <<
PrintReg(
I.first.Reg, &P.TRI,
I.first.Sub) <<
" -> " << RL <<
"\n";
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const_iterator end(StringRef path)
Get end iterator over path.
iterator_range< livein_iterator > liveins() const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static RegisterSet expandToSubRegs(RegisterRef R, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI)
regclass_iterator regclass_end() const
bool isValid() const
Returns true if this iterator is not yet at the end.
const_iterator begin(StringRef path)
Get begin iterator over path.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx. ...
std::set< RegisterRef > RegisterSet
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
iterator begin() const
begin/end - Return all of the registers in this class.
bool overlaps(const IndexRange &A) const
MachineBasicBlock & getBlock() const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
IndexType getNextIndex(IndexType Idx) const
static bool add(uint64_t *dest, const uint64_t *x, const uint64_t *y, unsigned len)
This function adds the integer array x to the integer array Y and places the result in dest...
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
INITIALIZE_PASS(HexagonEarlyIfConversion,"hexagon-eif","Hexagon early if conversion", false, false) bool HexagonEarlyIfConversion MachineBasicBlock * SB
MachineInstr * getInstr(IndexType Idx) const
unsigned const MachineRegisterInfo * MRI
regclass_iterator regclass_begin() const
Register class iterators.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSubRegIterator enumerates all sub-registers of Reg.
void subtract(const IndexRange &Range)
void include(const RangeList &RL)
static void Merge(const std::string &Input, const std::vector< std::string > Result, size_t NumNewFeatures)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
HexagonBlockRanges(MachineFunction &MF)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
IndexType getPrevIndex(IndexType Idx) const
Representation of each machine instruction.
bool contains(const IndexRange &A) const
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
RegToRangeMap computeLiveMap(InstrIndexMap &IndexMap)
std::map< RegisterRef, RangeList > RegToRangeMap
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
IndexType getIndex(MachineInstr *MI) const
void merge(const IndexRange &A)
RegToRangeMap computeDeadMap(InstrIndexMap &IndexMap, RegToRangeMap &LiveMap)
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void unionize(bool MergeAdjacent=false)
This class implements an extremely fast bulk output stream that can only output to a stream...
void replaceInstr(MachineInstr *OldMI, MachineInstr *NewMI)
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
InstrIndexMap(MachineBasicBlock &B)
Statically lint checks LLVM IR
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.