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llvm.src
include
llvm
CodeGen
MachineCombinerPattern.h
Go to the documentation of this file.
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//===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
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// combiner ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines instruction pattern supported by combiner
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
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#define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
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namespace
llvm {
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/// These are instruction patterns matched by the machine combiner pass.
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enum class
MachineCombinerPattern
{
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// These are commutative variants for reassociating a computation chain. See
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// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
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REASSOC_AX_BY
,
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REASSOC_AX_YB
,
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REASSOC_XA_BY
,
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REASSOC_XA_YB
,
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// These are multiply-add patterns matched by the AArch64 machine combiner.
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MULADDW_OP1
,
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MULADDW_OP2
,
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MULSUBW_OP1
,
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MULSUBW_OP2
,
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MULADDWI_OP1
,
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MULSUBWI_OP1
,
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MULADDX_OP1
,
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MULADDX_OP2
,
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MULSUBX_OP1
,
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MULSUBX_OP2
,
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MULADDXI_OP1
,
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MULSUBXI_OP1
,
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// Floating Point
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FMULADDS_OP1
,
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FMULADDS_OP2
,
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FMULSUBS_OP1
,
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FMULSUBS_OP2
,
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FMULADDD_OP1
,
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FMULADDD_OP2
,
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FMULSUBD_OP1
,
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FMULSUBD_OP2
,
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FMLAv1i32_indexed_OP1
,
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FMLAv1i32_indexed_OP2
,
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FMLAv1i64_indexed_OP1
,
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FMLAv1i64_indexed_OP2
,
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FMLAv2f32_OP2
,
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FMLAv2f32_OP1
,
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FMLAv2f64_OP1
,
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FMLAv2f64_OP2
,
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FMLAv2i32_indexed_OP1
,
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FMLAv2i32_indexed_OP2
,
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FMLAv2i64_indexed_OP1
,
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FMLAv2i64_indexed_OP2
,
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FMLAv4f32_OP1
,
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FMLAv4f32_OP2
,
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FMLAv4i32_indexed_OP1
,
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FMLAv4i32_indexed_OP2
,
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FMLSv1i32_indexed_OP2
,
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FMLSv1i64_indexed_OP2
,
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FMLSv2i32_indexed_OP2
,
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FMLSv2i64_indexed_OP2
,
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FMLSv2f32_OP2
,
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FMLSv2f64_OP2
,
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FMLSv4i32_indexed_OP2
,
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FMLSv4f32_OP2
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};
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}
// end namespace llvm
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#endif
llvm::MachineCombinerPattern::FMULSUBS_OP2
llvm::MachineCombinerPattern::FMLSv2i64_indexed_OP2
llvm::MachineCombinerPattern::FMULADDD_OP2
llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP1
llvm::MachineCombinerPattern::FMULSUBS_OP1
llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP2
llvm::MachineCombinerPattern::FMULADDS_OP2
llvm::MachineCombinerPattern::FMLAv4i32_indexed_OP2
llvm::MachineCombinerPattern::MULADDX_OP1
llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP2
llvm::MachineCombinerPattern::MULSUBW_OP1
llvm::MachineCombinerPattern::FMLSv2f64_OP2
llvm::MachineCombinerPattern::FMLSv2f32_OP2
llvm::MachineCombinerPattern::FMLAv1i32_indexed_OP1
llvm::MachineCombinerPattern::MULSUBXI_OP1
llvm::MachineCombinerPattern::FMLSv4i32_indexed_OP2
llvm::MachineCombinerPattern::FMLAv2f64_OP2
llvm::MachineCombinerPattern::REASSOC_AX_YB
llvm::MachineCombinerPattern::MULSUBWI_OP1
llvm::MachineCombinerPattern::FMLSv4f32_OP2
llvm::MachineCombinerPattern::MULSUBW_OP2
llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP2
llvm::MachineCombinerPattern::FMULSUBD_OP2
llvm::MachineCombinerPattern::FMLAv4f32_OP2
llvm::MachineCombinerPattern::MULSUBX_OP2
llvm::MachineCombinerPattern::FMLAv2f32_OP1
llvm::MachineCombinerPattern::FMLAv2i32_indexed_OP1
llvm::MachineCombinerPattern::FMLSv2i32_indexed_OP2
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition:
MachineCombinerPattern.h:21
llvm::MachineCombinerPattern::FMULSUBD_OP1
llvm::MachineCombinerPattern::FMULADDD_OP1
llvm::MachineCombinerPattern::FMLAv4f32_OP1
llvm::MachineCombinerPattern::FMLAv1i64_indexed_OP1
llvm::MachineCombinerPattern::REASSOC_AX_BY
llvm::MachineCombinerPattern::FMULADDS_OP1
llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP2
llvm::MachineCombinerPattern::FMLAv2f64_OP1
llvm::MachineCombinerPattern::FMLAv2f32_OP2
llvm::MachineCombinerPattern::MULADDW_OP2
llvm::MachineCombinerPattern::REASSOC_XA_BY
llvm::MachineCombinerPattern::MULSUBX_OP1
llvm::MachineCombinerPattern::FMLSv1i64_indexed_OP2
llvm::MachineCombinerPattern::MULADDXI_OP1
llvm::MachineCombinerPattern::MULADDX_OP2
llvm::MachineCombinerPattern::FMLAv2i64_indexed_OP1
llvm::MachineCombinerPattern::REASSOC_XA_YB
llvm::MachineCombinerPattern::FMLSv1i32_indexed_OP2
llvm::MachineCombinerPattern::MULADDW_OP1
llvm::MachineCombinerPattern::MULADDWI_OP1
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