17 #define _USE_MATH_DEFINES
42 "amdgpu-vgpr-index-mode",
43 cl::desc(
"Use GPR indexing mode instead of movrel for vector indexing"),
48 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
49 for (
unsigned Reg = 0;
Reg < NumSGPRs; ++
Reg) {
51 return AMDGPU::SGPR0 +
Reg;
369 unsigned IntrID)
const {
371 case Intrinsic::amdgcn_atomic_inc:
372 case Intrinsic::amdgcn_atomic_dec:
393 bool SITargetLowering::isLegalFlatAddressingMode(
const AddrMode &AM)
const {
396 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
399 bool SITargetLowering::isLegalMUBUFAddressingMode(
const AddrMode &AM)
const {
409 if (!isUInt<12>(AM.BaseOffs))
453 return isLegalFlatAddressingMode(AM);
456 return isLegalMUBUFAddressingMode(AM);
463 return isLegalMUBUFAddressingMode(AM);
470 return isLegalMUBUFAddressingMode(AM);
498 return isLegalMUBUFAddressingMode(AM);
524 return isLegalFlatAddressingMode(AM);
534 bool *IsFast)
const {
552 bool AlignedBy4 = (Align % 4 == 0);
554 *IsFast = AlignedBy4;
573 (Align % 4 == 0) :
true;
593 unsigned SrcAlign,
bool IsMemset,
602 if (Size >= 16 && DstAlign >= 4)
605 if (Size >= 8 && DstAlign >= 4)
619 unsigned DestAS)
const {
624 const MemSDNode *MemNode = cast<MemSDNode>(
N);
631 unsigned DestAS)
const {
641 const MemSDNode *MemNode = cast<MemSDNode>(
N);
648 if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
649 isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
714 unsigned Offset,
bool Signed,
723 SDValue Ptr = LowerParameterPtr(DAG, SL, Chain, Offset);
737 Val = getFPExtOrFPTrunc(DAG, Val, SL, VT);
760 *Fn,
"unsupported non-compute shaders with HSA", DL.
getDebugLoc());
767 if (ST.debuggerEmitPrologue())
768 createDebuggerPrologueStackObjects(MF);
773 for (
unsigned i = 0, e = Ins.
size(), PSInputNum = 0;
i != e; ++
i) {
807 for (
unsigned j = 0; j != NumElements; ++j) {
837 CCInfo.AllocateReg(AMDGPU::VGPR1);
855 MF.
addLiveIn(PrivateMemoryPtrReg, &AMDGPU::SReg_64RegClass);
856 CCInfo.AllocateReg(PrivateMemoryPtrReg);
862 MF.
addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
863 CCInfo.AllocateReg(PrivateSegmentBufferReg);
868 MF.
addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
869 CCInfo.AllocateReg(DispatchPtrReg);
874 MF.
addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
875 CCInfo.AllocateReg(QueuePtrReg);
880 MF.
addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
881 CCInfo.AllocateReg(InputPtrReg);
886 MF.
addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
887 CCInfo.AllocateReg(DispatchIDReg);
892 MF.
addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
893 CCInfo.AllocateReg(FlatScratchInitReg);
903 for (
unsigned i = 0, e = Ins.
size(), ArgIdx = 0;
i != e; ++
i) {
921 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
922 Offset, Ins[i].
Flags.isSExt(),
947 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
948 &AMDGPU::SGPR_64RegClass);
949 Reg = MF.
addLiveIn(Reg, &AMDGPU::SGPR_64RegClass);
968 for (
unsigned j = 1; j != NumElements; ++j) {
969 Reg = ArgLocs[ArgIdx++].getLocReg();
993 MF.
addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
994 CCInfo.AllocateReg(Reg);
999 MF.
addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1000 CCInfo.AllocateReg(Reg);
1005 MF.
addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1006 CCInfo.AllocateReg(Reg);
1011 MF.
addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
1012 CCInfo.AllocateReg(Reg);
1017 unsigned PrivateSegmentWaveByteOffsetReg;
1025 MF.
addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
1026 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
1034 if (HasStackObjects)
1040 HasStackObjects =
true;
1042 if (ST.isAmdCodeObjectV2(MF)) {
1043 if (HasStackObjects) {
1056 unsigned ReservedBufferReg
1058 unsigned ReservedOffsetReg
1077 if (HasStackObjects) {
1082 unsigned ReservedOffsetReg
1090 MF.
addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1091 CCInfo.AllocateReg(Reg);
1096 MF.
addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1097 CCInfo.AllocateReg(Reg);
1102 MF.
addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1103 CCInfo.AllocateReg(Reg);
1131 for (
unsigned i = 0, e = Outs.
size();
i != e; ++
i) {
1144 for (
unsigned j = 0; j != NumElements; ++j) {
1172 for (
unsigned i = 0, realRVLocIdx = 0;
1174 ++
i, ++realRVLocIdx) {
1178 SDValue Arg = SplitVals[realRVLocIdx];
1207 .Case(
"m0", AMDGPU::M0)
1208 .
Case(
"exec", AMDGPU::EXEC)
1209 .
Case(
"exec_lo", AMDGPU::EXEC_LO)
1210 .
Case(
"exec_hi", AMDGPU::EXEC_HI)
1211 .
Case(
"flat_scratch", AMDGPU::FLAT_SCR)
1212 .
Case(
"flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
1213 .
Case(
"flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
1216 if (Reg == AMDGPU::NoRegister) {
1225 +
StringRef(RegName) +
"\" for subtarget."));
1230 case AMDGPU::EXEC_LO:
1231 case AMDGPU::EXEC_HI:
1232 case AMDGPU::FLAT_SCR_LO:
1233 case AMDGPU::FLAT_SCR_HI:
1238 case AMDGPU::FLAT_SCR:
1259 if (SplitPoint == BB->
end()) {
1261 MI.
setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
1275 MI.
setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
1294 unsigned InitSaveExecReg,
1296 bool UseGPRIdxMode) {
1304 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
1310 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
1311 .addReg(InitSaveExecReg)
1317 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
1321 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
1322 .addReg(CurrentIdxReg)
1325 if (UseGPRIdxMode) {
1328 IdxReg = CurrentIdxReg;
1331 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
1337 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_IDX))
1343 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1346 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
1353 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), NewExec)
1360 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
1361 .addReg(AMDGPU::EXEC)
1368 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
1382 unsigned InitResultReg,
1385 bool UseGPRIdxMode) {
1395 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
1398 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64), SaveExec)
1399 .addReg(AMDGPU::EXEC);
1408 MF->
insert(MBBI, LoopBB);
1409 MF->
insert(MBBI, RemainderBB);
1423 InitResultReg, DstReg, PhiReg, TmpExec,
1424 Offset, UseGPRIdxMode);
1427 BuildMI(*RemainderBB, First, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
1434 static std::pair<unsigned, int>
1439 int NumElts = SuperRC->
getSize() / 4;
1443 if (Offset >= NumElts || Offset < 0)
1444 return std::make_pair(AMDGPU::sub0, Offset);
1446 return std::make_pair(AMDGPU::sub0 + Offset, 0);
1455 bool IsIndirectSrc) {
1468 if (UseGPRIdxMode) {
1469 unsigned IdxMode = IsIndirectSrc ?
1473 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
1480 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
1484 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
1495 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1498 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
1522 std::tie(SubReg, Offset)
1531 if (UseGPRIdxMode) {
1535 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
1539 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1541 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
1558 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
1560 if (UseGPRIdxMode) {
1567 BuildMI(MBB, std::next(I), DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1570 auto InsPt =
loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, UseGPRIdxMode);
1573 if (UseGPRIdxMode) {
1574 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
1579 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
1592 return AMDGPU::V_MOVRELD_B32_V1;
1594 return AMDGPU::V_MOVRELD_B32_V2;
1596 return AMDGPU::V_MOVRELD_B32_V4;
1598 return AMDGPU::V_MOVRELD_B32_V8;
1600 return AMDGPU::V_MOVRELD_B32_V16;
1630 if (Idx->
getReg() == AMDGPU::NoRegister) {
1636 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
1649 if (UseGPRIdxMode) {
1650 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
1657 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1661 BuildMI(MBB, I, DL, MovRelDesc)
1665 .addImm(SubReg - AMDGPU::sub0);
1677 if (UseGPRIdxMode) {
1686 BuildMI(MBB, std::next(I), DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1695 if (UseGPRIdxMode) {
1696 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
1705 BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
1709 .
addImm(SubReg - AMDGPU::sub0);
1744 case AMDGPU::SI_INIT_M0: {
1746 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1751 case AMDGPU::GET_GROUPSTATICSIZE: {
1753 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
1759 case AMDGPU::SI_INDIRECT_SRC_V1:
1760 case AMDGPU::SI_INDIRECT_SRC_V2:
1761 case AMDGPU::SI_INDIRECT_SRC_V4:
1762 case AMDGPU::SI_INDIRECT_SRC_V8:
1763 case AMDGPU::SI_INDIRECT_SRC_V16:
1765 case AMDGPU::SI_INDIRECT_DST_V1:
1766 case AMDGPU::SI_INDIRECT_DST_V2:
1767 case AMDGPU::SI_INDIRECT_DST_V4:
1768 case AMDGPU::SI_INDIRECT_DST_V8:
1769 case AMDGPU::SI_INDIRECT_DST_V16:
1771 case AMDGPU::SI_KILL:
1773 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
1785 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
1786 .addReg(Src0, 0, AMDGPU::sub0)
1787 .
addReg(Src1, 0, AMDGPU::sub0)
1789 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
1790 .addReg(Src0, 0, AMDGPU::sub1)
1791 .
addReg(Src1, 0, AMDGPU::sub1)
1794 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
1802 case AMDGPU::SI_BR_UNDEF: {
1889 SDValue Result = LowerLOAD(Op, DAG);
1892 "Load should return a value and a chain");
1898 return LowerTrig(Op, DAG);
1900 case ISD::FDIV:
return LowerFDIV(Op, DAG);
1906 return LowerGlobalAddress(MFI, Op, DAG);
1912 case ISD::TRAP:
return lowerTRAP(Op, DAG);
1914 return lowerFP_ROUND(Op, DAG);
1926 if (
I.getUse().get() != Value)
1929 if (
I->getOpcode() == Opcode)
1935 bool SITargetLowering::isCFIntrinsic(
const SDNode *Intr)
const {
1937 switch (cast<ConstantSDNode>(Intr->
getOperand(1))->getZExtValue()) {
1938 case AMDGPUIntrinsic::amdgcn_if:
1939 case AMDGPUIntrinsic::amdgcn_else:
1940 case AMDGPUIntrinsic::amdgcn_end_cf:
1941 case AMDGPUIntrinsic::amdgcn_loop:
1949 switch (cast<ConstantSDNode>(Intr->
getOperand(0))->getZExtValue()) {
1950 case AMDGPUIntrinsic::amdgcn_break:
1951 case AMDGPUIntrinsic::amdgcn_if_break:
1952 case AMDGPUIntrinsic::amdgcn_else_break:
1962 void SITargetLowering::createDebuggerPrologueStackObjects(
1978 for (
unsigned i = 0;
i < 3; ++
i) {
1988 bool SITargetLowering::shouldEmitFixup(
const GlobalValue *GV)
const {
1994 bool SITargetLowering::shouldEmitGOTReloc(
const GlobalValue *GV)
const {
1997 !shouldEmitFixup(GV) &&
2001 bool SITargetLowering::shouldEmitPCReloc(
const GlobalValue *GV)
const {
2002 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
2035 if (!isCFIntrinsic(Intr)) {
2119 "Do not know how to custom lower FP_ROUND for non-f16 type");
2122 EVT SrcVT = Src.getValueType();
2133 SDValue SITargetLowering::getSegmentAperture(
unsigned AS,
2139 assert(UserSGPR != AMDGPU::NoRegister);
2142 DAG, &AMDGPU::SReg_64RegClass, UserSGPR,
MVT::i64);
2183 NonNull, Ptr, SegmentNullPtr);
2223 SDLoc DL,
unsigned Offset,
EVT PtrVT,
2259 GAFlags : GAFlags + 1);
2276 if (shouldEmitFixup(GV))
2278 else if (shouldEmitPCReloc(GV))
2301 "trap handler not supported",
2333 unsigned Offset)
const {
2344 "non-hsa intrinsic with hsa target",
2352 "intrinsic not supported on subtarget",
2366 unsigned IntrinsicID = cast<ConstantSDNode>(Op.
getOperand(0))->getZExtValue();
2370 switch (IntrinsicID) {
2371 case Intrinsic::amdgcn_implicit_buffer_ptr: {
2375 case Intrinsic::amdgcn_dispatch_ptr:
2376 case Intrinsic::amdgcn_queue_ptr: {
2379 *MF.
getFunction(),
"unsupported hsa intrinsic without hsa target",
2385 auto Reg = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
2388 TRI->getPreloadedValue(MF, Reg), VT);
2390 case Intrinsic::amdgcn_implicitarg_ptr: {
2392 return LowerParameterPtr(DAG, DL, DAG.
getEntryNode(), offset);
2394 case Intrinsic::amdgcn_kernarg_segment_ptr: {
2399 case Intrinsic::amdgcn_dispatch_id: {
2403 case Intrinsic::amdgcn_rcp:
2405 case Intrinsic::amdgcn_rsq:
2406 case AMDGPUIntrinsic::AMDGPU_rsq:
2408 case Intrinsic::amdgcn_rsq_legacy: {
2414 case Intrinsic::amdgcn_rcp_legacy: {
2419 case Intrinsic::amdgcn_rsq_clamp: {
2433 case Intrinsic::r600_read_ngroups_x:
2437 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
2439 case Intrinsic::r600_read_ngroups_y:
2443 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
2445 case Intrinsic::r600_read_ngroups_z:
2449 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
2451 case Intrinsic::r600_read_global_size_x:
2455 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
2457 case Intrinsic::r600_read_global_size_y:
2461 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
2463 case Intrinsic::r600_read_global_size_z:
2467 return LowerParameter(DAG, VT, VT, DL, DAG.
getEntryNode(),
2469 case Intrinsic::r600_read_local_size_x:
2473 return lowerImplicitZextParam(DAG, Op,
MVT::i16,
2475 case Intrinsic::r600_read_local_size_y:
2479 return lowerImplicitZextParam(DAG, Op,
MVT::i16,
2481 case Intrinsic::r600_read_local_size_z:
2485 return lowerImplicitZextParam(DAG, Op,
MVT::i16,
2487 case Intrinsic::amdgcn_workgroup_id_x:
2488 case Intrinsic::r600_read_tgid_x:
2491 case Intrinsic::amdgcn_workgroup_id_y:
2492 case Intrinsic::r600_read_tgid_y:
2495 case Intrinsic::amdgcn_workgroup_id_z:
2496 case Intrinsic::r600_read_tgid_z:
2499 case Intrinsic::amdgcn_workitem_id_x:
2500 case Intrinsic::r600_read_tidig_x:
2503 case Intrinsic::amdgcn_workitem_id_y:
2504 case Intrinsic::r600_read_tidig_y:
2507 case Intrinsic::amdgcn_workitem_id_z:
2508 case Intrinsic::r600_read_tidig_z:
2511 case AMDGPUIntrinsic::SI_load_const: {
2525 case AMDGPUIntrinsic::amdgcn_fdiv_fast: {
2526 return lowerFDIV_FAST(Op, DAG);
2528 case AMDGPUIntrinsic::SI_vs_load_input:
2534 case AMDGPUIntrinsic::SI_fs_constant: {
2541 case AMDGPUIntrinsic::SI_packf16:
2545 case AMDGPUIntrinsic::SI_fs_interp: {
2562 case Intrinsic::amdgcn_interp_mov: {
2568 case Intrinsic::amdgcn_interp_p1: {
2574 case Intrinsic::amdgcn_interp_p2: {
2581 case Intrinsic::amdgcn_sin:
2584 case Intrinsic::amdgcn_cos:
2587 case Intrinsic::amdgcn_log_clamp: {
2592 *MF.
getFunction(),
"intrinsic not supported on subtarget",
2597 case Intrinsic::amdgcn_ldexp:
2601 case Intrinsic::amdgcn_fract:
2604 case Intrinsic::amdgcn_class:
2607 case Intrinsic::amdgcn_div_fmas:
2612 case Intrinsic::amdgcn_div_fixup:
2616 case Intrinsic::amdgcn_trig_preop:
2619 case Intrinsic::amdgcn_div_scale: {
2638 Denominator, Numerator);
2640 case Intrinsic::amdgcn_icmp: {
2644 if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
2645 CondCode >= ICmpInst::Predicate::BAD_ICMP_PREDICATE)
2653 case Intrinsic::amdgcn_fcmp: {
2657 if (CondCode <= FCmpInst::Predicate::FCMP_FALSE ||
2658 CondCode >= FCmpInst::Predicate::FCMP_TRUE)
2666 case Intrinsic::amdgcn_fmul_legacy:
2669 case Intrinsic::amdgcn_sffbh:
2670 case AMDGPUIntrinsic::AMDGPU_flbit_i32:
2679 unsigned IntrID = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
2682 case Intrinsic::amdgcn_atomic_inc:
2683 case Intrinsic::amdgcn_atomic_dec: {
2685 unsigned Opc = (IntrID == Intrinsic::amdgcn_atomic_inc) ?
2696 case Intrinsic::amdgcn_buffer_load:
2697 case Intrinsic::amdgcn_buffer_load_format: {
2709 unsigned Opc = (IntrID == Intrinsic::amdgcn_buffer_load) ?
2731 unsigned IntrinsicID = cast<ConstantSDNode>(Op.
getOperand(1))->getZExtValue();
2733 switch (IntrinsicID) {
2734 case AMDGPUIntrinsic::SI_sendmsg:
2735 case Intrinsic::amdgcn_s_sendmsg: {
2741 case Intrinsic::amdgcn_s_sendmsghalt: {
2747 case AMDGPUIntrinsic::SI_tbuffer_store: {
2774 case AMDGPUIntrinsic::AMDGPU_kill: {
2777 if (!K->isNegative())
2787 case AMDGPUIntrinsic::SI_export: {
2806 unsigned Opc = Done->isNullValue() ?
2832 BasePtr, RealMemVT, MMO);
2846 "Custom lowering for non-i32 vectors hasn't been implemented.");
2885 if (NumElements > 4)
2897 if (NumElements > 2)
2902 if (NumElements > 4)
2910 if (NumElements > 2)
2913 if (NumElements == 2)
2964 if (CLHS->isExactlyValue(1.0)) {
2984 if (CLHS->isExactlyValue(-1.0)) {
3009 return DAG.
getNode(Opcode, SL, VT, A, B);
3030 return DAG.
getNode(Opcode, SL, VT, A, B, C);
3048 if (
SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
3102 if (
SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
3136 EnableDenormValue, BitField);
3147 ApproxRcp, One, NegDivScale0);
3156 NumeratorScaled, Mul);
3161 NumeratorScaled, Fma3);
3164 const SDValue DisableDenormValue =
3173 DisableDenorm, DAG.
getRoot());
3179 Fma4, Fma1, Fma3, Scale);
3186 return lowerFastUnsafeFDIV(Op, DAG);
3214 NegDivScale0, Mul, DivScale1);
3246 Fma4, Fma3, Mul, Scale);
3255 return LowerFDIV32(Op, DAG);
3258 return LowerFDIV64(Op, DAG);
3261 return LowerFDIV16(Op, DAG);
3294 unsigned NumElements = VT.getVectorNumElements();
3298 if (NumElements > 4)
3306 if (NumElements > 2)
3310 if (NumElements > 4)
3318 if (NumElements > 2)
3321 if (NumElements == 2)
3373 SDValue Ops[] = { ChainIn, Addr, NewOld };
3384 DAGCombinerInfo &DCI)
const {
3400 if (DCI.isAfterLegalizeVectorOps() && SrcVT ==
MVT::i32) {
3403 DCI.AddToWorklist(Cvt.
getNode());
3418 return isUInt<12>(OffsetSize);
3424 return isUInt<20>(OffsetSize);
3426 return (OffsetSize % 4 == 0) &&
isUInt<8>(OffsetSize / 4);
3456 DAGCombinerInfo &DCI)
const {
3488 DAGCombinerInfo &DCI)
const {
3509 return (Opc ==
ISD::AND && (Val == 0 || Val == 0xffffffff)) ||
3510 (Opc ==
ISD::OR && (Val == 0xffffffff || Val == 0)) ||
3519 SDValue SITargetLowering::splitBinaryBitConstantOp(
3520 DAGCombinerInfo &DCI,
3542 DAGCombinerInfo &DCI)
const {
3543 if (DCI.isBeforeLegalize())
3556 = splitBinaryBitConstantOp(DCI,
SDLoc(N),
ISD::AND, LHS, CRHS))
3605 DAGCombinerInfo &DCI)
const {
3625 static const uint32_t MaxMask = 0x3ff;
3657 DCI.AddToWorklist(LowOr.
getNode());
3658 DCI.AddToWorklist(HiBits.
getNode());
3669 = splitBinaryBitConstantOp(DCI,
SDLoc(N),
ISD::OR, LHS, CRHS))
3677 DAGCombinerInfo &DCI)
const {
3688 = splitBinaryBitConstantOp(DCI,
SDLoc(N),
ISD::XOR, LHS, CRHS))
3696 DAGCombinerInfo &DCI)
const {
3701 if (
const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
3702 if (CMask->isNullValue())
3713 SDValue SITargetLowering::performFCanonicalizeCombine(
3715 DAGCombinerInfo &DCI)
const {
3800 Tmp3 = DAG.
getNode(ExtOp, SL, NVT, Op1);
3846 DAGCombinerInfo &DCI)
const {
3906 unsigned SITargetLowering::getFusedOpcode(
const SelectionDAG &DAG,
3908 const SDNode *N1)
const {
3920 (cast<BinaryWithFlagsSDNode>(N0)->Flags.hasUnsafeAlgebra() &&
3930 DAGCombinerInfo &DCI)
const {
3949 unsigned FusedOp = getFusedOpcode(DAG, N, LHS.
getNode());
3952 return DAG.
getNode(FusedOp, SL, VT, A, Two, RHS);
3961 unsigned FusedOp = getFusedOpcode(DAG, N, RHS.
getNode());
3964 return DAG.
getNode(FusedOp, SL, VT, A, Two, LHS);
3973 DAGCombinerInfo &DCI)
const {
3993 unsigned FusedOp = getFusedOpcode(DAG, N, LHS.getNode());
3998 return DAG.
getNode(FusedOp, SL, VT, A, Two, NegRHS);
4008 unsigned FusedOp = getFusedOpcode(DAG, N, RHS.
getNode());
4011 return DAG.
getNode(FusedOp, SL, VT, A, NegTwo, LHS);
4020 DAGCombinerInfo &DCI)
const {
4051 SDValue SITargetLowering::performCvtF32UByteNCombine(
SDNode *N,
4052 DAGCombinerInfo &DCI)
const {
4069 dyn_cast<ConstantSDNode>(Srl.
getOperand(1))) {
4073 unsigned SrcOffset = C->getZExtValue() + 8 *
Offset;
4074 if (SrcOffset < 32 && SrcOffset % 8 == 0) {
4083 APInt KnownZero, KnownOne;
4085 !DCI.isBeforeLegalizeOps());
4087 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
4088 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
4089 DCI.CommitTargetLoweringOpt(TLO);
4101 return performFAddCombine(N, DCI);
4103 return performFSubCombine(N, DCI);
4105 return performSetCCCombine(N, DCI);
4117 return performMinMaxCombine(N, DCI);
4141 return performMemSDNodeCombine(cast<MemSDNode>(N), DCI);
4144 return performAndCombine(N, DCI);
4146 return performOrCombine(N, DCI);
4148 return performXorCombine(N, DCI);
4150 return performClassCombine(N, DCI);
4152 return performFCanonicalizeCombine(N, DCI);
4167 return performUCharToFloatCombine(N, DCI);
4172 return performCvtF32UByteNCombine(N, DCI);
4181 case AMDGPU::sub0:
return 0;
4182 case AMDGPU::sub1:
return 1;
4183 case AMDGPU::sub2:
return 2;
4184 case AMDGPU::sub3:
return 3;
4189 void SITargetLowering::adjustWritemask(
MachineSDNode *&Node,
4195 unsigned NewDmask = 0;
4214 for (
unsigned i = 0, Dmask = OldDmask;
i <= Lane;
i++) {
4217 Dmask &= ~(1 << Comp);
4225 NewDmask |= 1 << Comp;
4229 if (NewDmask == OldDmask)
4233 std::vector<SDValue> Ops;
4236 Ops.insert(Ops.end(), Node->
op_begin() + DmaskIdx + 1, Node->
op_end());
4241 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
4252 for (
unsigned i = 0, Idx = AMDGPU::sub0;
i < 4; ++
i) {
4263 case AMDGPU::sub0: Idx = AMDGPU::sub1;
break;
4264 case AMDGPU::sub1: Idx = AMDGPU::sub2;
break;
4265 case AMDGPU::sub2: Idx = AMDGPU::sub3;
break;
4274 return isa<FrameIndexSDNode>(
Op);
4305 if (TII->
isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
4307 adjustWritemask(Node, DAG);
4309 if (Opcode == AMDGPU::INSERT_SUBREG ||
4310 Opcode == AMDGPU::REG_SEQUENCE) {
4335 if (RC != &AMDGPU::VReg_128RegClass)
4340 unsigned BitsSet = 0;
4341 for (
unsigned i = 0;
i < 4; ++
i)
4342 BitsSet += Writemask & (1 <<
i) ? 1 : 0;
4345 case 1: RC = &AMDGPU::VGPR_32RegClass;
break;
4346 case 2: RC = &AMDGPU::VReg_64RegClass;
break;
4347 case 3: RC = &AMDGPU::VReg_96RegClass;
break;
4351 MI.
setDesc(TII->get(NewOpcode));
4358 if (NoRetAtomicOp != -1) {
4360 MI.
setDesc(TII->get(NoRetAtomicOp));
4378 MI.
setDesc(TII->get(NoRetAtomicOp));
4386 TII->get(AMDGPU::IMPLICIT_DEF),
Def);
4435 uint64_t RsrcDword2And3)
const {
4445 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
4465 unsigned Reg,
EVT VT)
const {
4469 cast<RegisterSDNode>(VReg)->getReg(), VT);
4476 std::pair<unsigned, const TargetRegisterClass *>
4483 if (Constraint.
size() == 1) {
4484 switch (Constraint[0]) {
4489 return std::make_pair(0U,
nullptr);
4492 return std::make_pair(0U, &AMDGPU::SReg_32_XM0RegClass);
4494 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
4496 return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
4498 return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
4504 return std::make_pair(0U,
nullptr);
4507 return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
4509 return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
4511 return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
4513 return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
4515 return std::make_pair(0U, &AMDGPU::VReg_256RegClass);
4517 return std::make_pair(0U, &AMDGPU::VReg_512RegClass);
4522 if (Constraint.
size() > 1) {
4524 if (Constraint[1] ==
'v') {
4525 RC = &AMDGPU::VGPR_32RegClass;
4526 }
else if (Constraint[1] ==
's') {
4527 RC = &AMDGPU::SGPR_32RegClass;
4533 if (!Failed && Idx < RC->getNumRegs())
4542 if (Constraint.
size() == 1) {
4543 switch (Constraint[0]) {
value_iterator value_begin() const
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
constexpr bool isUInt< 32 >(uint64_t x)
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
void push_back(const T &Elt)
BUILTIN_OP_END - This must be the last enum value in this list.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
static void r3(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
A parsed version of the target data layout string in and methods for querying it. ...
const AMDGPURegisterInfo * getRegisterInfo() const override=0
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Interface definition for SIRegisterInfo.
SDValue getValue(unsigned R) const
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
const DebugLoc & getDebugLoc() const
static void r2(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const
Given a MIMG Opcode that writes all 4 channels, return the equivalent opcode that writes Channels Cha...
CombineLevel getDAGCombineLevel()
unsigned getQueuePtrUserSGPR() const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool hasFlatScratchInit() const
LLVMContext * getContext() const
Diagnostic information for unsupported feature in backend.
AMDGPU specific subclass of TargetSubtarget.
static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, SDLoc DL, EVT VT)
uint64_t getZExtValue() const
Get zero extended value.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
bool isKnownNeverNaN(SDValue Op) const
Test whether the given SDValue is known to never be NaN.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
BR_CC - Conditional branch.
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
LocInfo getLocInfo() const
unsigned getRegister(unsigned i) const
Return the specified register in the class.
void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool hasOneUse() const
Return true if there is exactly one use of this node.
unsigned getDestAddressSpace() const
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
void AnalyzeFormalArguments(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
const TargetMachine & getTargetMachine() const
SDVTList getVTList() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool hasUnalignedBufferAccess() const
constexpr uint32_t Lo_32(uint64_t Value)
Lo_32 - This function returns the low 32 bits of a 64 bit value.
virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, SelectionDAG &DAG) const
bool hasDispatchID() const
const TargetMachine & getTarget() const
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
Describe properties that are true of each instruction in the target description file.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
bool hasFastFMAF32() const
void setIsUndef(bool Val=true)
unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI)
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
This class represents a function call, abstracting a target machine's calling convention.
const SIInstrInfo * getInstrInfo() const override
unsigned getSrcAddressSpace() const
unsigned addWorkGroupIDY()
const GlobalValue * getGlobal() const
static unsigned getMOVRELDPseudo(const TargetRegisterClass *VecRC)
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space...
float BitsToFloat(uint32_t Bits)
BitsToFloat - This function takes a 32-bit integer and returns the bit equivalent float...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool hasWorkGroupIDZ() const
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Type * getTypeForEVT(LLVMContext &Context) const
getTypeForEVT - This method returns an LLVM type corresponding to the specified EVT.
unsigned getSizeInBits() const
bool isMemOpUniform(const SDNode *N) const
static bool bitOpWithConstantIsReducible(unsigned Opc, uint32_t Val)
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
unsigned getNumOperands() const
Return the number of values used by this operation.
static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue C, SDValue GlueChain)
const SDValue & getOperand(unsigned Num) const
bool isSGPRClass(const TargetRegisterClass *RC) const
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
Address space for local memory.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
iv Induction Variable Users
unsigned addPrivateMemoryPtr(const SIRegisterInfo &TRI)
bool hasWorkItemIDZ() const
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Turn load of vector type into a load of the individual elements.
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
const SDValue & getBasePtr() const
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
std::pair< SDValue, SDValue > split64BitValue(SDValue Op, SelectionDAG &DAG) const
Return 64-bit value Op as two 32-bit integers.
const AMDGPUImagePseudoSourceValue * getImagePSV() const
bool isAmdCodeObjectV2(const MachineFunction &MF) const
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS, uint32_t ValLo, uint32_t ValHi) const
Split the 64-bit value LHS into two 32-bit components, and perform the binary operation Opc to it wit...
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
bool isAllOnesValue() const
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
static bool isFlatGlobalAddrSpace(unsigned AS)
bool hasWorkGroupIDY() const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
const Triple & getTargetTriple() const
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors...
bool isVector() const
isVector - Return true if this is a vector value type.
void setPrivateSegmentWaveByteOffset(unsigned Reg)
#define FP_DENORM_FLUSH_NONE
void setDebuggerWorkGroupIDStackObjectIndex(unsigned Dim, int ObjectIdx)
Sets stack object index for Dim's work group ID to ObjectIdx.
unsigned getSize() const
Return the size of the register in bytes, which is also the size of a stack slot allocated to hold a ...
static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, SDLoc DL, EVT VT)
bool isNegative() const
Return true if the value is negative.
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
void setScratchRSrcReg(unsigned Reg)
static unsigned findFirstFreeSGPR(CCState &CCInfo)
const AMDGPUBufferPseudoSourceValue * getBufferPSV() const
A description of a memory reference used in the backend.
bool hasWorkGroupInfo() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
struct fuzzer::@269 Flags
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
int64_t getOffset() const
const HexagonInstrInfo * TII
Shift and rotation operations.
static bool isGather4(const MachineInstr &MI)
void setHasNonSpillStackObjects(bool StackObject=true)
unsigned addDispatchID(const SIRegisterInfo &TRI)
static bool isMIMG(const MachineInstr &MI)
void setDebuggerWorkItemIDStackObjectIndex(unsigned Dim, int ObjectIdx)
Sets stack object index for Dim's work item ID to ObjectIdx.
void setIfReturnsVoid(bool Value)
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
MachineFunction & getMachineFunction() const
unsigned getLDSSize() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
static unsigned SubIdx2Lane(unsigned Idx)
Helper function for adjustWritemask.
CopyToReg - This node has three operands: a chain, a register number to set to this value...
virtual SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
LLVM_ATTRIBUTE_ALWAYS_INLINE R Default(const T &Value) const
unsigned getAddressSpace() const
Reg
All possible values of the reg field in the ModR/M byte.
APInt bitcastToAPInt() const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
The memory access is dereferenceable (i.e., doesn't trap).
EVT getScalarType() const
getScalarType - If this is a vector type, return the element type, otherwise return this...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
This is an SDNode representing atomic operations.
bool getScalarizeGlobalBehavior() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
EVT getVectorElementType() const
getVectorElementType - Given a vector type, return the type of each element.
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
LLVM_ATTRIBUTE_ALWAYS_INLINE StringSwitch & Case(const char(&S)[N], const T &Value)
bool isShuffleMaskLegal(const SmallVectorImpl< int > &, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
unsigned getLocReg() const
Class to represent function types.
unsigned getPSInputAddr() const
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
const AMDGPUSubtarget * Subtarget
bool hasStackObjects() const
Return true if there are any stack objects in this function.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
value_iterator value_end() const
bool hasVGPRIndexMode() const
Simple integer binary arithmetic operators.
static MachineBasicBlock * emitIndirectSrc(MachineInstr &MI, MachineBasicBlock &MBB, const SISubtarget &ST)
bool hasWorkGroupIDX() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type...
static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc)
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
const SDValue & getBasePtr() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
cmpResult
IEEE-754R 5.11: Floating Point Comparison Relations.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
const APInt & getAPIntValue() const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
EVT getMemoryVT() const
Return the type of the in-memory value.
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred)
getFCmpCondCode - Return the ISD condition code corresponding to the given LLVM IR floating-point con...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Generation getGeneration() const
unsigned getUndefRegState(bool B)
void markPSInputAllocated(unsigned Index)
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const DataLayout & getDataLayout() const
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
const SIRegisterInfo & getRegisterInfo() const
Class to represent pointers.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
This class is used to represent ISD::STORE nodes.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Address space for region memory.
uint32_t FloatToBits(float Float)
FloatToBits - This function takes a float and returns the bit equivalent 32-bit integer.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
const MachineBasicBlock * getParent() const
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the specified, possibly variable...
bool isPSInputAllocated(unsigned Index) const
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const override
Helper function that adds Reg to the LiveIn list of the DAG's MachineFunction.
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
MinAlign - A and B are either alignments or offsets.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getStoreSize() const
getStoreSize - Return the number of bytes overwritten by a store of the specified value type...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
A switch()-like statement whose cases are string literals.
Type * getParamType(unsigned i) const
Parameter type accessors.
initializer< Ty > init(const Ty &Val)
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
Control flow instructions. These all have token chains.
const SDValue & getBasePtr() const
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors...
constexpr bool isUInt< 8 >(uint64_t x)
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
unsigned getVectorNumElements() const
bool hasFloatingPointExceptions() const
Return true if target supports floating point exceptions.
MVT - Machine Value Type.
bool isShader(CallingConv::ID cc)
unsigned addWorkGroupInfo()
const SDValue & getOperand(unsigned i) const
The instances of the Type class are immutable: once they are created, they are never changed...
bool isCompareAndSwap() const
Returns true if this SDNode represents cmpxchg atomic operation, false otherwise. ...
This is an important class for using LLVM in a threaded context.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Address space for constant memory (VTX2)
Simple binary floating point operators.
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
unsigned getPreloadedValue(const MachineFunction &MF, enum PreloadedValue Value) const
Returns the physical register that Value is stored in.
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true, unsigned Size=0)
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
bool sge(const APInt &RHS) const
Signed greather or equal comparison.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Address space for private memory.
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
bool isVector() const
isVector - Return true if this is a vector value type.
static SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, SDValue Op0, SDValue Op1)
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
const MachineOperand & getOperand(unsigned i) const
static MachineBasicBlock * emitIndirectDst(MachineInstr &MI, MachineBasicBlock &MBB, const SISubtarget &ST)
unsigned getLiveInVirtReg(unsigned PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
Returns the target specific optimal type for load and store operations as a result of memset...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
bool hasUnalignedScratchAccess() const
SI DAG Lowering interface definition.
bool hasDispatchPtr() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
This class provides iterator support for SDUse operands that use a specific SDNode.
SITargetLowering(const TargetMachine &tm, const SISubtarget &STI)
bool hasKernargSegmentPtr() const
bool hasAllowReciprocal() const
bool isBeforeLegalize() const
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
unsigned addQueuePtr(const SIRegisterInfo &TRI)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool hasWorkItemIDX() const
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
unsigned getOpcode() const
TRAP - Trapping instruction.
bool hasFP32Denormals() const
Value * getOperand(unsigned i) const
uint64_t getDefaultRsrcDataFormat() const
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
self_iterator getIterator()
The memory access is non-temporal.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
static std::pair< unsigned, int > computeIndirectRegAndOffset(const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, unsigned VecReg, int Offset)
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
Address space for flat memory.
const SDValue & getValue() const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
bool has16BitInsts() const
static void r1(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
static SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, SDValue Op0, SDValue Op1, bool Signed)
Bit counting operators with an undefined result for zero inputs.
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
unsigned getSubReg() const
EVT - Extended Value Type.
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
const APFloat & getValueAPF() const
void setScratchWaveOffsetReg(unsigned Reg)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
getVectorVT - Returns the EVT that represents a vector NumElements in length, where each element is o...
This class contains a discriminated union of information about pointers in memory operands...
uint64_t getConstantOperandVal(unsigned Num) const
Helper method returns the integer value of a ConstantSDNode operand.
Calling convention used for Mesa pixel shaders.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasFP64Denormals() const
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
unsigned addDispatchPtr(const SIRegisterInfo &TRI)
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, unsigned Alignment=0, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands...
Triple - Helper class for working with autoconf configuration names.
The memory access writes data.
bool isInlineConstant(const APInt &Imm) const
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineInstr &MI, int Offset, bool UseGPRIdxMode, bool IsIndirectSrc)
SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const
Split a vector store into 2 stores of half the vector.
TokenFactor - This node takes multiple tokens as input and produces a single token result...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
bool memoperands_empty() const
Return true if we don't have any memory operands which described the the memory access done by this i...
Iterator for intrusive lists based on ilist_node.
CCState - This class holds information needed while lowering arguments and return values...
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const DebugLoc & getDebugLoc() const
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const override
Return the preferred vector type legalization action.
Returns platform specific canonical encoding of a floating point number.
static bool isKnownNeverSNan(SelectionDAG &DAG, SDValue Op)
SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const
Split a vector load into 2 loads of half the vector.
bool isInfinity() const
Return true if the value is an infinity.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
const SIRegisterInfo * getRegisterInfo() const override
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
ADDRSPACECAST - This operator converts between pointers of different address spaces.
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Type * getType() const
All values are typed, get the type of this value.
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
CCValAssign - Represent assignment of one arg/retval to a location.
BRCOND - Conditional branch.
An SDNode that represents everything that will be needed to construct a MachineInstr.
const SDValue & getChain() const
Byte Swap and Counting operators.
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
static SDValue getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue GlueChain)
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
const fltSemantics & getFltSemantics() const
static SDValue buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV, SDLoc DL, unsigned Offset, EVT PtrVT, unsigned GAFlags=SIInstrInfo::MO_NONE)
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array...
static bool canFoldOffset(unsigned OffsetSize, unsigned AS, const SISubtarget &STI)
Return true if the given offset Size in bytes can be folded into the immediate offsets of a memory in...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static SDNode * findUser(SDValue Value, unsigned Opcode)
Helper function for LowerBRCOND.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
const Value * getValue() const
Return the base address of the memory access.
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
Select(COND, TRUEVAL, FALSEVAL).
Interface for the AMDGPU Implementation of the Intrinsic Info class.
int64_t getSExtValue() const
op_iterator op_begin() const
static use_iterator use_end()
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
ZERO_EXTEND - Used for integer types, zeroing the new bits.
AddrMode
ARM Addressing Modes.
unsigned getVectorNumElements() const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *IsFast) const override
Determine if the target supports unaligned memory accesses.
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
static bool isVOP3(const MachineInstr &MI)
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
Flags
Flags values. These may be or'd together.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
unsigned addFlatScratchInit(const SIRegisterInfo &TRI)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
const SISubtarget * getSubtarget() const
Representation of each machine instruction.
These are IR-level optimization flags that may be propagated to SDNodes.
PointerType * getType() const
Global values are always pointers.
static SDValue buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL, uint64_t Val)
unsigned PartOffset
Offset in bytes of current output value relative to the beginning of original argument.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Interface definition for SIInstrInfo.
void AnalyzeReturn(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs) const
Bitwise operators - logical and, logical or, logical xor.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
unsigned getMaxPrivateElementSize() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Modify anything using 'From' to use 'To' instead.
static cl::opt< bool > EnableVGPRIndexMode("amdgpu-vgpr-index-mode", cl::desc("Use GPR indexing mode instead of movrel for vector indexing"), cl::init(false))
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
FunctionType * getFunctionType() const
Returns the FunctionType for me.
The memory access always returns the same value (or traps).
bool isAllocated(unsigned Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
op_iterator op_end() const
unsigned getExplicitKernelArgOffset(const MachineFunction &MF) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument...
bool shouldEmitConstantsToTextSection(const Triple &TT)
void analyzeFormalArgumentsCompute(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins) const
The SelectionDAGBuilder will automatically promote function arguments with illegal types...
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
bool hasUnsafeAlgebra() const
unsigned addWorkGroupIDZ()
static void r0(uint32_t &A, uint32_t &B, uint32_t &C, uint32_t &D, uint32_t &E, int I, uint32_t *Buf)
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
constexpr bool isUInt< 16 >(uint64_t x)
void setSimpleHint(unsigned VReg, unsigned PrefReg)
Specify the preferred register allocation hint for the specified virtual register.
EVT getValueType() const
Return the ValueType of the referenced return value.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getCondCode(ISD::CondCode Cond)
static bool isFrameIndexOp(SDValue Op)
void setUnsafeAlgebra(bool b)
static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI, unsigned InitResultReg, unsigned PhiReg, int Offset, bool UseGPRIdxMode)
bool hasWorkItemIDY() const
void setABIArgOffset(unsigned NewOffset)
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
unsigned getReg() const
getReg - Returns the register number.
unsigned addPrivateSegmentWaveByteOffset()
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void insert(iterator MBBI, MachineBasicBlock *MBB)
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
bool isSimple() const
isSimple - Test if the given EVT is simple (as opposed to being extended).
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array...
constexpr uint32_t Hi_32(uint64_t Value)
Hi_32 - This function returns the high 32 bits of a 64 bit value.
Module * getParent()
Get the module that this global value is contained inside of...
LLVM Value Representation.
FMA - Perform a * b + c with no intermediate rounding step.
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
SDValue getRegister(unsigned Reg, EVT VT)
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
EVT changeTypeToInteger()
Return the type converted to an equivalently sized integer or vector with integer element type...
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
SDValue getValueType(EVT)
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
const TargetLowering & getTargetLoweringInfo() const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.Val alone...
cmpResult compare(const APFloat &RHS) const
Primary interface to the complete machine description for the target machine.
bool hasPrivateMemoryInputPtr() const
void setRegClass(unsigned Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
StringRef - Represent a constant reference to a string, i.e.
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
SetCC operator - This evaluates to a true value iff the condition is true.
uint32_t getImplicitParameterOffset(const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const
Helper function that returns the byte offset of the given type of implicit parameter.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
bool hasFP16Denormals() const
unsigned getLocMemOffset() const
MVT getVectorElementType() const
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
TRUNCATE - Completely drop the high bits.
static void Split(std::vector< std::string > &V, StringRef S)
Split - Splits a string of comma separated items in to a vector of strings.
unsigned getAlignment() const
unsigned AllocateReg(unsigned Reg)
AllocateReg - Attempt to allocate one register.
unsigned addWorkGroupIDX()
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary floating point operations.
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
static IntegerType * getInt8Ty(LLVMContext &C)
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
const fltSemantics & getSemantics() const
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself...
MVT getSimpleVT() const
getSimpleVT - Return the SimpleValueType held in the specified simple EVT.
const SDNodeFlags * getFlags() const
This could be defined as a virtual function and implemented more simply and directly, but it is not to avoid creating a vtable for this class.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode...
static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(const SIInstrInfo *TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, const DebugLoc &DL, const MachineOperand &IdxReg, unsigned InitReg, unsigned ResultReg, unsigned PhiReg, unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode)
unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const override
Return the register ID of the name passed in.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
bool hasPrivateSegmentWaveByteOffset() const
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
bool hasPrivateSegmentBuffer() const
Address space for global memory (RAT0, VTX0).
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
uint64_t getZExtValue() const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
unsigned getVectorNumElements() const
getVectorNumElements - Given a vector type, return the number of elements it contains.
This class is used to represent ISD::LOAD nodes.