LLVM  4.0.0
X86Operand.h
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1 //===-- X86Operand.h - Parsed X86 machine instruction --------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
11 #define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
12 
13 #include "X86AsmParserCommon.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
18 #include "llvm/ADT/STLExtras.h"
20 
21 namespace llvm {
22 
23 /// X86Operand - Instances of this class represent a parsed X86 machine
24 /// instruction.
25 struct X86Operand : public MCParsedAsmOperand {
26  enum KindTy {
31  } Kind;
32 
36  void *OpDecl;
37  bool AddressOf;
38 
39  struct TokOp {
40  const char *Data;
41  unsigned Length;
42  };
43 
44  struct RegOp {
45  unsigned RegNo;
46  };
47 
48  struct ImmOp {
49  const MCExpr *Val;
50  };
51 
52  struct MemOp {
53  unsigned SegReg;
54  const MCExpr *Disp;
55  unsigned BaseReg;
56  unsigned IndexReg;
57  unsigned Scale;
58  unsigned Size;
59  unsigned ModeSize;
60  };
61 
62  union {
63  struct TokOp Tok;
64  struct RegOp Reg;
65  struct ImmOp Imm;
66  struct MemOp Mem;
67  };
68 
70  : Kind(K), StartLoc(Start), EndLoc(End) {}
71 
72  StringRef getSymName() override { return SymName; }
73  void *getOpDecl() override { return OpDecl; }
74 
75  /// getStartLoc - Get the location of the first token of this operand.
76  SMLoc getStartLoc() const override { return StartLoc; }
77  /// getEndLoc - Get the location of the last token of this operand.
78  SMLoc getEndLoc() const override { return EndLoc; }
79  /// getLocRange - Get the range between the first and last token of this
80  /// operand.
81  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
82  /// getOffsetOfLoc - Get the location of the offset operator.
83  SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
84 
85  void print(raw_ostream &OS) const override {}
86 
87  StringRef getToken() const {
88  assert(Kind == Token && "Invalid access!");
89  return StringRef(Tok.Data, Tok.Length);
90  }
92  assert(Kind == Token && "Invalid access!");
93  Tok.Data = Value.data();
94  Tok.Length = Value.size();
95  }
96 
97  unsigned getReg() const override {
98  assert(Kind == Register && "Invalid access!");
99  return Reg.RegNo;
100  }
101 
102  const MCExpr *getImm() const {
103  assert(Kind == Immediate && "Invalid access!");
104  return Imm.Val;
105  }
106 
107  const MCExpr *getMemDisp() const {
108  assert(Kind == Memory && "Invalid access!");
109  return Mem.Disp;
110  }
111  unsigned getMemSegReg() const {
112  assert(Kind == Memory && "Invalid access!");
113  return Mem.SegReg;
114  }
115  unsigned getMemBaseReg() const {
116  assert(Kind == Memory && "Invalid access!");
117  return Mem.BaseReg;
118  }
119  unsigned getMemIndexReg() const {
120  assert(Kind == Memory && "Invalid access!");
121  return Mem.IndexReg;
122  }
123  unsigned getMemScale() const {
124  assert(Kind == Memory && "Invalid access!");
125  return Mem.Scale;
126  }
127  unsigned getMemModeSize() const {
128  assert(Kind == Memory && "Invalid access!");
129  return Mem.ModeSize;
130  }
131 
132  bool isToken() const override {return Kind == Token; }
133 
134  bool isImm() const override { return Kind == Immediate; }
135 
136  bool isImmSExti16i8() const {
137  if (!isImm())
138  return false;
139 
140  // If this isn't a constant expr, just assume it fits and let relaxation
141  // handle it.
143  if (!CE)
144  return true;
145 
146  // Otherwise, check the value is in a range that makes sense for this
147  // extension.
148  return isImmSExti16i8Value(CE->getValue());
149  }
150  bool isImmSExti32i8() const {
151  if (!isImm())
152  return false;
153 
154  // If this isn't a constant expr, just assume it fits and let relaxation
155  // handle it.
157  if (!CE)
158  return true;
159 
160  // Otherwise, check the value is in a range that makes sense for this
161  // extension.
162  return isImmSExti32i8Value(CE->getValue());
163  }
164  bool isImmSExti64i8() const {
165  if (!isImm())
166  return false;
167 
168  // If this isn't a constant expr, just assume it fits and let relaxation
169  // handle it.
171  if (!CE)
172  return true;
173 
174  // Otherwise, check the value is in a range that makes sense for this
175  // extension.
176  return isImmSExti64i8Value(CE->getValue());
177  }
178  bool isImmSExti64i32() const {
179  if (!isImm())
180  return false;
181 
182  // If this isn't a constant expr, just assume it fits and let relaxation
183  // handle it.
185  if (!CE)
186  return true;
187 
188  // Otherwise, check the value is in a range that makes sense for this
189  // extension.
190  return isImmSExti64i32Value(CE->getValue());
191  }
192 
193  bool isImmUnsignedi8() const {
194  if (!isImm()) return false;
195  // If this isn't a constant expr, just assume it fits and let relaxation
196  // handle it.
198  if (!CE) return true;
199  return isImmUnsignedi8Value(CE->getValue());
200  }
201 
202  bool isOffsetOf() const override {
203  return OffsetOfLoc.getPointer();
204  }
205 
206  bool needAddressOf() const override {
207  return AddressOf;
208  }
209 
210  bool isMem() const override { return Kind == Memory; }
211  bool isMemUnsized() const {
212  return Kind == Memory && Mem.Size == 0;
213  }
214  bool isMem8() const {
215  return Kind == Memory && (!Mem.Size || Mem.Size == 8);
216  }
217  bool isMem16() const {
218  return Kind == Memory && (!Mem.Size || Mem.Size == 16);
219  }
220  bool isMem32() const {
221  return Kind == Memory && (!Mem.Size || Mem.Size == 32);
222  }
223  bool isMem64() const {
224  return Kind == Memory && (!Mem.Size || Mem.Size == 64);
225  }
226  bool isMem80() const {
227  return Kind == Memory && (!Mem.Size || Mem.Size == 80);
228  }
229  bool isMem128() const {
230  return Kind == Memory && (!Mem.Size || Mem.Size == 128);
231  }
232  bool isMem256() const {
233  return Kind == Memory && (!Mem.Size || Mem.Size == 256);
234  }
235  bool isMem512() const {
236  return Kind == Memory && (!Mem.Size || Mem.Size == 512);
237  }
238  bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
239  assert(Kind == Memory && "Invalid access!");
240  return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
241  }
242 
243  bool isMem64_RC128() const {
244  return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
245  }
246  bool isMem128_RC128() const {
247  return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15);
248  }
249  bool isMem128_RC256() const {
250  return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM15);
251  }
252  bool isMem256_RC128() const {
253  return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15);
254  }
255  bool isMem256_RC256() const {
256  return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM15);
257  }
258 
259  bool isMem64_RC128X() const {
260  return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31);
261  }
262  bool isMem128_RC128X() const {
263  return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31);
264  }
265  bool isMem128_RC256X() const {
266  return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM31);
267  }
268  bool isMem256_RC128X() const {
269  return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31);
270  }
271  bool isMem256_RC256X() const {
272  return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM31);
273  }
274  bool isMem512_RC256X() const {
275  return isMem512() && isMemIndexReg(X86::YMM0, X86::YMM31);
276  }
277  bool isMem512_RC512() const {
278  return isMem512() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
279  }
280 
281  bool isAbsMem() const {
282  return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
283  !getMemIndexReg() && getMemScale() == 1;
284  }
285  bool isAVX512RC() const{
286  return isImm();
287  }
288 
289  bool isAbsMem16() const {
290  return isAbsMem() && Mem.ModeSize == 16;
291  }
292 
293  bool isSrcIdx() const {
294  return !getMemIndexReg() && getMemScale() == 1 &&
295  (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
296  getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
297  cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
298  }
299  bool isSrcIdx8() const {
300  return isMem8() && isSrcIdx();
301  }
302  bool isSrcIdx16() const {
303  return isMem16() && isSrcIdx();
304  }
305  bool isSrcIdx32() const {
306  return isMem32() && isSrcIdx();
307  }
308  bool isSrcIdx64() const {
309  return isMem64() && isSrcIdx();
310  }
311 
312  bool isDstIdx() const {
313  return !getMemIndexReg() && getMemScale() == 1 &&
314  (getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
315  (getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
316  getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
317  cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
318  }
319  bool isDstIdx8() const {
320  return isMem8() && isDstIdx();
321  }
322  bool isDstIdx16() const {
323  return isMem16() && isDstIdx();
324  }
325  bool isDstIdx32() const {
326  return isMem32() && isDstIdx();
327  }
328  bool isDstIdx64() const {
329  return isMem64() && isDstIdx();
330  }
331 
332  bool isMemOffs() const {
333  return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
334  getMemScale() == 1;
335  }
336 
337  bool isMemOffs16_8() const {
338  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
339  }
340  bool isMemOffs16_16() const {
341  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
342  }
343  bool isMemOffs16_32() const {
344  return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
345  }
346  bool isMemOffs32_8() const {
347  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
348  }
349  bool isMemOffs32_16() const {
350  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
351  }
352  bool isMemOffs32_32() const {
353  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
354  }
355  bool isMemOffs32_64() const {
356  return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
357  }
358  bool isMemOffs64_8() const {
359  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
360  }
361  bool isMemOffs64_16() const {
362  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
363  }
364  bool isMemOffs64_32() const {
365  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
366  }
367  bool isMemOffs64_64() const {
368  return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
369  }
370 
371  bool isReg() const override { return Kind == Register; }
372 
373  bool isGR32orGR64() const {
374  return Kind == Register &&
375  (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
376  X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
377  }
378 
379  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
380  // Add as immediates when possible.
381  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
382  Inst.addOperand(MCOperand::createImm(CE->getValue()));
383  else
384  Inst.addOperand(MCOperand::createExpr(Expr));
385  }
386 
387  void addRegOperands(MCInst &Inst, unsigned N) const {
388  assert(N == 1 && "Invalid number of operands!");
390  }
391 
392  static unsigned getGR32FromGR64(unsigned RegNo) {
393  switch (RegNo) {
394  default: llvm_unreachable("Unexpected register");
395  case X86::RAX: return X86::EAX;
396  case X86::RCX: return X86::ECX;
397  case X86::RDX: return X86::EDX;
398  case X86::RBX: return X86::EBX;
399  case X86::RBP: return X86::EBP;
400  case X86::RSP: return X86::ESP;
401  case X86::RSI: return X86::ESI;
402  case X86::RDI: return X86::EDI;
403  case X86::R8: return X86::R8D;
404  case X86::R9: return X86::R9D;
405  case X86::R10: return X86::R10D;
406  case X86::R11: return X86::R11D;
407  case X86::R12: return X86::R12D;
408  case X86::R13: return X86::R13D;
409  case X86::R14: return X86::R14D;
410  case X86::R15: return X86::R15D;
411  case X86::RIP: return X86::EIP;
412  }
413  }
414 
415  void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
416  assert(N == 1 && "Invalid number of operands!");
417  unsigned RegNo = getReg();
418  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
419  RegNo = getGR32FromGR64(RegNo);
420  Inst.addOperand(MCOperand::createReg(RegNo));
421  }
422  void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
423  assert(N == 1 && "Invalid number of operands!");
424  addExpr(Inst, getImm());
425  }
426  void addImmOperands(MCInst &Inst, unsigned N) const {
427  assert(N == 1 && "Invalid number of operands!");
428  addExpr(Inst, getImm());
429  }
430 
431  void addMemOperands(MCInst &Inst, unsigned N) const {
432  assert((N == 5) && "Invalid number of operands!");
436  addExpr(Inst, getMemDisp());
438  }
439 
440  void addAbsMemOperands(MCInst &Inst, unsigned N) const {
441  assert((N == 1) && "Invalid number of operands!");
442  // Add as immediates when possible.
443  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
444  Inst.addOperand(MCOperand::createImm(CE->getValue()));
445  else
447  }
448 
449  void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
450  assert((N == 2) && "Invalid number of operands!");
453  }
454  void addDstIdxOperands(MCInst &Inst, unsigned N) const {
455  assert((N == 1) && "Invalid number of operands!");
457  }
458 
459  void addMemOffsOperands(MCInst &Inst, unsigned N) const {
460  assert((N == 2) && "Invalid number of operands!");
461  // Add as immediates when possible.
462  if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
463  Inst.addOperand(MCOperand::createImm(CE->getValue()));
464  else
467  }
468 
469  static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
471  auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
472  Res->Tok.Data = Str.data();
473  Res->Tok.Length = Str.size();
474  return Res;
475  }
476 
477  static std::unique_ptr<X86Operand>
478  CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
479  bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
480  StringRef SymName = StringRef(), void *OpDecl = nullptr) {
481  auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
482  Res->Reg.RegNo = RegNo;
483  Res->AddressOf = AddressOf;
484  Res->OffsetOfLoc = OffsetOfLoc;
485  Res->SymName = SymName;
486  Res->OpDecl = OpDecl;
487  return Res;
488  }
489 
490  static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
491  SMLoc StartLoc, SMLoc EndLoc) {
492  auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
493  Res->Imm.Val = Val;
494  return Res;
495  }
496 
497  /// Create an absolute memory operand.
498  static std::unique_ptr<X86Operand>
499  CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
500  unsigned Size = 0, StringRef SymName = StringRef(),
501  void *OpDecl = nullptr) {
502  auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
503  Res->Mem.SegReg = 0;
504  Res->Mem.Disp = Disp;
505  Res->Mem.BaseReg = 0;
506  Res->Mem.IndexReg = 0;
507  Res->Mem.Scale = 1;
508  Res->Mem.Size = Size;
509  Res->Mem.ModeSize = ModeSize;
510  Res->SymName = SymName;
511  Res->OpDecl = OpDecl;
512  Res->AddressOf = false;
513  return Res;
514  }
515 
516  /// Create a generalized memory operand.
517  static std::unique_ptr<X86Operand>
518  CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
519  unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
520  SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(),
521  void *OpDecl = nullptr) {
522  // We should never just have a displacement, that should be parsed as an
523  // absolute memory operand.
524  assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
525 
526  // The scale should always be one of {1,2,4,8}.
527  assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
528  "Invalid scale!");
529  auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
530  Res->Mem.SegReg = SegReg;
531  Res->Mem.Disp = Disp;
532  Res->Mem.BaseReg = BaseReg;
533  Res->Mem.IndexReg = IndexReg;
534  Res->Mem.Scale = Scale;
535  Res->Mem.Size = Size;
536  Res->Mem.ModeSize = ModeSize;
537  Res->SymName = SymName;
538  Res->OpDecl = OpDecl;
539  Res->AddressOf = false;
540  return Res;
541  }
542 };
543 
544 } // End of namespace llvm
545 
546 #endif
void addImmOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:426
StringRef getToken() const
Definition: X86Operand.h:87
bool isMemOffs64_16() const
Definition: X86Operand.h:361
Represents a range in source code.
Definition: SMLoc.h:49
const MCExpr * Val
Definition: X86Operand.h:49
const char * getPointer() const
Definition: SMLoc.h:35
bool isDstIdx8() const
Definition: X86Operand.h:319
SMLoc getOffsetOfLoc() const override
getOffsetOfLoc - Get the location of the offset operator.
Definition: X86Operand.h:83
bool isMem128_RC128X() const
Definition: X86Operand.h:262
bool isMemOffs64_32() const
Definition: X86Operand.h:364
bool isImmUnsignedi8Value(uint64_t Value)
bool isMem512_RC512() const
Definition: X86Operand.h:277
void addAVX512RCOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:422
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
bool isDstIdx32() const
Definition: X86Operand.h:325
This class provides various memory handling functions that manipulate MemoryBlock instances...
Definition: Memory.h:46
struct ImmOp Imm
Definition: X86Operand.h:65
bool isMemOffs16_32() const
Definition: X86Operand.h:343
bool isMem256_RC256() const
Definition: X86Operand.h:255
bool isSrcIdx32() const
Definition: X86Operand.h:305
unsigned getMemModeSize() const
Definition: X86Operand.h:127
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr)
Create an absolute memory operand.
Definition: X86Operand.h:499
bool isAVX512RC() const
Definition: X86Operand.h:285
bool isMem128() const
Definition: X86Operand.h:229
bool isMemOffs64_64() const
Definition: X86Operand.h:367
bool isMem256_RC128X() const
Definition: X86Operand.h:268
unsigned getMemScale() const
Definition: X86Operand.h:123
return AArch64::GPR64RegClass contains(Reg)
bool isImmSExti64i32() const
Definition: X86Operand.h:178
bool isSrcIdx16() const
Definition: X86Operand.h:302
bool isMem16() const
Definition: X86Operand.h:217
bool isMem512_RC256X() const
Definition: X86Operand.h:274
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
bool isImmSExti64i8Value(uint64_t Value)
SMLoc getEndLoc() const override
getEndLoc - Get the location of the last token of this operand.
Definition: X86Operand.h:78
bool isMem8() const
Definition: X86Operand.h:214
bool isImm() const override
isImm - Is this an immediate operand?
Definition: X86Operand.h:134
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
const MCExpr * getImm() const
Definition: X86Operand.h:102
void addMemOffsOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:459
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
static std::unique_ptr< X86Operand > CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc)
Definition: X86Operand.h:490
bool isMem128_RC256X() const
Definition: X86Operand.h:265
StringRef getSymName() override
Definition: X86Operand.h:72
bool isImmSExti64i32Value(uint64_t Value)
unsigned getReg() const override
Definition: X86Operand.h:97
bool isMemOffs16_16() const
Definition: X86Operand.h:340
bool isMemOffs64_8() const
Definition: X86Operand.h:358
bool isMem80() const
Definition: X86Operand.h:226
bool isImmSExti16i8Value(uint64_t Value)
bool isMemOffs32_8() const
Definition: X86Operand.h:346
bool isDstIdx64() const
Definition: X86Operand.h:328
const MCExpr * getMemDisp() const
Definition: X86Operand.h:107
bool isMem64_RC128() const
Definition: X86Operand.h:243
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Definition: StringRef.h:135
bool isAbsMem() const
Definition: X86Operand.h:281
bool isMem64() const
Definition: X86Operand.h:223
bool isMem256() const
Definition: X86Operand.h:232
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
struct TokOp Tok
Definition: X86Operand.h:63
bool isMem32() const
Definition: X86Operand.h:220
bool isImmSExti32i8() const
Definition: X86Operand.h:150
X86Operand - Instances of this class represent a parsed X86 machine instruction.
Definition: X86Operand.h:25
SMRange getLocRange() const
getLocRange - Get the range between the first and last token of this operand.
Definition: X86Operand.h:81
int64_t getValue() const
Definition: MCExpr.h:147
bool isMem128_RC256() const
Definition: X86Operand.h:249
bool isImmUnsignedi8() const
Definition: X86Operand.h:193
static const unsigned End
static std::unique_ptr< X86Operand > CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc, SMLoc EndLoc, unsigned Size=0, StringRef SymName=StringRef(), void *OpDecl=nullptr)
Create a generalized memory operand.
Definition: X86Operand.h:518
void setTokenValue(StringRef Value)
Definition: X86Operand.h:91
bool isToken() const override
isToken - Is this a token operand?
Definition: X86Operand.h:132
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
SMLoc getStartLoc() const override
getStartLoc - Get the location of the first token of this operand.
Definition: X86Operand.h:76
bool isMem64_RC128X() const
Definition: X86Operand.h:259
unsigned getMemSegReg() const
Definition: X86Operand.h:111
void addGR32orGR64Operands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:415
StringRef SymName
Definition: X86Operand.h:35
bool isMemOffs32_16() const
Definition: X86Operand.h:349
void * getOpDecl() override
Definition: X86Operand.h:73
bool isMemOffs32_64() const
Definition: X86Operand.h:355
void addRegOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:387
struct MemOp Mem
Definition: X86Operand.h:66
bool isMem128_RC128() const
Definition: X86Operand.h:246
bool isSrcIdx64() const
Definition: X86Operand.h:308
bool isOffsetOf() const override
isOffsetOf - Do we need to emit code to get the offset of the variable, rather then the value of the ...
Definition: X86Operand.h:202
bool isMem256_RC256X() const
Definition: X86Operand.h:271
bool isMemUnsized() const
Definition: X86Operand.h:211
bool isMemOffs16_8() const
Definition: X86Operand.h:337
static unsigned getGR32FromGR64(unsigned RegNo)
Definition: X86Operand.h:392
bool isImmSExti16i8() const
Definition: X86Operand.h:136
void print(raw_ostream &OS) const override
print - Print a debug representation of the operand to the given stream.
Definition: X86Operand.h:85
unsigned getMemBaseReg() const
Definition: X86Operand.h:115
static std::unique_ptr< X86Operand > CreateToken(StringRef Str, SMLoc Loc)
Definition: X86Operand.h:469
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:37
static std::unique_ptr< X86Operand > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, bool AddressOf=false, SMLoc OffsetOfLoc=SMLoc(), StringRef SymName=StringRef(), void *OpDecl=nullptr)
Definition: X86Operand.h:478
struct RegOp Reg
Definition: X86Operand.h:64
bool isImmSExti64i8() const
Definition: X86Operand.h:164
X86Operand(KindTy K, SMLoc Start, SMLoc End)
Definition: X86Operand.h:69
bool isDstIdx16() const
Definition: X86Operand.h:322
bool isMemIndexReg(unsigned LowR, unsigned HighR) const
Definition: X86Operand.h:238
bool isDstIdx() const
Definition: X86Operand.h:312
#define N
bool isMem512() const
Definition: X86Operand.h:235
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:287
bool isMem256_RC128() const
Definition: X86Operand.h:252
bool isSrcIdx8() const
Definition: X86Operand.h:299
bool isGR32orGR64() const
Definition: X86Operand.h:373
void addAbsMemOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:440
bool isMemOffs() const
Definition: X86Operand.h:332
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:71
bool isImmSExti32i8Value(uint64_t Value)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:125
void addMemOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:431
bool isReg() const override
isReg - Is this a register operand?
Definition: X86Operand.h:371
bool isAbsMem16() const
Definition: X86Operand.h:289
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
void addSrcIdxOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:449
const MCExpr * Disp
Definition: X86Operand.h:54
enum llvm::X86Operand::KindTy Kind
void addExpr(MCInst &Inst, const MCExpr *Expr) const
Definition: X86Operand.h:379
bool isSrcIdx() const
Definition: X86Operand.h:293
Represents a location in source code.
Definition: SMLoc.h:24
bool isMemOffs32_32() const
Definition: X86Operand.h:352
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:117
void addDstIdxOperands(MCInst &Inst, unsigned N) const
Definition: X86Operand.h:454
unsigned getMemIndexReg() const
Definition: X86Operand.h:119
bool isMem() const override
isMem - Is this a memory operand?
Definition: X86Operand.h:210
bool needAddressOf() const override
needAddressOf - Do we need to emit code to get the address of the variable/label? Only valid when par...
Definition: X86Operand.h:206