LLVM  4.0.0
AArch64RegisterBankInfo.h
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1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file declares the targeting of the RegisterBankInfo class for AArch64.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
16 
18 
19 namespace llvm {
20 
21 class TargetRegisterInfo;
22 
23 namespace AArch64 {
24 enum {
25  GPRRegBankID = 0, /// General Purpose Registers: W, X.
26  FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.
27  CCRRegBankID = 2, /// Conditional register: NZCV.
29 };
30 
34 } // End AArch64 namespace.
35 
36 /// This class provides the information for the target register banks.
38  /// See RegisterBankInfo::applyMapping.
39  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
40 
41  /// Get an instruction mapping where all the operands map to
42  /// the same register bank and have similar size.
43  ///
44  /// \pre MI.getNumOperands() <= 3
45  ///
46  /// \return An InstructionMappings with a statically allocated
47  /// OperandsMapping.
48  static InstructionMapping
49  getSameKindOfOperandsMapping(const MachineInstr &MI);
50 
51 public:
53 
54  unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
55  unsigned Size) const override;
56 
57  const RegisterBank &
58  getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
59 
61  getInstrAlternativeMappings(const MachineInstr &MI) const override;
62 
63  InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
64 };
65 } // End llvm namespace.
66 #endif
RegisterBank FPRRegBank
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Holds all the information related to register banks.
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
InstructionMapping getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
Conditional register: NZCV.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:843
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
This class implements the register bank concept.
Definition: RegisterBank.h:29
RegisterBank GPRRegBank
Representation of each machine instruction.
Definition: MachineInstr.h:52
This class provides the information for the target register banks.
Floating Point/Vector Registers: B, H, S, D, Q.
RegisterBank CCRRegBank
General Purpose Registers: W, X.
IRTranslator LLVM IR MI
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC) const override
Get a register bank that covers RC.
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")