LLVM  4.0.0
ARMInstructionSelector.cpp
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1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the targeting of the InstructionSelector class for ARM.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMInstructionSelector.h"
15 #include "ARMRegisterBankInfo.h"
16 #include "ARMSubtarget.h"
17 #include "ARMTargetMachine.h"
19 #include "llvm/Support/Debug.h"
20 
21 #define DEBUG_TYPE "arm-isel"
22 
23 using namespace llvm;
24 
25 #ifndef LLVM_BUILD_GLOBAL_ISEL
26 #error "You shouldn't build this"
27 #endif
28 
30  const ARMRegisterBankInfo &RBI)
31  : InstructionSelector(), TII(*STI.getInstrInfo()),
32  TRI(*STI.getRegisterInfo()), RBI(RBI) {}
33 
36  const RegisterBankInfo &RBI) {
37  unsigned DstReg = I.getOperand(0).getReg();
39  return true;
40 
41  const RegisterBank *RegBank = RBI.getRegBank(DstReg, MRI, TRI);
42  (void)RegBank;
43  assert(RegBank && "Can't get reg bank for virtual register");
44 
45  const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
46  (void)DstSize;
47  unsigned SrcReg = I.getOperand(1).getReg();
48  const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
49  (void)SrcSize;
50  assert((DstSize == SrcSize ||
51  // Copies are a means to setup initial types, the number of
52  // bits may not exactly match.
54  DstSize <= SrcSize)) &&
55  "Copy with different width?!");
56 
57  assert(RegBank->getID() == ARM::GPRRegBankID && "Unsupported reg bank");
58  const TargetRegisterClass *RC = &ARM::GPRRegClass;
59 
60  // No need to constrain SrcReg. It will get constrained when
61  // we hit another of its uses or its defs.
62  // Copies do not have constraints.
63  if (!RBI.constrainGenericRegister(DstReg, *RC, MRI)) {
64  DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
65  << " operand\n");
66  return false;
67  }
68  return true;
69 }
70 
72  assert(I.getParent() && "Instruction should be in a basic block!");
73  assert(I.getParent()->getParent() && "Instruction should be in a function!");
74 
75  auto &MBB = *I.getParent();
76  auto &MF = *MBB.getParent();
77  auto &MRI = MF.getRegInfo();
78 
80  if (I.isCopy())
81  return selectCopy(I, TII, MRI, TRI, RBI);
82 
83  return true;
84  }
85 
86  MachineInstrBuilder MIB{MF, I};
87 
88  using namespace TargetOpcode;
89  switch (I.getOpcode()) {
90  case G_ADD:
91  I.setDesc(TII.get(ARM::ADDrr));
93  break;
94  case G_FRAME_INDEX:
95  // Add 0 to the given frame index and hope it will eventually be folded into
96  // the user(s).
97  I.setDesc(TII.get(ARM::ADDri));
98  AddDefaultCC(AddDefaultPred(MIB.addImm(0)));
99  break;
100  case G_LOAD:
101  I.setDesc(TII.get(ARM::LDRi12));
102  AddDefaultPred(MIB.addImm(0));
103  break;
104  default:
105  return false;
106  }
107 
108  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
109 }
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
LLT getType(unsigned VReg) const
Get the low-level type of VReg or LLT{} if VReg is not a generic (target independent) virtual registe...
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Holds all the information related to register banks.
static const MachineInstrBuilder & AddDefaultPred(const MachineInstrBuilder &MIB)
const HexagonInstrInfo * TII
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:51
MachineBasicBlock * MBB
This class provides the information for the target register banks.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
This file declares the targeting of the RegisterBankInfo class for ARM.
ARMInstructionSelector(const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
unsigned getID() const
Get the identifier of this register bank.
Definition: RegisterBank.h:48
virtual bool select(MachineInstr &I) const override
Select the (possibly generic) instruction I to only use target-specific opcodes.
bool isCopy() const
Definition: MachineInstr.h:807
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
static const MachineInstrBuilder & AddDefaultCC(const MachineInstrBuilder &MIB)
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
Definition: RegisterBank.h:29
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel...
Definition: TargetOpcodes.h:31
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
Definition: MachineInstr.h:52
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
This file declares the targeting of the InstructionSelector class for ARM.
#define I(x, y, z)
Definition: MD5.cpp:54
static const TargetRegisterClass * constrainGenericRegister(unsigned Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
#define DEBUG(X)
Definition: Debug.h:100
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:104