29 #define GET_INSTRINFO_CTOR_DTOR
30 #include "SparcGenInstrInfo.inc"
33 void SparcInstrInfo::anchor() {}
147 return Opc == SP::FBCOND || Opc == SP::BCOND;
151 return Opc == SP::BINDrr || Opc == SP::BINDri;
164 bool AllowModify)
const {
169 if (!isUnpredicatedTerminator(*I))
174 unsigned LastOpc = LastInst->
getOpcode();
177 if (I == MBB.
begin() || !isUnpredicatedTerminator(*--I)) {
192 unsigned SecondLastOpc = SecondLastInst->
getOpcode();
199 LastInst = SecondLastInst;
201 if (I == MBB.
begin() || !isUnpredicatedTerminator(*--I)) {
206 SecondLastInst = &*
I;
207 SecondLastOpc = SecondLastInst->
getOpcode();
213 if (SecondLastInst && I != MBB.
begin() && isUnpredicatedTerminator(*--I))
235 I->eraseFromParent();
248 int *BytesAdded)
const {
249 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
251 "Sparc branch conditions should have one component!");
252 assert(!BytesAdded &&
"code size not handled");
255 assert(!FBB &&
"Unconditional branch with multiple successors!");
261 unsigned CC = Cond[0].getImm();
275 int *BytesRemoved)
const {
276 assert(!BytesRemoved &&
"code size not handled");
280 while (I != MBB.
begin()) {
283 if (I->isDebugValue())
286 if (I->getOpcode() != SP::BA
287 && I->getOpcode() != SP::BCOND
288 && I->getOpcode() != SP::FBCOND)
291 I->eraseFromParent();
308 const DebugLoc &DL,
unsigned DestReg,
309 unsigned SrcReg,
bool KillSrc)
const {
310 unsigned numSubRegs = 0;
312 const unsigned *subRegIdx =
nullptr;
313 bool ExtraG0 =
false;
315 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
316 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
317 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
318 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
319 SP::sub_odd64_then_sub_even,
320 SP::sub_odd64_then_sub_odd };
322 if (SP::IntRegsRegClass.
contains(DestReg, SrcReg))
325 else if (SP::IntPairRegClass.
contains(DestReg, SrcReg)) {
326 subRegIdx = DW_SubRegsIdx;
330 }
else if (SP::FPRegsRegClass.
contains(DestReg, SrcReg))
331 BuildMI(MBB, I, DL,
get(SP::FMOVS), DestReg)
333 else if (SP::DFPRegsRegClass.
contains(DestReg, SrcReg)) {
334 if (Subtarget.
isV9()) {
335 BuildMI(MBB, I, DL,
get(SP::FMOVD), DestReg)
339 subRegIdx = DFP_FP_SubRegsIdx;
343 }
else if (SP::QFPRegsRegClass.
contains(DestReg, SrcReg)) {
344 if (Subtarget.
isV9()) {
346 BuildMI(MBB, I, DL,
get(SP::FMOVQ), DestReg)
350 subRegIdx = QFP_DFP_SubRegsIdx;
356 subRegIdx = QFP_FP_SubRegsIdx;
360 }
else if (SP::ASRRegsRegClass.
contains(DestReg) &&
361 SP::IntRegsRegClass.
contains(SrcReg)) {
362 BuildMI(MBB, I, DL,
get(SP::WRASRrr), DestReg)
365 }
else if (SP::IntRegsRegClass.
contains(DestReg) &&
366 SP::ASRRegsRegClass.
contains(SrcReg)) {
367 BuildMI(MBB, I, DL,
get(SP::RDASR), DestReg)
372 if (numSubRegs == 0 || subRegIdx ==
nullptr || movOpc == 0)
378 for (
unsigned i = 0;
i != numSubRegs; ++
i) {
379 unsigned Dst = TRI->
getSubReg(DestReg, subRegIdx[
i]);
380 unsigned Src = TRI->
getSubReg(SrcReg, subRegIdx[i]);
381 assert(Dst && Src &&
"Bad sub-register");
397 unsigned SrcReg,
bool isKill,
int FI,
401 if (I != MBB.
end()) DL = I->getDebugLoc();
410 if (RC == &SP::I64RegsRegClass)
413 else if (RC == &SP::IntRegsRegClass)
416 else if (RC == &SP::IntPairRegClass)
419 else if (RC == &SP::FPRegsRegClass)
422 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
425 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
436 unsigned DestReg,
int FI,
440 if (I != MBB.
end()) DL = I->getDebugLoc();
448 if (RC == &SP::I64RegsRegClass)
451 else if (RC == &SP::IntRegsRegClass)
454 else if (RC == &SP::IntPairRegClass)
457 else if (RC == &SP::FPRegsRegClass)
460 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
463 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
476 if (GlobalBaseReg != 0)
485 Subtarget.
is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
490 BuildMI(FirstMBB, MBBI, dl,
get(SP::GETPCX), GlobalBaseReg);
497 case TargetOpcode::LOAD_STACK_GUARD: {
499 "Only Linux target is expected to contain LOAD_STACK_GUARD");
void push_back(const T &Elt)
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
MachineBasicBlock * getMBB() const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
return AArch64::GPR64RegClass contains(Reg)
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry...
A description of a memory reference used in the backend.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool IsIntegerCC(unsigned CC)
const MachineBasicBlock & front() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
size_t size() const
size - Get the array size.
const SparcRegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
static bool isCondBranchOpcode(int Opc)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineOperand & getOperand(unsigned i) const
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool empty() const
empty - Check if the array is empty.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
The memory access writes data.
static bool isIndirectBranchOpcode(int Opc)
static bool isUncondBranchOpcode(int Opc)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot...
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isTargetLinux() const
void setGlobalBaseReg(unsigned Reg)
const MachineInstrBuilder & addFrameIndex(int Idx) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
unsigned getGlobalBaseReg() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Target - Wrapper for Target specific information.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SparcInstrInfo(SparcSubtarget &ST)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
bool addRegisterKilled(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot...
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly. ...