38 #define DEBUG_TYPE "arm-subtarget"
40 #define GET_SUBTARGETINFO_TARGET_DESC
41 #define GET_SUBTARGETINFO_CTOR
42 #include "ARMGenSubtargetInfo.inc"
58 "Generate IT block based on arch"),
60 "Disallow deprecated IT based on ARMv8"),
62 "Allow IT blocks based on ARMv7")));
74 initializeEnvironment();
75 initSubtargetFeatures(CPU, FS);
94 const std::string &FS,
98 TargetTriple(TT), Options(TM.Options), TM(TM),
99 FrameLowering(initializeFrameLowering(CPU, FS)),
102 InstrInfo(isThumb1Only()
107 TLInfo(TM, *this), GISel() {}
110 assert(GISel &&
"Access to GlobalISel APIs not set");
111 return GISel->getCallLowering();
115 assert(GISel &&
"Access to GlobalISel APIs not set");
116 return GISel->getInstructionSelector();
120 assert(GISel &&
"Access to GlobalISel APIs not set");
121 return GISel->getLegalizerInfo();
125 assert(GISel &&
"Access to GlobalISel APIs not set");
126 return GISel->getRegBankInfo();
134 void ARMSubtarget::initializeEnvironment() {
142 "inconsistent sjlj choice between CodeGen and MC");
152 if (ArchKind == llvm::ARM::AK_ARMV7S)
155 else if (ArchKind == llvm::ARM::AK_ARMV7K)
168 ArchFS = (
Twine(ArchFS) +
"," + FS).str();
234 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) &&
340 return getSchedModel().isOutOfOrder() &&
isSwift();
347 if (getSchedModel().isOutOfOrder() &&
isSwift())
bool NoMovt
NoMovt - True if MOVT / MOVW pairs are not used for materialization of 32-bit imms (including global ...
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::ZeroOrMore, cl::values(clEnumValN(DefaultIT,"arm-default-it","Generate IT block based on arch"), clEnumValN(RestrictedIT,"arm-restrict-it","Disallow deprecated IT based on ARMv8"), clEnumValN(NoRestrictedIT,"arm-no-restrict-it","Allow IT blocks based on ARMv7")))
unsigned MispredictPenalty
unsigned stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
unsigned getMispredictionPenalty() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
static cl::opt< bool > EnableExecuteOnly("arm-execute-only")
EnableExecuteOnly - Enables the generation of execute-only code on supported targets.
bool isAAPCS16_ABI() const
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
DWARF-like instruction based exceptions.
bool useFastISel() const
True if fast-isel is used.
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
const LegalizerInfo * getLegalizerInfo() const override
bool isThumb1Only() const
const ARMBaseTargetMachine & TM
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
static bool isThumb(const MCSubtargetInfo &STI)
bool optForMinSize() const
Optimize this function for minimum size (-Oz).
Holds all the information related to register banks.
bool hasCommonLinkage() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
bool isTargetDarwin() const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool useStride4VFPs(const MachineFunction &MF) const
This file contains the simple types necessary to represent the attributes associated with functions a...
const Triple & getTargetTriple() const
bool enableAtomicExpand() const override
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned...
virtual bool isXRaySupported() const override
bool isTargetMachO() const
bool NoARM
NoARM - True if subtarget does not support ARM mode execution.
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
bool hasAnyDataBarrier() const
bool isTargetWatchOS() const
ValuesClass values(OptsTy...Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of deprecated IT blocks to conform to ARMv8 ...
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
bool isPositionIndependent() const
ExceptionHandling getExceptionHandlingType() const
bool isTargetWatchABI() const
bool hasV8MBaselineOps() const
const CallLowering * getCallLowering() const override
bool hasSinCos() const
This function returns true if the target has sincos() routine in its compiler runtime or math librari...
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
bool genExecuteOnly() const
Triple - Helper class for working with autoconf configuration names.
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle)
This constructor initializes the data members to match that of the specified triple.
bool isTargetNaCl() const
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
const InstructionSelector * getInstructionSelector() const override
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
const TargetOptions & Options
Options passed via command line that could influence the target.
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Provides the logic to select generic machine instructions.
bool isTargetLinux() const
bool ReserveR9
ReserveR9 - True if R9 is not available as a general purpose register.
StringRef getArchName() const
getArchName - Get the architecture (first) component of the triple.
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
bool UseNEONForSinglePrecisionFP
UseNEONForSinglePrecisionFP - if the NEONFP attribute has been specified.
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
unsigned parseArch(StringRef Arch)
bool useMovt(const MachineFunction &MF) const
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc)...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Module * getParent()
Get the module that this global value is contained inside of...
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Can load/store 2 registers/cycle.
std::string CPUString
CPUString - String name of used CPU.
StringRef - Represent a constant reference to a string, i.e.
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
bool isDeclarationForLinker() const
bool isTargetWindows() const
const RegisterBankInfo * getRegBankInfo() const override
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
unsigned MaxInterleaveFactor