15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
43 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
46 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
49 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
53 assert(Reg != 0 &&
"Invalid CR bit register");
120 int &FrameIdx)
const override;
122 unsigned FIOperandNum,
128 unsigned BaseReg,
int FrameIdx,
129 int64_t
Offset)
const override;
131 int64_t
Offset)
const override;
133 int64_t
Offset)
const override;
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Returns true if the instruction's frame index reference would be better served by a base register oth...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresRegisterScavenging(const MachineFunction &MF) const override
We require the register scavenger.
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getFrameRegister(const MachineFunction &MF) const override
void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx at the beginning of the basic ...
unsigned getBaseRegister(const MachineFunction &MF) const
Common code between 32-bit and 64-bit PowerPC targets.
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
PPCRegisterInfo(const PPCTargetMachine &TM)
static unsigned getCRFromCRBit(unsigned SrcReg)
const uint32_t * getNoPreservedMask() const override
void lowerDynamicAlloc(MachineBasicBlock::iterator II) const
lowerDynamicAlloc - Generate the code for allocating an object in the current frame.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
void lowerCRBitRestore(MachineBasicBlock::iterator II, unsigned FrameIndex) const
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override
Representation of each machine instruction.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Return the register class to use to hold pointers.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
lowerCRSpilling - Generate the code for spilling a CR register.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void lowerCRBitSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex) const
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool hasBasePointer(const MachineFunction &MF) const
bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override