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LLVM
4.0.0
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#include "PPC.h"#include "MCTargetDesc/PPCPredicates.h"#include "PPCMachineFunctionInfo.h"#include "PPCTargetMachine.h"#include "llvm/Analysis/BranchProbabilityInfo.h"#include "llvm/CodeGen/FunctionLoweringInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/IR/Constants.h"#include "llvm/IR/Function.h"#include "llvm/IR/GlobalAlias.h"#include "llvm/IR/GlobalValue.h"#include "llvm/IR/GlobalVariable.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/Module.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetOptions.h"#include "PPCGenDAGISel.inc"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "ppc-codegen" |
Functions | |
| static bool | isIntS16Immediate (SDNode *N, short &Imm) |
| isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value. More... | |
| static bool | isIntS16Immediate (SDValue Op, short &Imm) |
| static bool | isInt32Immediate (SDNode *N, unsigned &Imm) |
| isInt32Immediate - This method tests to see if the node is a 32-bit constant operand. More... | |
| static bool | isInt64Immediate (SDNode *N, uint64_t &Imm) |
| isInt64Immediate - This method tests to see if the node is a 64-bit constant operand. More... | |
| static bool | isInt32Immediate (SDValue N, unsigned &Imm) |
| static unsigned | getBranchHint (unsigned PCC, FunctionLoweringInfo *FuncInfo, const SDValue &DestMBB) |
| static bool | isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm) |
| static unsigned | getInt64CountDirect (int64_t Imm) |
| static uint64_t | Rot64 (uint64_t Imm, unsigned R) |
| static unsigned | getInt64Count (int64_t Imm) |
| static SDNode * | getInt64Direct (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) |
| static SDNode * | getInt64 (SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) |
| static SDNode * | getInt64 (SelectionDAG *CurDAG, SDNode *N) |
| static PPC::Predicate | getPredicateForSetCC (ISD::CondCode CC) |
| static unsigned | getCRIdxForSetCC (ISD::CondCode CC, bool &Invert) |
| getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted. More... | |
| static unsigned int | getVCmpInst (MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate) |
| static bool | PeepholePPC64ZExtGather (SDValue Op32, SmallPtrSetImpl< SDNode * > &ToPromote) |
Variables | |
| cl::opt< bool > | ANDIGlueBug ("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden) |
| static cl::opt< bool > | UseBitPermRewriter ("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden) |
| static cl::opt< bool > | BPermRewriterNoMasking ("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for ""bit permutations"), cl::Hidden) |
| static cl::opt< bool > | EnableBranchHint ("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden) |
| #define DEBUG_TYPE "ppc-codegen" |
Definition at line 41 of file PPCISelDAGToDAG.cpp.
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Definition at line 398 of file PPCISelDAGToDAG.cpp.
References assert(), llvm::FunctionLoweringInfo::BPI, llvm::PPC::BR_NO_HINT, llvm::PPC::BR_NONTAKEN_HINT, llvm::PPC::BR_TAKEN_HINT, llvm::dbgs(), DEBUG, llvm::FunctionLoweringInfo::Fn, llvm::MachineBasicBlock::getBasicBlock(), llvm::BranchProbabilityInfo::getEdgeProbability(), llvm::Value::getName(), llvm::TerminatorInst::getNumSuccessors(), llvm::TerminatorInst::getSuccessor(), llvm::BasicBlock::getTerminator(), llvm::FunctionLoweringInfo::MBB, fuzzer::min(), std::swap(), and Threshold.
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getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.
That is, lt = 0; ge = 0 inverted.
Definition at line 2154 of file PPCISelDAGToDAG.cpp.
References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.
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Definition at line 770 of file PPCISelDAGToDAG.cpp.
References llvm::findLastSet(), getInt64CountDirect(), getInt64Direct(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::MVT::i64, llvm::AArch64CC::LS, and Rot64().
Referenced by getInt64().
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Definition at line 827 of file PPCISelDAGToDAG.cpp.
References getInt64(), and N.
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Definition at line 660 of file PPCISelDAGToDAG.cpp.
References llvm::findLastSet(), getInt64CountDirect(), llvm::AArch64CC::LS, fuzzer::min(), and Rot64().
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Definition at line 592 of file PPCISelDAGToDAG.cpp.
References llvm::isInt< 16 >(), llvm::isInt< 32 >(), and llvm::MipsISD::Lo.
Referenced by getInt64(), and getInt64Count().
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Definition at line 687 of file PPCISelDAGToDAG.cpp.
References llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MipsISD::Hi, llvm::MVT::i32, llvm::MVT::i64, llvm::isInt< 16 >(), llvm::isInt< 32 >(), and llvm::MipsISD::Lo.
Referenced by getInt64().
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Definition at line 2123 of file PPCISelDAGToDAG.cpp.
References llvm_unreachable, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::PPC::PRED_NU, llvm::PPC::PRED_UN, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.
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Definition at line 2186 of file PPCISelDAGToDAG.cpp.
References llvm::MVT::isFloatingPoint(), llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::MVT::v8i16.
isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
If so Imm will receive the 32-bit value.
Definition at line 374 of file PPCISelDAGToDAG.cpp.
References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i32, and N.
Referenced by isInt32Immediate(), and isOpcWithIntImmediate().
Definition at line 394 of file PPCISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), and isInt32Immediate().
isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.
If so Imm will receive the 64-bit value.
Definition at line 384 of file PPCISelDAGToDAG.cpp.
References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i64, and N.
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate, and if the value can be accurately represented as a sign extension from a 16-bit value.
If so, this returns true and the immediate.
Definition at line 356 of file PPCISelDAGToDAG.cpp.
References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i32, and N.
Referenced by isIntS16Immediate().
Definition at line 367 of file PPCISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), and isIntS16Immediate().
Definition at line 451 of file PPCISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isInt32Immediate().
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Definition at line 4001 of file PPCISelDAGToDAG.cpp.
References llvm::ISD::AND, B, llvm::SmallPtrSetImpl< PtrType >::begin(), llvm::SmallPtrSetImpl< PtrType >::end(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SDValue::isMachineOpcode(), and OR.
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Definition at line 656 of file PPCISelDAGToDAG.cpp.
Referenced by getInt64(), and getInt64Count().
| cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden) |
Referenced by llvm::PPCTargetLowering::PPCTargetLowering().
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1.8.6