LLVM  4.0.0
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MachineScheduler.cpp File Reference
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/ADT/PriorityQueue.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDFS.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
Include dependency graph for MachineScheduler.cpp:

Go to the source code of this file.

Classes

struct  llvm::GraphTraits< ScheduleDAGMI * >
 
struct  llvm::DOTGraphTraits< ScheduleDAGMI * >
 

Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 

Macros

#define DEBUG_TYPE   "misched"
 

Functions

cl::opt< boolllvm::ForceTopDown ("misched-topdown", cl::Hidden, cl::desc("Force top-down list scheduling"))
 
cl::opt< boolllvm::ForceBottomUp ("misched-bottomup", cl::Hidden, cl::desc("Force bottom-up list scheduling"))
 
 INITIALIZE_PASS_BEGIN (MachineScheduler,"machine-scheduler","Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(MachineScheduler
 
 INITIALIZE_PASS (PostMachineScheduler,"postmisched","PostRA Machine Instruction Scheduler", false, false) PostMachineScheduler
 
static ScheduleDAGInstrsuseDefaultMachineSched (MachineSchedContext *C)
 A dummy default scheduler factory indicates whether the scheduler is overridden on the command line. More...
 
static
MachineBasicBlock::const_iterator 
priorNonDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator Beg)
 Decrement this iterator until reaching the top or a non-debug instr. More...
 
static MachineBasicBlock::iterator priorNonDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator Beg)
 Non-const version. More...
 
static
MachineBasicBlock::const_iterator 
nextIfDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator End)
 If this iterator is a debug value, increment until reaching the End or a non-debug instruction. More...
 
static MachineBasicBlock::iterator nextIfDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End)
 Non-const version. More...
 
static bool isSchedBoundary (MachineBasicBlock::iterator MI, MachineBasicBlock *MBB, MachineFunction *MF, const TargetInstrInfo *TII)
 Return true of the given instruction should not be included in a scheduling region. More...
 
std::unique_ptr
< ScheduleDAGMutation
llvm::createLoadClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
 
std::unique_ptr
< ScheduleDAGMutation
llvm::createStoreClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
 
std::unique_ptr
< ScheduleDAGMutation
llvm::createMacroFusionDAGMutation (const TargetInstrInfo *TII)
 
std::unique_ptr
< ScheduleDAGMutation
llvm::createCopyConstrainDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
 
static bool tryLess (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
 Return true if this heuristic determines order. More...
 
static bool tryGreater (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
 
static bool tryLatency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)
 
static void tracePick (GenericSchedulerBase::CandReason Reason, bool IsTop)
 
static void tracePick (const GenericSchedulerBase::SchedCandidate &Cand)
 
static bool tryPressure (const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)
 
static unsigned getWeakLeft (const SUnit *SU, bool isTop)
 
static int biasPhysRegCopy (const SUnit *SU, bool isTop)
 Minimize physical register live ranges. More...
 
static ScheduleDAGInstrscreateConveringSched (MachineSchedContext *C)
 
static ScheduleDAGInstrscreateILPMaxScheduler (MachineSchedContext *C)
 
static ScheduleDAGInstrscreateILPMinScheduler (MachineSchedContext *C)
 
static ScheduleDAGInstrscreateInstructionShuffler (MachineSchedContext *C)
 

Variables

cl::opt< boolllvm::DumpCriticalPathLength ("misched-dcpl", cl::Hidden, cl::desc("Print critical path length to stdout"))
 
static cl::opt< boolViewMISchedDAGs ("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed"))
 
static cl::opt< unsignedViewMISchedCutoff ("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff"))
 In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them. More...
 
static cl::opt< unsignedMISchedCutoff ("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U))
 
static cl::opt< std::string > SchedOnlyFunc ("misched-only-func", cl::Hidden, cl::desc("Only schedule this function"))
 
static cl::opt< unsignedSchedOnlyBlock ("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#"))
 
static cl::opt< unsignedReadyListLimit ("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256))
 Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists. More...
 
static cl::opt< boolEnableRegPressure ("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true))
 
static cl::opt< boolEnableCyclicPath ("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true))
 
static cl::opt< boolEnableMemOpCluster ("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true))
 
static cl::opt< boolEnableMacroFusion ("misched-fusion", cl::Hidden, cl::desc("Enable scheduling for macro fusion."), cl::init(true))
 
static cl::opt< boolVerifyScheduling ("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling"))
 
static const unsigned MinSubtreeSize = 8
 
machine scheduler
 
machine Machine Instruction Scheduler
 
machine Machine Instruction false
 
static cl::opt
< MachineSchedRegistry::ScheduleDAGCtor,
false, RegisterPassParser
< MachineSchedRegistry > > 
MachineSchedOpt ("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use"))
 MachineSchedOpt allows command line selection of the scheduler. More...
 
static MachineSchedRegistry DefaultSchedRegistry ("default","Use the target's default scheduler choice.", useDefaultMachineSched)
 
static cl::opt< boolEnableMachineSched ("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden)
 
static cl::opt< boolEnablePostRAMachineSched ("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden)
 
static const unsigned InvalidCycle = ~0U
 
static MachineSchedRegistry GenericSchedRegistry ("converge","Standard converging scheduler.", createConveringSched)
 
static MachineSchedRegistry ILPMaxRegistry ("ilpmax","Schedule bottom-up for max ILP", createILPMaxScheduler)
 
static MachineSchedRegistry ILPMinRegistry ("ilpmin","Schedule bottom-up for min ILP", createILPMinScheduler)
 
static MachineSchedRegistry ShufflerRegistry ("shuffle","Shuffle machine instructions alternating directions", createInstructionShuffler)
 

Macro Definition Documentation

#define DEBUG_TYPE   "misched"

Definition at line 36 of file MachineScheduler.cpp.

Function Documentation

static int biasPhysRegCopy ( const SUnit SU,
bool  isTop 
)
static

Minimize physical register live ranges.

Regalloc wants them adjacent to their physreg def/use.

FIXME: This is an unnecessary check on the critical path. Most are root/leaf copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled with the operation that produces or consumes the physreg. We'll do this when regalloc has support for parallel copies.

Definition at line 2783 of file MachineScheduler.cpp.

References llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isCopy(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::SUnit::NumPredsLeft, and llvm::SUnit::NumSuccsLeft.

Referenced by llvm::GenericScheduler::tryCandidate().

static ScheduleDAGInstrs* createConveringSched ( MachineSchedContext C)
static

Definition at line 3167 of file MachineScheduler.cpp.

References llvm::createGenericSchedLive().

static ScheduleDAGInstrs* createILPMaxScheduler ( MachineSchedContext C)
static

Definition at line 3410 of file MachineScheduler.cpp.

static ScheduleDAGInstrs* createILPMinScheduler ( MachineSchedContext C)
static

Definition at line 3413 of file MachineScheduler.cpp.

static ScheduleDAGInstrs* createInstructionShuffler ( MachineSchedContext C)
static

Definition at line 3497 of file MachineScheduler.cpp.

References assert(), llvm::ForceBottomUp, and llvm::ForceTopDown.

static unsigned getWeakLeft ( const SUnit SU,
bool  isTop 
)
static
INITIALIZE_PASS ( PostMachineScheduler  ,
"postmisched"  ,
"PostRA Machine Instruction Scheduler ,
false  ,
false   
)
INITIALIZE_PASS_BEGIN ( MachineScheduler  ,
"machine-scheduler ,
"Machine Instruction Scheduler ,
false  ,
false   
)
static bool isSchedBoundary ( MachineBasicBlock::iterator  MI,
MachineBasicBlock MBB,
MachineFunction MF,
const TargetInstrInfo TII 
)
static

Return true of the given instruction should not be included in a scheduling region.

MachineScheduler does not currently support scheduling across calls. To handle calls, the DAG builder needs to be modified to create register anti/output dependencies on the registers clobbered by the call's regmask operand. In PreRA scheduling, the stack pointer adjustment already prevents scheduling across calls. In PostRA scheduling, we need the isCall to enforce the boundary, but there would be no benefit to postRA scheduling across calls this late anyway.

Definition at line 396 of file MachineScheduler.cpp.

References llvm::TargetInstrInfo::isSchedulingBoundary().

If this iterator is a debug value, increment until reaching the End or a non-debug instruction.

Definition at line 256 of file MachineScheduler.cpp.

References llvm::WebAssembly::End, and I.

Referenced by llvm::ScheduleDAGMI::initQueues(), nextIfDebug(), llvm::ScheduleDAGMI::schedule(), llvm::ScheduleDAGMILive::scheduleMI(), and llvm::ScheduleDAGMILive::updatePressureDiffs().

Decrement this iterator until reaching the top or a non-debug instr.

Definition at line 235 of file MachineScheduler.cpp.

References assert(), and I.

Referenced by priorNonDebug(), llvm::ScheduleDAGMI::schedule(), and llvm::ScheduleDAGMILive::scheduleMI().

static void tracePick ( GenericSchedulerBase::CandReason  Reason,
bool  IsTop 
)
static
static void tracePick ( const GenericSchedulerBase::SchedCandidate Cand)
static
static bool tryGreater ( int  TryVal,
int  CandVal,
GenericSchedulerBase::SchedCandidate TryCand,
GenericSchedulerBase::SchedCandidate Cand,
GenericSchedulerBase::CandReason  Reason 
)
static
static bool tryLatency ( GenericSchedulerBase::SchedCandidate TryCand,
GenericSchedulerBase::SchedCandidate Cand,
SchedBoundary Zone 
)
static
static bool tryLess ( int  TryVal,
int  CandVal,
GenericSchedulerBase::SchedCandidate TryCand,
GenericSchedulerBase::SchedCandidate Cand,
GenericSchedulerBase::CandReason  Reason 
)
static
static ScheduleDAGInstrs* useDefaultMachineSched ( MachineSchedContext C)
static

A dummy default scheduler factory indicates whether the scheduler is overridden on the command line.

Definition at line 208 of file MachineScheduler.cpp.

Variable Documentation

MachineSchedRegistry DefaultSchedRegistry("default","Use the target's default scheduler choice.", useDefaultMachineSched)
static
cl::opt<bool> EnableCyclicPath("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true))
static
cl::opt<bool> EnableMachineSched("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden)
static
cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden, cl::desc("Enable scheduling for macro fusion."), cl::init(true))
static
cl::opt<bool> EnableMemOpCluster("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true))
static
cl::opt<bool> EnablePostRAMachineSched("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden)
static
cl::opt<bool> EnableRegPressure("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true))
static
machine Machine Instruction false

Definition at line 163 of file MachineScheduler.cpp.

MachineSchedRegistry GenericSchedRegistry("converge","Standard converging scheduler.", createConveringSched)
static
MachineSchedRegistry ILPMaxRegistry("ilpmax","Schedule bottom-up for max ILP", createILPMaxScheduler)
static
MachineSchedRegistry ILPMinRegistry("ilpmin","Schedule bottom-up for min ILP", createILPMinScheduler)
static
const unsigned InvalidCycle = ~0U
static
cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false, RegisterPassParser<MachineSchedRegistry> > MachineSchedOpt("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use"))
static

MachineSchedOpt allows command line selection of the scheduler.

const unsigned MinSubtreeSize = 8
static

Definition at line 91 of file MachineScheduler.cpp.

Referenced by llvm::ScheduleDAGMILive::computeDFSResult().

cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U))
static
cl::opt<unsigned> ReadyListLimit("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256))
static

Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists.

Referenced by llvm::SchedBoundary::releaseNode(), and llvm::SchedBoundary::releasePending().

cl::opt<unsigned> SchedOnlyBlock("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#"))
static
cl::opt<std::string> SchedOnlyFunc("misched-only-func", cl::Hidden, cl::desc("Only schedule this function"))
static
machine scheduler

Definition at line 163 of file MachineScheduler.cpp.

machine Machine Instruction Scheduler
MachineSchedRegistry ShufflerRegistry("shuffle","Shuffle machine instructions alternating directions", createInstructionShuffler)
static
cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling"))
static
cl::opt<unsigned> ViewMISchedCutoff("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff"))
static

In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them.

Referenced by llvm::DOTGraphTraits< ScheduleDAGMI * >::isNodeHidden().

cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed"))
static