10 #ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
11 #define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
49 bool has(
unsigned Reg)
const;
50 const RegisterCell &
lookup(
unsigned Reg)
const;
51 RegisterCell
get(RegisterRef RR)
const;
52 void put(RegisterRef RR,
const RegisterCell &RC);
53 void subst(RegisterRef OldRR, RegisterRef NewRR);
63 void visitUsesOf(
unsigned Reg);
66 typedef std::pair<int,int> CFGEdge;
67 typedef std::set<CFGEdge> EdgeSetType;
68 typedef std::set<const MachineInstr *> InstrSetType;
69 typedef std::queue<CFGEdge> EdgeQueueType;
72 InstrSetType InstrExec;
76 const MachineEvaluator &ME;
165 bool is(
unsigned T)
const {
168 : (T == 1 ?
Type ==
One :
false);
278 uint16_t cl(
bool B)
const;
279 uint16_t ct(
bool B)
const;
298 static const unsigned DefaultBitN = 32;
306 return Map.find(Reg) != Map.end();
311 CellMapType::const_iterator
F = Map.find(Reg);
319 for (uint16_t
i = 0;
i < Width; ++
i)
327 for (uint16_t
i = 0;
i < Width; ++
i)
334 uint16_t W = C.
width();
336 for (
unsigned i = 0;
i < W; ++
i)
418 virtual BitMask mask(
unsigned Reg,
unsigned Sub)
const;
439 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
RegisterRef(unsigned R=0, unsigned S=0)
RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const
MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
const TargetRegisterInfo & TRI
BitValue(ValueType T=Top)
void trace(bool On=false)
std::map< unsigned, RegisterCell > CellMapType
void print_cells(raw_ostream &OS) const
BitValue(unsigned Reg, uint16_t Pos)
static RegisterCell top(uint16_t Width)
void visit(const MachineInstr &MI)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
static RegisterCell self(unsigned Reg, uint16_t Width)
const BitValue & operator[](uint16_t BitN) const
Reg
All possible values of the reg field in the ModR/M byte.
BitValue & operator[](uint16_t BitN)
bool is(unsigned T) const
BitRef(unsigned R=0, uint16_t P=0)
BitMask(uint16_t b, uint16_t e)
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
Control flow instructions. These all have token chains.
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
constexpr bool isInt(int64_t x)
isInt - Checks if an integer fits into the given bit width.
static uint32_t rol(uint32_t Number, int Bits)
void subst(RegisterRef OldRR, RegisterRef NewRR)
bool operator==(const BitRef &BR) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SetVector< const MachineBasicBlock * > BranchTargetList
bool operator!=(const BitValue &V) const
const RegisterCell & lookup(unsigned Reg) const
This is the shared class of boolean and integer constants.
static BitValue self(const BitRef &Self=BitRef())
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo & MRI
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool operator==(const BitValue &V) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool has(unsigned Reg) const
bool operator!=(uint64_t V1, const APInt &V2)
Representation of each machine instruction.
virtual bool track(const TargetRegisterClass *RC) const
BitTracker(const MachineEvaluator &E, MachineFunction &F)
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
bool reached(const MachineBasicBlock *B) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterRef(const MachineOperand &MO)
RegisterCell(uint16_t Width=DefaultBitN)
friend raw_ostream & operator<<(raw_ostream &OS, const BitValue &BV)
A vector that has set insertion semantics.
void put(RegisterRef RR, const RegisterCell &RC)
This class implements an extremely fast bulk output stream that can only output to a stream...
bool operator==(uint64_t V1, const APInt &V2)
static RegisterCell ref(const RegisterCell &C)
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
bool meet(const BitValue &V, const BitRef &Self)
static BitValue ref(const BitValue &V)