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LLVM
4.0.0
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Representation of each machine instruction. More...
#include <MachineInstr.h>
Public Types | |
| enum | CommentFlag { ReloadReuse = 0x1 } |
| Flags to specify different kinds of comments to output in assembly code. More... | |
| enum | MIFlag { NoFlags = 0, FrameSetup = 1 << 0, FrameDestroy = 1 << 1, BundledPred = 1 << 2, BundledSucc = 1 << 3 } |
| enum | QueryType { IgnoreBundle, AnyInBundle, AllInBundle } |
| API for querying MachineInstr properties. More... | |
| enum | MICheckType { CheckDefs, CheckKillDead, IgnoreDefs, IgnoreVRegDefs } |
| typedef MachineMemOperand ** | mmo_iterator |
| typedef MachineOperand * | mop_iterator |
| iterator/begin/end - Iterate over all operands of a machine instruction. More... | |
| typedef const MachineOperand * | const_mop_iterator |
Public Member Functions | |
| const MachineBasicBlock * | getParent () const |
| MachineBasicBlock * | getParent () |
| uint8_t | getAsmPrinterFlags () const |
| Return the asm printer flags bitvector. More... | |
| void | clearAsmPrinterFlags () |
| Clear the AsmPrinter bitvector. More... | |
| bool | getAsmPrinterFlag (CommentFlag Flag) const |
| Return whether an AsmPrinter flag is set. More... | |
| void | setAsmPrinterFlag (uint8_t Flag) |
| Set a flag for the AsmPrinter. More... | |
| void | clearAsmPrinterFlag (CommentFlag Flag) |
| Clear specific AsmPrinter flags. More... | |
| uint8_t | getFlags () const |
| Return the MI flags bitvector. More... | |
| bool | getFlag (MIFlag Flag) const |
| Return whether an MI flag is set. More... | |
| void | setFlag (MIFlag Flag) |
| Set a MI flag. More... | |
| void | setFlags (unsigned flags) |
| void | clearFlag (MIFlag Flag) |
| clearFlag - Clear a MI flag. More... | |
| bool | isInsideBundle () const |
| Return true if MI is in a bundle (but not the first MI in a bundle). More... | |
| bool | isBundled () const |
| Return true if this instruction part of a bundle. More... | |
| bool | isBundledWithPred () const |
| Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle. More... | |
| bool | isBundledWithSucc () const |
| Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle. More... | |
| void | bundleWithPred () |
| Bundle this instruction with its predecessor. More... | |
| void | bundleWithSucc () |
| Bundle this instruction with its successor. More... | |
| void | unbundleFromPred () |
| Break bundle above this instruction. More... | |
| void | unbundleFromSucc () |
| Break bundle below this instruction. More... | |
| const DebugLoc & | getDebugLoc () const |
| Returns the debug location id of this MachineInstr. More... | |
| const DILocalVariable * | getDebugVariable () const |
| Return the debug variable referenced by this DBG_VALUE instruction. More... | |
| const DIExpression * | getDebugExpression () const |
| Return the complex address expression referenced by this DBG_VALUE instruction. More... | |
| void | emitError (StringRef Msg) const |
| Emit an error referring to the source location of this instruction. More... | |
| const MCInstrDesc & | getDesc () const |
| Returns the target instruction descriptor of this MachineInstr. More... | |
| unsigned | getOpcode () const |
| Returns the opcode of this MachineInstr. More... | |
| unsigned | getNumOperands () const |
| Access to explicit operands of the instruction. More... | |
| const MachineOperand & | getOperand (unsigned i) const |
| MachineOperand & | getOperand (unsigned i) |
| unsigned | getNumExplicitOperands () const |
| Returns the number of non-implicit operands. More... | |
| mop_iterator | operands_begin () |
| mop_iterator | operands_end () |
| const_mop_iterator | operands_begin () const |
| const_mop_iterator | operands_end () const |
| iterator_range< mop_iterator > | operands () |
| iterator_range < const_mop_iterator > | operands () const |
| iterator_range< mop_iterator > | explicit_operands () |
| iterator_range < const_mop_iterator > | explicit_operands () const |
| iterator_range< mop_iterator > | implicit_operands () |
| iterator_range < const_mop_iterator > | implicit_operands () const |
| iterator_range< mop_iterator > | defs () |
| Returns a range over all explicit operands that are register definitions. More... | |
| iterator_range < const_mop_iterator > | defs () const |
| Returns a range over all explicit operands that are register definitions. More... | |
| iterator_range< mop_iterator > | uses () |
| Returns a range that includes all operands that are register uses. More... | |
| iterator_range < const_mop_iterator > | uses () const |
| Returns a range that includes all operands that are register uses. More... | |
| iterator_range< mop_iterator > | explicit_uses () |
| iterator_range < const_mop_iterator > | explicit_uses () const |
| unsigned | getOperandNo (const_mop_iterator I) const |
Returns the number of the operand iterator I points to. More... | |
| mmo_iterator | memoperands_begin () const |
| Access to memory operands of the instruction. More... | |
| mmo_iterator | memoperands_end () const |
| bool | memoperands_empty () const |
| Return true if we don't have any memory operands which described the the memory access done by this instruction. More... | |
| iterator_range< mmo_iterator > | memoperands () |
| iterator_range< mmo_iterator > | memoperands () const |
| bool | hasOneMemOperand () const |
| Return true if this instruction has exactly one MachineMemOperand. More... | |
| bool | hasProperty (unsigned MCFlag, QueryType Type=AnyInBundle) const |
| Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property. More... | |
| bool | isVariadic (QueryType Type=IgnoreBundle) const |
| Return true if this instruction can have a variable number of operands. More... | |
| bool | hasOptionalDef (QueryType Type=IgnoreBundle) const |
| Set if this instruction has an optional definition, e.g. More... | |
| bool | isPseudo (QueryType Type=IgnoreBundle) const |
| Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. More... | |
| bool | isReturn (QueryType Type=AnyInBundle) const |
| bool | isCall (QueryType Type=AnyInBundle) const |
| bool | isBarrier (QueryType Type=AnyInBundle) const |
| Returns true if the specified instruction stops control flow from executing the instruction immediately following it. More... | |
| bool | isTerminator (QueryType Type=AnyInBundle) const |
| Returns true if this instruction part of the terminator for a basic block. More... | |
| bool | isBranch (QueryType Type=AnyInBundle) const |
| Returns true if this is a conditional, unconditional, or indirect branch. More... | |
| bool | isIndirectBranch (QueryType Type=AnyInBundle) const |
| Return true if this is an indirect branch, such as a branch through a register. More... | |
| bool | isConditionalBranch (QueryType Type=AnyInBundle) const |
| Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. More... | |
| bool | isUnconditionalBranch (QueryType Type=AnyInBundle) const |
| Return true if this is a branch which always transfers control flow to some other block. More... | |
| bool | isPredicable (QueryType Type=AllInBundle) const |
| Return true if this instruction has a predicate operand that controls execution. More... | |
| bool | isCompare (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a comparison. More... | |
| bool | isMoveImmediate (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a move immediate (including conditional moves) instruction. More... | |
| bool | isBitcast (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a bitcast instruction. More... | |
| bool | isSelect (QueryType Type=IgnoreBundle) const |
| Return true if this instruction is a select instruction. More... | |
| bool | isNotDuplicable (QueryType Type=AnyInBundle) const |
| Return true if this instruction cannot be safely duplicated. More... | |
| bool | isConvergent (QueryType Type=AnyInBundle) const |
| Return true if this instruction is convergent. More... | |
| bool | hasDelaySlot (QueryType Type=AnyInBundle) const |
| Returns true if the specified instruction has a delay slot which must be filled by the code generator. More... | |
| bool | canFoldAsLoad (QueryType Type=IgnoreBundle) const |
| Return true for instructions that can be folded as memory operands in other instructions. More... | |
| bool | isRegSequenceLike (QueryType Type=IgnoreBundle) const |
| Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. More... | |
| bool | isExtractSubregLike (QueryType Type=IgnoreBundle) const |
| Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. More... | |
| bool | isInsertSubregLike (QueryType Type=IgnoreBundle) const |
| Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. More... | |
| bool | mayLoad (QueryType Type=AnyInBundle) const |
| Return true if this instruction could possibly read memory. More... | |
| bool | mayStore (QueryType Type=AnyInBundle) const |
| Return true if this instruction could possibly modify memory. More... | |
| bool | mayLoadOrStore (QueryType Type=AnyInBundle) const |
| Return true if this instruction could possibly read or modify memory. More... | |
| bool | isCommutable (QueryType Type=IgnoreBundle) const |
| Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. More... | |
| bool | isConvertibleTo3Addr (QueryType Type=IgnoreBundle) const |
| Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. More... | |
| bool | usesCustomInsertionHook (QueryType Type=IgnoreBundle) const |
| Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. More... | |
| bool | hasPostISelHook (QueryType Type=IgnoreBundle) const |
| Return true if this instruction requires adjustment after instruction selection by calling a target hook. More... | |
| bool | isRematerializable (QueryType Type=AllInBundle) const |
| Returns true if this instruction is a candidate for remat. More... | |
| bool | isAsCheapAsAMove (QueryType Type=AllInBundle) const |
| Returns true if this instruction has the same cost (or less) than a move instruction. More... | |
| bool | hasExtraSrcRegAllocReq (QueryType Type=AnyInBundle) const |
| Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. More... | |
| bool | hasExtraDefRegAllocReq (QueryType Type=AnyInBundle) const |
| Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. More... | |
| bool | isIdenticalTo (const MachineInstr &Other, MICheckType Check=CheckDefs) const |
Return true if this instruction is identical to Other. More... | |
| MachineInstr * | removeFromParent () |
| Unlink 'this' from the containing basic block, and return it without deleting it. More... | |
| MachineInstr * | removeFromBundle () |
| Unlink this instruction from its basic block and return it without deleting it. More... | |
| void | eraseFromParent () |
| Unlink 'this' from the containing basic block and delete it. More... | |
| void | eraseFromParentAndMarkDBGValuesForRemoval () |
| Unlink 'this' from the containing basic block and delete it. More... | |
| void | eraseFromBundle () |
| Unlink 'this' form its basic block and delete it. More... | |
| bool | isEHLabel () const |
| bool | isGCLabel () const |
| bool | isLabel () const |
| Returns true if the MachineInstr represents a label. More... | |
| bool | isCFIInstruction () const |
| bool | isPosition () const |
| bool | isDebugValue () const |
| bool | isIndirectDebugValue () const |
| A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate. More... | |
| bool | isPHI () const |
| bool | isKill () const |
| bool | isImplicitDef () const |
| bool | isInlineAsm () const |
| bool | isMSInlineAsm () const |
| bool | isStackAligningInlineAsm () const |
| InlineAsm::AsmDialect | getInlineAsmDialect () const |
| bool | isInsertSubreg () const |
| bool | isSubregToReg () const |
| bool | isRegSequence () const |
| bool | isBundle () const |
| bool | isCopy () const |
| bool | isFullCopy () const |
| bool | isExtractSubreg () const |
| bool | isCopyLike () const |
| Return true if the instruction behaves like a copy. More... | |
| bool | isIdentityCopy () const |
| Return true is the instruction is an identity copy. More... | |
| bool | isTransient () const |
| Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost. More... | |
| unsigned | getBundleSize () const |
| Return the number of instructions inside the MI bundle, excluding the bundle header. More... | |
| bool | readsRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const |
| Return true if the MachineInstr reads the specified register. More... | |
| bool | readsVirtualRegister (unsigned Reg) const |
| Return true if the MachineInstr reads the specified virtual register. More... | |
| std::pair< bool, bool > | readsWritesVirtualRegister (unsigned Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const |
| Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg. More... | |
| bool | killsRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const |
| Return true if the MachineInstr kills the specified register. More... | |
| bool | definesRegister (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const |
| Return true if the MachineInstr fully defines the specified register. More... | |
| bool | modifiesRegister (unsigned Reg, const TargetRegisterInfo *TRI) const |
| Return true if the MachineInstr modifies (fully define or partially define) the specified register. More... | |
| bool | registerDefIsDead (unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const |
| Returns true if the register is dead in this machine instruction. More... | |
| bool | hasRegisterImplicitUseOperand (unsigned Reg) const |
| Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers). More... | |
| int | findRegisterUseOperandIdx (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const |
| Returns the operand index that is a use of the specific register or -1 if it is not found. More... | |
| MachineOperand * | findRegisterUseOperand (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) |
| Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index. More... | |
| const MachineOperand * | findRegisterUseOperand (unsigned Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const |
| int | findRegisterDefOperandIdx (unsigned Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const |
| Returns the operand index that is a def of the specified register or -1 if it is not found. More... | |
| MachineOperand * | findRegisterDefOperand (unsigned Reg, bool isDead=false, const TargetRegisterInfo *TRI=nullptr) |
| Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index. More... | |
| int | findFirstPredOperandIdx () const |
| Find the index of the first operand in the operand list that is used to represent the predicate. More... | |
| int | findInlineAsmFlagIdx (unsigned OpIdx, unsigned *GroupNo=nullptr) const |
| Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction. More... | |
| const TargetRegisterClass * | getRegClassConstraint (unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const |
| Compute the static register class constraint for operand OpIdx. More... | |
| const TargetRegisterClass * | getRegClassConstraintEffectForVReg (unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const |
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC. More... | |
| const TargetRegisterClass * | getRegClassConstraintEffect (unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const |
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC. More... | |
| void | tieOperands (unsigned DefIdx, unsigned UseIdx) |
| Add a tie between the register operands at DefIdx and UseIdx. More... | |
| unsigned | findTiedOperandIdx (unsigned OpIdx) const |
| Given the index of a tied register operand, find the operand it is tied to. More... | |
| bool | isRegTiedToUseOperand (unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const |
| Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints. More... | |
| bool | isRegTiedToDefOperand (unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const |
| Return true if the use operand of the specified index is tied to a def operand. More... | |
| void | clearKillInfo () |
| Clears kill flags on all operands. More... | |
| void | substituteRegister (unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) |
| Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary. More... | |
| bool | addRegisterKilled (unsigned IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false) |
| We have determined MI kills a register. More... | |
| void | clearRegisterKills (unsigned Reg, const TargetRegisterInfo *RegInfo) |
| Clear all kill flags affecting Reg. More... | |
| bool | addRegisterDead (unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false) |
| We have determined MI defined a register without a use. More... | |
| void | clearRegisterDeads (unsigned Reg) |
Clear all dead flags on operands defining register Reg. More... | |
| void | setRegisterDefReadUndef (unsigned Reg, bool IsUndef=true) |
Mark all subregister defs of register Reg with the undef flag. More... | |
| void | addRegisterDefined (unsigned Reg, const TargetRegisterInfo *RegInfo=nullptr) |
| We have determined MI defines a register. More... | |
| void | setPhysRegsDeadExcept (ArrayRef< unsigned > UsedRegs, const TargetRegisterInfo &TRI) |
| Mark every physreg used by this instruction as dead except those in the UsedRegs list. More... | |
| bool | isSafeToMove (AliasAnalysis *AA, bool &SawStore) const |
| Return true if it is safe to move this instruction. More... | |
| bool | hasOrderedMemoryRef () const |
| Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available. More... | |
| bool | isDereferenceableInvariantLoad (AliasAnalysis *AA) const |
| Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function. More... | |
| unsigned | isConstantValuePHI () const |
| If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0. More... | |
| bool | hasUnmodeledSideEffects () const |
| Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc. More... | |
| bool | isLoadFoldBarrier () const |
| Returns true if it is illegal to fold a load across this instruction. More... | |
| bool | allDefsAreDead () const |
| Return true if all the defs of this instruction are dead. More... | |
| void | copyImplicitOps (MachineFunction &MF, const MachineInstr &MI) |
| Copy implicit register operands from specified instruction to this instruction. More... | |
| void | print (raw_ostream &OS, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const |
| void | print (raw_ostream &OS, ModuleSlotTracker &MST, bool SkipOpers=false, const TargetInstrInfo *TII=nullptr) const |
| void | dump (const TargetInstrInfo *TII=nullptr) const |
| void | addOperand (MachineFunction &MF, const MachineOperand &Op) |
| Add the specified operand to the instruction. More... | |
| void | addOperand (const MachineOperand &Op) |
| Add an operand without providing an MF reference. More... | |
| void | setDesc (const MCInstrDesc &tid) |
| Replace the instruction descriptor (thus opcode) of the current instruction with a new one. More... | |
| void | setDebugLoc (DebugLoc dl) |
| Replace current source information with new such. More... | |
| void | RemoveOperand (unsigned i) |
| Erase an operand from an instruction, leaving it with one fewer operand than it started with. More... | |
| void | addMemOperand (MachineFunction &MF, MachineMemOperand *MO) |
| Add a MachineMemOperand to the machine instruction. More... | |
| void | setMemRefs (mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) |
| Assign this MachineInstr's memory reference descriptor list. More... | |
| void | setMemRefs (std::pair< mmo_iterator, unsigned > NewMemRefs) |
| Assign this MachineInstr's memory reference descriptor list. More... | |
| std::pair< mmo_iterator, unsigned > | mergeMemRefsWith (const MachineInstr &Other) |
| Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of both MachineInstrs. More... | |
| void | dropMemRefs () |
| Clear this MachineInstr's memory reference descriptor list. More... | |
| void | untieRegOperand (unsigned OpIdx) |
| Break any tie involving OpIdx. More... | |
| void | addImplicitDefUseOperands (MachineFunction &MF) |
| Add all implicit def and use operands to this instruction. More... | |
Public Member Functions inherited from llvm::ilist_node_with_parent< MachineInstr, MachineBasicBlock, ilist_sentinel_tracking< true > > | |
| MachineInstr * | getPrevNode () |
| const MachineInstr * | getPrevNode () const |
Get the previous node, or nullptr for the list head. More... | |
| MachineInstr * | getNextNode () |
Get the next node, or nullptr for the list tail. More... | |
| const MachineInstr * | getNextNode () const |
Get the next node, or nullptr for the list tail. More... | |
Public Member Functions inherited from llvm::ilist_node_impl< ilist_detail::compute_node_options< MachineInstr, Options...>::type > | |
| self_iterator | getIterator () |
| const_self_iterator | getIterator () const |
| reverse_self_iterator | getReverseIterator () |
| const_reverse_self_iterator | getReverseIterator () const |
| bool | isSentinel () const |
| Check whether this is the sentinel node. More... | |
Friends | |
| struct | ilist_traits< MachineInstr > |
| struct | ilist_callback_traits< MachineBasicBlock > |
| class | MachineFunction |
Representation of each machine instruction.
This class isn't a POD type, but it must have a trivial destructor. When a MachineFunction is deleted, all the contained MachineInstrs are deallocated without having their destructor called.
Definition at line 52 of file MachineInstr.h.
Definition at line 293 of file MachineInstr.h.
Definition at line 56 of file MachineInstr.h.
iterator/begin/end - Iterate over all operands of a machine instruction.
Definition at line 292 of file MachineInstr.h.
Flags to specify different kinds of comments to output in assembly code.
These flags carry semantic information not otherwise easily derivable from the IR text.
| Enumerator | |
|---|---|
| ReloadReuse | |
Definition at line 62 of file MachineInstr.h.
| Enumerator | |
|---|---|
| CheckDefs | |
| CheckKillDead | |
| IgnoreDefs | |
| IgnoreVRegDefs | |
Definition at line 717 of file MachineInstr.h.
| Enumerator | |
|---|---|
| NoFlags | |
| FrameSetup | |
| FrameDestroy | |
| BundledPred | |
| BundledSucc | |
Definition at line 66 of file MachineInstr.h.
API for querying MachineInstr properties.
They are the same as MCInstrDesc queries but they are bundle aware.
| Enumerator | |
|---|---|
| IgnoreBundle | |
| AnyInBundle | |
| AllInBundle | |
Definition at line 380 of file MachineInstr.h.
| void MachineInstr::addImplicitDefUseOperands | ( | MachineFunction & | MF | ) |
Add all implicit def and use operands to this instruction.
Definition at line 691 of file MachineInstr.cpp.
Referenced by llvm::SIInstrInfo::FoldImmediate(), and llvm::SIInstrInfo::moveToVALU().
| void MachineInstr::addMemOperand | ( | MachineFunction & | MF, |
| MachineMemOperand * | MO | ||
| ) |
Add a MachineMemOperand to the machine instruction.
addMemOperand - Add a MachineMemOperand to the machine instruction.
This function should be used only occasionally. The setMemRefs function is the primary method for setting up a MachineInstr's MemRefs list.
Definition at line 914 of file MachineInstr.cpp.
References llvm::MachineFunction::allocateMemRefsArray().
Referenced by llvm::MachineInstrBuilder::addMemOperand(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::PPCInstrInfo::loadRegFromStackSlot(), and llvm::PPCInstrInfo::storeRegToStackSlot().
| void MachineInstr::addOperand | ( | MachineFunction & | MF, |
| const MachineOperand & | Op | ||
| ) |
Add the specified operand to the instruction.
addOperand - Add the specified operand to the instruction.
If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).
MF must be the machine function that was used to allocate this instruction.
MachineInstrBuilder provides a more convenient interface for creating instructions and adding operands.
If it is an implicit operand, it is added to the end of the operand list. If it is an explicit operand it is added at the end of the explicit operand list (before the first implicit operand).
Definition at line 792 of file MachineInstr.cpp.
References addOperand().
Referenced by llvm::MachineInstrBuilder::addBlockAddress(), llvm::MachineInstrBuilder::addCFIIndex(), llvm::MachineInstrBuilder::addCImm(), llvm::MachineInstrBuilder::addConstantPoolIndex(), llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addFPImm(), llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addIntrinsicID(), llvm::MachineInstrBuilder::addJumpTableIndex(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addMetadata(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addPredicate(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addRegMask(), llvm::MachineInstrBuilder::addSym(), llvm::MachineInstrBuilder::addTargetIndex(), llvm::HexagonPacketizerList::addToPacket(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), ConvertImplicitDefToConstZero(), copyExtraImplicitOps(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonFrameLowering::emitPrologue(), ImposeStackOrdering(), llvm::SIInstrInfo::moveToVALU(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::rewriteT2FrameIndex(), and llvm::AArch64InstructionSelector::select().
| void MachineInstr::addOperand | ( | const MachineOperand & | Op | ) |
Add an operand without providing an MF reference.
This only works for instructions that are inserted in a basic block.
MachineInstrBuilder and the two-argument addOperand(MF, MO) should be preferred.
Definition at line 769 of file MachineInstr.cpp.
| bool MachineInstr::addRegisterDead | ( | unsigned | Reg, |
| const TargetRegisterInfo * | RegInfo, | ||
| bool | AddIfNotFound = false |
||
| ) |
We have determined MI defined a register without a use.
Look for the operand that defines it and mark it as IsDead. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.
Definition at line 2079 of file MachineInstr.cpp.
References addOperand(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase::empty(), llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImplicit(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MCRegAliasIterator::isValid(), llvm::SmallVectorTemplateBase< T, isPodLike >::pop_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::MachineOperand::setIsDead().
Referenced by llvm::LiveVariables::addVirtualRegisterDead().
| void MachineInstr::addRegisterDefined | ( | unsigned | Reg, |
| const TargetRegisterInfo * | RegInfo = nullptr |
||
| ) |
We have determined MI defines a register.
Make sure there is an operand defining Reg.
Definition at line 2147 of file MachineInstr.cpp.
References addOperand(), llvm::MachineOperand::CreateReg(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineOperand::isReg().
Referenced by llvm::SparcInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), and llvm::LanaiInstrInfo::optimizeCompareInstr().
| bool MachineInstr::addRegisterKilled | ( | unsigned | IncomingReg, |
| const TargetRegisterInfo * | RegInfo, | ||
| bool | AddIfNotFound = false |
||
| ) |
We have determined MI kills a register.
Look for the operand that uses it and mark it as IsKill. If AddIfNotFound is true, add a implicit operand if it's not found. Returns true if the operand exists / is added.
Definition at line 2000 of file MachineInstr.cpp.
References addOperand(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::MachineOperand::CreateReg(), llvm::SmallVectorBase::empty(), llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isDebug(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), llvm::MCRegisterInfo::isSuperRegister(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::MCRegAliasIterator::isValid(), llvm::SmallVectorTemplateBase< T, isPodLike >::pop_back(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::MachineOperand::setIsKill().
Referenced by llvm::LiveIntervals::addKillFlags(), llvm::LiveVariables::addVirtualRegisterKilled(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::SparcInstrInfo::copyPhysReg(), llvm::ARMBaseInstrInfo::copyPhysReg(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::XCoreFrameLowering::emitPrologue(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), and ReplaceDominatedUses().
| bool MachineInstr::allDefsAreDead | ( | ) | const |
Return true if all the defs of this instruction are dead.
allDefsAreDead - Return true if all the defs of this instruction are dead.
Definition at line 1673 of file MachineInstr.cpp.
References llvm::MachineOperand::isDead(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().
| void MachineInstr::bundleWithPred | ( | ) |
Bundle this instruction with its predecessor.
This can be an unbundled instruction, or it can be the first instruction in a bundle.
Definition at line 1120 of file MachineInstr.cpp.
References assert(), and llvm::MachineOperand::Pred.
Referenced by llvm::MIBundleBuilder::insert(), and llvm::MIBundleBuilder::MIBundleBuilder().
| void MachineInstr::bundleWithSucc | ( | ) |
Bundle this instruction with its successor.
This can be an unbundled instruction, or it can be the last instruction in a bundle.
Definition at line 1129 of file MachineInstr.cpp.
References assert().
Referenced by llvm::MIBundleBuilder::insert().
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Return true for instructions that can be folded as memory operands in other instructions.
The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.
Definition at line 538 of file MachineInstr.h.
References llvm::MCID::FoldableAsLoad, and hasProperty().
Referenced by llvm::TargetInstrInfo::foldMemoryOperand().
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Clear specific AsmPrinter flags.
Definition at line 151 of file MachineInstr.h.
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Clear the AsmPrinter bitvector.
Definition at line 138 of file MachineInstr.h.
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clearFlag - Clear a MI flag.
Definition at line 177 of file MachineInstr.h.
References fuzzer::Flags.
Referenced by moveInstrOut(), and llvm::MachineBasicBlock::remove_instr().
| void MachineInstr::clearKillInfo | ( | ) |
Clears kill flags on all operands.
clearKillInfo - Clears kill flags on all operands.
Definition at line 1514 of file MachineInstr.cpp.
References llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), and llvm::MachineOperand::setIsKill().
Referenced by llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), and llvm::rdf::Liveness::resetKills().
| void MachineInstr::clearRegisterDeads | ( | unsigned | Reg | ) |
Clear all dead flags on operands defining register Reg.
Definition at line 2131 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::Reg, and llvm::MachineOperand::setIsDead().
Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().
| void MachineInstr::clearRegisterKills | ( | unsigned | Reg, |
| const TargetRegisterInfo * | RegInfo | ||
| ) |
Clear all kill flags affecting Reg.
If RegInfo is provided, this includes all aliasing registers.
Definition at line 2066 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::TargetRegisterInfo::regsOverlap(), and llvm::MachineOperand::setIsKill().
Referenced by llvm::LiveIntervals::addKillFlags().
| void MachineInstr::copyImplicitOps | ( | MachineFunction & | MF, |
| const MachineInstr & | MI | ||
| ) |
Copy implicit register operands from specified instruction to this instruction.
copyImplicitOps - Copy implicit register operands from specified instruction to this instruction.
Definition at line 1685 of file MachineInstr.cpp.
References addOperand(), getDesc(), llvm::MCInstrDesc::getNumOperands(), getNumOperands(), getOperand(), i, llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isRegMask().
Referenced by llvm::MachineInstrBuilder::copyImplicitOps().
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Return true if the MachineInstr fully defines the specified register.
If TargetRegisterInfo is passed, then it also checks if there is a def of a super-register. NOTE: It's ignoring subreg indices on virtual registers.
Definition at line 895 of file MachineInstr.h.
References findRegisterDefOperandIdx().
Referenced by llvm::ARMBaseInstrInfo::breakPartialRegDependency(), checkAndUpdateEFLAGSKill(), convertFlagSettingOpcode(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), getImplicitSPRUseForDPRUse(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), ImposeStackOrdering(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), IsSafeToMove(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::AArch64InstrInfo::optimizeCompareInstr(), and llvm::PPCInstrInfo::optimizeCompareInstr().
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Returns a range over all explicit operands that are register definitions.
Implicit definition are not included!
Definition at line 323 of file MachineInstr.h.
References getDesc(), llvm::make_range(), and operands_begin().
Referenced by addDefsToList().
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Returns a range over all explicit operands that are register definitions.
Implicit definition are not included!
Definition at line 328 of file MachineInstr.h.
References getDesc(), llvm::make_range(), and operands_begin().
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Clear this MachineInstr's memory reference descriptor list.
This resets the memrefs to their most conservative state. This should be used only as a last resort since it greatly pessimizes our knowledge of the memory access performed by the instruction.
Definition at line 1227 of file MachineInstr.h.
| LLVM_DUMP_METHOD void MachineInstr::dump | ( | const TargetInstrInfo * | TII = nullptr | ) | const |
Definition at line 1695 of file MachineInstr.cpp.
References llvm::dbgs(), and llvm::MachineOperand::print().
Referenced by llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::cleanUpDotCur(), llvm::ScheduleDAGInstrs::dumpNode(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::HexagonLowerToMC(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::HexagonInstrInfo::isLateInstrFeedsEarlyInstr(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::AVRMCInstLower::lowerInstruction(), llvm::LowerPPCMachineInstrToMCInst(), MoveAndTeeForMultiUse(), MoveForSingleUse(), llvm::AggressiveAntiDepBreaker::Observe(), llvm::HexagonInstrInfo::PredicateInstruction(), RematerializeCheapDef(), and llvm::HexagonInstrInfo::reversePredSense().
| void MachineInstr::emitError | ( | StringRef | Msg | ) | const |
Emit an error referring to the source location of this instruction.
This should only be used for inline assembly that is somehow impossible to compile. Other errors should have been handled much earlier.
If this method returns, the caller should try to recover from the error.
Definition at line 2206 of file MachineInstr.cpp.
References llvm::MachineOperand::CI, llvm::MachineOperand::getMetadata(), llvm::MDNode::getNumOperands(), llvm::MDNode::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::ConstantInt::getZExtValue(), i, llvm::MachineOperand::isMetadata(), llvm::MachineOperand::MBB, and llvm::report_fatal_error().
Referenced by llvm::RegAllocBase::allocatePhysRegs().
| void MachineInstr::eraseFromBundle | ( | ) |
Unlink 'this' form its basic block and delete it.
If the instruction is part of a bundle, the other instructions in the bundle remain bundled.
Definition at line 1100 of file MachineInstr.cpp.
References assert(), and llvm::MachineOperand::getParent().
| void MachineInstr::eraseFromParent | ( | ) |
Unlink 'this' from the containing basic block and delete it.
If this instruction is the header of a bundle, the whole bundle is erased. This function can not be used for instructions inside a bundle, use eraseFromBundle() to erase individual bundled instructions.
Definition at line 1075 of file MachineInstr.cpp.
References assert(), and llvm::MachineOperand::getParent().
Referenced by llvm::SparcInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::ARMBaseInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::Legalizer::combineExtracts(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AArch64TargetLowering::EmitF128CSEL(), emitIndirectDst(), emitIndirectSrc(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), emitMonitor(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), emitRDPKRU(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitWRPKRU(), emitXBegin(), llvm::rdf::DeadCodeElimination::erase(), eraseFromParentAndMarkDBGValuesForRemoval(), eraseIfDead(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::LegalizerHelper::fewerElementsVector(), llvm::fixStackStores(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), HandleVRSaveUpdate(), INITIALIZE_PASS(), llvm::X86FrameLowering::inlineStackProbe(), llvm::LegalizerHelper::libcall(), llvm::LegalizerHelper::lower(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::HexagonInstrInfo::reduceLoopCount(), RematerializeCheapDef(), llvm::FastISel::removeDeadCode(), removeIPMBasedCompare(), RemoveVRSaveCode(), llvm::rewriteAArch64FrameIndex(), llvm::FixFSMULD::runOnMachineFunction(), llvm::ReplaceFMULS::runOnMachineFunction(), llvm::AArch64InstructionSelector::select(), llvm::FastISel::selectPatchpoint(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tryOptimizeLEAtoMOV(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), and llvm::LegalizerHelper::widenScalar().
| void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval | ( | ) |
Unlink 'this' from the containing basic block and delete it.
For all definitions mark their uses in DBG_VALUE nodes as undefined. Otherwise like eraseFromParent().
Definition at line 1080 of file MachineInstr.cpp.
References assert(), eraseFromParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), llvm::MachineOperand::MBB, MI, operands(), and llvm::MachineOperand::Reg.
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Definition at line 307 of file MachineInstr.h.
References getNumExplicitOperands(), llvm::make_range(), and operands_begin().
Referenced by implicit_operands(), and llvm::AMDGPUMCInstLower::lower().
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Definition at line 311 of file MachineInstr.h.
References getNumExplicitOperands(), llvm::make_range(), and operands_begin().
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Definition at line 343 of file MachineInstr.h.
References getDesc(), getNumExplicitOperands(), llvm::make_range(), and operands_begin().
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Definition at line 347 of file MachineInstr.h.
References getDesc(), getNumExplicitOperands(), llvm::make_range(), and operands_begin().
| int MachineInstr::findFirstPredOperandIdx | ( | ) | const |
Find the index of the first operand in the operand list that is used to represent the predicate.
findFirstPredOperandIdx() - Find the index of the first operand in the operand list that is used to represent the predicate.
It returns -1 if none is found.
Definition at line 1402 of file MachineInstr.cpp.
References llvm::HexagonMCInstrInfo::getDesc(), i, llvm::MCInstrDesc::isPredicable(), llvm::MCOperandInfo::isPredicate(), and llvm::MCInstrDesc::OpInfo.
Referenced by llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::getInstrPredicate(), llvm::ARMBaseInstrInfo::getPredicate(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::R600InstrInfo::isPredicated(), llvm::ARMBaseInstrInfo::PredicateInstruction(), and llvm::R600InstrInfo::PredicateInstruction().
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instruction.
Returns -1 if getOperand(OpIdx) does not belong to an inline asm operand group.
If GroupNo is not NULL, it will receive the number of the operand group containing OpIdx.
The flag operand is an immediate that can be decoded with methods like InlineAsm::hasRegClassConstraint().
Definition at line 1171 of file MachineInstr.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::InlineAsm::getNumOperandRegisters(), i, llvm::MachineOperand::isImm(), and llvm::InlineAsm::MIOp_FirstOperand.
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Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an index.
Definition at line 952 of file MachineInstr.h.
References findRegisterDefOperandIdx(), and getOperand().
Referenced by llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), and transferDeadCC().
| int MachineInstr::findRegisterDefOperandIdx | ( | unsigned | Reg, |
| bool | isDead = false, |
||
| bool | Overlap = false, |
||
| const TargetRegisterInfo * | TRI = nullptr |
||
| ) | const |
Returns the operand index that is a def of the specified register or -1 if it is not found.
findRegisterDefOperandIdx() - Returns the operand index that is a def of the specified register or -1 if it is not found.
If isDead is true, defs that are not dead are skipped. If Overlap is true, then it also looks for defs that merely overlap the specified register. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register. This may also return a register mask operand when Overlap is true.
If isDead is true, defs that are not dead are skipped. If TargetRegisterInfo is non-null, then it also checks if there is a def of a super-register.
Definition at line 1373 of file MachineInstr.cpp.
References llvm::MachineOperand::clobbersPhysReg(), llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MCRegisterInfo::isSubRegister(), llvm::MachineOperand::Reg, and llvm::TargetRegisterInfo::regsOverlap().
Referenced by canFoldIntoCSel(), llvm::R600InstrInfo::definesAddressRegister(), definesRegister(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), findRegisterDefOperand(), getMaddPatterns(), modifiesRegister(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), and registerDefIsDead().
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Wrapper for findRegisterUseOperandIdx, it returns a pointer to the MachineOperand rather than an index.
Definition at line 927 of file MachineInstr.h.
References findRegisterUseOperandIdx(), getOperand(), and isKill().
Referenced by findRegisterUseOperand().
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Definition at line 933 of file MachineInstr.h.
References findRegisterUseOperand(), and isKill().
| int MachineInstr::findRegisterUseOperandIdx | ( | unsigned | Reg, |
| bool | isKill = false, |
||
| const TargetRegisterInfo * | TRI = nullptr |
||
| ) | const |
Returns the operand index that is a use of the specific register or -1 if it is not found.
findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of the specific register or -1 if it is not found.
It further tightens the search criteria to a use that kills the register if isKill is true.
Definition at line 1322 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MCRegisterInfo::isSubRegister(), and llvm::MachineOperand::isUse().
Referenced by findCondCodeUsedByInstr(), findRegisterUseOperand(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), killsRegister(), readsRegister(), and llvm::R600InstrInfo::usesAddressRegister().
Given the index of a tied register operand, find the operand it is tied to.
Defs are tied to uses and vice versa. Returns the index of the tied operand which must exist.
Definition at line 1457 of file MachineInstr.cpp.
References assert(), llvm::MachineOperand::getImm(), llvm::InlineAsm::getNumOperandRegisters(), i, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), llvm::InlineAsm::isUseOperandTiedToDef(), llvm_unreachable, llvm::InlineAsm::MIOp_FirstOperand, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by hasComplexRegisterTies(), isRegTiedToDefOperand(), isRegTiedToUseOperand(), llvm::MIPrinter::print(), and untieRegOperand().
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Return whether an AsmPrinter flag is set.
Definition at line 141 of file MachineInstr.h.
Referenced by emitComments().
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Return the asm printer flags bitvector.
Definition at line 135 of file MachineInstr.h.
Referenced by llvm::X86AsmPrinter::EmitInstruction().
| unsigned MachineInstr::getBundleSize | ( | ) | const |
Return the number of instructions inside the MI bundle, excluding the bundle header.
Return the number of instructions inside the MI bundle, not counting the header instruction.
This is the number of instructions that MachineBasicBlock::iterator skips, 0 for unbundled instructions.
Definition at line 1298 of file MachineInstr.cpp.
References I.
| const DIExpression * MachineInstr::getDebugExpression | ( | ) | const |
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition at line 1204 of file MachineInstr.cpp.
References assert().
Referenced by emitDebugValueComment(), getDebugLocValue(), llvm::DbgVariable::initializeDbgValue(), and llvm::SelectionDAGISel::runOnMachineFunction().
Returns the debug location id of this MachineInstr.
Definition at line 250 of file MachineInstr.h.
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), attachMEMCPYScratchRegs(), llvm::CodeViewDebug::beginInstruction(), llvm::DwarfDebug::beginInstruction(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::classifyLEAReg(), CombineCVTAToLocal(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::constrainOperandRegClass(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AArch64TargetLowering::EmitF128CSEL(), emitIndirectDst(), emitIndirectSrc(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::NVPTXAsmPrinter::emitLineNumberAsDotLoc(), emitMonitor(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), emitRDPKRU(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitWRPKRU(), emitXBegin(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::fixStackStores(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), forceReg(), FuseInst(), FuseTwoAddrInst(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::HexagonHazardRecognizer::getHazardType(), HandleVRSaveUpdate(), INITIALIZE_PASS(), llvm::DbgVariable::initializeDbgValue(), insertCopy(), insertDivByZeroTrap(), InsertFPConstInst(), InsertFPImmInst(), insertNopBeforeInstruction(), insertPHI(), InsertSPConstInst(), InsertSPImmInst(), isIdenticalTo(), llvm::SIInstrInfo::legalizeOperands(), loadM0FromVGPR(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), MakeM0Inst(), MaybeRewriteToFallthrough(), MoveAndTeeForMultiUse(), llvm::SIInstrInfo::moveToVALU(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), llvm::TargetInstrInfo::reassociateOps(), llvm::HexagonInstrInfo::reduceLoopCount(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::rewriteAArch64FrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::AArch64InstructionSelector::select(), llvm::ARMBaseInstrInfo::setExecutionDomain(), setM0ToIndexFromSGPR(), tryOptimizeLEAtoMOV(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), and llvm::X86InstrInfo::unfoldMemoryOperand().
| const DILocalVariable * MachineInstr::getDebugVariable | ( | ) | const |
Return the debug variable referenced by this DBG_VALUE instruction.
Definition at line 1199 of file MachineInstr.cpp.
References assert().
Referenced by llvm::MachineInstrBuilder::addMetadata(), emitDebugValueComment(), llvm::DbgVariable::initializeDbgValue(), and llvm::SelectionDAGISel::runOnMachineFunction().
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Returns the target instruction descriptor of this MachineInstr.
Definition at line 270 of file MachineInstr.h.
Referenced by llvm::addFrameReference(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::TargetInstrInfo::analyzeSelect(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::DFAPacketizer::canReserveResources(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::TargetSchedModel::computeOperandLatency(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), copyImplicitOps(), defs(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::Mips16InstrInfo::expandPostRAPseudo(), llvm::MipsSEInstrInfo::expandPostRAPseudo(), explicit_uses(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), FuseTwoAddrInst(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::LegalizerInfo::getAction(), llvm::HexagonInstrInfo::getAddrMode(), llvm::HexagonInstrInfo::getCExtOpNum(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::X86InstrInfo::getExecutionDomain(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::ARMHazardRecognizer::getHazardType(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::ScheduleDAG::getInstrDesc(), llvm::PPCInstrInfo::getInstrLatency(), llvm::TargetInstrInfo::getInstrLatency(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), getLSMultipleTransferSize(), llvm::HexagonInstrInfo::getMaxValue(), llvm::HexagonInstrInfo::getMemAccessSize(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), getMemoryOpOffset(), llvm::HexagonInstrInfo::getMinValue(), llvm::HexagonInstrInfo::getNonExtOpcode(), llvm::TargetSchedModel::getNumMicroOps(), llvm::ARMBaseInstrInfo::getNumMicroOps(), llvm::TargetInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getOperandLatency(), getPostIncrementOperand(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::HexagonInstrInfo::getSize(), getTargetMBB(), getTruncatedShiftCount(), llvm::HexagonInstrInfo::getType(), getTypeToPrint(), llvm::HexagonInstrInfo::getUnits(), hasComplexRegisterTies(), llvm::MipsInstrInfo::HasForbiddenSlot(), llvm::TargetInstrInfo::hasLowDefLatency(), llvm::HexagonInstrInfo::hasNonExtEquivalent(), hasProperty(), hasRAWHazard(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), llvm::HexagonInstrInfo::isAccumulator(), llvm::HexagonInstrInfo::isComplex(), llvm::HexagonInstrInfo::isConditionalLoad(), llvm::HexagonInstrInfo::isConstExtended(), isControlFlow(), llvm::HexagonInstrInfo::isDependent(), llvm::SIInstrInfo::isDisableWQM(), llvm::SIInstrInfo::isDPP(), llvm::SIInstrInfo::isDS(), llvm::HexagonInstrInfo::isEarlySourceInstr(), llvm::SIInstrInfo::isEXP(), llvm::HexagonInstrInfo::isExtendable(), llvm::HexagonInstrInfo::isExtended(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::SIInstrInfo::isFixedSize(), llvm::SIInstrInfo::isFLAT(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), llvm::SIInstrInfo::isGather4(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), llvm::SIInstrInfo::isInlineConstant(), llvm::HexagonInstrInfo::isLateResultInstr(), llvm::HexagonInstrInfo::isLateSourceInstr(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::NVPTXInstrInfo::isLoadInstr(), llvm::SIInstrInfo::isMIMG(), llvm::NVPTXInstrInfo::isMoveInstr(), llvm::SIInstrInfo::isMTBUF(), llvm::SIInstrInfo::isMUBUF(), llvm::HexagonInstrInfo::isNewValue(), llvm::HexagonInstrInfo::isNewValueStore(), llvm::HexagonInstrInfo::isOperandExtended(), llvm::SIInstrInfo::isOperandLegal(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicable(), llvm::TargetInstrInfo::isPredicable(), llvm::HexagonInstrInfo::isPredicated(), llvm::HexagonInstrInfo::isPredicatedNew(), llvm::HexagonInstrInfo::isPredicatedTrue(), isSafeToFold(), llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isScalarStore(), llvm::SIInstrInfo::isScalarUnit(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::SIInstrInfo::isSGPRSpill(), isSimpleBD12Move(), isSimpleMove(), llvm::SIInstrInfo::isSMRD(), llvm::HexagonInstrInfo::isSolo(), llvm::SIInstrInfo::isSOP1(), llvm::SIInstrInfo::isSOP2(), llvm::SIInstrInfo::isSOPC(), llvm::SIInstrInfo::isSOPK(), llvm::SIInstrInfo::isSOPP(), llvm::NVPTXInstrInfo::isStoreInstr(), llvm::HexagonInstrInfo::isTC1(), llvm::HexagonInstrInfo::isTC2(), llvm::HexagonInstrInfo::isTC2Early(), llvm::HexagonInstrInfo::isTC4x(), llvm::TargetInstrInfo::isTriviallyReMaterializable(), llvm::SIInstrInfo::isVALU(), llvm::SIInstrInfo::isVGPRSpill(), llvm::SIInstrInfo::isVOP1(), llvm::SIInstrInfo::isVOP2(), llvm::SIInstrInfo::isVOP3(), llvm::SIInstrInfo::isVOPC(), llvm::SIInstrInfo::isWQM(), llvm::HexagonInstrInfo::mayBeCurLoad(), llvm::HexagonInstrInfo::mayBeNewStore(), OneUseDominatesOtherUses(), llvm::SystemZInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::DFAPacketizer::reserveResources(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::TargetSchedModel::resolveSchedClass(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), RewriteP2Align(), llvm::rewriteT2FrameIndex(), llvm::MipsInstrInfo::SafeInForbiddenSlot(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), llvm::SIInstrInfo::sopkIsZext(), stripExtraCopyOperands(), tieOpsIfNeeded(), uses(), llvm::SIInstrInfo::usesVM_CNT(), and llvm::SIInstrInfo::verifyInstruction().
Return whether an MI flag is set.
Definition at line 161 of file MachineInstr.h.
References fuzzer::Flags.
Referenced by llvm::CodeViewDebug::beginInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), isBundledWithPred(), isBundledWithSucc(), isInsideBundle(), and llvm::MIPrinter::print().
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Return the MI flags bitvector.
Definition at line 156 of file MachineInstr.h.
References fuzzer::Flags.
| InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect | ( | ) | const |
Definition at line 1165 of file MachineInstr.cpp.
References assert(), llvm::InlineAsm::Extra_AsmDialect, and llvm::InlineAsm::MIOp_ExtraInfo.
Referenced by isMSInlineAsm().
| unsigned MachineInstr::getNumExplicitOperands | ( | ) | const |
Returns the number of non-implicit operands.
getNumExplicitOperands - Returns the number of non-implicit operands.
Definition at line 1107 of file MachineInstr.cpp.
References i, llvm::MachineOperand::isImplicit(), and llvm::MachineOperand::isReg().
Referenced by llvm::HexagonInstrInfo::analyzeBranch(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), explicit_operands(), explicit_uses(), fixupCalleeSaveRestoreStackOffset(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getTypeToPrint(), isCompareZero(), llvm::AArch64InstructionSelector::select(), and llvm::SIInstrInfo::verifyInstruction().
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Access to explicit operands of the instruction.
Definition at line 277 of file MachineInstr.h.
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::EHStreamer::callToNoUnwindFunction(), canCombine(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldCopy(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), clobbersCTR(), llvm::Legalizer::combineExtracts(), commuteVPTERNLOG(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), copyImplicitOps(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::BPFRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), EmitGCCInlineAsmStr(), llvm::X86AsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), emitKill(), EmitMSInlineAsmStr(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), eraseGPOpnd(), llvm::HexagonEvaluator::evaluate(), findCorrespondingPred(), finishConvertToThreeAddress(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::PPCInstrInfo::FoldImmediate(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), FuseInst(), FuseTwoAddrInst(), getCallTargetRegOpnd(), getDebugLocValue(), getFrameIndexOperandNum(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::HexagonHazardRecognizer::getHazardType(), getInitPhiReg(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::PPCInstrInfo::getInstrLatency(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), getInstrVecReg(), getLoopPhiReg(), getLSMultipleTransferSize(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getOperand(), getPHIDeps(), getPhiRegs(), llvm::getPHISrcRegOpIdx(), llvm::LEONMachineFunctionPass::GetRegIndexForOperand(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::HexagonInstrInfo::getSize(), getStoreValueOperand(), HandleVRSaveUpdate(), hasComplexRegisterTies(), HashMachineInstr(), llvm::X86InstrInfo::hasLiveCondCodeDef(), llvm::X86InstrInfo::hasReassociableOperands(), hasVGPROperands(), llvm::HexagonLowerToMC(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::WebAssembly::isChild(), isCSRestore(), isDescribedByReg(), isIdenticalTo(), llvm::isLeaMem(), llvm::isMem(), llvm::SIInstrInfo::isOperandLegal(), isSafeToFold(), isSourceDefinedByImplicitDef(), llvm::ARMBaseInstrInfo::isSwiftFastImmShift(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTwoAddrUse(), llvm::SIInstrInfo::legalizeOperands(), llvm::XCoreMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LowerARMMachineInstrToMCInst(), llvm::LowerPPCMachineInstrToMCInst(), llvm::LowerSparcMachineInstrToMCInst(), llvm::SIInstrInfo::moveToVALU(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseOperands(), llvm::PatchPointOpers::PatchPointOpers(), phiHasBreakDef(), phiHasVGPROperands(), llvm::HexagonInstrInfo::predCanBeUsedAsDotNew(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::printMemOperand(), llvm::MipsAsmPrinter::printRegisterList(), llvm::ARMBaseInstrInfo::produceSameValue(), removeKillInfo(), removeOperands(), removePhis(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), resultTests(), llvm::rewriteT2FrameIndex(), llvm::FixFSMULD::runOnMachineFunction(), llvm::ReplaceFMULS::runOnMachineFunction(), llvm::DetectRoundChange::runOnMachineFunction(), llvm::AArch64InstructionSelector::select(), llvm::X86InstrInfo::setSpecialOperandAttr(), sizeOfSPAdjustment(), llvm::StackMapOpers::StackMapOpers(), stripExtraCopyOperands(), TrackDefUses(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::X86InstrInfo::unfoldMemoryOperand(), UpdateOperandRegClass(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::ValueIsNewPHI(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and llvm::MachineRegisterInfo::verifyUseList().
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Returns the opcode of this MachineInstr.
Definition at line 273 of file MachineInstr.h.
References llvm::MCInstrDesc::Opcode.
Referenced by llvm::R600InstrInfo::addFlag(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::R600InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), llvm::LanaiInstrInfo::analyzeSelect(), llvm::ARMBaseInstrInfo::analyzeSelect(), areCandidatesToMergeOrPair(), areCombinableOperations(), BBIsJumpedOver(), branchTargetOperand(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), llvm::R600InstrInfo::canBeConsideredALU(), canCombine(), canCompareBeNewValueJump(), canDefBePartOfLOH(), canFoldIntoCSel(), canInstrSubstituteCmpInstr(), cannotCoexistAsymm(), llvm::SIInstrInfo::canReadVGPR(), canShrink(), changesVGPRIndexingMode(), llvm::R600InstrInfo::clearFlag(), llvm::Legalizer::combineExtracts(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteOpcode(), convertFlagSettingOpcode(), ConvertImplicitDefToConstZero(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::R600InstrInfo::DefinesPredicate(), llvm::HexagonPacketizerList::demoteToDotOld(), doesNotGeneratecode(), llvm::HexagonInstrInfo::doesNotReturn(), llvm::SystemZHazardRecognizer::dumpSU(), llvm::ARMBaseInstrInfo::duplicate(), llvm::SparcFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::HexagonFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::Mips16TargetLowering::EmitInstrWithCustomInserter(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::MipsSETargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::SparcTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::SystemZTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::HexagonFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), ExpandMOVImmSExti8(), llvm::SparcInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::LegalizerHelper::fewerElementsVector(), llvm::PPCInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), findCondCodeUsedByInstr(), findFirstPredicateSetterFrom(), llvm::R600InstrInfo::fitsConstReadLimitations(), fixupCalleeSaveRestoreStackOffset(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::HexagonInstrInfo::getAbsoluteForm(), llvm::LegalizerInfo::getAction(), llvm::HexagonInstrInfo::getBaseWithLongOffset(), llvm::HexagonInstrInfo::getBaseWithRegOffset(), llvm::SIInstrInfo::getBranchDestBlock(), llvm::AArch64InstrInfo::getBranchDestBlock(), llvm::SystemZInstrInfo::getBranchInfo(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), getCopyRewriter(), llvm::HexagonInstrInfo::getDotCurOp(), llvm::HexagonInstrInfo::getDotNewOp(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), llvm::HexagonInstrInfo::getDotNewPredOp(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), llvm::HexagonInstrInfo::getEquivalentHWInstr(), llvm::ARMBaseInstrInfo::getExecutionDomain(), llvm::X86InstrInfo::getExecutionDomain(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::R600InstrInfo::getFlagOp(), llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands(), getFMAPatterns(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::ARMHazardRecognizer::getHazardType(), llvm::HexagonHazardRecognizer::getHazardType(), llvm::GCNHazardRecognizer::getHazardType(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::PPCInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::getITInstrPredicate(), getLSMultipleTransferSize(), getMaddPatterns(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfs(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getMemoryOpOffset(), getMemScale(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), getNewValueJumpOpcode(), llvm::HexagonInstrInfo::getNonExtOpcode(), GetNonPseudoCallIndirectOpcode(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getNumMicroOpsSwiftLdSt(), llvm::SIInstrInfo::getNumWaitStates(), getOffsetONFromFION(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::getOpRegClass(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::HexagonInstrInfo::getPseudoInstrPair(), llvm::HexagonInstrInfo::getRegForm(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::HexagonInstrInfo::getSize(), llvm::TargetInstrInfo::getSPAdjust(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getStartOrEndSlot(), getStoreOffset(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::SIInstrInfo::getVALUOp(), getWinAllocaAmount(), handleMiddleInst(), handleUse(), llvm::AArch64InstrInfo::hasExtendedReg(), llvm::X86InstrInfo::hasHighOperandLatency(), HashMachineInstr(), llvm::HexagonInstrInfo::hasNonExtEquivalent(), llvm::HexagonInstrInfo::hasPseudoInstrPair(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::AArch64InstrInfo::hasShiftedReg(), llvm::HexagonLowerToMC(), llvm::NVPTXAsmPrinter::ignoreLoc(), INITIALIZE_PASS(), InsertFPConstInst(), InsertFPImmInst(), InsertSPConstInst(), InsertSPImmInst(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::isAArch64FrameOffsetLegal(), llvm::WebAssembly::isArgument(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::PPCInstrInfo::isAssociativeAndCommutative(), llvm::AArch64InstrInfo::isAssociativeAndCommutative(), llvm::X86InstrInfo::isAssociativeAndCommutative(), llvm::AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(), isBundle(), isCandidateLoad(), isCandidateStore(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isCFIInstruction(), isCMOVPseudo(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), llvm::PPCInstrInfo::isCoalescableExtInstr(), llvm::X86InstrInfo::isCoalescableExtInstr(), isCombineInstrCandidateFP(), isCompareZero(), llvm::HexagonInstrInfo::isConditionalALU32(), llvm::HexagonInstrInfo::isConditionalLoad(), llvm::HexagonInstrInfo::isConditionalStore(), llvm::HexagonInstrInfo::isConditionalTransfer(), llvm::WebAssembly::isCopy(), isCopy(), isCopy(), isCopyToExec(), isCrossCopy(), isCSRestore(), isCVTAToLocalCombinationCandidate(), llvm::HexagonInstrInfo::isDeallocRet(), isDebugValue(), isDefConvertible(), isDirectJump(), llvm::HexagonInstrInfo::isDotCurInst(), isEHLabel(), isEligibleForITBlock(), llvm::HexagonInstrInfo::isExtendable(), isExtractSubreg(), isFirstInstructionInSequence(), llvm::HexagonInstrInfo::isFloat(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), isFuncletReturnInstr(), isGCLabel(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), isHardwareLoop(), isHighLatencyCPSR(), llvm::SIInstrInfo::isHighLatencyInstruction(), isIdenticalTo(), llvm::SIInstrInfo::isImmOperandLegal(), isImplicitDef(), isIncrementOrDecrement(), llvm::HexagonInstrInfo::isIndirectCall(), llvm::HexagonInstrInfo::isIndirectL4Return(), isInlineAsm(), isInsertSubreg(), llvm::HexagonInstrInfo::isJumpR(), llvm::HexagonInstrInfo::isJumpWithinBranchRange(), isKill(), llvm::HexagonInstrInfo::isLateResultInstr(), isLEA(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLoadAbsSet(), isLoadAndTestAsCmp(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlotPostFE(), llvm::X86InstrInfo::isLoadFromStackSlotPostFE(), llvm::HexagonInstrInfo::isLoopN(), llvm::SIInstrInfo::isLowLatencyInstruction(), isMatchingStore(), llvm::HexagonInstrInfo::isMemOp(), isMemoryOp(), isMla(), isMSInlineAsm(), isMul(), isNonFoldablePartialRegisterLoad(), llvm::AArch64InstrInfo::isPairableLdStInst(), isPairedLdSt(), isPHI(), isPhysicalRegCopy(), llvm::R600InstrInfo::isPredicable(), llvm::SystemZInstrInfo::isPredicable(), llvm::PPCInstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), isPromotableZeroStoreInst(), isPushPop(), llvm::WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(), llvm::SIInstrInfo::isReallyTriviallyReMaterializable(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRedundantFlagInstr(), llvm::R600InstrInfo::isRegisterLoad(), llvm::R600InstrInfo::isRegisterStore(), isRegSequence(), llvm::VLIWResourceModel::isResourceAvailable(), isSafeToFold(), isSafeToFoldImmIntoCopy(), llvm::HexagonInstrInfo::isSaveCalleeSavedRegsCall(), llvm::AArch64InstrInfo::isScaledAddr(), isSchedBarrier(), llvm::SIInstrInfo::isSchedulingBoundary(), isSecondInstructionInSequence(), isSExtLoad(), isShift(), llvm::HexagonInstrInfo::isSignExtendingLoad(), isSimpleIndexCalc(), llvm::HexagonPacketizerList::isSoloInstruction(), llvm::HexagonInstrInfo::isSpillPredRegOp(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlotPostFE(), isSubregToReg(), isSuitableForMask(), isSystemInstr(), llvm::X86InstrInfo::isTailCall(), llvm::WebAssembly::isTee(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTransformable(), isTransient(), llvm::R600InstrInfo::isTransOnly(), llvm::TargetInstrInfo::isTriviallyReMaterializable(), llvm::AArch64InstrInfo::isUnscaledLdSt(), isUseDefConvertible(), llvm::HexagonInstrInfo::isVecALU(), llvm::R600InstrInfo::isVector(), llvm::R600InstrInfo::isVectorOnly(), llvm::HexagonInstrInfo::isZeroExtendingLoad(), isZExtLoad(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::LegalizerHelper::libcall(), llvm::XCoreMCInstLower::Lower(), llvm::SystemZMCInstLower::lower(), llvm::MipsMCInstLower::Lower(), llvm::MSP430MCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::AArch64MCInstLower::Lower(), llvm::AMDGPUMCInstLower::lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LegalizerHelper::lower(), llvm::LowerARMMachineInstrToMCInst(), llvm::AVRMCInstLower::lowerInstruction(), llvm::LowerPPCMachineInstrToMCInst(), llvm::LowerSparcMachineInstrToMCInst(), MatchingStackOffset(), mayCombineMisaligned(), llvm::mayOptimizeThumb2Instruction(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), needsStackFrame(), llvm::rdf::operator<<(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseCondBranch(), phiHasBreakDef(), llvm::HexagonInstrInfo::predCanBeUsedAsDotNew(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::GCNHazardRecognizer::PreEmitNoops(), llvm::MIPrinter::print(), llvm::MipsAsmPrinter::printMemOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), Query(), llvm::R600InstrInfo::readsLDSSrcReg(), readsVCCZ(), llvm::TargetInstrInfo::reassociateOps(), llvm::StackMaps::recordPatchPoint(), llvm::StackMaps::recordStackMap(), llvm::StackMaps::recordStatepoint(), llvm::HexagonInstrInfo::reduceLoopCount(), regIsPICBase(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), removeIPMBasedCompare(), removeModOperands(), removeTerminatorBit(), llvm::VLIWResourceModel::reserveResources(), resultTests(), llvm::HexagonInstrInfo::reversePredSense(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), RewriteP2Align(), llvm::rewriteT2FrameIndex(), llvm::InsertNOPLoad::runOnMachineFunction(), llvm::FixFSMULD::runOnMachineFunction(), llvm::ReplaceFMULS::runOnMachineFunction(), llvm::DetectRoundChange::runOnMachineFunction(), llvm::FixAllFDIVSQRT::runOnMachineFunction(), llvm::RegBankSelect::runOnMachineFunction(), llvm::ARMInstructionSelector::select(), llvm::AArch64InstructionSelector::select(), selectCopy(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), sForm(), llvm::AArch64InstrInfo::shouldClusterMemOps(), shouldReadExec(), llvm::AArch64InstrInfo::shouldScheduleAdjacent(), llvm::X86InstrInfo::shouldScheduleAdjacent(), shrinkScalarCompare(), sizeOfSPAdjustment(), supportLoadFromLiteral(), toggleBundleKillFlag(), tryAddToFoldList(), tryConstantFoldOp(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::HexagonPacketizerList::useCalleesSP(), llvm::HexagonPacketizerList::useCallersSP(), usesIXAddr(), llvm::R600InstrInfo::usesTextureCache(), llvm::R600InstrInfo::usesVertexCache(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::LegalizerHelper::widenScalar(), and llvm::HexagonInstrInfo::xformRegToImmOffset().
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Definition at line 279 of file MachineInstr.h.
References assert(), getNumOperands(), and i.
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::HexagonPacketizerList::addToPacket(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::ScheduleDAGInstrs::addVRegUseDeps(), adjustDefLatency(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::R600InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), llvm::LanaiInstrInfo::analyzeSelect(), llvm::ARMBaseInstrInfo::analyzeSelect(), llvm::RegisterBankInfo::applyDefaultMapping(), areCombinableOperations(), attachMEMCPYScratchRegs(), BBIsJumpedOver(), biasPhysRegCopy(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), llvm::EHStreamer::callToNoUnwindFunction(), canBeExpandedToORR(), canCombine(), canCompareBeNewValueJump(), canDefBePartOfLOH(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::HexagonPacketizerList::cleanUpDotCur(), clobbersCTR(), collectDebugValues(), CombineCVTAToLocal(), llvm::Legalizer::combineExtracts(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetSchedModel::computeOutputLatency(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), ConvertImplicitDefToConstZero(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), copyHint(), copyImplicitOps(), llvm::R600InstrInfo::copyPhysReg(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::CreateEmptyPHI(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::ARMBaseInstrInfo::duplicate(), llvm::SparcFrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::AVRFrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::MipsRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::AsmPrinter::emitCFIInstruction(), emitDebugValueComment(), llvm::SparcTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SparcTargetLowering::emitEHSjLjSetJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AVRFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::AsmPrinter::emitFrameAlloc(), EmitGCCInlineAsmStr(), llvm::AsmPrinter::emitImplicitDef(), emitIncrement(), emitIndirectDst(), emitIndirectSrc(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableAddrs(), llvm::ARMAsmPrinter::EmitJumpTableInsts(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitKill(), emitLoadM0FromVGPRLoop(), emitMonitor(), EmitMSInlineAsmStr(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::AVRFrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), emitRDPKRU(), llvm::MSP430TargetLowering::EmitShiftInstr(), llvm::X86FrameLowering::emitSPUpdate(), emitWRPKRU(), emitXBegin(), eraseGPOpnd(), eraseIfDead(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), llvm::LegalizerHelper::fewerElementsVector(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), findCondCodeUsedByInstr(), findCorrespondingPred(), findDefIdx(), findRegisterDefOperand(), findRegisterUseOperand(), findUseIdx(), finishConvertToThreeAddress(), llvm::fixStackStores(), fixupCalleeSaveRestoreStackOffset(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), foldImmediates(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), FuseInst(), FuseTwoAddrInst(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), getAbsSetOperand(), llvm::LegalizerInfo::getAction(), llvm::getAddressFromInstr(), getBaseAddressRegister(), llvm::HexagonInstrInfo::getBaseAndOffset(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), llvm::SIInstrInfo::getBranchDestBlock(), llvm::AArch64InstrInfo::getBranchDestBlock(), llvm::SystemZInstrInfo::getBranchInfo(), llvm::StatepointOpers::getCallTarget(), getCallTargetRegOpnd(), getCompareSourceReg(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), getCopyRegClasses(), getDebugLocValue(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::R600InstrInfo::getFlagOp(), getFMAPatterns(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), getFrameIndexOperandNum(), llvm::SystemZInstrInfo::getFusedCompare(), llvm::HexagonHazardRecognizer::getHazardType(), llvm::StackMapOpers::getID(), llvm::StatepointOpers::getID(), getImmOrMaterializedImm(), llvm::HexagonInstrInfo::getIncrementValue(), getInitPhiReg(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::PPCInstrInfo::getInstrLatency(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::getInstrPredicate(), getInstrVecReg(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::PPCInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), getLdStBaseOp(), llvm::NVPTXInstrInfo::getLdStCodeAddrSpace(), getLdStOffsetOp(), getLdStRegOp(), getLoadStoreBaseOp(), getLoadStoreRegOp(), getLoopPhiReg(), getMaddPatterns(), llvm::X86InstrInfo::getMemOpBaseRegImmOfs(), llvm::LanaiInstrInfo::getMemOpBaseRegImmOfsWidth(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getMemOpKey(), getMemoryOpOffset(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::PatchPointOpers::getNumCallArgs(), getNumMicroOpsSwiftLdSt(), llvm::StackMapOpers::getNumPatchBytes(), llvm::StatepointOpers::getNumPatchBytes(), llvm::SIInstrInfo::getNumWaitStates(), llvm::PPCInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), getPHIDeps(), getPhiRegs(), llvm::getPHISrcRegOpIdx(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPHIValue(), getPostIncrementOperand(), llvm::ARMBaseInstrInfo::getPredicate(), llvm::LEONMachineFunctionPass::GetRegIndexForOperand(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), getShuffleComment(), llvm::HexagonInstrInfo::getSize(), llvm::TargetInstrInfo::getSPAdjust(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getStartOrEndSlot(), getStoreOffset(), getStoreValueOperand(), getTargetMBB(), getTruncatedShiftCount(), getTypeToPrint(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetUndefVal(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::SIInstrInfo::getVALUOp(), llvm::StatepointOpers::getVarIdx(), getWinAllocaAmount(), handleMiddleInst(), handleUse(), HandleVRSaveUpdate(), hasComplexRegisterTies(), llvm::AArch64InstrInfo::hasExtendedReg(), HashMachineInstr(), llvm::X86InstrInfo::hasLiveCondCodeDef(), hasRAWHazard(), llvm::X86InstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::AArch64InstrInfo::hasShiftedReg(), hasVGPROperands(), llvm::HexagonLowerToMC(), llvm::HexagonInstrInfo::immediateExtend(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::insertBranch(), llvm::R600InstrInfo::insertBranch(), llvm::SIInstrInfo::insertBranch(), insertDivByZeroTrap(), InsertFPConstInst(), InsertFPImmInst(), insertPHI(), InsertSPConstInst(), InsertSPImmInst(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::isAArch64FrameOffsetLegal(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::HexagonPacketizerList::isCallDependent(), isCandidateLoad(), isCandidateStore(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::WebAssembly::isChild(), llvm::rdf::TargetOperandInfo::isClobbering(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), llvm::PPCInstrInfo::isCoalescableExtInstr(), llvm::X86InstrInfo::isCoalescableExtInstr(), isCompareZero(), llvm::HexagonInstrInfo::isConstExtended(), isConvergent(), isCopyToExec(), isCopyToReg(), isCrossCopy(), isCSRestore(), isCVTAToLocalCombinationCandidate(), isDependent(), isDescribedByReg(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::AArch64InstrInfo::isFPRCopy(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), isFullCopy(), isFullCopyOf(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), isIdenticalTo(), isIdentityCopy(), isIncrementOrDecrement(), isIndirectDebugValue(), llvm::SIInstrInfo::isInlineConstant(), llvm::isLeaMem(), isLEASimpleIncOrDec(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLiteralConstant(), isLoadAndTestAsCmp(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::PPCInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), isLocalCopy(), llvm::isMem(), isMemoryOp(), llvm::NVPTXInstrInfo::isMoveInstr(), isNonFoldablePartialRegisterLoad(), llvm::SIInstrInfo::isOperandLegal(), isPhysicalRegCopy(), llvm::R600InstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::R600InstrInfo::isPredicated(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRedundantFlagInstr(), isRegTiedToDefOperand(), isRegTiedToUseOperand(), isRematerializable(), isSafeToFoldImmIntoCopy(), llvm::AArch64InstrInfo::isScaledAddr(), isSecondInstructionInSequence(), isShift(), isSimpleBD12Move(), isSimpleIndexCalc(), isSimpleMove(), isSourceDefinedByImplicitDef(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), isSuitableForMask(), llvm::ARMBaseInstrInfo::isSwiftFastImmShift(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTwoAddrUse(), llvm::SIInstrInfo::isVGPRCopy(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::LegalizerHelper::libcall(), loadM0FromVGPR(), llvm::XCoreMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::LegalizerHelper::lower(), llvm::LowerARMMachineInstrToMCInst(), llvm::AArch64CallLowering::lowerCall(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), llvm::LowerPPCMachineInstrToMCInst(), lowerRIEfLow(), lowerRIHigh(), lowerRILow(), llvm::LowerSparcMachineInstrToMCInst(), lowerSubvectorLoad(), lowerSubvectorStore(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), MatchingStackOffset(), MaybeRewriteToFallthrough(), mayLoad(), mayStore(), MoveAndTeeForMultiUse(), MoveForSingleUse(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), OneUseDominatesOtherUses(), optimizeCall(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), parseCondBranch(), parseOperands(), llvm::PatchPointOpers::PatchPointOpers(), phiHasBreakDef(), phiHasVGPROperands(), llvm::HexagonInstrInfo::predCanBeUsedAsDotNew(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::SystemZAsmPrinter::PrintAsmMemoryOperand(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::SystemZAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::printFCCOperand(), printIntelMemReference(), printLeaMemReference(), printMemReference(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), printOperand(), printPCRelImm(), llvm::ARMBaseInstrInfo::produceSameValue(), QueryCallee(), readsVCCZ(), llvm::TargetInstrInfo::reassociateOps(), llvm::MachineRegisterInfo::recomputeRegClass(), llvm::StackMaps::recordStackMap(), llvm::HexagonInstrInfo::reduceLoopCount(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), llvm::TargetInstrInfo::reMaterialize(), removeCopies(), removeIPMBasedCompare(), removeKillInfo(), removePhis(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), ReplaceDominatedUses(), replaceFI(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::X86FrameLowering::restoreWin32EHStackPointers(), resultTests(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), RewriteP2Align(), llvm::rewriteT2FrameIndex(), llvm::FixFSMULD::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ReplaceFMULS::runOnMachineFunction(), llvm::DetectRoundChange::runOnMachineFunction(), llvm::AArch64InstructionSelector::select(), selectCopy(), llvm::setDirectAddressInInstr(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::R600InstrInfo::setImmOperand(), setM0ToIndexFromSGPR(), llvm::X86InstrInfo::setSpecialOperandAttr(), llvm::AArch64InstrInfo::shouldClusterMemOps(), shrinkScalarCompare(), smallData(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tieOpsIfNeeded(), TrackDefUses(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), tryAddToFoldList(), tryConstantFoldOp(), llvm::tryFoldSPUpdateIntoPushPop(), tryOptimizeLEAtoMOV(), tryOrrMovk(), trySequenceOfOnes(), tryToreplicateChunks(), llvm::X86InstrInfo::unfoldMemoryOperand(), unsupportedBinOp(), untieRegOperand(), llvm::AntiDepBreaker::UpdateDbgValue(), updateOperand(), UpdateOperandRegClass(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::HexagonPacketizerList::useCalleesSP(), llvm::HexagonPacketizerList::useCallersSP(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), and llvm::LegalizerHelper::widenScalar().
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Definition at line 283 of file MachineInstr.h.
References assert(), getNumOperands(), and i.
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Returns the number of the operand iterator I points to.
Definition at line 353 of file MachineInstr.h.
References operands_begin().
Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), getDataDeps(), isCandidateStore(), isCrossCopy(), llvm::SIInstrInfo::isInlineConstant(), isKImmOperand(), isKUImmOperand(), updatePhysDepsDownwards(), and updatePhysDepsUpwards().
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Definition at line 131 of file MachineInstr.h.
Referenced by llvm::addFrameReference(), llvm::LiveIntervals::addSegmentToEndOfBlock(), llvm::HexagonPacketizerList::addToPacket(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), attachMEMCPYScratchRegs(), llvm::DwarfDebug::beginInstruction(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), canCombine(), canFoldCopy(), canInstrSubstituteCmpInstr(), cannotCoexistAsymm(), llvm::X86InstrInfo::classifyLEAReg(), collectDebugValues(), CombineCVTAToLocal(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::SystemZInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::TargetSchedModel::computeOutputLatency(), llvm::constrainOperandRegClass(), llvm::InstructionSelector::constrainSelectedInstRegOperands(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), doesModifyCalleeSavedReg(), llvm::MachineDominatorTree::dominates(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::MipsRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitComments(), llvm::HexagonAsmPrinter::EmitInstruction(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::ScheduleDAGSDNodes::EmitSchedule(), llvm::DbgValueHistoryMap::endInstrRange(), llvm::DebugHandlerBase::endInstruction(), llvm::SplitEditor::enterIntvAfter(), llvm::SplitEditor::enterIntvBefore(), eraseGPOpnd(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), llvm::Mips16InstrInfo::expandPostRAPseudo(), llvm::MipsSEInstrInfo::expandPostRAPseudo(), llvm::SparcInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), findOnlyInterestingUse(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), forceReg(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), getBundledUseMI(), getConstantFromPool(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), getFMAPatterns(), llvm::ARMHazardRecognizer::getHazardType(), llvm::HexagonHazardRecognizer::getHazardType(), getImplicitSPRUseForDPRUse(), llvm::SlotIndexes::getIndexAfter(), llvm::SlotIndexes::getIndexBefore(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::MachineTraceMetrics::Trace::getInstrSlack(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::PPCInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), getLiveRegsAt(), getLoadStoreOffsetSizeInBits(), llvm::PPCInstrInfo::getMachineCombinerPatterns(), getMaddPatterns(), getNewValueJumpOpcode(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), getRegClassConstraint(), llvm::HexagonInstrInfo::getSize(), llvm::TargetInstrInfo::getSPAdjust(), llvm::X86InstrInfo::getSPAdjust(), llvm::LiveIntervals::getSpillWeight(), GetSymbolRef(), llvm::HexagonInstrInfo::getUnits(), llvm::LiveIntervals::handleMove(), llvm::LiveVariables::HandleVirtRegUse(), HandleVRSaveUpdate(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), hasVGPROperands(), insertCopy(), InsertFPConstInst(), InsertFPImmInst(), llvm::SlotIndexes::insertMachineInstrInMaps(), insertNopBeforeInstruction(), insertPHI(), InsertSPConstInst(), InsertSPImmInst(), llvm::AArch64InstrInfo::isAssociativeAndCommutative(), llvm::X86InstrInfo::isAssociativeAndCommutative(), isCombineInstrCandidateFP(), llvm::HexagonInstrInfo::isComplex(), isCVTAToLocalCombinationCandidate(), llvm::MachineTraceMetrics::Trace::isDepInTrace(), isDereferenceableInvariantLoad(), llvm::LiveVariables::VarInfo::isLiveIn(), isNoReturnDef(), llvm::SIInstrInfo::isOperandLegal(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::R600InstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), llvm::TargetInstrInfo::isReassociationCandidate(), llvm::VLIWResourceModel::isResourceAvailable(), IsSafeToMove(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::SIInstrInfo::isVGPRCopy(), jumpTableFollowsTB(), llvm::SplitEditor::leaveIntvAfter(), llvm::SplitEditor::leaveIntvBefore(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::AMDGPUMCInstLower::lower(), llvm::WebAssemblyMCInstLower::Lower(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), llvm::AMDGPUMCInstLower::lowerOperand(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), llvm::MachineOperandIteratorBase::MachineOperandIteratorBase(), llvm::HexagonInstrInfo::mayBeCurLoad(), mergeMemRefsWith(), MIsNeedChainEdge(), moveInstrOut(), llvm::SIInstrInfo::moveToVALU(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), OneUseDominatesOtherUses(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MIPrinter::printTargetFlags(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::HexagonPacketizerList::producesStall(), llvm::rdf::DataFlowGraph::pushDefs(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), llvm::TargetInstrInfo::reassociateOps(), llvm::AsmPrinter::recordSled(), removeIPMBasedCompare(), RemoveVRSaveCode(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), replaceFI(), replaceRegUsesAfterLoop(), reportSelectionError(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::rewriteAArch64FrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::MachineSSAUpdater::RewriteUse(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::RegScavenger::scavengeRegister(), llvm::ARMInstructionSelector::select(), llvm::AArch64InstructionSelector::select(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::MachineIRBuilder::setInstr(), setM0ToIndexFromSGPR(), llvm::CoalescerPair::setRegisters(), llvm::SIInstrInfo::shouldClusterMemOps(), llvm::ARMBaseRegisterInfo::shouldCoalesce(), SinkingPreventsImplicitNullCheck(), llvm::TailDuplicator::tailDuplicateAndUpdate(), llvm::tryFoldSPUpdateIntoPushPop(), tryOptimizeLEAtoMOV(), llvm::FastISel::tryToFoldLoad(), UpdateOperandRegClass(), UpdatePredRedefs(), llvm::R600InstrInfo::usesTextureCache(), llvm::R600InstrInfo::usesVertexCache(), validAtEntry(), llvm::RegisterBankInfo::InstructionMapping::verify(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 132 of file MachineInstr.h.
| const TargetRegisterClass * MachineInstr::getRegClassConstraint | ( | unsigned | OpIdx, |
| const TargetInstrInfo * | TII, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Compute the static register class constraint for operand OpIdx.
For normal instructions, this is derived from the MCInstrDesc. For inline assembly it is derived from the flag words.
Returns NULL if the static register class constraint cannot be determined.
Definition at line 1210 of file MachineInstr.cpp.
References assert(), llvm::HexagonMCInstrInfo::getDesc(), llvm::InlineAsm::getKind(), getParent(), llvm::MachineOperand::getParent(), llvm::TargetRegisterInfo::getPointerRegClass(), llvm::TargetInstrInfo::getRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::InlineAsm::hasRegClassConstraint(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::InlineAsm::Kind_Mem, llvm::InlineAsm::Kind_RegDef, llvm::InlineAsm::Kind_RegDefEarlyClobber, and llvm::InlineAsm::Kind_RegUse.
Referenced by llvm::RegisterBankInfo::getRegBankFromConstraints(), llvm::TargetInstrInfo::reassociateOps(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().
| const TargetRegisterClass * MachineInstr::getRegClassConstraintEffect | ( | unsigned | OpIdx, |
| const TargetRegisterClass * | CurRC, | ||
| const TargetInstrInfo * | TII, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const |
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
Returns the register class that satisfies both CurRC and the constraints set by OpIdx MI. Returns NULL if such a register class does not exist.
OpIdx must be a register. Definition at line 1278 of file MachineInstr.cpp.
References assert(), llvm::TargetRegisterInfo::getCommonSubClass(), llvm::TargetRegisterInfo::getMatchingSuperRegClass(), llvm::TargetRegisterInfo::getSubClassWithSubReg(), llvm::MachineOperand::getSubReg(), and llvm::MachineOperand::isReg().
Referenced by llvm::MachineRegisterInfo::recomputeRegClass().
| const TargetRegisterClass * MachineInstr::getRegClassConstraintEffectForVReg | ( | unsigned | Reg, |
| const TargetRegisterClass * | CurRC, | ||
| const TargetInstrInfo * | TII, | ||
| const TargetRegisterInfo * | TRI, | ||
| bool | ExploreBundle = false |
||
| ) | const |
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
If ExploreBundle is set and MI is part of a bundle, all the instructions inside the bundle will be taken into account. In other words, this method accumulates all the constraints of the operand of this MI and the related bundle if MI is a bundle or inside a bundle.
Returns the register class that satisfies both CurRC and the constraints set by MI. Returns NULL if such a register class does not exist.
Definition at line 1249 of file MachineInstr.cpp.
References i, llvm::MachineOperandIteratorBase::isValid(), llvm::MachineOperand::Reg, and TII.
Referenced by getNumAllocatableRegsForConstraints().
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Returns true if the specified instruction has a delay slot which must be filled by the code generator.
Definition at line 526 of file MachineInstr.h.
References llvm::MCID::DelaySlot, and hasProperty().
Referenced by hasUnoccupiedSlot().
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Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.
Definition at line 712 of file MachineInstr.h.
References llvm::MCID::ExtraDefRegAllocReq, and hasProperty().
Referenced by llvm::CriticalAntiDepBreaker::BreakAntiDependencies().
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Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.
Definition at line 702 of file MachineInstr.h.
References llvm::MCID::ExtraSrcRegAllocReq, and hasProperty().
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Return true if this instruction has exactly one MachineMemOperand.
Definition at line 373 of file MachineInstr.h.
Referenced by llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getUnderlyingObjects(), INITIALIZE_PASS(), isMemoryOp(), MIsNeedChainEdge(), llvm::X86InstrInfo::optimizeCompareInstr(), RewriteP2Align(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Set if this instruction has an optional definition, e.g.
ARM instructions which can set condition code if 's' bit is set.
Definition at line 410 of file MachineInstr.h.
References llvm::MCID::HasOptionalDef, and hasProperty().
Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), and llvm::ARMBaseInstrInfo::optimizeSelect().
| bool MachineInstr::hasOrderedMemoryRef | ( | ) | const |
Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.
hasOrderedMemoryRef - Return true if this instruction may have an ordered or volatile memory reference, or if the information describing the memory reference is not available.
Return false if it is known to have no ordered or volatile memory references.
Return false if it is known to have no ordered memory references.
Definition at line 1578 of file MachineInstr.cpp.
References llvm::any_of(), and llvm::MachineMemOperand::isUnordered().
Referenced by areCandidatesToMergeOrPair(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isDependenceBarrier(), isGlobalMemoryObject(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), and Query().
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Return true if this instruction requires adjustment after instruction selection by calling a target hook.
For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.
Definition at line 671 of file MachineInstr.h.
References llvm::MCID::HasPostISelHook, and hasProperty().
Referenced by llvm::TargetLowering::AdjustInstrPostInstrSelection().
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Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has the specified property.
The first argument is the property being queried. The second argument indicates whether the query should look inside instruction bundles.
Definition at line 391 of file MachineInstr.h.
References getDesc(), llvm::MCInstrDesc::getFlags(), IgnoreBundle, isBundled(), and isBundledWithPred().
Referenced by canFoldAsLoad(), hasDelaySlot(), hasExtraDefRegAllocReq(), hasExtraSrcRegAllocReq(), hasOptionalDef(), hasPostISelHook(), isAsCheapAsAMove(), isBarrier(), isBitcast(), isBranch(), isCall(), isCommutable(), isCompare(), isConvergent(), isConvertibleTo3Addr(), isExtractSubregLike(), isIndirectBranch(), isInsertSubregLike(), isMoveImmediate(), isNotDuplicable(), isPredicable(), isPseudo(), isRegSequenceLike(), isRematerializable(), isReturn(), isSelect(), isTerminator(), isVariadic(), mayLoad(), mayStore(), and usesCustomInsertionHook().
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not considering sub/super-registers).
Definition at line 1310 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), and llvm::MachineOperand::Reg.
Referenced by llvm::SIInstrInfo::verifyInstruction().
| bool MachineInstr::hasUnmodeledSideEffects | ( | ) | const |
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore, etc.
For all instructions, the property is encoded in MCInstrDesc::Flags (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is INLINEASM instruction, in which case the side effect property is encoded in one of its operands (see InlineAsm::Extra_HasSideEffect).
Definition at line 1655 of file MachineInstr.cpp.
References llvm::InlineAsm::Extra_HasSideEffects, llvm::InlineAsm::MIOp_ExtraInfo, and llvm::MCID::UnmodeledSideEffects.
Referenced by llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), CanMovePastDMB(), isDependenceBarrier(), isGlobalMemoryObject(), isUnsafeToMoveAcross(), and Query().
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Definition at line 315 of file MachineInstr.h.
References llvm::sys::path::end(), explicit_operands(), llvm::make_range(), and operands_end().
Referenced by copyFlagsToImplicitVCC(), and findImplicitSGPRRead().
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Definition at line 318 of file MachineInstr.h.
References llvm::sys::path::end(), explicit_operands(), llvm::make_range(), and operands_end().
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Returns true if this instruction has the same cost (or less) than a move instruction.
This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.
Definition at line 691 of file MachineInstr.h.
References llvm::MCID::CheapAsAMove, and hasProperty().
Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::TargetInstrInfo::isAsCheapAsAMove(), and ShouldRematerialize().
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Returns true if the specified instruction stops control flow from executing the instruction immediately following it.
Examples include unconditional branches and return instructions.
Definition at line 431 of file MachineInstr.h.
References llvm::MCID::Barrier, and hasProperty().
Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::MachineBasicBlock::canFallThrough(), cannotCoexistAsymm(), llvm::ARMHazardRecognizer::getHazardType(), llvm::HexagonPacketizerList::hasControlDependence(), isConditionalBranch(), isUnconditionalBranch(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), and ProfitableToMerge().
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Return true if this instruction is a bitcast instruction.
Definition at line 496 of file MachineInstr.h.
References llvm::MCID::Bitcast, and hasProperty().
Referenced by getCopyRewriter().
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Returns true if this is a conditional, unconditional, or indirect branch.
Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to get more information.
Definition at line 448 of file MachineInstr.h.
References llvm::MCID::Branch, and hasProperty().
Referenced by cannotCoexistAsymm(), llvm::PPCInstrInfo::getOperandLatency(), llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::HexagonInstrInfo::isComplex(), llvm::HexagonInstrInfo::isCompoundBranchInstr(), llvm::HexagonInstrInfo::isCondInst(), isConditionalBranch(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::HexagonInstrInfo::isNewValueJump(), llvm::HexagonInstrInfo::isTailCall(), isUnconditionalBranch(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), llvm::rdf::operator<<(), llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::BitTracker::visit().
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Definition at line 804 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::TargetSchedModel::computeInstrLatency(), llvm::HexagonAsmPrinter::EmitInstruction(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::ARMBaseInstrInfo::getOperandLatency(), INITIALIZE_PASS(), isIdenticalTo(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), llvm::TargetInstrInfo::PredicateInstruction(), and llvm::HexagonPacketizerList::unpacketizeSoloInstrs().
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Return true if this instruction part of a bundle.
This is true if either itself or its following instruction is marked "InsideBundle".
Definition at line 223 of file MachineInstr.h.
References isBundledWithPred(), and isBundledWithSucc().
Referenced by llvm::LiveIntervals::handleMove(), hasProperty(), and llvm::X86FrameLowering::inlineStackProbe().
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Return true if this instruction is part of a bundle, and it is not the first instruction in the bundle.
Definition at line 229 of file MachineInstr.h.
References BundledPred, and getFlag().
Referenced by hasProperty(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), isBundled(), moveInstrOut(), and unbundleSingleMI().
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Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle.
Definition at line 233 of file MachineInstr.h.
References BundledSucc, and getFlag().
Referenced by hasUnoccupiedSlot(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), isBundled(), moveInstrOut(), and unbundleSingleMI().
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Definition at line 424 of file MachineInstr.h.
References llvm::MCID::Call, and hasProperty().
Referenced by llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), callClobbersAnyYmmReg(), llvm::EHStreamer::callToNoUnwindFunction(), CanMovePastDMB(), cannotCoexistAsymm(), llvm::SystemZHazardRecognizer::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::X86InstrInfo::getSPAdjust(), llvm::HexagonPacketizerList::hasControlDependence(), llvm::HexagonPacketizerList::hasDeadDependence(), hasYmmReg(), llvm::rdf::TargetOperandInfo::isClobbering(), llvm::HexagonInstrInfo::isComplex(), llvm::HexagonInstrInfo::isConstExtended(), isDependenceBarrier(), llvm::rdf::TargetOperandInfo::isFixedReg(), isGlobalMemoryObject(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isNoReturnDef(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::HexagonInstrInfo::isSchedulingBoundary(), needsStackFrame(), llvm::rdf::operator<<(), Query(), and llvm::TailDuplicator::shouldTailDuplicate().
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Definition at line 770 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::DwarfDebug::beginInstruction(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), isPosition(), llvm::HexagonPacketizerList::isSoloInstruction(), and llvm::MIPrinter::print().
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Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.
Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.
Definition at line 633 of file MachineInstr.h.
References llvm::MCID::Commutable, and hasProperty().
Referenced by llvm::TargetInstrInfo::commuteInstruction(), llvm::SIInstrInfo::findCommutedOpIndices(), foldImmediates(), llvm::SIInstrInfo::legalizeOperandsVOP2(), and tryConstantFoldOp().
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Return true if this instruction is a comparison.
Definition at line 485 of file MachineInstr.h.
References llvm::MCID::Compare, and hasProperty().
Referenced by llvm::SystemZInstrInfo::analyzeCompare(), getCompareSourceReg(), llvm::HexagonInstrInfo::isEarlySourceInstr(), lowerRIHigh(), and lowerRILow().
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Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block.
The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 462 of file MachineInstr.h.
References isBarrier(), isBranch(), and isIndirectBranch().
| unsigned MachineInstr::isConstantValuePHI | ( | ) | const |
If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.
isConstantValuePHI - If the specified instruction is a PHI that always merges together the same virtual register, return the register, otherwise return 0.
Definition at line 1642 of file MachineInstr.cpp.
References assert(), llvm::MachineOperand::getReg(), i, and llvm::MachineOperand::Reg.
Referenced by llvm::MachineSSAUpdater::GetValueInMiddleOfBlock().
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Return true if this instruction is convergent.
Convergent instructions can not be made control-dependent on any additional values.
Definition at line 515 of file MachineInstr.h.
References llvm::MCID::Convergent, llvm::InlineAsm::Extra_IsConvergent, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), and llvm::InlineAsm::MIOp_ExtraInfo.
Referenced by llvm::TailDuplicator::shouldTailDuplicate().
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Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.
Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.
If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).
Definition at line 651 of file MachineInstr.h.
References llvm::MCID::ConvertibleTo3Addr, and hasProperty().
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Definition at line 807 of file MachineInstr.h.
References getOpcode().
Referenced by biasPhysRegCopy(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), canFoldCopy(), llvm::HexagonEvaluator::evaluate(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), llvm::RegisterBankInfo::getInstrMappingImpl(), getWinAllocaAmount(), isCopyLike(), isCopyToReg(), isFullCopy(), isIdentityCopy(), llvm::SIInstrInfo::isInlineConstant(), isLocalCopy(), llvm::SIInstrInfo::isVGPRCopy(), MIIsInTerminatorSequence(), llvm::SIInstrInfo::moveToVALU(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::GenericScheduler::reschedulePhysRegCopies(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ARMInstructionSelector::select(), llvm::AArch64InstructionSelector::select(), selectCopy(), llvm::TailDuplicator::tailDuplicateAndUpdate(), and llvm::RegisterBankInfo::InstructionMapping::verify().
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Return true if the instruction behaves like a copy.
This does not include native copy instructions.
Definition at line 819 of file MachineInstr.h.
References isCopy(), and isSubregToReg().
Referenced by llvm::ARMBaseInstrInfo::getOperandLatency(), isTerminalReg(), and llvm::SplitAnalysis::shouldSplitSingleBlock().
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Definition at line 777 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::MachineInstrBuilder::addMetadata(), llvm::CodeViewDebug::beginInstruction(), llvm::DwarfDebug::beginInstruction(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::RegPressureTracker::bumpDownwardPressure(), llvm::RegPressureTracker::bumpUpwardPressure(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), llvm::ConnectedVNInfoEqClasses::Distribute(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), llvm::ARMHazardRecognizer::EmitInstruction(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::DebugHandlerBase::endInstruction(), llvm::ScheduleDAGInstrs::fixupKills(), getDataDeps(), llvm::HexagonInstrInfo::getFirstNonDbgInst(), llvm::ARMHazardRecognizer::getHazardType(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::HexagonInstrInfo::getSize(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), llvm::SlotIndexes::insertMachineInstrInMaps(), isDefBetween(), isDescribedByReg(), isIndirectDebugValue(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::HexagonInstrInfo::isSchedulingBoundary(), isUnsafeToMoveAcross(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), MIIsInTerminatorSequence(), llvm::CriticalAntiDepBreaker::Observe(), llvm::X86FrameLowering::orderFrameObjects(), Query(), llvm::SlotIndexes::repairIndexesInRange(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::rdf::Liveness::resetKills(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::TailDuplicator::shouldTailDuplicate(), llvm::LiveIntervals::shrinkToUses(), llvm::DbgValueHistoryMap::startInstrRange(), llvm::TailDuplicator::tailDuplicateAndUpdate(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), llvm::RegScavenger::unprocess(), and llvm::AntiDepBreaker::UpdateDbgValue().
| bool MachineInstr::isDereferenceableInvariantLoad | ( | AliasAnalysis * | AA | ) | const |
Return true if this load instruction never traps and points to a memory location whose value doesn't change during the execution of this function.
isDereferenceableInvariantLoad - Return true if this instruction will never trap and is loading from a location whose value is invariant across a run of this function.
Examples include loading a value from the constant pool or from the argument area of a function (if it does not change). If the instruction does multiple loads, this returns true only if all of the loads are dereferenceable and invariant.
Definition at line 1600 of file MachineInstr.cpp.
References getParent(), llvm::MachineOperand::getParent(), and llvm::AAResults::pointsToConstantMemory().
Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), isDependenceBarrier(), isGlobalMemoryObject(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), and Query().
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Definition at line 765 of file MachineInstr.h.
References llvm::ISD::EH_LABEL, and getOpcode().
Referenced by isLabel(), and llvm::HexagonPacketizerList::isSoloInstruction().
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Definition at line 813 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::TargetInstrInfo::getExtractSubregInputs().
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Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.
Definition at line 567 of file MachineInstr.h.
References llvm::MCID::ExtractSubreg, and hasProperty().
Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getExtractSubregInputs(), and llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs().
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Definition at line 810 of file MachineInstr.h.
References getOperand(), llvm::MachineOperand::getSubReg(), and isCopy().
Referenced by llvm::AArch64InstrInfo::foldMemoryOperandImpl(), isFullCopyOf(), isRematerializable(), and removeCopies().
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| bool MachineInstr::isIdenticalTo | ( | const MachineInstr & | Other, |
| MICheckType | Check = CheckDefs |
||
| ) | const |
Return true if this instruction is identical to Other.
Two instructions are identical if they have the same opcode and all their operands are identical (with respect to MachineOperand::isIdenticalTo()). Note that this means liveness related flags (dead, undef, kill) do not affect the notion of identical.
Definition at line 994 of file MachineInstr.cpp.
References assert(), getDebugLoc(), llvm::ilist_node_impl< OptionsT >::getIterator(), getNumOperands(), getOpcode(), getOperand(), llvm::MachineOperand::getReg(), i, llvm::HexagonMCInstrInfo::isBundle(), isBundle(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), and llvm::MachineOperand::isReg().
Referenced by llvm::MachineInstrExpressionTrait::isEqual(), llvm::ARMBaseInstrInfo::produceSameValue(), and llvm::TargetInstrInfo::produceSameValue().
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Return true is the instruction is an identity copy.
Definition at line 824 of file MachineInstr.h.
References getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isCopy().
Referenced by llvm::VirtRegAuxInfo::calculateSpillWeightAndHint().
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Definition at line 788 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::HexagonPacketizerList::addToPacket(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), and MIIsInTerminatorSequence().
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Return true if this is an indirect branch, such as a branch through a register.
Definition at line 454 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::IndirectBranch.
Referenced by llvm::MipsInstrInfo::analyzeBranch(), isConditionalBranch(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), isUnconditionalBranch(), and llvm::TailDuplicator::shouldTailDuplicate().
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A DBG_VALUE is indirect iff the first operand is a register and the second operand is an immediate.
Definition at line 780 of file MachineInstr.h.
References getOperand(), isDebugValue(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isReg().
Referenced by llvm::SelectionDAGISel::runOnMachineFunction().
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Definition at line 789 of file MachineInstr.h.
References getOpcode(), and llvm::ISD::INLINEASM.
Referenced by llvm::RegAllocBase::allocatePhysRegs(), cannotCoexistAsymm(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::PPCRegisterInfo::eliminateFrameIndex(), getOffsetONFromFION(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), isConvergent(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::HexagonPacketizerList::isSoloInstruction(), isUnsafeToMoveAcross(), mayLoad(), mayStore(), llvm::MipsInstrInfo::SafeInForbiddenSlot(), llvm::HexagonPacketizerList::unpacketizeSoloInstrs(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 795 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getOperandLatency(), and isCopyToReg().
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Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.
Definition at line 581 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::InsertSubreg.
Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getInsertSubregInputs(), and llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs().
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Return true if MI is in a bundle (but not the first MI in a bundle).
In this case, the first MI starts a bundle but is not inside a bundle, the next 2 MIs are considered "inside" the bundle.
The first instruction has the special opcode "BUNDLE". It's not "inside" a bundle, but the next three MIs are.
Definition at line 217 of file MachineInstr.h.
References BundledPred, and getFlag().
Referenced by llvm::BuildMI(), llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::MIPrinter::print(), and llvm::HexagonPacketizerList::unpacketizeSoloInstrs().
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Definition at line 787 of file MachineInstr.h.
References getOpcode(), and llvm::AMDGPUISD::KILL.
Referenced by llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), findRegisterUseOperand(), and llvm::CriticalAntiDepBreaker::Observe().
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Returns true if the MachineInstr represents a label.
Definition at line 769 of file MachineInstr.h.
References isEHLabel(), and isGCLabel().
Referenced by isPosition().
| bool MachineInstr::isLoadFoldBarrier | ( | ) | const |
Returns true if it is illegal to fold a load across this instruction.
Definition at line 1667 of file MachineInstr.cpp.
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Return true if this instruction is a move immediate (including conditional moves) instruction.
Definition at line 491 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::MoveImm.
Referenced by foldImmediates(), getImmOrMaterializedImm(), isSafeToFoldImmIntoCopy(), and llvm::SIInstrInfo::legalizeGenericOperand().
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Definition at line 790 of file MachineInstr.h.
References getInlineAsmDialect(), getOpcode(), and llvm::ISD::INLINEASM.
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Return true if this instruction cannot be safely duplicated.
For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.
Definition at line 508 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::NotDuplicable.
Referenced by llvm::TargetInstrInfo::duplicate(), and llvm::TailDuplicator::shouldTailDuplicate().
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Definition at line 786 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), computeLiveOuts(), llvm::RegisterBankInfo::getInstrMappingImpl(), getPHIDeps(), getPhiRegs(), llvm::RegBankSelect::InstrInsertPoint::InstrInsertPoint(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::InstrIsPHI(), ProcessSourceNode(), removePhis(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::MachineSSAUpdater::RewriteUse(), llvm::TailDuplicator::shouldTailDuplicate(), llvm::TailDuplicator::tailDuplicateAndUpdate(), llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and llvm::RegisterBankInfo::InstructionMapping::verify().
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Definition at line 775 of file MachineInstr.h.
References isCFIInstruction(), and isLabel().
Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::HexagonInstrInfo::getSize(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::HexagonInstrInfo::isSchedulingBoundary(), llvm::TargetInstrInfo::isSchedulingBoundary(), and Query().
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Return true if this instruction has a predicate operand that controls execution.
It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.
Definition at line 478 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Predicable.
Referenced by canFoldIntoMOVCC(), canFoldIntoSelect(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseInstrInfo::isPredicable(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::PredicateInstruction(), and SinkingPreventsImplicitNullCheck().
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Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.
Definition at line 416 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Pseudo.
Referenced by llvm::ConvergingVLIWScheduler::SchedulingCost().
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Definition at line 801 of file MachineInstr.h.
References getOpcode().
Referenced by llvm::HexagonSubtarget::adjustSchedDependency(), foldVGPRCopyIntoRegSequence(), llvm::ARMBaseInstrInfo::getOperandLatency(), and llvm::TargetInstrInfo::getRegSequenceInputs().
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Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.
E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.
Definition at line 552 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::RegSequence.
Referenced by getCopyRewriter(), llvm::TargetInstrInfo::getRegSequenceInputs(), and llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs().
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Return true if the use operand of the specified index is tied to a def operand.
It also returns the def operand index by reference if DefOpIdx is not null.
Definition at line 1048 of file MachineInstr.h.
References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), and llvm::MachineOperand::isUse().
Referenced by llvm::MachineOperandIteratorBase::analyzeVirtReg(), and isTwoAddrUse().
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Given the index of a register def operand, check if the register def is tied to a source operand, due to either two-address elimination or inline assembly constraints.
Returns the first tied use operand index by reference if UseOpIdx is not null.
Definition at line 1035 of file MachineInstr.h.
References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTied().
Referenced by llvm::ScheduleDAGInstrs::fixupKills(), and llvm::SIInstrInfo::verifyInstruction().
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Returns true if this instruction is a candidate for remat.
This flag is deprecated, please don't use it anymore. If this flag is set, the isReallyTriviallyReMaterializable() method is called to verify the instruction is really rematable.
Definition at line 679 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Rematerializable.
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Definition at line 420 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Return.
Referenced by CanMovePastDMB(), llvm::HexagonPacketizerList::canPromoteToDotNew(), llvm::HexagonInstrInfo::isComplex(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::HexagonPacketizerList::isNewifiable(), llvm::MachineBasicBlock::isReturnBlock(), and llvm::TailDuplicator::shouldTailDuplicate().
| bool MachineInstr::isSafeToMove | ( | AliasAnalysis * | AA, |
| bool & | SawStore | ||
| ) | const |
Return true if it is safe to move this instruction.
isSafeToMove - Return true if it is safe to move this instruction.
If SawStore is set to true, it means that there is a store (or call) between the instruction's location and its intended destination.
Definition at line 1545 of file MachineInstr.cpp.
References SawStore.
Referenced by canFoldIntoMOVCC(), canFoldIntoSelect(), MaySpeculate(), and llvm::X86InstrInfo::optimizeLoadInstr().
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Return true if this instruction is a select instruction.
Definition at line 501 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Select.
| bool MachineInstr::isStackAligningInlineAsm | ( | ) | const |
Definition at line 1156 of file MachineInstr.cpp.
References llvm::InlineAsm::Extra_IsAlignStack, and llvm::InlineAsm::MIOp_ExtraInfo.
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Definition at line 798 of file MachineInstr.h.
References getOpcode().
Referenced by isCopyLike(), and isCopyToReg().
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Returns true if this instruction part of the terminator for a basic block.
Typically this is things like return and branch instructions.
Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.
Definition at line 440 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Terminator.
Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph(), cannotCoexistAsymm(), findInsertLocation(), llvm::ARMBaseInstrInfo::isSchedulingBoundary(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::MSP430InstrInfo::isUnpredicatedTerminator(), llvm::PPCInstrInfo::isUnpredicatedTerminator(), llvm::X86InstrInfo::isUnpredicatedTerminator(), llvm::TargetInstrInfo::isUnpredicatedTerminator(), Query(), and llvm::RegBankSelect::RepairingPlacement::RepairingPlacement().
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Return true if this is a transient instruction that is either very likely to be eliminated during register allocation (such as copy-like instructions), or if this instruction doesn't have an execution-time cost.
Definition at line 833 of file MachineInstr.h.
References llvm::ISD::EH_LABEL, getOpcode(), and llvm::AMDGPUISD::KILL.
Referenced by llvm::TargetSchedModel::computeOperandLatency(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::HexagonInstrInfo::getInstrTimingClassLatency(), llvm::TargetSchedModel::getNumMicroOps(), updatePhysDepsUpwards(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::SchedDFSImpl::visitPreorder().
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Return true if this is a branch which always transfers control flow to some other block.
The TargetInstrInfo::AnalyzeBranch method can be used to get more information about this branch.
Definition at line 470 of file MachineInstr.h.
References isBarrier(), isBranch(), and isIndirectBranch().
Referenced by llvm::MipsInstrInfo::analyzeBranch().
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Return true if this instruction can have a variable number of operands.
In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).
Definition at line 404 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::Variadic.
Referenced by llvm::SIInstrInfo::getOpRegClass(), and getTypeToPrint().
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Return true if the MachineInstr kills the specified register.
If TargetRegisterInfo is passed, then it also checks if there is a kill of a super-register.
Definition at line 886 of file MachineInstr.h.
References findRegisterUseOperandIdx().
Referenced by llvm::X86InstrInfo::breakPartialRegDependency(), isPlainlyKilled(), and llvm::X86InstrInfo::optimizeCompareInstr().
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Return true if this instruction could possibly read memory.
Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.
Definition at line 592 of file MachineInstr.h.
References llvm::InlineAsm::Extra_MayLoad, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayLoad, and llvm::InlineAsm::MIOp_ExtraInfo.
Referenced by llvm::SUnit::addPredBarrier(), llvm::HexagonSubtarget::HexagonDAGMutation::apply(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ScheduleDAGInstrs::buildSchedGraph(), CanMovePastDMB(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::TargetInstrInfo::defaultDefLatency(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::HexagonEvaluator::evaluate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), llvm::TargetInstrInfo::getInstrLatency(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), getPostIncrementOperand(), isDependenceBarrier(), llvm::HexagonInstrInfo::isEarlySourceInstr(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlotPostFE(), mayLoadFromGOTOrConstantPool(), mayLoadOrStore(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), Query(), and SinkingPreventsImplicitNullCheck().
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Return true if this instruction could possibly read or modify memory.
Definition at line 615 of file MachineInstr.h.
References mayLoad(), and mayStore().
Referenced by llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), canMoveInstsAcrossMemOp(), llvm::ARMHazardRecognizer::getHazardType(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(), getMemOpKey(), isFirstInstructionInSequence(), mayAlias(), and llvm::SIRegisterInfo::needsFrameBaseReg().
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Return true if this instruction could possibly modify memory.
Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.
Definition at line 605 of file MachineInstr.h.
References llvm::InlineAsm::Extra_MayStore, llvm::MachineOperand::getImm(), getOperand(), hasProperty(), isInlineAsm(), llvm::MCID::MayStore, and llvm::InlineAsm::MIOp_ExtraInfo.
Referenced by llvm::SUnit::addPredBarrier(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::HexagonDAGMutation::apply(), llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::ScheduleDAGInstrs::buildSchedGraph(), CanMovePastDMB(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), getInstrVecReg(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), hasRAWHazard(), llvm::HexagonPacketizerList::hasV4SpecificDependence(), llvm::HexagonInstrInfo::isCondInst(), llvm::HexagonInstrInfo::isEarlySourceInstr(), llvm::HexagonInstrInfo::isHVXMemWithAIndirect(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::HexagonPacketizerList::isNewifiable(), llvm::SIInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlotPostFE(), mayAlias(), mayLoadOrStore(), MIsNeedChainEdge(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), Query(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 365 of file MachineInstr.h.
References llvm::make_range(), memoperands_begin(), and memoperands_end().
Referenced by getUnderlyingObjectsForInstr(), InstructionStoresToFI(), llvm::AArch64InstrInfo::isLdStPairSuppressed(), llvm::SIInstrInfo::mayAccessFlatAddressSpace(), mayLoadFromGOTOrConstantPool(), llvm::MIPrinter::print(), and Query().
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Definition at line 368 of file MachineInstr.h.
References llvm::make_range(), memoperands_begin(), and memoperands_end().
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Access to memory operands of the instruction.
Definition at line 358 of file MachineInstr.h.
Referenced by llvm::SIInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SystemZInstrInfo::areMemAccessesTriviallyDisjoint(), emitComments(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::PPCHazardRecognizer970::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), expandLoadStackGuard(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::PPCHazardRecognizer970::getHazardType(), llvm::ARMBaseInstrInfo::getNumLDMAddresses(), llvm::ARMBaseInstrInfo::getNumMicroOps(), getStoreTarget(), getUnderlyingObjects(), hasIdenticalMMOs(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), INITIALIZE_PASS(), InsertFPConstInst(), InsertFPImmInst(), InsertSPConstInst(), InsertSPImmInst(), isMemoryOp(), llvm::SIInstrInfo::isStackAccess(), llvm::SIInstrInfo::legalizeOperands(), memoperands(), mergeMemRefsWith(), MIsNeedChainEdge(), llvm::ARMBaseInstrInfo::reMaterialize(), RewriteP2Align(), llvm::AArch64InstrInfo::suppressLdStPair(), llvm::X86InstrInfo::unfoldMemoryOperand(), and llvm::LegalizerHelper::widenScalar().
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Return true if we don't have any memory operands which described the the memory access done by this instruction.
If this is true, calling code must be conservative.
Definition at line 363 of file MachineInstr.h.
Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::PPCHazardRecognizer970::getHazardType(), getStoreTarget(), InstructionStoresToFI(), llvm::SIInstrInfo::isStackAccess(), llvm::SIInstrInfo::mayAccessFlatAddressSpace(), mayLoadFromGOTOrConstantPool(), mergeMemRefsWith(), llvm::MIPrinter::print(), and llvm::AArch64InstrInfo::suppressLdStPair().
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Definition at line 359 of file MachineInstr.h.
Referenced by llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::ARMBaseInstrInfo::getNumLDMAddresses(), hasIdenticalMMOs(), llvm::TargetInstrInfo::hasLoadFromStackSlot(), llvm::TargetInstrInfo::hasStoreToStackSlot(), llvm::SIInstrInfo::legalizeOperands(), memoperands(), mergeMemRefsWith(), llvm::ARMBaseInstrInfo::reMaterialize(), and llvm::X86InstrInfo::unfoldMemoryOperand().
| std::pair< MachineInstr::mmo_iterator, unsigned > MachineInstr::mergeMemRefsWith | ( | const MachineInstr & | Other | ) |
Return a set of memrefs (begin iterator, size) which conservatively describe the memory behavior of both MachineInstrs.
This is appropriate for use when merging two MachineInstrs into one. This routine does not modify the memrefs of the this MachineInstr.
Definition at line 942 of file MachineInstr.cpp.
References llvm::MachineFunction::allocateMemRefsArray(), assert(), getParent(), llvm::MachineOperand::getParent(), hasIdenticalMMOs(), memoperands_begin(), memoperands_empty(), and memoperands_end().
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Return true if the MachineInstr modifies (fully define or partially define) the specified register.
NOTE: It's ignoring subreg indices on virtual registers.
Definition at line 903 of file MachineInstr.h.
References findRegisterDefOperandIdx().
Referenced by areCFlagsAccessedBetweenInstrs(), canInstrSubstituteCmpInstr(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), doesModifyCalleeSavedReg(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isSchedulingBoundary(), llvm::TargetInstrInfo::isSchedulingBoundary(), isUnsafeToMoveAcross(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and removeIPMBasedCompare().
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Definition at line 301 of file MachineInstr.h.
References llvm::make_range(), operands_begin(), and operands_end().
Referenced by llvm::LiveIntervals::addKillFlags(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::RegScavenger::backward(), callClobbersAnyYmmReg(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), ClearKillFlags(), llvm::ScheduleDAGMILive::collectVRegUses(), computeLiveOuts(), definesFullReg(), doScavengeFrameVirtualRegs(), llvm::HexagonHazardRecognizer::EmitInstruction(), eraseFromParentAndMarkDBGValuesForRemoval(), llvm::ScheduleDAGInstrs::fixupKills(), getCalledFunction(), llvm::MachineInstrExpressionTrait::getHashValue(), getPostIncrementOperand(), getPredicatedRegister(), handleNormalInst(), llvm::HexagonPacketizerList::hasDeadDependence(), hasWriteToReadDep(), hasYmmReg(), isCPSRDefined(), isDependent(), llvm::rdf::TargetOperandInfo::isFixedReg(), isImplicitDependency(), IsSafeToMove(), llvm::HexagonInstrInfo::isTailCall(), llvm::AArch64MCInstLower::Lower(), llvm::AVRMCInstLower::lowerInstruction(), MaySpeculate(), needsStackFrame(), llvm::rdf::operator<<(), llvm::X86FrameLowering::orderFrameObjects(), llvm::X86InstrInfo::reMaterialize(), llvm::rdf::Liveness::resetKills(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::RegScavenger::scavengeRegister(), trackRegDefsUses(), unsupportedBinOp(), llvm::LiveIntervals::HMEditor::updateAllRanges(), UpdateCPSRDef(), and UpdateCPSRUse().
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Definition at line 304 of file MachineInstr.h.
References llvm::make_range(), operands_begin(), and operands_end().
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Definition at line 295 of file MachineInstr.h.
Referenced by defs(), explicit_operands(), explicit_uses(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getDataDeps(), getOperandNo(), llvm::HexagonInstrInfo::isExtended(), MIIsInTerminatorSequence(), operands(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::StackMaps::recordPatchPoint(), llvm::StackMaps::recordStackMap(), llvm::StackMaps::recordStatepoint(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::R600SchedStrategy::schedNode(), llvm::MachineBasicBlock::SplitCriticalEdge(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), and uses().
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Definition at line 298 of file MachineInstr.h.
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Definition at line 296 of file MachineInstr.h.
Referenced by getDataDeps(), implicit_operands(), llvm::HexagonInstrInfo::isExtended(), MIIsInTerminatorSequence(), operands(), llvm::rdf::operator<<(), llvm::R600InstrInfo::readsLDSSrcReg(), llvm::StackMaps::recordPatchPoint(), llvm::StackMaps::recordStackMap(), llvm::StackMaps::recordStatepoint(), llvm::LiveIntervals::repairIntervalsInRange(), llvm::R600SchedStrategy::schedNode(), llvm::MachineBasicBlock::SplitCriticalEdge(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), and uses().
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Definition at line 299 of file MachineInstr.h.
| void MachineInstr::print | ( | raw_ostream & | OS, |
| bool | SkipOpers = false, |
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| const TargetInstrInfo * | TII = nullptr |
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| ) | const |
Definition at line 1702 of file MachineInstr.cpp.
References llvm::Module::getFunction(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::GlobalValue::getParent(), llvm::MachineOperand::MBB, and llvm::MachineOperand::print().
Referenced by llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ScheduleDAGInstrs::getGraphNodeLabel(), and llvm::operator<<().
| void MachineInstr::print | ( | raw_ostream & | OS, |
| ModuleSlotTracker & | MST, | ||
| bool | SkipOpers = false, |
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| const TargetInstrInfo * | TII = nullptr |
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| ) | const |
Definition at line 1713 of file MachineInstr.cpp.
References llvm::InlineAsm::AD_ATT, llvm::InlineAsm::AD_Intel, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::InlineAsm::Constraint_es, llvm::InlineAsm::Constraint_i, llvm::InlineAsm::Constraint_m, llvm::InlineAsm::Constraint_o, llvm::InlineAsm::Constraint_Q, llvm::InlineAsm::Constraint_R, llvm::InlineAsm::Constraint_S, llvm::InlineAsm::Constraint_T, llvm::InlineAsm::Constraint_Um, llvm::InlineAsm::Constraint_Un, llvm::InlineAsm::Constraint_Uq, llvm::InlineAsm::Constraint_Us, llvm::InlineAsm::Constraint_Ut, llvm::InlineAsm::Constraint_Uv, llvm::InlineAsm::Constraint_Uy, llvm::InlineAsm::Constraint_v, llvm::InlineAsm::Constraint_X, llvm::InlineAsm::Constraint_Z, llvm::InlineAsm::Constraint_ZC, llvm::InlineAsm::Constraint_Zy, llvm::dyn_cast(), llvm::SmallVectorBase::empty(), llvm::SmallVectorImpl< T >::erase(), llvm::InlineAsm::Extra_HasSideEffects, llvm::InlineAsm::Extra_IsAlignStack, llvm::InlineAsm::Extra_IsConvergent, llvm::InlineAsm::Extra_MayLoad, llvm::InlineAsm::Extra_MayStore, fuzzer::Flags, llvm::PointerUnion< PT1, PT2 >::get(), llvm::HexagonMCInstrInfo::getDesc(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::TargetMachine::getIntrinsicInfo(), llvm::InlineAsm::getKind(), llvm::InlineAsm::getMemoryConstraintID(), llvm::MachineOperand::getMetadata(), getName(), llvm::MCInstrInfo::getName(), llvm::InlineAsm::getNumOperandRegisters(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetRegisterInfo::getRegClassName(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterInfo::getSubRegIndexName(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::MachineRegisterInfo::getType(), llvm::InlineAsm::hasRegClassConstraint(), i, llvm::PointerUnion< PT1, PT2 >::is(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImm(), llvm::InlineAsm::isImmKind(), llvm::MachineOperand::isImplicit(), llvm::InlineAsm::isMemKind(), llvm::MachineOperand::isMetadata(), llvm::MCOperandInfo::isOptionalDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MCOperandInfo::isPredicate(), llvm::MachineOperand::isReg(), llvm::InlineAsm::isUseOperandTiedToDef(), llvm::LLT::isValid(), llvm::MCRegAliasIterator::isValid(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::InlineAsm::Kind_Clobber, llvm::InlineAsm::Kind_Imm, llvm::InlineAsm::Kind_Mem, llvm::InlineAsm::Kind_RegDef, llvm::InlineAsm::Kind_RegDefEarlyClobber, llvm::InlineAsm::Kind_RegUse, llvm::MachineOperand::MBB, llvm::InlineAsm::MIOp_AsmString, llvm::InlineAsm::MIOp_ExtraInfo, llvm::InlineAsm::MIOp_FirstOperand, llvm::MCInstrDesc::NumOperands, llvm::MCInstrDesc::OpInfo, llvm::DebugLoc::print(), llvm::MachineOperand::print(), llvm::PrintReg(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::MachineRegisterInfo::use_empty().
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Return true if the MachineInstr reads the specified register.
If TargetRegisterInfo is passed, then it also checks if there is a read of a super-register. This does not count partial redefines of virtual registers as reads: reg1024:6 = OP.
Definition at line 865 of file MachineInstr.h.
References findRegisterUseOperandIdx().
Referenced by areCFlagsAccessedBetweenInstrs(), canInstrSubstituteCmpInstr(), checkAndUpdateEFLAGSKill(), llvm::TargetSchedModel::computeOutputLatency(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::getCompoundOpcode(), getImplicitSPRUseForDPRUse(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), hasRAWHazard(), hasWriteToReadDep(), ImposeStackOrdering(), IsSafeToMove(), isUnsafeToMoveAcross(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::ARMBaseInstrInfo::setExecutionDomain().
Return true if the MachineInstr reads the specified virtual register.
Take into account that a partial define is a read-modify-write operation.
Definition at line 873 of file MachineInstr.h.
References readsWritesVirtualRegister().
Referenced by addToListsIfDependent(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::SplitEditor::leaveIntvAfter(), and llvm::LiveIntervals::shrinkToUses().
| std::pair< bool, bool > MachineInstr::readsWritesVirtualRegister | ( | unsigned | Reg, |
| SmallVectorImpl< unsigned > * | Ops = nullptr |
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| ) | const |
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
readsWritesVirtualRegister - Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
This also considers partial defines. If Ops is not null, all operand indices for Reg are added.
This also considers partial defines.
Definition at line 1344 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), i, llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), and llvm::MachineOperand::Reg.
Referenced by llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), and readsVirtualRegister().
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Returns true if the register is dead in this machine instruction.
If TargetRegisterInfo is passed, then it also checks if there is a dead def of a super-register.
Definition at line 910 of file MachineInstr.h.
References findRegisterDefOperandIdx().
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::X86InstrInfo::optimizeCompareInstr(), and transferDeadCC().
| MachineInstr * MachineInstr::removeFromBundle | ( | ) |
Unlink this instruction from its basic block and return it without deleting it.
If the instruction is part of a bundle, the other instructions in the bundle remain bundled.
Definition at line 1070 of file MachineInstr.cpp.
References assert(), and llvm::MachineOperand::getParent().
| MachineInstr * MachineInstr::removeFromParent | ( | ) |
Unlink 'this' from the containing basic block, and return it without deleting it.
This function can not be used on bundled instructions, use removeFromBundle() to remove individual instructions from a bundle.
Definition at line 1065 of file MachineInstr.cpp.
References assert(), and llvm::MachineOperand::getParent().
Referenced by llvm::SIInstrInfo::legalizeOperands().
| void MachineInstr::RemoveOperand | ( | unsigned | i | ) |
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
RemoveOperand - Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition at line 887 of file MachineInstr.cpp.
References assert(), i, llvm::MachineOperand::isReg(), llvm::MachineOperand::isTied(), moveOperands(), N, and llvm::MachineRegisterInfo::removeRegOperandFromUseList().
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), eraseGPOpnd(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::FoldImmediate(), llvm::MipsInstrInfo::genInstrWithNewOpc(), llvm::SIInstrInfo::moveToVALU(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), removeModOperands(), removeOperands(), removePhis(), llvm::rewriteARMFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::ARMBaseInstrInfo::setExecutionDomain(), stripExtraCopyOperands(), tryConstantFoldOp(), and llvm::tryFoldSPUpdateIntoPushPop().
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Set a flag for the AsmPrinter.
Definition at line 146 of file MachineInstr.h.
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Replace current source information with new such.
Avoid using this, the constructor argument is preferable.
Definition at line 1186 of file MachineInstr.h.
References assert(), and llvm::DebugLoc::hasTrivialDestructor().
Referenced by expandLoadStackGuard().
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Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition at line 1182 of file MachineInstr.h.
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonPacketizerList::cleanUpDotCur(), llvm::SIInstrInfo::commuteInstructionImpl(), ConvertImplicitDefToConstZero(), llvm::HexagonPacketizerList::demoteToDotOld(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), Expand2AddrKreg(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::SparcInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::fixStackStores(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::HexagonInstrInfo::invertAndChangeJumpTarget(), llvm::SIInstrInfo::legalizeOperandsVOP2(), MaybeRewriteToFallthrough(), llvm::SIInstrInfo::moveToVALU(), mutateCopyOp(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::HexagonInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::HexagonPacketizerList::promoteToDotCur(), llvm::HexagonPacketizerList::promoteToDotNew(), removeTerminatorBit(), llvm::HexagonInstrInfo::reversePredSense(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::ARMInstructionSelector::select(), llvm::AArch64InstructionSelector::select(), selectCopy(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomain(), shrinkScalarCompare(), llvm::SITargetLowering::splitKillBlock(), tryAddToFoldList(), and llvm::X86InstrInfo::unfoldMemoryOperand().
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Set a MI flag.
Definition at line 166 of file MachineInstr.h.
References fuzzer::Flags.
Referenced by llvm::X86FrameLowering::emitPrologue(), llvm::X86FrameLowering::emitSPUpdate(), llvm::MIBundleBuilder::insert(), and llvm::MachineInstrBuilder::setMIFlag().
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Definition at line 170 of file MachineInstr.h.
References BundledPred, BundledSucc, fuzzer::Flags, and llvm::BitmaskEnumDetail::Mask().
Referenced by llvm::MachineInstrBuilder::setMIFlags().
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Assign this MachineInstr's memory reference descriptor list.
This does not transfer ownership.
Definition at line 1202 of file MachineInstr.h.
Referenced by llvm::TargetLoweringBase::emitPatchPoint(), emitPCMPSTRI(), emitPCMPSTRM(), llvm::TargetInstrInfo::foldMemoryOperand(), INITIALIZE_PASS(), llvm::ARMBaseInstrInfo::reMaterialize(), and llvm::MachineInstrBuilder::setMemRefs().
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Assign this MachineInstr's memory reference descriptor list.
First element in the pair is the begin iterator/pointer to the array; the second is the number of MemoryOperands. This does not transfer ownership of the underlying memory.
Definition at line 1210 of file MachineInstr.h.
References assert().
| void MachineInstr::setPhysRegsDeadExcept | ( | ArrayRef< unsigned > | UsedRegs, |
| const TargetRegisterInfo & | TRI | ||
| ) |
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
On instructions with register mask operands, also add implicit-def operands for all registers in UsedRegs.
Definition at line 2165 of file MachineInstr.cpp.
References llvm::ArrayRef< T >::begin(), E, llvm::ArrayRef< T >::end(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::none_of(), llvm::TargetRegisterInfo::regsOverlap(), and llvm::MachineOperand::setIsDead().
Referenced by llvm::FastISel::lowerCallTo(), and llvm::FastISel::selectPatchpoint().
Mark all subregister defs of register Reg with the undef flag.
This function is used when we determined to have a subregister def in an otherwise undefined super register.
Definition at line 2139 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::setIsUndef().
Referenced by llvm::RegisterOperands::adjustLaneLiveness().
| void MachineInstr::substituteRegister | ( | unsigned | FromReg, |
| unsigned | ToReg, | ||
| unsigned | SubIdx, | ||
| const TargetRegisterInfo & | RegInfo | ||
| ) |
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessary.
Definition at line 1521 of file MachineInstr.cpp.
References llvm::MachineOperand::getReg(), llvm::MCRegisterInfo::getSubReg(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineOperand::substPhysReg(), and llvm::MachineOperand::substVirtReg().
Referenced by llvm::HexagonInstrInfo::reduceLoopCount(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), and llvm::TargetInstrInfo::reMaterialize().
Add a tie between the register operands at DefIdx and UseIdx.
tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
The tie will cause the register allocator to ensure that the two operands are assigned the same physical register.
Tied operands are managed automatically for explicit operands in the MCInstrDesc. This method is for exceptional cases like inline asm.
Use and def operands can be tied together, indicated by a non-zero TiedTo field. TiedTo can have these values:
0: Operand is not tied to anything. 1 to TiedMax-1: Tied to getOperand(TiedTo-1). TiedMax: Tied to an operand >= TiedMax-1.
The tied def must be one of the first TiedMax operands on a normal instruction. INLINEASM instructions allow more tied defs.
Definition at line 1432 of file MachineInstr.cpp.
References assert(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isTied(), llvm::MachineOperand::isUse(), fuzzer::min(), and TiedMax.
Referenced by llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), and tieOpsIfNeeded().
| void MachineInstr::unbundleFromPred | ( | ) |
Break bundle above this instruction.
Definition at line 1138 of file MachineInstr.cpp.
References assert(), and llvm::MachineOperand::Pred.
Referenced by moveInstrOut(), and unbundleSingleMI().
| void MachineInstr::unbundleFromSucc | ( | ) |
Break bundle below this instruction.
Definition at line 1147 of file MachineInstr.cpp.
References assert().
Referenced by unbundleSingleMI().
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Break any tie involving OpIdx.
Definition at line 1233 of file MachineInstr.h.
References findTiedOperandIdx(), getOperand(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTied().
Referenced by llvm::SIInstrInfo::FoldImmediate(), and tryAddToFoldList().
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Returns a range that includes all operands that are register uses.
This may include unrelated operands which are not register uses.
Definition at line 334 of file MachineInstr.h.
References getDesc(), llvm::make_range(), operands_begin(), and operands_end().
Referenced by llvm::RegScavenger::backward(), and handleNormalInst().
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Returns a range that includes all operands that are register uses.
This may include unrelated operands which are not register uses.
Definition at line 339 of file MachineInstr.h.
References getDesc(), llvm::make_range(), operands_begin(), and operands_end().
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Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.
If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.
If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.
Definition at line 663 of file MachineInstr.h.
References hasProperty(), and llvm::MCID::UsesCustomInserter.
Referenced by INITIALIZE_PASS().
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Definition at line 114 of file MachineInstr.h.
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Definition at line 113 of file MachineInstr.h.
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Definition at line 128 of file MachineInstr.h.
1.8.6