LLVM  4.0.0
X86InstrInfo.h
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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
16 
18 #include "X86InstrFMA3Info.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
22 
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
25 
26 namespace llvm {
27  class MachineInstrBuilder;
28  class X86RegisterInfo;
29  class X86Subtarget;
30 
31 namespace X86 {
32  // X86 specific condition code. These correspond to X86_*_COND in
33  // X86InstrInfo.td. They must be kept in synch.
34 enum CondCode {
35  COND_A = 0,
36  COND_AE = 1,
37  COND_B = 2,
38  COND_BE = 3,
39  COND_E = 4,
40  COND_G = 5,
41  COND_GE = 6,
42  COND_L = 7,
43  COND_LE = 8,
44  COND_NE = 9,
45  COND_NO = 10,
46  COND_NP = 11,
47  COND_NS = 12,
48  COND_O = 13,
49  COND_P = 14,
50  COND_S = 15,
52 
53  // Artificial condition codes. These are used by AnalyzeBranch
54  // to indicate a block terminated with two conditional branches that together
55  // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
56  // which can't be represented on x86 with a single condition. These
57  // are never used in MachineInstrs and are inverses of one another.
60 
62 };
63 
64 // Turn condition code into conditional branch opcode.
65 unsigned GetCondBranchFromCond(CondCode CC);
66 
67 /// \brief Return a set opcode for the given condition and whether it has
68 /// a memory operand.
69 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
70 
71 /// \brief Return a cmov opcode for the given condition, register size in
72 /// bytes, and operand type.
73 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
74  bool HasMemoryOperand = false);
75 
76 // Turn CMov opcode into condition code.
77 CondCode getCondFromCMovOpc(unsigned Opc);
78 
79 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
80 /// e.g. turning COND_E to COND_NE.
82 } // end namespace X86;
83 
84 
85 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
86 /// a reference to a stub for a global, not the global itself.
87 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
88  switch (TargetFlag) {
89  case X86II::MO_DLLIMPORT: // dllimport stub.
90  case X86II::MO_GOTPCREL: // rip-relative GOT reference.
91  case X86II::MO_GOT: // normal GOT reference.
92  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
93  case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
94  return true;
95  default:
96  return false;
97  }
98 }
99 
100 /// isGlobalRelativeToPICBase - Return true if the specified global value
101 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
102 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
103 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
104  switch (TargetFlag) {
105  case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
106  case X86II::MO_GOT: // isPICStyleGOT: other global.
107  case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
108  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
109  case X86II::MO_TLVP: // ??? Pretty sure..
110  return true;
111  default:
112  return false;
113  }
114 }
115 
116 inline static bool isScale(const MachineOperand &MO) {
117  return MO.isImm() &&
118  (MO.getImm() == 1 || MO.getImm() == 2 ||
119  MO.getImm() == 4 || MO.getImm() == 8);
120 }
121 
122 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
123  if (MI.getOperand(Op).isFI())
124  return true;
125  return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
126  MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
128  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
129  (MI.getOperand(Op + X86::AddrDisp).isImm() ||
130  MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
131  MI.getOperand(Op + X86::AddrDisp).isCPI() ||
132  MI.getOperand(Op + X86::AddrDisp).isJTI());
133 }
134 
135 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
136  if (MI.getOperand(Op).isFI())
137  return true;
138  return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
139  MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
140 }
141 
142 class X86InstrInfo final : public X86GenInstrInfo {
143  X86Subtarget &Subtarget;
144  const X86RegisterInfo RI;
145 
146  /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
147  /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
148  ///
149  typedef DenseMap<unsigned,
150  std::pair<uint16_t, uint16_t> > RegOp2MemOpTableType;
151  RegOp2MemOpTableType RegOp2MemOpTable2Addr;
152  RegOp2MemOpTableType RegOp2MemOpTable0;
153  RegOp2MemOpTableType RegOp2MemOpTable1;
154  RegOp2MemOpTableType RegOp2MemOpTable2;
155  RegOp2MemOpTableType RegOp2MemOpTable3;
156  RegOp2MemOpTableType RegOp2MemOpTable4;
157 
158  /// MemOp2RegOpTable - Load / store unfolding opcode map.
159  ///
160  typedef DenseMap<unsigned,
161  std::pair<uint16_t, uint16_t> > MemOp2RegOpTableType;
162  MemOp2RegOpTableType MemOp2RegOpTable;
163 
164  static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
165  MemOp2RegOpTableType &M2RTable,
166  uint16_t RegOp, uint16_t MemOp, uint16_t Flags);
167 
168  virtual void anchor();
169 
170  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
171  MachineBasicBlock *&FBB,
173  SmallVectorImpl<MachineInstr *> &CondBranches,
174  bool AllowModify) const;
175 
176 public:
177  explicit X86InstrInfo(X86Subtarget &STI);
178 
179  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
180  /// such, whenever a client has an instance of instruction info, it should
181  /// always be able to get register info as well (through this method).
182  ///
183  const X86RegisterInfo &getRegisterInfo() const { return RI; }
184 
185  /// getSPAdjust - This returns the stack pointer adjustment made by
186  /// this instruction. For x86, we need to handle more complex call
187  /// sequences involving PUSHes.
188  int getSPAdjust(const MachineInstr &MI) const override;
189 
190  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
191  /// extension instruction. That is, it's like a copy where it's legal for the
192  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
193  /// true, then it's expected the pre-extension value is available as a subreg
194  /// of the result register. This also returns the sub-register index in
195  /// SubIdx.
197  unsigned &SrcReg, unsigned &DstReg,
198  unsigned &SubIdx) const override;
199 
200  unsigned isLoadFromStackSlot(const MachineInstr &MI,
201  int &FrameIndex) const override;
202  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
203  /// stack locations as well. This uses a heuristic so it isn't
204  /// reliable for correctness.
205  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
206  int &FrameIndex) const override;
207 
208  unsigned isStoreToStackSlot(const MachineInstr &MI,
209  int &FrameIndex) const override;
210  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
211  /// stack locations as well. This uses a heuristic so it isn't
212  /// reliable for correctness.
213  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
214  int &FrameIndex) const override;
215 
217  AliasAnalysis *AA) const override;
219  unsigned DestReg, unsigned SubIdx,
220  const MachineInstr &Orig,
221  const TargetRegisterInfo &TRI) const override;
222 
223  /// Given an operand within a MachineInstr, insert preceding code to put it
224  /// into the right format for a particular kind of LEA instruction. This may
225  /// involve using an appropriate super-register instead (with an implicit use
226  /// of the original) or creating a new virtual register and inserting COPY
227  /// instructions to get the data into the right class.
228  ///
229  /// Reference parameters are set to indicate how caller should add this
230  /// operand to the LEA instruction.
231  bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
232  unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc,
233  bool &isKill, bool &isUndef,
234  MachineOperand &ImplicitOp, LiveVariables *LV) const;
235 
236  /// convertToThreeAddress - This method must be implemented by targets that
237  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
238  /// may be able to convert a two-address instruction into a true
239  /// three-address instruction on demand. This allows the X86 target (for
240  /// example) to convert ADD and SHL instructions into LEA instructions if they
241  /// would require register copies due to two-addressness.
242  ///
243  /// This method returns a null pointer if the transformation cannot be
244  /// performed, otherwise it returns the new instruction.
245  ///
247  MachineInstr &MI,
248  LiveVariables *LV) const override;
249 
250  /// Returns true iff the routine could find two commutable operands in the
251  /// given machine instruction.
252  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
253  /// input values can be re-defined in this method only if the input values
254  /// are not pre-defined, which is designated by the special value
255  /// 'CommuteAnyOperandIndex' assigned to it.
256  /// If both of indices are pre-defined and refer to some operands, then the
257  /// method simply returns true if the corresponding operands are commutable
258  /// and returns false otherwise.
259  ///
260  /// For example, calling this method this way:
261  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
262  /// findCommutedOpIndices(MI, Op1, Op2);
263  /// can be interpreted as a query asking to find an operand that would be
264  /// commutable with the operand#1.
265  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
266  unsigned &SrcOpIdx2) const override;
267 
268  /// Returns true if the routine could find two commutable operands
269  /// in the given FMA instruction \p MI. Otherwise, returns false.
270  ///
271  /// \p SrcOpIdx1 and \p SrcOpIdx2 are INPUT and OUTPUT arguments.
272  /// The output indices of the commuted operands are returned in these
273  /// arguments. Also, the input values of these arguments may be preset either
274  /// to indices of operands that must be commuted or be equal to a special
275  /// value 'CommuteAnyOperandIndex' which means that the corresponding
276  /// operand index is not set and this method is free to pick any of
277  /// available commutable operands.
278  /// The parameter \p FMA3Group keeps the reference to the group of relative
279  /// FMA3 opcodes including register/memory forms of 132/213/231 opcodes.
280  ///
281  /// For example, calling this method this way:
282  /// unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex;
283  /// findFMA3CommutedOpIndices(MI, Idx1, Idx2, FMA3Group);
284  /// can be interpreted as a query asking if the operand #1 can be swapped
285  /// with any other available operand (e.g. operand #2, operand #3, etc.).
286  ///
287  /// The returned FMA opcode may differ from the opcode in the given MI.
288  /// For example, commuting the operands #1 and #3 in the following FMA
289  /// FMA213 #1, #2, #3
290  /// results into instruction with adjusted opcode:
291  /// FMA231 #3, #2, #1
293  unsigned &SrcOpIdx1,
294  unsigned &SrcOpIdx2,
295  const X86InstrFMA3Group &FMA3Group) const;
296 
297  /// Returns an adjusted FMA opcode that must be used in FMA instruction that
298  /// performs the same computations as the given \p MI but which has the
299  /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
300  /// It may return 0 if it is unsafe to commute the operands.
301  /// Note that a machine instruction (instead of its opcode) is passed as the
302  /// first parameter to make it possible to analyze the instruction's uses and
303  /// commute the first operand of FMA even when it seems unsafe when you look
304  /// at the opcode. For example, it is Ok to commute the first operand of
305  /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
306  ///
307  /// The returned FMA opcode may differ from the opcode in the given \p MI.
308  /// For example, commuting the operands #1 and #3 in the following FMA
309  /// FMA213 #1, #2, #3
310  /// results into instruction with adjusted opcode:
311  /// FMA231 #3, #2, #1
313  unsigned SrcOpIdx1,
314  unsigned SrcOpIdx2,
315  const X86InstrFMA3Group &FMA3Group) const;
316 
317  // Branch analysis.
318  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
320  MachineBasicBlock *&FBB,
322  bool AllowModify) const override;
323 
324  bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
325  int64_t &Offset,
326  const TargetRegisterInfo *TRI) const override;
329  bool AllowModify = false) const override;
330 
331  unsigned removeBranch(MachineBasicBlock &MBB,
332  int *BytesRemoved = nullptr) const override;
335  const DebugLoc &DL,
336  int *BytesAdded = nullptr) const override;
338  unsigned, unsigned, int&, int&, int&) const override;
340  const DebugLoc &DL, unsigned DstReg,
341  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
342  unsigned FalseReg) const override;
344  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
345  bool KillSrc) const override;
348  unsigned SrcReg, bool isKill, int FrameIndex,
349  const TargetRegisterClass *RC,
350  const TargetRegisterInfo *TRI) const override;
351 
352  void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
354  const TargetRegisterClass *RC,
357  SmallVectorImpl<MachineInstr*> &NewMIs) const;
358 
361  unsigned DestReg, int FrameIndex,
362  const TargetRegisterClass *RC,
363  const TargetRegisterInfo *TRI) const override;
364 
365  void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
367  const TargetRegisterClass *RC,
370  SmallVectorImpl<MachineInstr*> &NewMIs) const;
371 
372  bool expandPostRAPseudo(MachineInstr &MI) const override;
373 
374  /// Check whether the target can fold a load that feeds a subreg operand
375  /// (or a subreg operand that feeds a store).
376  bool isSubregFoldable() const override { return true; }
377 
378  /// foldMemoryOperand - If this target supports it, fold a load or store of
379  /// the specified stack slot into the specified machine instruction for the
380  /// specified operand(s). If this is possible, the target should perform the
381  /// folding and return true, otherwise it should return false. If it folds
382  /// the instruction, it is likely that the MachineInstruction the iterator
383  /// references has been changed.
384  MachineInstr *
386  ArrayRef<unsigned> Ops,
388  LiveIntervals *LIS = nullptr) const override;
389 
390  /// foldMemoryOperand - Same as the previous version except it allows folding
391  /// of any load and store from / to any address, not just from a specific
392  /// stack slot.
395  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
396  LiveIntervals *LIS = nullptr) const override;
397 
398  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
399  /// a store or a load and a store into two or more instruction. If this is
400  /// possible, returns true as well as the new instructions by reference.
401  bool
403  bool UnfoldLoad, bool UnfoldStore,
404  SmallVectorImpl<MachineInstr *> &NewMIs) const override;
405 
407  SmallVectorImpl<SDNode*> &NewNodes) const override;
408 
409  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
410  /// instruction after load / store are unfolded from an instruction of the
411  /// specified opcode. It returns zero if the specified unfolding is not
412  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
413  /// index of the operand which will hold the register holding the loaded
414  /// value.
415  unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
416  bool UnfoldLoad, bool UnfoldStore,
417  unsigned *LoadRegIndex = nullptr) const override;
418 
419  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
420  /// to determine if two loads are loading from the same base address. It
421  /// should only return true if the base pointers are the same and the
422  /// only differences between the two addresses are the offset. It also returns
423  /// the offsets by reference.
424  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
425  int64_t &Offset2) const override;
426 
427  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
428  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
429  /// be scheduled togther. On some targets if two loads are loading from
430  /// addresses in the same cache line, it's better if they are scheduled
431  /// together. This function takes two integers that represent the load offsets
432  /// from the common base address. It returns true if it decides it's desirable
433  /// to schedule the two loads together. "NumLoads" is the number of loads that
434  /// have already been scheduled after Load1.
435  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
436  int64_t Offset1, int64_t Offset2,
437  unsigned NumLoads) const override;
438 
439  bool shouldScheduleAdjacent(const MachineInstr &First,
440  const MachineInstr &Second) const override;
441 
442  void getNoopForMachoTarget(MCInst &NopInst) const override;
443 
444  bool
446 
447  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
448  /// instruction that defines the specified register class.
449  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
450 
451  /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
452  /// would clobber the EFLAGS condition register. Note the result may be
453  /// conservative. If it cannot definitely determine the safety after visiting
454  /// a few instructions in each direction it assumes it's not safe.
457 
458  /// True if MI has a condition code def, e.g. EFLAGS, that is
459  /// not marked dead.
460  bool hasLiveCondCodeDef(MachineInstr &MI) const;
461 
462  /// getGlobalBaseReg - Return a virtual register initialized with the
463  /// the global base register value. Output instructions required to
464  /// initialize the register in the function entry block, if necessary.
465  ///
466  unsigned getGlobalBaseReg(MachineFunction *MF) const;
467 
468  std::pair<uint16_t, uint16_t>
469  getExecutionDomain(const MachineInstr &MI) const override;
470 
471  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
472 
473  unsigned
474  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
475  const TargetRegisterInfo *TRI) const override;
476  unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
477  const TargetRegisterInfo *TRI) const override;
478  void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
479  const TargetRegisterInfo *TRI) const override;
480 
482  unsigned OpNum,
485  unsigned Size, unsigned Alignment,
486  bool AllowCommute) const;
487 
488  bool isHighLatencyDef(int opc) const override;
489 
490  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
491  const MachineRegisterInfo *MRI,
492  const MachineInstr &DefMI, unsigned DefIdx,
493  const MachineInstr &UseMI,
494  unsigned UseIdx) const override;
495 
496  bool useMachineCombiner() const override {
497  return true;
498  }
499 
500  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
501 
502  bool hasReassociableOperands(const MachineInstr &Inst,
503  const MachineBasicBlock *MBB) const override;
504 
505  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
506  MachineInstr &NewMI1,
507  MachineInstr &NewMI2) const override;
508 
509  /// analyzeCompare - For a comparison instruction, return the source registers
510  /// in SrcReg and SrcReg2 if having two register operands, and the value it
511  /// compares against in CmpValue. Return true if the comparison instruction
512  /// can be analyzed.
513  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
514  unsigned &SrcReg2, int &CmpMask,
515  int &CmpValue) const override;
516 
517  /// optimizeCompareInstr - Check if there exists an earlier instruction that
518  /// operates on the same source operands and sets flags in the same way as
519  /// Compare; remove Compare if possible.
520  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
521  unsigned SrcReg2, int CmpMask, int CmpValue,
522  const MachineRegisterInfo *MRI) const override;
523 
524  /// optimizeLoadInstr - Try to remove the load by folding it to a register
525  /// operand at the use. We fold the load instructions if and only if the
526  /// def and use are in the same BB. We only look at one load and see
527  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
528  /// defined by the load we are trying to fold. DefMI returns the machine
529  /// instruction that defines FoldAsLoadDefReg, and the function returns
530  /// the machine instruction generated due to folding.
532  const MachineRegisterInfo *MRI,
533  unsigned &FoldAsLoadDefReg,
534  MachineInstr *&DefMI) const override;
535 
536  std::pair<unsigned, unsigned>
537  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
538 
541 
542  bool isTailCall(const MachineInstr &Inst) const override;
543 
544 protected:
545  /// Commutes the operands in the given instruction by changing the operands
546  /// order and/or changing the instruction's opcode and/or the immediate value
547  /// operand.
548  ///
549  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
550  /// to be commuted.
551  ///
552  /// Do not call this method for a non-commutable instruction or
553  /// non-commutable operands.
554  /// Even though the instruction is commutable, the method may still
555  /// fail to commute the operands, null pointer is returned in such cases.
557  unsigned CommuteOpIdx1,
558  unsigned CommuteOpIdx2) const override;
559 
560 private:
561  MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
563  MachineInstr &MI,
564  LiveVariables *LV) const;
565 
566  /// Handles memory folding for special case instructions, for instance those
567  /// requiring custom manipulation of the address.
568  MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
569  unsigned OpNum,
572  unsigned Size, unsigned Align) const;
573 
574  /// isFrameOperand - Return true and the FrameIndex if the specified
575  /// operand and follow operands form a reference to the stack frame.
576  bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
577  int &FrameIndex) const;
578 
579  /// Returns true iff the routine could find two commutable operands in the
580  /// given machine instruction with 3 vector inputs.
581  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
582  /// input values can be re-defined in this method only if the input values
583  /// are not pre-defined, which is designated by the special value
584  /// 'CommuteAnyOperandIndex' assigned to it.
585  /// If both of indices are pre-defined and refer to some operands, then the
586  /// method simply returns true if the corresponding operands are commutable
587  /// and returns false otherwise.
588  ///
589  /// For example, calling this method this way:
590  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
591  /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
592  /// can be interpreted as a query asking to find an operand that would be
593  /// commutable with the operand#1.
594  bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
595  unsigned &SrcOpIdx1,
596  unsigned &SrcOpIdx2) const;
597 };
598 
599 } // End llvm namespace
600 
601 #endif
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:183
unsigned GetCondBranchFromCond(CondCode CC)
bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:116
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool shouldScheduleAdjacent(const MachineInstr &First, const MachineInstr &Second) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
CondCode getCondFromCMovOpc(unsigned Opc)
Return condition code of a CMov opcode.
bool isHighLatencyDef(int opc) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override
Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register rea...
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
A debug info location.
Definition: DebugLoc.h:34
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:97
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
Represents a predicate at the MachineFunction level.
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:39
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
bool findFMA3CommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns true if the routine could find two commutable operands in the given FMA instruction MI...
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:197
A description of a memory reference used in the backend.
struct fuzzer::@269 Flags
Provide an instruction scheduling machine model to CodeGen passes.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use...
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:32
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:87
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
Reg
All possible values of the reg field in the ModR/M byte.
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction...
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:135
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:103
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:82
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
MachineBasicBlock * MBB
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp, LiveVariables *LV) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool isUnpredicatedTerminator(const MachineInstr &MI) const override
int64_t getImm() const
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:122
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:192
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction. ...
unsigned const MachineRegisterInfo * MRI
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:203
MachineInstrBuilder & UseMI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
X86InstrInfo(X86Subtarget &STI)
uint32_t Offset
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:496
This class is used to group {132, 213, 231} forms of FMA opcodes together.
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand=false)
Return a set opcode for the given condition and whether it has a memory operand.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS c...
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
Iterator for intrusive lists based on ilist_node.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:166
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well...
MachineOperand class - Representation of each machine instruction operand.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Represents one node in the SelectionDAG.
void getNoopForMachoTarget(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given condition, register size in bytes, and operand type...
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:376
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
Representation of each machine instruction.
Definition: MachineInstr.h:52
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:89
#define I(x, y, z)
Definition: MD5.cpp:54
#define N
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
bool isTailCall(const MachineInstr &Inst) const override
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:75
IRTranslator LLVM IR MI
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction...
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:187
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override