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LLVM
4.0.0
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Namespaces | |
| EncValues | |
| Hwreg | |
| SDWA | |
| SendMsg | |
Classes | |
| struct | IsaVersion |
Variables | |
| const uint64_t | RSRC_DATA_FORMAT = 0xf00000000000LL |
| const uint64_t | RSRC_ELEMENT_SIZE_SHIFT = (32 + 19) |
| const uint64_t | RSRC_INDEX_STRIDE_SHIFT = (32 + 21) |
| const uint64_t | RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23) |
| enum llvm::AMDGPU::Fixups |
| Enumerator | |
|---|---|
| fixup_si_sopp_br |
16-bit PC relative fixup for SOPP branch instructions. |
| LastTargetFixupKind | |
| NumTargetFixupKinds | |
Definition at line 17 of file AMDGPUFixupKinds.h.
Definition at line 89 of file SIDefines.h.
| Enumerator | |
|---|---|
| TF_LONG_BRANCH_FORWARD | |
| TF_LONG_BRANCH_BACKWARD | |
Definition at line 767 of file SIInstrInfo.h.
Waitcnt for given isa Version. Definition at line 243 of file AMDGPUBaseInfo.cpp.
Referenced by decodeWaitcnt().
Waitcnt for given isa Version. Definition at line 247 of file AMDGPUBaseInfo.cpp.
Referenced by decodeWaitcnt().
Waitcnt for given isa Version. Definition at line 239 of file AMDGPUBaseInfo.cpp.
Referenced by decodeWaitcnt().
| void llvm::AMDGPU::decodeWaitcnt | ( | IsaVersion | Version, |
| unsigned | Waitcnt, | ||
| unsigned & | Vmcnt, | ||
| unsigned & | Expcnt, | ||
| unsigned & | Lgkmcnt | ||
| ) |
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.
Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] Expcnt = Waitcnt[6:4] Lgkmcnt = Waitcnt[11:8]
Definition at line 251 of file AMDGPUBaseInfo.cpp.
References decodeExpcnt(), decodeLgkmcnt(), and decodeVmcnt().
Waitcnt with encoded Expcnt for given isa Version. Definition at line 262 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
Waitcnt with encoded Lgkmcnt for given isa Version. Definition at line 266 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
Waitcnt with encoded Vmcnt for given isa Version. Definition at line 258 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
| unsigned llvm::AMDGPU::encodeWaitcnt | ( | IsaVersion | Version, |
| unsigned | Vmcnt, | ||
| unsigned | Expcnt, | ||
| unsigned | Lgkmcnt | ||
| ) |
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[3:0] = Vmcnt Waitcnt[6:4] = Expcnt Waitcnt[11:8] = Lgkmcnt
Vmcnt, Expcnt and Lgkmcnt for given isa Version. Definition at line 270 of file AMDGPUBaseInfo.cpp.
References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), and getWaitcntBitMask().
| LLVM_READONLY int llvm::AMDGPU::getAddr64Inst | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::legalizeOperands().
| LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection().
| LLVM_READONLY int llvm::AMDGPU::getAtomicRetOp | ( | uint16_t | Opcode | ) |
| LLVM_READONLY int llvm::AMDGPU::getCommuteOrig | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
| LLVM_READONLY int llvm::AMDGPU::getCommuteRev | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
| unsigned llvm::AMDGPU::getExpcntBitMask | ( | IsaVersion | Version | ) |
Version. Definition at line 231 of file AMDGPUBaseInfo.cpp.
| MCSection * llvm::AMDGPU::getHSADataGlobalAgentSection | ( | MCContext & | Ctx | ) |
Definition at line 145 of file AMDGPUBaseInfo.cpp.
References llvm::MCContext::getELFSection(), llvm::ELF::SHF_ALLOC, llvm::ELF::SHF_AMDGPU_HSA_AGENT, llvm::ELF::SHF_AMDGPU_HSA_GLOBAL, llvm::ELF::SHF_WRITE, and llvm::ELF::SHT_PROGBITS.
| MCSection * llvm::AMDGPU::getHSADataGlobalProgramSection | ( | MCContext & | Ctx | ) |
Definition at line 152 of file AMDGPUBaseInfo.cpp.
References llvm::MCContext::getELFSection(), llvm::ELF::SHF_ALLOC, llvm::ELF::SHF_AMDGPU_HSA_GLOBAL, llvm::ELF::SHF_WRITE, and llvm::ELF::SHT_PROGBITS.
| MCSection * llvm::AMDGPU::getHSARodataReadonlyAgentSection | ( | MCContext & | Ctx | ) |
Definition at line 158 of file AMDGPUBaseInfo.cpp.
References llvm::MCContext::getELFSection(), llvm::ELF::SHF_ALLOC, llvm::ELF::SHF_AMDGPU_HSA_AGENT, llvm::ELF::SHF_AMDGPU_HSA_READONLY, and llvm::ELF::SHT_PROGBITS.
| MCSection * llvm::AMDGPU::getHSATextSection | ( | MCContext & | Ctx | ) |
Definition at line 137 of file AMDGPUBaseInfo.cpp.
References llvm::MCContext::getELFSection(), llvm::ELF::SHF_ALLOC, llvm::ELF::SHF_AMDGPU_HSA_AGENT, llvm::ELF::SHF_AMDGPU_HSA_CODE, llvm::ELF::SHF_EXECINSTR, llvm::ELF::SHF_WRITE, and llvm::ELF::SHT_PROGBITS.
Definition at line 279 of file AMDGPUBaseInfo.cpp.
References getIntegerAttribute().
Referenced by PrivateMemoryInputPtr().
| int llvm::AMDGPU::getIntegerAttribute | ( | const Function & | F, |
| StringRef | Name, | ||
| int | Default | ||
| ) |
F's Name attribute.Default if attribute is not present.Default and emits error if requested value cannot be converted to integer. Definition at line 180 of file AMDGPUBaseInfo.cpp.
References A, llvm::LLVMContext::emitError(), llvm::StringRef::getAsInteger(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), and llvm::Attribute::isStringAttribute().
Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), getInitialPSInputAddr(), llvm::SIRegisterInfo::getMaxNumSGPRs(), and llvm::SIRegisterInfo::getMaxNumVGPRs().
| std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute | ( | const Function & | F, |
| StringRef | Name, | ||
| std::pair< int, int > | Default, | ||
| bool | OnlyFirstRequired = false |
||
| ) |
F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).Default if attribute is not present.Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present. Definition at line 195 of file AMDGPUBaseInfo.cpp.
References A, llvm::LLVMContext::emitError(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), llvm::Attribute::isStringAttribute(), and llvm::StringRef::split().
Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().
| IsaVersion llvm::AMDGPU::getIsaVersion | ( | const FeatureBitset & | Features | ) |
Definition at line 82 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUAsmPrinter::EmitStartOfAsmFile(), and initDefaultAMDKernelCodeT().
| int llvm::AMDGPU::getLDSNoRetOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().
| unsigned llvm::AMDGPU::getLgkmcntBitMask | ( | IsaVersion | Version | ) |
Version. Definition at line 235 of file AMDGPUBaseInfo.cpp.
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static |
Definition at line 77 of file AMDGPUInstrInfo.cpp.
Referenced by llvm::AMDGPUInstrInfo::pseudoToMCOpcode().
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition at line 311 of file AMDGPUBaseInfo.cpp.
References assert(), isCI(), and isSI().
Referenced by llvm::AMDGPUDisassembler::decodeSpecialReg32(), llvm::AMDGPUDisassembler::decodeSpecialReg64(), and llvm::AMDGPUMCInstLower::lowerOperand().
| LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx | ( | uint16_t | Opcode, |
| uint16_t | NamedIdx | ||
| ) |
Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getMemOpBaseRegImmOfs(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::hasModifiers(), isInlineConstantIfFolded(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), nodesHaveSameOperandValue(), removeModOperands(), tryAddToFoldList(), tryConstantFoldOp(), and llvm::SIInstrInfo::verifyInstruction().
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inline |
Definition at line 173 of file AMDGPUBaseInfo.h.
References llvm_unreachable, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_INT64, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, and llvm::MCOperandInfo::OperandType.
Referenced by getOperandSize().
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inline |
Definition at line 199 of file AMDGPUBaseInfo.h.
References getOperandSize(), and llvm::MCInstrDesc::OpInfo.
Get the size in bits of a register from the register class RC.
Definition at line 359 of file AMDGPUBaseInfo.cpp.
References llvm_unreachable.
Referenced by getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().
Get the size in bits of a register from the register class RC.
Definition at line 389 of file AMDGPUBaseInfo.cpp.
References llvm::MCRegisterClass::getID(), and getRegBitWidth().
| unsigned llvm::AMDGPU::getRegOperandSize | ( | const MCRegisterInfo * | MRI, |
| const MCInstrDesc & | Desc, | ||
| unsigned | OpNo | ||
| ) |
Get size of register operand.
Definition at line 393 of file AMDGPUBaseInfo.cpp.
References getRegBitWidth(), llvm::MCRegisterInfo::getRegClass(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
| LLVM_READONLY int llvm::AMDGPU::getSOPKOp | ( | uint16_t | Opcode | ) |
Referenced by shrinkScalarCompare().
| unsigned llvm::AMDGPU::getVmcntBitMask | ( | IsaVersion | Version | ) |
Version. Definition at line 227 of file AMDGPUBaseInfo.cpp.
| LLVM_READONLY int llvm::AMDGPU::getVOPe32 | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding().
| LLVM_READONLY int llvm::AMDGPU::getVOPe64 | ( | uint16_t | Opcode | ) |
| unsigned llvm::AMDGPU::getWaitcntBitMask | ( | IsaVersion | Version | ) |
Version. Definition at line 220 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
| void llvm::AMDGPU::initDefaultAMDKernelCodeT | ( | amd_kernel_code_t & | Header, |
| const FeatureBitset & | Features | ||
| ) |
Definition at line 114 of file AMDGPUBaseInfo.cpp.
References amd_kernel_code_s::amd_kernel_code_version_major, amd_kernel_code_s::amd_kernel_code_version_minor, amd_kernel_code_s::amd_machine_kind, amd_kernel_code_s::amd_machine_version_major, amd_kernel_code_s::amd_machine_version_minor, amd_kernel_code_s::amd_machine_version_stepping, getIsaVersion(), amd_kernel_code_s::group_segment_alignment, amd_kernel_code_s::kernarg_segment_alignment, amd_kernel_code_s::kernel_code_entry_byte_offset, llvm::AMDGPU::IsaVersion::Major, llvm::AMDGPU::IsaVersion::Minor, amd_kernel_code_s::private_segment_alignment, llvm::AMDGPU::IsaVersion::Stepping, and amd_kernel_code_s::wavefront_size.
Definition at line 303 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by getMCReg().
| bool llvm::AMDGPU::isCompute | ( | CallingConv::ID | cc | ) |
Definition at line 295 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, and isShader().
Referenced by llvm::SIFrameLowering::emitPrologue(), llvm::AMDGPUSubtarget::enableIEEEBit(), llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().
Definition at line 168 of file AMDGPUBaseInfo.cpp.
References llvm::PointerType::getAddressSpace(), llvm::GlobalValue::getType(), and AMDGPUAS::GLOBAL_ADDRESS.
Definition at line 164 of file AMDGPUBaseInfo.cpp.
References llvm::PointerType::getAddressSpace(), llvm::GlobalValue::getType(), and AMDGPUAS::LOCAL_ADDRESS.
Referenced by llvm::AMDGPUAsmPrinter::EmitGlobalVariable().
| LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 | ( | int16_t | Literal, |
| bool | HasInv2Pi | ||
| ) |
Definition at line 442 of file AMDGPUBaseInfo.cpp.
References assert().
Referenced by llvm::SIInstrInfo::isInlineConstant().
| LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 | ( | int32_t | Literal, |
| bool | HasInv2Pi | ||
| ) |
Definition at line 416 of file AMDGPUBaseInfo.cpp.
References llvm::FloatToBits().
Referenced by llvm::SIInstrInfo::isInlineConstant().
| LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 | ( | int64_t | Literal, |
| bool | HasInv2Pi | ||
| ) |
Is this literal inlinable.
Definition at line 399 of file AMDGPUBaseInfo.cpp.
References llvm::DoubleToBits().
Referenced by llvm::SIInstrInfo::isInlineConstant().
Definition at line 172 of file AMDGPUBaseInfo.cpp.
References AMDGPUAS::CONSTANT_ADDRESS, llvm::PointerType::getAddressSpace(), and llvm::GlobalValue::getType().
Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().
| bool llvm::AMDGPU::isShader | ( | CallingConv::ID | cc | ) |
Definition at line 283 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_PS, and llvm::CallingConv::AMDGPU_VS.
Referenced by llvm::SIInstrInfo::calculateLDSSpillAddress(), isArgPassedInSGPR(), isCompute(), llvm::AMDGPUSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::SISubtarget::isVGPRSpillingEnabled(), llvm::SIInstrInfo::legalizeOperands(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::LowerReturn(), and PrivateMemoryInputPtr().
Definition at line 299 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by getMCReg().
Is this floating-point operand?
Definition at line 336 of file AMDGPUBaseInfo.cpp.
References OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.
Does this opearnd support only inlinable literals?
Definition at line 351 of file AMDGPUBaseInfo.cpp.
References OPERAND_REG_INLINE_C_FIRST, OPERAND_REG_INLINE_C_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.
Can this operand also contain immediate values?
Definition at line 330 of file AMDGPUBaseInfo.cpp.
References OPERAND_SRC_FIRST, OPERAND_SRC_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.
Definition at line 307 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by llvm::AMDGPUDisassembler::getInstruction().
TT, false otherwise. Definition at line 176 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::AMDHSA, and llvm::Triple::getOS().
Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().
| const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL |
Definition at line 761 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat(), and llvm::SIInstrInfo::getScratchRsrcWords23().
| const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19) |
Definition at line 762 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().
| const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21) |
Definition at line 763 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().
| const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23) |
Definition at line 764 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().
1.8.6