31 #define DEBUG_TYPE "mccodeemitter"
33 STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
37 SparcMCCodeEmitter(
const SparcMCCodeEmitter &) =
delete;
38 void operator=(
const SparcMCCodeEmitter &) =
delete;
44 : MCII(mcii), Ctx(ctx) {}
46 ~SparcMCCodeEmitter()
override {}
54 uint64_t getBinaryCodeForInstr(
const MCInst &
MI,
64 unsigned getCallTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
70 unsigned getBranchPredTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
73 unsigned getBranchOnRegTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
78 uint64_t computeAvailableFeatures(
const FeatureBitset &FB)
const;
79 void verifyInstructionPredicates(
const MCInst &
MI,
80 uint64_t AvailableFeatures)
const;
87 return new SparcMCCodeEmitter(MCII, Ctx);
93 verifyInstructionPredicates(MI,
96 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
98 if (Ctx.getAsmInfo()->isLittleEndian()) {
105 unsigned tlsOpNo = 0;
112 case SP::TLS_LDXrr: tlsOpNo = 3;
break;
116 uint64_t
op = getMachineOpValue(MI, MO, Fixups, STI);
117 assert(op == 0 &&
"Unexpected operand value!");
125 unsigned SparcMCCodeEmitter::
131 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
138 if (
const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
145 if (Expr->evaluateAsAbsolute(Res))
152 unsigned SparcMCCodeEmitter::
153 getCallTargetOpValue(
const MCInst &MI,
unsigned OpNo,
158 return getMachineOpValue(MI, MO, Fixups, STI);
167 "Unexpected expression in TLS_CALL");
169 assert(SymExpr->getSymbol().getName() ==
"__tls_get_addr" &&
170 "Unexpected function for TLS_CALL");
193 return getMachineOpValue(MI, MO, Fixups, STI);
200 unsigned SparcMCCodeEmitter::
201 getBranchPredTargetOpValue(
const MCInst &MI,
unsigned OpNo,
206 return getMachineOpValue(MI, MO, Fixups, STI);
212 unsigned SparcMCCodeEmitter::
213 getBranchOnRegTargetOpValue(
const MCInst &MI,
unsigned OpNo,
218 return getMachineOpValue(MI, MO, Fixups, STI);
228 #define ENABLE_INSTR_PREDICATE_VERIFIER
229 #include "SparcGenMCCodeEmitter.inc"
void push_back(const T &Elt)
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
STATISTIC(NumFunctions,"Total number of functions")
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Base class for the full range of assembler expressions which are needed for parsing.
Represent a reference to a symbol from inside an expression.
Context object for machine code objects.
unsigned getReg() const
Returns the register number.
Instances of this class represent a single low-level machine instruction.
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const MCExpr * getExpr() const
unsigned const MachineRegisterInfo * MRI
MCCodeEmitter - Generic instruction encoding interface.
Interface to description of machine instruction set.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
VariantKind getKind() const
getOpcode - Get the kind of this expression.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
fixup_sparc_bpr - 16-bit fixup for bpr
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
unsigned getOpcode() const
MCSubtargetInfo - Generic base class for all target subtargets.
References to labels and assigned expressions.
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
fixup_sparc_br22 - 22-bit PC relative relocation for branches
This class implements an extremely fast bulk output stream that can only output to a stream...
Instances of this class represent operands of the MCInst class.
const MCOperand & getOperand(unsigned i) const