LLVM  4.0.0
MipsAsmPrinter.cpp
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1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
12 //
13 //===----------------------------------------------------------------------===//
14 
18 #include "Mips.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetMachine.h"
23 #include "MipsTargetStreamer.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/Twine.h"
32 #include "llvm/IR/BasicBlock.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/Mangler.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCSectionELF.h"
44 #include "llvm/MC/MCSymbolELF.h"
45 #include "llvm/Support/ELF.h"
50 #include <string>
51 
52 using namespace llvm;
53 
54 #define DEBUG_TYPE "mips-asm-printer"
55 
56 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
57  return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
58 }
59 
62 
64  if (Subtarget->inMips16Mode())
65  for (std::map<
66  const char *,
67  const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
68  it = MipsFI->StubsNeeded.begin();
69  it != MipsFI->StubsNeeded.end(); ++it) {
70  const char *Symbol = it->first;
71  const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
72  if (StubsNeeded.find(Symbol) == StubsNeeded.end())
73  StubsNeeded[Symbol] = Signature;
74  }
75  MCP = MF.getConstantPool();
76 
77  // In NaCl, all indirect jump targets must be aligned to bundle size.
78  if (Subtarget->isTargetNaCl())
79  NaClAlignIndirectJumpTargets(MF);
80 
82  return true;
83 }
84 
85 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
86  MCOp = MCInstLowering.LowerOperand(MO);
87  return MCOp.isValid();
88 }
89 
90 #include "MipsGenMCPseudoLowering.inc"
91 
92 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
93 // JALR, or JALR64 as appropriate for the target
94 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
95  const MachineInstr *MI) {
96  bool HasLinkReg = false;
97  bool InMicroMipsMode = Subtarget->inMicroMipsMode();
98  MCInst TmpInst0;
99 
100  if (Subtarget->hasMips64r6()) {
101  // MIPS64r6 should use (JALR64 ZERO_64, $rs)
102  TmpInst0.setOpcode(Mips::JALR64);
103  HasLinkReg = true;
104  } else if (Subtarget->hasMips32r6()) {
105  // MIPS32r6 should use (JALR ZERO, $rs)
106  if (InMicroMipsMode)
107  TmpInst0.setOpcode(Mips::JRC16_MMR6);
108  else {
109  TmpInst0.setOpcode(Mips::JALR);
110  HasLinkReg = true;
111  }
112  } else if (Subtarget->inMicroMipsMode())
113  // microMIPS should use (JR_MM $rs)
114  TmpInst0.setOpcode(Mips::JR_MM);
115  else {
116  // Everything else should use (JR $rs)
117  TmpInst0.setOpcode(Mips::JR);
118  }
119 
120  MCOperand MCOp;
121 
122  if (HasLinkReg) {
123  unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
124  TmpInst0.addOperand(MCOperand::createReg(ZeroReg));
125  }
126 
127  lowerOperand(MI->getOperand(0), MCOp);
128  TmpInst0.addOperand(MCOp);
129 
130  EmitToStreamer(OutStreamer, TmpInst0);
131 }
132 
134  MipsTargetStreamer &TS = getTargetStreamer();
136 
137  if (MI->isDebugValue()) {
138  SmallString<128> Str;
139  raw_svector_ostream OS(Str);
140 
141  PrintDebugValueComment(MI, OS);
142  return;
143  }
144 
145  // If we just ended a constant pool, mark it as such.
146  if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
147  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
148  InConstantPool = false;
149  }
150  if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
151  // CONSTPOOL_ENTRY - This instruction represents a floating
152  //constant pool in the function. The first operand is the ID#
153  // for this instruction, the second is the index into the
154  // MachineConstantPool that this is, the third is the size in
155  // bytes of this constant pool entry.
156  // The required alignment is specified on the basic block holding this MI.
157  //
158  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
159  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
160 
161  // If this is the first entry of the pool, mark it.
162  if (!InConstantPool) {
163  OutStreamer->EmitDataRegion(MCDR_DataRegion);
164  InConstantPool = true;
165  }
166 
167  OutStreamer->EmitLabel(GetCPISymbol(LabelId));
168 
169  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
170  if (MCPE.isMachineConstantPoolEntry())
172  else
174  return;
175  }
176 
177 
180 
181  do {
182  // Do any auto-generated pseudo lowerings.
183  if (emitPseudoExpansionLowering(*OutStreamer, &*I))
184  continue;
185 
186  if (I->getOpcode() == Mips::PseudoReturn ||
187  I->getOpcode() == Mips::PseudoReturn64 ||
188  I->getOpcode() == Mips::PseudoIndirectBranch ||
189  I->getOpcode() == Mips::PseudoIndirectBranch64 ||
190  I->getOpcode() == Mips::TAILCALLREG ||
191  I->getOpcode() == Mips::TAILCALLREG64) {
192  emitPseudoIndirectBranch(*OutStreamer, &*I);
193  continue;
194  }
195 
196  // The inMips16Mode() test is not permanent.
197  // Some instructions are marked as pseudo right now which
198  // would make the test fail for the wrong reason but
199  // that will be fixed soon. We need this here because we are
200  // removing another test for this situation downstream in the
201  // callchain.
202  //
203  if (I->isPseudo() && !Subtarget->inMips16Mode()
204  && !isLongBranchPseudo(I->getOpcode()))
205  llvm_unreachable("Pseudo opcode found in EmitInstruction()");
206 
207  MCInst TmpInst0;
208  MCInstLowering.Lower(&*I, TmpInst0);
209  EmitToStreamer(*OutStreamer, TmpInst0);
210  } while ((++I != E) && I->isInsideBundle()); // Delay slot check
211 }
212 
213 //===----------------------------------------------------------------------===//
214 //
215 // Mips Asm Directives
216 //
217 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
218 // Describe the stack frame.
219 //
220 // -- Mask directives "(f)mask bitmask, offset"
221 // Tells the assembler which registers are saved and where.
222 // bitmask - contain a little endian bitset indicating which registers are
223 // saved on function prologue (e.g. with a 0x80000000 mask, the
224 // assembler knows the register 31 (RA) is saved at prologue.
225 // offset - the position before stack pointer subtraction indicating where
226 // the first saved register on prologue is located. (e.g. with a
227 //
228 // Consider the following function prologue:
229 //
230 // .frame $fp,48,$ra
231 // .mask 0xc0000000,-8
232 // addiu $sp, $sp, -48
233 // sw $ra, 40($sp)
234 // sw $fp, 36($sp)
235 //
236 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
237 // 30 (FP) are saved at prologue. As the save order on prologue is from
238 // left to right, RA is saved first. A -8 offset means that after the
239 // stack pointer subtration, the first register in the mask (RA) will be
240 // saved at address 48-8=40.
241 //
242 //===----------------------------------------------------------------------===//
243 
244 //===----------------------------------------------------------------------===//
245 // Mask directives
246 //===----------------------------------------------------------------------===//
247 
248 // Create a bitmask with all callee saved registers for CPU or Floating Point
249 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
251  // CPU and FPU Saved Registers Bitmasks
252  unsigned CPUBitmask = 0, FPUBitmask = 0;
253  int CPUTopSavedRegOff, FPUTopSavedRegOff;
254 
255  // Set the CPU and FPU Bitmasks
256  const MachineFrameInfo &MFI = MF->getFrameInfo();
258  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
259  // size of stack area to which FP callee-saved regs are saved.
260  unsigned CPURegSize = Mips::GPR32RegClass.getSize();
261  unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
262  unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
263  bool HasAFGR64Reg = false;
264  unsigned CSFPRegsSize = 0;
265 
266  for (const auto &I : CSI) {
267  unsigned Reg = I.getReg();
268  unsigned RegNum = TRI->getEncodingValue(Reg);
269 
270  // If it's a floating point register, set the FPU Bitmask.
271  // If it's a general purpose register, set the CPU Bitmask.
272  if (Mips::FGR32RegClass.contains(Reg)) {
273  FPUBitmask |= (1 << RegNum);
274  CSFPRegsSize += FGR32RegSize;
275  } else if (Mips::AFGR64RegClass.contains(Reg)) {
276  FPUBitmask |= (3 << RegNum);
277  CSFPRegsSize += AFGR64RegSize;
278  HasAFGR64Reg = true;
279  } else if (Mips::GPR32RegClass.contains(Reg))
280  CPUBitmask |= (1 << RegNum);
281  }
282 
283  // FP Regs are saved right below where the virtual frame pointer points to.
284  FPUTopSavedRegOff = FPUBitmask ?
285  (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
286 
287  // CPU Regs are saved below FP Regs.
288  CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
289 
290  MipsTargetStreamer &TS = getTargetStreamer();
291  // Print CPUBitmask
292  TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
293 
294  // Print FPUBitmask
295  TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
296 }
297 
298 //===----------------------------------------------------------------------===//
299 // Frame and Set directives
300 //===----------------------------------------------------------------------===//
301 
302 /// Frame Directive
305 
306  unsigned stackReg = RI.getFrameRegister(*MF);
307  unsigned returnReg = RI.getRARegister();
308  unsigned stackSize = MF->getFrameInfo().getStackSize();
309 
310  getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
311 }
312 
313 /// Emit Set directives.
315  switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
316  case MipsABIInfo::ABI::O32: return "abi32";
317  case MipsABIInfo::ABI::N32: return "abiN32";
318  case MipsABIInfo::ABI::N64: return "abi64";
319  default: llvm_unreachable("Unknown Mips ABI");
320  }
321 }
322 
324  MipsTargetStreamer &TS = getTargetStreamer();
325 
326  // NaCl sandboxing requires that indirect call instructions are masked.
327  // This means that function entry points should be bundle-aligned.
328  if (Subtarget->isTargetNaCl())
330 
331  if (Subtarget->inMicroMipsMode()) {
333  TS.setUsesMicroMips();
334  } else
336 
337  if (Subtarget->inMips16Mode())
339  else
341 
343  OutStreamer->EmitLabel(CurrentFnSym);
344 }
345 
346 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
347 /// the first basic block in the function.
349  MipsTargetStreamer &TS = getTargetStreamer();
350 
352 
353  bool IsNakedFunction = MF->getFunction()->hasFnAttribute(Attribute::Naked);
354  if (!IsNakedFunction)
356 
357  if (!IsNakedFunction)
359 
360  if (!Subtarget->inMips16Mode()) {
364  }
365 }
366 
367 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
368 /// the last basic block in the function.
370  MipsTargetStreamer &TS = getTargetStreamer();
371 
372  // There are instruction for this macros, but they must
373  // always be at the function end, and we can't emit and
374  // break with BB logic.
375  if (!Subtarget->inMips16Mode()) {
376  TS.emitDirectiveSetAt();
379  }
381  // Make sure to terminate any constant pools that were at the end
382  // of the function.
383  if (!InConstantPool)
384  return;
385  InConstantPool = false;
386  OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
387 }
388 
390  MipsTargetStreamer &TS = getTargetStreamer();
391  if (MBB.size() == 0)
392  TS.emitDirectiveInsn();
393 }
394 
395 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
396 /// exactly one predecessor and the control transfer mechanism between
397 /// the predecessor and this block is a fall-through.
399  MBB) const {
400  // The predecessor has to be immediately before this block.
401  const MachineBasicBlock *Pred = *MBB->pred_begin();
402 
403  // If the predecessor is a switch statement, assume a jump table
404  // implementation, so it is not a fall through.
405  if (const BasicBlock *bb = Pred->getBasicBlock())
406  if (isa<SwitchInst>(bb->getTerminator()))
407  return false;
408 
409  // If this is a landing pad, it isn't a fall through. If it has no preds,
410  // then nothing falls through to it.
411  if (MBB->isEHPad() || MBB->pred_empty())
412  return false;
413 
414  // If there isn't exactly one predecessor, it can't be a fall through.
416  ++PI2;
417 
418  if (PI2 != MBB->pred_end())
419  return false;
420 
421  // The predecessor has to be immediately before this block.
422  if (!Pred->isLayoutSuccessor(MBB))
423  return false;
424 
425  // If the block is completely empty, then it definitely does fall through.
426  if (Pred->empty())
427  return true;
428 
429  // Otherwise, check the last instruction.
430  // Check if the last terminator is an unconditional branch.
432  while (I != Pred->begin() && !(--I)->isTerminator()) ;
433 
434  return !I->isBarrier();
435 }
436 
437 // Print out an operand for an inline asm expression.
438 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
439  unsigned AsmVariant, const char *ExtraCode,
440  raw_ostream &O) {
441  // Does this asm operand have a single letter operand modifier?
442  if (ExtraCode && ExtraCode[0]) {
443  if (ExtraCode[1] != 0) return true; // Unknown modifier.
444 
445  const MachineOperand &MO = MI->getOperand(OpNum);
446  switch (ExtraCode[0]) {
447  default:
448  // See if this is a generic print operand
449  return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
450  case 'X': // hex const int
452  return true;
453  O << "0x" << Twine::utohexstr(MO.getImm());
454  return false;
455  case 'x': // hex const int (low 16 bits)
457  return true;
458  O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
459  return false;
460  case 'd': // decimal const int
462  return true;
463  O << MO.getImm();
464  return false;
465  case 'm': // decimal const int minus 1
467  return true;
468  O << MO.getImm() - 1;
469  return false;
470  case 'z': {
471  // $0 if zero, regular printing otherwise
472  if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
473  O << "$0";
474  return false;
475  }
476  // If not, call printOperand as normal.
477  break;
478  }
479  case 'D': // Second part of a double word register operand
480  case 'L': // Low order register of a double word register operand
481  case 'M': // High order register of a double word register operand
482  {
483  if (OpNum == 0)
484  return true;
485  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
486  if (!FlagsOP.isImm())
487  return true;
488  unsigned Flags = FlagsOP.getImm();
489  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
490  // Number of registers represented by this operand. We are looking
491  // for 2 for 32 bit mode and 1 for 64 bit mode.
492  if (NumVals != 2) {
493  if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
494  unsigned Reg = MO.getReg();
495  O << '$' << MipsInstPrinter::getRegisterName(Reg);
496  return false;
497  }
498  return true;
499  }
500 
501  unsigned RegOp = OpNum;
502  if (!Subtarget->isGP64bit()){
503  // Endianness reverses which register holds the high or low value
504  // between M and L.
505  switch(ExtraCode[0]) {
506  case 'M':
507  RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
508  break;
509  case 'L':
510  RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
511  break;
512  case 'D': // Always the second part
513  RegOp = OpNum + 1;
514  }
515  if (RegOp >= MI->getNumOperands())
516  return true;
517  const MachineOperand &MO = MI->getOperand(RegOp);
518  if (!MO.isReg())
519  return true;
520  unsigned Reg = MO.getReg();
521  O << '$' << MipsInstPrinter::getRegisterName(Reg);
522  return false;
523  }
524  }
525  case 'w':
526  // Print MSA registers for the 'f' constraint
527  // In LLVM, the 'w' modifier doesn't need to do anything.
528  // We can just call printOperand as normal.
529  break;
530  }
531  }
532 
533  printOperand(MI, OpNum, O);
534  return false;
535 }
536 
538  unsigned OpNum, unsigned AsmVariant,
539  const char *ExtraCode,
540  raw_ostream &O) {
541  assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
542  const MachineOperand &BaseMO = MI->getOperand(OpNum);
543  const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
544  assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
545  assert(OffsetMO.isImm() && "Unexpected offset for inline asm memory operand.");
546  int Offset = OffsetMO.getImm();
547 
548  // Currently we are expecting either no ExtraCode or 'D'
549  if (ExtraCode) {
550  if (ExtraCode[0] == 'D')
551  Offset += 4;
552  else
553  return true; // Unknown modifier.
554  // FIXME: M = high order bits
555  // FIXME: L = low order bits
556  }
557 
558  O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg()) << ")";
559 
560  return false;
561 }
562 
563 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
564  raw_ostream &O) {
565  const MachineOperand &MO = MI->getOperand(opNum);
566  bool closeP = false;
567 
568  if (MO.getTargetFlags())
569  closeP = true;
570 
571  switch(MO.getTargetFlags()) {
572  case MipsII::MO_GPREL: O << "%gp_rel("; break;
573  case MipsII::MO_GOT_CALL: O << "%call16("; break;
574  case MipsII::MO_GOT: O << "%got("; break;
575  case MipsII::MO_ABS_HI: O << "%hi("; break;
576  case MipsII::MO_ABS_LO: O << "%lo("; break;
577  case MipsII::MO_TLSGD: O << "%tlsgd("; break;
578  case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
579  case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
580  case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
581  case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
582  case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
583  case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
584  case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
585  case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
586  }
587 
588  switch (MO.getType()) {
590  O << '$'
592  break;
593 
595  O << MO.getImm();
596  break;
597 
599  MO.getMBB()->getSymbol()->print(O, MAI);
600  return;
601 
603  getSymbol(MO.getGlobal())->print(O, MAI);
604  break;
605 
608  O << BA->getName();
609  break;
610  }
611 
613  O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
614  << getFunctionNumber() << "_" << MO.getIndex();
615  if (MO.getOffset())
616  O << "+" << MO.getOffset();
617  break;
618 
619  default:
620  llvm_unreachable("<unknown operand type>");
621  }
622 
623  if (closeP) O << ")";
624 }
625 
626 void MipsAsmPrinter::
627 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
628  // Load/Store memory operands -- imm($reg)
629  // If PIC target the target is loaded as the
630  // pattern lw $25,%call16($28)
631 
632  // opNum can be invalid if instruction has reglist as operand.
633  // MemOperand is always last operand of instruction (base + offset).
634  switch (MI->getOpcode()) {
635  default:
636  break;
637  case Mips::SWM32_MM:
638  case Mips::LWM32_MM:
639  opNum = MI->getNumOperands() - 2;
640  break;
641  }
642 
643  printOperand(MI, opNum+1, O);
644  O << "(";
645  printOperand(MI, opNum, O);
646  O << ")";
647 }
648 
649 void MipsAsmPrinter::
650 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
651  // when using stack locations for not load/store instructions
652  // print the same way as all normal 3 operand instructions.
653  printOperand(MI, opNum, O);
654  O << ", ";
655  printOperand(MI, opNum+1, O);
656  return;
657 }
658 
659 void MipsAsmPrinter::
660 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
661  const char *Modifier) {
662  const MachineOperand &MO = MI->getOperand(opNum);
664 }
665 
666 void MipsAsmPrinter::
667 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
668  for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
669  if (i != opNum) O << ", ";
670  printOperand(MI, i, O);
671  }
672 }
673 
675  MipsTargetStreamer &TS = getTargetStreamer();
676 
677  // MipsTargetStreamer has an initialization order problem when emitting an
678  // object file directly (see MipsTargetELFStreamer for full details). Work
679  // around it by re-initializing the PIC state here.
681 
682  // Compute MIPS architecture attributes based on the default subtarget
683  // that we'd have constructed. Module level directives aren't LTO
684  // clean anyhow.
685  // FIXME: For ifunc related functions we could iterate over and look
686  // for a feature string that doesn't match the default one.
687  const Triple &TT = TM.getTargetTriple();
690  const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
691  const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
692 
693  bool IsABICalls = STI.isABICalls();
694  const MipsABIInfo &ABI = MTM.getABI();
695  if (IsABICalls) {
697  // FIXME: This condition should be a lot more complicated that it is here.
698  // Ideally it should test for properties of the ABI and not the ABI
699  // itself.
700  // For the moment, I'm only correcting enough to make MIPS-IV work.
701  if (!isPositionIndependent() && !ABI.IsN64())
703  }
704 
705  // Tell the assembler which ABI we are using
706  std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
707  OutStreamer->SwitchSection(
708  OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
709 
710  // NaN: At the moment we only support:
711  // 1. .nan legacy (default)
712  // 2. .nan 2008
713  STI.isNaN2008() ? TS.emitDirectiveNaN2008()
714  : TS.emitDirectiveNaNLegacy();
715 
716  // TODO: handle O64 ABI
717 
718  TS.updateABIInfo(STI);
719 
720  // We should always emit a '.module fp=...' but binutils 2.24 does not accept
721  // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
722  // -mfp64) and omit it otherwise.
723  if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
725 
726  // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
727  // accept it. We therefore emit it when it contradicts the default or an
728  // option has changed the default (i.e. FPXX) and omit it otherwise.
729  if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
731 }
732 
733 void MipsAsmPrinter::emitInlineAsmStart() const {
734  MipsTargetStreamer &TS = getTargetStreamer();
735 
736  // GCC's choice of assembler options for inline assembly code ('at', 'macro'
737  // and 'reorder') is different from LLVM's choice for generated code ('noat',
738  // 'nomacro' and 'noreorder').
739  // In order to maintain compatibility with inline assembly code which depends
740  // on GCC's assembler options being used, we have to switch to those options
741  // for the duration of the inline assembly block and then switch back.
743  TS.emitDirectiveSetAt();
746  OutStreamer->AddBlankLine();
747 }
748 
749 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
750  const MCSubtargetInfo *EndInfo) const {
751  OutStreamer->AddBlankLine();
752  getTargetStreamer().emitDirectiveSetPop();
753 }
754 
755 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
756  MCInst I;
757  I.setOpcode(Mips::JAL);
758  I.addOperand(
760  OutStreamer->EmitInstruction(I, STI);
761 }
762 
763 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
764  unsigned Reg) {
765  MCInst I;
766  I.setOpcode(Opcode);
768  OutStreamer->EmitInstruction(I, STI);
769 }
770 
771 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
772  unsigned Opcode, unsigned Reg1,
773  unsigned Reg2) {
774  MCInst I;
775  //
776  // Because of the current td files for Mips32, the operands for MTC1
777  // appear backwards from their normal assembly order. It's not a trivial
778  // change to fix this in the td file so we adjust for it here.
779  //
780  if (Opcode == Mips::MTC1) {
781  unsigned Temp = Reg1;
782  Reg1 = Reg2;
783  Reg2 = Temp;
784  }
785  I.setOpcode(Opcode);
788  OutStreamer->EmitInstruction(I, STI);
789 }
790 
791 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
792  unsigned Opcode, unsigned Reg1,
793  unsigned Reg2, unsigned Reg3) {
794  MCInst I;
795  I.setOpcode(Opcode);
799  OutStreamer->EmitInstruction(I, STI);
800 }
801 
802 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
803  unsigned MovOpc, unsigned Reg1,
804  unsigned Reg2, unsigned FPReg1,
805  unsigned FPReg2, bool LE) {
806  if (!LE) {
807  unsigned temp = Reg1;
808  Reg1 = Reg2;
809  Reg2 = temp;
810  }
811  EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
812  EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
813 }
814 
815 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
817  bool LE, bool ToFP) {
818  using namespace Mips16HardFloatInfo;
819  unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
820  switch (PV) {
821  case FSig:
822  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
823  break;
824  case FFSig:
825  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
826  break;
827  case FDSig:
828  EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
829  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
830  break;
831  case DSig:
832  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
833  break;
834  case DDSig:
835  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
836  EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
837  break;
838  case DFSig:
839  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
840  EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
841  break;
842  case NoSig:
843  return;
844  }
845 }
846 
847 void MipsAsmPrinter::EmitSwapFPIntRetval(
849  bool LE) {
850  using namespace Mips16HardFloatInfo;
851  unsigned MovOpc = Mips::MFC1;
852  switch (RV) {
853  case FRet:
854  EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
855  break;
856  case DRet:
857  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
858  break;
859  case CFRet:
860  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
861  break;
862  case CDRet:
863  EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
864  EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
865  break;
866  case NoFPRet:
867  break;
868  }
869 }
870 
871 void MipsAsmPrinter::EmitFPCallStub(
872  const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
873  MCSymbol *MSymbol = OutContext.getOrCreateSymbol(StringRef(Symbol));
874  using namespace Mips16HardFloatInfo;
875  bool LE = getDataLayout().isLittleEndian();
876  // Construct a local MCSubtargetInfo here.
877  // This is because the MachineFunction won't exist (but have not yet been
878  // freed) and since we're at the global level we can use the default
879  // constructed subtarget.
880  std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
883 
884  //
885  // .global xxxx
886  //
887  OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global);
888  const char *RetType;
889  //
890  // make the comment field identifying the return and parameter
891  // types of the floating point stub
892  // # Stub function to call rettype xxxx (params)
893  //
894  switch (Signature->RetSig) {
895  case FRet:
896  RetType = "float";
897  break;
898  case DRet:
899  RetType = "double";
900  break;
901  case CFRet:
902  RetType = "complex";
903  break;
904  case CDRet:
905  RetType = "double complex";
906  break;
907  case NoFPRet:
908  RetType = "";
909  break;
910  }
911  const char *Parms;
912  switch (Signature->ParamSig) {
913  case FSig:
914  Parms = "float";
915  break;
916  case FFSig:
917  Parms = "float, float";
918  break;
919  case FDSig:
920  Parms = "float, double";
921  break;
922  case DSig:
923  Parms = "double";
924  break;
925  case DDSig:
926  Parms = "double, double";
927  break;
928  case DFSig:
929  Parms = "double, float";
930  break;
931  case NoSig:
932  Parms = "";
933  break;
934  }
935  OutStreamer->AddComment("\t# Stub function to call " + Twine(RetType) + " " +
936  Twine(Symbol) + " (" + Twine(Parms) + ")");
937  //
938  // probably not necessary but we save and restore the current section state
939  //
940  OutStreamer->PushSection();
941  //
942  // .section mips16.call.fpxxxx,"ax",@progbits
943  //
945  ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
947  OutStreamer->SwitchSection(M, nullptr);
948  //
949  // .align 2
950  //
951  OutStreamer->EmitValueToAlignment(4);
952  MipsTargetStreamer &TS = getTargetStreamer();
953  //
954  // .set nomips16
955  // .set nomicromips
956  //
959  //
960  // .ent __call_stub_fp_xxxx
961  // .type __call_stub_fp_xxxx,@function
962  // __call_stub_fp_xxxx:
963  //
964  std::string x = "__call_stub_fp_" + std::string(Symbol);
965  MCSymbolELF *Stub =
966  cast<MCSymbolELF>(OutContext.getOrCreateSymbol(StringRef(x)));
967  TS.emitDirectiveEnt(*Stub);
968  MCSymbol *MType =
969  OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
970  OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
971  OutStreamer->EmitLabel(Stub);
972 
973  // Only handle non-pic for now.
975  "should not be here if we are compiling pic");
977  //
978  // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
979  // stubs without raw text but this current patch is for compiler generated
980  // functions and they all return some value.
981  // The calling sequence for non pic is different in that case and we need
982  // to implement %lo and %hi in order to handle the case of no return value
983  // See the corresponding method in Mips16HardFloat for details.
984  //
985  // mov the return address to S2.
986  // we have no stack space to store it and we are about to make another call.
987  // We need to make sure that the enclosing function knows to save S2
988  // This should have already been handled.
989  //
990  // Mov $18, $31
991 
992  EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
993 
994  EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
995 
996  // Jal xxxx
997  //
998  EmitJal(*STI, MSymbol);
999 
1000  // fix return values
1001  EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1002  //
1003  // do the return
1004  // if (Signature->RetSig == NoFPRet)
1005  // llvm_unreachable("should not be any stubs here with no return value");
1006  // else
1007  EmitInstrReg(*STI, Mips::JR, Mips::S2);
1008 
1010  OutStreamer->EmitLabel(Tmp);
1013  const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext);
1014  OutStreamer->emitELFSize(Stub, T_min_E);
1015  TS.emitDirectiveEnd(x);
1016  OutStreamer->PopSection();
1017 }
1018 
1020  // Emit needed stubs
1021  //
1022  for (std::map<
1023  const char *,
1024  const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1025  it = StubsNeeded.begin();
1026  it != StubsNeeded.end(); ++it) {
1027  const char *Symbol = it->first;
1028  const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1029  EmitFPCallStub(Symbol, Signature);
1030  }
1031  // return to the text section
1033 }
1034 
1036  raw_ostream &OS) {
1037  // TODO: implement
1038 }
1039 
1040 // Emit .dtprelword or .dtpreldword directive
1041 // and value for debug thread local expression.
1043  unsigned Size) const {
1044  switch (Size) {
1045  case 4:
1046  OutStreamer->EmitDTPRel32Value(Value);
1047  break;
1048  case 8:
1049  OutStreamer->EmitDTPRel64Value(Value);
1050  break;
1051  default:
1052  llvm_unreachable("Unexpected size of expression value.");
1053  }
1054 }
1055 
1056 // Align all targets of indirect branches on bundle size. Used only if target
1057 // is NaCl.
1058 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1059  // Align all blocks that are jumped to through jump table.
1060  if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1061  const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1062  for (unsigned I = 0; I < JT.size(); ++I) {
1063  const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1064 
1065  for (unsigned J = 0; J < MBBs.size(); ++J)
1066  MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1067  }
1068  }
1069 
1070  // If basic block address is taken, block can be target of indirect branch.
1071  for (auto &MBB : MF) {
1072  if (MBB.hasAddressTaken())
1074  }
1075 }
1076 
1077 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1078  return (Opcode == Mips::LONG_BRANCH_LUi
1079  || Opcode == Mips::LONG_BRANCH_ADDiu
1080  || Opcode == Mips::LONG_BRANCH_DADDiu);
1081 }
1082 
1083 // Force static initialization.
1084 extern "C" void LLVMInitializeMipsAsmPrinter() {
1089 }
MachineConstantPoolValue * MachineCPVal
virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff)
bool isEHPad() const
Returns true if the block is a landing pad.
unsigned getAlignment() const
getAlignment - Return the alignment (log2, not bytes) of the function.
StringRef getPrivateGlobalPrefix() const
Definition: DataLayout.h:284
StringRef getTargetCPU() const
const GlobalValue * getGlobal() const
bool isValid() const
Definition: MCInst.h:55
instr_iterator instr_end()
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:84
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:298
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:371
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:53
size_t i
MachineBasicBlock * getMBB() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:39
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:52
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:148
virtual void AddBlankLine()
AddBlankLine - Emit a blank line to a .s file to pretty it up.
Definition: MCStreamer.h:289
void Lower(const MachineInstr *MI, MCInst &OutMI) const
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:79
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:129
void EmitFunctionBodyEnd() override
EmitFunctionBodyEnd - Targets can override this to emit stuff after the last basic block in the funct...
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
void EmitDebugValue(const MCExpr *Value, unsigned Size) const override
Emit the directive and value for debug thread local expression.
const MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:87
Target & getTheMipselTarget()
virtual void EmitDTPRel64Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (64-bit DTP relative) value.
Definition: MCStreamer.cpp:131
virtual void emitDirectiveSetNoReorder()
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:490
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
isBlockOnlyReachableByFallthough - Return true if the basic block has exactly one predecessor and the...
void PushSection()
Save the current and previous section on the section stack.
Definition: MCStreamer.h:324
MachineBasicBlock reference.
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:140
const std::string & str() const
Definition: Triple.h:339
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
void Initialize(MCContext *C)
void EmitFunctionBodyStart() override
EmitFunctionBodyStart - Targets can override this to emit stuff before the first basic block in the f...
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:765
void setAlignment(unsigned Align)
Set alignment of the basic block.
void EmitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
return AArch64::GPR64RegClass contains(Reg)
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
const Triple & getTargetTriple() const
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects...
MCSubtargetInfo * createMCSubtargetInfo(StringRef TheTriple, StringRef CPU, StringRef Features) const
createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
virtual void emitDirectiveSetMicroMips()
const MipsABIInfo & getABI() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:111
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
struct fuzzer::@269 Flags
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
virtual void emitFrame(unsigned StackReg, unsigned StackSize, unsigned ReturnReg)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void LLVMInitializeMipsAsmPrinter()
bool isReg() const
isReg - Tests if this is a MO_Register operand.
virtual void emitDirectiveSetNoMacro()
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:34
virtual void emitDirectiveEnd(StringRef Name)
Reg
All possible values of the reg field in the ModR/M byte.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:161
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual unsigned getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol address.
Definition: MipsBaseInfo.h:52
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:277
virtual void emitDirectiveModuleOddSPReg()
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:269
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
Definition: AsmPrinter.h:244
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:497
MachineBasicBlock * MBB
Target & getTheMips64Target()
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O)
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:220
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
This class is a data container for one entry in a MachineConstantPool.
int64_t getImm() const
MCContext & getContext() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS)
void EmitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:150
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:273
MO_GPREL - Represents the offset from the current gp value to be used for the relocatable object file...
Definition: MipsBaseInfo.h:48
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:131
bool isDebugValue() const
Definition: MachineInstr.h:777
Address of a global value.
unsigned getTargetFlags() const
Streaming machine code generation interface.
Definition: MCStreamer.h:161
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
MCSymbol * createTempSymbol(bool CanBeUnnamed=true)
Create and return a new assembler temporary symbol with a unique but unspecified name.
Definition: MCContext.cpp:218
Target & getTheMips64elTarget()
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:95
LLVM Basic Block Representation.
Definition: BasicBlock.h:51
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:75
virtual void emitDirectiveSetNoMicroMips()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
virtual void emitDirectiveSetMips16()
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Definition: MCStreamer.cpp:829
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:279
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant...
void EmitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
static ManagedStatic< OptionRegistry > OR
Definition: Options.cpp:31
virtual void emitDirectiveSetMacro()
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:71
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag...
Definition: InlineAsm.h:335
virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:817
virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
Address of a basic block.
uint32_t Offset
bool IsN64() const
Definition: MipsABIInfo.h:44
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang","erlang-compatible garbage collector")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int64_t getOffset() const
Return the offset from the symbol in this operand.
StringRef selectMipsCPU(const Triple &TT, StringRef CPU)
Select the Mips CPU for the given triple and cpu name.
self_iterator getIterator()
Definition: ilist_node.h:81
virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff)
MCSection * getTextSection() const
bool inMicroMipsMode() const
const char * getCurrentABIString() const
Emit Set directives.
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
bool inMips16Mode() const
MipsMCInstLower MCInstLowering
bool hasMips32r6() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
virtual void EmitDataRegion(MCDataRegionType Kind)
Note in the output the specified region Kind.
Definition: MCStreamer.h:408
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
void EmitAlignment(unsigned NumBits, const GlobalObject *GO=nullptr) const
Emit an alignment directive to the specified power of two boundary.
std::vector< MachineBasicBlock * >::const_iterator const_pred_iterator
size_t size() const
Definition: MCInst.h:174
virtual void emitDirectiveAbiCalls()
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
Definition: MipsBaseInfo.h:38
Iterator for intrusive lists based on ilist_node.
void setOpcode(unsigned Op)
Definition: MCInst.h:158
bool isTargetNaCl() const
bool isABICalls() const
StringRef getTargetFeatureString() const
virtual void EmitLabel(MCSymbol *Symbol)
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:293
bool IsO32() const
Definition: MipsABIInfo.h:42
virtual void emitDirectiveOptionPic0()
MachineOperand class - Representation of each machine instruction operand.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:161
bool isLittle() const
static Twine utohexstr(const uint64_t &Val)
Definition: Twine.h:395
bool isPositionIndependent() const
virtual void emitDirectiveSetNoMips16()
bool hasMips64r6() const
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:134
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier=nullptr)
void EmitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
const char * MipsFCCToString(Mips::CondCode CC)
bool isGP64bit() const
Target & getTheMipsTarget()
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
static const unsigned MIPS_NACL_BUNDLE_ALIGN
Definition: MipsMCNaCl.h:18
virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV)
virtual void setPic(bool Value)
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
Representation of each machine instruction.
Definition: MachineInstr.h:52
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
void updateABIInfo(const PredicateLibrary &P)
virtual void emitDirectiveEnt(const MCSymbol &Symbol)
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:199
const MipsSubtarget * Subtarget
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:226
.type _foo,
Definition: MCDirectives.h:30
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:114
.type _foo, STT_FUNC # aka
Definition: MCDirectives.h:23
#define I(x, y, z)
Definition: MD5.cpp:54
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
virtual void EmitDTPRel32Value(const MCExpr *Value)
Emit the expression Value into the output as a dtprel (32-bit DTP relative) value.
Definition: MCStreamer.cpp:135
MCSubtargetInfo - Generic base class for all target subtargets.
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O)
virtual void emitELFSize(MCSymbol *Symbol, const MCExpr *Value)
Emit an ELF .size directive.
Definition: MCStreamer.cpp:800
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:30
const char SectionName[]
Definition: AMDGPUPTNote.h:24
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O)
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool PopSection()
Restore the current and previous section from the section stack.
Definition: MCStreamer.h:333
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:341
virtual void emitDirectiveSetReorder()
static const char * getRegisterName(unsigned RegNo)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void EmitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
LLVM Value Representation.
Definition: Value.h:71
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:247
RegisterAsmPrinter - Helper template for registering a target specific assembly printer, for use in the target machine initialization function.
virtual void emitDirectiveNaNLegacy()
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
MCOperand LowerOperand(const MachineOperand &MO, unsigned offset=0) const
static TraceState * TS
const Target & getTarget() const
const MipsFunctionInfo * MipsFI
const std::vector< MachineConstantPoolEntry > & getConstants() const
IRTranslator LLVM IR MI
void emitFrameDirective()
Frame Directive.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void addOperand(const MCOperand &Op)
Definition: MCInst.h:168
virtual void print(raw_ostream &O, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:117
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:47
const BlockAddress * getBlockAddress() const
Address of indexed Constant in Constant Pool.
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
union llvm::MachineConstantPoolEntry::@35 Val
The constant itself.
void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override
Targets can override this to emit stuff at the end of a basic block.
unsigned getRARegister() const
This method should return the register where the return address can be found.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:33
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:122
.end_data_region
Definition: MCDirectives.h:61