LLVM  4.0.0
BitTracker.h
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1 //===--- BitTracker.h -------------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
11 #define LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
12 
13 #include "llvm/ADT/SetVector.h"
14 #include "llvm/ADT/SmallVector.h"
17 #include <cassert>
18 #include <cstdint>
19 #include <map>
20 #include <queue>
21 #include <set>
22 #include <utility>
23 
24 namespace llvm {
25 
26 class ConstantInt;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineInstr;
30 class raw_ostream;
31 
32 struct BitTracker {
33  struct BitRef;
34  struct RegisterRef;
35  struct BitValue;
36  struct BitMask;
37  struct RegisterCell;
39 
41 
42  typedef std::map<unsigned, RegisterCell> CellMapType;
43 
45  ~BitTracker();
46 
47  void run();
48  void trace(bool On = false) { Trace = On; }
49  bool has(unsigned Reg) const;
50  const RegisterCell &lookup(unsigned Reg) const;
51  RegisterCell get(RegisterRef RR) const;
52  void put(RegisterRef RR, const RegisterCell &RC);
53  void subst(RegisterRef OldRR, RegisterRef NewRR);
54  bool reached(const MachineBasicBlock *B) const;
55  void visit(const MachineInstr &MI);
56 
57  void print_cells(raw_ostream &OS) const;
58 
59 private:
60  void visitPHI(const MachineInstr &PI);
61  void visitNonBranch(const MachineInstr &MI);
62  void visitBranchesFrom(const MachineInstr &BI);
63  void visitUsesOf(unsigned Reg);
64  void reset();
65 
66  typedef std::pair<int,int> CFGEdge;
67  typedef std::set<CFGEdge> EdgeSetType;
68  typedef std::set<const MachineInstr *> InstrSetType;
69  typedef std::queue<CFGEdge> EdgeQueueType;
70 
71  EdgeSetType EdgeExec; // Executable flow graph edges.
72  InstrSetType InstrExec; // Executable instructions.
73  EdgeQueueType FlowQ; // Work queue of CFG edges.
74  bool Trace; // Enable tracing for debugging.
75 
76  const MachineEvaluator &ME;
77  MachineFunction &MF;
79  CellMapType &Map;
80 };
81 
82 // Abstraction of a reference to bit at position Pos from a register Reg.
84  BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {}
85 
86  bool operator== (const BitRef &BR) const {
87  // If Reg is 0, disregard Pos.
88  return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
89  }
90 
91  unsigned Reg;
92  uint16_t Pos;
93 };
94 
95 // Abstraction of a register reference in MachineOperand. It contains the
96 // register number and the subregister index.
98  RegisterRef(unsigned R = 0, unsigned S = 0)
99  : Reg(R), Sub(S) {}
101  : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
102 
103  unsigned Reg, Sub;
104 };
105 
106 // Value that a single bit can take. This is outside of the context of
107 // any register, it is more of an abstraction of the two-element set of
108 // possible bit values. One extension here is the "Ref" type, which
109 // indicates that this bit takes the same value as the bit described by
110 // RefInfo.
112  enum ValueType {
113  Top, // Bit not yet defined.
114  Zero, // Bit = 0.
115  One, // Bit = 1.
116  Ref // Bit value same as the one described in RefI.
117  // Conceptually, there is no explicit "bottom" value: the lattice's
118  // bottom will be expressed as a "ref to itself", which, in the context
119  // of registers, could be read as "this value of this bit is defined by
120  // this bit".
121  // The ordering is:
122  // x <= Top,
123  // Self <= x, where "Self" is "ref to itself".
124  // This makes the value lattice different for each virtual register
125  // (even for each bit in the same virtual register), since the "bottom"
126  // for one register will be a simple "ref" for another register.
127  // Since we do not store the "Self" bit and register number, the meet
128  // operation will need to take it as a parameter.
129  //
130  // In practice there is a special case for values that are not associa-
131  // ted with any specific virtual register. An example would be a value
132  // corresponding to a bit of a physical register, or an intermediate
133  // value obtained in some computation (such as instruction evaluation).
134  // Such cases are identical to the usual Ref type, but the register
135  // number is 0. In such case the Pos field of the reference is ignored.
136  //
137  // What is worthy of notice is that in value V (that is a "ref"), as long
138  // as the RefI.Reg is not 0, it may actually be the same register as the
139  // one in which V will be contained. If the RefI.Pos refers to the posi-
140  // tion of V, then V is assumed to be "bottom" (as a "ref to itself"),
141  // otherwise V is taken to be identical to the referenced bit of the
142  // same register.
143  // If RefI.Reg is 0, however, such a reference to the same register is
144  // not possible. Any value V that is a "ref", and whose RefI.Reg is 0
145  // is treated as "bottom".
146  };
149 
151  BitValue(bool B) : Type(B ? One : Zero) {}
152  BitValue(unsigned Reg, uint16_t Pos) : Type(Ref), RefI(Reg, Pos) {}
153 
154  bool operator== (const BitValue &V) const {
155  if (Type != V.Type)
156  return false;
157  if (Type == Ref && !(RefI == V.RefI))
158  return false;
159  return true;
160  }
161  bool operator!= (const BitValue &V) const {
162  return !operator==(V);
163  }
164 
165  bool is(unsigned T) const {
166  assert(T == 0 || T == 1);
167  return T == 0 ? Type == Zero
168  : (T == 1 ? Type == One : false);
169  }
170 
171  // The "meet" operation is the "." operation in a semilattice (L, ., T, B):
172  // (1) x.x = x
173  // (2) x.y = y.x
174  // (3) x.(y.z) = (x.y).z
175  // (4) x.T = x (i.e. T = "top")
176  // (5) x.B = B (i.e. B = "bottom")
177  //
178  // This "meet" function will update the value of the "*this" object with
179  // the newly calculated one, and return "true" if the value of *this has
180  // changed, and "false" otherwise.
181  // To prove that it satisfies the conditions (1)-(5), it is sufficient
182  // to show that a relation
183  // x <= y <=> x.y = x
184  // defines a partial order (i.e. that "meet" is same as "infimum").
185  bool meet(const BitValue &V, const BitRef &Self) {
186  // First, check the cases where there is nothing to be done.
187  if (Type == Ref && RefI == Self) // Bottom.meet(V) = Bottom (i.e. This)
188  return false;
189  if (V.Type == Top) // This.meet(Top) = This
190  return false;
191  if (*this == V) // This.meet(This) = This
192  return false;
193 
194  // At this point, we know that the value of "this" will change.
195  // If it is Top, it will become the same as V, otherwise it will
196  // become "bottom" (i.e. Self).
197  if (Type == Top) {
198  Type = V.Type;
199  RefI = V.RefI; // This may be irrelevant, but copy anyway.
200  return true;
201  }
202  // Become "bottom".
203  Type = Ref;
204  RefI = Self;
205  return true;
206  }
207 
208  // Create a reference to the bit value V.
209  static BitValue ref(const BitValue &V);
210  // Create a "self".
211  static BitValue self(const BitRef &Self = BitRef());
212 
213  bool num() const {
214  return Type == Zero || Type == One;
215  }
216 
217  operator bool() const {
218  assert(Type == Zero || Type == One);
219  return Type == One;
220  }
221 
222  friend raw_ostream &operator<<(raw_ostream &OS, const BitValue &BV);
223 };
224 
225 // This operation must be idempotent, i.e. ref(ref(V)) == ref(V).
228  if (V.Type != Ref)
229  return BitValue(V.Type);
230  if (V.RefI.Reg != 0)
231  return BitValue(V.RefI.Reg, V.RefI.Pos);
232  return self();
233 }
234 
237  return BitValue(Self.Reg, Self.Pos);
238 }
239 
240 // A sequence of bits starting from index B up to and including index E.
241 // If E < B, the mask represents two sections: [0..E] and [B..W) where
242 // W is the width of the register.
244  BitMask() = default;
245  BitMask(uint16_t b, uint16_t e) : B(b), E(e) {}
246 
247  uint16_t first() const { return B; }
248  uint16_t last() const { return E; }
249 
250 private:
251  uint16_t B = 0;
252  uint16_t E = 0;
253 };
254 
255 // Representation of a register: a list of BitValues.
257  RegisterCell(uint16_t Width = DefaultBitN) : Bits(Width) {}
258 
259  uint16_t width() const {
260  return Bits.size();
261  }
262 
263  const BitValue &operator[](uint16_t BitN) const {
264  assert(BitN < Bits.size());
265  return Bits[BitN];
266  }
267  BitValue &operator[](uint16_t BitN) {
268  assert(BitN < Bits.size());
269  return Bits[BitN];
270  }
271 
272  bool meet(const RegisterCell &RC, unsigned SelfR);
273  RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
274  RegisterCell extract(const BitMask &M) const; // Returns a new cell.
275  RegisterCell &rol(uint16_t Sh); // Rotate left.
276  RegisterCell &fill(uint16_t B, uint16_t E, const BitValue &V);
277  RegisterCell &cat(const RegisterCell &RC); // Concatenate.
278  uint16_t cl(bool B) const;
279  uint16_t ct(bool B) const;
280 
281  bool operator== (const RegisterCell &RC) const;
282  bool operator!= (const RegisterCell &RC) const {
283  return !operator==(RC);
284  }
285 
286  // Generate a "ref" cell for the corresponding register. In the resulting
287  // cell each bit will be described as being the same as the corresponding
288  // bit in register Reg (i.e. the cell is "defined" by register Reg).
289  static RegisterCell self(unsigned Reg, uint16_t Width);
290  // Generate a "top" cell of given size.
291  static RegisterCell top(uint16_t Width);
292  // Generate a cell that is a "ref" to another cell.
293  static RegisterCell ref(const RegisterCell &C);
294 
295 private:
296  // The DefaultBitN is here only to avoid frequent reallocation of the
297  // memory in the vector.
298  static const unsigned DefaultBitN = 32;
299  typedef SmallVector<BitValue, DefaultBitN> BitValueList;
300  BitValueList Bits;
301 
302  friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
303 };
304 
305 inline bool BitTracker::has(unsigned Reg) const {
306  return Map.find(Reg) != Map.end();
307 }
308 
309 inline const BitTracker::RegisterCell&
310 BitTracker::lookup(unsigned Reg) const {
311  CellMapType::const_iterator F = Map.find(Reg);
312  assert(F != Map.end());
313  return F->second;
314 }
315 
317 BitTracker::RegisterCell::self(unsigned Reg, uint16_t Width) {
318  RegisterCell RC(Width);
319  for (uint16_t i = 0; i < Width; ++i)
320  RC.Bits[i] = BitValue::self(BitRef(Reg, i));
321  return RC;
322 }
323 
326  RegisterCell RC(Width);
327  for (uint16_t i = 0; i < Width; ++i)
328  RC.Bits[i] = BitValue(BitValue::Top);
329  return RC;
330 }
331 
334  uint16_t W = C.width();
335  RegisterCell RC(W);
336  for (unsigned i = 0; i < W; ++i)
337  RC[i] = BitValue::ref(C[i]);
338  return RC;
339 }
340 
341 // A class to evaluate target's instructions and update the cell maps.
342 // This is used internally by the bit tracker. A target that wants to
343 // utilize this should implement the evaluation functions (noted below)
344 // in a subclass of this class.
347  : TRI(T), MRI(M) {}
348  virtual ~MachineEvaluator() = default;
349 
350  uint16_t getRegBitWidth(const RegisterRef &RR) const;
351 
352  RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
353  void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
354 
355  // A result of any operation should use refs to the source cells, not
356  // the cells directly. This function is a convenience wrapper to quickly
357  // generate a ref for a cell corresponding to a register reference.
358  RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const {
359  RegisterCell RC = getCell(RR, M);
360  return RegisterCell::ref(RC);
361  }
362 
363  // Helper functions.
364  // Check if a cell is an immediate value (i.e. all bits are either 0 or 1).
365  bool isInt(const RegisterCell &A) const;
366  // Convert cell to an immediate value.
367  uint64_t toInt(const RegisterCell &A) const;
368 
369  // Generate cell from an immediate value.
370  RegisterCell eIMM(int64_t V, uint16_t W) const;
371  RegisterCell eIMM(const ConstantInt *CI) const;
372 
373  // Arithmetic.
374  RegisterCell eADD(const RegisterCell &A1, const RegisterCell &A2) const;
375  RegisterCell eSUB(const RegisterCell &A1, const RegisterCell &A2) const;
376  RegisterCell eMLS(const RegisterCell &A1, const RegisterCell &A2) const;
377  RegisterCell eMLU(const RegisterCell &A1, const RegisterCell &A2) const;
378 
379  // Shifts.
380  RegisterCell eASL(const RegisterCell &A1, uint16_t Sh) const;
381  RegisterCell eLSR(const RegisterCell &A1, uint16_t Sh) const;
382  RegisterCell eASR(const RegisterCell &A1, uint16_t Sh) const;
383 
384  // Logical.
385  RegisterCell eAND(const RegisterCell &A1, const RegisterCell &A2) const;
386  RegisterCell eORL(const RegisterCell &A1, const RegisterCell &A2) const;
387  RegisterCell eXOR(const RegisterCell &A1, const RegisterCell &A2) const;
388  RegisterCell eNOT(const RegisterCell &A1) const;
389 
390  // Set bit, clear bit.
391  RegisterCell eSET(const RegisterCell &A1, uint16_t BitN) const;
392  RegisterCell eCLR(const RegisterCell &A1, uint16_t BitN) const;
393 
394  // Count leading/trailing bits (zeros/ones).
395  RegisterCell eCLB(const RegisterCell &A1, bool B, uint16_t W) const;
396  RegisterCell eCTB(const RegisterCell &A1, bool B, uint16_t W) const;
397 
398  // Sign/zero extension.
399  RegisterCell eSXT(const RegisterCell &A1, uint16_t FromN) const;
400  RegisterCell eZXT(const RegisterCell &A1, uint16_t FromN) const;
401 
402  // Extract/insert
403  // XTR R,b,e: extract bits from A1 starting at bit b, ending at e-1.
404  // INS R,S,b: take R and replace bits starting from b with S.
405  RegisterCell eXTR(const RegisterCell &A1, uint16_t B, uint16_t E) const;
406  RegisterCell eINS(const RegisterCell &A1, const RegisterCell &A2,
407  uint16_t AtN) const;
408 
409  // User-provided functions for individual targets:
410 
411  // Return a sub-register mask that indicates which bits in Reg belong
412  // to the subregister Sub. These bits are assumed to be contiguous in
413  // the super-register, and have the same ordering in the sub-register
414  // as in the super-register. It is valid to call this function with
415  // Sub == 0, in this case, the function should return a mask that spans
416  // the entire register Reg (which is what the default implementation
417  // does).
418  virtual BitMask mask(unsigned Reg, unsigned Sub) const;
419  // Indicate whether a given register class should be tracked.
420  virtual bool track(const TargetRegisterClass *RC) const { return true; }
421  // Evaluate a non-branching machine instruction, given the cell map with
422  // the input values. Place the results in the Outputs map. Return "true"
423  // if evaluation succeeded, "false" otherwise.
424  virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
425  CellMapType &Outputs) const;
426  // Evaluate a branch, given the cell map with the input values. Fill out
427  // a list of all possible branch targets and indicate (through a flag)
428  // whether the branch could fall-through. Return "true" if this information
429  // has been successfully computed, "false" otherwise.
430  virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
431  BranchTargetList &Targets, bool &FallsThru) const = 0;
432 
435 };
436 
437 } // end namespace llvm
438 
439 #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H
RegisterRef(unsigned R=0, unsigned S=0)
Definition: BitTracker.h:98
RegisterCell getRef(const RegisterRef &RR, const CellMapType &M) const
Definition: BitTracker.h:358
MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
Definition: BitTracker.h:346
const TargetRegisterInfo & TRI
Definition: BitTracker.h:433
BitValue(ValueType T=Top)
Definition: BitTracker.h:150
void trace(bool On=false)
Definition: BitTracker.h:48
size_t i
std::map< unsigned, RegisterCell > CellMapType
Definition: BitTracker.h:42
void print_cells(raw_ostream &OS) const
Definition: BitTracker.cpp:183
BitValue(unsigned Reg, uint16_t Pos)
Definition: BitTracker.h:152
static RegisterCell top(uint16_t Width)
Definition: BitTracker.h:325
void visit(const MachineInstr &MI)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
static RegisterCell self(unsigned Reg, uint16_t Width)
Definition: BitTracker.h:317
const BitValue & operator[](uint16_t BitN) const
Definition: BitTracker.h:263
Reg
All possible values of the reg field in the ModR/M byte.
BitValue & operator[](uint16_t BitN)
Definition: BitTracker.h:267
bool is(unsigned T) const
Definition: BitTracker.h:165
#define F(x, y, z)
Definition: MD5.cpp:51
BitRef(unsigned R=0, uint16_t P=0)
Definition: BitTracker.h:84
BitMask(uint16_t b, uint16_t e)
Definition: BitTracker.h:245
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
#define P(N)
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:551
unsigned const MachineRegisterInfo * MRI
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
constexpr bool isInt(int64_t x)
isInt - Checks if an integer fits into the given bit width.
Definition: MathExtras.h:264
static uint32_t rol(uint32_t Number, int Bits)
Definition: SHA1.cpp:30
uint16_t first() const
Definition: BitTracker.h:247
void subst(RegisterRef OldRR, RegisterRef NewRR)
Definition: BitTracker.cpp:982
bool operator==(const BitRef &BR) const
Definition: BitTracker.h:86
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SetVector< const MachineBasicBlock * > BranchTargetList
Definition: BitTracker.h:38
bool operator!=(const BitValue &V) const
Definition: BitTracker.h:161
const RegisterCell & lookup(unsigned Reg) const
Definition: BitTracker.h:310
This is the shared class of boolean and integer constants.
Definition: Constants.h:88
static BitValue self(const BitRef &Self=BitRef())
Definition: BitTracker.h:236
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo & MRI
Definition: BitTracker.h:434
static GCRegistry::Add< ShadowStackGC > C("shadow-stack","Very portable GC for uncooperative code generators")
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool operator==(const BitValue &V) const
Definition: BitTracker.h:154
loop extract
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool has(unsigned Reg) const
Definition: BitTracker.h:305
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:1724
Representation of each machine instruction.
Definition: MachineInstr.h:52
virtual bool track(const TargetRegisterClass *RC) const
Definition: BitTracker.h:420
BitTracker(const MachineEvaluator &E, MachineFunction &F)
Definition: BitTracker.cpp:188
raw_ostream & operator<<(raw_ostream &OS, const APInt &I)
Definition: APInt.h:1726
bool reached(const MachineBasicBlock *B) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterRef(const MachineOperand &MO)
Definition: BitTracker.h:100
RegisterCell(uint16_t Width=DefaultBitN)
Definition: BitTracker.h:257
friend raw_ostream & operator<<(raw_ostream &OS, const BitValue &BV)
Definition: BitTracker.cpp:98
A vector that has set insertion semantics.
Definition: SetVector.h:41
void put(RegisterRef RR, const RegisterCell &RC)
Definition: BitTracker.cpp:976
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
IRTranslator LLVM IR MI
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1722
static RegisterCell ref(const RegisterCell &C)
Definition: BitTracker.h:333
uint16_t last() const
Definition: BitTracker.h:248
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
bool meet(const BitValue &V, const BitRef &Self)
Definition: BitTracker.h:185
static BitValue ref(const BitValue &V)
Definition: BitTracker.h:227