56 #define DEBUG_TYPE "hexagon-instrinfo"
58 #define GET_INSTRINFO_CTOR_DTOR
59 #define GET_INSTRMAP_INFO
60 #include "HexagonGenInstrInfo.inc"
61 #include "HexagonGenDFAPacketizer.inc"
65 "packetization boundary."));
72 cl::desc(
"Disable schedule adjustment for new value stores."));
76 cl::desc(
"Enable timing class latency"));
80 cl::desc(
"Enable vec alu forwarding"));
84 cl::desc(
"Enable vec acc forwarding"));
91 cl::desc(
"Use the DFA based hazard recognizer."));
124 void HexagonInstrInfo::anchor() {}
131 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
132 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
144 for (; MIB != MIE; ++MIB) {
145 if (!MIB->isDebugValue())
159 if (EndLoopOp == Hexagon::ENDLOOP0) {
160 LOOPi = Hexagon::J2_loop0i;
161 LOOPr = Hexagon::J2_loop0r;
163 LOOPi = Hexagon::J2_loop1i;
164 LOOPr = Hexagon::J2_loop1r;
169 PE = BB->
pred_end(); PB != PE; ++PB) {
171 if (!Visited.
insert(*PB).second)
176 E = (*PB)->instr_rend();
I !=
E; ++
I) {
177 int Opc =
I->getOpcode();
178 if (Opc == LOOPi || Opc == LOOPr)
181 if (Opc == EndLoopOp)
254 case Hexagon::L2_loadri_io:
255 case Hexagon::L2_loadrd_io:
256 case Hexagon::V6_vL32b_ai:
257 case Hexagon::V6_vL32b_ai_128B:
258 case Hexagon::V6_vL32Ub_ai:
259 case Hexagon::V6_vL32Ub_ai_128B:
260 case Hexagon::LDriw_pred:
261 case Hexagon::LDriw_mod:
262 case Hexagon::PS_vloadrq_ai:
263 case Hexagon::PS_vloadrw_ai:
264 case Hexagon::PS_vloadrq_ai_128B:
265 case Hexagon::PS_vloadrw_ai_128B: {
276 case Hexagon::L2_ploadrit_io:
277 case Hexagon::L2_ploadrif_io:
278 case Hexagon::L2_ploadrdt_io:
279 case Hexagon::L2_ploadrdf_io: {
304 case Hexagon::S2_storerb_io:
305 case Hexagon::S2_storerh_io:
306 case Hexagon::S2_storeri_io:
307 case Hexagon::S2_storerd_io:
308 case Hexagon::V6_vS32b_ai:
309 case Hexagon::V6_vS32b_ai_128B:
310 case Hexagon::V6_vS32Ub_ai:
311 case Hexagon::V6_vS32Ub_ai_128B:
312 case Hexagon::STriw_pred:
313 case Hexagon::STriw_mod:
314 case Hexagon::PS_vstorerq_ai:
315 case Hexagon::PS_vstorerw_ai:
316 case Hexagon::PS_vstorerq_ai_128B:
317 case Hexagon::PS_vstorerw_ai_128B: {
328 case Hexagon::S2_pstorerbt_io:
329 case Hexagon::S2_pstorerbf_io:
330 case Hexagon::S2_pstorerht_io:
331 case Hexagon::S2_pstorerhf_io:
332 case Hexagon::S2_pstorerit_io:
333 case Hexagon::S2_pstorerif_io:
334 case Hexagon::S2_pstorerdt_io:
335 case Hexagon::S2_pstorerdf_io: {
370 bool AllowModify)
const {
402 while (I->isDebugValue()) {
408 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
409 I->getOperand(0).isMBB();
411 if (AllowModify && JumpToBlock &&
413 DEBUG(
dbgs() <<
"\nErasing the jump to successor block\n";);
414 I->eraseFromParent();
420 if (!isUnpredicatedTerminator(*I))
428 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
430 SecondLastInst = &*
I;
441 int SecLastOpcode = SecondLastInst ? SecondLastInst->
getOpcode() : 0;
444 if (LastOpcode == Hexagon::J2_jump && !LastInst->
getOperand(0).
isMBB())
446 if (SecLastOpcode == Hexagon::J2_jump &&
457 if (LastInst && !SecondLastInst) {
458 if (LastOpcode == Hexagon::J2_jump) {
468 if (LastOpcodeHasJMP_c) {
483 <<
" with one jump\n";);
490 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
501 if (SecLastOpcodeHasNVJump &&
503 (LastOpcode == Hexagon::J2_jump)) {
514 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
518 I->eraseFromParent();
523 if (
isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
531 <<
" with two jumps";);
537 int *BytesRemoved)
const {
538 assert(!BytesRemoved &&
"code size not handled");
543 while (I != MBB.
begin()) {
545 if (I->isDebugValue())
550 if (Count && (I->getOpcode() == Hexagon::J2_jump))
564 int *BytesAdded)
const {
565 unsigned BOpc = Hexagon::J2_jump;
566 unsigned BccOpc = Hexagon::J2_jumpt;
568 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
569 assert(!BytesAdded &&
"code size not handled");
574 if (!Cond.
empty() && Cond[0].isImm())
575 BccOpc = Cond[0].getImm();
595 int EndLoopOp = Cond[0].getImm();
601 assert(Loop != 0 &&
"Inserting an ENDLOOP without a LOOP");
606 assert((Cond.
size() == 3) &&
"Only supporting rr/ri version of nvjump");
612 if (Cond[2].
isReg()) {
616 }
else if(Cond[2].isImm()) {
618 addImm(Cond[2].getImm()).
addMBB(TBB);
622 assert((Cond.
size() == 2) &&
"Malformed cond vector");
630 "Cond. cannot be empty when multiple branchings are required");
632 "NV-jump cannot be inserted with another branch");
635 int EndLoopOp = Cond[0].getImm();
641 assert(Loop != 0 &&
"Inserting an ENDLOOP without a LOOP");
668 IndVarInst =
nullptr;
682 unsigned Iter,
unsigned MaxIter)
const {
686 &&
"Expecting a hardware loop");
695 if (Loop->
getOpcode() == Hexagon::J2_loop0i ||
696 Loop->
getOpcode() == Hexagon::J2_loop1i) {
706 assert(Loop->
getOpcode() == Hexagon::J2_loop0r &&
"Unexpected instruction");
711 addReg(LoopCount).
addImm(1);
714 addReg(LoopCount).
addImm(-1);
717 E = PrevInsts.
end();
I !=
E; ++
I)
725 BuildMI(&MBB, DL,
get(Hexagon::J2_loop0r)).
736 unsigned NumCycles,
unsigned ExtraPredCycles,
750 return NumInstrs <= 4;
755 const DebugLoc &DL,
unsigned DestReg,
756 unsigned SrcReg,
bool KillSrc)
const {
760 if (Hexagon::IntRegsRegClass.
contains(SrcReg, DestReg)) {
761 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfr), DestReg)
762 .
addReg(SrcReg, KillFlag);
765 if (Hexagon::DoubleRegsRegClass.
contains(SrcReg, DestReg)) {
766 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrp), DestReg)
767 .
addReg(SrcReg, KillFlag);
770 if (Hexagon::PredRegsRegClass.
contains(SrcReg, DestReg)) {
772 BuildMI(MBB, I, DL,
get(Hexagon::C2_or), DestReg)
776 if (Hexagon::CtrRegsRegClass.
contains(DestReg) &&
777 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
778 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrrcr), DestReg)
779 .
addReg(SrcReg, KillFlag);
782 if (Hexagon::IntRegsRegClass.
contains(DestReg) &&
783 Hexagon::CtrRegsRegClass.
contains(SrcReg)) {
784 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrcrr), DestReg)
785 .
addReg(SrcReg, KillFlag);
788 if (Hexagon::ModRegsRegClass.
contains(DestReg) &&
789 Hexagon::IntRegsRegClass.
contains(SrcReg)) {
790 BuildMI(MBB, I, DL,
get(Hexagon::A2_tfrrcr), DestReg)
791 .
addReg(SrcReg, KillFlag);
794 if (Hexagon::PredRegsRegClass.
contains(SrcReg) &&
795 Hexagon::IntRegsRegClass.
contains(DestReg)) {
796 BuildMI(MBB, I, DL,
get(Hexagon::C2_tfrpr), DestReg)
797 .
addReg(SrcReg, KillFlag);
800 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
801 Hexagon::PredRegsRegClass.
contains(DestReg)) {
802 BuildMI(MBB, I, DL,
get(Hexagon::C2_tfrrp), DestReg)
803 .
addReg(SrcReg, KillFlag);
806 if (Hexagon::PredRegsRegClass.
contains(SrcReg) &&
807 Hexagon::IntRegsRegClass.
contains(DestReg)) {
808 BuildMI(MBB, I, DL,
get(Hexagon::C2_tfrpr), DestReg)
809 .
addReg(SrcReg, KillFlag);
812 if (Hexagon::VectorRegsRegClass.
contains(SrcReg, DestReg)) {
813 BuildMI(MBB, I, DL,
get(Hexagon::V6_vassign), DestReg).
814 addReg(SrcReg, KillFlag);
817 if (Hexagon::VecDblRegsRegClass.
contains(SrcReg, DestReg)) {
818 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
819 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
820 BuildMI(MBB, I, DL,
get(Hexagon::V6_vcombine), DestReg)
825 if (Hexagon::VecPredRegsRegClass.
contains(SrcReg, DestReg)) {
826 BuildMI(MBB, I, DL,
get(Hexagon::V6_pred_and), DestReg)
828 .
addReg(SrcReg, KillFlag);
831 if (Hexagon::VecPredRegsRegClass.
contains(SrcReg) &&
832 Hexagon::VectorRegsRegClass.
contains(DestReg)) {
836 if (Hexagon::VecPredRegsRegClass.
contains(DestReg) &&
837 Hexagon::VectorRegsRegClass.
contains(SrcReg)) {
841 if (Hexagon::VecPredRegs128BRegClass.
contains(SrcReg, DestReg)) {
842 unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
843 unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
844 unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
845 unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
846 BuildMI(MBB, I, DL,
get(Hexagon::V6_pred_and), HiDst)
848 BuildMI(MBB, I, DL,
get(Hexagon::V6_pred_and), LoDst)
855 dbgs() <<
"Invalid registers for copy in BB#" << MBB.
getNumber()
857 <<
" = " <<
PrintReg(SrcReg, &HRI) <<
'\n';
875 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
876 BuildMI(MBB, I, DL,
get(Hexagon::S2_storeri_io))
879 }
else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
880 BuildMI(MBB, I, DL,
get(Hexagon::S2_storerd_io))
883 }
else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
884 BuildMI(MBB, I, DL,
get(Hexagon::STriw_pred))
887 }
else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
888 BuildMI(MBB, I, DL,
get(Hexagon::STriw_mod))
891 }
else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
892 BuildMI(MBB, I, DL,
get(Hexagon::PS_vstorerq_ai_128B))
895 }
else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
896 BuildMI(MBB, I, DL,
get(Hexagon::PS_vstorerq_ai))
899 }
else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
900 unsigned Opc = Align < 128 ? Hexagon::V6_vS32Ub_ai_128B
901 : Hexagon::V6_vS32b_ai_128B;
905 }
else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
906 unsigned Opc = Align < 64 ? Hexagon::V6_vS32Ub_ai
907 : Hexagon::V6_vS32b_ai;
911 }
else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
912 unsigned Opc = Align < 64 ? Hexagon::PS_vstorerwu_ai
913 : Hexagon::PS_vstorerw_ai;
917 }
else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
918 unsigned Opc = Align < 128 ? Hexagon::PS_vstorerwu_ai_128B
919 : Hexagon::PS_vstorerw_ai_128B;
941 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
942 BuildMI(MBB, I, DL,
get(Hexagon::L2_loadri_io), DestReg)
944 }
else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
945 BuildMI(MBB, I, DL,
get(Hexagon::L2_loadrd_io), DestReg)
947 }
else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
948 BuildMI(MBB, I, DL,
get(Hexagon::LDriw_pred), DestReg)
950 }
else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
951 BuildMI(MBB, I, DL,
get(Hexagon::LDriw_mod), DestReg)
953 }
else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
954 BuildMI(MBB, I, DL,
get(Hexagon::PS_vloadrq_ai_128B), DestReg)
956 }
else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
957 BuildMI(MBB, I, DL,
get(Hexagon::PS_vloadrq_ai), DestReg)
959 }
else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
960 unsigned Opc = Align < 128 ? Hexagon::PS_vloadrwu_ai_128B
961 : Hexagon::PS_vloadrw_ai_128B;
962 BuildMI(MBB, I, DL,
get(Opc), DestReg)
964 }
else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
965 unsigned Opc = Align < 128 ? Hexagon::V6_vL32Ub_ai_128B
966 : Hexagon::V6_vL32b_ai_128B;
967 BuildMI(MBB, I, DL,
get(Opc), DestReg)
969 }
else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
970 unsigned Opc = Align < 64 ? Hexagon::V6_vL32Ub_ai
971 : Hexagon::V6_vL32b_ai;
972 BuildMI(MBB, I, DL,
get(Opc), DestReg)
974 }
else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
975 unsigned Opc = Align < 64 ? Hexagon::PS_vloadrwu_ai
976 : Hexagon::PS_vloadrw_ai;
977 BuildMI(MBB, I, DL,
get(Opc), DestReg)
1004 const unsigned VecOffset = 1;
1007 case TargetOpcode::COPY: {
1013 std::prev(MBBI)->copyImplicitOps(*MBB.
getParent(),
MI);
1018 case Hexagon::PS_aligna:
1024 case Hexagon::V6_vassignp_128B:
1025 case Hexagon::V6_vassignp: {
1029 BuildMI(MBB, MI, DL,
get(Hexagon::V6_vcombine), DstReg)
1030 .
addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi),
Kill)
1031 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo),
Kill);
1035 case Hexagon::V6_lo_128B:
1036 case Hexagon::V6_lo: {
1039 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1045 case Hexagon::V6_hi_128B:
1046 case Hexagon::V6_hi: {
1049 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1055 case Hexagon::PS_vstorerw_ai:
1056 case Hexagon::PS_vstorerwu_ai:
1057 case Hexagon::PS_vstorerw_ai_128B:
1058 case Hexagon::PS_vstorerwu_ai_128B: {
1059 bool Is128B = (Opc == Hexagon::PS_vstorerw_ai_128B ||
1060 Opc == Hexagon::PS_vstorerwu_ai_128B);
1061 bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
1062 Opc == Hexagon::PS_vstorerw_ai_128B);
1064 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1065 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1068 NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
1069 : Hexagon::V6_vS32b_ai;
1071 NewOpc = Is128B ? Hexagon::V6_vS32Ub_ai_128B
1072 : Hexagon::V6_vS32Ub_ai;
1074 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1076 BuildMI(MBB, MI, DL,
get(NewOpc))
1082 BuildMI(MBB, MI, DL,
get(NewOpc))
1091 case Hexagon::PS_vloadrw_ai:
1092 case Hexagon::PS_vloadrwu_ai:
1093 case Hexagon::PS_vloadrw_ai_128B:
1094 case Hexagon::PS_vloadrwu_ai_128B: {
1095 bool Is128B = (Opc == Hexagon::PS_vloadrw_ai_128B ||
1096 Opc == Hexagon::PS_vloadrwu_ai_128B);
1097 bool Aligned = (Opc == Hexagon::PS_vloadrw_ai ||
1098 Opc == Hexagon::PS_vloadrw_ai_128B);
1101 NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
1102 : Hexagon::V6_vL32b_ai;
1104 NewOpc = Is128B ? Hexagon::V6_vL32Ub_ai_128B
1105 : Hexagon::V6_vL32Ub_ai;
1108 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
1110 BuildMI(MBB, MI, DL,
get(NewOpc),
1111 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1115 BuildMI(MBB, MI, DL,
get(NewOpc),
1116 HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1124 case Hexagon::PS_true: {
1126 BuildMI(MBB, MI, DL,
get(Hexagon::C2_orn), Reg)
1132 case Hexagon::PS_false: {
1134 BuildMI(MBB, MI, DL,
get(Hexagon::C2_andn), Reg)
1140 case Hexagon::PS_vmulw: {
1145 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1146 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1147 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1148 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1150 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1154 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1164 case Hexagon::PS_vmulw_acc: {
1170 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1171 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1172 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1173 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1174 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1175 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1177 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1182 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1195 case Hexagon::PS_pselect: {
1200 unsigned Rd = Op0.
getReg();
1201 unsigned Pu = Op1.
getReg();
1202 unsigned Rs = Op2.
getReg();
1203 unsigned Rt = Op3.
getReg();
1209 BuildMI(MBB, MI, DL,
get(Hexagon::A2_tfrpt), Rd)
1210 .
addReg(Pu, (Rd == Rt) ? K1 : 0)
1213 BuildMI(MBB, MI, DL,
get(Hexagon::A2_tfrpf), Rd)
1219 case Hexagon::PS_vselect:
1220 case Hexagon::PS_vselect_128B: {
1229 auto T =
BuildMI(MBB, MI, DL,
get(Hexagon::V6_vcmov))
1238 auto T =
BuildMI(MBB, MI, DL,
get(Hexagon::V6_vncmov))
1248 case Hexagon::PS_wselect:
1249 case Hexagon::PS_wselect_128B: {
1259 unsigned SrcLo = HRI.getSubReg(Op2.
getReg(), Hexagon::vsub_lo);
1260 unsigned SrcHi = HRI.getSubReg(Op2.
getReg(), Hexagon::vsub_hi);
1261 auto T =
BuildMI(MBB, MI, DL,
get(Hexagon::V6_vccombine))
1271 unsigned SrcLo = HRI.getSubReg(Op3.
getReg(), Hexagon::vsub_lo);
1272 unsigned SrcHi = HRI.getSubReg(Op3.
getReg(), Hexagon::vsub_hi);
1273 auto T =
BuildMI(MBB, MI, DL,
get(Hexagon::V6_vnccombine))
1284 case Hexagon::PS_tailcall_i:
1285 MI.
setDesc(
get(Hexagon::J2_jump));
1287 case Hexagon::PS_tailcall_r:
1288 case Hexagon::PS_jmpret:
1289 MI.
setDesc(
get(Hexagon::J2_jumpr));
1291 case Hexagon::PS_jmprett:
1292 MI.
setDesc(
get(Hexagon::J2_jumprt));
1294 case Hexagon::PS_jmpretf:
1295 MI.
setDesc(
get(Hexagon::J2_jumprf));
1297 case Hexagon::PS_jmprettnewpt:
1298 MI.
setDesc(
get(Hexagon::J2_jumprtnewpt));
1300 case Hexagon::PS_jmpretfnewpt:
1301 MI.
setDesc(
get(Hexagon::J2_jumprfnewpt));
1303 case Hexagon::PS_jmprettnew:
1304 MI.
setDesc(
get(Hexagon::J2_jumprtnew));
1306 case Hexagon::PS_jmpretfnew:
1307 MI.
setDesc(
get(Hexagon::J2_jumprfnew));
1320 assert(Cond[0].isImm() &&
"First entry in the cond vector not imm-val");
1321 unsigned opcode = Cond[0].getImm();
1323 assert(
get(opcode).
isBranch() &&
"Should be a branching condition.");
1327 Cond[0].setImm(NewOpcode);
1334 BuildMI(MBB, MI, DL,
get(Hexagon::A2_nop));
1375 while (NOp < NumOps) {
1383 unsigned PredReg, PredRegPos, PredRegFlags;
1384 bool GotPredReg =
getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1387 T.
addReg(PredReg, PredRegFlags);
1388 while (NOp < NumOps)
1418 if (RC == &Hexagon::PredRegsRegClass) {
1479 bool atInsnStart =
true;
1480 unsigned Length = 0;
1481 for (; *Str; ++Str) {
1485 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1487 atInsnStart =
false;
1491 atInsnStart =
false;
1496 Length += AStr.
count(Occ)*4;
1515 unsigned &SrcReg2,
int &
Mask,
1521 case Hexagon::C2_cmpeq:
1522 case Hexagon::C2_cmpeqp:
1523 case Hexagon::C2_cmpgt:
1524 case Hexagon::C2_cmpgtp:
1525 case Hexagon::C2_cmpgtu:
1526 case Hexagon::C2_cmpgtup:
1527 case Hexagon::C4_cmpneq:
1528 case Hexagon::C4_cmplte:
1529 case Hexagon::C4_cmplteu:
1530 case Hexagon::C2_cmpeqi:
1531 case Hexagon::C2_cmpgti:
1532 case Hexagon::C2_cmpgtui:
1533 case Hexagon::C4_cmpneqi:
1534 case Hexagon::C4_cmplteui:
1535 case Hexagon::C4_cmpltei:
1539 case Hexagon::A4_cmpbeq:
1540 case Hexagon::A4_cmpbgt:
1541 case Hexagon::A4_cmpbgtu:
1542 case Hexagon::A4_cmpbeqi:
1543 case Hexagon::A4_cmpbgti:
1544 case Hexagon::A4_cmpbgtui:
1548 case Hexagon::A4_cmpheq:
1549 case Hexagon::A4_cmphgt:
1550 case Hexagon::A4_cmphgtu:
1551 case Hexagon::A4_cmpheqi:
1552 case Hexagon::A4_cmphgti:
1553 case Hexagon::A4_cmphgtui:
1561 case Hexagon::C2_cmpeq:
1562 case Hexagon::C2_cmpeqp:
1563 case Hexagon::C2_cmpgt:
1564 case Hexagon::C2_cmpgtp:
1565 case Hexagon::C2_cmpgtu:
1566 case Hexagon::C2_cmpgtup:
1567 case Hexagon::A4_cmpbeq:
1568 case Hexagon::A4_cmpbgt:
1569 case Hexagon::A4_cmpbgtu:
1570 case Hexagon::A4_cmpheq:
1571 case Hexagon::A4_cmphgt:
1572 case Hexagon::A4_cmphgtu:
1573 case Hexagon::C4_cmpneq:
1574 case Hexagon::C4_cmplte:
1575 case Hexagon::C4_cmplteu:
1579 case Hexagon::C2_cmpeqi:
1580 case Hexagon::C2_cmpgtui:
1581 case Hexagon::C2_cmpgti:
1582 case Hexagon::C4_cmpneqi:
1583 case Hexagon::C4_cmplteui:
1584 case Hexagon::C4_cmpltei:
1585 case Hexagon::A4_cmpbeqi:
1586 case Hexagon::A4_cmpbgti:
1587 case Hexagon::A4_cmpbgtui:
1588 case Hexagon::A4_cmpheqi:
1589 case Hexagon::A4_cmphgti:
1590 case Hexagon::A4_cmphgtui:
1601 unsigned *PredCost)
const {
1617 int OffsetA = 0, OffsetB = 0;
1618 unsigned SizeA = 0, SizeB = 0;
1631 if (!BaseRegA || !SizeA)
1636 if (!BaseRegB || !SizeB)
1639 if (BaseRegA != BaseRegB)
1644 if (OffsetA > OffsetB) {
1645 uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1646 return (SizeB <= offDiff);
1647 }
else if (OffsetA < OffsetB) {
1648 uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1649 return (SizeA <= offDiff);
1659 unsigned AccessSize;
1662 if (MI.
getOpcode() == Hexagon::A2_addi) {
1674 TRC = &Hexagon::PredRegsRegClass;
1676 TRC = &Hexagon::IntRegsRegClass;
1678 TRC = &Hexagon::DoubleRegsRegClass;
1733 case Hexagon::A2_paddf:
1734 case Hexagon::A2_paddfnew:
1735 case Hexagon::A2_paddif:
1736 case Hexagon::A2_paddifnew:
1737 case Hexagon::A2_paddit:
1738 case Hexagon::A2_padditnew:
1739 case Hexagon::A2_paddt:
1740 case Hexagon::A2_paddtnew:
1741 case Hexagon::A2_pandf:
1742 case Hexagon::A2_pandfnew:
1743 case Hexagon::A2_pandt:
1744 case Hexagon::A2_pandtnew:
1745 case Hexagon::A2_porf:
1746 case Hexagon::A2_porfnew:
1747 case Hexagon::A2_port:
1748 case Hexagon::A2_portnew:
1749 case Hexagon::A2_psubf:
1750 case Hexagon::A2_psubfnew:
1751 case Hexagon::A2_psubt:
1752 case Hexagon::A2_psubtnew:
1753 case Hexagon::A2_pxorf:
1754 case Hexagon::A2_pxorfnew:
1755 case Hexagon::A2_pxort:
1756 case Hexagon::A2_pxortnew:
1757 case Hexagon::A4_paslhf:
1758 case Hexagon::A4_paslhfnew:
1759 case Hexagon::A4_paslht:
1760 case Hexagon::A4_paslhtnew:
1761 case Hexagon::A4_pasrhf:
1762 case Hexagon::A4_pasrhfnew:
1763 case Hexagon::A4_pasrht:
1764 case Hexagon::A4_pasrhtnew:
1765 case Hexagon::A4_psxtbf:
1766 case Hexagon::A4_psxtbfnew:
1767 case Hexagon::A4_psxtbt:
1768 case Hexagon::A4_psxtbtnew:
1769 case Hexagon::A4_psxthf:
1770 case Hexagon::A4_psxthfnew:
1771 case Hexagon::A4_psxtht:
1772 case Hexagon::A4_psxthtnew:
1773 case Hexagon::A4_pzxtbf:
1774 case Hexagon::A4_pzxtbfnew:
1775 case Hexagon::A4_pzxtbt:
1776 case Hexagon::A4_pzxtbtnew:
1777 case Hexagon::A4_pzxthf:
1778 case Hexagon::A4_pzxthfnew:
1779 case Hexagon::A4_pzxtht:
1780 case Hexagon::A4_pzxthtnew:
1781 case Hexagon::C2_ccombinewf:
1782 case Hexagon::C2_ccombinewt:
1794 int PNewOpcode = Hexagon::getPredNewOpcode(MI.
getOpcode());
1796 return PNewOpcode >= 0;
1805 default:
return false;
1806 case Hexagon::S4_storeirbt_io:
1807 case Hexagon::S4_storeirbf_io:
1808 case Hexagon::S4_pstorerbt_rr:
1809 case Hexagon::S4_pstorerbf_rr:
1810 case Hexagon::S2_pstorerbt_io:
1811 case Hexagon::S2_pstorerbf_io:
1812 case Hexagon::S2_pstorerbt_pi:
1813 case Hexagon::S2_pstorerbf_pi:
1814 case Hexagon::S2_pstorerdt_io:
1815 case Hexagon::S2_pstorerdf_io:
1816 case Hexagon::S4_pstorerdt_rr:
1817 case Hexagon::S4_pstorerdf_rr:
1818 case Hexagon::S2_pstorerdt_pi:
1819 case Hexagon::S2_pstorerdf_pi:
1820 case Hexagon::S2_pstorerht_io:
1821 case Hexagon::S2_pstorerhf_io:
1822 case Hexagon::S4_storeirht_io:
1823 case Hexagon::S4_storeirhf_io:
1824 case Hexagon::S4_pstorerht_rr:
1825 case Hexagon::S4_pstorerhf_rr:
1826 case Hexagon::S2_pstorerht_pi:
1827 case Hexagon::S2_pstorerhf_pi:
1828 case Hexagon::S2_pstorerit_io:
1829 case Hexagon::S2_pstorerif_io:
1830 case Hexagon::S4_storeirit_io:
1831 case Hexagon::S4_storeirif_io:
1832 case Hexagon::S4_pstorerit_rr:
1833 case Hexagon::S4_pstorerif_rr:
1834 case Hexagon::S2_pstorerit_pi:
1835 case Hexagon::S2_pstorerif_pi:
1838 case Hexagon::S4_pstorerdt_abs:
1839 case Hexagon::S4_pstorerdf_abs:
1840 case Hexagon::S4_pstorerbt_abs:
1841 case Hexagon::S4_pstorerbf_abs:
1842 case Hexagon::S4_pstorerht_abs:
1843 case Hexagon::S4_pstorerhf_abs:
1844 case Hexagon::S4_pstorerit_abs:
1845 case Hexagon::S4_pstorerif_abs:
1858 case Hexagon::A2_tfrt:
1859 case Hexagon::A2_tfrf:
1860 case Hexagon::C2_cmoveit:
1861 case Hexagon::C2_cmoveif:
1862 case Hexagon::A2_tfrtnew:
1863 case Hexagon::A2_tfrfnew:
1864 case Hexagon::C2_cmovenewit:
1865 case Hexagon::C2_cmovenewif:
1866 case Hexagon::A2_tfrpt:
1867 case Hexagon::A2_tfrpf:
1915 assert(MO.
isImm() &&
"Extendable operand must be Immediate type");
1919 int ImmValue = MO.
getImm();
1921 return (ImmValue < MinValue || ImmValue > MaxValue);
1926 case Hexagon::L4_return :
1927 case Hexagon::L4_return_t :
1928 case Hexagon::L4_return_f :
1929 case Hexagon::L4_return_tnew_pnt :
1930 case Hexagon::L4_return_fnew_pnt :
1931 case Hexagon::L4_return_tnew_pt :
1932 case Hexagon::L4_return_fnew_pt :
1954 for (
auto &RegA : DefsA)
1955 for (
auto &RegB : UsesB) {
1960 if (Hexagon::DoubleRegsRegClass.
contains(RegA))
1962 if (RegB == *SubRegs)
1965 if (Hexagon::DoubleRegsRegClass.
contains(RegB))
1967 if (RegA == *SubRegs)
1977 case Hexagon::V6_vL32b_cur_pi:
1978 case Hexagon::V6_vL32b_cur_ai:
1979 case Hexagon::V6_vL32b_cur_pi_128B:
1980 case Hexagon::V6_vL32b_cur_ai_128B:
2009 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
2015 return (Opcode == Hexagon::ENDLOOP0 ||
2016 Opcode == Hexagon::ENDLOOP1);
2043 case Hexagon::PS_fi:
2044 case Hexagon::PS_fia:
2072 const uint64_t
F =
get(Opcode).TSFlags;
2088 case Hexagon::J2_callr :
2089 case Hexagon::J2_callrf :
2090 case Hexagon::J2_callrt :
2091 case Hexagon::PS_call_nr :
2099 case Hexagon::L4_return :
2100 case Hexagon::L4_return_t :
2101 case Hexagon::L4_return_f :
2102 case Hexagon::L4_return_fnew_pnt :
2103 case Hexagon::L4_return_fnew_pt :
2104 case Hexagon::L4_return_tnew_pnt :
2105 case Hexagon::L4_return_tnew_pt :
2113 case Hexagon::J2_jumpr :
2114 case Hexagon::J2_jumprt :
2115 case Hexagon::J2_jumprf :
2116 case Hexagon::J2_jumprtnewpt :
2117 case Hexagon::J2_jumprfnewpt :
2118 case Hexagon::J2_jumprtnew :
2119 case Hexagon::J2_jumprfnew :
2130 unsigned offset)
const {
2134 return isInt<11>(offset);
2140 case Hexagon::J2_jump:
2141 case Hexagon::J2_call:
2142 case Hexagon::PS_call_nr:
2143 return isInt<24>(offset);
2144 case Hexagon::J2_jumpt:
2145 case Hexagon::J2_jumpf:
2146 case Hexagon::J2_jumptnew:
2147 case Hexagon::J2_jumptnewpt:
2148 case Hexagon::J2_jumpfnew:
2149 case Hexagon::J2_jumpfnewpt:
2150 case Hexagon::J2_callt:
2151 case Hexagon::J2_callf:
2152 return isInt<17>(offset);
2153 case Hexagon::J2_loop0i:
2154 case Hexagon::J2_loop0iext:
2155 case Hexagon::J2_loop0r:
2156 case Hexagon::J2_loop0rext:
2157 case Hexagon::J2_loop1i:
2158 case Hexagon::J2_loop1iext:
2159 case Hexagon::J2_loop1r:
2160 case Hexagon::J2_loop1rext:
2161 return isInt<9>(offset);
2163 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2164 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2165 return isInt<11>(offset);
2174 DEBUG(
dbgs() <<
"V60" << (isLate ?
"-LR " :
" -- "));
2176 DEBUG(
dbgs() <<
"V60" << (isEarly ?
"-ES " :
" -- "));
2179 if (isLate && isEarly) {
2180 DEBUG(
dbgs() <<
"++Is Late Result feeding Early Source\n");
2189 case TargetOpcode::EXTRACT_SUBREG:
2190 case TargetOpcode::INSERT_SUBREG:
2191 case TargetOpcode::SUBREG_TO_REG:
2192 case TargetOpcode::REG_SEQUENCE:
2193 case TargetOpcode::IMPLICIT_DEF:
2194 case TargetOpcode::COPY:
2196 case TargetOpcode::PHI:
2204 switch (SchedClass) {
2205 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2206 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2207 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2208 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2209 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2210 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2211 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2212 case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
2213 case Hexagon::Sched::V2LDST_tc_st_SLOT0:
2214 case Hexagon::Sched::V2LDST_tc_st_SLOT01:
2215 case Hexagon::Sched::V4LDST_tc_ld_SLOT01:
2216 case Hexagon::Sched::V4LDST_tc_st_SLOT0:
2217 case Hexagon::Sched::V4LDST_tc_st_SLOT01:
2231 return Opcode == Hexagon::J2_loop0i ||
2232 Opcode == Hexagon::J2_loop0r ||
2233 Opcode == Hexagon::J2_loop0iext ||
2234 Opcode == Hexagon::J2_loop0rext ||
2235 Opcode == Hexagon::J2_loop1i ||
2236 Opcode == Hexagon::J2_loop1r ||
2237 Opcode == Hexagon::J2_loop1iext ||
2238 Opcode == Hexagon::J2_loop1rext;
2243 default:
return false;
2244 case Hexagon::L4_iadd_memopw_io :
2245 case Hexagon::L4_isub_memopw_io :
2246 case Hexagon::L4_add_memopw_io :
2247 case Hexagon::L4_sub_memopw_io :
2248 case Hexagon::L4_and_memopw_io :
2249 case Hexagon::L4_or_memopw_io :
2250 case Hexagon::L4_iadd_memoph_io :
2251 case Hexagon::L4_isub_memoph_io :
2252 case Hexagon::L4_add_memoph_io :
2253 case Hexagon::L4_sub_memoph_io :
2254 case Hexagon::L4_and_memoph_io :
2255 case Hexagon::L4_or_memoph_io :
2256 case Hexagon::L4_iadd_memopb_io :
2257 case Hexagon::L4_isub_memopb_io :
2258 case Hexagon::L4_add_memopb_io :
2259 case Hexagon::L4_sub_memopb_io :
2260 case Hexagon::L4_and_memopb_io :
2261 case Hexagon::L4_or_memopb_io :
2262 case Hexagon::L4_ior_memopb_io:
2263 case Hexagon::L4_ior_memoph_io:
2264 case Hexagon::L4_ior_memopw_io:
2265 case Hexagon::L4_iand_memopb_io:
2266 case Hexagon::L4_iand_memoph_io:
2267 case Hexagon::L4_iand_memopw_io:
2279 const uint64_t
F =
get(Opcode).TSFlags;
2301 const uint64_t
F =
get(Opcode).TSFlags;
2307 unsigned OperandNum)
const {
2320 const uint64_t
F =
get(Opcode).TSFlags;
2332 const uint64_t
F =
get(Opcode).TSFlags;
2340 const uint64_t
F =
get(Opcode).TSFlags;
2345 const uint64_t
F =
get(Opcode).TSFlags;
2350 const uint64_t
F =
get(Opcode).TSFlags;
2357 return MI.
getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2358 MI.
getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2359 MI.
getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2360 MI.
getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2366 case Hexagon::L2_loadrb_io:
2367 case Hexagon::L4_loadrb_ur:
2368 case Hexagon::L4_loadrb_ap:
2369 case Hexagon::L2_loadrb_pr:
2370 case Hexagon::L2_loadrb_pbr:
2371 case Hexagon::L2_loadrb_pi:
2372 case Hexagon::L2_loadrb_pci:
2373 case Hexagon::L2_loadrb_pcr:
2374 case Hexagon::L2_loadbsw2_io:
2375 case Hexagon::L4_loadbsw2_ur:
2376 case Hexagon::L4_loadbsw2_ap:
2377 case Hexagon::L2_loadbsw2_pr:
2378 case Hexagon::L2_loadbsw2_pbr:
2379 case Hexagon::L2_loadbsw2_pi:
2380 case Hexagon::L2_loadbsw2_pci:
2381 case Hexagon::L2_loadbsw2_pcr:
2382 case Hexagon::L2_loadbsw4_io:
2383 case Hexagon::L4_loadbsw4_ur:
2384 case Hexagon::L4_loadbsw4_ap:
2385 case Hexagon::L2_loadbsw4_pr:
2386 case Hexagon::L2_loadbsw4_pbr:
2387 case Hexagon::L2_loadbsw4_pi:
2388 case Hexagon::L2_loadbsw4_pci:
2389 case Hexagon::L2_loadbsw4_pcr:
2390 case Hexagon::L4_loadrb_rr:
2391 case Hexagon::L2_ploadrbt_io:
2392 case Hexagon::L2_ploadrbt_pi:
2393 case Hexagon::L2_ploadrbf_io:
2394 case Hexagon::L2_ploadrbf_pi:
2395 case Hexagon::L2_ploadrbtnew_io:
2396 case Hexagon::L2_ploadrbfnew_io:
2397 case Hexagon::L4_ploadrbt_rr:
2398 case Hexagon::L4_ploadrbf_rr:
2399 case Hexagon::L4_ploadrbtnew_rr:
2400 case Hexagon::L4_ploadrbfnew_rr:
2401 case Hexagon::L2_ploadrbtnew_pi:
2402 case Hexagon::L2_ploadrbfnew_pi:
2403 case Hexagon::L4_ploadrbt_abs:
2404 case Hexagon::L4_ploadrbf_abs:
2405 case Hexagon::L4_ploadrbtnew_abs:
2406 case Hexagon::L4_ploadrbfnew_abs:
2407 case Hexagon::L2_loadrbgp:
2409 case Hexagon::L2_loadrh_io:
2410 case Hexagon::L4_loadrh_ur:
2411 case Hexagon::L4_loadrh_ap:
2412 case Hexagon::L2_loadrh_pr:
2413 case Hexagon::L2_loadrh_pbr:
2414 case Hexagon::L2_loadrh_pi:
2415 case Hexagon::L2_loadrh_pci:
2416 case Hexagon::L2_loadrh_pcr:
2417 case Hexagon::L4_loadrh_rr:
2418 case Hexagon::L2_ploadrht_io:
2419 case Hexagon::L2_ploadrht_pi:
2420 case Hexagon::L2_ploadrhf_io:
2421 case Hexagon::L2_ploadrhf_pi:
2422 case Hexagon::L2_ploadrhtnew_io:
2423 case Hexagon::L2_ploadrhfnew_io:
2424 case Hexagon::L4_ploadrht_rr:
2425 case Hexagon::L4_ploadrhf_rr:
2426 case Hexagon::L4_ploadrhtnew_rr:
2427 case Hexagon::L4_ploadrhfnew_rr:
2428 case Hexagon::L2_ploadrhtnew_pi:
2429 case Hexagon::L2_ploadrhfnew_pi:
2430 case Hexagon::L4_ploadrht_abs:
2431 case Hexagon::L4_ploadrhf_abs:
2432 case Hexagon::L4_ploadrhtnew_abs:
2433 case Hexagon::L4_ploadrhfnew_abs:
2434 case Hexagon::L2_loadrhgp:
2448 case Hexagon::STriw_pred :
2449 case Hexagon::LDriw_pred :
2461 if (
Op.isGlobal() ||
Op.isSymbol())
2469 switch (SchedClass) {
2470 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2471 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2472 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2473 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2474 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2476 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2477 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2487 switch (SchedClass) {
2488 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
2489 case Hexagon::Sched::ALU64_tc_2_SLOT23:
2490 case Hexagon::Sched::CR_tc_2_SLOT3:
2491 case Hexagon::Sched::M_tc_2_SLOT23:
2492 case Hexagon::Sched::S_2op_tc_2_SLOT23:
2493 case Hexagon::Sched::S_3op_tc_2_SLOT23:
2503 switch (SchedClass) {
2504 case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
2505 case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
2506 case Hexagon::Sched::ALU64_tc_2early_SLOT23:
2507 case Hexagon::Sched::CR_tc_2early_SLOT23:
2508 case Hexagon::Sched::CR_tc_2early_SLOT3:
2509 case Hexagon::Sched::J_tc_2early_SLOT0123:
2510 case Hexagon::Sched::J_tc_2early_SLOT2:
2511 case Hexagon::Sched::J_tc_2early_SLOT23:
2512 case Hexagon::Sched::S_2op_tc_2early_SLOT23:
2513 case Hexagon::Sched::S_3op_tc_2early_SLOT23:
2523 return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
2533 for (
int I = 0;
I <
N;
I++)
2538 if (MI2.
getOpcode() == Hexagon::V6_vS32b_pi)
2546 const uint64_t V =
getType(MI);
2557 (Offset & 0x3f) == 0);
2564 (Offset & 0x7f) == 0);
2569 (Offset & 0x7) == 0);
2574 (Offset & 0x3) == 0);
2579 (Offset & 0x1) == 0);
2589 bool Extend)
const {
2600 case Hexagon::PS_vstorerq_ai:
2601 case Hexagon::PS_vstorerw_ai:
2602 case Hexagon::PS_vloadrq_ai:
2603 case Hexagon::PS_vloadrw_ai:
2604 case Hexagon::V6_vL32b_ai:
2605 case Hexagon::V6_vS32b_ai:
2606 case Hexagon::V6_vL32Ub_ai:
2607 case Hexagon::V6_vS32Ub_ai:
2611 case Hexagon::PS_vstorerq_ai_128B:
2612 case Hexagon::PS_vstorerw_ai_128B:
2613 case Hexagon::PS_vloadrq_ai_128B:
2614 case Hexagon::PS_vloadrw_ai_128B:
2615 case Hexagon::V6_vL32b_ai_128B:
2616 case Hexagon::V6_vS32b_ai_128B:
2617 case Hexagon::V6_vL32Ub_ai_128B:
2618 case Hexagon::V6_vS32Ub_ai_128B:
2622 case Hexagon::J2_loop0i:
2623 case Hexagon::J2_loop1i:
2624 return isUInt<10>(
Offset);
2626 case Hexagon::S4_storeirb_io:
2627 case Hexagon::S4_storeirbt_io:
2628 case Hexagon::S4_storeirbf_io:
2629 return isUInt<6>(
Offset);
2631 case Hexagon::S4_storeirh_io:
2632 case Hexagon::S4_storeirht_io:
2633 case Hexagon::S4_storeirhf_io:
2634 return isShiftedUInt<6,1>(
Offset);
2636 case Hexagon::S4_storeiri_io:
2637 case Hexagon::S4_storeirit_io:
2638 case Hexagon::S4_storeirif_io:
2639 return isShiftedUInt<6,2>(
Offset);
2646 case Hexagon::L2_loadri_io:
2647 case Hexagon::S2_storeri_io:
2651 case Hexagon::L2_loadrd_io:
2652 case Hexagon::S2_storerd_io:
2656 case Hexagon::L2_loadrh_io:
2657 case Hexagon::L2_loadruh_io:
2658 case Hexagon::S2_storerh_io:
2662 case Hexagon::L2_loadrb_io:
2663 case Hexagon::L2_loadrub_io:
2664 case Hexagon::S2_storerb_io:
2668 case Hexagon::A2_addi:
2672 case Hexagon::L4_iadd_memopw_io :
2673 case Hexagon::L4_isub_memopw_io :
2674 case Hexagon::L4_add_memopw_io :
2675 case Hexagon::L4_sub_memopw_io :
2676 case Hexagon::L4_and_memopw_io :
2677 case Hexagon::L4_or_memopw_io :
2678 return (0 <= Offset && Offset <= 255);
2680 case Hexagon::L4_iadd_memoph_io :
2681 case Hexagon::L4_isub_memoph_io :
2682 case Hexagon::L4_add_memoph_io :
2683 case Hexagon::L4_sub_memoph_io :
2684 case Hexagon::L4_and_memoph_io :
2685 case Hexagon::L4_or_memoph_io :
2686 return (0 <= Offset && Offset <= 127);
2688 case Hexagon::L4_iadd_memopb_io :
2689 case Hexagon::L4_isub_memopb_io :
2690 case Hexagon::L4_add_memopb_io :
2691 case Hexagon::L4_sub_memopb_io :
2692 case Hexagon::L4_and_memopb_io :
2693 case Hexagon::L4_or_memopb_io :
2694 return (0 <= Offset && Offset <= 63);
2698 case Hexagon::STriw_pred:
2699 case Hexagon::LDriw_pred:
2700 case Hexagon::STriw_mod:
2701 case Hexagon::LDriw_mod:
2704 case Hexagon::PS_fi:
2705 case Hexagon::PS_fia:
2709 case Hexagon::L2_ploadrbt_io:
2710 case Hexagon::L2_ploadrbf_io:
2711 case Hexagon::L2_ploadrubt_io:
2712 case Hexagon::L2_ploadrubf_io:
2713 case Hexagon::S2_pstorerbt_io:
2714 case Hexagon::S2_pstorerbf_io:
2715 return isUInt<6>(
Offset);
2717 case Hexagon::L2_ploadrht_io:
2718 case Hexagon::L2_ploadrhf_io:
2719 case Hexagon::L2_ploadruht_io:
2720 case Hexagon::L2_ploadruhf_io:
2721 case Hexagon::S2_pstorerht_io:
2722 case Hexagon::S2_pstorerhf_io:
2723 return isShiftedUInt<6,1>(
Offset);
2725 case Hexagon::L2_ploadrit_io:
2726 case Hexagon::L2_ploadrif_io:
2727 case Hexagon::S2_pstorerit_io:
2728 case Hexagon::S2_pstorerif_io:
2729 return isShiftedUInt<6,2>(
Offset);
2731 case Hexagon::L2_ploadrdt_io:
2732 case Hexagon::L2_ploadrdf_io:
2733 case Hexagon::S2_pstorerdt_io:
2734 case Hexagon::S2_pstorerdf_io:
2735 return isShiftedUInt<6,3>(
Offset);
2739 "Please define it in the above switch statement!");
2747 const uint64_t
F =
get(MI.
getOpcode()).TSFlags;
2771 case Hexagon::L2_loadrub_io:
2772 case Hexagon::L4_loadrub_ur:
2773 case Hexagon::L4_loadrub_ap:
2774 case Hexagon::L2_loadrub_pr:
2775 case Hexagon::L2_loadrub_pbr:
2776 case Hexagon::L2_loadrub_pi:
2777 case Hexagon::L2_loadrub_pci:
2778 case Hexagon::L2_loadrub_pcr:
2779 case Hexagon::L2_loadbzw2_io:
2780 case Hexagon::L4_loadbzw2_ur:
2781 case Hexagon::L4_loadbzw2_ap:
2782 case Hexagon::L2_loadbzw2_pr:
2783 case Hexagon::L2_loadbzw2_pbr:
2784 case Hexagon::L2_loadbzw2_pi:
2785 case Hexagon::L2_loadbzw2_pci:
2786 case Hexagon::L2_loadbzw2_pcr:
2787 case Hexagon::L2_loadbzw4_io:
2788 case Hexagon::L4_loadbzw4_ur:
2789 case Hexagon::L4_loadbzw4_ap:
2790 case Hexagon::L2_loadbzw4_pr:
2791 case Hexagon::L2_loadbzw4_pbr:
2792 case Hexagon::L2_loadbzw4_pi:
2793 case Hexagon::L2_loadbzw4_pci:
2794 case Hexagon::L2_loadbzw4_pcr:
2795 case Hexagon::L4_loadrub_rr:
2796 case Hexagon::L2_ploadrubt_io:
2797 case Hexagon::L2_ploadrubt_pi:
2798 case Hexagon::L2_ploadrubf_io:
2799 case Hexagon::L2_ploadrubf_pi:
2800 case Hexagon::L2_ploadrubtnew_io:
2801 case Hexagon::L2_ploadrubfnew_io:
2802 case Hexagon::L4_ploadrubt_rr:
2803 case Hexagon::L4_ploadrubf_rr:
2804 case Hexagon::L4_ploadrubtnew_rr:
2805 case Hexagon::L4_ploadrubfnew_rr:
2806 case Hexagon::L2_ploadrubtnew_pi:
2807 case Hexagon::L2_ploadrubfnew_pi:
2808 case Hexagon::L4_ploadrubt_abs:
2809 case Hexagon::L4_ploadrubf_abs:
2810 case Hexagon::L4_ploadrubtnew_abs:
2811 case Hexagon::L4_ploadrubfnew_abs:
2812 case Hexagon::L2_loadrubgp:
2814 case Hexagon::L2_loadruh_io:
2815 case Hexagon::L4_loadruh_ur:
2816 case Hexagon::L4_loadruh_ap:
2817 case Hexagon::L2_loadruh_pr:
2818 case Hexagon::L2_loadruh_pbr:
2819 case Hexagon::L2_loadruh_pi:
2820 case Hexagon::L2_loadruh_pci:
2821 case Hexagon::L2_loadruh_pcr:
2822 case Hexagon::L4_loadruh_rr:
2823 case Hexagon::L2_ploadruht_io:
2824 case Hexagon::L2_ploadruht_pi:
2825 case Hexagon::L2_ploadruhf_io:
2826 case Hexagon::L2_ploadruhf_pi:
2827 case Hexagon::L2_ploadruhtnew_io:
2828 case Hexagon::L2_ploadruhfnew_io:
2829 case Hexagon::L4_ploadruht_rr:
2830 case Hexagon::L4_ploadruhf_rr:
2831 case Hexagon::L4_ploadruhtnew_rr:
2832 case Hexagon::L4_ploadruhfnew_rr:
2833 case Hexagon::L2_ploadruhtnew_pi:
2834 case Hexagon::L2_ploadruhfnew_pi:
2835 case Hexagon::L4_ploadruht_abs:
2836 case Hexagon::L4_ploadruhf_abs:
2837 case Hexagon::L4_ploadruhtnew_abs:
2838 case Hexagon::L4_ploadruhfnew_abs:
2839 case Hexagon::L2_loadruhgp:
2859 unsigned AccessSize = 0;
2863 return BaseReg != 0;
2876 if (!Stored.
isReg())
2889 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2905 if (Hexagon::getRegForm(MI.
getOpcode()) >= 0)
2915 NonExtOpcode = Hexagon::getBaseWithImmOffset(MI.
getOpcode());
2921 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI.
getOpcode());
2924 NonExtOpcode = Hexagon::getRegShlForm(MI.
getOpcode());
2929 if (NonExtOpcode < 0)
2937 return Hexagon::getRealHWInstr(MI.
getOpcode(),
2938 Hexagon::InstrType_Pseudo) >= 0;
2993 if (!MII->isBundle()) {
3002 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3011 unsigned PredReg)
const {
3021 return MI.
getOpcode() != Hexagon::A4_tlbmatch;
3025 return (Opcode == Hexagon::J2_jumpt) ||
3026 (Opcode == Hexagon::J2_jumpf) ||
3027 (Opcode == Hexagon::J2_jumptnew) ||
3028 (Opcode == Hexagon::J2_jumpfnew) ||
3029 (Opcode == Hexagon::J2_jumptnewpt) ||
3030 (Opcode == Hexagon::J2_jumpfnewpt);
3040 return Hexagon::getAbsoluteForm(MI.
getOpcode());
3051 int &
Offset,
unsigned &AccessSize)
const {
3061 "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
3069 unsigned basePos = 0, offsetPos = 0;
3086 unsigned &BasePos,
unsigned &OffsetPos)
const {
3148 while (I->isDebugValue()) {
3153 if (!isUnpredicatedTerminator(*I))
3162 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3163 if (!SecondLastInst) {
3164 SecondLastInst = &*
I;
3179 return Hexagon::getBaseWithLongOffset(Opcode);
3183 return Hexagon::getBaseWithLongOffset(MI.
getOpcode());
3187 return Hexagon::getBaseWithRegOffset(MI.
getOpcode());
3200 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3211 case Hexagon::C2_cmpeq:
3212 case Hexagon::C2_cmpgt:
3213 case Hexagon::C2_cmpgtu:
3217 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3218 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3222 case Hexagon::C2_cmpeqi:
3223 case Hexagon::C2_cmpgti:
3224 case Hexagon::C2_cmpgtui:
3228 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3229 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3235 case Hexagon::A2_tfr:
3242 case Hexagon::A2_tfrsi:
3250 case Hexagon::S2_tstbit_i:
3253 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3254 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3263 case Hexagon::J2_jumptnew:
3264 case Hexagon::J2_jumpfnew:
3265 case Hexagon::J2_jumptnewpt:
3266 case Hexagon::J2_jumpfnewpt:
3268 if (Hexagon::PredRegsRegClass.
contains(Src1Reg) &&
3269 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3276 case Hexagon::J2_jump:
3277 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3278 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3291 if ((GA.
getOpcode() != Hexagon::C2_cmpeqi) ||
3292 (GB.
getOpcode() != Hexagon::J2_jumptnew))
3297 if (DestReg == Hexagon::P0)
3298 return Hexagon::J4_cmpeqi_tp0_jump_nt;
3299 if (DestReg == Hexagon::P1)
3300 return Hexagon::J4_cmpeqi_tp1_jump_nt;
3305 enum Hexagon::PredSense inPredSense;
3306 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3307 Hexagon::PredSense_true;
3308 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3309 if (CondOpcode >= 0)
3319 case Hexagon::V6_vL32b_pi:
3320 return Hexagon::V6_vL32b_cur_pi;
3321 case Hexagon::V6_vL32b_ai:
3322 return Hexagon::V6_vL32b_cur_ai;
3324 case Hexagon::V6_vL32b_pi_128B:
3325 return Hexagon::V6_vL32b_cur_pi_128B;
3326 case Hexagon::V6_vL32b_ai_128B:
3327 return Hexagon::V6_vL32b_cur_ai_128B;
3413 int NVOpcode = Hexagon::getNewValueOpcode(MI.
getOpcode());
3419 case Hexagon::S4_storerb_ur:
3420 return Hexagon::S4_storerbnew_ur;
3422 case Hexagon::S2_storerb_pci:
3423 return Hexagon::S2_storerb_pci;
3425 case Hexagon::S2_storeri_pci:
3426 return Hexagon::S2_storeri_pci;
3428 case Hexagon::S2_storerh_pci:
3429 return Hexagon::S2_storerh_pci;
3431 case Hexagon::S2_storerd_pci:
3432 return Hexagon::S2_storerd_pci;
3434 case Hexagon::S2_storerf_pci:
3435 return Hexagon::S2_storerf_pci;
3437 case Hexagon::V6_vS32b_ai:
3438 return Hexagon::V6_vS32b_new_ai;
3440 case Hexagon::V6_vS32b_pi:
3441 return Hexagon::V6_vS32b_new_pi;
3444 case Hexagon::V6_vS32b_ai_128B:
3445 return Hexagon::V6_vS32b_new_ai_128B;
3447 case Hexagon::V6_vS32b_pi_128B:
3448 return Hexagon::V6_vS32b_new_pi_128B;
3469 case Hexagon::J2_jumpt:
3470 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3471 case Hexagon::J2_jumpf:
3472 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3482 int NewOpcode = Hexagon::getPredNewOpcode(MI.
getOpcode());
3488 case Hexagon::J2_jumpt:
3489 case Hexagon::J2_jumpf:
3493 assert(0 &&
"Unknown .new type");
3501 NewOp = Hexagon::getPredOldOpcode(NewOp);
3503 "Couldn't change predicate new instruction to its old form.");
3507 NewOp = Hexagon::getNonNVStore(NewOp);
3508 assert(NewOp >= 0 &&
"Couldn't change new-value store to its old form.");
3517 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3528 case Hexagon::L2_loadri_io:
3534 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
3535 HRI.getStackRegister() == SrcReg &&
3546 case Hexagon::L2_loadrub_io:
3564 case Hexagon::L2_loadrh_io:
3565 case Hexagon::L2_loadruh_io:
3574 case Hexagon::L2_loadrb_io:
3583 case Hexagon::L2_loadrd_io:
3588 Hexagon::IntRegsRegClass.
contains(SrcReg) &&
3589 HRI.getStackRegister() == SrcReg &&
3596 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3597 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3598 case Hexagon::L4_return:
3599 case Hexagon::L2_deallocframe:
3601 case Hexagon::EH_RETURN_JMPR:
3602 case Hexagon::PS_jmpret:
3606 if (Hexagon::IntRegsRegClass.
contains(DstReg) && (Hexagon::R31 == DstReg))
3609 case Hexagon::PS_jmprett:
3610 case Hexagon::PS_jmpretf:
3611 case Hexagon::PS_jmprettnewpt:
3612 case Hexagon::PS_jmpretfnewpt:
3613 case Hexagon::PS_jmprettnew:
3614 case Hexagon::PS_jmpretfnew:
3618 if ((Hexagon::PredRegsRegClass.
contains(SrcReg) &&
3619 (Hexagon::P0 == SrcReg)) &&
3620 (Hexagon::IntRegsRegClass.
contains(DstReg) && (Hexagon::R31 == DstReg)))
3623 case Hexagon::L4_return_t :
3624 case Hexagon::L4_return_f :
3625 case Hexagon::L4_return_tnew_pnt :
3626 case Hexagon::L4_return_fnew_pnt :
3627 case Hexagon::L4_return_tnew_pt :
3628 case Hexagon::L4_return_fnew_pt :
3631 if (Hexagon::PredRegsRegClass.
contains(SrcReg) && (Hexagon::P0 == SrcReg))
3639 case Hexagon::S2_storeri_io:
3644 if (Hexagon::IntRegsRegClass.
contains(Src1Reg) &&
3655 case Hexagon::S2_storerb_io:
3672 case Hexagon::S2_storerh_io:
3681 case Hexagon::S2_storerd_io:
3686 Hexagon::IntRegsRegClass.
contains(Src1Reg) &&
3691 case Hexagon::S4_storeiri_io:
3699 case Hexagon::S4_storeirb_io:
3707 case Hexagon::S2_allocframe:
3730 case Hexagon::A2_addi:
3735 if (Hexagon::IntRegsRegClass.
contains(SrcReg) &&
3751 case Hexagon::A2_add:
3760 case Hexagon::A2_andir:
3772 case Hexagon::A2_tfr:
3779 case Hexagon::A2_tfrsi:
3788 case Hexagon::C2_cmoveit:
3789 case Hexagon::C2_cmovenewit:
3790 case Hexagon::C2_cmoveif:
3791 case Hexagon::C2_cmovenewif:
3798 Hexagon::PredRegsRegClass.
contains(SrcReg) && Hexagon::P0 == SrcReg &&
3802 case Hexagon::C2_cmpeqi:
3806 if (Hexagon::PredRegsRegClass.
contains(DstReg) &&
3811 case Hexagon::A2_combineii:
3812 case Hexagon::A4_combineii:
3824 case Hexagon::A4_combineri:
3833 case Hexagon::A4_combineir:
3842 case Hexagon::A2_sxtb:
3843 case Hexagon::A2_sxth:
3844 case Hexagon::A2_zxtb:
3845 case Hexagon::A2_zxth:
3858 return Hexagon::getRealHWInstr(MI.
getOpcode(), Hexagon::InstrType_Real);
3902 Cond[0].setImm(Opc);
3909 : Hexagon::getTruePredOpcode(Opc);
3910 if (InvPredOpcode >= 0)
3911 return InvPredOpcode;
3925 return ~(-1U << (bits - 1));
3927 return ~(-1U <<
bits);
3944 return -1U << (bits - 1);
3953 short NonExtOpcode = Hexagon::getRegForm(MI.
getOpcode());
3954 if (NonExtOpcode >= 0)
3955 return NonExtOpcode;
3961 return Hexagon::getBaseWithImmOffset(MI.
getOpcode());
3963 return Hexagon::getBaseWithRegOffset(MI.
getOpcode());
3965 return Hexagon::getRegShlForm(MI.
getOpcode());
3975 unsigned &PredReg,
unsigned &PredRegPos,
unsigned &PredRegFlags)
const {
3980 DEBUG(
dbgs() <<
"No predregs for new-value jumps/endloop");
3983 PredReg = Cond[1].getReg();
3987 if (Cond[1].isImplicit())
3989 if (Cond[1].isUndef())
3995 return Hexagon::getRealHWInstr(MI.
getOpcode(), Hexagon::InstrType_Pseudo);
3999 return Hexagon::getRegForm(MI.
getOpcode());
4026 unsigned NumDefs = 0;
4054 const uint64_t
F =
get(Opcode).TSFlags;
4065 assert(BundleHead->isBundle() &&
"Not a bundle header");
4075 "Instruction must be extendable");
4081 "Branch with unknown extendable field type");
4088 DEBUG(
dbgs() <<
"\n[invertAndChangeJumpTarget] to BB#"
4114 for (
unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4115 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4116 NewMI =
BuildMI(B, I, DL,
get(insn));
4128 DEBUG(
dbgs() <<
"\nTrying to reverse pred. sense of:"; MI.
dump());
4135 int PredRevOpcode = -1;
4137 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4139 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4140 assert(PredRevOpcode > 0);
4141 return PredRevOpcode;
4147 return Cond.
empty() || (Cond[0].isImm() && (Cond.
size() != 1));
4151 return Hexagon::xformRegToImmOffset(MI.
getOpcode());
static bool isReg(const MCInst &MI, unsigned OpNo)
bool hasPseudoInstrPair(const MachineInstr &MI) const
void push_back(const T &Elt)
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
mop_iterator operands_end()
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
bool isIndirectCall(const MachineInstr &MI) const
This class is the base class for the comparison instructions.
short getBaseWithLongOffset(short Opcode) const
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
unsigned reversePrediction(unsigned Opcode) const
instr_iterator instr_end()
const int Hexagon_ADDI_OFFSET_MAX
bool isTC1(const MachineInstr &MI) const
unsigned getFrameRegister(const MachineFunction &MF) const override
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
const int Hexagon_MEMH_OFFSET_MIN
bool isIndirectL4Return(const MachineInstr &MI) const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
MachineBasicBlock * getMBB() const
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
bool isNewValueInst(const MachineInstr &MI) const
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool isPredicateLate(unsigned Opcode) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
short getPseudoInstrPair(const MachineInstr &MI) const
bool mayStore() const
Return true if this instruction could possibly modify memory.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
short getNonExtOpcode(const MachineInstr &MI) const
bool isPredicatedTrue(const MachineInstr &MI) const
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Address of indexed Jump Table for switch.
bool PredOpcodeHasJMP_c(unsigned Opcode) const
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const int Hexagon_MEMV_OFFSET_MAX_128B
Constants for Hexagon instructions.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
const int Hexagon_ADDI_OFFSET_MIN
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const int Hexagon_MEMV_OFFSET_MIN
bool isMemOp(const MachineInstr &MI) const
MachineBasicBlock reference.
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
const char * getSymbolName() const
bool isTailCall(const MachineInstr &MI) const override
bool isNewValue(const MachineInstr &MI) const
const int Hexagon_MEMV_AUTOINC_MIN
const int Hexagon_MEMD_OFFSET_MAX
iterator_range< mop_iterator > operands()
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isVecAcc(const MachineInstr &MI) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
StringRef getCommentString() const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
bool isAbsoluteSet(const MachineInstr &MI) const
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
struct fuzzer::@269 Flags
const HexagonInstrInfo * TII
bool isExpr(unsigned OpType) const
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
bool isTC4x(const MachineInstr &MI) const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
short getAbsoluteForm(const MachineInstr &MI) const
Name of external global symbol.
Reg
All possible values of the reg field in the ModR/M byte.
static StringRef getName(Value *V)
bool isSpillPredRegOp(const MachineInstr &MI) const
unsigned getUnits() const
Returns the choice of FUs.
bool isLateResultInstr(const MachineInstr &MI) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
short xformRegToImmOffset(const MachineInstr &MI) const
bool isTerminator() const
Returns true if this instruction part of the terminator for a basic block.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
bool isCondInst(const MachineInstr &MI) const
const int Hexagon_MEMH_AUTOINC_MIN
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isLoopN(const MachineInstr &MI) const
const int Hexagon_MEMB_AUTOINC_MAX
int getMaxValue(const MachineInstr &MI) const
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
LLVM_NODISCARD bool empty() const
unsigned getNumOperands() const
Access to explicit operands of the instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
void RemoveOperand(unsigned i)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const HexagonRegisterInfo & getRegisterInfo() const
HexagonInstrInfo specifics.
void genAllInsnTimingClasses(MachineFunction &MF) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
bool isComplex(const MachineInstr &MI) const
bool isConditionalALU32(const MachineInstr &MI) const
bool isAccumulator(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool isPredictedTaken(unsigned Opcode) const
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
const int Hexagon_MEMD_AUTOINC_MIN
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Itinerary data supplied by a subtarget to be used by a target.
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
static GCRegistry::Add< OcamlGC > B("ocaml","ocaml 3.10-compatible GC")
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
bool isEarlySourceInstr(const MachineInstr &MI) const
std::vector< MachineBasicBlock * >::iterator pred_iterator
const int Hexagon_MEMV_AUTOINC_MAX
unsigned getInvertedPredicatedOpcode(const int Opc) const
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE size_t size() const
size - Get the string size.
Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubRegIdx=0)
Prints virtual and physical registers with or without a TRI instance.
unsigned getUndefRegState(bool B)
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
bool isJumpR(const MachineInstr &MI) const
size_t size() const
size - Get the array size.
const int Hexagon_MEMW_AUTOINC_MAX
reverse_iterator rbegin()
unsigned getKillRegState(bool B)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
static GCRegistry::Add< CoreCLRGC > E("coreclr","CoreCLR-compatible GC")
const int Hexagon_MEMD_OFFSET_MIN
const MachineBasicBlock * getParent() const
TargetInstrInfo - Interface to description of machine instruction set.
bool isDebugValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
int getDotOldOp(const int opc) const
mmo_iterator memoperands_end() const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
bool isVecALU(const MachineInstr &MI) const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Address of a global value.
initializer< Ty > init(const Ty &Val)
unsigned getTargetFlags() const
bool isReturn(QueryType Type=AnyInBundle) const
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
const int Hexagon_MEMW_OFFSET_MAX
const int Hexagon_MEMH_AUTOINC_MAX
unsigned getCExtOpNum(const MachineInstr &MI) const
unsigned const MachineRegisterInfo * MRI
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
MVT - Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
bool reversePredSense(MachineInstr &MI) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isLateSourceInstr(const MachineInstr &MI) const
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin()
const MachineOperand & getOperand(unsigned i) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
bool isNewValueStore(const MachineInstr &MI) const
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
void setMBB(MachineBasicBlock *MBB)
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle): Remove Defs, add uses.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Address of a basic block.
static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI)
unsigned getSize(const MachineInstr &MI) const
static const unsigned End
void setImm(int64_t immVal)
unsigned createVR(MachineFunction *MF, MVT VT) const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore...
int64_t getOffset() const
Return the offset from the symbol in this operand.
MachineInstr * getFirstNonDbgInst(MachineBasicBlock *BB) const
self_iterator getIterator()
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool empty() const
empty - Check if the array is empty.
bool isTC2(const MachineInstr &MI) const
EVT - Extended Value Type.
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
bool isDotCurInst(const MachineInstr &MI) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isExtended(const MachineInstr &MI) const
MCSubRegIterator enumerates all sub-registers of Reg.
pred_iterator pred_begin()
static cl::opt< unsigned > MaxIter("bb-vectorize-max-iter", cl::init(0), cl::Hidden, cl::desc("The maximum number of pairing iterations"))
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
cl::opt< bool > ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, cl::init(false), cl::desc("Do not consider inline-asm a scheduling/""packetization boundary."))
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasUncondBranch(const MachineBasicBlock *B) const
bool hasNonExtEquivalent(const MachineInstr &MI) const
static cl::opt< bool > EnableACCForwarding("enable-acc-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec acc forwarding"))
bool isConditionalTransfer(const MachineInstr &MI) const
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
void setIsKill(bool Val=true)
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE instructions.
unsigned getOpcode() const
Return the opcode number for this descriptor.
The memory access writes data.
short getEquivalentHWInstr(const MachineInstr &MI) const
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
unsigned getMemAccessSize(const MachineInstr &MI) const
unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const override
Generate code to reduce the loop iteration by one and check if the loop is finished.
bool isZeroExtendingLoad(const MachineInstr &MI) const
static bool isIntRegForSubInst(unsigned Reg)
bool hasEHLabel(const MachineBasicBlock *B) const
Iterator for intrusive lists based on ilist_node.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements...
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
const int Hexagon_MEMW_AUTOINC_MIN
HexagonInstrInfo(HexagonSubtarget &ST)
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static MachineInstr * findLoopInstr(MachineBasicBlock *BB, int EndLoopOp, SmallPtrSet< MachineBasicBlock *, 8 > &Visited)
Find the hardware loop instruction used to set-up the specified loop.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
const int Hexagon_MEMV_OFFSET_MAX
MachineOperand class - Representation of each machine instruction operand.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isCompoundBranchInstr(const MachineInstr &MI) const
int getCondOpcode(int Opc, bool sense) const
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
bool isTC2Early(const MachineInstr &MI) const
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI)
bool isPredicable(MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
const int Hexagon_MEMV_OFFSET_MIN_128B
bool mayLoad() const
Return true if this instruction could possibly read memory.
instr_iterator getInstrIterator() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void dump(const TargetInstrInfo *TII=nullptr) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
bool isV60VectorInstruction(const MachineInstr &MI) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const override
Measure the specified inline asm to determine an approximation of its length.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SynchronizationScope SynchScope=CrossThread, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
static bool isDuplexPairMatch(unsigned Ga, unsigned Gb)
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
unsigned getBaseAndOffset(const MachineInstr &MI, int &Offset, unsigned &AccessSize) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
bool isEndLoopN(unsigned Opcode) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
bool isSignExtendingLoad(const MachineInstr &MI) const
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
bool isPredicatedNew(const MachineInstr &MI) const
bool isDeallocRet(const MachineInstr &MI) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
TargetSubtargetInfo - Generic base class for all target subtargets.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool isFloat(const MachineInstr &MI) const
Representation of each machine instruction.
unsigned getAddrMode(const MachineInstr &MI) const
LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end()
unsigned getSchedClass() const
Return the scheduling class for this instruction.
void addTargetFlag(unsigned F)
bool isDotNewInst(const MachineInstr &MI) const
static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB, MachineBasicBlock::const_instr_iterator MIE)
Calculate number of instructions excluding the debug instructions.
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
const int Hexagon_MEMB_OFFSET_MAX
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
A set of live physical registers with functions to track liveness when walking backward/forward throu...
bool isValidAutoIncImm(const EVT VT, const int Offset) const
bool isExtendable(const MachineInstr &MI) const
int getDotNewOp(const MachineInstr &MI) const
short getRegForm(const MachineInstr &MI) const
These values represent a non-pipelined step in the execution of an instruction.
Represents a single loop in the control flow graph.
short getBaseWithRegOffset(const MachineInstr &MI) const
const char * getSeparatorString() const
unsigned getValidSubTargets(const unsigned Opcode) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
static MachineOperand CreateImm(int64_t Val)
bool isCall(QueryType Type=AnyInBundle) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const int Hexagon_MEMW_OFFSET_MIN
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
int getDotCurOp(const MachineInstr &MI) const
bool isConditionalStore(const MachineInstr &MI) const
bool isConditionalLoad(const MachineInstr &MI) const
bool mayBeNewStore(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
unsigned getReg() const
getReg - Returns the register number.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isBranch(unsigned Opcode)
bool doesNotReturn(const MachineInstr &CallMI) const
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
#define HEXAGON_INSTR_SIZE
virtual const TargetInstrInfo * getInstrInfo() const
LLVM Value Representation.
const int Hexagon_MEMV_AUTOINC_MIN_128B
unsigned getMaxInstLength() const
mop_iterator operands_begin()
bool mayBeCurLoad(const MachineInstr &MI) const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
bool available(const MachineRegisterInfo &MRI, unsigned Reg) const
Returns true if register Reg and no aliasing register is in the set.
MachineInstrBundleIterator< const MachineInstr > const_iterator
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
BasicBlockListType::iterator iterator
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
static cl::opt< bool > EnableTimingClassLatency("enable-timing-class-latency", cl::Hidden, cl::init(false), cl::desc("Enable timing class latency"))
int getMinValue(const MachineInstr &MI) const
StringRef - Represent a constant reference to a string, i.e.
Address of indexed Constant in Constant Pool.
const int Hexagon_MEMD_AUTOINC_MAX
const int Hexagon_MEMV_AUTOINC_MAX_128B
MachineBasicBlock::instr_iterator getBundleEnd(MachineBasicBlock::instr_iterator I)
Returns an iterator pointing beyond the bundle containing I.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
bool isValidOffset(unsigned Opcode, int Offset, bool Extend=true) const
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const int Hexagon_MEMB_AUTOINC_MIN
static GCRegistry::Add< ErlangGC > A("erlang","erlang-compatible garbage collector")
bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const override
Analyze the loop code, return true if it cannot be understood.
bool isConstExtended(const MachineInstr &MI) const
bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
uint64_t getType(const MachineInstr &MI) const
const int Hexagon_MEMB_OFFSET_MIN
unsigned getUnits(const MachineInstr &MI) const
bool isNewValueJump(const MachineInstr &MI) const
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const