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LLVM
4.0.0
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#include <X86InstrInfo.h>
Public Member Functions | |
| X86InstrInfo (X86Subtarget &STI) | |
| const X86RegisterInfo & | getRegisterInfo () const |
| getRegisterInfo - TargetInstrInfo is a superset of MRegister info. More... | |
| int | getSPAdjust (const MachineInstr &MI) const override |
| getSPAdjust - This returns the stack pointer adjustment made by this instruction. More... | |
| bool | isCoalescableExtInstr (const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override |
| isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. More... | |
| unsigned | isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
| unsigned | isLoadFromStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
| isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More... | |
| unsigned | isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override |
| unsigned | isStoreToStackSlotPostFE (const MachineInstr &MI, int &FrameIndex) const override |
| isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. More... | |
| bool | isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override |
| void | reMaterialize (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override |
| bool | classifyLEAReg (MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp, LiveVariables *LV) const |
| Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. More... | |
| MachineInstr * | convertToThreeAddress (MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const override |
| convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. More... | |
| bool | findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override |
| Returns true iff the routine could find two commutable operands in the given machine instruction. More... | |
| bool | findFMA3CommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const |
Returns true if the routine could find two commutable operands in the given FMA instruction MI. More... | |
| unsigned | getFMA3OpcodeToCommuteOperands (const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const |
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted. More... | |
| bool | isUnpredicatedTerminator (const MachineInstr &MI) const override |
| bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override |
| bool | getMemOpBaseRegImmOfs (MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override |
| bool | analyzeBranchPredicate (MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override |
| unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override |
| unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override |
| bool | canInsertSelect (const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, unsigned, unsigned, int &, int &, int &) const override |
| void | insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override |
| void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override |
| void | storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
| void | storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const |
| void | loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override |
| void | loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const |
| bool | expandPostRAPseudo (MachineInstr &MI) const override |
| bool | isSubregFoldable () const override |
| Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). More... | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr) const override |
| foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). More... | |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const override |
| foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot. More... | |
| bool | unfoldMemoryOperand (MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override |
| unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. More... | |
| bool | unfoldMemoryOperand (SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override |
| unsigned | getOpcodeAfterMemoryUnfold (unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override |
| getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. More... | |
| bool | areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override |
| areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. More... | |
| bool | shouldScheduleLoadsNear (SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override |
| shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. More... | |
| bool | shouldScheduleAdjacent (const MachineInstr &First, const MachineInstr &Second) const override |
| void | getNoopForMachoTarget (MCInst &NopInst) const override |
| Return the noop instruction to use for a noop. More... | |
| bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override |
| bool | isSafeToMoveRegClassDefs (const TargetRegisterClass *RC) const override |
| isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class. More... | |
| bool | isSafeToClobberEFLAGS (MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const |
| isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register. More... | |
| bool | hasLiveCondCodeDef (MachineInstr &MI) const |
| True if MI has a condition code def, e.g. More... | |
| unsigned | getGlobalBaseReg (MachineFunction *MF) const |
| getGlobalBaseReg - Return a virtual register initialized with the the global base register value. More... | |
| std::pair< uint16_t, uint16_t > | getExecutionDomain (const MachineInstr &MI) const override |
| void | setExecutionDomain (MachineInstr &MI, unsigned Domain) const override |
| unsigned | getPartialRegUpdateClearance (const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update. More... | |
| unsigned | getUndefRegClearance (const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override |
| Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register reads. More... | |
| void | breakPartialRegDependency (MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override |
| MachineInstr * | foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, unsigned Alignment, bool AllowCommute) const |
| bool | isHighLatencyDef (int opc) const override |
| bool | hasHighOperandLatency (const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override |
| bool | useMachineCombiner () const override |
| bool | isAssociativeAndCommutative (const MachineInstr &Inst) const override |
| bool | hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const override |
| void | setSpecialOperandAttr (MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override |
| This is an architecture-specific helper function of reassociateOps. More... | |
| bool | analyzeCompare (const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override |
| analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. More... | |
| bool | optimizeCompareInstr (MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override |
| optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible. More... | |
| MachineInstr * | optimizeLoadInstr (MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override |
| optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. More... | |
| std::pair< unsigned, unsigned > | decomposeMachineOperandsTargetFlags (unsigned TF) const override |
| ArrayRef< std::pair< unsigned, const char * > > | getSerializableDirectMachineOperandTargetFlags () const override |
| bool | isTailCall (const MachineInstr &Inst) const override |
Protected Member Functions | |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override |
| Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand. More... | |
Definition at line 142 of file X86InstrInfo.h.
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Definition at line 115 of file X86InstrInfo.cpp.
References E, I, llvm::X86InstrFMA3Info::rm_begin(), llvm::X86InstrFMA3Info::rm_end(), TB_ALIGN_16, TB_ALIGN_32, TB_ALIGN_64, TB_ALIGN_NONE, TB_FOLDED_LOAD, TB_FOLDED_STORE, TB_INDEX_0, TB_INDEX_1, TB_INDEX_2, TB_INDEX_3, TB_INDEX_4, and TB_NO_REVERSE.
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Definition at line 5293 of file X86InstrInfo.cpp.
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Definition at line 5302 of file X86InstrInfo.cpp.
References assert(), llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MachineOperand::CreateImm(), E, llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getNextNode(), getRegisterInfo(), I, llvm::PPC::PRED_EQ, llvm::PPC::PRED_NE, llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::rend(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::MachineBasicBlock::successors().
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analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue.
Return true if the comparison instruction can be analyzed.
Definition at line 6008 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isImm().
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areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address.
It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Definition at line 7985 of file X86InstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), and llvm::SDNode::isMachineOpcode().
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Definition at line 7408 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterKilled(), llvm::BuildMI(), contains(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MCRegisterInfo::getSubReg(), llvm::X86Subtarget::hasAVX(), llvm::RegState::ImplicitDefine, llvm::MachineInstr::killsRegister(), MI, and llvm::RegState::Undef.
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Definition at line 5455 of file X86InstrInfo.cpp.
References llvm::X86::COND_S, llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::X86Subtarget::hasCMov(), MRI, and llvm::ArrayRef< T >::size().
| bool X86InstrInfo::classifyLEAReg | ( | MachineInstr & | MI, |
| const MachineOperand & | Src, | ||
| unsigned | LEAOpcode, | ||
| bool | AllowSP, | ||
| unsigned & | NewSrc, | ||
| bool & | isKill, | ||
| bool & | isUndef, | ||
| MachineOperand & | ImplicitOp, | ||
| LiveVariables * | LV | ||
| ) | const |
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction.
This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.
Reference parameters are set to indicate how caller should add this operand to the LEA instruction.
Definition at line 3615 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::getX86SubSuperRegister(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), MI, llvm::LiveVariables::replaceKillInstruction(), llvm::MachineOperand::setImplicit(), and llvm::RegState::Undef.
Referenced by convertToThreeAddress().
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Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand.
The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands to be commuted.
Do not call this method for a non-commutable instruction or non-commutable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Definition at line 4306 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::MachineOperand::CreateImm(), getCommutedVPERMV3Opcode(), llvm::MachineInstr::getDebugLoc(), llvm::X86InstrFMA3Info::getFMA3Group(), getFMA3OpcodeToCommuteOperands(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), isCommutableVPERMV3Instruction(), llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), MI, and MRI.
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convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.
Definition at line 3791 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), assert(), llvm::BuildMI(), classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::MachineInstr::getDebugLoc(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), llvm::getUndefRegState(), hasLiveCondCodeDef(), llvm::X86Subtarget::is64Bit(), is64Bit(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isKill(), isTruncatedShiftCountForLEA(), llvm::MachineOperand::isUndef(), llvm::TargetRegisterInfo::isVirtualRegister(), MI, and llvm::LiveVariables::replaceKillInstruction().
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Definition at line 5606 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::LivePhysRegs::addLiveOuts(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineBasicBlock::computeRegisterLiveness(), llvm::LivePhysRegs::contains(), contains(), CopyToFromAsymmetricReg(), llvm::dbgs(), DEBUG, llvm::MachineBasicBlock::end(), llvm::getKillRegState(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getRegisterInfo(), llvm::X86Subtarget::hasAVX(), llvm::X86Subtarget::hasBWI(), llvm::X86Subtarget::hasLAHFSAHF(), llvm::X86Subtarget::hasVLX(), I, llvm::X86Subtarget::is64Bit(), isHReg(), llvm::MCRegAliasIterator::isValid(), llvm_unreachable, llvm::MachineBasicBlock::LQR_Dead, llvm::MachineBasicBlock::LQR_Live, llvm::MachineBasicBlock::LQR_Unknown, llvm::X86ISD::SAHF, and llvm::LivePhysRegs::stepBackward().
Referenced by tryOptimizeLEAtoMOV().
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Definition at line 9428 of file X86InstrInfo.cpp.
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Definition at line 6738 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), Expand2AddrKreg(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::getRegState(), llvm::X86Subtarget::hasAVX(), MI, llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.
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Returns true iff the routine could find two commutable operands in the given machine instruction.
The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.
For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.
Definition at line 4748 of file X86InstrInfo.cpp.
References Desc, llvm::X86II::EVEX_K, llvm::X86II::EVEX_Z, llvm::TargetInstrInfo::findCommutedOpIndices(), findFMA3CommutedOpIndices(), llvm::MachineInstr::getDesc(), llvm::X86InstrFMA3Info::getFMA3Group(), llvm::MachineOperand::getImm(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::X86Subtarget::hasSSE41(), llvm::MCInstrDesc::isCommutable(), llvm::MachineOperand::isReg(), llvm::MCOI::TIED_TO, and llvm::MCInstrDesc::TSFlags.
Referenced by foldMemoryOperandImpl().
| bool X86InstrInfo::findFMA3CommutedOpIndices | ( | const MachineInstr & | MI, |
| unsigned & | SrcOpIdx1, | ||
| unsigned & | SrcOpIdx2, | ||
| const X86InstrFMA3Group & | FMA3Group | ||
| ) | const |
Returns true if the routine could find two commutable operands in the given FMA instruction MI.
Otherwise, returns false.
SrcOpIdx1 and SrcOpIdx2 are INPUT and OUTPUT arguments. The output indices of the commuted operands are returned in these arguments. Also, the input values of these arguments may be preset either to indices of operands that must be commuted or be equal to a special value 'CommuteAnyOperandIndex' which means that the corresponding operand index is not set and this method is free to pick any of available commutable operands. The parameter FMA3Group keeps the reference to the group of relative FMA3 opcodes including register/memory forms of 132/213/231 opcodes.
For example, calling this method this way: unsigned Idx1 = 1, Idx2 = CommuteAnyOperandIndex; findFMA3CommutedOpIndices(MI, Idx1, Idx2, FMA3Group); can be interpreted as a query asking if the operand #1 can be swapped with any other available operand (e.g. operand #2, operand #3, etc.).
The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1
Definition at line 4654 of file X86InstrInfo.cpp.
References getFMA3OpcodeToCommuteOperands().
Referenced by findCommutedOpIndices().
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foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).
If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.
Definition at line 7436 of file X86InstrInfo.cpp.
References llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateFI(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::TargetFrameLowering::getStackAlignment(), llvm::MachineOperand::getSubReg(), hasPartialRegUpdate(), llvm::MachineOperand::isDef(), fuzzer::min(), NoFusing, llvm::Function::optForSize(), llvm::MachineInstr::setDesc(), and SubReg.
Referenced by foldMemoryOperandImpl().
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foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 7581 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), C, llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), foldMemoryOperandImpl(), llvm::ISD::FrameIndex, llvm::VectorType::get(), getAlignment(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::MachineInstr::hasOneMemOperand(), hasPartialRegUpdate(), llvm::X86Subtarget::is64Bit(), isLoadFromStackSlot(), isNonFoldablePartialRegisterLoad(), llvm::TargetMachine::isPositionIndependent(), llvm::CodeModel::Kernel, llvm::MachineInstr::memoperands_begin(), NoFusing, llvm::MachineInstr::operands_begin(), llvm::Function::optForSize(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), and llvm::CodeModel::Small.
| MachineInstr * X86InstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, |
| MachineInstr & | MI, | ||
| unsigned | OpNum, | ||
| ArrayRef< MachineOperand > | MOs, | ||
| MachineBasicBlock::iterator | InsertPt, | ||
| unsigned | Size, | ||
| unsigned | Alignment, | ||
| bool | AllowCommute | ||
| ) | const |
Definition at line 7000 of file X86InstrInfo.cpp.
References llvm::X86Subtarget::callRegIndirect(), llvm::dbgs(), llvm::MachineInstr::eraseFromParent(), findCommutedOpIndices(), foldMemoryOperandImpl(), FuseInst(), FuseTwoAddrInst(), llvm::MachineInstr::getDesc(), llvm::MachineFunction::getFunction(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::getTargetFlags(), llvm::MachineInstr::isCopy(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), MakeM0Inst(), MI, llvm::MinAlign(), llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::Function::optForMinSize(), PrintFailedFusing, llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), TB_ALIGN_MASK, TB_ALIGN_SHIFT, and llvm::MCOI::TIED_TO.
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Definition at line 8763 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasDQI(), lookup(), lookupAVX512(), ReplaceableInstrs, llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.
| unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands | ( | const MachineInstr & | MI, |
| unsigned | SrcOpIdx1, | ||
| unsigned | SrcOpIdx2, | ||
| const X86InstrFMA3Group & | FMA3Group | ||
| ) | const |
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted.
It may return 0 if it is unsafe to commute the operands. Note that a machine instruction (instead of its opcode) is passed as the first parameter to make it possible to analyze the instruction's uses and commute the first operand of FMA even when it seems unsafe when you look at the opcode. For example, it is Ok to commute the first operand of VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1
Definition at line 4122 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::X86InstrFMA3Group::getMem132Opcode(), llvm::X86InstrFMA3Group::getMem213Opcode(), llvm::X86InstrFMA3Group::getMem231Opcode(), llvm::MachineInstr::getOpcode(), llvm::X86InstrFMA3Group::getReg132Opcode(), llvm::X86InstrFMA3Group::getReg213Opcode(), llvm::X86InstrFMA3Group::getReg231Opcode(), getThreeSrcCommuteCase(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm::X86InstrFMA3Group::isRegOpcodeFromGroup(), std::swap(), and llvm::MCInstrDesc::TSFlags.
Referenced by commuteInstructionImpl(), and findFMA3CommutedOpIndices().
| unsigned X86InstrInfo::getGlobalBaseReg | ( | MachineFunction * | MF | ) | const |
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
Return a virtual register initialized with the the global base register value.
Output instructions required to initialize the register in the function entry block, if necessary.
Output instructions required to initialize the register in the function entry block, if necessary.
TODO: Eliminate this and move the code to X86MachineFunctionInfo.
Definition at line 8399 of file X86InstrInfo.cpp.
References assert(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::PPCISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().
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Definition at line 5888 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, Desc, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::MachineInstr::getOperand(), llvm::X86II::getOperandBias(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), and llvm::MCInstrDesc::TSFlags.
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Return the noop instruction to use for a noop.
Definition at line 8823 of file X86InstrInfo.cpp.
References llvm::MCInst::setOpcode().
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getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode.
It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Definition at line 7967 of file X86InstrInfo.cpp.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.
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Inform the ExeDepsFix pass how many idle instructions we would like before a partial register update.
Definition at line 7231 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasPartialRegUpdate(), llvm::TargetRegisterInfo::isVirtualRegister(), PartialRegUpdateClearance, llvm::MachineOperand::readsReg(), llvm::MachineInstr::readsRegister(), and llvm::MachineInstr::readsVirtualRegister().
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getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 183 of file X86InstrInfo.h.
Referenced by analyzeBranchPredicate(), copyPhysReg(), expandPostRAPseudo(), llvm::X86Subtarget::getRegisterInfo(), and optimizeCompareInstr().
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Definition at line 9433 of file X86InstrInfo.cpp.
References llvm::makeArrayRef(), llvm::X86II::MO_DARWIN_NONLAZY, llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE, llvm::ARMII::MO_DLLIMPORT, llvm::X86II::MO_DTPOFF, llvm::AArch64II::MO_GOT, llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::X86II::MO_GOTNTPOFF, llvm::X86II::MO_GOTOFF, llvm::X86II::MO_GOTPCREL, llvm::X86II::MO_GOTTPOFF, llvm::SystemZII::MO_INDNTPOFF, llvm::X86II::MO_NTPOFF, llvm::X86II::MO_PIC_BASE_OFFSET, llvm::PPCII::MO_PLT, llvm::ARMII::MO_SECREL, llvm::MipsII::MO_TLSGD, llvm::X86II::MO_TLSLD, llvm::MipsII::MO_TLSLDM, llvm::X86II::MO_TLVP, llvm::X86II::MO_TLVP_PIC_BASE, and llvm::X86II::MO_TPOFF.
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getSPAdjust - This returns the stack pointer adjustment made by this instruction.
For x86, we need to handle more complex call sequences involving PUSHes.
Definition at line 3062 of file X86InstrInfo.cpp.
References E, llvm::MachineBasicBlock::end(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::TargetFrameLowering::getStackAlignment(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineInstr::isCall(), and MBB.
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Inform the ExeDepsFix pass how many idle instructions we would like before certain undef register reads.
This catches the VCVTSI2SD family of instructions:
vcvtsi2sdq rax, xmm0<undef>, xmm14
We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:
vxorps xmm1<undef>, xmm1<undef>, xmm1
Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.
Definition at line 7393 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isUndef(), and UndefRegClearance.
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Definition at line 9137 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and isHighLatencyDef().
| bool X86InstrInfo::hasLiveCondCodeDef | ( | MachineInstr & | MI | ) | const |
True if MI has a condition code def, e.g.
True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
EFLAGS, that is not marked dead.
Definition at line 3584 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), i, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().
Referenced by convertToThreeAddress().
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Definition at line 5394 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), llvm::X86::COND_E_AND_NP, llvm::X86::COND_NE_OR_P, llvm::ArrayRef< T >::empty(), GetCondBranchFromCond(), getFallThroughMBB(), and llvm::ArrayRef< T >::size().
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Definition at line 5491 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::X86::getCMovFromCond(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getSize(), MRI, and llvm::ArrayRef< T >::size().
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Definition at line 9172 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getTarget(), llvm::TargetMachine::Options, and llvm::TargetOptions::UnsafeFPMath.
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isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 3015 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::X86Subtarget::is64Bit(), and llvm_unreachable.
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Definition at line 8827 of file X86InstrInfo.cpp.
Referenced by hasHighOperandLatency().
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Definition at line 3292 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameLoadOpcode().
Referenced by foldMemoryOperandImpl(), isLoadFromStackSlotPostFE(), and MatchingStackOffset().
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isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 3300 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameLoadOpcode(), and isLoadFromStackSlot().
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Definition at line 3352 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isDereferenceableInvariantLoad(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), MRI, regIsPICBase(), and ReMatPICStubLoad.
| bool X86InstrInfo::isSafeToClobberEFLAGS | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I | ||
| ) | const |
isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha would clobber the EFLAGS condition register.
Note the result may be conservative. If it cannot definitely determine the safety after visiting a few instructions in each direction it assumes it's not safe.
Definition at line 3468 of file X86InstrInfo.cpp.
References B, llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), E, llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), I, i, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineOperand::isUse(), and llvm::MachineBasicBlock::successors().
Referenced by reMaterialize().
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isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.
Definition at line 8386 of file X86InstrInfo.cpp.
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Definition at line 3313 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and isFrameStoreOpcode().
Referenced by isStoreToStackSlotPostFE().
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isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 3322 of file X86InstrInfo.cpp.
References llvm::NVPTXISD::Dummy, llvm::MachineInstr::getOpcode(), isFrameStoreOpcode(), and isStoreToStackSlot().
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Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).
Definition at line 376 of file X86InstrInfo.h.
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Definition at line 9460 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode().
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Definition at line 5100 of file X86InstrInfo.cpp.
References llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isPredicable(), llvm::HexagonMCInstrInfo::isPredicated(), and llvm::MachineInstr::isTerminator().
| void X86InstrInfo::loadRegFromAddr | ( | MachineFunction & | MF, |
| unsigned | DestReg, | ||
| SmallVectorImpl< MachineOperand > & | Addr, | ||
| const TargetRegisterClass * | RC, | ||
| MachineInstr::mmo_iterator | MMOBegin, | ||
| MachineInstr::mmo_iterator | MMOEnd, | ||
| SmallVectorImpl< MachineInstr * > & | NewMIs | ||
| ) | const |
Definition at line 5990 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineMemOperand::getAlignment(), getLoadRegOpcode(), llvm::TargetRegisterClass::getSize(), i, isAligned(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by unfoldMemoryOperand().
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Definition at line 5975 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::MachineBasicBlock::findDebugLoc(), llvm::X86Subtarget::getFrameLowering(), getLoadRegOpcode(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), llvm::TargetFrameLowering::getStackAlignment(), and isAligned().
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optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Definition at line 6229 of file X86InstrInfo.cpp.
References assert(), llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_O, llvm::tgtok::Def, E, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::X86::getCMovFromCond(), GetCondBranchFromCond(), getCondFromBranchOpc(), llvm::X86::getCondFromCMovOpc(), getCondFromSETOpc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), getRegisterInfo(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), llvm::X86::getSETFromCond(), llvm::TargetRegisterClass::getSize(), getSwappedCondition(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineInstr::hasOneMemOperand(), I, i, llvm::MachineBasicBlock::insert(), llvm::MachineInstr::isBranch(), llvm::MachineOperand::isDef(), isDefConvertible(), isRedundantFlagInstr(), llvm::MachineOperand::isReg(), isUseDefConvertible(), llvm::MachineInstr::killsRegister(), llvm_unreachable, MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::readsRegister(), llvm::MachineInstr::registerDefIsDead(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::RemoveOperand(), llvm::MachineBasicBlock::rend(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::Successor, llvm::MachineBasicBlock::successors(), and llvm::MachineRegisterInfo::use_nodbg_empty().
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optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
Try to remove the load by folding it to a register operand at the use.
We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
We fold the load instructions if load defines a virtual register, the virtual register is used once in the same BB, and the instructions in-between do not load or store, and have no side effects.
Definition at line 6520 of file X86InstrInfo.cpp.
References assert(), llvm::SmallVectorBase::empty(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), i, llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isSafeToMove(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), and SawStore.
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Definition at line 3545 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), isSafeToClobberEFLAGS(), llvm_unreachable, llvm::MachineInstr::operands(), and llvm::MachineInstr::substituteRegister().
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Definition at line 5371 of file X86InstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), llvm::X86::COND_INVALID, llvm::MachineBasicBlock::end(), getCondFromBranchOpc(), and I.
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Definition at line 8378 of file X86InstrInfo.cpp.
References assert(), GetOppositeBranchCondition(), and llvm::SmallVectorTemplateCommon< T >::size().
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Definition at line 8787 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasAVX512(), llvm::X86Subtarget::hasDQI(), lookup(), lookupAVX512(), ReplaceableInstrs, ReplaceableInstrsAVX2, ReplaceableInstrsAVX512, ReplaceableInstrsAVX512DQ, ReplaceableInstrsAVX512DQMasked, llvm::MachineInstr::setDesc(), llvm::X86II::SSEDomainShift, and llvm::MCInstrDesc::TSFlags.
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This is an architecture-specific helper function of reassociateOps.
Set special operand attributes for new instructions after reassociation.
Definition at line 9389 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::setIsDead().
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Definition at line 8218 of file X86InstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), and llvm::X86Subtarget::hasAVX().
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shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 8170 of file X86InstrInfo.cpp.
References assert(), llvm::MVT::f32, llvm::MVT::f64, llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), and llvm::MVT::SimpleTy.
| void X86InstrInfo::storeRegToAddr | ( | MachineFunction & | MF, |
| unsigned | SrcReg, | ||
| bool | isKill, | ||
| SmallVectorImpl< MachineOperand > & | Addr, | ||
| const TargetRegisterClass * | RC, | ||
| MachineInstr::mmo_iterator | MMOBegin, | ||
| MachineInstr::mmo_iterator | MMOEnd, | ||
| SmallVectorImpl< MachineInstr * > & | NewMIs | ||
| ) | const |
Definition at line 5954 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineMemOperand::getAlignment(), llvm::getKillRegState(), llvm::TargetRegisterClass::getSize(), getStoreRegOpcode(), i, isAligned(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstrBuilder::setMemRefs(), and llvm::SmallVectorTemplateCommon< T >::size().
Referenced by unfoldMemoryOperand().
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Definition at line 5936 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::getKillRegState(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetRegisterClass::getSize(), llvm::TargetFrameLowering::getStackAlignment(), getStoreRegOpcode(), and isAligned().
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unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction.
If this is possible, returns true as well as the new instructions by reference.
Definition at line 7739 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, llvm::MachineOperand::ChangeToRegister(), llvm::MachineFunction::CreateMachineInstr(), llvm::RegState::Define, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineFunction::extractLoadMemRefs(), llvm::MachineFunction::extractStoreMemRefs(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::getUndefRegState(), llvm::MachineInstr::hasOneMemOperand(), i, llvm::RegState::Implicit, llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isReg(), llvm::X86Subtarget::isUnalignedMem16Slow(), llvm_unreachable, loadRegFromAddr(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), storeRegToAddr(), TB_FOLDED_LOAD, TB_FOLDED_STORE, and TB_INDEX_MASK.
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Definition at line 7859 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineFunction::extractLoadMemRefs(), llvm::MachineFunction::extractStoreMemRefs(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SDNode::getMachineOpcode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOperand(), getRegClass(), llvm::TargetRegisterClass::getSize(), getStoreRegOpcode(), llvm::SDNode::getValueType(), i, isAligned(), llvm::SDNode::isMachineOpcode(), llvm::X86Subtarget::isUnalignedMem16Slow(), llvm::SPII::Load, llvm::MCInstrDesc::NumDefs, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::SPII::Store, TB_FOLDED_LOAD, TB_FOLDED_STORE, TB_INDEX_MASK, and llvm::TargetRegisterClass::vt_begin().
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Definition at line 496 of file X86InstrInfo.h.
1.8.6