30 const HexagonMCChecker::PredSense
31 HexagonMCChecker::Unconditional(Hexagon::NoRegister,
false);
33 void HexagonMCChecker::init() {
39 Defs[Hexagon::SA0].
insert(Unconditional);
40 Defs[Hexagon::LC0].
insert(Unconditional);
43 Defs[Hexagon::SA1].
insert(Unconditional);
44 Defs[Hexagon::LC1].
insert(Unconditional);
56 void HexagonMCChecker::init(
MCInst const& MCI) {
58 unsigned PredReg = Hexagon::NoRegister;
73 NewPreds.insert(PredReg);
88 for (; *ImpDef; ++ImpDef) {
91 if (Hexagon::R31 != R && MCID.
isCall())
100 if (Hexagon::USR_OVF == R)
107 else if (isPredicateRegister(R) &&
112 Defs[R].
insert(PredSense(PredReg, isTrue));
118 S = Hexagon::NoRegister;
122 if (R == Hexagon::C8)
143 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
148 SoftDefs.insert(*SRI);
151 LatePreds.insert(*SRI);
156 CurDefs.insert(*SRI), Defs[*SRI].
insert(PredSense(PredReg, isTrue));
163 TmpDefs.insert(*SRI);
169 Defs[*SRI].
insert(PredSense(PredReg, isTrue));
178 compoundRegisterMap(R);
208 if (isPredicateRegister(P))
228 : MCB(mcb), MCBDX(mcbdx), RI(ri), MCII(MCII), STI(STI),
229 bLoadErrInfo(
false) {
234 bool chkB = checkBranches();
235 bool chkP = checkPredicates();
236 bool chkNV = checkNewValues();
237 bool chkR = checkRegisters();
238 bool chkS = checkSolo();
239 bool chkSh = checkShuffle();
240 bool chkSl = checkSlots();
241 bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl;
246 bool HexagonMCChecker::checkSlots()
249 unsigned slotsUsed = 0;
251 MCInst const& MCI = *HMI.getInst();
270 bool HexagonMCChecker::checkBranches() {
273 bool hasConditional =
false;
274 unsigned Branches = 0, Returns = 0, NewIndirectBranches = 0,
289 ++NewIndirectBranches;
295 hasConditional =
true;
315 if (!hasConditional || Conditional > Unconditional) {
328 bool HexagonMCChecker::checkPredicates() {
331 for (
const auto&
I : NewPreds) {
334 if (!Defs.
count(P) || LatePreds.count(P)) {
345 for (
const auto&
I : LatePreds) {
348 if (LatePreds.count(P) > 1 || Defs.
count(P)) {
362 bool HexagonMCChecker::checkNewValues() {
364 memset(&errInfo, 0,
sizeof(errInfo));
365 for (
auto&
I : NewUses) {
366 unsigned R =
I.first;
367 NewSense &US =
I.second;
369 if (!hasValidNewValueDef(US, NewDefs[R])) {
380 bool HexagonMCChecker::checkRegisters() {
383 for (
const auto&
I : Defs) {
384 unsigned R =
I.first;
386 if (ReadOnly.count(R)) {
392 if (isLoopRegister(R) && Defs.count(R) > 1 &&
400 if (SoftDefs.count(R)) {
403 unsigned UsrR = Hexagon::USR;
404 unsigned BadR = RI.
isSubRegister(Hexagon::USR, R) ? UsrR : R;
409 if (!isPredicateRegister(R) && Defs[R].size() > 1) {
411 PredSet &PM = Defs[R];
414 if (PM.count(Unconditional)) {
417 unsigned UsrR = Hexagon::USR;
418 unsigned BadR = RI.
isSubRegister(Hexagon::USR, R) ? UsrR : R;
424 for (
const auto& J : PM) {
428 if (PM.count(P) > 1) {
436 P.second = !P.second;
437 if (PM.count(P) && PM.size() > 2) {
450 for (
const auto&
I : CurDefs) {
453 if (!Uses.count(R)) {
462 for (
const auto&
I : TmpDefs) {
465 if (!Uses.count(R)) {
467 bool vHistFound =
false;
475 if (vHistFound ==
false) {
487 bool HexagonMCChecker::checkSolo() {
503 bool HexagonMCChecker::checkShuffle() {
517 if (!MCSDX.check()) {
526 void HexagonMCChecker::compoundRegisterMap(
unsigned&
Register) {
531 Register = Hexagon::R23;
534 Register = Hexagon::R22;
537 Register = Hexagon::R21;
540 Register = Hexagon::R20;
543 Register = Hexagon::R19;
546 Register = Hexagon::R18;
549 Register = Hexagon::R17;
552 Register = Hexagon::R16;
557 bool HexagonMCChecker::hasValidNewValueDef(
const NewSense &
Use,
558 const NewSenseList &Defs)
const {
561 for (
unsigned i = 0, n = Defs.size();
i < n; ++
i) {
562 const NewSense &
Def = Defs[
i];
564 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0))
568 if (Def.PredReg == 0)
573 if (Def.PredReg == Use.PredReg && Def.Cond == Use.Cond)
579 if (Def.PredReg != Use.PredReg || Def.Cond == Use.Cond)
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, MCInst &mcbdx, const MCRegisterInfo &ri)
Describe properties that are true of each instruction in the target description file.
void setWarning(unsigned w, unsigned r=Hexagon::NoRegister)
bool isBundle(MCInst const &MCI)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn is newly predicated.
bool isSubRegister(unsigned RegA, unsigned RegB) const
Returns true if RegB is a sub-register of RegA.
bool isOuterLoop(MCInst const &MCI)
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
bool isImmext(MCInst const &MCI)
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
A Use represents the edge between a Value definition and its users.
#define HEXAGON_PACKET_SIZE
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
bool isCall() const
Return true if the instruction is a call.
void addErrInfo(HexagonMCErrInfo &err)
add a new error/warning
No free slots for branch insns.
unsigned getReg() const
Returns the register number.
Function Alias Analysis false
const MCPhysReg * getImplicitDefs() const
Return a list of registers that are potentially written by any instance of this machine instruction...
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
initializer< Ty > init(const Ty &Val)
bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI)
Interface to description of machine instruction set.
static cl::opt< bool > RelaxNVChecks("relax-nv-checks", cl::init(false), cl::ZeroOrMore, cl::Hidden, cl::desc("Relax checks of new-value validity"))
MCRegAliasIterator enumerates all registers aliasing Reg.
iterator_range< MCInst::const_iterator > bundleInstructions(MCInst const &MCI)
MCSubRegIterator enumerates all sub-registers of Reg.
size_t const bundleInstructionsOffset
Promote Memory to Register
INITIALIZE_PASS(HexagonGenMux,"hexagon-mux","Hexagon generate mux instructions", false, false) void HexagonGenMux I isValid()
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI)
MCSubtargetInfo - Generic base class for all target subtargets.
#define HEXAGON_PRESHUFFLE_PACKET_SIZE
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
size_t bundleSize(MCInst const &MCI)
void setShuffleError(unsigned e)
bool isInnerLoop(MCInst const &MCI)
static bool isBranch(unsigned Opcode)
bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether it is a floating-point insn.
bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI)
void setError(unsigned e, unsigned r=Hexagon::NoRegister)
const MCOperand & getOperand(unsigned i) const
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)