40 #define DEBUG_TYPE "mips-reg-info"
57 return &Mips::GPR32RegClass;
60 return &Mips::GPR64RegClass;
106 switch (ConstraintID) {
149 int64_t SPOffset)
const {
165 MinCSFI = CSI[0].getFrameIdx();
166 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
170 bool IsISRRegFI = MipsFI->
isISRRegFI(FrameIndex);
181 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
183 FrameReg = ABI.GetStackPtr();
184 else if (RegInfo->needsStackRealignment(MF)) {
186 FrameReg = ABI.GetBasePtr();
190 FrameReg = ABI.GetStackPtr();
204 Offset = SPOffset + (int64_t)StackSize;
207 DEBUG(
errs() <<
"Offset : " << Offset <<
"\n" <<
"<--------->\n");
213 unsigned OffsetBitSize =
217 if (OffsetBitSize < 16 &&
isInt<16>(Offset) &&
218 (!
isIntN(OffsetBitSize, Offset) ||
225 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
231 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
248 OffsetBitSize == 16 ? &NewImm :
nullptr);
249 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).
addReg(FrameReg)
253 Offset = SignExtend64<16>(NewImm);
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
raw_ostream & errs()
This returns a reference to a raw_ostream for standard error.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getFrameRegister(const MachineFunction &MF) const override
Debug information queries.
constexpr bool isInt< 16 >(int64_t x)
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
INLINEASM - Represents an inline asm block.
bool requiresRegisterScavenging(const MachineFunction &MF) const override
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
const MachineBasicBlock * getParent() const
bool isDebugValue() const
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const MachineOperand & getOperand(unsigned i) const
static unsigned getMemoryConstraintID(unsigned Flag)
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool inMicroMipsMode() const
bool isIntN(unsigned N, int64_t x)
isIntN - Checks if an signed integer fits into the given (dynamic) bit width.
bool isISRRegFI(int FI) const
bool isEhDataRegFI(int FI) const
MachineOperand class - Representation of each machine instruction operand.
const TargetRegisterClass * intRegClass(unsigned Size) const override
Return GPR register class.
CHAIN = SC CHAIN, Imm128 - System call.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
virtual const TargetInstrInfo * getInstrInfo() const
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
uint64_t OffsetToAlignment(uint64_t Value, uint64_t Align)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
static unsigned getLoadStoreOffsetAlign(const unsigned Opcode)
Get the scale factor applied to the immediate in the given load/store.
static unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode, MachineOperand MO)
Get the size of the offset supported by the given load/store/inline asm.
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override