clang  7.0.0
TargetInfo.cpp
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1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "TargetInfo.h"
16 #include "ABIInfo.h"
17 #include "CGBlocks.h"
18 #include "CGCXXABI.h"
19 #include "CGValue.h"
20 #include "CodeGenFunction.h"
21 #include "clang/AST/RecordLayout.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <algorithm> // std::sort
33 
34 using namespace clang;
35 using namespace CodeGen;
36 
37 // Helper for coercing an aggregate argument or return value into an integer
38 // array of the same size (including padding) and alignment. This alternate
39 // coercion happens only for the RenderScript ABI and can be removed after
40 // runtimes that rely on it are no longer supported.
41 //
42 // RenderScript assumes that the size of the argument / return value in the IR
43 // is the same as the size of the corresponding qualified type. This helper
44 // coerces the aggregate type into an array of the same size (including
45 // padding). This coercion is used in lieu of expansion of struct members or
46 // other canonical coercions that return a coerced-type of larger size.
47 //
48 // Ty - The argument / return value type
49 // Context - The associated ASTContext
50 // LLVMContext - The associated LLVMContext
52  ASTContext &Context,
53  llvm::LLVMContext &LLVMContext) {
54  // Alignment and Size are measured in bits.
55  const uint64_t Size = Context.getTypeSize(Ty);
56  const uint64_t Alignment = Context.getTypeAlign(Ty);
57  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
58  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
59  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
60 }
61 
63  llvm::Value *Array,
65  unsigned FirstIndex,
66  unsigned LastIndex) {
67  // Alternatively, we could emit this as a loop in the source.
68  for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
69  llvm::Value *Cell =
70  Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
71  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
72  }
73 }
74 
78 }
79 
81 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
82  llvm::Type *Padding) const {
83  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
84  ByRef, Realign, Padding);
85 }
86 
89  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
90  /*ByRef*/ false, Realign);
91 }
92 
94  QualType Ty) const {
95  return Address::invalid();
96 }
97 
99 
100 /// Does the given lowering require more than the given number of
101 /// registers when expanded?
102 ///
103 /// This is intended to be the basis of a reasonable basic implementation
104 /// of should{Pass,Return}IndirectlyForSwift.
105 ///
106 /// For most targets, a limit of four total registers is reasonable; this
107 /// limits the amount of code required in order to move around the value
108 /// in case it wasn't produced immediately prior to the call by the caller
109 /// (or wasn't produced in exactly the right registers) or isn't used
110 /// immediately within the callee. But some targets may need to further
111 /// limit the register count due to an inability to support that many
112 /// return registers.
114  ArrayRef<llvm::Type*> scalarTypes,
115  unsigned maxAllRegisters) {
116  unsigned intCount = 0, fpCount = 0;
117  for (llvm::Type *type : scalarTypes) {
118  if (type->isPointerTy()) {
119  intCount++;
120  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
121  auto ptrWidth = cgt.getTarget().getPointerWidth(0);
122  intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
123  } else {
124  assert(type->isVectorTy() || type->isFloatingPointTy());
125  fpCount++;
126  }
127  }
128 
129  return (intCount + fpCount > maxAllRegisters);
130 }
131 
133  llvm::Type *eltTy,
134  unsigned numElts) const {
135  // The default implementation of this assumes that the target guarantees
136  // 128-bit SIMD support but nothing more.
137  return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
138 }
139 
141  CGCXXABI &CXXABI) {
142  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
143  if (!RD) {
144  if (!RT->getDecl()->canPassInRegisters())
145  return CGCXXABI::RAA_Indirect;
146  return CGCXXABI::RAA_Default;
147  }
148  return CXXABI.getRecordArgABI(RD);
149 }
150 
152  CGCXXABI &CXXABI) {
153  const RecordType *RT = T->getAs<RecordType>();
154  if (!RT)
155  return CGCXXABI::RAA_Default;
156  return getRecordArgABI(RT, CXXABI);
157 }
158 
160  const ABIInfo &Info) {
161  QualType Ty = FI.getReturnType();
162 
163  if (const auto *RT = Ty->getAs<RecordType>())
164  if (!isa<CXXRecordDecl>(RT->getDecl()) &&
165  !RT->getDecl()->canPassInRegisters()) {
166  FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
167  return true;
168  }
169 
170  return CXXABI.classifyReturnType(FI);
171 }
172 
173 /// Pass transparent unions as if they were the type of the first element. Sema
174 /// should ensure that all elements of the union have the same "machine type".
176  if (const RecordType *UT = Ty->getAsUnionType()) {
177  const RecordDecl *UD = UT->getDecl();
178  if (UD->hasAttr<TransparentUnionAttr>()) {
179  assert(!UD->field_empty() && "sema created an empty transparent union");
180  return UD->field_begin()->getType();
181  }
182  }
183  return Ty;
184 }
185 
187  return CGT.getCXXABI();
188 }
189 
191  return CGT.getContext();
192 }
193 
194 llvm::LLVMContext &ABIInfo::getVMContext() const {
195  return CGT.getLLVMContext();
196 }
197 
198 const llvm::DataLayout &ABIInfo::getDataLayout() const {
199  return CGT.getDataLayout();
200 }
201 
203  return CGT.getTarget();
204 }
205 
207  return CGT.getCodeGenOpts();
208 }
209 
210 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
211 
213  return false;
214 }
215 
217  uint64_t Members) const {
218  return false;
219 }
220 
221 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
222  raw_ostream &OS = llvm::errs();
223  OS << "(ABIArgInfo Kind=";
224  switch (TheKind) {
225  case Direct:
226  OS << "Direct Type=";
227  if (llvm::Type *Ty = getCoerceToType())
228  Ty->print(OS);
229  else
230  OS << "null";
231  break;
232  case Extend:
233  OS << "Extend";
234  break;
235  case Ignore:
236  OS << "Ignore";
237  break;
238  case InAlloca:
239  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
240  break;
241  case Indirect:
242  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
243  << " ByVal=" << getIndirectByVal()
244  << " Realign=" << getIndirectRealign();
245  break;
246  case Expand:
247  OS << "Expand";
248  break;
249  case CoerceAndExpand:
250  OS << "CoerceAndExpand Type=";
251  getCoerceAndExpandType()->print(OS);
252  break;
253  }
254  OS << ")\n";
255 }
256 
257 // Dynamically round a pointer up to a multiple of the given alignment.
259  llvm::Value *Ptr,
260  CharUnits Align) {
261  llvm::Value *PtrAsInt = Ptr;
262  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
263  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
264  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
265  llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
266  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
267  llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
268  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
269  Ptr->getType(),
270  Ptr->getName() + ".aligned");
271  return PtrAsInt;
272 }
273 
274 /// Emit va_arg for a platform using the common void* representation,
275 /// where arguments are simply emitted in an array of slots on the stack.
276 ///
277 /// This version implements the core direct-value passing rules.
278 ///
279 /// \param SlotSize - The size and alignment of a stack slot.
280 /// Each argument will be allocated to a multiple of this number of
281 /// slots, and all the slots will be aligned to this value.
282 /// \param AllowHigherAlign - The slot alignment is not a cap;
283 /// an argument type with an alignment greater than the slot size
284 /// will be emitted on a higher-alignment address, potentially
285 /// leaving one or more empty slots behind as padding. If this
286 /// is false, the returned address might be less-aligned than
287 /// DirectAlign.
289  Address VAListAddr,
290  llvm::Type *DirectTy,
291  CharUnits DirectSize,
292  CharUnits DirectAlign,
293  CharUnits SlotSize,
294  bool AllowHigherAlign) {
295  // Cast the element type to i8* if necessary. Some platforms define
296  // va_list as a struct containing an i8* instead of just an i8*.
297  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
298  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
299 
300  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
301 
302  // If the CC aligns values higher than the slot size, do so if needed.
303  Address Addr = Address::invalid();
304  if (AllowHigherAlign && DirectAlign > SlotSize) {
305  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
306  DirectAlign);
307  } else {
308  Addr = Address(Ptr, SlotSize);
309  }
310 
311  // Advance the pointer past the argument, then store that back.
312  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
313  llvm::Value *NextPtr =
314  CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
315  "argp.next");
316  CGF.Builder.CreateStore(NextPtr, VAListAddr);
317 
318  // If the argument is smaller than a slot, and this is a big-endian
319  // target, the argument will be right-adjusted in its slot.
320  if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
321  !DirectTy->isStructTy()) {
322  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
323  }
324 
325  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
326  return Addr;
327 }
328 
329 /// Emit va_arg for a platform using the common void* representation,
330 /// where arguments are simply emitted in an array of slots on the stack.
331 ///
332 /// \param IsIndirect - Values of this type are passed indirectly.
333 /// \param ValueInfo - The size and alignment of this type, generally
334 /// computed with getContext().getTypeInfoInChars(ValueTy).
335 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
336 /// Each argument will be allocated to a multiple of this number of
337 /// slots, and all the slots will be aligned to this value.
338 /// \param AllowHigherAlign - The slot alignment is not a cap;
339 /// an argument type with an alignment greater than the slot size
340 /// will be emitted on a higher-alignment address, potentially
341 /// leaving one or more empty slots behind as padding.
343  QualType ValueTy, bool IsIndirect,
344  std::pair<CharUnits, CharUnits> ValueInfo,
345  CharUnits SlotSizeAndAlign,
346  bool AllowHigherAlign) {
347  // The size and alignment of the value that was passed directly.
348  CharUnits DirectSize, DirectAlign;
349  if (IsIndirect) {
350  DirectSize = CGF.getPointerSize();
351  DirectAlign = CGF.getPointerAlign();
352  } else {
353  DirectSize = ValueInfo.first;
354  DirectAlign = ValueInfo.second;
355  }
356 
357  // Cast the address we've calculated to the right type.
358  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
359  if (IsIndirect)
360  DirectTy = DirectTy->getPointerTo(0);
361 
362  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
363  DirectSize, DirectAlign,
364  SlotSizeAndAlign,
365  AllowHigherAlign);
366 
367  if (IsIndirect) {
368  Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
369  }
370 
371  return Addr;
372 
373 }
374 
376  Address Addr1, llvm::BasicBlock *Block1,
377  Address Addr2, llvm::BasicBlock *Block2,
378  const llvm::Twine &Name = "") {
379  assert(Addr1.getType() == Addr2.getType());
380  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
381  PHI->addIncoming(Addr1.getPointer(), Block1);
382  PHI->addIncoming(Addr2.getPointer(), Block2);
383  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
384  return Address(PHI, Align);
385 }
386 
388 
389 // If someone can figure out a general rule for this, that would be great.
390 // It's probably just doomed to be platform-dependent, though.
392  // Verified for:
393  // x86-64 FreeBSD, Linux, Darwin
394  // x86-32 FreeBSD, Linux, Darwin
395  // PowerPC Linux, Darwin
396  // ARM Darwin (*not* EABI)
397  // AArch64 Linux
398  return 32;
399 }
400 
402  const FunctionNoProtoType *fnType) const {
403  // The following conventions are known to require this to be false:
404  // x86_stdcall
405  // MIPS
406  // For everything else, we just prefer false unless we opt out.
407  return false;
408 }
409 
410 void
412  llvm::SmallString<24> &Opt) const {
413  // This assumes the user is passing a library name like "rt" instead of a
414  // filename like "librt.a/so", and that they don't care whether it's static or
415  // dynamic.
416  Opt = "-l";
417  Opt += Lib;
418 }
419 
421  // OpenCL kernels are called via an explicit runtime API with arguments
422  // set with clSetKernelArg(), not as normal sub-functions.
423  // Return SPIR_KERNEL by default as the kernel calling convention to
424  // ensure the fingerprint is fixed such way that each OpenCL argument
425  // gets one matching argument in the produced kernel function argument
426  // list to enable feasible implementation of clSetKernelArg() with
427  // aggregates etc. In case we would use the default C calling conv here,
428  // clSetKernelArg() might break depending on the target-specific
429  // conventions; different targets might split structs passed as values
430  // to multiple function arguments etc.
431  return llvm::CallingConv::SPIR_KERNEL;
432 }
433 
435  llvm::PointerType *T, QualType QT) const {
436  return llvm::ConstantPointerNull::get(T);
437 }
438 
440  const VarDecl *D) const {
441  assert(!CGM.getLangOpts().OpenCL &&
442  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
443  "Address space agnostic languages only");
444  return D ? D->getType().getAddressSpace() : LangAS::Default;
445 }
446 
448  CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
449  LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
450  // Since target may map different address spaces in AST to the same address
451  // space, an address space conversion may end up as a bitcast.
452  if (auto *C = dyn_cast<llvm::Constant>(Src))
453  return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
454  return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
455 }
456 
457 llvm::Constant *
459  LangAS SrcAddr, LangAS DestAddr,
460  llvm::Type *DestTy) const {
461  // Since target may map different address spaces in AST to the same address
462  // space, an address space conversion may end up as a bitcast.
463  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
464 }
465 
467 TargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const {
468  return C.getOrInsertSyncScopeID(""); /* default sync scope */
469 }
470 
471 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
472 
473 /// isEmptyField - Return true iff a the field is "empty", that is it
474 /// is an unnamed bit-field or an (array of) empty record(s).
475 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
476  bool AllowArrays) {
477  if (FD->isUnnamedBitfield())
478  return true;
479 
480  QualType FT = FD->getType();
481 
482  // Constant arrays of empty records count as empty, strip them off.
483  // Constant arrays of zero length always count as empty.
484  if (AllowArrays)
485  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
486  if (AT->getSize() == 0)
487  return true;
488  FT = AT->getElementType();
489  }
490 
491  const RecordType *RT = FT->getAs<RecordType>();
492  if (!RT)
493  return false;
494 
495  // C++ record fields are never empty, at least in the Itanium ABI.
496  //
497  // FIXME: We should use a predicate for whether this behavior is true in the
498  // current ABI.
499  if (isa<CXXRecordDecl>(RT->getDecl()))
500  return false;
501 
502  return isEmptyRecord(Context, FT, AllowArrays);
503 }
504 
505 /// isEmptyRecord - Return true iff a structure contains only empty
506 /// fields. Note that a structure with a flexible array member is not
507 /// considered empty.
508 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
509  const RecordType *RT = T->getAs<RecordType>();
510  if (!RT)
511  return false;
512  const RecordDecl *RD = RT->getDecl();
513  if (RD->hasFlexibleArrayMember())
514  return false;
515 
516  // If this is a C++ record, check the bases first.
517  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
518  for (const auto &I : CXXRD->bases())
519  if (!isEmptyRecord(Context, I.getType(), true))
520  return false;
521 
522  for (const auto *I : RD->fields())
523  if (!isEmptyField(Context, I, AllowArrays))
524  return false;
525  return true;
526 }
527 
528 /// isSingleElementStruct - Determine if a structure is a "single
529 /// element struct", i.e. it has exactly one non-empty field or
530 /// exactly one field which is itself a single element
531 /// struct. Structures with flexible array members are never
532 /// considered single element structs.
533 ///
534 /// \return The field declaration for the single non-empty field, if
535 /// it exists.
536 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
537  const RecordType *RT = T->getAs<RecordType>();
538  if (!RT)
539  return nullptr;
540 
541  const RecordDecl *RD = RT->getDecl();
542  if (RD->hasFlexibleArrayMember())
543  return nullptr;
544 
545  const Type *Found = nullptr;
546 
547  // If this is a C++ record, check the bases first.
548  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
549  for (const auto &I : CXXRD->bases()) {
550  // Ignore empty records.
551  if (isEmptyRecord(Context, I.getType(), true))
552  continue;
553 
554  // If we already found an element then this isn't a single-element struct.
555  if (Found)
556  return nullptr;
557 
558  // If this is non-empty and not a single element struct, the composite
559  // cannot be a single element struct.
560  Found = isSingleElementStruct(I.getType(), Context);
561  if (!Found)
562  return nullptr;
563  }
564  }
565 
566  // Check for single element.
567  for (const auto *FD : RD->fields()) {
568  QualType FT = FD->getType();
569 
570  // Ignore empty fields.
571  if (isEmptyField(Context, FD, true))
572  continue;
573 
574  // If we already found an element then this isn't a single-element
575  // struct.
576  if (Found)
577  return nullptr;
578 
579  // Treat single element arrays as the element.
580  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
581  if (AT->getSize().getZExtValue() != 1)
582  break;
583  FT = AT->getElementType();
584  }
585 
586  if (!isAggregateTypeForABI(FT)) {
587  Found = FT.getTypePtr();
588  } else {
589  Found = isSingleElementStruct(FT, Context);
590  if (!Found)
591  return nullptr;
592  }
593  }
594 
595  // We don't consider a struct a single-element struct if it has
596  // padding beyond the element type.
597  if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
598  return nullptr;
599 
600  return Found;
601 }
602 
603 namespace {
604 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
605  const ABIArgInfo &AI) {
606  // This default implementation defers to the llvm backend's va_arg
607  // instruction. It can handle only passing arguments directly
608  // (typically only handled in the backend for primitive types), or
609  // aggregates passed indirectly by pointer (NOTE: if the "byval"
610  // flag has ABI impact in the callee, this implementation cannot
611  // work.)
612 
613  // Only a few cases are covered here at the moment -- those needed
614  // by the default abi.
615  llvm::Value *Val;
616 
617  if (AI.isIndirect()) {
618  assert(!AI.getPaddingType() &&
619  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
620  assert(
621  !AI.getIndirectRealign() &&
622  "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
623 
624  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
625  CharUnits TyAlignForABI = TyInfo.second;
626 
627  llvm::Type *BaseTy =
628  llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
629  llvm::Value *Addr =
630  CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
631  return Address(Addr, TyAlignForABI);
632  } else {
633  assert((AI.isDirect() || AI.isExtend()) &&
634  "Unexpected ArgInfo Kind in generic VAArg emitter!");
635 
636  assert(!AI.getInReg() &&
637  "Unexpected InReg seen in arginfo in generic VAArg emitter!");
638  assert(!AI.getPaddingType() &&
639  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
640  assert(!AI.getDirectOffset() &&
641  "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
642  assert(!AI.getCoerceToType() &&
643  "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
644 
645  Address Temp = CGF.CreateMemTemp(Ty, "varet");
646  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
647  CGF.Builder.CreateStore(Val, Temp);
648  return Temp;
649  }
650 }
651 
652 /// DefaultABIInfo - The default implementation for ABI specific
653 /// details. This implementation provides information which results in
654 /// self-consistent and sensible LLVM IR generation, but does not
655 /// conform to any particular ABI.
656 class DefaultABIInfo : public ABIInfo {
657 public:
658  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
659 
662 
663  void computeInfo(CGFunctionInfo &FI) const override {
664  if (!getCXXABI().classifyReturnType(FI))
666  for (auto &I : FI.arguments())
667  I.info = classifyArgumentType(I.type);
668  }
669 
670  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
671  QualType Ty) const override {
672  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
673  }
674 };
675 
676 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
677 public:
678  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
679  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
680 };
681 
684 
685  if (isAggregateTypeForABI(Ty)) {
686  // Records with non-trivial destructors/copy-constructors should not be
687  // passed by value.
690 
691  return getNaturalAlignIndirect(Ty);
692  }
693 
694  // Treat an enum type as its underlying type.
695  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
696  Ty = EnumTy->getDecl()->getIntegerType();
697 
700 }
701 
703  if (RetTy->isVoidType())
704  return ABIArgInfo::getIgnore();
705 
706  if (isAggregateTypeForABI(RetTy))
707  return getNaturalAlignIndirect(RetTy);
708 
709  // Treat an enum type as its underlying type.
710  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
711  RetTy = EnumTy->getDecl()->getIntegerType();
712 
713  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
715 }
716 
717 //===----------------------------------------------------------------------===//
718 // WebAssembly ABI Implementation
719 //
720 // This is a very simple ABI that relies a lot on DefaultABIInfo.
721 //===----------------------------------------------------------------------===//
722 
723 class WebAssemblyABIInfo final : public DefaultABIInfo {
724 public:
725  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
726  : DefaultABIInfo(CGT) {}
727 
728 private:
731 
732  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
733  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
734  // overload them.
735  void computeInfo(CGFunctionInfo &FI) const override {
736  if (!getCXXABI().classifyReturnType(FI))
738  for (auto &Arg : FI.arguments())
739  Arg.info = classifyArgumentType(Arg.type);
740  }
741 
742  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
743  QualType Ty) const override;
744 };
745 
746 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
747 public:
748  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
749  : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
750 
751  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
752  CodeGen::CodeGenModule &CGM) const override {
753  if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
754  llvm::Function *Fn = cast<llvm::Function>(GV);
755  if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype())
756  Fn->addFnAttr("no-prototype");
757  }
758  }
759 };
760 
761 /// Classify argument of given type \p Ty.
764 
765  if (isAggregateTypeForABI(Ty)) {
766  // Records with non-trivial destructors/copy-constructors should not be
767  // passed by value.
768  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
770  // Ignore empty structs/unions.
771  if (isEmptyRecord(getContext(), Ty, true))
772  return ABIArgInfo::getIgnore();
773  // Lower single-element structs to just pass a regular value. TODO: We
774  // could do reasonable-size multiple-element structs too, using getExpand(),
775  // though watch out for things like bitfields.
776  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
777  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
778  }
779 
780  // Otherwise just do the default thing.
782 }
783 
785  if (isAggregateTypeForABI(RetTy)) {
786  // Records with non-trivial destructors/copy-constructors should not be
787  // returned by value.
788  if (!getRecordArgABI(RetTy, getCXXABI())) {
789  // Ignore empty structs/unions.
790  if (isEmptyRecord(getContext(), RetTy, true))
791  return ABIArgInfo::getIgnore();
792  // Lower single-element structs to just return a regular value. TODO: We
793  // could do reasonable-size multiple-element structs too, using
794  // ABIArgInfo::getDirect().
795  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
796  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
797  }
798  }
799 
800  // Otherwise just do the default thing.
802 }
803 
804 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
805  QualType Ty) const {
806  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
807  getContext().getTypeInfoInChars(Ty),
809  /*AllowHigherAlign=*/ true);
810 }
811 
812 //===----------------------------------------------------------------------===//
813 // le32/PNaCl bitcode ABI Implementation
814 //
815 // This is a simplified version of the x86_32 ABI. Arguments and return values
816 // are always passed on the stack.
817 //===----------------------------------------------------------------------===//
818 
819 class PNaClABIInfo : public ABIInfo {
820  public:
821  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
822 
825 
826  void computeInfo(CGFunctionInfo &FI) const override;
828  Address VAListAddr, QualType Ty) const override;
829 };
830 
831 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
832  public:
833  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
834  : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
835 };
836 
837 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
838  if (!getCXXABI().classifyReturnType(FI))
840 
841  for (auto &I : FI.arguments())
842  I.info = classifyArgumentType(I.type);
843 }
844 
845 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
846  QualType Ty) const {
847  // The PNaCL ABI is a bit odd, in that varargs don't use normal
848  // function classification. Structs get passed directly for varargs
849  // functions, through a rewriting transform in
850  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
851  // this target to actually support a va_arg instructions with an
852  // aggregate type, unlike other targets.
853  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
854 }
855 
856 /// Classify argument of given type \p Ty.
858  if (isAggregateTypeForABI(Ty)) {
861  return getNaturalAlignIndirect(Ty);
862  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
863  // Treat an enum type as its underlying type.
864  Ty = EnumTy->getDecl()->getIntegerType();
865  } else if (Ty->isFloatingType()) {
866  // Floating-point types don't go inreg.
867  return ABIArgInfo::getDirect();
868  }
869 
872 }
873 
875  if (RetTy->isVoidType())
876  return ABIArgInfo::getIgnore();
877 
878  // In the PNaCl ABI we always return records/structures on the stack.
879  if (isAggregateTypeForABI(RetTy))
880  return getNaturalAlignIndirect(RetTy);
881 
882  // Treat an enum type as its underlying type.
883  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
884  RetTy = EnumTy->getDecl()->getIntegerType();
885 
886  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
888 }
889 
890 /// IsX86_MMXType - Return true if this is an MMX type.
891 bool IsX86_MMXType(llvm::Type *IRType) {
892  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
893  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
894  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
895  IRType->getScalarSizeInBits() != 64;
896 }
897 
898 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
899  StringRef Constraint,
900  llvm::Type* Ty) {
901  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
902  .Cases("y", "&y", "^Ym", true)
903  .Default(false);
904  if (IsMMXCons && Ty->isVectorTy()) {
905  if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
906  // Invalid MMX constraint
907  return nullptr;
908  }
909 
910  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
911  }
912 
913  // No operation needed
914  return Ty;
915 }
916 
917 /// Returns true if this type can be passed in SSE registers with the
918 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
919 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
920  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
921  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
922  if (BT->getKind() == BuiltinType::LongDouble) {
923  if (&Context.getTargetInfo().getLongDoubleFormat() ==
924  &llvm::APFloat::x87DoubleExtended())
925  return false;
926  }
927  return true;
928  }
929  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
930  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
931  // registers specially.
932  unsigned VecSize = Context.getTypeSize(VT);
933  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
934  return true;
935  }
936  return false;
937 }
938 
939 /// Returns true if this aggregate is small enough to be passed in SSE registers
940 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
941 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
942  return NumMembers <= 4;
943 }
944 
945 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
946 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
947  auto AI = ABIArgInfo::getDirect(T);
948  AI.setInReg(true);
949  AI.setCanBeFlattened(false);
950  return AI;
951 }
952 
953 //===----------------------------------------------------------------------===//
954 // X86-32 ABI Implementation
955 //===----------------------------------------------------------------------===//
956 
957 /// Similar to llvm::CCState, but for Clang.
958 struct CCState {
959  CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
960 
961  unsigned CC;
962  unsigned FreeRegs;
963  unsigned FreeSSERegs;
964 };
965 
966 enum {
967  // Vectorcall only allows the first 6 parameters to be passed in registers.
968  VectorcallMaxParamNumAsReg = 6
969 };
970 
971 /// X86_32ABIInfo - The X86-32 ABI information.
972 class X86_32ABIInfo : public SwiftABIInfo {
973  enum Class {
974  Integer,
975  Float
976  };
977 
978  static const unsigned MinABIStackAlignInBytes = 4;
979 
980  bool IsDarwinVectorABI;
981  bool IsRetSmallStructInRegABI;
982  bool IsWin32StructABI;
983  bool IsSoftFloatABI;
984  bool IsMCUABI;
985  unsigned DefaultNumRegisterParameters;
986 
987  static bool isRegisterSize(unsigned Size) {
988  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
989  }
990 
991  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
992  // FIXME: Assumes vectorcall is in use.
993  return isX86VectorTypeForVectorCall(getContext(), Ty);
994  }
995 
997  uint64_t NumMembers) const override {
998  // FIXME: Assumes vectorcall is in use.
999  return isX86VectorCallAggregateSmallEnough(NumMembers);
1000  }
1001 
1002  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1003 
1004  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1005  /// such that the argument will be passed in memory.
1006  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1007 
1008  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1009 
1010  /// Return the alignment to use for the given type on the stack.
1011  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1012 
1013  Class classify(QualType Ty) const;
1014  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1015  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1016 
1017  /// Updates the number of available free registers, returns
1018  /// true if any registers were allocated.
1019  bool updateFreeRegs(QualType Ty, CCState &State) const;
1020 
1021  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1022  bool &NeedsPadding) const;
1023  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1024 
1025  bool canExpandIndirectArgument(QualType Ty) const;
1026 
1027  /// Rewrite the function info so that all memory arguments use
1028  /// inalloca.
1029  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1030 
1031  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1032  CharUnits &StackOffset, ABIArgInfo &Info,
1033  QualType Type) const;
1034  void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1035  bool &UsedInAlloca) const;
1036 
1037 public:
1038 
1039  void computeInfo(CGFunctionInfo &FI) const override;
1040  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1041  QualType Ty) const override;
1042 
1043  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1044  bool RetSmallStructInRegABI, bool Win32StructABI,
1045  unsigned NumRegisterParameters, bool SoftFloatABI)
1046  : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1047  IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1048  IsWin32StructABI(Win32StructABI),
1049  IsSoftFloatABI(SoftFloatABI),
1050  IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1051  DefaultNumRegisterParameters(NumRegisterParameters) {}
1052 
1053  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1054  bool asReturnValue) const override {
1055  // LLVM's x86-32 lowering currently only assigns up to three
1056  // integer registers and three fp registers. Oddly, it'll use up to
1057  // four vector registers for vectors, but those can overlap with the
1058  // scalar registers.
1059  return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1060  }
1061 
1062  bool isSwiftErrorInRegister() const override {
1063  // x86-32 lowering does not support passing swifterror in a register.
1064  return false;
1065  }
1066 };
1067 
1068 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1069 public:
1070  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1071  bool RetSmallStructInRegABI, bool Win32StructABI,
1072  unsigned NumRegisterParameters, bool SoftFloatABI)
1073  : TargetCodeGenInfo(new X86_32ABIInfo(
1074  CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1075  NumRegisterParameters, SoftFloatABI)) {}
1076 
1077  static bool isStructReturnInRegABI(
1078  const llvm::Triple &Triple, const CodeGenOptions &Opts);
1079 
1080  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1081  CodeGen::CodeGenModule &CGM) const override;
1082 
1083  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1084  // Darwin uses different dwarf register numbers for EH.
1085  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1086  return 4;
1087  }
1088 
1089  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1090  llvm::Value *Address) const override;
1091 
1092  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1093  StringRef Constraint,
1094  llvm::Type* Ty) const override {
1095  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1096  }
1097 
1098  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1099  std::string &Constraints,
1100  std::vector<llvm::Type *> &ResultRegTypes,
1101  std::vector<llvm::Type *> &ResultTruncRegTypes,
1102  std::vector<LValue> &ResultRegDests,
1103  std::string &AsmString,
1104  unsigned NumOutputs) const override;
1105 
1106  llvm::Constant *
1107  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1108  unsigned Sig = (0xeb << 0) | // jmp rel8
1109  (0x06 << 8) | // .+0x08
1110  ('v' << 16) |
1111  ('2' << 24);
1112  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1113  }
1114 
1115  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1116  return "movl\t%ebp, %ebp"
1117  "\t\t// marker for objc_retainAutoreleaseReturnValue";
1118  }
1119 };
1120 
1121 }
1122 
1123 /// Rewrite input constraint references after adding some output constraints.
1124 /// In the case where there is one output and one input and we add one output,
1125 /// we need to replace all operand references greater than or equal to 1:
1126 /// mov $0, $1
1127 /// mov eax, $1
1128 /// The result will be:
1129 /// mov $0, $2
1130 /// mov eax, $2
1131 static void rewriteInputConstraintReferences(unsigned FirstIn,
1132  unsigned NumNewOuts,
1133  std::string &AsmString) {
1134  std::string Buf;
1135  llvm::raw_string_ostream OS(Buf);
1136  size_t Pos = 0;
1137  while (Pos < AsmString.size()) {
1138  size_t DollarStart = AsmString.find('$', Pos);
1139  if (DollarStart == std::string::npos)
1140  DollarStart = AsmString.size();
1141  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1142  if (DollarEnd == std::string::npos)
1143  DollarEnd = AsmString.size();
1144  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1145  Pos = DollarEnd;
1146  size_t NumDollars = DollarEnd - DollarStart;
1147  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1148  // We have an operand reference.
1149  size_t DigitStart = Pos;
1150  size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1151  if (DigitEnd == std::string::npos)
1152  DigitEnd = AsmString.size();
1153  StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1154  unsigned OperandIndex;
1155  if (!OperandStr.getAsInteger(10, OperandIndex)) {
1156  if (OperandIndex >= FirstIn)
1157  OperandIndex += NumNewOuts;
1158  OS << OperandIndex;
1159  } else {
1160  OS << OperandStr;
1161  }
1162  Pos = DigitEnd;
1163  }
1164  }
1165  AsmString = std::move(OS.str());
1166 }
1167 
1168 /// Add output constraints for EAX:EDX because they are return registers.
1169 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1170  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1171  std::vector<llvm::Type *> &ResultRegTypes,
1172  std::vector<llvm::Type *> &ResultTruncRegTypes,
1173  std::vector<LValue> &ResultRegDests, std::string &AsmString,
1174  unsigned NumOutputs) const {
1175  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1176 
1177  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1178  // larger.
1179  if (!Constraints.empty())
1180  Constraints += ',';
1181  if (RetWidth <= 32) {
1182  Constraints += "={eax}";
1183  ResultRegTypes.push_back(CGF.Int32Ty);
1184  } else {
1185  // Use the 'A' constraint for EAX:EDX.
1186  Constraints += "=A";
1187  ResultRegTypes.push_back(CGF.Int64Ty);
1188  }
1189 
1190  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1191  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1192  ResultTruncRegTypes.push_back(CoerceTy);
1193 
1194  // Coerce the integer by bitcasting the return slot pointer.
1195  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1196  CoerceTy->getPointerTo()));
1197  ResultRegDests.push_back(ReturnSlot);
1198 
1199  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1200 }
1201 
1202 /// shouldReturnTypeInRegister - Determine if the given type should be
1203 /// returned in a register (for the Darwin and MCU ABI).
1204 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1205  ASTContext &Context) const {
1206  uint64_t Size = Context.getTypeSize(Ty);
1207 
1208  // For i386, type must be register sized.
1209  // For the MCU ABI, it only needs to be <= 8-byte
1210  if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1211  return false;
1212 
1213  if (Ty->isVectorType()) {
1214  // 64- and 128- bit vectors inside structures are not returned in
1215  // registers.
1216  if (Size == 64 || Size == 128)
1217  return false;
1218 
1219  return true;
1220  }
1221 
1222  // If this is a builtin, pointer, enum, complex type, member pointer, or
1223  // member function pointer it is ok.
1224  if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1225  Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1226  Ty->isBlockPointerType() || Ty->isMemberPointerType())
1227  return true;
1228 
1229  // Arrays are treated like records.
1230  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1231  return shouldReturnTypeInRegister(AT->getElementType(), Context);
1232 
1233  // Otherwise, it must be a record type.
1234  const RecordType *RT = Ty->getAs<RecordType>();
1235  if (!RT) return false;
1236 
1237  // FIXME: Traverse bases here too.
1238 
1239  // Structure types are passed in register if all fields would be
1240  // passed in a register.
1241  for (const auto *FD : RT->getDecl()->fields()) {
1242  // Empty fields are ignored.
1243  if (isEmptyField(Context, FD, true))
1244  continue;
1245 
1246  // Check fields recursively.
1247  if (!shouldReturnTypeInRegister(FD->getType(), Context))
1248  return false;
1249  }
1250  return true;
1251 }
1252 
1253 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1254  // Treat complex types as the element type.
1255  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1256  Ty = CTy->getElementType();
1257 
1258  // Check for a type which we know has a simple scalar argument-passing
1259  // convention without any padding. (We're specifically looking for 32
1260  // and 64-bit integer and integer-equivalents, float, and double.)
1261  if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1262  !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1263  return false;
1264 
1265  uint64_t Size = Context.getTypeSize(Ty);
1266  return Size == 32 || Size == 64;
1267 }
1268 
1269 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1270  uint64_t &Size) {
1271  for (const auto *FD : RD->fields()) {
1272  // Scalar arguments on the stack get 4 byte alignment on x86. If the
1273  // argument is smaller than 32-bits, expanding the struct will create
1274  // alignment padding.
1275  if (!is32Or64BitBasicType(FD->getType(), Context))
1276  return false;
1277 
1278  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1279  // how to expand them yet, and the predicate for telling if a bitfield still
1280  // counts as "basic" is more complicated than what we were doing previously.
1281  if (FD->isBitField())
1282  return false;
1283 
1284  Size += Context.getTypeSize(FD->getType());
1285  }
1286  return true;
1287 }
1288 
1289 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1290  uint64_t &Size) {
1291  // Don't do this if there are any non-empty bases.
1292  for (const CXXBaseSpecifier &Base : RD->bases()) {
1293  if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1294  Size))
1295  return false;
1296  }
1297  if (!addFieldSizes(Context, RD, Size))
1298  return false;
1299  return true;
1300 }
1301 
1302 /// Test whether an argument type which is to be passed indirectly (on the
1303 /// stack) would have the equivalent layout if it was expanded into separate
1304 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1305 /// optimizations.
1306 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1307  // We can only expand structure types.
1308  const RecordType *RT = Ty->getAs<RecordType>();
1309  if (!RT)
1310  return false;
1311  const RecordDecl *RD = RT->getDecl();
1312  uint64_t Size = 0;
1313  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1314  if (!IsWin32StructABI) {
1315  // On non-Windows, we have to conservatively match our old bitcode
1316  // prototypes in order to be ABI-compatible at the bitcode level.
1317  if (!CXXRD->isCLike())
1318  return false;
1319  } else {
1320  // Don't do this for dynamic classes.
1321  if (CXXRD->isDynamicClass())
1322  return false;
1323  }
1324  if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1325  return false;
1326  } else {
1327  if (!addFieldSizes(getContext(), RD, Size))
1328  return false;
1329  }
1330 
1331  // We can do this if there was no alignment padding.
1332  return Size == getContext().getTypeSize(Ty);
1333 }
1334 
1335 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1336  // If the return value is indirect, then the hidden argument is consuming one
1337  // integer register.
1338  if (State.FreeRegs) {
1339  --State.FreeRegs;
1340  if (!IsMCUABI)
1341  return getNaturalAlignIndirectInReg(RetTy);
1342  }
1343  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1344 }
1345 
1347  CCState &State) const {
1348  if (RetTy->isVoidType())
1349  return ABIArgInfo::getIgnore();
1350 
1351  const Type *Base = nullptr;
1352  uint64_t NumElts = 0;
1353  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1354  State.CC == llvm::CallingConv::X86_RegCall) &&
1355  isHomogeneousAggregate(RetTy, Base, NumElts)) {
1356  // The LLVM struct type for such an aggregate should lower properly.
1357  return ABIArgInfo::getDirect();
1358  }
1359 
1360  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1361  // On Darwin, some vectors are returned in registers.
1362  if (IsDarwinVectorABI) {
1363  uint64_t Size = getContext().getTypeSize(RetTy);
1364 
1365  // 128-bit vectors are a special case; they are returned in
1366  // registers and we need to make sure to pick a type the LLVM
1367  // backend will like.
1368  if (Size == 128)
1369  return ABIArgInfo::getDirect(llvm::VectorType::get(
1370  llvm::Type::getInt64Ty(getVMContext()), 2));
1371 
1372  // Always return in register if it fits in a general purpose
1373  // register, or if it is 64 bits and has a single element.
1374  if ((Size == 8 || Size == 16 || Size == 32) ||
1375  (Size == 64 && VT->getNumElements() == 1))
1376  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1377  Size));
1378 
1379  return getIndirectReturnResult(RetTy, State);
1380  }
1381 
1382  return ABIArgInfo::getDirect();
1383  }
1384 
1385  if (isAggregateTypeForABI(RetTy)) {
1386  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1387  // Structures with flexible arrays are always indirect.
1388  if (RT->getDecl()->hasFlexibleArrayMember())
1389  return getIndirectReturnResult(RetTy, State);
1390  }
1391 
1392  // If specified, structs and unions are always indirect.
1393  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1394  return getIndirectReturnResult(RetTy, State);
1395 
1396  // Ignore empty structs/unions.
1397  if (isEmptyRecord(getContext(), RetTy, true))
1398  return ABIArgInfo::getIgnore();
1399 
1400  // Small structures which are register sized are generally returned
1401  // in a register.
1402  if (shouldReturnTypeInRegister(RetTy, getContext())) {
1403  uint64_t Size = getContext().getTypeSize(RetTy);
1404 
1405  // As a special-case, if the struct is a "single-element" struct, and
1406  // the field is of type "float" or "double", return it in a
1407  // floating-point register. (MSVC does not apply this special case.)
1408  // We apply a similar transformation for pointer types to improve the
1409  // quality of the generated IR.
1410  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1411  if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1412  || SeltTy->hasPointerRepresentation())
1413  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1414 
1415  // FIXME: We should be able to narrow this integer in cases with dead
1416  // padding.
1417  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1418  }
1419 
1420  return getIndirectReturnResult(RetTy, State);
1421  }
1422 
1423  // Treat an enum type as its underlying type.
1424  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1425  RetTy = EnumTy->getDecl()->getIntegerType();
1426 
1427  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
1428  : ABIArgInfo::getDirect());
1429 }
1430 
1431 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1432  return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1433 }
1434 
1435 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1436  const RecordType *RT = Ty->getAs<RecordType>();
1437  if (!RT)
1438  return 0;
1439  const RecordDecl *RD = RT->getDecl();
1440 
1441  // If this is a C++ record, check the bases first.
1442  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1443  for (const auto &I : CXXRD->bases())
1444  if (!isRecordWithSSEVectorType(Context, I.getType()))
1445  return false;
1446 
1447  for (const auto *i : RD->fields()) {
1448  QualType FT = i->getType();
1449 
1450  if (isSSEVectorType(Context, FT))
1451  return true;
1452 
1453  if (isRecordWithSSEVectorType(Context, FT))
1454  return true;
1455  }
1456 
1457  return false;
1458 }
1459 
1460 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1461  unsigned Align) const {
1462  // Otherwise, if the alignment is less than or equal to the minimum ABI
1463  // alignment, just use the default; the backend will handle this.
1464  if (Align <= MinABIStackAlignInBytes)
1465  return 0; // Use default alignment.
1466 
1467  // On non-Darwin, the stack type alignment is always 4.
1468  if (!IsDarwinVectorABI) {
1469  // Set explicit alignment, since we may need to realign the top.
1470  return MinABIStackAlignInBytes;
1471  }
1472 
1473  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1474  if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1476  return 16;
1477 
1478  return MinABIStackAlignInBytes;
1479 }
1480 
1481 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1482  CCState &State) const {
1483  if (!ByVal) {
1484  if (State.FreeRegs) {
1485  --State.FreeRegs; // Non-byval indirects just use one pointer.
1486  if (!IsMCUABI)
1487  return getNaturalAlignIndirectInReg(Ty);
1488  }
1489  return getNaturalAlignIndirect(Ty, false);
1490  }
1491 
1492  // Compute the byval alignment.
1493  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1494  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1495  if (StackAlign == 0)
1496  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1497 
1498  // If the stack alignment is less than the type alignment, realign the
1499  // argument.
1500  bool Realign = TypeAlign > StackAlign;
1502  /*ByVal=*/true, Realign);
1503 }
1504 
1505 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1506  const Type *T = isSingleElementStruct(Ty, getContext());
1507  if (!T)
1508  T = Ty.getTypePtr();
1509 
1510  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1511  BuiltinType::Kind K = BT->getKind();
1512  if (K == BuiltinType::Float || K == BuiltinType::Double)
1513  return Float;
1514  }
1515  return Integer;
1516 }
1517 
1518 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1519  if (!IsSoftFloatABI) {
1520  Class C = classify(Ty);
1521  if (C == Float)
1522  return false;
1523  }
1524 
1525  unsigned Size = getContext().getTypeSize(Ty);
1526  unsigned SizeInRegs = (Size + 31) / 32;
1527 
1528  if (SizeInRegs == 0)
1529  return false;
1530 
1531  if (!IsMCUABI) {
1532  if (SizeInRegs > State.FreeRegs) {
1533  State.FreeRegs = 0;
1534  return false;
1535  }
1536  } else {
1537  // The MCU psABI allows passing parameters in-reg even if there are
1538  // earlier parameters that are passed on the stack. Also,
1539  // it does not allow passing >8-byte structs in-register,
1540  // even if there are 3 free registers available.
1541  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1542  return false;
1543  }
1544 
1545  State.FreeRegs -= SizeInRegs;
1546  return true;
1547 }
1548 
1549 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1550  bool &InReg,
1551  bool &NeedsPadding) const {
1552  // On Windows, aggregates other than HFAs are never passed in registers, and
1553  // they do not consume register slots. Homogenous floating-point aggregates
1554  // (HFAs) have already been dealt with at this point.
1555  if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1556  return false;
1557 
1558  NeedsPadding = false;
1559  InReg = !IsMCUABI;
1560 
1561  if (!updateFreeRegs(Ty, State))
1562  return false;
1563 
1564  if (IsMCUABI)
1565  return true;
1566 
1567  if (State.CC == llvm::CallingConv::X86_FastCall ||
1568  State.CC == llvm::CallingConv::X86_VectorCall ||
1569  State.CC == llvm::CallingConv::X86_RegCall) {
1570  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1571  NeedsPadding = true;
1572 
1573  return false;
1574  }
1575 
1576  return true;
1577 }
1578 
1579 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1580  if (!updateFreeRegs(Ty, State))
1581  return false;
1582 
1583  if (IsMCUABI)
1584  return false;
1585 
1586  if (State.CC == llvm::CallingConv::X86_FastCall ||
1587  State.CC == llvm::CallingConv::X86_VectorCall ||
1588  State.CC == llvm::CallingConv::X86_RegCall) {
1589  if (getContext().getTypeSize(Ty) > 32)
1590  return false;
1591 
1592  return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1593  Ty->isReferenceType());
1594  }
1595 
1596  return true;
1597 }
1598 
1600  CCState &State) const {
1601  // FIXME: Set alignment on indirect arguments.
1602 
1604 
1605  // Check with the C++ ABI first.
1606  const RecordType *RT = Ty->getAs<RecordType>();
1607  if (RT) {
1609  if (RAA == CGCXXABI::RAA_Indirect) {
1610  return getIndirectResult(Ty, false, State);
1611  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1612  // The field index doesn't matter, we'll fix it up later.
1613  return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1614  }
1615  }
1616 
1617  // Regcall uses the concept of a homogenous vector aggregate, similar
1618  // to other targets.
1619  const Type *Base = nullptr;
1620  uint64_t NumElts = 0;
1621  if (State.CC == llvm::CallingConv::X86_RegCall &&
1622  isHomogeneousAggregate(Ty, Base, NumElts)) {
1623 
1624  if (State.FreeSSERegs >= NumElts) {
1625  State.FreeSSERegs -= NumElts;
1626  if (Ty->isBuiltinType() || Ty->isVectorType())
1627  return ABIArgInfo::getDirect();
1628  return ABIArgInfo::getExpand();
1629  }
1630  return getIndirectResult(Ty, /*ByVal=*/false, State);
1631  }
1632 
1633  if (isAggregateTypeForABI(Ty)) {
1634  // Structures with flexible arrays are always indirect.
1635  // FIXME: This should not be byval!
1636  if (RT && RT->getDecl()->hasFlexibleArrayMember())
1637  return getIndirectResult(Ty, true, State);
1638 
1639  // Ignore empty structs/unions on non-Windows.
1640  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1641  return ABIArgInfo::getIgnore();
1642 
1643  llvm::LLVMContext &LLVMContext = getVMContext();
1644  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1645  bool NeedsPadding = false;
1646  bool InReg;
1647  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1648  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1649  SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1650  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1651  if (InReg)
1652  return ABIArgInfo::getDirectInReg(Result);
1653  else
1654  return ABIArgInfo::getDirect(Result);
1655  }
1656  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1657 
1658  // Expand small (<= 128-bit) record types when we know that the stack layout
1659  // of those arguments will match the struct. This is important because the
1660  // LLVM backend isn't smart enough to remove byval, which inhibits many
1661  // optimizations.
1662  // Don't do this for the MCU if there are still free integer registers
1663  // (see X86_64 ABI for full explanation).
1664  if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1665  (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1667  State.CC == llvm::CallingConv::X86_FastCall ||
1668  State.CC == llvm::CallingConv::X86_VectorCall ||
1669  State.CC == llvm::CallingConv::X86_RegCall,
1670  PaddingType);
1671 
1672  return getIndirectResult(Ty, true, State);
1673  }
1674 
1675  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1676  // On Darwin, some vectors are passed in memory, we handle this by passing
1677  // it as an i8/i16/i32/i64.
1678  if (IsDarwinVectorABI) {
1679  uint64_t Size = getContext().getTypeSize(Ty);
1680  if ((Size == 8 || Size == 16 || Size == 32) ||
1681  (Size == 64 && VT->getNumElements() == 1))
1682  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1683  Size));
1684  }
1685 
1686  if (IsX86_MMXType(CGT.ConvertType(Ty)))
1687  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1688 
1689  return ABIArgInfo::getDirect();
1690  }
1691 
1692 
1693  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1694  Ty = EnumTy->getDecl()->getIntegerType();
1695 
1696  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1697 
1698  if (Ty->isPromotableIntegerType()) {
1699  if (InReg)
1700  return ABIArgInfo::getExtendInReg(Ty);
1701  return ABIArgInfo::getExtend(Ty);
1702  }
1703 
1704  if (InReg)
1705  return ABIArgInfo::getDirectInReg();
1706  return ABIArgInfo::getDirect();
1707 }
1708 
1709 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1710  bool &UsedInAlloca) const {
1711  // Vectorcall x86 works subtly different than in x64, so the format is
1712  // a bit different than the x64 version. First, all vector types (not HVAs)
1713  // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1714  // This differs from the x64 implementation, where the first 6 by INDEX get
1715  // registers.
1716  // After that, integers AND HVAs are assigned Left to Right in the same pass.
1717  // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1718  // first take up the remaining YMM/XMM registers. If insufficient registers
1719  // remain but an integer register (ECX/EDX) is available, it will be passed
1720  // in that, else, on the stack.
1721  for (auto &I : FI.arguments()) {
1722  // First pass do all the vector types.
1723  const Type *Base = nullptr;
1724  uint64_t NumElts = 0;
1725  const QualType& Ty = I.type;
1726  if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1727  isHomogeneousAggregate(Ty, Base, NumElts)) {
1728  if (State.FreeSSERegs >= NumElts) {
1729  State.FreeSSERegs -= NumElts;
1730  I.info = ABIArgInfo::getDirect();
1731  } else {
1732  I.info = classifyArgumentType(Ty, State);
1733  }
1734  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1735  }
1736  }
1737 
1738  for (auto &I : FI.arguments()) {
1739  // Second pass, do the rest!
1740  const Type *Base = nullptr;
1741  uint64_t NumElts = 0;
1742  const QualType& Ty = I.type;
1743  bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1744 
1745  if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1746  // Assign true HVAs (non vector/native FP types).
1747  if (State.FreeSSERegs >= NumElts) {
1748  State.FreeSSERegs -= NumElts;
1749  I.info = getDirectX86Hva();
1750  } else {
1751  I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1752  }
1753  } else if (!IsHva) {
1754  // Assign all Non-HVAs, so this will exclude Vector/FP args.
1755  I.info = classifyArgumentType(Ty, State);
1756  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1757  }
1758  }
1759 }
1760 
1761 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1762  CCState State(FI.getCallingConvention());
1763  if (IsMCUABI)
1764  State.FreeRegs = 3;
1765  else if (State.CC == llvm::CallingConv::X86_FastCall)
1766  State.FreeRegs = 2;
1767  else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1768  State.FreeRegs = 2;
1769  State.FreeSSERegs = 6;
1770  } else if (FI.getHasRegParm())
1771  State.FreeRegs = FI.getRegParm();
1772  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1773  State.FreeRegs = 5;
1774  State.FreeSSERegs = 8;
1775  } else
1776  State.FreeRegs = DefaultNumRegisterParameters;
1777 
1778  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1780  } else if (FI.getReturnInfo().isIndirect()) {
1781  // The C++ ABI is not aware of register usage, so we have to check if the
1782  // return value was sret and put it in a register ourselves if appropriate.
1783  if (State.FreeRegs) {
1784  --State.FreeRegs; // The sret parameter consumes a register.
1785  if (!IsMCUABI)
1786  FI.getReturnInfo().setInReg(true);
1787  }
1788  }
1789 
1790  // The chain argument effectively gives us another free register.
1791  if (FI.isChainCall())
1792  ++State.FreeRegs;
1793 
1794  bool UsedInAlloca = false;
1795  if (State.CC == llvm::CallingConv::X86_VectorCall) {
1796  computeVectorCallArgs(FI, State, UsedInAlloca);
1797  } else {
1798  // If not vectorcall, revert to normal behavior.
1799  for (auto &I : FI.arguments()) {
1800  I.info = classifyArgumentType(I.type, State);
1801  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1802  }
1803  }
1804 
1805  // If we needed to use inalloca for any argument, do a second pass and rewrite
1806  // all the memory arguments to use inalloca.
1807  if (UsedInAlloca)
1808  rewriteWithInAlloca(FI);
1809 }
1810 
1811 void
1812 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1813  CharUnits &StackOffset, ABIArgInfo &Info,
1814  QualType Type) const {
1815  // Arguments are always 4-byte-aligned.
1816  CharUnits FieldAlign = CharUnits::fromQuantity(4);
1817 
1818  assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1819  Info = ABIArgInfo::getInAlloca(FrameFields.size());
1820  FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1821  StackOffset += getContext().getTypeSizeInChars(Type);
1822 
1823  // Insert padding bytes to respect alignment.
1824  CharUnits FieldEnd = StackOffset;
1825  StackOffset = FieldEnd.alignTo(FieldAlign);
1826  if (StackOffset != FieldEnd) {
1827  CharUnits NumBytes = StackOffset - FieldEnd;
1828  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1829  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1830  FrameFields.push_back(Ty);
1831  }
1832 }
1833 
1834 static bool isArgInAlloca(const ABIArgInfo &Info) {
1835  // Leave ignored and inreg arguments alone.
1836  switch (Info.getKind()) {
1837  case ABIArgInfo::InAlloca:
1838  return true;
1839  case ABIArgInfo::Indirect:
1840  assert(Info.getIndirectByVal());
1841  return true;
1842  case ABIArgInfo::Ignore:
1843  return false;
1844  case ABIArgInfo::Direct:
1845  case ABIArgInfo::Extend:
1846  if (Info.getInReg())
1847  return false;
1848  return true;
1849  case ABIArgInfo::Expand:
1851  // These are aggregate types which are never passed in registers when
1852  // inalloca is involved.
1853  return true;
1854  }
1855  llvm_unreachable("invalid enum");
1856 }
1857 
1858 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1859  assert(IsWin32StructABI && "inalloca only supported on win32");
1860 
1861  // Build a packed struct type for all of the arguments in memory.
1862  SmallVector<llvm::Type *, 6> FrameFields;
1863 
1864  // The stack alignment is always 4.
1865  CharUnits StackAlign = CharUnits::fromQuantity(4);
1866 
1867  CharUnits StackOffset;
1868  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1869 
1870  // Put 'this' into the struct before 'sret', if necessary.
1871  bool IsThisCall =
1872  FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1873  ABIArgInfo &Ret = FI.getReturnInfo();
1874  if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1875  isArgInAlloca(I->info)) {
1876  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1877  ++I;
1878  }
1879 
1880  // Put the sret parameter into the inalloca struct if it's in memory.
1881  if (Ret.isIndirect() && !Ret.getInReg()) {
1883  addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1884  // On Windows, the hidden sret parameter is always returned in eax.
1885  Ret.setInAllocaSRet(IsWin32StructABI);
1886  }
1887 
1888  // Skip the 'this' parameter in ecx.
1889  if (IsThisCall)
1890  ++I;
1891 
1892  // Put arguments passed in memory into the struct.
1893  for (; I != E; ++I) {
1894  if (isArgInAlloca(I->info))
1895  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1896  }
1897 
1898  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1899  /*isPacked=*/true),
1900  StackAlign);
1901 }
1902 
1903 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1904  Address VAListAddr, QualType Ty) const {
1905 
1906  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1907 
1908  // x86-32 changes the alignment of certain arguments on the stack.
1909  //
1910  // Just messing with TypeInfo like this works because we never pass
1911  // anything indirectly.
1913  getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1914 
1915  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1917  /*AllowHigherAlign*/ true);
1918 }
1919 
1920 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1921  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1922  assert(Triple.getArch() == llvm::Triple::x86);
1923 
1924  switch (Opts.getStructReturnConvention()) {
1926  break;
1927  case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1928  return false;
1929  case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1930  return true;
1931  }
1932 
1933  if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1934  return true;
1935 
1936  switch (Triple.getOS()) {
1937  case llvm::Triple::DragonFly:
1938  case llvm::Triple::FreeBSD:
1939  case llvm::Triple::OpenBSD:
1940  case llvm::Triple::Win32:
1941  return true;
1942  default:
1943  return false;
1944  }
1945 }
1946 
1947 void X86_32TargetCodeGenInfo::setTargetAttributes(
1948  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1949  if (GV->isDeclaration())
1950  return;
1951  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1952  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1953  llvm::Function *Fn = cast<llvm::Function>(GV);
1954  Fn->addFnAttr("stackrealign");
1955  }
1956  if (FD->hasAttr<AnyX86InterruptAttr>()) {
1957  llvm::Function *Fn = cast<llvm::Function>(GV);
1958  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1959  }
1960  }
1961 }
1962 
1963 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1965  llvm::Value *Address) const {
1966  CodeGen::CGBuilderTy &Builder = CGF.Builder;
1967 
1968  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1969 
1970  // 0-7 are the eight integer registers; the order is different
1971  // on Darwin (for EH), but the range is the same.
1972  // 8 is %eip.
1973  AssignToArrayRange(Builder, Address, Four8, 0, 8);
1974 
1975  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1976  // 12-16 are st(0..4). Not sure why we stop at 4.
1977  // These have size 16, which is sizeof(long double) on
1978  // platforms with 8-byte alignment for that type.
1979  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1980  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1981 
1982  } else {
1983  // 9 is %eflags, which doesn't get a size on Darwin for some
1984  // reason.
1985  Builder.CreateAlignedStore(
1986  Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1987  CharUnits::One());
1988 
1989  // 11-16 are st(0..5). Not sure why we stop at 5.
1990  // These have size 12, which is sizeof(long double) on
1991  // platforms with 4-byte alignment for that type.
1992  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
1993  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
1994  }
1995 
1996  return false;
1997 }
1998 
1999 //===----------------------------------------------------------------------===//
2000 // X86-64 ABI Implementation
2001 //===----------------------------------------------------------------------===//
2002 
2003 
2004 namespace {
2005 /// The AVX ABI level for X86 targets.
2006 enum class X86AVXABILevel {
2007  None,
2008  AVX,
2009  AVX512
2010 };
2011 
2012 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2013 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2014  switch (AVXLevel) {
2015  case X86AVXABILevel::AVX512:
2016  return 512;
2017  case X86AVXABILevel::AVX:
2018  return 256;
2019  case X86AVXABILevel::None:
2020  return 128;
2021  }
2022  llvm_unreachable("Unknown AVXLevel");
2023 }
2024 
2025 /// X86_64ABIInfo - The X86_64 ABI information.
2026 class X86_64ABIInfo : public SwiftABIInfo {
2027  enum Class {
2028  Integer = 0,
2029  SSE,
2030  SSEUp,
2031  X87,
2032  X87Up,
2033  ComplexX87,
2034  NoClass,
2035  Memory
2036  };
2037 
2038  /// merge - Implement the X86_64 ABI merging algorithm.
2039  ///
2040  /// Merge an accumulating classification \arg Accum with a field
2041  /// classification \arg Field.
2042  ///
2043  /// \param Accum - The accumulating classification. This should
2044  /// always be either NoClass or the result of a previous merge
2045  /// call. In addition, this should never be Memory (the caller
2046  /// should just return Memory for the aggregate).
2047  static Class merge(Class Accum, Class Field);
2048 
2049  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2050  ///
2051  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2052  /// final MEMORY or SSE classes when necessary.
2053  ///
2054  /// \param AggregateSize - The size of the current aggregate in
2055  /// the classification process.
2056  ///
2057  /// \param Lo - The classification for the parts of the type
2058  /// residing in the low word of the containing object.
2059  ///
2060  /// \param Hi - The classification for the parts of the type
2061  /// residing in the higher words of the containing object.
2062  ///
2063  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2064 
2065  /// classify - Determine the x86_64 register classes in which the
2066  /// given type T should be passed.
2067  ///
2068  /// \param Lo - The classification for the parts of the type
2069  /// residing in the low word of the containing object.
2070  ///
2071  /// \param Hi - The classification for the parts of the type
2072  /// residing in the high word of the containing object.
2073  ///
2074  /// \param OffsetBase - The bit offset of this type in the
2075  /// containing object. Some parameters are classified different
2076  /// depending on whether they straddle an eightbyte boundary.
2077  ///
2078  /// \param isNamedArg - Whether the argument in question is a "named"
2079  /// argument, as used in AMD64-ABI 3.5.7.
2080  ///
2081  /// If a word is unused its result will be NoClass; if a type should
2082  /// be passed in Memory then at least the classification of \arg Lo
2083  /// will be Memory.
2084  ///
2085  /// The \arg Lo class will be NoClass iff the argument is ignored.
2086  ///
2087  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2088  /// also be ComplexX87.
2089  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2090  bool isNamedArg) const;
2091 
2092  llvm::Type *GetByteVectorType(QualType Ty) const;
2093  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2094  unsigned IROffset, QualType SourceTy,
2095  unsigned SourceOffset) const;
2096  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2097  unsigned IROffset, QualType SourceTy,
2098  unsigned SourceOffset) const;
2099 
2100  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2101  /// such that the argument will be returned in memory.
2102  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2103 
2104  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2105  /// such that the argument will be passed in memory.
2106  ///
2107  /// \param freeIntRegs - The number of free integer registers remaining
2108  /// available.
2109  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2110 
2111  ABIArgInfo classifyReturnType(QualType RetTy) const;
2112 
2113  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2114  unsigned &neededInt, unsigned &neededSSE,
2115  bool isNamedArg) const;
2116 
2117  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2118  unsigned &NeededSSE) const;
2119 
2120  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2121  unsigned &NeededSSE) const;
2122 
2123  bool IsIllegalVectorType(QualType Ty) const;
2124 
2125  /// The 0.98 ABI revision clarified a lot of ambiguities,
2126  /// unfortunately in ways that were not always consistent with
2127  /// certain previous compilers. In particular, platforms which
2128  /// required strict binary compatibility with older versions of GCC
2129  /// may need to exempt themselves.
2130  bool honorsRevision0_98() const {
2131  return !getTarget().getTriple().isOSDarwin();
2132  }
2133 
2134  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2135  /// classify it as INTEGER (for compatibility with older clang compilers).
2136  bool classifyIntegerMMXAsSSE() const {
2137  // Clang <= 3.8 did not do this.
2138  if (getContext().getLangOpts().getClangABICompat() <=
2140  return false;
2141 
2142  const llvm::Triple &Triple = getTarget().getTriple();
2143  if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2144  return false;
2145  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2146  return false;
2147  return true;
2148  }
2149 
2150  X86AVXABILevel AVXLevel;
2151  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2152  // 64-bit hardware.
2153  bool Has64BitPointers;
2154 
2155 public:
2156  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2157  SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2158  Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2159  }
2160 
2161  bool isPassedUsingAVXType(QualType type) const {
2162  unsigned neededInt, neededSSE;
2163  // The freeIntRegs argument doesn't matter here.
2164  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2165  /*isNamedArg*/true);
2166  if (info.isDirect()) {
2167  llvm::Type *ty = info.getCoerceToType();
2168  if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2169  return (vectorTy->getBitWidth() > 128);
2170  }
2171  return false;
2172  }
2173 
2174  void computeInfo(CGFunctionInfo &FI) const override;
2175 
2176  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2177  QualType Ty) const override;
2178  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2179  QualType Ty) const override;
2180 
2181  bool has64BitPointers() const {
2182  return Has64BitPointers;
2183  }
2184 
2185  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2186  bool asReturnValue) const override {
2187  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2188  }
2189  bool isSwiftErrorInRegister() const override {
2190  return true;
2191  }
2192 };
2193 
2194 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2195 class WinX86_64ABIInfo : public SwiftABIInfo {
2196 public:
2197  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2198  : SwiftABIInfo(CGT),
2199  IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2200 
2201  void computeInfo(CGFunctionInfo &FI) const override;
2202 
2203  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2204  QualType Ty) const override;
2205 
2206  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2207  // FIXME: Assumes vectorcall is in use.
2208  return isX86VectorTypeForVectorCall(getContext(), Ty);
2209  }
2210 
2211  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2212  uint64_t NumMembers) const override {
2213  // FIXME: Assumes vectorcall is in use.
2214  return isX86VectorCallAggregateSmallEnough(NumMembers);
2215  }
2216 
2217  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2218  bool asReturnValue) const override {
2219  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2220  }
2221 
2222  bool isSwiftErrorInRegister() const override {
2223  return true;
2224  }
2225 
2226 private:
2227  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2228  bool IsVectorCall, bool IsRegCall) const;
2229  ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2230  const ABIArgInfo &current) const;
2231  void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2232  bool IsVectorCall, bool IsRegCall) const;
2233 
2234  bool IsMingw64;
2235 };
2236 
2237 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2238 public:
2239  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2240  : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2241 
2242  const X86_64ABIInfo &getABIInfo() const {
2243  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2244  }
2245 
2246  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2247  return 7;
2248  }
2249 
2250  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2251  llvm::Value *Address) const override {
2252  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2253 
2254  // 0-15 are the 16 integer registers.
2255  // 16 is %rip.
2256  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2257  return false;
2258  }
2259 
2260  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2261  StringRef Constraint,
2262  llvm::Type* Ty) const override {
2263  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2264  }
2265 
2266  bool isNoProtoCallVariadic(const CallArgList &args,
2267  const FunctionNoProtoType *fnType) const override {
2268  // The default CC on x86-64 sets %al to the number of SSA
2269  // registers used, and GCC sets this when calling an unprototyped
2270  // function, so we override the default behavior. However, don't do
2271  // that when AVX types are involved: the ABI explicitly states it is
2272  // undefined, and it doesn't work in practice because of how the ABI
2273  // defines varargs anyway.
2274  if (fnType->getCallConv() == CC_C) {
2275  bool HasAVXType = false;
2276  for (CallArgList::const_iterator
2277  it = args.begin(), ie = args.end(); it != ie; ++it) {
2278  if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2279  HasAVXType = true;
2280  break;
2281  }
2282  }
2283 
2284  if (!HasAVXType)
2285  return true;
2286  }
2287 
2288  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2289  }
2290 
2291  llvm::Constant *
2292  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2293  unsigned Sig = (0xeb << 0) | // jmp rel8
2294  (0x06 << 8) | // .+0x08
2295  ('v' << 16) |
2296  ('2' << 24);
2297  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2298  }
2299 
2300  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2301  CodeGen::CodeGenModule &CGM) const override {
2302  if (GV->isDeclaration())
2303  return;
2304  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2305  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2306  llvm::Function *Fn = cast<llvm::Function>(GV);
2307  Fn->addFnAttr("stackrealign");
2308  }
2309  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2310  llvm::Function *Fn = cast<llvm::Function>(GV);
2311  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2312  }
2313  }
2314  }
2315 };
2316 
2317 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2318 public:
2319  PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2320  : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2321 
2322  void getDependentLibraryOption(llvm::StringRef Lib,
2323  llvm::SmallString<24> &Opt) const override {
2324  Opt = "\01";
2325  // If the argument contains a space, enclose it in quotes.
2326  if (Lib.find(" ") != StringRef::npos)
2327  Opt += "\"" + Lib.str() + "\"";
2328  else
2329  Opt += Lib;
2330  }
2331 };
2332 
2333 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2334  // If the argument does not end in .lib, automatically add the suffix.
2335  // If the argument contains a space, enclose it in quotes.
2336  // This matches the behavior of MSVC.
2337  bool Quote = (Lib.find(" ") != StringRef::npos);
2338  std::string ArgStr = Quote ? "\"" : "";
2339  ArgStr += Lib;
2340  if (!Lib.endswith_lower(".lib"))
2341  ArgStr += ".lib";
2342  ArgStr += Quote ? "\"" : "";
2343  return ArgStr;
2344 }
2345 
2346 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2347 public:
2348  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2349  bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2350  unsigned NumRegisterParameters)
2351  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2352  Win32StructABI, NumRegisterParameters, false) {}
2353 
2354  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2355  CodeGen::CodeGenModule &CGM) const override;
2356 
2357  void getDependentLibraryOption(llvm::StringRef Lib,
2358  llvm::SmallString<24> &Opt) const override {
2359  Opt = "/DEFAULTLIB:";
2360  Opt += qualifyWindowsLibrary(Lib);
2361  }
2362 
2363  void getDetectMismatchOption(llvm::StringRef Name,
2364  llvm::StringRef Value,
2365  llvm::SmallString<32> &Opt) const override {
2366  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2367  }
2368 };
2369 
2370 static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2371  CodeGen::CodeGenModule &CGM) {
2372  if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2373 
2374  if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2375  Fn->addFnAttr("stack-probe-size",
2376  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2377  if (CGM.getCodeGenOpts().NoStackArgProbe)
2378  Fn->addFnAttr("no-stack-arg-probe");
2379  }
2380 }
2381 
2382 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2383  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2384  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2385  if (GV->isDeclaration())
2386  return;
2387  addStackProbeTargetAttributes(D, GV, CGM);
2388 }
2389 
2390 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2391 public:
2392  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2393  X86AVXABILevel AVXLevel)
2394  : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2395 
2396  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2397  CodeGen::CodeGenModule &CGM) const override;
2398 
2399  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2400  return 7;
2401  }
2402 
2403  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2404  llvm::Value *Address) const override {
2405  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2406 
2407  // 0-15 are the 16 integer registers.
2408  // 16 is %rip.
2409  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2410  return false;
2411  }
2412 
2413  void getDependentLibraryOption(llvm::StringRef Lib,
2414  llvm::SmallString<24> &Opt) const override {
2415  Opt = "/DEFAULTLIB:";
2416  Opt += qualifyWindowsLibrary(Lib);
2417  }
2418 
2419  void getDetectMismatchOption(llvm::StringRef Name,
2420  llvm::StringRef Value,
2421  llvm::SmallString<32> &Opt) const override {
2422  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2423  }
2424 };
2425 
2426 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2427  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2429  if (GV->isDeclaration())
2430  return;
2431  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2432  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2433  llvm::Function *Fn = cast<llvm::Function>(GV);
2434  Fn->addFnAttr("stackrealign");
2435  }
2436  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2437  llvm::Function *Fn = cast<llvm::Function>(GV);
2438  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2439  }
2440  }
2441 
2442  addStackProbeTargetAttributes(D, GV, CGM);
2443 }
2444 }
2445 
2446 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2447  Class &Hi) const {
2448  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2449  //
2450  // (a) If one of the classes is Memory, the whole argument is passed in
2451  // memory.
2452  //
2453  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2454  // memory.
2455  //
2456  // (c) If the size of the aggregate exceeds two eightbytes and the first
2457  // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2458  // argument is passed in memory. NOTE: This is necessary to keep the
2459  // ABI working for processors that don't support the __m256 type.
2460  //
2461  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2462  //
2463  // Some of these are enforced by the merging logic. Others can arise
2464  // only with unions; for example:
2465  // union { _Complex double; unsigned; }
2466  //
2467  // Note that clauses (b) and (c) were added in 0.98.
2468  //
2469  if (Hi == Memory)
2470  Lo = Memory;
2471  if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2472  Lo = Memory;
2473  if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2474  Lo = Memory;
2475  if (Hi == SSEUp && Lo != SSE)
2476  Hi = SSE;
2477 }
2478 
2479 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2480  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2481  // classified recursively so that always two fields are
2482  // considered. The resulting class is calculated according to
2483  // the classes of the fields in the eightbyte:
2484  //
2485  // (a) If both classes are equal, this is the resulting class.
2486  //
2487  // (b) If one of the classes is NO_CLASS, the resulting class is
2488  // the other class.
2489  //
2490  // (c) If one of the classes is MEMORY, the result is the MEMORY
2491  // class.
2492  //
2493  // (d) If one of the classes is INTEGER, the result is the
2494  // INTEGER.
2495  //
2496  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2497  // MEMORY is used as class.
2498  //
2499  // (f) Otherwise class SSE is used.
2500 
2501  // Accum should never be memory (we should have returned) or
2502  // ComplexX87 (because this cannot be passed in a structure).
2503  assert((Accum != Memory && Accum != ComplexX87) &&
2504  "Invalid accumulated classification during merge.");
2505  if (Accum == Field || Field == NoClass)
2506  return Accum;
2507  if (Field == Memory)
2508  return Memory;
2509  if (Accum == NoClass)
2510  return Field;
2511  if (Accum == Integer || Field == Integer)
2512  return Integer;
2513  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2514  Accum == X87 || Accum == X87Up)
2515  return Memory;
2516  return SSE;
2517 }
2518 
2519 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2520  Class &Lo, Class &Hi, bool isNamedArg) const {
2521  // FIXME: This code can be simplified by introducing a simple value class for
2522  // Class pairs with appropriate constructor methods for the various
2523  // situations.
2524 
2525  // FIXME: Some of the split computations are wrong; unaligned vectors
2526  // shouldn't be passed in registers for example, so there is no chance they
2527  // can straddle an eightbyte. Verify & simplify.
2528 
2529  Lo = Hi = NoClass;
2530 
2531  Class &Current = OffsetBase < 64 ? Lo : Hi;
2532  Current = Memory;
2533 
2534  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2535  BuiltinType::Kind k = BT->getKind();
2536 
2537  if (k == BuiltinType::Void) {
2538  Current = NoClass;
2539  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2540  Lo = Integer;
2541  Hi = Integer;
2542  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2543  Current = Integer;
2544  } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2545  Current = SSE;
2546  } else if (k == BuiltinType::LongDouble) {
2547  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2548  if (LDF == &llvm::APFloat::IEEEquad()) {
2549  Lo = SSE;
2550  Hi = SSEUp;
2551  } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2552  Lo = X87;
2553  Hi = X87Up;
2554  } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2555  Current = SSE;
2556  } else
2557  llvm_unreachable("unexpected long double representation!");
2558  }
2559  // FIXME: _Decimal32 and _Decimal64 are SSE.
2560  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2561  return;
2562  }
2563 
2564  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2565  // Classify the underlying integer type.
2566  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2567  return;
2568  }
2569 
2570  if (Ty->hasPointerRepresentation()) {
2571  Current = Integer;
2572  return;
2573  }
2574 
2575  if (Ty->isMemberPointerType()) {
2576  if (Ty->isMemberFunctionPointerType()) {
2577  if (Has64BitPointers) {
2578  // If Has64BitPointers, this is an {i64, i64}, so classify both
2579  // Lo and Hi now.
2580  Lo = Hi = Integer;
2581  } else {
2582  // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2583  // straddles an eightbyte boundary, Hi should be classified as well.
2584  uint64_t EB_FuncPtr = (OffsetBase) / 64;
2585  uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2586  if (EB_FuncPtr != EB_ThisAdj) {
2587  Lo = Hi = Integer;
2588  } else {
2589  Current = Integer;
2590  }
2591  }
2592  } else {
2593  Current = Integer;
2594  }
2595  return;
2596  }
2597 
2598  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2599  uint64_t Size = getContext().getTypeSize(VT);
2600  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2601  // gcc passes the following as integer:
2602  // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2603  // 2 bytes - <2 x char>, <1 x short>
2604  // 1 byte - <1 x char>
2605  Current = Integer;
2606 
2607  // If this type crosses an eightbyte boundary, it should be
2608  // split.
2609  uint64_t EB_Lo = (OffsetBase) / 64;
2610  uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2611  if (EB_Lo != EB_Hi)
2612  Hi = Lo;
2613  } else if (Size == 64) {
2614  QualType ElementType = VT->getElementType();
2615 
2616  // gcc passes <1 x double> in memory. :(
2617  if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2618  return;
2619 
2620  // gcc passes <1 x long long> as SSE but clang used to unconditionally
2621  // pass them as integer. For platforms where clang is the de facto
2622  // platform compiler, we must continue to use integer.
2623  if (!classifyIntegerMMXAsSSE() &&
2624  (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2625  ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2626  ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2627  ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2628  Current = Integer;
2629  else
2630  Current = SSE;
2631 
2632  // If this type crosses an eightbyte boundary, it should be
2633  // split.
2634  if (OffsetBase && OffsetBase != 64)
2635  Hi = Lo;
2636  } else if (Size == 128 ||
2637  (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2638  // Arguments of 256-bits are split into four eightbyte chunks. The
2639  // least significant one belongs to class SSE and all the others to class
2640  // SSEUP. The original Lo and Hi design considers that types can't be
2641  // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2642  // This design isn't correct for 256-bits, but since there're no cases
2643  // where the upper parts would need to be inspected, avoid adding
2644  // complexity and just consider Hi to match the 64-256 part.
2645  //
2646  // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2647  // registers if they are "named", i.e. not part of the "..." of a
2648  // variadic function.
2649  //
2650  // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2651  // split into eight eightbyte chunks, one SSE and seven SSEUP.
2652  Lo = SSE;
2653  Hi = SSEUp;
2654  }
2655  return;
2656  }
2657 
2658  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2659  QualType ET = getContext().getCanonicalType(CT->getElementType());
2660 
2661  uint64_t Size = getContext().getTypeSize(Ty);
2662  if (ET->isIntegralOrEnumerationType()) {
2663  if (Size <= 64)
2664  Current = Integer;
2665  else if (Size <= 128)
2666  Lo = Hi = Integer;
2667  } else if (ET == getContext().FloatTy) {
2668  Current = SSE;
2669  } else if (ET == getContext().DoubleTy) {
2670  Lo = Hi = SSE;
2671  } else if (ET == getContext().LongDoubleTy) {
2672  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2673  if (LDF == &llvm::APFloat::IEEEquad())
2674  Current = Memory;
2675  else if (LDF == &llvm::APFloat::x87DoubleExtended())
2676  Current = ComplexX87;
2677  else if (LDF == &llvm::APFloat::IEEEdouble())
2678  Lo = Hi = SSE;
2679  else
2680  llvm_unreachable("unexpected long double representation!");
2681  }
2682 
2683  // If this complex type crosses an eightbyte boundary then it
2684  // should be split.
2685  uint64_t EB_Real = (OffsetBase) / 64;
2686  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2687  if (Hi == NoClass && EB_Real != EB_Imag)
2688  Hi = Lo;
2689 
2690  return;
2691  }
2692 
2693  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2694  // Arrays are treated like structures.
2695 
2696  uint64_t Size = getContext().getTypeSize(Ty);
2697 
2698  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2699  // than eight eightbytes, ..., it has class MEMORY.
2700  if (Size > 512)
2701  return;
2702 
2703  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2704  // fields, it has class MEMORY.
2705  //
2706  // Only need to check alignment of array base.
2707  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2708  return;
2709 
2710  // Otherwise implement simplified merge. We could be smarter about
2711  // this, but it isn't worth it and would be harder to verify.
2712  Current = NoClass;
2713  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2714  uint64_t ArraySize = AT->getSize().getZExtValue();
2715 
2716  // The only case a 256-bit wide vector could be used is when the array
2717  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2718  // to work for sizes wider than 128, early check and fallback to memory.
2719  //
2720  if (Size > 128 &&
2721  (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2722  return;
2723 
2724  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2725  Class FieldLo, FieldHi;
2726  classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2727  Lo = merge(Lo, FieldLo);
2728  Hi = merge(Hi, FieldHi);
2729  if (Lo == Memory || Hi == Memory)
2730  break;
2731  }
2732 
2733  postMerge(Size, Lo, Hi);
2734  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2735  return;
2736  }
2737 
2738  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2739  uint64_t Size = getContext().getTypeSize(Ty);
2740 
2741  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2742  // than eight eightbytes, ..., it has class MEMORY.
2743  if (Size > 512)
2744  return;
2745 
2746  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2747  // copy constructor or a non-trivial destructor, it is passed by invisible
2748  // reference.
2749  if (getRecordArgABI(RT, getCXXABI()))
2750  return;
2751 
2752  const RecordDecl *RD = RT->getDecl();
2753 
2754  // Assume variable sized types are passed in memory.
2755  if (RD->hasFlexibleArrayMember())
2756  return;
2757 
2758  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2759 
2760  // Reset Lo class, this will be recomputed.
2761  Current = NoClass;
2762 
2763  // If this is a C++ record, classify the bases first.
2764  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2765  for (const auto &I : CXXRD->bases()) {
2766  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2767  "Unexpected base class!");
2768  const CXXRecordDecl *Base =
2769  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2770 
2771  // Classify this field.
2772  //
2773  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2774  // single eightbyte, each is classified separately. Each eightbyte gets
2775  // initialized to class NO_CLASS.
2776  Class FieldLo, FieldHi;
2777  uint64_t Offset =
2778  OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2779  classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2780  Lo = merge(Lo, FieldLo);
2781  Hi = merge(Hi, FieldHi);
2782  if (Lo == Memory || Hi == Memory) {
2783  postMerge(Size, Lo, Hi);
2784  return;
2785  }
2786  }
2787  }
2788 
2789  // Classify the fields one at a time, merging the results.
2790  unsigned idx = 0;
2791  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2792  i != e; ++i, ++idx) {
2793  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2794  bool BitField = i->isBitField();
2795 
2796  // Ignore padding bit-fields.
2797  if (BitField && i->isUnnamedBitfield())
2798  continue;
2799 
2800  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2801  // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2802  //
2803  // The only case a 256-bit wide vector could be used is when the struct
2804  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2805  // to work for sizes wider than 128, early check and fallback to memory.
2806  //
2807  if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2808  Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2809  Lo = Memory;
2810  postMerge(Size, Lo, Hi);
2811  return;
2812  }
2813  // Note, skip this test for bit-fields, see below.
2814  if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2815  Lo = Memory;
2816  postMerge(Size, Lo, Hi);
2817  return;
2818  }
2819 
2820  // Classify this field.
2821  //
2822  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2823  // exceeds a single eightbyte, each is classified
2824  // separately. Each eightbyte gets initialized to class
2825  // NO_CLASS.
2826  Class FieldLo, FieldHi;
2827 
2828  // Bit-fields require special handling, they do not force the
2829  // structure to be passed in memory even if unaligned, and
2830  // therefore they can straddle an eightbyte.
2831  if (BitField) {
2832  assert(!i->isUnnamedBitfield());
2833  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2834  uint64_t Size = i->getBitWidthValue(getContext());
2835 
2836  uint64_t EB_Lo = Offset / 64;
2837  uint64_t EB_Hi = (Offset + Size - 1) / 64;
2838 
2839  if (EB_Lo) {
2840  assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2841  FieldLo = NoClass;
2842  FieldHi = Integer;
2843  } else {
2844  FieldLo = Integer;
2845  FieldHi = EB_Hi ? Integer : NoClass;
2846  }
2847  } else
2848  classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2849  Lo = merge(Lo, FieldLo);
2850  Hi = merge(Hi, FieldHi);
2851  if (Lo == Memory || Hi == Memory)
2852  break;
2853  }
2854 
2855  postMerge(Size, Lo, Hi);
2856  }
2857 }
2858 
2859 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2860  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2861  // place naturally.
2862  if (!isAggregateTypeForABI(Ty)) {
2863  // Treat an enum type as its underlying type.
2864  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2865  Ty = EnumTy->getDecl()->getIntegerType();
2866 
2868  : ABIArgInfo::getDirect());
2869  }
2870 
2871  return getNaturalAlignIndirect(Ty);
2872 }
2873 
2874 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2875  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2876  uint64_t Size = getContext().getTypeSize(VecTy);
2877  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2878  if (Size <= 64 || Size > LargestVector)
2879  return true;
2880  }
2881 
2882  return false;
2883 }
2884 
2885 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2886  unsigned freeIntRegs) const {
2887  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2888  // place naturally.
2889  //
2890  // This assumption is optimistic, as there could be free registers available
2891  // when we need to pass this argument in memory, and LLVM could try to pass
2892  // the argument in the free register. This does not seem to happen currently,
2893  // but this code would be much safer if we could mark the argument with
2894  // 'onstack'. See PR12193.
2895  if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2896  // Treat an enum type as its underlying type.
2897  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2898  Ty = EnumTy->getDecl()->getIntegerType();
2899 
2901  : ABIArgInfo::getDirect());
2902  }
2903 
2906 
2907  // Compute the byval alignment. We specify the alignment of the byval in all
2908  // cases so that the mid-level optimizer knows the alignment of the byval.
2909  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2910 
2911  // Attempt to avoid passing indirect results using byval when possible. This
2912  // is important for good codegen.
2913  //
2914  // We do this by coercing the value into a scalar type which the backend can
2915  // handle naturally (i.e., without using byval).
2916  //
2917  // For simplicity, we currently only do this when we have exhausted all of the
2918  // free integer registers. Doing this when there are free integer registers
2919  // would require more care, as we would have to ensure that the coerced value
2920  // did not claim the unused register. That would require either reording the
2921  // arguments to the function (so that any subsequent inreg values came first),
2922  // or only doing this optimization when there were no following arguments that
2923  // might be inreg.
2924  //
2925  // We currently expect it to be rare (particularly in well written code) for
2926  // arguments to be passed on the stack when there are still free integer
2927  // registers available (this would typically imply large structs being passed
2928  // by value), so this seems like a fair tradeoff for now.
2929  //
2930  // We can revisit this if the backend grows support for 'onstack' parameter
2931  // attributes. See PR12193.
2932  if (freeIntRegs == 0) {
2933  uint64_t Size = getContext().getTypeSize(Ty);
2934 
2935  // If this type fits in an eightbyte, coerce it into the matching integral
2936  // type, which will end up on the stack (with alignment 8).
2937  if (Align == 8 && Size <= 64)
2938  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2939  Size));
2940  }
2941 
2943 }
2944 
2945 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2946 /// register. Pick an LLVM IR type that will be passed as a vector register.
2947 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2948  // Wrapper structs/arrays that only contain vectors are passed just like
2949  // vectors; strip them off if present.
2950  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2951  Ty = QualType(InnerTy, 0);
2952 
2953  llvm::Type *IRType = CGT.ConvertType(Ty);
2954  if (isa<llvm::VectorType>(IRType) ||
2955  IRType->getTypeID() == llvm::Type::FP128TyID)
2956  return IRType;
2957 
2958  // We couldn't find the preferred IR vector type for 'Ty'.
2959  uint64_t Size = getContext().getTypeSize(Ty);
2960  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2961 
2962  // Return a LLVM IR vector type based on the size of 'Ty'.
2963  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2964  Size / 64);
2965 }
2966 
2967 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2968 /// is known to either be off the end of the specified type or being in
2969 /// alignment padding. The user type specified is known to be at most 128 bits
2970 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2971 /// classification that put one of the two halves in the INTEGER class.
2972 ///
2973 /// It is conservatively correct to return false.
2974 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2975  unsigned EndBit, ASTContext &Context) {
2976  // If the bytes being queried are off the end of the type, there is no user
2977  // data hiding here. This handles analysis of builtins, vectors and other
2978  // types that don't contain interesting padding.
2979  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2980  if (TySize <= StartBit)
2981  return true;
2982 
2983  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2984  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2985  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2986 
2987  // Check each element to see if the element overlaps with the queried range.
2988  for (unsigned i = 0; i != NumElts; ++i) {
2989  // If the element is after the span we care about, then we're done..
2990  unsigned EltOffset = i*EltSize;
2991  if (EltOffset >= EndBit) break;
2992 
2993  unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2994  if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2995  EndBit-EltOffset, Context))
2996  return false;
2997  }
2998  // If it overlaps no elements, then it is safe to process as padding.
2999  return true;
3000  }
3001 
3002  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3003  const RecordDecl *RD = RT->getDecl();
3004  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3005 
3006  // If this is a C++ record, check the bases first.
3007  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3008  for (const auto &I : CXXRD->bases()) {
3009  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3010  "Unexpected base class!");
3011  const CXXRecordDecl *Base =
3012  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3013 
3014  // If the base is after the span we care about, ignore it.
3015  unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3016  if (BaseOffset >= EndBit) continue;
3017 
3018  unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3019  if (!BitsContainNoUserData(I.getType(), BaseStart,
3020  EndBit-BaseOffset, Context))
3021  return false;
3022  }
3023  }
3024 
3025  // Verify that no field has data that overlaps the region of interest. Yes
3026  // this could be sped up a lot by being smarter about queried fields,
3027  // however we're only looking at structs up to 16 bytes, so we don't care
3028  // much.
3029  unsigned idx = 0;
3030  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3031  i != e; ++i, ++idx) {
3032  unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3033 
3034  // If we found a field after the region we care about, then we're done.
3035  if (FieldOffset >= EndBit) break;
3036 
3037  unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3038  if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3039  Context))
3040  return false;
3041  }
3042 
3043  // If nothing in this record overlapped the area of interest, then we're
3044  // clean.
3045  return true;
3046  }
3047 
3048  return false;
3049 }
3050 
3051 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3052 /// float member at the specified offset. For example, {int,{float}} has a
3053 /// float at offset 4. It is conservatively correct for this routine to return
3054 /// false.
3055 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3056  const llvm::DataLayout &TD) {
3057  // Base case if we find a float.
3058  if (IROffset == 0 && IRType->isFloatTy())
3059  return true;
3060 
3061  // If this is a struct, recurse into the field at the specified offset.
3062  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3063  const llvm::StructLayout *SL = TD.getStructLayout(STy);
3064  unsigned Elt = SL->getElementContainingOffset(IROffset);
3065  IROffset -= SL->getElementOffset(Elt);
3066  return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3067  }
3068 
3069  // If this is an array, recurse into the field at the specified offset.
3070  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3071  llvm::Type *EltTy = ATy->getElementType();
3072  unsigned EltSize = TD.getTypeAllocSize(EltTy);
3073  IROffset -= IROffset/EltSize*EltSize;
3074  return ContainsFloatAtOffset(EltTy, IROffset, TD);
3075  }
3076 
3077  return false;
3078 }
3079 
3080 
3081 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3082 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3083 llvm::Type *X86_64ABIInfo::
3084 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3085  QualType SourceTy, unsigned SourceOffset) const {
3086  // The only three choices we have are either double, <2 x float>, or float. We
3087  // pass as float if the last 4 bytes is just padding. This happens for
3088  // structs that contain 3 floats.
3089  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3090  SourceOffset*8+64, getContext()))
3091  return llvm::Type::getFloatTy(getVMContext());
3092 
3093  // We want to pass as <2 x float> if the LLVM IR type contains a float at
3094  // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3095  // case.
3096  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3097  ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3098  return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3099 
3100  return llvm::Type::getDoubleTy(getVMContext());
3101 }
3102 
3103 
3104 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3105 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3106 /// about the high or low part of an up-to-16-byte struct. This routine picks
3107 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3108 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3109 /// etc).
3110 ///
3111 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3112 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3113 /// the 8-byte value references. PrefType may be null.
3114 ///
3115 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3116 /// an offset into this that we're processing (which is always either 0 or 8).
3117 ///
3118 llvm::Type *X86_64ABIInfo::
3119 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3120  QualType SourceTy, unsigned SourceOffset) const {
3121  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3122  // returning an 8-byte unit starting with it. See if we can safely use it.
3123  if (IROffset == 0) {
3124  // Pointers and int64's always fill the 8-byte unit.
3125  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3126  IRType->isIntegerTy(64))
3127  return IRType;
3128 
3129  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3130  // goodness in the source type is just tail padding. This is allowed to
3131  // kick in for struct {double,int} on the int, but not on
3132  // struct{double,int,int} because we wouldn't return the second int. We
3133  // have to do this analysis on the source type because we can't depend on
3134  // unions being lowered a specific way etc.
3135  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3136  IRType->isIntegerTy(32) ||
3137  (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3138  unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3139  cast<llvm::IntegerType>(IRType)->getBitWidth();
3140 
3141  if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3142  SourceOffset*8+64, getContext()))
3143  return IRType;
3144  }
3145  }
3146 
3147  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3148  // If this is a struct, recurse into the field at the specified offset.
3149  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3150  if (IROffset < SL->getSizeInBytes()) {
3151  unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3152  IROffset -= SL->getElementOffset(FieldIdx);
3153 
3154  return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3155  SourceTy, SourceOffset);
3156  }
3157  }
3158 
3159  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3160  llvm::Type *EltTy = ATy->getElementType();
3161  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3162  unsigned EltOffset = IROffset/EltSize*EltSize;
3163  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3164  SourceOffset);
3165  }
3166 
3167  // Okay, we don't have any better idea of what to pass, so we pass this in an
3168  // integer register that isn't too big to fit the rest of the struct.
3169  unsigned TySizeInBytes =
3170  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3171 
3172  assert(TySizeInBytes != SourceOffset && "Empty field?");
3173 
3174  // It is always safe to classify this as an integer type up to i64 that
3175  // isn't larger than the structure.
3176  return llvm::IntegerType::get(getVMContext(),
3177  std::min(TySizeInBytes-SourceOffset, 8U)*8);
3178 }
3179 
3180 
3181 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3182 /// be used as elements of a two register pair to pass or return, return a
3183 /// first class aggregate to represent them. For example, if the low part of
3184 /// a by-value argument should be passed as i32* and the high part as float,
3185 /// return {i32*, float}.
3186 static llvm::Type *
3188  const llvm::DataLayout &TD) {
3189  // In order to correctly satisfy the ABI, we need to the high part to start
3190  // at offset 8. If the high and low parts we inferred are both 4-byte types
3191  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3192  // the second element at offset 8. Check for this:
3193  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3194  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3195  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3196  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3197 
3198  // To handle this, we have to increase the size of the low part so that the
3199  // second element will start at an 8 byte offset. We can't increase the size
3200  // of the second element because it might make us access off the end of the
3201  // struct.
3202  if (HiStart != 8) {
3203  // There are usually two sorts of types the ABI generation code can produce
3204  // for the low part of a pair that aren't 8 bytes in size: float or
3205  // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3206  // NaCl).
3207  // Promote these to a larger type.
3208  if (Lo->isFloatTy())
3209  Lo = llvm::Type::getDoubleTy(Lo->getContext());
3210  else {
3211  assert((Lo->isIntegerTy() || Lo->isPointerTy())
3212  && "Invalid/unknown lo type");
3213  Lo = llvm::Type::getInt64Ty(Lo->getContext());
3214  }
3215  }
3216 
3217  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3218 
3219  // Verify that the second element is at an 8-byte offset.
3220  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3221  "Invalid x86-64 argument pair!");
3222  return Result;
3223 }
3224 
3226 classifyReturnType(QualType RetTy) const {
3227  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3228  // classification algorithm.
3229  X86_64ABIInfo::Class Lo, Hi;
3230  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3231 
3232  // Check some invariants.
3233  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3234  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3235 
3236  llvm::Type *ResType = nullptr;
3237  switch (Lo) {
3238  case NoClass:
3239  if (Hi == NoClass)
3240  return ABIArgInfo::getIgnore();
3241  // If the low part is just padding, it takes no register, leave ResType
3242  // null.
3243  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3244  "Unknown missing lo part");
3245  break;
3246 
3247  case SSEUp:
3248  case X87Up:
3249  llvm_unreachable("Invalid classification for lo word.");
3250 
3251  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3252  // hidden argument.
3253  case Memory:
3254  return getIndirectReturnResult(RetTy);
3255 
3256  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3257  // available register of the sequence %rax, %rdx is used.
3258  case Integer:
3259  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3260 
3261  // If we have a sign or zero extended integer, make sure to return Extend
3262  // so that the parameter gets the right LLVM IR attributes.
3263  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3264  // Treat an enum type as its underlying type.
3265  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3266  RetTy = EnumTy->getDecl()->getIntegerType();
3267 
3268  if (RetTy->isIntegralOrEnumerationType() &&
3269  RetTy->isPromotableIntegerType())
3270  return ABIArgInfo::getExtend(RetTy);
3271  }
3272  break;
3273 
3274  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3275  // available SSE register of the sequence %xmm0, %xmm1 is used.
3276  case SSE:
3277  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3278  break;
3279 
3280  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3281  // returned on the X87 stack in %st0 as 80-bit x87 number.
3282  case X87:
3283  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3284  break;
3285 
3286  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3287  // part of the value is returned in %st0 and the imaginary part in
3288  // %st1.
3289  case ComplexX87:
3290  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3291  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3292  llvm::Type::getX86_FP80Ty(getVMContext()));
3293  break;
3294  }
3295 
3296  llvm::Type *HighPart = nullptr;
3297  switch (Hi) {
3298  // Memory was handled previously and X87 should
3299  // never occur as a hi class.
3300  case Memory:
3301  case X87:
3302  llvm_unreachable("Invalid classification for hi word.");
3303 
3304  case ComplexX87: // Previously handled.
3305  case NoClass:
3306  break;
3307 
3308  case Integer:
3309  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3310  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3311  return ABIArgInfo::getDirect(HighPart, 8);
3312  break;
3313  case SSE:
3314  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3315  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3316  return ABIArgInfo::getDirect(HighPart, 8);
3317  break;
3318 
3319  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3320  // is passed in the next available eightbyte chunk if the last used
3321  // vector register.
3322  //
3323  // SSEUP should always be preceded by SSE, just widen.
3324  case SSEUp:
3325  assert(Lo == SSE && "Unexpected SSEUp classification.");
3326  ResType = GetByteVectorType(RetTy);
3327  break;
3328 
3329  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3330  // returned together with the previous X87 value in %st0.
3331  case X87Up:
3332  // If X87Up is preceded by X87, we don't need to do
3333  // anything. However, in some cases with unions it may not be
3334  // preceded by X87. In such situations we follow gcc and pass the
3335  // extra bits in an SSE reg.
3336  if (Lo != X87) {
3337  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3338  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3339  return ABIArgInfo::getDirect(HighPart, 8);
3340  }
3341  break;
3342  }
3343 
3344  // If a high part was specified, merge it together with the low part. It is
3345  // known to pass in the high eightbyte of the result. We do this by forming a
3346  // first class struct aggregate with the high and low part: {low, high}
3347  if (HighPart)
3348  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3349 
3350  return ABIArgInfo::getDirect(ResType);
3351 }
3352 
3354  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3355  bool isNamedArg)
3356  const
3357 {
3359 
3360  X86_64ABIInfo::Class Lo, Hi;
3361  classify(Ty, 0, Lo, Hi, isNamedArg);
3362 
3363  // Check some invariants.
3364  // FIXME: Enforce these by construction.
3365  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3366  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3367 
3368  neededInt = 0;
3369  neededSSE = 0;
3370  llvm::Type *ResType = nullptr;
3371  switch (Lo) {
3372  case NoClass:
3373  if (Hi == NoClass)
3374  return ABIArgInfo::getIgnore();
3375  // If the low part is just padding, it takes no register, leave ResType
3376  // null.
3377  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3378  "Unknown missing lo part");
3379  break;
3380 
3381  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3382  // on the stack.
3383  case Memory:
3384 
3385  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3386  // COMPLEX_X87, it is passed in memory.
3387  case X87:
3388  case ComplexX87:
3390  ++neededInt;
3391  return getIndirectResult(Ty, freeIntRegs);
3392 
3393  case SSEUp:
3394  case X87Up:
3395  llvm_unreachable("Invalid classification for lo word.");
3396 
3397  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3398  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3399  // and %r9 is used.
3400  case Integer:
3401  ++neededInt;
3402 
3403  // Pick an 8-byte type based on the preferred type.
3404  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3405 
3406  // If we have a sign or zero extended integer, make sure to return Extend
3407  // so that the parameter gets the right LLVM IR attributes.
3408  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3409  // Treat an enum type as its underlying type.
3410  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3411  Ty = EnumTy->getDecl()->getIntegerType();
3412 
3413  if (Ty->isIntegralOrEnumerationType() &&
3415  return ABIArgInfo::getExtend(Ty);
3416  }
3417 
3418  break;
3419 
3420  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3421  // available SSE register is used, the registers are taken in the
3422  // order from %xmm0 to %xmm7.
3423  case SSE: {
3424  llvm::Type *IRType = CGT.ConvertType(Ty);
3425  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3426  ++neededSSE;
3427  break;
3428  }
3429  }
3430 
3431  llvm::Type *HighPart = nullptr;
3432  switch (Hi) {
3433  // Memory was handled previously, ComplexX87 and X87 should
3434  // never occur as hi classes, and X87Up must be preceded by X87,
3435  // which is passed in memory.
3436  case Memory:
3437  case X87:
3438  case ComplexX87:
3439  llvm_unreachable("Invalid classification for hi word.");
3440 
3441  case NoClass: break;
3442 
3443  case Integer:
3444  ++neededInt;
3445  // Pick an 8-byte type based on the preferred type.
3446  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3447 
3448  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3449  return ABIArgInfo::getDirect(HighPart, 8);
3450  break;
3451 
3452  // X87Up generally doesn't occur here (long double is passed in
3453  // memory), except in situations involving unions.
3454  case X87Up:
3455  case SSE:
3456  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3457 
3458  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3459  return ABIArgInfo::getDirect(HighPart, 8);
3460 
3461  ++neededSSE;
3462  break;
3463 
3464  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3465  // eightbyte is passed in the upper half of the last used SSE
3466  // register. This only happens when 128-bit vectors are passed.
3467  case SSEUp:
3468  assert(Lo == SSE && "Unexpected SSEUp classification");
3469  ResType = GetByteVectorType(Ty);
3470  break;
3471  }
3472 
3473  // If a high part was specified, merge it together with the low part. It is
3474  // known to pass in the high eightbyte of the result. We do this by forming a
3475  // first class struct aggregate with the high and low part: {low, high}
3476  if (HighPart)
3477  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3478 
3479  return ABIArgInfo::getDirect(ResType);
3480 }
3481 
3482 ABIArgInfo
3483 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3484  unsigned &NeededSSE) const {
3485  auto RT = Ty->getAs<RecordType>();
3486  assert(RT && "classifyRegCallStructType only valid with struct types");
3487 
3488  if (RT->getDecl()->hasFlexibleArrayMember())
3489  return getIndirectReturnResult(Ty);
3490 
3491  // Sum up bases
3492  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3493  if (CXXRD->isDynamicClass()) {
3494  NeededInt = NeededSSE = 0;
3495  return getIndirectReturnResult(Ty);
3496  }
3497 
3498  for (const auto &I : CXXRD->bases())
3499  if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3500  .isIndirect()) {
3501  NeededInt = NeededSSE = 0;
3502  return getIndirectReturnResult(Ty);
3503  }
3504  }
3505 
3506  // Sum up members
3507  for (const auto *FD : RT->getDecl()->fields()) {
3508  if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3509  if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3510  .isIndirect()) {
3511  NeededInt = NeededSSE = 0;
3512  return getIndirectReturnResult(Ty);
3513  }
3514  } else {
3515  unsigned LocalNeededInt, LocalNeededSSE;
3516  if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3517  LocalNeededSSE, true)
3518  .isIndirect()) {
3519  NeededInt = NeededSSE = 0;
3520  return getIndirectReturnResult(Ty);
3521  }
3522  NeededInt += LocalNeededInt;
3523  NeededSSE += LocalNeededSSE;
3524  }
3525  }
3526 
3527  return ABIArgInfo::getDirect();
3528 }
3529 
3530 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3531  unsigned &NeededInt,
3532  unsigned &NeededSSE) const {
3533 
3534  NeededInt = 0;
3535  NeededSSE = 0;
3536 
3537  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3538 }
3539 
3540 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3541 
3542  const unsigned CallingConv = FI.getCallingConvention();
3543  // It is possible to force Win64 calling convention on any x86_64 target by
3544  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3545  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3546  if (CallingConv == llvm::CallingConv::Win64) {
3547  WinX86_64ABIInfo Win64ABIInfo(CGT);
3548  Win64ABIInfo.computeInfo(FI);
3549  return;
3550  }
3551 
3552  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3553 
3554  // Keep track of the number of assigned registers.
3555  unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3556  unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3557  unsigned NeededInt, NeededSSE;
3558 
3559  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3560  if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3561  !FI.getReturnType()->getTypePtr()->isUnionType()) {
3562  FI.getReturnInfo() =
3563  classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3564  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3565  FreeIntRegs -= NeededInt;
3566  FreeSSERegs -= NeededSSE;
3567  } else {
3568  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3569  }
3570  } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3571  // Complex Long Double Type is passed in Memory when Regcall
3572  // calling convention is used.
3573  const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3576  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3577  } else
3579  }
3580 
3581  // If the return value is indirect, then the hidden argument is consuming one
3582  // integer register.
3583  if (FI.getReturnInfo().isIndirect())
3584  --FreeIntRegs;
3585 
3586  // The chain argument effectively gives us another free register.
3587  if (FI.isChainCall())
3588  ++FreeIntRegs;
3589 
3590  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3591  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3592  // get assigned (in left-to-right order) for passing as follows...
3593  unsigned ArgNo = 0;
3594  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3595  it != ie; ++it, ++ArgNo) {
3596  bool IsNamedArg = ArgNo < NumRequiredArgs;
3597 
3598  if (IsRegCall && it->type->isStructureOrClassType())
3599  it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3600  else
3601  it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3602  NeededSSE, IsNamedArg);
3603 
3604  // AMD64-ABI 3.2.3p3: If there are no registers available for any
3605  // eightbyte of an argument, the whole argument is passed on the
3606  // stack. If registers have already been assigned for some
3607  // eightbytes of such an argument, the assignments get reverted.
3608  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3609  FreeIntRegs -= NeededInt;
3610  FreeSSERegs -= NeededSSE;
3611  } else {
3612  it->info = getIndirectResult(it->type, FreeIntRegs);
3613  }
3614  }
3615 }
3616 
3618  Address VAListAddr, QualType Ty) {
3619  Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3620  VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3621  llvm::Value *overflow_arg_area =
3622  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3623 
3624  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3625  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3626  // It isn't stated explicitly in the standard, but in practice we use
3627  // alignment greater than 16 where necessary.
3628  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3629  if (Align > CharUnits::fromQuantity(8)) {
3630  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3631  Align);
3632  }
3633 
3634  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3635  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3636  llvm::Value *Res =
3637  CGF.Builder.CreateBitCast(overflow_arg_area,
3638  llvm::PointerType::getUnqual(LTy));
3639 
3640  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3641  // l->overflow_arg_area + sizeof(type).
3642  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3643  // an 8 byte boundary.
3644 
3645  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3646  llvm::Value *Offset =
3647  llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3648  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3649  "overflow_arg_area.next");
3650  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3651 
3652  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3653  return Address(Res, Align);
3654 }
3655 
3656 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3657  QualType Ty) const {
3658  // Assume that va_list type is correct; should be pointer to LLVM type:
3659  // struct {
3660  // i32 gp_offset;
3661  // i32 fp_offset;
3662  // i8* overflow_arg_area;
3663  // i8* reg_save_area;
3664  // };
3665  unsigned neededInt, neededSSE;
3666 
3667  Ty = getContext().getCanonicalType(Ty);
3668  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3669  /*isNamedArg*/false);
3670 
3671  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3672  // in the registers. If not go to step 7.
3673  if (!neededInt && !neededSSE)
3674  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3675 
3676  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3677  // general purpose registers needed to pass type and num_fp to hold
3678  // the number of floating point registers needed.
3679 
3680  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3681  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3682  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3683  //
3684  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3685  // register save space).
3686 
3687  llvm::Value *InRegs = nullptr;
3688  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3689  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3690  if (neededInt) {
3691  gp_offset_p =
3692  CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3693  "gp_offset_p");
3694  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3695  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3696  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3697  }
3698 
3699  if (neededSSE) {
3700  fp_offset_p =
3701  CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3702  "fp_offset_p");
3703  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3704  llvm::Value *FitsInFP =
3705  llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3706  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3707  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3708  }
3709 
3710  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3711  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3712  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3713  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3714 
3715  // Emit code to load the value if it was passed in registers.
3716 
3717  CGF.EmitBlock(InRegBlock);
3718 
3719  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3720  // an offset of l->gp_offset and/or l->fp_offset. This may require
3721  // copying to a temporary location in case the parameter is passed
3722  // in different register classes or requires an alignment greater
3723  // than 8 for general purpose registers and 16 for XMM registers.
3724  //
3725  // FIXME: This really results in shameful code when we end up needing to
3726  // collect arguments from different places; often what should result in a
3727  // simple assembling of a structure from scattered addresses has many more
3728  // loads than necessary. Can we clean this up?
3729  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3730  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3731  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3732  "reg_save_area");
3733 
3734  Address RegAddr = Address::invalid();
3735  if (neededInt && neededSSE) {
3736  // FIXME: Cleanup.
3737  assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3738  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3739  Address Tmp = CGF.CreateMemTemp(Ty);
3740  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3741  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3742  llvm::Type *TyLo = ST->getElementType(0);
3743  llvm::Type *TyHi = ST->getElementType(1);
3744  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3745  "Unexpected ABI info for mixed regs");
3746  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3747  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3748  llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3749  llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3750  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3751  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3752 
3753  // Copy the first element.
3754  // FIXME: Our choice of alignment here and below is probably pessimistic.
3756  TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3757  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3758  CGF.Builder.CreateStore(V,
3759  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3760 
3761  // Copy the second element.
3762  V = CGF.Builder.CreateAlignedLoad(
3763  TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3764  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3766  getDataLayout().getStructLayout(ST)->getElementOffset(1));
3767  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3768 
3769  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3770  } else if (neededInt) {
3771  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3773  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3774 
3775  // Copy to a temporary if necessary to ensure the appropriate alignment.
3776  std::pair<CharUnits, CharUnits> SizeAlign =
3778  uint64_t TySize = SizeAlign.first.getQuantity();
3779  CharUnits TyAlign = SizeAlign.second;
3780 
3781  // Copy into a temporary if the type is more aligned than the
3782  // register save area.
3783  if (TyAlign.getQuantity() > 8) {
3784  Address Tmp = CGF.CreateMemTemp(Ty);
3785  CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3786  RegAddr = Tmp;
3787  }
3788 
3789  } else if (neededSSE == 1) {
3790  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3792  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3793  } else {
3794  assert(neededSSE == 2 && "Invalid number of needed registers!");
3795  // SSE registers are spaced 16 bytes apart in the register save
3796  // area, we need to collect the two eightbytes together.
3797  // The ABI isn't explicit about this, but it seems reasonable
3798  // to assume that the slots are 16-byte aligned, since the stack is
3799  // naturally 16-byte aligned and the prologue is expected to store
3800  // all the SSE registers to the RSA.
3801  Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3803  Address RegAddrHi =
3804  CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3806  llvm::Type *ST = AI.canHaveCoerceToType()
3807  ? AI.getCoerceToType()
3808  : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
3809  llvm::Value *V;
3810  Address Tmp = CGF.CreateMemTemp(Ty);
3811  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3813  RegAddrLo, ST->getStructElementType(0)));
3814  CGF.Builder.CreateStore(V,
3815  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3817  RegAddrHi, ST->getStructElementType(1)));
3818  CGF.Builder.CreateStore(V,
3820 
3821  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3822  }
3823 
3824  // AMD64-ABI 3.5.7p5: Step 5. Set:
3825  // l->gp_offset = l->gp_offset + num_gp * 8
3826  // l->fp_offset = l->fp_offset + num_fp * 16.
3827  if (neededInt) {
3828  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3829  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3830  gp_offset_p);
3831  }
3832  if (neededSSE) {
3833  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3834  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3835  fp_offset_p);
3836  }
3837  CGF.EmitBranch(ContBlock);
3838 
3839  // Emit code to load the value if it was passed in memory.
3840 
3841  CGF.EmitBlock(InMemBlock);
3842  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3843 
3844  // Return the appropriate result.
3845 
3846  CGF.EmitBlock(ContBlock);
3847  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3848  "vaarg.addr");
3849  return ResAddr;
3850 }
3851 
3852 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3853  QualType Ty) const {
3854  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3855  CGF.getContext().getTypeInfoInChars(Ty),
3857  /*allowHigherAlign*/ false);
3858 }
3859 
3860 ABIArgInfo
3861 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3862  const ABIArgInfo &current) const {
3863  // Assumes vectorCall calling convention.
3864  const Type *Base = nullptr;
3865  uint64_t NumElts = 0;
3866 
3867  if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3868  isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3869  FreeSSERegs -= NumElts;
3870  return getDirectX86Hva();
3871  }
3872  return current;
3873 }
3874 
3875 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3876  bool IsReturnType, bool IsVectorCall,
3877  bool IsRegCall) const {
3878 
3879  if (Ty->isVoidType())
3880  return ABIArgInfo::getIgnore();
3881 
3882  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3883  Ty = EnumTy->getDecl()->getIntegerType();
3884 
3885  TypeInfo Info = getContext().getTypeInfo(Ty);
3886  uint64_t Width = Info.Width;
3888 
3889  const RecordType *RT = Ty->getAs<RecordType>();
3890  if (RT) {
3891  if (!IsReturnType) {
3894  }
3895 
3896  if (RT->getDecl()->hasFlexibleArrayMember())
3897  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3898 
3899  }
3900 
3901  const Type *Base = nullptr;
3902  uint64_t NumElts = 0;
3903  // vectorcall adds the concept of a homogenous vector aggregate, similar to
3904  // other targets.
3905  if ((IsVectorCall || IsRegCall) &&
3906  isHomogeneousAggregate(Ty, Base, NumElts)) {
3907  if (IsRegCall) {
3908  if (FreeSSERegs >= NumElts) {
3909  FreeSSERegs -= NumElts;
3910  if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3911  return ABIArgInfo::getDirect();
3912  return ABIArgInfo::getExpand();
3913  }
3914  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3915  } else if (IsVectorCall) {
3916  if (FreeSSERegs >= NumElts &&
3917  (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3918  FreeSSERegs -= NumElts;
3919  return ABIArgInfo::getDirect();
3920  } else if (IsReturnType) {
3921  return ABIArgInfo::getExpand();
3922  } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3923  // HVAs are delayed and reclassified in the 2nd step.
3924  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3925  }
3926  }
3927  }
3928 
3929  if (Ty->isMemberPointerType()) {
3930  // If the member pointer is represented by an LLVM int or ptr, pass it
3931  // directly.
3932  llvm::Type *LLTy = CGT.ConvertType(Ty);
3933  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3934  return ABIArgInfo::getDirect();
3935  }
3936 
3937  if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3938  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3939  // not 1, 2, 4, or 8 bytes, must be passed by reference."
3940  if (Width > 64 || !llvm::isPowerOf2_64(Width))
3941  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3942 
3943  // Otherwise, coerce it to a small integer.
3944  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3945  }
3946 
3947  // Bool type is always extended to the ABI, other builtin types are not
3948  // extended.
3949  const BuiltinType *BT = Ty->getAs<BuiltinType>();
3950  if (BT && BT->getKind() == BuiltinType::Bool)
3951  return ABIArgInfo::getExtend(Ty);
3952 
3953  // Mingw64 GCC uses the old 80 bit extended precision floating point unit. It
3954  // passes them indirectly through memory.
3955  if (IsMingw64 && BT && BT->getKind() == BuiltinType::LongDouble) {
3956  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3957  if (LDF == &llvm::APFloat::x87DoubleExtended())
3958  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3959  }
3960 
3961  return ABIArgInfo::getDirect();
3962 }
3963 
3964 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3965  unsigned FreeSSERegs,
3966  bool IsVectorCall,
3967  bool IsRegCall) const {
3968  unsigned Count = 0;
3969  for (auto &I : FI.arguments()) {
3970  // Vectorcall in x64 only permits the first 6 arguments to be passed
3971  // as XMM/YMM registers.
3972  if (Count < VectorcallMaxParamNumAsReg)
3973  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
3974  else {
3975  // Since these cannot be passed in registers, pretend no registers
3976  // are left.
3977  unsigned ZeroSSERegsAvail = 0;
3978  I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
3979  IsVectorCall, IsRegCall);
3980  }
3981  ++Count;
3982  }
3983 
3984  for (auto &I : FI.arguments()) {
3985  I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
3986  }
3987 }
3988 
3989 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3990  bool IsVectorCall =
3991  FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
3992  bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
3993 
3994  unsigned FreeSSERegs = 0;
3995  if (IsVectorCall) {
3996  // We can use up to 4 SSE return registers with vectorcall.
3997  FreeSSERegs = 4;
3998  } else if (IsRegCall) {
3999  // RegCall gives us 16 SSE registers.
4000  FreeSSERegs = 16;
4001  }
4002 
4003  if (!getCXXABI().classifyReturnType(FI))
4004  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4005  IsVectorCall, IsRegCall);
4006 
4007  if (IsVectorCall) {
4008  // We can use up to 6 SSE register parameters with vectorcall.
4009  FreeSSERegs = 6;
4010  } else if (IsRegCall) {
4011  // RegCall gives us 16 SSE registers, we can reuse the return registers.
4012  FreeSSERegs = 16;
4013  }
4014 
4015  if (IsVectorCall) {
4016  computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4017  } else {
4018  for (auto &I : FI.arguments())
4019  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4020  }
4021 
4022 }
4023 
4024 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4025  QualType Ty) const {
4026 
4027  bool IsIndirect = false;
4028 
4029  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4030  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4031  if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
4032  uint64_t Width = getContext().getTypeSize(Ty);
4033  IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4034  }
4035 
4036  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4037  CGF.getContext().getTypeInfoInChars(Ty),
4039  /*allowHigherAlign*/ false);
4040 }
4041 
4042 // PowerPC-32
4043 namespace {
4044 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4045 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4046  bool IsSoftFloatABI;
4047 
4048  CharUnits getParamTypeAlignment(QualType Ty) const;
4049 
4050 public:
4051  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4052  : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4053 
4054  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4055  QualType Ty) const override;
4056 };
4057 
4058 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4059 public:
4060  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4061  : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4062 
4063  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4064  // This is recovered from gcc output.
4065  return 1; // r1 is the dedicated stack pointer
4066  }
4067 
4068  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4069  llvm::Value *Address) const override;
4070 };
4071 }
4072 
4073 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4074  // Complex types are passed just like their elements
4075  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4076  Ty = CTy->getElementType();
4077 
4078  if (Ty->isVectorType())
4079  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4080  : 4);
4081 
4082  // For single-element float/vector structs, we consider the whole type
4083  // to have the same alignment requirements as its single element.
4084  const Type *AlignTy = nullptr;
4085  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4086  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4087  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4088  (BT && BT->isFloatingPoint()))
4089  AlignTy = EltType;
4090  }
4091 
4092  if (AlignTy)
4093  return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4094  return CharUnits::fromQuantity(4);
4095 }
4096 
4097 // TODO: this implementation is now likely redundant with
4098 // DefaultABIInfo::EmitVAArg.
4099 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4100  QualType Ty) const {
4101  if (getTarget().getTriple().isOSDarwin()) {
4102  auto TI = getContext().getTypeInfoInChars(Ty);
4103  TI.second = getParamTypeAlignment(Ty);
4104 
4105  CharUnits SlotSize = CharUnits::fromQuantity(4);
4106  return emitVoidPtrVAArg(CGF, VAList, Ty,
4107  classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4108  /*AllowHigherAlign=*/true);
4109  }
4110 
4111  const unsigned OverflowLimit = 8;
4112  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4113  // TODO: Implement this. For now ignore.
4114  (void)CTy;
4115  return Address::invalid(); // FIXME?
4116  }
4117 
4118  // struct __va_list_tag {
4119  // unsigned char gpr;
4120  // unsigned char fpr;
4121  // unsigned short reserved;
4122  // void *overflow_arg_area;
4123  // void *reg_save_area;
4124  // };
4125 
4126  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4127  bool isInt =
4128  Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4129  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4130 
4131  // All aggregates are passed indirectly? That doesn't seem consistent
4132  // with the argument-lowering code.
4133  bool isIndirect = Ty->isAggregateType();
4134 
4135  CGBuilderTy &Builder = CGF.Builder;
4136 
4137  // The calling convention either uses 1-2 GPRs or 1 FPR.
4138  Address NumRegsAddr = Address::invalid();
4139  if (isInt || IsSoftFloatABI) {
4140  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
4141  } else {
4142  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
4143  }
4144 
4145  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4146 
4147  // "Align" the register count when TY is i64.
4148  if (isI64 || (isF64 && IsSoftFloatABI)) {
4149  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4150  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4151  }
4152 
4153  llvm::Value *CC =
4154  Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4155 
4156  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4157  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4158  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4159 
4160  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4161 
4162  llvm::Type *DirectTy = CGF.ConvertType(Ty);
4163  if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4164 
4165  // Case 1: consume registers.
4166  Address RegAddr = Address::invalid();
4167  {
4168  CGF.EmitBlock(UsingRegs);
4169 
4170  Address RegSaveAreaPtr =
4171  Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
4172  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4174  assert(RegAddr.getElementType() == CGF.Int8Ty);
4175 
4176  // Floating-point registers start after the general-purpose registers.
4177  if (!(isInt || IsSoftFloatABI)) {
4178  RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4180  }
4181 
4182  // Get the address of the saved value by scaling the number of
4183  // registers we've used by the number of
4184  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4185  llvm::Value *RegOffset =
4186  Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4187  RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4188  RegAddr.getPointer(), RegOffset),
4189  RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4190  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4191 
4192  // Increase the used-register count.
4193  NumRegs =
4194  Builder.CreateAdd(NumRegs,
4195  Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4196  Builder.CreateStore(NumRegs, NumRegsAddr);
4197 
4198  CGF.EmitBranch(Cont);
4199  }
4200 
4201  // Case 2: consume space in the overflow area.
4202  Address MemAddr = Address::invalid();
4203  {
4204  CGF.EmitBlock(UsingOverflow);
4205 
4206  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4207 
4208  // Everything in the overflow area is rounded up to a size of at least 4.
4209  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4210 
4211  CharUnits Size;
4212  if (!isIndirect) {
4213  auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4214  Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4215  } else {
4216  Size = CGF.getPointerSize();
4217  }
4218 
4219  Address OverflowAreaAddr =
4220  Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
4221  Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4222  OverflowAreaAlign);
4223  // Round up address of argument to alignment
4224  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4225  if (Align > OverflowAreaAlign) {
4226  llvm::Value *Ptr = OverflowArea.getPointer();
4227  OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4228  Align);
4229  }
4230 
4231  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4232 
4233  // Increase the overflow area.
4234  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4235  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4236  CGF.EmitBranch(Cont);
4237  }
4238 
4239  CGF.EmitBlock(Cont);
4240 
4241  // Merge the cases with a phi.
4242  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4243  "vaarg.addr");
4244 
4245  // Load the pointer if the argument was passed indirectly.
4246  if (isIndirect) {
4247  Result = Address(Builder.CreateLoad(Result, "aggr"),
4249  }
4250 
4251  return Result;
4252 }
4253 
4254 bool
4255 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4256  llvm::Value *Address) const {
4257  // This is calculated from the LLVM and GCC tables and verified
4258  // against gcc output. AFAIK all ABIs use the same encoding.
4259 
4260  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4261 
4262  llvm::IntegerType *i8 = CGF.Int8Ty;
4263  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4264  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4265  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4266 
4267  // 0-31: r0-31, the 4-byte general-purpose registers
4268  AssignToArrayRange(Builder, Address, Four8, 0, 31);
4269 
4270  // 32-63: fp0-31, the 8-byte floating-point registers
4271  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4272 
4273  // 64-76 are various 4-byte special-purpose registers:
4274  // 64: mq
4275  // 65: lr
4276  // 66: ctr
4277  // 67: ap
4278  // 68-75 cr0-7
4279  // 76: xer
4280  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4281 
4282  // 77-108: v0-31, the 16-byte vector registers
4283  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4284 
4285  // 109: vrsave
4286  // 110: vscr
4287  // 111: spe_acc
4288  // 112: spefscr
4289  // 113: sfp
4290  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4291 
4292  return false;
4293 }
4294 
4295 // PowerPC-64
4296 
4297 namespace {
4298 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4299 class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4300 public:
4301  enum ABIKind {
4302  ELFv1 = 0,
4303  ELFv2
4304  };
4305 
4306 private:
4307  static const unsigned GPRBits = 64;
4308  ABIKind Kind;
4309  bool HasQPX;
4310  bool IsSoftFloatABI;
4311 
4312  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4313  // will be passed in a QPX register.
4314  bool IsQPXVectorTy(const Type *Ty) const {
4315  if (!HasQPX)
4316  return false;
4317 
4318  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4319  unsigned NumElements = VT->getNumElements();
4320  if (NumElements == 1)
4321  return false;
4322 
4323  if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4324  if (getContext().getTypeSize(Ty) <= 256)
4325  return true;
4326  } else if (VT->getElementType()->
4327  isSpecificBuiltinType(BuiltinType::Float)) {
4328  if (getContext().getTypeSize(Ty) <= 128)
4329  return true;
4330  }
4331  }
4332 
4333  return false;
4334  }
4335 
4336  bool IsQPXVectorTy(QualType Ty) const {
4337  return IsQPXVectorTy(Ty.getTypePtr());
4338  }
4339 
4340 public:
4341  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4342  bool SoftFloatABI)
4343  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4344  IsSoftFloatABI(SoftFloatABI) {}
4345 
4346  bool isPromotableTypeForABI(QualType Ty) const;
4347  CharUnits getParamTypeAlignment(QualType Ty) const;
4348 
4349  ABIArgInfo classifyReturnType(QualType RetTy) const;
4351 
4352  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4353  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4354  uint64_t Members) const override;
4355 
4356  // TODO: We can add more logic to computeInfo to improve performance.
4357  // Example: For aggregate arguments that fit in a register, we could
4358  // use getDirectInReg (as is done below for structs containing a single
4359  // floating-point value) to avoid pushing them to memory on function
4360  // entry. This would require changing the logic in PPCISelLowering
4361  // when lowering the parameters in the caller and args in the callee.
4362  void computeInfo(CGFunctionInfo &FI) const override {
4363  if (!getCXXABI().classifyReturnType(FI))
4365  for (auto &I : FI.arguments()) {
4366  // We rely on the default argument classification for the most part.
4367  // One exception: An aggregate containing a single floating-point
4368  // or vector item must be passed in a register if one is available.
4369  const Type *T = isSingleElementStruct(I.type, getContext());
4370  if (T) {
4371  const BuiltinType *BT = T->getAs<BuiltinType>();
4372  if (IsQPXVectorTy(T) ||
4373  (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4374  (BT && BT->isFloatingPoint())) {
4375  QualType QT(T, 0);
4376  I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4377  continue;
4378  }
4379  }
4380  I.info = classifyArgumentType(I.type);
4381  }
4382  }
4383 
4384  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4385  QualType Ty) const override;
4386 
4387  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4388  bool asReturnValue) const override {
4389  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4390  }
4391 
4392  bool isSwiftErrorInRegister() const override {
4393  return false;
4394  }
4395 };
4396 
4397 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4398 
4399 public:
4400  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4401  PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4402  bool SoftFloatABI)
4403  : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4404  SoftFloatABI)) {}
4405 
4406  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4407  // This is recovered from gcc output.
4408  return 1; // r1 is the dedicated stack pointer
4409  }
4410 
4411  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4412  llvm::Value *Address) const override;
4413 };
4414 
4415 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4416 public:
4417  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4418 
4419  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4420  // This is recovered from gcc output.
4421  return 1; // r1 is the dedicated stack pointer
4422  }
4423 
4424  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4425  llvm::Value *Address) const override;
4426 };
4427 
4428 }
4429 
4430 // Return true if the ABI requires Ty to be passed sign- or zero-
4431 // extended to 64 bits.
4432 bool
4433 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4434  // Treat an enum type as its underlying type.
4435  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4436  Ty = EnumTy->getDecl()->getIntegerType();
4437 
4438  // Promotable integer types are required to be promoted by the ABI.
4439  if (Ty->isPromotableIntegerType())
4440  return true;
4441 
4442  // In addition to the usual promotable integer types, we also need to
4443  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4444  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4445  switch (BT->getKind()) {
4446  case BuiltinType::Int:
4447  case BuiltinType::UInt:
4448  return true;
4449  default:
4450  break;
4451  }
4452 
4453  return false;
4454 }
4455 
4456 /// isAlignedParamType - Determine whether a type requires 16-byte or
4457 /// higher alignment in the parameter area. Always returns at least 8.
4458 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4459  // Complex types are passed just like their elements.
4460  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4461  Ty = CTy->getElementType();
4462 
4463  // Only vector types of size 16 bytes need alignment (larger types are
4464  // passed via reference, smaller types are not aligned).
4465  if (IsQPXVectorTy(Ty)) {
4466  if (getContext().getTypeSize(Ty) > 128)
4467  return CharUnits::fromQuantity(32);
4468 
4469  return CharUnits::fromQuantity(16);
4470  } else if (Ty->isVectorType()) {
4471  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4472  }
4473 
4474  // For single-element float/vector structs, we consider the whole type
4475  // to have the same alignment requirements as its single element.
4476  const Type *AlignAsType = nullptr;
4477  const Type *EltType = isSingleElementStruct(Ty, getContext());
4478  if (EltType) {
4479  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4480  if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4481  getContext().getTypeSize(EltType) == 128) ||
4482  (BT && BT->isFloatingPoint()))
4483  AlignAsType = EltType;
4484  }
4485 
4486  // Likewise for ELFv2 homogeneous aggregates.
4487  const Type *Base = nullptr;
4488  uint64_t Members = 0;
4489  if (!AlignAsType && Kind == ELFv2 &&
4490  isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4491  AlignAsType = Base;
4492 
4493  // With special case aggregates, only vector base types need alignment.
4494  if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4495  if (getContext().getTypeSize(AlignAsType) > 128)
4496  return CharUnits::fromQuantity(32);
4497 
4498  return CharUnits::fromQuantity(16);
4499  } else if (AlignAsType) {
4500  return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4501  }
4502 
4503  // Otherwise, we only need alignment for any aggregate type that
4504  // has an alignment requirement of >= 16 bytes.
4505  if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4506  if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4507  return CharUnits::fromQuantity(32);
4508  return CharUnits::fromQuantity(16);
4509  }
4510 
4511  return CharUnits::fromQuantity(8);
4512 }
4513 
4514 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4515 /// aggregate. Base is set to the base element type, and Members is set
4516 /// to the number of base elements.
4518  uint64_t &Members) const {
4519  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4520  uint64_t NElements = AT->getSize().getZExtValue();
4521  if (NElements == 0)
4522  return false;
4523  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4524  return false;
4525  Members *= NElements;
4526  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4527  const RecordDecl *RD = RT->getDecl();
4528  if (RD->hasFlexibleArrayMember())
4529  return false;
4530 
4531  Members = 0;
4532 
4533  // If this is a C++ record, check the bases first.
4534  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4535  for (const auto &I : CXXRD->bases()) {
4536  // Ignore empty records.
4537  if (isEmptyRecord(getContext(), I.getType(), true))
4538  continue;
4539 
4540  uint64_t FldMembers;
4541  if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4542  return false;
4543 
4544  Members += FldMembers;
4545  }
4546  }
4547 
4548  for (const auto *FD : RD->fields()) {
4549  // Ignore (non-zero arrays of) empty records.
4550  QualType FT = FD->getType();
4551  while (const ConstantArrayType *AT =
4552  getContext().getAsConstantArrayType(FT)) {
4553  if (AT->getSize().getZExtValue() == 0)
4554  return false;
4555  FT = AT->getElementType();
4556  }
4557  if (isEmptyRecord(getContext(), FT, true))
4558  continue;
4559 
4560  // For compatibility with GCC, ignore empty bitfields in C++ mode.
4561  if (getContext().getLangOpts().CPlusPlus &&
4562  FD->isZeroLengthBitField(getContext()))
4563  continue;
4564 
4565  uint64_t FldMembers;
4566  if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4567  return false;
4568 
4569  Members = (RD->isUnion() ?
4570  std::max(Members, FldMembers) : Members + FldMembers);
4571  }
4572 
4573  if (!Base)
4574  return false;
4575 
4576  // Ensure there is no padding.
4577  if (getContext().getTypeSize(Base) * Members !=
4578  getContext().getTypeSize(Ty))
4579  return false;
4580  } else {
4581  Members = 1;
4582  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4583  Members = 2;
4584  Ty = CT->getElementType();
4585  }
4586 
4587  // Most ABIs only support float, double, and some vector type widths.
4589  return false;
4590 
4591  // The base type must be the same for all members. Types that
4592  // agree in both total size and mode (float vs. vector) are
4593  // treated as being equivalent here.
4594  const Type *TyPtr = Ty.getTypePtr();
4595  if (!Base) {
4596  Base = TyPtr;
4597  // If it's a non-power-of-2 vector, its size is already a power-of-2,
4598  // so make sure to widen it explicitly.
4599  if (const VectorType *VT = Base->getAs<VectorType>()) {
4600  QualType EltTy = VT->getElementType();
4601  unsigned NumElements =
4602  getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4603  Base = getContext()
4604  .getVectorType(EltTy, NumElements, VT->getVectorKind())
4605  .getTypePtr();
4606  }
4607  }
4608 
4609  if (Base->isVectorType() != TyPtr->isVectorType() ||
4610  getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4611  return false;
4612  }
4613  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4614 }
4615 
4616 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4617  // Homogeneous aggregates for ELFv2 must have base types of float,
4618  // double, long double, or 128-bit vectors.
4619  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4620  if (BT->getKind() == BuiltinType::Float ||
4621  BT->getKind() == BuiltinType::Double ||
4622  BT->getKind() == BuiltinType::LongDouble ||
4624  (BT->getKind() == BuiltinType::Float128))) {
4625  if (IsSoftFloatABI)
4626  return false;
4627  return true;
4628  }
4629  }
4630  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4631  if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4632  return true;
4633  }
4634  return false;
4635 }
4636 
4637 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4638  const Type *Base, uint64_t Members) const {
4639  // Vector and fp128 types require one register, other floating point types
4640  // require one or two registers depending on their size.
4641  uint32_t NumRegs =
4643  Base->isFloat128Type()) ||
4644  Base->isVectorType()) ? 1
4645  : (getContext().getTypeSize(Base) + 63) / 64;
4646 
4647  // Homogeneous Aggregates may occupy at most 8 registers.
4648  return Members * NumRegs <= 8;
4649 }
4650 
4651 ABIArgInfo
4654 
4655  if (Ty->isAnyComplexType())
4656  return ABIArgInfo::getDirect();
4657 
4658  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4659  // or via reference (larger than 16 bytes).
4660  if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4661  uint64_t Size = getContext().getTypeSize(Ty);
4662  if (Size > 128)
4663  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4664  else if (Size < 128) {
4665  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4666  return ABIArgInfo::getDirect(CoerceTy);
4667  }
4668  }
4669 
4670  if (isAggregateTypeForABI(Ty)) {
4673 
4674  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4675  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4676 
4677  // ELFv2 homogeneous aggregates are passed as array types.
4678  const Type *Base = nullptr;
4679  uint64_t Members = 0;
4680  if (Kind == ELFv2 &&
4681  isHomogeneousAggregate(Ty, Base, Members)) {
4682  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4683  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4684  return ABIArgInfo::getDirect(CoerceTy);
4685  }
4686 
4687  // If an aggregate may end up fully in registers, we do not
4688  // use the ByVal method, but pass the aggregate as array.
4689  // This is usually beneficial since we avoid forcing the
4690  // back-end to store the argument to memory.
4691  uint64_t Bits = getContext().getTypeSize(Ty);
4692  if (Bits > 0 && Bits <= 8 * GPRBits) {
4693  llvm::Type *CoerceTy;
4694 
4695  // Types up to 8 bytes are passed as integer type (which will be
4696  // properly aligned in the argument save area doubleword).
4697  if (Bits <= GPRBits)
4698  CoerceTy =
4699  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4700  // Larger types are passed as arrays, with the base type selected
4701  // according to the required alignment in the save area.
4702  else {
4703  uint64_t RegBits = ABIAlign * 8;
4704  uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4705  llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4706  CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4707  }
4708 
4709  return ABIArgInfo::getDirect(CoerceTy);
4710  }
4711 
4712  // All other aggregates are passed ByVal.
4714  /*ByVal=*/true,
4715  /*Realign=*/TyAlign > ABIAlign);
4716  }
4717 
4718  return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
4719  : ABIArgInfo::getDirect());
4720 }
4721 
4722 ABIArgInfo
4724  if (RetTy->isVoidType())
4725  return ABIArgInfo::getIgnore();
4726 
4727  if (RetTy->isAnyComplexType())
4728  return ABIArgInfo::getDirect();
4729 
4730  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4731  // or via reference (larger than 16 bytes).
4732  if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4733  uint64_t Size = getContext().getTypeSize(RetTy);
4734  if (Size > 128)
4735  return getNaturalAlignIndirect(RetTy);
4736  else if (Size < 128) {
4737  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4738  return ABIArgInfo::getDirect(CoerceTy);
4739  }
4740  }
4741 
4742  if (isAggregateTypeForABI(RetTy)) {
4743  // ELFv2 homogeneous aggregates are returned as array types.
4744  const Type *Base = nullptr;
4745  uint64_t Members = 0;
4746  if (Kind == ELFv2 &&
4747  isHomogeneousAggregate(RetTy, Base, Members)) {
4748  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4749  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4750  return ABIArgInfo::getDirect(CoerceTy);
4751  }
4752 
4753  // ELFv2 small aggregates are returned in up to two registers.
4754  uint64_t Bits = getContext().getTypeSize(RetTy);
4755  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4756  if (Bits == 0)
4757  return ABIArgInfo::getIgnore();
4758 
4759  llvm::Type *CoerceTy;
4760  if (Bits > GPRBits) {
4761  CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4762  CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4763  } else
4764  CoerceTy =
4765  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4766  return ABIArgInfo::getDirect(CoerceTy);
4767  }
4768 
4769  // All other aggregates are returned indirectly.
4770  return getNaturalAlignIndirect(RetTy);
4771  }
4772 
4773  return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
4774  : ABIArgInfo::getDirect());
4775 }
4776 
4777 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4778 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4779  QualType Ty) const {
4780  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4781  TypeInfo.second = getParamTypeAlignment(Ty);
4782 
4783  CharUnits SlotSize = CharUnits::fromQuantity(8);
4784 
4785  // If we have a complex type and the base type is smaller than 8 bytes,
4786  // the ABI calls for the real and imaginary parts to be right-adjusted
4787  // in separate doublewords. However, Clang expects us to produce a
4788  // pointer to a structure with the two parts packed tightly. So generate
4789  // loads of the real and imaginary parts relative to the va_list pointer,
4790  // and store them to a temporary structure.
4791  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4792  CharUnits EltSize = TypeInfo.first / 2;
4793  if (EltSize < SlotSize) {
4794  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4795  SlotSize * 2, SlotSize,
4796  SlotSize, /*AllowHigher*/ true);
4797 
4798  Address RealAddr = Addr;
4799  Address ImagAddr = RealAddr;
4800  if (CGF.CGM.getDataLayout().isBigEndian()) {
4801  RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4802  SlotSize - EltSize);
4803  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4804  2 * SlotSize - EltSize);
4805  } else {
4806  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4807  }
4808 
4809  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4810  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4811  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4812  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4813  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4814 
4815  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4816  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4817  /*init*/ true);
4818  return Temp;
4819  }
4820  }
4821 
4822  // Otherwise, just use the general rule.
4823  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4824  TypeInfo, SlotSize, /*AllowHigher*/ true);
4825 }
4826 
4827 static bool
4829  llvm::Value *Address) {
4830  // This is calculated from the LLVM and GCC tables and verified
4831  // against gcc output. AFAIK all ABIs use the same encoding.
4832 
4833  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4834 
4835  llvm::IntegerType *i8 = CGF.Int8Ty;
4836  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4837  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4838  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4839 
4840  // 0-31: r0-31, the 8-byte general-purpose registers
4841  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4842 
4843  // 32-63: fp0-31, the 8-byte floating-point registers
4844  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4845 
4846  // 64-67 are various 8-byte special-purpose registers:
4847  // 64: mq
4848  // 65: lr
4849  // 66: ctr
4850  // 67: ap
4851  AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4852 
4853  // 68-76 are various 4-byte special-purpose registers:
4854  // 68-75 cr0-7
4855  // 76: xer
4856  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4857 
4858  // 77-108: v0-31, the 16-byte vector registers
4859  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4860 
4861  // 109: vrsave
4862  // 110: vscr
4863  // 111: spe_acc
4864  // 112: spefscr
4865  // 113: sfp
4866  // 114: tfhar
4867  // 115: tfiar
4868  // 116: texasr
4869  AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4870 
4871  return false;
4872 }
4873 
4874 bool
4875 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4877  llvm::Value *Address) const {
4878 
4879  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4880 }
4881 
4882 bool
4883 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4884  llvm::Value *Address) const {
4885 
4886  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4887 }
4888 
4889 //===----------------------------------------------------------------------===//
4890 // AArch64 ABI Implementation
4891 //===----------------------------------------------------------------------===//
4892 
4893 namespace {
4894 
4895 class AArch64ABIInfo : public SwiftABIInfo {
4896 public:
4897  enum ABIKind {
4898  AAPCS = 0,
4899  DarwinPCS,
4900  Win64
4901  };
4902 
4903 private:
4904  ABIKind Kind;
4905 
4906 public:
4907  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4908  : SwiftABIInfo(CGT), Kind(Kind) {}
4909 
4910 private:
4911  ABIKind getABIKind() const { return Kind; }
4912  bool isDarwinPCS() const { return Kind == DarwinPCS; }
4913 
4914  ABIArgInfo classifyReturnType(QualType RetTy) const;
4916  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4917  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4918  uint64_t Members) const override;
4919 
4920  bool isIllegalVectorType(QualType Ty) const;
4921 
4922  void computeInfo(CGFunctionInfo &FI) const override {
4923  if (!::classifyReturnType(getCXXABI(), FI, *this))
4925 
4926  for (auto &it : FI.arguments())
4927  it.info = classifyArgumentType(it.type);
4928  }
4929 
4930  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4931  CodeGenFunction &CGF) const;
4932 
4933  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4934  CodeGenFunction &CGF) const;
4935 
4936  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4937  QualType Ty) const override {
4938  return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4939  : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4940  : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4941  }
4942 
4943  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4944  QualType Ty) const override;
4945 
4946  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4947  bool asReturnValue) const override {
4948  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4949  }
4950  bool isSwiftErrorInRegister() const override {
4951  return true;
4952  }
4953 
4954  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4955  unsigned elts) const override;
4956 };
4957 
4958 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4959 public:
4960  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4961  : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4962 
4963  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4964  return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
4965  }
4966 
4967  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4968  return 31;
4969  }
4970 
4971  bool doesReturnSlotInterfereWithArgs() const override { return false; }
4972 };
4973 
4974 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
4975 public:
4976  WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
4977  : AArch64TargetCodeGenInfo(CGT, K) {}
4978 
4979  void getDependentLibraryOption(llvm::StringRef Lib,
4980  llvm::SmallString<24> &Opt) const override {
4981  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
4982  }
4983 
4984  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
4985  llvm::SmallString<32> &Opt) const override {
4986  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
4987  }
4988 };
4989 }
4990 
4993 
4994  // Handle illegal vector types here.
4995  if (isIllegalVectorType(Ty)) {
4996  uint64_t Size = getContext().getTypeSize(Ty);
4997  // Android promotes <2 x i8> to i16, not i32
4998  if (isAndroid() && (Size <= 16)) {
4999  llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
5000  return ABIArgInfo::getDirect(ResType);
5001  }
5002  if (Size <= 32) {
5003  llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
5004  return ABIArgInfo::getDirect(ResType);
5005  }
5006  if (Size == 64) {
5007  llvm::Type *ResType =
5008  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
5009  return ABIArgInfo::getDirect(ResType);
5010  }
5011  if (Size == 128) {
5012  llvm::Type *ResType =
5013  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
5014  return ABIArgInfo::getDirect(ResType);
5015  }
5016  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5017  }
5018 
5019  if (!isAggregateTypeForABI(Ty)) {
5020  // Treat an enum type as its underlying type.
5021  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5022  Ty = EnumTy->getDecl()->getIntegerType();
5023 
5024  return (Ty->isPromotableIntegerType() && isDarwinPCS()
5025  ? ABIArgInfo::getExtend(Ty)
5026  : ABIArgInfo::getDirect());
5027  }
5028 
5029  // Structures with either a non-trivial destructor or a non-trivial
5030  // copy constructor are always indirect.
5032  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
5034  }
5035 
5036  // Empty records are always ignored on Darwin, but actually passed in C++ mode
5037  // elsewhere for GNU compatibility.
5038  uint64_t Size = getContext().getTypeSize(Ty);
5039  bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5040  if (IsEmpty || Size == 0) {
5041  if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
5042  return ABIArgInfo::getIgnore();
5043 
5044  // GNU C mode. The only argument that gets ignored is an empty one with size
5045  // 0.
5046  if (IsEmpty && Size == 0)
5047  return ABIArgInfo::getIgnore();
5048  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5049  }
5050 
5051  // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5052  const Type *Base = nullptr;
5053  uint64_t Members = 0;
5054  if (isHomogeneousAggregate(Ty, Base, Members)) {
5055  return ABIArgInfo::getDirect(
5056  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5057  }
5058 
5059  // Aggregates <= 16 bytes are passed directly in registers or on the stack.
5060  if (Size <= 128) {
5061  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5062  // same size and alignment.
5063  if (getTarget().isRenderScriptTarget()) {
5064  return coerceToIntArray(Ty, getContext(), getVMContext());
5065  }
5066  unsigned Alignment;
5067  if (Kind == AArch64ABIInfo::AAPCS) {
5068  Alignment = getContext().getTypeUnadjustedAlign(Ty);
5069  Alignment = Alignment < 128 ? 64 : 128;
5070  } else {
5071  Alignment = getContext().getTypeAlign(Ty);
5072  }
5073  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5074 
5075  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5076  // For aggregates with 16-byte alignment, we use i128.
5077  if (Alignment < 128 && Size == 128) {
5078  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5079  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5080  }
5081  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5082  }
5083 
5084  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5085 }
5086 
5088  if (RetTy->isVoidType())
5089  return ABIArgInfo::getIgnore();
5090 
5091  // Large vector types should be returned via memory.
5092  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5093  return getNaturalAlignIndirect(RetTy);
5094 
5095  if (!isAggregateTypeForABI(RetTy)) {
5096  // Treat an enum type as its underlying type.
5097  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5098  RetTy = EnumTy->getDecl()->getIntegerType();
5099 
5100  return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5101  ? ABIArgInfo::getExtend(RetTy)
5102  : ABIArgInfo::getDirect());
5103  }
5104 
5105  uint64_t Size = getContext().getTypeSize(RetTy);
5106  if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
5107  return ABIArgInfo::getIgnore();
5108 
5109  const Type *Base = nullptr;
5110  uint64_t Members = 0;
5111  if (isHomogeneousAggregate(RetTy, Base, Members))
5112  // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5113  return ABIArgInfo::getDirect();
5114 
5115  // Aggregates <= 16 bytes are returned directly in registers or on the stack.
5116  if (Size <= 128) {
5117  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5118  // same size and alignment.
5119  if (getTarget().isRenderScriptTarget()) {
5120  return coerceToIntArray(RetTy, getContext(), getVMContext());
5121  }
5122  unsigned Alignment = getContext().getTypeAlign(RetTy);
5123  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5124 
5125  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5126  // For aggregates with 16-byte alignment, we use i128.
5127  if (Alignment < 128 && Size == 128) {
5128  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5129  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5130  }
5131  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5132  }
5133 
5134  return getNaturalAlignIndirect(RetTy);
5135 }
5136 
5137 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5138 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5139  if (const VectorType *VT = Ty->getAs<VectorType>()) {
5140  // Check whether VT is legal.
5141  unsigned NumElements = VT->getNumElements();
5142  uint64_t Size = getContext().getTypeSize(VT);
5143  // NumElements should be power of 2.
5144  if (!llvm::isPowerOf2_32(NumElements))
5145  return true;
5146  return Size != 64 && (Size != 128 || NumElements == 1);
5147  }
5148  return false;
5149 }
5150 
5151 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5152  llvm::Type *eltTy,
5153  unsigned elts) const {
5154  if (!llvm::isPowerOf2_32(elts))
5155  return false;
5156  if (totalSize.getQuantity() != 8 &&
5157  (totalSize.getQuantity() != 16 || elts == 1))
5158  return false;
5159  return true;
5160 }
5161 
5162 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5163  // Homogeneous aggregates for AAPCS64 must have base types of a floating
5164  // point type or a short-vector type. This is the same as the 32-bit ABI,
5165  // but with the difference that any floating-point type is allowed,
5166  // including __fp16.
5167  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5168  if (BT->isFloatingPoint())
5169  return true;
5170  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5171  unsigned VecSize = getContext().getTypeSize(VT);
5172  if (VecSize == 64 || VecSize == 128)
5173  return true;
5174  }
5175  return false;
5176 }
5177 
5178 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5179  uint64_t Members) const {
5180  return Members <= 4;
5181 }
5182 
5183 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5184  QualType Ty,
5185  CodeGenFunction &CGF) const {
5187  bool IsIndirect = AI.isIndirect();
5188 
5189  llvm::Type *BaseTy = CGF.ConvertType(Ty);
5190  if (IsIndirect)
5191  BaseTy = llvm::PointerType::getUnqual(BaseTy);
5192  else if (AI.getCoerceToType())
5193  BaseTy = AI.getCoerceToType();
5194 
5195  unsigned NumRegs = 1;
5196  if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5197  BaseTy = ArrTy->getElementType();
5198  NumRegs = ArrTy->getNumElements();
5199  }
5200  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5201 
5202  // The AArch64 va_list type and handling is specified in the Procedure Call
5203  // Standard, section B.4:
5204  //
5205  // struct {
5206  // void *__stack;
5207  // void *__gr_top;
5208  // void *__vr_top;
5209  // int __gr_offs;
5210  // int __vr_offs;
5211  // };
5212 
5213  llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5214  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5215  llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5216  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5217 
5218  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5219  CharUnits TyAlign = TyInfo.second;
5220 
5221  Address reg_offs_p = Address::invalid();
5222  llvm::Value *reg_offs = nullptr;
5223  int reg_top_index;
5224  CharUnits reg_top_offset;
5225  int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5226  if (!IsFPR) {
5227  // 3 is the field number of __gr_offs
5228  reg_offs_p =
5229  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5230  "gr_offs_p");
5231  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5232  reg_top_index = 1; // field number for __gr_top
5233  reg_top_offset = CharUnits::fromQuantity(8);
5234  RegSize = llvm::alignTo(RegSize, 8);
5235  } else {
5236  // 4 is the field number of __vr_offs.
5237  reg_offs_p =
5238  CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
5239  "vr_offs_p");
5240  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5241  reg_top_index = 2; // field number for __vr_top
5242  reg_top_offset = CharUnits::fromQuantity(16);
5243  RegSize = 16 * NumRegs;
5244  }
5245 
5246  //=======================================
5247  // Find out where argument was passed
5248  //=======================================
5249 
5250  // If reg_offs >= 0 we're already using the stack for this type of
5251  // argument. We don't want to keep updating reg_offs (in case it overflows,
5252  // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5253  // whatever they get).
5254  llvm::Value *UsingStack = nullptr;
5255  UsingStack = CGF.Builder.CreateICmpSGE(
5256  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5257 
5258  CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5259 
5260  // Otherwise, at least some kind of argument could go in these registers, the
5261  // question is whether this particular type is too big.
5262  CGF.EmitBlock(MaybeRegBlock);
5263 
5264  // Integer arguments may need to correct register alignment (for example a
5265  // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5266  // align __gr_offs to calculate the potential address.
5267  if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5268  int Align = TyAlign.getQuantity();
5269 
5270  reg_offs = CGF.Builder.CreateAdd(
5271  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5272  "align_regoffs");
5273  reg_offs = CGF.Builder.CreateAnd(
5274  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5275  "aligned_regoffs");
5276  }
5277 
5278  // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5279  // The fact that this is done unconditionally reflects the fact that
5280  // allocating an argument to the stack also uses up all the remaining
5281  // registers of the appropriate kind.
5282  llvm::Value *NewOffset = nullptr;
5283  NewOffset = CGF.Builder.CreateAdd(
5284  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5285  CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5286 
5287  // Now we're in a position to decide whether this argument really was in
5288  // registers or not.
5289  llvm::Value *InRegs = nullptr;
5290  InRegs = CGF.Builder.CreateICmpSLE(
5291  NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5292 
5293  CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5294 
5295  //=======================================
5296  // Argument was in registers
5297  //=======================================
5298 
5299  // Now we emit the code for if the argument was originally passed in
5300  // registers. First start the appropriate block:
5301  CGF.EmitBlock(InRegBlock);
5302 
5303  llvm::Value *reg_top = nullptr;
5304  Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
5305  reg_top_offset, "reg_top_p");
5306  reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5307  Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5308  CharUnits::fromQuantity(IsFPR ? 16 : 8));
5309  Address RegAddr = Address::invalid();
5310  llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5311 
5312  if (IsIndirect) {
5313  // If it's been passed indirectly (actually a struct), whatever we find from
5314  // stored registers or on the stack will actually be a struct **.
5315  MemTy = llvm::PointerType::getUnqual(MemTy);
5316  }
5317 
5318  const Type *Base = nullptr;
5319  uint64_t NumMembers = 0;
5320  bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5321  if (IsHFA && NumMembers > 1) {
5322  // Homogeneous aggregates passed in registers will have their elements split
5323  // and stored 16-bytes apart regardless of size (they're notionally in qN,
5324  // qN+1, ...). We reload and store into a temporary local variable
5325  // contiguously.
5326  assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5327  auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5328  llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5329  llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5330  Address Tmp = CGF.CreateTempAlloca(HFATy,
5331  std::max(TyAlign, BaseTyInfo.second));
5332 
5333  // On big-endian platforms, the value will be right-aligned in its slot.
5334  int Offset = 0;
5335  if (CGF.CGM.getDataLayout().isBigEndian() &&
5336  BaseTyInfo.first.getQuantity() < 16)
5337  Offset = 16 - BaseTyInfo.first.getQuantity();
5338 
5339  for (unsigned i = 0; i < NumMembers; ++i) {
5340  CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5341  Address LoadAddr =
5342  CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5343  LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5344 
5345  Address StoreAddr =
5346  CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
5347 
5348  llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5349  CGF.Builder.CreateStore(Elem, StoreAddr);
5350  }
5351 
5352  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5353  } else {
5354  // Otherwise the object is contiguous in memory.
5355 
5356  // It might be right-aligned in its slot.
5357  CharUnits SlotSize = BaseAddr.getAlignment();
5358  if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5359  (IsHFA || !isAggregateTypeForABI(Ty)) &&
5360  TyInfo.first < SlotSize) {
5361  CharUnits Offset = SlotSize - TyInfo.first;
5362  BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5363  }
5364 
5365  RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5366  }
5367 
5368  CGF.EmitBranch(ContBlock);
5369 
5370  //=======================================
5371  // Argument was on the stack
5372  //=======================================
5373  CGF.EmitBlock(OnStackBlock);
5374 
5375  Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
5376  CharUnits::Zero(), "stack_p");
5377  llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5378 
5379  // Again, stack arguments may need realignment. In this case both integer and
5380  // floating-point ones might be affected.
5381  if (!IsIndirect && TyAlign.getQuantity() > 8) {
5382  int Align = TyAlign.getQuantity();
5383 
5384  OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5385 
5386  OnStackPtr = CGF.Builder.CreateAdd(
5387  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5388  "align_stack");
5389  OnStackPtr = CGF.Builder.CreateAnd(
5390  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5391  "align_stack");
5392 
5393  OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5394  }
5395  Address OnStackAddr(OnStackPtr,
5396  std::max(CharUnits::fromQuantity(8), TyAlign));
5397 
5398  // All stack slots are multiples of 8 bytes.
5399  CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5400  CharUnits StackSize;
5401  if (IsIndirect)
5402  StackSize = StackSlotSize;
5403  else
5404  StackSize = TyInfo.first.alignTo(StackSlotSize);
5405 
5406  llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5407  llvm::Value *NewStack =
5408  CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5409 
5410  // Write the new value of __stack for the next call to va_arg
5411  CGF.Builder.CreateStore(NewStack, stack_p);
5412 
5413  if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5414  TyInfo.first < StackSlotSize) {
5415  CharUnits Offset = StackSlotSize - TyInfo.first;
5416  OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5417  }
5418 
5419  OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5420 
5421  CGF.EmitBranch(ContBlock);
5422 
5423  //=======================================
5424  // Tidy up
5425  //=======================================
5426  CGF.EmitBlock(ContBlock);
5427 
5428  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5429  OnStackAddr, OnStackBlock, "vaargs.addr");
5430 
5431  if (IsIndirect)
5432  return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5433  TyInfo.second);
5434 
5435  return ResAddr;
5436 }
5437 
5438 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5439  CodeGenFunction &CGF) const {
5440  // The backend's lowering doesn't support va_arg for aggregates or
5441  // illegal vector types. Lower VAArg here for these cases and use
5442  // the LLVM va_arg instruction for everything else.
5443  if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5444  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5445 
5446  CharUnits SlotSize = CharUnits::fromQuantity(8);
5447 
5448  // Empty records are ignored for parameter passing purposes.
5449  if (isEmptyRecord(getContext(), Ty, true)) {
5450  Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5451  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5452  return Addr;
5453  }
5454 
5455  // The size of the actual thing passed, which might end up just
5456  // being a pointer for indirect types.
5457  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5458 
5459  // Arguments bigger than 16 bytes which aren't homogeneous
5460  // aggregates should be passed indirectly.
5461  bool IsIndirect = false;
5462  if (TyInfo.first.getQuantity() > 16) {
5463  const Type *Base = nullptr;
5464  uint64_t Members = 0;
5465  IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5466  }
5467 
5468  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5469  TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5470 }
5471 
5472 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5473  QualType Ty) const {
5474  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5475  CGF.getContext().getTypeInfoInChars(Ty),
5477  /*allowHigherAlign*/ false);
5478 }
5479 
5480 //===----------------------------------------------------------------------===//
5481 // ARM ABI Implementation
5482 //===----------------------------------------------------------------------===//
5483 
5484 namespace {
5485 
5486 class ARMABIInfo : public SwiftABIInfo {
5487 public:
5488  enum ABIKind {
5489  APCS = 0,
5490  AAPCS = 1,
5491  AAPCS_VFP = 2,
5492  AAPCS16_VFP = 3,
5493  };
5494 
5495 private:
5496  ABIKind Kind;
5497 
5498 public:
5499  ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5500  : SwiftABIInfo(CGT), Kind(_Kind) {
5501  setCCs();
5502  }
5503 
5504  bool isEABI() const {
5505  switch (getTarget().getTriple().getEnvironment()) {
5506  case llvm::Triple::Android:
5507  case llvm::Triple::EABI:
5508  case llvm::Triple::EABIHF:
5509  case llvm::Triple::GNUEABI:
5510  case llvm::Triple::GNUEABIHF:
5511  case llvm::Triple::MuslEABI:
5512  case llvm::Triple::MuslEABIHF:
5513  return true;
5514  default:
5515  return false;
5516  }
5517  }
5518 
5519  bool isEABIHF() const {
5520  switch (getTarget().getTriple().getEnvironment()) {
5521  case llvm::Triple::EABIHF:
5522  case llvm::Triple::GNUEABIHF:
5523  case llvm::Triple::MuslEABIHF:
5524  return true;
5525  default:
5526  return false;
5527  }
5528  }
5529 
5530  ABIKind getABIKind() const { return Kind; }
5531 
5532 private:
5533  ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5534  ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5535  bool isIllegalVectorType(QualType Ty) const;
5536 
5537  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5538  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5539  uint64_t Members) const override;
5540 
5541  void computeInfo(CGFunctionInfo &FI) const override;
5542 
5543  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5544  QualType Ty) const override;
5545 
5546  llvm::CallingConv::ID getLLVMDefaultCC() const;
5547  llvm::CallingConv::ID getABIDefaultCC() const;
5548  void setCCs();
5549 
5550  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
5551  bool asReturnValue) const override {
5552  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5553  }
5554  bool isSwiftErrorInRegister() const override {
5555  return true;
5556  }
5557  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5558  unsigned elts) const override;
5559 };
5560 
5561 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5562 public:
5563  ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5564  :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5565 
5566  const ARMABIInfo &getABIInfo() const {
5567  return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5568  }
5569 
5570  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5571  return 13;
5572  }
5573 
5574  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5575  return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
5576  }
5577 
5578  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5579  llvm::Value *Address) const override {
5580  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5581 
5582  // 0-15 are the 16 integer registers.
5583  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5584  return false;
5585  }
5586 
5587  unsigned getSizeOfUnwindException() const override {
5588  if (getABIInfo().isEABI()) return 88;
5590  }
5591 
5592  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5593  CodeGen::CodeGenModule &CGM) const override {
5594  if (GV->isDeclaration())
5595  return;
5596  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5597  if (!FD)
5598  return;
5599 
5600  const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5601  if (!Attr)
5602  return;
5603 
5604  const char *Kind;
5605  switch (Attr->getInterrupt()) {
5606  case ARMInterruptAttr::Generic: Kind = ""; break;
5607  case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5608  case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5609  case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5610  case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5611  case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5612  }
5613 
5614  llvm::Function *Fn = cast<llvm::Function>(GV);
5615 
5616  Fn->addFnAttr("interrupt", Kind);
5617 
5618  ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5619  if (ABI == ARMABIInfo::APCS)
5620  return;
5621 
5622  // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5623  // however this is not necessarily true on taking any interrupt. Instruct
5624  // the backend to perform a realignment as part of the function prologue.
5625  llvm::AttrBuilder B;
5626  B.addStackAlignmentAttr(8);
5627  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5628  }
5629 };
5630 
5631 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5632 public:
5633  WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5634  : ARMTargetCodeGenInfo(CGT, K) {}
5635 
5636  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5637  CodeGen::CodeGenModule &CGM) const override;
5638 
5639  void getDependentLibraryOption(llvm::StringRef Lib,
5640  llvm::SmallString<24> &Opt) const override {
5641  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5642  }
5643 
5644  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5645  llvm::SmallString<32> &Opt) const override {
5646  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5647  }
5648 };
5649 
5650 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5651  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5652  ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5653  if (GV->isDeclaration())
5654  return;
5655  addStackProbeTargetAttributes(D, GV, CGM);
5656 }
5657 }
5658 
5659 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5660  if (!::classifyReturnType(getCXXABI(), FI, *this))
5661  FI.getReturnInfo() =
5663 
5664  for (auto &I : FI.arguments())
5665  I.info = classifyArgumentType(I.type, FI.isVariadic());
5666 
5667  // Always honor user-specified calling convention.
5669  return;
5670 
5672  if (cc != llvm::CallingConv::C)
5674 }
5675 
5676 /// Return the default calling convention that LLVM will use.
5677 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5678  // The default calling convention that LLVM will infer.
5679  if (isEABIHF() || getTarget().getTriple().isWatchABI())
5680  return llvm::CallingConv::ARM_AAPCS_VFP;
5681  else if (isEABI())
5682  return llvm::CallingConv::ARM_AAPCS;
5683  else
5684  return llvm::CallingConv::ARM_APCS;
5685 }
5686 
5687 /// Return the calling convention that our ABI would like us to use
5688 /// as the C calling convention.
5689 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5690  switch (getABIKind()) {
5691  case APCS: return llvm::CallingConv::ARM_APCS;
5692  case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5693  case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5694  case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5695  }
5696  llvm_unreachable("bad ABI kind");
5697 }
5698 
5699 void ARMABIInfo::setCCs() {
5700  assert(getRuntimeCC() == llvm::CallingConv::C);
5701 
5702  // Don't muddy up the IR with a ton of explicit annotations if
5703  // they'd just match what LLVM will infer from the triple.
5704  llvm::CallingConv::ID abiCC = getABIDefaultCC();
5705  if (abiCC != getLLVMDefaultCC())
5706  RuntimeCC = abiCC;
5707 }
5708 
5710  bool isVariadic) const {
5711  // 6.1.2.1 The following argument types are VFP CPRCs:
5712  // A single-precision floating-point type (including promoted
5713  // half-precision types); A double-precision floating-point type;
5714  // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5715  // with a Base Type of a single- or double-precision floating-point type,
5716  // 64-bit containerized vectors or 128-bit containerized vectors with one
5717  // to four Elements.
5718  bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
5719 
5721 
5722  // Handle illegal vector types here.
5723  if (isIllegalVectorType(Ty)) {
5724  uint64_t Size = getContext().getTypeSize(Ty);
5725  if (Size <= 32) {
5726  llvm::Type *ResType =
5727  llvm::Type::getInt32Ty(getVMContext());
5728  return ABIArgInfo::getDirect(ResType);
5729  }
5730  if (Size == 64) {
5731  llvm::Type *ResType = llvm::VectorType::get(
5732  llvm::Type::getInt32Ty(getVMContext()), 2);
5733  return ABIArgInfo::getDirect(ResType);
5734  }
5735  if (Size == 128) {
5736  llvm::Type *ResType = llvm::VectorType::get(
5737  llvm::Type::getInt32Ty(getVMContext()), 4);
5738  return ABIArgInfo::getDirect(ResType);
5739  }
5740  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5741  }
5742 
5743  // _Float16 and __fp16 get passed as if it were an int or float, but with
5744  // the top 16 bits unspecified. This is not done for OpenCL as it handles the
5745  // half type natively, and does not need to interwork with AAPCS code.
5746  if ((Ty->isFloat16Type() || Ty->isHalfType()) &&
5747  !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5748  llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5749  llvm::Type::getFloatTy(getVMContext()) :
5750  llvm::Type::getInt32Ty(getVMContext());
5751  return ABIArgInfo::getDirect(ResType);
5752  }
5753 
5754  if (!isAggregateTypeForABI(Ty)) {
5755  // Treat an enum type as its underlying type.
5756  if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5757  Ty = EnumTy->getDecl()->getIntegerType();
5758  }
5759 
5761  : ABIArgInfo::getDirect());
5762  }
5763 
5766  }
5767 
5768  // Ignore empty records.
5769  if (isEmptyRecord(getContext(), Ty, true))
5770  return ABIArgInfo::getIgnore();
5771 
5772  if (IsEffectivelyAAPCS_VFP) {
5773  // Homogeneous Aggregates need to be expanded when we can fit the aggregate
5774  // into VFP registers.
5775  const Type *Base = nullptr;
5776  uint64_t Members = 0;
5777  if (isHomogeneousAggregate(Ty, Base, Members)) {
5778  assert(Base && "Base class should be set for homogeneous aggregate");
5779  // Base can be a floating-point or a vector.
5780  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5781  }
5782  } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5783  // WatchOS does have homogeneous aggregates. Note that we intentionally use
5784  // this convention even for a variadic function: the backend will use GPRs
5785  // if needed.
5786  const Type *Base = nullptr;
5787  uint64_t Members = 0;
5788  if (isHomogeneousAggregate(Ty, Base, Members)) {
5789  assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5790  llvm::Type *Ty =
5791  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5792  return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5793  }
5794  }
5795 
5796  if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5797  getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5798  // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5799  // bigger than 128-bits, they get placed in space allocated by the caller,
5800  // and a pointer is passed.
5801  return ABIArgInfo::getIndirect(
5802  CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5803  }
5804 
5805  // Support byval for ARM.
5806  // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5807  // most 8-byte. We realign the indirect argument if type alignment is bigger
5808  // than ABI alignment.
5809  uint64_t ABIAlign = 4;
5810  uint64_t TyAlign;
5811  if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5812  getABIKind() == ARMABIInfo::AAPCS) {
5814  ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5815  } else {
5816  TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
5817  }
5818  if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5819  assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5821  /*ByVal=*/true,
5822  /*Realign=*/TyAlign > ABIAlign);
5823  }
5824 
5825  // On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
5826  // same size and alignment.
5827  if (getTarget().isRenderScriptTarget()) {
5828  return coerceToIntArray(Ty, getContext(), getVMContext());
5829  }
5830 
5831  // Otherwise, pass by coercing to a structure of the appropriate size.
5832  llvm::Type* ElemTy;
5833  unsigned SizeRegs;
5834  // FIXME: Try to match the types of the arguments more accurately where
5835  // we can.
5836  if (TyAlign <= 4) {
5837  ElemTy = llvm::Type::getInt32Ty(getVMContext());
5838  SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5839  } else {
5840  ElemTy = llvm::Type::getInt64Ty(getVMContext());
5841  SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5842  }
5843 
5844  return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5845 }
5846 
5847 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5848  llvm::LLVMContext &VMContext) {
5849  // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5850  // is called integer-like if its size is less than or equal to one word, and
5851  // the offset of each of its addressable sub-fields is zero.
5852 
5853  uint64_t Size = Context.getTypeSize(Ty);
5854 
5855  // Check that the type fits in a word.
5856  if (Size > 32)
5857  return false;
5858 
5859  // FIXME: Handle vector types!
5860  if (Ty->isVectorType())
5861  return false;
5862 
5863  // Float types are never treated as "integer like".
5864  if (Ty->isRealFloatingType())
5865  return false;
5866 
5867  // If this is a builtin or pointer type then it is ok.
5868  if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
5869  return true;
5870 
5871  // Small complex integer types are "integer like".
5872  if (const ComplexType *CT = Ty->getAs<ComplexType>())
5873  return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5874 
5875  // Single element and zero sized arrays should be allowed, by the definition
5876  // above, but they are not.
5877 
5878  // Otherwise, it must be a record type.
5879  const RecordType *RT = Ty->getAs<RecordType>();
5880  if (!RT) return false;
5881 
5882  // Ignore records with flexible arrays.
5883  const RecordDecl *RD = RT->getDecl();
5884  if (RD->hasFlexibleArrayMember())
5885  return false;
5886 
5887  // Check that all sub-fields are at offset 0, and are themselves "integer
5888  // like".
5889  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5890 
5891  bool HadField = false;
5892  unsigned idx = 0;
5893  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5894  i != e; ++i, ++idx) {
5895  const FieldDecl *FD = *i;
5896 
5897  // Bit-fields are not addressable, we only need to verify they are "integer
5898  // like". We still have to disallow a subsequent non-bitfield, for example:
5899  // struct { int : 0; int x }
5900  // is non-integer like according to gcc.
5901  if (FD->isBitField()) {
5902  if (!RD->isUnion())
5903  HadField = true;
5904 
5905  if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5906  return false;
5907 
5908  continue;
5909  }
5910 
5911  // Check if this field is at offset 0.
5912  if (Layout.getFieldOffset(idx) != 0)
5913  return false;
5914 
5915  if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5916  return false;
5917 
5918  // Only allow at most one field in a structure. This doesn't match the
5919  // wording above, but follows gcc in situations with a field following an
5920  // empty structure.
5921  if (!RD->isUnion()) {
5922  if (HadField)
5923  return false;
5924 
5925  HadField = true;
5926  }
5927  }
5928 
5929  return true;
5930 }
5931 
5933  bool isVariadic) const {
5934  bool IsEffectivelyAAPCS_VFP =
5935  (getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;
5936 
5937  if (RetTy->isVoidType())
5938  return ABIArgInfo::getIgnore();
5939 
5940  // Large vector types should be returned via memory.
5941  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128) {
5942  return getNaturalAlignIndirect(RetTy);
5943  }
5944 
5945  // _Float16 and __fp16 get returned as if it were an int or float, but with
5946  // the top 16 bits unspecified. This is not done for OpenCL as it handles the
5947  // half type natively, and does not need to interwork with AAPCS code.
5948  if ((RetTy->isFloat16Type() || RetTy->isHalfType()) &&
5949  !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5950  llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5951  llvm::Type::getFloatTy(getVMContext()) :
5952  llvm::Type::getInt32Ty(getVMContext());
5953  return ABIArgInfo::getDirect(ResType);
5954  }
5955 
5956  if (!isAggregateTypeForABI(RetTy)) {
5957  // Treat an enum type as its underlying type.
5958  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5959  RetTy = EnumTy->getDecl()->getIntegerType();
5960 
5961  return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
5963  }
5964 
5965  // Are we following APCS?
5966  if (getABIKind() == APCS) {
5967  if (isEmptyRecord(getContext(), RetTy, false))
5968  return ABIArgInfo::getIgnore();
5969 
5970  // Complex types are all returned as packed integers.
5971  //
5972  // FIXME: Consider using 2 x vector types if the back end handles them
5973  // correctly.
5974  if (RetTy->isAnyComplexType())
5975  return ABIArgInfo::getDirect(llvm::IntegerType::get(
5976  getVMContext(), getContext().getTypeSize(RetTy)));
5977 
5978  // Integer like structures are returned in r0.
5979  if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
5980  // Return in the smallest viable integer type.
5981  uint64_t Size = getContext().getTypeSize(RetTy);
5982  if (Size <= 8)
5983  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5984  if (Size <= 16)
5985  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
5986  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
5987  }
5988 
5989  // Otherwise return in memory.
5990  return getNaturalAlignIndirect(RetTy);
5991  }
5992 
5993  // Otherwise this is an AAPCS variant.
5994 
5995  if (isEmptyRecord(getContext(), RetTy, true))
5996  return ABIArgInfo::getIgnore();
5997 
5998  // Check for homogeneous aggregates with AAPCS-VFP.
5999  if (IsEffectivelyAAPCS_VFP) {
6000  const Type *Base = nullptr;
6001  uint64_t Members = 0;
6002  if (isHomogeneousAggregate(RetTy, Base, Members)) {
6003  assert(Base && "Base class should be set for homogeneous aggregate");
6004  // Homogeneous Aggregates are returned directly.
6005  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
6006  }
6007  }
6008 
6009  // Aggregates <= 4 bytes are returned in r0; other aggregates
6010  // are returned indirectly.
6011  uint64_t Size = getContext().getTypeSize(RetTy);
6012  if (Size <= 32) {
6013  // On RenderScript, coerce Aggregates <= 4 bytes to an integer array of
6014  // same size and alignment.
6015  if (getTarget().isRenderScriptTarget()) {
6016  return coerceToIntArray(RetTy, getContext(), getVMContext());
6017  }
6018  if (getDataLayout().isBigEndian())
6019  // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
6020  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6021 
6022  // Return in the smallest viable integer type.
6023  if (Size <= 8)
6024  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6025  if (Size <= 16)
6026  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6027  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6028  } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
6029  llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
6030  llvm::Type *CoerceTy =
6031  llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
6032  return ABIArgInfo::getDirect(CoerceTy);
6033  }
6034 
6035  return getNaturalAlignIndirect(RetTy);
6036 }
6037 
6038 /// isIllegalVector - check whether Ty is an illegal vector type.
6039 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
6040  if (const VectorType *VT = Ty->getAs<VectorType> ()) {
6041  if (isAndroid()) {
6042  // Android shipped using Clang 3.1, which supported a slightly different
6043  // vector ABI. The primary differences were that 3-element vector types
6044  // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
6045  // accepts that legacy behavior for Android only.
6046  // Check whether VT is legal.
6047  unsigned NumElements = VT->getNumElements();
6048  // NumElements should be power of 2 or equal to 3.
6049  if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
6050  return true;
6051  } else {
6052  // Check whether VT is legal.
6053  unsigned NumElements = VT->getNumElements();
6054  uint64_t Size = getContext().getTypeSize(VT);
6055  // NumElements should be power of 2.
6056  if (!llvm::isPowerOf2_32(NumElements))
6057  return true;
6058  // Size should be greater than 32 bits.
6059  return Size <= 32;
6060  }
6061  }
6062  return false;
6063 }
6064 
6065 bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
6066  llvm::Type *eltTy,
6067  unsigned numElts) const {
6068  if (!llvm::isPowerOf2_32(numElts))
6069  return false;
6070  unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy);
6071  if (size > 64)
6072  return false;
6073  if (vectorSize.getQuantity() != 8 &&
6074  (vectorSize.getQuantity() != 16 || numElts == 1))
6075  return false;
6076  return true;
6077 }
6078 
6079 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
6080  // Homogeneous aggregates for AAPCS-VFP must have base types of float,
6081  // double, or 64-bit or 128-bit vectors.
6082  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
6083  if (BT->getKind() == BuiltinType::Float ||
6084  BT->getKind() == BuiltinType::Double ||
6085  BT->getKind() == BuiltinType::LongDouble)
6086  return true;
6087  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
6088  unsigned VecSize = getContext().getTypeSize(VT);
6089  if (VecSize == 64 || VecSize == 128)
6090  return true;
6091  }
6092  return false;
6093 }
6094 
6095 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
6096  uint64_t Members) const {
6097  return Members <= 4;
6098 }
6099 
6100 Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6101  QualType Ty) const {
6102  CharUnits SlotSize = CharUnits::fromQuantity(4);
6103 
6104  // Empty records are ignored for parameter passing purposes.
6105  if (isEmptyRecord(getContext(), Ty, true)) {
6106  Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
6107  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
6108  return Addr;
6109  }
6110 
6111  auto TyInfo = getContext().getTypeInfoInChars(Ty);
6112  CharUnits TyAlignForABI = TyInfo.second;
6113 
6114  // Use indirect if size of the illegal vector is bigger than 16 bytes.
6115  bool IsIndirect = false;
6116  const Type *Base = nullptr;
6117  uint64_t Members = 0;
6118  if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
6119  IsIndirect = true;
6120 
6121  // ARMv7k passes structs bigger than 16 bytes indirectly, in space
6122  // allocated by the caller.
6123  } else if (TyInfo.first > CharUnits::fromQuantity(16) &&
6124  getABIKind() == ARMABIInfo::AAPCS16_VFP &&
6125  !isHomogeneousAggregate(Ty, Base, Members)) {
6126  IsIndirect = true;
6127 
6128  // Otherwise, bound the type's ABI alignment.
6129  // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
6130  // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
6131  // Our callers should be prepared to handle an under-aligned address.
6132  } else if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
6133  getABIKind() == ARMABIInfo::AAPCS) {
6134  TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6135  TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
6136  } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
6137  // ARMv7k allows type alignment up to 16 bytes.
6138  TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6139  TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
6140  } else {
6141  TyAlignForABI = CharUnits::fromQuantity(4);
6142  }
6143  TyInfo.second = TyAlignForABI;
6144 
6145  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
6146  SlotSize, /*AllowHigherAlign*/ true);
6147 }
6148 
6149 //===----------------------------------------------------------------------===//
6150 // NVPTX ABI Implementation
6151 //===----------------------------------------------------------------------===//
6152 
6153 namespace {
6154 
6155 class NVPTXABIInfo : public ABIInfo {
6156 public:
6157  NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6158 
6159  ABIArgInfo classifyReturnType(QualType RetTy) const;
6161 
6162  void computeInfo(CGFunctionInfo &FI) const override;
6163  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6164  QualType Ty) const override;
6165 };
6166 
6167 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
6168 public:
6169  NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
6170  : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
6171 
6172  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6173  CodeGen::CodeGenModule &M) const override;
6174  bool shouldEmitStaticExternCAliases() const override;
6175 
6176 private:
6177  // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
6178  // resulting MDNode to the nvvm.annotations MDNode.
6179  static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
6180 };
6181 
6183  if (RetTy->isVoidType())
6184  return ABIArgInfo::getIgnore();
6185 
6186  // note: this is different from default ABI
6187  if (!RetTy->isScalarType())
6188  return ABIArgInfo::getDirect();
6189 
6190  // Treat an enum type as its underlying type.
6191  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6192  RetTy = EnumTy->getDecl()->getIntegerType();
6193 
6194  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
6195  : ABIArgInfo::getDirect());
6196 }
6197 
6199  // Treat an enum type as its underlying type.
6200  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6201  Ty = EnumTy->getDecl()->getIntegerType();
6202 
6203  // Return aggregates type as indirect by value
6204  if (isAggregateTypeForABI(Ty))
6205  return getNaturalAlignIndirect(Ty, /* byval */ true);
6206 
6208  : ABIArgInfo::getDirect());
6209 }
6210 
6211 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
6212  if (!getCXXABI().classifyReturnType(FI))
6214  for (auto &I : FI.arguments())
6215  I.info = classifyArgumentType(I.type);
6216 
6217  // Always honor user-specified calling convention.
6219  return;
6220 
6222 }
6223 
6224 Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6225  QualType Ty) const {
6226  llvm_unreachable("NVPTX does not support varargs");
6227 }
6228 
6229 void NVPTXTargetCodeGenInfo::setTargetAttributes(
6230  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6231  if (GV->isDeclaration())
6232  return;
6233  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6234  if (!FD) return;
6235 
6236  llvm::Function *F = cast<llvm::Function>(GV);
6237 
6238  // Perform special handling in OpenCL mode
6239  if (M.getLangOpts().OpenCL) {
6240  // Use OpenCL function attributes to check for kernel functions
6241  // By default, all functions are device functions
6242  if (FD->hasAttr<OpenCLKernelAttr>()) {
6243  // OpenCL __kernel functions get kernel metadata
6244  // Create !{<func-ref>, metadata !"kernel", i32 1} node
6245  addNVVMMetadata(F, "kernel", 1);
6246  // And kernel functions are not subject to inlining
6247  F->addFnAttr(llvm::Attribute::NoInline);
6248  }
6249  }
6250 
6251  // Perform special handling in CUDA mode.
6252  if (M.getLangOpts().CUDA) {
6253  // CUDA __global__ functions get a kernel metadata entry. Since
6254  // __global__ functions cannot be called from the device, we do not
6255  // need to set the noinline attribute.
6256  if (FD->hasAttr<CUDAGlobalAttr>()) {
6257  // Create !{<func-ref>, metadata !"kernel", i32 1} node
6258  addNVVMMetadata(F, "kernel", 1);
6259  }
6260  if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
6261  // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
6262  llvm::APSInt MaxThreads(32);
6263  MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
6264  if (MaxThreads > 0)
6265  addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
6266 
6267  // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
6268  // not specified in __launch_bounds__ or if the user specified a 0 value,
6269  // we don't have to add a PTX directive.
6270  if (Attr->getMinBlocks()) {
6271  llvm::APSInt MinBlocks(32);
6272  MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
6273  if (MinBlocks > 0)
6274  // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
6275  addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
6276  }
6277  }
6278  }
6279 }
6280 
6281 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
6282  int Operand) {
6283  llvm::Module *M = F->getParent();
6284  llvm::LLVMContext &Ctx = M->getContext();
6285 
6286  // Get "nvvm.annotations" metadata node
6287  llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
6288 
6289  llvm::Metadata *MDVals[] = {
6290  llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
6291  llvm::ConstantAsMetadata::get(
6292  llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
6293  // Append metadata to nvvm.annotations
6294  MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6295 }
6296 
6297 bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
6298  return false;
6299 }
6300 }
6301 
6302 //===----------------------------------------------------------------------===//
6303 // SystemZ ABI Implementation
6304 //===----------------------------------------------------------------------===//
6305 
6306 namespace {
6307 
6308 class SystemZABIInfo : public SwiftABIInfo {
6309  bool HasVector;
6310 
6311 public:
6312  SystemZABIInfo(CodeGenTypes &CGT, bool HV)
6313  : SwiftABIInfo(CGT), HasVector(HV) {}
6314 
6315  bool isPromotableIntegerType(QualType Ty) const;
6316  bool isCompoundType(QualType Ty) const;
6317  bool isVectorArgumentType(QualType Ty) const;
6318  bool isFPArgumentType(QualType Ty) const;
6319  QualType GetSingleElementType(QualType Ty) const;
6320 
6321  ABIArgInfo classifyReturnType(QualType RetTy) const;
6323 
6324  void computeInfo(CGFunctionInfo &FI) const override {
6325  if (!getCXXABI().classifyReturnType(FI))
6327  for (auto &I : FI.arguments())
6328  I.info = classifyArgumentType(I.type);
6329  }
6330 
6331  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6332  QualType Ty) const override;
6333 
6334  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
6335  bool asReturnValue) const override {
6336  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
6337  }
6338  bool isSwiftErrorInRegister() const override {
6339  return false;
6340  }
6341 };
6342 
6343 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
6344 public:
6345  SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
6346  : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
6347 };
6348 
6349 }
6350 
6351 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
6352  // Treat an enum type as its underlying type.
6353  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6354  Ty = EnumTy->getDecl()->getIntegerType();
6355 
6356  // Promotable integer types are required to be promoted by the ABI.
6357  if (Ty->isPromotableIntegerType())
6358  return true;
6359 
6360  // 32-bit values must also be promoted.
6361  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6362  switch (BT->getKind()) {
6363  case BuiltinType::Int:
6364  case BuiltinType::UInt:
6365  return true;
6366  default:
6367  return false;
6368  }
6369  return false;
6370 }
6371 
6372 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
6373  return (Ty->isAnyComplexType() ||
6374  Ty->isVectorType() ||
6375  isAggregateTypeForABI(Ty));
6376 }
6377 
6378 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
6379  return (HasVector &&
6380  Ty->isVectorType() &&
6381  getContext().getTypeSize(Ty) <= 128);
6382 }
6383 
6384 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
6385  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6386  switch (BT->getKind()) {
6387  case BuiltinType::Float:
6388  case BuiltinType::Double:
6389  return true;
6390  default:
6391  return false;
6392  }
6393 
6394  return false;
6395 }
6396 
6397 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
6398  if (const RecordType *RT = Ty->getAsStructureType()) {
6399  const RecordDecl *RD = RT->getDecl();
6400  QualType Found;
6401 
6402  // If this is a C++ record, check the bases first.
6403  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
6404  for (const auto &I : CXXRD->bases()) {
6405  QualType Base = I.getType();
6406 
6407  // Empty bases don't affect things either way.
6408  if (isEmptyRecord(getContext(), Base, true))
6409  continue;
6410 
6411  if (!Found.isNull())
6412  return Ty;
6413  Found = GetSingleElementType(Base);
6414  }
6415 
6416  // Check the fields.
6417  for (const auto *FD : RD->fields()) {
6418  // For compatibility with GCC, ignore empty bitfields in C++ mode.
6419  // Unlike isSingleElementStruct(), empty structure and array fields
6420  // do count. So do anonymous bitfields that aren't zero-sized.
6421  if (getContext().getLangOpts().CPlusPlus &&
6422  FD->isZeroLengthBitField(getContext()))
6423  continue;
6424 
6425  // Unlike isSingleElementStruct(), arrays do not count.
6426  // Nested structures still do though.
6427  if (!Found.isNull())
6428  return Ty;
6429  Found = GetSingleElementType(FD->getType());
6430  }
6431 
6432  // Unlike isSingleElementStruct(), trailing padding is allowed.
6433  // An 8-byte aligned struct s { float f; } is passed as a double.
6434  if (!Found.isNull())
6435  return Found;
6436  }
6437 
6438  return Ty;
6439 }
6440 
6441 Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6442  QualType Ty) const {
6443  // Assume that va_list type is correct; should be pointer to LLVM type:
6444  // struct {
6445  // i64 __gpr;
6446  // i64 __fpr;
6447  // i8 *__overflow_arg_area;
6448  // i8 *__reg_save_area;
6449  // };
6450 
6451  // Every non-vector argument occupies 8 bytes and is passed by preference
6452  // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
6453  // always passed on the stack.
6454  Ty = getContext().getCanonicalType(Ty);
6455  auto TyInfo = getContext().getTypeInfoInChars(Ty);
6456  llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
6457  llvm::Type *DirectTy = ArgTy;
6459  bool IsIndirect = AI.isIndirect();
6460  bool InFPRs = false;
6461  bool IsVector = false;
6462  CharUnits UnpaddedSize;
6463  CharUnits DirectAlign;
6464  if (IsIndirect) {
6465  DirectTy = llvm::PointerType::getUnqual(DirectTy);
6466  UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
6467  } else {
6468  if (AI.getCoerceToType())
6469  ArgTy = AI.getCoerceToType();
6470  InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
6471  IsVector = ArgTy->isVectorTy();
6472  UnpaddedSize = TyInfo.first;
6473  DirectAlign = TyInfo.second;
6474  }
6475  CharUnits PaddedSize = CharUnits::fromQuantity(8);
6476  if (IsVector && UnpaddedSize > PaddedSize)
6477  PaddedSize = CharUnits::fromQuantity(16);
6478  assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
6479 
6480  CharUnits Padding = (PaddedSize - UnpaddedSize);
6481 
6482  llvm::Type *IndexTy = CGF.Int64Ty;
6483  llvm::Value *PaddedSizeV =
6484  llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
6485 
6486  if (IsVector) {
6487  // Work out the address of a vector argument on the stack.
6488  // Vector arguments are always passed in the high bits of a
6489  // single (8 byte) or double (16 byte) stack slot.
6490  Address OverflowArgAreaPtr =
6491  CGF.Builder.CreateStructGEP(VAListAddr, 2, CharUnits::fromQuantity(16),
6492  "overflow_arg_area_ptr");
6493  Address OverflowArgArea =
6494  Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6495  TyInfo.second);
6496  Address MemAddr =
6497  CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
6498 
6499  // Update overflow_arg_area_ptr pointer
6500  llvm::Value *NewOverflowArgArea =
6501  CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6502  "overflow_arg_area");
6503  CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6504 
6505  return MemAddr;
6506  }
6507 
6508  assert(PaddedSize.getQuantity() == 8);
6509 
6510  unsigned MaxRegs, RegCountField, RegSaveIndex;
6511  CharUnits RegPadding;
6512  if (InFPRs) {
6513  MaxRegs = 4; // Maximum of 4 FPR arguments
6514  RegCountField = 1; // __fpr
6515  RegSaveIndex = 16; // save offset for f0
6516  RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
6517  } else {
6518  MaxRegs = 5; // Maximum of 5 GPR arguments
6519  RegCountField = 0; // __gpr
6520  RegSaveIndex = 2; // save offset for r2
6521  RegPadding = Padding; // values are passed in the low bits of a GPR
6522  }
6523 
6524  Address RegCountPtr = CGF.Builder.CreateStructGEP(
6525  VAListAddr, RegCountField, RegCountField * CharUnits::fromQuantity(8),
6526  "reg_count_ptr");
6527  llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
6528  llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
6529  llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
6530  "fits_in_regs");
6531 
6532  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
6533  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
6534  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
6535  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
6536 
6537  // Emit code to load the value if it was passed in registers.
6538  CGF.EmitBlock(InRegBlock);
6539 
6540  // Work out the address of an argument register.
6541  llvm::Value *ScaledRegCount =
6542  CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
6543  llvm::Value *RegBase =
6544  llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
6545  + RegPadding.getQuantity());
6546  llvm::Value *RegOffset =
6547  CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
6548  Address RegSaveAreaPtr =
6549  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
6550  "reg_save_area_ptr");
6551  llvm::Value *RegSaveArea =
6552  CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
6553  Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
6554  "raw_reg_addr"),
6555  PaddedSize);
6556  Address RegAddr =
6557  CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
6558 
6559  // Update the register count
6560  llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
6561  llvm::Value *NewRegCount =
6562  CGF.Builder.CreateAdd(RegCount, One, "reg_count");
6563  CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
6564  CGF.EmitBranch(ContBlock);
6565 
6566  // Emit code to load the value if it was passed in memory.
6567  CGF.EmitBlock(InMemBlock);
6568 
6569  // Work out the address of a stack argument.
6570  Address OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
6571  VAListAddr, 2, CharUnits::fromQuantity(16), "overflow_arg_area_ptr");
6572  Address OverflowArgArea =
6573  Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6574  PaddedSize);
6575  Address RawMemAddr =
6576  CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6577  Address MemAddr =
6578  CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6579 
6580  // Update overflow_arg_area_ptr pointer
6581  llvm::Value *NewOverflowArgArea =
6582  CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6583  "overflow_arg_area");
6584  CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6585  CGF.EmitBranch(ContBlock);
6586 
6587  // Return the appropriate result.
6588  CGF.EmitBlock(ContBlock);
6589  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6590  MemAddr, InMemBlock, "va_arg.addr");
6591 
6592  if (IsIndirect)
6593  ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6594  TyInfo.second);
6595 
6596  return ResAddr;
6597 }
6598 
6600  if (RetTy->isVoidType())
6601  return ABIArgInfo::getIgnore();
6602  if (isVectorArgumentType(RetTy))
6603  return ABIArgInfo::getDirect();
6604  if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
6605  return getNaturalAlignIndirect(RetTy);
6606  return (isPromotableIntegerType(RetTy) ? ABIArgInfo::getExtend(RetTy)
6607  : ABIArgInfo::getDirect());
6608 }
6609 
6611  // Handle the generic C++ ABI.
6614 
6615  // Integers and enums are extended to full register width.
6616  if (isPromotableIntegerType(Ty))
6617  return ABIArgInfo::getExtend(Ty);
6618 
6619  // Handle vector types and vector-like structure types. Note that
6620  // as opposed to float-like structure types, we do not allow any
6621  // padding for vector-like structures, so verify the sizes match.
6622  uint64_t Size = getContext().getTypeSize(Ty);
6623  QualType SingleElementTy = GetSingleElementType(Ty);
6624  if (isVectorArgumentType(SingleElementTy) &&
6625  getContext().getTypeSize(SingleElementTy) == Size)
6626  return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6627 
6628  // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6629  if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6630  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6631 
6632  // Handle small structures.
6633  if (const RecordType *RT = Ty->getAs<RecordType>()) {
6634  // Structures with flexible arrays have variable length, so really
6635  // fail the size test above.
6636  const RecordDecl *RD = RT->getDecl();
6637  if (RD->hasFlexibleArrayMember())
6638  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6639 
6640  // The structure is passed as an unextended integer, a float, or a double.
6641  llvm::Type *PassTy;
6642  if (isFPArgumentType(SingleElementTy)) {
6643  assert(Size == 32 || Size == 64);
6644  if (Size == 32)
6645  PassTy = llvm::Type::getFloatTy(getVMContext());
6646  else
6647  PassTy = llvm::Type::getDoubleTy(getVMContext());
6648  } else
6649  PassTy = llvm::IntegerType::get(getVMContext(), Size);
6650  return ABIArgInfo::getDirect(PassTy);
6651  }
6652 
6653  // Non-structure compounds are passed indirectly.
6654  if (isCompoundType(Ty))
6655  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6656 
6657  return ABIArgInfo::getDirect(nullptr);
6658 }
6659 
6660 //===----------------------------------------------------------------------===//
6661 // MSP430 ABI Implementation
6662 //===----------------------------------------------------------------------===//
6663 
6664 namespace {
6665 
6666 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6667 public:
6668  MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6669  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6670  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6671  CodeGen::CodeGenModule &M) const override;
6672 };
6673 
6674 }
6675 
6676 void MSP430TargetCodeGenInfo::setTargetAttributes(
6677  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6678  if (GV->isDeclaration())
6679  return;
6680  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6681  if (const MSP430InterruptAttr *attr = FD->getAttr<MSP430InterruptAttr>()) {
6682  // Handle 'interrupt' attribute:
6683  llvm::Function *F = cast<llvm::Function>(GV);
6684 
6685  // Step 1: Set ISR calling convention.
6686  F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6687 
6688  // Step 2: Add attributes goodness.
6689  F->addFnAttr(llvm::Attribute::NoInline);
6690 
6691  // Step 3: Emit ISR vector alias.
6692  unsigned Num = attr->getNumber() / 2;
6694  "__isr_" + Twine(Num), F);
6695  }
6696  }
6697 }
6698 
6699 //===----------------------------------------------------------------------===//
6700 // MIPS ABI Implementation. This works for both little-endian and
6701 // big-endian variants.
6702 //===----------------------------------------------------------------------===//
6703 
6704 namespace {
6705 class MipsABIInfo : public ABIInfo {
6706  bool IsO32;
6707  unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6708  void CoerceToIntArgs(uint64_t TySize,
6709  SmallVectorImpl<llvm::Type *> &ArgList) const;
6710  llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6711  llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6712  llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6713 public:
6714  MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6715  ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6716  StackAlignInBytes(IsO32 ? 8 : 16) {}
6717 
6718  ABIArgInfo classifyReturnType(QualType RetTy) const;
6719  ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6720  void computeInfo(CGFunctionInfo &FI) const override;
6721  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6722  QualType Ty) const override;
6723  ABIArgInfo extendType(QualType Ty) const;
6724 };
6725 
6726 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6727  unsigned SizeOfUnwindException;
6728 public:
6729  MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6730  : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6731  SizeOfUnwindException(IsO32 ? 24 : 32) {}
6732 
6733  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6734  return 29;
6735  }
6736 
6737  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6738  CodeGen::CodeGenModule &CGM) const override {
6739  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6740  if (!FD) return;
6741  llvm::Function *Fn = cast<llvm::Function>(GV);
6742 
6743  if (FD->hasAttr<MipsLongCallAttr>())
6744  Fn->addFnAttr("long-call");
6745  else if (FD->hasAttr<MipsShortCallAttr>())
6746  Fn->addFnAttr("short-call");
6747 
6748  // Other attributes do not have a meaning for declarations.
6749  if (GV->isDeclaration())
6750  return;
6751 
6752  if (FD->hasAttr<Mips16Attr>()) {
6753  Fn->addFnAttr("mips16");
6754  }
6755  else if (FD->hasAttr<NoMips16Attr>()) {
6756  Fn->addFnAttr("nomips16");
6757  }
6758 
6759  if (FD->hasAttr<MicroMipsAttr>())
6760  Fn->addFnAttr("micromips");
6761  else if (FD->hasAttr<NoMicroMipsAttr>())
6762  Fn->addFnAttr("nomicromips");
6763 
6764  const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6765  if (!Attr)
6766  return;
6767 
6768  const char *Kind;
6769  switch (Attr->getInterrupt()) {
6770  case MipsInterruptAttr::eic: Kind = "eic"; break;
6771  case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6772  case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6773  case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6774  case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6775  case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6776  case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6777  case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6778  case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6779  }
6780 
6781  Fn->addFnAttr("interrupt", Kind);
6782 
6783  }
6784 
6785  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6786  llvm::Value *Address) const override;
6787 
6788  unsigned getSizeOfUnwindException() const override {
6789  return SizeOfUnwindException;
6790  }
6791 };
6792 }
6793 
6794 void MipsABIInfo::CoerceToIntArgs(
6795  uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6796  llvm::IntegerType *IntTy =
6797  llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6798 
6799  // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6800  for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6801  ArgList.push_back(IntTy);
6802 
6803  // If necessary, add one more integer type to ArgList.
6804  unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6805 
6806  if (R)
6807  ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6808 }
6809 
6810 // In N32/64, an aligned double precision floating point field is passed in
6811 // a register.
6812 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6813  SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6814 
6815  if (IsO32) {
6816  CoerceToIntArgs(TySize, ArgList);
6817  return llvm::StructType::get(getVMContext(), ArgList);
6818  }
6819 
6820  if (Ty->isComplexType())
6821  return CGT.ConvertType(Ty);
6822 
6823  const RecordType *RT = Ty->getAs<RecordType>();
6824 
6825  // Unions/vectors are passed in integer registers.
6826  if (!RT || !RT->isStructureOrClassType()) {
6827  CoerceToIntArgs(TySize, ArgList);
6828  return llvm::StructType::get(getVMContext(), ArgList);
6829  }
6830 
6831  const RecordDecl *RD = RT->getDecl();
6832  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6833  assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6834 
6835  uint64_t LastOffset = 0;
6836  unsigned idx = 0;
6837  llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6838 
6839  // Iterate over fields in the struct/class and check if there are any aligned
6840  // double fields.
6841  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
6842  i != e; ++i, ++idx) {
6843  const QualType Ty = i->getType();
6844  const BuiltinType *BT = Ty->getAs<BuiltinType>();
6845 
6846  if (!BT || BT->getKind() != BuiltinType::Double)
6847  continue;
6848 
6849  uint64_t Offset = Layout.getFieldOffset(idx);
6850  if (Offset % 64) // Ignore doubles that are not aligned.
6851  continue;
6852 
6853  // Add ((Offset - LastOffset) / 64) args of type i64.
6854  for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
6855  ArgList.push_back(I64);
6856 
6857  // Add double type.
6858  ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
6859  LastOffset = Offset + 64;
6860  }
6861 
6862  CoerceToIntArgs(TySize - LastOffset, IntArgList);
6863  ArgList.append(IntArgList.begin(), IntArgList.end());
6864 
6865  return llvm::StructType::get(getVMContext(), ArgList);
6866 }
6867 
6868 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
6869  uint64_t Offset) const {
6870  if (OrigOffset + MinABIStackAlignInBytes > Offset)
6871  return nullptr;
6872 
6873  return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
6874 }
6875 
6876 ABIArgInfo
6877 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
6879 
6880  uint64_t OrigOffset = Offset;
6881  uint64_t TySize = getContext().getTypeSize(Ty);
6882  uint64_t Align = getContext().getTypeAlign(Ty) / 8;
6883 
6884  Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
6885  (uint64_t)StackAlignInBytes);
6886  unsigned CurrOffset = llvm::alignTo(Offset, Align);
6887  Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
6888 
6889  if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
6890  // Ignore empty aggregates.
6891  if (TySize == 0)
6892  return ABIArgInfo::getIgnore();
6893 
6895  Offset = OrigOffset + MinABIStackAlignInBytes;
6897  }
6898 
6899  // If we have reached here, aggregates are passed directly by coercing to
6900  // another structure type. Padding is inserted if the offset of the
6901  // aggregate is unaligned.
6902  ABIArgInfo ArgInfo =
6903  ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
6904  getPaddingType(OrigOffset, CurrOffset));
6905  ArgInfo.setInReg(true);
6906  return ArgInfo;
6907  }
6908 
6909  // Treat an enum type as its underlying type.
6910  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6911  Ty = EnumTy->getDecl()->getIntegerType();
6912 
6913  // All integral types are promoted to the GPR width.
6914  if (Ty->isIntegralOrEnumerationType())
6915  return extendType(Ty);
6916 
6917  return ABIArgInfo::getDirect(
6918  nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
6919 }
6920 
6921 llvm::Type*
6922 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
6923  const RecordType *RT = RetTy->getAs<RecordType>();
6925 
6926  if (RT && RT->isStructureOrClassType()) {
6927  const RecordDecl *RD = RT->getDecl();
6928  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6929  unsigned FieldCnt = Layout.getFieldCount();
6930 
6931  // N32/64 returns struct/classes in floating point registers if the
6932  // following conditions are met:
6933  // 1. The size of the struct/class is no larger than 128-bit.
6934  // 2. The struct/class has one or two fields all of which are floating
6935  // point types.
6936  // 3. The offset of the first field is zero (this follows what gcc does).
6937  //
6938  // Any other composite results are returned in integer registers.
6939  //
6940  if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
6941  RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
6942  for (; b != e; ++b) {
6943  const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
6944 
6945  if (!BT || !BT->isFloatingPoint())
6946  break;
6947 
6948  RTList.push_back(CGT.ConvertType(b->getType()));
6949  }
6950 
6951  if (b == e)
6952  return llvm::StructType::get(getVMContext(), RTList,
6953  RD->hasAttr<PackedAttr>());
6954 
6955  RTList.clear();
6956  }
6957  }
6958 
6959  CoerceToIntArgs(Size, RTList);
6960  return llvm::StructType::get(getVMContext(), RTList);
6961 }
6962 
6964  uint64_t Size = getContext().getTypeSize(RetTy);
6965 
6966  if (RetTy->isVoidType())
6967  return ABIArgInfo::getIgnore();
6968 
6969  // O32 doesn't treat zero-sized structs differently from other structs.
6970  // However, N32/N64 ignores zero sized return values.
6971  if (!IsO32 && Size == 0)
6972  return ABIArgInfo::getIgnore();
6973 
6974  if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
6975  if (Size <= 128) {
6976  if (RetTy->isAnyComplexType())
6977  return ABIArgInfo::getDirect();
6978 
6979  // O32 returns integer vectors in registers and N32/N64 returns all small
6980  // aggregates in registers.
6981  if (!IsO32 ||
6982  (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
6983  ABIArgInfo ArgInfo =
6984  ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
6985  ArgInfo.setInReg(true);
6986  return ArgInfo;
6987  }
6988  }
6989 
6990  return getNaturalAlignIndirect(RetTy);
6991  }
6992 
6993  // Treat an enum type as its underlying type.
6994  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6995  RetTy = EnumTy->getDecl()->getIntegerType();
6996 
6997  if (RetTy->isPromotableIntegerType())
6998  return ABIArgInfo::getExtend(RetTy);
6999 
7000  if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
7001  RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
7002  return ABIArgInfo::getSignExtend(RetTy);
7003 
7004  return ABIArgInfo::getDirect();
7005 }
7006 
7007 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
7008  ABIArgInfo &RetInfo = FI.getReturnInfo();
7009  if (!getCXXABI().classifyReturnType(FI))
7010  RetInfo = classifyReturnType(FI.getReturnType());
7011 
7012  // Check if a pointer to an aggregate is passed as a hidden argument.
7013  uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
7014 
7015  for (auto &I : FI.arguments())
7016  I.info = classifyArgumentType(I.type, Offset);
7017 }
7018 
7019 Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7020  QualType OrigTy) const {
7021  QualType Ty = OrigTy;
7022 
7023  // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
7024  // Pointers are also promoted in the same way but this only matters for N32.
7025  unsigned SlotSizeInBits = IsO32 ? 32 : 64;
7026  unsigned PtrWidth = getTarget().getPointerWidth(0);
7027  bool DidPromote = false;
7028  if ((Ty->isIntegerType() &&
7029  getContext().getIntWidth(Ty) < SlotSizeInBits) ||
7030  (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
7031  DidPromote = true;
7032  Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
7033  Ty->isSignedIntegerType());
7034  }
7035 
7036  auto TyInfo = getContext().getTypeInfoInChars(Ty);
7037 
7038  // The alignment of things in the argument area is never larger than
7039  // StackAlignInBytes.
7040  TyInfo.second =
7041  std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
7042 
7043  // MinABIStackAlignInBytes is the size of argument slots on the stack.
7044  CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
7045 
7046  Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7047  TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true);
7048 
7049 
7050  // If there was a promotion, "unpromote" into a temporary.
7051  // TODO: can we just use a pointer into a subset of the original slot?
7052  if (DidPromote) {
7053  Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
7054  llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
7055 
7056  // Truncate down to the right width.
7057  llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
7058  : CGF.IntPtrTy);
7059  llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
7060  if (OrigTy->isPointerType())
7061  V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
7062 
7063  CGF.Builder.CreateStore(V, Temp);
7064  Addr = Temp;
7065  }
7066 
7067  return Addr;
7068 }
7069 
7070 ABIArgInfo MipsABIInfo::extendType(QualType Ty) const {
7071  int TySize = getContext().getTypeSize(Ty);
7072 
7073  // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
7074  if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
7075  return ABIArgInfo::getSignExtend(Ty);
7076 
7077  return ABIArgInfo::getExtend(Ty);
7078 }
7079 
7080 bool
7081 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7082  llvm::Value *Address) const {
7083  // This information comes from gcc's implementation, which seems to
7084  // as canonical as it gets.
7085 
7086  // Everything on MIPS is 4 bytes. Double-precision FP registers
7087  // are aliased to pairs of single-precision FP registers.
7088  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
7089 
7090  // 0-31 are the general purpose registers, $0 - $31.
7091  // 32-63 are the floating-point registers, $f0 - $f31.
7092  // 64 and 65 are the multiply/divide registers, $hi and $lo.
7093  // 66 is the (notional, I think) register for signal-handler return.
7094  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
7095 
7096  // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
7097  // They are one bit wide and ignored here.
7098 
7099  // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
7100  // (coprocessor 1 is the FP unit)
7101  // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
7102  // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
7103  // 176-181 are the DSP accumulator registers.
7104  AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
7105  return false;
7106 }
7107 
7108 //===----------------------------------------------------------------------===//
7109 // AVR ABI Implementation.
7110 //===----------------------------------------------------------------------===//
7111 
7112 namespace {
7113 class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
7114 public:
7115  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
7116  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
7117 
7118  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7119  CodeGen::CodeGenModule &CGM) const override {
7120  if (GV->isDeclaration())
7121  return;
7122  const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
7123  if (!FD) return;
7124  auto *Fn = cast<llvm::Function>(GV);
7125 
7126  if (FD->getAttr<AVRInterruptAttr>())
7127  Fn->addFnAttr("interrupt");
7128 
7129  if (FD->getAttr<AVRSignalAttr>())
7130  Fn->addFnAttr("signal");
7131  }
7132 };
7133 }
7134 
7135 //===----------------------------------------------------------------------===//
7136 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
7137 // Currently subclassed only to implement custom OpenCL C function attribute
7138 // handling.
7139 //===----------------------------------------------------------------------===//
7140 
7141 namespace {
7142 
7143 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
7144 public:
7145  TCETargetCodeGenInfo(CodeGenTypes &CGT)
7146  : DefaultTargetCodeGenInfo(CGT) {}
7147 
7148  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7149  CodeGen::CodeGenModule &M) const override;
7150 };
7151 
7152 void TCETargetCodeGenInfo::setTargetAttributes(
7153  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
7154  if (GV->isDeclaration())
7155  return;
7156  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7157  if (!FD) return;
7158 
7159  llvm::Function *F = cast<llvm::Function>(GV);
7160 
7161  if (M.getLangOpts().OpenCL) {
7162  if (FD->hasAttr<OpenCLKernelAttr>()) {
7163  // OpenCL C Kernel functions are not subject to inlining
7164  F->addFnAttr(llvm::Attribute::NoInline);
7165  const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
7166  if (Attr) {
7167  // Convert the reqd_work_group_size() attributes to metadata.
7168  llvm::LLVMContext &Context = F->getContext();
7169  llvm::NamedMDNode *OpenCLMetadata =
7170  M.getModule().getOrInsertNamedMetadata(
7171  "opencl.kernel_wg_size_info");
7172 
7174  Operands.push_back(llvm::ConstantAsMetadata::get(F));
7175 
7176  Operands.push_back(
7177  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7178  M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
7179  Operands.push_back(
7180  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7181  M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
7182  Operands.push_back(
7183  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7184  M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
7185 
7186  // Add a boolean constant operand for "required" (true) or "hint"
7187  // (false) for implementing the work_group_size_hint attr later.
7188  // Currently always true as the hint is not yet implemented.
7189  Operands.push_back(
7190  llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
7191  OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
7192  }
7193  }
7194  }
7195 }
7196 
7197 }
7198 
7199 //===----------------------------------------------------------------------===//
7200 // Hexagon ABI Implementation
7201 //===----------------------------------------------------------------------===//
7202 
7203 namespace {
7204 
7205 class HexagonABIInfo : public ABIInfo {
7206 
7207 
7208 public:
7209  HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7210 
7211 private:
7212 
7213  ABIArgInfo classifyReturnType(QualType RetTy) const;
7215 
7216  void computeInfo(CGFunctionInfo &FI) const override;
7217 
7218  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7219  QualType Ty) const override;
7220 };
7221 
7222 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
7223 public:
7224  HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
7225  :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
7226 
7227  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7228  return 29;
7229  }
7230 };
7231 
7232 }
7233 
7234 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
7235  if (!getCXXABI().classifyReturnType(FI))
7237  for (auto &I : FI.arguments())
7238  I.info = classifyArgumentType(I.type);
7239 }
7240 
7242  if (!isAggregateTypeForABI(Ty)) {
7243  // Treat an enum type as its underlying type.
7244  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7245  Ty = EnumTy->getDecl()->getIntegerType();
7246 
7248  : ABIArgInfo::getDirect());
7249  }
7250 
7253 
7254  // Ignore empty records.
7255  if (isEmptyRecord(getContext(), Ty, true))
7256  return ABIArgInfo::getIgnore();
7257 
7258  uint64_t Size = getContext().getTypeSize(Ty);
7259  if (Size > 64)
7260  return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
7261  // Pass in the smallest viable integer type.
7262  else if (Size > 32)
7263  return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7264  else if (Size > 16)
7265  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7266  else if (Size > 8)
7267  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7268  else
7269  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7270 }
7271 
7273  if (RetTy->isVoidType())
7274  return ABIArgInfo::getIgnore();
7275 
7276  // Large vector types should be returned via memory.
7277  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
7278  return getNaturalAlignIndirect(RetTy);
7279 
7280  if (!isAggregateTypeForABI(RetTy)) {
7281  // Treat an enum type as its underlying type.
7282  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7283  RetTy = EnumTy->getDecl()->getIntegerType();
7284 
7285  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
7286  : ABIArgInfo::getDirect());
7287  }
7288 
7289  if (isEmptyRecord(getContext(), RetTy, true))
7290  return ABIArgInfo::getIgnore();
7291 
7292  // Aggregates <= 8 bytes are returned in r0; other aggregates
7293  // are returned indirectly.
7294  uint64_t Size = getContext().getTypeSize(RetTy);
7295  if (Size <= 64) {
7296  // Return in the smallest viable integer type.
7297  if (Size <= 8)
7298  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7299  if (Size <= 16)
7300  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7301  if (Size <= 32)
7302  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7303  return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7304  }
7305 
7306  return getNaturalAlignIndirect(RetTy, /*ByVal=*/true);
7307 }
7308 
7309 Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7310  QualType Ty) const {
7311  // FIXME: Someone needs to audit that this handle alignment correctly.
7312  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7313  getContext().getTypeInfoInChars(Ty),
7315  /*AllowHigherAlign*/ true);
7316 }
7317 
7318 //===----------------------------------------------------------------------===//
7319 // Lanai ABI Implementation
7320 //===----------------------------------------------------------------------===//
7321 
7322 namespace {
7323 class LanaiABIInfo : public DefaultABIInfo {
7324 public:
7325  LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7326 
7327  bool shouldUseInReg(QualType Ty, CCState &State) const;
7328 
7329  void computeInfo(CGFunctionInfo &FI) const override {
7330  CCState State(FI.getCallingConvention());
7331  // Lanai uses 4 registers to pass arguments unless the function has the
7332  // regparm attribute set.
7333  if (FI.getHasRegParm()) {
7334  State.FreeRegs = FI.getRegParm();
7335  } else {
7336  State.FreeRegs = 4;
7337  }
7338 
7339  if (!getCXXABI().classifyReturnType(FI))
7341  for (auto &I : FI.arguments())
7342  I.info = classifyArgumentType(I.type, State);
7343  }
7344 
7345  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
7346  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
7347 };
7348 } // end anonymous namespace
7349 
7350 bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
7351  unsigned Size = getContext().getTypeSize(Ty);
7352  unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
7353 
7354  if (SizeInRegs == 0)
7355  return false;
7356 
7357  if (SizeInRegs > State.FreeRegs) {
7358  State.FreeRegs = 0;
7359  return false;
7360  }
7361 
7362  State.FreeRegs -= SizeInRegs;
7363 
7364  return true;
7365 }
7366 
7367 ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
7368  CCState &State) const {
7369  if (!ByVal) {
7370  if (State.FreeRegs) {
7371  --State.FreeRegs; // Non-byval indirects just use one pointer.
7372  return getNaturalAlignIndirectInReg(Ty);
7373  }
7374  return getNaturalAlignIndirect(Ty, false);
7375  }
7376 
7377  // Compute the byval alignment.
7378  const unsigned MinABIStackAlignInBytes = 4;
7379  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
7380  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
7381  /*Realign=*/TypeAlign >
7382  MinABIStackAlignInBytes);
7383 }
7384 
7386  CCState &State) const {
7387  // Check with the C++ ABI first.
7388  const RecordType *RT = Ty->getAs<RecordType>();
7389  if (RT) {
7391  if (RAA == CGCXXABI::RAA_Indirect) {
7392  return getIndirectResult(Ty, /*ByVal=*/false, State);
7393  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
7394  return getNaturalAlignIndirect(Ty, /*ByRef=*/true);
7395  }
7396  }
7397 
7398  if (isAggregateTypeForABI(Ty)) {
7399  // Structures with flexible arrays are always indirect.
7400  if (RT && RT->getDecl()->hasFlexibleArrayMember())
7401  return getIndirectResult(Ty, /*ByVal=*/true, State);
7402 
7403  // Ignore empty structs/unions.
7404  if (isEmptyRecord(getContext(), Ty, true))
7405  return ABIArgInfo::getIgnore();
7406 
7407  llvm::LLVMContext &LLVMContext = getVMContext();
7408  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
7409  if (SizeInRegs <= State.FreeRegs) {
7410  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
7411  SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
7412  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
7413  State.FreeRegs -= SizeInRegs;
7414  return ABIArgInfo::getDirectInReg(Result);
7415  } else {
7416  State.FreeRegs = 0;
7417  }
7418  return getIndirectResult(Ty, true, State);
7419  }
7420 
7421  // Treat an enum type as its underlying type.
7422  if (const auto *EnumTy = Ty->getAs<EnumType>())
7423  Ty = EnumTy->getDecl()->getIntegerType();
7424 
7425  bool InReg = shouldUseInReg(Ty, State);
7426  if (Ty->isPromotableIntegerType()) {
7427  if (InReg)
7428  return ABIArgInfo::getDirectInReg();
7429  return ABIArgInfo::getExtend(Ty);
7430  }
7431  if (InReg)
7432  return ABIArgInfo::getDirectInReg();
7433  return ABIArgInfo::getDirect();
7434 }
7435 
7436 namespace {
7437 class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
7438 public:
7439  LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7440  : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
7441 };
7442 }
7443 
7444 //===----------------------------------------------------------------------===//
7445 // AMDGPU ABI Implementation
7446 //===----------------------------------------------------------------------===//
7447 
7448 namespace {
7449 
7450 class AMDGPUABIInfo final : public DefaultABIInfo {
7451 private:
7452  static const unsigned MaxNumRegsForArgsRet = 16;
7453 
7454  unsigned numRegsForType(QualType Ty) const;
7455 
7456  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
7457  bool isHomogeneousAggregateSmallEnough(const Type *Base,
7458  uint64_t Members) const override;
7459 
7460 public:
7461  explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) :
7462  DefaultABIInfo(CGT) {}
7463 
7464  ABIArgInfo classifyReturnType(QualType RetTy) const;
7465  ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
7466  ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegsLeft) const;
7467 
7468  void computeInfo(CGFunctionInfo &FI) const override;
7469 };
7470 
7471 bool AMDGPUABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
7472  return true;
7473 }
7474 
7475 bool AMDGPUABIInfo::isHomogeneousAggregateSmallEnough(
7476  const Type *Base, uint64_t Members) const {
7477  uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32;
7478 
7479  // Homogeneous Aggregates may occupy at most 16 registers.
7480  return Members * NumRegs <= MaxNumRegsForArgsRet;
7481 }
7482 
7483 /// Estimate number of registers the type will use when passed in registers.
7484 unsigned AMDGPUABIInfo::numRegsForType(QualType Ty) const {
7485  unsigned NumRegs = 0;
7486 
7487  if (const VectorType *VT = Ty->getAs<VectorType>()) {
7488  // Compute from the number of elements. The reported size is based on the
7489  // in-memory size, which includes the padding 4th element for 3-vectors.
7490  QualType EltTy = VT->getElementType();
7491  unsigned EltSize = getContext().getTypeSize(EltTy);
7492 
7493  // 16-bit element vectors should be passed as packed.
7494  if (EltSize == 16)
7495  return (VT->getNumElements() + 1) / 2;
7496 
7497  unsigned EltNumRegs = (EltSize + 31) / 32;
7498  return EltNumRegs * VT->getNumElements();
7499  }
7500 
7501  if (const RecordType *RT = Ty->getAs<RecordType>()) {
7502  const RecordDecl *RD = RT->getDecl();
7503  assert(!RD->hasFlexibleArrayMember());
7504 
7505  for (const FieldDecl *Field : RD->fields()) {
7506  QualType FieldTy = Field->getType();
7507  NumRegs += numRegsForType(FieldTy);
7508  }
7509 
7510  return NumRegs;
7511  }
7512 
7513  return (getContext().getTypeSize(Ty) + 31) / 32;
7514 }
7515 
7516 void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
7518 
7519  if (!getCXXABI().classifyReturnType(FI))
7521 
7522  unsigned NumRegsLeft = MaxNumRegsForArgsRet;
7523  for (auto &Arg : FI.arguments()) {
7524  if (CC == llvm::CallingConv::AMDGPU_KERNEL) {
7525  Arg.info = classifyKernelArgumentType(Arg.type);
7526  } else {
7527  Arg.info = classifyArgumentType(Arg.type, NumRegsLeft);
7528  }
7529  }
7530 }
7531 
7533  if (isAggregateTypeForABI(RetTy)) {
7534  // Records with non-trivial destructors/copy-constructors should not be
7535  // returned by value.
7536  if (!getRecordArgABI(RetTy, getCXXABI())) {
7537  // Ignore empty structs/unions.
7538  if (isEmptyRecord(getContext(), RetTy, true))
7539  return ABIArgInfo::getIgnore();
7540 
7541  // Lower single-element structs to just return a regular value.
7542  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
7543  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7544 
7545  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
7546  const RecordDecl *RD = RT->getDecl();
7547  if (RD->hasFlexibleArrayMember())
7548  return DefaultABIInfo::classifyReturnType(RetTy);
7549  }
7550 
7551  // Pack aggregates <= 4 bytes into single VGPR or pair.
7552  uint64_t Size = getContext().getTypeSize(RetTy);
7553  if (Size <= 16)
7554  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7555 
7556  if (Size <= 32)
7557  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7558 
7559  if (Size <= 64) {
7560  llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7561  return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7562  }
7563 
7564  if (numRegsForType(RetTy) <= MaxNumRegsForArgsRet)
7565  return ABIArgInfo::getDirect();
7566  }
7567  }
7568 
7569  // Otherwise just do the default thing.
7570  return DefaultABIInfo::classifyReturnType(RetTy);
7571 }
7572 
7573 /// For kernels all parameters are really passed in a special buffer. It doesn't
7574 /// make sense to pass anything byval, so everything must be direct.
7575 ABIArgInfo AMDGPUABIInfo::classifyKernelArgumentType(QualType Ty) const {
7577 
7578  // TODO: Can we omit empty structs?
7579 
7580  // Coerce single element structs to its element.
7581  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7582  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7583 
7584  // If we set CanBeFlattened to true, CodeGen will expand the struct to its
7585  // individual elements, which confuses the Clover OpenCL backend; therefore we
7586  // have to set it to false here. Other args of getDirect() are just defaults.
7587  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
7588 }
7589 
7591  unsigned &NumRegsLeft) const {
7592  assert(NumRegsLeft <= MaxNumRegsForArgsRet && "register estimate underflow");
7593 
7595 
7596  if (isAggregateTypeForABI(Ty)) {
7597  // Records with non-trivial destructors/copy-constructors should not be
7598  // passed by value.
7599  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
7601 
7602  // Ignore empty structs/unions.
7603  if (isEmptyRecord(getContext(), Ty, true))
7604  return ABIArgInfo::getIgnore();
7605 
7606  // Lower single-element structs to just pass a regular value. TODO: We
7607  // could do reasonable-size multiple-element structs too, using getExpand(),
7608  // though watch out for things like bitfields.
7609  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7610  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7611 
7612  if (const RecordType *RT = Ty->getAs<RecordType>()) {
7613  const RecordDecl *RD = RT->getDecl();
7614  if (RD->hasFlexibleArrayMember())
7616  }
7617 
7618  // Pack aggregates <= 8 bytes into single VGPR or pair.
7619  uint64_t Size = getContext().getTypeSize(Ty);
7620  if (Size <= 64) {
7621  unsigned NumRegs = (Size + 31) / 32;
7622  NumRegsLeft -= std::min(NumRegsLeft, NumRegs);
7623 
7624  if (Size <= 16)
7625  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7626 
7627  if (Size <= 32)
7628  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7629 
7630  // XXX: Should this be i64 instead, and should the limit increase?
7631  llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7632  return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7633  }
7634 
7635  if (NumRegsLeft > 0) {
7636  unsigned NumRegs = numRegsForType(Ty);
7637  if (NumRegsLeft >= NumRegs) {
7638  NumRegsLeft -= NumRegs;
7639  return ABIArgInfo::getDirect();
7640  }
7641  }
7642  }
7643 
7644  // Otherwise just do the default thing.
7646  if (!ArgInfo.isIndirect()) {
7647  unsigned NumRegs = numRegsForType(Ty);
7648  NumRegsLeft -= std::min(NumRegs, NumRegsLeft);
7649  }
7650 
7651  return ArgInfo;
7652 }
7653 
7654 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
7655 public:
7656  AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
7657  : TargetCodeGenInfo(new AMDGPUABIInfo(CGT)) {}
7658  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7659  CodeGen::CodeGenModule &M) const override;
7660  unsigned getOpenCLKernelCallingConv() const override;
7661 
7662  llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
7663  llvm::PointerType *T, QualType QT) const override;
7664 
7665  LangAS getASTAllocaAddressSpace() const override {
7666  return getLangASFromTargetAS(
7667  getABIInfo().getDataLayout().getAllocaAddrSpace());
7668  }
7669  LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
7670  const VarDecl *D) const override;
7671  llvm::SyncScope::ID getLLVMSyncScopeID(SyncScope S,
7672  llvm::LLVMContext &C) const override;
7673  llvm::Function *
7674  createEnqueuedBlockKernel(CodeGenFunction &CGF,
7675  llvm::Function *BlockInvokeFunc,
7676  llvm::Value *BlockLiteral) const override;
7677  bool shouldEmitStaticExternCAliases() const override;
7678  void setCUDAKernelCallingConvention(const FunctionType *&FT) const override;
7679 };
7680 }
7681 
7682 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
7683  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
7684  if (GV->isDeclaration())
7685  return;
7686  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7687  if (!FD)
7688  return;
7689 
7690  llvm::Function *F = cast<llvm::Function>(GV);
7691 
7692  const auto *ReqdWGS = M.getLangOpts().OpenCL ?
7693  FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
7694 
7695  if (M.getLangOpts().OpenCL && FD->hasAttr<OpenCLKernelAttr>() &&
7696  (M.getTriple().getOS() == llvm::Triple::AMDHSA))
7697  F->addFnAttr("amdgpu-implicitarg-num-bytes", "48");
7698 
7699  const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
7700  if (ReqdWGS || FlatWGS) {
7701  unsigned Min = FlatWGS ? FlatWGS->getMin() : 0;
7702  unsigned Max = FlatWGS ? FlatWGS->getMax() : 0;
7703  if (ReqdWGS && Min == 0 && Max == 0)
7704  Min = Max = ReqdWGS->getXDim() * ReqdWGS->getYDim() * ReqdWGS->getZDim();
7705 
7706  if (Min != 0) {
7707  assert(Min <= Max && "Min must be less than or equal Max");
7708 
7709  std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max);
7710  F->addFnAttr("amdgpu-flat-work-group-size", AttrVal);
7711  } else
7712  assert(Max == 0 && "Max must be zero");
7713  }
7714 
7715  if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) {
7716  unsigned Min = Attr->getMin();
7717  unsigned Max = Attr->getMax();
7718 
7719  if (Min != 0) {
7720  assert((Max == 0 || Min <= Max) && "Min must be less than or equal Max");
7721 
7722  std::string AttrVal = llvm::utostr(Min);
7723  if (Max != 0)
7724  AttrVal = AttrVal + "," + llvm::utostr(Max);
7725  F->addFnAttr("amdgpu-waves-per-eu", AttrVal);
7726  } else
7727  assert(Max == 0 && "Max must be zero");
7728  }
7729 
7730  if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
7731  unsigned NumSGPR = Attr->getNumSGPR();
7732 
7733  if (NumSGPR != 0)
7734  F->addFnAttr("amdgpu-num-sgpr", llvm::utostr(NumSGPR));
7735  }
7736 
7737  if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
7738  uint32_t NumVGPR = Attr->getNumVGPR();
7739 
7740  if (NumVGPR != 0)
7741  F->addFnAttr("amdgpu-num-vgpr", llvm::utostr(NumVGPR));
7742  }
7743 }
7744 
7745 unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7746  return llvm::CallingConv::AMDGPU_KERNEL;
7747 }
7748 
7749 // Currently LLVM assumes null pointers always have value 0,
7750 // which results in incorrectly transformed IR. Therefore, instead of
7751 // emitting null pointers in private and local address spaces, a null
7752 // pointer in generic address space is emitted which is casted to a
7753 // pointer in local or private address space.
7754 llvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer(
7755  const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT,
7756  QualType QT) const {
7757  if (CGM.getContext().getTargetNullPointerValue(QT) == 0)
7758  return llvm::ConstantPointerNull::get(PT);
7759 
7760  auto &Ctx = CGM.getContext();
7761  auto NPT = llvm::PointerType::get(PT->getElementType(),
7762  Ctx.getTargetAddressSpace(LangAS::opencl_generic));
7763  return llvm::ConstantExpr::getAddrSpaceCast(
7764  llvm::ConstantPointerNull::get(NPT), PT);
7765 }
7766 
7767 LangAS
7768 AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
7769  const VarDecl *D) const {
7770  assert(!CGM.getLangOpts().OpenCL &&
7771  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
7772  "Address space agnostic languages only");
7773  LangAS DefaultGlobalAS = getLangASFromTargetAS(
7775  if (!D)
7776  return DefaultGlobalAS;
7777 
7778  LangAS AddrSpace = D->getType().getAddressSpace();
7779  assert(AddrSpace == LangAS::Default || isTargetAddressSpace(AddrSpace));
7780  if (AddrSpace != LangAS::Default)
7781  return AddrSpace;
7782 
7783  if (CGM.isTypeConstant(D->getType(), false)) {
7784  if (auto ConstAS = CGM.getTarget().getConstantAddressSpace())
7785  return ConstAS.getValue();
7786  }
7787  return DefaultGlobalAS;
7788 }
7789 
7791 AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S,
7792  llvm::LLVMContext &C) const {
7793  StringRef Name;
7794  switch (S) {
7796  Name = "workgroup";
7797  break;
7799  Name = "agent";
7800  break;
7802  Name = "";
7803  break;
7805  Name = "subgroup";
7806  }
7807  return C.getOrInsertSyncScopeID(Name);
7808 }
7809 
7810 bool AMDGPUTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
7811  return false;
7812 }
7813 
7815  const FunctionType *&FT) const {
7816  FT = getABIInfo().getContext().adjustFunctionType(
7818 }
7819 
7820 //===----------------------------------------------------------------------===//
7821 // SPARC v8 ABI Implementation.
7822 // Based on the SPARC Compliance Definition version 2.4.1.
7823 //
7824 // Ensures that complex values are passed in registers.
7825 //
7826 namespace {
7827 class SparcV8ABIInfo : public DefaultABIInfo {
7828 public:
7829  SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7830 
7831 private:
7832  ABIArgInfo classifyReturnType(QualType RetTy) const;
7833  void computeInfo(CGFunctionInfo &FI) const override;
7834 };
7835 } // end anonymous namespace
7836 
7837 
7838 ABIArgInfo
7840  if (Ty->isAnyComplexType()) {
7841  return ABIArgInfo::getDirect();
7842  }
7843  else {
7845  }
7846 }
7847 
7848 void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7849 
7851  for (auto &Arg : FI.arguments())
7852  Arg.info = classifyArgumentType(Arg.type);
7853 }
7854 
7855 namespace {
7856 class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
7857 public:
7858  SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
7859  : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
7860 };
7861 } // end anonymous namespace
7862 
7863 //===----------------------------------------------------------------------===//
7864 // SPARC v9 ABI Implementation.
7865 // Based on the SPARC Compliance Definition version 2.4.1.
7866 //
7867 // Function arguments a mapped to a nominal "parameter array" and promoted to
7868 // registers depending on their type. Each argument occupies 8 or 16 bytes in
7869 // the array, structs larger than 16 bytes are passed indirectly.
7870 //
7871 // One case requires special care:
7872 //
7873 // struct mixed {
7874 // int i;
7875 // float f;
7876 // };
7877 //
7878 // When a struct mixed is passed by value, it only occupies 8 bytes in the
7879 // parameter array, but the int is passed in an integer register, and the float
7880 // is passed in a floating point register. This is represented as two arguments
7881 // with the LLVM IR inreg attribute:
7882 //
7883 // declare void f(i32 inreg %i, float inreg %f)
7884 //
7885 // The code generator will only allocate 4 bytes from the parameter array for
7886 // the inreg arguments. All other arguments are allocated a multiple of 8
7887 // bytes.
7888 //
7889 namespace {
7890 class SparcV9ABIInfo : public ABIInfo {
7891 public:
7892  SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7893 
7894 private:
7895  ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
7896  void computeInfo(CGFunctionInfo &FI) const override;
7897  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7898  QualType Ty) const override;
7899 
7900  // Coercion type builder for structs passed in registers. The coercion type
7901  // serves two purposes:
7902  //
7903  // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
7904  // in registers.
7905  // 2. Expose aligned floating point elements as first-level elements, so the
7906  // code generator knows to pass them in floating point registers.
7907  //
7908  // We also compute the InReg flag which indicates that the struct contains
7909  // aligned 32-bit floats.
7910  //
7911  struct CoerceBuilder {
7912  llvm::LLVMContext &Context;
7913  const llvm::DataLayout &DL;
7915  uint64_t Size;
7916  bool InReg;
7917 
7918  CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
7919  : Context(c), DL(dl), Size(0), InReg(false) {}
7920 
7921  // Pad Elems with integers until Size is ToSize.
7922  void pad(uint64_t ToSize) {
7923  assert(ToSize >= Size && "Cannot remove elements");
7924  if (ToSize == Size)
7925  return;
7926 
7927  // Finish the current 64-bit word.
7928  uint64_t Aligned = llvm::alignTo(Size, 64);
7929  if (Aligned > Size && Aligned <= ToSize) {
7930  Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
7931  Size = Aligned;
7932  }
7933 
7934  // Add whole 64-bit words.
7935  while (Size + 64 <= ToSize) {
7936  Elems.push_back(llvm::Type::getInt64Ty(Context));
7937  Size += 64;
7938  }
7939 
7940  // Final in-word padding.
7941  if (Size < ToSize) {
7942  Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
7943  Size = ToSize;
7944  }
7945  }
7946 
7947  // Add a floating point element at Offset.
7948  void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
7949  // Unaligned floats are treated as integers.
7950  if (Offset % Bits)
7951  return;
7952  // The InReg flag is only required if there are any floats < 64 bits.
7953  if (Bits < 64)
7954  InReg = true;
7955  pad(Offset);
7956  Elems.push_back(Ty);
7957  Size = Offset + Bits;
7958  }
7959 
7960  // Add a struct type to the coercion type, starting at Offset (in bits).
7961  void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
7962  const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
7963  for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
7964  llvm::Type *ElemTy = StrTy->getElementType(i);
7965  uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
7966  switch (ElemTy->getTypeID()) {
7967  case llvm::Type::StructTyID:
7968  addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
7969  break;
7970  case llvm::Type::FloatTyID:
7971  addFloat(ElemOffset, ElemTy, 32);
7972  break;
7973  case llvm::Type::DoubleTyID:
7974  addFloat(ElemOffset, ElemTy, 64);
7975  break;
7976  case llvm::Type::FP128TyID:
7977  addFloat(ElemOffset, ElemTy, 128);
7978  break;
7979  case llvm::Type::PointerTyID:
7980  if (ElemOffset % 64 == 0) {
7981  pad(ElemOffset);
7982  Elems.push_back(ElemTy);
7983  Size += 64;
7984  }
7985  break;
7986  default:
7987  break;
7988  }
7989  }
7990  }
7991 
7992  // Check if Ty is a usable substitute for the coercion type.
7993  bool isUsableType(llvm::StructType *Ty) const {
7994  return llvm::makeArrayRef(Elems) == Ty->elements();
7995  }
7996 
7997  // Get the coercion type as a literal struct type.
7998  llvm::Type *getType() const {
7999  if (Elems.size() == 1)
8000  return Elems.front();
8001  else
8002  return llvm::StructType::get(Context, Elems);
8003  }
8004  };
8005 };
8006 } // end anonymous namespace
8007 
8008 ABIArgInfo
8009 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
8010  if (Ty->isVoidType())
8011  return ABIArgInfo::getIgnore();
8012 
8013  uint64_t Size = getContext().getTypeSize(Ty);
8014 
8015  // Anything too big to fit in registers is passed with an explicit indirect
8016  // pointer / sret pointer.
8017  if (Size > SizeLimit)
8018  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
8019 
8020  // Treat an enum type as its underlying type.
8021  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8022  Ty = EnumTy->getDecl()->getIntegerType();
8023 
8024  // Integer types smaller than a register are extended.
8025  if (Size < 64 && Ty->isIntegerType())
8026  return ABIArgInfo::getExtend(Ty);
8027 
8028  // Other non-aggregates go in registers.
8029  if (!isAggregateTypeForABI(Ty))
8030  return ABIArgInfo::getDirect();
8031 
8032  // If a C++ object has either a non-trivial copy constructor or a non-trivial
8033  // destructor, it is passed with an explicit indirect pointer / sret pointer.
8036 
8037  // This is a small aggregate type that should be passed in registers.
8038  // Build a coercion type from the LLVM struct type.
8039  llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
8040  if (!StrTy)
8041  return ABIArgInfo::getDirect();
8042 
8043  CoerceBuilder CB(getVMContext(), getDataLayout());
8044  CB.addStruct(0, StrTy);
8045  CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
8046 
8047  // Try to use the original type for coercion.
8048  llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
8049 
8050  if (CB.InReg)
8051  return ABIArgInfo::getDirectInReg(CoerceTy);
8052  else
8053  return ABIArgInfo::getDirect(CoerceTy);
8054 }
8055 
8056 Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8057  QualType Ty) const {
8058  ABIArgInfo AI = classifyType(Ty, 16 * 8);
8059  llvm::Type *ArgTy = CGT.ConvertType(Ty);
8060  if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8061  AI.setCoerceToType(ArgTy);
8062 
8063  CharUnits SlotSize = CharUnits::fromQuantity(8);
8064 
8065  CGBuilderTy &Builder = CGF.Builder;
8066  Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
8067  llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8068 
8069  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
8070 
8071  Address ArgAddr = Address::invalid();
8072  CharUnits Stride;
8073  switch (AI.getKind()) {
8074  case ABIArgInfo::Expand:
8076  case ABIArgInfo::InAlloca:
8077  llvm_unreachable("Unsupported ABI kind for va_arg");
8078 
8079  case ABIArgInfo::Extend: {
8080  Stride = SlotSize;
8081  CharUnits Offset = SlotSize - TypeInfo.first;
8082  ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
8083  break;
8084  }
8085 
8086  case ABIArgInfo::Direct: {
8087  auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
8088  Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
8089  ArgAddr = Addr;
8090  break;
8091  }
8092 
8093  case ABIArgInfo::Indirect:
8094  Stride = SlotSize;
8095  ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
8096  ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
8097  TypeInfo.second);
8098  break;
8099 
8100  case ABIArgInfo::Ignore:
8101  return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
8102  }
8103 
8104  // Update VAList.
8105  llvm::Value *NextPtr =
8106  Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), Stride, "ap.next");
8107  Builder.CreateStore(NextPtr, VAListAddr);
8108 
8109  return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
8110 }
8111 
8112 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
8113  FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
8114  for (auto &I : FI.arguments())
8115  I.info = classifyType(I.type, 16 * 8);
8116 }
8117 
8118 namespace {
8119 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
8120 public:
8121  SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
8122  : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
8123 
8124  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
8125  return 14;
8126  }
8127 
8128  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8129  llvm::Value *Address) const override;
8130 };
8131 } // end anonymous namespace
8132 
8133 bool
8134 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8135  llvm::Value *Address) const {
8136  // This is calculated from the LLVM and GCC tables and verified
8137  // against gcc output. AFAIK all ABIs use the same encoding.
8138 
8139  CodeGen::CGBuilderTy &Builder = CGF.Builder;
8140 
8141  llvm::IntegerType *i8 = CGF.Int8Ty;
8142  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
8143  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
8144 
8145  // 0-31: the 8-byte general-purpose registers
8146  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
8147 
8148  // 32-63: f0-31, the 4-byte floating-point registers
8149  AssignToArrayRange(Builder, Address, Four8, 32, 63);
8150 
8151  // Y = 64
8152  // PSR = 65
8153  // WIM = 66
8154  // TBR = 67
8155  // PC = 68
8156  // NPC = 69
8157  // FSR = 70
8158  // CSR = 71
8159  AssignToArrayRange(Builder, Address, Eight8, 64, 71);
8160 
8161  // 72-87: d0-15, the 8-byte floating-point registers
8162  AssignToArrayRange(Builder, Address, Eight8, 72, 87);
8163 
8164  return false;
8165 }
8166 
8167 
8168 //===----------------------------------------------------------------------===//
8169 // XCore ABI Implementation
8170 //===----------------------------------------------------------------------===//
8171 
8172 namespace {
8173 
8174 /// A SmallStringEnc instance is used to build up the TypeString by passing
8175 /// it by reference between functions that append to it.
8176 typedef llvm::SmallString<128> SmallStringEnc;
8177 
8178 /// TypeStringCache caches the meta encodings of Types.
8179 ///
8180 /// The reason for caching TypeStrings is two fold:
8181 /// 1. To cache a type's encoding for later uses;
8182 /// 2. As a means to break recursive member type inclusion.
8183 ///
8184 /// A cache Entry can have a Status of:
8185 /// NonRecursive: The type encoding is not recursive;
8186 /// Recursive: The type encoding is recursive;
8187 /// Incomplete: An incomplete TypeString;
8188 /// IncompleteUsed: An incomplete TypeString that has been used in a
8189 /// Recursive type encoding.
8190 ///
8191 /// A NonRecursive entry will have all of its sub-members expanded as fully
8192 /// as possible. Whilst it may contain types which are recursive, the type
8193 /// itself is not recursive and thus its encoding may be safely used whenever
8194 /// the type is encountered.
8195 ///
8196 /// A Recursive entry will have all of its sub-members expanded as fully as
8197 /// possible. The type itself is recursive and it may contain other types which
8198 /// are recursive. The Recursive encoding must not be used during the expansion
8199 /// of a recursive type's recursive branch. For simplicity the code uses
8200 /// IncompleteCount to reject all usage of Recursive encodings for member types.
8201 ///
8202 /// An Incomplete entry is always a RecordType and only encodes its
8203 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
8204 /// are placed into the cache during type expansion as a means to identify and
8205 /// handle recursive inclusion of types as sub-members. If there is recursion
8206 /// the entry becomes IncompleteUsed.
8207 ///
8208 /// During the expansion of a RecordType's members:
8209 ///
8210 /// If the cache contains a NonRecursive encoding for the member type, the
8211 /// cached encoding is used;
8212 ///
8213 /// If the cache contains a Recursive encoding for the member type, the
8214 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
8215 ///
8216 /// If the member is a RecordType, an Incomplete encoding is placed into the
8217 /// cache to break potential recursive inclusion of itself as a sub-member;
8218 ///
8219 /// Once a member RecordType has been expanded, its temporary incomplete
8220 /// entry is removed from the cache. If a Recursive encoding was swapped out
8221 /// it is swapped back in;
8222 ///
8223 /// If an incomplete entry is used to expand a sub-member, the incomplete
8224 /// entry is marked as IncompleteUsed. The cache keeps count of how many
8225 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
8226 ///
8227 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
8228 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
8229 /// Else the member is part of a recursive type and thus the recursion has
8230 /// been exited too soon for the encoding to be correct for the member.
8231 ///
8232 class TypeStringCache {
8233  enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
8234  struct Entry {
8235  std::string Str; // The encoded TypeString for the type.
8236  enum Status State; // Information about the encoding in 'Str'.
8237  std::string Swapped; // A temporary place holder for a Recursive encoding
8238  // during the expansion of RecordType's members.
8239  };
8240  std::map<const IdentifierInfo *, struct Entry> Map;
8241  unsigned IncompleteCount; // Number of Incomplete entries in the Map.
8242  unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
8243 public:
8244  TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
8245  void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
8246  bool removeIncomplete(const IdentifierInfo *ID);
8247  void addIfComplete(const IdentifierInfo *ID, StringRef Str,
8248  bool IsRecursive);
8249  StringRef lookupStr(const IdentifierInfo *ID);
8250 };
8251 
8252 /// TypeString encodings for enum & union fields must be order.
8253 /// FieldEncoding is a helper for this ordering process.
8254 class FieldEncoding {
8255  bool HasName;
8256  std::string Enc;
8257 public:
8258  FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
8259  StringRef str() { return Enc; }
8260  bool operator<(const FieldEncoding &rhs) const {
8261  if (HasName != rhs.HasName) return HasName;
8262  return Enc < rhs.Enc;
8263  }
8264 };
8265 
8266 class XCoreABIInfo : public DefaultABIInfo {
8267 public:
8268  XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
8269  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8270  QualType Ty) const override;
8271 };
8272 
8273 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
8274  mutable TypeStringCache TSC;
8275 public:
8276  XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
8277  :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
8278  void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8279  CodeGen::CodeGenModule &M) const override;
8280 };
8281 
8282 } // End anonymous namespace.
8283 
8284 // TODO: this implementation is likely now redundant with the default
8285 // EmitVAArg.
8286 Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8287  QualType Ty) const {
8288  CGBuilderTy &Builder = CGF.Builder;
8289 
8290  // Get the VAList.
8291  CharUnits SlotSize = CharUnits::fromQuantity(4);
8292  Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
8293 
8294  // Handle the argument.
8296  CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
8297  llvm::Type *ArgTy = CGT.ConvertType(Ty);
8298  if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8299  AI.setCoerceToType(ArgTy);
8300  llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8301 
8302  Address Val = Address::invalid();
8303  CharUnits ArgSize = CharUnits::Zero();
8304  switch (AI.getKind()) {
8305  case ABIArgInfo::Expand:
8307  case ABIArgInfo::InAlloca:
8308  llvm_unreachable("Unsupported ABI kind for va_arg");
8309  case ABIArgInfo::Ignore:
8310  Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
8311  ArgSize = CharUnits::Zero();
8312  break;
8313  case ABIArgInfo::Extend:
8314  case ABIArgInfo::Direct:
8315  Val = Builder.CreateBitCast(AP, ArgPtrTy);
8316  ArgSize = CharUnits::fromQuantity(
8317  getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
8318  ArgSize = ArgSize.alignTo(SlotSize);
8319  break;
8320  case ABIArgInfo::Indirect:
8321  Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
8322  Val = Address(Builder.CreateLoad(Val), TypeAlign);
8323  ArgSize = SlotSize;
8324  break;
8325  }
8326 
8327  // Increment the VAList.
8328  if (!ArgSize.isZero()) {
8329  llvm::Value *APN =
8330  Builder.CreateConstInBoundsByteGEP(AP.getPointer(), ArgSize);
8331  Builder.CreateStore(APN, VAListAddr);
8332  }
8333 
8334  return Val;
8335 }
8336 
8337 /// During the expansion of a RecordType, an incomplete TypeString is placed
8338 /// into the cache as a means to identify and break recursion.
8339 /// If there is a Recursive encoding in the cache, it is swapped out and will
8340 /// be reinserted by removeIncomplete().
8341 /// All other types of encoding should have been used rather than arriving here.
8342 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
8343  std::string StubEnc) {
8344  if (!ID)
8345  return;
8346  Entry &E = Map[ID];
8347  assert( (E.Str.empty() || E.State == Recursive) &&
8348  "Incorrectly use of addIncomplete");
8349  assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
8350  E.Swapped.swap(E.Str); // swap out the Recursive
8351  E.Str.swap(StubEnc);
8352  E.State = Incomplete;
8353  ++IncompleteCount;
8354 }
8355 
8356 /// Once the RecordType has been expanded, the temporary incomplete TypeString
8357 /// must be removed from the cache.
8358 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
8359 /// Returns true if the RecordType was defined recursively.
8360 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
8361  if (!ID)
8362  return false;
8363  auto I = Map.find(ID);
8364  assert(I != Map.end() && "Entry not present");
8365  Entry &E = I->second;
8366  assert( (E.State == Incomplete ||
8367  E.State == IncompleteUsed) &&
8368  "Entry must be an incomplete type");
8369  bool IsRecursive = false;
8370  if (E.State == IncompleteUsed) {
8371  // We made use of our Incomplete encoding, thus we are recursive.
8372  IsRecursive = true;
8373  --IncompleteUsedCount;
8374  }
8375  if (E.Swapped.empty())
8376  Map.erase(I);
8377  else {
8378  // Swap the Recursive back.
8379  E.Swapped.swap(E.Str);
8380  E.Swapped.clear();
8381  E.State = Recursive;
8382  }
8383  --IncompleteCount;
8384  return IsRecursive;
8385 }
8386 
8387 /// Add the encoded TypeString to the cache only if it is NonRecursive or
8388 /// Recursive (viz: all sub-members were expanded as fully as possible).
8389 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
8390  bool IsRecursive) {
8391  if (!ID || IncompleteUsedCount)
8392  return; // No key or it is is an incomplete sub-type so don't add.
8393  Entry &E = Map[ID];
8394  if (IsRecursive && !E.Str.empty()) {
8395  assert(E.State==Recursive && E.Str.size() == Str.size() &&
8396  "This is not the same Recursive entry");
8397  // The parent container was not recursive after all, so we could have used
8398  // this Recursive sub-member entry after all, but we assumed the worse when
8399  // we started viz: IncompleteCount!=0.
8400  return;
8401  }
8402  assert(E.Str.empty() && "Entry already present");
8403  E.Str = Str.str();
8404  E.State = IsRecursive? Recursive : NonRecursive;
8405 }
8406 
8407 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
8408 /// are recursively expanding a type (IncompleteCount != 0) and the cached
8409 /// encoding is Recursive, return an empty StringRef.
8410 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
8411  if (!ID)
8412  return StringRef(); // We have no key.
8413  auto I = Map.find(ID);
8414  if (I == Map.end())
8415  return StringRef(); // We have no encoding.
8416  Entry &E = I->second;
8417  if (E.State == Recursive && IncompleteCount)
8418  return StringRef(); // We don't use Recursive encodings for member types.
8419 
8420  if (E.State == Incomplete) {
8421  // The incomplete type is being used to break out of recursion.
8422  E.State = IncompleteUsed;
8423  ++IncompleteUsedCount;
8424  }
8425  return E.Str;
8426 }
8427 
8428 /// The XCore ABI includes a type information section that communicates symbol
8429 /// type information to the linker. The linker uses this information to verify
8430 /// safety/correctness of things such as array bound and pointers et al.
8431 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
8432 /// This type information (TypeString) is emitted into meta data for all global
8433 /// symbols: definitions, declarations, functions & variables.
8434 ///
8435 /// The TypeString carries type, qualifier, name, size & value details.
8436 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
8437 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
8438 /// The output is tested by test/CodeGen/xcore-stringtype.c.
8439 ///
8440 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8441  CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
8442 
8443 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
8444 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8445  CodeGen::CodeGenModule &CGM) const {
8446  SmallStringEnc Enc;
8447  if (getTypeString(Enc, D, CGM, TSC)) {
8448  llvm::LLVMContext &Ctx = CGM.getModule().getContext();
8449  llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
8450  llvm::MDString::get(Ctx, Enc.str())};
8451  llvm::NamedMDNode *MD =
8452  CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
8453  MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
8454  }
8455 }
8456 
8457 //===----------------------------------------------------------------------===//
8458 // SPIR ABI Implementation
8459 //===----------------------------------------------------------------------===//
8460 
8461 namespace {
8462 class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
8463 public:
8464  SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
8465  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
8466  unsigned getOpenCLKernelCallingConv() const override;
8467 };
8468 
8469 } // End anonymous namespace.
8470 
8471 namespace clang {
8472 namespace CodeGen {
8474  DefaultABIInfo SPIRABI(CGM.getTypes());
8475  SPIRABI.computeInfo(FI);
8476 }
8477 }
8478 }
8479 
8480 unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
8481  return llvm::CallingConv::SPIR_KERNEL;
8482 }
8483 
8484 static bool appendType(SmallStringEnc &Enc, QualType QType,
8485  const CodeGen::CodeGenModule &CGM,
8486  TypeStringCache &TSC);
8487 
8488 /// Helper function for appendRecordType().
8489 /// Builds a SmallVector containing the encoded field types in declaration
8490 /// order.
8492  const RecordDecl *RD,
8493  const CodeGen::CodeGenModule &CGM,
8494  TypeStringCache &TSC) {
8495  for (const auto *Field : RD->fields()) {
8496  SmallStringEnc Enc;
8497  Enc += "m(";
8498  Enc += Field->getName();
8499  Enc += "){";
8500  if (Field->isBitField()) {
8501  Enc += "b(";
8502  llvm::raw_svector_ostream OS(Enc);
8503  OS << Field->getBitWidthValue(CGM.getContext());
8504  Enc += ':';
8505  }
8506  if (!appendType(Enc, Field->getType(), CGM, TSC))
8507  return false;
8508  if (Field->isBitField())
8509  Enc += ')';
8510  Enc += '}';
8511  FE.emplace_back(!Field->getName().empty(), Enc);
8512  }
8513  return true;
8514 }
8515 
8516 /// Appends structure and union types to Enc and adds encoding to cache.
8517 /// Recursively calls appendType (via extractFieldType) for each field.
8518 /// Union types have their fields ordered according to the ABI.
8519 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
8520  const CodeGen::CodeGenModule &CGM,
8521  TypeStringCache &TSC, const IdentifierInfo *ID) {
8522  // Append the cached TypeString if we have one.
8523  StringRef TypeString = TSC.lookupStr(ID);
8524  if (!TypeString.empty()) {
8525  Enc += TypeString;
8526  return true;
8527  }
8528 
8529  // Start to emit an incomplete TypeString.
8530  size_t Start = Enc.size();
8531  Enc += (RT->isUnionType()? 'u' : 's');
8532  Enc += '(';
8533  if (ID)
8534  Enc += ID->getName();
8535  Enc += "){";
8536 
8537  // We collect all encoded fields and order as necessary.
8538  bool IsRecursive = false;
8539  const RecordDecl *RD = RT->getDecl()->getDefinition();
8540  if (RD && !RD->field_empty()) {
8541  // An incomplete TypeString stub is placed in the cache for this RecordType
8542  // so that recursive calls to this RecordType will use it whilst building a
8543  // complete TypeString for this RecordType.
8545  std::string StubEnc(Enc.substr(Start).str());
8546  StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
8547  TSC.addIncomplete(ID, std::move(StubEnc));
8548  if (!extractFieldType(FE, RD, CGM, TSC)) {
8549  (void) TSC.removeIncomplete(ID);
8550  return false;
8551  }
8552  IsRecursive = TSC.removeIncomplete(ID);
8553  // The ABI requires unions to be sorted but not structures.
8554  // See FieldEncoding::operator< for sort algorithm.
8555  if (RT->isUnionType())
8556  llvm::sort(FE.begin(), FE.end());
8557  // We can now complete the TypeString.
8558  unsigned E = FE.size();
8559  for (unsigned I = 0; I != E; ++I) {
8560  if (I)
8561  Enc += ',';
8562  Enc += FE[I].str();
8563  }
8564  }
8565  Enc += '}';
8566  TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
8567  return true;
8568 }
8569 
8570 /// Appends enum types to Enc and adds the encoding to the cache.
8571 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
8572  TypeStringCache &TSC,
8573  const IdentifierInfo *ID) {
8574  // Append the cached TypeString if we have one.
8575  StringRef TypeString = TSC.lookupStr(ID);
8576  if (!TypeString.empty()) {
8577  Enc += TypeString;
8578  return true;
8579  }
8580 
8581  size_t Start = Enc.size();
8582  Enc += "e(";
8583  if (ID)
8584  Enc += ID->getName();
8585  Enc += "){";
8586 
8587  // We collect all encoded enumerations and order them alphanumerically.
8588  if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
8590  for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
8591  ++I) {
8592  SmallStringEnc EnumEnc;
8593  EnumEnc += "m(";
8594  EnumEnc += I->getName();
8595  EnumEnc += "){";
8596  I->getInitVal().toString(EnumEnc);
8597  EnumEnc += '}';
8598  FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
8599  }
8600  llvm::sort(FE.begin(), FE.end());
8601  unsigned E = FE.size();
8602  for (unsigned I = 0; I != E; ++I) {
8603  if (I)
8604  Enc += ',';
8605  Enc += FE[I].str();
8606  }
8607  }
8608  Enc += '}';
8609  TSC.addIfComplete(ID, Enc.substr(Start), false);
8610  return true;
8611 }
8612 
8613 /// Appends type's qualifier to Enc.
8614 /// This is done prior to appending the type's encoding.
8615 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
8616  // Qualifiers are emitted in alphabetical order.
8617  static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
8618  int Lookup = 0;
8619  if (QT.isConstQualified())
8620  Lookup += 1<<0;
8621  if (QT.isRestrictQualified())
8622  Lookup += 1<<1;
8623  if (QT.isVolatileQualified())
8624  Lookup += 1<<2;
8625  Enc += Table[Lookup];
8626 }
8627 
8628 /// Appends built-in types to Enc.
8629 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
8630  const char *EncType;
8631  switch (BT->getKind()) {
8632  case BuiltinType::Void:
8633  EncType = "0";
8634  break;
8635  case BuiltinType::Bool:
8636  EncType = "b";
8637  break;
8638  case BuiltinType::Char_U:
8639  EncType = "uc";
8640  break;
8641  case BuiltinType::UChar:
8642  EncType = "uc";
8643  break;
8644  case BuiltinType::SChar:
8645  EncType = "sc";
8646  break;
8647  case BuiltinType::UShort:
8648  EncType = "us";
8649  break;
8650  case BuiltinType::Short:
8651  EncType = "ss";
8652  break;
8653  case BuiltinType::UInt:
8654  EncType = "ui";
8655  break;
8656  case BuiltinType::Int:
8657  EncType = "si";
8658  break;
8659  case BuiltinType::ULong:
8660  EncType = "ul";
8661  break;
8662  case BuiltinType::Long:
8663  EncType = "sl";
8664  break;
8665  case BuiltinType::ULongLong:
8666  EncType = "ull";
8667  break;
8668  case BuiltinType::LongLong:
8669  EncType = "sll";
8670  break;
8671  case BuiltinType::Float:
8672  EncType = "ft";
8673  break;
8674  case BuiltinType::Double:
8675  EncType = "d";
8676  break;
8677  case BuiltinType::LongDouble:
8678  EncType = "ld";
8679  break;
8680  default:
8681  return false;
8682  }
8683  Enc += EncType;
8684  return true;
8685 }
8686 
8687 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
8688 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
8689  const CodeGen::CodeGenModule &CGM,
8690  TypeStringCache &TSC) {
8691  Enc += "p(";
8692  if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
8693  return false;
8694  Enc += ')';
8695  return true;
8696 }
8697 
8698 /// Appends array encoding to Enc before calling appendType for the element.
8699 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
8700  const ArrayType *AT,
8701  const CodeGen::CodeGenModule &CGM,
8702  TypeStringCache &TSC, StringRef NoSizeEnc) {
8703  if (AT->getSizeModifier() != ArrayType::Normal)
8704  return false;
8705  Enc += "a(";
8706  if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
8707  CAT->getSize().toStringUnsigned(Enc);
8708  else
8709  Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
8710  Enc += ':';
8711  // The Qualifiers should be attached to the type rather than the array.
8712  appendQualifier(Enc, QT);
8713  if (!appendType(Enc, AT->getElementType(), CGM, TSC))
8714  return false;
8715  Enc += ')';
8716  return true;
8717 }
8718 
8719 /// Appends a function encoding to Enc, calling appendType for the return type
8720 /// and the arguments.
8721 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
8722  const CodeGen::CodeGenModule &CGM,
8723  TypeStringCache &TSC) {
8724  Enc += "f{";
8725  if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
8726  return false;
8727  Enc += "}(";
8728  if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
8729  // N.B. we are only interested in the adjusted param types.
8730  auto I = FPT->param_type_begin();
8731  auto E = FPT->param_type_end();
8732  if (I != E) {
8733  do {
8734  if (!appendType(Enc, *I, CGM, TSC))
8735  return false;
8736  ++I;
8737  if (I != E)
8738  Enc += ',';
8739  } while (I != E);
8740  if (FPT->isVariadic())
8741  Enc += ",va";
8742  } else {
8743  if (FPT->isVariadic())
8744  Enc += "va";
8745  else
8746  Enc += '0';
8747  }
8748  }
8749  Enc += ')';
8750  return true;
8751 }
8752 
8753 /// Handles the type's qualifier before dispatching a call to handle specific
8754 /// type encodings.
8755 static bool appendType(SmallStringEnc &Enc, QualType QType,
8756  const CodeGen::CodeGenModule &CGM,
8757  TypeStringCache &TSC) {
8758 
8759  QualType QT = QType.getCanonicalType();
8760 
8761  if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
8762  // The Qualifiers should be attached to the type rather than the array.
8763  // Thus we don't call appendQualifier() here.
8764  return appendArrayType(Enc, QT, AT, CGM, TSC, "");
8765 
8766  appendQualifier(Enc, QT);
8767 
8768  if (const BuiltinType *BT = QT->getAs<BuiltinType>())
8769  return appendBuiltinType(Enc, BT);
8770 
8771  if (const PointerType *PT = QT->getAs<PointerType>())
8772  return appendPointerType(Enc, PT, CGM, TSC);
8773 
8774  if (const EnumType *ET = QT->getAs<EnumType>())
8775  return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
8776 
8777  if (const RecordType *RT = QT->getAsStructureType())
8778  return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8779 
8780  if (const RecordType *RT = QT->getAsUnionType())
8781  return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
8782 
8783  if (const FunctionType *FT = QT->getAs<FunctionType>())
8784  return appendFunctionType(Enc, FT, CGM, TSC);
8785 
8786  return false;
8787 }
8788 
8789 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8790  CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
8791  if (!D)
8792  return false;
8793 
8794  if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
8795  if (FD->getLanguageLinkage() != CLanguageLinkage)
8796  return false;
8797  return appendType(Enc, FD->getType(), CGM, TSC);
8798  }
8799 
8800  if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
8801  if (VD->getLanguageLinkage() != CLanguageLinkage)
8802  return false;
8803  QualType QT = VD->getType().getCanonicalType();
8804  if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
8805  // Global ArrayTypes are given a size of '*' if the size is unknown.
8806  // The Qualifiers should be attached to the type rather than the array.
8807  // Thus we don't call appendQualifier() here.
8808  return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
8809  }
8810  return appendType(Enc, QT, CGM, TSC);
8811  }
8812  return false;
8813 }
8814 
8815 //===----------------------------------------------------------------------===//
8816 // RISCV ABI Implementation
8817 //===----------------------------------------------------------------------===//
8818 
8819 namespace {
8820 class RISCVABIInfo : public DefaultABIInfo {
8821 private:
8822  unsigned XLen; // Size of the integer ('x') registers in bits.
8823  static const int NumArgGPRs = 8;
8824 
8825 public:
8826  RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
8827  : DefaultABIInfo(CGT), XLen(XLen) {}
8828 
8829  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
8830  // non-virtual, but computeInfo is virtual, so we overload it.
8831  void computeInfo(CGFunctionInfo &FI) const override;
8832 
8833  ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed,
8834  int &ArgGPRsLeft) const;
8835  ABIArgInfo classifyReturnType(QualType RetTy) const;
8836 
8837  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8838  QualType Ty) const override;
8839 
8840  ABIArgInfo extendType(QualType Ty) const;
8841 };
8842 } // end anonymous namespace
8843 
8844 void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
8845  QualType RetTy = FI.getReturnType();
8846  if (!getCXXABI().classifyReturnType(FI))
8847  FI.getReturnInfo() = classifyReturnType(RetTy);
8848 
8849  // IsRetIndirect is true if classifyArgumentType indicated the value should
8850  // be passed indirect or if the type size is greater than 2*xlen. e.g. fp128
8851  // is passed direct in LLVM IR, relying on the backend lowering code to
8852  // rewrite the argument list and pass indirectly on RV32.
8853  bool IsRetIndirect = FI.getReturnInfo().getKind() == ABIArgInfo::Indirect ||
8854  getContext().getTypeSize(RetTy) > (2 * XLen);
8855 
8856  // We must track the number of GPRs used in order to conform to the RISC-V
8857  // ABI, as integer scalars passed in registers should have signext/zeroext
8858  // when promoted, but are anyext if passed on the stack. As GPR usage is
8859  // different for variadic arguments, we must also track whether we are
8860  // examining a vararg or not.
8861  int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs;
8862  int NumFixedArgs = FI.getNumRequiredArgs();
8863 
8864  int ArgNum = 0;
8865  for (auto &ArgInfo : FI.arguments()) {
8866  bool IsFixed = ArgNum < NumFixedArgs;
8867  ArgInfo.info = classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft);
8868  ArgNum++;
8869  }
8870 }
8871 
8873  int &ArgGPRsLeft) const {
8874  assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
8876 
8877  // Structures with either a non-trivial destructor or a non-trivial
8878  // copy constructor are always passed indirectly.
8880  if (ArgGPRsLeft)
8881  ArgGPRsLeft -= 1;
8882  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
8884  }
8885 
8886  // Ignore empty structs/unions.
8887  if (isEmptyRecord(getContext(), Ty, true))
8888  return ABIArgInfo::getIgnore();
8889 
8890  uint64_t Size = getContext().getTypeSize(Ty);
8891  uint64_t NeededAlign = getContext().getTypeAlign(Ty);
8892  bool MustUseStack = false;
8893  // Determine the number of GPRs needed to pass the current argument
8894  // according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
8895  // register pairs, so may consume 3 registers.
8896  int NeededArgGPRs = 1;
8897  if (!IsFixed && NeededAlign == 2 * XLen)
8898  NeededArgGPRs = 2 + (ArgGPRsLeft % 2);
8899  else if (Size > XLen && Size <= 2 * XLen)
8900  NeededArgGPRs = 2;
8901 
8902  if (NeededArgGPRs > ArgGPRsLeft) {
8903  MustUseStack = true;
8904  NeededArgGPRs = ArgGPRsLeft;
8905  }
8906 
8907  ArgGPRsLeft -= NeededArgGPRs;
8908 
8909  if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType()) {
8910  // Treat an enum type as its underlying type.
8911  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8912  Ty = EnumTy->getDecl()->getIntegerType();
8913 
8914  // All integral types are promoted to XLen width, unless passed on the
8915  // stack.
8916  if (Size < XLen && Ty->isIntegralOrEnumerationType() && !MustUseStack) {
8917  return extendType(Ty);
8918  }
8919 
8920  return ABIArgInfo::getDirect();
8921  }
8922 
8923  // Aggregates which are <= 2*XLen will be passed in registers if possible,
8924  // so coerce to integers.
8925  if (Size <= 2 * XLen) {
8926  unsigned Alignment = getContext().getTypeAlign(Ty);
8927 
8928  // Use a single XLen int if possible, 2*XLen if 2*XLen alignment is
8929  // required, and a 2-element XLen array if only XLen alignment is required.
8930  if (Size <= XLen) {
8931  return ABIArgInfo::getDirect(
8932  llvm::IntegerType::get(getVMContext(), XLen));
8933  } else if (Alignment == 2 * XLen) {
8934  return ABIArgInfo::getDirect(
8935  llvm::IntegerType::get(getVMContext(), 2 * XLen));
8936  } else {
8937  return ABIArgInfo::getDirect(llvm::ArrayType::get(
8938  llvm::IntegerType::get(getVMContext(), XLen), 2));
8939  }
8940  }
8941  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
8942 }
8943 
8945  if (RetTy->isVoidType())
8946  return ABIArgInfo::getIgnore();
8947 
8948  int ArgGPRsLeft = 2;
8949 
8950  // The rules for return and argument types are the same, so defer to
8951  // classifyArgumentType.
8952  return classifyArgumentType(RetTy, /*IsFixed=*/true, ArgGPRsLeft);
8953 }
8954 
8955 Address RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8956  QualType Ty) const {
8957  CharUnits SlotSize = CharUnits::fromQuantity(XLen / 8);
8958 
8959  // Empty records are ignored for parameter passing purposes.
8960  if (isEmptyRecord(getContext(), Ty, true)) {
8961  Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
8962  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
8963  return Addr;
8964  }
8965 
8966  std::pair<CharUnits, CharUnits> SizeAndAlign =
8968 
8969  // Arguments bigger than 2*Xlen bytes are passed indirectly.
8970  bool IsIndirect = SizeAndAlign.first > 2 * SlotSize;
8971 
8972  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, SizeAndAlign,
8973  SlotSize, /*AllowHigherAlign=*/true);
8974 }
8975 
8976 ABIArgInfo RISCVABIInfo::extendType(QualType Ty) const {
8977  int TySize = getContext().getTypeSize(Ty);
8978  // RV64 ABI requires unsigned 32 bit integers to be sign extended.
8979  if (XLen == 64 && Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
8980  return ABIArgInfo::getSignExtend(Ty);
8981  return ABIArgInfo::getExtend(Ty);
8982 }
8983 
8984 namespace {
8985 class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
8986 public:
8987  RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
8988  : TargetCodeGenInfo(new RISCVABIInfo(CGT, XLen)) {}
8989 
8990  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
8991  CodeGen::CodeGenModule &CGM) const override {
8992  const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
8993  if (!FD) return;
8994 
8995  const auto *Attr = FD->getAttr<RISCVInterruptAttr>();
8996  if (!Attr)
8997  return;
8998 
8999  const char *Kind;
9000  switch (Attr->getInterrupt()) {
9001  case RISCVInterruptAttr::user: Kind = "user"; break;
9002  case RISCVInterruptAttr::supervisor: Kind = "supervisor"; break;
9003  case RISCVInterruptAttr::machine: Kind = "machine"; break;
9004  }
9005 
9006  auto *Fn = cast<llvm::Function>(GV);
9007 
9008  Fn->addFnAttr("interrupt", Kind);
9009  }
9010 };
9011 } // namespace
9012 
9013 //===----------------------------------------------------------------------===//
9014 // Driver code
9015 //===----------------------------------------------------------------------===//
9016 
9018  return getTriple().supportsCOMDAT();
9019 }
9020 
9022  if (TheTargetCodeGenInfo)
9023  return *TheTargetCodeGenInfo;
9024 
9025  // Helper to set the unique_ptr while still keeping the return value.
9026  auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
9027  this->TheTargetCodeGenInfo.reset(P);
9028  return *P;
9029  };
9030 
9031  const llvm::Triple &Triple = getTarget().getTriple();
9032  switch (Triple.getArch()) {
9033  default:
9034  return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
9035 
9036  case llvm::Triple::le32:
9037  return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9038  case llvm::Triple::mips:
9039  case llvm::Triple::mipsel:
9040  if (Triple.getOS() == llvm::Triple::NaCl)
9041  return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9042  return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
9043 
9044  case llvm::Triple::mips64:
9045  case llvm::Triple::mips64el:
9046  return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
9047 
9048  case llvm::Triple::avr:
9049  return SetCGInfo(new AVRTargetCodeGenInfo(Types));
9050 
9051  case llvm::Triple::aarch64:
9052  case llvm::Triple::aarch64_be: {
9053  AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
9054  if (getTarget().getABI() == "darwinpcs")
9055  Kind = AArch64ABIInfo::DarwinPCS;
9056  else if (Triple.isOSWindows())
9057  return SetCGInfo(
9058  new WindowsAArch64TargetCodeGenInfo(Types, AArch64ABIInfo::Win64));
9059 
9060  return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
9061  }
9062 
9063  case llvm::Triple::wasm32:
9064  case llvm::Triple::wasm64:
9065  return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
9066 
9067  case llvm::Triple::arm:
9068  case llvm::Triple::armeb:
9069  case llvm::Triple::thumb:
9070  case llvm::Triple::thumbeb: {
9071  if (Triple.getOS() == llvm::Triple::Win32) {
9072  return SetCGInfo(
9073  new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
9074  }
9075 
9076  ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
9077  StringRef ABIStr = getTarget().getABI();
9078  if (ABIStr == "apcs-gnu")
9079  Kind = ARMABIInfo::APCS;
9080  else if (ABIStr == "aapcs16")
9081  Kind = ARMABIInfo::AAPCS16_VFP;
9082  else if (CodeGenOpts.FloatABI == "hard" ||
9083  (CodeGenOpts.FloatABI != "soft" &&
9084  (Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
9085  Triple.getEnvironment() == llvm::Triple::MuslEABIHF ||
9086  Triple.getEnvironment() == llvm::Triple::EABIHF)))
9087  Kind = ARMABIInfo::AAPCS_VFP;
9088 
9089  return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
9090  }
9091 
9092  case llvm::Triple::ppc:
9093  return SetCGInfo(
9094  new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
9095  case llvm::Triple::ppc64:
9096  if (Triple.isOSBinFormatELF()) {
9097  PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
9098  if (getTarget().getABI() == "elfv2")
9099  Kind = PPC64_SVR4_ABIInfo::ELFv2;
9100  bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9101  bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9102 
9103  return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9104  IsSoftFloat));
9105  } else
9106  return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
9107  case llvm::Triple::ppc64le: {
9108  assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
9109  PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
9110  if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
9111  Kind = PPC64_SVR4_ABIInfo::ELFv1;
9112  bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9113  bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9114 
9115  return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9116  IsSoftFloat));
9117  }
9118 
9119  case llvm::Triple::nvptx:
9120  case llvm::Triple::nvptx64:
9121  return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
9122 
9123  case llvm::Triple::msp430:
9124  return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
9125 
9126  case llvm::Triple::riscv32:
9127  return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 32));
9128  case llvm::Triple::riscv64:
9129  return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 64));
9130 
9131  case llvm::Triple::systemz: {
9132  bool HasVector = getTarget().getABI() == "vector";
9133  return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
9134  }
9135 
9136  case llvm::Triple::tce:
9137  case llvm::Triple::tcele:
9138  return SetCGInfo(new TCETargetCodeGenInfo(Types));
9139 
9140  case llvm::Triple::x86: {
9141  bool IsDarwinVectorABI = Triple.isOSDarwin();
9142  bool RetSmallStructInRegABI =
9143  X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
9144  bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
9145 
9146  if (Triple.getOS() == llvm::Triple::Win32) {
9147  return SetCGInfo(new WinX86_32TargetCodeGenInfo(
9148  Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9149  IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
9150  } else {
9151  return SetCGInfo(new X86_32TargetCodeGenInfo(
9152  Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9153  IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
9154  CodeGenOpts.FloatABI == "soft"));
9155  }
9156  }
9157 
9158  case llvm::Triple::x86_64: {
9159  StringRef ABI = getTarget().getABI();
9160  X86AVXABILevel AVXLevel =
9161  (ABI == "avx512"
9162  ? X86AVXABILevel::AVX512
9163  : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
9164 
9165  switch (Triple.getOS()) {
9166  case llvm::Triple::Win32:
9167  return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
9168  case llvm::Triple::PS4:
9169  return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
9170  default:
9171  return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
9172  }
9173  }
9174  case llvm::Triple::hexagon:
9175  return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
9176  case llvm::Triple::lanai:
9177  return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
9178  case llvm::Triple::r600:
9179  return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9180  case llvm::Triple::amdgcn:
9181  return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9182  case llvm::Triple::sparc:
9183  return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
9184  case llvm::Triple::sparcv9:
9185  return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
9186  case llvm::Triple::xcore:
9187  return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
9188  case llvm::Triple::spir:
9189  case llvm::Triple::spir64:
9190  return SetCGInfo(new SPIRTargetCodeGenInfo(Types));
9191  }
9192 }
9193 
9194 /// Create an OpenCL kernel for an enqueued block.
9195 ///
9196 /// The kernel has the same function type as the block invoke function. Its
9197 /// name is the name of the block invoke function postfixed with "_kernel".
9198 /// It simply calls the block invoke function then returns.
9199 llvm::Function *
9201  llvm::Function *Invoke,
9202  llvm::Value *BlockLiteral) const {
9203  auto *InvokeFT = Invoke->getFunctionType();
9205  for (auto &P : InvokeFT->params())
9206  ArgTys.push_back(P);
9207  auto &C = CGF.getLLVMContext();
9208  std::string Name = Invoke->getName().str() + "_kernel";
9209  auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9211  &CGF.CGM.getModule());
9212  auto IP = CGF.Builder.saveIP();
9213  auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9214  auto &Builder = CGF.Builder;
9215  Builder.SetInsertPoint(BB);
9217  for (auto &A : F->args())
9218  Args.push_back(&A);
9219  Builder.CreateCall(Invoke, Args);
9220  Builder.CreateRetVoid();
9221  Builder.restoreIP(IP);
9222  return F;
9223 }
9224 
9225 /// Create an OpenCL kernel for an enqueued block.
9226 ///
9227 /// The type of the first argument (the block literal) is the struct type
9228 /// of the block literal instead of a pointer type. The first argument
9229 /// (block literal) is passed directly by value to the kernel. The kernel
9230 /// allocates the same type of struct on stack and stores the block literal
9231 /// to it and passes its pointer to the block invoke function. The kernel
9232 /// has "enqueued-block" function attribute and kernel argument metadata.
9233 llvm::Function *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel(
9234  CodeGenFunction &CGF, llvm::Function *Invoke,
9235  llvm::Value *BlockLiteral) const {
9236  auto &Builder = CGF.Builder;
9237  auto &C = CGF.getLLVMContext();
9238 
9239  auto *BlockTy = BlockLiteral->getType()->getPointerElementType();
9240  auto *InvokeFT = Invoke->getFunctionType();
9245  llvm::SmallVector<llvm::Metadata *, 8> ArgBaseTypeNames;
9248 
9249  ArgTys.push_back(BlockTy);
9250  ArgTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9251  AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(0)));
9252  ArgBaseTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9253  ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9254  AccessQuals.push_back(llvm::MDString::get(C, "none"));
9255  ArgNames.push_back(llvm::MDString::get(C, "block_literal"));
9256  for (unsigned I = 1, E = InvokeFT->getNumParams(); I < E; ++I) {
9257  ArgTys.push_back(InvokeFT->getParamType(I));
9258  ArgTypeNames.push_back(llvm::MDString::get(C, "void*"));
9259  AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(3)));
9260  AccessQuals.push_back(llvm::MDString::get(C, "none"));
9261  ArgBaseTypeNames.push_back(llvm::MDString::get(C, "void*"));
9262  ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9263  ArgNames.push_back(
9264  llvm::MDString::get(C, (Twine("local_arg") + Twine(I)).str()));
9265  }
9266  std::string Name = Invoke->getName().str() + "_kernel";
9267  auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9269  &CGF.CGM.getModule());
9270  F->addFnAttr("enqueued-block");
9271  auto IP = CGF.Builder.saveIP();
9272  auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9273  Builder.SetInsertPoint(BB);
9274  unsigned BlockAlign = CGF.CGM.getDataLayout().getPrefTypeAlignment(BlockTy);
9275  auto *BlockPtr = Builder.CreateAlloca(BlockTy, nullptr);
9276  BlockPtr->setAlignment(BlockAlign);
9277  Builder.CreateAlignedStore(F->arg_begin(), BlockPtr, BlockAlign);
9278  auto *Cast = Builder.CreatePointerCast(BlockPtr, InvokeFT->getParamType(0));
9280  Args.push_back(Cast);
9281  for (auto I = F->arg_begin() + 1, E = F->arg_end(); I != E; ++I)
9282  Args.push_back(I);
9283  Builder.CreateCall(Invoke, Args);
9284  Builder.CreateRetVoid();
9285  Builder.restoreIP(IP);
9286 
9287  F->setMetadata("kernel_arg_addr_space", llvm::MDNode::get(C, AddressQuals));
9288  F->setMetadata("kernel_arg_access_qual", llvm::MDNode::get(C, AccessQuals));
9289  F->setMetadata("kernel_arg_type", llvm::MDNode::get(C, ArgTypeNames));
9290  F->setMetadata("kernel_arg_base_type",
9291  llvm::MDNode::get(C, ArgBaseTypeNames));
9292  F->setMetadata("kernel_arg_type_qual", llvm::MDNode::get(C, ArgTypeQuals));
9293  if (CGF.CGM.getCodeGenOpts().EmitOpenCLArgMetadata)
9294  F->setMetadata("kernel_arg_name", llvm::MDNode::get(C, ArgNames));
9295 
9296  return F;
9297 }
const llvm::DataLayout & getDataLayout() const
CGCXXABI & getCXXABI() const
Definition: CodeGenTypes.h:177
Ignore - Ignore the argument (treat as void).
bool isFloatingPoint() const
Definition: Type.h:2299
CharUnits alignTo(const CharUnits &Align) const
alignTo - Returns the next integer (mod 2**64) that is greater than or equal to this quantity and is ...
Definition: CharUnits.h:184
Represents a function declaration or definition.
Definition: Decl.h:1716
void setEffectiveCallingConvention(unsigned Value)
External linkage, which indicates that the entity can be referred to from other translation units...
Definition: Linkage.h:60
static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD, uint64_t &Size)
if(T->getSizeExpr()) TRY_TO(TraverseStmt(T -> getSizeExpr()))
PointerType - C99 6.7.5.1 - Pointer Declarators.
Definition: Type.h:2393
QualType getPointeeType() const
Definition: Type.h:2406
A (possibly-)qualified type.
Definition: Type.h:655
bool isBlockPointerType() const
Definition: Type.h:6121
base_class_range bases()
Definition: DeclCXX.h:825
bool isMemberPointerType() const
Definition: Type.h:6144
llvm::Type * ConvertTypeForMem(QualType T)
const CodeGenOptions & getCodeGenOpts() const
bool isUnsignedIntegerOrEnumerationType() const
Determines whether this is an integer type that is unsigned or an enumeration types whose underlying ...
Definition: Type.cpp:1904
bool isHomogeneousAggregate(QualType Ty, const Type *&Base, uint64_t &Members) const
isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous aggregate. ...
static void setCUDAKernelCallingConvention(CanQualType &FTy, CodeGenModule &CGM, const FunctionDecl *FD)
Set calling convention for CUDA/HIP kernel.
Definition: CGCall.cpp:259
Address CreateMemTemp(QualType T, const Twine &Name="tmp", Address *Alloca=nullptr)
CreateMemTemp - Create a temporary memory object of the given type, with appropriate alignmen and cas...
Definition: CGExpr.cpp:139
static ABIArgInfo classifyType(CodeGenModule &CGM, CanQualType type, bool forReturn)
const ASTRecordLayout & getASTRecordLayout(const RecordDecl *D) const
Get or compute information about the layout of the specified record (struct/union/class) D...
Kind getKind() const
Definition: Type.h:2274
FunctionType - C99 6.7.5.3 - Function Declarators.
Definition: Type.h:3211
llvm::ConstantInt * getSize(CharUnits N)
Definition: CGBuilder.h:61
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:941
CharUnits getBaseClassOffset(const CXXRecordDecl *Base) const
getBaseClassOffset - Get the offset, in chars, for the given base class.
Definition: RecordLayout.h:233
bool isRealFloatingType() const
Floating point categories.
Definition: Type.cpp:1941
Extend - Valid only for integer argument types.
bool isRecordType() const
Definition: Type.h:6186
Decl - This represents one declaration (or definition), e.g.
Definition: DeclBase.h:86
static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET, TypeStringCache &TSC, const IdentifierInfo *ID)
Appends enum types to Enc and adds the encoding to the cache.
const RecordType * getAsStructureType() const
Definition: Type.cpp:513
Direct - Pass the argument directly using the normal converted LLVM type, or by coercing to another s...
const llvm::DataLayout & getDataLayout() const
Definition: CodeGenTypes.h:171
StringRef P
static const Type * isSingleElementStruct(QualType T, ASTContext &Context)
isSingleElementStruct - Determine if a structure is a "single element struct", i.e.
Definition: TargetInfo.cpp:536
The base class of the type hierarchy.
Definition: Type.h:1428
const ABIInfo & getABIInfo() const
getABIInfo() - Returns ABI info helper for the target.
Definition: TargetInfo.h:55
Represents an array type, per C99 6.7.5.2 - Array Declarators.
Definition: Type.h:2668
bool isRestrictQualified() const
Determine whether this type is restrict-qualified.
Definition: Type.h:5953
bool isZero() const
isZero - Test whether the quantity equals zero.
Definition: CharUnits.h:116
const TargetInfo & getTargetInfo() const
Definition: ASTContext.h:679
static bool appendType(SmallStringEnc &Enc, QualType QType, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Handles the type&#39;s qualifier before dispatching a call to handle specific type encodings.
llvm::IntegerType * Int8Ty
i8, i16, i32, and i64
void setCanBeFlattened(bool Flatten)
QualType getElementType() const
Definition: Type.h:2703
const RecordType * getAsUnionType() const
NOTE: getAs*ArrayType are methods on ASTContext.
Definition: Type.cpp:532
unsigned getTypeAlign(QualType T) const
Return the ABI-specified alignment of a (complete) type T, in bits.
Definition: ASTContext.h:2073
ASTContext & getContext() const
Definition: TargetInfo.cpp:190
Represents a variable declaration or definition.
Definition: Decl.h:814
LangAS getLangASFromTargetAS(unsigned TargetAS)
Definition: AddressSpaces.h:67
bool isEnumeralType() const
Definition: Type.h:6190
const T * getAs() const
Member-template getAs<specific type>&#39;.
Definition: Type.h:6526
bool hasPointerRepresentation() const
Whether this type is represented natively as a pointer.
Definition: Type.h:6475
LangAS
Defines the address space values used by the address space qualifier of QualType. ...
Definition: AddressSpaces.h:26
llvm::LLVMContext & getVMContext() const
Definition: TargetInfo.cpp:194
void setCoerceToType(llvm::Type *T)
bool field_empty() const
Definition: Decl.h:3794
Address CreateConstInBoundsByteGEP(Address Addr, CharUnits Offset, const llvm::Twine &Name="")
Given a pointer to i8, adjust it by a given constant offset.
Definition: CGBuilder.h:234
llvm::Value * getPointer() const
Definition: Address.h:38
llvm::Type * ConvertTypeForMem(QualType T)
ConvertTypeForMem - Convert type T into a llvm::Type.
static ABIArgInfo getIgnore()
static bool isAggregateTypeForABI(QualType T)
Definition: TargetInfo.cpp:75
bool hasFloatingRepresentation() const
Determine whether this type has a floating-point representation of some sort, e.g., it is a floating-point type or a vector thereof.
Definition: Type.cpp:1934
virtual unsigned getOpenCLKernelCallingConv() const
Get LLVM calling convention for OpenCL kernel.
Definition: TargetInfo.cpp:420
Represents a struct/union/class.
Definition: Decl.h:3570
uint64_t getPointerWidth(unsigned AddrSpace) const
Return the width of pointers on this target, for the specified address space.
Definition: TargetInfo.h:340
static ABIArgInfo coerceToIntArray(QualType Ty, ASTContext &Context, llvm::LLVMContext &LLVMContext)
Definition: TargetInfo.cpp:51
CodeGen::CodeGenTypes & CGT
Definition: ABIInfo.h:53
One of these records is kept for each identifier that is lexed.
Address getAddress() const
Definition: CGValue.h:327
Indirect - Pass the argument indirectly via a hidden pointer with the specified alignment (0 indicate...
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
llvm::Type * ConvertType(QualType T)
ConvertType - Convert type T into a llvm::Type.
Holds long-lived AST nodes (such as types and decls) that can be referred to throughout the semantic ...
Definition: ASTContext.h:150
LineState State
ABIArgInfo classifyArgumentType(CodeGenModule &CGM, CanQualType type)
Classify the rules for how to pass a particular type.
RecordDecl * getDefinition() const
Returns the RecordDecl that actually defines this struct/union/class.
Definition: Decl.h:3776
static llvm::Type * GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, const llvm::DataLayout &TD)
GetX86_64ByValArgumentPair - Given a high and low type that can ideally be used as elements of a two ...
static CharUnits getTypeAllocSize(CodeGenModule &CGM, llvm::Type *type)
field_range fields() const
Definition: Decl.h:3786
static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF, Address VAListAddr, QualType Ty)
Represents a member of a struct/union/class.
Definition: Decl.h:2534
bool isReferenceType() const
Definition: Type.h:6125
CharUnits getTypeUnadjustedAlignInChars(QualType T) const
getTypeUnadjustedAlignInChars - Return the ABI-specified alignment of a type, in characters, before alignment adjustments.
bool isSpecificBuiltinType(unsigned K) const
Test for a particular builtin type.
Definition: Type.h:6307
static CharUnits Zero()
Zero - Construct a CharUnits quantity of zero.
Definition: CharUnits.h:53
static bool occupiesMoreThan(CodeGenTypes &cgt, ArrayRef< llvm::Type *> scalarTypes, unsigned maxAllRegisters)
Does the given lowering require more than the given number of registers when expanded?
Definition: TargetInfo.cpp:113
ABIInfo(CodeGen::CodeGenTypes &cgt)
Definition: ABIInfo.h:57
bool isIntegralOrEnumerationType() const
Determine whether this type is an integral or enumeration type.
Definition: Type.h:6440
static ABIArgInfo getIndirectInReg(CharUnits Alignment, bool ByVal=true, bool Realign=false)
virtual StringRef getABI() const
Get the ABI currently in use.
Definition: TargetInfo.h:1007
static ABIArgInfo getDirect(llvm::Type *T=nullptr, unsigned Offset=0, llvm::Type *Padding=nullptr, bool CanBeFlattened=true)
static bool hasScalarEvaluationKind(QualType T)
bool isBitField() const
Determines whether this field is a bitfield.
Definition: Decl.h:2612
static ABIArgInfo getExpandWithPadding(bool PaddingInReg, llvm::Type *Padding)
static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC, const IdentifierInfo *ID)
Appends structure and union types to Enc and adds encoding to cache.
Address CreateElementBitCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Cast the element type of the given address to a different type, preserving information like the align...
Definition: CGBuilder.h:157
CharUnits - This is an opaque type for sizes expressed in character units.
Definition: CharUnits.h:38
uint32_t Offset
Definition: CacheTokens.cpp:43
const ArrayType * getAsArrayTypeUnsafe() const
A variant of getAs<> for array types which silently discards qualifiers from the outermost type...
Definition: Type.h:6575
CharUnits getAlignment() const
Return the alignment of this pointer.
Definition: Address.h:67
static void rewriteInputConstraintReferences(unsigned FirstIn, unsigned NumNewOuts, std::string &AsmString)
Rewrite input constraint references after adding some output constraints.
static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty)
bool isVolatileQualified() const
Determine whether this type is volatile-qualified.
Definition: Type.h:5959
const_arg_iterator arg_begin() const
static ABIArgInfo getExtendInReg(QualType Ty, llvm::Type *T=nullptr)
llvm::CallInst * CreateMemCpy(Address Dest, Address Src, llvm::Value *Size, bool IsVolatile=false)
Definition: CGBuilder.h:274
ABIArgInfo - Helper class to encapsulate information about how a specific C type should be passed to ...
CanQualType LongDoubleTy
Definition: ASTContext.h:1016
const Type * getTypePtr() const
Retrieves a pointer to the underlying (unqualified) type.
Definition: Type.h:5889
unsigned Align
Definition: ASTContext.h:140
field_iterator field_begin() const
Definition: Decl.cpp:4040
llvm::BasicBlock * createBasicBlock(const Twine &name="", llvm::Function *parent=nullptr, llvm::BasicBlock *before=nullptr)
createBasicBlock - Create an LLVM basic block.
static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, unsigned EndBit, ASTContext &Context)
BitsContainNoUserData - Return true if the specified [start,end) bit range is known to either be off ...
static ABIArgInfo getExpand()
bool isFloat128Type() const
Definition: Type.h:6359
bool isScalarType() const
Definition: Type.h:6425
#define UINT_MAX
Definition: limits.h:72
llvm::AllocaInst * CreateTempAlloca(llvm::Type *Ty, const Twine &Name="tmp", llvm::Value *ArraySize=nullptr)
CreateTempAlloca - This creates an alloca and inserts it into the entry block if ArraySize is nullptr...
Definition: CGExpr.cpp:106
unsigned getTypeUnadjustedAlign(QualType T) const
Return the ABI-specified natural alignment of a (complete) type T, before alignment adjustments...
Definition: ASTContext.h:2081
const T * getTypePtr() const
Retrieve the underlying type pointer, which refers to a canonical type.
Definition: CanonicalType.h:84
static QualType useFirstFieldIfTransparentUnion(QualType Ty)
Pass transparent unions as if they were the type of the first element.
Definition: TargetInfo.cpp:175
virtual llvm::Value * performAddrSpaceCast(CodeGen::CodeGenFunction &CGF, llvm::Value *V, LangAS SrcAddr, LangAS DestAddr, llvm::Type *DestTy, bool IsNonNull=false) const
Perform address space cast of an expression of pointer type.
Definition: TargetInfo.cpp:447
bool isTypeConstant(QualType QTy, bool ExcludeCtorDtor)
isTypeConstant - Determine whether an object of this type can be emitted as a constant.
ExtInfo withCallingConv(CallingConv cc) const
Definition: Type.h:3341
Represents a K&R-style &#39;int foo()&#39; function, which has no information available about its arguments...
Definition: Type.h:3397
static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, const llvm::DataLayout &TD)
ContainsFloatAtOffset - Return true if the specified LLVM IR type has a float member at the specified...
bool isHalfType() const
Definition: Type.h:6346
static ABIArgInfo getSignExtend(QualType Ty, llvm::Type *T=nullptr)
bool hasAttr() const
Definition: DeclBase.h:538
CanQualType getReturnType() const
bool isPromotableIntegerType() const
More type predicates useful for type checking/promotion.
Definition: Type.cpp:2458
static CharUnits One()
One - Construct a CharUnits quantity of one.
Definition: CharUnits.h:58
Represents a prototype with parameter type info, e.g.
Definition: Type.h:3432
virtual CodeGen::Address EmitMSVAArg(CodeGen::CodeGenFunction &CGF, CodeGen::Address VAListAddr, QualType Ty) const
Emit the target dependent code to load a value of.
Definition: TargetInfo.cpp:93
const TargetCodeGenInfo & getTargetCodeGenInfo()
bool isComplexType() const
isComplexType() does not include complex integers (a GCC extension).
Definition: Type.cpp:473
static bool extractFieldType(SmallVectorImpl< FieldEncoding > &FE, const RecordDecl *RD, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Helper function for appendRecordType().
virtual void getDependentLibraryOption(llvm::StringRef Lib, llvm::SmallString< 24 > &Opt) const
Gets the linker options necessary to link a dependent library on this platform.
Definition: TargetInfo.cpp:411
static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, llvm::Value *Array, llvm::Value *Value, unsigned FirstIndex, unsigned LastIndex)
Definition: TargetInfo.cpp:62
static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context)
void setAddress(Address address)
Definition: CGValue.h:328
QuantityType getQuantity() const
getQuantity - Get the raw integer representation of this quantity.
Definition: CharUnits.h:179
ASTRecordLayout - This class contains layout information for one RecordDecl, which is a struct/union/...
Definition: RecordLayout.h:39
const llvm::fltSemantics & getLongDoubleFormat() const
Definition: TargetInfo.h:567
Exposes information about the current target.
Definition: TargetInfo.h:54
CodeGen::ABIArgInfo getNaturalAlignIndirect(QualType Ty, bool ByRef=true, bool Realign=false, llvm::Type *Padding=nullptr) const
A convenience method to return an indirect ABIArgInfo with an expected alignment equal to the ABI ali...
Definition: TargetInfo.cpp:81
QualType getElementType() const
Definition: Type.h:2346
QualType getVectorType(QualType VectorType, unsigned NumElts, VectorType::VectorKind VecKind) const
Return the unique reference to a vector type of the specified element type and size.
static ABIArgInfo getExtend(QualType Ty, llvm::Type *T=nullptr)
static Address invalid()
Definition: Address.h:35
const IdentifierInfo * getBaseTypeIdentifier() const
Retrieves a pointer to the name of the base type.
Definition: Type.cpp:71
static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT)
Appends built-in types to Enc.
field_iterator field_end() const
Definition: Decl.h:3789
virtual bool classifyReturnType(CGFunctionInfo &FI) const =0
If the C++ ABI requires the given type be returned in a particular way, this method sets RetAI and re...
llvm::PointerType * getType() const
Return the type of the pointer value.
Definition: Address.h:44
CharUnits getTypeAlignInChars(QualType T) const
Return the ABI-specified alignment of a (complete) type T, in characters.
bool isAnyComplexType() const
Definition: Type.h:6194
static CharUnits fromQuantity(QuantityType Quantity)
fromQuantity - Construct a CharUnits quantity from a raw integer type.
Definition: CharUnits.h:63
static bool getTypeString(SmallStringEnc &Enc, const Decl *D, CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
The XCore ABI includes a type information section that communicates symbol type information to the li...
unsigned getFieldCount() const
getFieldCount - Get the number of fields in the layout.
Definition: RecordLayout.h:187
EnumDecl * getDefinition() const
Definition: Decl.h:3389
llvm::CallingConv::ID RuntimeCC
Definition: ABIInfo.h:55
static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI, const ABIInfo &Info)
Definition: TargetInfo.cpp:159
llvm::LLVMContext & getLLVMContext()
bool isSignedIntegerType() const
Return true if this is an integer type that is signed, according to C99 6.2.5p4 [char, signed char, short, int, long..], or an enum decl which has a signed representation.
Definition: Type.cpp:1848
CodeGen::ABIArgInfo getNaturalAlignIndirectInReg(QualType Ty, bool Realign=false) const
Definition: TargetInfo.cpp:88
const CodeGenOptions & getCodeGenOpts() const
CharUnits alignmentOfArrayElement(CharUnits elementSize) const
Given that this is the alignment of the first element of an array, return the minimum alignment of an...
Definition: CharUnits.h:197
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF, Address VAListAddr, llvm::Type *DirectTy, CharUnits DirectSize, CharUnits DirectAlign, CharUnits SlotSize, bool AllowHigherAlign)
Emit va_arg for a platform using the common void* representation, where arguments are simply emitted ...
Definition: TargetInfo.cpp:288
Represents a GCC generic vector type.
Definition: Type.h:3024
ArraySizeModifier getSizeModifier() const
Definition: Type.h:2705
virtual unsigned getSizeOfUnwindException() const
Determines the size of struct _Unwind_Exception on this platform, in 8-bit units. ...
Definition: TargetInfo.cpp:391
Implements C++ ABI-specific semantic analysis functions.
Definition: CXXABI.h:30
const TargetInfo & getTarget() const
bool isUnionType() const
Definition: Type.cpp:467
const LangOptions & getLangOpts() const
ASTContext & getContext() const
bool isNull() const
Return true if this QualType doesn&#39;t point to a type yet.
Definition: Type.h:720
Attempt to be ABI-compatible with code generated by Clang 3.8.x (SVN r257626).
virtual llvm::Constant * getNullPointer(const CodeGen::CodeGenModule &CGM, llvm::PointerType *T, QualType QT) const
Get target specific null pointer.
Definition: TargetInfo.cpp:434
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:236
bool isConstQualified() const
Determine whether this type is const-qualified.
Definition: Type.h:5948
The l-value was considered opaque, so the alignment was determined from a type.
RecordDecl * getDecl() const
Definition: Type.h:4145
Pass it as a pointer to temporary memory.
Definition: CGCXXABI.h:137
uint64_t getFieldOffset(unsigned FieldNo) const
getFieldOffset - Get the offset of the given field index, in bits.
Definition: RecordLayout.h:191
bool isStructureOrClassType() const
Definition: Type.cpp:453
static void appendQualifier(SmallStringEnc &Enc, QualType QT)
Appends type&#39;s qualifier to Enc.
static Address emitMergePHI(CodeGenFunction &CGF, Address Addr1, llvm::BasicBlock *Block1, Address Addr2, llvm::BasicBlock *Block2, const llvm::Twine &Name="")
Definition: TargetInfo.cpp:375
static bool isEmptyField(ASTContext &Context, const FieldDecl *FD, bool AllowArrays)
isEmptyField - Return true iff a the field is "empty", that is it is an unnamed bit-field or an (arra...
Definition: TargetInfo.cpp:475
Address CreateBitCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Definition: CGBuilder.h:142
Kind
QualType getCanonicalType() const
Definition: Type.h:5928
bool isBuiltinType() const
Helper methods to distinguish type categories.
Definition: Type.h:6182
QualType getReturnType() const
Definition: Type.h:3365
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of enums...
Definition: Type.h:4161
LangAS getAddressSpace() const
Return the address space of this type.
Definition: Type.h:6005
const TargetInfo & getTarget() const
Definition: TargetInfo.cpp:202
bool isUnnamedBitfield() const
Determines whether this is an unnamed bitfield.
Definition: Decl.h:2615
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays)
isEmptyRecord - Return true iff a structure contains only empty fields.
Definition: TargetInfo.cpp:508
static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Appends a function encoding to Enc, calling appendType for the return type and the arguments...
SyncScope
Defines synch scope values used internally by clang.
Definition: SyncScope.h:43
const llvm::DataLayout & getDataLayout() const
Definition: TargetInfo.cpp:198
void setArgStruct(llvm::StructType *Ty, CharUnits Align)
virtual void computeInfo(CodeGen::CGFunctionInfo &FI) const =0
const ConstantArrayType * getAsConstantArrayType(QualType T) const
Definition: ASTContext.h:2395
const_arg_iterator arg_end() const
CanQualType FloatTy
Definition: ASTContext.h:1016
CoerceAndExpand - Only valid for aggregate argument types.
bool isSignedIntegerOrEnumerationType() const
Determines whether this is an integer type that is signed or an enumeration types whose underlying ty...
Definition: Type.cpp:1864
bool isMemberFunctionPointerType() const
Definition: Type.h:6148
An aligned address.
Definition: Address.h:25
llvm::LLVMContext & getLLVMContext()
Definition: CodeGenTypes.h:178
bool canPassInRegisters() const
Determine whether this class can be passed in registers.
Definition: Decl.h:3721
bool operator<(DeclarationName LHS, DeclarationName RHS)
Ordering on two declaration names.
bool isTargetAddressSpace(LangAS AS)
Definition: AddressSpaces.h:58
EnumDecl * getDecl() const
Definition: Type.h:4168
bool isVectorType() const
Definition: Type.h:6198
TargetCodeGenInfo - This class organizes various target-specific codegeneration issues, like target-specific attributes, builtins and so on.
Definition: TargetInfo.h:46
InAlloca - Pass the argument directly using the LLVM inalloca attribute.
X86AVXABILevel
The AVX ABI level for X86 targets.
QualType getType() const
Definition: CGValue.h:264
llvm::CallingConv::ID getRuntimeCC() const
Return the calling convention to use for system runtime functions.
Definition: ABIInfo.h:73
bool hasFlexibleArrayMember() const
Definition: Decl.h:3661
static llvm::Value * emitRoundPointerUpToAlignment(CodeGenFunction &CGF, llvm::Value *Ptr, CharUnits Align)
Definition: TargetInfo.cpp:258
CanProxy< U > getAs() const
Retrieve a canonical type pointer with a different static type, upcasting or downcasting as needed...
std::pair< CharUnits, CharUnits > getTypeInfoInChars(const Type *T) const
llvm::Type * getPaddingType() const
StringRef getName() const
Return the actual identifier string.
const TargetInfo & getTarget() const
Definition: CodeGenTypes.h:176
virtual CodeGen::Address EmitVAArg(CodeGen::CodeGenFunction &CGF, CodeGen::Address VAListAddr, QualType Ty) const =0
EmitVAArg - Emit the target dependent code to load a value of.
CGFunctionInfo - Class to encapsulate the information about a function definition.
This class organizes the cross-function state that is used while generating LLVM code.
Dataflow Directional Tag Classes.
bool isFloat16Type() const
Definition: Type.h:6353
virtual LangAS getGlobalVarAddressSpace(CodeGenModule &CGM, const VarDecl *D) const
Get target favored AST address space of a global variable for languages other than OpenCL and CUDA...
Definition: TargetInfo.cpp:439
ExtInfo getExtInfo() const
Definition: Type.h:3376
A refining implementation of ABIInfo for targets that support swiftcall.
Definition: ABIInfo.h:124
static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD, uint64_t &Size)
virtual llvm::Function * createEnqueuedBlockKernel(CodeGenFunction &CGF, llvm::Function *BlockInvokeFunc, llvm::Value *BlockLiteral) const
Create an OpenCL kernel for an enqueued block.
static ABIArgInfo getDirectInReg(llvm::Type *T=nullptr)
Address CreateStructGEP(Address Addr, unsigned Index, CharUnits Offset, const llvm::Twine &Name="")
Definition: CGBuilder.h:172
virtual bool isHomogeneousAggregateSmallEnough(const Type *Base, uint64_t Members) const
Definition: TargetInfo.cpp:216
llvm::LoadInst * CreateAlignedLoad(llvm::Value *Addr, CharUnits Align, const llvm::Twine &Name="")
Definition: CGBuilder.h:91
static bool appendArrayType(SmallStringEnc &Enc, QualType QT, const ArrayType *AT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC, StringRef NoSizeEnc)
Appends array encoding to Enc before calling appendType for the element.
std::unique_ptr< DiagnosticConsumer > create(StringRef OutputFile, DiagnosticOptions *Diags, bool MergeChildRecords=false)
Returns a DiagnosticConsumer that serializes diagnostics to a bitcode file.
llvm::LoadInst * CreateLoad(Address Addr, const llvm::Twine &Name="")
Definition: CGBuilder.h:70
Represents an enum.
Definition: Decl.h:3313
virtual bool isNoProtoCallVariadic(const CodeGen::CallArgList &args, const FunctionNoProtoType *fnType) const
Determine whether a call to an unprototyped functions under the given calling convention should use t...
Definition: TargetInfo.cpp:401
llvm::StoreInst * CreateStore(llvm::Value *Val, Address Addr, bool IsVolatile=false)
Definition: CGBuilder.h:108
bool isAggregateType() const
Determines whether the type is a C++ aggregate type or C aggregate or union type. ...
Definition: Type.cpp:2010
llvm::Module & getModule() const
virtual bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy, unsigned elts) const
Definition: TargetInfo.cpp:132
LValue MakeAddrLValue(Address Addr, QualType T, AlignmentSource Source=AlignmentSource::Type)
specific_decl_iterator - Iterates over a subrange of declarations stored in a DeclContext, providing only those that are of type SpecificDecl (or a class derived from it).
Definition: DeclBase.h:1608
unsigned getIntWidth(QualType T) const
virtual void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const
setTargetAttributes - Provides a convenient hook to handle extra target-specific attributes for the g...
Definition: TargetInfo.h:59
virtual llvm::Optional< LangAS > getConstantAddressSpace() const
Return an AST address space which can be used opportunistically for constant global memory...
Definition: TargetInfo.h:1175
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of structs/unions/cl...
Definition: Type.h:4135
Complex values, per C99 6.2.5p11.
Definition: Type.h:2333
Pass it using the normal C aggregate rules for the ABI, potentially introducing extra copies and pass...
Definition: CGCXXABI.h:129
Address CreateConstArrayGEP(Address Addr, uint64_t Index, CharUnits EltSize, const llvm::Twine &Name="")
Given addr = [n x T]* ...
Definition: CGBuilder.h:195
bool isIntegerType() const
isIntegerType() does not include complex integers (a GCC extension).
Definition: Type.h:6374
void EmitStoreOfComplex(ComplexPairTy V, LValue dest, bool isInit)
EmitStoreOfComplex - Store a complex number into the specified l-value.
Implements C++ ABI-specific code generation functions.
Definition: CGCXXABI.h:44
T * getAttr() const
Definition: DeclBase.h:534
llvm::Type * getElementType() const
Return the type of the values stored in this address.
Definition: Address.h:52
This class organizes the cross-module state that is used while lowering AST types to LLVM types...
Definition: CodeGenTypes.h:120
CodeGen::CGCXXABI & getCXXABI() const
Definition: TargetInfo.cpp:186
CodeGenOptions - Track various options which control how the code is optimized and passed to the back...
Expand - Only valid for aggregate argument types.
Internal linkage, which indicates that the entity can be referred to from within the translation unit...
Definition: Linkage.h:32
virtual bool hasFloat128Type() const
Determine whether the __float128 type is supported on this target.
Definition: TargetInfo.h:510
void EmitBlock(llvm::BasicBlock *BB, bool IsFinished=false)
EmitBlock - Emit the given block.
Definition: CGStmt.cpp:445
static bool isArgInAlloca(const ABIArgInfo &Info)
static ABIArgInfo getInAlloca(unsigned FieldIndex)
Represents a base class of a C++ class.
Definition: DeclCXX.h:192
uint64_t getTypeSize(QualType T) const
Return the size of the specified (complete) type T, in bits.
Definition: ASTContext.h:2052
ASTContext & getContext() const
Definition: CodeGenTypes.h:174
Pass it on the stack using its defined layout.
Definition: CGCXXABI.h:134
static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, CGCXXABI &CXXABI)
Definition: TargetInfo.cpp:140
CanQualType getCanonicalType(QualType T) const
Return the canonical (structural) type corresponding to the specified potentially non-canonical type ...
Definition: ASTContext.h:2235
CharUnits toCharUnitsFromBits(int64_t BitSize) const
Convert a size in bits to a size in characters.
bool isMultipleOf(CharUnits N) const
Test whether this is a multiple of the other value.
Definition: CharUnits.h:137
int64_t toBits(CharUnits CharSize) const
Convert a size in characters to a size in bits.
virtual llvm::SyncScope::ID getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const
Get the syncscope used in LLVM IR.
Definition: TargetInfo.cpp:467
CallingConv getCallConv() const
Definition: Type.h:3375
unsigned getCallingConvention() const
getCallingConvention - Return the user specified calling convention, which has been translated into a...
Address CreateConstByteGEP(Address Addr, CharUnits Offset, const llvm::Twine &Name="")
Definition: CGBuilder.h:240
Represents a C++ struct/union/class.
Definition: DeclCXX.h:302
void EmitBranch(llvm::BasicBlock *Block)
EmitBranch - Emit a branch to the specified basic block from the current insert block, taking care to avoid creation of branches from dummy blocks.
Definition: CGStmt.cpp:465
bool isVoidType() const
Definition: Type.h:6340
TypeInfo getTypeInfo(const Type *T) const
Get the size and alignment of the specified complete type in bits.
llvm::Type * ConvertType(QualType T)
virtual RecordArgABI getRecordArgABI(const CXXRecordDecl *RD) const =0
Returns how an argument of the given record type should be passed.
QualType getPointerType(QualType T) const
Return the uniqued reference to the type for a pointer to the specified type.
This class is used for builtin types like &#39;int&#39;.
Definition: Type.h:2250
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType ValueTy, bool IsIndirect, std::pair< CharUnits, CharUnits > ValueInfo, CharUnits SlotSizeAndAlign, bool AllowHigherAlign)
Emit va_arg for a platform using the common void* representation, where arguments are simply emitted ...
Definition: TargetInfo.cpp:342
ABIInfo - Target specific hooks for defining how a type should be passed or returned from functions...
Definition: ABIInfo.h:51
uint64_t Width
Definition: ASTContext.h:139
__DEVICE__ int max(int __a, int __b)
static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Appends a pointer encoding to Enc before calling appendType for the pointee.
uint64_t getTargetNullPointerValue(QualType QT) const
Get target-dependent integer value for null pointer which is used for constant folding.
virtual bool isHomogeneousAggregateBaseType(QualType Ty) const
Definition: TargetInfo.cpp:212
bool isUnion() const
Definition: Decl.h:3239
bool isPointerType() const
Definition: Type.h:6113
unsigned getNumRequiredArgs() const
__DEVICE__ int min(int __a, int __b)
unsigned getDirectOffset() const
CharUnits getTypeSizeInChars(QualType T) const
Return the size of the specified (complete) type T, in characters.
llvm::StoreInst * CreateAlignedStore(llvm::Value *Val, llvm::Value *Addr, CharUnits Align, bool IsVolatile=false)
Definition: CGBuilder.h:115
void computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI)
QualType getType() const
Definition: Decl.h:648
bool isFloatingType() const
Definition: Type.cpp:1925
LValue - This represents an lvalue references.
Definition: CGValue.h:167
llvm::Type * getCoerceToType() const
void setInAllocaSRet(bool SRet)
unsigned getTargetAddressSpace(QualType T) const
Definition: ASTContext.h:2481
CanQualType DoubleTy
Definition: ASTContext.h:1016
RecordArgABI
Specify how one should pass an argument of a record type.
Definition: CGCXXABI.h:126
Address CreatePointerBitCastOrAddrSpaceCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Definition: CGBuilder.h:164
static bool isIntegerLikeType(QualType Ty, ASTContext &Context, llvm::LLVMContext &VMContext)
static bool isSSEVectorType(ASTContext &Context, QualType Ty)
CallArgList - Type for representing both the value and type of arguments in a call.
Definition: CGCall.h:260
const LangOptions & getLangOpts() const
Definition: ASTContext.h:696
static bool PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, llvm::Value *Address)
Represents the canonical version of C arrays with a specified constant size.
Definition: Type.h:2728
static ABIArgInfo getIndirect(CharUnits Alignment, bool ByVal=true, bool Realign=false, llvm::Type *Padding=nullptr)
Attr - This represents one attribute.
Definition: Attr.h:43
QualType getIntTypeForBitwidth(unsigned DestWidth, unsigned Signed) const
getIntTypeForBitwidth - sets integer QualTy according to specified details: bitwidth, signed/unsigned.
static OMPLinearClause * Create(const ASTContext &C, SourceLocation StartLoc, SourceLocation LParenLoc, OpenMPLinearClauseKind Modifier, SourceLocation ModifierLoc, SourceLocation ColonLoc, SourceLocation EndLoc, ArrayRef< Expr *> VL, ArrayRef< Expr *> PL, ArrayRef< Expr *> IL, Expr *Step, Expr *CalcStep, Stmt *PreInit, Expr *PostUpdate)
Creates clause with a list of variables VL and a linear step Step.
const CodeGenOptions & getCodeGenOpts() const
Definition: TargetInfo.cpp:206
const llvm::Triple & getTriple() const